1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * Copyright (c) 2020, The Linux Foundation. A 3 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
4 */ 4 */
5 5
6 #include <dt-bindings/interrupt-controller/arm 6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,dispcc-sm8250 7 #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
8 #include <dt-bindings/clock/qcom,gcc-sm8250.h> 8 #include <dt-bindings/clock/qcom,gcc-sm8250.h>
9 #include <dt-bindings/clock/qcom,gpucc-sm8250. 9 #include <dt-bindings/clock/qcom,gpucc-sm8250.h>
10 #include <dt-bindings/clock/qcom,rpmh.h> 10 #include <dt-bindings/clock/qcom,rpmh.h>
>> 11 #include <dt-bindings/clock/qcom,sm8250-lpass-aoncc.h>
>> 12 #include <dt-bindings/clock/qcom,sm8250-lpass-audiocc.h>
11 #include <dt-bindings/dma/qcom-gpi.h> 13 #include <dt-bindings/dma/qcom-gpi.h>
12 #include <dt-bindings/gpio/gpio.h> 14 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interconnect/qcom,osm-l3 15 #include <dt-bindings/interconnect/qcom,osm-l3.h>
14 #include <dt-bindings/interconnect/qcom,sm8250 16 #include <dt-bindings/interconnect/qcom,sm8250.h>
15 #include <dt-bindings/mailbox/qcom-ipcc.h> 17 #include <dt-bindings/mailbox/qcom-ipcc.h>
16 #include <dt-bindings/phy/phy-qcom-qmp.h> <<
17 #include <dt-bindings/power/qcom-rpmpd.h> 18 #include <dt-bindings/power/qcom-rpmpd.h>
18 #include <dt-bindings/power/qcom,rpmhpd.h> <<
19 #include <dt-bindings/soc/qcom,apr.h> 19 #include <dt-bindings/soc/qcom,apr.h>
20 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 20 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
21 #include <dt-bindings/sound/qcom,q6afe.h> 21 #include <dt-bindings/sound/qcom,q6afe.h>
22 #include <dt-bindings/thermal/thermal.h> 22 #include <dt-bindings/thermal/thermal.h>
23 #include <dt-bindings/clock/qcom,camcc-sm8250. 23 #include <dt-bindings/clock/qcom,camcc-sm8250.h>
24 #include <dt-bindings/clock/qcom,videocc-sm825 24 #include <dt-bindings/clock/qcom,videocc-sm8250.h>
25 25
26 / { 26 / {
27 interrupt-parent = <&intc>; 27 interrupt-parent = <&intc>;
28 28
29 #address-cells = <2>; 29 #address-cells = <2>;
30 #size-cells = <2>; 30 #size-cells = <2>;
31 31
32 aliases { 32 aliases {
33 i2c0 = &i2c0; 33 i2c0 = &i2c0;
34 i2c1 = &i2c1; 34 i2c1 = &i2c1;
35 i2c2 = &i2c2; 35 i2c2 = &i2c2;
36 i2c3 = &i2c3; 36 i2c3 = &i2c3;
37 i2c4 = &i2c4; 37 i2c4 = &i2c4;
38 i2c5 = &i2c5; 38 i2c5 = &i2c5;
39 i2c6 = &i2c6; 39 i2c6 = &i2c6;
40 i2c7 = &i2c7; 40 i2c7 = &i2c7;
41 i2c8 = &i2c8; 41 i2c8 = &i2c8;
42 i2c9 = &i2c9; 42 i2c9 = &i2c9;
43 i2c10 = &i2c10; 43 i2c10 = &i2c10;
44 i2c11 = &i2c11; 44 i2c11 = &i2c11;
45 i2c12 = &i2c12; 45 i2c12 = &i2c12;
46 i2c13 = &i2c13; 46 i2c13 = &i2c13;
47 i2c14 = &i2c14; 47 i2c14 = &i2c14;
48 i2c15 = &i2c15; 48 i2c15 = &i2c15;
49 i2c16 = &i2c16; 49 i2c16 = &i2c16;
50 i2c17 = &i2c17; 50 i2c17 = &i2c17;
51 i2c18 = &i2c18; 51 i2c18 = &i2c18;
52 i2c19 = &i2c19; 52 i2c19 = &i2c19;
53 spi0 = &spi0; 53 spi0 = &spi0;
54 spi1 = &spi1; 54 spi1 = &spi1;
55 spi2 = &spi2; 55 spi2 = &spi2;
56 spi3 = &spi3; 56 spi3 = &spi3;
57 spi4 = &spi4; 57 spi4 = &spi4;
58 spi5 = &spi5; 58 spi5 = &spi5;
59 spi6 = &spi6; 59 spi6 = &spi6;
60 spi7 = &spi7; 60 spi7 = &spi7;
61 spi8 = &spi8; 61 spi8 = &spi8;
62 spi9 = &spi9; 62 spi9 = &spi9;
63 spi10 = &spi10; 63 spi10 = &spi10;
64 spi11 = &spi11; 64 spi11 = &spi11;
65 spi12 = &spi12; 65 spi12 = &spi12;
66 spi13 = &spi13; 66 spi13 = &spi13;
67 spi14 = &spi14; 67 spi14 = &spi14;
68 spi15 = &spi15; 68 spi15 = &spi15;
69 spi16 = &spi16; 69 spi16 = &spi16;
70 spi17 = &spi17; 70 spi17 = &spi17;
71 spi18 = &spi18; 71 spi18 = &spi18;
72 spi19 = &spi19; 72 spi19 = &spi19;
73 }; 73 };
74 74
75 chosen { }; 75 chosen { };
76 76
77 clocks { 77 clocks {
78 xo_board: xo-board { 78 xo_board: xo-board {
79 compatible = "fixed-cl 79 compatible = "fixed-clock";
80 #clock-cells = <0>; 80 #clock-cells = <0>;
81 clock-frequency = <384 81 clock-frequency = <38400000>;
82 clock-output-names = " 82 clock-output-names = "xo_board";
83 }; 83 };
84 84
85 sleep_clk: sleep-clk { 85 sleep_clk: sleep-clk {
86 compatible = "fixed-cl 86 compatible = "fixed-clock";
87 clock-frequency = <327 87 clock-frequency = <32768>;
88 #clock-cells = <0>; 88 #clock-cells = <0>;
89 }; 89 };
90 }; 90 };
91 91
92 cpus { 92 cpus {
93 #address-cells = <2>; 93 #address-cells = <2>;
94 #size-cells = <0>; 94 #size-cells = <0>;
95 95
96 CPU0: cpu@0 { 96 CPU0: cpu@0 {
97 device_type = "cpu"; 97 device_type = "cpu";
98 compatible = "qcom,kry 98 compatible = "qcom,kryo485";
99 reg = <0x0 0x0>; 99 reg = <0x0 0x0>;
100 clocks = <&cpufreq_hw <<
101 enable-method = "psci" 100 enable-method = "psci";
102 capacity-dmips-mhz = < 101 capacity-dmips-mhz = <448>;
103 dynamic-power-coeffici !! 102 dynamic-power-coefficient = <205>;
104 next-level-cache = <&L 103 next-level-cache = <&L2_0>;
105 power-domains = <&CPU_ 104 power-domains = <&CPU_PD0>;
106 power-domain-names = " 105 power-domain-names = "psci";
107 qcom,freq-domain = <&c 106 qcom,freq-domain = <&cpufreq_hw 0>;
108 operating-points-v2 = 107 operating-points-v2 = <&cpu0_opp_table>;
109 interconnects = <&gem_ !! 108 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
110 <&epss 109 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
111 #cooling-cells = <2>; 110 #cooling-cells = <2>;
112 L2_0: l2-cache { 111 L2_0: l2-cache {
113 compatible = " 112 compatible = "cache";
114 cache-level = 113 cache-level = <2>;
115 cache-size = < 114 cache-size = <0x20000>;
116 cache-unified; 115 cache-unified;
117 next-level-cac 116 next-level-cache = <&L3_0>;
118 L3_0: l3-cache 117 L3_0: l3-cache {
119 compat 118 compatible = "cache";
120 cache- 119 cache-level = <3>;
121 cache- 120 cache-size = <0x400000>;
122 cache- 121 cache-unified;
123 }; 122 };
124 }; 123 };
125 }; 124 };
126 125
127 CPU1: cpu@100 { 126 CPU1: cpu@100 {
128 device_type = "cpu"; 127 device_type = "cpu";
129 compatible = "qcom,kry 128 compatible = "qcom,kryo485";
130 reg = <0x0 0x100>; 129 reg = <0x0 0x100>;
131 clocks = <&cpufreq_hw <<
132 enable-method = "psci" 130 enable-method = "psci";
133 capacity-dmips-mhz = < 131 capacity-dmips-mhz = <448>;
134 dynamic-power-coeffici !! 132 dynamic-power-coefficient = <205>;
135 next-level-cache = <&L 133 next-level-cache = <&L2_100>;
136 power-domains = <&CPU_ 134 power-domains = <&CPU_PD1>;
137 power-domain-names = " 135 power-domain-names = "psci";
138 qcom,freq-domain = <&c 136 qcom,freq-domain = <&cpufreq_hw 0>;
139 operating-points-v2 = 137 operating-points-v2 = <&cpu0_opp_table>;
140 interconnects = <&gem_ !! 138 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
141 <&epss 139 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
142 #cooling-cells = <2>; 140 #cooling-cells = <2>;
143 L2_100: l2-cache { 141 L2_100: l2-cache {
144 compatible = " 142 compatible = "cache";
145 cache-level = 143 cache-level = <2>;
146 cache-size = < 144 cache-size = <0x20000>;
147 cache-unified; 145 cache-unified;
148 next-level-cac 146 next-level-cache = <&L3_0>;
149 }; 147 };
150 }; 148 };
151 149
152 CPU2: cpu@200 { 150 CPU2: cpu@200 {
153 device_type = "cpu"; 151 device_type = "cpu";
154 compatible = "qcom,kry 152 compatible = "qcom,kryo485";
155 reg = <0x0 0x200>; 153 reg = <0x0 0x200>;
156 clocks = <&cpufreq_hw <<
157 enable-method = "psci" 154 enable-method = "psci";
158 capacity-dmips-mhz = < 155 capacity-dmips-mhz = <448>;
159 dynamic-power-coeffici !! 156 dynamic-power-coefficient = <205>;
160 next-level-cache = <&L 157 next-level-cache = <&L2_200>;
161 power-domains = <&CPU_ 158 power-domains = <&CPU_PD2>;
162 power-domain-names = " 159 power-domain-names = "psci";
163 qcom,freq-domain = <&c 160 qcom,freq-domain = <&cpufreq_hw 0>;
164 operating-points-v2 = 161 operating-points-v2 = <&cpu0_opp_table>;
165 interconnects = <&gem_ !! 162 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
166 <&epss 163 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
167 #cooling-cells = <2>; 164 #cooling-cells = <2>;
168 L2_200: l2-cache { 165 L2_200: l2-cache {
169 compatible = " 166 compatible = "cache";
170 cache-level = 167 cache-level = <2>;
171 cache-size = < 168 cache-size = <0x20000>;
172 cache-unified; 169 cache-unified;
173 next-level-cac 170 next-level-cache = <&L3_0>;
174 }; 171 };
175 }; 172 };
176 173
177 CPU3: cpu@300 { 174 CPU3: cpu@300 {
178 device_type = "cpu"; 175 device_type = "cpu";
179 compatible = "qcom,kry 176 compatible = "qcom,kryo485";
180 reg = <0x0 0x300>; 177 reg = <0x0 0x300>;
181 clocks = <&cpufreq_hw <<
182 enable-method = "psci" 178 enable-method = "psci";
183 capacity-dmips-mhz = < 179 capacity-dmips-mhz = <448>;
184 dynamic-power-coeffici !! 180 dynamic-power-coefficient = <205>;
185 next-level-cache = <&L 181 next-level-cache = <&L2_300>;
186 power-domains = <&CPU_ 182 power-domains = <&CPU_PD3>;
187 power-domain-names = " 183 power-domain-names = "psci";
188 qcom,freq-domain = <&c 184 qcom,freq-domain = <&cpufreq_hw 0>;
189 operating-points-v2 = 185 operating-points-v2 = <&cpu0_opp_table>;
190 interconnects = <&gem_ !! 186 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
191 <&epss 187 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
192 #cooling-cells = <2>; 188 #cooling-cells = <2>;
193 L2_300: l2-cache { 189 L2_300: l2-cache {
194 compatible = " 190 compatible = "cache";
195 cache-level = 191 cache-level = <2>;
196 cache-size = < 192 cache-size = <0x20000>;
197 cache-unified; 193 cache-unified;
198 next-level-cac 194 next-level-cache = <&L3_0>;
199 }; 195 };
200 }; 196 };
201 197
202 CPU4: cpu@400 { 198 CPU4: cpu@400 {
203 device_type = "cpu"; 199 device_type = "cpu";
204 compatible = "qcom,kry 200 compatible = "qcom,kryo485";
205 reg = <0x0 0x400>; 201 reg = <0x0 0x400>;
206 clocks = <&cpufreq_hw <<
207 enable-method = "psci" 202 enable-method = "psci";
208 capacity-dmips-mhz = < 203 capacity-dmips-mhz = <1024>;
209 dynamic-power-coeffici 204 dynamic-power-coefficient = <379>;
210 next-level-cache = <&L 205 next-level-cache = <&L2_400>;
211 power-domains = <&CPU_ 206 power-domains = <&CPU_PD4>;
212 power-domain-names = " 207 power-domain-names = "psci";
213 qcom,freq-domain = <&c 208 qcom,freq-domain = <&cpufreq_hw 1>;
214 operating-points-v2 = 209 operating-points-v2 = <&cpu4_opp_table>;
215 interconnects = <&gem_ !! 210 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
216 <&epss 211 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
217 #cooling-cells = <2>; 212 #cooling-cells = <2>;
218 L2_400: l2-cache { 213 L2_400: l2-cache {
219 compatible = " 214 compatible = "cache";
220 cache-level = 215 cache-level = <2>;
221 cache-size = < 216 cache-size = <0x40000>;
222 cache-unified; 217 cache-unified;
223 next-level-cac 218 next-level-cache = <&L3_0>;
224 }; 219 };
225 }; 220 };
226 221
227 CPU5: cpu@500 { 222 CPU5: cpu@500 {
228 device_type = "cpu"; 223 device_type = "cpu";
229 compatible = "qcom,kry 224 compatible = "qcom,kryo485";
230 reg = <0x0 0x500>; 225 reg = <0x0 0x500>;
231 clocks = <&cpufreq_hw <<
232 enable-method = "psci" 226 enable-method = "psci";
233 capacity-dmips-mhz = < 227 capacity-dmips-mhz = <1024>;
234 dynamic-power-coeffici 228 dynamic-power-coefficient = <379>;
235 next-level-cache = <&L 229 next-level-cache = <&L2_500>;
236 power-domains = <&CPU_ 230 power-domains = <&CPU_PD5>;
237 power-domain-names = " 231 power-domain-names = "psci";
238 qcom,freq-domain = <&c 232 qcom,freq-domain = <&cpufreq_hw 1>;
239 operating-points-v2 = 233 operating-points-v2 = <&cpu4_opp_table>;
240 interconnects = <&gem_ !! 234 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
241 <&epss 235 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
242 #cooling-cells = <2>; 236 #cooling-cells = <2>;
243 L2_500: l2-cache { 237 L2_500: l2-cache {
244 compatible = " 238 compatible = "cache";
245 cache-level = 239 cache-level = <2>;
246 cache-size = < 240 cache-size = <0x40000>;
247 cache-unified; 241 cache-unified;
248 next-level-cac 242 next-level-cache = <&L3_0>;
249 }; 243 };
>> 244
250 }; 245 };
251 246
252 CPU6: cpu@600 { 247 CPU6: cpu@600 {
253 device_type = "cpu"; 248 device_type = "cpu";
254 compatible = "qcom,kry 249 compatible = "qcom,kryo485";
255 reg = <0x0 0x600>; 250 reg = <0x0 0x600>;
256 clocks = <&cpufreq_hw <<
257 enable-method = "psci" 251 enable-method = "psci";
258 capacity-dmips-mhz = < 252 capacity-dmips-mhz = <1024>;
259 dynamic-power-coeffici 253 dynamic-power-coefficient = <379>;
260 next-level-cache = <&L 254 next-level-cache = <&L2_600>;
261 power-domains = <&CPU_ 255 power-domains = <&CPU_PD6>;
262 power-domain-names = " 256 power-domain-names = "psci";
263 qcom,freq-domain = <&c 257 qcom,freq-domain = <&cpufreq_hw 1>;
264 operating-points-v2 = 258 operating-points-v2 = <&cpu4_opp_table>;
265 interconnects = <&gem_ !! 259 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
266 <&epss 260 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
267 #cooling-cells = <2>; 261 #cooling-cells = <2>;
268 L2_600: l2-cache { 262 L2_600: l2-cache {
269 compatible = " 263 compatible = "cache";
270 cache-level = 264 cache-level = <2>;
271 cache-size = < 265 cache-size = <0x40000>;
272 cache-unified; 266 cache-unified;
273 next-level-cac 267 next-level-cache = <&L3_0>;
274 }; 268 };
275 }; 269 };
276 270
277 CPU7: cpu@700 { 271 CPU7: cpu@700 {
278 device_type = "cpu"; 272 device_type = "cpu";
279 compatible = "qcom,kry 273 compatible = "qcom,kryo485";
280 reg = <0x0 0x700>; 274 reg = <0x0 0x700>;
281 clocks = <&cpufreq_hw <<
282 enable-method = "psci" 275 enable-method = "psci";
283 capacity-dmips-mhz = < 276 capacity-dmips-mhz = <1024>;
284 dynamic-power-coeffici 277 dynamic-power-coefficient = <444>;
285 next-level-cache = <&L 278 next-level-cache = <&L2_700>;
286 power-domains = <&CPU_ 279 power-domains = <&CPU_PD7>;
287 power-domain-names = " 280 power-domain-names = "psci";
288 qcom,freq-domain = <&c 281 qcom,freq-domain = <&cpufreq_hw 2>;
289 operating-points-v2 = 282 operating-points-v2 = <&cpu7_opp_table>;
290 interconnects = <&gem_ !! 283 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
291 <&epss 284 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
292 #cooling-cells = <2>; 285 #cooling-cells = <2>;
293 L2_700: l2-cache { 286 L2_700: l2-cache {
294 compatible = " 287 compatible = "cache";
295 cache-level = 288 cache-level = <2>;
296 cache-size = < 289 cache-size = <0x80000>;
297 cache-unified; 290 cache-unified;
298 next-level-cac 291 next-level-cache = <&L3_0>;
299 }; 292 };
300 }; 293 };
301 294
302 cpu-map { 295 cpu-map {
303 cluster0 { 296 cluster0 {
304 core0 { 297 core0 {
305 cpu = 298 cpu = <&CPU0>;
306 }; 299 };
307 300
308 core1 { 301 core1 {
309 cpu = 302 cpu = <&CPU1>;
310 }; 303 };
311 304
312 core2 { 305 core2 {
313 cpu = 306 cpu = <&CPU2>;
314 }; 307 };
315 308
316 core3 { 309 core3 {
317 cpu = 310 cpu = <&CPU3>;
318 }; 311 };
319 312
320 core4 { 313 core4 {
321 cpu = 314 cpu = <&CPU4>;
322 }; 315 };
323 316
324 core5 { 317 core5 {
325 cpu = 318 cpu = <&CPU5>;
326 }; 319 };
327 320
328 core6 { 321 core6 {
329 cpu = 322 cpu = <&CPU6>;
330 }; 323 };
331 324
332 core7 { 325 core7 {
333 cpu = 326 cpu = <&CPU7>;
334 }; 327 };
335 }; 328 };
336 }; 329 };
337 330
338 idle-states { 331 idle-states {
339 entry-method = "psci"; 332 entry-method = "psci";
340 333
341 LITTLE_CPU_SLEEP_0: cp 334 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
342 compatible = " 335 compatible = "arm,idle-state";
343 idle-state-nam 336 idle-state-name = "silver-rail-power-collapse";
344 arm,psci-suspe 337 arm,psci-suspend-param = <0x40000004>;
345 entry-latency- 338 entry-latency-us = <360>;
346 exit-latency-u 339 exit-latency-us = <531>;
347 min-residency- 340 min-residency-us = <3934>;
348 local-timer-st 341 local-timer-stop;
349 }; 342 };
350 343
351 BIG_CPU_SLEEP_0: cpu-s 344 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
352 compatible = " 345 compatible = "arm,idle-state";
353 idle-state-nam 346 idle-state-name = "gold-rail-power-collapse";
354 arm,psci-suspe 347 arm,psci-suspend-param = <0x40000004>;
355 entry-latency- 348 entry-latency-us = <702>;
356 exit-latency-u 349 exit-latency-us = <1061>;
357 min-residency- 350 min-residency-us = <4488>;
358 local-timer-st 351 local-timer-stop;
359 }; 352 };
360 }; 353 };
361 354
362 domain-idle-states { 355 domain-idle-states {
363 CLUSTER_SLEEP_0: clust 356 CLUSTER_SLEEP_0: cluster-sleep-0 {
364 compatible = " 357 compatible = "domain-idle-state";
>> 358 idle-state-name = "cluster-llcc-off";
365 arm,psci-suspe 359 arm,psci-suspend-param = <0x4100c244>;
366 entry-latency- 360 entry-latency-us = <3264>;
367 exit-latency-u 361 exit-latency-us = <6562>;
368 min-residency- 362 min-residency-us = <9987>;
>> 363 local-timer-stop;
369 }; 364 };
370 }; 365 };
371 }; 366 };
372 367
373 qup_virt: interconnect-qup-virt { <<
374 compatible = "qcom,sm8250-qup- <<
375 #interconnect-cells = <2>; <<
376 qcom,bcm-voters = <&apps_bcm_v <<
377 }; <<
378 <<
379 cpu0_opp_table: opp-table-cpu0 { 368 cpu0_opp_table: opp-table-cpu0 {
380 compatible = "operating-points 369 compatible = "operating-points-v2";
381 opp-shared; 370 opp-shared;
382 371
383 cpu0_opp1: opp-300000000 { 372 cpu0_opp1: opp-300000000 {
384 opp-hz = /bits/ 64 <30 373 opp-hz = /bits/ 64 <300000000>;
385 opp-peak-kBps = <80000 374 opp-peak-kBps = <800000 9600000>;
386 }; 375 };
387 376
388 cpu0_opp2: opp-403200000 { 377 cpu0_opp2: opp-403200000 {
389 opp-hz = /bits/ 64 <40 378 opp-hz = /bits/ 64 <403200000>;
390 opp-peak-kBps = <80000 379 opp-peak-kBps = <800000 9600000>;
391 }; 380 };
392 381
393 cpu0_opp3: opp-518400000 { 382 cpu0_opp3: opp-518400000 {
394 opp-hz = /bits/ 64 <51 383 opp-hz = /bits/ 64 <518400000>;
395 opp-peak-kBps = <80000 384 opp-peak-kBps = <800000 16588800>;
396 }; 385 };
397 386
398 cpu0_opp4: opp-614400000 { 387 cpu0_opp4: opp-614400000 {
399 opp-hz = /bits/ 64 <61 388 opp-hz = /bits/ 64 <614400000>;
400 opp-peak-kBps = <80000 389 opp-peak-kBps = <800000 16588800>;
401 }; 390 };
402 391
403 cpu0_opp5: opp-691200000 { 392 cpu0_opp5: opp-691200000 {
404 opp-hz = /bits/ 64 <69 393 opp-hz = /bits/ 64 <691200000>;
405 opp-peak-kBps = <80000 394 opp-peak-kBps = <800000 19660800>;
406 }; 395 };
407 396
408 cpu0_opp6: opp-787200000 { 397 cpu0_opp6: opp-787200000 {
409 opp-hz = /bits/ 64 <78 398 opp-hz = /bits/ 64 <787200000>;
410 opp-peak-kBps = <18040 399 opp-peak-kBps = <1804000 19660800>;
411 }; 400 };
412 401
413 cpu0_opp7: opp-883200000 { 402 cpu0_opp7: opp-883200000 {
414 opp-hz = /bits/ 64 <88 403 opp-hz = /bits/ 64 <883200000>;
415 opp-peak-kBps = <18040 404 opp-peak-kBps = <1804000 23347200>;
416 }; 405 };
417 406
418 cpu0_opp8: opp-979200000 { 407 cpu0_opp8: opp-979200000 {
419 opp-hz = /bits/ 64 <97 408 opp-hz = /bits/ 64 <979200000>;
420 opp-peak-kBps = <18040 409 opp-peak-kBps = <1804000 26419200>;
421 }; 410 };
422 411
423 cpu0_opp9: opp-1075200000 { 412 cpu0_opp9: opp-1075200000 {
424 opp-hz = /bits/ 64 <10 413 opp-hz = /bits/ 64 <1075200000>;
425 opp-peak-kBps = <18040 414 opp-peak-kBps = <1804000 29491200>;
426 }; 415 };
427 416
428 cpu0_opp10: opp-1171200000 { 417 cpu0_opp10: opp-1171200000 {
429 opp-hz = /bits/ 64 <11 418 opp-hz = /bits/ 64 <1171200000>;
430 opp-peak-kBps = <18040 419 opp-peak-kBps = <1804000 32563200>;
431 }; 420 };
432 421
433 cpu0_opp11: opp-1248000000 { 422 cpu0_opp11: opp-1248000000 {
434 opp-hz = /bits/ 64 <12 423 opp-hz = /bits/ 64 <1248000000>;
435 opp-peak-kBps = <18040 424 opp-peak-kBps = <1804000 36249600>;
436 }; 425 };
437 426
438 cpu0_opp12: opp-1344000000 { 427 cpu0_opp12: opp-1344000000 {
439 opp-hz = /bits/ 64 <13 428 opp-hz = /bits/ 64 <1344000000>;
440 opp-peak-kBps = <21880 429 opp-peak-kBps = <2188000 36249600>;
441 }; 430 };
442 431
443 cpu0_opp13: opp-1420800000 { 432 cpu0_opp13: opp-1420800000 {
444 opp-hz = /bits/ 64 <14 433 opp-hz = /bits/ 64 <1420800000>;
445 opp-peak-kBps = <21880 434 opp-peak-kBps = <2188000 39321600>;
446 }; 435 };
447 436
448 cpu0_opp14: opp-1516800000 { 437 cpu0_opp14: opp-1516800000 {
449 opp-hz = /bits/ 64 <15 438 opp-hz = /bits/ 64 <1516800000>;
450 opp-peak-kBps = <30720 439 opp-peak-kBps = <3072000 42393600>;
451 }; 440 };
452 441
453 cpu0_opp15: opp-1612800000 { 442 cpu0_opp15: opp-1612800000 {
454 opp-hz = /bits/ 64 <16 443 opp-hz = /bits/ 64 <1612800000>;
455 opp-peak-kBps = <30720 444 opp-peak-kBps = <3072000 42393600>;
456 }; 445 };
457 446
458 cpu0_opp16: opp-1708800000 { 447 cpu0_opp16: opp-1708800000 {
459 opp-hz = /bits/ 64 <17 448 opp-hz = /bits/ 64 <1708800000>;
460 opp-peak-kBps = <40680 449 opp-peak-kBps = <4068000 42393600>;
461 }; 450 };
462 451
463 cpu0_opp17: opp-1804800000 { 452 cpu0_opp17: opp-1804800000 {
464 opp-hz = /bits/ 64 <18 453 opp-hz = /bits/ 64 <1804800000>;
465 opp-peak-kBps = <40680 454 opp-peak-kBps = <4068000 42393600>;
466 }; 455 };
467 }; 456 };
468 457
469 cpu4_opp_table: opp-table-cpu4 { 458 cpu4_opp_table: opp-table-cpu4 {
470 compatible = "operating-points 459 compatible = "operating-points-v2";
471 opp-shared; 460 opp-shared;
472 461
473 cpu4_opp1: opp-710400000 { 462 cpu4_opp1: opp-710400000 {
474 opp-hz = /bits/ 64 <71 463 opp-hz = /bits/ 64 <710400000>;
475 opp-peak-kBps = <18040 464 opp-peak-kBps = <1804000 19660800>;
476 }; 465 };
477 466
478 cpu4_opp2: opp-825600000 { 467 cpu4_opp2: opp-825600000 {
479 opp-hz = /bits/ 64 <82 468 opp-hz = /bits/ 64 <825600000>;
480 opp-peak-kBps = <21880 469 opp-peak-kBps = <2188000 23347200>;
481 }; 470 };
482 471
483 cpu4_opp3: opp-940800000 { 472 cpu4_opp3: opp-940800000 {
484 opp-hz = /bits/ 64 <94 473 opp-hz = /bits/ 64 <940800000>;
485 opp-peak-kBps = <21880 474 opp-peak-kBps = <2188000 26419200>;
486 }; 475 };
487 476
488 cpu4_opp4: opp-1056000000 { 477 cpu4_opp4: opp-1056000000 {
489 opp-hz = /bits/ 64 <10 478 opp-hz = /bits/ 64 <1056000000>;
490 opp-peak-kBps = <30720 479 opp-peak-kBps = <3072000 26419200>;
491 }; 480 };
492 481
493 cpu4_opp5: opp-1171200000 { 482 cpu4_opp5: opp-1171200000 {
494 opp-hz = /bits/ 64 <11 483 opp-hz = /bits/ 64 <1171200000>;
495 opp-peak-kBps = <30720 484 opp-peak-kBps = <3072000 29491200>;
496 }; 485 };
497 486
498 cpu4_opp6: opp-1286400000 { 487 cpu4_opp6: opp-1286400000 {
499 opp-hz = /bits/ 64 <12 488 opp-hz = /bits/ 64 <1286400000>;
500 opp-peak-kBps = <40680 489 opp-peak-kBps = <4068000 29491200>;
501 }; 490 };
502 491
503 cpu4_opp7: opp-1382400000 { 492 cpu4_opp7: opp-1382400000 {
504 opp-hz = /bits/ 64 <13 493 opp-hz = /bits/ 64 <1382400000>;
505 opp-peak-kBps = <40680 494 opp-peak-kBps = <4068000 32563200>;
506 }; 495 };
507 496
508 cpu4_opp8: opp-1478400000 { 497 cpu4_opp8: opp-1478400000 {
509 opp-hz = /bits/ 64 <14 498 opp-hz = /bits/ 64 <1478400000>;
510 opp-peak-kBps = <40680 499 opp-peak-kBps = <4068000 32563200>;
511 }; 500 };
512 501
513 cpu4_opp9: opp-1574400000 { 502 cpu4_opp9: opp-1574400000 {
514 opp-hz = /bits/ 64 <15 503 opp-hz = /bits/ 64 <1574400000>;
515 opp-peak-kBps = <54120 504 opp-peak-kBps = <5412000 39321600>;
516 }; 505 };
517 506
518 cpu4_opp10: opp-1670400000 { 507 cpu4_opp10: opp-1670400000 {
519 opp-hz = /bits/ 64 <16 508 opp-hz = /bits/ 64 <1670400000>;
520 opp-peak-kBps = <54120 509 opp-peak-kBps = <5412000 42393600>;
521 }; 510 };
522 511
523 cpu4_opp11: opp-1766400000 { 512 cpu4_opp11: opp-1766400000 {
524 opp-hz = /bits/ 64 <17 513 opp-hz = /bits/ 64 <1766400000>;
525 opp-peak-kBps = <54120 514 opp-peak-kBps = <5412000 45465600>;
526 }; 515 };
527 516
528 cpu4_opp12: opp-1862400000 { 517 cpu4_opp12: opp-1862400000 {
529 opp-hz = /bits/ 64 <18 518 opp-hz = /bits/ 64 <1862400000>;
530 opp-peak-kBps = <62200 519 opp-peak-kBps = <6220000 45465600>;
531 }; 520 };
532 521
533 cpu4_opp13: opp-1958400000 { 522 cpu4_opp13: opp-1958400000 {
534 opp-hz = /bits/ 64 <19 523 opp-hz = /bits/ 64 <1958400000>;
535 opp-peak-kBps = <62200 524 opp-peak-kBps = <6220000 48537600>;
536 }; 525 };
537 526
538 cpu4_opp14: opp-2054400000 { 527 cpu4_opp14: opp-2054400000 {
539 opp-hz = /bits/ 64 <20 528 opp-hz = /bits/ 64 <2054400000>;
540 opp-peak-kBps = <72160 529 opp-peak-kBps = <7216000 48537600>;
541 }; 530 };
542 531
543 cpu4_opp15: opp-2150400000 { 532 cpu4_opp15: opp-2150400000 {
544 opp-hz = /bits/ 64 <21 533 opp-hz = /bits/ 64 <2150400000>;
545 opp-peak-kBps = <72160 534 opp-peak-kBps = <7216000 51609600>;
546 }; 535 };
547 536
548 cpu4_opp16: opp-2246400000 { 537 cpu4_opp16: opp-2246400000 {
549 opp-hz = /bits/ 64 <22 538 opp-hz = /bits/ 64 <2246400000>;
550 opp-peak-kBps = <72160 539 opp-peak-kBps = <7216000 51609600>;
551 }; 540 };
552 541
553 cpu4_opp17: opp-2342400000 { 542 cpu4_opp17: opp-2342400000 {
554 opp-hz = /bits/ 64 <23 543 opp-hz = /bits/ 64 <2342400000>;
555 opp-peak-kBps = <83680 544 opp-peak-kBps = <8368000 51609600>;
556 }; 545 };
557 546
558 cpu4_opp18: opp-2419200000 { 547 cpu4_opp18: opp-2419200000 {
559 opp-hz = /bits/ 64 <24 548 opp-hz = /bits/ 64 <2419200000>;
560 opp-peak-kBps = <83680 549 opp-peak-kBps = <8368000 51609600>;
561 }; 550 };
562 }; 551 };
563 552
564 cpu7_opp_table: opp-table-cpu7 { 553 cpu7_opp_table: opp-table-cpu7 {
565 compatible = "operating-points 554 compatible = "operating-points-v2";
566 opp-shared; 555 opp-shared;
567 556
568 cpu7_opp1: opp-844800000 { 557 cpu7_opp1: opp-844800000 {
569 opp-hz = /bits/ 64 <84 558 opp-hz = /bits/ 64 <844800000>;
570 opp-peak-kBps = <21880 559 opp-peak-kBps = <2188000 19660800>;
571 }; 560 };
572 561
573 cpu7_opp2: opp-960000000 { 562 cpu7_opp2: opp-960000000 {
574 opp-hz = /bits/ 64 <96 563 opp-hz = /bits/ 64 <960000000>;
575 opp-peak-kBps = <21880 564 opp-peak-kBps = <2188000 26419200>;
576 }; 565 };
577 566
578 cpu7_opp3: opp-1075200000 { 567 cpu7_opp3: opp-1075200000 {
579 opp-hz = /bits/ 64 <10 568 opp-hz = /bits/ 64 <1075200000>;
580 opp-peak-kBps = <30720 569 opp-peak-kBps = <3072000 26419200>;
581 }; 570 };
582 571
583 cpu7_opp4: opp-1190400000 { 572 cpu7_opp4: opp-1190400000 {
584 opp-hz = /bits/ 64 <11 573 opp-hz = /bits/ 64 <1190400000>;
585 opp-peak-kBps = <30720 574 opp-peak-kBps = <3072000 29491200>;
586 }; 575 };
587 576
588 cpu7_opp5: opp-1305600000 { 577 cpu7_opp5: opp-1305600000 {
589 opp-hz = /bits/ 64 <13 578 opp-hz = /bits/ 64 <1305600000>;
590 opp-peak-kBps = <40680 579 opp-peak-kBps = <4068000 32563200>;
591 }; 580 };
592 581
593 cpu7_opp6: opp-1401600000 { 582 cpu7_opp6: opp-1401600000 {
594 opp-hz = /bits/ 64 <14 583 opp-hz = /bits/ 64 <1401600000>;
595 opp-peak-kBps = <40680 584 opp-peak-kBps = <4068000 32563200>;
596 }; 585 };
597 586
598 cpu7_opp7: opp-1516800000 { 587 cpu7_opp7: opp-1516800000 {
599 opp-hz = /bits/ 64 <15 588 opp-hz = /bits/ 64 <1516800000>;
600 opp-peak-kBps = <40680 589 opp-peak-kBps = <4068000 36249600>;
601 }; 590 };
602 591
603 cpu7_opp8: opp-1632000000 { 592 cpu7_opp8: opp-1632000000 {
604 opp-hz = /bits/ 64 <16 593 opp-hz = /bits/ 64 <1632000000>;
605 opp-peak-kBps = <54120 594 opp-peak-kBps = <5412000 39321600>;
606 }; 595 };
607 596
608 cpu7_opp9: opp-1747200000 { 597 cpu7_opp9: opp-1747200000 {
609 opp-hz = /bits/ 64 <17 598 opp-hz = /bits/ 64 <1708800000>;
610 opp-peak-kBps = <54120 599 opp-peak-kBps = <5412000 42393600>;
611 }; 600 };
612 601
613 cpu7_opp10: opp-1862400000 { 602 cpu7_opp10: opp-1862400000 {
614 opp-hz = /bits/ 64 <18 603 opp-hz = /bits/ 64 <1862400000>;
615 opp-peak-kBps = <62200 604 opp-peak-kBps = <6220000 45465600>;
616 }; 605 };
617 606
618 cpu7_opp11: opp-1977600000 { 607 cpu7_opp11: opp-1977600000 {
619 opp-hz = /bits/ 64 <19 608 opp-hz = /bits/ 64 <1977600000>;
620 opp-peak-kBps = <62200 609 opp-peak-kBps = <6220000 48537600>;
621 }; 610 };
622 611
623 cpu7_opp12: opp-2073600000 { 612 cpu7_opp12: opp-2073600000 {
624 opp-hz = /bits/ 64 <20 613 opp-hz = /bits/ 64 <2073600000>;
625 opp-peak-kBps = <72160 614 opp-peak-kBps = <7216000 48537600>;
626 }; 615 };
627 616
628 cpu7_opp13: opp-2169600000 { 617 cpu7_opp13: opp-2169600000 {
629 opp-hz = /bits/ 64 <21 618 opp-hz = /bits/ 64 <2169600000>;
630 opp-peak-kBps = <72160 619 opp-peak-kBps = <7216000 51609600>;
631 }; 620 };
632 621
633 cpu7_opp14: opp-2265600000 { 622 cpu7_opp14: opp-2265600000 {
634 opp-hz = /bits/ 64 <22 623 opp-hz = /bits/ 64 <2265600000>;
635 opp-peak-kBps = <72160 624 opp-peak-kBps = <7216000 51609600>;
636 }; 625 };
637 626
638 cpu7_opp15: opp-2361600000 { 627 cpu7_opp15: opp-2361600000 {
639 opp-hz = /bits/ 64 <23 628 opp-hz = /bits/ 64 <2361600000>;
640 opp-peak-kBps = <83680 629 opp-peak-kBps = <8368000 51609600>;
641 }; 630 };
642 631
643 cpu7_opp16: opp-2457600000 { 632 cpu7_opp16: opp-2457600000 {
644 opp-hz = /bits/ 64 <24 633 opp-hz = /bits/ 64 <2457600000>;
645 opp-peak-kBps = <83680 634 opp-peak-kBps = <8368000 51609600>;
646 }; 635 };
647 636
648 cpu7_opp17: opp-2553600000 { 637 cpu7_opp17: opp-2553600000 {
649 opp-hz = /bits/ 64 <25 638 opp-hz = /bits/ 64 <2553600000>;
650 opp-peak-kBps = <83680 639 opp-peak-kBps = <8368000 51609600>;
651 }; 640 };
652 641
653 cpu7_opp18: opp-2649600000 { 642 cpu7_opp18: opp-2649600000 {
654 opp-hz = /bits/ 64 <26 643 opp-hz = /bits/ 64 <2649600000>;
655 opp-peak-kBps = <83680 644 opp-peak-kBps = <8368000 51609600>;
656 }; 645 };
657 646
658 cpu7_opp19: opp-2745600000 { 647 cpu7_opp19: opp-2745600000 {
659 opp-hz = /bits/ 64 <27 648 opp-hz = /bits/ 64 <2745600000>;
660 opp-peak-kBps = <83680 649 opp-peak-kBps = <8368000 51609600>;
661 }; 650 };
662 651
663 cpu7_opp20: opp-2841600000 { 652 cpu7_opp20: opp-2841600000 {
664 opp-hz = /bits/ 64 <28 653 opp-hz = /bits/ 64 <2841600000>;
665 opp-peak-kBps = <83680 654 opp-peak-kBps = <8368000 51609600>;
666 }; 655 };
667 }; 656 };
668 657
669 firmware { 658 firmware {
670 scm: scm { 659 scm: scm {
671 compatible = "qcom,scm 660 compatible = "qcom,scm-sm8250", "qcom,scm";
672 qcom,dload-mode = <&tc <<
673 #reset-cells = <1>; 661 #reset-cells = <1>;
674 }; 662 };
675 }; 663 };
676 664
677 memory@80000000 { 665 memory@80000000 {
678 device_type = "memory"; 666 device_type = "memory";
679 /* We expect the bootloader to 667 /* We expect the bootloader to fill in the size */
680 reg = <0x0 0x80000000 0x0 0x0> 668 reg = <0x0 0x80000000 0x0 0x0>;
681 }; 669 };
682 670
683 pmu { 671 pmu {
684 compatible = "arm,armv8-pmuv3" 672 compatible = "arm,armv8-pmuv3";
685 interrupts = <GIC_PPI 7 IRQ_TY 673 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
686 }; 674 };
687 675
688 psci { 676 psci {
689 compatible = "arm,psci-1.0"; 677 compatible = "arm,psci-1.0";
690 method = "smc"; 678 method = "smc";
691 679
692 CPU_PD0: power-domain-cpu0 { 680 CPU_PD0: power-domain-cpu0 {
693 #power-domain-cells = 681 #power-domain-cells = <0>;
694 power-domains = <&CLUS 682 power-domains = <&CLUSTER_PD>;
695 domain-idle-states = < 683 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
696 }; 684 };
697 685
698 CPU_PD1: power-domain-cpu1 { 686 CPU_PD1: power-domain-cpu1 {
699 #power-domain-cells = 687 #power-domain-cells = <0>;
700 power-domains = <&CLUS 688 power-domains = <&CLUSTER_PD>;
701 domain-idle-states = < 689 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
702 }; 690 };
703 691
704 CPU_PD2: power-domain-cpu2 { 692 CPU_PD2: power-domain-cpu2 {
705 #power-domain-cells = 693 #power-domain-cells = <0>;
706 power-domains = <&CLUS 694 power-domains = <&CLUSTER_PD>;
707 domain-idle-states = < 695 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
708 }; 696 };
709 697
710 CPU_PD3: power-domain-cpu3 { 698 CPU_PD3: power-domain-cpu3 {
711 #power-domain-cells = 699 #power-domain-cells = <0>;
712 power-domains = <&CLUS 700 power-domains = <&CLUSTER_PD>;
713 domain-idle-states = < 701 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
714 }; 702 };
715 703
716 CPU_PD4: power-domain-cpu4 { 704 CPU_PD4: power-domain-cpu4 {
717 #power-domain-cells = 705 #power-domain-cells = <0>;
718 power-domains = <&CLUS 706 power-domains = <&CLUSTER_PD>;
719 domain-idle-states = < 707 domain-idle-states = <&BIG_CPU_SLEEP_0>;
720 }; 708 };
721 709
722 CPU_PD5: power-domain-cpu5 { 710 CPU_PD5: power-domain-cpu5 {
723 #power-domain-cells = 711 #power-domain-cells = <0>;
724 power-domains = <&CLUS 712 power-domains = <&CLUSTER_PD>;
725 domain-idle-states = < 713 domain-idle-states = <&BIG_CPU_SLEEP_0>;
726 }; 714 };
727 715
728 CPU_PD6: power-domain-cpu6 { 716 CPU_PD6: power-domain-cpu6 {
729 #power-domain-cells = 717 #power-domain-cells = <0>;
730 power-domains = <&CLUS 718 power-domains = <&CLUSTER_PD>;
731 domain-idle-states = < 719 domain-idle-states = <&BIG_CPU_SLEEP_0>;
732 }; 720 };
733 721
734 CPU_PD7: power-domain-cpu7 { 722 CPU_PD7: power-domain-cpu7 {
735 #power-domain-cells = 723 #power-domain-cells = <0>;
736 power-domains = <&CLUS 724 power-domains = <&CLUSTER_PD>;
737 domain-idle-states = < 725 domain-idle-states = <&BIG_CPU_SLEEP_0>;
738 }; 726 };
739 727
740 CLUSTER_PD: power-domain-cpu-c 728 CLUSTER_PD: power-domain-cpu-cluster0 {
741 #power-domain-cells = 729 #power-domain-cells = <0>;
742 domain-idle-states = < 730 domain-idle-states = <&CLUSTER_SLEEP_0>;
743 }; 731 };
744 }; 732 };
745 733
746 qup_opp_table: opp-table-qup { 734 qup_opp_table: opp-table-qup {
747 compatible = "operating-points 735 compatible = "operating-points-v2";
748 736
749 opp-50000000 { 737 opp-50000000 {
750 opp-hz = /bits/ 64 <50 738 opp-hz = /bits/ 64 <50000000>;
751 required-opps = <&rpmh 739 required-opps = <&rpmhpd_opp_min_svs>;
752 }; 740 };
753 741
754 opp-75000000 { 742 opp-75000000 {
755 opp-hz = /bits/ 64 <75 743 opp-hz = /bits/ 64 <75000000>;
756 required-opps = <&rpmh 744 required-opps = <&rpmhpd_opp_low_svs>;
757 }; 745 };
758 746
759 opp-120000000 { 747 opp-120000000 {
760 opp-hz = /bits/ 64 <12 748 opp-hz = /bits/ 64 <120000000>;
761 required-opps = <&rpmh 749 required-opps = <&rpmhpd_opp_svs>;
762 }; 750 };
763 }; 751 };
764 752
765 reserved-memory { 753 reserved-memory {
766 #address-cells = <2>; 754 #address-cells = <2>;
767 #size-cells = <2>; 755 #size-cells = <2>;
768 ranges; 756 ranges;
769 757
770 hyp_mem: memory@80000000 { 758 hyp_mem: memory@80000000 {
771 reg = <0x0 0x80000000 759 reg = <0x0 0x80000000 0x0 0x600000>;
772 no-map; 760 no-map;
773 }; 761 };
774 762
775 xbl_aop_mem: memory@80700000 { 763 xbl_aop_mem: memory@80700000 {
776 reg = <0x0 0x80700000 764 reg = <0x0 0x80700000 0x0 0x160000>;
777 no-map; 765 no-map;
778 }; 766 };
779 767
780 cmd_db: memory@80860000 { 768 cmd_db: memory@80860000 {
781 compatible = "qcom,cmd 769 compatible = "qcom,cmd-db";
782 reg = <0x0 0x80860000 770 reg = <0x0 0x80860000 0x0 0x20000>;
783 no-map; 771 no-map;
784 }; 772 };
785 773
786 smem_mem: memory@80900000 { 774 smem_mem: memory@80900000 {
787 reg = <0x0 0x80900000 775 reg = <0x0 0x80900000 0x0 0x200000>;
788 no-map; 776 no-map;
789 }; 777 };
790 778
791 removed_mem: memory@80b00000 { 779 removed_mem: memory@80b00000 {
792 reg = <0x0 0x80b00000 780 reg = <0x0 0x80b00000 0x0 0x5300000>;
793 no-map; 781 no-map;
794 }; 782 };
795 783
796 camera_mem: memory@86200000 { 784 camera_mem: memory@86200000 {
797 reg = <0x0 0x86200000 785 reg = <0x0 0x86200000 0x0 0x500000>;
798 no-map; 786 no-map;
799 }; 787 };
800 788
801 wlan_mem: memory@86700000 { 789 wlan_mem: memory@86700000 {
802 reg = <0x0 0x86700000 790 reg = <0x0 0x86700000 0x0 0x100000>;
803 no-map; 791 no-map;
804 }; 792 };
805 793
806 ipa_fw_mem: memory@86800000 { 794 ipa_fw_mem: memory@86800000 {
807 reg = <0x0 0x86800000 795 reg = <0x0 0x86800000 0x0 0x10000>;
808 no-map; 796 no-map;
809 }; 797 };
810 798
811 ipa_gsi_mem: memory@86810000 { 799 ipa_gsi_mem: memory@86810000 {
812 reg = <0x0 0x86810000 800 reg = <0x0 0x86810000 0x0 0xa000>;
813 no-map; 801 no-map;
814 }; 802 };
815 803
816 gpu_mem: memory@8681a000 { 804 gpu_mem: memory@8681a000 {
817 reg = <0x0 0x8681a000 805 reg = <0x0 0x8681a000 0x0 0x2000>;
818 no-map; 806 no-map;
819 }; 807 };
820 808
821 npu_mem: memory@86900000 { 809 npu_mem: memory@86900000 {
822 reg = <0x0 0x86900000 810 reg = <0x0 0x86900000 0x0 0x500000>;
823 no-map; 811 no-map;
824 }; 812 };
825 813
826 video_mem: memory@86e00000 { 814 video_mem: memory@86e00000 {
827 reg = <0x0 0x86e00000 815 reg = <0x0 0x86e00000 0x0 0x500000>;
828 no-map; 816 no-map;
829 }; 817 };
830 818
831 cvp_mem: memory@87300000 { 819 cvp_mem: memory@87300000 {
832 reg = <0x0 0x87300000 820 reg = <0x0 0x87300000 0x0 0x500000>;
833 no-map; 821 no-map;
834 }; 822 };
835 823
836 cdsp_mem: memory@87800000 { 824 cdsp_mem: memory@87800000 {
837 reg = <0x0 0x87800000 825 reg = <0x0 0x87800000 0x0 0x1400000>;
838 no-map; 826 no-map;
839 }; 827 };
840 828
841 slpi_mem: memory@88c00000 { 829 slpi_mem: memory@88c00000 {
842 reg = <0x0 0x88c00000 830 reg = <0x0 0x88c00000 0x0 0x1500000>;
843 no-map; 831 no-map;
844 }; 832 };
845 833
846 adsp_mem: memory@8a100000 { 834 adsp_mem: memory@8a100000 {
847 reg = <0x0 0x8a100000 835 reg = <0x0 0x8a100000 0x0 0x1d00000>;
848 no-map; 836 no-map;
849 }; 837 };
850 838
851 spss_mem: memory@8be00000 { 839 spss_mem: memory@8be00000 {
852 reg = <0x0 0x8be00000 840 reg = <0x0 0x8be00000 0x0 0x100000>;
853 no-map; 841 no-map;
854 }; 842 };
855 843
856 cdsp_secure_heap: memory@8bf00 844 cdsp_secure_heap: memory@8bf00000 {
857 reg = <0x0 0x8bf00000 845 reg = <0x0 0x8bf00000 0x0 0x4600000>;
858 no-map; 846 no-map;
859 }; 847 };
860 }; 848 };
861 849
862 smem { 850 smem {
863 compatible = "qcom,smem"; 851 compatible = "qcom,smem";
864 memory-region = <&smem_mem>; 852 memory-region = <&smem_mem>;
865 hwlocks = <&tcsr_mutex 3>; 853 hwlocks = <&tcsr_mutex 3>;
866 }; 854 };
867 855
868 smp2p-adsp { 856 smp2p-adsp {
869 compatible = "qcom,smp2p"; 857 compatible = "qcom,smp2p";
870 qcom,smem = <443>, <429>; 858 qcom,smem = <443>, <429>;
871 interrupts-extended = <&ipcc I 859 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
872 I 860 IPCC_MPROC_SIGNAL_SMP2P
873 I 861 IRQ_TYPE_EDGE_RISING>;
874 mboxes = <&ipcc IPCC_CLIENT_LP 862 mboxes = <&ipcc IPCC_CLIENT_LPASS
875 IPCC_MPROC_SIG 863 IPCC_MPROC_SIGNAL_SMP2P>;
876 864
877 qcom,local-pid = <0>; 865 qcom,local-pid = <0>;
878 qcom,remote-pid = <2>; 866 qcom,remote-pid = <2>;
879 867
880 smp2p_adsp_out: master-kernel 868 smp2p_adsp_out: master-kernel {
881 qcom,entry-name = "mas 869 qcom,entry-name = "master-kernel";
882 #qcom,smem-state-cells 870 #qcom,smem-state-cells = <1>;
883 }; 871 };
884 872
885 smp2p_adsp_in: slave-kernel { 873 smp2p_adsp_in: slave-kernel {
886 qcom,entry-name = "sla 874 qcom,entry-name = "slave-kernel";
887 interrupt-controller; 875 interrupt-controller;
888 #interrupt-cells = <2> 876 #interrupt-cells = <2>;
889 }; 877 };
890 }; 878 };
891 879
892 smp2p-cdsp { 880 smp2p-cdsp {
893 compatible = "qcom,smp2p"; 881 compatible = "qcom,smp2p";
894 qcom,smem = <94>, <432>; 882 qcom,smem = <94>, <432>;
895 interrupts-extended = <&ipcc I 883 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
896 I 884 IPCC_MPROC_SIGNAL_SMP2P
897 I 885 IRQ_TYPE_EDGE_RISING>;
898 mboxes = <&ipcc IPCC_CLIENT_CD 886 mboxes = <&ipcc IPCC_CLIENT_CDSP
899 IPCC_MPROC_SIG 887 IPCC_MPROC_SIGNAL_SMP2P>;
900 888
901 qcom,local-pid = <0>; 889 qcom,local-pid = <0>;
902 qcom,remote-pid = <5>; 890 qcom,remote-pid = <5>;
903 891
904 smp2p_cdsp_out: master-kernel 892 smp2p_cdsp_out: master-kernel {
905 qcom,entry-name = "mas 893 qcom,entry-name = "master-kernel";
906 #qcom,smem-state-cells 894 #qcom,smem-state-cells = <1>;
907 }; 895 };
908 896
909 smp2p_cdsp_in: slave-kernel { 897 smp2p_cdsp_in: slave-kernel {
910 qcom,entry-name = "sla 898 qcom,entry-name = "slave-kernel";
911 interrupt-controller; 899 interrupt-controller;
912 #interrupt-cells = <2> 900 #interrupt-cells = <2>;
913 }; 901 };
914 }; 902 };
915 903
916 smp2p-slpi { 904 smp2p-slpi {
917 compatible = "qcom,smp2p"; 905 compatible = "qcom,smp2p";
918 qcom,smem = <481>, <430>; 906 qcom,smem = <481>, <430>;
919 interrupts-extended = <&ipcc I 907 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
920 I 908 IPCC_MPROC_SIGNAL_SMP2P
921 I 909 IRQ_TYPE_EDGE_RISING>;
922 mboxes = <&ipcc IPCC_CLIENT_SL 910 mboxes = <&ipcc IPCC_CLIENT_SLPI
923 IPCC_MPROC_SIG 911 IPCC_MPROC_SIGNAL_SMP2P>;
924 912
925 qcom,local-pid = <0>; 913 qcom,local-pid = <0>;
926 qcom,remote-pid = <3>; 914 qcom,remote-pid = <3>;
927 915
928 smp2p_slpi_out: master-kernel 916 smp2p_slpi_out: master-kernel {
929 qcom,entry-name = "mas 917 qcom,entry-name = "master-kernel";
930 #qcom,smem-state-cells 918 #qcom,smem-state-cells = <1>;
931 }; 919 };
932 920
933 smp2p_slpi_in: slave-kernel { 921 smp2p_slpi_in: slave-kernel {
934 qcom,entry-name = "sla 922 qcom,entry-name = "slave-kernel";
935 interrupt-controller; 923 interrupt-controller;
936 #interrupt-cells = <2> 924 #interrupt-cells = <2>;
937 }; 925 };
938 }; 926 };
939 927
940 soc: soc@0 { 928 soc: soc@0 {
941 #address-cells = <2>; 929 #address-cells = <2>;
942 #size-cells = <2>; 930 #size-cells = <2>;
943 ranges = <0 0 0 0 0x10 0>; 931 ranges = <0 0 0 0 0x10 0>;
944 dma-ranges = <0 0 0 0 0x10 0>; 932 dma-ranges = <0 0 0 0 0x10 0>;
945 compatible = "simple-bus"; 933 compatible = "simple-bus";
946 934
947 gcc: clock-controller@100000 { 935 gcc: clock-controller@100000 {
948 compatible = "qcom,gcc 936 compatible = "qcom,gcc-sm8250";
949 reg = <0x0 0x00100000 937 reg = <0x0 0x00100000 0x0 0x1f0000>;
950 #clock-cells = <1>; 938 #clock-cells = <1>;
951 #reset-cells = <1>; 939 #reset-cells = <1>;
952 #power-domain-cells = 940 #power-domain-cells = <1>;
953 clock-names = "bi_tcxo 941 clock-names = "bi_tcxo",
954 "bi_tcxo 942 "bi_tcxo_ao",
955 "sleep_c 943 "sleep_clk";
956 clocks = <&rpmhcc RPMH 944 clocks = <&rpmhcc RPMH_CXO_CLK>,
957 <&rpmhcc RPMH 945 <&rpmhcc RPMH_CXO_CLK_A>,
958 <&sleep_clk>; 946 <&sleep_clk>;
959 }; 947 };
960 948
961 ipcc: mailbox@408000 { 949 ipcc: mailbox@408000 {
962 compatible = "qcom,sm8 950 compatible = "qcom,sm8250-ipcc", "qcom,ipcc";
963 reg = <0 0x00408000 0 951 reg = <0 0x00408000 0 0x1000>;
964 interrupts = <GIC_SPI 952 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
965 interrupt-controller; 953 interrupt-controller;
966 #interrupt-cells = <3> 954 #interrupt-cells = <3>;
967 #mbox-cells = <2>; 955 #mbox-cells = <2>;
968 }; 956 };
969 957
970 qfprom: efuse@784000 { <<
971 compatible = "qcom,sm8 <<
972 reg = <0 0x00784000 0 <<
973 #address-cells = <1>; <<
974 #size-cells = <1>; <<
975 <<
976 gpu_speed_bin: gpu-spe <<
977 reg = <0x19b 0 <<
978 bits = <5 3>; <<
979 }; <<
980 }; <<
981 <<
982 rng: rng@793000 { 958 rng: rng@793000 {
983 compatible = "qcom,prn 959 compatible = "qcom,prng-ee";
984 reg = <0 0x00793000 0 960 reg = <0 0x00793000 0 0x1000>;
985 clocks = <&gcc GCC_PRN 961 clocks = <&gcc GCC_PRNG_AHB_CLK>;
986 clock-names = "core"; 962 clock-names = "core";
987 }; 963 };
988 964
989 gpi_dma2: dma-controller@80000 965 gpi_dma2: dma-controller@800000 {
990 compatible = "qcom,sm8 966 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma";
991 reg = <0 0x00800000 0 967 reg = <0 0x00800000 0 0x70000>;
992 interrupts = <GIC_SPI 968 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
993 <GIC_SPI 969 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
994 <GIC_SPI 970 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
995 <GIC_SPI 971 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
996 <GIC_SPI 972 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
997 <GIC_SPI 973 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
998 <GIC_SPI 974 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
999 <GIC_SPI 975 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
1000 <GIC_SPI 976 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
1001 <GIC_SPI 977 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>;
1002 dma-channels = <10>; 978 dma-channels = <10>;
1003 dma-channel-mask = <0 979 dma-channel-mask = <0x3f>;
1004 iommus = <&apps_smmu 980 iommus = <&apps_smmu 0x76 0x0>;
1005 #dma-cells = <3>; 981 #dma-cells = <3>;
1006 status = "disabled"; 982 status = "disabled";
1007 }; 983 };
1008 984
1009 qupv3_id_2: geniqup@8c0000 { 985 qupv3_id_2: geniqup@8c0000 {
1010 compatible = "qcom,ge 986 compatible = "qcom,geni-se-qup";
1011 reg = <0x0 0x008c0000 987 reg = <0x0 0x008c0000 0x0 0x6000>;
1012 clock-names = "m-ahb" 988 clock-names = "m-ahb", "s-ahb";
1013 clocks = <&gcc GCC_QU 989 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
1014 <&gcc GCC_QU 990 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
1015 #address-cells = <2>; 991 #address-cells = <2>;
1016 #size-cells = <2>; 992 #size-cells = <2>;
1017 iommus = <&apps_smmu 993 iommus = <&apps_smmu 0x63 0x0>;
1018 ranges; 994 ranges;
1019 status = "disabled"; 995 status = "disabled";
1020 996
1021 i2c14: i2c@880000 { 997 i2c14: i2c@880000 {
1022 compatible = 998 compatible = "qcom,geni-i2c";
1023 reg = <0 0x00 999 reg = <0 0x00880000 0 0x4000>;
1024 clock-names = 1000 clock-names = "se";
1025 clocks = <&gc 1001 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1026 pinctrl-names 1002 pinctrl-names = "default";
1027 pinctrl-0 = < 1003 pinctrl-0 = <&qup_i2c14_default>;
1028 interrupts = 1004 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1029 dmas = <&gpi_ 1005 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
1030 <&gpi_ 1006 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
1031 dma-names = " 1007 dma-names = "tx", "rx";
1032 power-domains <<
1033 interconnects <<
1034 <<
1035 <<
1036 interconnect- <<
1037 <<
1038 <<
1039 #address-cell 1008 #address-cells = <1>;
1040 #size-cells = 1009 #size-cells = <0>;
1041 status = "dis 1010 status = "disabled";
1042 }; 1011 };
1043 1012
1044 spi14: spi@880000 { 1013 spi14: spi@880000 {
1045 compatible = 1014 compatible = "qcom,geni-spi";
1046 reg = <0 0x00 1015 reg = <0 0x00880000 0 0x4000>;
1047 clock-names = 1016 clock-names = "se";
1048 clocks = <&gc 1017 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1049 interrupts = 1018 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1050 dmas = <&gpi_ 1019 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
1051 <&gpi_ 1020 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
1052 dma-names = " 1021 dma-names = "tx", "rx";
1053 power-domains !! 1022 power-domains = <&rpmhpd SM8250_CX>;
1054 operating-poi 1023 operating-points-v2 = <&qup_opp_table>;
1055 interconnects <<
1056 <<
1057 <<
1058 interconnect- <<
1059 <<
1060 <<
1061 #address-cell 1024 #address-cells = <1>;
1062 #size-cells = 1025 #size-cells = <0>;
1063 status = "dis 1026 status = "disabled";
1064 }; 1027 };
1065 1028
1066 i2c15: i2c@884000 { 1029 i2c15: i2c@884000 {
1067 compatible = 1030 compatible = "qcom,geni-i2c";
1068 reg = <0 0x00 1031 reg = <0 0x00884000 0 0x4000>;
1069 clock-names = 1032 clock-names = "se";
1070 clocks = <&gc 1033 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1071 pinctrl-names 1034 pinctrl-names = "default";
1072 pinctrl-0 = < 1035 pinctrl-0 = <&qup_i2c15_default>;
1073 interrupts = 1036 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1074 dmas = <&gpi_ 1037 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
1075 <&gpi_ 1038 <&gpi_dma2 1 1 QCOM_GPI_I2C>;
1076 dma-names = " 1039 dma-names = "tx", "rx";
1077 power-domains <<
1078 interconnects <<
1079 <<
1080 <<
1081 interconnect- <<
1082 <<
1083 <<
1084 #address-cell 1040 #address-cells = <1>;
1085 #size-cells = 1041 #size-cells = <0>;
1086 status = "dis 1042 status = "disabled";
1087 }; 1043 };
1088 1044
1089 spi15: spi@884000 { 1045 spi15: spi@884000 {
1090 compatible = 1046 compatible = "qcom,geni-spi";
1091 reg = <0 0x00 1047 reg = <0 0x00884000 0 0x4000>;
1092 clock-names = 1048 clock-names = "se";
1093 clocks = <&gc 1049 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1094 interrupts = 1050 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1095 dmas = <&gpi_ 1051 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
1096 <&gpi_ 1052 <&gpi_dma2 1 1 QCOM_GPI_SPI>;
1097 dma-names = " 1053 dma-names = "tx", "rx";
1098 power-domains !! 1054 power-domains = <&rpmhpd SM8250_CX>;
1099 operating-poi 1055 operating-points-v2 = <&qup_opp_table>;
1100 interconnects <<
1101 <<
1102 <<
1103 interconnect- <<
1104 <<
1105 <<
1106 #address-cell 1056 #address-cells = <1>;
1107 #size-cells = 1057 #size-cells = <0>;
1108 status = "dis 1058 status = "disabled";
1109 }; 1059 };
1110 1060
1111 i2c16: i2c@888000 { 1061 i2c16: i2c@888000 {
1112 compatible = 1062 compatible = "qcom,geni-i2c";
1113 reg = <0 0x00 1063 reg = <0 0x00888000 0 0x4000>;
1114 clock-names = 1064 clock-names = "se";
1115 clocks = <&gc 1065 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1116 pinctrl-names 1066 pinctrl-names = "default";
1117 pinctrl-0 = < 1067 pinctrl-0 = <&qup_i2c16_default>;
1118 interrupts = 1068 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1119 dmas = <&gpi_ 1069 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
1120 <&gpi_ 1070 <&gpi_dma2 1 2 QCOM_GPI_I2C>;
1121 dma-names = " 1071 dma-names = "tx", "rx";
1122 power-domains <<
1123 interconnects <<
1124 <<
1125 <<
1126 interconnect- <<
1127 <<
1128 <<
1129 #address-cell 1072 #address-cells = <1>;
1130 #size-cells = 1073 #size-cells = <0>;
1131 status = "dis 1074 status = "disabled";
1132 }; 1075 };
1133 1076
1134 spi16: spi@888000 { 1077 spi16: spi@888000 {
1135 compatible = 1078 compatible = "qcom,geni-spi";
1136 reg = <0 0x00 1079 reg = <0 0x00888000 0 0x4000>;
1137 clock-names = 1080 clock-names = "se";
1138 clocks = <&gc 1081 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1139 interrupts = 1082 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1140 dmas = <&gpi_ 1083 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
1141 <&gpi_ 1084 <&gpi_dma2 1 2 QCOM_GPI_SPI>;
1142 dma-names = " 1085 dma-names = "tx", "rx";
1143 power-domains !! 1086 power-domains = <&rpmhpd SM8250_CX>;
1144 operating-poi 1087 operating-points-v2 = <&qup_opp_table>;
1145 interconnects <<
1146 <<
1147 <<
1148 interconnect- <<
1149 <<
1150 <<
1151 #address-cell 1088 #address-cells = <1>;
1152 #size-cells = 1089 #size-cells = <0>;
1153 status = "dis 1090 status = "disabled";
1154 }; 1091 };
1155 1092
1156 i2c17: i2c@88c000 { 1093 i2c17: i2c@88c000 {
1157 compatible = 1094 compatible = "qcom,geni-i2c";
1158 reg = <0 0x00 1095 reg = <0 0x0088c000 0 0x4000>;
1159 clock-names = 1096 clock-names = "se";
1160 clocks = <&gc 1097 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1161 pinctrl-names 1098 pinctrl-names = "default";
1162 pinctrl-0 = < 1099 pinctrl-0 = <&qup_i2c17_default>;
1163 interrupts = 1100 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1164 dmas = <&gpi_ 1101 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
1165 <&gpi_ 1102 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
1166 dma-names = " 1103 dma-names = "tx", "rx";
1167 power-domains <<
1168 interconnects <<
1169 <<
1170 <<
1171 interconnect- <<
1172 <<
1173 <<
1174 #address-cell 1104 #address-cells = <1>;
1175 #size-cells = 1105 #size-cells = <0>;
1176 status = "dis 1106 status = "disabled";
1177 }; 1107 };
1178 1108
1179 spi17: spi@88c000 { 1109 spi17: spi@88c000 {
1180 compatible = 1110 compatible = "qcom,geni-spi";
1181 reg = <0 0x00 1111 reg = <0 0x0088c000 0 0x4000>;
1182 clock-names = 1112 clock-names = "se";
1183 clocks = <&gc 1113 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1184 interrupts = 1114 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1185 dmas = <&gpi_ 1115 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
1186 <&gpi_ 1116 <&gpi_dma2 1 3 QCOM_GPI_SPI>;
1187 dma-names = " 1117 dma-names = "tx", "rx";
1188 power-domains !! 1118 power-domains = <&rpmhpd SM8250_CX>;
1189 operating-poi 1119 operating-points-v2 = <&qup_opp_table>;
1190 interconnects <<
1191 <<
1192 <<
1193 interconnect- <<
1194 <<
1195 <<
1196 #address-cell 1120 #address-cells = <1>;
1197 #size-cells = 1121 #size-cells = <0>;
1198 status = "dis 1122 status = "disabled";
1199 }; 1123 };
1200 1124
1201 uart17: serial@88c000 1125 uart17: serial@88c000 {
1202 compatible = 1126 compatible = "qcom,geni-uart";
1203 reg = <0 0x00 1127 reg = <0 0x0088c000 0 0x4000>;
1204 clock-names = 1128 clock-names = "se";
1205 clocks = <&gc 1129 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1206 pinctrl-names 1130 pinctrl-names = "default";
1207 pinctrl-0 = < 1131 pinctrl-0 = <&qup_uart17_default>;
1208 interrupts = 1132 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1209 power-domains !! 1133 power-domains = <&rpmhpd SM8250_CX>;
1210 operating-poi 1134 operating-points-v2 = <&qup_opp_table>;
1211 interconnects <<
1212 <<
1213 interconnect- <<
1214 <<
1215 status = "dis 1135 status = "disabled";
1216 }; 1136 };
1217 1137
1218 i2c18: i2c@890000 { 1138 i2c18: i2c@890000 {
1219 compatible = 1139 compatible = "qcom,geni-i2c";
1220 reg = <0 0x00 1140 reg = <0 0x00890000 0 0x4000>;
1221 clock-names = 1141 clock-names = "se";
1222 clocks = <&gc 1142 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1223 pinctrl-names 1143 pinctrl-names = "default";
1224 pinctrl-0 = < 1144 pinctrl-0 = <&qup_i2c18_default>;
1225 interrupts = 1145 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1226 dmas = <&gpi_ 1146 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1227 <&gpi_ 1147 <&gpi_dma2 1 4 QCOM_GPI_I2C>;
1228 dma-names = " 1148 dma-names = "tx", "rx";
1229 power-domains <<
1230 interconnects <<
1231 <<
1232 <<
1233 interconnect- <<
1234 <<
1235 <<
1236 #address-cell 1149 #address-cells = <1>;
1237 #size-cells = 1150 #size-cells = <0>;
1238 status = "dis 1151 status = "disabled";
1239 }; 1152 };
1240 1153
1241 spi18: spi@890000 { 1154 spi18: spi@890000 {
1242 compatible = 1155 compatible = "qcom,geni-spi";
1243 reg = <0 0x00 1156 reg = <0 0x00890000 0 0x4000>;
1244 clock-names = 1157 clock-names = "se";
1245 clocks = <&gc 1158 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1246 interrupts = 1159 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1247 dmas = <&gpi_ 1160 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
1248 <&gpi_ 1161 <&gpi_dma2 1 4 QCOM_GPI_SPI>;
1249 dma-names = " 1162 dma-names = "tx", "rx";
1250 power-domains !! 1163 power-domains = <&rpmhpd SM8250_CX>;
1251 operating-poi 1164 operating-points-v2 = <&qup_opp_table>;
1252 interconnects <<
1253 <<
1254 <<
1255 interconnect- <<
1256 <<
1257 <<
1258 #address-cell 1165 #address-cells = <1>;
1259 #size-cells = 1166 #size-cells = <0>;
1260 status = "dis 1167 status = "disabled";
1261 }; 1168 };
1262 1169
1263 uart18: serial@890000 1170 uart18: serial@890000 {
1264 compatible = 1171 compatible = "qcom,geni-uart";
1265 reg = <0 0x00 1172 reg = <0 0x00890000 0 0x4000>;
1266 clock-names = 1173 clock-names = "se";
1267 clocks = <&gc 1174 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1268 pinctrl-names 1175 pinctrl-names = "default";
1269 pinctrl-0 = < 1176 pinctrl-0 = <&qup_uart18_default>;
1270 interrupts = 1177 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1271 power-domains !! 1178 power-domains = <&rpmhpd SM8250_CX>;
1272 operating-poi 1179 operating-points-v2 = <&qup_opp_table>;
1273 interconnects <<
1274 <<
1275 interconnect- <<
1276 <<
1277 status = "dis 1180 status = "disabled";
1278 }; 1181 };
1279 1182
1280 i2c19: i2c@894000 { 1183 i2c19: i2c@894000 {
1281 compatible = 1184 compatible = "qcom,geni-i2c";
1282 reg = <0 0x00 1185 reg = <0 0x00894000 0 0x4000>;
1283 clock-names = 1186 clock-names = "se";
1284 clocks = <&gc 1187 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1285 pinctrl-names 1188 pinctrl-names = "default";
1286 pinctrl-0 = < 1189 pinctrl-0 = <&qup_i2c19_default>;
1287 interrupts = 1190 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1288 dmas = <&gpi_ 1191 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1289 <&gpi_ 1192 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1290 dma-names = " 1193 dma-names = "tx", "rx";
1291 power-domains <<
1292 interconnects <<
1293 <<
1294 <<
1295 interconnect- <<
1296 <<
1297 <<
1298 #address-cell 1194 #address-cells = <1>;
1299 #size-cells = 1195 #size-cells = <0>;
1300 status = "dis 1196 status = "disabled";
1301 }; 1197 };
1302 1198
1303 spi19: spi@894000 { 1199 spi19: spi@894000 {
1304 compatible = 1200 compatible = "qcom,geni-spi";
1305 reg = <0 0x00 1201 reg = <0 0x00894000 0 0x4000>;
1306 clock-names = 1202 clock-names = "se";
1307 clocks = <&gc 1203 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1308 interrupts = 1204 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1309 dmas = <&gpi_ 1205 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1310 <&gpi_ 1206 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1311 dma-names = " 1207 dma-names = "tx", "rx";
1312 power-domains !! 1208 power-domains = <&rpmhpd SM8250_CX>;
1313 operating-poi 1209 operating-points-v2 = <&qup_opp_table>;
1314 interconnects <<
1315 <<
1316 <<
1317 interconnect- <<
1318 <<
1319 <<
1320 #address-cell 1210 #address-cells = <1>;
1321 #size-cells = 1211 #size-cells = <0>;
1322 status = "dis 1212 status = "disabled";
1323 }; 1213 };
1324 }; 1214 };
1325 1215
1326 gpi_dma0: dma-controller@9000 1216 gpi_dma0: dma-controller@900000 {
1327 compatible = "qcom,sm 1217 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma";
1328 reg = <0 0x00900000 0 1218 reg = <0 0x00900000 0 0x70000>;
1329 interrupts = <GIC_SPI 1219 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
1330 <GIC_SPI 1220 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
1331 <GIC_SPI 1221 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
1332 <GIC_SPI 1222 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
1333 <GIC_SPI 1223 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
1334 <GIC_SPI 1224 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
1335 <GIC_SPI 1225 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
1336 <GIC_SPI 1226 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
1337 <GIC_SPI 1227 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
1338 <GIC_SPI 1228 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
1339 <GIC_SPI 1229 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
1340 <GIC_SPI 1230 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
1341 <GIC_SPI 1231 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
1342 dma-channels = <15>; 1232 dma-channels = <15>;
1343 dma-channel-mask = <0 1233 dma-channel-mask = <0x7ff>;
1344 iommus = <&apps_smmu 1234 iommus = <&apps_smmu 0x5b6 0x0>;
1345 #dma-cells = <3>; 1235 #dma-cells = <3>;
1346 status = "disabled"; 1236 status = "disabled";
1347 }; 1237 };
1348 1238
1349 qupv3_id_0: geniqup@9c0000 { 1239 qupv3_id_0: geniqup@9c0000 {
1350 compatible = "qcom,ge 1240 compatible = "qcom,geni-se-qup";
1351 reg = <0x0 0x009c0000 1241 reg = <0x0 0x009c0000 0x0 0x6000>;
1352 clock-names = "m-ahb" 1242 clock-names = "m-ahb", "s-ahb";
1353 clocks = <&gcc GCC_QU 1243 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1354 <&gcc GCC_QU 1244 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1355 #address-cells = <2>; 1245 #address-cells = <2>;
1356 #size-cells = <2>; 1246 #size-cells = <2>;
1357 iommus = <&apps_smmu 1247 iommus = <&apps_smmu 0x5a3 0x0>;
1358 ranges; 1248 ranges;
1359 status = "disabled"; 1249 status = "disabled";
1360 1250
1361 i2c0: i2c@980000 { 1251 i2c0: i2c@980000 {
1362 compatible = 1252 compatible = "qcom,geni-i2c";
1363 reg = <0 0x00 1253 reg = <0 0x00980000 0 0x4000>;
1364 clock-names = 1254 clock-names = "se";
1365 clocks = <&gc 1255 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1366 pinctrl-names 1256 pinctrl-names = "default";
1367 pinctrl-0 = < 1257 pinctrl-0 = <&qup_i2c0_default>;
1368 interrupts = 1258 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1369 dmas = <&gpi_ 1259 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1370 <&gpi_ 1260 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1371 dma-names = " 1261 dma-names = "tx", "rx";
1372 power-domains <<
1373 interconnects <<
1374 <<
1375 <<
1376 interconnect- <<
1377 <<
1378 <<
1379 #address-cell 1262 #address-cells = <1>;
1380 #size-cells = 1263 #size-cells = <0>;
1381 status = "dis 1264 status = "disabled";
1382 }; 1265 };
1383 1266
1384 spi0: spi@980000 { 1267 spi0: spi@980000 {
1385 compatible = 1268 compatible = "qcom,geni-spi";
1386 reg = <0 0x00 1269 reg = <0 0x00980000 0 0x4000>;
1387 clock-names = 1270 clock-names = "se";
1388 clocks = <&gc 1271 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1389 interrupts = 1272 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1390 dmas = <&gpi_ 1273 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1391 <&gpi_ 1274 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1392 dma-names = " 1275 dma-names = "tx", "rx";
1393 power-domains !! 1276 power-domains = <&rpmhpd SM8250_CX>;
1394 operating-poi 1277 operating-points-v2 = <&qup_opp_table>;
1395 interconnects <<
1396 <<
1397 <<
1398 interconnect- <<
1399 <<
1400 <<
1401 #address-cell 1278 #address-cells = <1>;
1402 #size-cells = 1279 #size-cells = <0>;
1403 status = "dis 1280 status = "disabled";
1404 }; 1281 };
1405 1282
1406 i2c1: i2c@984000 { 1283 i2c1: i2c@984000 {
1407 compatible = 1284 compatible = "qcom,geni-i2c";
1408 reg = <0 0x00 1285 reg = <0 0x00984000 0 0x4000>;
1409 clock-names = 1286 clock-names = "se";
1410 clocks = <&gc 1287 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1411 pinctrl-names 1288 pinctrl-names = "default";
1412 pinctrl-0 = < 1289 pinctrl-0 = <&qup_i2c1_default>;
1413 interrupts = 1290 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1414 dmas = <&gpi_ 1291 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1415 <&gpi_ 1292 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1416 dma-names = " 1293 dma-names = "tx", "rx";
1417 power-domains <<
1418 interconnects <<
1419 <<
1420 <<
1421 interconnect- <<
1422 <<
1423 <<
1424 #address-cell 1294 #address-cells = <1>;
1425 #size-cells = 1295 #size-cells = <0>;
1426 status = "dis 1296 status = "disabled";
1427 }; 1297 };
1428 1298
1429 spi1: spi@984000 { 1299 spi1: spi@984000 {
1430 compatible = 1300 compatible = "qcom,geni-spi";
1431 reg = <0 0x00 1301 reg = <0 0x00984000 0 0x4000>;
1432 clock-names = 1302 clock-names = "se";
1433 clocks = <&gc 1303 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1434 interrupts = 1304 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1435 dmas = <&gpi_ 1305 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1436 <&gpi_ 1306 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1437 dma-names = " 1307 dma-names = "tx", "rx";
1438 power-domains !! 1308 power-domains = <&rpmhpd SM8250_CX>;
1439 operating-poi 1309 operating-points-v2 = <&qup_opp_table>;
1440 interconnects <<
1441 <<
1442 <<
1443 interconnect- <<
1444 <<
1445 <<
1446 #address-cell 1310 #address-cells = <1>;
1447 #size-cells = 1311 #size-cells = <0>;
1448 status = "dis 1312 status = "disabled";
1449 }; 1313 };
1450 1314
1451 i2c2: i2c@988000 { 1315 i2c2: i2c@988000 {
1452 compatible = 1316 compatible = "qcom,geni-i2c";
1453 reg = <0 0x00 1317 reg = <0 0x00988000 0 0x4000>;
1454 clock-names = 1318 clock-names = "se";
1455 clocks = <&gc 1319 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1456 pinctrl-names 1320 pinctrl-names = "default";
1457 pinctrl-0 = < 1321 pinctrl-0 = <&qup_i2c2_default>;
1458 interrupts = 1322 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1459 dmas = <&gpi_ 1323 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1460 <&gpi_ 1324 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1461 dma-names = " 1325 dma-names = "tx", "rx";
1462 power-domains <<
1463 interconnects <<
1464 <<
1465 <<
1466 interconnect- <<
1467 <<
1468 <<
1469 #address-cell 1326 #address-cells = <1>;
1470 #size-cells = 1327 #size-cells = <0>;
1471 status = "dis 1328 status = "disabled";
1472 }; 1329 };
1473 1330
1474 spi2: spi@988000 { 1331 spi2: spi@988000 {
1475 compatible = 1332 compatible = "qcom,geni-spi";
1476 reg = <0 0x00 1333 reg = <0 0x00988000 0 0x4000>;
1477 clock-names = 1334 clock-names = "se";
1478 clocks = <&gc 1335 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1479 interrupts = 1336 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1480 dmas = <&gpi_ 1337 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1481 <&gpi_ 1338 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1482 dma-names = " 1339 dma-names = "tx", "rx";
1483 power-domains !! 1340 power-domains = <&rpmhpd SM8250_CX>;
1484 operating-poi 1341 operating-points-v2 = <&qup_opp_table>;
1485 interconnects <<
1486 <<
1487 <<
1488 interconnect- <<
1489 <<
1490 <<
1491 #address-cell 1342 #address-cells = <1>;
1492 #size-cells = 1343 #size-cells = <0>;
1493 status = "dis 1344 status = "disabled";
1494 }; 1345 };
1495 1346
1496 uart2: serial@988000 1347 uart2: serial@988000 {
1497 compatible = 1348 compatible = "qcom,geni-debug-uart";
1498 reg = <0 0x00 1349 reg = <0 0x00988000 0 0x4000>;
1499 clock-names = 1350 clock-names = "se";
1500 clocks = <&gc 1351 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1501 pinctrl-names 1352 pinctrl-names = "default";
1502 pinctrl-0 = < 1353 pinctrl-0 = <&qup_uart2_default>;
1503 interrupts = 1354 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1504 power-domains !! 1355 power-domains = <&rpmhpd SM8250_CX>;
1505 operating-poi 1356 operating-points-v2 = <&qup_opp_table>;
1506 interconnects <<
1507 <<
1508 interconnect- <<
1509 <<
1510 status = "dis 1357 status = "disabled";
1511 }; 1358 };
1512 1359
1513 i2c3: i2c@98c000 { 1360 i2c3: i2c@98c000 {
1514 compatible = 1361 compatible = "qcom,geni-i2c";
1515 reg = <0 0x00 1362 reg = <0 0x0098c000 0 0x4000>;
1516 clock-names = 1363 clock-names = "se";
1517 clocks = <&gc 1364 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1518 pinctrl-names 1365 pinctrl-names = "default";
1519 pinctrl-0 = < 1366 pinctrl-0 = <&qup_i2c3_default>;
1520 interrupts = 1367 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1521 dmas = <&gpi_ 1368 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1522 <&gpi_ 1369 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1523 dma-names = " 1370 dma-names = "tx", "rx";
1524 power-domains <<
1525 interconnects <<
1526 <<
1527 <<
1528 interconnect- <<
1529 <<
1530 <<
1531 #address-cell 1371 #address-cells = <1>;
1532 #size-cells = 1372 #size-cells = <0>;
1533 status = "dis 1373 status = "disabled";
1534 }; 1374 };
1535 1375
1536 spi3: spi@98c000 { 1376 spi3: spi@98c000 {
1537 compatible = 1377 compatible = "qcom,geni-spi";
1538 reg = <0 0x00 1378 reg = <0 0x0098c000 0 0x4000>;
1539 clock-names = 1379 clock-names = "se";
1540 clocks = <&gc 1380 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1541 interrupts = 1381 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1542 dmas = <&gpi_ 1382 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1543 <&gpi_ 1383 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1544 dma-names = " 1384 dma-names = "tx", "rx";
1545 power-domains !! 1385 power-domains = <&rpmhpd SM8250_CX>;
1546 operating-poi 1386 operating-points-v2 = <&qup_opp_table>;
1547 interconnects <<
1548 <<
1549 <<
1550 interconnect- <<
1551 <<
1552 <<
1553 #address-cell 1387 #address-cells = <1>;
1554 #size-cells = 1388 #size-cells = <0>;
1555 status = "dis 1389 status = "disabled";
1556 }; 1390 };
1557 1391
1558 i2c4: i2c@990000 { 1392 i2c4: i2c@990000 {
1559 compatible = 1393 compatible = "qcom,geni-i2c";
1560 reg = <0 0x00 1394 reg = <0 0x00990000 0 0x4000>;
1561 clock-names = 1395 clock-names = "se";
1562 clocks = <&gc 1396 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1563 pinctrl-names 1397 pinctrl-names = "default";
1564 pinctrl-0 = < 1398 pinctrl-0 = <&qup_i2c4_default>;
1565 interrupts = 1399 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1566 dmas = <&gpi_ 1400 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1567 <&gpi_ 1401 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1568 dma-names = " 1402 dma-names = "tx", "rx";
1569 power-domains <<
1570 interconnects <<
1571 <<
1572 <<
1573 interconnect- <<
1574 <<
1575 <<
1576 #address-cell 1403 #address-cells = <1>;
1577 #size-cells = 1404 #size-cells = <0>;
1578 status = "dis 1405 status = "disabled";
1579 }; 1406 };
1580 1407
1581 spi4: spi@990000 { 1408 spi4: spi@990000 {
1582 compatible = 1409 compatible = "qcom,geni-spi";
1583 reg = <0 0x00 1410 reg = <0 0x00990000 0 0x4000>;
1584 clock-names = 1411 clock-names = "se";
1585 clocks = <&gc 1412 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1586 interrupts = 1413 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1587 dmas = <&gpi_ 1414 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1588 <&gpi_ 1415 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1589 dma-names = " 1416 dma-names = "tx", "rx";
1590 power-domains !! 1417 power-domains = <&rpmhpd SM8250_CX>;
1591 operating-poi 1418 operating-points-v2 = <&qup_opp_table>;
1592 interconnects <<
1593 <<
1594 <<
1595 interconnect- <<
1596 <<
1597 <<
1598 #address-cell 1419 #address-cells = <1>;
1599 #size-cells = 1420 #size-cells = <0>;
1600 status = "dis 1421 status = "disabled";
1601 }; 1422 };
1602 1423
1603 i2c5: i2c@994000 { 1424 i2c5: i2c@994000 {
1604 compatible = 1425 compatible = "qcom,geni-i2c";
1605 reg = <0 0x00 1426 reg = <0 0x00994000 0 0x4000>;
1606 clock-names = 1427 clock-names = "se";
1607 clocks = <&gc 1428 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1608 pinctrl-names 1429 pinctrl-names = "default";
1609 pinctrl-0 = < 1430 pinctrl-0 = <&qup_i2c5_default>;
1610 interrupts = 1431 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1611 dmas = <&gpi_ 1432 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1612 <&gpi_ 1433 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1613 dma-names = " 1434 dma-names = "tx", "rx";
1614 power-domains <<
1615 interconnects <<
1616 <<
1617 <<
1618 interconnect- <<
1619 <<
1620 <<
1621 #address-cell 1435 #address-cells = <1>;
1622 #size-cells = 1436 #size-cells = <0>;
1623 status = "dis 1437 status = "disabled";
1624 }; 1438 };
1625 1439
1626 spi5: spi@994000 { 1440 spi5: spi@994000 {
1627 compatible = 1441 compatible = "qcom,geni-spi";
1628 reg = <0 0x00 1442 reg = <0 0x00994000 0 0x4000>;
1629 clock-names = 1443 clock-names = "se";
1630 clocks = <&gc 1444 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1631 interrupts = 1445 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1632 dmas = <&gpi_ 1446 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1633 <&gpi_ 1447 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1634 dma-names = " 1448 dma-names = "tx", "rx";
1635 power-domains !! 1449 power-domains = <&rpmhpd SM8250_CX>;
1636 operating-poi 1450 operating-points-v2 = <&qup_opp_table>;
1637 interconnects <<
1638 <<
1639 <<
1640 interconnect- <<
1641 <<
1642 <<
1643 #address-cell 1451 #address-cells = <1>;
1644 #size-cells = 1452 #size-cells = <0>;
1645 status = "dis 1453 status = "disabled";
1646 }; 1454 };
1647 1455
1648 i2c6: i2c@998000 { 1456 i2c6: i2c@998000 {
1649 compatible = 1457 compatible = "qcom,geni-i2c";
1650 reg = <0 0x00 1458 reg = <0 0x00998000 0 0x4000>;
1651 clock-names = 1459 clock-names = "se";
1652 clocks = <&gc 1460 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1653 pinctrl-names 1461 pinctrl-names = "default";
1654 pinctrl-0 = < 1462 pinctrl-0 = <&qup_i2c6_default>;
1655 interrupts = 1463 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1656 dmas = <&gpi_ 1464 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1657 <&gpi_ 1465 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1658 dma-names = " 1466 dma-names = "tx", "rx";
1659 power-domains <<
1660 interconnects <<
1661 <<
1662 <<
1663 interconnect- <<
1664 <<
1665 <<
1666 #address-cell 1467 #address-cells = <1>;
1667 #size-cells = 1468 #size-cells = <0>;
1668 status = "dis 1469 status = "disabled";
1669 }; 1470 };
1670 1471
1671 spi6: spi@998000 { 1472 spi6: spi@998000 {
1672 compatible = 1473 compatible = "qcom,geni-spi";
1673 reg = <0 0x00 1474 reg = <0 0x00998000 0 0x4000>;
1674 clock-names = 1475 clock-names = "se";
1675 clocks = <&gc 1476 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1676 interrupts = 1477 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1677 dmas = <&gpi_ 1478 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1678 <&gpi_ 1479 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1679 dma-names = " 1480 dma-names = "tx", "rx";
1680 power-domains !! 1481 power-domains = <&rpmhpd SM8250_CX>;
1681 operating-poi 1482 operating-points-v2 = <&qup_opp_table>;
1682 interconnects <<
1683 <<
1684 <<
1685 interconnect- <<
1686 <<
1687 <<
1688 #address-cell 1483 #address-cells = <1>;
1689 #size-cells = 1484 #size-cells = <0>;
1690 status = "dis 1485 status = "disabled";
1691 }; 1486 };
1692 1487
1693 uart6: serial@998000 1488 uart6: serial@998000 {
1694 compatible = 1489 compatible = "qcom,geni-uart";
1695 reg = <0 0x00 1490 reg = <0 0x00998000 0 0x4000>;
1696 clock-names = 1491 clock-names = "se";
1697 clocks = <&gc 1492 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1698 pinctrl-names 1493 pinctrl-names = "default";
1699 pinctrl-0 = < 1494 pinctrl-0 = <&qup_uart6_default>;
1700 interrupts = 1495 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1701 power-domains !! 1496 power-domains = <&rpmhpd SM8250_CX>;
1702 operating-poi 1497 operating-points-v2 = <&qup_opp_table>;
1703 interconnects <<
1704 <<
1705 interconnect- <<
1706 <<
1707 status = "dis 1498 status = "disabled";
1708 }; 1499 };
1709 1500
1710 i2c7: i2c@99c000 { 1501 i2c7: i2c@99c000 {
1711 compatible = 1502 compatible = "qcom,geni-i2c";
1712 reg = <0 0x00 1503 reg = <0 0x0099c000 0 0x4000>;
1713 clock-names = 1504 clock-names = "se";
1714 clocks = <&gc 1505 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1715 pinctrl-names 1506 pinctrl-names = "default";
1716 pinctrl-0 = < 1507 pinctrl-0 = <&qup_i2c7_default>;
1717 interrupts = 1508 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1718 dmas = <&gpi_ 1509 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1719 <&gpi_ 1510 <&gpi_dma0 1 7 QCOM_GPI_I2C>;
1720 dma-names = " 1511 dma-names = "tx", "rx";
1721 power-domains <<
1722 interconnects <<
1723 <<
1724 <<
1725 interconnect- <<
1726 <<
1727 <<
1728 #address-cell 1512 #address-cells = <1>;
1729 #size-cells = 1513 #size-cells = <0>;
1730 status = "dis 1514 status = "disabled";
1731 }; 1515 };
1732 1516
1733 spi7: spi@99c000 { 1517 spi7: spi@99c000 {
1734 compatible = 1518 compatible = "qcom,geni-spi";
1735 reg = <0 0x00 1519 reg = <0 0x0099c000 0 0x4000>;
1736 clock-names = 1520 clock-names = "se";
1737 clocks = <&gc 1521 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1738 interrupts = 1522 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1739 dmas = <&gpi_ 1523 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1740 <&gpi_ 1524 <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1741 dma-names = " 1525 dma-names = "tx", "rx";
1742 power-domains !! 1526 power-domains = <&rpmhpd SM8250_CX>;
1743 operating-poi 1527 operating-points-v2 = <&qup_opp_table>;
1744 interconnects <<
1745 <<
1746 <<
1747 interconnect- <<
1748 <<
1749 <<
1750 #address-cell 1528 #address-cells = <1>;
1751 #size-cells = 1529 #size-cells = <0>;
1752 status = "dis 1530 status = "disabled";
1753 }; 1531 };
1754 }; 1532 };
1755 1533
1756 gpi_dma1: dma-controller@a000 1534 gpi_dma1: dma-controller@a00000 {
1757 compatible = "qcom,sm 1535 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma";
1758 reg = <0 0x00a00000 0 1536 reg = <0 0x00a00000 0 0x70000>;
1759 interrupts = <GIC_SPI 1537 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1760 <GIC_SPI 1538 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1761 <GIC_SPI 1539 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1762 <GIC_SPI 1540 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1763 <GIC_SPI 1541 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1764 <GIC_SPI 1542 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1765 <GIC_SPI 1543 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1766 <GIC_SPI 1544 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1767 <GIC_SPI 1545 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1768 <GIC_SPI 1546 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>;
1769 dma-channels = <10>; 1547 dma-channels = <10>;
1770 dma-channel-mask = <0 1548 dma-channel-mask = <0x3f>;
1771 iommus = <&apps_smmu 1549 iommus = <&apps_smmu 0x56 0x0>;
1772 #dma-cells = <3>; 1550 #dma-cells = <3>;
1773 status = "disabled"; 1551 status = "disabled";
1774 }; 1552 };
1775 1553
1776 qupv3_id_1: geniqup@ac0000 { 1554 qupv3_id_1: geniqup@ac0000 {
1777 compatible = "qcom,ge 1555 compatible = "qcom,geni-se-qup";
1778 reg = <0x0 0x00ac0000 1556 reg = <0x0 0x00ac0000 0x0 0x6000>;
1779 clock-names = "m-ahb" 1557 clock-names = "m-ahb", "s-ahb";
1780 clocks = <&gcc GCC_QU 1558 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1781 <&gcc GCC_QU 1559 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1782 #address-cells = <2>; 1560 #address-cells = <2>;
1783 #size-cells = <2>; 1561 #size-cells = <2>;
1784 iommus = <&apps_smmu 1562 iommus = <&apps_smmu 0x43 0x0>;
1785 ranges; 1563 ranges;
1786 status = "disabled"; 1564 status = "disabled";
1787 1565
1788 i2c8: i2c@a80000 { 1566 i2c8: i2c@a80000 {
1789 compatible = 1567 compatible = "qcom,geni-i2c";
1790 reg = <0 0x00 1568 reg = <0 0x00a80000 0 0x4000>;
1791 clock-names = 1569 clock-names = "se";
1792 clocks = <&gc 1570 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1793 pinctrl-names 1571 pinctrl-names = "default";
1794 pinctrl-0 = < 1572 pinctrl-0 = <&qup_i2c8_default>;
1795 interrupts = 1573 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1796 dmas = <&gpi_ 1574 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1797 <&gpi_ 1575 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1798 dma-names = " 1576 dma-names = "tx", "rx";
1799 power-domains <<
1800 interconnects <<
1801 <<
1802 <<
1803 interconnect- <<
1804 <<
1805 <<
1806 #address-cell 1577 #address-cells = <1>;
1807 #size-cells = 1578 #size-cells = <0>;
1808 status = "dis 1579 status = "disabled";
1809 }; 1580 };
1810 1581
1811 spi8: spi@a80000 { 1582 spi8: spi@a80000 {
1812 compatible = 1583 compatible = "qcom,geni-spi";
1813 reg = <0 0x00 1584 reg = <0 0x00a80000 0 0x4000>;
1814 clock-names = 1585 clock-names = "se";
1815 clocks = <&gc 1586 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1816 interrupts = 1587 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1817 dmas = <&gpi_ 1588 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1818 <&gpi_ 1589 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1819 dma-names = " 1590 dma-names = "tx", "rx";
1820 power-domains !! 1591 power-domains = <&rpmhpd SM8250_CX>;
1821 operating-poi 1592 operating-points-v2 = <&qup_opp_table>;
1822 interconnects <<
1823 <<
1824 <<
1825 interconnect- <<
1826 <<
1827 <<
1828 #address-cell 1593 #address-cells = <1>;
1829 #size-cells = 1594 #size-cells = <0>;
1830 status = "dis 1595 status = "disabled";
1831 }; 1596 };
1832 1597
1833 i2c9: i2c@a84000 { 1598 i2c9: i2c@a84000 {
1834 compatible = 1599 compatible = "qcom,geni-i2c";
1835 reg = <0 0x00 1600 reg = <0 0x00a84000 0 0x4000>;
1836 clock-names = 1601 clock-names = "se";
1837 clocks = <&gc 1602 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1838 pinctrl-names 1603 pinctrl-names = "default";
1839 pinctrl-0 = < 1604 pinctrl-0 = <&qup_i2c9_default>;
1840 interrupts = 1605 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1841 dmas = <&gpi_ 1606 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1842 <&gpi_ 1607 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1843 dma-names = " 1608 dma-names = "tx", "rx";
1844 power-domains <<
1845 interconnects <<
1846 <<
1847 <<
1848 interconnect- <<
1849 <<
1850 <<
1851 #address-cell 1609 #address-cells = <1>;
1852 #size-cells = 1610 #size-cells = <0>;
1853 status = "dis 1611 status = "disabled";
1854 }; 1612 };
1855 1613
1856 spi9: spi@a84000 { 1614 spi9: spi@a84000 {
1857 compatible = 1615 compatible = "qcom,geni-spi";
1858 reg = <0 0x00 1616 reg = <0 0x00a84000 0 0x4000>;
1859 clock-names = 1617 clock-names = "se";
1860 clocks = <&gc 1618 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1861 interrupts = 1619 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1862 dmas = <&gpi_ 1620 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1863 <&gpi_ 1621 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1864 dma-names = " 1622 dma-names = "tx", "rx";
1865 power-domains !! 1623 power-domains = <&rpmhpd SM8250_CX>;
1866 operating-poi 1624 operating-points-v2 = <&qup_opp_table>;
1867 interconnects <<
1868 <<
1869 <<
1870 interconnect- <<
1871 <<
1872 <<
1873 #address-cell 1625 #address-cells = <1>;
1874 #size-cells = 1626 #size-cells = <0>;
1875 status = "dis 1627 status = "disabled";
1876 }; 1628 };
1877 1629
1878 i2c10: i2c@a88000 { 1630 i2c10: i2c@a88000 {
1879 compatible = 1631 compatible = "qcom,geni-i2c";
1880 reg = <0 0x00 1632 reg = <0 0x00a88000 0 0x4000>;
1881 clock-names = 1633 clock-names = "se";
1882 clocks = <&gc 1634 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1883 pinctrl-names 1635 pinctrl-names = "default";
1884 pinctrl-0 = < 1636 pinctrl-0 = <&qup_i2c10_default>;
1885 interrupts = 1637 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1886 dmas = <&gpi_ 1638 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1887 <&gpi_ 1639 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1888 dma-names = " 1640 dma-names = "tx", "rx";
1889 power-domains <<
1890 interconnects <<
1891 <<
1892 <<
1893 interconnect- <<
1894 <<
1895 <<
1896 #address-cell 1641 #address-cells = <1>;
1897 #size-cells = 1642 #size-cells = <0>;
1898 status = "dis 1643 status = "disabled";
1899 }; 1644 };
1900 1645
1901 spi10: spi@a88000 { 1646 spi10: spi@a88000 {
1902 compatible = 1647 compatible = "qcom,geni-spi";
1903 reg = <0 0x00 1648 reg = <0 0x00a88000 0 0x4000>;
1904 clock-names = 1649 clock-names = "se";
1905 clocks = <&gc 1650 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1906 interrupts = 1651 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1907 dmas = <&gpi_ 1652 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1908 <&gpi_ 1653 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1909 dma-names = " 1654 dma-names = "tx", "rx";
1910 power-domains !! 1655 power-domains = <&rpmhpd SM8250_CX>;
1911 operating-poi 1656 operating-points-v2 = <&qup_opp_table>;
1912 interconnects <<
1913 <<
1914 <<
1915 interconnect- <<
1916 <<
1917 <<
1918 #address-cell 1657 #address-cells = <1>;
1919 #size-cells = 1658 #size-cells = <0>;
1920 status = "dis 1659 status = "disabled";
1921 }; 1660 };
1922 1661
1923 i2c11: i2c@a8c000 { 1662 i2c11: i2c@a8c000 {
1924 compatible = 1663 compatible = "qcom,geni-i2c";
1925 reg = <0 0x00 1664 reg = <0 0x00a8c000 0 0x4000>;
1926 clock-names = 1665 clock-names = "se";
1927 clocks = <&gc 1666 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1928 pinctrl-names 1667 pinctrl-names = "default";
1929 pinctrl-0 = < 1668 pinctrl-0 = <&qup_i2c11_default>;
1930 interrupts = 1669 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1931 dmas = <&gpi_ 1670 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1932 <&gpi_ 1671 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1933 dma-names = " 1672 dma-names = "tx", "rx";
1934 power-domains <<
1935 interconnects <<
1936 <<
1937 <<
1938 interconnect- <<
1939 <<
1940 <<
1941 #address-cell 1673 #address-cells = <1>;
1942 #size-cells = 1674 #size-cells = <0>;
1943 status = "dis 1675 status = "disabled";
1944 }; 1676 };
1945 1677
1946 spi11: spi@a8c000 { 1678 spi11: spi@a8c000 {
1947 compatible = 1679 compatible = "qcom,geni-spi";
1948 reg = <0 0x00 1680 reg = <0 0x00a8c000 0 0x4000>;
1949 clock-names = 1681 clock-names = "se";
1950 clocks = <&gc 1682 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1951 interrupts = 1683 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1952 dmas = <&gpi_ 1684 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1953 <&gpi_ 1685 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1954 dma-names = " 1686 dma-names = "tx", "rx";
1955 power-domains !! 1687 power-domains = <&rpmhpd SM8250_CX>;
1956 operating-poi 1688 operating-points-v2 = <&qup_opp_table>;
1957 interconnects <<
1958 <<
1959 <<
1960 interconnect- <<
1961 <<
1962 <<
1963 #address-cell 1689 #address-cells = <1>;
1964 #size-cells = 1690 #size-cells = <0>;
1965 status = "dis 1691 status = "disabled";
1966 }; 1692 };
1967 1693
1968 i2c12: i2c@a90000 { 1694 i2c12: i2c@a90000 {
1969 compatible = 1695 compatible = "qcom,geni-i2c";
1970 reg = <0 0x00 1696 reg = <0 0x00a90000 0 0x4000>;
1971 clock-names = 1697 clock-names = "se";
1972 clocks = <&gc 1698 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1973 pinctrl-names 1699 pinctrl-names = "default";
1974 pinctrl-0 = < 1700 pinctrl-0 = <&qup_i2c12_default>;
1975 interrupts = 1701 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1976 dmas = <&gpi_ 1702 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1977 <&gpi_ 1703 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1978 dma-names = " 1704 dma-names = "tx", "rx";
1979 power-domains <<
1980 interconnects <<
1981 <<
1982 <<
1983 interconnect- <<
1984 <<
1985 <<
1986 #address-cell 1705 #address-cells = <1>;
1987 #size-cells = 1706 #size-cells = <0>;
1988 status = "dis 1707 status = "disabled";
1989 }; 1708 };
1990 1709
1991 spi12: spi@a90000 { 1710 spi12: spi@a90000 {
1992 compatible = 1711 compatible = "qcom,geni-spi";
1993 reg = <0 0x00 1712 reg = <0 0x00a90000 0 0x4000>;
1994 clock-names = 1713 clock-names = "se";
1995 clocks = <&gc 1714 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1996 interrupts = 1715 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1997 dmas = <&gpi_ 1716 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1998 <&gpi_ 1717 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1999 dma-names = " 1718 dma-names = "tx", "rx";
2000 power-domains !! 1719 power-domains = <&rpmhpd SM8250_CX>;
2001 operating-poi 1720 operating-points-v2 = <&qup_opp_table>;
2002 interconnects <<
2003 <<
2004 <<
2005 interconnect- <<
2006 <<
2007 <<
2008 #address-cell 1721 #address-cells = <1>;
2009 #size-cells = 1722 #size-cells = <0>;
2010 status = "dis 1723 status = "disabled";
2011 }; 1724 };
2012 1725
2013 uart12: serial@a90000 1726 uart12: serial@a90000 {
2014 compatible = 1727 compatible = "qcom,geni-debug-uart";
2015 reg = <0x0 0x 1728 reg = <0x0 0x00a90000 0x0 0x4000>;
2016 clock-names = 1729 clock-names = "se";
2017 clocks = <&gc 1730 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
2018 pinctrl-names 1731 pinctrl-names = "default";
2019 pinctrl-0 = < 1732 pinctrl-0 = <&qup_uart12_default>;
2020 interrupts = 1733 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
2021 power-domains !! 1734 power-domains = <&rpmhpd SM8250_CX>;
2022 operating-poi 1735 operating-points-v2 = <&qup_opp_table>;
2023 interconnects <<
2024 <<
2025 interconnect- <<
2026 <<
2027 status = "dis 1736 status = "disabled";
2028 }; 1737 };
2029 1738
2030 i2c13: i2c@a94000 { 1739 i2c13: i2c@a94000 {
2031 compatible = 1740 compatible = "qcom,geni-i2c";
2032 reg = <0 0x00 1741 reg = <0 0x00a94000 0 0x4000>;
2033 clock-names = 1742 clock-names = "se";
2034 clocks = <&gc 1743 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2035 pinctrl-names 1744 pinctrl-names = "default";
2036 pinctrl-0 = < 1745 pinctrl-0 = <&qup_i2c13_default>;
2037 interrupts = 1746 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2038 dmas = <&gpi_ 1747 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
2039 <&gpi_ 1748 <&gpi_dma1 1 5 QCOM_GPI_I2C>;
2040 dma-names = " 1749 dma-names = "tx", "rx";
2041 power-domains <<
2042 interconnects <<
2043 <<
2044 <<
2045 interconnect- <<
2046 <<
2047 <<
2048 #address-cell 1750 #address-cells = <1>;
2049 #size-cells = 1751 #size-cells = <0>;
2050 status = "dis 1752 status = "disabled";
2051 }; 1753 };
2052 1754
2053 spi13: spi@a94000 { 1755 spi13: spi@a94000 {
2054 compatible = 1756 compatible = "qcom,geni-spi";
2055 reg = <0 0x00 1757 reg = <0 0x00a94000 0 0x4000>;
2056 clock-names = 1758 clock-names = "se";
2057 clocks = <&gc 1759 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2058 interrupts = 1760 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2059 dmas = <&gpi_ 1761 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
2060 <&gpi_ 1762 <&gpi_dma1 1 5 QCOM_GPI_SPI>;
2061 dma-names = " 1763 dma-names = "tx", "rx";
2062 power-domains !! 1764 power-domains = <&rpmhpd SM8250_CX>;
2063 operating-poi 1765 operating-points-v2 = <&qup_opp_table>;
2064 interconnects <<
2065 <<
2066 <<
2067 interconnect- <<
2068 <<
2069 <<
2070 #address-cell 1766 #address-cells = <1>;
2071 #size-cells = 1767 #size-cells = <0>;
2072 status = "dis 1768 status = "disabled";
2073 }; 1769 };
2074 }; 1770 };
2075 1771
2076 config_noc: interconnect@1500 1772 config_noc: interconnect@1500000 {
2077 compatible = "qcom,sm 1773 compatible = "qcom,sm8250-config-noc";
2078 reg = <0 0x01500000 0 1774 reg = <0 0x01500000 0 0xa580>;
2079 #interconnect-cells = !! 1775 #interconnect-cells = <1>;
2080 qcom,bcm-voters = <&a 1776 qcom,bcm-voters = <&apps_bcm_voter>;
2081 }; 1777 };
2082 1778
2083 system_noc: interconnect@1620 1779 system_noc: interconnect@1620000 {
2084 compatible = "qcom,sm 1780 compatible = "qcom,sm8250-system-noc";
2085 reg = <0 0x01620000 0 1781 reg = <0 0x01620000 0 0x1c200>;
2086 #interconnect-cells = !! 1782 #interconnect-cells = <1>;
2087 qcom,bcm-voters = <&a 1783 qcom,bcm-voters = <&apps_bcm_voter>;
2088 }; 1784 };
2089 1785
2090 mc_virt: interconnect@163d000 1786 mc_virt: interconnect@163d000 {
2091 compatible = "qcom,sm 1787 compatible = "qcom,sm8250-mc-virt";
2092 reg = <0 0x0163d000 0 1788 reg = <0 0x0163d000 0 0x1000>;
2093 #interconnect-cells = !! 1789 #interconnect-cells = <1>;
2094 qcom,bcm-voters = <&a 1790 qcom,bcm-voters = <&apps_bcm_voter>;
2095 }; 1791 };
2096 1792
2097 aggre1_noc: interconnect@16e0 1793 aggre1_noc: interconnect@16e0000 {
2098 compatible = "qcom,sm 1794 compatible = "qcom,sm8250-aggre1-noc";
2099 reg = <0 0x016e0000 0 1795 reg = <0 0x016e0000 0 0x1f180>;
2100 #interconnect-cells = !! 1796 #interconnect-cells = <1>;
2101 qcom,bcm-voters = <&a 1797 qcom,bcm-voters = <&apps_bcm_voter>;
2102 }; 1798 };
2103 1799
2104 aggre2_noc: interconnect@1700 1800 aggre2_noc: interconnect@1700000 {
2105 compatible = "qcom,sm 1801 compatible = "qcom,sm8250-aggre2-noc";
2106 reg = <0 0x01700000 0 1802 reg = <0 0x01700000 0 0x33000>;
2107 #interconnect-cells = !! 1803 #interconnect-cells = <1>;
2108 qcom,bcm-voters = <&a 1804 qcom,bcm-voters = <&apps_bcm_voter>;
2109 }; 1805 };
2110 1806
2111 compute_noc: interconnect@173 1807 compute_noc: interconnect@1733000 {
2112 compatible = "qcom,sm 1808 compatible = "qcom,sm8250-compute-noc";
2113 reg = <0 0x01733000 0 1809 reg = <0 0x01733000 0 0xa180>;
2114 #interconnect-cells = !! 1810 #interconnect-cells = <1>;
2115 qcom,bcm-voters = <&a 1811 qcom,bcm-voters = <&apps_bcm_voter>;
2116 }; 1812 };
2117 1813
2118 mmss_noc: interconnect@174000 1814 mmss_noc: interconnect@1740000 {
2119 compatible = "qcom,sm 1815 compatible = "qcom,sm8250-mmss-noc";
2120 reg = <0 0x01740000 0 1816 reg = <0 0x01740000 0 0x1f080>;
2121 #interconnect-cells = !! 1817 #interconnect-cells = <1>;
2122 qcom,bcm-voters = <&a 1818 qcom,bcm-voters = <&apps_bcm_voter>;
2123 }; 1819 };
2124 1820
2125 pcie0: pcie@1c00000 { !! 1821 pcie0: pci@1c00000 {
2126 compatible = "qcom,pc 1822 compatible = "qcom,pcie-sm8250";
2127 reg = <0 0x01c00000 0 1823 reg = <0 0x01c00000 0 0x3000>,
2128 <0 0x60000000 0 1824 <0 0x60000000 0 0xf1d>,
2129 <0 0x60000f20 0 1825 <0 0x60000f20 0 0xa8>,
2130 <0 0x60001000 0 1826 <0 0x60001000 0 0x1000>,
2131 <0 0x60100000 0 !! 1827 <0 0x60100000 0 0x100000>;
2132 <0 0x01c03000 0 !! 1828 reg-names = "parf", "dbi", "elbi", "atu", "config";
2133 reg-names = "parf", " <<
2134 device_type = "pci"; 1829 device_type = "pci";
2135 linux,pci-domain = <0 1830 linux,pci-domain = <0>;
2136 bus-range = <0x00 0xf 1831 bus-range = <0x00 0xff>;
2137 num-lanes = <1>; 1832 num-lanes = <1>;
2138 1833
2139 #address-cells = <3>; 1834 #address-cells = <3>;
2140 #size-cells = <2>; 1835 #size-cells = <2>;
2141 1836
2142 ranges = <0x01000000 1837 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
2143 <0x02000000 1838 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
2144 1839
2145 interrupts = <GIC_SPI 1840 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
2146 <GIC_SPI 1841 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
2147 <GIC_SPI 1842 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
2148 <GIC_SPI 1843 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
2149 <GIC_SPI 1844 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
2150 <GIC_SPI 1845 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
2151 <GIC_SPI 1846 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
2152 <GIC_SPI 1847 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2153 interrupt-names = "ms !! 1848 interrupt-names = "msi0", "msi1", "msi2", "msi3",
2154 "ms !! 1849 "msi4", "msi5", "msi6", "msi7";
2155 "ms <<
2156 "ms <<
2157 "ms <<
2158 "ms <<
2159 "ms <<
2160 "ms <<
2161 #interrupt-cells = <1 1850 #interrupt-cells = <1>;
2162 interrupt-map-mask = 1851 interrupt-map-mask = <0 0 0 0x7>;
2163 interrupt-map = <0 0 1852 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2164 <0 0 1853 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2165 <0 0 1854 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2166 <0 0 1855 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2167 1856
2168 clocks = <&gcc GCC_PC 1857 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
2169 <&gcc GCC_PC 1858 <&gcc GCC_PCIE_0_AUX_CLK>,
2170 <&gcc GCC_PC 1859 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2171 <&gcc GCC_PC 1860 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
2172 <&gcc GCC_PC 1861 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
2173 <&gcc GCC_PC 1862 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
2174 <&gcc GCC_AG 1863 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
2175 <&gcc GCC_DD 1864 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
2176 clock-names = "pipe", 1865 clock-names = "pipe",
2177 "aux", 1866 "aux",
2178 "cfg", 1867 "cfg",
2179 "bus_ma 1868 "bus_master",
2180 "bus_sl 1869 "bus_slave",
2181 "slave_ 1870 "slave_q2a",
2182 "tbu", 1871 "tbu",
2183 "ddrss_ 1872 "ddrss_sf_tbu";
2184 1873
>> 1874 iommus = <&apps_smmu 0x1c00 0x7f>;
2185 iommu-map = <0x0 &a 1875 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
2186 <0x100 &a 1876 <0x100 &apps_smmu 0x1c01 0x1>;
2187 1877
2188 resets = <&gcc GCC_PC 1878 resets = <&gcc GCC_PCIE_0_BCR>;
2189 reset-names = "pci"; 1879 reset-names = "pci";
2190 1880
2191 power-domains = <&gcc 1881 power-domains = <&gcc PCIE_0_GDSC>;
2192 1882
2193 phys = <&pcie0_phy>; !! 1883 phys = <&pcie0_lane>;
2194 phy-names = "pciephy" 1884 phy-names = "pciephy";
2195 1885
2196 perst-gpios = <&tlmm 1886 perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>;
2197 wake-gpios = <&tlmm 8 1887 wake-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
2198 1888
2199 pinctrl-names = "defa 1889 pinctrl-names = "default";
2200 pinctrl-0 = <&pcie0_d 1890 pinctrl-0 = <&pcie0_default_state>;
2201 dma-coherent; <<
2202 1891
2203 status = "disabled"; 1892 status = "disabled";
2204 <<
2205 pcieport0: pcie@0 { <<
2206 device_type = <<
2207 reg = <0x0 0x <<
2208 bus-range = < <<
2209 <<
2210 #address-cell <<
2211 #size-cells = <<
2212 ranges; <<
2213 }; <<
2214 }; 1893 };
2215 1894
2216 pcie0_phy: phy@1c06000 { 1895 pcie0_phy: phy@1c06000 {
2217 compatible = "qcom,sm 1896 compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy";
2218 reg = <0 0x01c06000 0 !! 1897 reg = <0 0x01c06000 0 0x1c0>;
2219 !! 1898 #address-cells = <2>;
>> 1899 #size-cells = <2>;
>> 1900 ranges;
2220 clocks = <&gcc GCC_PC 1901 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2221 <&gcc GCC_PC 1902 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2222 <&gcc GCC_PC 1903 <&gcc GCC_PCIE_WIFI_CLKREF_EN>,
2223 <&gcc GCC_PC !! 1904 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
2224 <&gcc GCC_PC !! 1905 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2225 clock-names = "aux", <<
2226 "cfg_ah <<
2227 "ref", <<
2228 "refgen <<
2229 "pipe"; <<
2230 <<
2231 clock-output-names = <<
2232 #clock-cells = <0>; <<
2233 <<
2234 #phy-cells = <0>; <<
2235 1906
2236 resets = <&gcc GCC_PC 1907 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
2237 reset-names = "phy"; 1908 reset-names = "phy";
2238 1909
2239 assigned-clocks = <&g 1910 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
2240 assigned-clock-rates 1911 assigned-clock-rates = <100000000>;
2241 1912
2242 status = "disabled"; 1913 status = "disabled";
>> 1914
>> 1915 pcie0_lane: phy@1c06200 {
>> 1916 reg = <0 0x01c06200 0 0x170>, /* tx */
>> 1917 <0 0x01c06400 0 0x200>, /* rx */
>> 1918 <0 0x01c06800 0 0x1f0>, /* pcs */
>> 1919 <0 0x01c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */
>> 1920 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
>> 1921 clock-names = "pipe0";
>> 1922
>> 1923 #phy-cells = <0>;
>> 1924
>> 1925 #clock-cells = <0>;
>> 1926 clock-output-names = "pcie_0_pipe_clk";
>> 1927 };
2243 }; 1928 };
2244 1929
2245 pcie1: pcie@1c08000 { !! 1930 pcie1: pci@1c08000 {
2246 compatible = "qcom,pc 1931 compatible = "qcom,pcie-sm8250";
2247 reg = <0 0x01c08000 0 1932 reg = <0 0x01c08000 0 0x3000>,
2248 <0 0x40000000 0 1933 <0 0x40000000 0 0xf1d>,
2249 <0 0x40000f20 0 1934 <0 0x40000f20 0 0xa8>,
2250 <0 0x40001000 0 1935 <0 0x40001000 0 0x1000>,
2251 <0 0x40100000 0 !! 1936 <0 0x40100000 0 0x100000>;
2252 <0 0x01c0b000 0 !! 1937 reg-names = "parf", "dbi", "elbi", "atu", "config";
2253 reg-names = "parf", " <<
2254 device_type = "pci"; 1938 device_type = "pci";
2255 linux,pci-domain = <1 1939 linux,pci-domain = <1>;
2256 bus-range = <0x00 0xf 1940 bus-range = <0x00 0xff>;
2257 num-lanes = <2>; 1941 num-lanes = <2>;
2258 1942
2259 #address-cells = <3>; 1943 #address-cells = <3>;
2260 #size-cells = <2>; 1944 #size-cells = <2>;
2261 1945
2262 ranges = <0x01000000 1946 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
2263 <0x02000000 1947 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
2264 1948
2265 interrupts = <GIC_SPI !! 1949 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
2266 <GIC_SPI !! 1950 interrupt-names = "msi";
2267 <GIC_SPI <<
2268 <GIC_SPI <<
2269 <GIC_SPI <<
2270 <GIC_SPI <<
2271 <GIC_SPI <<
2272 <GIC_SPI <<
2273 interrupt-names = "ms <<
2274 "ms <<
2275 "ms <<
2276 "ms <<
2277 "ms <<
2278 "ms <<
2279 "ms <<
2280 "ms <<
2281 #interrupt-cells = <1 1951 #interrupt-cells = <1>;
2282 interrupt-map-mask = 1952 interrupt-map-mask = <0 0 0 0x7>;
2283 interrupt-map = <0 0 1953 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2284 <0 0 1954 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2285 <0 0 1955 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2286 <0 0 1956 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2287 1957
2288 clocks = <&gcc GCC_PC 1958 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
2289 <&gcc GCC_PC 1959 <&gcc GCC_PCIE_1_AUX_CLK>,
2290 <&gcc GCC_PC 1960 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2291 <&gcc GCC_PC 1961 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
2292 <&gcc GCC_PC 1962 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
2293 <&gcc GCC_PC 1963 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
2294 <&gcc GCC_PC 1964 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
2295 <&gcc GCC_AG 1965 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
2296 <&gcc GCC_DD 1966 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
2297 clock-names = "pipe", 1967 clock-names = "pipe",
2298 "aux", 1968 "aux",
2299 "cfg", 1969 "cfg",
2300 "bus_ma 1970 "bus_master",
2301 "bus_sl 1971 "bus_slave",
2302 "slave_ 1972 "slave_q2a",
2303 "ref", 1973 "ref",
2304 "tbu", 1974 "tbu",
2305 "ddrss_ 1975 "ddrss_sf_tbu";
2306 1976
2307 assigned-clocks = <&g 1977 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2308 assigned-clock-rates 1978 assigned-clock-rates = <19200000>;
2309 1979
>> 1980 iommus = <&apps_smmu 0x1c80 0x7f>;
2310 iommu-map = <0x0 &a 1981 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
2311 <0x100 &a 1982 <0x100 &apps_smmu 0x1c81 0x1>;
2312 1983
2313 resets = <&gcc GCC_PC 1984 resets = <&gcc GCC_PCIE_1_BCR>;
2314 reset-names = "pci"; 1985 reset-names = "pci";
2315 1986
2316 power-domains = <&gcc 1987 power-domains = <&gcc PCIE_1_GDSC>;
2317 1988
2318 phys = <&pcie1_phy>; !! 1989 phys = <&pcie1_lane>;
2319 phy-names = "pciephy" 1990 phy-names = "pciephy";
2320 1991
2321 perst-gpios = <&tlmm 1992 perst-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>;
2322 wake-gpios = <&tlmm 8 1993 wake-gpios = <&tlmm 84 GPIO_ACTIVE_HIGH>;
2323 1994
2324 pinctrl-names = "defa 1995 pinctrl-names = "default";
2325 pinctrl-0 = <&pcie1_d 1996 pinctrl-0 = <&pcie1_default_state>;
2326 dma-coherent; <<
2327 1997
2328 status = "disabled"; 1998 status = "disabled";
2329 <<
2330 pcie@0 { <<
2331 device_type = <<
2332 reg = <0x0 0x <<
2333 bus-range = < <<
2334 <<
2335 #address-cell <<
2336 #size-cells = <<
2337 ranges; <<
2338 }; <<
2339 }; 1999 };
2340 2000
2341 pcie1_phy: phy@1c0e000 { 2001 pcie1_phy: phy@1c0e000 {
2342 compatible = "qcom,sm 2002 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
2343 reg = <0 0x01c0e000 0 !! 2003 reg = <0 0x01c0e000 0 0x1c0>;
2344 !! 2004 #address-cells = <2>;
>> 2005 #size-cells = <2>;
>> 2006 ranges;
2345 clocks = <&gcc GCC_PC 2007 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2346 <&gcc GCC_PC 2008 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2347 <&gcc GCC_PC 2009 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
2348 <&gcc GCC_PC !! 2010 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
2349 <&gcc GCC_PC !! 2011 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2350 clock-names = "aux", <<
2351 "cfg_ah <<
2352 "ref", <<
2353 "refgen <<
2354 "pipe"; <<
2355 <<
2356 clock-output-names = <<
2357 #clock-cells = <0>; <<
2358 <<
2359 #phy-cells = <0>; <<
2360 2012
2361 resets = <&gcc GCC_PC 2013 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2362 reset-names = "phy"; 2014 reset-names = "phy";
2363 2015
2364 assigned-clocks = <&g 2016 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
2365 assigned-clock-rates 2017 assigned-clock-rates = <100000000>;
2366 2018
2367 status = "disabled"; 2019 status = "disabled";
>> 2020
>> 2021 pcie1_lane: phy@1c0e200 {
>> 2022 reg = <0 0x01c0e200 0 0x170>, /* tx0 */
>> 2023 <0 0x01c0e400 0 0x200>, /* rx0 */
>> 2024 <0 0x01c0ea00 0 0x1f0>, /* pcs */
>> 2025 <0 0x01c0e600 0 0x170>, /* tx1 */
>> 2026 <0 0x01c0e800 0 0x200>, /* rx1 */
>> 2027 <0 0x01c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */
>> 2028 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
>> 2029 clock-names = "pipe0";
>> 2030
>> 2031 #phy-cells = <0>;
>> 2032
>> 2033 #clock-cells = <0>;
>> 2034 clock-output-names = "pcie_1_pipe_clk";
>> 2035 };
2368 }; 2036 };
2369 2037
2370 pcie2: pcie@1c10000 { !! 2038 pcie2: pci@1c10000 {
2371 compatible = "qcom,pc 2039 compatible = "qcom,pcie-sm8250";
2372 reg = <0 0x01c10000 0 2040 reg = <0 0x01c10000 0 0x3000>,
2373 <0 0x64000000 0 2041 <0 0x64000000 0 0xf1d>,
2374 <0 0x64000f20 0 2042 <0 0x64000f20 0 0xa8>,
2375 <0 0x64001000 0 2043 <0 0x64001000 0 0x1000>,
2376 <0 0x64100000 0 !! 2044 <0 0x64100000 0 0x100000>;
2377 <0 0x01c13000 0 !! 2045 reg-names = "parf", "dbi", "elbi", "atu", "config";
2378 reg-names = "parf", " <<
2379 device_type = "pci"; 2046 device_type = "pci";
2380 linux,pci-domain = <2 2047 linux,pci-domain = <2>;
2381 bus-range = <0x00 0xf 2048 bus-range = <0x00 0xff>;
2382 num-lanes = <2>; 2049 num-lanes = <2>;
2383 2050
2384 #address-cells = <3>; 2051 #address-cells = <3>;
2385 #size-cells = <2>; 2052 #size-cells = <2>;
2386 2053
2387 ranges = <0x01000000 2054 ranges = <0x01000000 0x0 0x00000000 0x0 0x64200000 0x0 0x100000>,
2388 <0x02000000 2055 <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>;
2389 2056
2390 interrupts = <GIC_SPI !! 2057 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
2391 <GIC_SPI !! 2058 interrupt-names = "msi";
2392 <GIC_SPI <<
2393 <GIC_SPI <<
2394 <GIC_SPI <<
2395 <GIC_SPI <<
2396 <GIC_SPI <<
2397 <GIC_SPI <<
2398 interrupt-names = "ms <<
2399 "ms <<
2400 "ms <<
2401 "ms <<
2402 "ms <<
2403 "ms <<
2404 "ms <<
2405 "ms <<
2406 #interrupt-cells = <1 2059 #interrupt-cells = <1>;
2407 interrupt-map-mask = 2060 interrupt-map-mask = <0 0 0 0x7>;
2408 interrupt-map = <0 0 2061 interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2409 <0 0 2062 <0 0 0 2 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2410 <0 0 2063 <0 0 0 3 &intc 0 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2411 <0 0 2064 <0 0 0 4 &intc 0 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2412 2065
2413 clocks = <&gcc GCC_PC 2066 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
2414 <&gcc GCC_PC 2067 <&gcc GCC_PCIE_2_AUX_CLK>,
2415 <&gcc GCC_PC 2068 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2416 <&gcc GCC_PC 2069 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
2417 <&gcc GCC_PC 2070 <&gcc GCC_PCIE_2_SLV_AXI_CLK>,
2418 <&gcc GCC_PC 2071 <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>,
2419 <&gcc GCC_PC 2072 <&gcc GCC_PCIE_MDM_CLKREF_EN>,
2420 <&gcc GCC_AG 2073 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
2421 <&gcc GCC_DD 2074 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
2422 clock-names = "pipe", 2075 clock-names = "pipe",
2423 "aux", 2076 "aux",
2424 "cfg", 2077 "cfg",
2425 "bus_ma 2078 "bus_master",
2426 "bus_sl 2079 "bus_slave",
2427 "slave_ 2080 "slave_q2a",
2428 "ref", 2081 "ref",
2429 "tbu", 2082 "tbu",
2430 "ddrss_ 2083 "ddrss_sf_tbu";
2431 2084
2432 assigned-clocks = <&g 2085 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>;
2433 assigned-clock-rates 2086 assigned-clock-rates = <19200000>;
2434 2087
>> 2088 iommus = <&apps_smmu 0x1d00 0x7f>;
2435 iommu-map = <0x0 &a 2089 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>,
2436 <0x100 &a 2090 <0x100 &apps_smmu 0x1d01 0x1>;
2437 2091
2438 resets = <&gcc GCC_PC 2092 resets = <&gcc GCC_PCIE_2_BCR>;
2439 reset-names = "pci"; 2093 reset-names = "pci";
2440 2094
2441 power-domains = <&gcc 2095 power-domains = <&gcc PCIE_2_GDSC>;
2442 2096
2443 phys = <&pcie2_phy>; !! 2097 phys = <&pcie2_lane>;
2444 phy-names = "pciephy" 2098 phy-names = "pciephy";
2445 2099
2446 perst-gpios = <&tlmm 2100 perst-gpios = <&tlmm 85 GPIO_ACTIVE_LOW>;
2447 wake-gpios = <&tlmm 8 2101 wake-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>;
2448 2102
2449 pinctrl-names = "defa 2103 pinctrl-names = "default";
2450 pinctrl-0 = <&pcie2_d 2104 pinctrl-0 = <&pcie2_default_state>;
2451 dma-coherent; <<
2452 2105
2453 status = "disabled"; 2106 status = "disabled";
2454 <<
2455 pcie@0 { <<
2456 device_type = <<
2457 reg = <0x0 0x <<
2458 bus-range = < <<
2459 <<
2460 #address-cell <<
2461 #size-cells = <<
2462 ranges; <<
2463 }; <<
2464 }; 2107 };
2465 2108
2466 pcie2_phy: phy@1c16000 { 2109 pcie2_phy: phy@1c16000 {
2467 compatible = "qcom,sm 2110 compatible = "qcom,sm8250-qmp-modem-pcie-phy";
2468 reg = <0 0x01c16000 0 !! 2111 reg = <0 0x01c16000 0 0x1c0>;
2469 !! 2112 #address-cells = <2>;
>> 2113 #size-cells = <2>;
>> 2114 ranges;
2470 clocks = <&gcc GCC_PC 2115 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2471 <&gcc GCC_PC 2116 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2472 <&gcc GCC_PC 2117 <&gcc GCC_PCIE_MDM_CLKREF_EN>,
2473 <&gcc GCC_PC !! 2118 <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
2474 <&gcc GCC_PC !! 2119 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2475 clock-names = "aux", <<
2476 "cfg_ah <<
2477 "ref", <<
2478 "refgen <<
2479 "pipe"; <<
2480 <<
2481 clock-output-names = <<
2482 #clock-cells = <0>; <<
2483 <<
2484 #phy-cells = <0>; <<
2485 2120
2486 resets = <&gcc GCC_PC 2121 resets = <&gcc GCC_PCIE_2_PHY_BCR>;
2487 reset-names = "phy"; 2122 reset-names = "phy";
2488 2123
2489 assigned-clocks = <&g 2124 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
2490 assigned-clock-rates 2125 assigned-clock-rates = <100000000>;
2491 2126
2492 status = "disabled"; 2127 status = "disabled";
>> 2128
>> 2129 pcie2_lane: phy@1c16200 {
>> 2130 reg = <0 0x01c16200 0 0x170>, /* tx0 */
>> 2131 <0 0x01c16400 0 0x200>, /* rx0 */
>> 2132 <0 0x01c16a00 0 0x1f0>, /* pcs */
>> 2133 <0 0x01c16600 0 0x170>, /* tx1 */
>> 2134 <0 0x01c16800 0 0x200>, /* rx1 */
>> 2135 <0 0x01c16e00 0 0xf4>; /* "pcs_com" same as pcs_misc? */
>> 2136 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
>> 2137 clock-names = "pipe0";
>> 2138
>> 2139 #phy-cells = <0>;
>> 2140
>> 2141 #clock-cells = <0>;
>> 2142 clock-output-names = "pcie_2_pipe_clk";
>> 2143 };
2493 }; 2144 };
2494 2145
2495 ufs_mem_hc: ufshc@1d84000 { 2146 ufs_mem_hc: ufshc@1d84000 {
2496 compatible = "qcom,sm 2147 compatible = "qcom,sm8250-ufshc", "qcom,ufshc",
2497 "jedec,u 2148 "jedec,ufs-2.0";
2498 reg = <0 0x01d84000 0 2149 reg = <0 0x01d84000 0 0x3000>;
2499 interrupts = <GIC_SPI 2150 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2500 phys = <&ufs_mem_phy> !! 2151 phys = <&ufs_mem_phy_lanes>;
2501 phy-names = "ufsphy"; 2152 phy-names = "ufsphy";
2502 lanes-per-direction = 2153 lanes-per-direction = <2>;
2503 #reset-cells = <1>; 2154 #reset-cells = <1>;
2504 resets = <&gcc GCC_UF 2155 resets = <&gcc GCC_UFS_PHY_BCR>;
2505 reset-names = "rst"; 2156 reset-names = "rst";
2506 2157
2507 power-domains = <&gcc 2158 power-domains = <&gcc UFS_PHY_GDSC>;
2508 2159
2509 iommus = <&apps_smmu 2160 iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>;
2510 2161
2511 clock-names = 2162 clock-names =
2512 "core_clk", 2163 "core_clk",
2513 "bus_aggr_clk 2164 "bus_aggr_clk",
2514 "iface_clk", 2165 "iface_clk",
2515 "core_clk_uni 2166 "core_clk_unipro",
2516 "ref_clk", 2167 "ref_clk",
2517 "tx_lane0_syn 2168 "tx_lane0_sync_clk",
2518 "rx_lane0_syn 2169 "rx_lane0_sync_clk",
2519 "rx_lane1_syn 2170 "rx_lane1_sync_clk";
2520 clocks = 2171 clocks =
2521 <&gcc GCC_UFS 2172 <&gcc GCC_UFS_PHY_AXI_CLK>,
2522 <&gcc GCC_AGG 2173 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2523 <&gcc GCC_UFS 2174 <&gcc GCC_UFS_PHY_AHB_CLK>,
2524 <&gcc GCC_UFS 2175 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2525 <&rpmhcc RPMH 2176 <&rpmhcc RPMH_CXO_CLK>,
2526 <&gcc GCC_UFS 2177 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2527 <&gcc GCC_UFS 2178 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2528 <&gcc GCC_UFS 2179 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
2529 !! 2180 freq-table-hz =
2530 operating-points-v2 = !! 2181 <37500000 300000000>,
2531 !! 2182 <0 0>,
2532 interconnects = <&agg !! 2183 <0 0>,
2533 <&gem !! 2184 <37500000 300000000>,
2534 interconnect-names = !! 2185 <0 0>,
>> 2186 <0 0>,
>> 2187 <0 0>,
>> 2188 <0 0>;
2535 2189
2536 status = "disabled"; 2190 status = "disabled";
2537 <<
2538 ufs_opp_table: opp-ta <<
2539 compatible = <<
2540 <<
2541 opp-37500000 <<
2542 opp-h <<
2543 <<
2544 <<
2545 <<
2546 <<
2547 <<
2548 <<
2549 <<
2550 requi <<
2551 }; <<
2552 <<
2553 opp-300000000 <<
2554 opp-h <<
2555 <<
2556 <<
2557 <<
2558 <<
2559 <<
2560 <<
2561 <<
2562 requi <<
2563 }; <<
2564 }; <<
2565 }; 2191 };
2566 2192
2567 ufs_mem_phy: phy@1d87000 { 2193 ufs_mem_phy: phy@1d87000 {
2568 compatible = "qcom,sm 2194 compatible = "qcom,sm8250-qmp-ufs-phy";
2569 reg = <0 0x01d87000 0 !! 2195 reg = <0 0x01d87000 0 0x1c0>;
2570 !! 2196 #address-cells = <2>;
2571 clocks = <&rpmhcc RPM !! 2197 #size-cells = <2>;
2572 <&gcc GCC_UF !! 2198 ranges;
2573 <&gcc GCC_UF <<
2574 clock-names = "ref", 2199 clock-names = "ref",
2575 "ref_au !! 2200 "ref_aux";
2576 "qref"; !! 2201 clocks = <&rpmhcc RPMH_CXO_CLK>,
>> 2202 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2577 2203
2578 resets = <&ufs_mem_hc 2204 resets = <&ufs_mem_hc 0>;
2579 reset-names = "ufsphy 2205 reset-names = "ufsphy";
2580 <<
2581 power-domains = <&gcc <<
2582 <<
2583 #phy-cells = <0>; <<
2584 <<
2585 status = "disabled"; 2206 status = "disabled";
2586 }; <<
2587 2207
2588 cryptobam: dma-controller@1dc !! 2208 ufs_mem_phy_lanes: phy@1d87400 {
2589 compatible = "qcom,ba !! 2209 reg = <0 0x01d87400 0 0x16c>,
2590 reg = <0 0x01dc4000 0 !! 2210 <0 0x01d87600 0 0x200>,
2591 interrupts = <GIC_SPI !! 2211 <0 0x01d87c00 0 0x200>,
2592 #dma-cells = <1>; !! 2212 <0 0x01d87800 0 0x16c>,
2593 qcom,ee = <0>; !! 2213 <0 0x01d87a00 0 0x200>;
2594 qcom,controlled-remot !! 2214 #phy-cells = <0>;
2595 num-channels = <8>; !! 2215 };
2596 qcom,num-ees = <2>; <<
2597 iommus = <&apps_smmu <<
2598 <&apps_smmu <<
2599 <&apps_smmu <<
2600 <&apps_smmu <<
2601 <&apps_smmu <<
2602 <&apps_smmu <<
2603 }; <<
2604 <<
2605 crypto: crypto@1dfa000 { <<
2606 compatible = "qcom,sm <<
2607 reg = <0 0x01dfa000 0 <<
2608 dmas = <&cryptobam 4> <<
2609 dma-names = "rx", "tx <<
2610 iommus = <&apps_smmu <<
2611 <&apps_smmu <<
2612 <&apps_smmu <<
2613 <&apps_smmu <<
2614 <&apps_smmu <<
2615 <&apps_smmu <<
2616 interconnects = <&agg <<
2617 interconnect-names = <<
2618 }; 2216 };
2619 2217
2620 tcsr_mutex: hwlock@1f40000 { 2218 tcsr_mutex: hwlock@1f40000 {
2621 compatible = "qcom,tc 2219 compatible = "qcom,tcsr-mutex";
2622 reg = <0x0 0x01f40000 2220 reg = <0x0 0x01f40000 0x0 0x40000>;
2623 #hwlock-cells = <1>; 2221 #hwlock-cells = <1>;
2624 }; 2222 };
2625 2223
2626 tcsr: syscon@1fc0000 { <<
2627 compatible = "qcom,sm <<
2628 reg = <0x0 0x1fc0000 <<
2629 }; <<
2630 <<
2631 wsamacro: codec@3240000 { 2224 wsamacro: codec@3240000 {
2632 compatible = "qcom,sm 2225 compatible = "qcom,sm8250-lpass-wsa-macro";
2633 reg = <0 0x03240000 0 2226 reg = <0 0x03240000 0 0x1000>;
2634 clocks = <&q6afecc LP !! 2227 clocks = <&audiocc LPASS_CDC_WSA_MCLK>,
2635 <&q6afecc LP !! 2228 <&audiocc LPASS_CDC_WSA_NPL>,
2636 <&q6afecc LP 2229 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2637 <&q6afecc LP 2230 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 2231 <&aoncc LPASS_CDC_VA_MCLK>,
2638 <&vamacro>; 2232 <&vamacro>;
2639 2233
2640 clock-names = "mclk", !! 2234 clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen";
2641 2235
2642 #clock-cells = <0>; 2236 #clock-cells = <0>;
2643 clock-output-names = 2237 clock-output-names = "mclk";
2644 #sound-dai-cells = <1 2238 #sound-dai-cells = <1>;
2645 2239
2646 pinctrl-names = "defa 2240 pinctrl-names = "default";
2647 pinctrl-0 = <&wsa_swr 2241 pinctrl-0 = <&wsa_swr_active>;
2648 2242
2649 status = "disabled"; 2243 status = "disabled";
2650 }; 2244 };
2651 2245
2652 swr0: soundwire@3250000 { !! 2246 swr0: soundwire-controller@3250000 {
2653 reg = <0 0x03250000 0 2247 reg = <0 0x03250000 0 0x2000>;
2654 compatible = "qcom,so 2248 compatible = "qcom,soundwire-v1.5.1";
2655 interrupts = <GIC_SPI 2249 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
2656 clocks = <&wsamacro>; 2250 clocks = <&wsamacro>;
2657 clock-names = "iface" 2251 clock-names = "iface";
2658 2252
2659 qcom,din-ports = <2>; 2253 qcom,din-ports = <2>;
2660 qcom,dout-ports = <6> 2254 qcom,dout-ports = <6>;
2661 2255
2662 qcom,ports-sinterval- 2256 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2663 qcom,ports-offset1 = 2257 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2664 qcom,ports-offset2 = 2258 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2665 qcom,ports-block-pack 2259 qcom,ports-block-pack-mode = /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>;
2666 2260
2667 #sound-dai-cells = <1 2261 #sound-dai-cells = <1>;
2668 #address-cells = <2>; 2262 #address-cells = <2>;
2669 #size-cells = <0>; 2263 #size-cells = <0>;
2670 2264
2671 status = "disabled"; 2265 status = "disabled";
2672 }; 2266 };
2673 2267
>> 2268 audiocc: clock-controller@3300000 {
>> 2269 compatible = "qcom,sm8250-lpass-audiocc";
>> 2270 reg = <0 0x03300000 0 0x30000>;
>> 2271 #clock-cells = <1>;
>> 2272 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 2273 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 2274 <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
>> 2275 clock-names = "core", "audio", "bus";
>> 2276 };
>> 2277
2674 vamacro: codec@3370000 { 2278 vamacro: codec@3370000 {
2675 compatible = "qcom,sm 2279 compatible = "qcom,sm8250-lpass-va-macro";
2676 reg = <0 0x03370000 0 2280 reg = <0 0x03370000 0 0x1000>;
2677 clocks = <&q6afecc LP !! 2281 clocks = <&aoncc LPASS_CDC_VA_MCLK>,
2678 <&q6afecc LPA 2282 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2679 <&q6afecc LPA 2283 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2680 2284
2681 clock-names = "mclk", 2285 clock-names = "mclk", "macro", "dcodec";
2682 2286
2683 #clock-cells = <0>; 2287 #clock-cells = <0>;
2684 clock-output-names = 2288 clock-output-names = "fsgen";
2685 #sound-dai-cells = <1 2289 #sound-dai-cells = <1>;
2686 }; 2290 };
2687 2291
2688 rxmacro: rxmacro@3200000 { 2292 rxmacro: rxmacro@3200000 {
2689 pinctrl-names = "defa 2293 pinctrl-names = "default";
2690 pinctrl-0 = <&rx_swr_ 2294 pinctrl-0 = <&rx_swr_active>;
2691 compatible = "qcom,sm 2295 compatible = "qcom,sm8250-lpass-rx-macro";
2692 reg = <0 0x03200000 0 2296 reg = <0 0x03200000 0 0x1000>;
2693 status = "disabled"; 2297 status = "disabled";
2694 2298
2695 clocks = <&q6afecc LP 2299 clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2696 <&q6afecc LPA 2300 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2697 <&q6afecc LPA 2301 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2698 <&q6afecc LPA 2302 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2699 <&vamacro>; 2303 <&vamacro>;
2700 2304
2701 clock-names = "mclk", 2305 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2702 2306
2703 #clock-cells = <0>; 2307 #clock-cells = <0>;
2704 clock-output-names = 2308 clock-output-names = "mclk";
2705 #sound-dai-cells = <1 2309 #sound-dai-cells = <1>;
2706 }; 2310 };
2707 2311
2708 swr1: soundwire@3210000 { !! 2312 swr1: soundwire-controller@3210000 {
2709 reg = <0 0x03210000 0 2313 reg = <0 0x03210000 0 0x2000>;
2710 compatible = "qcom,so 2314 compatible = "qcom,soundwire-v1.5.1";
2711 status = "disabled"; 2315 status = "disabled";
2712 interrupts = <GIC_SPI 2316 interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
2713 clocks = <&rxmacro>; 2317 clocks = <&rxmacro>;
2714 clock-names = "iface" 2318 clock-names = "iface";
2715 label = "RX"; 2319 label = "RX";
2716 qcom,din-ports = <0>; 2320 qcom,din-ports = <0>;
2717 qcom,dout-ports = <5> 2321 qcom,dout-ports = <5>;
2718 2322
2719 qcom,ports-sinterval- 2323 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
2720 qcom,ports-offset1 = 2324 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>;
2721 qcom,ports-offset2 = 2325 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
2722 qcom,ports-hstart = 2326 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
2723 qcom,ports-hstop = 2327 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
2724 qcom,ports-word-lengt 2328 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2725 qcom,ports-block-pack 2329 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
2726 qcom,ports-lane-contr 2330 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2727 qcom,ports-block-grou 2331 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
2728 2332
2729 #sound-dai-cells = <1 2333 #sound-dai-cells = <1>;
2730 #address-cells = <2>; 2334 #address-cells = <2>;
2731 #size-cells = <0>; 2335 #size-cells = <0>;
2732 }; 2336 };
2733 2337
2734 txmacro: txmacro@3220000 { 2338 txmacro: txmacro@3220000 {
2735 pinctrl-names = "defa 2339 pinctrl-names = "default";
2736 pinctrl-0 = <&tx_swr_ 2340 pinctrl-0 = <&tx_swr_active>;
2737 compatible = "qcom,sm 2341 compatible = "qcom,sm8250-lpass-tx-macro";
2738 reg = <0 0x03220000 0 2342 reg = <0 0x03220000 0 0x1000>;
2739 status = "disabled"; 2343 status = "disabled";
2740 2344
2741 clocks = <&q6afecc LP 2345 clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2742 <&q6afecc LP 2346 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2743 <&q6afecc LP 2347 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2744 <&q6afecc LP 2348 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2745 <&vamacro>; 2349 <&vamacro>;
2746 2350
2747 clock-names = "mclk", 2351 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2748 2352
2749 #clock-cells = <0>; 2353 #clock-cells = <0>;
2750 clock-output-names = 2354 clock-output-names = "mclk";
2751 #sound-dai-cells = <1 2355 #sound-dai-cells = <1>;
2752 }; 2356 };
2753 2357
2754 /* tx macro */ 2358 /* tx macro */
2755 swr2: soundwire@3230000 { !! 2359 swr2: soundwire-controller@3230000 {
2756 reg = <0 0x03230000 0 2360 reg = <0 0x03230000 0 0x2000>;
2757 compatible = "qcom,so 2361 compatible = "qcom,soundwire-v1.5.1";
2758 interrupts = <GIC_SPI !! 2362 interrupts-extended = <&intc GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
2759 interrupt-names = "co 2363 interrupt-names = "core";
2760 status = "disabled"; 2364 status = "disabled";
2761 2365
2762 clocks = <&txmacro>; 2366 clocks = <&txmacro>;
2763 clock-names = "iface" 2367 clock-names = "iface";
2764 label = "TX"; 2368 label = "TX";
2765 2369
2766 qcom,din-ports = <5>; 2370 qcom,din-ports = <5>;
2767 qcom,dout-ports = <0> 2371 qcom,dout-ports = <0>;
2768 qcom,ports-sinterval- 2372 qcom,ports-sinterval-low = /bits/ 8 <0xff 0x01 0x01 0x03 0x03>;
2769 qcom,ports-offset1 = 2373 qcom,ports-offset1 = /bits/ 8 <0xff 0x01 0x00 0x02 0x00>;
2770 qcom,ports-offset2 = 2374 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x00 0x00 0x00>;
2771 qcom,ports-block-pack 2375 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2772 qcom,ports-hstart = 2376 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2773 qcom,ports-hstop = 2377 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2774 qcom,ports-word-lengt 2378 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2775 qcom,ports-block-grou 2379 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2776 qcom,ports-lane-contr 2380 qcom,ports-lane-control = /bits/ 8 <0xff 0x00 0x01 0x00 0x01>;
2777 #sound-dai-cells = <1 2381 #sound-dai-cells = <1>;
2778 #address-cells = <2>; 2382 #address-cells = <2>;
2779 #size-cells = <0>; 2383 #size-cells = <0>;
2780 }; 2384 };
2781 2385
>> 2386 aoncc: clock-controller@3380000 {
>> 2387 compatible = "qcom,sm8250-lpass-aoncc";
>> 2388 reg = <0 0x03380000 0 0x40000>;
>> 2389 #clock-cells = <1>;
>> 2390 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 2391 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 2392 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
>> 2393 clock-names = "core", "audio", "bus";
>> 2394 };
>> 2395
2782 lpass_tlmm: pinctrl@33c0000 { 2396 lpass_tlmm: pinctrl@33c0000 {
2783 compatible = "qcom,sm 2397 compatible = "qcom,sm8250-lpass-lpi-pinctrl";
2784 reg = <0 0x033c0000 0 2398 reg = <0 0x033c0000 0x0 0x20000>,
2785 <0 0x03550000 0 2399 <0 0x03550000 0x0 0x10000>;
2786 gpio-controller; 2400 gpio-controller;
2787 #gpio-cells = <2>; 2401 #gpio-cells = <2>;
2788 gpio-ranges = <&lpass 2402 gpio-ranges = <&lpass_tlmm 0 0 14>;
2789 2403
2790 clocks = <&q6afecc LP 2404 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2791 <&q6afecc LPA 2405 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2792 clock-names = "core", 2406 clock-names = "core", "audio";
2793 2407
2794 wsa_swr_active: wsa-s 2408 wsa_swr_active: wsa-swr-active-state {
2795 clk-pins { 2409 clk-pins {
2796 pins 2410 pins = "gpio10";
2797 funct 2411 function = "wsa_swr_clk";
2798 drive 2412 drive-strength = <2>;
2799 slew- 2413 slew-rate = <1>;
2800 bias- 2414 bias-disable;
2801 }; 2415 };
2802 2416
2803 data-pins { 2417 data-pins {
2804 pins 2418 pins = "gpio11";
2805 funct 2419 function = "wsa_swr_data";
2806 drive 2420 drive-strength = <2>;
2807 slew- 2421 slew-rate = <1>;
2808 bias- 2422 bias-bus-hold;
>> 2423
2809 }; 2424 };
2810 }; 2425 };
2811 2426
2812 wsa_swr_sleep: wsa-sw 2427 wsa_swr_sleep: wsa-swr-sleep-state {
2813 clk-pins { 2428 clk-pins {
2814 pins 2429 pins = "gpio10";
2815 funct 2430 function = "wsa_swr_clk";
2816 drive 2431 drive-strength = <2>;
>> 2432 input-enable;
2817 bias- 2433 bias-pull-down;
2818 }; 2434 };
2819 2435
2820 data-pins { 2436 data-pins {
2821 pins 2437 pins = "gpio11";
2822 funct 2438 function = "wsa_swr_data";
2823 drive 2439 drive-strength = <2>;
>> 2440 input-enable;
2824 bias- 2441 bias-pull-down;
>> 2442
2825 }; 2443 };
2826 }; 2444 };
2827 2445
2828 dmic01_active: dmic01 2446 dmic01_active: dmic01-active-state {
2829 clk-pins { 2447 clk-pins {
2830 pins 2448 pins = "gpio6";
2831 funct 2449 function = "dmic1_clk";
2832 drive 2450 drive-strength = <8>;
2833 outpu 2451 output-high;
2834 }; 2452 };
2835 data-pins { 2453 data-pins {
2836 pins 2454 pins = "gpio7";
2837 funct 2455 function = "dmic1_data";
2838 drive 2456 drive-strength = <8>;
>> 2457 input-enable;
2839 }; 2458 };
2840 }; 2459 };
2841 2460
2842 dmic01_sleep: dmic01- 2461 dmic01_sleep: dmic01-sleep-state {
2843 clk-pins { 2462 clk-pins {
2844 pins 2463 pins = "gpio6";
2845 funct 2464 function = "dmic1_clk";
2846 drive 2465 drive-strength = <2>;
2847 bias- 2466 bias-disable;
2848 outpu 2467 output-low;
2849 }; 2468 };
2850 2469
2851 data-pins { 2470 data-pins {
2852 pins 2471 pins = "gpio7";
2853 funct 2472 function = "dmic1_data";
2854 drive 2473 drive-strength = <2>;
2855 bias- 2474 bias-pull-down;
>> 2475 input-enable;
2856 }; 2476 };
2857 }; 2477 };
2858 2478
2859 rx_swr_active: rx-swr 2479 rx_swr_active: rx-swr-active-state {
2860 clk-pins { 2480 clk-pins {
2861 pins 2481 pins = "gpio3";
2862 funct 2482 function = "swr_rx_clk";
2863 drive 2483 drive-strength = <2>;
2864 slew- 2484 slew-rate = <1>;
2865 bias- 2485 bias-disable;
2866 }; 2486 };
2867 2487
2868 data-pins { 2488 data-pins {
2869 pins 2489 pins = "gpio4", "gpio5";
2870 funct 2490 function = "swr_rx_data";
2871 drive 2491 drive-strength = <2>;
2872 slew- 2492 slew-rate = <1>;
2873 bias- 2493 bias-bus-hold;
2874 }; 2494 };
2875 }; 2495 };
2876 2496
2877 tx_swr_active: tx-swr 2497 tx_swr_active: tx-swr-active-state {
2878 clk-pins { 2498 clk-pins {
2879 pins 2499 pins = "gpio0";
2880 funct 2500 function = "swr_tx_clk";
2881 drive 2501 drive-strength = <2>;
2882 slew- 2502 slew-rate = <1>;
2883 bias- 2503 bias-disable;
2884 }; 2504 };
2885 2505
2886 data-pins { 2506 data-pins {
2887 pins 2507 pins = "gpio1", "gpio2";
2888 funct 2508 function = "swr_tx_data";
2889 drive 2509 drive-strength = <2>;
2890 slew- 2510 slew-rate = <1>;
2891 bias- 2511 bias-bus-hold;
2892 }; 2512 };
2893 }; 2513 };
2894 2514
2895 tx_swr_sleep: tx-swr- 2515 tx_swr_sleep: tx-swr-sleep-state {
2896 clk-pins { 2516 clk-pins {
2897 pins 2517 pins = "gpio0";
2898 funct 2518 function = "swr_tx_clk";
2899 drive 2519 drive-strength = <2>;
>> 2520 input-enable;
2900 bias- 2521 bias-pull-down;
2901 }; 2522 };
2902 2523
2903 data1-pins { 2524 data1-pins {
2904 pins 2525 pins = "gpio1";
2905 funct 2526 function = "swr_tx_data";
2906 drive 2527 drive-strength = <2>;
>> 2528 input-enable;
2907 bias- 2529 bias-bus-hold;
2908 }; 2530 };
2909 2531
2910 data2-pins { 2532 data2-pins {
2911 pins 2533 pins = "gpio2";
2912 funct 2534 function = "swr_tx_data";
2913 drive 2535 drive-strength = <2>;
>> 2536 input-enable;
2914 bias- 2537 bias-pull-down;
2915 }; 2538 };
2916 }; 2539 };
2917 }; 2540 };
2918 2541
2919 gpu: gpu@3d00000 { 2542 gpu: gpu@3d00000 {
2920 compatible = "qcom,ad 2543 compatible = "qcom,adreno-650.2",
2921 "qcom,ad 2544 "qcom,adreno";
2922 2545
2923 reg = <0 0x03d00000 0 2546 reg = <0 0x03d00000 0 0x40000>;
2924 reg-names = "kgsl_3d0 2547 reg-names = "kgsl_3d0_reg_memory";
2925 2548
2926 interrupts = <GIC_SPI 2549 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2927 2550
2928 iommus = <&adreno_smm 2551 iommus = <&adreno_smmu 0 0x401>;
2929 2552
2930 operating-points-v2 = 2553 operating-points-v2 = <&gpu_opp_table>;
2931 2554
2932 qcom,gmu = <&gmu>; 2555 qcom,gmu = <&gmu>;
2933 2556
2934 nvmem-cells = <&gpu_s <<
2935 nvmem-cell-names = "s <<
2936 #cooling-cells = <2>; <<
2937 <<
2938 status = "disabled"; 2557 status = "disabled";
2939 2558
2940 zap-shader { 2559 zap-shader {
2941 memory-region 2560 memory-region = <&gpu_mem>;
2942 }; 2561 };
2943 2562
>> 2563 /* note: downstream checks gpu binning for 670 Mhz */
2944 gpu_opp_table: opp-ta 2564 gpu_opp_table: opp-table {
2945 compatible = 2565 compatible = "operating-points-v2";
2946 2566
2947 opp-670000000 2567 opp-670000000 {
2948 opp-h 2568 opp-hz = /bits/ 64 <670000000>;
2949 opp-l 2569 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2950 opp-s <<
2951 }; 2570 };
2952 2571
2953 opp-587000000 2572 opp-587000000 {
2954 opp-h 2573 opp-hz = /bits/ 64 <587000000>;
2955 opp-l 2574 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2956 opp-s <<
2957 }; 2575 };
2958 2576
2959 opp-525000000 2577 opp-525000000 {
2960 opp-h 2578 opp-hz = /bits/ 64 <525000000>;
2961 opp-l 2579 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2962 opp-s <<
2963 }; 2580 };
2964 2581
2965 opp-490000000 2582 opp-490000000 {
2966 opp-h 2583 opp-hz = /bits/ 64 <490000000>;
2967 opp-l 2584 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2968 opp-s <<
2969 }; 2585 };
2970 2586
2971 opp-441600000 2587 opp-441600000 {
2972 opp-h 2588 opp-hz = /bits/ 64 <441600000>;
2973 opp-l 2589 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
2974 opp-s <<
2975 }; 2590 };
2976 2591
2977 opp-400000000 2592 opp-400000000 {
2978 opp-h 2593 opp-hz = /bits/ 64 <400000000>;
2979 opp-l 2594 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2980 opp-s <<
2981 }; 2595 };
2982 2596
2983 opp-305000000 2597 opp-305000000 {
2984 opp-h 2598 opp-hz = /bits/ 64 <305000000>;
2985 opp-l 2599 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2986 opp-s <<
2987 }; 2600 };
2988 }; 2601 };
2989 }; 2602 };
2990 2603
2991 gmu: gmu@3d6a000 { 2604 gmu: gmu@3d6a000 {
2992 compatible = "qcom,ad 2605 compatible = "qcom,adreno-gmu-650.2", "qcom,adreno-gmu";
2993 2606
2994 reg = <0 0x03d6a000 0 2607 reg = <0 0x03d6a000 0 0x30000>,
2995 <0 0x3de0000 0 2608 <0 0x3de0000 0 0x10000>,
2996 <0 0xb290000 0 2609 <0 0xb290000 0 0x10000>,
2997 <0 0xb490000 0 2610 <0 0xb490000 0 0x10000>;
2998 reg-names = "gmu", "r 2611 reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq";
2999 2612
3000 interrupts = <GIC_SPI 2613 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
3001 <GIC_SPI 2614 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
3002 interrupt-names = "hf 2615 interrupt-names = "hfi", "gmu";
3003 2616
3004 clocks = <&gpucc GPU_ 2617 clocks = <&gpucc GPU_CC_AHB_CLK>,
3005 <&gpucc GPU_ 2618 <&gpucc GPU_CC_CX_GMU_CLK>,
3006 <&gpucc GPU_ 2619 <&gpucc GPU_CC_CXO_CLK>,
3007 <&gcc GCC_DD 2620 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
3008 <&gcc GCC_GP 2621 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
3009 clock-names = "ahb", 2622 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
3010 2623
3011 power-domains = <&gpu 2624 power-domains = <&gpucc GPU_CX_GDSC>,
3012 <&gpu 2625 <&gpucc GPU_GX_GDSC>;
3013 power-domain-names = 2626 power-domain-names = "cx", "gx";
3014 2627
3015 iommus = <&adreno_smm 2628 iommus = <&adreno_smmu 5 0x400>;
3016 2629
3017 operating-points-v2 = 2630 operating-points-v2 = <&gmu_opp_table>;
3018 2631
3019 status = "disabled"; 2632 status = "disabled";
3020 2633
3021 gmu_opp_table: opp-ta 2634 gmu_opp_table: opp-table {
3022 compatible = 2635 compatible = "operating-points-v2";
3023 2636
3024 opp-200000000 2637 opp-200000000 {
3025 opp-h 2638 opp-hz = /bits/ 64 <200000000>;
3026 opp-l 2639 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3027 }; 2640 };
3028 }; 2641 };
3029 }; 2642 };
3030 2643
3031 gpucc: clock-controller@3d900 2644 gpucc: clock-controller@3d90000 {
3032 compatible = "qcom,sm 2645 compatible = "qcom,sm8250-gpucc";
3033 reg = <0 0x03d90000 0 2646 reg = <0 0x03d90000 0 0x9000>;
3034 clocks = <&rpmhcc RPM 2647 clocks = <&rpmhcc RPMH_CXO_CLK>,
3035 <&gcc GCC_GP 2648 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
3036 <&gcc GCC_GP 2649 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
3037 clock-names = "bi_tcx 2650 clock-names = "bi_tcxo",
3038 "gcc_gp 2651 "gcc_gpu_gpll0_clk_src",
3039 "gcc_gp 2652 "gcc_gpu_gpll0_div_clk_src";
3040 #clock-cells = <1>; 2653 #clock-cells = <1>;
3041 #reset-cells = <1>; 2654 #reset-cells = <1>;
3042 #power-domain-cells = 2655 #power-domain-cells = <1>;
3043 }; 2656 };
3044 2657
3045 adreno_smmu: iommu@3da0000 { 2658 adreno_smmu: iommu@3da0000 {
3046 compatible = "qcom,sm !! 2659 compatible = "qcom,sm8250-smmu-500", "qcom,adreno-smmu", "arm,mmu-500";
3047 "qcom,sm <<
3048 reg = <0 0x03da0000 0 2660 reg = <0 0x03da0000 0 0x10000>;
3049 #iommu-cells = <2>; 2661 #iommu-cells = <2>;
3050 #global-interrupts = 2662 #global-interrupts = <2>;
3051 interrupts = <GIC_SPI 2663 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
3052 <GIC_SPI 2664 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
3053 <GIC_SPI 2665 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
3054 <GIC_SPI 2666 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
3055 <GIC_SPI 2667 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
3056 <GIC_SPI 2668 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
3057 <GIC_SPI 2669 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
3058 <GIC_SPI 2670 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
3059 <GIC_SPI 2671 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
3060 <GIC_SPI 2672 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>;
3061 clocks = <&gpucc GPU_ 2673 clocks = <&gpucc GPU_CC_AHB_CLK>,
3062 <&gcc GCC_GP 2674 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
3063 <&gcc GCC_GP 2675 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
3064 clock-names = "ahb", 2676 clock-names = "ahb", "bus", "iface";
3065 2677
3066 power-domains = <&gpu 2678 power-domains = <&gpucc GPU_CX_GDSC>;
3067 dma-coherent; <<
3068 }; 2679 };
3069 2680
3070 slpi: remoteproc@5c00000 { 2681 slpi: remoteproc@5c00000 {
3071 compatible = "qcom,sm 2682 compatible = "qcom,sm8250-slpi-pas";
3072 reg = <0 0x05c00000 0 2683 reg = <0 0x05c00000 0 0x4000>;
3073 2684
3074 interrupts-extended = !! 2685 interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
3075 2686 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
3076 2687 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
3077 2688 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
3078 2689 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
3079 interrupt-names = "wd 2690 interrupt-names = "wdog", "fatal", "ready",
3080 "ha 2691 "handover", "stop-ack";
3081 2692
3082 clocks = <&rpmhcc RPM 2693 clocks = <&rpmhcc RPMH_CXO_CLK>;
3083 clock-names = "xo"; 2694 clock-names = "xo";
3084 2695
3085 power-domains = <&rpm !! 2696 power-domains = <&rpmhpd SM8250_LCX>,
3086 <&rpm !! 2697 <&rpmhpd SM8250_LMX>;
3087 power-domain-names = 2698 power-domain-names = "lcx", "lmx";
3088 2699
3089 memory-region = <&slp 2700 memory-region = <&slpi_mem>;
3090 2701
3091 qcom,qmp = <&aoss_qmp 2702 qcom,qmp = <&aoss_qmp>;
3092 2703
3093 qcom,smem-states = <& 2704 qcom,smem-states = <&smp2p_slpi_out 0>;
3094 qcom,smem-state-names 2705 qcom,smem-state-names = "stop";
3095 2706
3096 status = "disabled"; 2707 status = "disabled";
3097 2708
3098 glink-edge { 2709 glink-edge {
3099 interrupts-ex 2710 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
3100 2711 IPCC_MPROC_SIGNAL_GLINK_QMP
3101 2712 IRQ_TYPE_EDGE_RISING>;
3102 mboxes = <&ip 2713 mboxes = <&ipcc IPCC_CLIENT_SLPI
3103 2714 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3104 2715
3105 label = "slpi 2716 label = "slpi";
3106 qcom,remote-p 2717 qcom,remote-pid = <3>;
3107 2718
3108 fastrpc { 2719 fastrpc {
3109 compa 2720 compatible = "qcom,fastrpc";
3110 qcom, 2721 qcom,glink-channels = "fastrpcglink-apps-dsp";
3111 label 2722 label = "sdsp";
3112 qcom, 2723 qcom,non-secure-domain;
3113 #addr 2724 #address-cells = <1>;
3114 #size 2725 #size-cells = <0>;
3115 2726
3116 compu 2727 compute-cb@1 {
3117 2728 compatible = "qcom,fastrpc-compute-cb";
3118 2729 reg = <1>;
3119 2730 iommus = <&apps_smmu 0x0541 0x0>;
3120 }; 2731 };
3121 2732
3122 compu 2733 compute-cb@2 {
3123 2734 compatible = "qcom,fastrpc-compute-cb";
3124 2735 reg = <2>;
3125 2736 iommus = <&apps_smmu 0x0542 0x0>;
3126 }; 2737 };
3127 2738
3128 compu 2739 compute-cb@3 {
3129 2740 compatible = "qcom,fastrpc-compute-cb";
3130 2741 reg = <3>;
3131 2742 iommus = <&apps_smmu 0x0543 0x0>;
3132 2743 /* note: shared-cb = <4> in downstream */
3133 }; 2744 };
3134 }; 2745 };
3135 }; 2746 };
3136 }; 2747 };
3137 2748
3138 stm@6002000 { 2749 stm@6002000 {
3139 compatible = "arm,cor 2750 compatible = "arm,coresight-stm", "arm,primecell";
3140 reg = <0 0x06002000 0 2751 reg = <0 0x06002000 0 0x1000>, <0 0x16280000 0 0x180000>;
3141 reg-names = "stm-base 2752 reg-names = "stm-base", "stm-stimulus-base";
3142 2753
3143 clocks = <&aoss_qmp>; 2754 clocks = <&aoss_qmp>;
3144 clock-names = "apb_pc 2755 clock-names = "apb_pclk";
3145 2756
3146 out-ports { 2757 out-ports {
3147 port { 2758 port {
3148 stm_o 2759 stm_out: endpoint {
3149 2760 remote-endpoint = <&funnel0_in7>;
3150 }; 2761 };
3151 }; 2762 };
3152 }; 2763 };
3153 }; 2764 };
3154 2765
3155 tpda@6004000 { <<
3156 compatible = "qcom,co <<
3157 reg = <0 0x06004000 0 <<
3158 <<
3159 clocks = <&aoss_qmp>; <<
3160 clock-names = "apb_pc <<
3161 <<
3162 out-ports { <<
3163 <<
3164 port { <<
3165 tpda_ <<
3166 <<
3167 }; <<
3168 }; <<
3169 }; <<
3170 <<
3171 in-ports { <<
3172 #address-cell <<
3173 #size-cells = <<
3174 <<
3175 port@9 { <<
3176 reg = <<
3177 tpda_ <<
3178 <<
3179 }; <<
3180 }; <<
3181 <<
3182 port@17 { <<
3183 reg = <<
3184 tpda_ <<
3185 <<
3186 }; <<
3187 }; <<
3188 }; <<
3189 }; <<
3190 <<
3191 funnel@6005000 { <<
3192 compatible = "arm,cor <<
3193 reg = <0 0x06005000 0 <<
3194 <<
3195 clocks = <&aoss_qmp>; <<
3196 clock-names = "apb_pc <<
3197 <<
3198 out-ports { <<
3199 port { <<
3200 funne <<
3201 <<
3202 }; <<
3203 }; <<
3204 }; <<
3205 <<
3206 in-ports { <<
3207 port { <<
3208 funne <<
3209 <<
3210 }; <<
3211 }; <<
3212 }; <<
3213 }; <<
3214 <<
3215 funnel@6041000 { 2766 funnel@6041000 {
3216 compatible = "arm,cor 2767 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3217 reg = <0 0x06041000 0 2768 reg = <0 0x06041000 0 0x1000>;
3218 2769
3219 clocks = <&aoss_qmp>; 2770 clocks = <&aoss_qmp>;
3220 clock-names = "apb_pc 2771 clock-names = "apb_pclk";
3221 2772
3222 out-ports { 2773 out-ports {
3223 port { 2774 port {
3224 funne 2775 funnel_in0_out_funnel_merg: endpoint {
3225 2776 remote-endpoint = <&funnel_merg_in_funnel_in0>;
3226 }; 2777 };
3227 }; 2778 };
3228 }; 2779 };
3229 2780
3230 in-ports { 2781 in-ports {
3231 #address-cell 2782 #address-cells = <1>;
3232 #size-cells = 2783 #size-cells = <0>;
3233 2784
3234 port@6 { <<
3235 reg = <<
3236 funne <<
3237 <<
3238 }; <<
3239 }; <<
3240 <<
3241 port@7 { 2785 port@7 {
3242 reg = 2786 reg = <7>;
3243 funne 2787 funnel0_in7: endpoint {
3244 2788 remote-endpoint = <&stm_out>;
3245 }; 2789 };
3246 }; 2790 };
3247 }; 2791 };
3248 }; 2792 };
3249 2793
3250 funnel@6042000 { 2794 funnel@6042000 {
3251 compatible = "arm,cor 2795 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3252 reg = <0 0x06042000 0 2796 reg = <0 0x06042000 0 0x1000>;
3253 2797
3254 clocks = <&aoss_qmp>; 2798 clocks = <&aoss_qmp>;
3255 clock-names = "apb_pc 2799 clock-names = "apb_pclk";
3256 2800
3257 out-ports { 2801 out-ports {
3258 port { !! 2802 #address-cells = <1>;
>> 2803 #size-cells = <0>;
>> 2804
>> 2805 port@0 {
>> 2806 reg = <0>;
3259 funne 2807 funnel_in1_out_funnel_merg: endpoint {
3260 2808 remote-endpoint = <&funnel_merg_in_funnel_in1>;
3261 }; 2809 };
3262 }; 2810 };
3263 }; 2811 };
3264 2812
3265 in-ports { 2813 in-ports {
3266 #address-cell 2814 #address-cells = <1>;
3267 #size-cells = 2815 #size-cells = <0>;
3268 2816
3269 port@4 { 2817 port@4 {
3270 reg = 2818 reg = <4>;
3271 funne 2819 funnel_in1_in_funnel_apss_merg: endpoint {
3272 remot 2820 remote-endpoint = <&funnel_apss_merg_out_funnel_in1>;
3273 }; 2821 };
3274 }; 2822 };
3275 }; 2823 };
3276 }; 2824 };
3277 2825
3278 funnel@6045000 { 2826 funnel@6045000 {
3279 compatible = "arm,cor 2827 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3280 reg = <0 0x06045000 0 2828 reg = <0 0x06045000 0 0x1000>;
3281 2829
3282 clocks = <&aoss_qmp>; 2830 clocks = <&aoss_qmp>;
3283 clock-names = "apb_pc 2831 clock-names = "apb_pclk";
3284 2832
3285 out-ports { 2833 out-ports {
3286 port { 2834 port {
3287 funne 2835 funnel_merg_out_funnel_swao: endpoint {
3288 remot 2836 remote-endpoint = <&funnel_swao_in_funnel_merg>;
3289 }; 2837 };
3290 }; 2838 };
3291 }; 2839 };
3292 2840
3293 in-ports { 2841 in-ports {
3294 #address-cell 2842 #address-cells = <1>;
3295 #size-cells = 2843 #size-cells = <0>;
3296 2844
3297 port@0 { 2845 port@0 {
3298 reg = 2846 reg = <0>;
3299 funne 2847 funnel_merg_in_funnel_in0: endpoint {
3300 remot 2848 remote-endpoint = <&funnel_in0_out_funnel_merg>;
3301 }; 2849 };
3302 }; 2850 };
3303 2851
3304 port@1 { 2852 port@1 {
3305 reg = 2853 reg = <1>;
3306 funne 2854 funnel_merg_in_funnel_in1: endpoint {
3307 remot 2855 remote-endpoint = <&funnel_in1_out_funnel_merg>;
3308 }; 2856 };
3309 }; 2857 };
3310 }; 2858 };
3311 }; 2859 };
3312 2860
3313 replicator@6046000 { 2861 replicator@6046000 {
3314 compatible = "arm,cor 2862 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3315 reg = <0 0x06046000 0 2863 reg = <0 0x06046000 0 0x1000>;
3316 2864
3317 clocks = <&aoss_qmp>; 2865 clocks = <&aoss_qmp>;
3318 clock-names = "apb_pc 2866 clock-names = "apb_pclk";
3319 2867
3320 out-ports { 2868 out-ports {
3321 port { 2869 port {
3322 repli 2870 replicator_out: endpoint {
3323 2871 remote-endpoint = <&etr_in>;
3324 }; 2872 };
3325 }; 2873 };
3326 }; 2874 };
3327 2875
3328 in-ports { 2876 in-ports {
3329 port { 2877 port {
3330 repli 2878 replicator_cx_in_swao_out: endpoint {
3331 2879 remote-endpoint = <&replicator_swao_out_cx_in>;
3332 }; 2880 };
3333 }; 2881 };
3334 }; 2882 };
3335 }; 2883 };
3336 2884
3337 etr@6048000 { 2885 etr@6048000 {
3338 compatible = "arm,cor 2886 compatible = "arm,coresight-tmc", "arm,primecell";
3339 reg = <0 0x06048000 0 2887 reg = <0 0x06048000 0 0x1000>;
3340 2888
3341 clocks = <&aoss_qmp>; 2889 clocks = <&aoss_qmp>;
3342 clock-names = "apb_pc 2890 clock-names = "apb_pclk";
3343 arm,scatter-gather; 2891 arm,scatter-gather;
3344 2892
3345 in-ports { 2893 in-ports {
3346 port { 2894 port {
3347 etr_i 2895 etr_in: endpoint {
3348 2896 remote-endpoint = <&replicator_out>;
3349 }; 2897 };
3350 }; 2898 };
3351 }; 2899 };
3352 }; 2900 };
3353 2901
3354 tpdm@684c000 { <<
3355 compatible = "qcom,co <<
3356 reg = <0 0x0684c000 0 <<
3357 <<
3358 clocks = <&aoss_qmp>; <<
3359 clock-names = "apb_pc <<
3360 <<
3361 out-ports { <<
3362 port { <<
3363 tpdm_ <<
3364 <<
3365 }; <<
3366 }; <<
3367 }; <<
3368 }; <<
3369 <<
3370 funnel@6b04000 { 2902 funnel@6b04000 {
3371 compatible = "arm,cor 2903 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3372 arm,primecell-periphi 2904 arm,primecell-periphid = <0x000bb908>;
3373 2905
3374 reg = <0 0x06b04000 0 2906 reg = <0 0x06b04000 0 0x1000>;
>> 2907 reg-names = "funnel-base";
3375 2908
3376 clocks = <&aoss_qmp>; 2909 clocks = <&aoss_qmp>;
3377 clock-names = "apb_pc 2910 clock-names = "apb_pclk";
3378 2911
3379 out-ports { 2912 out-ports {
3380 port { 2913 port {
3381 funne 2914 funnel_swao_out_etf: endpoint {
3382 2915 remote-endpoint = <&etf_in_funnel_swao_out>;
3383 }; 2916 };
3384 }; 2917 };
3385 }; 2918 };
3386 2919
3387 in-ports { 2920 in-ports {
3388 #address-cell 2921 #address-cells = <1>;
3389 #size-cells = 2922 #size-cells = <0>;
3390 2923
3391 port@7 { 2924 port@7 {
3392 reg = 2925 reg = <7>;
3393 funne 2926 funnel_swao_in_funnel_merg: endpoint {
3394 !! 2927 remote-endpoint= <&funnel_merg_out_funnel_swao>;
3395 }; 2928 };
3396 }; 2929 };
3397 }; 2930 };
>> 2931
3398 }; 2932 };
3399 2933
3400 etf@6b05000 { 2934 etf@6b05000 {
3401 compatible = "arm,cor 2935 compatible = "arm,coresight-tmc", "arm,primecell";
3402 reg = <0 0x06b05000 0 2936 reg = <0 0x06b05000 0 0x1000>;
3403 2937
3404 clocks = <&aoss_qmp>; 2938 clocks = <&aoss_qmp>;
3405 clock-names = "apb_pc 2939 clock-names = "apb_pclk";
3406 2940
3407 out-ports { 2941 out-ports {
3408 port { 2942 port {
3409 etf_o 2943 etf_out: endpoint {
3410 2944 remote-endpoint = <&replicator_in>;
3411 }; 2945 };
3412 }; 2946 };
3413 }; 2947 };
3414 2948
3415 in-ports { 2949 in-ports {
>> 2950 #address-cells = <1>;
>> 2951 #size-cells = <0>;
3416 2952
3417 port { !! 2953 port@0 {
>> 2954 reg = <0>;
3418 etf_i 2955 etf_in_funnel_swao_out: endpoint {
3419 2956 remote-endpoint = <&funnel_swao_out_etf>;
3420 }; 2957 };
3421 }; 2958 };
3422 }; 2959 };
3423 }; 2960 };
3424 2961
3425 replicator@6b06000 { 2962 replicator@6b06000 {
3426 compatible = "arm,cor 2963 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3427 reg = <0 0x06b06000 0 2964 reg = <0 0x06b06000 0 0x1000>;
3428 2965
3429 clocks = <&aoss_qmp>; 2966 clocks = <&aoss_qmp>;
3430 clock-names = "apb_pc 2967 clock-names = "apb_pclk";
3431 2968
3432 out-ports { 2969 out-ports {
3433 port { 2970 port {
3434 repli 2971 replicator_swao_out_cx_in: endpoint {
3435 2972 remote-endpoint = <&replicator_cx_in_swao_out>;
3436 }; 2973 };
3437 }; 2974 };
3438 }; 2975 };
3439 2976
3440 in-ports { 2977 in-ports {
3441 port { 2978 port {
3442 repli 2979 replicator_in: endpoint {
3443 2980 remote-endpoint = <&etf_out>;
3444 }; 2981 };
3445 }; 2982 };
3446 }; 2983 };
3447 }; 2984 };
3448 2985
3449 tpdm@6c08000 { <<
3450 compatible = "qcom,co <<
3451 reg = <0 0x06c08000 0 <<
3452 <<
3453 clocks = <&aoss_qmp>; <<
3454 clock-names = "apb_pc <<
3455 <<
3456 out-ports { <<
3457 port { <<
3458 tpdm_ <<
3459 <<
3460 }; <<
3461 }; <<
3462 }; <<
3463 }; <<
3464 <<
3465 funnel@6c0b000 { <<
3466 compatible = "arm,cor <<
3467 reg = <0 0x06c0b000 0 <<
3468 <<
3469 clocks = <&aoss_qmp>; <<
3470 clock-names = "apb_pc <<
3471 <<
3472 out-ports { <<
3473 port { <<
3474 funne <<
3475 remot <<
3476 }; <<
3477 }; <<
3478 }; <<
3479 <<
3480 in-ports { <<
3481 #address-cell <<
3482 #size-cells = <<
3483 <<
3484 port@3 { <<
3485 reg = <<
3486 funne <<
3487 <<
3488 }; <<
3489 }; <<
3490 }; <<
3491 }; <<
3492 <<
3493 funnel@6c2d000 { <<
3494 compatible = "arm,cor <<
3495 reg = <0 0x06c2d000 0 <<
3496 <<
3497 clocks = <&aoss_qmp>; <<
3498 clock-names = "apb_pc <<
3499 <<
3500 out-ports { <<
3501 port { <<
3502 tpdm_ <<
3503 <<
3504 }; <<
3505 }; <<
3506 }; <<
3507 <<
3508 in-ports { <<
3509 #address-cell <<
3510 #size-cells = <<
3511 <<
3512 port@2 { <<
3513 reg = <<
3514 funne <<
3515 remot <<
3516 }; <<
3517 }; <<
3518 }; <<
3519 }; <<
3520 <<
3521 etm@7040000 { 2986 etm@7040000 {
3522 compatible = "arm,cor 2987 compatible = "arm,coresight-etm4x", "arm,primecell";
3523 reg = <0 0x07040000 0 2988 reg = <0 0x07040000 0 0x1000>;
3524 2989
3525 cpu = <&CPU0>; 2990 cpu = <&CPU0>;
3526 2991
3527 clocks = <&aoss_qmp>; 2992 clocks = <&aoss_qmp>;
3528 clock-names = "apb_pc 2993 clock-names = "apb_pclk";
3529 arm,coresight-loses-c 2994 arm,coresight-loses-context-with-cpu;
3530 2995
3531 out-ports { 2996 out-ports {
3532 port { 2997 port {
3533 etm0_ 2998 etm0_out: endpoint {
3534 2999 remote-endpoint = <&apss_funnel_in0>;
3535 }; 3000 };
3536 }; 3001 };
3537 }; 3002 };
3538 }; 3003 };
3539 3004
3540 etm@7140000 { 3005 etm@7140000 {
3541 compatible = "arm,cor 3006 compatible = "arm,coresight-etm4x", "arm,primecell";
3542 reg = <0 0x07140000 0 3007 reg = <0 0x07140000 0 0x1000>;
3543 3008
3544 cpu = <&CPU1>; 3009 cpu = <&CPU1>;
3545 3010
3546 clocks = <&aoss_qmp>; 3011 clocks = <&aoss_qmp>;
3547 clock-names = "apb_pc 3012 clock-names = "apb_pclk";
3548 arm,coresight-loses-c 3013 arm,coresight-loses-context-with-cpu;
3549 3014
3550 out-ports { 3015 out-ports {
3551 port { 3016 port {
3552 etm1_ 3017 etm1_out: endpoint {
3553 3018 remote-endpoint = <&apss_funnel_in1>;
3554 }; 3019 };
3555 }; 3020 };
3556 }; 3021 };
3557 }; 3022 };
3558 3023
3559 etm@7240000 { 3024 etm@7240000 {
3560 compatible = "arm,cor 3025 compatible = "arm,coresight-etm4x", "arm,primecell";
3561 reg = <0 0x07240000 0 3026 reg = <0 0x07240000 0 0x1000>;
3562 3027
3563 cpu = <&CPU2>; 3028 cpu = <&CPU2>;
3564 3029
3565 clocks = <&aoss_qmp>; 3030 clocks = <&aoss_qmp>;
3566 clock-names = "apb_pc 3031 clock-names = "apb_pclk";
3567 arm,coresight-loses-c 3032 arm,coresight-loses-context-with-cpu;
3568 3033
3569 out-ports { 3034 out-ports {
3570 port { 3035 port {
3571 etm2_ 3036 etm2_out: endpoint {
3572 3037 remote-endpoint = <&apss_funnel_in2>;
3573 }; 3038 };
3574 }; 3039 };
3575 }; 3040 };
3576 }; 3041 };
3577 3042
3578 etm@7340000 { 3043 etm@7340000 {
3579 compatible = "arm,cor 3044 compatible = "arm,coresight-etm4x", "arm,primecell";
3580 reg = <0 0x07340000 0 3045 reg = <0 0x07340000 0 0x1000>;
3581 3046
3582 cpu = <&CPU3>; 3047 cpu = <&CPU3>;
3583 3048
3584 clocks = <&aoss_qmp>; 3049 clocks = <&aoss_qmp>;
3585 clock-names = "apb_pc 3050 clock-names = "apb_pclk";
3586 arm,coresight-loses-c 3051 arm,coresight-loses-context-with-cpu;
3587 3052
3588 out-ports { 3053 out-ports {
3589 port { 3054 port {
3590 etm3_ 3055 etm3_out: endpoint {
3591 3056 remote-endpoint = <&apss_funnel_in3>;
3592 }; 3057 };
3593 }; 3058 };
3594 }; 3059 };
3595 }; 3060 };
3596 3061
3597 etm@7440000 { 3062 etm@7440000 {
3598 compatible = "arm,cor 3063 compatible = "arm,coresight-etm4x", "arm,primecell";
3599 reg = <0 0x07440000 0 3064 reg = <0 0x07440000 0 0x1000>;
3600 3065
3601 cpu = <&CPU4>; 3066 cpu = <&CPU4>;
3602 3067
3603 clocks = <&aoss_qmp>; 3068 clocks = <&aoss_qmp>;
3604 clock-names = "apb_pc 3069 clock-names = "apb_pclk";
3605 arm,coresight-loses-c 3070 arm,coresight-loses-context-with-cpu;
3606 3071
3607 out-ports { 3072 out-ports {
3608 port { 3073 port {
3609 etm4_ 3074 etm4_out: endpoint {
3610 3075 remote-endpoint = <&apss_funnel_in4>;
3611 }; 3076 };
3612 }; 3077 };
3613 }; 3078 };
3614 }; 3079 };
3615 3080
3616 etm@7540000 { 3081 etm@7540000 {
3617 compatible = "arm,cor 3082 compatible = "arm,coresight-etm4x", "arm,primecell";
3618 reg = <0 0x07540000 0 3083 reg = <0 0x07540000 0 0x1000>;
3619 3084
3620 cpu = <&CPU5>; 3085 cpu = <&CPU5>;
3621 3086
3622 clocks = <&aoss_qmp>; 3087 clocks = <&aoss_qmp>;
3623 clock-names = "apb_pc 3088 clock-names = "apb_pclk";
3624 arm,coresight-loses-c 3089 arm,coresight-loses-context-with-cpu;
3625 3090
3626 out-ports { 3091 out-ports {
3627 port { 3092 port {
3628 etm5_ 3093 etm5_out: endpoint {
3629 3094 remote-endpoint = <&apss_funnel_in5>;
3630 }; 3095 };
3631 }; 3096 };
3632 }; 3097 };
3633 }; 3098 };
3634 3099
3635 etm@7640000 { 3100 etm@7640000 {
3636 compatible = "arm,cor 3101 compatible = "arm,coresight-etm4x", "arm,primecell";
3637 reg = <0 0x07640000 0 3102 reg = <0 0x07640000 0 0x1000>;
3638 3103
3639 cpu = <&CPU6>; 3104 cpu = <&CPU6>;
3640 3105
3641 clocks = <&aoss_qmp>; 3106 clocks = <&aoss_qmp>;
3642 clock-names = "apb_pc 3107 clock-names = "apb_pclk";
3643 arm,coresight-loses-c 3108 arm,coresight-loses-context-with-cpu;
3644 3109
3645 out-ports { 3110 out-ports {
3646 port { 3111 port {
3647 etm6_ 3112 etm6_out: endpoint {
3648 3113 remote-endpoint = <&apss_funnel_in6>;
3649 }; 3114 };
3650 }; 3115 };
3651 }; 3116 };
3652 }; 3117 };
3653 3118
3654 etm@7740000 { 3119 etm@7740000 {
3655 compatible = "arm,cor 3120 compatible = "arm,coresight-etm4x", "arm,primecell";
3656 reg = <0 0x07740000 0 3121 reg = <0 0x07740000 0 0x1000>;
3657 3122
3658 cpu = <&CPU7>; 3123 cpu = <&CPU7>;
3659 3124
3660 clocks = <&aoss_qmp>; 3125 clocks = <&aoss_qmp>;
3661 clock-names = "apb_pc 3126 clock-names = "apb_pclk";
3662 arm,coresight-loses-c 3127 arm,coresight-loses-context-with-cpu;
3663 3128
3664 out-ports { 3129 out-ports {
3665 port { 3130 port {
3666 etm7_ 3131 etm7_out: endpoint {
3667 3132 remote-endpoint = <&apss_funnel_in7>;
3668 }; 3133 };
3669 }; 3134 };
3670 }; 3135 };
3671 }; 3136 };
3672 3137
3673 funnel@7800000 { 3138 funnel@7800000 {
3674 compatible = "arm,cor 3139 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3675 reg = <0 0x07800000 0 3140 reg = <0 0x07800000 0 0x1000>;
3676 3141
3677 clocks = <&aoss_qmp>; 3142 clocks = <&aoss_qmp>;
3678 clock-names = "apb_pc 3143 clock-names = "apb_pclk";
3679 3144
3680 out-ports { 3145 out-ports {
3681 port { 3146 port {
3682 funne 3147 funnel_apss_out_funnel_apss_merg: endpoint {
3683 remot 3148 remote-endpoint = <&funnel_apss_merg_in_funnel_apss>;
3684 }; 3149 };
3685 }; 3150 };
3686 }; 3151 };
3687 3152
3688 in-ports { 3153 in-ports {
3689 #address-cell 3154 #address-cells = <1>;
3690 #size-cells = 3155 #size-cells = <0>;
3691 3156
3692 port@0 { 3157 port@0 {
3693 reg = 3158 reg = <0>;
3694 apss_ 3159 apss_funnel_in0: endpoint {
3695 3160 remote-endpoint = <&etm0_out>;
3696 }; 3161 };
3697 }; 3162 };
3698 3163
3699 port@1 { 3164 port@1 {
3700 reg = 3165 reg = <1>;
3701 apss_ 3166 apss_funnel_in1: endpoint {
3702 3167 remote-endpoint = <&etm1_out>;
3703 }; 3168 };
3704 }; 3169 };
3705 3170
3706 port@2 { 3171 port@2 {
3707 reg = 3172 reg = <2>;
3708 apss_ 3173 apss_funnel_in2: endpoint {
3709 3174 remote-endpoint = <&etm2_out>;
3710 }; 3175 };
3711 }; 3176 };
3712 3177
3713 port@3 { 3178 port@3 {
3714 reg = 3179 reg = <3>;
3715 apss_ 3180 apss_funnel_in3: endpoint {
3716 3181 remote-endpoint = <&etm3_out>;
3717 }; 3182 };
3718 }; 3183 };
3719 3184
3720 port@4 { 3185 port@4 {
3721 reg = 3186 reg = <4>;
3722 apss_ 3187 apss_funnel_in4: endpoint {
3723 3188 remote-endpoint = <&etm4_out>;
3724 }; 3189 };
3725 }; 3190 };
3726 3191
3727 port@5 { 3192 port@5 {
3728 reg = 3193 reg = <5>;
3729 apss_ 3194 apss_funnel_in5: endpoint {
3730 3195 remote-endpoint = <&etm5_out>;
3731 }; 3196 };
3732 }; 3197 };
3733 3198
3734 port@6 { 3199 port@6 {
3735 reg = 3200 reg = <6>;
3736 apss_ 3201 apss_funnel_in6: endpoint {
3737 3202 remote-endpoint = <&etm6_out>;
3738 }; 3203 };
3739 }; 3204 };
3740 3205
3741 port@7 { 3206 port@7 {
3742 reg = 3207 reg = <7>;
3743 apss_ 3208 apss_funnel_in7: endpoint {
3744 3209 remote-endpoint = <&etm7_out>;
3745 }; 3210 };
3746 }; 3211 };
3747 }; 3212 };
3748 }; 3213 };
3749 3214
3750 funnel@7810000 { 3215 funnel@7810000 {
3751 compatible = "arm,cor 3216 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3752 reg = <0 0x07810000 0 3217 reg = <0 0x07810000 0 0x1000>;
3753 3218
3754 clocks = <&aoss_qmp>; 3219 clocks = <&aoss_qmp>;
3755 clock-names = "apb_pc 3220 clock-names = "apb_pclk";
3756 3221
3757 out-ports { 3222 out-ports {
>> 3223 #address-cells = <1>;
>> 3224 #size-cells = <0>;
>> 3225
3758 port { 3226 port {
3759 funne 3227 funnel_apss_merg_out_funnel_in1: endpoint {
3760 remot 3228 remote-endpoint = <&funnel_in1_in_funnel_apss_merg>;
3761 }; 3229 };
3762 }; 3230 };
3763 }; 3231 };
3764 3232
3765 in-ports { 3233 in-ports {
3766 port { !! 3234 #address-cells = <1>;
>> 3235 #size-cells = <0>;
>> 3236
>> 3237 port@0 {
>> 3238 reg = <0>;
3767 funne 3239 funnel_apss_merg_in_funnel_apss: endpoint {
3768 remot 3240 remote-endpoint = <&funnel_apss_out_funnel_apss_merg>;
3769 }; 3241 };
3770 }; 3242 };
3771 }; 3243 };
3772 }; 3244 };
3773 3245
3774 cdsp: remoteproc@8300000 { 3246 cdsp: remoteproc@8300000 {
3775 compatible = "qcom,sm 3247 compatible = "qcom,sm8250-cdsp-pas";
3776 reg = <0 0x08300000 0 3248 reg = <0 0x08300000 0 0x10000>;
3777 3249
3778 interrupts-extended = !! 3250 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
3779 3251 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
3780 3252 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
3781 3253 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
3782 3254 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
3783 interrupt-names = "wd 3255 interrupt-names = "wdog", "fatal", "ready",
3784 "ha 3256 "handover", "stop-ack";
3785 3257
3786 clocks = <&rpmhcc RPM 3258 clocks = <&rpmhcc RPMH_CXO_CLK>;
3787 clock-names = "xo"; 3259 clock-names = "xo";
3788 3260
3789 power-domains = <&rpm !! 3261 power-domains = <&rpmhpd SM8250_CX>;
3790 3262
3791 memory-region = <&cds 3263 memory-region = <&cdsp_mem>;
3792 3264
3793 qcom,qmp = <&aoss_qmp 3265 qcom,qmp = <&aoss_qmp>;
3794 3266
3795 qcom,smem-states = <& 3267 qcom,smem-states = <&smp2p_cdsp_out 0>;
3796 qcom,smem-state-names 3268 qcom,smem-state-names = "stop";
3797 3269
3798 status = "disabled"; 3270 status = "disabled";
3799 3271
3800 glink-edge { 3272 glink-edge {
3801 interrupts-ex 3273 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
3802 3274 IPCC_MPROC_SIGNAL_GLINK_QMP
3803 3275 IRQ_TYPE_EDGE_RISING>;
3804 mboxes = <&ip 3276 mboxes = <&ipcc IPCC_CLIENT_CDSP
3805 3277 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3806 3278
3807 label = "cdsp 3279 label = "cdsp";
3808 qcom,remote-p 3280 qcom,remote-pid = <5>;
3809 3281
3810 fastrpc { 3282 fastrpc {
3811 compa 3283 compatible = "qcom,fastrpc";
3812 qcom, 3284 qcom,glink-channels = "fastrpcglink-apps-dsp";
3813 label 3285 label = "cdsp";
3814 qcom, 3286 qcom,non-secure-domain;
3815 #addr 3287 #address-cells = <1>;
3816 #size 3288 #size-cells = <0>;
3817 3289
3818 compu 3290 compute-cb@1 {
3819 3291 compatible = "qcom,fastrpc-compute-cb";
3820 3292 reg = <1>;
3821 3293 iommus = <&apps_smmu 0x1001 0x0460>;
3822 }; 3294 };
3823 3295
3824 compu 3296 compute-cb@2 {
3825 3297 compatible = "qcom,fastrpc-compute-cb";
3826 3298 reg = <2>;
3827 3299 iommus = <&apps_smmu 0x1002 0x0460>;
3828 }; 3300 };
3829 3301
3830 compu 3302 compute-cb@3 {
3831 3303 compatible = "qcom,fastrpc-compute-cb";
3832 3304 reg = <3>;
3833 3305 iommus = <&apps_smmu 0x1003 0x0460>;
3834 }; 3306 };
3835 3307
3836 compu 3308 compute-cb@4 {
3837 3309 compatible = "qcom,fastrpc-compute-cb";
3838 3310 reg = <4>;
3839 3311 iommus = <&apps_smmu 0x1004 0x0460>;
3840 }; 3312 };
3841 3313
3842 compu 3314 compute-cb@5 {
3843 3315 compatible = "qcom,fastrpc-compute-cb";
3844 3316 reg = <5>;
3845 3317 iommus = <&apps_smmu 0x1005 0x0460>;
3846 }; 3318 };
3847 3319
3848 compu 3320 compute-cb@6 {
3849 3321 compatible = "qcom,fastrpc-compute-cb";
3850 3322 reg = <6>;
3851 3323 iommus = <&apps_smmu 0x1006 0x0460>;
3852 }; 3324 };
3853 3325
3854 compu 3326 compute-cb@7 {
3855 3327 compatible = "qcom,fastrpc-compute-cb";
3856 3328 reg = <7>;
3857 3329 iommus = <&apps_smmu 0x1007 0x0460>;
3858 }; 3330 };
3859 3331
3860 compu 3332 compute-cb@8 {
3861 3333 compatible = "qcom,fastrpc-compute-cb";
3862 3334 reg = <8>;
3863 3335 iommus = <&apps_smmu 0x1008 0x0460>;
3864 }; 3336 };
3865 3337
3866 /* no 3338 /* note: secure cb9 in downstream */
3867 }; 3339 };
3868 }; 3340 };
3869 }; 3341 };
3870 3342
3871 usb_1_hsphy: phy@88e3000 { 3343 usb_1_hsphy: phy@88e3000 {
3872 compatible = "qcom,sm 3344 compatible = "qcom,sm8250-usb-hs-phy",
3873 "qcom,us 3345 "qcom,usb-snps-hs-7nm-phy";
3874 reg = <0 0x088e3000 0 3346 reg = <0 0x088e3000 0 0x400>;
3875 status = "disabled"; 3347 status = "disabled";
3876 #phy-cells = <0>; 3348 #phy-cells = <0>;
3877 3349
3878 clocks = <&rpmhcc RPM 3350 clocks = <&rpmhcc RPMH_CXO_CLK>;
3879 clock-names = "ref"; 3351 clock-names = "ref";
3880 3352
3881 resets = <&gcc GCC_QU 3353 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3882 }; 3354 };
3883 3355
3884 usb_2_hsphy: phy@88e4000 { 3356 usb_2_hsphy: phy@88e4000 {
3885 compatible = "qcom,sm 3357 compatible = "qcom,sm8250-usb-hs-phy",
3886 "qcom,us 3358 "qcom,usb-snps-hs-7nm-phy";
3887 reg = <0 0x088e4000 0 3359 reg = <0 0x088e4000 0 0x400>;
3888 status = "disabled"; 3360 status = "disabled";
3889 #phy-cells = <0>; 3361 #phy-cells = <0>;
3890 3362
3891 clocks = <&rpmhcc RPM 3363 clocks = <&rpmhcc RPMH_CXO_CLK>;
3892 clock-names = "ref"; 3364 clock-names = "ref";
3893 3365
3894 resets = <&gcc GCC_QU 3366 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3895 }; 3367 };
3896 3368
3897 usb_1_qmpphy: phy@88e8000 { !! 3369 usb_1_qmpphy: phy@88e9000 {
3898 compatible = "qcom,sm 3370 compatible = "qcom,sm8250-qmp-usb3-dp-phy";
3899 reg = <0 0x088e8000 0 !! 3371 reg = <0 0x088e9000 0 0x200>,
>> 3372 <0 0x088e8000 0 0x40>,
>> 3373 <0 0x088ea000 0 0x200>;
3900 status = "disabled"; 3374 status = "disabled";
>> 3375 #address-cells = <2>;
>> 3376 #size-cells = <2>;
>> 3377 ranges;
3901 3378
3902 clocks = <&gcc GCC_US 3379 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
3903 <&rpmhcc RPM 3380 <&rpmhcc RPMH_CXO_CLK>,
3904 <&gcc GCC_US !! 3381 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
3905 <&gcc GCC_US !! 3382 clock-names = "aux", "ref_clk_src", "com_aux";
3906 clock-names = "aux", <<
3907 "ref", <<
3908 "com_au <<
3909 "usb3_p <<
3910 3383
3911 resets = <&gcc GCC_US 3384 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
3912 <&gcc GCC_US 3385 <&gcc GCC_USB3_PHY_PRIM_BCR>;
3913 reset-names = "phy", 3386 reset-names = "phy", "common";
3914 3387
3915 #clock-cells = <1>; !! 3388 usb_1_ssphy: usb3-phy@88e9200 {
3916 #phy-cells = <1>; !! 3389 reg = <0 0x088e9200 0 0x200>,
3917 !! 3390 <0 0x088e9400 0 0x200>,
3918 orientation-switch; !! 3391 <0 0x088e9c00 0 0x400>,
3919 !! 3392 <0 0x088e9600 0 0x200>,
3920 ports { !! 3393 <0 0x088e9800 0 0x200>,
3921 #address-cell !! 3394 <0 0x088e9a00 0 0x100>;
3922 #size-cells = !! 3395 #clock-cells = <0>;
3923 !! 3396 #phy-cells = <0>;
3924 port@0 { !! 3397 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3925 reg = !! 3398 clock-names = "pipe0";
3926 usb_1 !! 3399 clock-output-names = "usb3_phy_pipe_clk_src";
3927 }; !! 3400 };
3928 <<
3929 port@1 { <<
3930 reg = <<
3931 <<
3932 usb_1 <<
3933 <<
3934 }; <<
3935 }; <<
3936 <<
3937 port@2 { <<
3938 reg = <<
3939 3401
3940 usb_1 !! 3402 dp_phy: dp-phy@88ea200 {
3941 }; !! 3403 reg = <0 0x088ea200 0 0x200>,
>> 3404 <0 0x088ea400 0 0x200>,
>> 3405 <0 0x088eaa00 0 0x200>,
>> 3406 <0 0x088ea600 0 0x200>,
>> 3407 <0 0x088ea800 0 0x200>;
>> 3408 #phy-cells = <0>;
>> 3409 #clock-cells = <1>;
3942 }; 3410 };
3943 }; 3411 };
3944 3412
3945 usb_2_qmpphy: phy@88eb000 { 3413 usb_2_qmpphy: phy@88eb000 {
3946 compatible = "qcom,sm 3414 compatible = "qcom,sm8250-qmp-usb3-uni-phy";
3947 reg = <0 0x088eb000 0 !! 3415 reg = <0 0x088eb000 0 0x200>;
>> 3416 status = "disabled";
>> 3417 #address-cells = <2>;
>> 3418 #size-cells = <2>;
>> 3419 ranges;
3948 3420
3949 clocks = <&gcc GCC_US 3421 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
>> 3422 <&rpmhcc RPMH_CXO_CLK>,
3950 <&gcc GCC_US 3423 <&gcc GCC_USB3_SEC_CLKREF_EN>,
3951 <&gcc GCC_US !! 3424 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
3952 <&gcc GCC_US !! 3425 clock-names = "aux", "ref_clk_src", "ref", "com_aux";
3953 clock-names = "aux", <<
3954 "ref", <<
3955 "com_au <<
3956 "pipe"; <<
3957 clock-output-names = <<
3958 #clock-cells = <0>; <<
3959 #phy-cells = <0>; <<
3960 3426
3961 resets = <&gcc GCC_US !! 3427 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
3962 <&gcc GCC_US !! 3428 <&gcc GCC_USB3_PHY_SEC_BCR>;
3963 reset-names = "phy", !! 3429 reset-names = "phy", "common";
3964 "phy_ph <<
3965 3430
3966 status = "disabled"; !! 3431 usb_2_ssphy: phy@88eb200 {
>> 3432 reg = <0 0x088eb200 0 0x200>,
>> 3433 <0 0x088eb400 0 0x200>,
>> 3434 <0 0x088eb800 0 0x800>;
>> 3435 #clock-cells = <0>;
>> 3436 #phy-cells = <0>;
>> 3437 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
>> 3438 clock-names = "pipe0";
>> 3439 clock-output-names = "usb3_uni_phy_pipe_clk_src";
>> 3440 };
3967 }; 3441 };
3968 3442
3969 sdhc_2: mmc@8804000 { 3443 sdhc_2: mmc@8804000 {
3970 compatible = "qcom,sm 3444 compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
3971 reg = <0 0x08804000 0 3445 reg = <0 0x08804000 0 0x1000>;
3972 3446
3973 interrupts = <GIC_SPI 3447 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
3974 <GIC_SPI 3448 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
3975 interrupt-names = "hc 3449 interrupt-names = "hc_irq", "pwr_irq";
3976 3450
3977 clocks = <&gcc GCC_SD 3451 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3978 <&gcc GCC_SD 3452 <&gcc GCC_SDCC2_APPS_CLK>,
3979 <&rpmhcc RPM 3453 <&rpmhcc RPMH_CXO_CLK>;
3980 clock-names = "iface" 3454 clock-names = "iface", "core", "xo";
3981 iommus = <&apps_smmu 3455 iommus = <&apps_smmu 0x4a0 0x0>;
3982 qcom,dll-config = <0x 3456 qcom,dll-config = <0x0007642c>;
3983 qcom,ddr-config = <0x 3457 qcom,ddr-config = <0x80040868>;
3984 power-domains = <&rpm !! 3458 power-domains = <&rpmhpd SM8250_CX>;
3985 operating-points-v2 = 3459 operating-points-v2 = <&sdhc2_opp_table>;
3986 3460
3987 status = "disabled"; 3461 status = "disabled";
3988 3462
3989 sdhc2_opp_table: opp- 3463 sdhc2_opp_table: opp-table {
3990 compatible = 3464 compatible = "operating-points-v2";
3991 3465
3992 opp-19200000 3466 opp-19200000 {
3993 opp-h 3467 opp-hz = /bits/ 64 <19200000>;
3994 requi 3468 required-opps = <&rpmhpd_opp_min_svs>;
3995 }; 3469 };
3996 3470
3997 opp-50000000 3471 opp-50000000 {
3998 opp-h 3472 opp-hz = /bits/ 64 <50000000>;
3999 requi 3473 required-opps = <&rpmhpd_opp_low_svs>;
4000 }; 3474 };
4001 3475
4002 opp-100000000 3476 opp-100000000 {
4003 opp-h 3477 opp-hz = /bits/ 64 <100000000>;
4004 requi 3478 required-opps = <&rpmhpd_opp_svs>;
4005 }; 3479 };
4006 3480
4007 opp-202000000 3481 opp-202000000 {
4008 opp-h 3482 opp-hz = /bits/ 64 <202000000>;
4009 requi 3483 required-opps = <&rpmhpd_opp_svs_l1>;
4010 }; 3484 };
4011 }; 3485 };
4012 }; 3486 };
4013 3487
4014 pmu@9091000 { <<
4015 compatible = "qcom,sm <<
4016 reg = <0 0x09091000 0 <<
4017 <<
4018 interrupts = <GIC_SPI <<
4019 <<
4020 interconnects = <&mc_ <<
4021 <<
4022 operating-points-v2 = <<
4023 <<
4024 llcc_bwmon_opp_table: <<
4025 compatible = <<
4026 <<
4027 opp-800000 { <<
4028 opp-p <<
4029 }; <<
4030 <<
4031 opp-1200000 { <<
4032 opp-p <<
4033 }; <<
4034 <<
4035 opp-1804000 { <<
4036 opp-p <<
4037 }; <<
4038 <<
4039 opp-2188000 { <<
4040 opp-p <<
4041 }; <<
4042 <<
4043 opp-2724000 { <<
4044 opp-p <<
4045 }; <<
4046 <<
4047 opp-3072000 { <<
4048 opp-p <<
4049 }; <<
4050 <<
4051 opp-4068000 { <<
4052 opp-p <<
4053 }; <<
4054 <<
4055 /* 1353 MHz, <<
4056 <<
4057 opp-6220000 { <<
4058 opp-p <<
4059 }; <<
4060 <<
4061 opp-7216000 { <<
4062 opp-p <<
4063 }; <<
4064 <<
4065 opp-8368000 { <<
4066 opp-p <<
4067 }; <<
4068 <<
4069 /* LPDDR5 */ <<
4070 opp-10944000 <<
4071 opp-p <<
4072 }; <<
4073 }; <<
4074 }; <<
4075 <<
4076 pmu@90b6400 { <<
4077 compatible = "qcom,sm <<
4078 reg = <0 0x090b6400 0 <<
4079 <<
4080 interrupts = <GIC_SPI <<
4081 <<
4082 interconnects = <&gem <<
4083 operating-points-v2 = <<
4084 <<
4085 cpu_bwmon_opp_table: <<
4086 compatible = <<
4087 <<
4088 opp-800000 { <<
4089 opp-p <<
4090 }; <<
4091 <<
4092 opp-1804000 { <<
4093 opp-p <<
4094 }; <<
4095 <<
4096 opp-2188000 { <<
4097 opp-p <<
4098 }; <<
4099 <<
4100 opp-2724000 { <<
4101 opp-p <<
4102 }; <<
4103 <<
4104 opp-3072000 { <<
4105 opp-p <<
4106 }; <<
4107 <<
4108 /* 1017MHz, 1 <<
4109 <<
4110 opp-6220000 { <<
4111 opp-p <<
4112 }; <<
4113 <<
4114 opp-6832000 { <<
4115 opp-p <<
4116 }; <<
4117 <<
4118 opp-8368000 { <<
4119 opp-p <<
4120 }; <<
4121 <<
4122 /* 2133MHz, L <<
4123 <<
4124 /* LPDDR5 */ <<
4125 opp-10944000 <<
4126 opp-p <<
4127 }; <<
4128 <<
4129 /* LPDDR5 */ <<
4130 opp-12784000 <<
4131 opp-p <<
4132 }; <<
4133 }; <<
4134 }; <<
4135 <<
4136 dc_noc: interconnect@90c0000 3488 dc_noc: interconnect@90c0000 {
4137 compatible = "qcom,sm 3489 compatible = "qcom,sm8250-dc-noc";
4138 reg = <0 0x090c0000 0 3490 reg = <0 0x090c0000 0 0x4200>;
4139 #interconnect-cells = !! 3491 #interconnect-cells = <1>;
4140 qcom,bcm-voters = <&a 3492 qcom,bcm-voters = <&apps_bcm_voter>;
4141 }; 3493 };
4142 3494
4143 gem_noc: interconnect@9100000 3495 gem_noc: interconnect@9100000 {
4144 compatible = "qcom,sm 3496 compatible = "qcom,sm8250-gem-noc";
4145 reg = <0 0x09100000 0 3497 reg = <0 0x09100000 0 0xb4000>;
4146 #interconnect-cells = !! 3498 #interconnect-cells = <1>;
4147 qcom,bcm-voters = <&a 3499 qcom,bcm-voters = <&apps_bcm_voter>;
4148 }; 3500 };
4149 3501
4150 npu_noc: interconnect@9990000 3502 npu_noc: interconnect@9990000 {
4151 compatible = "qcom,sm 3503 compatible = "qcom,sm8250-npu-noc";
4152 reg = <0 0x09990000 0 3504 reg = <0 0x09990000 0 0x1600>;
4153 #interconnect-cells = !! 3505 #interconnect-cells = <1>;
4154 qcom,bcm-voters = <&a 3506 qcom,bcm-voters = <&apps_bcm_voter>;
4155 }; 3507 };
4156 3508
4157 usb_1: usb@a6f8800 { 3509 usb_1: usb@a6f8800 {
4158 compatible = "qcom,sm 3510 compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
4159 reg = <0 0x0a6f8800 0 3511 reg = <0 0x0a6f8800 0 0x400>;
4160 status = "disabled"; 3512 status = "disabled";
4161 #address-cells = <2>; 3513 #address-cells = <2>;
4162 #size-cells = <2>; 3514 #size-cells = <2>;
4163 ranges; 3515 ranges;
4164 dma-ranges; 3516 dma-ranges;
4165 3517
4166 clocks = <&gcc GCC_CF 3518 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
4167 <&gcc GCC_US 3519 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
4168 <&gcc GCC_AG 3520 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
4169 <&gcc GCC_US 3521 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
4170 <&gcc GCC_US 3522 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4171 <&gcc GCC_US 3523 <&gcc GCC_USB3_SEC_CLKREF_EN>;
4172 clock-names = "cfg_no 3524 clock-names = "cfg_noc",
4173 "core", 3525 "core",
4174 "iface" 3526 "iface",
4175 "sleep" 3527 "sleep",
4176 "mock_u 3528 "mock_utmi",
4177 "xo"; 3529 "xo";
4178 3530
4179 assigned-clocks = <&g 3531 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4180 <&g 3532 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
4181 assigned-clock-rates 3533 assigned-clock-rates = <19200000>, <200000000>;
4182 3534
4183 interrupts-extended = !! 3535 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
4184 !! 3536 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
4185 <<
4186 3537 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
4187 !! 3538 <&pdc 14 IRQ_TYPE_EDGE_BOTH>;
4188 interrupt-names = "pw !! 3539 interrupt-names = "hs_phy_irq",
4189 "hs !! 3540 "ss_phy_irq",
4190 "dp <<
4191 "dm 3541 "dm_hs_phy_irq",
4192 "ss !! 3542 "dp_hs_phy_irq";
4193 3543
4194 power-domains = <&gcc 3544 power-domains = <&gcc USB30_PRIM_GDSC>;
4195 wakeup-source; <<
4196 3545
4197 resets = <&gcc GCC_US 3546 resets = <&gcc GCC_USB30_PRIM_BCR>;
4198 3547
4199 interconnects = <&agg <<
4200 <&gem <<
4201 interconnect-names = <<
4202 <<
4203 usb_1_dwc3: usb@a6000 3548 usb_1_dwc3: usb@a600000 {
4204 compatible = 3549 compatible = "snps,dwc3";
4205 reg = <0 0x0a 3550 reg = <0 0x0a600000 0 0xcd00>;
4206 interrupts = 3551 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
4207 iommus = <&ap 3552 iommus = <&apps_smmu 0x0 0x0>;
4208 snps,dis_u2_s 3553 snps,dis_u2_susphy_quirk;
4209 snps,dis_enbl 3554 snps,dis_enblslpm_quirk;
4210 phys = <&usb_ !! 3555 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
4211 phy-names = " 3556 phy-names = "usb2-phy", "usb3-phy";
4212 <<
4213 ports { <<
4214 #addr <<
4215 #size <<
4216 <<
4217 port@ <<
4218 <<
4219 <<
4220 <<
4221 <<
4222 }; <<
4223 <<
4224 port@ <<
4225 <<
4226 <<
4227 <<
4228 <<
4229 <<
4230 }; <<
4231 }; <<
4232 }; 3557 };
4233 }; 3558 };
4234 3559
4235 system-cache-controller@92000 3560 system-cache-controller@9200000 {
4236 compatible = "qcom,sm 3561 compatible = "qcom,sm8250-llcc";
4237 reg = <0 0x09200000 0 !! 3562 reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>;
4238 <0 0x09300000 0 !! 3563 reg-names = "llcc_base", "llcc_broadcast_base";
4239 <0 0x09600000 0 <<
4240 reg-names = "llcc0_ba <<
4241 "llcc3_ba <<
4242 }; 3564 };
4243 3565
4244 usb_2: usb@a8f8800 { 3566 usb_2: usb@a8f8800 {
4245 compatible = "qcom,sm 3567 compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
4246 reg = <0 0x0a8f8800 0 3568 reg = <0 0x0a8f8800 0 0x400>;
4247 status = "disabled"; 3569 status = "disabled";
4248 #address-cells = <2>; 3570 #address-cells = <2>;
4249 #size-cells = <2>; 3571 #size-cells = <2>;
4250 ranges; 3572 ranges;
4251 dma-ranges; 3573 dma-ranges;
4252 3574
4253 clocks = <&gcc GCC_CF 3575 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
4254 <&gcc GCC_US 3576 <&gcc GCC_USB30_SEC_MASTER_CLK>,
4255 <&gcc GCC_AG 3577 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
4256 <&gcc GCC_US 3578 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
4257 <&gcc GCC_US 3579 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4258 <&gcc GCC_US 3580 <&gcc GCC_USB3_SEC_CLKREF_EN>;
4259 clock-names = "cfg_no 3581 clock-names = "cfg_noc",
4260 "core", 3582 "core",
4261 "iface" 3583 "iface",
4262 "sleep" 3584 "sleep",
4263 "mock_u 3585 "mock_utmi",
4264 "xo"; 3586 "xo";
4265 3587
4266 assigned-clocks = <&g 3588 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4267 <&g 3589 <&gcc GCC_USB30_SEC_MASTER_CLK>;
4268 assigned-clock-rates 3590 assigned-clock-rates = <19200000>, <200000000>;
4269 3591
4270 interrupts-extended = !! 3592 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
4271 !! 3593 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>,
4272 <<
4273 3594 <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
4274 !! 3595 <&pdc 12 IRQ_TYPE_EDGE_BOTH>;
4275 interrupt-names = "pw !! 3596 interrupt-names = "hs_phy_irq",
4276 "hs !! 3597 "ss_phy_irq",
4277 "dp <<
4278 "dm 3598 "dm_hs_phy_irq",
4279 "ss !! 3599 "dp_hs_phy_irq";
4280 3600
4281 power-domains = <&gcc 3601 power-domains = <&gcc USB30_SEC_GDSC>;
4282 wakeup-source; <<
4283 3602
4284 resets = <&gcc GCC_US 3603 resets = <&gcc GCC_USB30_SEC_BCR>;
4285 3604
4286 interconnects = <&agg <<
4287 <&gem <<
4288 interconnect-names = <<
4289 <<
4290 usb_2_dwc3: usb@a8000 3605 usb_2_dwc3: usb@a800000 {
4291 compatible = 3606 compatible = "snps,dwc3";
4292 reg = <0 0x0a 3607 reg = <0 0x0a800000 0 0xcd00>;
4293 interrupts = 3608 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
4294 iommus = <&ap 3609 iommus = <&apps_smmu 0x20 0>;
4295 snps,dis_u2_s 3610 snps,dis_u2_susphy_quirk;
4296 snps,dis_enbl 3611 snps,dis_enblslpm_quirk;
4297 phys = <&usb_ !! 3612 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
4298 phy-names = " 3613 phy-names = "usb2-phy", "usb3-phy";
4299 }; 3614 };
4300 }; 3615 };
4301 3616
4302 venus: video-codec@aa00000 { 3617 venus: video-codec@aa00000 {
4303 compatible = "qcom,sm 3618 compatible = "qcom,sm8250-venus";
4304 reg = <0 0x0aa00000 0 3619 reg = <0 0x0aa00000 0 0x100000>;
4305 interrupts = <GIC_SPI 3620 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
4306 power-domains = <&vid 3621 power-domains = <&videocc MVS0C_GDSC>,
4307 <&vid 3622 <&videocc MVS0_GDSC>,
4308 <&rpm !! 3623 <&rpmhpd SM8250_MX>;
4309 power-domain-names = 3624 power-domain-names = "venus", "vcodec0", "mx";
4310 operating-points-v2 = 3625 operating-points-v2 = <&venus_opp_table>;
4311 3626
4312 clocks = <&gcc GCC_VI 3627 clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
4313 <&videocc VI 3628 <&videocc VIDEO_CC_MVS0C_CLK>,
4314 <&videocc VI 3629 <&videocc VIDEO_CC_MVS0_CLK>;
4315 clock-names = "iface" 3630 clock-names = "iface", "core", "vcodec0_core";
4316 3631
4317 interconnects = <&gem !! 3632 interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_VENUS_CFG>,
4318 <&mms !! 3633 <&mmss_noc MASTER_VIDEO_P0 &mc_virt SLAVE_EBI_CH0>;
4319 interconnect-names = 3634 interconnect-names = "cpu-cfg", "video-mem";
4320 3635
4321 iommus = <&apps_smmu 3636 iommus = <&apps_smmu 0x2100 0x0400>;
4322 memory-region = <&vid 3637 memory-region = <&video_mem>;
4323 3638
4324 resets = <&gcc GCC_VI 3639 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
4325 <&videocc VI 3640 <&videocc VIDEO_CC_MVS0C_CLK_ARES>;
4326 reset-names = "bus", 3641 reset-names = "bus", "core";
4327 3642
4328 status = "disabled"; 3643 status = "disabled";
4329 3644
4330 video-decoder { 3645 video-decoder {
4331 compatible = 3646 compatible = "venus-decoder";
4332 }; 3647 };
4333 3648
4334 video-encoder { 3649 video-encoder {
4335 compatible = 3650 compatible = "venus-encoder";
4336 }; 3651 };
4337 3652
4338 venus_opp_table: opp- 3653 venus_opp_table: opp-table {
4339 compatible = 3654 compatible = "operating-points-v2";
4340 3655
4341 opp-720000000 3656 opp-720000000 {
4342 opp-h 3657 opp-hz = /bits/ 64 <720000000>;
4343 requi 3658 required-opps = <&rpmhpd_opp_low_svs>;
4344 }; 3659 };
4345 3660
4346 opp-101400000 3661 opp-1014000000 {
4347 opp-h 3662 opp-hz = /bits/ 64 <1014000000>;
4348 requi 3663 required-opps = <&rpmhpd_opp_svs>;
4349 }; 3664 };
4350 3665
4351 opp-109800000 3666 opp-1098000000 {
4352 opp-h 3667 opp-hz = /bits/ 64 <1098000000>;
4353 requi 3668 required-opps = <&rpmhpd_opp_svs_l1>;
4354 }; 3669 };
4355 3670
4356 opp-133200000 3671 opp-1332000000 {
4357 opp-h 3672 opp-hz = /bits/ 64 <1332000000>;
4358 requi 3673 required-opps = <&rpmhpd_opp_nom>;
4359 }; 3674 };
4360 }; 3675 };
4361 }; 3676 };
4362 3677
4363 videocc: clock-controller@abf 3678 videocc: clock-controller@abf0000 {
4364 compatible = "qcom,sm 3679 compatible = "qcom,sm8250-videocc";
4365 reg = <0 0x0abf0000 0 3680 reg = <0 0x0abf0000 0 0x10000>;
4366 clocks = <&gcc GCC_VI 3681 clocks = <&gcc GCC_VIDEO_AHB_CLK>,
4367 <&rpmhcc RPM 3682 <&rpmhcc RPMH_CXO_CLK>,
4368 <&rpmhcc RPM 3683 <&rpmhcc RPMH_CXO_CLK_A>;
4369 power-domains = <&rpm !! 3684 power-domains = <&rpmhpd SM8250_MMCX>;
4370 required-opps = <&rpm 3685 required-opps = <&rpmhpd_opp_low_svs>;
4371 clock-names = "iface" 3686 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao";
4372 #clock-cells = <1>; 3687 #clock-cells = <1>;
4373 #reset-cells = <1>; 3688 #reset-cells = <1>;
4374 #power-domain-cells = 3689 #power-domain-cells = <1>;
4375 }; 3690 };
4376 3691
4377 cci0: cci@ac4f000 { 3692 cci0: cci@ac4f000 {
4378 compatible = "qcom,sm 3693 compatible = "qcom,sm8250-cci", "qcom,msm8996-cci";
4379 #address-cells = <1>; 3694 #address-cells = <1>;
4380 #size-cells = <0>; 3695 #size-cells = <0>;
4381 3696
4382 reg = <0 0x0ac4f000 0 3697 reg = <0 0x0ac4f000 0 0x1000>;
4383 interrupts = <GIC_SPI 3698 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
4384 power-domains = <&cam 3699 power-domains = <&camcc TITAN_TOP_GDSC>;
4385 3700
4386 clocks = <&camcc CAM_ 3701 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
4387 <&camcc CAM_ 3702 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4388 <&camcc CAM_ 3703 <&camcc CAM_CC_CPAS_AHB_CLK>,
4389 <&camcc CAM_ 3704 <&camcc CAM_CC_CCI_0_CLK>,
4390 <&camcc CAM_ 3705 <&camcc CAM_CC_CCI_0_CLK_SRC>;
4391 clock-names = "camnoc 3706 clock-names = "camnoc_axi",
4392 "slow_a 3707 "slow_ahb_src",
4393 "cpas_a 3708 "cpas_ahb",
4394 "cci", 3709 "cci",
4395 "cci_sr 3710 "cci_src";
4396 3711
4397 pinctrl-0 = <&cci0_de 3712 pinctrl-0 = <&cci0_default>;
4398 pinctrl-1 = <&cci0_sl 3713 pinctrl-1 = <&cci0_sleep>;
4399 pinctrl-names = "defa 3714 pinctrl-names = "default", "sleep";
4400 3715
4401 status = "disabled"; 3716 status = "disabled";
4402 3717
4403 cci0_i2c0: i2c-bus@0 3718 cci0_i2c0: i2c-bus@0 {
4404 reg = <0>; 3719 reg = <0>;
4405 clock-frequen 3720 clock-frequency = <1000000>;
4406 #address-cell 3721 #address-cells = <1>;
4407 #size-cells = 3722 #size-cells = <0>;
4408 }; 3723 };
4409 3724
4410 cci0_i2c1: i2c-bus@1 3725 cci0_i2c1: i2c-bus@1 {
4411 reg = <1>; 3726 reg = <1>;
4412 clock-frequen 3727 clock-frequency = <1000000>;
4413 #address-cell 3728 #address-cells = <1>;
4414 #size-cells = 3729 #size-cells = <0>;
4415 }; 3730 };
4416 }; 3731 };
4417 3732
4418 cci1: cci@ac50000 { 3733 cci1: cci@ac50000 {
4419 compatible = "qcom,sm 3734 compatible = "qcom,sm8250-cci", "qcom,msm8996-cci";
4420 #address-cells = <1>; 3735 #address-cells = <1>;
4421 #size-cells = <0>; 3736 #size-cells = <0>;
4422 3737
4423 reg = <0 0x0ac50000 0 3738 reg = <0 0x0ac50000 0 0x1000>;
4424 interrupts = <GIC_SPI 3739 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>;
4425 power-domains = <&cam 3740 power-domains = <&camcc TITAN_TOP_GDSC>;
4426 3741
4427 clocks = <&camcc CAM_ 3742 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
4428 <&camcc CAM_ 3743 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4429 <&camcc CAM_ 3744 <&camcc CAM_CC_CPAS_AHB_CLK>,
4430 <&camcc CAM_ 3745 <&camcc CAM_CC_CCI_1_CLK>,
4431 <&camcc CAM_ 3746 <&camcc CAM_CC_CCI_1_CLK_SRC>;
4432 clock-names = "camnoc 3747 clock-names = "camnoc_axi",
4433 "slow_a 3748 "slow_ahb_src",
4434 "cpas_a 3749 "cpas_ahb",
4435 "cci", 3750 "cci",
4436 "cci_sr 3751 "cci_src";
4437 3752
4438 pinctrl-0 = <&cci1_de 3753 pinctrl-0 = <&cci1_default>;
4439 pinctrl-1 = <&cci1_sl 3754 pinctrl-1 = <&cci1_sleep>;
4440 pinctrl-names = "defa 3755 pinctrl-names = "default", "sleep";
4441 3756
4442 status = "disabled"; 3757 status = "disabled";
4443 3758
4444 cci1_i2c0: i2c-bus@0 3759 cci1_i2c0: i2c-bus@0 {
4445 reg = <0>; 3760 reg = <0>;
4446 clock-frequen 3761 clock-frequency = <1000000>;
4447 #address-cell 3762 #address-cells = <1>;
4448 #size-cells = 3763 #size-cells = <0>;
4449 }; 3764 };
4450 3765
4451 cci1_i2c1: i2c-bus@1 3766 cci1_i2c1: i2c-bus@1 {
4452 reg = <1>; 3767 reg = <1>;
4453 clock-frequen 3768 clock-frequency = <1000000>;
4454 #address-cell 3769 #address-cells = <1>;
4455 #size-cells = 3770 #size-cells = <0>;
4456 }; 3771 };
4457 }; 3772 };
4458 3773
4459 camss: camss@ac6a000 { 3774 camss: camss@ac6a000 {
4460 compatible = "qcom,sm 3775 compatible = "qcom,sm8250-camss";
4461 status = "disabled"; 3776 status = "disabled";
4462 3777
4463 reg = <0 0x0ac6a000 0 3778 reg = <0 0x0ac6a000 0 0x2000>,
4464 <0 0x0ac6c000 0 3779 <0 0x0ac6c000 0 0x2000>,
4465 <0 0x0ac6e000 0 3780 <0 0x0ac6e000 0 0x1000>,
4466 <0 0x0ac70000 0 3781 <0 0x0ac70000 0 0x1000>,
4467 <0 0x0ac72000 0 3782 <0 0x0ac72000 0 0x1000>,
4468 <0 0x0ac74000 0 3783 <0 0x0ac74000 0 0x1000>,
4469 <0 0x0acb4000 0 3784 <0 0x0acb4000 0 0xd000>,
4470 <0 0x0acc3000 0 3785 <0 0x0acc3000 0 0xd000>,
4471 <0 0x0acd9000 0 3786 <0 0x0acd9000 0 0x2200>,
4472 <0 0x0acdb200 0 3787 <0 0x0acdb200 0 0x2200>;
4473 reg-names = "csiphy0" 3788 reg-names = "csiphy0",
4474 "csiphy1" 3789 "csiphy1",
4475 "csiphy2" 3790 "csiphy2",
4476 "csiphy3" 3791 "csiphy3",
4477 "csiphy4" 3792 "csiphy4",
4478 "csiphy5" 3793 "csiphy5",
4479 "vfe0", 3794 "vfe0",
4480 "vfe1", 3795 "vfe1",
4481 "vfe_lite 3796 "vfe_lite0",
4482 "vfe_lite 3797 "vfe_lite1";
4483 3798
4484 interrupts = <GIC_SPI 3799 interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
4485 <GIC_SPI 3800 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
4486 <GIC_SPI 3801 <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
4487 <GIC_SPI 3802 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
4488 <GIC_SPI 3803 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
4489 <GIC_SPI 3804 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
4490 <GIC_SPI 3805 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
4491 <GIC_SPI 3806 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
4492 <GIC_SPI 3807 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
4493 <GIC_SPI 3808 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
4494 <GIC_SPI 3809 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
4495 <GIC_SPI 3810 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
4496 <GIC_SPI 3811 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
4497 <GIC_SPI 3812 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
4498 interrupt-names = "cs 3813 interrupt-names = "csiphy0",
4499 "cs 3814 "csiphy1",
4500 "cs 3815 "csiphy2",
4501 "cs 3816 "csiphy3",
4502 "cs 3817 "csiphy4",
4503 "cs 3818 "csiphy5",
4504 "cs 3819 "csid0",
4505 "cs 3820 "csid1",
4506 "cs 3821 "csid2",
4507 "cs 3822 "csid3",
4508 "vf 3823 "vfe0",
4509 "vf 3824 "vfe1",
4510 "vf 3825 "vfe_lite0",
4511 "vf 3826 "vfe_lite1";
4512 3827
4513 power-domains = <&cam 3828 power-domains = <&camcc IFE_0_GDSC>,
4514 <&cam 3829 <&camcc IFE_1_GDSC>,
4515 <&cam 3830 <&camcc TITAN_TOP_GDSC>;
4516 3831
4517 clocks = <&gcc GCC_CA 3832 clocks = <&gcc GCC_CAMERA_AHB_CLK>,
4518 <&gcc GCC_CA 3833 <&gcc GCC_CAMERA_HF_AXI_CLK>,
4519 <&gcc GCC_CA 3834 <&gcc GCC_CAMERA_SF_AXI_CLK>,
4520 <&camcc CAM_ 3835 <&camcc CAM_CC_CAMNOC_AXI_CLK>,
4521 <&camcc CAM_ 3836 <&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>,
4522 <&camcc CAM_ 3837 <&camcc CAM_CC_CORE_AHB_CLK>,
4523 <&camcc CAM_ 3838 <&camcc CAM_CC_CPAS_AHB_CLK>,
4524 <&camcc CAM_ 3839 <&camcc CAM_CC_CSIPHY0_CLK>,
4525 <&camcc CAM_ 3840 <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
4526 <&camcc CAM_ 3841 <&camcc CAM_CC_CSIPHY1_CLK>,
4527 <&camcc CAM_ 3842 <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
4528 <&camcc CAM_ 3843 <&camcc CAM_CC_CSIPHY2_CLK>,
4529 <&camcc CAM_ 3844 <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
4530 <&camcc CAM_ 3845 <&camcc CAM_CC_CSIPHY3_CLK>,
4531 <&camcc CAM_ 3846 <&camcc CAM_CC_CSI3PHYTIMER_CLK>,
4532 <&camcc CAM_ 3847 <&camcc CAM_CC_CSIPHY4_CLK>,
4533 <&camcc CAM_ 3848 <&camcc CAM_CC_CSI4PHYTIMER_CLK>,
4534 <&camcc CAM_ 3849 <&camcc CAM_CC_CSIPHY5_CLK>,
4535 <&camcc CAM_ 3850 <&camcc CAM_CC_CSI5PHYTIMER_CLK>,
4536 <&camcc CAM_ 3851 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4537 <&camcc CAM_ 3852 <&camcc CAM_CC_IFE_0_AHB_CLK>,
4538 <&camcc CAM_ 3853 <&camcc CAM_CC_IFE_0_AXI_CLK>,
4539 <&camcc CAM_ 3854 <&camcc CAM_CC_IFE_0_CLK>,
4540 <&camcc CAM_ 3855 <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
4541 <&camcc CAM_ 3856 <&camcc CAM_CC_IFE_0_CSID_CLK>,
4542 <&camcc CAM_ 3857 <&camcc CAM_CC_IFE_0_AREG_CLK>,
4543 <&camcc CAM_ 3858 <&camcc CAM_CC_IFE_1_AHB_CLK>,
4544 <&camcc CAM_ 3859 <&camcc CAM_CC_IFE_1_AXI_CLK>,
4545 <&camcc CAM_ 3860 <&camcc CAM_CC_IFE_1_CLK>,
4546 <&camcc CAM_ 3861 <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
4547 <&camcc CAM_ 3862 <&camcc CAM_CC_IFE_1_CSID_CLK>,
4548 <&camcc CAM_ 3863 <&camcc CAM_CC_IFE_1_AREG_CLK>,
4549 <&camcc CAM_ 3864 <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
4550 <&camcc CAM_ 3865 <&camcc CAM_CC_IFE_LITE_AXI_CLK>,
4551 <&camcc CAM_ 3866 <&camcc CAM_CC_IFE_LITE_CLK>,
4552 <&camcc CAM_ 3867 <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
4553 <&camcc CAM_ 3868 <&camcc CAM_CC_IFE_LITE_CSID_CLK>;
4554 3869
4555 clock-names = "cam_ah 3870 clock-names = "cam_ahb_clk",
4556 "cam_hf 3871 "cam_hf_axi",
4557 "cam_sf 3872 "cam_sf_axi",
4558 "camnoc 3873 "camnoc_axi",
4559 "camnoc 3874 "camnoc_axi_src",
4560 "core_a 3875 "core_ahb",
4561 "cpas_a 3876 "cpas_ahb",
4562 "csiphy 3877 "csiphy0",
4563 "csiphy 3878 "csiphy0_timer",
4564 "csiphy 3879 "csiphy1",
4565 "csiphy 3880 "csiphy1_timer",
4566 "csiphy 3881 "csiphy2",
4567 "csiphy 3882 "csiphy2_timer",
4568 "csiphy 3883 "csiphy3",
4569 "csiphy 3884 "csiphy3_timer",
4570 "csiphy 3885 "csiphy4",
4571 "csiphy 3886 "csiphy4_timer",
4572 "csiphy 3887 "csiphy5",
4573 "csiphy 3888 "csiphy5_timer",
4574 "slow_a 3889 "slow_ahb_src",
4575 "vfe0_a 3890 "vfe0_ahb",
4576 "vfe0_a 3891 "vfe0_axi",
4577 "vfe0", 3892 "vfe0",
4578 "vfe0_c 3893 "vfe0_cphy_rx",
4579 "vfe0_c 3894 "vfe0_csid",
4580 "vfe0_a 3895 "vfe0_areg",
4581 "vfe1_a 3896 "vfe1_ahb",
4582 "vfe1_a 3897 "vfe1_axi",
4583 "vfe1", 3898 "vfe1",
4584 "vfe1_c 3899 "vfe1_cphy_rx",
4585 "vfe1_c 3900 "vfe1_csid",
4586 "vfe1_a 3901 "vfe1_areg",
4587 "vfe_li 3902 "vfe_lite_ahb",
4588 "vfe_li 3903 "vfe_lite_axi",
4589 "vfe_li 3904 "vfe_lite",
4590 "vfe_li 3905 "vfe_lite_cphy_rx",
4591 "vfe_li 3906 "vfe_lite_csid";
4592 3907
4593 iommus = <&apps_smmu 3908 iommus = <&apps_smmu 0x800 0x400>,
4594 <&apps_smmu 3909 <&apps_smmu 0x801 0x400>,
4595 <&apps_smmu 3910 <&apps_smmu 0x840 0x400>,
4596 <&apps_smmu 3911 <&apps_smmu 0x841 0x400>,
4597 <&apps_smmu 3912 <&apps_smmu 0xc00 0x400>,
4598 <&apps_smmu 3913 <&apps_smmu 0xc01 0x400>,
4599 <&apps_smmu 3914 <&apps_smmu 0xc40 0x400>,
4600 <&apps_smmu 3915 <&apps_smmu 0xc41 0x400>;
4601 3916
4602 interconnects = <&gem !! 3917 interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_CAMERA_CFG>,
4603 <&mms !! 3918 <&mmss_noc MASTER_CAMNOC_HF &mc_virt SLAVE_EBI_CH0>,
4604 <&mms !! 3919 <&mmss_noc MASTER_CAMNOC_SF &mc_virt SLAVE_EBI_CH0>,
4605 <&mms !! 3920 <&mmss_noc MASTER_CAMNOC_ICP &mc_virt SLAVE_EBI_CH0>;
4606 interconnect-names = 3921 interconnect-names = "cam_ahb",
4607 3922 "cam_hf_0_mnoc",
4608 3923 "cam_sf_0_mnoc",
4609 3924 "cam_sf_icp_mnoc";
4610 3925
4611 ports { 3926 ports {
4612 #address-cell 3927 #address-cells = <1>;
4613 #size-cells = 3928 #size-cells = <0>;
4614 3929
4615 port@0 { 3930 port@0 {
4616 reg = 3931 reg = <0>;
4617 }; 3932 };
4618 3933
4619 port@1 { 3934 port@1 {
4620 reg = 3935 reg = <1>;
4621 }; 3936 };
4622 3937
4623 port@2 { 3938 port@2 {
4624 reg = 3939 reg = <2>;
4625 }; 3940 };
4626 3941
4627 port@3 { 3942 port@3 {
4628 reg = 3943 reg = <3>;
4629 }; 3944 };
4630 3945
4631 port@4 { 3946 port@4 {
4632 reg = 3947 reg = <4>;
4633 }; 3948 };
4634 3949
4635 port@5 { 3950 port@5 {
4636 reg = 3951 reg = <5>;
4637 }; 3952 };
4638 }; 3953 };
4639 }; 3954 };
4640 3955
4641 camcc: clock-controller@ad000 3956 camcc: clock-controller@ad00000 {
4642 compatible = "qcom,sm 3957 compatible = "qcom,sm8250-camcc";
4643 reg = <0 0x0ad00000 0 3958 reg = <0 0x0ad00000 0 0x10000>;
4644 clocks = <&gcc GCC_CA 3959 clocks = <&gcc GCC_CAMERA_AHB_CLK>,
4645 <&rpmhcc RPM 3960 <&rpmhcc RPMH_CXO_CLK>,
4646 <&rpmhcc RPM 3961 <&rpmhcc RPMH_CXO_CLK_A>,
4647 <&sleep_clk> 3962 <&sleep_clk>;
4648 clock-names = "iface" 3963 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
4649 power-domains = <&rpm !! 3964 power-domains = <&rpmhpd SM8250_MMCX>;
4650 required-opps = <&rpm 3965 required-opps = <&rpmhpd_opp_low_svs>;
4651 status = "disabled"; 3966 status = "disabled";
4652 #clock-cells = <1>; 3967 #clock-cells = <1>;
4653 #reset-cells = <1>; 3968 #reset-cells = <1>;
4654 #power-domain-cells = 3969 #power-domain-cells = <1>;
4655 }; 3970 };
4656 3971
4657 mdss: display-subsystem@ae000 3972 mdss: display-subsystem@ae00000 {
4658 compatible = "qcom,sm 3973 compatible = "qcom,sm8250-mdss";
4659 reg = <0 0x0ae00000 0 3974 reg = <0 0x0ae00000 0 0x1000>;
4660 reg-names = "mdss"; 3975 reg-names = "mdss";
4661 3976
4662 interconnects = <&mms !! 3977 interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>,
4663 <&mms !! 3978 <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>;
4664 interconnect-names = 3979 interconnect-names = "mdp0-mem", "mdp1-mem";
4665 3980
4666 power-domains = <&dis 3981 power-domains = <&dispcc MDSS_GDSC>;
4667 3982
4668 clocks = <&dispcc DIS 3983 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4669 <&gcc GCC_DI 3984 <&gcc GCC_DISP_HF_AXI_CLK>,
4670 <&gcc GCC_DI 3985 <&gcc GCC_DISP_SF_AXI_CLK>,
4671 <&dispcc DIS 3986 <&dispcc DISP_CC_MDSS_MDP_CLK>;
4672 clock-names = "iface" 3987 clock-names = "iface", "bus", "nrt_bus", "core";
4673 3988
4674 interrupts = <GIC_SPI 3989 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
4675 interrupt-controller; 3990 interrupt-controller;
4676 #interrupt-cells = <1 3991 #interrupt-cells = <1>;
4677 3992
4678 iommus = <&apps_smmu 3993 iommus = <&apps_smmu 0x820 0x402>;
4679 3994
4680 status = "disabled"; 3995 status = "disabled";
4681 3996
4682 #address-cells = <2>; 3997 #address-cells = <2>;
4683 #size-cells = <2>; 3998 #size-cells = <2>;
4684 ranges; 3999 ranges;
4685 4000
4686 mdss_mdp: display-con 4001 mdss_mdp: display-controller@ae01000 {
4687 compatible = 4002 compatible = "qcom,sm8250-dpu";
4688 reg = <0 0x0a 4003 reg = <0 0x0ae01000 0 0x8f000>,
4689 <0 0x0a 4004 <0 0x0aeb0000 0 0x2008>;
4690 reg-names = " 4005 reg-names = "mdp", "vbif";
4691 4006
4692 clocks = <&di 4007 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4693 <&gc 4008 <&gcc GCC_DISP_HF_AXI_CLK>,
4694 <&di 4009 <&dispcc DISP_CC_MDSS_MDP_CLK>,
4695 <&di 4010 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4696 clock-names = 4011 clock-names = "iface", "bus", "core", "vsync";
4697 4012
4698 assigned-cloc 4013 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4699 assigned-cloc 4014 assigned-clock-rates = <19200000>;
4700 4015
4701 operating-poi 4016 operating-points-v2 = <&mdp_opp_table>;
4702 power-domains !! 4017 power-domains = <&rpmhpd SM8250_MMCX>;
4703 4018
4704 interrupt-par 4019 interrupt-parent = <&mdss>;
4705 interrupts = 4020 interrupts = <0>;
4706 4021
4707 ports { 4022 ports {
4708 #addr 4023 #address-cells = <1>;
4709 #size 4024 #size-cells = <0>;
4710 4025
4711 port@ 4026 port@0 {
4712 4027 reg = <0>;
4713 4028 dpu_intf1_out: endpoint {
4714 !! 4029 remote-endpoint = <&dsi0_in>;
4715 4030 };
4716 }; 4031 };
4717 4032
4718 port@ 4033 port@1 {
4719 4034 reg = <1>;
4720 4035 dpu_intf2_out: endpoint {
4721 !! 4036 remote-endpoint = <&dsi1_in>;
4722 <<
4723 }; <<
4724 <<
4725 port@ <<
4726 <<
4727 <<
4728 <<
4729 <<
4730 4037 };
4731 }; 4038 };
4732 }; 4039 };
4733 4040
4734 mdp_opp_table 4041 mdp_opp_table: opp-table {
4735 compa 4042 compatible = "operating-points-v2";
4736 4043
4737 opp-2 4044 opp-200000000 {
4738 4045 opp-hz = /bits/ 64 <200000000>;
4739 4046 required-opps = <&rpmhpd_opp_low_svs>;
4740 }; 4047 };
4741 4048
4742 opp-3 4049 opp-300000000 {
4743 4050 opp-hz = /bits/ 64 <300000000>;
4744 4051 required-opps = <&rpmhpd_opp_svs>;
4745 }; 4052 };
4746 4053
4747 opp-3 4054 opp-345000000 {
4748 4055 opp-hz = /bits/ 64 <345000000>;
4749 4056 required-opps = <&rpmhpd_opp_svs_l1>;
4750 }; 4057 };
4751 4058
4752 opp-4 4059 opp-460000000 {
4753 4060 opp-hz = /bits/ 64 <460000000>;
4754 4061 required-opps = <&rpmhpd_opp_nom>;
4755 }; 4062 };
4756 }; 4063 };
4757 }; 4064 };
4758 4065
4759 mdss_dp: displayport- !! 4066 dsi0: dsi@ae94000 {
4760 compatible = <<
4761 reg = <0 0xae <<
4762 <0 0xae <<
4763 <0 0xae <<
4764 <0 0xae <<
4765 <0 0xae <<
4766 interrupt-par <<
4767 interrupts = <<
4768 clocks = <&di <<
4769 <&di <<
4770 <&di <<
4771 <&di <<
4772 <&di <<
4773 clock-names = <<
4774 <<
4775 <<
4776 <<
4777 <<
4778 <<
4779 assigned-cloc <<
4780 <<
4781 assigned-cloc <<
4782 <<
4783 <<
4784 phys = <&usb_ <<
4785 phy-names = " <<
4786 <<
4787 #sound-dai-ce <<
4788 <<
4789 operating-poi <<
4790 power-domains <<
4791 <<
4792 status = "dis <<
4793 <<
4794 ports { <<
4795 #addr <<
4796 #size <<
4797 <<
4798 port@ <<
4799 <<
4800 <<
4801 <<
4802 <<
4803 }; <<
4804 <<
4805 port@ <<
4806 <<
4807 <<
4808 <<
4809 <<
4810 }; <<
4811 }; <<
4812 <<
4813 dp_opp_table: <<
4814 compa <<
4815 <<
4816 opp-1 <<
4817 <<
4818 <<
4819 }; <<
4820 <<
4821 opp-2 <<
4822 <<
4823 <<
4824 }; <<
4825 <<
4826 opp-5 <<
4827 <<
4828 <<
4829 }; <<
4830 <<
4831 opp-8 <<
4832 <<
4833 <<
4834 }; <<
4835 }; <<
4836 }; <<
4837 <<
4838 mdss_dsi0: dsi@ae9400 <<
4839 compatible = 4067 compatible = "qcom,sm8250-dsi-ctrl",
4840 4068 "qcom,mdss-dsi-ctrl";
4841 reg = <0 0x0a 4069 reg = <0 0x0ae94000 0 0x400>;
4842 reg-names = " 4070 reg-names = "dsi_ctrl";
4843 4071
4844 interrupt-par 4072 interrupt-parent = <&mdss>;
4845 interrupts = 4073 interrupts = <4>;
4846 4074
4847 clocks = <&di 4075 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
4848 <&di 4076 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
4849 <&di 4077 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
4850 <&di 4078 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
4851 <&di 4079 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4852 <&gcc 4080 <&gcc GCC_DISP_HF_AXI_CLK>;
4853 clock-names = 4081 clock-names = "byte",
4854 4082 "byte_intf",
4855 4083 "pixel",
4856 4084 "core",
4857 4085 "iface",
4858 4086 "bus";
4859 4087
4860 assigned-cloc 4088 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
4861 assigned-cloc !! 4089 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
4862 4090
4863 operating-poi 4091 operating-points-v2 = <&dsi_opp_table>;
4864 power-domains !! 4092 power-domains = <&rpmhpd SM8250_MMCX>;
4865 4093
4866 phys = <&mdss !! 4094 phys = <&dsi0_phy>;
4867 4095
4868 status = "dis 4096 status = "disabled";
4869 4097
4870 #address-cell 4098 #address-cells = <1>;
4871 #size-cells = 4099 #size-cells = <0>;
4872 4100
4873 ports { 4101 ports {
4874 #addr 4102 #address-cells = <1>;
4875 #size 4103 #size-cells = <0>;
4876 4104
4877 port@ 4105 port@0 {
4878 4106 reg = <0>;
4879 !! 4107 dsi0_in: endpoint {
4880 4108 remote-endpoint = <&dpu_intf1_out>;
4881 4109 };
4882 }; 4110 };
4883 4111
4884 port@ 4112 port@1 {
4885 4113 reg = <1>;
4886 !! 4114 dsi0_out: endpoint {
4887 4115 };
4888 }; 4116 };
4889 }; 4117 };
4890 4118
4891 dsi_opp_table 4119 dsi_opp_table: opp-table {
4892 compa 4120 compatible = "operating-points-v2";
4893 4121
4894 opp-1 4122 opp-187500000 {
4895 4123 opp-hz = /bits/ 64 <187500000>;
4896 4124 required-opps = <&rpmhpd_opp_low_svs>;
4897 }; 4125 };
4898 4126
4899 opp-3 4127 opp-300000000 {
4900 4128 opp-hz = /bits/ 64 <300000000>;
4901 4129 required-opps = <&rpmhpd_opp_svs>;
4902 }; 4130 };
4903 4131
4904 opp-3 4132 opp-358000000 {
4905 4133 opp-hz = /bits/ 64 <358000000>;
4906 4134 required-opps = <&rpmhpd_opp_svs_l1>;
4907 }; 4135 };
4908 }; 4136 };
4909 }; 4137 };
4910 4138
4911 mdss_dsi0_phy: phy@ae !! 4139 dsi0_phy: phy@ae94400 {
4912 compatible = 4140 compatible = "qcom,dsi-phy-7nm";
4913 reg = <0 0x0a 4141 reg = <0 0x0ae94400 0 0x200>,
4914 <0 0x0a 4142 <0 0x0ae94600 0 0x280>,
4915 <0 0x0a 4143 <0 0x0ae94900 0 0x260>;
4916 reg-names = " 4144 reg-names = "dsi_phy",
4917 " 4145 "dsi_phy_lane",
4918 " 4146 "dsi_pll";
4919 4147
4920 #clock-cells 4148 #clock-cells = <1>;
4921 #phy-cells = 4149 #phy-cells = <0>;
4922 4150
4923 clocks = <&di 4151 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4924 <&rp 4152 <&rpmhcc RPMH_CXO_CLK>;
4925 clock-names = 4153 clock-names = "iface", "ref";
4926 4154
4927 status = "dis 4155 status = "disabled";
4928 }; 4156 };
4929 4157
4930 mdss_dsi1: dsi@ae9600 !! 4158 dsi1: dsi@ae96000 {
4931 compatible = 4159 compatible = "qcom,sm8250-dsi-ctrl",
4932 4160 "qcom,mdss-dsi-ctrl";
4933 reg = <0 0x0a 4161 reg = <0 0x0ae96000 0 0x400>;
4934 reg-names = " 4162 reg-names = "dsi_ctrl";
4935 4163
4936 interrupt-par 4164 interrupt-parent = <&mdss>;
4937 interrupts = 4165 interrupts = <5>;
4938 4166
4939 clocks = <&di 4167 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
4940 <&di 4168 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
4941 <&di 4169 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
4942 <&di 4170 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
4943 <&di 4171 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4944 <&gc 4172 <&gcc GCC_DISP_HF_AXI_CLK>;
4945 clock-names = 4173 clock-names = "byte",
4946 4174 "byte_intf",
4947 4175 "pixel",
4948 4176 "core",
4949 4177 "iface",
4950 4178 "bus";
4951 4179
4952 assigned-cloc 4180 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
4953 assigned-cloc !! 4181 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
4954 4182
4955 operating-poi 4183 operating-points-v2 = <&dsi_opp_table>;
4956 power-domains !! 4184 power-domains = <&rpmhpd SM8250_MMCX>;
4957 4185
4958 phys = <&mdss !! 4186 phys = <&dsi1_phy>;
4959 4187
4960 status = "dis 4188 status = "disabled";
4961 4189
4962 #address-cell 4190 #address-cells = <1>;
4963 #size-cells = 4191 #size-cells = <0>;
4964 4192
4965 ports { 4193 ports {
4966 #addr 4194 #address-cells = <1>;
4967 #size 4195 #size-cells = <0>;
4968 4196
4969 port@ 4197 port@0 {
4970 4198 reg = <0>;
4971 !! 4199 dsi1_in: endpoint {
4972 4200 remote-endpoint = <&dpu_intf2_out>;
4973 4201 };
4974 }; 4202 };
4975 4203
4976 port@ 4204 port@1 {
4977 4205 reg = <1>;
4978 !! 4206 dsi1_out: endpoint {
4979 4207 };
4980 }; 4208 };
4981 }; 4209 };
4982 }; 4210 };
4983 4211
4984 mdss_dsi1_phy: phy@ae !! 4212 dsi1_phy: phy@ae96400 {
4985 compatible = 4213 compatible = "qcom,dsi-phy-7nm";
4986 reg = <0 0x0a 4214 reg = <0 0x0ae96400 0 0x200>,
4987 <0 0x0a 4215 <0 0x0ae96600 0 0x280>,
4988 <0 0x0a 4216 <0 0x0ae96900 0 0x260>;
4989 reg-names = " 4217 reg-names = "dsi_phy",
4990 " 4218 "dsi_phy_lane",
4991 " 4219 "dsi_pll";
4992 4220
4993 #clock-cells 4221 #clock-cells = <1>;
4994 #phy-cells = 4222 #phy-cells = <0>;
4995 4223
4996 clocks = <&di 4224 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4997 <&rp 4225 <&rpmhcc RPMH_CXO_CLK>;
4998 clock-names = 4226 clock-names = "iface", "ref";
4999 4227
5000 status = "dis 4228 status = "disabled";
5001 }; 4229 };
5002 }; 4230 };
5003 4231
5004 dispcc: clock-controller@af00 4232 dispcc: clock-controller@af00000 {
5005 compatible = "qcom,sm 4233 compatible = "qcom,sm8250-dispcc";
5006 reg = <0 0x0af00000 0 4234 reg = <0 0x0af00000 0 0x10000>;
5007 power-domains = <&rpm !! 4235 power-domains = <&rpmhpd SM8250_MMCX>;
5008 required-opps = <&rpm 4236 required-opps = <&rpmhpd_opp_low_svs>;
5009 clocks = <&rpmhcc RPM 4237 clocks = <&rpmhcc RPMH_CXO_CLK>,
5010 <&mdss_dsi0_ !! 4238 <&dsi0_phy 0>,
5011 <&mdss_dsi0_ !! 4239 <&dsi0_phy 1>,
5012 <&mdss_dsi1_ !! 4240 <&dsi1_phy 0>,
5013 <&mdss_dsi1_ !! 4241 <&dsi1_phy 1>,
5014 <&usb_1_qmpp !! 4242 <&dp_phy 0>,
5015 <&usb_1_qmpp !! 4243 <&dp_phy 1>;
5016 clock-names = "bi_tcx 4244 clock-names = "bi_tcxo",
5017 "dsi0_p 4245 "dsi0_phy_pll_out_byteclk",
5018 "dsi0_p 4246 "dsi0_phy_pll_out_dsiclk",
5019 "dsi1_p 4247 "dsi1_phy_pll_out_byteclk",
5020 "dsi1_p 4248 "dsi1_phy_pll_out_dsiclk",
5021 "dp_phy 4249 "dp_phy_pll_link_clk",
5022 "dp_phy 4250 "dp_phy_pll_vco_div_clk";
5023 #clock-cells = <1>; 4251 #clock-cells = <1>;
5024 #reset-cells = <1>; 4252 #reset-cells = <1>;
5025 #power-domain-cells = 4253 #power-domain-cells = <1>;
5026 }; 4254 };
5027 4255
5028 pdc: interrupt-controller@b22 4256 pdc: interrupt-controller@b220000 {
5029 compatible = "qcom,sm 4257 compatible = "qcom,sm8250-pdc", "qcom,pdc";
5030 reg = <0 0x0b220000 0 4258 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
5031 qcom,pdc-ranges = <0 4259 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
5032 <12 4260 <125 63 1>, <126 716 12>;
5033 #interrupt-cells = <2 4261 #interrupt-cells = <2>;
5034 interrupt-parent = <& 4262 interrupt-parent = <&intc>;
5035 interrupt-controller; 4263 interrupt-controller;
5036 }; 4264 };
5037 4265
5038 tsens0: thermal-sensor@c26300 4266 tsens0: thermal-sensor@c263000 {
5039 compatible = "qcom,sm 4267 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
5040 reg = <0 0x0c263000 0 4268 reg = <0 0x0c263000 0 0x1ff>, /* TM */
5041 <0 0x0c222000 0 4269 <0 0x0c222000 0 0x1ff>; /* SROT */
5042 #qcom,sensors = <16>; 4270 #qcom,sensors = <16>;
5043 interrupts = <GIC_SPI 4271 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
5044 <GIC_SPI 4272 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
5045 interrupt-names = "up 4273 interrupt-names = "uplow", "critical";
5046 #thermal-sensor-cells 4274 #thermal-sensor-cells = <1>;
5047 }; 4275 };
5048 4276
5049 tsens1: thermal-sensor@c26500 4277 tsens1: thermal-sensor@c265000 {
5050 compatible = "qcom,sm 4278 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
5051 reg = <0 0x0c265000 0 4279 reg = <0 0x0c265000 0 0x1ff>, /* TM */
5052 <0 0x0c223000 0 4280 <0 0x0c223000 0 0x1ff>; /* SROT */
5053 #qcom,sensors = <9>; 4281 #qcom,sensors = <9>;
5054 interrupts = <GIC_SPI 4282 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
5055 <GIC_SPI 4283 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
5056 interrupt-names = "up 4284 interrupt-names = "uplow", "critical";
5057 #thermal-sensor-cells 4285 #thermal-sensor-cells = <1>;
5058 }; 4286 };
5059 4287
5060 aoss_qmp: power-management@c3 4288 aoss_qmp: power-management@c300000 {
5061 compatible = "qcom,sm 4289 compatible = "qcom,sm8250-aoss-qmp", "qcom,aoss-qmp";
5062 reg = <0 0x0c300000 0 4290 reg = <0 0x0c300000 0 0x400>;
5063 interrupts-extended = 4291 interrupts-extended = <&ipcc IPCC_CLIENT_AOP
5064 4292 IPCC_MPROC_SIGNAL_GLINK_QMP
5065 4293 IRQ_TYPE_EDGE_RISING>;
5066 mboxes = <&ipcc IPCC_ 4294 mboxes = <&ipcc IPCC_CLIENT_AOP
5067 IPCC_ 4295 IPCC_MPROC_SIGNAL_GLINK_QMP>;
5068 4296
5069 #clock-cells = <0>; 4297 #clock-cells = <0>;
5070 }; 4298 };
5071 4299
5072 sram@c3f0000 { 4300 sram@c3f0000 {
5073 compatible = "qcom,rp 4301 compatible = "qcom,rpmh-stats";
5074 reg = <0 0x0c3f0000 0 4302 reg = <0 0x0c3f0000 0 0x400>;
5075 }; 4303 };
5076 4304
5077 spmi_bus: spmi@c440000 { 4305 spmi_bus: spmi@c440000 {
5078 compatible = "qcom,sp 4306 compatible = "qcom,spmi-pmic-arb";
5079 reg = <0x0 0x0c440000 4307 reg = <0x0 0x0c440000 0x0 0x0001100>,
5080 <0x0 0x0c600000 4308 <0x0 0x0c600000 0x0 0x2000000>,
5081 <0x0 0x0e600000 4309 <0x0 0x0e600000 0x0 0x0100000>,
5082 <0x0 0x0e700000 4310 <0x0 0x0e700000 0x0 0x00a0000>,
5083 <0x0 0x0c40a000 4311 <0x0 0x0c40a000 0x0 0x0026000>;
5084 reg-names = "core", " 4312 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
5085 interrupt-names = "pe 4313 interrupt-names = "periph_irq";
5086 interrupts-extended = 4314 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
5087 qcom,ee = <0>; 4315 qcom,ee = <0>;
5088 qcom,channel = <0>; 4316 qcom,channel = <0>;
5089 #address-cells = <2>; 4317 #address-cells = <2>;
5090 #size-cells = <0>; 4318 #size-cells = <0>;
5091 interrupt-controller; 4319 interrupt-controller;
5092 #interrupt-cells = <4 4320 #interrupt-cells = <4>;
5093 }; 4321 };
5094 4322
5095 tlmm: pinctrl@f100000 { 4323 tlmm: pinctrl@f100000 {
5096 compatible = "qcom,sm 4324 compatible = "qcom,sm8250-pinctrl";
5097 reg = <0 0x0f100000 0 4325 reg = <0 0x0f100000 0 0x300000>,
5098 <0 0x0f500000 0 4326 <0 0x0f500000 0 0x300000>,
5099 <0 0x0f900000 0 4327 <0 0x0f900000 0 0x300000>;
5100 reg-names = "west", " 4328 reg-names = "west", "south", "north";
5101 interrupts = <GIC_SPI 4329 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
5102 gpio-controller; 4330 gpio-controller;
5103 #gpio-cells = <2>; 4331 #gpio-cells = <2>;
5104 interrupt-controller; 4332 interrupt-controller;
5105 #interrupt-cells = <2 4333 #interrupt-cells = <2>;
5106 gpio-ranges = <&tlmm 4334 gpio-ranges = <&tlmm 0 0 181>;
5107 wakeup-parent = <&pdc 4335 wakeup-parent = <&pdc>;
5108 4336
5109 cam2_default: cam2-de 4337 cam2_default: cam2-default-state {
5110 rst-pins { 4338 rst-pins {
5111 pins 4339 pins = "gpio78";
5112 funct 4340 function = "gpio";
5113 drive 4341 drive-strength = <2>;
5114 bias- 4342 bias-disable;
5115 }; 4343 };
5116 4344
5117 mclk-pins { 4345 mclk-pins {
5118 pins 4346 pins = "gpio96";
5119 funct 4347 function = "cam_mclk";
5120 drive 4348 drive-strength = <16>;
5121 bias- 4349 bias-disable;
5122 }; 4350 };
5123 }; 4351 };
5124 4352
5125 cam2_suspend: cam2-su 4353 cam2_suspend: cam2-suspend-state {
5126 rst-pins { 4354 rst-pins {
5127 pins 4355 pins = "gpio78";
5128 funct 4356 function = "gpio";
5129 drive 4357 drive-strength = <2>;
5130 bias- 4358 bias-pull-down;
5131 outpu 4359 output-low;
5132 }; 4360 };
5133 4361
5134 mclk-pins { 4362 mclk-pins {
5135 pins 4363 pins = "gpio96";
5136 funct 4364 function = "cam_mclk";
5137 drive 4365 drive-strength = <2>;
5138 bias- 4366 bias-disable;
5139 }; 4367 };
5140 }; 4368 };
5141 4369
5142 cci0_default: cci0-de 4370 cci0_default: cci0-default-state {
5143 cci0_i2c0_def 4371 cci0_i2c0_default: cci0-i2c0-default-pins {
5144 /* SD 4372 /* SDA, SCL */
5145 pins 4373 pins = "gpio101", "gpio102";
5146 funct 4374 function = "cci_i2c";
5147 4375
5148 bias- 4376 bias-pull-up;
5149 drive 4377 drive-strength = <2>; /* 2 mA */
5150 }; 4378 };
5151 4379
5152 cci0_i2c1_def 4380 cci0_i2c1_default: cci0-i2c1-default-pins {
5153 /* SD 4381 /* SDA, SCL */
5154 pins 4382 pins = "gpio103", "gpio104";
5155 funct 4383 function = "cci_i2c";
5156 4384
5157 bias- 4385 bias-pull-up;
5158 drive 4386 drive-strength = <2>; /* 2 mA */
5159 }; 4387 };
5160 }; 4388 };
5161 4389
5162 cci0_sleep: cci0-slee 4390 cci0_sleep: cci0-sleep-state {
5163 cci0_i2c0_sle 4391 cci0_i2c0_sleep: cci0-i2c0-sleep-pins {
5164 /* SD 4392 /* SDA, SCL */
5165 pins 4393 pins = "gpio101", "gpio102";
5166 funct 4394 function = "cci_i2c";
5167 4395
5168 drive 4396 drive-strength = <2>; /* 2 mA */
5169 bias- 4397 bias-pull-down;
5170 }; 4398 };
5171 4399
5172 cci0_i2c1_sle 4400 cci0_i2c1_sleep: cci0-i2c1-sleep-pins {
5173 /* SD 4401 /* SDA, SCL */
5174 pins 4402 pins = "gpio103", "gpio104";
5175 funct 4403 function = "cci_i2c";
5176 4404
5177 drive 4405 drive-strength = <2>; /* 2 mA */
5178 bias- 4406 bias-pull-down;
5179 }; 4407 };
5180 }; 4408 };
5181 4409
5182 cci1_default: cci1-de 4410 cci1_default: cci1-default-state {
5183 cci1_i2c0_def 4411 cci1_i2c0_default: cci1-i2c0-default-pins {
5184 /* SD 4412 /* SDA, SCL */
5185 pins 4413 pins = "gpio105","gpio106";
5186 funct 4414 function = "cci_i2c";
5187 4415
5188 bias- 4416 bias-pull-up;
5189 drive 4417 drive-strength = <2>; /* 2 mA */
5190 }; 4418 };
5191 4419
5192 cci1_i2c1_def 4420 cci1_i2c1_default: cci1-i2c1-default-pins {
5193 /* SD 4421 /* SDA, SCL */
5194 pins 4422 pins = "gpio107","gpio108";
5195 funct 4423 function = "cci_i2c";
5196 4424
5197 bias- 4425 bias-pull-up;
5198 drive 4426 drive-strength = <2>; /* 2 mA */
5199 }; 4427 };
5200 }; 4428 };
5201 4429
5202 cci1_sleep: cci1-slee 4430 cci1_sleep: cci1-sleep-state {
5203 cci1_i2c0_sle 4431 cci1_i2c0_sleep: cci1-i2c0-sleep-pins {
5204 /* SD 4432 /* SDA, SCL */
5205 pins 4433 pins = "gpio105","gpio106";
5206 funct 4434 function = "cci_i2c";
5207 4435
5208 bias- 4436 bias-pull-down;
5209 drive 4437 drive-strength = <2>; /* 2 mA */
5210 }; 4438 };
5211 4439
5212 cci1_i2c1_sle 4440 cci1_i2c1_sleep: cci1-i2c1-sleep-pins {
5213 /* SD 4441 /* SDA, SCL */
5214 pins 4442 pins = "gpio107","gpio108";
5215 funct 4443 function = "cci_i2c";
5216 4444
5217 bias- 4445 bias-pull-down;
5218 drive 4446 drive-strength = <2>; /* 2 mA */
5219 }; 4447 };
5220 }; 4448 };
5221 4449
5222 pri_mi2s_active: pri- 4450 pri_mi2s_active: pri-mi2s-active-state {
5223 sclk-pins { 4451 sclk-pins {
5224 pins 4452 pins = "gpio138";
5225 funct 4453 function = "mi2s0_sck";
5226 drive 4454 drive-strength = <8>;
5227 bias- 4455 bias-disable;
5228 }; 4456 };
5229 4457
5230 ws-pins { 4458 ws-pins {
5231 pins 4459 pins = "gpio141";
5232 funct 4460 function = "mi2s0_ws";
5233 drive 4461 drive-strength = <8>;
5234 outpu 4462 output-high;
5235 }; 4463 };
5236 4464
5237 data0-pins { 4465 data0-pins {
5238 pins 4466 pins = "gpio139";
5239 funct 4467 function = "mi2s0_data0";
5240 drive 4468 drive-strength = <8>;
5241 bias- 4469 bias-disable;
5242 outpu 4470 output-high;
5243 }; 4471 };
5244 4472
5245 data1-pins { 4473 data1-pins {
5246 pins 4474 pins = "gpio140";
5247 funct 4475 function = "mi2s0_data1";
5248 drive 4476 drive-strength = <8>;
5249 outpu 4477 output-high;
5250 }; 4478 };
5251 }; 4479 };
5252 4480
5253 qup_i2c0_default: qup 4481 qup_i2c0_default: qup-i2c0-default-state {
5254 pins = "gpio2 4482 pins = "gpio28", "gpio29";
5255 function = "q 4483 function = "qup0";
5256 drive-strengt 4484 drive-strength = <2>;
5257 bias-disable; 4485 bias-disable;
5258 }; 4486 };
5259 4487
5260 qup_i2c1_default: qup 4488 qup_i2c1_default: qup-i2c1-default-state {
5261 pins = "gpio4 4489 pins = "gpio4", "gpio5";
5262 function = "q 4490 function = "qup1";
5263 drive-strengt 4491 drive-strength = <2>;
5264 bias-disable; 4492 bias-disable;
5265 }; 4493 };
5266 4494
5267 qup_i2c2_default: qup 4495 qup_i2c2_default: qup-i2c2-default-state {
5268 pins = "gpio1 4496 pins = "gpio115", "gpio116";
5269 function = "q 4497 function = "qup2";
5270 drive-strengt 4498 drive-strength = <2>;
5271 bias-disable; 4499 bias-disable;
5272 }; 4500 };
5273 4501
5274 qup_i2c3_default: qup 4502 qup_i2c3_default: qup-i2c3-default-state {
5275 pins = "gpio1 4503 pins = "gpio119", "gpio120";
5276 function = "q 4504 function = "qup3";
5277 drive-strengt 4505 drive-strength = <2>;
5278 bias-disable; 4506 bias-disable;
5279 }; 4507 };
5280 4508
5281 qup_i2c4_default: qup 4509 qup_i2c4_default: qup-i2c4-default-state {
5282 pins = "gpio8 4510 pins = "gpio8", "gpio9";
5283 function = "q 4511 function = "qup4";
5284 drive-strengt 4512 drive-strength = <2>;
5285 bias-disable; 4513 bias-disable;
5286 }; 4514 };
5287 4515
5288 qup_i2c5_default: qup 4516 qup_i2c5_default: qup-i2c5-default-state {
5289 pins = "gpio1 4517 pins = "gpio12", "gpio13";
5290 function = "q 4518 function = "qup5";
5291 drive-strengt 4519 drive-strength = <2>;
5292 bias-disable; 4520 bias-disable;
5293 }; 4521 };
5294 4522
5295 qup_i2c6_default: qup 4523 qup_i2c6_default: qup-i2c6-default-state {
5296 pins = "gpio1 4524 pins = "gpio16", "gpio17";
5297 function = "q 4525 function = "qup6";
5298 drive-strengt 4526 drive-strength = <2>;
5299 bias-disable; 4527 bias-disable;
5300 }; 4528 };
5301 4529
5302 qup_i2c7_default: qup 4530 qup_i2c7_default: qup-i2c7-default-state {
5303 pins = "gpio2 4531 pins = "gpio20", "gpio21";
5304 function = "q 4532 function = "qup7";
5305 drive-strengt 4533 drive-strength = <2>;
5306 bias-disable; 4534 bias-disable;
5307 }; 4535 };
5308 4536
5309 qup_i2c8_default: qup 4537 qup_i2c8_default: qup-i2c8-default-state {
5310 pins = "gpio2 4538 pins = "gpio24", "gpio25";
5311 function = "q 4539 function = "qup8";
5312 drive-strengt 4540 drive-strength = <2>;
5313 bias-disable; 4541 bias-disable;
5314 }; 4542 };
5315 4543
5316 qup_i2c9_default: qup 4544 qup_i2c9_default: qup-i2c9-default-state {
5317 pins = "gpio1 4545 pins = "gpio125", "gpio126";
5318 function = "q 4546 function = "qup9";
5319 drive-strengt 4547 drive-strength = <2>;
5320 bias-disable; 4548 bias-disable;
5321 }; 4549 };
5322 4550
5323 qup_i2c10_default: qu 4551 qup_i2c10_default: qup-i2c10-default-state {
5324 pins = "gpio1 4552 pins = "gpio129", "gpio130";
5325 function = "q 4553 function = "qup10";
5326 drive-strengt 4554 drive-strength = <2>;
5327 bias-disable; 4555 bias-disable;
5328 }; 4556 };
5329 4557
5330 qup_i2c11_default: qu 4558 qup_i2c11_default: qup-i2c11-default-state {
5331 pins = "gpio6 4559 pins = "gpio60", "gpio61";
5332 function = "q 4560 function = "qup11";
5333 drive-strengt 4561 drive-strength = <2>;
5334 bias-disable; 4562 bias-disable;
5335 }; 4563 };
5336 4564
5337 qup_i2c12_default: qu 4565 qup_i2c12_default: qup-i2c12-default-state {
5338 pins = "gpio3 4566 pins = "gpio32", "gpio33";
5339 function = "q 4567 function = "qup12";
5340 drive-strengt 4568 drive-strength = <2>;
5341 bias-disable; 4569 bias-disable;
5342 }; 4570 };
5343 4571
5344 qup_i2c13_default: qu 4572 qup_i2c13_default: qup-i2c13-default-state {
5345 pins = "gpio3 4573 pins = "gpio36", "gpio37";
5346 function = "q 4574 function = "qup13";
5347 drive-strengt 4575 drive-strength = <2>;
5348 bias-disable; 4576 bias-disable;
5349 }; 4577 };
5350 4578
5351 qup_i2c14_default: qu 4579 qup_i2c14_default: qup-i2c14-default-state {
5352 pins = "gpio4 4580 pins = "gpio40", "gpio41";
5353 function = "q 4581 function = "qup14";
5354 drive-strengt 4582 drive-strength = <2>;
5355 bias-disable; 4583 bias-disable;
5356 }; 4584 };
5357 4585
5358 qup_i2c15_default: qu 4586 qup_i2c15_default: qup-i2c15-default-state {
5359 pins = "gpio4 4587 pins = "gpio44", "gpio45";
5360 function = "q 4588 function = "qup15";
5361 drive-strengt 4589 drive-strength = <2>;
5362 bias-disable; 4590 bias-disable;
5363 }; 4591 };
5364 4592
5365 qup_i2c16_default: qu 4593 qup_i2c16_default: qup-i2c16-default-state {
5366 pins = "gpio4 4594 pins = "gpio48", "gpio49";
5367 function = "q 4595 function = "qup16";
5368 drive-strengt 4596 drive-strength = <2>;
5369 bias-disable; 4597 bias-disable;
5370 }; 4598 };
5371 4599
5372 qup_i2c17_default: qu 4600 qup_i2c17_default: qup-i2c17-default-state {
5373 pins = "gpio5 4601 pins = "gpio52", "gpio53";
5374 function = "q 4602 function = "qup17";
5375 drive-strengt 4603 drive-strength = <2>;
5376 bias-disable; 4604 bias-disable;
5377 }; 4605 };
5378 4606
5379 qup_i2c18_default: qu 4607 qup_i2c18_default: qup-i2c18-default-state {
5380 pins = "gpio5 4608 pins = "gpio56", "gpio57";
5381 function = "q 4609 function = "qup18";
5382 drive-strengt 4610 drive-strength = <2>;
5383 bias-disable; 4611 bias-disable;
5384 }; 4612 };
5385 4613
5386 qup_i2c19_default: qu 4614 qup_i2c19_default: qup-i2c19-default-state {
5387 pins = "gpio0 4615 pins = "gpio0", "gpio1";
5388 function = "q 4616 function = "qup19";
5389 drive-strengt 4617 drive-strength = <2>;
5390 bias-disable; 4618 bias-disable;
5391 }; 4619 };
5392 4620
5393 qup_spi0_cs: qup-spi0 4621 qup_spi0_cs: qup-spi0-cs-state {
5394 pins = "gpio3 4622 pins = "gpio31";
5395 function = "q 4623 function = "qup0";
5396 }; 4624 };
5397 4625
5398 qup_spi0_cs_gpio: qup 4626 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state {
5399 pins = "gpio3 4627 pins = "gpio31";
5400 function = "g 4628 function = "gpio";
5401 }; 4629 };
5402 4630
5403 qup_spi0_data_clk: qu 4631 qup_spi0_data_clk: qup-spi0-data-clk-state {
5404 pins = "gpio2 4632 pins = "gpio28", "gpio29",
5405 "gpio3 4633 "gpio30";
5406 function = "q 4634 function = "qup0";
5407 }; 4635 };
5408 4636
5409 qup_spi1_cs: qup-spi1 4637 qup_spi1_cs: qup-spi1-cs-state {
5410 pins = "gpio7 4638 pins = "gpio7";
5411 function = "q 4639 function = "qup1";
5412 }; 4640 };
5413 4641
5414 qup_spi1_cs_gpio: qup 4642 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state {
5415 pins = "gpio7 4643 pins = "gpio7";
5416 function = "g 4644 function = "gpio";
5417 }; 4645 };
5418 4646
5419 qup_spi1_data_clk: qu 4647 qup_spi1_data_clk: qup-spi1-data-clk-state {
5420 pins = "gpio4 4648 pins = "gpio4", "gpio5",
5421 "gpio6 4649 "gpio6";
5422 function = "q 4650 function = "qup1";
5423 }; 4651 };
5424 4652
5425 qup_spi2_cs: qup-spi2 4653 qup_spi2_cs: qup-spi2-cs-state {
5426 pins = "gpio1 4654 pins = "gpio118";
5427 function = "q 4655 function = "qup2";
5428 }; 4656 };
5429 4657
5430 qup_spi2_cs_gpio: qup 4658 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state {
5431 pins = "gpio1 4659 pins = "gpio118";
5432 function = "g 4660 function = "gpio";
5433 }; 4661 };
5434 4662
5435 qup_spi2_data_clk: qu 4663 qup_spi2_data_clk: qup-spi2-data-clk-state {
5436 pins = "gpio1 4664 pins = "gpio115", "gpio116",
5437 "gpio1 4665 "gpio117";
5438 function = "q 4666 function = "qup2";
5439 }; 4667 };
5440 4668
5441 qup_spi3_cs: qup-spi3 4669 qup_spi3_cs: qup-spi3-cs-state {
5442 pins = "gpio1 4670 pins = "gpio122";
5443 function = "q 4671 function = "qup3";
5444 }; 4672 };
5445 4673
5446 qup_spi3_cs_gpio: qup 4674 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state {
5447 pins = "gpio1 4675 pins = "gpio122";
5448 function = "g 4676 function = "gpio";
5449 }; 4677 };
5450 4678
5451 qup_spi3_data_clk: qu 4679 qup_spi3_data_clk: qup-spi3-data-clk-state {
5452 pins = "gpio1 4680 pins = "gpio119", "gpio120",
5453 "gpio1 4681 "gpio121";
5454 function = "q 4682 function = "qup3";
5455 }; 4683 };
5456 4684
5457 qup_spi4_cs: qup-spi4 4685 qup_spi4_cs: qup-spi4-cs-state {
5458 pins = "gpio1 4686 pins = "gpio11";
5459 function = "q 4687 function = "qup4";
5460 }; 4688 };
5461 4689
5462 qup_spi4_cs_gpio: qup 4690 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state {
5463 pins = "gpio1 4691 pins = "gpio11";
5464 function = "g 4692 function = "gpio";
5465 }; 4693 };
5466 4694
5467 qup_spi4_data_clk: qu 4695 qup_spi4_data_clk: qup-spi4-data-clk-state {
5468 pins = "gpio8 4696 pins = "gpio8", "gpio9",
5469 "gpio1 4697 "gpio10";
5470 function = "q 4698 function = "qup4";
5471 }; 4699 };
5472 4700
5473 qup_spi5_cs: qup-spi5 4701 qup_spi5_cs: qup-spi5-cs-state {
5474 pins = "gpio1 4702 pins = "gpio15";
5475 function = "q 4703 function = "qup5";
5476 }; 4704 };
5477 4705
5478 qup_spi5_cs_gpio: qup 4706 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state {
5479 pins = "gpio1 4707 pins = "gpio15";
5480 function = "g 4708 function = "gpio";
5481 }; 4709 };
5482 4710
5483 qup_spi5_data_clk: qu 4711 qup_spi5_data_clk: qup-spi5-data-clk-state {
5484 pins = "gpio1 4712 pins = "gpio12", "gpio13",
5485 "gpio1 4713 "gpio14";
5486 function = "q 4714 function = "qup5";
5487 }; 4715 };
5488 4716
5489 qup_spi6_cs: qup-spi6 4717 qup_spi6_cs: qup-spi6-cs-state {
5490 pins = "gpio1 4718 pins = "gpio19";
5491 function = "q 4719 function = "qup6";
5492 }; 4720 };
5493 4721
5494 qup_spi6_cs_gpio: qup 4722 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state {
5495 pins = "gpio1 4723 pins = "gpio19";
5496 function = "g 4724 function = "gpio";
5497 }; 4725 };
5498 4726
5499 qup_spi6_data_clk: qu 4727 qup_spi6_data_clk: qup-spi6-data-clk-state {
5500 pins = "gpio1 4728 pins = "gpio16", "gpio17",
5501 "gpio1 4729 "gpio18";
5502 function = "q 4730 function = "qup6";
5503 }; 4731 };
5504 4732
5505 qup_spi7_cs: qup-spi7 4733 qup_spi7_cs: qup-spi7-cs-state {
5506 pins = "gpio2 4734 pins = "gpio23";
5507 function = "q 4735 function = "qup7";
5508 }; 4736 };
5509 4737
5510 qup_spi7_cs_gpio: qup 4738 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state {
5511 pins = "gpio2 4739 pins = "gpio23";
5512 function = "g 4740 function = "gpio";
5513 }; 4741 };
5514 4742
5515 qup_spi7_data_clk: qu 4743 qup_spi7_data_clk: qup-spi7-data-clk-state {
5516 pins = "gpio2 4744 pins = "gpio20", "gpio21",
5517 "gpio2 4745 "gpio22";
5518 function = "q 4746 function = "qup7";
5519 }; 4747 };
5520 4748
5521 qup_spi8_cs: qup-spi8 4749 qup_spi8_cs: qup-spi8-cs-state {
5522 pins = "gpio2 4750 pins = "gpio27";
5523 function = "q 4751 function = "qup8";
5524 }; 4752 };
5525 4753
5526 qup_spi8_cs_gpio: qup 4754 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state {
5527 pins = "gpio2 4755 pins = "gpio27";
5528 function = "g 4756 function = "gpio";
5529 }; 4757 };
5530 4758
5531 qup_spi8_data_clk: qu 4759 qup_spi8_data_clk: qup-spi8-data-clk-state {
5532 pins = "gpio2 4760 pins = "gpio24", "gpio25",
5533 "gpio2 4761 "gpio26";
5534 function = "q 4762 function = "qup8";
5535 }; 4763 };
5536 4764
5537 qup_spi9_cs: qup-spi9 4765 qup_spi9_cs: qup-spi9-cs-state {
5538 pins = "gpio1 4766 pins = "gpio128";
5539 function = "q 4767 function = "qup9";
5540 }; 4768 };
5541 4769
5542 qup_spi9_cs_gpio: qup 4770 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state {
5543 pins = "gpio1 4771 pins = "gpio128";
5544 function = "g 4772 function = "gpio";
5545 }; 4773 };
5546 4774
5547 qup_spi9_data_clk: qu 4775 qup_spi9_data_clk: qup-spi9-data-clk-state {
5548 pins = "gpio1 4776 pins = "gpio125", "gpio126",
5549 "gpio1 4777 "gpio127";
5550 function = "q 4778 function = "qup9";
5551 }; 4779 };
5552 4780
5553 qup_spi10_cs: qup-spi 4781 qup_spi10_cs: qup-spi10-cs-state {
5554 pins = "gpio1 4782 pins = "gpio132";
5555 function = "q 4783 function = "qup10";
5556 }; 4784 };
5557 4785
5558 qup_spi10_cs_gpio: qu 4786 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state {
5559 pins = "gpio1 4787 pins = "gpio132";
5560 function = "g 4788 function = "gpio";
5561 }; 4789 };
5562 4790
5563 qup_spi10_data_clk: q 4791 qup_spi10_data_clk: qup-spi10-data-clk-state {
5564 pins = "gpio1 4792 pins = "gpio129", "gpio130",
5565 "gpio1 4793 "gpio131";
5566 function = "q 4794 function = "qup10";
5567 }; 4795 };
5568 4796
5569 qup_spi11_cs: qup-spi 4797 qup_spi11_cs: qup-spi11-cs-state {
5570 pins = "gpio6 4798 pins = "gpio63";
5571 function = "q 4799 function = "qup11";
5572 }; 4800 };
5573 4801
5574 qup_spi11_cs_gpio: qu 4802 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state {
5575 pins = "gpio6 4803 pins = "gpio63";
5576 function = "g 4804 function = "gpio";
5577 }; 4805 };
5578 4806
5579 qup_spi11_data_clk: q 4807 qup_spi11_data_clk: qup-spi11-data-clk-state {
5580 pins = "gpio6 4808 pins = "gpio60", "gpio61",
5581 "gpio6 4809 "gpio62";
5582 function = "q 4810 function = "qup11";
5583 }; 4811 };
5584 4812
5585 qup_spi12_cs: qup-spi 4813 qup_spi12_cs: qup-spi12-cs-state {
5586 pins = "gpio3 4814 pins = "gpio35";
5587 function = "q 4815 function = "qup12";
5588 }; 4816 };
5589 4817
5590 qup_spi12_cs_gpio: qu 4818 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state {
5591 pins = "gpio3 4819 pins = "gpio35";
5592 function = "g 4820 function = "gpio";
5593 }; 4821 };
5594 4822
5595 qup_spi12_data_clk: q 4823 qup_spi12_data_clk: qup-spi12-data-clk-state {
5596 pins = "gpio3 4824 pins = "gpio32", "gpio33",
5597 "gpio3 4825 "gpio34";
5598 function = "q 4826 function = "qup12";
5599 }; 4827 };
5600 4828
5601 qup_spi13_cs: qup-spi 4829 qup_spi13_cs: qup-spi13-cs-state {
5602 pins = "gpio3 4830 pins = "gpio39";
5603 function = "q 4831 function = "qup13";
5604 }; 4832 };
5605 4833
5606 qup_spi13_cs_gpio: qu 4834 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state {
5607 pins = "gpio3 4835 pins = "gpio39";
5608 function = "g 4836 function = "gpio";
5609 }; 4837 };
5610 4838
5611 qup_spi13_data_clk: q 4839 qup_spi13_data_clk: qup-spi13-data-clk-state {
5612 pins = "gpio3 4840 pins = "gpio36", "gpio37",
5613 "gpio3 4841 "gpio38";
5614 function = "q 4842 function = "qup13";
5615 }; 4843 };
5616 4844
5617 qup_spi14_cs: qup-spi 4845 qup_spi14_cs: qup-spi14-cs-state {
5618 pins = "gpio4 4846 pins = "gpio43";
5619 function = "q 4847 function = "qup14";
5620 }; 4848 };
5621 4849
5622 qup_spi14_cs_gpio: qu 4850 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state {
5623 pins = "gpio4 4851 pins = "gpio43";
5624 function = "g 4852 function = "gpio";
5625 }; 4853 };
5626 4854
5627 qup_spi14_data_clk: q 4855 qup_spi14_data_clk: qup-spi14-data-clk-state {
5628 pins = "gpio4 4856 pins = "gpio40", "gpio41",
5629 "gpio4 4857 "gpio42";
5630 function = "q 4858 function = "qup14";
5631 }; 4859 };
5632 4860
5633 qup_spi15_cs: qup-spi 4861 qup_spi15_cs: qup-spi15-cs-state {
5634 pins = "gpio4 4862 pins = "gpio47";
5635 function = "q 4863 function = "qup15";
5636 }; 4864 };
5637 4865
5638 qup_spi15_cs_gpio: qu 4866 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state {
5639 pins = "gpio4 4867 pins = "gpio47";
5640 function = "g 4868 function = "gpio";
5641 }; 4869 };
5642 4870
5643 qup_spi15_data_clk: q 4871 qup_spi15_data_clk: qup-spi15-data-clk-state {
5644 pins = "gpio4 4872 pins = "gpio44", "gpio45",
5645 "gpio4 4873 "gpio46";
5646 function = "q 4874 function = "qup15";
5647 }; 4875 };
5648 4876
5649 qup_spi16_cs: qup-spi 4877 qup_spi16_cs: qup-spi16-cs-state {
5650 pins = "gpio5 4878 pins = "gpio51";
5651 function = "q 4879 function = "qup16";
5652 }; 4880 };
5653 4881
5654 qup_spi16_cs_gpio: qu 4882 qup_spi16_cs_gpio: qup-spi16-cs-gpio-state {
5655 pins = "gpio5 4883 pins = "gpio51";
5656 function = "g 4884 function = "gpio";
5657 }; 4885 };
5658 4886
5659 qup_spi16_data_clk: q 4887 qup_spi16_data_clk: qup-spi16-data-clk-state {
5660 pins = "gpio4 4888 pins = "gpio48", "gpio49",
5661 "gpio5 4889 "gpio50";
5662 function = "q 4890 function = "qup16";
5663 }; 4891 };
5664 4892
5665 qup_spi17_cs: qup-spi 4893 qup_spi17_cs: qup-spi17-cs-state {
5666 pins = "gpio5 4894 pins = "gpio55";
5667 function = "q 4895 function = "qup17";
5668 }; 4896 };
5669 4897
5670 qup_spi17_cs_gpio: qu 4898 qup_spi17_cs_gpio: qup-spi17-cs-gpio-state {
5671 pins = "gpio5 4899 pins = "gpio55";
5672 function = "g 4900 function = "gpio";
5673 }; 4901 };
5674 4902
5675 qup_spi17_data_clk: q 4903 qup_spi17_data_clk: qup-spi17-data-clk-state {
5676 pins = "gpio5 4904 pins = "gpio52", "gpio53",
5677 "gpio5 4905 "gpio54";
5678 function = "q 4906 function = "qup17";
5679 }; 4907 };
5680 4908
5681 qup_spi18_cs: qup-spi 4909 qup_spi18_cs: qup-spi18-cs-state {
5682 pins = "gpio5 4910 pins = "gpio59";
5683 function = "q 4911 function = "qup18";
5684 }; 4912 };
5685 4913
5686 qup_spi18_cs_gpio: qu 4914 qup_spi18_cs_gpio: qup-spi18-cs-gpio-state {
5687 pins = "gpio5 4915 pins = "gpio59";
5688 function = "g 4916 function = "gpio";
5689 }; 4917 };
5690 4918
5691 qup_spi18_data_clk: q 4919 qup_spi18_data_clk: qup-spi18-data-clk-state {
5692 pins = "gpio5 4920 pins = "gpio56", "gpio57",
5693 "gpio5 4921 "gpio58";
5694 function = "q 4922 function = "qup18";
5695 }; 4923 };
5696 4924
5697 qup_spi19_cs: qup-spi 4925 qup_spi19_cs: qup-spi19-cs-state {
5698 pins = "gpio3 4926 pins = "gpio3";
5699 function = "q 4927 function = "qup19";
5700 }; 4928 };
5701 4929
5702 qup_spi19_cs_gpio: qu 4930 qup_spi19_cs_gpio: qup-spi19-cs-gpio-state {
5703 pins = "gpio3 4931 pins = "gpio3";
5704 function = "g 4932 function = "gpio";
5705 }; 4933 };
5706 4934
5707 qup_spi19_data_clk: q 4935 qup_spi19_data_clk: qup-spi19-data-clk-state {
5708 pins = "gpio0 4936 pins = "gpio0", "gpio1",
5709 "gpio2 4937 "gpio2";
5710 function = "q 4938 function = "qup19";
5711 }; 4939 };
5712 4940
5713 qup_uart2_default: qu 4941 qup_uart2_default: qup-uart2-default-state {
5714 pins = "gpio1 4942 pins = "gpio117", "gpio118";
5715 function = "q 4943 function = "qup2";
5716 }; 4944 };
5717 4945
5718 qup_uart6_default: qu 4946 qup_uart6_default: qup-uart6-default-state {
5719 pins = "gpio1 4947 pins = "gpio16", "gpio17", "gpio18", "gpio19";
5720 function = "q 4948 function = "qup6";
5721 }; 4949 };
5722 4950
5723 qup_uart12_default: q 4951 qup_uart12_default: qup-uart12-default-state {
5724 pins = "gpio3 4952 pins = "gpio34", "gpio35";
5725 function = "q 4953 function = "qup12";
5726 }; 4954 };
5727 4955
5728 qup_uart17_default: q 4956 qup_uart17_default: qup-uart17-default-state {
5729 pins = "gpio5 4957 pins = "gpio52", "gpio53", "gpio54", "gpio55";
5730 function = "q 4958 function = "qup17";
5731 }; 4959 };
5732 4960
5733 qup_uart18_default: q 4961 qup_uart18_default: qup-uart18-default-state {
5734 pins = "gpio5 4962 pins = "gpio58", "gpio59";
5735 function = "q 4963 function = "qup18";
5736 }; 4964 };
5737 4965
5738 tert_mi2s_active: ter 4966 tert_mi2s_active: tert-mi2s-active-state {
5739 sck-pins { 4967 sck-pins {
5740 pins 4968 pins = "gpio133";
5741 funct 4969 function = "mi2s2_sck";
5742 drive 4970 drive-strength = <8>;
5743 bias- 4971 bias-disable;
5744 }; 4972 };
5745 4973
5746 data0-pins { 4974 data0-pins {
5747 pins 4975 pins = "gpio134";
5748 funct 4976 function = "mi2s2_data0";
5749 drive 4977 drive-strength = <8>;
5750 bias- 4978 bias-disable;
5751 outpu 4979 output-high;
5752 }; 4980 };
5753 4981
5754 ws-pins { 4982 ws-pins {
5755 pins 4983 pins = "gpio135";
5756 funct 4984 function = "mi2s2_ws";
5757 drive 4985 drive-strength = <8>;
5758 outpu 4986 output-high;
5759 }; 4987 };
5760 }; 4988 };
5761 4989
5762 sdc2_sleep_state: sdc 4990 sdc2_sleep_state: sdc2-sleep-state {
5763 clk-pins { 4991 clk-pins {
5764 pins 4992 pins = "sdc2_clk";
5765 drive 4993 drive-strength = <2>;
5766 bias- 4994 bias-disable;
5767 }; 4995 };
5768 4996
5769 cmd-pins { 4997 cmd-pins {
5770 pins 4998 pins = "sdc2_cmd";
5771 drive 4999 drive-strength = <2>;
5772 bias- 5000 bias-pull-up;
5773 }; 5001 };
5774 5002
5775 data-pins { 5003 data-pins {
5776 pins 5004 pins = "sdc2_data";
5777 drive 5005 drive-strength = <2>;
5778 bias- 5006 bias-pull-up;
5779 }; 5007 };
5780 }; 5008 };
5781 5009
5782 pcie0_default_state: 5010 pcie0_default_state: pcie0-default-state {
5783 perst-pins { 5011 perst-pins {
5784 pins 5012 pins = "gpio79";
5785 funct 5013 function = "gpio";
5786 drive 5014 drive-strength = <2>;
5787 bias- 5015 bias-pull-down;
5788 }; 5016 };
5789 5017
5790 clkreq-pins { 5018 clkreq-pins {
5791 pins 5019 pins = "gpio80";
5792 funct 5020 function = "pci_e0";
5793 drive 5021 drive-strength = <2>;
5794 bias- 5022 bias-pull-up;
5795 }; 5023 };
5796 5024
5797 wake-pins { 5025 wake-pins {
5798 pins 5026 pins = "gpio81";
5799 funct 5027 function = "gpio";
5800 drive 5028 drive-strength = <2>;
5801 bias- 5029 bias-pull-up;
5802 }; 5030 };
5803 }; 5031 };
5804 5032
5805 pcie1_default_state: 5033 pcie1_default_state: pcie1-default-state {
5806 perst-pins { 5034 perst-pins {
5807 pins 5035 pins = "gpio82";
5808 funct 5036 function = "gpio";
5809 drive 5037 drive-strength = <2>;
5810 bias- 5038 bias-pull-down;
5811 }; 5039 };
5812 5040
5813 clkreq-pins { 5041 clkreq-pins {
5814 pins 5042 pins = "gpio83";
5815 funct 5043 function = "pci_e1";
5816 drive 5044 drive-strength = <2>;
5817 bias- 5045 bias-pull-up;
5818 }; 5046 };
5819 5047
5820 wake-pins { 5048 wake-pins {
5821 pins 5049 pins = "gpio84";
5822 funct 5050 function = "gpio";
5823 drive 5051 drive-strength = <2>;
5824 bias- 5052 bias-pull-up;
5825 }; 5053 };
5826 }; 5054 };
5827 5055
5828 pcie2_default_state: 5056 pcie2_default_state: pcie2-default-state {
5829 perst-pins { 5057 perst-pins {
5830 pins 5058 pins = "gpio85";
5831 funct 5059 function = "gpio";
5832 drive 5060 drive-strength = <2>;
5833 bias- 5061 bias-pull-down;
5834 }; 5062 };
5835 5063
5836 clkreq-pins { 5064 clkreq-pins {
5837 pins 5065 pins = "gpio86";
5838 funct 5066 function = "pci_e2";
5839 drive 5067 drive-strength = <2>;
5840 bias- 5068 bias-pull-up;
5841 }; 5069 };
5842 5070
5843 wake-pins { 5071 wake-pins {
5844 pins 5072 pins = "gpio87";
5845 funct 5073 function = "gpio";
5846 drive 5074 drive-strength = <2>;
5847 bias- 5075 bias-pull-up;
5848 }; 5076 };
5849 }; 5077 };
5850 }; 5078 };
5851 5079
5852 apps_smmu: iommu@15000000 { 5080 apps_smmu: iommu@15000000 {
5853 compatible = "qcom,sm !! 5081 compatible = "qcom,sm8250-smmu-500", "arm,mmu-500";
5854 reg = <0 0x15000000 0 5082 reg = <0 0x15000000 0 0x100000>;
5855 #iommu-cells = <2>; 5083 #iommu-cells = <2>;
5856 #global-interrupts = 5084 #global-interrupts = <2>;
5857 interrupts = <GIC_SPI !! 5085 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
5858 <GIC_SPI !! 5086 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
5859 <GIC_SPI !! 5087 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
5860 <GIC_SPI !! 5088 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
5861 <GIC_SPI !! 5089 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
5862 <GIC_SPI !! 5090 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
5863 <GIC_SPI !! 5091 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
5864 <GIC_SPI !! 5092 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
5865 <GIC_SPI !! 5093 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
5866 <GIC_SPI !! 5094 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
5867 <GIC_SPI !! 5095 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
5868 <GIC_SPI !! 5096 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
5869 <GIC_SPI !! 5097 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
5870 <GIC_SPI !! 5098 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
5871 <GIC_SPI !! 5099 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
5872 <GIC_SPI !! 5100 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
5873 <GIC_SPI !! 5101 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
5874 <GIC_SPI !! 5102 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
5875 <GIC_SPI !! 5103 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
5876 <GIC_SPI !! 5104 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
5877 <GIC_SPI !! 5105 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
5878 <GIC_SPI !! 5106 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
5879 <GIC_SPI !! 5107 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
5880 <GIC_SPI !! 5108 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
5881 <GIC_SPI !! 5109 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
5882 <GIC_SPI !! 5110 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
5883 <GIC_SPI !! 5111 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
5884 <GIC_SPI !! 5112 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
5885 <GIC_SPI !! 5113 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
5886 <GIC_SPI !! 5114 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
5887 <GIC_SPI !! 5115 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
5888 <GIC_SPI !! 5116 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
5889 <GIC_SPI !! 5117 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
5890 <GIC_SPI !! 5118 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
5891 <GIC_SPI !! 5119 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
5892 <GIC_SPI !! 5120 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
5893 <GIC_SPI !! 5121 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
5894 <GIC_SPI !! 5122 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
5895 <GIC_SPI !! 5123 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
5896 <GIC_SPI !! 5124 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
5897 <GIC_SPI !! 5125 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
5898 <GIC_SPI !! 5126 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
5899 <GIC_SPI !! 5127 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
5900 <GIC_SPI !! 5128 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
5901 <GIC_SPI !! 5129 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
5902 <GIC_SPI !! 5130 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
5903 <GIC_SPI !! 5131 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
5904 <GIC_SPI !! 5132 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
5905 <GIC_SPI !! 5133 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
5906 <GIC_SPI !! 5134 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
5907 <GIC_SPI !! 5135 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
5908 <GIC_SPI !! 5136 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
5909 <GIC_SPI !! 5137 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
5910 <GIC_SPI !! 5138 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
5911 <GIC_SPI !! 5139 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
5912 <GIC_SPI !! 5140 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
5913 <GIC_SPI !! 5141 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
5914 <GIC_SPI !! 5142 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
5915 <GIC_SPI !! 5143 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
5916 <GIC_SPI !! 5144 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
5917 <GIC_SPI !! 5145 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
5918 <GIC_SPI !! 5146 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
5919 <GIC_SPI !! 5147 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
5920 <GIC_SPI !! 5148 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
5921 <GIC_SPI !! 5149 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
5922 <GIC_SPI !! 5150 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
5923 <GIC_SPI !! 5151 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
5924 <GIC_SPI !! 5152 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
5925 <GIC_SPI !! 5153 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
5926 <GIC_SPI !! 5154 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
5927 <GIC_SPI !! 5155 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
5928 <GIC_SPI !! 5156 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
5929 <GIC_SPI !! 5157 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
5930 <GIC_SPI !! 5158 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
5931 <GIC_SPI !! 5159 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
5932 <GIC_SPI !! 5160 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
5933 <GIC_SPI !! 5161 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
5934 <GIC_SPI !! 5162 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
5935 <GIC_SPI !! 5163 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
5936 <GIC_SPI !! 5164 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
5937 <GIC_SPI !! 5165 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
5938 <GIC_SPI !! 5166 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
5939 <GIC_SPI !! 5167 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
5940 <GIC_SPI !! 5168 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
5941 <GIC_SPI !! 5169 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
5942 <GIC_SPI !! 5170 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
5943 <GIC_SPI !! 5171 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
5944 <GIC_SPI !! 5172 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
5945 <GIC_SPI !! 5173 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
5946 <GIC_SPI !! 5174 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
5947 <GIC_SPI !! 5175 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
5948 <GIC_SPI !! 5176 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
5949 <GIC_SPI !! 5177 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
5950 <GIC_SPI !! 5178 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
5951 <GIC_SPI !! 5179 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
5952 <GIC_SPI !! 5180 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
5953 <GIC_SPI !! 5181 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
5954 <GIC_SPI !! 5182 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>;
5955 dma-coherent; <<
5956 }; 5183 };
5957 5184
5958 adsp: remoteproc@17300000 { 5185 adsp: remoteproc@17300000 {
5959 compatible = "qcom,sm 5186 compatible = "qcom,sm8250-adsp-pas";
5960 reg = <0 0x17300000 0 5187 reg = <0 0x17300000 0 0x100>;
5961 5188
5962 interrupts-extended = !! 5189 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
5963 5190 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
5964 5191 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
5965 5192 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
5966 5193 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
5967 interrupt-names = "wd 5194 interrupt-names = "wdog", "fatal", "ready",
5968 "ha 5195 "handover", "stop-ack";
5969 5196
5970 clocks = <&rpmhcc RPM 5197 clocks = <&rpmhcc RPMH_CXO_CLK>;
5971 clock-names = "xo"; 5198 clock-names = "xo";
5972 5199
5973 power-domains = <&rpm !! 5200 power-domains = <&rpmhpd SM8250_LCX>,
5974 <&rpm !! 5201 <&rpmhpd SM8250_LMX>;
5975 power-domain-names = 5202 power-domain-names = "lcx", "lmx";
5976 5203
5977 memory-region = <&ads 5204 memory-region = <&adsp_mem>;
5978 5205
5979 qcom,qmp = <&aoss_qmp 5206 qcom,qmp = <&aoss_qmp>;
5980 5207
5981 qcom,smem-states = <& 5208 qcom,smem-states = <&smp2p_adsp_out 0>;
5982 qcom,smem-state-names 5209 qcom,smem-state-names = "stop";
5983 5210
5984 status = "disabled"; 5211 status = "disabled";
5985 5212
5986 glink-edge { 5213 glink-edge {
5987 interrupts-ex 5214 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
5988 5215 IPCC_MPROC_SIGNAL_GLINK_QMP
5989 5216 IRQ_TYPE_EDGE_RISING>;
5990 mboxes = <&ip 5217 mboxes = <&ipcc IPCC_CLIENT_LPASS
5991 5218 IPCC_MPROC_SIGNAL_GLINK_QMP>;
5992 5219
5993 label = "lpas 5220 label = "lpass";
5994 qcom,remote-p 5221 qcom,remote-pid = <2>;
5995 5222
5996 apr { 5223 apr {
5997 compa 5224 compatible = "qcom,apr-v2";
5998 qcom, 5225 qcom,glink-channels = "apr_audio_svc";
5999 qcom, 5226 qcom,domain = <APR_DOMAIN_ADSP>;
6000 #addr 5227 #address-cells = <1>;
6001 #size 5228 #size-cells = <0>;
6002 5229
6003 servi 5230 service@3 {
6004 5231 reg = <APR_SVC_ADSP_CORE>;
6005 5232 compatible = "qcom,q6core";
6006 5233 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6007 }; 5234 };
6008 5235
6009 q6afe 5236 q6afe: service@4 {
6010 5237 compatible = "qcom,q6afe";
6011 5238 reg = <APR_SVC_AFE>;
6012 5239 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6013 5240 q6afedai: dais {
6014 5241 compatible = "qcom,q6afe-dais";
6015 5242 #address-cells = <1>;
6016 5243 #size-cells = <0>;
6017 5244 #sound-dai-cells = <1>;
6018 5245 };
6019 5246
6020 5247 q6afecc: clock-controller {
6021 5248 compatible = "qcom,q6afe-clocks";
6022 5249 #clock-cells = <2>;
6023 5250 };
6024 }; 5251 };
6025 5252
6026 q6asm 5253 q6asm: service@7 {
6027 5254 compatible = "qcom,q6asm";
6028 5255 reg = <APR_SVC_ASM>;
6029 5256 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6030 5257 q6asmdai: dais {
6031 5258 compatible = "qcom,q6asm-dais";
6032 5259 #address-cells = <1>;
6033 5260 #size-cells = <0>;
6034 5261 #sound-dai-cells = <1>;
6035 5262 iommus = <&apps_smmu 0x1801 0x0>;
6036 5263 };
6037 }; 5264 };
6038 5265
6039 q6adm 5266 q6adm: service@8 {
6040 5267 compatible = "qcom,q6adm";
6041 5268 reg = <APR_SVC_ADM>;
6042 5269 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6043 5270 q6routing: routing {
6044 5271 compatible = "qcom,q6adm-routing";
6045 5272 #sound-dai-cells = <0>;
6046 5273 };
6047 }; 5274 };
6048 }; 5275 };
6049 5276
6050 fastrpc { 5277 fastrpc {
6051 compa 5278 compatible = "qcom,fastrpc";
6052 qcom, 5279 qcom,glink-channels = "fastrpcglink-apps-dsp";
6053 label 5280 label = "adsp";
6054 qcom, 5281 qcom,non-secure-domain;
6055 #addr 5282 #address-cells = <1>;
6056 #size 5283 #size-cells = <0>;
6057 5284
6058 compu 5285 compute-cb@3 {
6059 5286 compatible = "qcom,fastrpc-compute-cb";
6060 5287 reg = <3>;
6061 5288 iommus = <&apps_smmu 0x1803 0x0>;
6062 }; 5289 };
6063 5290
6064 compu 5291 compute-cb@4 {
6065 5292 compatible = "qcom,fastrpc-compute-cb";
6066 5293 reg = <4>;
6067 5294 iommus = <&apps_smmu 0x1804 0x0>;
6068 }; 5295 };
6069 5296
6070 compu 5297 compute-cb@5 {
6071 5298 compatible = "qcom,fastrpc-compute-cb";
6072 5299 reg = <5>;
6073 5300 iommus = <&apps_smmu 0x1805 0x0>;
6074 }; 5301 };
6075 }; 5302 };
6076 }; 5303 };
6077 }; 5304 };
6078 5305
6079 intc: interrupt-controller@17 5306 intc: interrupt-controller@17a00000 {
6080 compatible = "arm,gic 5307 compatible = "arm,gic-v3";
6081 #interrupt-cells = <3 5308 #interrupt-cells = <3>;
6082 interrupt-controller; 5309 interrupt-controller;
6083 reg = <0x0 0x17a00000 5310 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
6084 <0x0 0x17a60000 5311 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
6085 interrupts = <GIC_PPI 5312 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
6086 }; 5313 };
6087 5314
6088 watchdog@17c10000 { 5315 watchdog@17c10000 {
6089 compatible = "qcom,ap 5316 compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt";
6090 reg = <0 0x17c10000 0 5317 reg = <0 0x17c10000 0 0x1000>;
6091 clocks = <&sleep_clk> 5318 clocks = <&sleep_clk>;
6092 interrupts = <GIC_SPI !! 5319 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
6093 }; 5320 };
6094 5321
6095 timer@17c20000 { 5322 timer@17c20000 {
6096 #address-cells = <1>; 5323 #address-cells = <1>;
6097 #size-cells = <1>; 5324 #size-cells = <1>;
6098 ranges = <0 0 0 0x200 5325 ranges = <0 0 0 0x20000000>;
6099 compatible = "arm,arm 5326 compatible = "arm,armv7-timer-mem";
6100 reg = <0x0 0x17c20000 5327 reg = <0x0 0x17c20000 0x0 0x1000>;
6101 clock-frequency = <19 5328 clock-frequency = <19200000>;
6102 5329
6103 frame@17c21000 { 5330 frame@17c21000 {
6104 frame-number 5331 frame-number = <0>;
6105 interrupts = 5332 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
6106 5333 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
6107 reg = <0x17c2 5334 reg = <0x17c21000 0x1000>,
6108 <0x17c2 5335 <0x17c22000 0x1000>;
6109 }; 5336 };
6110 5337
6111 frame@17c23000 { 5338 frame@17c23000 {
6112 frame-number 5339 frame-number = <1>;
6113 interrupts = 5340 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
6114 reg = <0x17c2 5341 reg = <0x17c23000 0x1000>;
6115 status = "dis 5342 status = "disabled";
6116 }; 5343 };
6117 5344
6118 frame@17c25000 { 5345 frame@17c25000 {
6119 frame-number 5346 frame-number = <2>;
6120 interrupts = 5347 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
6121 reg = <0x17c2 5348 reg = <0x17c25000 0x1000>;
6122 status = "dis 5349 status = "disabled";
6123 }; 5350 };
6124 5351
6125 frame@17c27000 { 5352 frame@17c27000 {
6126 frame-number 5353 frame-number = <3>;
6127 interrupts = 5354 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
6128 reg = <0x17c2 5355 reg = <0x17c27000 0x1000>;
6129 status = "dis 5356 status = "disabled";
6130 }; 5357 };
6131 5358
6132 frame@17c29000 { 5359 frame@17c29000 {
6133 frame-number 5360 frame-number = <4>;
6134 interrupts = 5361 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
6135 reg = <0x17c2 5362 reg = <0x17c29000 0x1000>;
6136 status = "dis 5363 status = "disabled";
6137 }; 5364 };
6138 5365
6139 frame@17c2b000 { 5366 frame@17c2b000 {
6140 frame-number 5367 frame-number = <5>;
6141 interrupts = 5368 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
6142 reg = <0x17c2 5369 reg = <0x17c2b000 0x1000>;
6143 status = "dis 5370 status = "disabled";
6144 }; 5371 };
6145 5372
6146 frame@17c2d000 { 5373 frame@17c2d000 {
6147 frame-number 5374 frame-number = <6>;
6148 interrupts = 5375 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
6149 reg = <0x17c2 5376 reg = <0x17c2d000 0x1000>;
6150 status = "dis 5377 status = "disabled";
6151 }; 5378 };
6152 }; 5379 };
6153 5380
6154 apps_rsc: rsc@18200000 { 5381 apps_rsc: rsc@18200000 {
6155 label = "apps_rsc"; 5382 label = "apps_rsc";
6156 compatible = "qcom,rp 5383 compatible = "qcom,rpmh-rsc";
6157 reg = <0x0 0x18200000 5384 reg = <0x0 0x18200000 0x0 0x10000>,
6158 <0x0 0x182100 5385 <0x0 0x18210000 0x0 0x10000>,
6159 <0x0 0x182200 5386 <0x0 0x18220000 0x0 0x10000>;
6160 reg-names = "drv-0", 5387 reg-names = "drv-0", "drv-1", "drv-2";
6161 interrupts = <GIC_SPI 5388 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
6162 <GIC_SPI 5389 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
6163 <GIC_SPI 5390 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
6164 qcom,tcs-offset = <0x 5391 qcom,tcs-offset = <0xd00>;
6165 qcom,drv-id = <2>; 5392 qcom,drv-id = <2>;
6166 qcom,tcs-config = <AC 5393 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
6167 <WA 5394 <WAKE_TCS 3>, <CONTROL_TCS 1>;
6168 power-domains = <&CLU 5395 power-domains = <&CLUSTER_PD>;
6169 5396
6170 rpmhcc: clock-control 5397 rpmhcc: clock-controller {
6171 compatible = 5398 compatible = "qcom,sm8250-rpmh-clk";
6172 #clock-cells 5399 #clock-cells = <1>;
6173 clock-names = 5400 clock-names = "xo";
6174 clocks = <&xo 5401 clocks = <&xo_board>;
6175 }; 5402 };
6176 5403
6177 rpmhpd: power-control 5404 rpmhpd: power-controller {
6178 compatible = 5405 compatible = "qcom,sm8250-rpmhpd";
6179 #power-domain 5406 #power-domain-cells = <1>;
6180 operating-poi 5407 operating-points-v2 = <&rpmhpd_opp_table>;
6181 5408
6182 rpmhpd_opp_ta 5409 rpmhpd_opp_table: opp-table {
6183 compa 5410 compatible = "operating-points-v2";
6184 5411
6185 rpmhp 5412 rpmhpd_opp_ret: opp1 {
6186 5413 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
6187 }; 5414 };
6188 5415
6189 rpmhp 5416 rpmhpd_opp_min_svs: opp2 {
6190 5417 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
6191 }; 5418 };
6192 5419
6193 rpmhp 5420 rpmhpd_opp_low_svs: opp3 {
6194 5421 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
6195 }; 5422 };
6196 5423
6197 rpmhp 5424 rpmhpd_opp_svs: opp4 {
6198 5425 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
6199 }; 5426 };
6200 5427
6201 rpmhp 5428 rpmhpd_opp_svs_l1: opp5 {
6202 5429 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
6203 }; 5430 };
6204 5431
6205 rpmhp 5432 rpmhpd_opp_nom: opp6 {
6206 5433 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
6207 }; 5434 };
6208 5435
6209 rpmhp 5436 rpmhpd_opp_nom_l1: opp7 {
6210 5437 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
6211 }; 5438 };
6212 5439
6213 rpmhp 5440 rpmhpd_opp_nom_l2: opp8 {
6214 5441 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
6215 }; 5442 };
6216 5443
6217 rpmhp 5444 rpmhpd_opp_turbo: opp9 {
6218 5445 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
6219 }; 5446 };
6220 5447
6221 rpmhp 5448 rpmhpd_opp_turbo_l1: opp10 {
6222 5449 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
6223 }; 5450 };
6224 }; 5451 };
6225 }; 5452 };
6226 5453
6227 apps_bcm_voter: bcm-v 5454 apps_bcm_voter: bcm-voter {
6228 compatible = 5455 compatible = "qcom,bcm-voter";
6229 }; 5456 };
6230 }; 5457 };
6231 5458
6232 epss_l3: interconnect@1859000 5459 epss_l3: interconnect@18590000 {
6233 compatible = "qcom,sm 5460 compatible = "qcom,sm8250-epss-l3", "qcom,epss-l3";
6234 reg = <0 0x18590000 0 5461 reg = <0 0x18590000 0 0x1000>;
6235 5462
6236 clocks = <&rpmhcc RPM 5463 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
6237 clock-names = "xo", " 5464 clock-names = "xo", "alternate";
6238 5465
6239 #interconnect-cells = 5466 #interconnect-cells = <1>;
6240 }; 5467 };
6241 5468
6242 cpufreq_hw: cpufreq@18591000 5469 cpufreq_hw: cpufreq@18591000 {
6243 compatible = "qcom,sm 5470 compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss";
6244 reg = <0 0x18591000 0 5471 reg = <0 0x18591000 0 0x1000>,
6245 <0 0x18592000 0 5472 <0 0x18592000 0 0x1000>,
6246 <0 0x18593000 0 5473 <0 0x18593000 0 0x1000>;
6247 reg-names = "freq-dom 5474 reg-names = "freq-domain0", "freq-domain1",
6248 "freq-dom 5475 "freq-domain2";
6249 5476
6250 clocks = <&rpmhcc RPM 5477 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
6251 clock-names = "xo", " 5478 clock-names = "xo", "alternate";
6252 interrupts = <GIC_SPI 5479 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
6253 <GIC_SPI 5480 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
6254 <GIC_SPI 5481 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
6255 interrupt-names = "dc 5482 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
6256 #freq-domain-cells = 5483 #freq-domain-cells = <1>;
6257 #clock-cells = <1>; <<
6258 }; 5484 };
6259 }; 5485 };
6260 5486
6261 sound: sound { 5487 sound: sound {
6262 }; 5488 };
6263 5489
6264 timer { 5490 timer {
6265 compatible = "arm,armv8-timer 5491 compatible = "arm,armv8-timer";
6266 interrupts = <GIC_PPI 13 5492 interrupts = <GIC_PPI 13
6267 (GIC_CPU_MASK 5493 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6268 <GIC_PPI 14 5494 <GIC_PPI 14
6269 (GIC_CPU_MASK 5495 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6270 <GIC_PPI 11 5496 <GIC_PPI 11
6271 (GIC_CPU_MASK 5497 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6272 <GIC_PPI 10 5498 <GIC_PPI 10
6273 (GIC_CPU_MASK 5499 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
6274 }; 5500 };
6275 5501
6276 thermal-zones { 5502 thermal-zones {
6277 cpu0-thermal { 5503 cpu0-thermal {
6278 polling-delay-passive 5504 polling-delay-passive = <250>;
>> 5505 polling-delay = <1000>;
6279 5506
6280 thermal-sensors = <&t 5507 thermal-sensors = <&tsens0 1>;
6281 5508
6282 trips { 5509 trips {
6283 cpu0_alert0: 5510 cpu0_alert0: trip-point0 {
6284 tempe 5511 temperature = <90000>;
6285 hyste 5512 hysteresis = <2000>;
6286 type 5513 type = "passive";
6287 }; 5514 };
6288 5515
6289 cpu0_alert1: 5516 cpu0_alert1: trip-point1 {
6290 tempe 5517 temperature = <95000>;
6291 hyste 5518 hysteresis = <2000>;
6292 type 5519 type = "passive";
6293 }; 5520 };
6294 5521
6295 cpu0_crit: cp 5522 cpu0_crit: cpu-crit {
6296 tempe 5523 temperature = <110000>;
6297 hyste 5524 hysteresis = <1000>;
6298 type 5525 type = "critical";
6299 }; 5526 };
6300 }; 5527 };
6301 5528
6302 cooling-maps { 5529 cooling-maps {
6303 map0 { 5530 map0 {
6304 trip 5531 trip = <&cpu0_alert0>;
6305 cooli 5532 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6306 5533 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6307 5534 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6308 5535 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6309 }; 5536 };
6310 map1 { 5537 map1 {
6311 trip 5538 trip = <&cpu0_alert1>;
6312 cooli 5539 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6313 5540 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6314 5541 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6315 5542 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6316 }; 5543 };
6317 }; 5544 };
6318 }; 5545 };
6319 5546
6320 cpu1-thermal { 5547 cpu1-thermal {
6321 polling-delay-passive 5548 polling-delay-passive = <250>;
>> 5549 polling-delay = <1000>;
6322 5550
6323 thermal-sensors = <&t 5551 thermal-sensors = <&tsens0 2>;
6324 5552
6325 trips { 5553 trips {
6326 cpu1_alert0: 5554 cpu1_alert0: trip-point0 {
6327 tempe 5555 temperature = <90000>;
6328 hyste 5556 hysteresis = <2000>;
6329 type 5557 type = "passive";
6330 }; 5558 };
6331 5559
6332 cpu1_alert1: 5560 cpu1_alert1: trip-point1 {
6333 tempe 5561 temperature = <95000>;
6334 hyste 5562 hysteresis = <2000>;
6335 type 5563 type = "passive";
6336 }; 5564 };
6337 5565
6338 cpu1_crit: cp 5566 cpu1_crit: cpu-crit {
6339 tempe 5567 temperature = <110000>;
6340 hyste 5568 hysteresis = <1000>;
6341 type 5569 type = "critical";
6342 }; 5570 };
6343 }; 5571 };
6344 5572
6345 cooling-maps { 5573 cooling-maps {
6346 map0 { 5574 map0 {
6347 trip 5575 trip = <&cpu1_alert0>;
6348 cooli 5576 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6349 5577 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6350 5578 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6351 5579 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6352 }; 5580 };
6353 map1 { 5581 map1 {
6354 trip 5582 trip = <&cpu1_alert1>;
6355 cooli 5583 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6356 5584 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6357 5585 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6358 5586 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6359 }; 5587 };
6360 }; 5588 };
6361 }; 5589 };
6362 5590
6363 cpu2-thermal { 5591 cpu2-thermal {
6364 polling-delay-passive 5592 polling-delay-passive = <250>;
>> 5593 polling-delay = <1000>;
6365 5594
6366 thermal-sensors = <&t 5595 thermal-sensors = <&tsens0 3>;
6367 5596
6368 trips { 5597 trips {
6369 cpu2_alert0: 5598 cpu2_alert0: trip-point0 {
6370 tempe 5599 temperature = <90000>;
6371 hyste 5600 hysteresis = <2000>;
6372 type 5601 type = "passive";
6373 }; 5602 };
6374 5603
6375 cpu2_alert1: 5604 cpu2_alert1: trip-point1 {
6376 tempe 5605 temperature = <95000>;
6377 hyste 5606 hysteresis = <2000>;
6378 type 5607 type = "passive";
6379 }; 5608 };
6380 5609
6381 cpu2_crit: cp 5610 cpu2_crit: cpu-crit {
6382 tempe 5611 temperature = <110000>;
6383 hyste 5612 hysteresis = <1000>;
6384 type 5613 type = "critical";
6385 }; 5614 };
6386 }; 5615 };
6387 5616
6388 cooling-maps { 5617 cooling-maps {
6389 map0 { 5618 map0 {
6390 trip 5619 trip = <&cpu2_alert0>;
6391 cooli 5620 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6392 5621 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6393 5622 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6394 5623 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6395 }; 5624 };
6396 map1 { 5625 map1 {
6397 trip 5626 trip = <&cpu2_alert1>;
6398 cooli 5627 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6399 5628 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6400 5629 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6401 5630 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6402 }; 5631 };
6403 }; 5632 };
6404 }; 5633 };
6405 5634
6406 cpu3-thermal { 5635 cpu3-thermal {
6407 polling-delay-passive 5636 polling-delay-passive = <250>;
>> 5637 polling-delay = <1000>;
6408 5638
6409 thermal-sensors = <&t 5639 thermal-sensors = <&tsens0 4>;
6410 5640
6411 trips { 5641 trips {
6412 cpu3_alert0: 5642 cpu3_alert0: trip-point0 {
6413 tempe 5643 temperature = <90000>;
6414 hyste 5644 hysteresis = <2000>;
6415 type 5645 type = "passive";
6416 }; 5646 };
6417 5647
6418 cpu3_alert1: 5648 cpu3_alert1: trip-point1 {
6419 tempe 5649 temperature = <95000>;
6420 hyste 5650 hysteresis = <2000>;
6421 type 5651 type = "passive";
6422 }; 5652 };
6423 5653
6424 cpu3_crit: cp 5654 cpu3_crit: cpu-crit {
6425 tempe 5655 temperature = <110000>;
6426 hyste 5656 hysteresis = <1000>;
6427 type 5657 type = "critical";
6428 }; 5658 };
6429 }; 5659 };
6430 5660
6431 cooling-maps { 5661 cooling-maps {
6432 map0 { 5662 map0 {
6433 trip 5663 trip = <&cpu3_alert0>;
6434 cooli 5664 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6435 5665 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6436 5666 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6437 5667 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6438 }; 5668 };
6439 map1 { 5669 map1 {
6440 trip 5670 trip = <&cpu3_alert1>;
6441 cooli 5671 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6442 5672 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6443 5673 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6444 5674 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6445 }; 5675 };
6446 }; 5676 };
6447 }; 5677 };
6448 5678
6449 cpu4-top-thermal { 5679 cpu4-top-thermal {
6450 polling-delay-passive 5680 polling-delay-passive = <250>;
>> 5681 polling-delay = <1000>;
6451 5682
6452 thermal-sensors = <&t 5683 thermal-sensors = <&tsens0 7>;
6453 5684
6454 trips { 5685 trips {
6455 cpu4_top_aler 5686 cpu4_top_alert0: trip-point0 {
6456 tempe 5687 temperature = <90000>;
6457 hyste 5688 hysteresis = <2000>;
6458 type 5689 type = "passive";
6459 }; 5690 };
6460 5691
6461 cpu4_top_aler 5692 cpu4_top_alert1: trip-point1 {
6462 tempe 5693 temperature = <95000>;
6463 hyste 5694 hysteresis = <2000>;
6464 type 5695 type = "passive";
6465 }; 5696 };
6466 5697
6467 cpu4_top_crit 5698 cpu4_top_crit: cpu-crit {
6468 tempe 5699 temperature = <110000>;
6469 hyste 5700 hysteresis = <1000>;
6470 type 5701 type = "critical";
6471 }; 5702 };
6472 }; 5703 };
6473 5704
6474 cooling-maps { 5705 cooling-maps {
6475 map0 { 5706 map0 {
6476 trip 5707 trip = <&cpu4_top_alert0>;
6477 cooli 5708 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6478 5709 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6479 5710 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6480 5711 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6481 }; 5712 };
6482 map1 { 5713 map1 {
6483 trip 5714 trip = <&cpu4_top_alert1>;
6484 cooli 5715 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6485 5716 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6486 5717 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6487 5718 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6488 }; 5719 };
6489 }; 5720 };
6490 }; 5721 };
6491 5722
6492 cpu5-top-thermal { 5723 cpu5-top-thermal {
6493 polling-delay-passive 5724 polling-delay-passive = <250>;
>> 5725 polling-delay = <1000>;
6494 5726
6495 thermal-sensors = <&t 5727 thermal-sensors = <&tsens0 8>;
6496 5728
6497 trips { 5729 trips {
6498 cpu5_top_aler 5730 cpu5_top_alert0: trip-point0 {
6499 tempe 5731 temperature = <90000>;
6500 hyste 5732 hysteresis = <2000>;
6501 type 5733 type = "passive";
6502 }; 5734 };
6503 5735
6504 cpu5_top_aler 5736 cpu5_top_alert1: trip-point1 {
6505 tempe 5737 temperature = <95000>;
6506 hyste 5738 hysteresis = <2000>;
6507 type 5739 type = "passive";
6508 }; 5740 };
6509 5741
6510 cpu5_top_crit 5742 cpu5_top_crit: cpu-crit {
6511 tempe 5743 temperature = <110000>;
6512 hyste 5744 hysteresis = <1000>;
6513 type 5745 type = "critical";
6514 }; 5746 };
6515 }; 5747 };
6516 5748
6517 cooling-maps { 5749 cooling-maps {
6518 map0 { 5750 map0 {
6519 trip 5751 trip = <&cpu5_top_alert0>;
6520 cooli 5752 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6521 5753 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6522 5754 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6523 5755 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6524 }; 5756 };
6525 map1 { 5757 map1 {
6526 trip 5758 trip = <&cpu5_top_alert1>;
6527 cooli 5759 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6528 5760 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6529 5761 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6530 5762 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6531 }; 5763 };
6532 }; 5764 };
6533 }; 5765 };
6534 5766
6535 cpu6-top-thermal { 5767 cpu6-top-thermal {
6536 polling-delay-passive 5768 polling-delay-passive = <250>;
>> 5769 polling-delay = <1000>;
6537 5770
6538 thermal-sensors = <&t 5771 thermal-sensors = <&tsens0 9>;
6539 5772
6540 trips { 5773 trips {
6541 cpu6_top_aler 5774 cpu6_top_alert0: trip-point0 {
6542 tempe 5775 temperature = <90000>;
6543 hyste 5776 hysteresis = <2000>;
6544 type 5777 type = "passive";
6545 }; 5778 };
6546 5779
6547 cpu6_top_aler 5780 cpu6_top_alert1: trip-point1 {
6548 tempe 5781 temperature = <95000>;
6549 hyste 5782 hysteresis = <2000>;
6550 type 5783 type = "passive";
6551 }; 5784 };
6552 5785
6553 cpu6_top_crit 5786 cpu6_top_crit: cpu-crit {
6554 tempe 5787 temperature = <110000>;
6555 hyste 5788 hysteresis = <1000>;
6556 type 5789 type = "critical";
6557 }; 5790 };
6558 }; 5791 };
6559 5792
6560 cooling-maps { 5793 cooling-maps {
6561 map0 { 5794 map0 {
6562 trip 5795 trip = <&cpu6_top_alert0>;
6563 cooli 5796 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6564 5797 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6565 5798 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6566 5799 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6567 }; 5800 };
6568 map1 { 5801 map1 {
6569 trip 5802 trip = <&cpu6_top_alert1>;
6570 cooli 5803 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6571 5804 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6572 5805 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6573 5806 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6574 }; 5807 };
6575 }; 5808 };
6576 }; 5809 };
6577 5810
6578 cpu7-top-thermal { 5811 cpu7-top-thermal {
6579 polling-delay-passive 5812 polling-delay-passive = <250>;
>> 5813 polling-delay = <1000>;
6580 5814
6581 thermal-sensors = <&t 5815 thermal-sensors = <&tsens0 10>;
6582 5816
6583 trips { 5817 trips {
6584 cpu7_top_aler 5818 cpu7_top_alert0: trip-point0 {
6585 tempe 5819 temperature = <90000>;
6586 hyste 5820 hysteresis = <2000>;
6587 type 5821 type = "passive";
6588 }; 5822 };
6589 5823
6590 cpu7_top_aler 5824 cpu7_top_alert1: trip-point1 {
6591 tempe 5825 temperature = <95000>;
6592 hyste 5826 hysteresis = <2000>;
6593 type 5827 type = "passive";
6594 }; 5828 };
6595 5829
6596 cpu7_top_crit 5830 cpu7_top_crit: cpu-crit {
6597 tempe 5831 temperature = <110000>;
6598 hyste 5832 hysteresis = <1000>;
6599 type 5833 type = "critical";
6600 }; 5834 };
6601 }; 5835 };
6602 5836
6603 cooling-maps { 5837 cooling-maps {
6604 map0 { 5838 map0 {
6605 trip 5839 trip = <&cpu7_top_alert0>;
6606 cooli 5840 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6607 5841 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6608 5842 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6609 5843 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6610 }; 5844 };
6611 map1 { 5845 map1 {
6612 trip 5846 trip = <&cpu7_top_alert1>;
6613 cooli 5847 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6614 5848 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6615 5849 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6616 5850 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6617 }; 5851 };
6618 }; 5852 };
6619 }; 5853 };
6620 5854
6621 cpu4-bottom-thermal { 5855 cpu4-bottom-thermal {
6622 polling-delay-passive 5856 polling-delay-passive = <250>;
>> 5857 polling-delay = <1000>;
6623 5858
6624 thermal-sensors = <&t 5859 thermal-sensors = <&tsens0 11>;
6625 5860
6626 trips { 5861 trips {
6627 cpu4_bottom_a 5862 cpu4_bottom_alert0: trip-point0 {
6628 tempe 5863 temperature = <90000>;
6629 hyste 5864 hysteresis = <2000>;
6630 type 5865 type = "passive";
6631 }; 5866 };
6632 5867
6633 cpu4_bottom_a 5868 cpu4_bottom_alert1: trip-point1 {
6634 tempe 5869 temperature = <95000>;
6635 hyste 5870 hysteresis = <2000>;
6636 type 5871 type = "passive";
6637 }; 5872 };
6638 5873
6639 cpu4_bottom_c 5874 cpu4_bottom_crit: cpu-crit {
6640 tempe 5875 temperature = <110000>;
6641 hyste 5876 hysteresis = <1000>;
6642 type 5877 type = "critical";
6643 }; 5878 };
6644 }; 5879 };
6645 5880
6646 cooling-maps { 5881 cooling-maps {
6647 map0 { 5882 map0 {
6648 trip 5883 trip = <&cpu4_bottom_alert0>;
6649 cooli 5884 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6650 5885 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6651 5886 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6652 5887 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6653 }; 5888 };
6654 map1 { 5889 map1 {
6655 trip 5890 trip = <&cpu4_bottom_alert1>;
6656 cooli 5891 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6657 5892 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6658 5893 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6659 5894 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6660 }; 5895 };
6661 }; 5896 };
6662 }; 5897 };
6663 5898
6664 cpu5-bottom-thermal { 5899 cpu5-bottom-thermal {
6665 polling-delay-passive 5900 polling-delay-passive = <250>;
>> 5901 polling-delay = <1000>;
6666 5902
6667 thermal-sensors = <&t 5903 thermal-sensors = <&tsens0 12>;
6668 5904
6669 trips { 5905 trips {
6670 cpu5_bottom_a 5906 cpu5_bottom_alert0: trip-point0 {
6671 tempe 5907 temperature = <90000>;
6672 hyste 5908 hysteresis = <2000>;
6673 type 5909 type = "passive";
6674 }; 5910 };
6675 5911
6676 cpu5_bottom_a 5912 cpu5_bottom_alert1: trip-point1 {
6677 tempe 5913 temperature = <95000>;
6678 hyste 5914 hysteresis = <2000>;
6679 type 5915 type = "passive";
6680 }; 5916 };
6681 5917
6682 cpu5_bottom_c 5918 cpu5_bottom_crit: cpu-crit {
6683 tempe 5919 temperature = <110000>;
6684 hyste 5920 hysteresis = <1000>;
6685 type 5921 type = "critical";
6686 }; 5922 };
6687 }; 5923 };
6688 5924
6689 cooling-maps { 5925 cooling-maps {
6690 map0 { 5926 map0 {
6691 trip 5927 trip = <&cpu5_bottom_alert0>;
6692 cooli 5928 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6693 5929 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6694 5930 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6695 5931 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6696 }; 5932 };
6697 map1 { 5933 map1 {
6698 trip 5934 trip = <&cpu5_bottom_alert1>;
6699 cooli 5935 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6700 5936 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6701 5937 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6702 5938 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6703 }; 5939 };
6704 }; 5940 };
6705 }; 5941 };
6706 5942
6707 cpu6-bottom-thermal { 5943 cpu6-bottom-thermal {
6708 polling-delay-passive 5944 polling-delay-passive = <250>;
>> 5945 polling-delay = <1000>;
6709 5946
6710 thermal-sensors = <&t 5947 thermal-sensors = <&tsens0 13>;
6711 5948
6712 trips { 5949 trips {
6713 cpu6_bottom_a 5950 cpu6_bottom_alert0: trip-point0 {
6714 tempe 5951 temperature = <90000>;
6715 hyste 5952 hysteresis = <2000>;
6716 type 5953 type = "passive";
6717 }; 5954 };
6718 5955
6719 cpu6_bottom_a 5956 cpu6_bottom_alert1: trip-point1 {
6720 tempe 5957 temperature = <95000>;
6721 hyste 5958 hysteresis = <2000>;
6722 type 5959 type = "passive";
6723 }; 5960 };
6724 5961
6725 cpu6_bottom_c 5962 cpu6_bottom_crit: cpu-crit {
6726 tempe 5963 temperature = <110000>;
6727 hyste 5964 hysteresis = <1000>;
6728 type 5965 type = "critical";
6729 }; 5966 };
6730 }; 5967 };
6731 5968
6732 cooling-maps { 5969 cooling-maps {
6733 map0 { 5970 map0 {
6734 trip 5971 trip = <&cpu6_bottom_alert0>;
6735 cooli 5972 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6736 5973 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6737 5974 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6738 5975 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6739 }; 5976 };
6740 map1 { 5977 map1 {
6741 trip 5978 trip = <&cpu6_bottom_alert1>;
6742 cooli 5979 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6743 5980 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6744 5981 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6745 5982 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6746 }; 5983 };
6747 }; 5984 };
6748 }; 5985 };
6749 5986
6750 cpu7-bottom-thermal { 5987 cpu7-bottom-thermal {
6751 polling-delay-passive 5988 polling-delay-passive = <250>;
>> 5989 polling-delay = <1000>;
6752 5990
6753 thermal-sensors = <&t 5991 thermal-sensors = <&tsens0 14>;
6754 5992
6755 trips { 5993 trips {
6756 cpu7_bottom_a 5994 cpu7_bottom_alert0: trip-point0 {
6757 tempe 5995 temperature = <90000>;
6758 hyste 5996 hysteresis = <2000>;
6759 type 5997 type = "passive";
6760 }; 5998 };
6761 5999
6762 cpu7_bottom_a 6000 cpu7_bottom_alert1: trip-point1 {
6763 tempe 6001 temperature = <95000>;
6764 hyste 6002 hysteresis = <2000>;
6765 type 6003 type = "passive";
6766 }; 6004 };
6767 6005
6768 cpu7_bottom_c 6006 cpu7_bottom_crit: cpu-crit {
6769 tempe 6007 temperature = <110000>;
6770 hyste 6008 hysteresis = <1000>;
6771 type 6009 type = "critical";
6772 }; 6010 };
6773 }; 6011 };
6774 6012
6775 cooling-maps { 6013 cooling-maps {
6776 map0 { 6014 map0 {
6777 trip 6015 trip = <&cpu7_bottom_alert0>;
6778 cooli 6016 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6779 6017 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6780 6018 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6781 6019 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6782 }; 6020 };
6783 map1 { 6021 map1 {
6784 trip 6022 trip = <&cpu7_bottom_alert1>;
6785 cooli 6023 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6786 6024 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6787 6025 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6788 6026 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6789 }; 6027 };
6790 }; 6028 };
6791 }; 6029 };
6792 6030
6793 aoss0-thermal { 6031 aoss0-thermal {
6794 polling-delay-passive 6032 polling-delay-passive = <250>;
>> 6033 polling-delay = <1000>;
6795 6034
6796 thermal-sensors = <&t 6035 thermal-sensors = <&tsens0 0>;
6797 6036
6798 trips { 6037 trips {
6799 aoss0_alert0: 6038 aoss0_alert0: trip-point0 {
6800 tempe 6039 temperature = <90000>;
6801 hyste 6040 hysteresis = <2000>;
6802 type 6041 type = "hot";
6803 }; 6042 };
6804 }; 6043 };
6805 }; 6044 };
6806 6045
6807 cluster0-thermal { 6046 cluster0-thermal {
6808 polling-delay-passive 6047 polling-delay-passive = <250>;
>> 6048 polling-delay = <1000>;
6809 6049
6810 thermal-sensors = <&t 6050 thermal-sensors = <&tsens0 5>;
6811 6051
6812 trips { 6052 trips {
6813 cluster0_aler 6053 cluster0_alert0: trip-point0 {
6814 tempe 6054 temperature = <90000>;
6815 hyste 6055 hysteresis = <2000>;
6816 type 6056 type = "hot";
6817 }; 6057 };
6818 cluster0_crit !! 6058 cluster0_crit: cluster0_crit {
6819 tempe 6059 temperature = <110000>;
6820 hyste 6060 hysteresis = <2000>;
6821 type 6061 type = "critical";
6822 }; 6062 };
6823 }; 6063 };
6824 }; 6064 };
6825 6065
6826 cluster1-thermal { 6066 cluster1-thermal {
6827 polling-delay-passive 6067 polling-delay-passive = <250>;
>> 6068 polling-delay = <1000>;
6828 6069
6829 thermal-sensors = <&t 6070 thermal-sensors = <&tsens0 6>;
6830 6071
6831 trips { 6072 trips {
6832 cluster1_aler 6073 cluster1_alert0: trip-point0 {
6833 tempe 6074 temperature = <90000>;
6834 hyste 6075 hysteresis = <2000>;
6835 type 6076 type = "hot";
6836 }; 6077 };
6837 cluster1_crit !! 6078 cluster1_crit: cluster1_crit {
6838 tempe 6079 temperature = <110000>;
6839 hyste 6080 hysteresis = <2000>;
6840 type 6081 type = "critical";
6841 }; 6082 };
6842 }; 6083 };
6843 }; 6084 };
6844 6085
6845 gpu-top-thermal { 6086 gpu-top-thermal {
6846 polling-delay-passive 6087 polling-delay-passive = <250>;
>> 6088 polling-delay = <1000>;
6847 6089
6848 thermal-sensors = <&t 6090 thermal-sensors = <&tsens0 15>;
6849 6091
6850 cooling-maps { <<
6851 map0 { <<
6852 trip <<
6853 cooli <<
6854 }; <<
6855 }; <<
6856 <<
6857 trips { 6092 trips {
6858 gpu_top_alert !! 6093 gpu1_alert0: trip-point0 {
6859 tempe <<
6860 hyste <<
6861 type <<
6862 }; <<
6863 <<
6864 trip-point1 { <<
6865 tempe 6094 temperature = <90000>;
6866 hyste !! 6095 hysteresis = <2000>;
6867 type 6096 type = "hot";
6868 }; 6097 };
6869 <<
6870 trip-point2 { <<
6871 tempe <<
6872 hyste <<
6873 type <<
6874 }; <<
6875 }; 6098 };
6876 }; 6099 };
6877 6100
6878 aoss1-thermal { 6101 aoss1-thermal {
6879 polling-delay-passive 6102 polling-delay-passive = <250>;
>> 6103 polling-delay = <1000>;
6880 6104
6881 thermal-sensors = <&t 6105 thermal-sensors = <&tsens1 0>;
6882 6106
6883 trips { 6107 trips {
6884 aoss1_alert0: 6108 aoss1_alert0: trip-point0 {
6885 tempe 6109 temperature = <90000>;
6886 hyste 6110 hysteresis = <2000>;
6887 type 6111 type = "hot";
6888 }; 6112 };
6889 }; 6113 };
6890 }; 6114 };
6891 6115
6892 wlan-thermal { 6116 wlan-thermal {
6893 polling-delay-passive 6117 polling-delay-passive = <250>;
>> 6118 polling-delay = <1000>;
6894 6119
6895 thermal-sensors = <&t 6120 thermal-sensors = <&tsens1 1>;
6896 6121
6897 trips { 6122 trips {
6898 wlan_alert0: 6123 wlan_alert0: trip-point0 {
6899 tempe 6124 temperature = <90000>;
6900 hyste 6125 hysteresis = <2000>;
6901 type 6126 type = "hot";
6902 }; 6127 };
6903 }; 6128 };
6904 }; 6129 };
6905 6130
6906 video-thermal { 6131 video-thermal {
6907 polling-delay-passive 6132 polling-delay-passive = <250>;
>> 6133 polling-delay = <1000>;
6908 6134
6909 thermal-sensors = <&t 6135 thermal-sensors = <&tsens1 2>;
6910 6136
6911 trips { 6137 trips {
6912 video_alert0: 6138 video_alert0: trip-point0 {
6913 tempe 6139 temperature = <90000>;
6914 hyste 6140 hysteresis = <2000>;
6915 type 6141 type = "hot";
6916 }; 6142 };
6917 }; 6143 };
6918 }; 6144 };
6919 6145
6920 mem-thermal { 6146 mem-thermal {
6921 polling-delay-passive 6147 polling-delay-passive = <250>;
>> 6148 polling-delay = <1000>;
6922 6149
6923 thermal-sensors = <&t 6150 thermal-sensors = <&tsens1 3>;
6924 6151
6925 trips { 6152 trips {
6926 mem_alert0: t 6153 mem_alert0: trip-point0 {
6927 tempe 6154 temperature = <90000>;
6928 hyste 6155 hysteresis = <2000>;
6929 type 6156 type = "hot";
6930 }; 6157 };
6931 }; 6158 };
6932 }; 6159 };
6933 6160
6934 q6-hvx-thermal { 6161 q6-hvx-thermal {
6935 polling-delay-passive 6162 polling-delay-passive = <250>;
>> 6163 polling-delay = <1000>;
6936 6164
6937 thermal-sensors = <&t 6165 thermal-sensors = <&tsens1 4>;
6938 6166
6939 trips { 6167 trips {
6940 q6_hvx_alert0 6168 q6_hvx_alert0: trip-point0 {
6941 tempe 6169 temperature = <90000>;
6942 hyste 6170 hysteresis = <2000>;
6943 type 6171 type = "hot";
6944 }; 6172 };
6945 }; 6173 };
6946 }; 6174 };
6947 6175
6948 camera-thermal { 6176 camera-thermal {
6949 polling-delay-passive 6177 polling-delay-passive = <250>;
>> 6178 polling-delay = <1000>;
6950 6179
6951 thermal-sensors = <&t 6180 thermal-sensors = <&tsens1 5>;
6952 6181
6953 trips { 6182 trips {
6954 camera_alert0 6183 camera_alert0: trip-point0 {
6955 tempe 6184 temperature = <90000>;
6956 hyste 6185 hysteresis = <2000>;
6957 type 6186 type = "hot";
6958 }; 6187 };
6959 }; 6188 };
6960 }; 6189 };
6961 6190
6962 compute-thermal { 6191 compute-thermal {
6963 polling-delay-passive 6192 polling-delay-passive = <250>;
>> 6193 polling-delay = <1000>;
6964 6194
6965 thermal-sensors = <&t 6195 thermal-sensors = <&tsens1 6>;
6966 6196
6967 trips { 6197 trips {
6968 compute_alert 6198 compute_alert0: trip-point0 {
6969 tempe 6199 temperature = <90000>;
6970 hyste 6200 hysteresis = <2000>;
6971 type 6201 type = "hot";
6972 }; 6202 };
6973 }; 6203 };
6974 }; 6204 };
6975 6205
6976 npu-thermal { 6206 npu-thermal {
6977 polling-delay-passive 6207 polling-delay-passive = <250>;
>> 6208 polling-delay = <1000>;
6978 6209
6979 thermal-sensors = <&t 6210 thermal-sensors = <&tsens1 7>;
6980 6211
6981 trips { 6212 trips {
6982 npu_alert0: t 6213 npu_alert0: trip-point0 {
6983 tempe 6214 temperature = <90000>;
6984 hyste 6215 hysteresis = <2000>;
6985 type 6216 type = "hot";
6986 }; 6217 };
6987 }; 6218 };
6988 }; 6219 };
6989 6220
6990 gpu-bottom-thermal { 6221 gpu-bottom-thermal {
6991 polling-delay-passive 6222 polling-delay-passive = <250>;
>> 6223 polling-delay = <1000>;
6992 6224
6993 thermal-sensors = <&t 6225 thermal-sensors = <&tsens1 8>;
6994 6226
6995 cooling-maps { <<
6996 map0 { <<
6997 trip <<
6998 cooli <<
6999 }; <<
7000 }; <<
7001 <<
7002 trips { 6227 trips {
7003 gpu_bottom_al !! 6228 gpu2_alert0: trip-point0 {
7004 tempe <<
7005 hyste <<
7006 type <<
7007 }; <<
7008 <<
7009 trip-point1 { <<
7010 tempe 6229 temperature = <90000>;
7011 hyste !! 6230 hysteresis = <2000>;
7012 type 6231 type = "hot";
7013 }; <<
7014 <<
7015 trip-point2 { <<
7016 tempe <<
7017 hyste <<
7018 type <<
7019 }; 6232 };
7020 }; 6233 };
7021 }; 6234 };
7022 }; 6235 };
7023 }; 6236 };
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