1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * Copyright (c) 2020, The Linux Foundation. A 3 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
4 */ 4 */
5 5
6 #include <dt-bindings/interrupt-controller/arm 6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,dispcc-sm8250 7 #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
8 #include <dt-bindings/clock/qcom,gcc-sm8250.h> 8 #include <dt-bindings/clock/qcom,gcc-sm8250.h>
9 #include <dt-bindings/clock/qcom,gpucc-sm8250. 9 #include <dt-bindings/clock/qcom,gpucc-sm8250.h>
10 #include <dt-bindings/clock/qcom,rpmh.h> 10 #include <dt-bindings/clock/qcom,rpmh.h>
>> 11 #include <dt-bindings/clock/qcom,sm8250-lpass-aoncc.h>
>> 12 #include <dt-bindings/clock/qcom,sm8250-lpass-audiocc.h>
11 #include <dt-bindings/dma/qcom-gpi.h> 13 #include <dt-bindings/dma/qcom-gpi.h>
12 #include <dt-bindings/gpio/gpio.h> 14 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interconnect/qcom,osm-l3 15 #include <dt-bindings/interconnect/qcom,osm-l3.h>
14 #include <dt-bindings/interconnect/qcom,sm8250 16 #include <dt-bindings/interconnect/qcom,sm8250.h>
15 #include <dt-bindings/mailbox/qcom-ipcc.h> 17 #include <dt-bindings/mailbox/qcom-ipcc.h>
16 #include <dt-bindings/phy/phy-qcom-qmp.h> <<
17 #include <dt-bindings/power/qcom-rpmpd.h> 18 #include <dt-bindings/power/qcom-rpmpd.h>
18 #include <dt-bindings/power/qcom,rpmhpd.h> <<
19 #include <dt-bindings/soc/qcom,apr.h> 19 #include <dt-bindings/soc/qcom,apr.h>
20 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 20 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
21 #include <dt-bindings/sound/qcom,q6afe.h> 21 #include <dt-bindings/sound/qcom,q6afe.h>
22 #include <dt-bindings/thermal/thermal.h> 22 #include <dt-bindings/thermal/thermal.h>
23 #include <dt-bindings/clock/qcom,camcc-sm8250. 23 #include <dt-bindings/clock/qcom,camcc-sm8250.h>
24 #include <dt-bindings/clock/qcom,videocc-sm825 24 #include <dt-bindings/clock/qcom,videocc-sm8250.h>
25 25
26 / { 26 / {
27 interrupt-parent = <&intc>; 27 interrupt-parent = <&intc>;
28 28
29 #address-cells = <2>; 29 #address-cells = <2>;
30 #size-cells = <2>; 30 #size-cells = <2>;
31 31
32 aliases { 32 aliases {
33 i2c0 = &i2c0; 33 i2c0 = &i2c0;
34 i2c1 = &i2c1; 34 i2c1 = &i2c1;
35 i2c2 = &i2c2; 35 i2c2 = &i2c2;
36 i2c3 = &i2c3; 36 i2c3 = &i2c3;
37 i2c4 = &i2c4; 37 i2c4 = &i2c4;
38 i2c5 = &i2c5; 38 i2c5 = &i2c5;
39 i2c6 = &i2c6; 39 i2c6 = &i2c6;
40 i2c7 = &i2c7; 40 i2c7 = &i2c7;
41 i2c8 = &i2c8; 41 i2c8 = &i2c8;
42 i2c9 = &i2c9; 42 i2c9 = &i2c9;
43 i2c10 = &i2c10; 43 i2c10 = &i2c10;
44 i2c11 = &i2c11; 44 i2c11 = &i2c11;
45 i2c12 = &i2c12; 45 i2c12 = &i2c12;
46 i2c13 = &i2c13; 46 i2c13 = &i2c13;
47 i2c14 = &i2c14; 47 i2c14 = &i2c14;
48 i2c15 = &i2c15; 48 i2c15 = &i2c15;
49 i2c16 = &i2c16; 49 i2c16 = &i2c16;
50 i2c17 = &i2c17; 50 i2c17 = &i2c17;
51 i2c18 = &i2c18; 51 i2c18 = &i2c18;
52 i2c19 = &i2c19; 52 i2c19 = &i2c19;
53 spi0 = &spi0; 53 spi0 = &spi0;
54 spi1 = &spi1; 54 spi1 = &spi1;
55 spi2 = &spi2; 55 spi2 = &spi2;
56 spi3 = &spi3; 56 spi3 = &spi3;
57 spi4 = &spi4; 57 spi4 = &spi4;
58 spi5 = &spi5; 58 spi5 = &spi5;
59 spi6 = &spi6; 59 spi6 = &spi6;
60 spi7 = &spi7; 60 spi7 = &spi7;
61 spi8 = &spi8; 61 spi8 = &spi8;
62 spi9 = &spi9; 62 spi9 = &spi9;
63 spi10 = &spi10; 63 spi10 = &spi10;
64 spi11 = &spi11; 64 spi11 = &spi11;
65 spi12 = &spi12; 65 spi12 = &spi12;
66 spi13 = &spi13; 66 spi13 = &spi13;
67 spi14 = &spi14; 67 spi14 = &spi14;
68 spi15 = &spi15; 68 spi15 = &spi15;
69 spi16 = &spi16; 69 spi16 = &spi16;
70 spi17 = &spi17; 70 spi17 = &spi17;
71 spi18 = &spi18; 71 spi18 = &spi18;
72 spi19 = &spi19; 72 spi19 = &spi19;
73 }; 73 };
74 74
75 chosen { }; 75 chosen { };
76 76
77 clocks { 77 clocks {
78 xo_board: xo-board { 78 xo_board: xo-board {
79 compatible = "fixed-cl 79 compatible = "fixed-clock";
80 #clock-cells = <0>; 80 #clock-cells = <0>;
81 clock-frequency = <384 81 clock-frequency = <38400000>;
82 clock-output-names = " 82 clock-output-names = "xo_board";
83 }; 83 };
84 84
85 sleep_clk: sleep-clk { 85 sleep_clk: sleep-clk {
86 compatible = "fixed-cl 86 compatible = "fixed-clock";
87 clock-frequency = <327 87 clock-frequency = <32768>;
88 #clock-cells = <0>; 88 #clock-cells = <0>;
89 }; 89 };
90 }; 90 };
91 91
92 cpus { 92 cpus {
93 #address-cells = <2>; 93 #address-cells = <2>;
94 #size-cells = <0>; 94 #size-cells = <0>;
95 95
96 CPU0: cpu@0 { 96 CPU0: cpu@0 {
97 device_type = "cpu"; 97 device_type = "cpu";
98 compatible = "qcom,kry 98 compatible = "qcom,kryo485";
99 reg = <0x0 0x0>; 99 reg = <0x0 0x0>;
100 clocks = <&cpufreq_hw 100 clocks = <&cpufreq_hw 0>;
101 enable-method = "psci" 101 enable-method = "psci";
102 capacity-dmips-mhz = < 102 capacity-dmips-mhz = <448>;
103 dynamic-power-coeffici 103 dynamic-power-coefficient = <105>;
104 next-level-cache = <&L 104 next-level-cache = <&L2_0>;
105 power-domains = <&CPU_ 105 power-domains = <&CPU_PD0>;
106 power-domain-names = " 106 power-domain-names = "psci";
107 qcom,freq-domain = <&c 107 qcom,freq-domain = <&cpufreq_hw 0>;
108 operating-points-v2 = 108 operating-points-v2 = <&cpu0_opp_table>;
109 interconnects = <&gem_ 109 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
110 <&epss 110 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
111 #cooling-cells = <2>; 111 #cooling-cells = <2>;
112 L2_0: l2-cache { 112 L2_0: l2-cache {
113 compatible = " 113 compatible = "cache";
114 cache-level = 114 cache-level = <2>;
115 cache-size = < 115 cache-size = <0x20000>;
116 cache-unified; 116 cache-unified;
117 next-level-cac 117 next-level-cache = <&L3_0>;
118 L3_0: l3-cache 118 L3_0: l3-cache {
119 compat 119 compatible = "cache";
120 cache- 120 cache-level = <3>;
121 cache- 121 cache-size = <0x400000>;
122 cache- 122 cache-unified;
123 }; 123 };
124 }; 124 };
125 }; 125 };
126 126
127 CPU1: cpu@100 { 127 CPU1: cpu@100 {
128 device_type = "cpu"; 128 device_type = "cpu";
129 compatible = "qcom,kry 129 compatible = "qcom,kryo485";
130 reg = <0x0 0x100>; 130 reg = <0x0 0x100>;
131 clocks = <&cpufreq_hw 131 clocks = <&cpufreq_hw 0>;
132 enable-method = "psci" 132 enable-method = "psci";
133 capacity-dmips-mhz = < 133 capacity-dmips-mhz = <448>;
134 dynamic-power-coeffici 134 dynamic-power-coefficient = <105>;
135 next-level-cache = <&L 135 next-level-cache = <&L2_100>;
136 power-domains = <&CPU_ 136 power-domains = <&CPU_PD1>;
137 power-domain-names = " 137 power-domain-names = "psci";
138 qcom,freq-domain = <&c 138 qcom,freq-domain = <&cpufreq_hw 0>;
139 operating-points-v2 = 139 operating-points-v2 = <&cpu0_opp_table>;
140 interconnects = <&gem_ 140 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
141 <&epss 141 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
142 #cooling-cells = <2>; 142 #cooling-cells = <2>;
143 L2_100: l2-cache { 143 L2_100: l2-cache {
144 compatible = " 144 compatible = "cache";
145 cache-level = 145 cache-level = <2>;
146 cache-size = < 146 cache-size = <0x20000>;
147 cache-unified; 147 cache-unified;
148 next-level-cac 148 next-level-cache = <&L3_0>;
149 }; 149 };
150 }; 150 };
151 151
152 CPU2: cpu@200 { 152 CPU2: cpu@200 {
153 device_type = "cpu"; 153 device_type = "cpu";
154 compatible = "qcom,kry 154 compatible = "qcom,kryo485";
155 reg = <0x0 0x200>; 155 reg = <0x0 0x200>;
156 clocks = <&cpufreq_hw 156 clocks = <&cpufreq_hw 0>;
157 enable-method = "psci" 157 enable-method = "psci";
158 capacity-dmips-mhz = < 158 capacity-dmips-mhz = <448>;
159 dynamic-power-coeffici 159 dynamic-power-coefficient = <105>;
160 next-level-cache = <&L 160 next-level-cache = <&L2_200>;
161 power-domains = <&CPU_ 161 power-domains = <&CPU_PD2>;
162 power-domain-names = " 162 power-domain-names = "psci";
163 qcom,freq-domain = <&c 163 qcom,freq-domain = <&cpufreq_hw 0>;
164 operating-points-v2 = 164 operating-points-v2 = <&cpu0_opp_table>;
165 interconnects = <&gem_ 165 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
166 <&epss 166 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
167 #cooling-cells = <2>; 167 #cooling-cells = <2>;
168 L2_200: l2-cache { 168 L2_200: l2-cache {
169 compatible = " 169 compatible = "cache";
170 cache-level = 170 cache-level = <2>;
171 cache-size = < 171 cache-size = <0x20000>;
172 cache-unified; 172 cache-unified;
173 next-level-cac 173 next-level-cache = <&L3_0>;
174 }; 174 };
175 }; 175 };
176 176
177 CPU3: cpu@300 { 177 CPU3: cpu@300 {
178 device_type = "cpu"; 178 device_type = "cpu";
179 compatible = "qcom,kry 179 compatible = "qcom,kryo485";
180 reg = <0x0 0x300>; 180 reg = <0x0 0x300>;
181 clocks = <&cpufreq_hw 181 clocks = <&cpufreq_hw 0>;
182 enable-method = "psci" 182 enable-method = "psci";
183 capacity-dmips-mhz = < 183 capacity-dmips-mhz = <448>;
184 dynamic-power-coeffici 184 dynamic-power-coefficient = <105>;
185 next-level-cache = <&L 185 next-level-cache = <&L2_300>;
186 power-domains = <&CPU_ 186 power-domains = <&CPU_PD3>;
187 power-domain-names = " 187 power-domain-names = "psci";
188 qcom,freq-domain = <&c 188 qcom,freq-domain = <&cpufreq_hw 0>;
189 operating-points-v2 = 189 operating-points-v2 = <&cpu0_opp_table>;
190 interconnects = <&gem_ 190 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
191 <&epss 191 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
192 #cooling-cells = <2>; 192 #cooling-cells = <2>;
193 L2_300: l2-cache { 193 L2_300: l2-cache {
194 compatible = " 194 compatible = "cache";
195 cache-level = 195 cache-level = <2>;
196 cache-size = < 196 cache-size = <0x20000>;
197 cache-unified; 197 cache-unified;
198 next-level-cac 198 next-level-cache = <&L3_0>;
199 }; 199 };
200 }; 200 };
201 201
202 CPU4: cpu@400 { 202 CPU4: cpu@400 {
203 device_type = "cpu"; 203 device_type = "cpu";
204 compatible = "qcom,kry 204 compatible = "qcom,kryo485";
205 reg = <0x0 0x400>; 205 reg = <0x0 0x400>;
206 clocks = <&cpufreq_hw 206 clocks = <&cpufreq_hw 1>;
207 enable-method = "psci" 207 enable-method = "psci";
208 capacity-dmips-mhz = < 208 capacity-dmips-mhz = <1024>;
209 dynamic-power-coeffici 209 dynamic-power-coefficient = <379>;
210 next-level-cache = <&L 210 next-level-cache = <&L2_400>;
211 power-domains = <&CPU_ 211 power-domains = <&CPU_PD4>;
212 power-domain-names = " 212 power-domain-names = "psci";
213 qcom,freq-domain = <&c 213 qcom,freq-domain = <&cpufreq_hw 1>;
214 operating-points-v2 = 214 operating-points-v2 = <&cpu4_opp_table>;
215 interconnects = <&gem_ 215 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
216 <&epss 216 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
217 #cooling-cells = <2>; 217 #cooling-cells = <2>;
218 L2_400: l2-cache { 218 L2_400: l2-cache {
219 compatible = " 219 compatible = "cache";
220 cache-level = 220 cache-level = <2>;
221 cache-size = < 221 cache-size = <0x40000>;
222 cache-unified; 222 cache-unified;
223 next-level-cac 223 next-level-cache = <&L3_0>;
224 }; 224 };
225 }; 225 };
226 226
227 CPU5: cpu@500 { 227 CPU5: cpu@500 {
228 device_type = "cpu"; 228 device_type = "cpu";
229 compatible = "qcom,kry 229 compatible = "qcom,kryo485";
230 reg = <0x0 0x500>; 230 reg = <0x0 0x500>;
231 clocks = <&cpufreq_hw 231 clocks = <&cpufreq_hw 1>;
232 enable-method = "psci" 232 enable-method = "psci";
233 capacity-dmips-mhz = < 233 capacity-dmips-mhz = <1024>;
234 dynamic-power-coeffici 234 dynamic-power-coefficient = <379>;
235 next-level-cache = <&L 235 next-level-cache = <&L2_500>;
236 power-domains = <&CPU_ 236 power-domains = <&CPU_PD5>;
237 power-domain-names = " 237 power-domain-names = "psci";
238 qcom,freq-domain = <&c 238 qcom,freq-domain = <&cpufreq_hw 1>;
239 operating-points-v2 = 239 operating-points-v2 = <&cpu4_opp_table>;
240 interconnects = <&gem_ 240 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
241 <&epss 241 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
242 #cooling-cells = <2>; 242 #cooling-cells = <2>;
243 L2_500: l2-cache { 243 L2_500: l2-cache {
244 compatible = " 244 compatible = "cache";
245 cache-level = 245 cache-level = <2>;
246 cache-size = < 246 cache-size = <0x40000>;
247 cache-unified; 247 cache-unified;
248 next-level-cac 248 next-level-cache = <&L3_0>;
249 }; 249 };
250 }; 250 };
251 251
252 CPU6: cpu@600 { 252 CPU6: cpu@600 {
253 device_type = "cpu"; 253 device_type = "cpu";
254 compatible = "qcom,kry 254 compatible = "qcom,kryo485";
255 reg = <0x0 0x600>; 255 reg = <0x0 0x600>;
256 clocks = <&cpufreq_hw 256 clocks = <&cpufreq_hw 1>;
257 enable-method = "psci" 257 enable-method = "psci";
258 capacity-dmips-mhz = < 258 capacity-dmips-mhz = <1024>;
259 dynamic-power-coeffici 259 dynamic-power-coefficient = <379>;
260 next-level-cache = <&L 260 next-level-cache = <&L2_600>;
261 power-domains = <&CPU_ 261 power-domains = <&CPU_PD6>;
262 power-domain-names = " 262 power-domain-names = "psci";
263 qcom,freq-domain = <&c 263 qcom,freq-domain = <&cpufreq_hw 1>;
264 operating-points-v2 = 264 operating-points-v2 = <&cpu4_opp_table>;
265 interconnects = <&gem_ 265 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
266 <&epss 266 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
267 #cooling-cells = <2>; 267 #cooling-cells = <2>;
268 L2_600: l2-cache { 268 L2_600: l2-cache {
269 compatible = " 269 compatible = "cache";
270 cache-level = 270 cache-level = <2>;
271 cache-size = < 271 cache-size = <0x40000>;
272 cache-unified; 272 cache-unified;
273 next-level-cac 273 next-level-cache = <&L3_0>;
274 }; 274 };
275 }; 275 };
276 276
277 CPU7: cpu@700 { 277 CPU7: cpu@700 {
278 device_type = "cpu"; 278 device_type = "cpu";
279 compatible = "qcom,kry 279 compatible = "qcom,kryo485";
280 reg = <0x0 0x700>; 280 reg = <0x0 0x700>;
281 clocks = <&cpufreq_hw 281 clocks = <&cpufreq_hw 2>;
282 enable-method = "psci" 282 enable-method = "psci";
283 capacity-dmips-mhz = < 283 capacity-dmips-mhz = <1024>;
284 dynamic-power-coeffici 284 dynamic-power-coefficient = <444>;
285 next-level-cache = <&L 285 next-level-cache = <&L2_700>;
286 power-domains = <&CPU_ 286 power-domains = <&CPU_PD7>;
287 power-domain-names = " 287 power-domain-names = "psci";
288 qcom,freq-domain = <&c 288 qcom,freq-domain = <&cpufreq_hw 2>;
289 operating-points-v2 = 289 operating-points-v2 = <&cpu7_opp_table>;
290 interconnects = <&gem_ 290 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
291 <&epss 291 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
292 #cooling-cells = <2>; 292 #cooling-cells = <2>;
293 L2_700: l2-cache { 293 L2_700: l2-cache {
294 compatible = " 294 compatible = "cache";
295 cache-level = 295 cache-level = <2>;
296 cache-size = < 296 cache-size = <0x80000>;
297 cache-unified; 297 cache-unified;
298 next-level-cac 298 next-level-cache = <&L3_0>;
299 }; 299 };
300 }; 300 };
301 301
302 cpu-map { 302 cpu-map {
303 cluster0 { 303 cluster0 {
304 core0 { 304 core0 {
305 cpu = 305 cpu = <&CPU0>;
306 }; 306 };
307 307
308 core1 { 308 core1 {
309 cpu = 309 cpu = <&CPU1>;
310 }; 310 };
311 311
312 core2 { 312 core2 {
313 cpu = 313 cpu = <&CPU2>;
314 }; 314 };
315 315
316 core3 { 316 core3 {
317 cpu = 317 cpu = <&CPU3>;
318 }; 318 };
319 319
320 core4 { 320 core4 {
321 cpu = 321 cpu = <&CPU4>;
322 }; 322 };
323 323
324 core5 { 324 core5 {
325 cpu = 325 cpu = <&CPU5>;
326 }; 326 };
327 327
328 core6 { 328 core6 {
329 cpu = 329 cpu = <&CPU6>;
330 }; 330 };
331 331
332 core7 { 332 core7 {
333 cpu = 333 cpu = <&CPU7>;
334 }; 334 };
335 }; 335 };
336 }; 336 };
337 337
338 idle-states { 338 idle-states {
339 entry-method = "psci"; 339 entry-method = "psci";
340 340
341 LITTLE_CPU_SLEEP_0: cp 341 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
342 compatible = " 342 compatible = "arm,idle-state";
343 idle-state-nam 343 idle-state-name = "silver-rail-power-collapse";
344 arm,psci-suspe 344 arm,psci-suspend-param = <0x40000004>;
345 entry-latency- 345 entry-latency-us = <360>;
346 exit-latency-u 346 exit-latency-us = <531>;
347 min-residency- 347 min-residency-us = <3934>;
348 local-timer-st 348 local-timer-stop;
349 }; 349 };
350 350
351 BIG_CPU_SLEEP_0: cpu-s 351 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
352 compatible = " 352 compatible = "arm,idle-state";
353 idle-state-nam 353 idle-state-name = "gold-rail-power-collapse";
354 arm,psci-suspe 354 arm,psci-suspend-param = <0x40000004>;
355 entry-latency- 355 entry-latency-us = <702>;
356 exit-latency-u 356 exit-latency-us = <1061>;
357 min-residency- 357 min-residency-us = <4488>;
358 local-timer-st 358 local-timer-stop;
359 }; 359 };
360 }; 360 };
361 361
362 domain-idle-states { 362 domain-idle-states {
363 CLUSTER_SLEEP_0: clust 363 CLUSTER_SLEEP_0: cluster-sleep-0 {
364 compatible = " 364 compatible = "domain-idle-state";
365 arm,psci-suspe 365 arm,psci-suspend-param = <0x4100c244>;
366 entry-latency- 366 entry-latency-us = <3264>;
367 exit-latency-u 367 exit-latency-us = <6562>;
368 min-residency- 368 min-residency-us = <9987>;
369 }; 369 };
370 }; 370 };
371 }; 371 };
372 372
373 qup_virt: interconnect-qup-virt { <<
374 compatible = "qcom,sm8250-qup- <<
375 #interconnect-cells = <2>; <<
376 qcom,bcm-voters = <&apps_bcm_v <<
377 }; <<
378 <<
379 cpu0_opp_table: opp-table-cpu0 { 373 cpu0_opp_table: opp-table-cpu0 {
380 compatible = "operating-points 374 compatible = "operating-points-v2";
381 opp-shared; 375 opp-shared;
382 376
383 cpu0_opp1: opp-300000000 { 377 cpu0_opp1: opp-300000000 {
384 opp-hz = /bits/ 64 <30 378 opp-hz = /bits/ 64 <300000000>;
385 opp-peak-kBps = <80000 379 opp-peak-kBps = <800000 9600000>;
386 }; 380 };
387 381
388 cpu0_opp2: opp-403200000 { 382 cpu0_opp2: opp-403200000 {
389 opp-hz = /bits/ 64 <40 383 opp-hz = /bits/ 64 <403200000>;
390 opp-peak-kBps = <80000 384 opp-peak-kBps = <800000 9600000>;
391 }; 385 };
392 386
393 cpu0_opp3: opp-518400000 { 387 cpu0_opp3: opp-518400000 {
394 opp-hz = /bits/ 64 <51 388 opp-hz = /bits/ 64 <518400000>;
395 opp-peak-kBps = <80000 389 opp-peak-kBps = <800000 16588800>;
396 }; 390 };
397 391
398 cpu0_opp4: opp-614400000 { 392 cpu0_opp4: opp-614400000 {
399 opp-hz = /bits/ 64 <61 393 opp-hz = /bits/ 64 <614400000>;
400 opp-peak-kBps = <80000 394 opp-peak-kBps = <800000 16588800>;
401 }; 395 };
402 396
403 cpu0_opp5: opp-691200000 { 397 cpu0_opp5: opp-691200000 {
404 opp-hz = /bits/ 64 <69 398 opp-hz = /bits/ 64 <691200000>;
405 opp-peak-kBps = <80000 399 opp-peak-kBps = <800000 19660800>;
406 }; 400 };
407 401
408 cpu0_opp6: opp-787200000 { 402 cpu0_opp6: opp-787200000 {
409 opp-hz = /bits/ 64 <78 403 opp-hz = /bits/ 64 <787200000>;
410 opp-peak-kBps = <18040 404 opp-peak-kBps = <1804000 19660800>;
411 }; 405 };
412 406
413 cpu0_opp7: opp-883200000 { 407 cpu0_opp7: opp-883200000 {
414 opp-hz = /bits/ 64 <88 408 opp-hz = /bits/ 64 <883200000>;
415 opp-peak-kBps = <18040 409 opp-peak-kBps = <1804000 23347200>;
416 }; 410 };
417 411
418 cpu0_opp8: opp-979200000 { 412 cpu0_opp8: opp-979200000 {
419 opp-hz = /bits/ 64 <97 413 opp-hz = /bits/ 64 <979200000>;
420 opp-peak-kBps = <18040 414 opp-peak-kBps = <1804000 26419200>;
421 }; 415 };
422 416
423 cpu0_opp9: opp-1075200000 { 417 cpu0_opp9: opp-1075200000 {
424 opp-hz = /bits/ 64 <10 418 opp-hz = /bits/ 64 <1075200000>;
425 opp-peak-kBps = <18040 419 opp-peak-kBps = <1804000 29491200>;
426 }; 420 };
427 421
428 cpu0_opp10: opp-1171200000 { 422 cpu0_opp10: opp-1171200000 {
429 opp-hz = /bits/ 64 <11 423 opp-hz = /bits/ 64 <1171200000>;
430 opp-peak-kBps = <18040 424 opp-peak-kBps = <1804000 32563200>;
431 }; 425 };
432 426
433 cpu0_opp11: opp-1248000000 { 427 cpu0_opp11: opp-1248000000 {
434 opp-hz = /bits/ 64 <12 428 opp-hz = /bits/ 64 <1248000000>;
435 opp-peak-kBps = <18040 429 opp-peak-kBps = <1804000 36249600>;
436 }; 430 };
437 431
438 cpu0_opp12: opp-1344000000 { 432 cpu0_opp12: opp-1344000000 {
439 opp-hz = /bits/ 64 <13 433 opp-hz = /bits/ 64 <1344000000>;
440 opp-peak-kBps = <21880 434 opp-peak-kBps = <2188000 36249600>;
441 }; 435 };
442 436
443 cpu0_opp13: opp-1420800000 { 437 cpu0_opp13: opp-1420800000 {
444 opp-hz = /bits/ 64 <14 438 opp-hz = /bits/ 64 <1420800000>;
445 opp-peak-kBps = <21880 439 opp-peak-kBps = <2188000 39321600>;
446 }; 440 };
447 441
448 cpu0_opp14: opp-1516800000 { 442 cpu0_opp14: opp-1516800000 {
449 opp-hz = /bits/ 64 <15 443 opp-hz = /bits/ 64 <1516800000>;
450 opp-peak-kBps = <30720 444 opp-peak-kBps = <3072000 42393600>;
451 }; 445 };
452 446
453 cpu0_opp15: opp-1612800000 { 447 cpu0_opp15: opp-1612800000 {
454 opp-hz = /bits/ 64 <16 448 opp-hz = /bits/ 64 <1612800000>;
455 opp-peak-kBps = <30720 449 opp-peak-kBps = <3072000 42393600>;
456 }; 450 };
457 451
458 cpu0_opp16: opp-1708800000 { 452 cpu0_opp16: opp-1708800000 {
459 opp-hz = /bits/ 64 <17 453 opp-hz = /bits/ 64 <1708800000>;
460 opp-peak-kBps = <40680 454 opp-peak-kBps = <4068000 42393600>;
461 }; 455 };
462 456
463 cpu0_opp17: opp-1804800000 { 457 cpu0_opp17: opp-1804800000 {
464 opp-hz = /bits/ 64 <18 458 opp-hz = /bits/ 64 <1804800000>;
465 opp-peak-kBps = <40680 459 opp-peak-kBps = <4068000 42393600>;
466 }; 460 };
467 }; 461 };
468 462
469 cpu4_opp_table: opp-table-cpu4 { 463 cpu4_opp_table: opp-table-cpu4 {
470 compatible = "operating-points 464 compatible = "operating-points-v2";
471 opp-shared; 465 opp-shared;
472 466
473 cpu4_opp1: opp-710400000 { 467 cpu4_opp1: opp-710400000 {
474 opp-hz = /bits/ 64 <71 468 opp-hz = /bits/ 64 <710400000>;
475 opp-peak-kBps = <18040 469 opp-peak-kBps = <1804000 19660800>;
476 }; 470 };
477 471
478 cpu4_opp2: opp-825600000 { 472 cpu4_opp2: opp-825600000 {
479 opp-hz = /bits/ 64 <82 473 opp-hz = /bits/ 64 <825600000>;
480 opp-peak-kBps = <21880 474 opp-peak-kBps = <2188000 23347200>;
481 }; 475 };
482 476
483 cpu4_opp3: opp-940800000 { 477 cpu4_opp3: opp-940800000 {
484 opp-hz = /bits/ 64 <94 478 opp-hz = /bits/ 64 <940800000>;
485 opp-peak-kBps = <21880 479 opp-peak-kBps = <2188000 26419200>;
486 }; 480 };
487 481
488 cpu4_opp4: opp-1056000000 { 482 cpu4_opp4: opp-1056000000 {
489 opp-hz = /bits/ 64 <10 483 opp-hz = /bits/ 64 <1056000000>;
490 opp-peak-kBps = <30720 484 opp-peak-kBps = <3072000 26419200>;
491 }; 485 };
492 486
493 cpu4_opp5: opp-1171200000 { 487 cpu4_opp5: opp-1171200000 {
494 opp-hz = /bits/ 64 <11 488 opp-hz = /bits/ 64 <1171200000>;
495 opp-peak-kBps = <30720 489 opp-peak-kBps = <3072000 29491200>;
496 }; 490 };
497 491
498 cpu4_opp6: opp-1286400000 { 492 cpu4_opp6: opp-1286400000 {
499 opp-hz = /bits/ 64 <12 493 opp-hz = /bits/ 64 <1286400000>;
500 opp-peak-kBps = <40680 494 opp-peak-kBps = <4068000 29491200>;
501 }; 495 };
502 496
503 cpu4_opp7: opp-1382400000 { 497 cpu4_opp7: opp-1382400000 {
504 opp-hz = /bits/ 64 <13 498 opp-hz = /bits/ 64 <1382400000>;
505 opp-peak-kBps = <40680 499 opp-peak-kBps = <4068000 32563200>;
506 }; 500 };
507 501
508 cpu4_opp8: opp-1478400000 { 502 cpu4_opp8: opp-1478400000 {
509 opp-hz = /bits/ 64 <14 503 opp-hz = /bits/ 64 <1478400000>;
510 opp-peak-kBps = <40680 504 opp-peak-kBps = <4068000 32563200>;
511 }; 505 };
512 506
513 cpu4_opp9: opp-1574400000 { 507 cpu4_opp9: opp-1574400000 {
514 opp-hz = /bits/ 64 <15 508 opp-hz = /bits/ 64 <1574400000>;
515 opp-peak-kBps = <54120 509 opp-peak-kBps = <5412000 39321600>;
516 }; 510 };
517 511
518 cpu4_opp10: opp-1670400000 { 512 cpu4_opp10: opp-1670400000 {
519 opp-hz = /bits/ 64 <16 513 opp-hz = /bits/ 64 <1670400000>;
520 opp-peak-kBps = <54120 514 opp-peak-kBps = <5412000 42393600>;
521 }; 515 };
522 516
523 cpu4_opp11: opp-1766400000 { 517 cpu4_opp11: opp-1766400000 {
524 opp-hz = /bits/ 64 <17 518 opp-hz = /bits/ 64 <1766400000>;
525 opp-peak-kBps = <54120 519 opp-peak-kBps = <5412000 45465600>;
526 }; 520 };
527 521
528 cpu4_opp12: opp-1862400000 { 522 cpu4_opp12: opp-1862400000 {
529 opp-hz = /bits/ 64 <18 523 opp-hz = /bits/ 64 <1862400000>;
530 opp-peak-kBps = <62200 524 opp-peak-kBps = <6220000 45465600>;
531 }; 525 };
532 526
533 cpu4_opp13: opp-1958400000 { 527 cpu4_opp13: opp-1958400000 {
534 opp-hz = /bits/ 64 <19 528 opp-hz = /bits/ 64 <1958400000>;
535 opp-peak-kBps = <62200 529 opp-peak-kBps = <6220000 48537600>;
536 }; 530 };
537 531
538 cpu4_opp14: opp-2054400000 { 532 cpu4_opp14: opp-2054400000 {
539 opp-hz = /bits/ 64 <20 533 opp-hz = /bits/ 64 <2054400000>;
540 opp-peak-kBps = <72160 534 opp-peak-kBps = <7216000 48537600>;
541 }; 535 };
542 536
543 cpu4_opp15: opp-2150400000 { 537 cpu4_opp15: opp-2150400000 {
544 opp-hz = /bits/ 64 <21 538 opp-hz = /bits/ 64 <2150400000>;
545 opp-peak-kBps = <72160 539 opp-peak-kBps = <7216000 51609600>;
546 }; 540 };
547 541
548 cpu4_opp16: opp-2246400000 { 542 cpu4_opp16: opp-2246400000 {
549 opp-hz = /bits/ 64 <22 543 opp-hz = /bits/ 64 <2246400000>;
550 opp-peak-kBps = <72160 544 opp-peak-kBps = <7216000 51609600>;
551 }; 545 };
552 546
553 cpu4_opp17: opp-2342400000 { 547 cpu4_opp17: opp-2342400000 {
554 opp-hz = /bits/ 64 <23 548 opp-hz = /bits/ 64 <2342400000>;
555 opp-peak-kBps = <83680 549 opp-peak-kBps = <8368000 51609600>;
556 }; 550 };
557 551
558 cpu4_opp18: opp-2419200000 { 552 cpu4_opp18: opp-2419200000 {
559 opp-hz = /bits/ 64 <24 553 opp-hz = /bits/ 64 <2419200000>;
560 opp-peak-kBps = <83680 554 opp-peak-kBps = <8368000 51609600>;
561 }; 555 };
562 }; 556 };
563 557
564 cpu7_opp_table: opp-table-cpu7 { 558 cpu7_opp_table: opp-table-cpu7 {
565 compatible = "operating-points 559 compatible = "operating-points-v2";
566 opp-shared; 560 opp-shared;
567 561
568 cpu7_opp1: opp-844800000 { 562 cpu7_opp1: opp-844800000 {
569 opp-hz = /bits/ 64 <84 563 opp-hz = /bits/ 64 <844800000>;
570 opp-peak-kBps = <21880 564 opp-peak-kBps = <2188000 19660800>;
571 }; 565 };
572 566
573 cpu7_opp2: opp-960000000 { 567 cpu7_opp2: opp-960000000 {
574 opp-hz = /bits/ 64 <96 568 opp-hz = /bits/ 64 <960000000>;
575 opp-peak-kBps = <21880 569 opp-peak-kBps = <2188000 26419200>;
576 }; 570 };
577 571
578 cpu7_opp3: opp-1075200000 { 572 cpu7_opp3: opp-1075200000 {
579 opp-hz = /bits/ 64 <10 573 opp-hz = /bits/ 64 <1075200000>;
580 opp-peak-kBps = <30720 574 opp-peak-kBps = <3072000 26419200>;
581 }; 575 };
582 576
583 cpu7_opp4: opp-1190400000 { 577 cpu7_opp4: opp-1190400000 {
584 opp-hz = /bits/ 64 <11 578 opp-hz = /bits/ 64 <1190400000>;
585 opp-peak-kBps = <30720 579 opp-peak-kBps = <3072000 29491200>;
586 }; 580 };
587 581
588 cpu7_opp5: opp-1305600000 { 582 cpu7_opp5: opp-1305600000 {
589 opp-hz = /bits/ 64 <13 583 opp-hz = /bits/ 64 <1305600000>;
590 opp-peak-kBps = <40680 584 opp-peak-kBps = <4068000 32563200>;
591 }; 585 };
592 586
593 cpu7_opp6: opp-1401600000 { 587 cpu7_opp6: opp-1401600000 {
594 opp-hz = /bits/ 64 <14 588 opp-hz = /bits/ 64 <1401600000>;
595 opp-peak-kBps = <40680 589 opp-peak-kBps = <4068000 32563200>;
596 }; 590 };
597 591
598 cpu7_opp7: opp-1516800000 { 592 cpu7_opp7: opp-1516800000 {
599 opp-hz = /bits/ 64 <15 593 opp-hz = /bits/ 64 <1516800000>;
600 opp-peak-kBps = <40680 594 opp-peak-kBps = <4068000 36249600>;
601 }; 595 };
602 596
603 cpu7_opp8: opp-1632000000 { 597 cpu7_opp8: opp-1632000000 {
604 opp-hz = /bits/ 64 <16 598 opp-hz = /bits/ 64 <1632000000>;
605 opp-peak-kBps = <54120 599 opp-peak-kBps = <5412000 39321600>;
606 }; 600 };
607 601
608 cpu7_opp9: opp-1747200000 { 602 cpu7_opp9: opp-1747200000 {
609 opp-hz = /bits/ 64 <17 603 opp-hz = /bits/ 64 <1708800000>;
610 opp-peak-kBps = <54120 604 opp-peak-kBps = <5412000 42393600>;
611 }; 605 };
612 606
613 cpu7_opp10: opp-1862400000 { 607 cpu7_opp10: opp-1862400000 {
614 opp-hz = /bits/ 64 <18 608 opp-hz = /bits/ 64 <1862400000>;
615 opp-peak-kBps = <62200 609 opp-peak-kBps = <6220000 45465600>;
616 }; 610 };
617 611
618 cpu7_opp11: opp-1977600000 { 612 cpu7_opp11: opp-1977600000 {
619 opp-hz = /bits/ 64 <19 613 opp-hz = /bits/ 64 <1977600000>;
620 opp-peak-kBps = <62200 614 opp-peak-kBps = <6220000 48537600>;
621 }; 615 };
622 616
623 cpu7_opp12: opp-2073600000 { 617 cpu7_opp12: opp-2073600000 {
624 opp-hz = /bits/ 64 <20 618 opp-hz = /bits/ 64 <2073600000>;
625 opp-peak-kBps = <72160 619 opp-peak-kBps = <7216000 48537600>;
626 }; 620 };
627 621
628 cpu7_opp13: opp-2169600000 { 622 cpu7_opp13: opp-2169600000 {
629 opp-hz = /bits/ 64 <21 623 opp-hz = /bits/ 64 <2169600000>;
630 opp-peak-kBps = <72160 624 opp-peak-kBps = <7216000 51609600>;
631 }; 625 };
632 626
633 cpu7_opp14: opp-2265600000 { 627 cpu7_opp14: opp-2265600000 {
634 opp-hz = /bits/ 64 <22 628 opp-hz = /bits/ 64 <2265600000>;
635 opp-peak-kBps = <72160 629 opp-peak-kBps = <7216000 51609600>;
636 }; 630 };
637 631
638 cpu7_opp15: opp-2361600000 { 632 cpu7_opp15: opp-2361600000 {
639 opp-hz = /bits/ 64 <23 633 opp-hz = /bits/ 64 <2361600000>;
640 opp-peak-kBps = <83680 634 opp-peak-kBps = <8368000 51609600>;
641 }; 635 };
642 636
643 cpu7_opp16: opp-2457600000 { 637 cpu7_opp16: opp-2457600000 {
644 opp-hz = /bits/ 64 <24 638 opp-hz = /bits/ 64 <2457600000>;
645 opp-peak-kBps = <83680 639 opp-peak-kBps = <8368000 51609600>;
646 }; 640 };
647 641
648 cpu7_opp17: opp-2553600000 { 642 cpu7_opp17: opp-2553600000 {
649 opp-hz = /bits/ 64 <25 643 opp-hz = /bits/ 64 <2553600000>;
650 opp-peak-kBps = <83680 644 opp-peak-kBps = <8368000 51609600>;
651 }; 645 };
652 646
653 cpu7_opp18: opp-2649600000 { 647 cpu7_opp18: opp-2649600000 {
654 opp-hz = /bits/ 64 <26 648 opp-hz = /bits/ 64 <2649600000>;
655 opp-peak-kBps = <83680 649 opp-peak-kBps = <8368000 51609600>;
656 }; 650 };
657 651
658 cpu7_opp19: opp-2745600000 { 652 cpu7_opp19: opp-2745600000 {
659 opp-hz = /bits/ 64 <27 653 opp-hz = /bits/ 64 <2745600000>;
660 opp-peak-kBps = <83680 654 opp-peak-kBps = <8368000 51609600>;
661 }; 655 };
662 656
663 cpu7_opp20: opp-2841600000 { 657 cpu7_opp20: opp-2841600000 {
664 opp-hz = /bits/ 64 <28 658 opp-hz = /bits/ 64 <2841600000>;
665 opp-peak-kBps = <83680 659 opp-peak-kBps = <8368000 51609600>;
666 }; 660 };
667 }; 661 };
668 662
669 firmware { 663 firmware {
670 scm: scm { 664 scm: scm {
671 compatible = "qcom,scm 665 compatible = "qcom,scm-sm8250", "qcom,scm";
672 qcom,dload-mode = <&tc <<
673 #reset-cells = <1>; 666 #reset-cells = <1>;
674 }; 667 };
675 }; 668 };
676 669
677 memory@80000000 { 670 memory@80000000 {
678 device_type = "memory"; 671 device_type = "memory";
679 /* We expect the bootloader to 672 /* We expect the bootloader to fill in the size */
680 reg = <0x0 0x80000000 0x0 0x0> 673 reg = <0x0 0x80000000 0x0 0x0>;
681 }; 674 };
682 675
683 pmu { 676 pmu {
684 compatible = "arm,armv8-pmuv3" 677 compatible = "arm,armv8-pmuv3";
685 interrupts = <GIC_PPI 7 IRQ_TY 678 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
686 }; 679 };
687 680
688 psci { 681 psci {
689 compatible = "arm,psci-1.0"; 682 compatible = "arm,psci-1.0";
690 method = "smc"; 683 method = "smc";
691 684
692 CPU_PD0: power-domain-cpu0 { 685 CPU_PD0: power-domain-cpu0 {
693 #power-domain-cells = 686 #power-domain-cells = <0>;
694 power-domains = <&CLUS 687 power-domains = <&CLUSTER_PD>;
695 domain-idle-states = < 688 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
696 }; 689 };
697 690
698 CPU_PD1: power-domain-cpu1 { 691 CPU_PD1: power-domain-cpu1 {
699 #power-domain-cells = 692 #power-domain-cells = <0>;
700 power-domains = <&CLUS 693 power-domains = <&CLUSTER_PD>;
701 domain-idle-states = < 694 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
702 }; 695 };
703 696
704 CPU_PD2: power-domain-cpu2 { 697 CPU_PD2: power-domain-cpu2 {
705 #power-domain-cells = 698 #power-domain-cells = <0>;
706 power-domains = <&CLUS 699 power-domains = <&CLUSTER_PD>;
707 domain-idle-states = < 700 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
708 }; 701 };
709 702
710 CPU_PD3: power-domain-cpu3 { 703 CPU_PD3: power-domain-cpu3 {
711 #power-domain-cells = 704 #power-domain-cells = <0>;
712 power-domains = <&CLUS 705 power-domains = <&CLUSTER_PD>;
713 domain-idle-states = < 706 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
714 }; 707 };
715 708
716 CPU_PD4: power-domain-cpu4 { 709 CPU_PD4: power-domain-cpu4 {
717 #power-domain-cells = 710 #power-domain-cells = <0>;
718 power-domains = <&CLUS 711 power-domains = <&CLUSTER_PD>;
719 domain-idle-states = < 712 domain-idle-states = <&BIG_CPU_SLEEP_0>;
720 }; 713 };
721 714
722 CPU_PD5: power-domain-cpu5 { 715 CPU_PD5: power-domain-cpu5 {
723 #power-domain-cells = 716 #power-domain-cells = <0>;
724 power-domains = <&CLUS 717 power-domains = <&CLUSTER_PD>;
725 domain-idle-states = < 718 domain-idle-states = <&BIG_CPU_SLEEP_0>;
726 }; 719 };
727 720
728 CPU_PD6: power-domain-cpu6 { 721 CPU_PD6: power-domain-cpu6 {
729 #power-domain-cells = 722 #power-domain-cells = <0>;
730 power-domains = <&CLUS 723 power-domains = <&CLUSTER_PD>;
731 domain-idle-states = < 724 domain-idle-states = <&BIG_CPU_SLEEP_0>;
732 }; 725 };
733 726
734 CPU_PD7: power-domain-cpu7 { 727 CPU_PD7: power-domain-cpu7 {
735 #power-domain-cells = 728 #power-domain-cells = <0>;
736 power-domains = <&CLUS 729 power-domains = <&CLUSTER_PD>;
737 domain-idle-states = < 730 domain-idle-states = <&BIG_CPU_SLEEP_0>;
738 }; 731 };
739 732
740 CLUSTER_PD: power-domain-cpu-c 733 CLUSTER_PD: power-domain-cpu-cluster0 {
741 #power-domain-cells = 734 #power-domain-cells = <0>;
742 domain-idle-states = < 735 domain-idle-states = <&CLUSTER_SLEEP_0>;
743 }; 736 };
744 }; 737 };
745 738
746 qup_opp_table: opp-table-qup { 739 qup_opp_table: opp-table-qup {
747 compatible = "operating-points 740 compatible = "operating-points-v2";
748 741
749 opp-50000000 { 742 opp-50000000 {
750 opp-hz = /bits/ 64 <50 743 opp-hz = /bits/ 64 <50000000>;
751 required-opps = <&rpmh 744 required-opps = <&rpmhpd_opp_min_svs>;
752 }; 745 };
753 746
754 opp-75000000 { 747 opp-75000000 {
755 opp-hz = /bits/ 64 <75 748 opp-hz = /bits/ 64 <75000000>;
756 required-opps = <&rpmh 749 required-opps = <&rpmhpd_opp_low_svs>;
757 }; 750 };
758 751
759 opp-120000000 { 752 opp-120000000 {
760 opp-hz = /bits/ 64 <12 753 opp-hz = /bits/ 64 <120000000>;
761 required-opps = <&rpmh 754 required-opps = <&rpmhpd_opp_svs>;
762 }; 755 };
763 }; 756 };
764 757
765 reserved-memory { 758 reserved-memory {
766 #address-cells = <2>; 759 #address-cells = <2>;
767 #size-cells = <2>; 760 #size-cells = <2>;
768 ranges; 761 ranges;
769 762
770 hyp_mem: memory@80000000 { 763 hyp_mem: memory@80000000 {
771 reg = <0x0 0x80000000 764 reg = <0x0 0x80000000 0x0 0x600000>;
772 no-map; 765 no-map;
773 }; 766 };
774 767
775 xbl_aop_mem: memory@80700000 { 768 xbl_aop_mem: memory@80700000 {
776 reg = <0x0 0x80700000 769 reg = <0x0 0x80700000 0x0 0x160000>;
777 no-map; 770 no-map;
778 }; 771 };
779 772
780 cmd_db: memory@80860000 { 773 cmd_db: memory@80860000 {
781 compatible = "qcom,cmd 774 compatible = "qcom,cmd-db";
782 reg = <0x0 0x80860000 775 reg = <0x0 0x80860000 0x0 0x20000>;
783 no-map; 776 no-map;
784 }; 777 };
785 778
786 smem_mem: memory@80900000 { 779 smem_mem: memory@80900000 {
787 reg = <0x0 0x80900000 780 reg = <0x0 0x80900000 0x0 0x200000>;
788 no-map; 781 no-map;
789 }; 782 };
790 783
791 removed_mem: memory@80b00000 { 784 removed_mem: memory@80b00000 {
792 reg = <0x0 0x80b00000 785 reg = <0x0 0x80b00000 0x0 0x5300000>;
793 no-map; 786 no-map;
794 }; 787 };
795 788
796 camera_mem: memory@86200000 { 789 camera_mem: memory@86200000 {
797 reg = <0x0 0x86200000 790 reg = <0x0 0x86200000 0x0 0x500000>;
798 no-map; 791 no-map;
799 }; 792 };
800 793
801 wlan_mem: memory@86700000 { 794 wlan_mem: memory@86700000 {
802 reg = <0x0 0x86700000 795 reg = <0x0 0x86700000 0x0 0x100000>;
803 no-map; 796 no-map;
804 }; 797 };
805 798
806 ipa_fw_mem: memory@86800000 { 799 ipa_fw_mem: memory@86800000 {
807 reg = <0x0 0x86800000 800 reg = <0x0 0x86800000 0x0 0x10000>;
808 no-map; 801 no-map;
809 }; 802 };
810 803
811 ipa_gsi_mem: memory@86810000 { 804 ipa_gsi_mem: memory@86810000 {
812 reg = <0x0 0x86810000 805 reg = <0x0 0x86810000 0x0 0xa000>;
813 no-map; 806 no-map;
814 }; 807 };
815 808
816 gpu_mem: memory@8681a000 { 809 gpu_mem: memory@8681a000 {
817 reg = <0x0 0x8681a000 810 reg = <0x0 0x8681a000 0x0 0x2000>;
818 no-map; 811 no-map;
819 }; 812 };
820 813
821 npu_mem: memory@86900000 { 814 npu_mem: memory@86900000 {
822 reg = <0x0 0x86900000 815 reg = <0x0 0x86900000 0x0 0x500000>;
823 no-map; 816 no-map;
824 }; 817 };
825 818
826 video_mem: memory@86e00000 { 819 video_mem: memory@86e00000 {
827 reg = <0x0 0x86e00000 820 reg = <0x0 0x86e00000 0x0 0x500000>;
828 no-map; 821 no-map;
829 }; 822 };
830 823
831 cvp_mem: memory@87300000 { 824 cvp_mem: memory@87300000 {
832 reg = <0x0 0x87300000 825 reg = <0x0 0x87300000 0x0 0x500000>;
833 no-map; 826 no-map;
834 }; 827 };
835 828
836 cdsp_mem: memory@87800000 { 829 cdsp_mem: memory@87800000 {
837 reg = <0x0 0x87800000 830 reg = <0x0 0x87800000 0x0 0x1400000>;
838 no-map; 831 no-map;
839 }; 832 };
840 833
841 slpi_mem: memory@88c00000 { 834 slpi_mem: memory@88c00000 {
842 reg = <0x0 0x88c00000 835 reg = <0x0 0x88c00000 0x0 0x1500000>;
843 no-map; 836 no-map;
844 }; 837 };
845 838
846 adsp_mem: memory@8a100000 { 839 adsp_mem: memory@8a100000 {
847 reg = <0x0 0x8a100000 840 reg = <0x0 0x8a100000 0x0 0x1d00000>;
848 no-map; 841 no-map;
849 }; 842 };
850 843
851 spss_mem: memory@8be00000 { 844 spss_mem: memory@8be00000 {
852 reg = <0x0 0x8be00000 845 reg = <0x0 0x8be00000 0x0 0x100000>;
853 no-map; 846 no-map;
854 }; 847 };
855 848
856 cdsp_secure_heap: memory@8bf00 849 cdsp_secure_heap: memory@8bf00000 {
857 reg = <0x0 0x8bf00000 850 reg = <0x0 0x8bf00000 0x0 0x4600000>;
858 no-map; 851 no-map;
859 }; 852 };
860 }; 853 };
861 854
862 smem { 855 smem {
863 compatible = "qcom,smem"; 856 compatible = "qcom,smem";
864 memory-region = <&smem_mem>; 857 memory-region = <&smem_mem>;
865 hwlocks = <&tcsr_mutex 3>; 858 hwlocks = <&tcsr_mutex 3>;
866 }; 859 };
867 860
868 smp2p-adsp { 861 smp2p-adsp {
869 compatible = "qcom,smp2p"; 862 compatible = "qcom,smp2p";
870 qcom,smem = <443>, <429>; 863 qcom,smem = <443>, <429>;
871 interrupts-extended = <&ipcc I 864 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
872 I 865 IPCC_MPROC_SIGNAL_SMP2P
873 I 866 IRQ_TYPE_EDGE_RISING>;
874 mboxes = <&ipcc IPCC_CLIENT_LP 867 mboxes = <&ipcc IPCC_CLIENT_LPASS
875 IPCC_MPROC_SIG 868 IPCC_MPROC_SIGNAL_SMP2P>;
876 869
877 qcom,local-pid = <0>; 870 qcom,local-pid = <0>;
878 qcom,remote-pid = <2>; 871 qcom,remote-pid = <2>;
879 872
880 smp2p_adsp_out: master-kernel 873 smp2p_adsp_out: master-kernel {
881 qcom,entry-name = "mas 874 qcom,entry-name = "master-kernel";
882 #qcom,smem-state-cells 875 #qcom,smem-state-cells = <1>;
883 }; 876 };
884 877
885 smp2p_adsp_in: slave-kernel { 878 smp2p_adsp_in: slave-kernel {
886 qcom,entry-name = "sla 879 qcom,entry-name = "slave-kernel";
887 interrupt-controller; 880 interrupt-controller;
888 #interrupt-cells = <2> 881 #interrupt-cells = <2>;
889 }; 882 };
890 }; 883 };
891 884
892 smp2p-cdsp { 885 smp2p-cdsp {
893 compatible = "qcom,smp2p"; 886 compatible = "qcom,smp2p";
894 qcom,smem = <94>, <432>; 887 qcom,smem = <94>, <432>;
895 interrupts-extended = <&ipcc I 888 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
896 I 889 IPCC_MPROC_SIGNAL_SMP2P
897 I 890 IRQ_TYPE_EDGE_RISING>;
898 mboxes = <&ipcc IPCC_CLIENT_CD 891 mboxes = <&ipcc IPCC_CLIENT_CDSP
899 IPCC_MPROC_SIG 892 IPCC_MPROC_SIGNAL_SMP2P>;
900 893
901 qcom,local-pid = <0>; 894 qcom,local-pid = <0>;
902 qcom,remote-pid = <5>; 895 qcom,remote-pid = <5>;
903 896
904 smp2p_cdsp_out: master-kernel 897 smp2p_cdsp_out: master-kernel {
905 qcom,entry-name = "mas 898 qcom,entry-name = "master-kernel";
906 #qcom,smem-state-cells 899 #qcom,smem-state-cells = <1>;
907 }; 900 };
908 901
909 smp2p_cdsp_in: slave-kernel { 902 smp2p_cdsp_in: slave-kernel {
910 qcom,entry-name = "sla 903 qcom,entry-name = "slave-kernel";
911 interrupt-controller; 904 interrupt-controller;
912 #interrupt-cells = <2> 905 #interrupt-cells = <2>;
913 }; 906 };
914 }; 907 };
915 908
916 smp2p-slpi { 909 smp2p-slpi {
917 compatible = "qcom,smp2p"; 910 compatible = "qcom,smp2p";
918 qcom,smem = <481>, <430>; 911 qcom,smem = <481>, <430>;
919 interrupts-extended = <&ipcc I 912 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
920 I 913 IPCC_MPROC_SIGNAL_SMP2P
921 I 914 IRQ_TYPE_EDGE_RISING>;
922 mboxes = <&ipcc IPCC_CLIENT_SL 915 mboxes = <&ipcc IPCC_CLIENT_SLPI
923 IPCC_MPROC_SIG 916 IPCC_MPROC_SIGNAL_SMP2P>;
924 917
925 qcom,local-pid = <0>; 918 qcom,local-pid = <0>;
926 qcom,remote-pid = <3>; 919 qcom,remote-pid = <3>;
927 920
928 smp2p_slpi_out: master-kernel 921 smp2p_slpi_out: master-kernel {
929 qcom,entry-name = "mas 922 qcom,entry-name = "master-kernel";
930 #qcom,smem-state-cells 923 #qcom,smem-state-cells = <1>;
931 }; 924 };
932 925
933 smp2p_slpi_in: slave-kernel { 926 smp2p_slpi_in: slave-kernel {
934 qcom,entry-name = "sla 927 qcom,entry-name = "slave-kernel";
935 interrupt-controller; 928 interrupt-controller;
936 #interrupt-cells = <2> 929 #interrupt-cells = <2>;
937 }; 930 };
938 }; 931 };
939 932
940 soc: soc@0 { 933 soc: soc@0 {
941 #address-cells = <2>; 934 #address-cells = <2>;
942 #size-cells = <2>; 935 #size-cells = <2>;
943 ranges = <0 0 0 0 0x10 0>; 936 ranges = <0 0 0 0 0x10 0>;
944 dma-ranges = <0 0 0 0 0x10 0>; 937 dma-ranges = <0 0 0 0 0x10 0>;
945 compatible = "simple-bus"; 938 compatible = "simple-bus";
946 939
947 gcc: clock-controller@100000 { 940 gcc: clock-controller@100000 {
948 compatible = "qcom,gcc 941 compatible = "qcom,gcc-sm8250";
949 reg = <0x0 0x00100000 942 reg = <0x0 0x00100000 0x0 0x1f0000>;
950 #clock-cells = <1>; 943 #clock-cells = <1>;
951 #reset-cells = <1>; 944 #reset-cells = <1>;
952 #power-domain-cells = 945 #power-domain-cells = <1>;
953 clock-names = "bi_tcxo 946 clock-names = "bi_tcxo",
954 "bi_tcxo 947 "bi_tcxo_ao",
955 "sleep_c 948 "sleep_clk";
956 clocks = <&rpmhcc RPMH 949 clocks = <&rpmhcc RPMH_CXO_CLK>,
957 <&rpmhcc RPMH 950 <&rpmhcc RPMH_CXO_CLK_A>,
958 <&sleep_clk>; 951 <&sleep_clk>;
959 }; 952 };
960 953
961 ipcc: mailbox@408000 { 954 ipcc: mailbox@408000 {
962 compatible = "qcom,sm8 955 compatible = "qcom,sm8250-ipcc", "qcom,ipcc";
963 reg = <0 0x00408000 0 956 reg = <0 0x00408000 0 0x1000>;
964 interrupts = <GIC_SPI 957 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
965 interrupt-controller; 958 interrupt-controller;
966 #interrupt-cells = <3> 959 #interrupt-cells = <3>;
967 #mbox-cells = <2>; 960 #mbox-cells = <2>;
968 }; 961 };
969 962
970 qfprom: efuse@784000 { 963 qfprom: efuse@784000 {
971 compatible = "qcom,sm8 964 compatible = "qcom,sm8250-qfprom", "qcom,qfprom";
972 reg = <0 0x00784000 0 965 reg = <0 0x00784000 0 0x8ff>;
973 #address-cells = <1>; 966 #address-cells = <1>;
974 #size-cells = <1>; 967 #size-cells = <1>;
975 968
976 gpu_speed_bin: gpu-spe !! 969 gpu_speed_bin: gpu_speed_bin@19b {
977 reg = <0x19b 0 970 reg = <0x19b 0x1>;
978 bits = <5 3>; 971 bits = <5 3>;
979 }; 972 };
980 }; 973 };
981 974
982 rng: rng@793000 { 975 rng: rng@793000 {
983 compatible = "qcom,prn 976 compatible = "qcom,prng-ee";
984 reg = <0 0x00793000 0 977 reg = <0 0x00793000 0 0x1000>;
985 clocks = <&gcc GCC_PRN 978 clocks = <&gcc GCC_PRNG_AHB_CLK>;
986 clock-names = "core"; 979 clock-names = "core";
987 }; 980 };
988 981
989 gpi_dma2: dma-controller@80000 982 gpi_dma2: dma-controller@800000 {
990 compatible = "qcom,sm8 983 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma";
991 reg = <0 0x00800000 0 984 reg = <0 0x00800000 0 0x70000>;
992 interrupts = <GIC_SPI 985 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
993 <GIC_SPI 986 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
994 <GIC_SPI 987 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
995 <GIC_SPI 988 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
996 <GIC_SPI 989 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
997 <GIC_SPI 990 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
998 <GIC_SPI 991 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
999 <GIC_SPI 992 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
1000 <GIC_SPI 993 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
1001 <GIC_SPI 994 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>;
1002 dma-channels = <10>; 995 dma-channels = <10>;
1003 dma-channel-mask = <0 996 dma-channel-mask = <0x3f>;
1004 iommus = <&apps_smmu 997 iommus = <&apps_smmu 0x76 0x0>;
1005 #dma-cells = <3>; 998 #dma-cells = <3>;
1006 status = "disabled"; 999 status = "disabled";
1007 }; 1000 };
1008 1001
1009 qupv3_id_2: geniqup@8c0000 { 1002 qupv3_id_2: geniqup@8c0000 {
1010 compatible = "qcom,ge 1003 compatible = "qcom,geni-se-qup";
1011 reg = <0x0 0x008c0000 1004 reg = <0x0 0x008c0000 0x0 0x6000>;
1012 clock-names = "m-ahb" 1005 clock-names = "m-ahb", "s-ahb";
1013 clocks = <&gcc GCC_QU 1006 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
1014 <&gcc GCC_QU 1007 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
1015 #address-cells = <2>; 1008 #address-cells = <2>;
1016 #size-cells = <2>; 1009 #size-cells = <2>;
1017 iommus = <&apps_smmu 1010 iommus = <&apps_smmu 0x63 0x0>;
1018 ranges; 1011 ranges;
1019 status = "disabled"; 1012 status = "disabled";
1020 1013
1021 i2c14: i2c@880000 { 1014 i2c14: i2c@880000 {
1022 compatible = 1015 compatible = "qcom,geni-i2c";
1023 reg = <0 0x00 1016 reg = <0 0x00880000 0 0x4000>;
1024 clock-names = 1017 clock-names = "se";
1025 clocks = <&gc 1018 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1026 pinctrl-names 1019 pinctrl-names = "default";
1027 pinctrl-0 = < 1020 pinctrl-0 = <&qup_i2c14_default>;
1028 interrupts = 1021 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1029 dmas = <&gpi_ 1022 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
1030 <&gpi_ 1023 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
1031 dma-names = " 1024 dma-names = "tx", "rx";
1032 power-domains <<
1033 interconnects <<
1034 <<
1035 <<
1036 interconnect- <<
1037 <<
1038 <<
1039 #address-cell 1025 #address-cells = <1>;
1040 #size-cells = 1026 #size-cells = <0>;
1041 status = "dis 1027 status = "disabled";
1042 }; 1028 };
1043 1029
1044 spi14: spi@880000 { 1030 spi14: spi@880000 {
1045 compatible = 1031 compatible = "qcom,geni-spi";
1046 reg = <0 0x00 1032 reg = <0 0x00880000 0 0x4000>;
1047 clock-names = 1033 clock-names = "se";
1048 clocks = <&gc 1034 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1049 interrupts = 1035 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1050 dmas = <&gpi_ 1036 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
1051 <&gpi_ 1037 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
1052 dma-names = " 1038 dma-names = "tx", "rx";
1053 power-domains !! 1039 power-domains = <&rpmhpd SM8250_CX>;
1054 operating-poi 1040 operating-points-v2 = <&qup_opp_table>;
1055 interconnects <<
1056 <<
1057 <<
1058 interconnect- <<
1059 <<
1060 <<
1061 #address-cell 1041 #address-cells = <1>;
1062 #size-cells = 1042 #size-cells = <0>;
1063 status = "dis 1043 status = "disabled";
1064 }; 1044 };
1065 1045
1066 i2c15: i2c@884000 { 1046 i2c15: i2c@884000 {
1067 compatible = 1047 compatible = "qcom,geni-i2c";
1068 reg = <0 0x00 1048 reg = <0 0x00884000 0 0x4000>;
1069 clock-names = 1049 clock-names = "se";
1070 clocks = <&gc 1050 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1071 pinctrl-names 1051 pinctrl-names = "default";
1072 pinctrl-0 = < 1052 pinctrl-0 = <&qup_i2c15_default>;
1073 interrupts = 1053 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1074 dmas = <&gpi_ 1054 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
1075 <&gpi_ 1055 <&gpi_dma2 1 1 QCOM_GPI_I2C>;
1076 dma-names = " 1056 dma-names = "tx", "rx";
1077 power-domains <<
1078 interconnects <<
1079 <<
1080 <<
1081 interconnect- <<
1082 <<
1083 <<
1084 #address-cell 1057 #address-cells = <1>;
1085 #size-cells = 1058 #size-cells = <0>;
1086 status = "dis 1059 status = "disabled";
1087 }; 1060 };
1088 1061
1089 spi15: spi@884000 { 1062 spi15: spi@884000 {
1090 compatible = 1063 compatible = "qcom,geni-spi";
1091 reg = <0 0x00 1064 reg = <0 0x00884000 0 0x4000>;
1092 clock-names = 1065 clock-names = "se";
1093 clocks = <&gc 1066 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1094 interrupts = 1067 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1095 dmas = <&gpi_ 1068 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
1096 <&gpi_ 1069 <&gpi_dma2 1 1 QCOM_GPI_SPI>;
1097 dma-names = " 1070 dma-names = "tx", "rx";
1098 power-domains !! 1071 power-domains = <&rpmhpd SM8250_CX>;
1099 operating-poi 1072 operating-points-v2 = <&qup_opp_table>;
1100 interconnects <<
1101 <<
1102 <<
1103 interconnect- <<
1104 <<
1105 <<
1106 #address-cell 1073 #address-cells = <1>;
1107 #size-cells = 1074 #size-cells = <0>;
1108 status = "dis 1075 status = "disabled";
1109 }; 1076 };
1110 1077
1111 i2c16: i2c@888000 { 1078 i2c16: i2c@888000 {
1112 compatible = 1079 compatible = "qcom,geni-i2c";
1113 reg = <0 0x00 1080 reg = <0 0x00888000 0 0x4000>;
1114 clock-names = 1081 clock-names = "se";
1115 clocks = <&gc 1082 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1116 pinctrl-names 1083 pinctrl-names = "default";
1117 pinctrl-0 = < 1084 pinctrl-0 = <&qup_i2c16_default>;
1118 interrupts = 1085 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1119 dmas = <&gpi_ 1086 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
1120 <&gpi_ 1087 <&gpi_dma2 1 2 QCOM_GPI_I2C>;
1121 dma-names = " 1088 dma-names = "tx", "rx";
1122 power-domains <<
1123 interconnects <<
1124 <<
1125 <<
1126 interconnect- <<
1127 <<
1128 <<
1129 #address-cell 1089 #address-cells = <1>;
1130 #size-cells = 1090 #size-cells = <0>;
1131 status = "dis 1091 status = "disabled";
1132 }; 1092 };
1133 1093
1134 spi16: spi@888000 { 1094 spi16: spi@888000 {
1135 compatible = 1095 compatible = "qcom,geni-spi";
1136 reg = <0 0x00 1096 reg = <0 0x00888000 0 0x4000>;
1137 clock-names = 1097 clock-names = "se";
1138 clocks = <&gc 1098 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1139 interrupts = 1099 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1140 dmas = <&gpi_ 1100 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
1141 <&gpi_ 1101 <&gpi_dma2 1 2 QCOM_GPI_SPI>;
1142 dma-names = " 1102 dma-names = "tx", "rx";
1143 power-domains !! 1103 power-domains = <&rpmhpd SM8250_CX>;
1144 operating-poi 1104 operating-points-v2 = <&qup_opp_table>;
1145 interconnects <<
1146 <<
1147 <<
1148 interconnect- <<
1149 <<
1150 <<
1151 #address-cell 1105 #address-cells = <1>;
1152 #size-cells = 1106 #size-cells = <0>;
1153 status = "dis 1107 status = "disabled";
1154 }; 1108 };
1155 1109
1156 i2c17: i2c@88c000 { 1110 i2c17: i2c@88c000 {
1157 compatible = 1111 compatible = "qcom,geni-i2c";
1158 reg = <0 0x00 1112 reg = <0 0x0088c000 0 0x4000>;
1159 clock-names = 1113 clock-names = "se";
1160 clocks = <&gc 1114 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1161 pinctrl-names 1115 pinctrl-names = "default";
1162 pinctrl-0 = < 1116 pinctrl-0 = <&qup_i2c17_default>;
1163 interrupts = 1117 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1164 dmas = <&gpi_ 1118 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
1165 <&gpi_ 1119 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
1166 dma-names = " 1120 dma-names = "tx", "rx";
1167 power-domains <<
1168 interconnects <<
1169 <<
1170 <<
1171 interconnect- <<
1172 <<
1173 <<
1174 #address-cell 1121 #address-cells = <1>;
1175 #size-cells = 1122 #size-cells = <0>;
1176 status = "dis 1123 status = "disabled";
1177 }; 1124 };
1178 1125
1179 spi17: spi@88c000 { 1126 spi17: spi@88c000 {
1180 compatible = 1127 compatible = "qcom,geni-spi";
1181 reg = <0 0x00 1128 reg = <0 0x0088c000 0 0x4000>;
1182 clock-names = 1129 clock-names = "se";
1183 clocks = <&gc 1130 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1184 interrupts = 1131 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1185 dmas = <&gpi_ 1132 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
1186 <&gpi_ 1133 <&gpi_dma2 1 3 QCOM_GPI_SPI>;
1187 dma-names = " 1134 dma-names = "tx", "rx";
1188 power-domains !! 1135 power-domains = <&rpmhpd SM8250_CX>;
1189 operating-poi 1136 operating-points-v2 = <&qup_opp_table>;
1190 interconnects <<
1191 <<
1192 <<
1193 interconnect- <<
1194 <<
1195 <<
1196 #address-cell 1137 #address-cells = <1>;
1197 #size-cells = 1138 #size-cells = <0>;
1198 status = "dis 1139 status = "disabled";
1199 }; 1140 };
1200 1141
1201 uart17: serial@88c000 1142 uart17: serial@88c000 {
1202 compatible = 1143 compatible = "qcom,geni-uart";
1203 reg = <0 0x00 1144 reg = <0 0x0088c000 0 0x4000>;
1204 clock-names = 1145 clock-names = "se";
1205 clocks = <&gc 1146 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1206 pinctrl-names 1147 pinctrl-names = "default";
1207 pinctrl-0 = < 1148 pinctrl-0 = <&qup_uart17_default>;
1208 interrupts = 1149 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1209 power-domains !! 1150 power-domains = <&rpmhpd SM8250_CX>;
1210 operating-poi 1151 operating-points-v2 = <&qup_opp_table>;
1211 interconnects <<
1212 <<
1213 interconnect- <<
1214 <<
1215 status = "dis 1152 status = "disabled";
1216 }; 1153 };
1217 1154
1218 i2c18: i2c@890000 { 1155 i2c18: i2c@890000 {
1219 compatible = 1156 compatible = "qcom,geni-i2c";
1220 reg = <0 0x00 1157 reg = <0 0x00890000 0 0x4000>;
1221 clock-names = 1158 clock-names = "se";
1222 clocks = <&gc 1159 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1223 pinctrl-names 1160 pinctrl-names = "default";
1224 pinctrl-0 = < 1161 pinctrl-0 = <&qup_i2c18_default>;
1225 interrupts = 1162 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1226 dmas = <&gpi_ 1163 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1227 <&gpi_ 1164 <&gpi_dma2 1 4 QCOM_GPI_I2C>;
1228 dma-names = " 1165 dma-names = "tx", "rx";
1229 power-domains <<
1230 interconnects <<
1231 <<
1232 <<
1233 interconnect- <<
1234 <<
1235 <<
1236 #address-cell 1166 #address-cells = <1>;
1237 #size-cells = 1167 #size-cells = <0>;
1238 status = "dis 1168 status = "disabled";
1239 }; 1169 };
1240 1170
1241 spi18: spi@890000 { 1171 spi18: spi@890000 {
1242 compatible = 1172 compatible = "qcom,geni-spi";
1243 reg = <0 0x00 1173 reg = <0 0x00890000 0 0x4000>;
1244 clock-names = 1174 clock-names = "se";
1245 clocks = <&gc 1175 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1246 interrupts = 1176 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1247 dmas = <&gpi_ 1177 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
1248 <&gpi_ 1178 <&gpi_dma2 1 4 QCOM_GPI_SPI>;
1249 dma-names = " 1179 dma-names = "tx", "rx";
1250 power-domains !! 1180 power-domains = <&rpmhpd SM8250_CX>;
1251 operating-poi 1181 operating-points-v2 = <&qup_opp_table>;
1252 interconnects <<
1253 <<
1254 <<
1255 interconnect- <<
1256 <<
1257 <<
1258 #address-cell 1182 #address-cells = <1>;
1259 #size-cells = 1183 #size-cells = <0>;
1260 status = "dis 1184 status = "disabled";
1261 }; 1185 };
1262 1186
1263 uart18: serial@890000 1187 uart18: serial@890000 {
1264 compatible = 1188 compatible = "qcom,geni-uart";
1265 reg = <0 0x00 1189 reg = <0 0x00890000 0 0x4000>;
1266 clock-names = 1190 clock-names = "se";
1267 clocks = <&gc 1191 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1268 pinctrl-names 1192 pinctrl-names = "default";
1269 pinctrl-0 = < 1193 pinctrl-0 = <&qup_uart18_default>;
1270 interrupts = 1194 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1271 power-domains !! 1195 power-domains = <&rpmhpd SM8250_CX>;
1272 operating-poi 1196 operating-points-v2 = <&qup_opp_table>;
1273 interconnects <<
1274 <<
1275 interconnect- <<
1276 <<
1277 status = "dis 1197 status = "disabled";
1278 }; 1198 };
1279 1199
1280 i2c19: i2c@894000 { 1200 i2c19: i2c@894000 {
1281 compatible = 1201 compatible = "qcom,geni-i2c";
1282 reg = <0 0x00 1202 reg = <0 0x00894000 0 0x4000>;
1283 clock-names = 1203 clock-names = "se";
1284 clocks = <&gc 1204 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1285 pinctrl-names 1205 pinctrl-names = "default";
1286 pinctrl-0 = < 1206 pinctrl-0 = <&qup_i2c19_default>;
1287 interrupts = 1207 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1288 dmas = <&gpi_ 1208 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1289 <&gpi_ 1209 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1290 dma-names = " 1210 dma-names = "tx", "rx";
1291 power-domains <<
1292 interconnects <<
1293 <<
1294 <<
1295 interconnect- <<
1296 <<
1297 <<
1298 #address-cell 1211 #address-cells = <1>;
1299 #size-cells = 1212 #size-cells = <0>;
1300 status = "dis 1213 status = "disabled";
1301 }; 1214 };
1302 1215
1303 spi19: spi@894000 { 1216 spi19: spi@894000 {
1304 compatible = 1217 compatible = "qcom,geni-spi";
1305 reg = <0 0x00 1218 reg = <0 0x00894000 0 0x4000>;
1306 clock-names = 1219 clock-names = "se";
1307 clocks = <&gc 1220 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1308 interrupts = 1221 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1309 dmas = <&gpi_ 1222 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1310 <&gpi_ 1223 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1311 dma-names = " 1224 dma-names = "tx", "rx";
1312 power-domains !! 1225 power-domains = <&rpmhpd SM8250_CX>;
1313 operating-poi 1226 operating-points-v2 = <&qup_opp_table>;
1314 interconnects <<
1315 <<
1316 <<
1317 interconnect- <<
1318 <<
1319 <<
1320 #address-cell 1227 #address-cells = <1>;
1321 #size-cells = 1228 #size-cells = <0>;
1322 status = "dis 1229 status = "disabled";
1323 }; 1230 };
1324 }; 1231 };
1325 1232
1326 gpi_dma0: dma-controller@9000 1233 gpi_dma0: dma-controller@900000 {
1327 compatible = "qcom,sm 1234 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma";
1328 reg = <0 0x00900000 0 1235 reg = <0 0x00900000 0 0x70000>;
1329 interrupts = <GIC_SPI 1236 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
1330 <GIC_SPI 1237 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
1331 <GIC_SPI 1238 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
1332 <GIC_SPI 1239 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
1333 <GIC_SPI 1240 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
1334 <GIC_SPI 1241 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
1335 <GIC_SPI 1242 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
1336 <GIC_SPI 1243 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
1337 <GIC_SPI 1244 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
1338 <GIC_SPI 1245 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
1339 <GIC_SPI 1246 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
1340 <GIC_SPI 1247 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
1341 <GIC_SPI 1248 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
1342 dma-channels = <15>; 1249 dma-channels = <15>;
1343 dma-channel-mask = <0 1250 dma-channel-mask = <0x7ff>;
1344 iommus = <&apps_smmu 1251 iommus = <&apps_smmu 0x5b6 0x0>;
1345 #dma-cells = <3>; 1252 #dma-cells = <3>;
1346 status = "disabled"; 1253 status = "disabled";
1347 }; 1254 };
1348 1255
1349 qupv3_id_0: geniqup@9c0000 { 1256 qupv3_id_0: geniqup@9c0000 {
1350 compatible = "qcom,ge 1257 compatible = "qcom,geni-se-qup";
1351 reg = <0x0 0x009c0000 1258 reg = <0x0 0x009c0000 0x0 0x6000>;
1352 clock-names = "m-ahb" 1259 clock-names = "m-ahb", "s-ahb";
1353 clocks = <&gcc GCC_QU 1260 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1354 <&gcc GCC_QU 1261 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1355 #address-cells = <2>; 1262 #address-cells = <2>;
1356 #size-cells = <2>; 1263 #size-cells = <2>;
1357 iommus = <&apps_smmu 1264 iommus = <&apps_smmu 0x5a3 0x0>;
1358 ranges; 1265 ranges;
1359 status = "disabled"; 1266 status = "disabled";
1360 1267
1361 i2c0: i2c@980000 { 1268 i2c0: i2c@980000 {
1362 compatible = 1269 compatible = "qcom,geni-i2c";
1363 reg = <0 0x00 1270 reg = <0 0x00980000 0 0x4000>;
1364 clock-names = 1271 clock-names = "se";
1365 clocks = <&gc 1272 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1366 pinctrl-names 1273 pinctrl-names = "default";
1367 pinctrl-0 = < 1274 pinctrl-0 = <&qup_i2c0_default>;
1368 interrupts = 1275 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1369 dmas = <&gpi_ 1276 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1370 <&gpi_ 1277 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1371 dma-names = " 1278 dma-names = "tx", "rx";
1372 power-domains <<
1373 interconnects <<
1374 <<
1375 <<
1376 interconnect- <<
1377 <<
1378 <<
1379 #address-cell 1279 #address-cells = <1>;
1380 #size-cells = 1280 #size-cells = <0>;
1381 status = "dis 1281 status = "disabled";
1382 }; 1282 };
1383 1283
1384 spi0: spi@980000 { 1284 spi0: spi@980000 {
1385 compatible = 1285 compatible = "qcom,geni-spi";
1386 reg = <0 0x00 1286 reg = <0 0x00980000 0 0x4000>;
1387 clock-names = 1287 clock-names = "se";
1388 clocks = <&gc 1288 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1389 interrupts = 1289 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1390 dmas = <&gpi_ 1290 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1391 <&gpi_ 1291 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1392 dma-names = " 1292 dma-names = "tx", "rx";
1393 power-domains !! 1293 power-domains = <&rpmhpd SM8250_CX>;
1394 operating-poi 1294 operating-points-v2 = <&qup_opp_table>;
1395 interconnects <<
1396 <<
1397 <<
1398 interconnect- <<
1399 <<
1400 <<
1401 #address-cell 1295 #address-cells = <1>;
1402 #size-cells = 1296 #size-cells = <0>;
1403 status = "dis 1297 status = "disabled";
1404 }; 1298 };
1405 1299
1406 i2c1: i2c@984000 { 1300 i2c1: i2c@984000 {
1407 compatible = 1301 compatible = "qcom,geni-i2c";
1408 reg = <0 0x00 1302 reg = <0 0x00984000 0 0x4000>;
1409 clock-names = 1303 clock-names = "se";
1410 clocks = <&gc 1304 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1411 pinctrl-names 1305 pinctrl-names = "default";
1412 pinctrl-0 = < 1306 pinctrl-0 = <&qup_i2c1_default>;
1413 interrupts = 1307 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1414 dmas = <&gpi_ 1308 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1415 <&gpi_ 1309 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1416 dma-names = " 1310 dma-names = "tx", "rx";
1417 power-domains <<
1418 interconnects <<
1419 <<
1420 <<
1421 interconnect- <<
1422 <<
1423 <<
1424 #address-cell 1311 #address-cells = <1>;
1425 #size-cells = 1312 #size-cells = <0>;
1426 status = "dis 1313 status = "disabled";
1427 }; 1314 };
1428 1315
1429 spi1: spi@984000 { 1316 spi1: spi@984000 {
1430 compatible = 1317 compatible = "qcom,geni-spi";
1431 reg = <0 0x00 1318 reg = <0 0x00984000 0 0x4000>;
1432 clock-names = 1319 clock-names = "se";
1433 clocks = <&gc 1320 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1434 interrupts = 1321 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1435 dmas = <&gpi_ 1322 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1436 <&gpi_ 1323 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1437 dma-names = " 1324 dma-names = "tx", "rx";
1438 power-domains !! 1325 power-domains = <&rpmhpd SM8250_CX>;
1439 operating-poi 1326 operating-points-v2 = <&qup_opp_table>;
1440 interconnects <<
1441 <<
1442 <<
1443 interconnect- <<
1444 <<
1445 <<
1446 #address-cell 1327 #address-cells = <1>;
1447 #size-cells = 1328 #size-cells = <0>;
1448 status = "dis 1329 status = "disabled";
1449 }; 1330 };
1450 1331
1451 i2c2: i2c@988000 { 1332 i2c2: i2c@988000 {
1452 compatible = 1333 compatible = "qcom,geni-i2c";
1453 reg = <0 0x00 1334 reg = <0 0x00988000 0 0x4000>;
1454 clock-names = 1335 clock-names = "se";
1455 clocks = <&gc 1336 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1456 pinctrl-names 1337 pinctrl-names = "default";
1457 pinctrl-0 = < 1338 pinctrl-0 = <&qup_i2c2_default>;
1458 interrupts = 1339 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1459 dmas = <&gpi_ 1340 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1460 <&gpi_ 1341 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1461 dma-names = " 1342 dma-names = "tx", "rx";
1462 power-domains <<
1463 interconnects <<
1464 <<
1465 <<
1466 interconnect- <<
1467 <<
1468 <<
1469 #address-cell 1343 #address-cells = <1>;
1470 #size-cells = 1344 #size-cells = <0>;
1471 status = "dis 1345 status = "disabled";
1472 }; 1346 };
1473 1347
1474 spi2: spi@988000 { 1348 spi2: spi@988000 {
1475 compatible = 1349 compatible = "qcom,geni-spi";
1476 reg = <0 0x00 1350 reg = <0 0x00988000 0 0x4000>;
1477 clock-names = 1351 clock-names = "se";
1478 clocks = <&gc 1352 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1479 interrupts = 1353 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1480 dmas = <&gpi_ 1354 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1481 <&gpi_ 1355 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1482 dma-names = " 1356 dma-names = "tx", "rx";
1483 power-domains !! 1357 power-domains = <&rpmhpd SM8250_CX>;
1484 operating-poi 1358 operating-points-v2 = <&qup_opp_table>;
1485 interconnects <<
1486 <<
1487 <<
1488 interconnect- <<
1489 <<
1490 <<
1491 #address-cell 1359 #address-cells = <1>;
1492 #size-cells = 1360 #size-cells = <0>;
1493 status = "dis 1361 status = "disabled";
1494 }; 1362 };
1495 1363
1496 uart2: serial@988000 1364 uart2: serial@988000 {
1497 compatible = 1365 compatible = "qcom,geni-debug-uart";
1498 reg = <0 0x00 1366 reg = <0 0x00988000 0 0x4000>;
1499 clock-names = 1367 clock-names = "se";
1500 clocks = <&gc 1368 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1501 pinctrl-names 1369 pinctrl-names = "default";
1502 pinctrl-0 = < 1370 pinctrl-0 = <&qup_uart2_default>;
1503 interrupts = 1371 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1504 power-domains !! 1372 power-domains = <&rpmhpd SM8250_CX>;
1505 operating-poi 1373 operating-points-v2 = <&qup_opp_table>;
1506 interconnects <<
1507 <<
1508 interconnect- <<
1509 <<
1510 status = "dis 1374 status = "disabled";
1511 }; 1375 };
1512 1376
1513 i2c3: i2c@98c000 { 1377 i2c3: i2c@98c000 {
1514 compatible = 1378 compatible = "qcom,geni-i2c";
1515 reg = <0 0x00 1379 reg = <0 0x0098c000 0 0x4000>;
1516 clock-names = 1380 clock-names = "se";
1517 clocks = <&gc 1381 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1518 pinctrl-names 1382 pinctrl-names = "default";
1519 pinctrl-0 = < 1383 pinctrl-0 = <&qup_i2c3_default>;
1520 interrupts = 1384 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1521 dmas = <&gpi_ 1385 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1522 <&gpi_ 1386 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1523 dma-names = " 1387 dma-names = "tx", "rx";
1524 power-domains <<
1525 interconnects <<
1526 <<
1527 <<
1528 interconnect- <<
1529 <<
1530 <<
1531 #address-cell 1388 #address-cells = <1>;
1532 #size-cells = 1389 #size-cells = <0>;
1533 status = "dis 1390 status = "disabled";
1534 }; 1391 };
1535 1392
1536 spi3: spi@98c000 { 1393 spi3: spi@98c000 {
1537 compatible = 1394 compatible = "qcom,geni-spi";
1538 reg = <0 0x00 1395 reg = <0 0x0098c000 0 0x4000>;
1539 clock-names = 1396 clock-names = "se";
1540 clocks = <&gc 1397 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1541 interrupts = 1398 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1542 dmas = <&gpi_ 1399 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1543 <&gpi_ 1400 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1544 dma-names = " 1401 dma-names = "tx", "rx";
1545 power-domains !! 1402 power-domains = <&rpmhpd SM8250_CX>;
1546 operating-poi 1403 operating-points-v2 = <&qup_opp_table>;
1547 interconnects <<
1548 <<
1549 <<
1550 interconnect- <<
1551 <<
1552 <<
1553 #address-cell 1404 #address-cells = <1>;
1554 #size-cells = 1405 #size-cells = <0>;
1555 status = "dis 1406 status = "disabled";
1556 }; 1407 };
1557 1408
1558 i2c4: i2c@990000 { 1409 i2c4: i2c@990000 {
1559 compatible = 1410 compatible = "qcom,geni-i2c";
1560 reg = <0 0x00 1411 reg = <0 0x00990000 0 0x4000>;
1561 clock-names = 1412 clock-names = "se";
1562 clocks = <&gc 1413 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1563 pinctrl-names 1414 pinctrl-names = "default";
1564 pinctrl-0 = < 1415 pinctrl-0 = <&qup_i2c4_default>;
1565 interrupts = 1416 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1566 dmas = <&gpi_ 1417 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1567 <&gpi_ 1418 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1568 dma-names = " 1419 dma-names = "tx", "rx";
1569 power-domains <<
1570 interconnects <<
1571 <<
1572 <<
1573 interconnect- <<
1574 <<
1575 <<
1576 #address-cell 1420 #address-cells = <1>;
1577 #size-cells = 1421 #size-cells = <0>;
1578 status = "dis 1422 status = "disabled";
1579 }; 1423 };
1580 1424
1581 spi4: spi@990000 { 1425 spi4: spi@990000 {
1582 compatible = 1426 compatible = "qcom,geni-spi";
1583 reg = <0 0x00 1427 reg = <0 0x00990000 0 0x4000>;
1584 clock-names = 1428 clock-names = "se";
1585 clocks = <&gc 1429 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1586 interrupts = 1430 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1587 dmas = <&gpi_ 1431 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1588 <&gpi_ 1432 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1589 dma-names = " 1433 dma-names = "tx", "rx";
1590 power-domains !! 1434 power-domains = <&rpmhpd SM8250_CX>;
1591 operating-poi 1435 operating-points-v2 = <&qup_opp_table>;
1592 interconnects <<
1593 <<
1594 <<
1595 interconnect- <<
1596 <<
1597 <<
1598 #address-cell 1436 #address-cells = <1>;
1599 #size-cells = 1437 #size-cells = <0>;
1600 status = "dis 1438 status = "disabled";
1601 }; 1439 };
1602 1440
1603 i2c5: i2c@994000 { 1441 i2c5: i2c@994000 {
1604 compatible = 1442 compatible = "qcom,geni-i2c";
1605 reg = <0 0x00 1443 reg = <0 0x00994000 0 0x4000>;
1606 clock-names = 1444 clock-names = "se";
1607 clocks = <&gc 1445 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1608 pinctrl-names 1446 pinctrl-names = "default";
1609 pinctrl-0 = < 1447 pinctrl-0 = <&qup_i2c5_default>;
1610 interrupts = 1448 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1611 dmas = <&gpi_ 1449 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1612 <&gpi_ 1450 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1613 dma-names = " 1451 dma-names = "tx", "rx";
1614 power-domains <<
1615 interconnects <<
1616 <<
1617 <<
1618 interconnect- <<
1619 <<
1620 <<
1621 #address-cell 1452 #address-cells = <1>;
1622 #size-cells = 1453 #size-cells = <0>;
1623 status = "dis 1454 status = "disabled";
1624 }; 1455 };
1625 1456
1626 spi5: spi@994000 { 1457 spi5: spi@994000 {
1627 compatible = 1458 compatible = "qcom,geni-spi";
1628 reg = <0 0x00 1459 reg = <0 0x00994000 0 0x4000>;
1629 clock-names = 1460 clock-names = "se";
1630 clocks = <&gc 1461 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1631 interrupts = 1462 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1632 dmas = <&gpi_ 1463 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1633 <&gpi_ 1464 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1634 dma-names = " 1465 dma-names = "tx", "rx";
1635 power-domains !! 1466 power-domains = <&rpmhpd SM8250_CX>;
1636 operating-poi 1467 operating-points-v2 = <&qup_opp_table>;
1637 interconnects <<
1638 <<
1639 <<
1640 interconnect- <<
1641 <<
1642 <<
1643 #address-cell 1468 #address-cells = <1>;
1644 #size-cells = 1469 #size-cells = <0>;
1645 status = "dis 1470 status = "disabled";
1646 }; 1471 };
1647 1472
1648 i2c6: i2c@998000 { 1473 i2c6: i2c@998000 {
1649 compatible = 1474 compatible = "qcom,geni-i2c";
1650 reg = <0 0x00 1475 reg = <0 0x00998000 0 0x4000>;
1651 clock-names = 1476 clock-names = "se";
1652 clocks = <&gc 1477 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1653 pinctrl-names 1478 pinctrl-names = "default";
1654 pinctrl-0 = < 1479 pinctrl-0 = <&qup_i2c6_default>;
1655 interrupts = 1480 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1656 dmas = <&gpi_ 1481 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1657 <&gpi_ 1482 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1658 dma-names = " 1483 dma-names = "tx", "rx";
1659 power-domains <<
1660 interconnects <<
1661 <<
1662 <<
1663 interconnect- <<
1664 <<
1665 <<
1666 #address-cell 1484 #address-cells = <1>;
1667 #size-cells = 1485 #size-cells = <0>;
1668 status = "dis 1486 status = "disabled";
1669 }; 1487 };
1670 1488
1671 spi6: spi@998000 { 1489 spi6: spi@998000 {
1672 compatible = 1490 compatible = "qcom,geni-spi";
1673 reg = <0 0x00 1491 reg = <0 0x00998000 0 0x4000>;
1674 clock-names = 1492 clock-names = "se";
1675 clocks = <&gc 1493 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1676 interrupts = 1494 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1677 dmas = <&gpi_ 1495 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1678 <&gpi_ 1496 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1679 dma-names = " 1497 dma-names = "tx", "rx";
1680 power-domains !! 1498 power-domains = <&rpmhpd SM8250_CX>;
1681 operating-poi 1499 operating-points-v2 = <&qup_opp_table>;
1682 interconnects <<
1683 <<
1684 <<
1685 interconnect- <<
1686 <<
1687 <<
1688 #address-cell 1500 #address-cells = <1>;
1689 #size-cells = 1501 #size-cells = <0>;
1690 status = "dis 1502 status = "disabled";
1691 }; 1503 };
1692 1504
1693 uart6: serial@998000 1505 uart6: serial@998000 {
1694 compatible = 1506 compatible = "qcom,geni-uart";
1695 reg = <0 0x00 1507 reg = <0 0x00998000 0 0x4000>;
1696 clock-names = 1508 clock-names = "se";
1697 clocks = <&gc 1509 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1698 pinctrl-names 1510 pinctrl-names = "default";
1699 pinctrl-0 = < 1511 pinctrl-0 = <&qup_uart6_default>;
1700 interrupts = 1512 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1701 power-domains !! 1513 power-domains = <&rpmhpd SM8250_CX>;
1702 operating-poi 1514 operating-points-v2 = <&qup_opp_table>;
1703 interconnects <<
1704 <<
1705 interconnect- <<
1706 <<
1707 status = "dis 1515 status = "disabled";
1708 }; 1516 };
1709 1517
1710 i2c7: i2c@99c000 { 1518 i2c7: i2c@99c000 {
1711 compatible = 1519 compatible = "qcom,geni-i2c";
1712 reg = <0 0x00 1520 reg = <0 0x0099c000 0 0x4000>;
1713 clock-names = 1521 clock-names = "se";
1714 clocks = <&gc 1522 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1715 pinctrl-names 1523 pinctrl-names = "default";
1716 pinctrl-0 = < 1524 pinctrl-0 = <&qup_i2c7_default>;
1717 interrupts = 1525 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1718 dmas = <&gpi_ 1526 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1719 <&gpi_ 1527 <&gpi_dma0 1 7 QCOM_GPI_I2C>;
1720 dma-names = " 1528 dma-names = "tx", "rx";
1721 power-domains <<
1722 interconnects <<
1723 <<
1724 <<
1725 interconnect- <<
1726 <<
1727 <<
1728 #address-cell 1529 #address-cells = <1>;
1729 #size-cells = 1530 #size-cells = <0>;
1730 status = "dis 1531 status = "disabled";
1731 }; 1532 };
1732 1533
1733 spi7: spi@99c000 { 1534 spi7: spi@99c000 {
1734 compatible = 1535 compatible = "qcom,geni-spi";
1735 reg = <0 0x00 1536 reg = <0 0x0099c000 0 0x4000>;
1736 clock-names = 1537 clock-names = "se";
1737 clocks = <&gc 1538 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1738 interrupts = 1539 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1739 dmas = <&gpi_ 1540 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1740 <&gpi_ 1541 <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1741 dma-names = " 1542 dma-names = "tx", "rx";
1742 power-domains !! 1543 power-domains = <&rpmhpd SM8250_CX>;
1743 operating-poi 1544 operating-points-v2 = <&qup_opp_table>;
1744 interconnects <<
1745 <<
1746 <<
1747 interconnect- <<
1748 <<
1749 <<
1750 #address-cell 1545 #address-cells = <1>;
1751 #size-cells = 1546 #size-cells = <0>;
1752 status = "dis 1547 status = "disabled";
1753 }; 1548 };
1754 }; 1549 };
1755 1550
1756 gpi_dma1: dma-controller@a000 1551 gpi_dma1: dma-controller@a00000 {
1757 compatible = "qcom,sm 1552 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma";
1758 reg = <0 0x00a00000 0 1553 reg = <0 0x00a00000 0 0x70000>;
1759 interrupts = <GIC_SPI 1554 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1760 <GIC_SPI 1555 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1761 <GIC_SPI 1556 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1762 <GIC_SPI 1557 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1763 <GIC_SPI 1558 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1764 <GIC_SPI 1559 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1765 <GIC_SPI 1560 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1766 <GIC_SPI 1561 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1767 <GIC_SPI 1562 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1768 <GIC_SPI 1563 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>;
1769 dma-channels = <10>; 1564 dma-channels = <10>;
1770 dma-channel-mask = <0 1565 dma-channel-mask = <0x3f>;
1771 iommus = <&apps_smmu 1566 iommus = <&apps_smmu 0x56 0x0>;
1772 #dma-cells = <3>; 1567 #dma-cells = <3>;
1773 status = "disabled"; 1568 status = "disabled";
1774 }; 1569 };
1775 1570
1776 qupv3_id_1: geniqup@ac0000 { 1571 qupv3_id_1: geniqup@ac0000 {
1777 compatible = "qcom,ge 1572 compatible = "qcom,geni-se-qup";
1778 reg = <0x0 0x00ac0000 1573 reg = <0x0 0x00ac0000 0x0 0x6000>;
1779 clock-names = "m-ahb" 1574 clock-names = "m-ahb", "s-ahb";
1780 clocks = <&gcc GCC_QU 1575 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1781 <&gcc GCC_QU 1576 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1782 #address-cells = <2>; 1577 #address-cells = <2>;
1783 #size-cells = <2>; 1578 #size-cells = <2>;
1784 iommus = <&apps_smmu 1579 iommus = <&apps_smmu 0x43 0x0>;
1785 ranges; 1580 ranges;
1786 status = "disabled"; 1581 status = "disabled";
1787 1582
1788 i2c8: i2c@a80000 { 1583 i2c8: i2c@a80000 {
1789 compatible = 1584 compatible = "qcom,geni-i2c";
1790 reg = <0 0x00 1585 reg = <0 0x00a80000 0 0x4000>;
1791 clock-names = 1586 clock-names = "se";
1792 clocks = <&gc 1587 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1793 pinctrl-names 1588 pinctrl-names = "default";
1794 pinctrl-0 = < 1589 pinctrl-0 = <&qup_i2c8_default>;
1795 interrupts = 1590 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1796 dmas = <&gpi_ 1591 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1797 <&gpi_ 1592 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1798 dma-names = " 1593 dma-names = "tx", "rx";
1799 power-domains <<
1800 interconnects <<
1801 <<
1802 <<
1803 interconnect- <<
1804 <<
1805 <<
1806 #address-cell 1594 #address-cells = <1>;
1807 #size-cells = 1595 #size-cells = <0>;
1808 status = "dis 1596 status = "disabled";
1809 }; 1597 };
1810 1598
1811 spi8: spi@a80000 { 1599 spi8: spi@a80000 {
1812 compatible = 1600 compatible = "qcom,geni-spi";
1813 reg = <0 0x00 1601 reg = <0 0x00a80000 0 0x4000>;
1814 clock-names = 1602 clock-names = "se";
1815 clocks = <&gc 1603 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1816 interrupts = 1604 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1817 dmas = <&gpi_ 1605 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1818 <&gpi_ 1606 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1819 dma-names = " 1607 dma-names = "tx", "rx";
1820 power-domains !! 1608 power-domains = <&rpmhpd SM8250_CX>;
1821 operating-poi 1609 operating-points-v2 = <&qup_opp_table>;
1822 interconnects <<
1823 <<
1824 <<
1825 interconnect- <<
1826 <<
1827 <<
1828 #address-cell 1610 #address-cells = <1>;
1829 #size-cells = 1611 #size-cells = <0>;
1830 status = "dis 1612 status = "disabled";
1831 }; 1613 };
1832 1614
1833 i2c9: i2c@a84000 { 1615 i2c9: i2c@a84000 {
1834 compatible = 1616 compatible = "qcom,geni-i2c";
1835 reg = <0 0x00 1617 reg = <0 0x00a84000 0 0x4000>;
1836 clock-names = 1618 clock-names = "se";
1837 clocks = <&gc 1619 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1838 pinctrl-names 1620 pinctrl-names = "default";
1839 pinctrl-0 = < 1621 pinctrl-0 = <&qup_i2c9_default>;
1840 interrupts = 1622 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1841 dmas = <&gpi_ 1623 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1842 <&gpi_ 1624 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1843 dma-names = " 1625 dma-names = "tx", "rx";
1844 power-domains <<
1845 interconnects <<
1846 <<
1847 <<
1848 interconnect- <<
1849 <<
1850 <<
1851 #address-cell 1626 #address-cells = <1>;
1852 #size-cells = 1627 #size-cells = <0>;
1853 status = "dis 1628 status = "disabled";
1854 }; 1629 };
1855 1630
1856 spi9: spi@a84000 { 1631 spi9: spi@a84000 {
1857 compatible = 1632 compatible = "qcom,geni-spi";
1858 reg = <0 0x00 1633 reg = <0 0x00a84000 0 0x4000>;
1859 clock-names = 1634 clock-names = "se";
1860 clocks = <&gc 1635 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1861 interrupts = 1636 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1862 dmas = <&gpi_ 1637 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1863 <&gpi_ 1638 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1864 dma-names = " 1639 dma-names = "tx", "rx";
1865 power-domains !! 1640 power-domains = <&rpmhpd SM8250_CX>;
1866 operating-poi 1641 operating-points-v2 = <&qup_opp_table>;
1867 interconnects <<
1868 <<
1869 <<
1870 interconnect- <<
1871 <<
1872 <<
1873 #address-cell 1642 #address-cells = <1>;
1874 #size-cells = 1643 #size-cells = <0>;
1875 status = "dis 1644 status = "disabled";
1876 }; 1645 };
1877 1646
1878 i2c10: i2c@a88000 { 1647 i2c10: i2c@a88000 {
1879 compatible = 1648 compatible = "qcom,geni-i2c";
1880 reg = <0 0x00 1649 reg = <0 0x00a88000 0 0x4000>;
1881 clock-names = 1650 clock-names = "se";
1882 clocks = <&gc 1651 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1883 pinctrl-names 1652 pinctrl-names = "default";
1884 pinctrl-0 = < 1653 pinctrl-0 = <&qup_i2c10_default>;
1885 interrupts = 1654 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1886 dmas = <&gpi_ 1655 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1887 <&gpi_ 1656 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1888 dma-names = " 1657 dma-names = "tx", "rx";
1889 power-domains <<
1890 interconnects <<
1891 <<
1892 <<
1893 interconnect- <<
1894 <<
1895 <<
1896 #address-cell 1658 #address-cells = <1>;
1897 #size-cells = 1659 #size-cells = <0>;
1898 status = "dis 1660 status = "disabled";
1899 }; 1661 };
1900 1662
1901 spi10: spi@a88000 { 1663 spi10: spi@a88000 {
1902 compatible = 1664 compatible = "qcom,geni-spi";
1903 reg = <0 0x00 1665 reg = <0 0x00a88000 0 0x4000>;
1904 clock-names = 1666 clock-names = "se";
1905 clocks = <&gc 1667 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1906 interrupts = 1668 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1907 dmas = <&gpi_ 1669 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1908 <&gpi_ 1670 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1909 dma-names = " 1671 dma-names = "tx", "rx";
1910 power-domains !! 1672 power-domains = <&rpmhpd SM8250_CX>;
1911 operating-poi 1673 operating-points-v2 = <&qup_opp_table>;
1912 interconnects <<
1913 <<
1914 <<
1915 interconnect- <<
1916 <<
1917 <<
1918 #address-cell 1674 #address-cells = <1>;
1919 #size-cells = 1675 #size-cells = <0>;
1920 status = "dis 1676 status = "disabled";
1921 }; 1677 };
1922 1678
1923 i2c11: i2c@a8c000 { 1679 i2c11: i2c@a8c000 {
1924 compatible = 1680 compatible = "qcom,geni-i2c";
1925 reg = <0 0x00 1681 reg = <0 0x00a8c000 0 0x4000>;
1926 clock-names = 1682 clock-names = "se";
1927 clocks = <&gc 1683 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1928 pinctrl-names 1684 pinctrl-names = "default";
1929 pinctrl-0 = < 1685 pinctrl-0 = <&qup_i2c11_default>;
1930 interrupts = 1686 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1931 dmas = <&gpi_ 1687 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1932 <&gpi_ 1688 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1933 dma-names = " 1689 dma-names = "tx", "rx";
1934 power-domains <<
1935 interconnects <<
1936 <<
1937 <<
1938 interconnect- <<
1939 <<
1940 <<
1941 #address-cell 1690 #address-cells = <1>;
1942 #size-cells = 1691 #size-cells = <0>;
1943 status = "dis 1692 status = "disabled";
1944 }; 1693 };
1945 1694
1946 spi11: spi@a8c000 { 1695 spi11: spi@a8c000 {
1947 compatible = 1696 compatible = "qcom,geni-spi";
1948 reg = <0 0x00 1697 reg = <0 0x00a8c000 0 0x4000>;
1949 clock-names = 1698 clock-names = "se";
1950 clocks = <&gc 1699 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1951 interrupts = 1700 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1952 dmas = <&gpi_ 1701 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1953 <&gpi_ 1702 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1954 dma-names = " 1703 dma-names = "tx", "rx";
1955 power-domains !! 1704 power-domains = <&rpmhpd SM8250_CX>;
1956 operating-poi 1705 operating-points-v2 = <&qup_opp_table>;
1957 interconnects <<
1958 <<
1959 <<
1960 interconnect- <<
1961 <<
1962 <<
1963 #address-cell 1706 #address-cells = <1>;
1964 #size-cells = 1707 #size-cells = <0>;
1965 status = "dis 1708 status = "disabled";
1966 }; 1709 };
1967 1710
1968 i2c12: i2c@a90000 { 1711 i2c12: i2c@a90000 {
1969 compatible = 1712 compatible = "qcom,geni-i2c";
1970 reg = <0 0x00 1713 reg = <0 0x00a90000 0 0x4000>;
1971 clock-names = 1714 clock-names = "se";
1972 clocks = <&gc 1715 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1973 pinctrl-names 1716 pinctrl-names = "default";
1974 pinctrl-0 = < 1717 pinctrl-0 = <&qup_i2c12_default>;
1975 interrupts = 1718 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1976 dmas = <&gpi_ 1719 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1977 <&gpi_ 1720 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1978 dma-names = " 1721 dma-names = "tx", "rx";
1979 power-domains <<
1980 interconnects <<
1981 <<
1982 <<
1983 interconnect- <<
1984 <<
1985 <<
1986 #address-cell 1722 #address-cells = <1>;
1987 #size-cells = 1723 #size-cells = <0>;
1988 status = "dis 1724 status = "disabled";
1989 }; 1725 };
1990 1726
1991 spi12: spi@a90000 { 1727 spi12: spi@a90000 {
1992 compatible = 1728 compatible = "qcom,geni-spi";
1993 reg = <0 0x00 1729 reg = <0 0x00a90000 0 0x4000>;
1994 clock-names = 1730 clock-names = "se";
1995 clocks = <&gc 1731 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1996 interrupts = 1732 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1997 dmas = <&gpi_ 1733 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1998 <&gpi_ 1734 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1999 dma-names = " 1735 dma-names = "tx", "rx";
2000 power-domains !! 1736 power-domains = <&rpmhpd SM8250_CX>;
2001 operating-poi 1737 operating-points-v2 = <&qup_opp_table>;
2002 interconnects <<
2003 <<
2004 <<
2005 interconnect- <<
2006 <<
2007 <<
2008 #address-cell 1738 #address-cells = <1>;
2009 #size-cells = 1739 #size-cells = <0>;
2010 status = "dis 1740 status = "disabled";
2011 }; 1741 };
2012 1742
2013 uart12: serial@a90000 1743 uart12: serial@a90000 {
2014 compatible = 1744 compatible = "qcom,geni-debug-uart";
2015 reg = <0x0 0x 1745 reg = <0x0 0x00a90000 0x0 0x4000>;
2016 clock-names = 1746 clock-names = "se";
2017 clocks = <&gc 1747 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
2018 pinctrl-names 1748 pinctrl-names = "default";
2019 pinctrl-0 = < 1749 pinctrl-0 = <&qup_uart12_default>;
2020 interrupts = 1750 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
2021 power-domains !! 1751 power-domains = <&rpmhpd SM8250_CX>;
2022 operating-poi 1752 operating-points-v2 = <&qup_opp_table>;
2023 interconnects <<
2024 <<
2025 interconnect- <<
2026 <<
2027 status = "dis 1753 status = "disabled";
2028 }; 1754 };
2029 1755
2030 i2c13: i2c@a94000 { 1756 i2c13: i2c@a94000 {
2031 compatible = 1757 compatible = "qcom,geni-i2c";
2032 reg = <0 0x00 1758 reg = <0 0x00a94000 0 0x4000>;
2033 clock-names = 1759 clock-names = "se";
2034 clocks = <&gc 1760 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2035 pinctrl-names 1761 pinctrl-names = "default";
2036 pinctrl-0 = < 1762 pinctrl-0 = <&qup_i2c13_default>;
2037 interrupts = 1763 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2038 dmas = <&gpi_ 1764 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
2039 <&gpi_ 1765 <&gpi_dma1 1 5 QCOM_GPI_I2C>;
2040 dma-names = " 1766 dma-names = "tx", "rx";
2041 power-domains <<
2042 interconnects <<
2043 <<
2044 <<
2045 interconnect- <<
2046 <<
2047 <<
2048 #address-cell 1767 #address-cells = <1>;
2049 #size-cells = 1768 #size-cells = <0>;
2050 status = "dis 1769 status = "disabled";
2051 }; 1770 };
2052 1771
2053 spi13: spi@a94000 { 1772 spi13: spi@a94000 {
2054 compatible = 1773 compatible = "qcom,geni-spi";
2055 reg = <0 0x00 1774 reg = <0 0x00a94000 0 0x4000>;
2056 clock-names = 1775 clock-names = "se";
2057 clocks = <&gc 1776 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2058 interrupts = 1777 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2059 dmas = <&gpi_ 1778 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
2060 <&gpi_ 1779 <&gpi_dma1 1 5 QCOM_GPI_SPI>;
2061 dma-names = " 1780 dma-names = "tx", "rx";
2062 power-domains !! 1781 power-domains = <&rpmhpd SM8250_CX>;
2063 operating-poi 1782 operating-points-v2 = <&qup_opp_table>;
2064 interconnects <<
2065 <<
2066 <<
2067 interconnect- <<
2068 <<
2069 <<
2070 #address-cell 1783 #address-cells = <1>;
2071 #size-cells = 1784 #size-cells = <0>;
2072 status = "dis 1785 status = "disabled";
2073 }; 1786 };
2074 }; 1787 };
2075 1788
2076 config_noc: interconnect@1500 1789 config_noc: interconnect@1500000 {
2077 compatible = "qcom,sm 1790 compatible = "qcom,sm8250-config-noc";
2078 reg = <0 0x01500000 0 1791 reg = <0 0x01500000 0 0xa580>;
2079 #interconnect-cells = 1792 #interconnect-cells = <2>;
2080 qcom,bcm-voters = <&a 1793 qcom,bcm-voters = <&apps_bcm_voter>;
2081 }; 1794 };
2082 1795
2083 system_noc: interconnect@1620 1796 system_noc: interconnect@1620000 {
2084 compatible = "qcom,sm 1797 compatible = "qcom,sm8250-system-noc";
2085 reg = <0 0x01620000 0 1798 reg = <0 0x01620000 0 0x1c200>;
2086 #interconnect-cells = 1799 #interconnect-cells = <2>;
2087 qcom,bcm-voters = <&a 1800 qcom,bcm-voters = <&apps_bcm_voter>;
2088 }; 1801 };
2089 1802
2090 mc_virt: interconnect@163d000 1803 mc_virt: interconnect@163d000 {
2091 compatible = "qcom,sm 1804 compatible = "qcom,sm8250-mc-virt";
2092 reg = <0 0x0163d000 0 1805 reg = <0 0x0163d000 0 0x1000>;
2093 #interconnect-cells = 1806 #interconnect-cells = <2>;
2094 qcom,bcm-voters = <&a 1807 qcom,bcm-voters = <&apps_bcm_voter>;
2095 }; 1808 };
2096 1809
2097 aggre1_noc: interconnect@16e0 1810 aggre1_noc: interconnect@16e0000 {
2098 compatible = "qcom,sm 1811 compatible = "qcom,sm8250-aggre1-noc";
2099 reg = <0 0x016e0000 0 1812 reg = <0 0x016e0000 0 0x1f180>;
2100 #interconnect-cells = 1813 #interconnect-cells = <2>;
2101 qcom,bcm-voters = <&a 1814 qcom,bcm-voters = <&apps_bcm_voter>;
2102 }; 1815 };
2103 1816
2104 aggre2_noc: interconnect@1700 1817 aggre2_noc: interconnect@1700000 {
2105 compatible = "qcom,sm 1818 compatible = "qcom,sm8250-aggre2-noc";
2106 reg = <0 0x01700000 0 1819 reg = <0 0x01700000 0 0x33000>;
2107 #interconnect-cells = 1820 #interconnect-cells = <2>;
2108 qcom,bcm-voters = <&a 1821 qcom,bcm-voters = <&apps_bcm_voter>;
2109 }; 1822 };
2110 1823
2111 compute_noc: interconnect@173 1824 compute_noc: interconnect@1733000 {
2112 compatible = "qcom,sm 1825 compatible = "qcom,sm8250-compute-noc";
2113 reg = <0 0x01733000 0 1826 reg = <0 0x01733000 0 0xa180>;
2114 #interconnect-cells = 1827 #interconnect-cells = <2>;
2115 qcom,bcm-voters = <&a 1828 qcom,bcm-voters = <&apps_bcm_voter>;
2116 }; 1829 };
2117 1830
2118 mmss_noc: interconnect@174000 1831 mmss_noc: interconnect@1740000 {
2119 compatible = "qcom,sm 1832 compatible = "qcom,sm8250-mmss-noc";
2120 reg = <0 0x01740000 0 1833 reg = <0 0x01740000 0 0x1f080>;
2121 #interconnect-cells = 1834 #interconnect-cells = <2>;
2122 qcom,bcm-voters = <&a 1835 qcom,bcm-voters = <&apps_bcm_voter>;
2123 }; 1836 };
2124 1837
2125 pcie0: pcie@1c00000 { !! 1838 pcie0: pci@1c00000 {
2126 compatible = "qcom,pc 1839 compatible = "qcom,pcie-sm8250";
2127 reg = <0 0x01c00000 0 1840 reg = <0 0x01c00000 0 0x3000>,
2128 <0 0x60000000 0 1841 <0 0x60000000 0 0xf1d>,
2129 <0 0x60000f20 0 1842 <0 0x60000f20 0 0xa8>,
2130 <0 0x60001000 0 1843 <0 0x60001000 0 0x1000>,
2131 <0 0x60100000 0 1844 <0 0x60100000 0 0x100000>,
2132 <0 0x01c03000 0 1845 <0 0x01c03000 0 0x1000>;
2133 reg-names = "parf", " 1846 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2134 device_type = "pci"; 1847 device_type = "pci";
2135 linux,pci-domain = <0 1848 linux,pci-domain = <0>;
2136 bus-range = <0x00 0xf 1849 bus-range = <0x00 0xff>;
2137 num-lanes = <1>; 1850 num-lanes = <1>;
2138 1851
2139 #address-cells = <3>; 1852 #address-cells = <3>;
2140 #size-cells = <2>; 1853 #size-cells = <2>;
2141 1854
2142 ranges = <0x01000000 1855 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
2143 <0x02000000 1856 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
2144 1857
2145 interrupts = <GIC_SPI 1858 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
2146 <GIC_SPI 1859 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
2147 <GIC_SPI 1860 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
2148 <GIC_SPI 1861 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
2149 <GIC_SPI 1862 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
2150 <GIC_SPI 1863 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
2151 <GIC_SPI 1864 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
2152 <GIC_SPI 1865 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2153 interrupt-names = "ms !! 1866 interrupt-names = "msi0", "msi1", "msi2", "msi3",
2154 "ms !! 1867 "msi4", "msi5", "msi6", "msi7";
2155 "ms <<
2156 "ms <<
2157 "ms <<
2158 "ms <<
2159 "ms <<
2160 "ms <<
2161 #interrupt-cells = <1 1868 #interrupt-cells = <1>;
2162 interrupt-map-mask = 1869 interrupt-map-mask = <0 0 0 0x7>;
2163 interrupt-map = <0 0 1870 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2164 <0 0 1871 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2165 <0 0 1872 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2166 <0 0 1873 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2167 1874
2168 clocks = <&gcc GCC_PC 1875 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
2169 <&gcc GCC_PC 1876 <&gcc GCC_PCIE_0_AUX_CLK>,
2170 <&gcc GCC_PC 1877 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2171 <&gcc GCC_PC 1878 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
2172 <&gcc GCC_PC 1879 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
2173 <&gcc GCC_PC 1880 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
2174 <&gcc GCC_AG 1881 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
2175 <&gcc GCC_DD 1882 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
2176 clock-names = "pipe", 1883 clock-names = "pipe",
2177 "aux", 1884 "aux",
2178 "cfg", 1885 "cfg",
2179 "bus_ma 1886 "bus_master",
2180 "bus_sl 1887 "bus_slave",
2181 "slave_ 1888 "slave_q2a",
2182 "tbu", 1889 "tbu",
2183 "ddrss_ 1890 "ddrss_sf_tbu";
2184 1891
2185 iommu-map = <0x0 &a 1892 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
2186 <0x100 &a 1893 <0x100 &apps_smmu 0x1c01 0x1>;
2187 1894
2188 resets = <&gcc GCC_PC 1895 resets = <&gcc GCC_PCIE_0_BCR>;
2189 reset-names = "pci"; 1896 reset-names = "pci";
2190 1897
2191 power-domains = <&gcc 1898 power-domains = <&gcc PCIE_0_GDSC>;
2192 1899
2193 phys = <&pcie0_phy>; !! 1900 phys = <&pcie0_lane>;
2194 phy-names = "pciephy" 1901 phy-names = "pciephy";
2195 1902
2196 perst-gpios = <&tlmm 1903 perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>;
2197 wake-gpios = <&tlmm 8 1904 wake-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
2198 1905
2199 pinctrl-names = "defa 1906 pinctrl-names = "default";
2200 pinctrl-0 = <&pcie0_d 1907 pinctrl-0 = <&pcie0_default_state>;
2201 dma-coherent; 1908 dma-coherent;
2202 1909
2203 status = "disabled"; 1910 status = "disabled";
2204 <<
2205 pcieport0: pcie@0 { <<
2206 device_type = <<
2207 reg = <0x0 0x <<
2208 bus-range = < <<
2209 <<
2210 #address-cell <<
2211 #size-cells = <<
2212 ranges; <<
2213 }; <<
2214 }; 1911 };
2215 1912
2216 pcie0_phy: phy@1c06000 { 1913 pcie0_phy: phy@1c06000 {
2217 compatible = "qcom,sm 1914 compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy";
2218 reg = <0 0x01c06000 0 !! 1915 reg = <0 0x01c06000 0 0x1c0>;
2219 !! 1916 #address-cells = <2>;
>> 1917 #size-cells = <2>;
>> 1918 ranges;
2220 clocks = <&gcc GCC_PC 1919 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2221 <&gcc GCC_PC 1920 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2222 <&gcc GCC_PC 1921 <&gcc GCC_PCIE_WIFI_CLKREF_EN>,
2223 <&gcc GCC_PC !! 1922 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
2224 <&gcc GCC_PC !! 1923 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2225 clock-names = "aux", <<
2226 "cfg_ah <<
2227 "ref", <<
2228 "refgen <<
2229 "pipe"; <<
2230 <<
2231 clock-output-names = <<
2232 #clock-cells = <0>; <<
2233 <<
2234 #phy-cells = <0>; <<
2235 1924
2236 resets = <&gcc GCC_PC 1925 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
2237 reset-names = "phy"; 1926 reset-names = "phy";
2238 1927
2239 assigned-clocks = <&g 1928 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
2240 assigned-clock-rates 1929 assigned-clock-rates = <100000000>;
2241 1930
2242 status = "disabled"; 1931 status = "disabled";
>> 1932
>> 1933 pcie0_lane: phy@1c06200 {
>> 1934 reg = <0 0x01c06200 0 0x170>, /* tx */
>> 1935 <0 0x01c06400 0 0x200>, /* rx */
>> 1936 <0 0x01c06800 0 0x1f0>, /* pcs */
>> 1937 <0 0x01c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */
>> 1938 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
>> 1939 clock-names = "pipe0";
>> 1940
>> 1941 #phy-cells = <0>;
>> 1942
>> 1943 #clock-cells = <0>;
>> 1944 clock-output-names = "pcie_0_pipe_clk";
>> 1945 };
2243 }; 1946 };
2244 1947
2245 pcie1: pcie@1c08000 { !! 1948 pcie1: pci@1c08000 {
2246 compatible = "qcom,pc 1949 compatible = "qcom,pcie-sm8250";
2247 reg = <0 0x01c08000 0 1950 reg = <0 0x01c08000 0 0x3000>,
2248 <0 0x40000000 0 1951 <0 0x40000000 0 0xf1d>,
2249 <0 0x40000f20 0 1952 <0 0x40000f20 0 0xa8>,
2250 <0 0x40001000 0 1953 <0 0x40001000 0 0x1000>,
2251 <0 0x40100000 0 1954 <0 0x40100000 0 0x100000>,
2252 <0 0x01c0b000 0 1955 <0 0x01c0b000 0 0x1000>;
2253 reg-names = "parf", " 1956 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2254 device_type = "pci"; 1957 device_type = "pci";
2255 linux,pci-domain = <1 1958 linux,pci-domain = <1>;
2256 bus-range = <0x00 0xf 1959 bus-range = <0x00 0xff>;
2257 num-lanes = <2>; 1960 num-lanes = <2>;
2258 1961
2259 #address-cells = <3>; 1962 #address-cells = <3>;
2260 #size-cells = <2>; 1963 #size-cells = <2>;
2261 1964
2262 ranges = <0x01000000 1965 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
2263 <0x02000000 1966 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
2264 1967
2265 interrupts = <GIC_SPI !! 1968 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
2266 <GIC_SPI !! 1969 interrupt-names = "msi";
2267 <GIC_SPI <<
2268 <GIC_SPI <<
2269 <GIC_SPI <<
2270 <GIC_SPI <<
2271 <GIC_SPI <<
2272 <GIC_SPI <<
2273 interrupt-names = "ms <<
2274 "ms <<
2275 "ms <<
2276 "ms <<
2277 "ms <<
2278 "ms <<
2279 "ms <<
2280 "ms <<
2281 #interrupt-cells = <1 1970 #interrupt-cells = <1>;
2282 interrupt-map-mask = 1971 interrupt-map-mask = <0 0 0 0x7>;
2283 interrupt-map = <0 0 1972 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2284 <0 0 1973 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2285 <0 0 1974 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2286 <0 0 1975 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2287 1976
2288 clocks = <&gcc GCC_PC 1977 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
2289 <&gcc GCC_PC 1978 <&gcc GCC_PCIE_1_AUX_CLK>,
2290 <&gcc GCC_PC 1979 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2291 <&gcc GCC_PC 1980 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
2292 <&gcc GCC_PC 1981 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
2293 <&gcc GCC_PC 1982 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
2294 <&gcc GCC_PC 1983 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
2295 <&gcc GCC_AG 1984 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
2296 <&gcc GCC_DD 1985 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
2297 clock-names = "pipe", 1986 clock-names = "pipe",
2298 "aux", 1987 "aux",
2299 "cfg", 1988 "cfg",
2300 "bus_ma 1989 "bus_master",
2301 "bus_sl 1990 "bus_slave",
2302 "slave_ 1991 "slave_q2a",
2303 "ref", 1992 "ref",
2304 "tbu", 1993 "tbu",
2305 "ddrss_ 1994 "ddrss_sf_tbu";
2306 1995
2307 assigned-clocks = <&g 1996 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2308 assigned-clock-rates 1997 assigned-clock-rates = <19200000>;
2309 1998
2310 iommu-map = <0x0 &a 1999 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
2311 <0x100 &a 2000 <0x100 &apps_smmu 0x1c81 0x1>;
2312 2001
2313 resets = <&gcc GCC_PC 2002 resets = <&gcc GCC_PCIE_1_BCR>;
2314 reset-names = "pci"; 2003 reset-names = "pci";
2315 2004
2316 power-domains = <&gcc 2005 power-domains = <&gcc PCIE_1_GDSC>;
2317 2006
2318 phys = <&pcie1_phy>; !! 2007 phys = <&pcie1_lane>;
2319 phy-names = "pciephy" 2008 phy-names = "pciephy";
2320 2009
2321 perst-gpios = <&tlmm 2010 perst-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>;
2322 wake-gpios = <&tlmm 8 2011 wake-gpios = <&tlmm 84 GPIO_ACTIVE_HIGH>;
2323 2012
2324 pinctrl-names = "defa 2013 pinctrl-names = "default";
2325 pinctrl-0 = <&pcie1_d 2014 pinctrl-0 = <&pcie1_default_state>;
2326 dma-coherent; 2015 dma-coherent;
2327 2016
2328 status = "disabled"; 2017 status = "disabled";
2329 <<
2330 pcie@0 { <<
2331 device_type = <<
2332 reg = <0x0 0x <<
2333 bus-range = < <<
2334 <<
2335 #address-cell <<
2336 #size-cells = <<
2337 ranges; <<
2338 }; <<
2339 }; 2018 };
2340 2019
2341 pcie1_phy: phy@1c0e000 { 2020 pcie1_phy: phy@1c0e000 {
2342 compatible = "qcom,sm 2021 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
2343 reg = <0 0x01c0e000 0 !! 2022 reg = <0 0x01c0e000 0 0x1c0>;
2344 !! 2023 #address-cells = <2>;
>> 2024 #size-cells = <2>;
>> 2025 ranges;
2345 clocks = <&gcc GCC_PC 2026 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2346 <&gcc GCC_PC 2027 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2347 <&gcc GCC_PC 2028 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
2348 <&gcc GCC_PC !! 2029 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
2349 <&gcc GCC_PC !! 2030 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2350 clock-names = "aux", <<
2351 "cfg_ah <<
2352 "ref", <<
2353 "refgen <<
2354 "pipe"; <<
2355 <<
2356 clock-output-names = <<
2357 #clock-cells = <0>; <<
2358 <<
2359 #phy-cells = <0>; <<
2360 2031
2361 resets = <&gcc GCC_PC 2032 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2362 reset-names = "phy"; 2033 reset-names = "phy";
2363 2034
2364 assigned-clocks = <&g 2035 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
2365 assigned-clock-rates 2036 assigned-clock-rates = <100000000>;
2366 2037
2367 status = "disabled"; 2038 status = "disabled";
>> 2039
>> 2040 pcie1_lane: phy@1c0e200 {
>> 2041 reg = <0 0x01c0e200 0 0x170>, /* tx0 */
>> 2042 <0 0x01c0e400 0 0x200>, /* rx0 */
>> 2043 <0 0x01c0ea00 0 0x1f0>, /* pcs */
>> 2044 <0 0x01c0e600 0 0x170>, /* tx1 */
>> 2045 <0 0x01c0e800 0 0x200>, /* rx1 */
>> 2046 <0 0x01c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */
>> 2047 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
>> 2048 clock-names = "pipe0";
>> 2049
>> 2050 #phy-cells = <0>;
>> 2051
>> 2052 #clock-cells = <0>;
>> 2053 clock-output-names = "pcie_1_pipe_clk";
>> 2054 };
2368 }; 2055 };
2369 2056
2370 pcie2: pcie@1c10000 { !! 2057 pcie2: pci@1c10000 {
2371 compatible = "qcom,pc 2058 compatible = "qcom,pcie-sm8250";
2372 reg = <0 0x01c10000 0 2059 reg = <0 0x01c10000 0 0x3000>,
2373 <0 0x64000000 0 2060 <0 0x64000000 0 0xf1d>,
2374 <0 0x64000f20 0 2061 <0 0x64000f20 0 0xa8>,
2375 <0 0x64001000 0 2062 <0 0x64001000 0 0x1000>,
2376 <0 0x64100000 0 2063 <0 0x64100000 0 0x100000>,
2377 <0 0x01c13000 0 2064 <0 0x01c13000 0 0x1000>;
2378 reg-names = "parf", " 2065 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2379 device_type = "pci"; 2066 device_type = "pci";
2380 linux,pci-domain = <2 2067 linux,pci-domain = <2>;
2381 bus-range = <0x00 0xf 2068 bus-range = <0x00 0xff>;
2382 num-lanes = <2>; 2069 num-lanes = <2>;
2383 2070
2384 #address-cells = <3>; 2071 #address-cells = <3>;
2385 #size-cells = <2>; 2072 #size-cells = <2>;
2386 2073
2387 ranges = <0x01000000 2074 ranges = <0x01000000 0x0 0x00000000 0x0 0x64200000 0x0 0x100000>,
2388 <0x02000000 2075 <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>;
2389 2076
2390 interrupts = <GIC_SPI !! 2077 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
2391 <GIC_SPI !! 2078 interrupt-names = "msi";
2392 <GIC_SPI <<
2393 <GIC_SPI <<
2394 <GIC_SPI <<
2395 <GIC_SPI <<
2396 <GIC_SPI <<
2397 <GIC_SPI <<
2398 interrupt-names = "ms <<
2399 "ms <<
2400 "ms <<
2401 "ms <<
2402 "ms <<
2403 "ms <<
2404 "ms <<
2405 "ms <<
2406 #interrupt-cells = <1 2079 #interrupt-cells = <1>;
2407 interrupt-map-mask = 2080 interrupt-map-mask = <0 0 0 0x7>;
2408 interrupt-map = <0 0 2081 interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2409 <0 0 2082 <0 0 0 2 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2410 <0 0 2083 <0 0 0 3 &intc 0 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2411 <0 0 2084 <0 0 0 4 &intc 0 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2412 2085
2413 clocks = <&gcc GCC_PC 2086 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
2414 <&gcc GCC_PC 2087 <&gcc GCC_PCIE_2_AUX_CLK>,
2415 <&gcc GCC_PC 2088 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2416 <&gcc GCC_PC 2089 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
2417 <&gcc GCC_PC 2090 <&gcc GCC_PCIE_2_SLV_AXI_CLK>,
2418 <&gcc GCC_PC 2091 <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>,
2419 <&gcc GCC_PC 2092 <&gcc GCC_PCIE_MDM_CLKREF_EN>,
2420 <&gcc GCC_AG 2093 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
2421 <&gcc GCC_DD 2094 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
2422 clock-names = "pipe", 2095 clock-names = "pipe",
2423 "aux", 2096 "aux",
2424 "cfg", 2097 "cfg",
2425 "bus_ma 2098 "bus_master",
2426 "bus_sl 2099 "bus_slave",
2427 "slave_ 2100 "slave_q2a",
2428 "ref", 2101 "ref",
2429 "tbu", 2102 "tbu",
2430 "ddrss_ 2103 "ddrss_sf_tbu";
2431 2104
2432 assigned-clocks = <&g 2105 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>;
2433 assigned-clock-rates 2106 assigned-clock-rates = <19200000>;
2434 2107
2435 iommu-map = <0x0 &a 2108 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>,
2436 <0x100 &a 2109 <0x100 &apps_smmu 0x1d01 0x1>;
2437 2110
2438 resets = <&gcc GCC_PC 2111 resets = <&gcc GCC_PCIE_2_BCR>;
2439 reset-names = "pci"; 2112 reset-names = "pci";
2440 2113
2441 power-domains = <&gcc 2114 power-domains = <&gcc PCIE_2_GDSC>;
2442 2115
2443 phys = <&pcie2_phy>; !! 2116 phys = <&pcie2_lane>;
2444 phy-names = "pciephy" 2117 phy-names = "pciephy";
2445 2118
2446 perst-gpios = <&tlmm 2119 perst-gpios = <&tlmm 85 GPIO_ACTIVE_LOW>;
2447 wake-gpios = <&tlmm 8 2120 wake-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>;
2448 2121
2449 pinctrl-names = "defa 2122 pinctrl-names = "default";
2450 pinctrl-0 = <&pcie2_d 2123 pinctrl-0 = <&pcie2_default_state>;
2451 dma-coherent; 2124 dma-coherent;
2452 2125
2453 status = "disabled"; 2126 status = "disabled";
2454 <<
2455 pcie@0 { <<
2456 device_type = <<
2457 reg = <0x0 0x <<
2458 bus-range = < <<
2459 <<
2460 #address-cell <<
2461 #size-cells = <<
2462 ranges; <<
2463 }; <<
2464 }; 2127 };
2465 2128
2466 pcie2_phy: phy@1c16000 { 2129 pcie2_phy: phy@1c16000 {
2467 compatible = "qcom,sm 2130 compatible = "qcom,sm8250-qmp-modem-pcie-phy";
2468 reg = <0 0x01c16000 0 !! 2131 reg = <0 0x01c16000 0 0x1c0>;
2469 !! 2132 #address-cells = <2>;
>> 2133 #size-cells = <2>;
>> 2134 ranges;
2470 clocks = <&gcc GCC_PC 2135 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2471 <&gcc GCC_PC 2136 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2472 <&gcc GCC_PC 2137 <&gcc GCC_PCIE_MDM_CLKREF_EN>,
2473 <&gcc GCC_PC !! 2138 <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
2474 <&gcc GCC_PC !! 2139 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2475 clock-names = "aux", <<
2476 "cfg_ah <<
2477 "ref", <<
2478 "refgen <<
2479 "pipe"; <<
2480 <<
2481 clock-output-names = <<
2482 #clock-cells = <0>; <<
2483 <<
2484 #phy-cells = <0>; <<
2485 2140
2486 resets = <&gcc GCC_PC 2141 resets = <&gcc GCC_PCIE_2_PHY_BCR>;
2487 reset-names = "phy"; 2142 reset-names = "phy";
2488 2143
2489 assigned-clocks = <&g 2144 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
2490 assigned-clock-rates 2145 assigned-clock-rates = <100000000>;
2491 2146
2492 status = "disabled"; 2147 status = "disabled";
>> 2148
>> 2149 pcie2_lane: phy@1c16200 {
>> 2150 reg = <0 0x01c16200 0 0x170>, /* tx0 */
>> 2151 <0 0x01c16400 0 0x200>, /* rx0 */
>> 2152 <0 0x01c16a00 0 0x1f0>, /* pcs */
>> 2153 <0 0x01c16600 0 0x170>, /* tx1 */
>> 2154 <0 0x01c16800 0 0x200>, /* rx1 */
>> 2155 <0 0x01c16e00 0 0xf4>; /* "pcs_com" same as pcs_misc? */
>> 2156 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
>> 2157 clock-names = "pipe0";
>> 2158
>> 2159 #phy-cells = <0>;
>> 2160
>> 2161 #clock-cells = <0>;
>> 2162 clock-output-names = "pcie_2_pipe_clk";
>> 2163 };
2493 }; 2164 };
2494 2165
2495 ufs_mem_hc: ufshc@1d84000 { 2166 ufs_mem_hc: ufshc@1d84000 {
2496 compatible = "qcom,sm 2167 compatible = "qcom,sm8250-ufshc", "qcom,ufshc",
2497 "jedec,u 2168 "jedec,ufs-2.0";
2498 reg = <0 0x01d84000 0 2169 reg = <0 0x01d84000 0 0x3000>;
2499 interrupts = <GIC_SPI 2170 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2500 phys = <&ufs_mem_phy> !! 2171 phys = <&ufs_mem_phy_lanes>;
2501 phy-names = "ufsphy"; 2172 phy-names = "ufsphy";
2502 lanes-per-direction = 2173 lanes-per-direction = <2>;
2503 #reset-cells = <1>; 2174 #reset-cells = <1>;
2504 resets = <&gcc GCC_UF 2175 resets = <&gcc GCC_UFS_PHY_BCR>;
2505 reset-names = "rst"; 2176 reset-names = "rst";
2506 2177
2507 power-domains = <&gcc 2178 power-domains = <&gcc UFS_PHY_GDSC>;
2508 2179
2509 iommus = <&apps_smmu 2180 iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>;
2510 2181
2511 clock-names = 2182 clock-names =
2512 "core_clk", 2183 "core_clk",
2513 "bus_aggr_clk 2184 "bus_aggr_clk",
2514 "iface_clk", 2185 "iface_clk",
2515 "core_clk_uni 2186 "core_clk_unipro",
2516 "ref_clk", 2187 "ref_clk",
2517 "tx_lane0_syn 2188 "tx_lane0_sync_clk",
2518 "rx_lane0_syn 2189 "rx_lane0_sync_clk",
2519 "rx_lane1_syn 2190 "rx_lane1_sync_clk";
2520 clocks = 2191 clocks =
2521 <&gcc GCC_UFS 2192 <&gcc GCC_UFS_PHY_AXI_CLK>,
2522 <&gcc GCC_AGG 2193 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2523 <&gcc GCC_UFS 2194 <&gcc GCC_UFS_PHY_AHB_CLK>,
2524 <&gcc GCC_UFS 2195 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2525 <&rpmhcc RPMH 2196 <&rpmhcc RPMH_CXO_CLK>,
2526 <&gcc GCC_UFS 2197 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2527 <&gcc GCC_UFS 2198 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2528 <&gcc GCC_UFS 2199 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
2529 !! 2200 freq-table-hz =
2530 operating-points-v2 = !! 2201 <37500000 300000000>,
2531 !! 2202 <0 0>,
2532 interconnects = <&agg !! 2203 <0 0>,
2533 <&gem !! 2204 <37500000 300000000>,
2534 interconnect-names = !! 2205 <0 0>,
>> 2206 <0 0>,
>> 2207 <0 0>,
>> 2208 <0 0>;
2535 2209
2536 status = "disabled"; 2210 status = "disabled";
2537 <<
2538 ufs_opp_table: opp-ta <<
2539 compatible = <<
2540 <<
2541 opp-37500000 <<
2542 opp-h <<
2543 <<
2544 <<
2545 <<
2546 <<
2547 <<
2548 <<
2549 <<
2550 requi <<
2551 }; <<
2552 <<
2553 opp-300000000 <<
2554 opp-h <<
2555 <<
2556 <<
2557 <<
2558 <<
2559 <<
2560 <<
2561 <<
2562 requi <<
2563 }; <<
2564 }; <<
2565 }; 2211 };
2566 2212
2567 ufs_mem_phy: phy@1d87000 { 2213 ufs_mem_phy: phy@1d87000 {
2568 compatible = "qcom,sm 2214 compatible = "qcom,sm8250-qmp-ufs-phy";
2569 reg = <0 0x01d87000 0 !! 2215 reg = <0 0x01d87000 0 0x1c0>;
2570 !! 2216 #address-cells = <2>;
2571 clocks = <&rpmhcc RPM !! 2217 #size-cells = <2>;
2572 <&gcc GCC_UF !! 2218 ranges;
2573 <&gcc GCC_UF <<
2574 clock-names = "ref", 2219 clock-names = "ref",
2575 "ref_au !! 2220 "ref_aux";
2576 "qref"; !! 2221 clocks = <&rpmhcc RPMH_CXO_CLK>,
>> 2222 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2577 2223
2578 resets = <&ufs_mem_hc 2224 resets = <&ufs_mem_hc 0>;
2579 reset-names = "ufsphy 2225 reset-names = "ufsphy";
2580 <<
2581 power-domains = <&gcc <<
2582 <<
2583 #phy-cells = <0>; <<
2584 <<
2585 status = "disabled"; 2226 status = "disabled";
>> 2227
>> 2228 ufs_mem_phy_lanes: phy@1d87400 {
>> 2229 reg = <0 0x01d87400 0 0x16c>,
>> 2230 <0 0x01d87600 0 0x200>,
>> 2231 <0 0x01d87c00 0 0x200>,
>> 2232 <0 0x01d87800 0 0x16c>,
>> 2233 <0 0x01d87a00 0 0x200>;
>> 2234 #phy-cells = <0>;
>> 2235 };
2586 }; 2236 };
2587 2237
2588 cryptobam: dma-controller@1dc 2238 cryptobam: dma-controller@1dc4000 {
2589 compatible = "qcom,ba 2239 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
2590 reg = <0 0x01dc4000 0 2240 reg = <0 0x01dc4000 0 0x24000>;
2591 interrupts = <GIC_SPI 2241 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
2592 #dma-cells = <1>; 2242 #dma-cells = <1>;
2593 qcom,ee = <0>; 2243 qcom,ee = <0>;
2594 qcom,controlled-remot 2244 qcom,controlled-remotely;
2595 num-channels = <8>; 2245 num-channels = <8>;
2596 qcom,num-ees = <2>; 2246 qcom,num-ees = <2>;
2597 iommus = <&apps_smmu 2247 iommus = <&apps_smmu 0x592 0x0000>,
2598 <&apps_smmu 2248 <&apps_smmu 0x598 0x0000>,
2599 <&apps_smmu 2249 <&apps_smmu 0x599 0x0000>,
2600 <&apps_smmu 2250 <&apps_smmu 0x59f 0x0000>,
2601 <&apps_smmu 2251 <&apps_smmu 0x586 0x0011>,
2602 <&apps_smmu 2252 <&apps_smmu 0x596 0x0011>;
2603 }; 2253 };
2604 2254
2605 crypto: crypto@1dfa000 { 2255 crypto: crypto@1dfa000 {
2606 compatible = "qcom,sm 2256 compatible = "qcom,sm8250-qce", "qcom,sm8150-qce", "qcom,qce";
2607 reg = <0 0x01dfa000 0 2257 reg = <0 0x01dfa000 0 0x6000>;
2608 dmas = <&cryptobam 4> 2258 dmas = <&cryptobam 4>, <&cryptobam 5>;
2609 dma-names = "rx", "tx 2259 dma-names = "rx", "tx";
2610 iommus = <&apps_smmu 2260 iommus = <&apps_smmu 0x592 0x0000>,
2611 <&apps_smmu 2261 <&apps_smmu 0x598 0x0000>,
2612 <&apps_smmu 2262 <&apps_smmu 0x599 0x0000>,
2613 <&apps_smmu 2263 <&apps_smmu 0x59f 0x0000>,
2614 <&apps_smmu 2264 <&apps_smmu 0x586 0x0011>,
2615 <&apps_smmu 2265 <&apps_smmu 0x596 0x0011>;
2616 interconnects = <&agg 2266 interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 0 &mc_virt SLAVE_EBI_CH0 0>;
2617 interconnect-names = 2267 interconnect-names = "memory";
2618 }; 2268 };
2619 2269
2620 tcsr_mutex: hwlock@1f40000 { 2270 tcsr_mutex: hwlock@1f40000 {
2621 compatible = "qcom,tc 2271 compatible = "qcom,tcsr-mutex";
2622 reg = <0x0 0x01f40000 2272 reg = <0x0 0x01f40000 0x0 0x40000>;
2623 #hwlock-cells = <1>; 2273 #hwlock-cells = <1>;
2624 }; 2274 };
2625 2275
2626 tcsr: syscon@1fc0000 { <<
2627 compatible = "qcom,sm <<
2628 reg = <0x0 0x1fc0000 <<
2629 }; <<
2630 <<
2631 wsamacro: codec@3240000 { 2276 wsamacro: codec@3240000 {
2632 compatible = "qcom,sm 2277 compatible = "qcom,sm8250-lpass-wsa-macro";
2633 reg = <0 0x03240000 0 2278 reg = <0 0x03240000 0 0x1000>;
2634 clocks = <&q6afecc LP !! 2279 clocks = <&audiocc LPASS_CDC_WSA_MCLK>,
2635 <&q6afecc LP !! 2280 <&audiocc LPASS_CDC_WSA_NPL>,
2636 <&q6afecc LP 2281 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2637 <&q6afecc LP 2282 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 2283 <&aoncc LPASS_CDC_VA_MCLK>,
2638 <&vamacro>; 2284 <&vamacro>;
2639 2285
2640 clock-names = "mclk", !! 2286 clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen";
2641 2287
2642 #clock-cells = <0>; 2288 #clock-cells = <0>;
2643 clock-output-names = 2289 clock-output-names = "mclk";
2644 #sound-dai-cells = <1 2290 #sound-dai-cells = <1>;
2645 2291
2646 pinctrl-names = "defa 2292 pinctrl-names = "default";
2647 pinctrl-0 = <&wsa_swr 2293 pinctrl-0 = <&wsa_swr_active>;
2648 2294
2649 status = "disabled"; 2295 status = "disabled";
2650 }; 2296 };
2651 2297
2652 swr0: soundwire@3250000 { !! 2298 swr0: soundwire-controller@3250000 {
2653 reg = <0 0x03250000 0 2299 reg = <0 0x03250000 0 0x2000>;
2654 compatible = "qcom,so 2300 compatible = "qcom,soundwire-v1.5.1";
2655 interrupts = <GIC_SPI 2301 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
2656 clocks = <&wsamacro>; 2302 clocks = <&wsamacro>;
2657 clock-names = "iface" 2303 clock-names = "iface";
2658 2304
2659 qcom,din-ports = <2>; 2305 qcom,din-ports = <2>;
2660 qcom,dout-ports = <6> 2306 qcom,dout-ports = <6>;
2661 2307
2662 qcom,ports-sinterval- 2308 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2663 qcom,ports-offset1 = 2309 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2664 qcom,ports-offset2 = 2310 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2665 qcom,ports-block-pack 2311 qcom,ports-block-pack-mode = /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>;
2666 2312
2667 #sound-dai-cells = <1 2313 #sound-dai-cells = <1>;
2668 #address-cells = <2>; 2314 #address-cells = <2>;
2669 #size-cells = <0>; 2315 #size-cells = <0>;
2670 2316
2671 status = "disabled"; 2317 status = "disabled";
2672 }; 2318 };
2673 2319
>> 2320 audiocc: clock-controller@3300000 {
>> 2321 compatible = "qcom,sm8250-lpass-audiocc";
>> 2322 reg = <0 0x03300000 0 0x30000>;
>> 2323 #clock-cells = <1>;
>> 2324 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 2325 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 2326 <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
>> 2327 clock-names = "core", "audio", "bus";
>> 2328 };
>> 2329
2674 vamacro: codec@3370000 { 2330 vamacro: codec@3370000 {
2675 compatible = "qcom,sm 2331 compatible = "qcom,sm8250-lpass-va-macro";
2676 reg = <0 0x03370000 0 2332 reg = <0 0x03370000 0 0x1000>;
2677 clocks = <&q6afecc LP !! 2333 clocks = <&aoncc LPASS_CDC_VA_MCLK>,
2678 <&q6afecc LPA 2334 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2679 <&q6afecc LPA 2335 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2680 2336
2681 clock-names = "mclk", 2337 clock-names = "mclk", "macro", "dcodec";
2682 2338
2683 #clock-cells = <0>; 2339 #clock-cells = <0>;
2684 clock-output-names = 2340 clock-output-names = "fsgen";
2685 #sound-dai-cells = <1 2341 #sound-dai-cells = <1>;
2686 }; 2342 };
2687 2343
2688 rxmacro: rxmacro@3200000 { 2344 rxmacro: rxmacro@3200000 {
2689 pinctrl-names = "defa 2345 pinctrl-names = "default";
2690 pinctrl-0 = <&rx_swr_ 2346 pinctrl-0 = <&rx_swr_active>;
2691 compatible = "qcom,sm 2347 compatible = "qcom,sm8250-lpass-rx-macro";
2692 reg = <0 0x03200000 0 2348 reg = <0 0x03200000 0 0x1000>;
2693 status = "disabled"; 2349 status = "disabled";
2694 2350
2695 clocks = <&q6afecc LP 2351 clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2696 <&q6afecc LPA 2352 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2697 <&q6afecc LPA 2353 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2698 <&q6afecc LPA 2354 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2699 <&vamacro>; 2355 <&vamacro>;
2700 2356
2701 clock-names = "mclk", 2357 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2702 2358
2703 #clock-cells = <0>; 2359 #clock-cells = <0>;
2704 clock-output-names = 2360 clock-output-names = "mclk";
2705 #sound-dai-cells = <1 2361 #sound-dai-cells = <1>;
2706 }; 2362 };
2707 2363
2708 swr1: soundwire@3210000 { !! 2364 swr1: soundwire-controller@3210000 {
2709 reg = <0 0x03210000 0 2365 reg = <0 0x03210000 0 0x2000>;
2710 compatible = "qcom,so 2366 compatible = "qcom,soundwire-v1.5.1";
2711 status = "disabled"; 2367 status = "disabled";
2712 interrupts = <GIC_SPI 2368 interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
2713 clocks = <&rxmacro>; 2369 clocks = <&rxmacro>;
2714 clock-names = "iface" 2370 clock-names = "iface";
2715 label = "RX"; 2371 label = "RX";
2716 qcom,din-ports = <0>; 2372 qcom,din-ports = <0>;
2717 qcom,dout-ports = <5> 2373 qcom,dout-ports = <5>;
2718 2374
2719 qcom,ports-sinterval- 2375 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
2720 qcom,ports-offset1 = 2376 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>;
2721 qcom,ports-offset2 = 2377 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
2722 qcom,ports-hstart = 2378 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
2723 qcom,ports-hstop = 2379 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
2724 qcom,ports-word-lengt 2380 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2725 qcom,ports-block-pack 2381 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
2726 qcom,ports-lane-contr 2382 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2727 qcom,ports-block-grou 2383 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
2728 2384
2729 #sound-dai-cells = <1 2385 #sound-dai-cells = <1>;
2730 #address-cells = <2>; 2386 #address-cells = <2>;
2731 #size-cells = <0>; 2387 #size-cells = <0>;
2732 }; 2388 };
2733 2389
2734 txmacro: txmacro@3220000 { 2390 txmacro: txmacro@3220000 {
2735 pinctrl-names = "defa 2391 pinctrl-names = "default";
2736 pinctrl-0 = <&tx_swr_ 2392 pinctrl-0 = <&tx_swr_active>;
2737 compatible = "qcom,sm 2393 compatible = "qcom,sm8250-lpass-tx-macro";
2738 reg = <0 0x03220000 0 2394 reg = <0 0x03220000 0 0x1000>;
2739 status = "disabled"; 2395 status = "disabled";
2740 2396
2741 clocks = <&q6afecc LP 2397 clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2742 <&q6afecc LP 2398 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2743 <&q6afecc LP 2399 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2744 <&q6afecc LP 2400 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2745 <&vamacro>; 2401 <&vamacro>;
2746 2402
2747 clock-names = "mclk", 2403 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2748 2404
2749 #clock-cells = <0>; 2405 #clock-cells = <0>;
2750 clock-output-names = 2406 clock-output-names = "mclk";
2751 #sound-dai-cells = <1 2407 #sound-dai-cells = <1>;
2752 }; 2408 };
2753 2409
2754 /* tx macro */ 2410 /* tx macro */
2755 swr2: soundwire@3230000 { !! 2411 swr2: soundwire-controller@3230000 {
2756 reg = <0 0x03230000 0 2412 reg = <0 0x03230000 0 0x2000>;
2757 compatible = "qcom,so 2413 compatible = "qcom,soundwire-v1.5.1";
2758 interrupts = <GIC_SPI 2414 interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
2759 interrupt-names = "co 2415 interrupt-names = "core";
2760 status = "disabled"; 2416 status = "disabled";
2761 2417
2762 clocks = <&txmacro>; 2418 clocks = <&txmacro>;
2763 clock-names = "iface" 2419 clock-names = "iface";
2764 label = "TX"; 2420 label = "TX";
2765 2421
2766 qcom,din-ports = <5>; 2422 qcom,din-ports = <5>;
2767 qcom,dout-ports = <0> 2423 qcom,dout-ports = <0>;
2768 qcom,ports-sinterval- 2424 qcom,ports-sinterval-low = /bits/ 8 <0xff 0x01 0x01 0x03 0x03>;
2769 qcom,ports-offset1 = 2425 qcom,ports-offset1 = /bits/ 8 <0xff 0x01 0x00 0x02 0x00>;
2770 qcom,ports-offset2 = 2426 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x00 0x00 0x00>;
2771 qcom,ports-block-pack 2427 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2772 qcom,ports-hstart = 2428 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2773 qcom,ports-hstop = 2429 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2774 qcom,ports-word-lengt 2430 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2775 qcom,ports-block-grou 2431 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2776 qcom,ports-lane-contr 2432 qcom,ports-lane-control = /bits/ 8 <0xff 0x00 0x01 0x00 0x01>;
2777 #sound-dai-cells = <1 2433 #sound-dai-cells = <1>;
2778 #address-cells = <2>; 2434 #address-cells = <2>;
2779 #size-cells = <0>; 2435 #size-cells = <0>;
2780 }; 2436 };
2781 2437
>> 2438 aoncc: clock-controller@3380000 {
>> 2439 compatible = "qcom,sm8250-lpass-aoncc";
>> 2440 reg = <0 0x03380000 0 0x40000>;
>> 2441 #clock-cells = <1>;
>> 2442 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 2443 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 2444 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
>> 2445 clock-names = "core", "audio", "bus";
>> 2446 };
>> 2447
2782 lpass_tlmm: pinctrl@33c0000 { 2448 lpass_tlmm: pinctrl@33c0000 {
2783 compatible = "qcom,sm 2449 compatible = "qcom,sm8250-lpass-lpi-pinctrl";
2784 reg = <0 0x033c0000 0 2450 reg = <0 0x033c0000 0x0 0x20000>,
2785 <0 0x03550000 0 2451 <0 0x03550000 0x0 0x10000>;
2786 gpio-controller; 2452 gpio-controller;
2787 #gpio-cells = <2>; 2453 #gpio-cells = <2>;
2788 gpio-ranges = <&lpass 2454 gpio-ranges = <&lpass_tlmm 0 0 14>;
2789 2455
2790 clocks = <&q6afecc LP 2456 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2791 <&q6afecc LPA 2457 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2792 clock-names = "core", 2458 clock-names = "core", "audio";
2793 2459
2794 wsa_swr_active: wsa-s 2460 wsa_swr_active: wsa-swr-active-state {
2795 clk-pins { 2461 clk-pins {
2796 pins 2462 pins = "gpio10";
2797 funct 2463 function = "wsa_swr_clk";
2798 drive 2464 drive-strength = <2>;
2799 slew- 2465 slew-rate = <1>;
2800 bias- 2466 bias-disable;
2801 }; 2467 };
2802 2468
2803 data-pins { 2469 data-pins {
2804 pins 2470 pins = "gpio11";
2805 funct 2471 function = "wsa_swr_data";
2806 drive 2472 drive-strength = <2>;
2807 slew- 2473 slew-rate = <1>;
2808 bias- 2474 bias-bus-hold;
2809 }; 2475 };
2810 }; 2476 };
2811 2477
2812 wsa_swr_sleep: wsa-sw 2478 wsa_swr_sleep: wsa-swr-sleep-state {
2813 clk-pins { 2479 clk-pins {
2814 pins 2480 pins = "gpio10";
2815 funct 2481 function = "wsa_swr_clk";
2816 drive 2482 drive-strength = <2>;
2817 bias- 2483 bias-pull-down;
2818 }; 2484 };
2819 2485
2820 data-pins { 2486 data-pins {
2821 pins 2487 pins = "gpio11";
2822 funct 2488 function = "wsa_swr_data";
2823 drive 2489 drive-strength = <2>;
2824 bias- 2490 bias-pull-down;
2825 }; 2491 };
2826 }; 2492 };
2827 2493
2828 dmic01_active: dmic01 2494 dmic01_active: dmic01-active-state {
2829 clk-pins { 2495 clk-pins {
2830 pins 2496 pins = "gpio6";
2831 funct 2497 function = "dmic1_clk";
2832 drive 2498 drive-strength = <8>;
2833 outpu 2499 output-high;
2834 }; 2500 };
2835 data-pins { 2501 data-pins {
2836 pins 2502 pins = "gpio7";
2837 funct 2503 function = "dmic1_data";
2838 drive 2504 drive-strength = <8>;
2839 }; 2505 };
2840 }; 2506 };
2841 2507
2842 dmic01_sleep: dmic01- 2508 dmic01_sleep: dmic01-sleep-state {
2843 clk-pins { 2509 clk-pins {
2844 pins 2510 pins = "gpio6";
2845 funct 2511 function = "dmic1_clk";
2846 drive 2512 drive-strength = <2>;
2847 bias- 2513 bias-disable;
2848 outpu 2514 output-low;
2849 }; 2515 };
2850 2516
2851 data-pins { 2517 data-pins {
2852 pins 2518 pins = "gpio7";
2853 funct 2519 function = "dmic1_data";
2854 drive 2520 drive-strength = <2>;
2855 bias- 2521 bias-pull-down;
2856 }; 2522 };
2857 }; 2523 };
2858 2524
2859 rx_swr_active: rx-swr 2525 rx_swr_active: rx-swr-active-state {
2860 clk-pins { 2526 clk-pins {
2861 pins 2527 pins = "gpio3";
2862 funct 2528 function = "swr_rx_clk";
2863 drive 2529 drive-strength = <2>;
2864 slew- 2530 slew-rate = <1>;
2865 bias- 2531 bias-disable;
2866 }; 2532 };
2867 2533
2868 data-pins { 2534 data-pins {
2869 pins 2535 pins = "gpio4", "gpio5";
2870 funct 2536 function = "swr_rx_data";
2871 drive 2537 drive-strength = <2>;
2872 slew- 2538 slew-rate = <1>;
2873 bias- 2539 bias-bus-hold;
2874 }; 2540 };
2875 }; 2541 };
2876 2542
2877 tx_swr_active: tx-swr 2543 tx_swr_active: tx-swr-active-state {
2878 clk-pins { 2544 clk-pins {
2879 pins 2545 pins = "gpio0";
2880 funct 2546 function = "swr_tx_clk";
2881 drive 2547 drive-strength = <2>;
2882 slew- 2548 slew-rate = <1>;
2883 bias- 2549 bias-disable;
2884 }; 2550 };
2885 2551
2886 data-pins { 2552 data-pins {
2887 pins 2553 pins = "gpio1", "gpio2";
2888 funct 2554 function = "swr_tx_data";
2889 drive 2555 drive-strength = <2>;
2890 slew- 2556 slew-rate = <1>;
2891 bias- 2557 bias-bus-hold;
2892 }; 2558 };
2893 }; 2559 };
2894 2560
2895 tx_swr_sleep: tx-swr- 2561 tx_swr_sleep: tx-swr-sleep-state {
2896 clk-pins { 2562 clk-pins {
2897 pins 2563 pins = "gpio0";
2898 funct 2564 function = "swr_tx_clk";
2899 drive 2565 drive-strength = <2>;
2900 bias- 2566 bias-pull-down;
2901 }; 2567 };
2902 2568
2903 data1-pins { 2569 data1-pins {
2904 pins 2570 pins = "gpio1";
2905 funct 2571 function = "swr_tx_data";
2906 drive 2572 drive-strength = <2>;
2907 bias- 2573 bias-bus-hold;
2908 }; 2574 };
2909 2575
2910 data2-pins { 2576 data2-pins {
2911 pins 2577 pins = "gpio2";
2912 funct 2578 function = "swr_tx_data";
2913 drive 2579 drive-strength = <2>;
2914 bias- 2580 bias-pull-down;
2915 }; 2581 };
2916 }; 2582 };
2917 }; 2583 };
2918 2584
2919 gpu: gpu@3d00000 { 2585 gpu: gpu@3d00000 {
2920 compatible = "qcom,ad 2586 compatible = "qcom,adreno-650.2",
2921 "qcom,ad 2587 "qcom,adreno";
2922 2588
2923 reg = <0 0x03d00000 0 2589 reg = <0 0x03d00000 0 0x40000>;
2924 reg-names = "kgsl_3d0 2590 reg-names = "kgsl_3d0_reg_memory";
2925 2591
2926 interrupts = <GIC_SPI 2592 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2927 2593
2928 iommus = <&adreno_smm 2594 iommus = <&adreno_smmu 0 0x401>;
2929 2595
2930 operating-points-v2 = 2596 operating-points-v2 = <&gpu_opp_table>;
2931 2597
2932 qcom,gmu = <&gmu>; 2598 qcom,gmu = <&gmu>;
2933 2599
2934 nvmem-cells = <&gpu_s 2600 nvmem-cells = <&gpu_speed_bin>;
2935 nvmem-cell-names = "s 2601 nvmem-cell-names = "speed_bin";
2936 #cooling-cells = <2>; <<
2937 2602
2938 status = "disabled"; 2603 status = "disabled";
2939 2604
2940 zap-shader { 2605 zap-shader {
2941 memory-region 2606 memory-region = <&gpu_mem>;
2942 }; 2607 };
2943 2608
2944 gpu_opp_table: opp-ta 2609 gpu_opp_table: opp-table {
2945 compatible = 2610 compatible = "operating-points-v2";
2946 2611
2947 opp-670000000 2612 opp-670000000 {
2948 opp-h 2613 opp-hz = /bits/ 64 <670000000>;
2949 opp-l 2614 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2950 opp-s 2615 opp-supported-hw = <0xa>;
2951 }; 2616 };
2952 2617
2953 opp-587000000 2618 opp-587000000 {
2954 opp-h 2619 opp-hz = /bits/ 64 <587000000>;
2955 opp-l 2620 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2956 opp-s 2621 opp-supported-hw = <0xb>;
2957 }; 2622 };
2958 2623
2959 opp-525000000 2624 opp-525000000 {
2960 opp-h 2625 opp-hz = /bits/ 64 <525000000>;
2961 opp-l 2626 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2962 opp-s 2627 opp-supported-hw = <0xf>;
2963 }; 2628 };
2964 2629
2965 opp-490000000 2630 opp-490000000 {
2966 opp-h 2631 opp-hz = /bits/ 64 <490000000>;
2967 opp-l 2632 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2968 opp-s 2633 opp-supported-hw = <0xf>;
2969 }; 2634 };
2970 2635
2971 opp-441600000 2636 opp-441600000 {
2972 opp-h 2637 opp-hz = /bits/ 64 <441600000>;
2973 opp-l 2638 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
2974 opp-s 2639 opp-supported-hw = <0xf>;
2975 }; 2640 };
2976 2641
2977 opp-400000000 2642 opp-400000000 {
2978 opp-h 2643 opp-hz = /bits/ 64 <400000000>;
2979 opp-l 2644 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2980 opp-s 2645 opp-supported-hw = <0xf>;
2981 }; 2646 };
2982 2647
2983 opp-305000000 2648 opp-305000000 {
2984 opp-h 2649 opp-hz = /bits/ 64 <305000000>;
2985 opp-l 2650 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2986 opp-s 2651 opp-supported-hw = <0xf>;
2987 }; 2652 };
2988 }; 2653 };
2989 }; 2654 };
2990 2655
2991 gmu: gmu@3d6a000 { 2656 gmu: gmu@3d6a000 {
2992 compatible = "qcom,ad 2657 compatible = "qcom,adreno-gmu-650.2", "qcom,adreno-gmu";
2993 2658
2994 reg = <0 0x03d6a000 0 2659 reg = <0 0x03d6a000 0 0x30000>,
2995 <0 0x3de0000 0 2660 <0 0x3de0000 0 0x10000>,
2996 <0 0xb290000 0 2661 <0 0xb290000 0 0x10000>,
2997 <0 0xb490000 0 2662 <0 0xb490000 0 0x10000>;
2998 reg-names = "gmu", "r 2663 reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq";
2999 2664
3000 interrupts = <GIC_SPI 2665 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
3001 <GIC_SPI 2666 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
3002 interrupt-names = "hf 2667 interrupt-names = "hfi", "gmu";
3003 2668
3004 clocks = <&gpucc GPU_ 2669 clocks = <&gpucc GPU_CC_AHB_CLK>,
3005 <&gpucc GPU_ 2670 <&gpucc GPU_CC_CX_GMU_CLK>,
3006 <&gpucc GPU_ 2671 <&gpucc GPU_CC_CXO_CLK>,
3007 <&gcc GCC_DD 2672 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
3008 <&gcc GCC_GP 2673 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
3009 clock-names = "ahb", 2674 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
3010 2675
3011 power-domains = <&gpu 2676 power-domains = <&gpucc GPU_CX_GDSC>,
3012 <&gpu 2677 <&gpucc GPU_GX_GDSC>;
3013 power-domain-names = 2678 power-domain-names = "cx", "gx";
3014 2679
3015 iommus = <&adreno_smm 2680 iommus = <&adreno_smmu 5 0x400>;
3016 2681
3017 operating-points-v2 = 2682 operating-points-v2 = <&gmu_opp_table>;
3018 2683
3019 status = "disabled"; 2684 status = "disabled";
3020 2685
3021 gmu_opp_table: opp-ta 2686 gmu_opp_table: opp-table {
3022 compatible = 2687 compatible = "operating-points-v2";
3023 2688
3024 opp-200000000 2689 opp-200000000 {
3025 opp-h 2690 opp-hz = /bits/ 64 <200000000>;
3026 opp-l 2691 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3027 }; 2692 };
3028 }; 2693 };
3029 }; 2694 };
3030 2695
3031 gpucc: clock-controller@3d900 2696 gpucc: clock-controller@3d90000 {
3032 compatible = "qcom,sm 2697 compatible = "qcom,sm8250-gpucc";
3033 reg = <0 0x03d90000 0 2698 reg = <0 0x03d90000 0 0x9000>;
3034 clocks = <&rpmhcc RPM 2699 clocks = <&rpmhcc RPMH_CXO_CLK>,
3035 <&gcc GCC_GP 2700 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
3036 <&gcc GCC_GP 2701 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
3037 clock-names = "bi_tcx 2702 clock-names = "bi_tcxo",
3038 "gcc_gp 2703 "gcc_gpu_gpll0_clk_src",
3039 "gcc_gp 2704 "gcc_gpu_gpll0_div_clk_src";
3040 #clock-cells = <1>; 2705 #clock-cells = <1>;
3041 #reset-cells = <1>; 2706 #reset-cells = <1>;
3042 #power-domain-cells = 2707 #power-domain-cells = <1>;
3043 }; 2708 };
3044 2709
3045 adreno_smmu: iommu@3da0000 { 2710 adreno_smmu: iommu@3da0000 {
3046 compatible = "qcom,sm 2711 compatible = "qcom,sm8250-smmu-500", "qcom,adreno-smmu",
3047 "qcom,sm 2712 "qcom,smmu-500", "arm,mmu-500";
3048 reg = <0 0x03da0000 0 2713 reg = <0 0x03da0000 0 0x10000>;
3049 #iommu-cells = <2>; 2714 #iommu-cells = <2>;
3050 #global-interrupts = 2715 #global-interrupts = <2>;
3051 interrupts = <GIC_SPI 2716 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
3052 <GIC_SPI 2717 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
3053 <GIC_SPI 2718 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
3054 <GIC_SPI 2719 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
3055 <GIC_SPI 2720 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
3056 <GIC_SPI 2721 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
3057 <GIC_SPI 2722 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
3058 <GIC_SPI 2723 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
3059 <GIC_SPI 2724 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
3060 <GIC_SPI 2725 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>;
3061 clocks = <&gpucc GPU_ 2726 clocks = <&gpucc GPU_CC_AHB_CLK>,
3062 <&gcc GCC_GP 2727 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
3063 <&gcc GCC_GP 2728 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
3064 clock-names = "ahb", 2729 clock-names = "ahb", "bus", "iface";
3065 2730
3066 power-domains = <&gpu 2731 power-domains = <&gpucc GPU_CX_GDSC>;
3067 dma-coherent; 2732 dma-coherent;
3068 }; 2733 };
3069 2734
3070 slpi: remoteproc@5c00000 { 2735 slpi: remoteproc@5c00000 {
3071 compatible = "qcom,sm 2736 compatible = "qcom,sm8250-slpi-pas";
3072 reg = <0 0x05c00000 0 2737 reg = <0 0x05c00000 0 0x4000>;
3073 2738
3074 interrupts-extended = !! 2739 interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
3075 2740 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
3076 2741 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
3077 2742 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
3078 2743 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
3079 interrupt-names = "wd 2744 interrupt-names = "wdog", "fatal", "ready",
3080 "ha 2745 "handover", "stop-ack";
3081 2746
3082 clocks = <&rpmhcc RPM 2747 clocks = <&rpmhcc RPMH_CXO_CLK>;
3083 clock-names = "xo"; 2748 clock-names = "xo";
3084 2749
3085 power-domains = <&rpm !! 2750 power-domains = <&rpmhpd SM8250_LCX>,
3086 <&rpm !! 2751 <&rpmhpd SM8250_LMX>;
3087 power-domain-names = 2752 power-domain-names = "lcx", "lmx";
3088 2753
3089 memory-region = <&slp 2754 memory-region = <&slpi_mem>;
3090 2755
3091 qcom,qmp = <&aoss_qmp 2756 qcom,qmp = <&aoss_qmp>;
3092 2757
3093 qcom,smem-states = <& 2758 qcom,smem-states = <&smp2p_slpi_out 0>;
3094 qcom,smem-state-names 2759 qcom,smem-state-names = "stop";
3095 2760
3096 status = "disabled"; 2761 status = "disabled";
3097 2762
3098 glink-edge { 2763 glink-edge {
3099 interrupts-ex 2764 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
3100 2765 IPCC_MPROC_SIGNAL_GLINK_QMP
3101 2766 IRQ_TYPE_EDGE_RISING>;
3102 mboxes = <&ip 2767 mboxes = <&ipcc IPCC_CLIENT_SLPI
3103 2768 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3104 2769
3105 label = "slpi 2770 label = "slpi";
3106 qcom,remote-p 2771 qcom,remote-pid = <3>;
3107 2772
3108 fastrpc { 2773 fastrpc {
3109 compa 2774 compatible = "qcom,fastrpc";
3110 qcom, 2775 qcom,glink-channels = "fastrpcglink-apps-dsp";
3111 label 2776 label = "sdsp";
3112 qcom, 2777 qcom,non-secure-domain;
3113 #addr 2778 #address-cells = <1>;
3114 #size 2779 #size-cells = <0>;
3115 2780
3116 compu 2781 compute-cb@1 {
3117 2782 compatible = "qcom,fastrpc-compute-cb";
3118 2783 reg = <1>;
3119 2784 iommus = <&apps_smmu 0x0541 0x0>;
3120 }; 2785 };
3121 2786
3122 compu 2787 compute-cb@2 {
3123 2788 compatible = "qcom,fastrpc-compute-cb";
3124 2789 reg = <2>;
3125 2790 iommus = <&apps_smmu 0x0542 0x0>;
3126 }; 2791 };
3127 2792
3128 compu 2793 compute-cb@3 {
3129 2794 compatible = "qcom,fastrpc-compute-cb";
3130 2795 reg = <3>;
3131 2796 iommus = <&apps_smmu 0x0543 0x0>;
3132 2797 /* note: shared-cb = <4> in downstream */
3133 }; 2798 };
3134 }; 2799 };
3135 }; 2800 };
3136 }; 2801 };
3137 2802
3138 stm@6002000 { 2803 stm@6002000 {
3139 compatible = "arm,cor 2804 compatible = "arm,coresight-stm", "arm,primecell";
3140 reg = <0 0x06002000 0 2805 reg = <0 0x06002000 0 0x1000>, <0 0x16280000 0 0x180000>;
3141 reg-names = "stm-base 2806 reg-names = "stm-base", "stm-stimulus-base";
3142 2807
3143 clocks = <&aoss_qmp>; 2808 clocks = <&aoss_qmp>;
3144 clock-names = "apb_pc 2809 clock-names = "apb_pclk";
3145 2810
3146 out-ports { 2811 out-ports {
3147 port { 2812 port {
3148 stm_o 2813 stm_out: endpoint {
3149 2814 remote-endpoint = <&funnel0_in7>;
3150 }; 2815 };
3151 }; 2816 };
3152 }; 2817 };
3153 }; 2818 };
3154 2819
3155 tpda@6004000 { 2820 tpda@6004000 {
3156 compatible = "qcom,co 2821 compatible = "qcom,coresight-tpda", "arm,primecell";
3157 reg = <0 0x06004000 0 2822 reg = <0 0x06004000 0 0x1000>;
3158 2823
3159 clocks = <&aoss_qmp>; 2824 clocks = <&aoss_qmp>;
3160 clock-names = "apb_pc 2825 clock-names = "apb_pclk";
3161 2826
3162 out-ports { 2827 out-ports {
>> 2828 #address-cells = <1>;
>> 2829 #size-cells = <0>;
3163 2830
3164 port { !! 2831 port@0 {
>> 2832 reg = <0>;
3165 tpda_ 2833 tpda_out_funnel_qatb: endpoint {
3166 2834 remote-endpoint = <&funnel_qatb_in_tpda>;
3167 }; 2835 };
3168 }; 2836 };
3169 }; 2837 };
3170 2838
3171 in-ports { 2839 in-ports {
3172 #address-cell 2840 #address-cells = <1>;
3173 #size-cells = 2841 #size-cells = <0>;
3174 2842
3175 port@9 { 2843 port@9 {
3176 reg = 2844 reg = <9>;
3177 tpda_ 2845 tpda_9_in_tpdm_mm: endpoint {
3178 2846 remote-endpoint = <&tpdm_mm_out_tpda9>;
3179 }; 2847 };
3180 }; 2848 };
3181 2849
3182 port@17 { 2850 port@17 {
3183 reg = 2851 reg = <23>;
3184 tpda_ 2852 tpda_23_in_tpdm_prng: endpoint {
3185 2853 remote-endpoint = <&tpdm_prng_out_tpda_23>;
3186 }; 2854 };
3187 }; 2855 };
3188 }; 2856 };
3189 }; 2857 };
3190 2858
3191 funnel@6005000 { 2859 funnel@6005000 {
3192 compatible = "arm,cor 2860 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3193 reg = <0 0x06005000 0 2861 reg = <0 0x06005000 0 0x1000>;
3194 2862
3195 clocks = <&aoss_qmp>; 2863 clocks = <&aoss_qmp>;
3196 clock-names = "apb_pc 2864 clock-names = "apb_pclk";
3197 2865
3198 out-ports { 2866 out-ports {
3199 port { 2867 port {
3200 funne 2868 funnel_qatb_out_funnel_in0: endpoint {
3201 2869 remote-endpoint = <&funnel_in0_in_funnel_qatb>;
3202 }; 2870 };
3203 }; 2871 };
3204 }; 2872 };
3205 2873
3206 in-ports { 2874 in-ports {
3207 port { !! 2875 #address-cells = <1>;
>> 2876 #size-cells = <0>;
>> 2877
>> 2878 port@0 {
>> 2879 reg = <0>;
3208 funne 2880 funnel_qatb_in_tpda: endpoint {
3209 2881 remote-endpoint = <&tpda_out_funnel_qatb>;
3210 }; 2882 };
3211 }; 2883 };
3212 }; 2884 };
3213 }; 2885 };
3214 2886
3215 funnel@6041000 { 2887 funnel@6041000 {
3216 compatible = "arm,cor 2888 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3217 reg = <0 0x06041000 0 2889 reg = <0 0x06041000 0 0x1000>;
3218 2890
3219 clocks = <&aoss_qmp>; 2891 clocks = <&aoss_qmp>;
3220 clock-names = "apb_pc 2892 clock-names = "apb_pclk";
3221 2893
3222 out-ports { 2894 out-ports {
3223 port { 2895 port {
3224 funne 2896 funnel_in0_out_funnel_merg: endpoint {
3225 2897 remote-endpoint = <&funnel_merg_in_funnel_in0>;
3226 }; 2898 };
3227 }; 2899 };
3228 }; 2900 };
3229 2901
3230 in-ports { 2902 in-ports {
3231 #address-cell 2903 #address-cells = <1>;
3232 #size-cells = 2904 #size-cells = <0>;
3233 2905
3234 port@6 { 2906 port@6 {
3235 reg = 2907 reg = <6>;
3236 funne 2908 funnel_in0_in_funnel_qatb: endpoint {
3237 2909 remote-endpoint = <&funnel_qatb_out_funnel_in0>;
3238 }; 2910 };
3239 }; 2911 };
3240 2912
3241 port@7 { 2913 port@7 {
3242 reg = 2914 reg = <7>;
3243 funne 2915 funnel0_in7: endpoint {
3244 2916 remote-endpoint = <&stm_out>;
3245 }; 2917 };
3246 }; 2918 };
3247 }; 2919 };
3248 }; 2920 };
3249 2921
3250 funnel@6042000 { 2922 funnel@6042000 {
3251 compatible = "arm,cor 2923 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3252 reg = <0 0x06042000 0 2924 reg = <0 0x06042000 0 0x1000>;
3253 2925
3254 clocks = <&aoss_qmp>; 2926 clocks = <&aoss_qmp>;
3255 clock-names = "apb_pc 2927 clock-names = "apb_pclk";
3256 2928
3257 out-ports { 2929 out-ports {
3258 port { 2930 port {
3259 funne 2931 funnel_in1_out_funnel_merg: endpoint {
3260 2932 remote-endpoint = <&funnel_merg_in_funnel_in1>;
3261 }; 2933 };
3262 }; 2934 };
3263 }; 2935 };
3264 2936
3265 in-ports { 2937 in-ports {
3266 #address-cell 2938 #address-cells = <1>;
3267 #size-cells = 2939 #size-cells = <0>;
3268 2940
3269 port@4 { 2941 port@4 {
3270 reg = 2942 reg = <4>;
3271 funne 2943 funnel_in1_in_funnel_apss_merg: endpoint {
3272 remot 2944 remote-endpoint = <&funnel_apss_merg_out_funnel_in1>;
3273 }; 2945 };
3274 }; 2946 };
3275 }; 2947 };
3276 }; 2948 };
3277 2949
3278 funnel@6045000 { 2950 funnel@6045000 {
3279 compatible = "arm,cor 2951 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3280 reg = <0 0x06045000 0 2952 reg = <0 0x06045000 0 0x1000>;
3281 2953
3282 clocks = <&aoss_qmp>; 2954 clocks = <&aoss_qmp>;
3283 clock-names = "apb_pc 2955 clock-names = "apb_pclk";
3284 2956
3285 out-ports { 2957 out-ports {
3286 port { 2958 port {
3287 funne 2959 funnel_merg_out_funnel_swao: endpoint {
3288 remot 2960 remote-endpoint = <&funnel_swao_in_funnel_merg>;
3289 }; 2961 };
3290 }; 2962 };
3291 }; 2963 };
3292 2964
3293 in-ports { 2965 in-ports {
3294 #address-cell 2966 #address-cells = <1>;
3295 #size-cells = 2967 #size-cells = <0>;
3296 2968
3297 port@0 { 2969 port@0 {
3298 reg = 2970 reg = <0>;
3299 funne 2971 funnel_merg_in_funnel_in0: endpoint {
3300 remot 2972 remote-endpoint = <&funnel_in0_out_funnel_merg>;
3301 }; 2973 };
3302 }; 2974 };
3303 2975
3304 port@1 { 2976 port@1 {
3305 reg = 2977 reg = <1>;
3306 funne 2978 funnel_merg_in_funnel_in1: endpoint {
3307 remot 2979 remote-endpoint = <&funnel_in1_out_funnel_merg>;
3308 }; 2980 };
3309 }; 2981 };
3310 }; 2982 };
3311 }; 2983 };
3312 2984
3313 replicator@6046000 { 2985 replicator@6046000 {
3314 compatible = "arm,cor 2986 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3315 reg = <0 0x06046000 0 2987 reg = <0 0x06046000 0 0x1000>;
3316 2988
3317 clocks = <&aoss_qmp>; 2989 clocks = <&aoss_qmp>;
3318 clock-names = "apb_pc 2990 clock-names = "apb_pclk";
3319 2991
3320 out-ports { 2992 out-ports {
3321 port { 2993 port {
3322 repli 2994 replicator_out: endpoint {
3323 2995 remote-endpoint = <&etr_in>;
3324 }; 2996 };
3325 }; 2997 };
3326 }; 2998 };
3327 2999
3328 in-ports { 3000 in-ports {
3329 port { 3001 port {
3330 repli 3002 replicator_cx_in_swao_out: endpoint {
3331 3003 remote-endpoint = <&replicator_swao_out_cx_in>;
3332 }; 3004 };
3333 }; 3005 };
3334 }; 3006 };
3335 }; 3007 };
3336 3008
3337 etr@6048000 { 3009 etr@6048000 {
3338 compatible = "arm,cor 3010 compatible = "arm,coresight-tmc", "arm,primecell";
3339 reg = <0 0x06048000 0 3011 reg = <0 0x06048000 0 0x1000>;
3340 3012
3341 clocks = <&aoss_qmp>; 3013 clocks = <&aoss_qmp>;
3342 clock-names = "apb_pc 3014 clock-names = "apb_pclk";
3343 arm,scatter-gather; 3015 arm,scatter-gather;
3344 3016
3345 in-ports { 3017 in-ports {
3346 port { 3018 port {
3347 etr_i 3019 etr_in: endpoint {
3348 3020 remote-endpoint = <&replicator_out>;
3349 }; 3021 };
3350 }; 3022 };
3351 }; 3023 };
3352 }; 3024 };
3353 3025
3354 tpdm@684c000 { 3026 tpdm@684c000 {
3355 compatible = "qcom,co 3027 compatible = "qcom,coresight-tpdm", "arm,primecell";
3356 reg = <0 0x0684c000 0 3028 reg = <0 0x0684c000 0 0x1000>;
3357 3029
3358 clocks = <&aoss_qmp>; 3030 clocks = <&aoss_qmp>;
3359 clock-names = "apb_pc 3031 clock-names = "apb_pclk";
3360 3032
3361 out-ports { 3033 out-ports {
3362 port { 3034 port {
3363 tpdm_ 3035 tpdm_prng_out_tpda_23: endpoint {
3364 3036 remote-endpoint = <&tpda_23_in_tpdm_prng>;
3365 }; 3037 };
3366 }; 3038 };
3367 }; 3039 };
3368 }; 3040 };
3369 3041
3370 funnel@6b04000 { 3042 funnel@6b04000 {
3371 compatible = "arm,cor 3043 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3372 arm,primecell-periphi 3044 arm,primecell-periphid = <0x000bb908>;
3373 3045
3374 reg = <0 0x06b04000 0 3046 reg = <0 0x06b04000 0 0x1000>;
3375 3047
3376 clocks = <&aoss_qmp>; 3048 clocks = <&aoss_qmp>;
3377 clock-names = "apb_pc 3049 clock-names = "apb_pclk";
3378 3050
3379 out-ports { 3051 out-ports {
3380 port { 3052 port {
3381 funne 3053 funnel_swao_out_etf: endpoint {
3382 3054 remote-endpoint = <&etf_in_funnel_swao_out>;
3383 }; 3055 };
3384 }; 3056 };
3385 }; 3057 };
3386 3058
3387 in-ports { 3059 in-ports {
3388 #address-cell 3060 #address-cells = <1>;
3389 #size-cells = 3061 #size-cells = <0>;
3390 3062
3391 port@7 { 3063 port@7 {
3392 reg = 3064 reg = <7>;
3393 funne 3065 funnel_swao_in_funnel_merg: endpoint {
3394 3066 remote-endpoint = <&funnel_merg_out_funnel_swao>;
3395 }; 3067 };
3396 }; 3068 };
3397 }; 3069 };
3398 }; 3070 };
3399 3071
3400 etf@6b05000 { 3072 etf@6b05000 {
3401 compatible = "arm,cor 3073 compatible = "arm,coresight-tmc", "arm,primecell";
3402 reg = <0 0x06b05000 0 3074 reg = <0 0x06b05000 0 0x1000>;
3403 3075
3404 clocks = <&aoss_qmp>; 3076 clocks = <&aoss_qmp>;
3405 clock-names = "apb_pc 3077 clock-names = "apb_pclk";
3406 3078
3407 out-ports { 3079 out-ports {
3408 port { 3080 port {
3409 etf_o 3081 etf_out: endpoint {
3410 3082 remote-endpoint = <&replicator_in>;
3411 }; 3083 };
3412 }; 3084 };
3413 }; 3085 };
3414 3086
3415 in-ports { 3087 in-ports {
>> 3088 #address-cells = <1>;
>> 3089 #size-cells = <0>;
3416 3090
3417 port { !! 3091 port@0 {
>> 3092 reg = <0>;
3418 etf_i 3093 etf_in_funnel_swao_out: endpoint {
3419 3094 remote-endpoint = <&funnel_swao_out_etf>;
3420 }; 3095 };
3421 }; 3096 };
3422 }; 3097 };
3423 }; 3098 };
3424 3099
3425 replicator@6b06000 { 3100 replicator@6b06000 {
3426 compatible = "arm,cor 3101 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3427 reg = <0 0x06b06000 0 3102 reg = <0 0x06b06000 0 0x1000>;
3428 3103
3429 clocks = <&aoss_qmp>; 3104 clocks = <&aoss_qmp>;
3430 clock-names = "apb_pc 3105 clock-names = "apb_pclk";
3431 3106
3432 out-ports { 3107 out-ports {
3433 port { 3108 port {
3434 repli 3109 replicator_swao_out_cx_in: endpoint {
3435 3110 remote-endpoint = <&replicator_cx_in_swao_out>;
3436 }; 3111 };
3437 }; 3112 };
3438 }; 3113 };
3439 3114
3440 in-ports { 3115 in-ports {
3441 port { 3116 port {
3442 repli 3117 replicator_in: endpoint {
3443 3118 remote-endpoint = <&etf_out>;
3444 }; 3119 };
3445 }; 3120 };
3446 }; 3121 };
3447 }; 3122 };
3448 3123
3449 tpdm@6c08000 { 3124 tpdm@6c08000 {
3450 compatible = "qcom,co 3125 compatible = "qcom,coresight-tpdm", "arm,primecell";
3451 reg = <0 0x06c08000 0 3126 reg = <0 0x06c08000 0 0x1000>;
3452 3127
3453 clocks = <&aoss_qmp>; 3128 clocks = <&aoss_qmp>;
3454 clock-names = "apb_pc 3129 clock-names = "apb_pclk";
3455 3130
3456 out-ports { 3131 out-ports {
3457 port { 3132 port {
3458 tpdm_ 3133 tpdm_mm_out_funnel_dl_mm: endpoint {
3459 3134 remote-endpoint = <&funnel_dl_mm_in_tpdm_mm>;
3460 }; 3135 };
3461 }; 3136 };
3462 }; 3137 };
3463 }; 3138 };
3464 3139
3465 funnel@6c0b000 { 3140 funnel@6c0b000 {
3466 compatible = "arm,cor 3141 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3467 reg = <0 0x06c0b000 0 3142 reg = <0 0x06c0b000 0 0x1000>;
3468 3143
3469 clocks = <&aoss_qmp>; 3144 clocks = <&aoss_qmp>;
3470 clock-names = "apb_pc 3145 clock-names = "apb_pclk";
3471 3146
3472 out-ports { 3147 out-ports {
3473 port { 3148 port {
3474 funne 3149 funnel_dl_mm_out_funnel_dl_center: endpoint {
3475 remot 3150 remote-endpoint = <&funnel_dl_center_in_funnel_dl_mm>;
3476 }; 3151 };
3477 }; 3152 };
3478 }; 3153 };
3479 3154
3480 in-ports { 3155 in-ports {
3481 #address-cell 3156 #address-cells = <1>;
3482 #size-cells = 3157 #size-cells = <0>;
3483 3158
3484 port@3 { 3159 port@3 {
3485 reg = 3160 reg = <3>;
3486 funne 3161 funnel_dl_mm_in_tpdm_mm: endpoint {
3487 3162 remote-endpoint = <&tpdm_mm_out_funnel_dl_mm>;
3488 }; 3163 };
3489 }; 3164 };
3490 }; 3165 };
3491 }; 3166 };
3492 3167
3493 funnel@6c2d000 { 3168 funnel@6c2d000 {
3494 compatible = "arm,cor 3169 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3495 reg = <0 0x06c2d000 0 3170 reg = <0 0x06c2d000 0 0x1000>;
3496 3171
3497 clocks = <&aoss_qmp>; 3172 clocks = <&aoss_qmp>;
3498 clock-names = "apb_pc 3173 clock-names = "apb_pclk";
3499 3174
3500 out-ports { 3175 out-ports {
>> 3176 #address-cells = <1>;
>> 3177 #size-cells = <0>;
3501 port { 3178 port {
3502 tpdm_ 3179 tpdm_mm_out_tpda9: endpoint {
3503 3180 remote-endpoint = <&tpda_9_in_tpdm_mm>;
3504 }; 3181 };
3505 }; 3182 };
3506 }; 3183 };
3507 3184
3508 in-ports { 3185 in-ports {
3509 #address-cell 3186 #address-cells = <1>;
3510 #size-cells = 3187 #size-cells = <0>;
3511 3188
3512 port@2 { 3189 port@2 {
3513 reg = 3190 reg = <2>;
3514 funne 3191 funnel_dl_center_in_funnel_dl_mm: endpoint {
3515 remot 3192 remote-endpoint = <&funnel_dl_mm_out_funnel_dl_center>;
3516 }; 3193 };
3517 }; 3194 };
3518 }; 3195 };
3519 }; 3196 };
3520 3197
3521 etm@7040000 { 3198 etm@7040000 {
3522 compatible = "arm,cor 3199 compatible = "arm,coresight-etm4x", "arm,primecell";
3523 reg = <0 0x07040000 0 3200 reg = <0 0x07040000 0 0x1000>;
3524 3201
3525 cpu = <&CPU0>; 3202 cpu = <&CPU0>;
3526 3203
3527 clocks = <&aoss_qmp>; 3204 clocks = <&aoss_qmp>;
3528 clock-names = "apb_pc 3205 clock-names = "apb_pclk";
3529 arm,coresight-loses-c 3206 arm,coresight-loses-context-with-cpu;
3530 3207
3531 out-ports { 3208 out-ports {
3532 port { 3209 port {
3533 etm0_ 3210 etm0_out: endpoint {
3534 3211 remote-endpoint = <&apss_funnel_in0>;
3535 }; 3212 };
3536 }; 3213 };
3537 }; 3214 };
3538 }; 3215 };
3539 3216
3540 etm@7140000 { 3217 etm@7140000 {
3541 compatible = "arm,cor 3218 compatible = "arm,coresight-etm4x", "arm,primecell";
3542 reg = <0 0x07140000 0 3219 reg = <0 0x07140000 0 0x1000>;
3543 3220
3544 cpu = <&CPU1>; 3221 cpu = <&CPU1>;
3545 3222
3546 clocks = <&aoss_qmp>; 3223 clocks = <&aoss_qmp>;
3547 clock-names = "apb_pc 3224 clock-names = "apb_pclk";
3548 arm,coresight-loses-c 3225 arm,coresight-loses-context-with-cpu;
3549 3226
3550 out-ports { 3227 out-ports {
3551 port { 3228 port {
3552 etm1_ 3229 etm1_out: endpoint {
3553 3230 remote-endpoint = <&apss_funnel_in1>;
3554 }; 3231 };
3555 }; 3232 };
3556 }; 3233 };
3557 }; 3234 };
3558 3235
3559 etm@7240000 { 3236 etm@7240000 {
3560 compatible = "arm,cor 3237 compatible = "arm,coresight-etm4x", "arm,primecell";
3561 reg = <0 0x07240000 0 3238 reg = <0 0x07240000 0 0x1000>;
3562 3239
3563 cpu = <&CPU2>; 3240 cpu = <&CPU2>;
3564 3241
3565 clocks = <&aoss_qmp>; 3242 clocks = <&aoss_qmp>;
3566 clock-names = "apb_pc 3243 clock-names = "apb_pclk";
3567 arm,coresight-loses-c 3244 arm,coresight-loses-context-with-cpu;
3568 3245
3569 out-ports { 3246 out-ports {
3570 port { 3247 port {
3571 etm2_ 3248 etm2_out: endpoint {
3572 3249 remote-endpoint = <&apss_funnel_in2>;
3573 }; 3250 };
3574 }; 3251 };
3575 }; 3252 };
3576 }; 3253 };
3577 3254
3578 etm@7340000 { 3255 etm@7340000 {
3579 compatible = "arm,cor 3256 compatible = "arm,coresight-etm4x", "arm,primecell";
3580 reg = <0 0x07340000 0 3257 reg = <0 0x07340000 0 0x1000>;
3581 3258
3582 cpu = <&CPU3>; 3259 cpu = <&CPU3>;
3583 3260
3584 clocks = <&aoss_qmp>; 3261 clocks = <&aoss_qmp>;
3585 clock-names = "apb_pc 3262 clock-names = "apb_pclk";
3586 arm,coresight-loses-c 3263 arm,coresight-loses-context-with-cpu;
3587 3264
3588 out-ports { 3265 out-ports {
3589 port { 3266 port {
3590 etm3_ 3267 etm3_out: endpoint {
3591 3268 remote-endpoint = <&apss_funnel_in3>;
3592 }; 3269 };
3593 }; 3270 };
3594 }; 3271 };
3595 }; 3272 };
3596 3273
3597 etm@7440000 { 3274 etm@7440000 {
3598 compatible = "arm,cor 3275 compatible = "arm,coresight-etm4x", "arm,primecell";
3599 reg = <0 0x07440000 0 3276 reg = <0 0x07440000 0 0x1000>;
3600 3277
3601 cpu = <&CPU4>; 3278 cpu = <&CPU4>;
3602 3279
3603 clocks = <&aoss_qmp>; 3280 clocks = <&aoss_qmp>;
3604 clock-names = "apb_pc 3281 clock-names = "apb_pclk";
3605 arm,coresight-loses-c 3282 arm,coresight-loses-context-with-cpu;
3606 3283
3607 out-ports { 3284 out-ports {
3608 port { 3285 port {
3609 etm4_ 3286 etm4_out: endpoint {
3610 3287 remote-endpoint = <&apss_funnel_in4>;
3611 }; 3288 };
3612 }; 3289 };
3613 }; 3290 };
3614 }; 3291 };
3615 3292
3616 etm@7540000 { 3293 etm@7540000 {
3617 compatible = "arm,cor 3294 compatible = "arm,coresight-etm4x", "arm,primecell";
3618 reg = <0 0x07540000 0 3295 reg = <0 0x07540000 0 0x1000>;
3619 3296
3620 cpu = <&CPU5>; 3297 cpu = <&CPU5>;
3621 3298
3622 clocks = <&aoss_qmp>; 3299 clocks = <&aoss_qmp>;
3623 clock-names = "apb_pc 3300 clock-names = "apb_pclk";
3624 arm,coresight-loses-c 3301 arm,coresight-loses-context-with-cpu;
3625 3302
3626 out-ports { 3303 out-ports {
3627 port { 3304 port {
3628 etm5_ 3305 etm5_out: endpoint {
3629 3306 remote-endpoint = <&apss_funnel_in5>;
3630 }; 3307 };
3631 }; 3308 };
3632 }; 3309 };
3633 }; 3310 };
3634 3311
3635 etm@7640000 { 3312 etm@7640000 {
3636 compatible = "arm,cor 3313 compatible = "arm,coresight-etm4x", "arm,primecell";
3637 reg = <0 0x07640000 0 3314 reg = <0 0x07640000 0 0x1000>;
3638 3315
3639 cpu = <&CPU6>; 3316 cpu = <&CPU6>;
3640 3317
3641 clocks = <&aoss_qmp>; 3318 clocks = <&aoss_qmp>;
3642 clock-names = "apb_pc 3319 clock-names = "apb_pclk";
3643 arm,coresight-loses-c 3320 arm,coresight-loses-context-with-cpu;
3644 3321
3645 out-ports { 3322 out-ports {
3646 port { 3323 port {
3647 etm6_ 3324 etm6_out: endpoint {
3648 3325 remote-endpoint = <&apss_funnel_in6>;
3649 }; 3326 };
3650 }; 3327 };
3651 }; 3328 };
3652 }; 3329 };
3653 3330
3654 etm@7740000 { 3331 etm@7740000 {
3655 compatible = "arm,cor 3332 compatible = "arm,coresight-etm4x", "arm,primecell";
3656 reg = <0 0x07740000 0 3333 reg = <0 0x07740000 0 0x1000>;
3657 3334
3658 cpu = <&CPU7>; 3335 cpu = <&CPU7>;
3659 3336
3660 clocks = <&aoss_qmp>; 3337 clocks = <&aoss_qmp>;
3661 clock-names = "apb_pc 3338 clock-names = "apb_pclk";
3662 arm,coresight-loses-c 3339 arm,coresight-loses-context-with-cpu;
3663 3340
3664 out-ports { 3341 out-ports {
3665 port { 3342 port {
3666 etm7_ 3343 etm7_out: endpoint {
3667 3344 remote-endpoint = <&apss_funnel_in7>;
3668 }; 3345 };
3669 }; 3346 };
3670 }; 3347 };
3671 }; 3348 };
3672 3349
3673 funnel@7800000 { 3350 funnel@7800000 {
3674 compatible = "arm,cor 3351 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3675 reg = <0 0x07800000 0 3352 reg = <0 0x07800000 0 0x1000>;
3676 3353
3677 clocks = <&aoss_qmp>; 3354 clocks = <&aoss_qmp>;
3678 clock-names = "apb_pc 3355 clock-names = "apb_pclk";
3679 3356
3680 out-ports { 3357 out-ports {
3681 port { 3358 port {
3682 funne 3359 funnel_apss_out_funnel_apss_merg: endpoint {
3683 remot 3360 remote-endpoint = <&funnel_apss_merg_in_funnel_apss>;
3684 }; 3361 };
3685 }; 3362 };
3686 }; 3363 };
3687 3364
3688 in-ports { 3365 in-ports {
3689 #address-cell 3366 #address-cells = <1>;
3690 #size-cells = 3367 #size-cells = <0>;
3691 3368
3692 port@0 { 3369 port@0 {
3693 reg = 3370 reg = <0>;
3694 apss_ 3371 apss_funnel_in0: endpoint {
3695 3372 remote-endpoint = <&etm0_out>;
3696 }; 3373 };
3697 }; 3374 };
3698 3375
3699 port@1 { 3376 port@1 {
3700 reg = 3377 reg = <1>;
3701 apss_ 3378 apss_funnel_in1: endpoint {
3702 3379 remote-endpoint = <&etm1_out>;
3703 }; 3380 };
3704 }; 3381 };
3705 3382
3706 port@2 { 3383 port@2 {
3707 reg = 3384 reg = <2>;
3708 apss_ 3385 apss_funnel_in2: endpoint {
3709 3386 remote-endpoint = <&etm2_out>;
3710 }; 3387 };
3711 }; 3388 };
3712 3389
3713 port@3 { 3390 port@3 {
3714 reg = 3391 reg = <3>;
3715 apss_ 3392 apss_funnel_in3: endpoint {
3716 3393 remote-endpoint = <&etm3_out>;
3717 }; 3394 };
3718 }; 3395 };
3719 3396
3720 port@4 { 3397 port@4 {
3721 reg = 3398 reg = <4>;
3722 apss_ 3399 apss_funnel_in4: endpoint {
3723 3400 remote-endpoint = <&etm4_out>;
3724 }; 3401 };
3725 }; 3402 };
3726 3403
3727 port@5 { 3404 port@5 {
3728 reg = 3405 reg = <5>;
3729 apss_ 3406 apss_funnel_in5: endpoint {
3730 3407 remote-endpoint = <&etm5_out>;
3731 }; 3408 };
3732 }; 3409 };
3733 3410
3734 port@6 { 3411 port@6 {
3735 reg = 3412 reg = <6>;
3736 apss_ 3413 apss_funnel_in6: endpoint {
3737 3414 remote-endpoint = <&etm6_out>;
3738 }; 3415 };
3739 }; 3416 };
3740 3417
3741 port@7 { 3418 port@7 {
3742 reg = 3419 reg = <7>;
3743 apss_ 3420 apss_funnel_in7: endpoint {
3744 3421 remote-endpoint = <&etm7_out>;
3745 }; 3422 };
3746 }; 3423 };
3747 }; 3424 };
3748 }; 3425 };
3749 3426
3750 funnel@7810000 { 3427 funnel@7810000 {
3751 compatible = "arm,cor 3428 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3752 reg = <0 0x07810000 0 3429 reg = <0 0x07810000 0 0x1000>;
3753 3430
3754 clocks = <&aoss_qmp>; 3431 clocks = <&aoss_qmp>;
3755 clock-names = "apb_pc 3432 clock-names = "apb_pclk";
3756 3433
3757 out-ports { 3434 out-ports {
3758 port { 3435 port {
3759 funne 3436 funnel_apss_merg_out_funnel_in1: endpoint {
3760 remot 3437 remote-endpoint = <&funnel_in1_in_funnel_apss_merg>;
3761 }; 3438 };
3762 }; 3439 };
3763 }; 3440 };
3764 3441
3765 in-ports { 3442 in-ports {
3766 port { !! 3443 #address-cells = <1>;
>> 3444 #size-cells = <0>;
>> 3445
>> 3446 port@0 {
>> 3447 reg = <0>;
3767 funne 3448 funnel_apss_merg_in_funnel_apss: endpoint {
3768 remot 3449 remote-endpoint = <&funnel_apss_out_funnel_apss_merg>;
3769 }; 3450 };
3770 }; 3451 };
3771 }; 3452 };
3772 }; 3453 };
3773 3454
3774 cdsp: remoteproc@8300000 { 3455 cdsp: remoteproc@8300000 {
3775 compatible = "qcom,sm 3456 compatible = "qcom,sm8250-cdsp-pas";
3776 reg = <0 0x08300000 0 3457 reg = <0 0x08300000 0 0x10000>;
3777 3458
3778 interrupts-extended = !! 3459 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
3779 3460 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
3780 3461 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
3781 3462 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
3782 3463 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
3783 interrupt-names = "wd 3464 interrupt-names = "wdog", "fatal", "ready",
3784 "ha 3465 "handover", "stop-ack";
3785 3466
3786 clocks = <&rpmhcc RPM 3467 clocks = <&rpmhcc RPMH_CXO_CLK>;
3787 clock-names = "xo"; 3468 clock-names = "xo";
3788 3469
3789 power-domains = <&rpm !! 3470 power-domains = <&rpmhpd SM8250_CX>;
3790 3471
3791 memory-region = <&cds 3472 memory-region = <&cdsp_mem>;
3792 3473
3793 qcom,qmp = <&aoss_qmp 3474 qcom,qmp = <&aoss_qmp>;
3794 3475
3795 qcom,smem-states = <& 3476 qcom,smem-states = <&smp2p_cdsp_out 0>;
3796 qcom,smem-state-names 3477 qcom,smem-state-names = "stop";
3797 3478
3798 status = "disabled"; 3479 status = "disabled";
3799 3480
3800 glink-edge { 3481 glink-edge {
3801 interrupts-ex 3482 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
3802 3483 IPCC_MPROC_SIGNAL_GLINK_QMP
3803 3484 IRQ_TYPE_EDGE_RISING>;
3804 mboxes = <&ip 3485 mboxes = <&ipcc IPCC_CLIENT_CDSP
3805 3486 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3806 3487
3807 label = "cdsp 3488 label = "cdsp";
3808 qcom,remote-p 3489 qcom,remote-pid = <5>;
3809 3490
3810 fastrpc { 3491 fastrpc {
3811 compa 3492 compatible = "qcom,fastrpc";
3812 qcom, 3493 qcom,glink-channels = "fastrpcglink-apps-dsp";
3813 label 3494 label = "cdsp";
3814 qcom, 3495 qcom,non-secure-domain;
3815 #addr 3496 #address-cells = <1>;
3816 #size 3497 #size-cells = <0>;
3817 3498
3818 compu 3499 compute-cb@1 {
3819 3500 compatible = "qcom,fastrpc-compute-cb";
3820 3501 reg = <1>;
3821 3502 iommus = <&apps_smmu 0x1001 0x0460>;
3822 }; 3503 };
3823 3504
3824 compu 3505 compute-cb@2 {
3825 3506 compatible = "qcom,fastrpc-compute-cb";
3826 3507 reg = <2>;
3827 3508 iommus = <&apps_smmu 0x1002 0x0460>;
3828 }; 3509 };
3829 3510
3830 compu 3511 compute-cb@3 {
3831 3512 compatible = "qcom,fastrpc-compute-cb";
3832 3513 reg = <3>;
3833 3514 iommus = <&apps_smmu 0x1003 0x0460>;
3834 }; 3515 };
3835 3516
3836 compu 3517 compute-cb@4 {
3837 3518 compatible = "qcom,fastrpc-compute-cb";
3838 3519 reg = <4>;
3839 3520 iommus = <&apps_smmu 0x1004 0x0460>;
3840 }; 3521 };
3841 3522
3842 compu 3523 compute-cb@5 {
3843 3524 compatible = "qcom,fastrpc-compute-cb";
3844 3525 reg = <5>;
3845 3526 iommus = <&apps_smmu 0x1005 0x0460>;
3846 }; 3527 };
3847 3528
3848 compu 3529 compute-cb@6 {
3849 3530 compatible = "qcom,fastrpc-compute-cb";
3850 3531 reg = <6>;
3851 3532 iommus = <&apps_smmu 0x1006 0x0460>;
3852 }; 3533 };
3853 3534
3854 compu 3535 compute-cb@7 {
3855 3536 compatible = "qcom,fastrpc-compute-cb";
3856 3537 reg = <7>;
3857 3538 iommus = <&apps_smmu 0x1007 0x0460>;
3858 }; 3539 };
3859 3540
3860 compu 3541 compute-cb@8 {
3861 3542 compatible = "qcom,fastrpc-compute-cb";
3862 3543 reg = <8>;
3863 3544 iommus = <&apps_smmu 0x1008 0x0460>;
3864 }; 3545 };
3865 3546
3866 /* no 3547 /* note: secure cb9 in downstream */
3867 }; 3548 };
3868 }; 3549 };
3869 }; 3550 };
3870 3551
3871 usb_1_hsphy: phy@88e3000 { 3552 usb_1_hsphy: phy@88e3000 {
3872 compatible = "qcom,sm 3553 compatible = "qcom,sm8250-usb-hs-phy",
3873 "qcom,us 3554 "qcom,usb-snps-hs-7nm-phy";
3874 reg = <0 0x088e3000 0 3555 reg = <0 0x088e3000 0 0x400>;
3875 status = "disabled"; 3556 status = "disabled";
3876 #phy-cells = <0>; 3557 #phy-cells = <0>;
3877 3558
3878 clocks = <&rpmhcc RPM 3559 clocks = <&rpmhcc RPMH_CXO_CLK>;
3879 clock-names = "ref"; 3560 clock-names = "ref";
3880 3561
3881 resets = <&gcc GCC_QU 3562 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3882 }; 3563 };
3883 3564
3884 usb_2_hsphy: phy@88e4000 { 3565 usb_2_hsphy: phy@88e4000 {
3885 compatible = "qcom,sm 3566 compatible = "qcom,sm8250-usb-hs-phy",
3886 "qcom,us 3567 "qcom,usb-snps-hs-7nm-phy";
3887 reg = <0 0x088e4000 0 3568 reg = <0 0x088e4000 0 0x400>;
3888 status = "disabled"; 3569 status = "disabled";
3889 #phy-cells = <0>; 3570 #phy-cells = <0>;
3890 3571
3891 clocks = <&rpmhcc RPM 3572 clocks = <&rpmhcc RPMH_CXO_CLK>;
3892 clock-names = "ref"; 3573 clock-names = "ref";
3893 3574
3894 resets = <&gcc GCC_QU 3575 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3895 }; 3576 };
3896 3577
3897 usb_1_qmpphy: phy@88e8000 { !! 3578 usb_1_qmpphy: phy@88e9000 {
3898 compatible = "qcom,sm 3579 compatible = "qcom,sm8250-qmp-usb3-dp-phy";
3899 reg = <0 0x088e8000 0 !! 3580 reg = <0 0x088e9000 0 0x200>,
>> 3581 <0 0x088e8000 0 0x40>,
>> 3582 <0 0x088ea000 0 0x200>;
3900 status = "disabled"; 3583 status = "disabled";
>> 3584 #address-cells = <2>;
>> 3585 #size-cells = <2>;
>> 3586 ranges;
3901 3587
3902 clocks = <&gcc GCC_US 3588 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
3903 <&rpmhcc RPM 3589 <&rpmhcc RPMH_CXO_CLK>,
3904 <&gcc GCC_US !! 3590 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
3905 <&gcc GCC_US !! 3591 clock-names = "aux", "ref_clk_src", "com_aux";
3906 clock-names = "aux", <<
3907 "ref", <<
3908 "com_au <<
3909 "usb3_p <<
3910 3592
3911 resets = <&gcc GCC_US 3593 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
3912 <&gcc GCC_US 3594 <&gcc GCC_USB3_PHY_PRIM_BCR>;
3913 reset-names = "phy", 3595 reset-names = "phy", "common";
3914 3596
3915 #clock-cells = <1>; !! 3597 usb_1_ssphy: usb3-phy@88e9200 {
3916 #phy-cells = <1>; !! 3598 reg = <0 0x088e9200 0 0x200>,
3917 !! 3599 <0 0x088e9400 0 0x200>,
3918 orientation-switch; !! 3600 <0 0x088e9c00 0 0x400>,
3919 !! 3601 <0 0x088e9600 0 0x200>,
3920 ports { !! 3602 <0 0x088e9800 0 0x200>,
3921 #address-cell !! 3603 <0 0x088e9a00 0 0x100>;
3922 #size-cells = !! 3604 #clock-cells = <0>;
3923 !! 3605 #phy-cells = <0>;
3924 port@0 { !! 3606 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3925 reg = !! 3607 clock-names = "pipe0";
3926 usb_1 !! 3608 clock-output-names = "usb3_phy_pipe_clk_src";
3927 }; !! 3609 };
3928 <<
3929 port@1 { <<
3930 reg = <<
3931 <<
3932 usb_1 <<
3933 <<
3934 }; <<
3935 }; <<
3936 <<
3937 port@2 { <<
3938 reg = <<
3939 3610
3940 usb_1 !! 3611 dp_phy: dp-phy@88ea200 {
3941 }; !! 3612 reg = <0 0x088ea200 0 0x200>,
>> 3613 <0 0x088ea400 0 0x200>,
>> 3614 <0 0x088eaa00 0 0x200>,
>> 3615 <0 0x088ea600 0 0x200>,
>> 3616 <0 0x088ea800 0 0x200>;
>> 3617 #phy-cells = <0>;
>> 3618 #clock-cells = <1>;
3942 }; 3619 };
3943 }; 3620 };
3944 3621
3945 usb_2_qmpphy: phy@88eb000 { 3622 usb_2_qmpphy: phy@88eb000 {
3946 compatible = "qcom,sm 3623 compatible = "qcom,sm8250-qmp-usb3-uni-phy";
3947 reg = <0 0x088eb000 0 !! 3624 reg = <0 0x088eb000 0 0x200>;
>> 3625 status = "disabled";
>> 3626 #address-cells = <2>;
>> 3627 #size-cells = <2>;
>> 3628 ranges;
3948 3629
3949 clocks = <&gcc GCC_US 3630 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
>> 3631 <&rpmhcc RPMH_CXO_CLK>,
3950 <&gcc GCC_US 3632 <&gcc GCC_USB3_SEC_CLKREF_EN>,
3951 <&gcc GCC_US !! 3633 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
3952 <&gcc GCC_US !! 3634 clock-names = "aux", "ref_clk_src", "ref", "com_aux";
3953 clock-names = "aux", <<
3954 "ref", <<
3955 "com_au <<
3956 "pipe"; <<
3957 clock-output-names = <<
3958 #clock-cells = <0>; <<
3959 #phy-cells = <0>; <<
3960 3635
3961 resets = <&gcc GCC_US !! 3636 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
3962 <&gcc GCC_US !! 3637 <&gcc GCC_USB3_PHY_SEC_BCR>;
3963 reset-names = "phy", !! 3638 reset-names = "phy", "common";
3964 "phy_ph <<
3965 3639
3966 status = "disabled"; !! 3640 usb_2_ssphy: phy@88eb200 {
>> 3641 reg = <0 0x088eb200 0 0x200>,
>> 3642 <0 0x088eb400 0 0x200>,
>> 3643 <0 0x088eb800 0 0x800>;
>> 3644 #clock-cells = <0>;
>> 3645 #phy-cells = <0>;
>> 3646 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
>> 3647 clock-names = "pipe0";
>> 3648 clock-output-names = "usb3_uni_phy_pipe_clk_src";
>> 3649 };
3967 }; 3650 };
3968 3651
3969 sdhc_2: mmc@8804000 { 3652 sdhc_2: mmc@8804000 {
3970 compatible = "qcom,sm 3653 compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
3971 reg = <0 0x08804000 0 3654 reg = <0 0x08804000 0 0x1000>;
3972 3655
3973 interrupts = <GIC_SPI 3656 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
3974 <GIC_SPI 3657 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
3975 interrupt-names = "hc 3658 interrupt-names = "hc_irq", "pwr_irq";
3976 3659
3977 clocks = <&gcc GCC_SD 3660 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3978 <&gcc GCC_SD 3661 <&gcc GCC_SDCC2_APPS_CLK>,
3979 <&rpmhcc RPM 3662 <&rpmhcc RPMH_CXO_CLK>;
3980 clock-names = "iface" 3663 clock-names = "iface", "core", "xo";
3981 iommus = <&apps_smmu 3664 iommus = <&apps_smmu 0x4a0 0x0>;
3982 qcom,dll-config = <0x 3665 qcom,dll-config = <0x0007642c>;
3983 qcom,ddr-config = <0x 3666 qcom,ddr-config = <0x80040868>;
3984 power-domains = <&rpm !! 3667 power-domains = <&rpmhpd SM8250_CX>;
3985 operating-points-v2 = 3668 operating-points-v2 = <&sdhc2_opp_table>;
3986 3669
3987 status = "disabled"; 3670 status = "disabled";
3988 3671
3989 sdhc2_opp_table: opp- 3672 sdhc2_opp_table: opp-table {
3990 compatible = 3673 compatible = "operating-points-v2";
3991 3674
3992 opp-19200000 3675 opp-19200000 {
3993 opp-h 3676 opp-hz = /bits/ 64 <19200000>;
3994 requi 3677 required-opps = <&rpmhpd_opp_min_svs>;
3995 }; 3678 };
3996 3679
3997 opp-50000000 3680 opp-50000000 {
3998 opp-h 3681 opp-hz = /bits/ 64 <50000000>;
3999 requi 3682 required-opps = <&rpmhpd_opp_low_svs>;
4000 }; 3683 };
4001 3684
4002 opp-100000000 3685 opp-100000000 {
4003 opp-h 3686 opp-hz = /bits/ 64 <100000000>;
4004 requi 3687 required-opps = <&rpmhpd_opp_svs>;
4005 }; 3688 };
4006 3689
4007 opp-202000000 3690 opp-202000000 {
4008 opp-h 3691 opp-hz = /bits/ 64 <202000000>;
4009 requi 3692 required-opps = <&rpmhpd_opp_svs_l1>;
4010 }; 3693 };
4011 }; 3694 };
4012 }; 3695 };
4013 3696
4014 pmu@9091000 { <<
4015 compatible = "qcom,sm <<
4016 reg = <0 0x09091000 0 <<
4017 <<
4018 interrupts = <GIC_SPI <<
4019 <<
4020 interconnects = <&mc_ <<
4021 <<
4022 operating-points-v2 = <<
4023 <<
4024 llcc_bwmon_opp_table: <<
4025 compatible = <<
4026 <<
4027 opp-800000 { <<
4028 opp-p <<
4029 }; <<
4030 <<
4031 opp-1200000 { <<
4032 opp-p <<
4033 }; <<
4034 <<
4035 opp-1804000 { <<
4036 opp-p <<
4037 }; <<
4038 <<
4039 opp-2188000 { <<
4040 opp-p <<
4041 }; <<
4042 <<
4043 opp-2724000 { <<
4044 opp-p <<
4045 }; <<
4046 <<
4047 opp-3072000 { <<
4048 opp-p <<
4049 }; <<
4050 <<
4051 opp-4068000 { <<
4052 opp-p <<
4053 }; <<
4054 <<
4055 /* 1353 MHz, <<
4056 <<
4057 opp-6220000 { <<
4058 opp-p <<
4059 }; <<
4060 <<
4061 opp-7216000 { <<
4062 opp-p <<
4063 }; <<
4064 <<
4065 opp-8368000 { <<
4066 opp-p <<
4067 }; <<
4068 <<
4069 /* LPDDR5 */ <<
4070 opp-10944000 <<
4071 opp-p <<
4072 }; <<
4073 }; <<
4074 }; <<
4075 <<
4076 pmu@90b6400 { <<
4077 compatible = "qcom,sm <<
4078 reg = <0 0x090b6400 0 <<
4079 <<
4080 interrupts = <GIC_SPI <<
4081 <<
4082 interconnects = <&gem <<
4083 operating-points-v2 = <<
4084 <<
4085 cpu_bwmon_opp_table: <<
4086 compatible = <<
4087 <<
4088 opp-800000 { <<
4089 opp-p <<
4090 }; <<
4091 <<
4092 opp-1804000 { <<
4093 opp-p <<
4094 }; <<
4095 <<
4096 opp-2188000 { <<
4097 opp-p <<
4098 }; <<
4099 <<
4100 opp-2724000 { <<
4101 opp-p <<
4102 }; <<
4103 <<
4104 opp-3072000 { <<
4105 opp-p <<
4106 }; <<
4107 <<
4108 /* 1017MHz, 1 <<
4109 <<
4110 opp-6220000 { <<
4111 opp-p <<
4112 }; <<
4113 <<
4114 opp-6832000 { <<
4115 opp-p <<
4116 }; <<
4117 <<
4118 opp-8368000 { <<
4119 opp-p <<
4120 }; <<
4121 <<
4122 /* 2133MHz, L <<
4123 <<
4124 /* LPDDR5 */ <<
4125 opp-10944000 <<
4126 opp-p <<
4127 }; <<
4128 <<
4129 /* LPDDR5 */ <<
4130 opp-12784000 <<
4131 opp-p <<
4132 }; <<
4133 }; <<
4134 }; <<
4135 <<
4136 dc_noc: interconnect@90c0000 3697 dc_noc: interconnect@90c0000 {
4137 compatible = "qcom,sm 3698 compatible = "qcom,sm8250-dc-noc";
4138 reg = <0 0x090c0000 0 3699 reg = <0 0x090c0000 0 0x4200>;
4139 #interconnect-cells = 3700 #interconnect-cells = <2>;
4140 qcom,bcm-voters = <&a 3701 qcom,bcm-voters = <&apps_bcm_voter>;
4141 }; 3702 };
4142 3703
4143 gem_noc: interconnect@9100000 3704 gem_noc: interconnect@9100000 {
4144 compatible = "qcom,sm 3705 compatible = "qcom,sm8250-gem-noc";
4145 reg = <0 0x09100000 0 3706 reg = <0 0x09100000 0 0xb4000>;
4146 #interconnect-cells = 3707 #interconnect-cells = <2>;
4147 qcom,bcm-voters = <&a 3708 qcom,bcm-voters = <&apps_bcm_voter>;
4148 }; 3709 };
4149 3710
4150 npu_noc: interconnect@9990000 3711 npu_noc: interconnect@9990000 {
4151 compatible = "qcom,sm 3712 compatible = "qcom,sm8250-npu-noc";
4152 reg = <0 0x09990000 0 3713 reg = <0 0x09990000 0 0x1600>;
4153 #interconnect-cells = 3714 #interconnect-cells = <2>;
4154 qcom,bcm-voters = <&a 3715 qcom,bcm-voters = <&apps_bcm_voter>;
4155 }; 3716 };
4156 3717
4157 usb_1: usb@a6f8800 { 3718 usb_1: usb@a6f8800 {
4158 compatible = "qcom,sm 3719 compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
4159 reg = <0 0x0a6f8800 0 3720 reg = <0 0x0a6f8800 0 0x400>;
4160 status = "disabled"; 3721 status = "disabled";
4161 #address-cells = <2>; 3722 #address-cells = <2>;
4162 #size-cells = <2>; 3723 #size-cells = <2>;
4163 ranges; 3724 ranges;
4164 dma-ranges; 3725 dma-ranges;
4165 3726
4166 clocks = <&gcc GCC_CF 3727 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
4167 <&gcc GCC_US 3728 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
4168 <&gcc GCC_AG 3729 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
4169 <&gcc GCC_US 3730 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
4170 <&gcc GCC_US 3731 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4171 <&gcc GCC_US 3732 <&gcc GCC_USB3_SEC_CLKREF_EN>;
4172 clock-names = "cfg_no 3733 clock-names = "cfg_noc",
4173 "core", 3734 "core",
4174 "iface" 3735 "iface",
4175 "sleep" 3736 "sleep",
4176 "mock_u 3737 "mock_utmi",
4177 "xo"; 3738 "xo";
4178 3739
4179 assigned-clocks = <&g 3740 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4180 <&g 3741 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
4181 assigned-clock-rates 3742 assigned-clock-rates = <19200000>, <200000000>;
4182 3743
4183 interrupts-extended = !! 3744 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
4184 !! 3745 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
4185 <<
4186 3746 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
4187 !! 3747 <&pdc 14 IRQ_TYPE_EDGE_BOTH>;
4188 interrupt-names = "pw !! 3748 interrupt-names = "hs_phy_irq",
4189 "hs !! 3749 "ss_phy_irq",
4190 "dp <<
4191 "dm 3750 "dm_hs_phy_irq",
4192 "ss !! 3751 "dp_hs_phy_irq";
4193 3752
4194 power-domains = <&gcc 3753 power-domains = <&gcc USB30_PRIM_GDSC>;
4195 wakeup-source; <<
4196 3754
4197 resets = <&gcc GCC_US 3755 resets = <&gcc GCC_USB30_PRIM_BCR>;
4198 3756
4199 interconnects = <&agg 3757 interconnects = <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>,
4200 <&gem 3758 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>;
4201 interconnect-names = 3759 interconnect-names = "usb-ddr", "apps-usb";
4202 3760
4203 usb_1_dwc3: usb@a6000 3761 usb_1_dwc3: usb@a600000 {
4204 compatible = 3762 compatible = "snps,dwc3";
4205 reg = <0 0x0a 3763 reg = <0 0x0a600000 0 0xcd00>;
4206 interrupts = 3764 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
4207 iommus = <&ap 3765 iommus = <&apps_smmu 0x0 0x0>;
4208 snps,dis_u2_s 3766 snps,dis_u2_susphy_quirk;
4209 snps,dis_enbl 3767 snps,dis_enblslpm_quirk;
4210 phys = <&usb_ !! 3768 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
4211 phy-names = " 3769 phy-names = "usb2-phy", "usb3-phy";
4212 <<
4213 ports { <<
4214 #addr <<
4215 #size <<
4216 <<
4217 port@ <<
4218 <<
4219 <<
4220 <<
4221 <<
4222 }; <<
4223 <<
4224 port@ <<
4225 <<
4226 <<
4227 <<
4228 <<
4229 <<
4230 }; <<
4231 }; <<
4232 }; 3770 };
4233 }; 3771 };
4234 3772
4235 system-cache-controller@92000 3773 system-cache-controller@9200000 {
4236 compatible = "qcom,sm 3774 compatible = "qcom,sm8250-llcc";
4237 reg = <0 0x09200000 0 3775 reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>,
4238 <0 0x09300000 0 3776 <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>,
4239 <0 0x09600000 0 3777 <0 0x09600000 0 0x50000>;
4240 reg-names = "llcc0_ba 3778 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
4241 "llcc3_ba 3779 "llcc3_base", "llcc_broadcast_base";
4242 }; 3780 };
4243 3781
4244 usb_2: usb@a8f8800 { 3782 usb_2: usb@a8f8800 {
4245 compatible = "qcom,sm 3783 compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
4246 reg = <0 0x0a8f8800 0 3784 reg = <0 0x0a8f8800 0 0x400>;
4247 status = "disabled"; 3785 status = "disabled";
4248 #address-cells = <2>; 3786 #address-cells = <2>;
4249 #size-cells = <2>; 3787 #size-cells = <2>;
4250 ranges; 3788 ranges;
4251 dma-ranges; 3789 dma-ranges;
4252 3790
4253 clocks = <&gcc GCC_CF 3791 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
4254 <&gcc GCC_US 3792 <&gcc GCC_USB30_SEC_MASTER_CLK>,
4255 <&gcc GCC_AG 3793 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
4256 <&gcc GCC_US 3794 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
4257 <&gcc GCC_US 3795 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4258 <&gcc GCC_US 3796 <&gcc GCC_USB3_SEC_CLKREF_EN>;
4259 clock-names = "cfg_no 3797 clock-names = "cfg_noc",
4260 "core", 3798 "core",
4261 "iface" 3799 "iface",
4262 "sleep" 3800 "sleep",
4263 "mock_u 3801 "mock_utmi",
4264 "xo"; 3802 "xo";
4265 3803
4266 assigned-clocks = <&g 3804 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4267 <&g 3805 <&gcc GCC_USB30_SEC_MASTER_CLK>;
4268 assigned-clock-rates 3806 assigned-clock-rates = <19200000>, <200000000>;
4269 3807
4270 interrupts-extended = !! 3808 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
4271 !! 3809 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>,
4272 <<
4273 3810 <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
4274 !! 3811 <&pdc 12 IRQ_TYPE_EDGE_BOTH>;
4275 interrupt-names = "pw !! 3812 interrupt-names = "hs_phy_irq",
4276 "hs !! 3813 "ss_phy_irq",
4277 "dp <<
4278 "dm 3814 "dm_hs_phy_irq",
4279 "ss !! 3815 "dp_hs_phy_irq";
4280 3816
4281 power-domains = <&gcc 3817 power-domains = <&gcc USB30_SEC_GDSC>;
4282 wakeup-source; <<
4283 3818
4284 resets = <&gcc GCC_US 3819 resets = <&gcc GCC_USB30_SEC_BCR>;
4285 3820
4286 interconnects = <&agg 3821 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0>,
4287 <&gem 3822 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>;
4288 interconnect-names = 3823 interconnect-names = "usb-ddr", "apps-usb";
4289 3824
4290 usb_2_dwc3: usb@a8000 3825 usb_2_dwc3: usb@a800000 {
4291 compatible = 3826 compatible = "snps,dwc3";
4292 reg = <0 0x0a 3827 reg = <0 0x0a800000 0 0xcd00>;
4293 interrupts = 3828 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
4294 iommus = <&ap 3829 iommus = <&apps_smmu 0x20 0>;
4295 snps,dis_u2_s 3830 snps,dis_u2_susphy_quirk;
4296 snps,dis_enbl 3831 snps,dis_enblslpm_quirk;
4297 phys = <&usb_ !! 3832 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
4298 phy-names = " 3833 phy-names = "usb2-phy", "usb3-phy";
4299 }; 3834 };
4300 }; 3835 };
4301 3836
4302 venus: video-codec@aa00000 { 3837 venus: video-codec@aa00000 {
4303 compatible = "qcom,sm 3838 compatible = "qcom,sm8250-venus";
4304 reg = <0 0x0aa00000 0 3839 reg = <0 0x0aa00000 0 0x100000>;
4305 interrupts = <GIC_SPI 3840 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
4306 power-domains = <&vid 3841 power-domains = <&videocc MVS0C_GDSC>,
4307 <&vid 3842 <&videocc MVS0_GDSC>,
4308 <&rpm !! 3843 <&rpmhpd SM8250_MX>;
4309 power-domain-names = 3844 power-domain-names = "venus", "vcodec0", "mx";
4310 operating-points-v2 = 3845 operating-points-v2 = <&venus_opp_table>;
4311 3846
4312 clocks = <&gcc GCC_VI 3847 clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
4313 <&videocc VI 3848 <&videocc VIDEO_CC_MVS0C_CLK>,
4314 <&videocc VI 3849 <&videocc VIDEO_CC_MVS0_CLK>;
4315 clock-names = "iface" 3850 clock-names = "iface", "core", "vcodec0_core";
4316 3851
4317 interconnects = <&gem 3852 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_VENUS_CFG 0>,
4318 <&mms 3853 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI_CH0 0>;
4319 interconnect-names = 3854 interconnect-names = "cpu-cfg", "video-mem";
4320 3855
4321 iommus = <&apps_smmu 3856 iommus = <&apps_smmu 0x2100 0x0400>;
4322 memory-region = <&vid 3857 memory-region = <&video_mem>;
4323 3858
4324 resets = <&gcc GCC_VI 3859 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
4325 <&videocc VI 3860 <&videocc VIDEO_CC_MVS0C_CLK_ARES>;
4326 reset-names = "bus", 3861 reset-names = "bus", "core";
4327 3862
4328 status = "disabled"; 3863 status = "disabled";
4329 3864
4330 video-decoder { 3865 video-decoder {
4331 compatible = 3866 compatible = "venus-decoder";
4332 }; 3867 };
4333 3868
4334 video-encoder { 3869 video-encoder {
4335 compatible = 3870 compatible = "venus-encoder";
4336 }; 3871 };
4337 3872
4338 venus_opp_table: opp- 3873 venus_opp_table: opp-table {
4339 compatible = 3874 compatible = "operating-points-v2";
4340 3875
4341 opp-720000000 3876 opp-720000000 {
4342 opp-h 3877 opp-hz = /bits/ 64 <720000000>;
4343 requi 3878 required-opps = <&rpmhpd_opp_low_svs>;
4344 }; 3879 };
4345 3880
4346 opp-101400000 3881 opp-1014000000 {
4347 opp-h 3882 opp-hz = /bits/ 64 <1014000000>;
4348 requi 3883 required-opps = <&rpmhpd_opp_svs>;
4349 }; 3884 };
4350 3885
4351 opp-109800000 3886 opp-1098000000 {
4352 opp-h 3887 opp-hz = /bits/ 64 <1098000000>;
4353 requi 3888 required-opps = <&rpmhpd_opp_svs_l1>;
4354 }; 3889 };
4355 3890
4356 opp-133200000 3891 opp-1332000000 {
4357 opp-h 3892 opp-hz = /bits/ 64 <1332000000>;
4358 requi 3893 required-opps = <&rpmhpd_opp_nom>;
4359 }; 3894 };
4360 }; 3895 };
4361 }; 3896 };
4362 3897
4363 videocc: clock-controller@abf 3898 videocc: clock-controller@abf0000 {
4364 compatible = "qcom,sm 3899 compatible = "qcom,sm8250-videocc";
4365 reg = <0 0x0abf0000 0 3900 reg = <0 0x0abf0000 0 0x10000>;
4366 clocks = <&gcc GCC_VI 3901 clocks = <&gcc GCC_VIDEO_AHB_CLK>,
4367 <&rpmhcc RPM 3902 <&rpmhcc RPMH_CXO_CLK>,
4368 <&rpmhcc RPM 3903 <&rpmhcc RPMH_CXO_CLK_A>;
4369 power-domains = <&rpm !! 3904 power-domains = <&rpmhpd SM8250_MMCX>;
4370 required-opps = <&rpm 3905 required-opps = <&rpmhpd_opp_low_svs>;
4371 clock-names = "iface" 3906 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao";
4372 #clock-cells = <1>; 3907 #clock-cells = <1>;
4373 #reset-cells = <1>; 3908 #reset-cells = <1>;
4374 #power-domain-cells = 3909 #power-domain-cells = <1>;
4375 }; 3910 };
4376 3911
4377 cci0: cci@ac4f000 { 3912 cci0: cci@ac4f000 {
4378 compatible = "qcom,sm 3913 compatible = "qcom,sm8250-cci", "qcom,msm8996-cci";
4379 #address-cells = <1>; 3914 #address-cells = <1>;
4380 #size-cells = <0>; 3915 #size-cells = <0>;
4381 3916
4382 reg = <0 0x0ac4f000 0 3917 reg = <0 0x0ac4f000 0 0x1000>;
4383 interrupts = <GIC_SPI 3918 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
4384 power-domains = <&cam 3919 power-domains = <&camcc TITAN_TOP_GDSC>;
4385 3920
4386 clocks = <&camcc CAM_ 3921 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
4387 <&camcc CAM_ 3922 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4388 <&camcc CAM_ 3923 <&camcc CAM_CC_CPAS_AHB_CLK>,
4389 <&camcc CAM_ 3924 <&camcc CAM_CC_CCI_0_CLK>,
4390 <&camcc CAM_ 3925 <&camcc CAM_CC_CCI_0_CLK_SRC>;
4391 clock-names = "camnoc 3926 clock-names = "camnoc_axi",
4392 "slow_a 3927 "slow_ahb_src",
4393 "cpas_a 3928 "cpas_ahb",
4394 "cci", 3929 "cci",
4395 "cci_sr 3930 "cci_src";
4396 3931
4397 pinctrl-0 = <&cci0_de 3932 pinctrl-0 = <&cci0_default>;
4398 pinctrl-1 = <&cci0_sl 3933 pinctrl-1 = <&cci0_sleep>;
4399 pinctrl-names = "defa 3934 pinctrl-names = "default", "sleep";
4400 3935
4401 status = "disabled"; 3936 status = "disabled";
4402 3937
4403 cci0_i2c0: i2c-bus@0 3938 cci0_i2c0: i2c-bus@0 {
4404 reg = <0>; 3939 reg = <0>;
4405 clock-frequen 3940 clock-frequency = <1000000>;
4406 #address-cell 3941 #address-cells = <1>;
4407 #size-cells = 3942 #size-cells = <0>;
4408 }; 3943 };
4409 3944
4410 cci0_i2c1: i2c-bus@1 3945 cci0_i2c1: i2c-bus@1 {
4411 reg = <1>; 3946 reg = <1>;
4412 clock-frequen 3947 clock-frequency = <1000000>;
4413 #address-cell 3948 #address-cells = <1>;
4414 #size-cells = 3949 #size-cells = <0>;
4415 }; 3950 };
4416 }; 3951 };
4417 3952
4418 cci1: cci@ac50000 { 3953 cci1: cci@ac50000 {
4419 compatible = "qcom,sm 3954 compatible = "qcom,sm8250-cci", "qcom,msm8996-cci";
4420 #address-cells = <1>; 3955 #address-cells = <1>;
4421 #size-cells = <0>; 3956 #size-cells = <0>;
4422 3957
4423 reg = <0 0x0ac50000 0 3958 reg = <0 0x0ac50000 0 0x1000>;
4424 interrupts = <GIC_SPI 3959 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>;
4425 power-domains = <&cam 3960 power-domains = <&camcc TITAN_TOP_GDSC>;
4426 3961
4427 clocks = <&camcc CAM_ 3962 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
4428 <&camcc CAM_ 3963 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4429 <&camcc CAM_ 3964 <&camcc CAM_CC_CPAS_AHB_CLK>,
4430 <&camcc CAM_ 3965 <&camcc CAM_CC_CCI_1_CLK>,
4431 <&camcc CAM_ 3966 <&camcc CAM_CC_CCI_1_CLK_SRC>;
4432 clock-names = "camnoc 3967 clock-names = "camnoc_axi",
4433 "slow_a 3968 "slow_ahb_src",
4434 "cpas_a 3969 "cpas_ahb",
4435 "cci", 3970 "cci",
4436 "cci_sr 3971 "cci_src";
4437 3972
4438 pinctrl-0 = <&cci1_de 3973 pinctrl-0 = <&cci1_default>;
4439 pinctrl-1 = <&cci1_sl 3974 pinctrl-1 = <&cci1_sleep>;
4440 pinctrl-names = "defa 3975 pinctrl-names = "default", "sleep";
4441 3976
4442 status = "disabled"; 3977 status = "disabled";
4443 3978
4444 cci1_i2c0: i2c-bus@0 3979 cci1_i2c0: i2c-bus@0 {
4445 reg = <0>; 3980 reg = <0>;
4446 clock-frequen 3981 clock-frequency = <1000000>;
4447 #address-cell 3982 #address-cells = <1>;
4448 #size-cells = 3983 #size-cells = <0>;
4449 }; 3984 };
4450 3985
4451 cci1_i2c1: i2c-bus@1 3986 cci1_i2c1: i2c-bus@1 {
4452 reg = <1>; 3987 reg = <1>;
4453 clock-frequen 3988 clock-frequency = <1000000>;
4454 #address-cell 3989 #address-cells = <1>;
4455 #size-cells = 3990 #size-cells = <0>;
4456 }; 3991 };
4457 }; 3992 };
4458 3993
4459 camss: camss@ac6a000 { 3994 camss: camss@ac6a000 {
4460 compatible = "qcom,sm 3995 compatible = "qcom,sm8250-camss";
4461 status = "disabled"; 3996 status = "disabled";
4462 3997
4463 reg = <0 0x0ac6a000 0 3998 reg = <0 0x0ac6a000 0 0x2000>,
4464 <0 0x0ac6c000 0 3999 <0 0x0ac6c000 0 0x2000>,
4465 <0 0x0ac6e000 0 4000 <0 0x0ac6e000 0 0x1000>,
4466 <0 0x0ac70000 0 4001 <0 0x0ac70000 0 0x1000>,
4467 <0 0x0ac72000 0 4002 <0 0x0ac72000 0 0x1000>,
4468 <0 0x0ac74000 0 4003 <0 0x0ac74000 0 0x1000>,
4469 <0 0x0acb4000 0 4004 <0 0x0acb4000 0 0xd000>,
4470 <0 0x0acc3000 0 4005 <0 0x0acc3000 0 0xd000>,
4471 <0 0x0acd9000 0 4006 <0 0x0acd9000 0 0x2200>,
4472 <0 0x0acdb200 0 4007 <0 0x0acdb200 0 0x2200>;
4473 reg-names = "csiphy0" 4008 reg-names = "csiphy0",
4474 "csiphy1" 4009 "csiphy1",
4475 "csiphy2" 4010 "csiphy2",
4476 "csiphy3" 4011 "csiphy3",
4477 "csiphy4" 4012 "csiphy4",
4478 "csiphy5" 4013 "csiphy5",
4479 "vfe0", 4014 "vfe0",
4480 "vfe1", 4015 "vfe1",
4481 "vfe_lite 4016 "vfe_lite0",
4482 "vfe_lite 4017 "vfe_lite1";
4483 4018
4484 interrupts = <GIC_SPI 4019 interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
4485 <GIC_SPI 4020 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
4486 <GIC_SPI 4021 <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
4487 <GIC_SPI 4022 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
4488 <GIC_SPI 4023 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
4489 <GIC_SPI 4024 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
4490 <GIC_SPI 4025 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
4491 <GIC_SPI 4026 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
4492 <GIC_SPI 4027 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
4493 <GIC_SPI 4028 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
4494 <GIC_SPI 4029 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
4495 <GIC_SPI 4030 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
4496 <GIC_SPI 4031 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
4497 <GIC_SPI 4032 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
4498 interrupt-names = "cs 4033 interrupt-names = "csiphy0",
4499 "cs 4034 "csiphy1",
4500 "cs 4035 "csiphy2",
4501 "cs 4036 "csiphy3",
4502 "cs 4037 "csiphy4",
4503 "cs 4038 "csiphy5",
4504 "cs 4039 "csid0",
4505 "cs 4040 "csid1",
4506 "cs 4041 "csid2",
4507 "cs 4042 "csid3",
4508 "vf 4043 "vfe0",
4509 "vf 4044 "vfe1",
4510 "vf 4045 "vfe_lite0",
4511 "vf 4046 "vfe_lite1";
4512 4047
4513 power-domains = <&cam 4048 power-domains = <&camcc IFE_0_GDSC>,
4514 <&cam 4049 <&camcc IFE_1_GDSC>,
4515 <&cam 4050 <&camcc TITAN_TOP_GDSC>;
4516 4051
4517 clocks = <&gcc GCC_CA 4052 clocks = <&gcc GCC_CAMERA_AHB_CLK>,
4518 <&gcc GCC_CA 4053 <&gcc GCC_CAMERA_HF_AXI_CLK>,
4519 <&gcc GCC_CA 4054 <&gcc GCC_CAMERA_SF_AXI_CLK>,
4520 <&camcc CAM_ 4055 <&camcc CAM_CC_CAMNOC_AXI_CLK>,
4521 <&camcc CAM_ 4056 <&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>,
4522 <&camcc CAM_ 4057 <&camcc CAM_CC_CORE_AHB_CLK>,
4523 <&camcc CAM_ 4058 <&camcc CAM_CC_CPAS_AHB_CLK>,
4524 <&camcc CAM_ 4059 <&camcc CAM_CC_CSIPHY0_CLK>,
4525 <&camcc CAM_ 4060 <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
4526 <&camcc CAM_ 4061 <&camcc CAM_CC_CSIPHY1_CLK>,
4527 <&camcc CAM_ 4062 <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
4528 <&camcc CAM_ 4063 <&camcc CAM_CC_CSIPHY2_CLK>,
4529 <&camcc CAM_ 4064 <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
4530 <&camcc CAM_ 4065 <&camcc CAM_CC_CSIPHY3_CLK>,
4531 <&camcc CAM_ 4066 <&camcc CAM_CC_CSI3PHYTIMER_CLK>,
4532 <&camcc CAM_ 4067 <&camcc CAM_CC_CSIPHY4_CLK>,
4533 <&camcc CAM_ 4068 <&camcc CAM_CC_CSI4PHYTIMER_CLK>,
4534 <&camcc CAM_ 4069 <&camcc CAM_CC_CSIPHY5_CLK>,
4535 <&camcc CAM_ 4070 <&camcc CAM_CC_CSI5PHYTIMER_CLK>,
4536 <&camcc CAM_ 4071 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4537 <&camcc CAM_ 4072 <&camcc CAM_CC_IFE_0_AHB_CLK>,
4538 <&camcc CAM_ 4073 <&camcc CAM_CC_IFE_0_AXI_CLK>,
4539 <&camcc CAM_ 4074 <&camcc CAM_CC_IFE_0_CLK>,
4540 <&camcc CAM_ 4075 <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
4541 <&camcc CAM_ 4076 <&camcc CAM_CC_IFE_0_CSID_CLK>,
4542 <&camcc CAM_ 4077 <&camcc CAM_CC_IFE_0_AREG_CLK>,
4543 <&camcc CAM_ 4078 <&camcc CAM_CC_IFE_1_AHB_CLK>,
4544 <&camcc CAM_ 4079 <&camcc CAM_CC_IFE_1_AXI_CLK>,
4545 <&camcc CAM_ 4080 <&camcc CAM_CC_IFE_1_CLK>,
4546 <&camcc CAM_ 4081 <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
4547 <&camcc CAM_ 4082 <&camcc CAM_CC_IFE_1_CSID_CLK>,
4548 <&camcc CAM_ 4083 <&camcc CAM_CC_IFE_1_AREG_CLK>,
4549 <&camcc CAM_ 4084 <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
4550 <&camcc CAM_ 4085 <&camcc CAM_CC_IFE_LITE_AXI_CLK>,
4551 <&camcc CAM_ 4086 <&camcc CAM_CC_IFE_LITE_CLK>,
4552 <&camcc CAM_ 4087 <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
4553 <&camcc CAM_ 4088 <&camcc CAM_CC_IFE_LITE_CSID_CLK>;
4554 4089
4555 clock-names = "cam_ah 4090 clock-names = "cam_ahb_clk",
4556 "cam_hf 4091 "cam_hf_axi",
4557 "cam_sf 4092 "cam_sf_axi",
4558 "camnoc 4093 "camnoc_axi",
4559 "camnoc 4094 "camnoc_axi_src",
4560 "core_a 4095 "core_ahb",
4561 "cpas_a 4096 "cpas_ahb",
4562 "csiphy 4097 "csiphy0",
4563 "csiphy 4098 "csiphy0_timer",
4564 "csiphy 4099 "csiphy1",
4565 "csiphy 4100 "csiphy1_timer",
4566 "csiphy 4101 "csiphy2",
4567 "csiphy 4102 "csiphy2_timer",
4568 "csiphy 4103 "csiphy3",
4569 "csiphy 4104 "csiphy3_timer",
4570 "csiphy 4105 "csiphy4",
4571 "csiphy 4106 "csiphy4_timer",
4572 "csiphy 4107 "csiphy5",
4573 "csiphy 4108 "csiphy5_timer",
4574 "slow_a 4109 "slow_ahb_src",
4575 "vfe0_a 4110 "vfe0_ahb",
4576 "vfe0_a 4111 "vfe0_axi",
4577 "vfe0", 4112 "vfe0",
4578 "vfe0_c 4113 "vfe0_cphy_rx",
4579 "vfe0_c 4114 "vfe0_csid",
4580 "vfe0_a 4115 "vfe0_areg",
4581 "vfe1_a 4116 "vfe1_ahb",
4582 "vfe1_a 4117 "vfe1_axi",
4583 "vfe1", 4118 "vfe1",
4584 "vfe1_c 4119 "vfe1_cphy_rx",
4585 "vfe1_c 4120 "vfe1_csid",
4586 "vfe1_a 4121 "vfe1_areg",
4587 "vfe_li 4122 "vfe_lite_ahb",
4588 "vfe_li 4123 "vfe_lite_axi",
4589 "vfe_li 4124 "vfe_lite",
4590 "vfe_li 4125 "vfe_lite_cphy_rx",
4591 "vfe_li 4126 "vfe_lite_csid";
4592 4127
4593 iommus = <&apps_smmu 4128 iommus = <&apps_smmu 0x800 0x400>,
4594 <&apps_smmu 4129 <&apps_smmu 0x801 0x400>,
4595 <&apps_smmu 4130 <&apps_smmu 0x840 0x400>,
4596 <&apps_smmu 4131 <&apps_smmu 0x841 0x400>,
4597 <&apps_smmu 4132 <&apps_smmu 0xc00 0x400>,
4598 <&apps_smmu 4133 <&apps_smmu 0xc01 0x400>,
4599 <&apps_smmu 4134 <&apps_smmu 0xc40 0x400>,
4600 <&apps_smmu 4135 <&apps_smmu 0xc41 0x400>;
4601 4136
4602 interconnects = <&gem 4137 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_CAMERA_CFG 0>,
4603 <&mms 4138 <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI_CH0 0>,
4604 <&mms 4139 <&mmss_noc MASTER_CAMNOC_SF 0 &mc_virt SLAVE_EBI_CH0 0>,
4605 <&mms 4140 <&mmss_noc MASTER_CAMNOC_ICP 0 &mc_virt SLAVE_EBI_CH0 0>;
4606 interconnect-names = 4141 interconnect-names = "cam_ahb",
4607 4142 "cam_hf_0_mnoc",
4608 4143 "cam_sf_0_mnoc",
4609 4144 "cam_sf_icp_mnoc";
4610 4145
4611 ports { 4146 ports {
4612 #address-cell 4147 #address-cells = <1>;
4613 #size-cells = 4148 #size-cells = <0>;
4614 4149
4615 port@0 { 4150 port@0 {
4616 reg = 4151 reg = <0>;
4617 }; 4152 };
4618 4153
4619 port@1 { 4154 port@1 {
4620 reg = 4155 reg = <1>;
4621 }; 4156 };
4622 4157
4623 port@2 { 4158 port@2 {
4624 reg = 4159 reg = <2>;
4625 }; 4160 };
4626 4161
4627 port@3 { 4162 port@3 {
4628 reg = 4163 reg = <3>;
4629 }; 4164 };
4630 4165
4631 port@4 { 4166 port@4 {
4632 reg = 4167 reg = <4>;
4633 }; 4168 };
4634 4169
4635 port@5 { 4170 port@5 {
4636 reg = 4171 reg = <5>;
4637 }; 4172 };
4638 }; 4173 };
4639 }; 4174 };
4640 4175
4641 camcc: clock-controller@ad000 4176 camcc: clock-controller@ad00000 {
4642 compatible = "qcom,sm 4177 compatible = "qcom,sm8250-camcc";
4643 reg = <0 0x0ad00000 0 4178 reg = <0 0x0ad00000 0 0x10000>;
4644 clocks = <&gcc GCC_CA 4179 clocks = <&gcc GCC_CAMERA_AHB_CLK>,
4645 <&rpmhcc RPM 4180 <&rpmhcc RPMH_CXO_CLK>,
4646 <&rpmhcc RPM 4181 <&rpmhcc RPMH_CXO_CLK_A>,
4647 <&sleep_clk> 4182 <&sleep_clk>;
4648 clock-names = "iface" 4183 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
4649 power-domains = <&rpm !! 4184 power-domains = <&rpmhpd SM8250_MMCX>;
4650 required-opps = <&rpm 4185 required-opps = <&rpmhpd_opp_low_svs>;
4651 status = "disabled"; 4186 status = "disabled";
4652 #clock-cells = <1>; 4187 #clock-cells = <1>;
4653 #reset-cells = <1>; 4188 #reset-cells = <1>;
4654 #power-domain-cells = 4189 #power-domain-cells = <1>;
4655 }; 4190 };
4656 4191
4657 mdss: display-subsystem@ae000 4192 mdss: display-subsystem@ae00000 {
4658 compatible = "qcom,sm 4193 compatible = "qcom,sm8250-mdss";
4659 reg = <0 0x0ae00000 0 4194 reg = <0 0x0ae00000 0 0x1000>;
4660 reg-names = "mdss"; 4195 reg-names = "mdss";
4661 4196
4662 interconnects = <&mms 4197 interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mc_virt SLAVE_EBI_CH0 0>,
4663 <&mms 4198 <&mmss_noc MASTER_MDP_PORT1 0 &mc_virt SLAVE_EBI_CH0 0>;
4664 interconnect-names = 4199 interconnect-names = "mdp0-mem", "mdp1-mem";
4665 4200
4666 power-domains = <&dis 4201 power-domains = <&dispcc MDSS_GDSC>;
4667 4202
4668 clocks = <&dispcc DIS 4203 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4669 <&gcc GCC_DI 4204 <&gcc GCC_DISP_HF_AXI_CLK>,
4670 <&gcc GCC_DI 4205 <&gcc GCC_DISP_SF_AXI_CLK>,
4671 <&dispcc DIS 4206 <&dispcc DISP_CC_MDSS_MDP_CLK>;
4672 clock-names = "iface" 4207 clock-names = "iface", "bus", "nrt_bus", "core";
4673 4208
4674 interrupts = <GIC_SPI 4209 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
4675 interrupt-controller; 4210 interrupt-controller;
4676 #interrupt-cells = <1 4211 #interrupt-cells = <1>;
4677 4212
4678 iommus = <&apps_smmu 4213 iommus = <&apps_smmu 0x820 0x402>;
4679 4214
4680 status = "disabled"; 4215 status = "disabled";
4681 4216
4682 #address-cells = <2>; 4217 #address-cells = <2>;
4683 #size-cells = <2>; 4218 #size-cells = <2>;
4684 ranges; 4219 ranges;
4685 4220
4686 mdss_mdp: display-con 4221 mdss_mdp: display-controller@ae01000 {
4687 compatible = 4222 compatible = "qcom,sm8250-dpu";
4688 reg = <0 0x0a 4223 reg = <0 0x0ae01000 0 0x8f000>,
4689 <0 0x0a 4224 <0 0x0aeb0000 0 0x2008>;
4690 reg-names = " 4225 reg-names = "mdp", "vbif";
4691 4226
4692 clocks = <&di 4227 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4693 <&gc 4228 <&gcc GCC_DISP_HF_AXI_CLK>,
4694 <&di 4229 <&dispcc DISP_CC_MDSS_MDP_CLK>,
4695 <&di 4230 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4696 clock-names = 4231 clock-names = "iface", "bus", "core", "vsync";
4697 4232
4698 assigned-cloc 4233 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4699 assigned-cloc 4234 assigned-clock-rates = <19200000>;
4700 4235
4701 operating-poi 4236 operating-points-v2 = <&mdp_opp_table>;
4702 power-domains !! 4237 power-domains = <&rpmhpd SM8250_MMCX>;
4703 4238
4704 interrupt-par 4239 interrupt-parent = <&mdss>;
4705 interrupts = 4240 interrupts = <0>;
4706 4241
4707 ports { 4242 ports {
4708 #addr 4243 #address-cells = <1>;
4709 #size 4244 #size-cells = <0>;
4710 4245
4711 port@ 4246 port@0 {
4712 4247 reg = <0>;
4713 4248 dpu_intf1_out: endpoint {
4714 4249 remote-endpoint = <&mdss_dsi0_in>;
4715 4250 };
4716 }; 4251 };
4717 4252
4718 port@ 4253 port@1 {
4719 4254 reg = <1>;
4720 4255 dpu_intf2_out: endpoint {
4721 4256 remote-endpoint = <&mdss_dsi1_in>;
4722 4257 };
4723 }; 4258 };
4724 <<
4725 port@ <<
4726 <<
4727 <<
4728 <<
4729 <<
4730 <<
4731 }; <<
4732 }; 4259 };
4733 4260
4734 mdp_opp_table 4261 mdp_opp_table: opp-table {
4735 compa 4262 compatible = "operating-points-v2";
4736 4263
4737 opp-2 4264 opp-200000000 {
4738 4265 opp-hz = /bits/ 64 <200000000>;
4739 4266 required-opps = <&rpmhpd_opp_low_svs>;
4740 }; 4267 };
4741 4268
4742 opp-3 4269 opp-300000000 {
4743 4270 opp-hz = /bits/ 64 <300000000>;
4744 4271 required-opps = <&rpmhpd_opp_svs>;
4745 }; 4272 };
4746 4273
4747 opp-3 4274 opp-345000000 {
4748 4275 opp-hz = /bits/ 64 <345000000>;
4749 4276 required-opps = <&rpmhpd_opp_svs_l1>;
4750 }; 4277 };
4751 4278
4752 opp-4 4279 opp-460000000 {
4753 4280 opp-hz = /bits/ 64 <460000000>;
4754 4281 required-opps = <&rpmhpd_opp_nom>;
4755 }; 4282 };
4756 }; 4283 };
4757 }; 4284 };
4758 4285
4759 mdss_dp: displayport- <<
4760 compatible = <<
4761 reg = <0 0xae <<
4762 <0 0xae <<
4763 <0 0xae <<
4764 <0 0xae <<
4765 <0 0xae <<
4766 interrupt-par <<
4767 interrupts = <<
4768 clocks = <&di <<
4769 <&di <<
4770 <&di <<
4771 <&di <<
4772 <&di <<
4773 clock-names = <<
4774 <<
4775 <<
4776 <<
4777 <<
4778 <<
4779 assigned-cloc <<
4780 <<
4781 assigned-cloc <<
4782 <<
4783 <<
4784 phys = <&usb_ <<
4785 phy-names = " <<
4786 <<
4787 #sound-dai-ce <<
4788 <<
4789 operating-poi <<
4790 power-domains <<
4791 <<
4792 status = "dis <<
4793 <<
4794 ports { <<
4795 #addr <<
4796 #size <<
4797 <<
4798 port@ <<
4799 <<
4800 <<
4801 <<
4802 <<
4803 }; <<
4804 <<
4805 port@ <<
4806 <<
4807 <<
4808 <<
4809 <<
4810 }; <<
4811 }; <<
4812 <<
4813 dp_opp_table: <<
4814 compa <<
4815 <<
4816 opp-1 <<
4817 <<
4818 <<
4819 }; <<
4820 <<
4821 opp-2 <<
4822 <<
4823 <<
4824 }; <<
4825 <<
4826 opp-5 <<
4827 <<
4828 <<
4829 }; <<
4830 <<
4831 opp-8 <<
4832 <<
4833 <<
4834 }; <<
4835 }; <<
4836 }; <<
4837 <<
4838 mdss_dsi0: dsi@ae9400 4286 mdss_dsi0: dsi@ae94000 {
4839 compatible = 4287 compatible = "qcom,sm8250-dsi-ctrl",
4840 4288 "qcom,mdss-dsi-ctrl";
4841 reg = <0 0x0a 4289 reg = <0 0x0ae94000 0 0x400>;
4842 reg-names = " 4290 reg-names = "dsi_ctrl";
4843 4291
4844 interrupt-par 4292 interrupt-parent = <&mdss>;
4845 interrupts = 4293 interrupts = <4>;
4846 4294
4847 clocks = <&di 4295 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
4848 <&di 4296 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
4849 <&di 4297 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
4850 <&di 4298 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
4851 <&di 4299 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4852 <&gcc 4300 <&gcc GCC_DISP_HF_AXI_CLK>;
4853 clock-names = 4301 clock-names = "byte",
4854 4302 "byte_intf",
4855 4303 "pixel",
4856 4304 "core",
4857 4305 "iface",
4858 4306 "bus";
4859 4307
4860 assigned-cloc 4308 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
4861 assigned-cloc 4309 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
4862 4310
4863 operating-poi 4311 operating-points-v2 = <&dsi_opp_table>;
4864 power-domains !! 4312 power-domains = <&rpmhpd SM8250_MMCX>;
4865 4313
4866 phys = <&mdss 4314 phys = <&mdss_dsi0_phy>;
4867 4315
4868 status = "dis 4316 status = "disabled";
4869 4317
4870 #address-cell 4318 #address-cells = <1>;
4871 #size-cells = 4319 #size-cells = <0>;
4872 4320
4873 ports { 4321 ports {
4874 #addr 4322 #address-cells = <1>;
4875 #size 4323 #size-cells = <0>;
4876 4324
4877 port@ 4325 port@0 {
4878 4326 reg = <0>;
4879 4327 mdss_dsi0_in: endpoint {
4880 4328 remote-endpoint = <&dpu_intf1_out>;
4881 4329 };
4882 }; 4330 };
4883 4331
4884 port@ 4332 port@1 {
4885 4333 reg = <1>;
4886 4334 mdss_dsi0_out: endpoint {
4887 4335 };
4888 }; 4336 };
4889 }; 4337 };
4890 4338
4891 dsi_opp_table 4339 dsi_opp_table: opp-table {
4892 compa 4340 compatible = "operating-points-v2";
4893 4341
4894 opp-1 4342 opp-187500000 {
4895 4343 opp-hz = /bits/ 64 <187500000>;
4896 4344 required-opps = <&rpmhpd_opp_low_svs>;
4897 }; 4345 };
4898 4346
4899 opp-3 4347 opp-300000000 {
4900 4348 opp-hz = /bits/ 64 <300000000>;
4901 4349 required-opps = <&rpmhpd_opp_svs>;
4902 }; 4350 };
4903 4351
4904 opp-3 4352 opp-358000000 {
4905 4353 opp-hz = /bits/ 64 <358000000>;
4906 4354 required-opps = <&rpmhpd_opp_svs_l1>;
4907 }; 4355 };
4908 }; 4356 };
4909 }; 4357 };
4910 4358
4911 mdss_dsi0_phy: phy@ae 4359 mdss_dsi0_phy: phy@ae94400 {
4912 compatible = 4360 compatible = "qcom,dsi-phy-7nm";
4913 reg = <0 0x0a 4361 reg = <0 0x0ae94400 0 0x200>,
4914 <0 0x0a 4362 <0 0x0ae94600 0 0x280>,
4915 <0 0x0a 4363 <0 0x0ae94900 0 0x260>;
4916 reg-names = " 4364 reg-names = "dsi_phy",
4917 " 4365 "dsi_phy_lane",
4918 " 4366 "dsi_pll";
4919 4367
4920 #clock-cells 4368 #clock-cells = <1>;
4921 #phy-cells = 4369 #phy-cells = <0>;
4922 4370
4923 clocks = <&di 4371 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4924 <&rp 4372 <&rpmhcc RPMH_CXO_CLK>;
4925 clock-names = 4373 clock-names = "iface", "ref";
4926 4374
4927 status = "dis 4375 status = "disabled";
4928 }; 4376 };
4929 4377
4930 mdss_dsi1: dsi@ae9600 4378 mdss_dsi1: dsi@ae96000 {
4931 compatible = 4379 compatible = "qcom,sm8250-dsi-ctrl",
4932 4380 "qcom,mdss-dsi-ctrl";
4933 reg = <0 0x0a 4381 reg = <0 0x0ae96000 0 0x400>;
4934 reg-names = " 4382 reg-names = "dsi_ctrl";
4935 4383
4936 interrupt-par 4384 interrupt-parent = <&mdss>;
4937 interrupts = 4385 interrupts = <5>;
4938 4386
4939 clocks = <&di 4387 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
4940 <&di 4388 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
4941 <&di 4389 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
4942 <&di 4390 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
4943 <&di 4391 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4944 <&gc 4392 <&gcc GCC_DISP_HF_AXI_CLK>;
4945 clock-names = 4393 clock-names = "byte",
4946 4394 "byte_intf",
4947 4395 "pixel",
4948 4396 "core",
4949 4397 "iface",
4950 4398 "bus";
4951 4399
4952 assigned-cloc 4400 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
4953 assigned-cloc 4401 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
4954 4402
4955 operating-poi 4403 operating-points-v2 = <&dsi_opp_table>;
4956 power-domains !! 4404 power-domains = <&rpmhpd SM8250_MMCX>;
4957 4405
4958 phys = <&mdss 4406 phys = <&mdss_dsi1_phy>;
4959 4407
4960 status = "dis 4408 status = "disabled";
4961 4409
4962 #address-cell 4410 #address-cells = <1>;
4963 #size-cells = 4411 #size-cells = <0>;
4964 4412
4965 ports { 4413 ports {
4966 #addr 4414 #address-cells = <1>;
4967 #size 4415 #size-cells = <0>;
4968 4416
4969 port@ 4417 port@0 {
4970 4418 reg = <0>;
4971 4419 mdss_dsi1_in: endpoint {
4972 4420 remote-endpoint = <&dpu_intf2_out>;
4973 4421 };
4974 }; 4422 };
4975 4423
4976 port@ 4424 port@1 {
4977 4425 reg = <1>;
4978 4426 mdss_dsi1_out: endpoint {
4979 4427 };
4980 }; 4428 };
4981 }; 4429 };
4982 }; 4430 };
4983 4431
4984 mdss_dsi1_phy: phy@ae 4432 mdss_dsi1_phy: phy@ae96400 {
4985 compatible = 4433 compatible = "qcom,dsi-phy-7nm";
4986 reg = <0 0x0a 4434 reg = <0 0x0ae96400 0 0x200>,
4987 <0 0x0a 4435 <0 0x0ae96600 0 0x280>,
4988 <0 0x0a 4436 <0 0x0ae96900 0 0x260>;
4989 reg-names = " 4437 reg-names = "dsi_phy",
4990 " 4438 "dsi_phy_lane",
4991 " 4439 "dsi_pll";
4992 4440
4993 #clock-cells 4441 #clock-cells = <1>;
4994 #phy-cells = 4442 #phy-cells = <0>;
4995 4443
4996 clocks = <&di 4444 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4997 <&rp 4445 <&rpmhcc RPMH_CXO_CLK>;
4998 clock-names = 4446 clock-names = "iface", "ref";
4999 4447
5000 status = "dis 4448 status = "disabled";
5001 }; 4449 };
5002 }; 4450 };
5003 4451
5004 dispcc: clock-controller@af00 4452 dispcc: clock-controller@af00000 {
5005 compatible = "qcom,sm 4453 compatible = "qcom,sm8250-dispcc";
5006 reg = <0 0x0af00000 0 4454 reg = <0 0x0af00000 0 0x10000>;
5007 power-domains = <&rpm !! 4455 power-domains = <&rpmhpd SM8250_MMCX>;
5008 required-opps = <&rpm 4456 required-opps = <&rpmhpd_opp_low_svs>;
5009 clocks = <&rpmhcc RPM 4457 clocks = <&rpmhcc RPMH_CXO_CLK>,
5010 <&mdss_dsi0_ 4458 <&mdss_dsi0_phy 0>,
5011 <&mdss_dsi0_ 4459 <&mdss_dsi0_phy 1>,
5012 <&mdss_dsi1_ 4460 <&mdss_dsi1_phy 0>,
5013 <&mdss_dsi1_ 4461 <&mdss_dsi1_phy 1>,
5014 <&usb_1_qmpp !! 4462 <&dp_phy 0>,
5015 <&usb_1_qmpp !! 4463 <&dp_phy 1>;
5016 clock-names = "bi_tcx 4464 clock-names = "bi_tcxo",
5017 "dsi0_p 4465 "dsi0_phy_pll_out_byteclk",
5018 "dsi0_p 4466 "dsi0_phy_pll_out_dsiclk",
5019 "dsi1_p 4467 "dsi1_phy_pll_out_byteclk",
5020 "dsi1_p 4468 "dsi1_phy_pll_out_dsiclk",
5021 "dp_phy 4469 "dp_phy_pll_link_clk",
5022 "dp_phy 4470 "dp_phy_pll_vco_div_clk";
5023 #clock-cells = <1>; 4471 #clock-cells = <1>;
5024 #reset-cells = <1>; 4472 #reset-cells = <1>;
5025 #power-domain-cells = 4473 #power-domain-cells = <1>;
5026 }; 4474 };
5027 4475
5028 pdc: interrupt-controller@b22 4476 pdc: interrupt-controller@b220000 {
5029 compatible = "qcom,sm 4477 compatible = "qcom,sm8250-pdc", "qcom,pdc";
5030 reg = <0 0x0b220000 0 4478 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
5031 qcom,pdc-ranges = <0 4479 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
5032 <12 4480 <125 63 1>, <126 716 12>;
5033 #interrupt-cells = <2 4481 #interrupt-cells = <2>;
5034 interrupt-parent = <& 4482 interrupt-parent = <&intc>;
5035 interrupt-controller; 4483 interrupt-controller;
5036 }; 4484 };
5037 4485
5038 tsens0: thermal-sensor@c26300 4486 tsens0: thermal-sensor@c263000 {
5039 compatible = "qcom,sm 4487 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
5040 reg = <0 0x0c263000 0 4488 reg = <0 0x0c263000 0 0x1ff>, /* TM */
5041 <0 0x0c222000 0 4489 <0 0x0c222000 0 0x1ff>; /* SROT */
5042 #qcom,sensors = <16>; 4490 #qcom,sensors = <16>;
5043 interrupts = <GIC_SPI 4491 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
5044 <GIC_SPI 4492 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
5045 interrupt-names = "up 4493 interrupt-names = "uplow", "critical";
5046 #thermal-sensor-cells 4494 #thermal-sensor-cells = <1>;
5047 }; 4495 };
5048 4496
5049 tsens1: thermal-sensor@c26500 4497 tsens1: thermal-sensor@c265000 {
5050 compatible = "qcom,sm 4498 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
5051 reg = <0 0x0c265000 0 4499 reg = <0 0x0c265000 0 0x1ff>, /* TM */
5052 <0 0x0c223000 0 4500 <0 0x0c223000 0 0x1ff>; /* SROT */
5053 #qcom,sensors = <9>; 4501 #qcom,sensors = <9>;
5054 interrupts = <GIC_SPI 4502 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
5055 <GIC_SPI 4503 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
5056 interrupt-names = "up 4504 interrupt-names = "uplow", "critical";
5057 #thermal-sensor-cells 4505 #thermal-sensor-cells = <1>;
5058 }; 4506 };
5059 4507
5060 aoss_qmp: power-management@c3 4508 aoss_qmp: power-management@c300000 {
5061 compatible = "qcom,sm 4509 compatible = "qcom,sm8250-aoss-qmp", "qcom,aoss-qmp";
5062 reg = <0 0x0c300000 0 4510 reg = <0 0x0c300000 0 0x400>;
5063 interrupts-extended = 4511 interrupts-extended = <&ipcc IPCC_CLIENT_AOP
5064 4512 IPCC_MPROC_SIGNAL_GLINK_QMP
5065 4513 IRQ_TYPE_EDGE_RISING>;
5066 mboxes = <&ipcc IPCC_ 4514 mboxes = <&ipcc IPCC_CLIENT_AOP
5067 IPCC_ 4515 IPCC_MPROC_SIGNAL_GLINK_QMP>;
5068 4516
5069 #clock-cells = <0>; 4517 #clock-cells = <0>;
5070 }; 4518 };
5071 4519
5072 sram@c3f0000 { 4520 sram@c3f0000 {
5073 compatible = "qcom,rp 4521 compatible = "qcom,rpmh-stats";
5074 reg = <0 0x0c3f0000 0 4522 reg = <0 0x0c3f0000 0 0x400>;
5075 }; 4523 };
5076 4524
5077 spmi_bus: spmi@c440000 { 4525 spmi_bus: spmi@c440000 {
5078 compatible = "qcom,sp 4526 compatible = "qcom,spmi-pmic-arb";
5079 reg = <0x0 0x0c440000 4527 reg = <0x0 0x0c440000 0x0 0x0001100>,
5080 <0x0 0x0c600000 4528 <0x0 0x0c600000 0x0 0x2000000>,
5081 <0x0 0x0e600000 4529 <0x0 0x0e600000 0x0 0x0100000>,
5082 <0x0 0x0e700000 4530 <0x0 0x0e700000 0x0 0x00a0000>,
5083 <0x0 0x0c40a000 4531 <0x0 0x0c40a000 0x0 0x0026000>;
5084 reg-names = "core", " 4532 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
5085 interrupt-names = "pe 4533 interrupt-names = "periph_irq";
5086 interrupts-extended = 4534 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
5087 qcom,ee = <0>; 4535 qcom,ee = <0>;
5088 qcom,channel = <0>; 4536 qcom,channel = <0>;
5089 #address-cells = <2>; 4537 #address-cells = <2>;
5090 #size-cells = <0>; 4538 #size-cells = <0>;
5091 interrupt-controller; 4539 interrupt-controller;
5092 #interrupt-cells = <4 4540 #interrupt-cells = <4>;
5093 }; 4541 };
5094 4542
5095 tlmm: pinctrl@f100000 { 4543 tlmm: pinctrl@f100000 {
5096 compatible = "qcom,sm 4544 compatible = "qcom,sm8250-pinctrl";
5097 reg = <0 0x0f100000 0 4545 reg = <0 0x0f100000 0 0x300000>,
5098 <0 0x0f500000 0 4546 <0 0x0f500000 0 0x300000>,
5099 <0 0x0f900000 0 4547 <0 0x0f900000 0 0x300000>;
5100 reg-names = "west", " 4548 reg-names = "west", "south", "north";
5101 interrupts = <GIC_SPI 4549 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
5102 gpio-controller; 4550 gpio-controller;
5103 #gpio-cells = <2>; 4551 #gpio-cells = <2>;
5104 interrupt-controller; 4552 interrupt-controller;
5105 #interrupt-cells = <2 4553 #interrupt-cells = <2>;
5106 gpio-ranges = <&tlmm 4554 gpio-ranges = <&tlmm 0 0 181>;
5107 wakeup-parent = <&pdc 4555 wakeup-parent = <&pdc>;
5108 4556
5109 cam2_default: cam2-de 4557 cam2_default: cam2-default-state {
5110 rst-pins { 4558 rst-pins {
5111 pins 4559 pins = "gpio78";
5112 funct 4560 function = "gpio";
5113 drive 4561 drive-strength = <2>;
5114 bias- 4562 bias-disable;
5115 }; 4563 };
5116 4564
5117 mclk-pins { 4565 mclk-pins {
5118 pins 4566 pins = "gpio96";
5119 funct 4567 function = "cam_mclk";
5120 drive 4568 drive-strength = <16>;
5121 bias- 4569 bias-disable;
5122 }; 4570 };
5123 }; 4571 };
5124 4572
5125 cam2_suspend: cam2-su 4573 cam2_suspend: cam2-suspend-state {
5126 rst-pins { 4574 rst-pins {
5127 pins 4575 pins = "gpio78";
5128 funct 4576 function = "gpio";
5129 drive 4577 drive-strength = <2>;
5130 bias- 4578 bias-pull-down;
5131 outpu 4579 output-low;
5132 }; 4580 };
5133 4581
5134 mclk-pins { 4582 mclk-pins {
5135 pins 4583 pins = "gpio96";
5136 funct 4584 function = "cam_mclk";
5137 drive 4585 drive-strength = <2>;
5138 bias- 4586 bias-disable;
5139 }; 4587 };
5140 }; 4588 };
5141 4589
5142 cci0_default: cci0-de 4590 cci0_default: cci0-default-state {
5143 cci0_i2c0_def 4591 cci0_i2c0_default: cci0-i2c0-default-pins {
5144 /* SD 4592 /* SDA, SCL */
5145 pins 4593 pins = "gpio101", "gpio102";
5146 funct 4594 function = "cci_i2c";
5147 4595
5148 bias- 4596 bias-pull-up;
5149 drive 4597 drive-strength = <2>; /* 2 mA */
5150 }; 4598 };
5151 4599
5152 cci0_i2c1_def 4600 cci0_i2c1_default: cci0-i2c1-default-pins {
5153 /* SD 4601 /* SDA, SCL */
5154 pins 4602 pins = "gpio103", "gpio104";
5155 funct 4603 function = "cci_i2c";
5156 4604
5157 bias- 4605 bias-pull-up;
5158 drive 4606 drive-strength = <2>; /* 2 mA */
5159 }; 4607 };
5160 }; 4608 };
5161 4609
5162 cci0_sleep: cci0-slee 4610 cci0_sleep: cci0-sleep-state {
5163 cci0_i2c0_sle 4611 cci0_i2c0_sleep: cci0-i2c0-sleep-pins {
5164 /* SD 4612 /* SDA, SCL */
5165 pins 4613 pins = "gpio101", "gpio102";
5166 funct 4614 function = "cci_i2c";
5167 4615
5168 drive 4616 drive-strength = <2>; /* 2 mA */
5169 bias- 4617 bias-pull-down;
5170 }; 4618 };
5171 4619
5172 cci0_i2c1_sle 4620 cci0_i2c1_sleep: cci0-i2c1-sleep-pins {
5173 /* SD 4621 /* SDA, SCL */
5174 pins 4622 pins = "gpio103", "gpio104";
5175 funct 4623 function = "cci_i2c";
5176 4624
5177 drive 4625 drive-strength = <2>; /* 2 mA */
5178 bias- 4626 bias-pull-down;
5179 }; 4627 };
5180 }; 4628 };
5181 4629
5182 cci1_default: cci1-de 4630 cci1_default: cci1-default-state {
5183 cci1_i2c0_def 4631 cci1_i2c0_default: cci1-i2c0-default-pins {
5184 /* SD 4632 /* SDA, SCL */
5185 pins 4633 pins = "gpio105","gpio106";
5186 funct 4634 function = "cci_i2c";
5187 4635
5188 bias- 4636 bias-pull-up;
5189 drive 4637 drive-strength = <2>; /* 2 mA */
5190 }; 4638 };
5191 4639
5192 cci1_i2c1_def 4640 cci1_i2c1_default: cci1-i2c1-default-pins {
5193 /* SD 4641 /* SDA, SCL */
5194 pins 4642 pins = "gpio107","gpio108";
5195 funct 4643 function = "cci_i2c";
5196 4644
5197 bias- 4645 bias-pull-up;
5198 drive 4646 drive-strength = <2>; /* 2 mA */
5199 }; 4647 };
5200 }; 4648 };
5201 4649
5202 cci1_sleep: cci1-slee 4650 cci1_sleep: cci1-sleep-state {
5203 cci1_i2c0_sle 4651 cci1_i2c0_sleep: cci1-i2c0-sleep-pins {
5204 /* SD 4652 /* SDA, SCL */
5205 pins 4653 pins = "gpio105","gpio106";
5206 funct 4654 function = "cci_i2c";
5207 4655
5208 bias- 4656 bias-pull-down;
5209 drive 4657 drive-strength = <2>; /* 2 mA */
5210 }; 4658 };
5211 4659
5212 cci1_i2c1_sle 4660 cci1_i2c1_sleep: cci1-i2c1-sleep-pins {
5213 /* SD 4661 /* SDA, SCL */
5214 pins 4662 pins = "gpio107","gpio108";
5215 funct 4663 function = "cci_i2c";
5216 4664
5217 bias- 4665 bias-pull-down;
5218 drive 4666 drive-strength = <2>; /* 2 mA */
5219 }; 4667 };
5220 }; 4668 };
5221 4669
5222 pri_mi2s_active: pri- 4670 pri_mi2s_active: pri-mi2s-active-state {
5223 sclk-pins { 4671 sclk-pins {
5224 pins 4672 pins = "gpio138";
5225 funct 4673 function = "mi2s0_sck";
5226 drive 4674 drive-strength = <8>;
5227 bias- 4675 bias-disable;
5228 }; 4676 };
5229 4677
5230 ws-pins { 4678 ws-pins {
5231 pins 4679 pins = "gpio141";
5232 funct 4680 function = "mi2s0_ws";
5233 drive 4681 drive-strength = <8>;
5234 outpu 4682 output-high;
5235 }; 4683 };
5236 4684
5237 data0-pins { 4685 data0-pins {
5238 pins 4686 pins = "gpio139";
5239 funct 4687 function = "mi2s0_data0";
5240 drive 4688 drive-strength = <8>;
5241 bias- 4689 bias-disable;
5242 outpu 4690 output-high;
5243 }; 4691 };
5244 4692
5245 data1-pins { 4693 data1-pins {
5246 pins 4694 pins = "gpio140";
5247 funct 4695 function = "mi2s0_data1";
5248 drive 4696 drive-strength = <8>;
5249 outpu 4697 output-high;
5250 }; 4698 };
5251 }; 4699 };
5252 4700
5253 qup_i2c0_default: qup 4701 qup_i2c0_default: qup-i2c0-default-state {
5254 pins = "gpio2 4702 pins = "gpio28", "gpio29";
5255 function = "q 4703 function = "qup0";
5256 drive-strengt 4704 drive-strength = <2>;
5257 bias-disable; 4705 bias-disable;
5258 }; 4706 };
5259 4707
5260 qup_i2c1_default: qup 4708 qup_i2c1_default: qup-i2c1-default-state {
5261 pins = "gpio4 4709 pins = "gpio4", "gpio5";
5262 function = "q 4710 function = "qup1";
5263 drive-strengt 4711 drive-strength = <2>;
5264 bias-disable; 4712 bias-disable;
5265 }; 4713 };
5266 4714
5267 qup_i2c2_default: qup 4715 qup_i2c2_default: qup-i2c2-default-state {
5268 pins = "gpio1 4716 pins = "gpio115", "gpio116";
5269 function = "q 4717 function = "qup2";
5270 drive-strengt 4718 drive-strength = <2>;
5271 bias-disable; 4719 bias-disable;
5272 }; 4720 };
5273 4721
5274 qup_i2c3_default: qup 4722 qup_i2c3_default: qup-i2c3-default-state {
5275 pins = "gpio1 4723 pins = "gpio119", "gpio120";
5276 function = "q 4724 function = "qup3";
5277 drive-strengt 4725 drive-strength = <2>;
5278 bias-disable; 4726 bias-disable;
5279 }; 4727 };
5280 4728
5281 qup_i2c4_default: qup 4729 qup_i2c4_default: qup-i2c4-default-state {
5282 pins = "gpio8 4730 pins = "gpio8", "gpio9";
5283 function = "q 4731 function = "qup4";
5284 drive-strengt 4732 drive-strength = <2>;
5285 bias-disable; 4733 bias-disable;
5286 }; 4734 };
5287 4735
5288 qup_i2c5_default: qup 4736 qup_i2c5_default: qup-i2c5-default-state {
5289 pins = "gpio1 4737 pins = "gpio12", "gpio13";
5290 function = "q 4738 function = "qup5";
5291 drive-strengt 4739 drive-strength = <2>;
5292 bias-disable; 4740 bias-disable;
5293 }; 4741 };
5294 4742
5295 qup_i2c6_default: qup 4743 qup_i2c6_default: qup-i2c6-default-state {
5296 pins = "gpio1 4744 pins = "gpio16", "gpio17";
5297 function = "q 4745 function = "qup6";
5298 drive-strengt 4746 drive-strength = <2>;
5299 bias-disable; 4747 bias-disable;
5300 }; 4748 };
5301 4749
5302 qup_i2c7_default: qup 4750 qup_i2c7_default: qup-i2c7-default-state {
5303 pins = "gpio2 4751 pins = "gpio20", "gpio21";
5304 function = "q 4752 function = "qup7";
5305 drive-strengt 4753 drive-strength = <2>;
5306 bias-disable; 4754 bias-disable;
5307 }; 4755 };
5308 4756
5309 qup_i2c8_default: qup 4757 qup_i2c8_default: qup-i2c8-default-state {
5310 pins = "gpio2 4758 pins = "gpio24", "gpio25";
5311 function = "q 4759 function = "qup8";
5312 drive-strengt 4760 drive-strength = <2>;
5313 bias-disable; 4761 bias-disable;
5314 }; 4762 };
5315 4763
5316 qup_i2c9_default: qup 4764 qup_i2c9_default: qup-i2c9-default-state {
5317 pins = "gpio1 4765 pins = "gpio125", "gpio126";
5318 function = "q 4766 function = "qup9";
5319 drive-strengt 4767 drive-strength = <2>;
5320 bias-disable; 4768 bias-disable;
5321 }; 4769 };
5322 4770
5323 qup_i2c10_default: qu 4771 qup_i2c10_default: qup-i2c10-default-state {
5324 pins = "gpio1 4772 pins = "gpio129", "gpio130";
5325 function = "q 4773 function = "qup10";
5326 drive-strengt 4774 drive-strength = <2>;
5327 bias-disable; 4775 bias-disable;
5328 }; 4776 };
5329 4777
5330 qup_i2c11_default: qu 4778 qup_i2c11_default: qup-i2c11-default-state {
5331 pins = "gpio6 4779 pins = "gpio60", "gpio61";
5332 function = "q 4780 function = "qup11";
5333 drive-strengt 4781 drive-strength = <2>;
5334 bias-disable; 4782 bias-disable;
5335 }; 4783 };
5336 4784
5337 qup_i2c12_default: qu 4785 qup_i2c12_default: qup-i2c12-default-state {
5338 pins = "gpio3 4786 pins = "gpio32", "gpio33";
5339 function = "q 4787 function = "qup12";
5340 drive-strengt 4788 drive-strength = <2>;
5341 bias-disable; 4789 bias-disable;
5342 }; 4790 };
5343 4791
5344 qup_i2c13_default: qu 4792 qup_i2c13_default: qup-i2c13-default-state {
5345 pins = "gpio3 4793 pins = "gpio36", "gpio37";
5346 function = "q 4794 function = "qup13";
5347 drive-strengt 4795 drive-strength = <2>;
5348 bias-disable; 4796 bias-disable;
5349 }; 4797 };
5350 4798
5351 qup_i2c14_default: qu 4799 qup_i2c14_default: qup-i2c14-default-state {
5352 pins = "gpio4 4800 pins = "gpio40", "gpio41";
5353 function = "q 4801 function = "qup14";
5354 drive-strengt 4802 drive-strength = <2>;
5355 bias-disable; 4803 bias-disable;
5356 }; 4804 };
5357 4805
5358 qup_i2c15_default: qu 4806 qup_i2c15_default: qup-i2c15-default-state {
5359 pins = "gpio4 4807 pins = "gpio44", "gpio45";
5360 function = "q 4808 function = "qup15";
5361 drive-strengt 4809 drive-strength = <2>;
5362 bias-disable; 4810 bias-disable;
5363 }; 4811 };
5364 4812
5365 qup_i2c16_default: qu 4813 qup_i2c16_default: qup-i2c16-default-state {
5366 pins = "gpio4 4814 pins = "gpio48", "gpio49";
5367 function = "q 4815 function = "qup16";
5368 drive-strengt 4816 drive-strength = <2>;
5369 bias-disable; 4817 bias-disable;
5370 }; 4818 };
5371 4819
5372 qup_i2c17_default: qu 4820 qup_i2c17_default: qup-i2c17-default-state {
5373 pins = "gpio5 4821 pins = "gpio52", "gpio53";
5374 function = "q 4822 function = "qup17";
5375 drive-strengt 4823 drive-strength = <2>;
5376 bias-disable; 4824 bias-disable;
5377 }; 4825 };
5378 4826
5379 qup_i2c18_default: qu 4827 qup_i2c18_default: qup-i2c18-default-state {
5380 pins = "gpio5 4828 pins = "gpio56", "gpio57";
5381 function = "q 4829 function = "qup18";
5382 drive-strengt 4830 drive-strength = <2>;
5383 bias-disable; 4831 bias-disable;
5384 }; 4832 };
5385 4833
5386 qup_i2c19_default: qu 4834 qup_i2c19_default: qup-i2c19-default-state {
5387 pins = "gpio0 4835 pins = "gpio0", "gpio1";
5388 function = "q 4836 function = "qup19";
5389 drive-strengt 4837 drive-strength = <2>;
5390 bias-disable; 4838 bias-disable;
5391 }; 4839 };
5392 4840
5393 qup_spi0_cs: qup-spi0 4841 qup_spi0_cs: qup-spi0-cs-state {
5394 pins = "gpio3 4842 pins = "gpio31";
5395 function = "q 4843 function = "qup0";
5396 }; 4844 };
5397 4845
5398 qup_spi0_cs_gpio: qup 4846 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state {
5399 pins = "gpio3 4847 pins = "gpio31";
5400 function = "g 4848 function = "gpio";
5401 }; 4849 };
5402 4850
5403 qup_spi0_data_clk: qu 4851 qup_spi0_data_clk: qup-spi0-data-clk-state {
5404 pins = "gpio2 4852 pins = "gpio28", "gpio29",
5405 "gpio3 4853 "gpio30";
5406 function = "q 4854 function = "qup0";
5407 }; 4855 };
5408 4856
5409 qup_spi1_cs: qup-spi1 4857 qup_spi1_cs: qup-spi1-cs-state {
5410 pins = "gpio7 4858 pins = "gpio7";
5411 function = "q 4859 function = "qup1";
5412 }; 4860 };
5413 4861
5414 qup_spi1_cs_gpio: qup 4862 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state {
5415 pins = "gpio7 4863 pins = "gpio7";
5416 function = "g 4864 function = "gpio";
5417 }; 4865 };
5418 4866
5419 qup_spi1_data_clk: qu 4867 qup_spi1_data_clk: qup-spi1-data-clk-state {
5420 pins = "gpio4 4868 pins = "gpio4", "gpio5",
5421 "gpio6 4869 "gpio6";
5422 function = "q 4870 function = "qup1";
5423 }; 4871 };
5424 4872
5425 qup_spi2_cs: qup-spi2 4873 qup_spi2_cs: qup-spi2-cs-state {
5426 pins = "gpio1 4874 pins = "gpio118";
5427 function = "q 4875 function = "qup2";
5428 }; 4876 };
5429 4877
5430 qup_spi2_cs_gpio: qup 4878 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state {
5431 pins = "gpio1 4879 pins = "gpio118";
5432 function = "g 4880 function = "gpio";
5433 }; 4881 };
5434 4882
5435 qup_spi2_data_clk: qu 4883 qup_spi2_data_clk: qup-spi2-data-clk-state {
5436 pins = "gpio1 4884 pins = "gpio115", "gpio116",
5437 "gpio1 4885 "gpio117";
5438 function = "q 4886 function = "qup2";
5439 }; 4887 };
5440 4888
5441 qup_spi3_cs: qup-spi3 4889 qup_spi3_cs: qup-spi3-cs-state {
5442 pins = "gpio1 4890 pins = "gpio122";
5443 function = "q 4891 function = "qup3";
5444 }; 4892 };
5445 4893
5446 qup_spi3_cs_gpio: qup 4894 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state {
5447 pins = "gpio1 4895 pins = "gpio122";
5448 function = "g 4896 function = "gpio";
5449 }; 4897 };
5450 4898
5451 qup_spi3_data_clk: qu 4899 qup_spi3_data_clk: qup-spi3-data-clk-state {
5452 pins = "gpio1 4900 pins = "gpio119", "gpio120",
5453 "gpio1 4901 "gpio121";
5454 function = "q 4902 function = "qup3";
5455 }; 4903 };
5456 4904
5457 qup_spi4_cs: qup-spi4 4905 qup_spi4_cs: qup-spi4-cs-state {
5458 pins = "gpio1 4906 pins = "gpio11";
5459 function = "q 4907 function = "qup4";
5460 }; 4908 };
5461 4909
5462 qup_spi4_cs_gpio: qup 4910 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state {
5463 pins = "gpio1 4911 pins = "gpio11";
5464 function = "g 4912 function = "gpio";
5465 }; 4913 };
5466 4914
5467 qup_spi4_data_clk: qu 4915 qup_spi4_data_clk: qup-spi4-data-clk-state {
5468 pins = "gpio8 4916 pins = "gpio8", "gpio9",
5469 "gpio1 4917 "gpio10";
5470 function = "q 4918 function = "qup4";
5471 }; 4919 };
5472 4920
5473 qup_spi5_cs: qup-spi5 4921 qup_spi5_cs: qup-spi5-cs-state {
5474 pins = "gpio1 4922 pins = "gpio15";
5475 function = "q 4923 function = "qup5";
5476 }; 4924 };
5477 4925
5478 qup_spi5_cs_gpio: qup 4926 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state {
5479 pins = "gpio1 4927 pins = "gpio15";
5480 function = "g 4928 function = "gpio";
5481 }; 4929 };
5482 4930
5483 qup_spi5_data_clk: qu 4931 qup_spi5_data_clk: qup-spi5-data-clk-state {
5484 pins = "gpio1 4932 pins = "gpio12", "gpio13",
5485 "gpio1 4933 "gpio14";
5486 function = "q 4934 function = "qup5";
5487 }; 4935 };
5488 4936
5489 qup_spi6_cs: qup-spi6 4937 qup_spi6_cs: qup-spi6-cs-state {
5490 pins = "gpio1 4938 pins = "gpio19";
5491 function = "q 4939 function = "qup6";
5492 }; 4940 };
5493 4941
5494 qup_spi6_cs_gpio: qup 4942 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state {
5495 pins = "gpio1 4943 pins = "gpio19";
5496 function = "g 4944 function = "gpio";
5497 }; 4945 };
5498 4946
5499 qup_spi6_data_clk: qu 4947 qup_spi6_data_clk: qup-spi6-data-clk-state {
5500 pins = "gpio1 4948 pins = "gpio16", "gpio17",
5501 "gpio1 4949 "gpio18";
5502 function = "q 4950 function = "qup6";
5503 }; 4951 };
5504 4952
5505 qup_spi7_cs: qup-spi7 4953 qup_spi7_cs: qup-spi7-cs-state {
5506 pins = "gpio2 4954 pins = "gpio23";
5507 function = "q 4955 function = "qup7";
5508 }; 4956 };
5509 4957
5510 qup_spi7_cs_gpio: qup 4958 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state {
5511 pins = "gpio2 4959 pins = "gpio23";
5512 function = "g 4960 function = "gpio";
5513 }; 4961 };
5514 4962
5515 qup_spi7_data_clk: qu 4963 qup_spi7_data_clk: qup-spi7-data-clk-state {
5516 pins = "gpio2 4964 pins = "gpio20", "gpio21",
5517 "gpio2 4965 "gpio22";
5518 function = "q 4966 function = "qup7";
5519 }; 4967 };
5520 4968
5521 qup_spi8_cs: qup-spi8 4969 qup_spi8_cs: qup-spi8-cs-state {
5522 pins = "gpio2 4970 pins = "gpio27";
5523 function = "q 4971 function = "qup8";
5524 }; 4972 };
5525 4973
5526 qup_spi8_cs_gpio: qup 4974 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state {
5527 pins = "gpio2 4975 pins = "gpio27";
5528 function = "g 4976 function = "gpio";
5529 }; 4977 };
5530 4978
5531 qup_spi8_data_clk: qu 4979 qup_spi8_data_clk: qup-spi8-data-clk-state {
5532 pins = "gpio2 4980 pins = "gpio24", "gpio25",
5533 "gpio2 4981 "gpio26";
5534 function = "q 4982 function = "qup8";
5535 }; 4983 };
5536 4984
5537 qup_spi9_cs: qup-spi9 4985 qup_spi9_cs: qup-spi9-cs-state {
5538 pins = "gpio1 4986 pins = "gpio128";
5539 function = "q 4987 function = "qup9";
5540 }; 4988 };
5541 4989
5542 qup_spi9_cs_gpio: qup 4990 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state {
5543 pins = "gpio1 4991 pins = "gpio128";
5544 function = "g 4992 function = "gpio";
5545 }; 4993 };
5546 4994
5547 qup_spi9_data_clk: qu 4995 qup_spi9_data_clk: qup-spi9-data-clk-state {
5548 pins = "gpio1 4996 pins = "gpio125", "gpio126",
5549 "gpio1 4997 "gpio127";
5550 function = "q 4998 function = "qup9";
5551 }; 4999 };
5552 5000
5553 qup_spi10_cs: qup-spi 5001 qup_spi10_cs: qup-spi10-cs-state {
5554 pins = "gpio1 5002 pins = "gpio132";
5555 function = "q 5003 function = "qup10";
5556 }; 5004 };
5557 5005
5558 qup_spi10_cs_gpio: qu 5006 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state {
5559 pins = "gpio1 5007 pins = "gpio132";
5560 function = "g 5008 function = "gpio";
5561 }; 5009 };
5562 5010
5563 qup_spi10_data_clk: q 5011 qup_spi10_data_clk: qup-spi10-data-clk-state {
5564 pins = "gpio1 5012 pins = "gpio129", "gpio130",
5565 "gpio1 5013 "gpio131";
5566 function = "q 5014 function = "qup10";
5567 }; 5015 };
5568 5016
5569 qup_spi11_cs: qup-spi 5017 qup_spi11_cs: qup-spi11-cs-state {
5570 pins = "gpio6 5018 pins = "gpio63";
5571 function = "q 5019 function = "qup11";
5572 }; 5020 };
5573 5021
5574 qup_spi11_cs_gpio: qu 5022 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state {
5575 pins = "gpio6 5023 pins = "gpio63";
5576 function = "g 5024 function = "gpio";
5577 }; 5025 };
5578 5026
5579 qup_spi11_data_clk: q 5027 qup_spi11_data_clk: qup-spi11-data-clk-state {
5580 pins = "gpio6 5028 pins = "gpio60", "gpio61",
5581 "gpio6 5029 "gpio62";
5582 function = "q 5030 function = "qup11";
5583 }; 5031 };
5584 5032
5585 qup_spi12_cs: qup-spi 5033 qup_spi12_cs: qup-spi12-cs-state {
5586 pins = "gpio3 5034 pins = "gpio35";
5587 function = "q 5035 function = "qup12";
5588 }; 5036 };
5589 5037
5590 qup_spi12_cs_gpio: qu 5038 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state {
5591 pins = "gpio3 5039 pins = "gpio35";
5592 function = "g 5040 function = "gpio";
5593 }; 5041 };
5594 5042
5595 qup_spi12_data_clk: q 5043 qup_spi12_data_clk: qup-spi12-data-clk-state {
5596 pins = "gpio3 5044 pins = "gpio32", "gpio33",
5597 "gpio3 5045 "gpio34";
5598 function = "q 5046 function = "qup12";
5599 }; 5047 };
5600 5048
5601 qup_spi13_cs: qup-spi 5049 qup_spi13_cs: qup-spi13-cs-state {
5602 pins = "gpio3 5050 pins = "gpio39";
5603 function = "q 5051 function = "qup13";
5604 }; 5052 };
5605 5053
5606 qup_spi13_cs_gpio: qu 5054 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state {
5607 pins = "gpio3 5055 pins = "gpio39";
5608 function = "g 5056 function = "gpio";
5609 }; 5057 };
5610 5058
5611 qup_spi13_data_clk: q 5059 qup_spi13_data_clk: qup-spi13-data-clk-state {
5612 pins = "gpio3 5060 pins = "gpio36", "gpio37",
5613 "gpio3 5061 "gpio38";
5614 function = "q 5062 function = "qup13";
5615 }; 5063 };
5616 5064
5617 qup_spi14_cs: qup-spi 5065 qup_spi14_cs: qup-spi14-cs-state {
5618 pins = "gpio4 5066 pins = "gpio43";
5619 function = "q 5067 function = "qup14";
5620 }; 5068 };
5621 5069
5622 qup_spi14_cs_gpio: qu 5070 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state {
5623 pins = "gpio4 5071 pins = "gpio43";
5624 function = "g 5072 function = "gpio";
5625 }; 5073 };
5626 5074
5627 qup_spi14_data_clk: q 5075 qup_spi14_data_clk: qup-spi14-data-clk-state {
5628 pins = "gpio4 5076 pins = "gpio40", "gpio41",
5629 "gpio4 5077 "gpio42";
5630 function = "q 5078 function = "qup14";
5631 }; 5079 };
5632 5080
5633 qup_spi15_cs: qup-spi 5081 qup_spi15_cs: qup-spi15-cs-state {
5634 pins = "gpio4 5082 pins = "gpio47";
5635 function = "q 5083 function = "qup15";
5636 }; 5084 };
5637 5085
5638 qup_spi15_cs_gpio: qu 5086 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state {
5639 pins = "gpio4 5087 pins = "gpio47";
5640 function = "g 5088 function = "gpio";
5641 }; 5089 };
5642 5090
5643 qup_spi15_data_clk: q 5091 qup_spi15_data_clk: qup-spi15-data-clk-state {
5644 pins = "gpio4 5092 pins = "gpio44", "gpio45",
5645 "gpio4 5093 "gpio46";
5646 function = "q 5094 function = "qup15";
5647 }; 5095 };
5648 5096
5649 qup_spi16_cs: qup-spi 5097 qup_spi16_cs: qup-spi16-cs-state {
5650 pins = "gpio5 5098 pins = "gpio51";
5651 function = "q 5099 function = "qup16";
5652 }; 5100 };
5653 5101
5654 qup_spi16_cs_gpio: qu 5102 qup_spi16_cs_gpio: qup-spi16-cs-gpio-state {
5655 pins = "gpio5 5103 pins = "gpio51";
5656 function = "g 5104 function = "gpio";
5657 }; 5105 };
5658 5106
5659 qup_spi16_data_clk: q 5107 qup_spi16_data_clk: qup-spi16-data-clk-state {
5660 pins = "gpio4 5108 pins = "gpio48", "gpio49",
5661 "gpio5 5109 "gpio50";
5662 function = "q 5110 function = "qup16";
5663 }; 5111 };
5664 5112
5665 qup_spi17_cs: qup-spi 5113 qup_spi17_cs: qup-spi17-cs-state {
5666 pins = "gpio5 5114 pins = "gpio55";
5667 function = "q 5115 function = "qup17";
5668 }; 5116 };
5669 5117
5670 qup_spi17_cs_gpio: qu 5118 qup_spi17_cs_gpio: qup-spi17-cs-gpio-state {
5671 pins = "gpio5 5119 pins = "gpio55";
5672 function = "g 5120 function = "gpio";
5673 }; 5121 };
5674 5122
5675 qup_spi17_data_clk: q 5123 qup_spi17_data_clk: qup-spi17-data-clk-state {
5676 pins = "gpio5 5124 pins = "gpio52", "gpio53",
5677 "gpio5 5125 "gpio54";
5678 function = "q 5126 function = "qup17";
5679 }; 5127 };
5680 5128
5681 qup_spi18_cs: qup-spi 5129 qup_spi18_cs: qup-spi18-cs-state {
5682 pins = "gpio5 5130 pins = "gpio59";
5683 function = "q 5131 function = "qup18";
5684 }; 5132 };
5685 5133
5686 qup_spi18_cs_gpio: qu 5134 qup_spi18_cs_gpio: qup-spi18-cs-gpio-state {
5687 pins = "gpio5 5135 pins = "gpio59";
5688 function = "g 5136 function = "gpio";
5689 }; 5137 };
5690 5138
5691 qup_spi18_data_clk: q 5139 qup_spi18_data_clk: qup-spi18-data-clk-state {
5692 pins = "gpio5 5140 pins = "gpio56", "gpio57",
5693 "gpio5 5141 "gpio58";
5694 function = "q 5142 function = "qup18";
5695 }; 5143 };
5696 5144
5697 qup_spi19_cs: qup-spi 5145 qup_spi19_cs: qup-spi19-cs-state {
5698 pins = "gpio3 5146 pins = "gpio3";
5699 function = "q 5147 function = "qup19";
5700 }; 5148 };
5701 5149
5702 qup_spi19_cs_gpio: qu 5150 qup_spi19_cs_gpio: qup-spi19-cs-gpio-state {
5703 pins = "gpio3 5151 pins = "gpio3";
5704 function = "g 5152 function = "gpio";
5705 }; 5153 };
5706 5154
5707 qup_spi19_data_clk: q 5155 qup_spi19_data_clk: qup-spi19-data-clk-state {
5708 pins = "gpio0 5156 pins = "gpio0", "gpio1",
5709 "gpio2 5157 "gpio2";
5710 function = "q 5158 function = "qup19";
5711 }; 5159 };
5712 5160
5713 qup_uart2_default: qu 5161 qup_uart2_default: qup-uart2-default-state {
5714 pins = "gpio1 5162 pins = "gpio117", "gpio118";
5715 function = "q 5163 function = "qup2";
5716 }; 5164 };
5717 5165
5718 qup_uart6_default: qu 5166 qup_uart6_default: qup-uart6-default-state {
5719 pins = "gpio1 5167 pins = "gpio16", "gpio17", "gpio18", "gpio19";
5720 function = "q 5168 function = "qup6";
5721 }; 5169 };
5722 5170
5723 qup_uart12_default: q 5171 qup_uart12_default: qup-uart12-default-state {
5724 pins = "gpio3 5172 pins = "gpio34", "gpio35";
5725 function = "q 5173 function = "qup12";
5726 }; 5174 };
5727 5175
5728 qup_uart17_default: q 5176 qup_uart17_default: qup-uart17-default-state {
5729 pins = "gpio5 5177 pins = "gpio52", "gpio53", "gpio54", "gpio55";
5730 function = "q 5178 function = "qup17";
5731 }; 5179 };
5732 5180
5733 qup_uart18_default: q 5181 qup_uart18_default: qup-uart18-default-state {
5734 pins = "gpio5 5182 pins = "gpio58", "gpio59";
5735 function = "q 5183 function = "qup18";
5736 }; 5184 };
5737 5185
5738 tert_mi2s_active: ter 5186 tert_mi2s_active: tert-mi2s-active-state {
5739 sck-pins { 5187 sck-pins {
5740 pins 5188 pins = "gpio133";
5741 funct 5189 function = "mi2s2_sck";
5742 drive 5190 drive-strength = <8>;
5743 bias- 5191 bias-disable;
5744 }; 5192 };
5745 5193
5746 data0-pins { 5194 data0-pins {
5747 pins 5195 pins = "gpio134";
5748 funct 5196 function = "mi2s2_data0";
5749 drive 5197 drive-strength = <8>;
5750 bias- 5198 bias-disable;
5751 outpu 5199 output-high;
5752 }; 5200 };
5753 5201
5754 ws-pins { 5202 ws-pins {
5755 pins 5203 pins = "gpio135";
5756 funct 5204 function = "mi2s2_ws";
5757 drive 5205 drive-strength = <8>;
5758 outpu 5206 output-high;
5759 }; 5207 };
5760 }; 5208 };
5761 5209
5762 sdc2_sleep_state: sdc 5210 sdc2_sleep_state: sdc2-sleep-state {
5763 clk-pins { 5211 clk-pins {
5764 pins 5212 pins = "sdc2_clk";
5765 drive 5213 drive-strength = <2>;
5766 bias- 5214 bias-disable;
5767 }; 5215 };
5768 5216
5769 cmd-pins { 5217 cmd-pins {
5770 pins 5218 pins = "sdc2_cmd";
5771 drive 5219 drive-strength = <2>;
5772 bias- 5220 bias-pull-up;
5773 }; 5221 };
5774 5222
5775 data-pins { 5223 data-pins {
5776 pins 5224 pins = "sdc2_data";
5777 drive 5225 drive-strength = <2>;
5778 bias- 5226 bias-pull-up;
5779 }; 5227 };
5780 }; 5228 };
5781 5229
5782 pcie0_default_state: 5230 pcie0_default_state: pcie0-default-state {
5783 perst-pins { 5231 perst-pins {
5784 pins 5232 pins = "gpio79";
5785 funct 5233 function = "gpio";
5786 drive 5234 drive-strength = <2>;
5787 bias- 5235 bias-pull-down;
5788 }; 5236 };
5789 5237
5790 clkreq-pins { 5238 clkreq-pins {
5791 pins 5239 pins = "gpio80";
5792 funct 5240 function = "pci_e0";
5793 drive 5241 drive-strength = <2>;
5794 bias- 5242 bias-pull-up;
5795 }; 5243 };
5796 5244
5797 wake-pins { 5245 wake-pins {
5798 pins 5246 pins = "gpio81";
5799 funct 5247 function = "gpio";
5800 drive 5248 drive-strength = <2>;
5801 bias- 5249 bias-pull-up;
5802 }; 5250 };
5803 }; 5251 };
5804 5252
5805 pcie1_default_state: 5253 pcie1_default_state: pcie1-default-state {
5806 perst-pins { 5254 perst-pins {
5807 pins 5255 pins = "gpio82";
5808 funct 5256 function = "gpio";
5809 drive 5257 drive-strength = <2>;
5810 bias- 5258 bias-pull-down;
5811 }; 5259 };
5812 5260
5813 clkreq-pins { 5261 clkreq-pins {
5814 pins 5262 pins = "gpio83";
5815 funct 5263 function = "pci_e1";
5816 drive 5264 drive-strength = <2>;
5817 bias- 5265 bias-pull-up;
5818 }; 5266 };
5819 5267
5820 wake-pins { 5268 wake-pins {
5821 pins 5269 pins = "gpio84";
5822 funct 5270 function = "gpio";
5823 drive 5271 drive-strength = <2>;
5824 bias- 5272 bias-pull-up;
5825 }; 5273 };
5826 }; 5274 };
5827 5275
5828 pcie2_default_state: 5276 pcie2_default_state: pcie2-default-state {
5829 perst-pins { 5277 perst-pins {
5830 pins 5278 pins = "gpio85";
5831 funct 5279 function = "gpio";
5832 drive 5280 drive-strength = <2>;
5833 bias- 5281 bias-pull-down;
5834 }; 5282 };
5835 5283
5836 clkreq-pins { 5284 clkreq-pins {
5837 pins 5285 pins = "gpio86";
5838 funct 5286 function = "pci_e2";
5839 drive 5287 drive-strength = <2>;
5840 bias- 5288 bias-pull-up;
5841 }; 5289 };
5842 5290
5843 wake-pins { 5291 wake-pins {
5844 pins 5292 pins = "gpio87";
5845 funct 5293 function = "gpio";
5846 drive 5294 drive-strength = <2>;
5847 bias- 5295 bias-pull-up;
5848 }; 5296 };
5849 }; 5297 };
5850 }; 5298 };
5851 5299
5852 apps_smmu: iommu@15000000 { 5300 apps_smmu: iommu@15000000 {
5853 compatible = "qcom,sm 5301 compatible = "qcom,sm8250-smmu-500", "qcom,smmu-500", "arm,mmu-500";
5854 reg = <0 0x15000000 0 5302 reg = <0 0x15000000 0 0x100000>;
5855 #iommu-cells = <2>; 5303 #iommu-cells = <2>;
5856 #global-interrupts = 5304 #global-interrupts = <2>;
5857 interrupts = <GIC_SPI 5305 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
5858 <GIC_SPI 5306 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
5859 <GIC_SPI 5307 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
5860 <GIC_SPI 5308 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
5861 <GIC_SPI 5309 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
5862 <GIC_SPI 5310 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
5863 <GIC_SPI 5311 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
5864 <GIC_SPI 5312 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
5865 <GIC_SPI 5313 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
5866 <GIC_SPI 5314 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
5867 <GIC_SPI 5315 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
5868 <GIC_SPI 5316 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
5869 <GIC_SPI 5317 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
5870 <GIC_SPI 5318 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
5871 <GIC_SPI 5319 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
5872 <GIC_SPI 5320 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
5873 <GIC_SPI 5321 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
5874 <GIC_SPI 5322 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
5875 <GIC_SPI 5323 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
5876 <GIC_SPI 5324 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
5877 <GIC_SPI 5325 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
5878 <GIC_SPI 5326 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
5879 <GIC_SPI 5327 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
5880 <GIC_SPI 5328 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
5881 <GIC_SPI 5329 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
5882 <GIC_SPI 5330 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
5883 <GIC_SPI 5331 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
5884 <GIC_SPI 5332 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
5885 <GIC_SPI 5333 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
5886 <GIC_SPI 5334 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
5887 <GIC_SPI 5335 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
5888 <GIC_SPI 5336 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
5889 <GIC_SPI 5337 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
5890 <GIC_SPI 5338 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
5891 <GIC_SPI 5339 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
5892 <GIC_SPI 5340 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
5893 <GIC_SPI 5341 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
5894 <GIC_SPI 5342 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
5895 <GIC_SPI 5343 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
5896 <GIC_SPI 5344 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
5897 <GIC_SPI 5345 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
5898 <GIC_SPI 5346 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
5899 <GIC_SPI 5347 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
5900 <GIC_SPI 5348 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
5901 <GIC_SPI 5349 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
5902 <GIC_SPI 5350 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
5903 <GIC_SPI 5351 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
5904 <GIC_SPI 5352 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
5905 <GIC_SPI 5353 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
5906 <GIC_SPI 5354 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
5907 <GIC_SPI 5355 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
5908 <GIC_SPI 5356 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
5909 <GIC_SPI 5357 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
5910 <GIC_SPI 5358 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
5911 <GIC_SPI 5359 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
5912 <GIC_SPI 5360 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
5913 <GIC_SPI 5361 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
5914 <GIC_SPI 5362 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
5915 <GIC_SPI 5363 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
5916 <GIC_SPI 5364 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
5917 <GIC_SPI 5365 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
5918 <GIC_SPI 5366 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
5919 <GIC_SPI 5367 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
5920 <GIC_SPI 5368 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
5921 <GIC_SPI 5369 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
5922 <GIC_SPI 5370 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
5923 <GIC_SPI 5371 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
5924 <GIC_SPI 5372 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
5925 <GIC_SPI 5373 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
5926 <GIC_SPI 5374 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
5927 <GIC_SPI 5375 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
5928 <GIC_SPI 5376 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
5929 <GIC_SPI 5377 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
5930 <GIC_SPI 5378 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
5931 <GIC_SPI 5379 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
5932 <GIC_SPI 5380 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
5933 <GIC_SPI 5381 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
5934 <GIC_SPI 5382 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
5935 <GIC_SPI 5383 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
5936 <GIC_SPI 5384 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
5937 <GIC_SPI 5385 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
5938 <GIC_SPI 5386 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
5939 <GIC_SPI 5387 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
5940 <GIC_SPI 5388 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
5941 <GIC_SPI 5389 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
5942 <GIC_SPI 5390 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
5943 <GIC_SPI 5391 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
5944 <GIC_SPI 5392 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
5945 <GIC_SPI 5393 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
5946 <GIC_SPI 5394 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
5947 <GIC_SPI 5395 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
5948 <GIC_SPI 5396 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
5949 <GIC_SPI 5397 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
5950 <GIC_SPI 5398 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
5951 <GIC_SPI 5399 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
5952 <GIC_SPI 5400 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
5953 <GIC_SPI 5401 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
5954 <GIC_SPI 5402 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>;
5955 dma-coherent; 5403 dma-coherent;
5956 }; 5404 };
5957 5405
5958 adsp: remoteproc@17300000 { 5406 adsp: remoteproc@17300000 {
5959 compatible = "qcom,sm 5407 compatible = "qcom,sm8250-adsp-pas";
5960 reg = <0 0x17300000 0 5408 reg = <0 0x17300000 0 0x100>;
5961 5409
5962 interrupts-extended = !! 5410 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
5963 5411 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
5964 5412 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
5965 5413 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
5966 5414 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
5967 interrupt-names = "wd 5415 interrupt-names = "wdog", "fatal", "ready",
5968 "ha 5416 "handover", "stop-ack";
5969 5417
5970 clocks = <&rpmhcc RPM 5418 clocks = <&rpmhcc RPMH_CXO_CLK>;
5971 clock-names = "xo"; 5419 clock-names = "xo";
5972 5420
5973 power-domains = <&rpm !! 5421 power-domains = <&rpmhpd SM8250_LCX>,
5974 <&rpm !! 5422 <&rpmhpd SM8250_LMX>;
5975 power-domain-names = 5423 power-domain-names = "lcx", "lmx";
5976 5424
5977 memory-region = <&ads 5425 memory-region = <&adsp_mem>;
5978 5426
5979 qcom,qmp = <&aoss_qmp 5427 qcom,qmp = <&aoss_qmp>;
5980 5428
5981 qcom,smem-states = <& 5429 qcom,smem-states = <&smp2p_adsp_out 0>;
5982 qcom,smem-state-names 5430 qcom,smem-state-names = "stop";
5983 5431
5984 status = "disabled"; 5432 status = "disabled";
5985 5433
5986 glink-edge { 5434 glink-edge {
5987 interrupts-ex 5435 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
5988 5436 IPCC_MPROC_SIGNAL_GLINK_QMP
5989 5437 IRQ_TYPE_EDGE_RISING>;
5990 mboxes = <&ip 5438 mboxes = <&ipcc IPCC_CLIENT_LPASS
5991 5439 IPCC_MPROC_SIGNAL_GLINK_QMP>;
5992 5440
5993 label = "lpas 5441 label = "lpass";
5994 qcom,remote-p 5442 qcom,remote-pid = <2>;
5995 5443
5996 apr { 5444 apr {
5997 compa 5445 compatible = "qcom,apr-v2";
5998 qcom, 5446 qcom,glink-channels = "apr_audio_svc";
5999 qcom, 5447 qcom,domain = <APR_DOMAIN_ADSP>;
6000 #addr 5448 #address-cells = <1>;
6001 #size 5449 #size-cells = <0>;
6002 5450
6003 servi 5451 service@3 {
6004 5452 reg = <APR_SVC_ADSP_CORE>;
6005 5453 compatible = "qcom,q6core";
6006 5454 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6007 }; 5455 };
6008 5456
6009 q6afe 5457 q6afe: service@4 {
6010 5458 compatible = "qcom,q6afe";
6011 5459 reg = <APR_SVC_AFE>;
6012 5460 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6013 5461 q6afedai: dais {
6014 5462 compatible = "qcom,q6afe-dais";
6015 5463 #address-cells = <1>;
6016 5464 #size-cells = <0>;
6017 5465 #sound-dai-cells = <1>;
6018 5466 };
6019 5467
6020 5468 q6afecc: clock-controller {
6021 5469 compatible = "qcom,q6afe-clocks";
6022 5470 #clock-cells = <2>;
6023 5471 };
6024 }; 5472 };
6025 5473
6026 q6asm 5474 q6asm: service@7 {
6027 5475 compatible = "qcom,q6asm";
6028 5476 reg = <APR_SVC_ASM>;
6029 5477 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6030 5478 q6asmdai: dais {
6031 5479 compatible = "qcom,q6asm-dais";
6032 5480 #address-cells = <1>;
6033 5481 #size-cells = <0>;
6034 5482 #sound-dai-cells = <1>;
6035 5483 iommus = <&apps_smmu 0x1801 0x0>;
6036 5484 };
6037 }; 5485 };
6038 5486
6039 q6adm 5487 q6adm: service@8 {
6040 5488 compatible = "qcom,q6adm";
6041 5489 reg = <APR_SVC_ADM>;
6042 5490 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6043 5491 q6routing: routing {
6044 5492 compatible = "qcom,q6adm-routing";
6045 5493 #sound-dai-cells = <0>;
6046 5494 };
6047 }; 5495 };
6048 }; 5496 };
6049 5497
6050 fastrpc { 5498 fastrpc {
6051 compa 5499 compatible = "qcom,fastrpc";
6052 qcom, 5500 qcom,glink-channels = "fastrpcglink-apps-dsp";
6053 label 5501 label = "adsp";
6054 qcom, 5502 qcom,non-secure-domain;
6055 #addr 5503 #address-cells = <1>;
6056 #size 5504 #size-cells = <0>;
6057 5505
6058 compu 5506 compute-cb@3 {
6059 5507 compatible = "qcom,fastrpc-compute-cb";
6060 5508 reg = <3>;
6061 5509 iommus = <&apps_smmu 0x1803 0x0>;
6062 }; 5510 };
6063 5511
6064 compu 5512 compute-cb@4 {
6065 5513 compatible = "qcom,fastrpc-compute-cb";
6066 5514 reg = <4>;
6067 5515 iommus = <&apps_smmu 0x1804 0x0>;
6068 }; 5516 };
6069 5517
6070 compu 5518 compute-cb@5 {
6071 5519 compatible = "qcom,fastrpc-compute-cb";
6072 5520 reg = <5>;
6073 5521 iommus = <&apps_smmu 0x1805 0x0>;
6074 }; 5522 };
6075 }; 5523 };
6076 }; 5524 };
6077 }; 5525 };
6078 5526
6079 intc: interrupt-controller@17 5527 intc: interrupt-controller@17a00000 {
6080 compatible = "arm,gic 5528 compatible = "arm,gic-v3";
6081 #interrupt-cells = <3 5529 #interrupt-cells = <3>;
6082 interrupt-controller; 5530 interrupt-controller;
6083 reg = <0x0 0x17a00000 5531 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
6084 <0x0 0x17a60000 5532 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
6085 interrupts = <GIC_PPI 5533 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
6086 }; 5534 };
6087 5535
6088 watchdog@17c10000 { 5536 watchdog@17c10000 {
6089 compatible = "qcom,ap 5537 compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt";
6090 reg = <0 0x17c10000 0 5538 reg = <0 0x17c10000 0 0x1000>;
6091 clocks = <&sleep_clk> 5539 clocks = <&sleep_clk>;
6092 interrupts = <GIC_SPI !! 5540 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
6093 }; 5541 };
6094 5542
6095 timer@17c20000 { 5543 timer@17c20000 {
6096 #address-cells = <1>; 5544 #address-cells = <1>;
6097 #size-cells = <1>; 5545 #size-cells = <1>;
6098 ranges = <0 0 0 0x200 5546 ranges = <0 0 0 0x20000000>;
6099 compatible = "arm,arm 5547 compatible = "arm,armv7-timer-mem";
6100 reg = <0x0 0x17c20000 5548 reg = <0x0 0x17c20000 0x0 0x1000>;
6101 clock-frequency = <19 5549 clock-frequency = <19200000>;
6102 5550
6103 frame@17c21000 { 5551 frame@17c21000 {
6104 frame-number 5552 frame-number = <0>;
6105 interrupts = 5553 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
6106 5554 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
6107 reg = <0x17c2 5555 reg = <0x17c21000 0x1000>,
6108 <0x17c2 5556 <0x17c22000 0x1000>;
6109 }; 5557 };
6110 5558
6111 frame@17c23000 { 5559 frame@17c23000 {
6112 frame-number 5560 frame-number = <1>;
6113 interrupts = 5561 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
6114 reg = <0x17c2 5562 reg = <0x17c23000 0x1000>;
6115 status = "dis 5563 status = "disabled";
6116 }; 5564 };
6117 5565
6118 frame@17c25000 { 5566 frame@17c25000 {
6119 frame-number 5567 frame-number = <2>;
6120 interrupts = 5568 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
6121 reg = <0x17c2 5569 reg = <0x17c25000 0x1000>;
6122 status = "dis 5570 status = "disabled";
6123 }; 5571 };
6124 5572
6125 frame@17c27000 { 5573 frame@17c27000 {
6126 frame-number 5574 frame-number = <3>;
6127 interrupts = 5575 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
6128 reg = <0x17c2 5576 reg = <0x17c27000 0x1000>;
6129 status = "dis 5577 status = "disabled";
6130 }; 5578 };
6131 5579
6132 frame@17c29000 { 5580 frame@17c29000 {
6133 frame-number 5581 frame-number = <4>;
6134 interrupts = 5582 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
6135 reg = <0x17c2 5583 reg = <0x17c29000 0x1000>;
6136 status = "dis 5584 status = "disabled";
6137 }; 5585 };
6138 5586
6139 frame@17c2b000 { 5587 frame@17c2b000 {
6140 frame-number 5588 frame-number = <5>;
6141 interrupts = 5589 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
6142 reg = <0x17c2 5590 reg = <0x17c2b000 0x1000>;
6143 status = "dis 5591 status = "disabled";
6144 }; 5592 };
6145 5593
6146 frame@17c2d000 { 5594 frame@17c2d000 {
6147 frame-number 5595 frame-number = <6>;
6148 interrupts = 5596 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
6149 reg = <0x17c2 5597 reg = <0x17c2d000 0x1000>;
6150 status = "dis 5598 status = "disabled";
6151 }; 5599 };
6152 }; 5600 };
6153 5601
6154 apps_rsc: rsc@18200000 { 5602 apps_rsc: rsc@18200000 {
6155 label = "apps_rsc"; 5603 label = "apps_rsc";
6156 compatible = "qcom,rp 5604 compatible = "qcom,rpmh-rsc";
6157 reg = <0x0 0x18200000 5605 reg = <0x0 0x18200000 0x0 0x10000>,
6158 <0x0 0x182100 5606 <0x0 0x18210000 0x0 0x10000>,
6159 <0x0 0x182200 5607 <0x0 0x18220000 0x0 0x10000>;
6160 reg-names = "drv-0", 5608 reg-names = "drv-0", "drv-1", "drv-2";
6161 interrupts = <GIC_SPI 5609 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
6162 <GIC_SPI 5610 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
6163 <GIC_SPI 5611 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
6164 qcom,tcs-offset = <0x 5612 qcom,tcs-offset = <0xd00>;
6165 qcom,drv-id = <2>; 5613 qcom,drv-id = <2>;
6166 qcom,tcs-config = <AC 5614 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
6167 <WA 5615 <WAKE_TCS 3>, <CONTROL_TCS 1>;
6168 power-domains = <&CLU 5616 power-domains = <&CLUSTER_PD>;
6169 5617
6170 rpmhcc: clock-control 5618 rpmhcc: clock-controller {
6171 compatible = 5619 compatible = "qcom,sm8250-rpmh-clk";
6172 #clock-cells 5620 #clock-cells = <1>;
6173 clock-names = 5621 clock-names = "xo";
6174 clocks = <&xo 5622 clocks = <&xo_board>;
6175 }; 5623 };
6176 5624
6177 rpmhpd: power-control 5625 rpmhpd: power-controller {
6178 compatible = 5626 compatible = "qcom,sm8250-rpmhpd";
6179 #power-domain 5627 #power-domain-cells = <1>;
6180 operating-poi 5628 operating-points-v2 = <&rpmhpd_opp_table>;
6181 5629
6182 rpmhpd_opp_ta 5630 rpmhpd_opp_table: opp-table {
6183 compa 5631 compatible = "operating-points-v2";
6184 5632
6185 rpmhp 5633 rpmhpd_opp_ret: opp1 {
6186 5634 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
6187 }; 5635 };
6188 5636
6189 rpmhp 5637 rpmhpd_opp_min_svs: opp2 {
6190 5638 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
6191 }; 5639 };
6192 5640
6193 rpmhp 5641 rpmhpd_opp_low_svs: opp3 {
6194 5642 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
6195 }; 5643 };
6196 5644
6197 rpmhp 5645 rpmhpd_opp_svs: opp4 {
6198 5646 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
6199 }; 5647 };
6200 5648
6201 rpmhp 5649 rpmhpd_opp_svs_l1: opp5 {
6202 5650 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
6203 }; 5651 };
6204 5652
6205 rpmhp 5653 rpmhpd_opp_nom: opp6 {
6206 5654 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
6207 }; 5655 };
6208 5656
6209 rpmhp 5657 rpmhpd_opp_nom_l1: opp7 {
6210 5658 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
6211 }; 5659 };
6212 5660
6213 rpmhp 5661 rpmhpd_opp_nom_l2: opp8 {
6214 5662 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
6215 }; 5663 };
6216 5664
6217 rpmhp 5665 rpmhpd_opp_turbo: opp9 {
6218 5666 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
6219 }; 5667 };
6220 5668
6221 rpmhp 5669 rpmhpd_opp_turbo_l1: opp10 {
6222 5670 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
6223 }; 5671 };
6224 }; 5672 };
6225 }; 5673 };
6226 5674
6227 apps_bcm_voter: bcm-v 5675 apps_bcm_voter: bcm-voter {
6228 compatible = 5676 compatible = "qcom,bcm-voter";
6229 }; 5677 };
6230 }; 5678 };
6231 5679
6232 epss_l3: interconnect@1859000 5680 epss_l3: interconnect@18590000 {
6233 compatible = "qcom,sm 5681 compatible = "qcom,sm8250-epss-l3", "qcom,epss-l3";
6234 reg = <0 0x18590000 0 5682 reg = <0 0x18590000 0 0x1000>;
6235 5683
6236 clocks = <&rpmhcc RPM 5684 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
6237 clock-names = "xo", " 5685 clock-names = "xo", "alternate";
6238 5686
6239 #interconnect-cells = 5687 #interconnect-cells = <1>;
6240 }; 5688 };
6241 5689
6242 cpufreq_hw: cpufreq@18591000 5690 cpufreq_hw: cpufreq@18591000 {
6243 compatible = "qcom,sm 5691 compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss";
6244 reg = <0 0x18591000 0 5692 reg = <0 0x18591000 0 0x1000>,
6245 <0 0x18592000 0 5693 <0 0x18592000 0 0x1000>,
6246 <0 0x18593000 0 5694 <0 0x18593000 0 0x1000>;
6247 reg-names = "freq-dom 5695 reg-names = "freq-domain0", "freq-domain1",
6248 "freq-dom 5696 "freq-domain2";
6249 5697
6250 clocks = <&rpmhcc RPM 5698 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
6251 clock-names = "xo", " 5699 clock-names = "xo", "alternate";
6252 interrupts = <GIC_SPI 5700 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
6253 <GIC_SPI 5701 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
6254 <GIC_SPI 5702 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
6255 interrupt-names = "dc 5703 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
6256 #freq-domain-cells = 5704 #freq-domain-cells = <1>;
6257 #clock-cells = <1>; 5705 #clock-cells = <1>;
6258 }; 5706 };
6259 }; 5707 };
6260 5708
6261 sound: sound { 5709 sound: sound {
6262 }; 5710 };
6263 5711
6264 timer { 5712 timer {
6265 compatible = "arm,armv8-timer 5713 compatible = "arm,armv8-timer";
6266 interrupts = <GIC_PPI 13 5714 interrupts = <GIC_PPI 13
6267 (GIC_CPU_MASK 5715 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6268 <GIC_PPI 14 5716 <GIC_PPI 14
6269 (GIC_CPU_MASK 5717 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6270 <GIC_PPI 11 5718 <GIC_PPI 11
6271 (GIC_CPU_MASK 5719 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6272 <GIC_PPI 10 5720 <GIC_PPI 10
6273 (GIC_CPU_MASK 5721 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
6274 }; 5722 };
6275 5723
6276 thermal-zones { 5724 thermal-zones {
6277 cpu0-thermal { 5725 cpu0-thermal {
6278 polling-delay-passive 5726 polling-delay-passive = <250>;
>> 5727 polling-delay = <1000>;
6279 5728
6280 thermal-sensors = <&t 5729 thermal-sensors = <&tsens0 1>;
6281 5730
6282 trips { 5731 trips {
6283 cpu0_alert0: 5732 cpu0_alert0: trip-point0 {
6284 tempe 5733 temperature = <90000>;
6285 hyste 5734 hysteresis = <2000>;
6286 type 5735 type = "passive";
6287 }; 5736 };
6288 5737
6289 cpu0_alert1: 5738 cpu0_alert1: trip-point1 {
6290 tempe 5739 temperature = <95000>;
6291 hyste 5740 hysteresis = <2000>;
6292 type 5741 type = "passive";
6293 }; 5742 };
6294 5743
6295 cpu0_crit: cp 5744 cpu0_crit: cpu-crit {
6296 tempe 5745 temperature = <110000>;
6297 hyste 5746 hysteresis = <1000>;
6298 type 5747 type = "critical";
6299 }; 5748 };
6300 }; 5749 };
6301 5750
6302 cooling-maps { 5751 cooling-maps {
6303 map0 { 5752 map0 {
6304 trip 5753 trip = <&cpu0_alert0>;
6305 cooli 5754 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6306 5755 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6307 5756 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6308 5757 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6309 }; 5758 };
6310 map1 { 5759 map1 {
6311 trip 5760 trip = <&cpu0_alert1>;
6312 cooli 5761 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6313 5762 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6314 5763 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6315 5764 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6316 }; 5765 };
6317 }; 5766 };
6318 }; 5767 };
6319 5768
6320 cpu1-thermal { 5769 cpu1-thermal {
6321 polling-delay-passive 5770 polling-delay-passive = <250>;
>> 5771 polling-delay = <1000>;
6322 5772
6323 thermal-sensors = <&t 5773 thermal-sensors = <&tsens0 2>;
6324 5774
6325 trips { 5775 trips {
6326 cpu1_alert0: 5776 cpu1_alert0: trip-point0 {
6327 tempe 5777 temperature = <90000>;
6328 hyste 5778 hysteresis = <2000>;
6329 type 5779 type = "passive";
6330 }; 5780 };
6331 5781
6332 cpu1_alert1: 5782 cpu1_alert1: trip-point1 {
6333 tempe 5783 temperature = <95000>;
6334 hyste 5784 hysteresis = <2000>;
6335 type 5785 type = "passive";
6336 }; 5786 };
6337 5787
6338 cpu1_crit: cp 5788 cpu1_crit: cpu-crit {
6339 tempe 5789 temperature = <110000>;
6340 hyste 5790 hysteresis = <1000>;
6341 type 5791 type = "critical";
6342 }; 5792 };
6343 }; 5793 };
6344 5794
6345 cooling-maps { 5795 cooling-maps {
6346 map0 { 5796 map0 {
6347 trip 5797 trip = <&cpu1_alert0>;
6348 cooli 5798 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6349 5799 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6350 5800 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6351 5801 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6352 }; 5802 };
6353 map1 { 5803 map1 {
6354 trip 5804 trip = <&cpu1_alert1>;
6355 cooli 5805 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6356 5806 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6357 5807 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6358 5808 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6359 }; 5809 };
6360 }; 5810 };
6361 }; 5811 };
6362 5812
6363 cpu2-thermal { 5813 cpu2-thermal {
6364 polling-delay-passive 5814 polling-delay-passive = <250>;
>> 5815 polling-delay = <1000>;
6365 5816
6366 thermal-sensors = <&t 5817 thermal-sensors = <&tsens0 3>;
6367 5818
6368 trips { 5819 trips {
6369 cpu2_alert0: 5820 cpu2_alert0: trip-point0 {
6370 tempe 5821 temperature = <90000>;
6371 hyste 5822 hysteresis = <2000>;
6372 type 5823 type = "passive";
6373 }; 5824 };
6374 5825
6375 cpu2_alert1: 5826 cpu2_alert1: trip-point1 {
6376 tempe 5827 temperature = <95000>;
6377 hyste 5828 hysteresis = <2000>;
6378 type 5829 type = "passive";
6379 }; 5830 };
6380 5831
6381 cpu2_crit: cp 5832 cpu2_crit: cpu-crit {
6382 tempe 5833 temperature = <110000>;
6383 hyste 5834 hysteresis = <1000>;
6384 type 5835 type = "critical";
6385 }; 5836 };
6386 }; 5837 };
6387 5838
6388 cooling-maps { 5839 cooling-maps {
6389 map0 { 5840 map0 {
6390 trip 5841 trip = <&cpu2_alert0>;
6391 cooli 5842 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6392 5843 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6393 5844 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6394 5845 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6395 }; 5846 };
6396 map1 { 5847 map1 {
6397 trip 5848 trip = <&cpu2_alert1>;
6398 cooli 5849 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6399 5850 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6400 5851 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6401 5852 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6402 }; 5853 };
6403 }; 5854 };
6404 }; 5855 };
6405 5856
6406 cpu3-thermal { 5857 cpu3-thermal {
6407 polling-delay-passive 5858 polling-delay-passive = <250>;
>> 5859 polling-delay = <1000>;
6408 5860
6409 thermal-sensors = <&t 5861 thermal-sensors = <&tsens0 4>;
6410 5862
6411 trips { 5863 trips {
6412 cpu3_alert0: 5864 cpu3_alert0: trip-point0 {
6413 tempe 5865 temperature = <90000>;
6414 hyste 5866 hysteresis = <2000>;
6415 type 5867 type = "passive";
6416 }; 5868 };
6417 5869
6418 cpu3_alert1: 5870 cpu3_alert1: trip-point1 {
6419 tempe 5871 temperature = <95000>;
6420 hyste 5872 hysteresis = <2000>;
6421 type 5873 type = "passive";
6422 }; 5874 };
6423 5875
6424 cpu3_crit: cp 5876 cpu3_crit: cpu-crit {
6425 tempe 5877 temperature = <110000>;
6426 hyste 5878 hysteresis = <1000>;
6427 type 5879 type = "critical";
6428 }; 5880 };
6429 }; 5881 };
6430 5882
6431 cooling-maps { 5883 cooling-maps {
6432 map0 { 5884 map0 {
6433 trip 5885 trip = <&cpu3_alert0>;
6434 cooli 5886 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6435 5887 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6436 5888 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6437 5889 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6438 }; 5890 };
6439 map1 { 5891 map1 {
6440 trip 5892 trip = <&cpu3_alert1>;
6441 cooli 5893 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6442 5894 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6443 5895 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6444 5896 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6445 }; 5897 };
6446 }; 5898 };
6447 }; 5899 };
6448 5900
6449 cpu4-top-thermal { 5901 cpu4-top-thermal {
6450 polling-delay-passive 5902 polling-delay-passive = <250>;
>> 5903 polling-delay = <1000>;
6451 5904
6452 thermal-sensors = <&t 5905 thermal-sensors = <&tsens0 7>;
6453 5906
6454 trips { 5907 trips {
6455 cpu4_top_aler 5908 cpu4_top_alert0: trip-point0 {
6456 tempe 5909 temperature = <90000>;
6457 hyste 5910 hysteresis = <2000>;
6458 type 5911 type = "passive";
6459 }; 5912 };
6460 5913
6461 cpu4_top_aler 5914 cpu4_top_alert1: trip-point1 {
6462 tempe 5915 temperature = <95000>;
6463 hyste 5916 hysteresis = <2000>;
6464 type 5917 type = "passive";
6465 }; 5918 };
6466 5919
6467 cpu4_top_crit 5920 cpu4_top_crit: cpu-crit {
6468 tempe 5921 temperature = <110000>;
6469 hyste 5922 hysteresis = <1000>;
6470 type 5923 type = "critical";
6471 }; 5924 };
6472 }; 5925 };
6473 5926
6474 cooling-maps { 5927 cooling-maps {
6475 map0 { 5928 map0 {
6476 trip 5929 trip = <&cpu4_top_alert0>;
6477 cooli 5930 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6478 5931 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6479 5932 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6480 5933 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6481 }; 5934 };
6482 map1 { 5935 map1 {
6483 trip 5936 trip = <&cpu4_top_alert1>;
6484 cooli 5937 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6485 5938 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6486 5939 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6487 5940 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6488 }; 5941 };
6489 }; 5942 };
6490 }; 5943 };
6491 5944
6492 cpu5-top-thermal { 5945 cpu5-top-thermal {
6493 polling-delay-passive 5946 polling-delay-passive = <250>;
>> 5947 polling-delay = <1000>;
6494 5948
6495 thermal-sensors = <&t 5949 thermal-sensors = <&tsens0 8>;
6496 5950
6497 trips { 5951 trips {
6498 cpu5_top_aler 5952 cpu5_top_alert0: trip-point0 {
6499 tempe 5953 temperature = <90000>;
6500 hyste 5954 hysteresis = <2000>;
6501 type 5955 type = "passive";
6502 }; 5956 };
6503 5957
6504 cpu5_top_aler 5958 cpu5_top_alert1: trip-point1 {
6505 tempe 5959 temperature = <95000>;
6506 hyste 5960 hysteresis = <2000>;
6507 type 5961 type = "passive";
6508 }; 5962 };
6509 5963
6510 cpu5_top_crit 5964 cpu5_top_crit: cpu-crit {
6511 tempe 5965 temperature = <110000>;
6512 hyste 5966 hysteresis = <1000>;
6513 type 5967 type = "critical";
6514 }; 5968 };
6515 }; 5969 };
6516 5970
6517 cooling-maps { 5971 cooling-maps {
6518 map0 { 5972 map0 {
6519 trip 5973 trip = <&cpu5_top_alert0>;
6520 cooli 5974 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6521 5975 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6522 5976 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6523 5977 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6524 }; 5978 };
6525 map1 { 5979 map1 {
6526 trip 5980 trip = <&cpu5_top_alert1>;
6527 cooli 5981 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6528 5982 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6529 5983 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6530 5984 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6531 }; 5985 };
6532 }; 5986 };
6533 }; 5987 };
6534 5988
6535 cpu6-top-thermal { 5989 cpu6-top-thermal {
6536 polling-delay-passive 5990 polling-delay-passive = <250>;
>> 5991 polling-delay = <1000>;
6537 5992
6538 thermal-sensors = <&t 5993 thermal-sensors = <&tsens0 9>;
6539 5994
6540 trips { 5995 trips {
6541 cpu6_top_aler 5996 cpu6_top_alert0: trip-point0 {
6542 tempe 5997 temperature = <90000>;
6543 hyste 5998 hysteresis = <2000>;
6544 type 5999 type = "passive";
6545 }; 6000 };
6546 6001
6547 cpu6_top_aler 6002 cpu6_top_alert1: trip-point1 {
6548 tempe 6003 temperature = <95000>;
6549 hyste 6004 hysteresis = <2000>;
6550 type 6005 type = "passive";
6551 }; 6006 };
6552 6007
6553 cpu6_top_crit 6008 cpu6_top_crit: cpu-crit {
6554 tempe 6009 temperature = <110000>;
6555 hyste 6010 hysteresis = <1000>;
6556 type 6011 type = "critical";
6557 }; 6012 };
6558 }; 6013 };
6559 6014
6560 cooling-maps { 6015 cooling-maps {
6561 map0 { 6016 map0 {
6562 trip 6017 trip = <&cpu6_top_alert0>;
6563 cooli 6018 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6564 6019 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6565 6020 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6566 6021 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6567 }; 6022 };
6568 map1 { 6023 map1 {
6569 trip 6024 trip = <&cpu6_top_alert1>;
6570 cooli 6025 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6571 6026 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6572 6027 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6573 6028 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6574 }; 6029 };
6575 }; 6030 };
6576 }; 6031 };
6577 6032
6578 cpu7-top-thermal { 6033 cpu7-top-thermal {
6579 polling-delay-passive 6034 polling-delay-passive = <250>;
>> 6035 polling-delay = <1000>;
6580 6036
6581 thermal-sensors = <&t 6037 thermal-sensors = <&tsens0 10>;
6582 6038
6583 trips { 6039 trips {
6584 cpu7_top_aler 6040 cpu7_top_alert0: trip-point0 {
6585 tempe 6041 temperature = <90000>;
6586 hyste 6042 hysteresis = <2000>;
6587 type 6043 type = "passive";
6588 }; 6044 };
6589 6045
6590 cpu7_top_aler 6046 cpu7_top_alert1: trip-point1 {
6591 tempe 6047 temperature = <95000>;
6592 hyste 6048 hysteresis = <2000>;
6593 type 6049 type = "passive";
6594 }; 6050 };
6595 6051
6596 cpu7_top_crit 6052 cpu7_top_crit: cpu-crit {
6597 tempe 6053 temperature = <110000>;
6598 hyste 6054 hysteresis = <1000>;
6599 type 6055 type = "critical";
6600 }; 6056 };
6601 }; 6057 };
6602 6058
6603 cooling-maps { 6059 cooling-maps {
6604 map0 { 6060 map0 {
6605 trip 6061 trip = <&cpu7_top_alert0>;
6606 cooli 6062 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6607 6063 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6608 6064 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6609 6065 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6610 }; 6066 };
6611 map1 { 6067 map1 {
6612 trip 6068 trip = <&cpu7_top_alert1>;
6613 cooli 6069 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6614 6070 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6615 6071 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6616 6072 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6617 }; 6073 };
6618 }; 6074 };
6619 }; 6075 };
6620 6076
6621 cpu4-bottom-thermal { 6077 cpu4-bottom-thermal {
6622 polling-delay-passive 6078 polling-delay-passive = <250>;
>> 6079 polling-delay = <1000>;
6623 6080
6624 thermal-sensors = <&t 6081 thermal-sensors = <&tsens0 11>;
6625 6082
6626 trips { 6083 trips {
6627 cpu4_bottom_a 6084 cpu4_bottom_alert0: trip-point0 {
6628 tempe 6085 temperature = <90000>;
6629 hyste 6086 hysteresis = <2000>;
6630 type 6087 type = "passive";
6631 }; 6088 };
6632 6089
6633 cpu4_bottom_a 6090 cpu4_bottom_alert1: trip-point1 {
6634 tempe 6091 temperature = <95000>;
6635 hyste 6092 hysteresis = <2000>;
6636 type 6093 type = "passive";
6637 }; 6094 };
6638 6095
6639 cpu4_bottom_c 6096 cpu4_bottom_crit: cpu-crit {
6640 tempe 6097 temperature = <110000>;
6641 hyste 6098 hysteresis = <1000>;
6642 type 6099 type = "critical";
6643 }; 6100 };
6644 }; 6101 };
6645 6102
6646 cooling-maps { 6103 cooling-maps {
6647 map0 { 6104 map0 {
6648 trip 6105 trip = <&cpu4_bottom_alert0>;
6649 cooli 6106 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6650 6107 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6651 6108 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6652 6109 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6653 }; 6110 };
6654 map1 { 6111 map1 {
6655 trip 6112 trip = <&cpu4_bottom_alert1>;
6656 cooli 6113 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6657 6114 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6658 6115 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6659 6116 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6660 }; 6117 };
6661 }; 6118 };
6662 }; 6119 };
6663 6120
6664 cpu5-bottom-thermal { 6121 cpu5-bottom-thermal {
6665 polling-delay-passive 6122 polling-delay-passive = <250>;
>> 6123 polling-delay = <1000>;
6666 6124
6667 thermal-sensors = <&t 6125 thermal-sensors = <&tsens0 12>;
6668 6126
6669 trips { 6127 trips {
6670 cpu5_bottom_a 6128 cpu5_bottom_alert0: trip-point0 {
6671 tempe 6129 temperature = <90000>;
6672 hyste 6130 hysteresis = <2000>;
6673 type 6131 type = "passive";
6674 }; 6132 };
6675 6133
6676 cpu5_bottom_a 6134 cpu5_bottom_alert1: trip-point1 {
6677 tempe 6135 temperature = <95000>;
6678 hyste 6136 hysteresis = <2000>;
6679 type 6137 type = "passive";
6680 }; 6138 };
6681 6139
6682 cpu5_bottom_c 6140 cpu5_bottom_crit: cpu-crit {
6683 tempe 6141 temperature = <110000>;
6684 hyste 6142 hysteresis = <1000>;
6685 type 6143 type = "critical";
6686 }; 6144 };
6687 }; 6145 };
6688 6146
6689 cooling-maps { 6147 cooling-maps {
6690 map0 { 6148 map0 {
6691 trip 6149 trip = <&cpu5_bottom_alert0>;
6692 cooli 6150 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6693 6151 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6694 6152 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6695 6153 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6696 }; 6154 };
6697 map1 { 6155 map1 {
6698 trip 6156 trip = <&cpu5_bottom_alert1>;
6699 cooli 6157 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6700 6158 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6701 6159 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6702 6160 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6703 }; 6161 };
6704 }; 6162 };
6705 }; 6163 };
6706 6164
6707 cpu6-bottom-thermal { 6165 cpu6-bottom-thermal {
6708 polling-delay-passive 6166 polling-delay-passive = <250>;
>> 6167 polling-delay = <1000>;
6709 6168
6710 thermal-sensors = <&t 6169 thermal-sensors = <&tsens0 13>;
6711 6170
6712 trips { 6171 trips {
6713 cpu6_bottom_a 6172 cpu6_bottom_alert0: trip-point0 {
6714 tempe 6173 temperature = <90000>;
6715 hyste 6174 hysteresis = <2000>;
6716 type 6175 type = "passive";
6717 }; 6176 };
6718 6177
6719 cpu6_bottom_a 6178 cpu6_bottom_alert1: trip-point1 {
6720 tempe 6179 temperature = <95000>;
6721 hyste 6180 hysteresis = <2000>;
6722 type 6181 type = "passive";
6723 }; 6182 };
6724 6183
6725 cpu6_bottom_c 6184 cpu6_bottom_crit: cpu-crit {
6726 tempe 6185 temperature = <110000>;
6727 hyste 6186 hysteresis = <1000>;
6728 type 6187 type = "critical";
6729 }; 6188 };
6730 }; 6189 };
6731 6190
6732 cooling-maps { 6191 cooling-maps {
6733 map0 { 6192 map0 {
6734 trip 6193 trip = <&cpu6_bottom_alert0>;
6735 cooli 6194 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6736 6195 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6737 6196 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6738 6197 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6739 }; 6198 };
6740 map1 { 6199 map1 {
6741 trip 6200 trip = <&cpu6_bottom_alert1>;
6742 cooli 6201 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6743 6202 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6744 6203 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6745 6204 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6746 }; 6205 };
6747 }; 6206 };
6748 }; 6207 };
6749 6208
6750 cpu7-bottom-thermal { 6209 cpu7-bottom-thermal {
6751 polling-delay-passive 6210 polling-delay-passive = <250>;
>> 6211 polling-delay = <1000>;
6752 6212
6753 thermal-sensors = <&t 6213 thermal-sensors = <&tsens0 14>;
6754 6214
6755 trips { 6215 trips {
6756 cpu7_bottom_a 6216 cpu7_bottom_alert0: trip-point0 {
6757 tempe 6217 temperature = <90000>;
6758 hyste 6218 hysteresis = <2000>;
6759 type 6219 type = "passive";
6760 }; 6220 };
6761 6221
6762 cpu7_bottom_a 6222 cpu7_bottom_alert1: trip-point1 {
6763 tempe 6223 temperature = <95000>;
6764 hyste 6224 hysteresis = <2000>;
6765 type 6225 type = "passive";
6766 }; 6226 };
6767 6227
6768 cpu7_bottom_c 6228 cpu7_bottom_crit: cpu-crit {
6769 tempe 6229 temperature = <110000>;
6770 hyste 6230 hysteresis = <1000>;
6771 type 6231 type = "critical";
6772 }; 6232 };
6773 }; 6233 };
6774 6234
6775 cooling-maps { 6235 cooling-maps {
6776 map0 { 6236 map0 {
6777 trip 6237 trip = <&cpu7_bottom_alert0>;
6778 cooli 6238 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6779 6239 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6780 6240 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6781 6241 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6782 }; 6242 };
6783 map1 { 6243 map1 {
6784 trip 6244 trip = <&cpu7_bottom_alert1>;
6785 cooli 6245 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6786 6246 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6787 6247 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6788 6248 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6789 }; 6249 };
6790 }; 6250 };
6791 }; 6251 };
6792 6252
6793 aoss0-thermal { 6253 aoss0-thermal {
6794 polling-delay-passive 6254 polling-delay-passive = <250>;
>> 6255 polling-delay = <1000>;
6795 6256
6796 thermal-sensors = <&t 6257 thermal-sensors = <&tsens0 0>;
6797 6258
6798 trips { 6259 trips {
6799 aoss0_alert0: 6260 aoss0_alert0: trip-point0 {
6800 tempe 6261 temperature = <90000>;
6801 hyste 6262 hysteresis = <2000>;
6802 type 6263 type = "hot";
6803 }; 6264 };
6804 }; 6265 };
6805 }; 6266 };
6806 6267
6807 cluster0-thermal { 6268 cluster0-thermal {
6808 polling-delay-passive 6269 polling-delay-passive = <250>;
>> 6270 polling-delay = <1000>;
6809 6271
6810 thermal-sensors = <&t 6272 thermal-sensors = <&tsens0 5>;
6811 6273
6812 trips { 6274 trips {
6813 cluster0_aler 6275 cluster0_alert0: trip-point0 {
6814 tempe 6276 temperature = <90000>;
6815 hyste 6277 hysteresis = <2000>;
6816 type 6278 type = "hot";
6817 }; 6279 };
6818 cluster0_crit !! 6280 cluster0_crit: cluster0_crit {
6819 tempe 6281 temperature = <110000>;
6820 hyste 6282 hysteresis = <2000>;
6821 type 6283 type = "critical";
6822 }; 6284 };
6823 }; 6285 };
6824 }; 6286 };
6825 6287
6826 cluster1-thermal { 6288 cluster1-thermal {
6827 polling-delay-passive 6289 polling-delay-passive = <250>;
>> 6290 polling-delay = <1000>;
6828 6291
6829 thermal-sensors = <&t 6292 thermal-sensors = <&tsens0 6>;
6830 6293
6831 trips { 6294 trips {
6832 cluster1_aler 6295 cluster1_alert0: trip-point0 {
6833 tempe 6296 temperature = <90000>;
6834 hyste 6297 hysteresis = <2000>;
6835 type 6298 type = "hot";
6836 }; 6299 };
6837 cluster1_crit !! 6300 cluster1_crit: cluster1_crit {
6838 tempe 6301 temperature = <110000>;
6839 hyste 6302 hysteresis = <2000>;
6840 type 6303 type = "critical";
6841 }; 6304 };
6842 }; 6305 };
6843 }; 6306 };
6844 6307
6845 gpu-top-thermal { 6308 gpu-top-thermal {
6846 polling-delay-passive 6309 polling-delay-passive = <250>;
>> 6310 polling-delay = <1000>;
6847 6311
6848 thermal-sensors = <&t 6312 thermal-sensors = <&tsens0 15>;
6849 6313
6850 cooling-maps { <<
6851 map0 { <<
6852 trip <<
6853 cooli <<
6854 }; <<
6855 }; <<
6856 <<
6857 trips { 6314 trips {
6858 gpu_top_alert !! 6315 gpu1_alert0: trip-point0 {
6859 tempe <<
6860 hyste <<
6861 type <<
6862 }; <<
6863 <<
6864 trip-point1 { <<
6865 tempe 6316 temperature = <90000>;
6866 hyste !! 6317 hysteresis = <2000>;
6867 type 6318 type = "hot";
6868 }; 6319 };
6869 <<
6870 trip-point2 { <<
6871 tempe <<
6872 hyste <<
6873 type <<
6874 }; <<
6875 }; 6320 };
6876 }; 6321 };
6877 6322
6878 aoss1-thermal { 6323 aoss1-thermal {
6879 polling-delay-passive 6324 polling-delay-passive = <250>;
>> 6325 polling-delay = <1000>;
6880 6326
6881 thermal-sensors = <&t 6327 thermal-sensors = <&tsens1 0>;
6882 6328
6883 trips { 6329 trips {
6884 aoss1_alert0: 6330 aoss1_alert0: trip-point0 {
6885 tempe 6331 temperature = <90000>;
6886 hyste 6332 hysteresis = <2000>;
6887 type 6333 type = "hot";
6888 }; 6334 };
6889 }; 6335 };
6890 }; 6336 };
6891 6337
6892 wlan-thermal { 6338 wlan-thermal {
6893 polling-delay-passive 6339 polling-delay-passive = <250>;
>> 6340 polling-delay = <1000>;
6894 6341
6895 thermal-sensors = <&t 6342 thermal-sensors = <&tsens1 1>;
6896 6343
6897 trips { 6344 trips {
6898 wlan_alert0: 6345 wlan_alert0: trip-point0 {
6899 tempe 6346 temperature = <90000>;
6900 hyste 6347 hysteresis = <2000>;
6901 type 6348 type = "hot";
6902 }; 6349 };
6903 }; 6350 };
6904 }; 6351 };
6905 6352
6906 video-thermal { 6353 video-thermal {
6907 polling-delay-passive 6354 polling-delay-passive = <250>;
>> 6355 polling-delay = <1000>;
6908 6356
6909 thermal-sensors = <&t 6357 thermal-sensors = <&tsens1 2>;
6910 6358
6911 trips { 6359 trips {
6912 video_alert0: 6360 video_alert0: trip-point0 {
6913 tempe 6361 temperature = <90000>;
6914 hyste 6362 hysteresis = <2000>;
6915 type 6363 type = "hot";
6916 }; 6364 };
6917 }; 6365 };
6918 }; 6366 };
6919 6367
6920 mem-thermal { 6368 mem-thermal {
6921 polling-delay-passive 6369 polling-delay-passive = <250>;
>> 6370 polling-delay = <1000>;
6922 6371
6923 thermal-sensors = <&t 6372 thermal-sensors = <&tsens1 3>;
6924 6373
6925 trips { 6374 trips {
6926 mem_alert0: t 6375 mem_alert0: trip-point0 {
6927 tempe 6376 temperature = <90000>;
6928 hyste 6377 hysteresis = <2000>;
6929 type 6378 type = "hot";
6930 }; 6379 };
6931 }; 6380 };
6932 }; 6381 };
6933 6382
6934 q6-hvx-thermal { 6383 q6-hvx-thermal {
6935 polling-delay-passive 6384 polling-delay-passive = <250>;
>> 6385 polling-delay = <1000>;
6936 6386
6937 thermal-sensors = <&t 6387 thermal-sensors = <&tsens1 4>;
6938 6388
6939 trips { 6389 trips {
6940 q6_hvx_alert0 6390 q6_hvx_alert0: trip-point0 {
6941 tempe 6391 temperature = <90000>;
6942 hyste 6392 hysteresis = <2000>;
6943 type 6393 type = "hot";
6944 }; 6394 };
6945 }; 6395 };
6946 }; 6396 };
6947 6397
6948 camera-thermal { 6398 camera-thermal {
6949 polling-delay-passive 6399 polling-delay-passive = <250>;
>> 6400 polling-delay = <1000>;
6950 6401
6951 thermal-sensors = <&t 6402 thermal-sensors = <&tsens1 5>;
6952 6403
6953 trips { 6404 trips {
6954 camera_alert0 6405 camera_alert0: trip-point0 {
6955 tempe 6406 temperature = <90000>;
6956 hyste 6407 hysteresis = <2000>;
6957 type 6408 type = "hot";
6958 }; 6409 };
6959 }; 6410 };
6960 }; 6411 };
6961 6412
6962 compute-thermal { 6413 compute-thermal {
6963 polling-delay-passive 6414 polling-delay-passive = <250>;
>> 6415 polling-delay = <1000>;
6964 6416
6965 thermal-sensors = <&t 6417 thermal-sensors = <&tsens1 6>;
6966 6418
6967 trips { 6419 trips {
6968 compute_alert 6420 compute_alert0: trip-point0 {
6969 tempe 6421 temperature = <90000>;
6970 hyste 6422 hysteresis = <2000>;
6971 type 6423 type = "hot";
6972 }; 6424 };
6973 }; 6425 };
6974 }; 6426 };
6975 6427
6976 npu-thermal { 6428 npu-thermal {
6977 polling-delay-passive 6429 polling-delay-passive = <250>;
>> 6430 polling-delay = <1000>;
6978 6431
6979 thermal-sensors = <&t 6432 thermal-sensors = <&tsens1 7>;
6980 6433
6981 trips { 6434 trips {
6982 npu_alert0: t 6435 npu_alert0: trip-point0 {
6983 tempe 6436 temperature = <90000>;
6984 hyste 6437 hysteresis = <2000>;
6985 type 6438 type = "hot";
6986 }; 6439 };
6987 }; 6440 };
6988 }; 6441 };
6989 6442
6990 gpu-bottom-thermal { 6443 gpu-bottom-thermal {
6991 polling-delay-passive 6444 polling-delay-passive = <250>;
>> 6445 polling-delay = <1000>;
6992 6446
6993 thermal-sensors = <&t 6447 thermal-sensors = <&tsens1 8>;
6994 6448
6995 cooling-maps { <<
6996 map0 { <<
6997 trip <<
6998 cooli <<
6999 }; <<
7000 }; <<
7001 <<
7002 trips { 6449 trips {
7003 gpu_bottom_al !! 6450 gpu2_alert0: trip-point0 {
7004 tempe <<
7005 hyste <<
7006 type <<
7007 }; <<
7008 <<
7009 trip-point1 { <<
7010 tempe 6451 temperature = <90000>;
7011 hyste !! 6452 hysteresis = <2000>;
7012 type 6453 type = "hot";
7013 }; <<
7014 <<
7015 trip-point2 { <<
7016 tempe <<
7017 hyste <<
7018 type <<
7019 }; 6454 };
7020 }; 6455 };
7021 }; 6456 };
7022 }; 6457 };
7023 }; 6458 };
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