1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * Copyright (c) 2020, The Linux Foundation. A 3 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
4 */ 4 */
5 5
6 #include <dt-bindings/interrupt-controller/arm 6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,dispcc-sm8250 7 #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
8 #include <dt-bindings/clock/qcom,gcc-sm8250.h> 8 #include <dt-bindings/clock/qcom,gcc-sm8250.h>
9 #include <dt-bindings/clock/qcom,gpucc-sm8250. 9 #include <dt-bindings/clock/qcom,gpucc-sm8250.h>
10 #include <dt-bindings/clock/qcom,rpmh.h> 10 #include <dt-bindings/clock/qcom,rpmh.h>
>> 11 #include <dt-bindings/clock/qcom,sm8250-lpass-aoncc.h>
>> 12 #include <dt-bindings/clock/qcom,sm8250-lpass-audiocc.h>
11 #include <dt-bindings/dma/qcom-gpi.h> 13 #include <dt-bindings/dma/qcom-gpi.h>
12 #include <dt-bindings/gpio/gpio.h> 14 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interconnect/qcom,osm-l3 15 #include <dt-bindings/interconnect/qcom,osm-l3.h>
14 #include <dt-bindings/interconnect/qcom,sm8250 16 #include <dt-bindings/interconnect/qcom,sm8250.h>
15 #include <dt-bindings/mailbox/qcom-ipcc.h> 17 #include <dt-bindings/mailbox/qcom-ipcc.h>
16 #include <dt-bindings/phy/phy-qcom-qmp.h> <<
17 #include <dt-bindings/power/qcom-rpmpd.h> 18 #include <dt-bindings/power/qcom-rpmpd.h>
18 #include <dt-bindings/power/qcom,rpmhpd.h> 19 #include <dt-bindings/power/qcom,rpmhpd.h>
19 #include <dt-bindings/soc/qcom,apr.h> 20 #include <dt-bindings/soc/qcom,apr.h>
20 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 21 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
21 #include <dt-bindings/sound/qcom,q6afe.h> 22 #include <dt-bindings/sound/qcom,q6afe.h>
22 #include <dt-bindings/thermal/thermal.h> 23 #include <dt-bindings/thermal/thermal.h>
23 #include <dt-bindings/clock/qcom,camcc-sm8250. 24 #include <dt-bindings/clock/qcom,camcc-sm8250.h>
24 #include <dt-bindings/clock/qcom,videocc-sm825 25 #include <dt-bindings/clock/qcom,videocc-sm8250.h>
25 26
26 / { 27 / {
27 interrupt-parent = <&intc>; 28 interrupt-parent = <&intc>;
28 29
29 #address-cells = <2>; 30 #address-cells = <2>;
30 #size-cells = <2>; 31 #size-cells = <2>;
31 32
32 aliases { 33 aliases {
33 i2c0 = &i2c0; 34 i2c0 = &i2c0;
34 i2c1 = &i2c1; 35 i2c1 = &i2c1;
35 i2c2 = &i2c2; 36 i2c2 = &i2c2;
36 i2c3 = &i2c3; 37 i2c3 = &i2c3;
37 i2c4 = &i2c4; 38 i2c4 = &i2c4;
38 i2c5 = &i2c5; 39 i2c5 = &i2c5;
39 i2c6 = &i2c6; 40 i2c6 = &i2c6;
40 i2c7 = &i2c7; 41 i2c7 = &i2c7;
41 i2c8 = &i2c8; 42 i2c8 = &i2c8;
42 i2c9 = &i2c9; 43 i2c9 = &i2c9;
43 i2c10 = &i2c10; 44 i2c10 = &i2c10;
44 i2c11 = &i2c11; 45 i2c11 = &i2c11;
45 i2c12 = &i2c12; 46 i2c12 = &i2c12;
46 i2c13 = &i2c13; 47 i2c13 = &i2c13;
47 i2c14 = &i2c14; 48 i2c14 = &i2c14;
48 i2c15 = &i2c15; 49 i2c15 = &i2c15;
49 i2c16 = &i2c16; 50 i2c16 = &i2c16;
50 i2c17 = &i2c17; 51 i2c17 = &i2c17;
51 i2c18 = &i2c18; 52 i2c18 = &i2c18;
52 i2c19 = &i2c19; 53 i2c19 = &i2c19;
53 spi0 = &spi0; 54 spi0 = &spi0;
54 spi1 = &spi1; 55 spi1 = &spi1;
55 spi2 = &spi2; 56 spi2 = &spi2;
56 spi3 = &spi3; 57 spi3 = &spi3;
57 spi4 = &spi4; 58 spi4 = &spi4;
58 spi5 = &spi5; 59 spi5 = &spi5;
59 spi6 = &spi6; 60 spi6 = &spi6;
60 spi7 = &spi7; 61 spi7 = &spi7;
61 spi8 = &spi8; 62 spi8 = &spi8;
62 spi9 = &spi9; 63 spi9 = &spi9;
63 spi10 = &spi10; 64 spi10 = &spi10;
64 spi11 = &spi11; 65 spi11 = &spi11;
65 spi12 = &spi12; 66 spi12 = &spi12;
66 spi13 = &spi13; 67 spi13 = &spi13;
67 spi14 = &spi14; 68 spi14 = &spi14;
68 spi15 = &spi15; 69 spi15 = &spi15;
69 spi16 = &spi16; 70 spi16 = &spi16;
70 spi17 = &spi17; 71 spi17 = &spi17;
71 spi18 = &spi18; 72 spi18 = &spi18;
72 spi19 = &spi19; 73 spi19 = &spi19;
73 }; 74 };
74 75
75 chosen { }; 76 chosen { };
76 77
77 clocks { 78 clocks {
78 xo_board: xo-board { 79 xo_board: xo-board {
79 compatible = "fixed-cl 80 compatible = "fixed-clock";
80 #clock-cells = <0>; 81 #clock-cells = <0>;
81 clock-frequency = <384 82 clock-frequency = <38400000>;
82 clock-output-names = " 83 clock-output-names = "xo_board";
83 }; 84 };
84 85
85 sleep_clk: sleep-clk { 86 sleep_clk: sleep-clk {
86 compatible = "fixed-cl 87 compatible = "fixed-clock";
87 clock-frequency = <327 88 clock-frequency = <32768>;
88 #clock-cells = <0>; 89 #clock-cells = <0>;
89 }; 90 };
90 }; 91 };
91 92
92 cpus { 93 cpus {
93 #address-cells = <2>; 94 #address-cells = <2>;
94 #size-cells = <0>; 95 #size-cells = <0>;
95 96
96 CPU0: cpu@0 { 97 CPU0: cpu@0 {
97 device_type = "cpu"; 98 device_type = "cpu";
98 compatible = "qcom,kry 99 compatible = "qcom,kryo485";
99 reg = <0x0 0x0>; 100 reg = <0x0 0x0>;
100 clocks = <&cpufreq_hw 101 clocks = <&cpufreq_hw 0>;
101 enable-method = "psci" 102 enable-method = "psci";
102 capacity-dmips-mhz = < 103 capacity-dmips-mhz = <448>;
103 dynamic-power-coeffici 104 dynamic-power-coefficient = <105>;
104 next-level-cache = <&L 105 next-level-cache = <&L2_0>;
105 power-domains = <&CPU_ 106 power-domains = <&CPU_PD0>;
106 power-domain-names = " 107 power-domain-names = "psci";
107 qcom,freq-domain = <&c 108 qcom,freq-domain = <&cpufreq_hw 0>;
108 operating-points-v2 = 109 operating-points-v2 = <&cpu0_opp_table>;
109 interconnects = <&gem_ 110 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
110 <&epss 111 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
111 #cooling-cells = <2>; 112 #cooling-cells = <2>;
112 L2_0: l2-cache { 113 L2_0: l2-cache {
113 compatible = " 114 compatible = "cache";
114 cache-level = 115 cache-level = <2>;
115 cache-size = < 116 cache-size = <0x20000>;
116 cache-unified; 117 cache-unified;
117 next-level-cac 118 next-level-cache = <&L3_0>;
118 L3_0: l3-cache 119 L3_0: l3-cache {
119 compat 120 compatible = "cache";
120 cache- 121 cache-level = <3>;
121 cache- 122 cache-size = <0x400000>;
122 cache- 123 cache-unified;
123 }; 124 };
124 }; 125 };
125 }; 126 };
126 127
127 CPU1: cpu@100 { 128 CPU1: cpu@100 {
128 device_type = "cpu"; 129 device_type = "cpu";
129 compatible = "qcom,kry 130 compatible = "qcom,kryo485";
130 reg = <0x0 0x100>; 131 reg = <0x0 0x100>;
131 clocks = <&cpufreq_hw 132 clocks = <&cpufreq_hw 0>;
132 enable-method = "psci" 133 enable-method = "psci";
133 capacity-dmips-mhz = < 134 capacity-dmips-mhz = <448>;
134 dynamic-power-coeffici 135 dynamic-power-coefficient = <105>;
135 next-level-cache = <&L 136 next-level-cache = <&L2_100>;
136 power-domains = <&CPU_ 137 power-domains = <&CPU_PD1>;
137 power-domain-names = " 138 power-domain-names = "psci";
138 qcom,freq-domain = <&c 139 qcom,freq-domain = <&cpufreq_hw 0>;
139 operating-points-v2 = 140 operating-points-v2 = <&cpu0_opp_table>;
140 interconnects = <&gem_ 141 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
141 <&epss 142 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
142 #cooling-cells = <2>; 143 #cooling-cells = <2>;
143 L2_100: l2-cache { 144 L2_100: l2-cache {
144 compatible = " 145 compatible = "cache";
145 cache-level = 146 cache-level = <2>;
146 cache-size = < 147 cache-size = <0x20000>;
147 cache-unified; 148 cache-unified;
148 next-level-cac 149 next-level-cache = <&L3_0>;
149 }; 150 };
150 }; 151 };
151 152
152 CPU2: cpu@200 { 153 CPU2: cpu@200 {
153 device_type = "cpu"; 154 device_type = "cpu";
154 compatible = "qcom,kry 155 compatible = "qcom,kryo485";
155 reg = <0x0 0x200>; 156 reg = <0x0 0x200>;
156 clocks = <&cpufreq_hw 157 clocks = <&cpufreq_hw 0>;
157 enable-method = "psci" 158 enable-method = "psci";
158 capacity-dmips-mhz = < 159 capacity-dmips-mhz = <448>;
159 dynamic-power-coeffici 160 dynamic-power-coefficient = <105>;
160 next-level-cache = <&L 161 next-level-cache = <&L2_200>;
161 power-domains = <&CPU_ 162 power-domains = <&CPU_PD2>;
162 power-domain-names = " 163 power-domain-names = "psci";
163 qcom,freq-domain = <&c 164 qcom,freq-domain = <&cpufreq_hw 0>;
164 operating-points-v2 = 165 operating-points-v2 = <&cpu0_opp_table>;
165 interconnects = <&gem_ 166 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
166 <&epss 167 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
167 #cooling-cells = <2>; 168 #cooling-cells = <2>;
168 L2_200: l2-cache { 169 L2_200: l2-cache {
169 compatible = " 170 compatible = "cache";
170 cache-level = 171 cache-level = <2>;
171 cache-size = < 172 cache-size = <0x20000>;
172 cache-unified; 173 cache-unified;
173 next-level-cac 174 next-level-cache = <&L3_0>;
174 }; 175 };
175 }; 176 };
176 177
177 CPU3: cpu@300 { 178 CPU3: cpu@300 {
178 device_type = "cpu"; 179 device_type = "cpu";
179 compatible = "qcom,kry 180 compatible = "qcom,kryo485";
180 reg = <0x0 0x300>; 181 reg = <0x0 0x300>;
181 clocks = <&cpufreq_hw 182 clocks = <&cpufreq_hw 0>;
182 enable-method = "psci" 183 enable-method = "psci";
183 capacity-dmips-mhz = < 184 capacity-dmips-mhz = <448>;
184 dynamic-power-coeffici 185 dynamic-power-coefficient = <105>;
185 next-level-cache = <&L 186 next-level-cache = <&L2_300>;
186 power-domains = <&CPU_ 187 power-domains = <&CPU_PD3>;
187 power-domain-names = " 188 power-domain-names = "psci";
188 qcom,freq-domain = <&c 189 qcom,freq-domain = <&cpufreq_hw 0>;
189 operating-points-v2 = 190 operating-points-v2 = <&cpu0_opp_table>;
190 interconnects = <&gem_ 191 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
191 <&epss 192 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
192 #cooling-cells = <2>; 193 #cooling-cells = <2>;
193 L2_300: l2-cache { 194 L2_300: l2-cache {
194 compatible = " 195 compatible = "cache";
195 cache-level = 196 cache-level = <2>;
196 cache-size = < 197 cache-size = <0x20000>;
197 cache-unified; 198 cache-unified;
198 next-level-cac 199 next-level-cache = <&L3_0>;
199 }; 200 };
200 }; 201 };
201 202
202 CPU4: cpu@400 { 203 CPU4: cpu@400 {
203 device_type = "cpu"; 204 device_type = "cpu";
204 compatible = "qcom,kry 205 compatible = "qcom,kryo485";
205 reg = <0x0 0x400>; 206 reg = <0x0 0x400>;
206 clocks = <&cpufreq_hw 207 clocks = <&cpufreq_hw 1>;
207 enable-method = "psci" 208 enable-method = "psci";
208 capacity-dmips-mhz = < 209 capacity-dmips-mhz = <1024>;
209 dynamic-power-coeffici 210 dynamic-power-coefficient = <379>;
210 next-level-cache = <&L 211 next-level-cache = <&L2_400>;
211 power-domains = <&CPU_ 212 power-domains = <&CPU_PD4>;
212 power-domain-names = " 213 power-domain-names = "psci";
213 qcom,freq-domain = <&c 214 qcom,freq-domain = <&cpufreq_hw 1>;
214 operating-points-v2 = 215 operating-points-v2 = <&cpu4_opp_table>;
215 interconnects = <&gem_ 216 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
216 <&epss 217 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
217 #cooling-cells = <2>; 218 #cooling-cells = <2>;
218 L2_400: l2-cache { 219 L2_400: l2-cache {
219 compatible = " 220 compatible = "cache";
220 cache-level = 221 cache-level = <2>;
221 cache-size = < 222 cache-size = <0x40000>;
222 cache-unified; 223 cache-unified;
223 next-level-cac 224 next-level-cache = <&L3_0>;
224 }; 225 };
225 }; 226 };
226 227
227 CPU5: cpu@500 { 228 CPU5: cpu@500 {
228 device_type = "cpu"; 229 device_type = "cpu";
229 compatible = "qcom,kry 230 compatible = "qcom,kryo485";
230 reg = <0x0 0x500>; 231 reg = <0x0 0x500>;
231 clocks = <&cpufreq_hw 232 clocks = <&cpufreq_hw 1>;
232 enable-method = "psci" 233 enable-method = "psci";
233 capacity-dmips-mhz = < 234 capacity-dmips-mhz = <1024>;
234 dynamic-power-coeffici 235 dynamic-power-coefficient = <379>;
235 next-level-cache = <&L 236 next-level-cache = <&L2_500>;
236 power-domains = <&CPU_ 237 power-domains = <&CPU_PD5>;
237 power-domain-names = " 238 power-domain-names = "psci";
238 qcom,freq-domain = <&c 239 qcom,freq-domain = <&cpufreq_hw 1>;
239 operating-points-v2 = 240 operating-points-v2 = <&cpu4_opp_table>;
240 interconnects = <&gem_ 241 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
241 <&epss 242 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
242 #cooling-cells = <2>; 243 #cooling-cells = <2>;
243 L2_500: l2-cache { 244 L2_500: l2-cache {
244 compatible = " 245 compatible = "cache";
245 cache-level = 246 cache-level = <2>;
246 cache-size = < 247 cache-size = <0x40000>;
247 cache-unified; 248 cache-unified;
248 next-level-cac 249 next-level-cache = <&L3_0>;
249 }; 250 };
250 }; 251 };
251 252
252 CPU6: cpu@600 { 253 CPU6: cpu@600 {
253 device_type = "cpu"; 254 device_type = "cpu";
254 compatible = "qcom,kry 255 compatible = "qcom,kryo485";
255 reg = <0x0 0x600>; 256 reg = <0x0 0x600>;
256 clocks = <&cpufreq_hw 257 clocks = <&cpufreq_hw 1>;
257 enable-method = "psci" 258 enable-method = "psci";
258 capacity-dmips-mhz = < 259 capacity-dmips-mhz = <1024>;
259 dynamic-power-coeffici 260 dynamic-power-coefficient = <379>;
260 next-level-cache = <&L 261 next-level-cache = <&L2_600>;
261 power-domains = <&CPU_ 262 power-domains = <&CPU_PD6>;
262 power-domain-names = " 263 power-domain-names = "psci";
263 qcom,freq-domain = <&c 264 qcom,freq-domain = <&cpufreq_hw 1>;
264 operating-points-v2 = 265 operating-points-v2 = <&cpu4_opp_table>;
265 interconnects = <&gem_ 266 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
266 <&epss 267 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
267 #cooling-cells = <2>; 268 #cooling-cells = <2>;
268 L2_600: l2-cache { 269 L2_600: l2-cache {
269 compatible = " 270 compatible = "cache";
270 cache-level = 271 cache-level = <2>;
271 cache-size = < 272 cache-size = <0x40000>;
272 cache-unified; 273 cache-unified;
273 next-level-cac 274 next-level-cache = <&L3_0>;
274 }; 275 };
275 }; 276 };
276 277
277 CPU7: cpu@700 { 278 CPU7: cpu@700 {
278 device_type = "cpu"; 279 device_type = "cpu";
279 compatible = "qcom,kry 280 compatible = "qcom,kryo485";
280 reg = <0x0 0x700>; 281 reg = <0x0 0x700>;
281 clocks = <&cpufreq_hw 282 clocks = <&cpufreq_hw 2>;
282 enable-method = "psci" 283 enable-method = "psci";
283 capacity-dmips-mhz = < 284 capacity-dmips-mhz = <1024>;
284 dynamic-power-coeffici 285 dynamic-power-coefficient = <444>;
285 next-level-cache = <&L 286 next-level-cache = <&L2_700>;
286 power-domains = <&CPU_ 287 power-domains = <&CPU_PD7>;
287 power-domain-names = " 288 power-domain-names = "psci";
288 qcom,freq-domain = <&c 289 qcom,freq-domain = <&cpufreq_hw 2>;
289 operating-points-v2 = 290 operating-points-v2 = <&cpu7_opp_table>;
290 interconnects = <&gem_ 291 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
291 <&epss 292 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
292 #cooling-cells = <2>; 293 #cooling-cells = <2>;
293 L2_700: l2-cache { 294 L2_700: l2-cache {
294 compatible = " 295 compatible = "cache";
295 cache-level = 296 cache-level = <2>;
296 cache-size = < 297 cache-size = <0x80000>;
297 cache-unified; 298 cache-unified;
298 next-level-cac 299 next-level-cache = <&L3_0>;
299 }; 300 };
300 }; 301 };
301 302
302 cpu-map { 303 cpu-map {
303 cluster0 { 304 cluster0 {
304 core0 { 305 core0 {
305 cpu = 306 cpu = <&CPU0>;
306 }; 307 };
307 308
308 core1 { 309 core1 {
309 cpu = 310 cpu = <&CPU1>;
310 }; 311 };
311 312
312 core2 { 313 core2 {
313 cpu = 314 cpu = <&CPU2>;
314 }; 315 };
315 316
316 core3 { 317 core3 {
317 cpu = 318 cpu = <&CPU3>;
318 }; 319 };
319 320
320 core4 { 321 core4 {
321 cpu = 322 cpu = <&CPU4>;
322 }; 323 };
323 324
324 core5 { 325 core5 {
325 cpu = 326 cpu = <&CPU5>;
326 }; 327 };
327 328
328 core6 { 329 core6 {
329 cpu = 330 cpu = <&CPU6>;
330 }; 331 };
331 332
332 core7 { 333 core7 {
333 cpu = 334 cpu = <&CPU7>;
334 }; 335 };
335 }; 336 };
336 }; 337 };
337 338
338 idle-states { 339 idle-states {
339 entry-method = "psci"; 340 entry-method = "psci";
340 341
341 LITTLE_CPU_SLEEP_0: cp 342 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
342 compatible = " 343 compatible = "arm,idle-state";
343 idle-state-nam 344 idle-state-name = "silver-rail-power-collapse";
344 arm,psci-suspe 345 arm,psci-suspend-param = <0x40000004>;
345 entry-latency- 346 entry-latency-us = <360>;
346 exit-latency-u 347 exit-latency-us = <531>;
347 min-residency- 348 min-residency-us = <3934>;
348 local-timer-st 349 local-timer-stop;
349 }; 350 };
350 351
351 BIG_CPU_SLEEP_0: cpu-s 352 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
352 compatible = " 353 compatible = "arm,idle-state";
353 idle-state-nam 354 idle-state-name = "gold-rail-power-collapse";
354 arm,psci-suspe 355 arm,psci-suspend-param = <0x40000004>;
355 entry-latency- 356 entry-latency-us = <702>;
356 exit-latency-u 357 exit-latency-us = <1061>;
357 min-residency- 358 min-residency-us = <4488>;
358 local-timer-st 359 local-timer-stop;
359 }; 360 };
360 }; 361 };
361 362
362 domain-idle-states { 363 domain-idle-states {
363 CLUSTER_SLEEP_0: clust 364 CLUSTER_SLEEP_0: cluster-sleep-0 {
364 compatible = " 365 compatible = "domain-idle-state";
365 arm,psci-suspe 366 arm,psci-suspend-param = <0x4100c244>;
366 entry-latency- 367 entry-latency-us = <3264>;
367 exit-latency-u 368 exit-latency-us = <6562>;
368 min-residency- 369 min-residency-us = <9987>;
369 }; 370 };
370 }; 371 };
371 }; 372 };
372 373
373 qup_virt: interconnect-qup-virt { <<
374 compatible = "qcom,sm8250-qup- <<
375 #interconnect-cells = <2>; <<
376 qcom,bcm-voters = <&apps_bcm_v <<
377 }; <<
378 <<
379 cpu0_opp_table: opp-table-cpu0 { 374 cpu0_opp_table: opp-table-cpu0 {
380 compatible = "operating-points 375 compatible = "operating-points-v2";
381 opp-shared; 376 opp-shared;
382 377
383 cpu0_opp1: opp-300000000 { 378 cpu0_opp1: opp-300000000 {
384 opp-hz = /bits/ 64 <30 379 opp-hz = /bits/ 64 <300000000>;
385 opp-peak-kBps = <80000 380 opp-peak-kBps = <800000 9600000>;
386 }; 381 };
387 382
388 cpu0_opp2: opp-403200000 { 383 cpu0_opp2: opp-403200000 {
389 opp-hz = /bits/ 64 <40 384 opp-hz = /bits/ 64 <403200000>;
390 opp-peak-kBps = <80000 385 opp-peak-kBps = <800000 9600000>;
391 }; 386 };
392 387
393 cpu0_opp3: opp-518400000 { 388 cpu0_opp3: opp-518400000 {
394 opp-hz = /bits/ 64 <51 389 opp-hz = /bits/ 64 <518400000>;
395 opp-peak-kBps = <80000 390 opp-peak-kBps = <800000 16588800>;
396 }; 391 };
397 392
398 cpu0_opp4: opp-614400000 { 393 cpu0_opp4: opp-614400000 {
399 opp-hz = /bits/ 64 <61 394 opp-hz = /bits/ 64 <614400000>;
400 opp-peak-kBps = <80000 395 opp-peak-kBps = <800000 16588800>;
401 }; 396 };
402 397
403 cpu0_opp5: opp-691200000 { 398 cpu0_opp5: opp-691200000 {
404 opp-hz = /bits/ 64 <69 399 opp-hz = /bits/ 64 <691200000>;
405 opp-peak-kBps = <80000 400 opp-peak-kBps = <800000 19660800>;
406 }; 401 };
407 402
408 cpu0_opp6: opp-787200000 { 403 cpu0_opp6: opp-787200000 {
409 opp-hz = /bits/ 64 <78 404 opp-hz = /bits/ 64 <787200000>;
410 opp-peak-kBps = <18040 405 opp-peak-kBps = <1804000 19660800>;
411 }; 406 };
412 407
413 cpu0_opp7: opp-883200000 { 408 cpu0_opp7: opp-883200000 {
414 opp-hz = /bits/ 64 <88 409 opp-hz = /bits/ 64 <883200000>;
415 opp-peak-kBps = <18040 410 opp-peak-kBps = <1804000 23347200>;
416 }; 411 };
417 412
418 cpu0_opp8: opp-979200000 { 413 cpu0_opp8: opp-979200000 {
419 opp-hz = /bits/ 64 <97 414 opp-hz = /bits/ 64 <979200000>;
420 opp-peak-kBps = <18040 415 opp-peak-kBps = <1804000 26419200>;
421 }; 416 };
422 417
423 cpu0_opp9: opp-1075200000 { 418 cpu0_opp9: opp-1075200000 {
424 opp-hz = /bits/ 64 <10 419 opp-hz = /bits/ 64 <1075200000>;
425 opp-peak-kBps = <18040 420 opp-peak-kBps = <1804000 29491200>;
426 }; 421 };
427 422
428 cpu0_opp10: opp-1171200000 { 423 cpu0_opp10: opp-1171200000 {
429 opp-hz = /bits/ 64 <11 424 opp-hz = /bits/ 64 <1171200000>;
430 opp-peak-kBps = <18040 425 opp-peak-kBps = <1804000 32563200>;
431 }; 426 };
432 427
433 cpu0_opp11: opp-1248000000 { 428 cpu0_opp11: opp-1248000000 {
434 opp-hz = /bits/ 64 <12 429 opp-hz = /bits/ 64 <1248000000>;
435 opp-peak-kBps = <18040 430 opp-peak-kBps = <1804000 36249600>;
436 }; 431 };
437 432
438 cpu0_opp12: opp-1344000000 { 433 cpu0_opp12: opp-1344000000 {
439 opp-hz = /bits/ 64 <13 434 opp-hz = /bits/ 64 <1344000000>;
440 opp-peak-kBps = <21880 435 opp-peak-kBps = <2188000 36249600>;
441 }; 436 };
442 437
443 cpu0_opp13: opp-1420800000 { 438 cpu0_opp13: opp-1420800000 {
444 opp-hz = /bits/ 64 <14 439 opp-hz = /bits/ 64 <1420800000>;
445 opp-peak-kBps = <21880 440 opp-peak-kBps = <2188000 39321600>;
446 }; 441 };
447 442
448 cpu0_opp14: opp-1516800000 { 443 cpu0_opp14: opp-1516800000 {
449 opp-hz = /bits/ 64 <15 444 opp-hz = /bits/ 64 <1516800000>;
450 opp-peak-kBps = <30720 445 opp-peak-kBps = <3072000 42393600>;
451 }; 446 };
452 447
453 cpu0_opp15: opp-1612800000 { 448 cpu0_opp15: opp-1612800000 {
454 opp-hz = /bits/ 64 <16 449 opp-hz = /bits/ 64 <1612800000>;
455 opp-peak-kBps = <30720 450 opp-peak-kBps = <3072000 42393600>;
456 }; 451 };
457 452
458 cpu0_opp16: opp-1708800000 { 453 cpu0_opp16: opp-1708800000 {
459 opp-hz = /bits/ 64 <17 454 opp-hz = /bits/ 64 <1708800000>;
460 opp-peak-kBps = <40680 455 opp-peak-kBps = <4068000 42393600>;
461 }; 456 };
462 457
463 cpu0_opp17: opp-1804800000 { 458 cpu0_opp17: opp-1804800000 {
464 opp-hz = /bits/ 64 <18 459 opp-hz = /bits/ 64 <1804800000>;
465 opp-peak-kBps = <40680 460 opp-peak-kBps = <4068000 42393600>;
466 }; 461 };
467 }; 462 };
468 463
469 cpu4_opp_table: opp-table-cpu4 { 464 cpu4_opp_table: opp-table-cpu4 {
470 compatible = "operating-points 465 compatible = "operating-points-v2";
471 opp-shared; 466 opp-shared;
472 467
473 cpu4_opp1: opp-710400000 { 468 cpu4_opp1: opp-710400000 {
474 opp-hz = /bits/ 64 <71 469 opp-hz = /bits/ 64 <710400000>;
475 opp-peak-kBps = <18040 470 opp-peak-kBps = <1804000 19660800>;
476 }; 471 };
477 472
478 cpu4_opp2: opp-825600000 { 473 cpu4_opp2: opp-825600000 {
479 opp-hz = /bits/ 64 <82 474 opp-hz = /bits/ 64 <825600000>;
480 opp-peak-kBps = <21880 475 opp-peak-kBps = <2188000 23347200>;
481 }; 476 };
482 477
483 cpu4_opp3: opp-940800000 { 478 cpu4_opp3: opp-940800000 {
484 opp-hz = /bits/ 64 <94 479 opp-hz = /bits/ 64 <940800000>;
485 opp-peak-kBps = <21880 480 opp-peak-kBps = <2188000 26419200>;
486 }; 481 };
487 482
488 cpu4_opp4: opp-1056000000 { 483 cpu4_opp4: opp-1056000000 {
489 opp-hz = /bits/ 64 <10 484 opp-hz = /bits/ 64 <1056000000>;
490 opp-peak-kBps = <30720 485 opp-peak-kBps = <3072000 26419200>;
491 }; 486 };
492 487
493 cpu4_opp5: opp-1171200000 { 488 cpu4_opp5: opp-1171200000 {
494 opp-hz = /bits/ 64 <11 489 opp-hz = /bits/ 64 <1171200000>;
495 opp-peak-kBps = <30720 490 opp-peak-kBps = <3072000 29491200>;
496 }; 491 };
497 492
498 cpu4_opp6: opp-1286400000 { 493 cpu4_opp6: opp-1286400000 {
499 opp-hz = /bits/ 64 <12 494 opp-hz = /bits/ 64 <1286400000>;
500 opp-peak-kBps = <40680 495 opp-peak-kBps = <4068000 29491200>;
501 }; 496 };
502 497
503 cpu4_opp7: opp-1382400000 { 498 cpu4_opp7: opp-1382400000 {
504 opp-hz = /bits/ 64 <13 499 opp-hz = /bits/ 64 <1382400000>;
505 opp-peak-kBps = <40680 500 opp-peak-kBps = <4068000 32563200>;
506 }; 501 };
507 502
508 cpu4_opp8: opp-1478400000 { 503 cpu4_opp8: opp-1478400000 {
509 opp-hz = /bits/ 64 <14 504 opp-hz = /bits/ 64 <1478400000>;
510 opp-peak-kBps = <40680 505 opp-peak-kBps = <4068000 32563200>;
511 }; 506 };
512 507
513 cpu4_opp9: opp-1574400000 { 508 cpu4_opp9: opp-1574400000 {
514 opp-hz = /bits/ 64 <15 509 opp-hz = /bits/ 64 <1574400000>;
515 opp-peak-kBps = <54120 510 opp-peak-kBps = <5412000 39321600>;
516 }; 511 };
517 512
518 cpu4_opp10: opp-1670400000 { 513 cpu4_opp10: opp-1670400000 {
519 opp-hz = /bits/ 64 <16 514 opp-hz = /bits/ 64 <1670400000>;
520 opp-peak-kBps = <54120 515 opp-peak-kBps = <5412000 42393600>;
521 }; 516 };
522 517
523 cpu4_opp11: opp-1766400000 { 518 cpu4_opp11: opp-1766400000 {
524 opp-hz = /bits/ 64 <17 519 opp-hz = /bits/ 64 <1766400000>;
525 opp-peak-kBps = <54120 520 opp-peak-kBps = <5412000 45465600>;
526 }; 521 };
527 522
528 cpu4_opp12: opp-1862400000 { 523 cpu4_opp12: opp-1862400000 {
529 opp-hz = /bits/ 64 <18 524 opp-hz = /bits/ 64 <1862400000>;
530 opp-peak-kBps = <62200 525 opp-peak-kBps = <6220000 45465600>;
531 }; 526 };
532 527
533 cpu4_opp13: opp-1958400000 { 528 cpu4_opp13: opp-1958400000 {
534 opp-hz = /bits/ 64 <19 529 opp-hz = /bits/ 64 <1958400000>;
535 opp-peak-kBps = <62200 530 opp-peak-kBps = <6220000 48537600>;
536 }; 531 };
537 532
538 cpu4_opp14: opp-2054400000 { 533 cpu4_opp14: opp-2054400000 {
539 opp-hz = /bits/ 64 <20 534 opp-hz = /bits/ 64 <2054400000>;
540 opp-peak-kBps = <72160 535 opp-peak-kBps = <7216000 48537600>;
541 }; 536 };
542 537
543 cpu4_opp15: opp-2150400000 { 538 cpu4_opp15: opp-2150400000 {
544 opp-hz = /bits/ 64 <21 539 opp-hz = /bits/ 64 <2150400000>;
545 opp-peak-kBps = <72160 540 opp-peak-kBps = <7216000 51609600>;
546 }; 541 };
547 542
548 cpu4_opp16: opp-2246400000 { 543 cpu4_opp16: opp-2246400000 {
549 opp-hz = /bits/ 64 <22 544 opp-hz = /bits/ 64 <2246400000>;
550 opp-peak-kBps = <72160 545 opp-peak-kBps = <7216000 51609600>;
551 }; 546 };
552 547
553 cpu4_opp17: opp-2342400000 { 548 cpu4_opp17: opp-2342400000 {
554 opp-hz = /bits/ 64 <23 549 opp-hz = /bits/ 64 <2342400000>;
555 opp-peak-kBps = <83680 550 opp-peak-kBps = <8368000 51609600>;
556 }; 551 };
557 552
558 cpu4_opp18: opp-2419200000 { 553 cpu4_opp18: opp-2419200000 {
559 opp-hz = /bits/ 64 <24 554 opp-hz = /bits/ 64 <2419200000>;
560 opp-peak-kBps = <83680 555 opp-peak-kBps = <8368000 51609600>;
561 }; 556 };
562 }; 557 };
563 558
564 cpu7_opp_table: opp-table-cpu7 { 559 cpu7_opp_table: opp-table-cpu7 {
565 compatible = "operating-points 560 compatible = "operating-points-v2";
566 opp-shared; 561 opp-shared;
567 562
568 cpu7_opp1: opp-844800000 { 563 cpu7_opp1: opp-844800000 {
569 opp-hz = /bits/ 64 <84 564 opp-hz = /bits/ 64 <844800000>;
570 opp-peak-kBps = <21880 565 opp-peak-kBps = <2188000 19660800>;
571 }; 566 };
572 567
573 cpu7_opp2: opp-960000000 { 568 cpu7_opp2: opp-960000000 {
574 opp-hz = /bits/ 64 <96 569 opp-hz = /bits/ 64 <960000000>;
575 opp-peak-kBps = <21880 570 opp-peak-kBps = <2188000 26419200>;
576 }; 571 };
577 572
578 cpu7_opp3: opp-1075200000 { 573 cpu7_opp3: opp-1075200000 {
579 opp-hz = /bits/ 64 <10 574 opp-hz = /bits/ 64 <1075200000>;
580 opp-peak-kBps = <30720 575 opp-peak-kBps = <3072000 26419200>;
581 }; 576 };
582 577
583 cpu7_opp4: opp-1190400000 { 578 cpu7_opp4: opp-1190400000 {
584 opp-hz = /bits/ 64 <11 579 opp-hz = /bits/ 64 <1190400000>;
585 opp-peak-kBps = <30720 580 opp-peak-kBps = <3072000 29491200>;
586 }; 581 };
587 582
588 cpu7_opp5: opp-1305600000 { 583 cpu7_opp5: opp-1305600000 {
589 opp-hz = /bits/ 64 <13 584 opp-hz = /bits/ 64 <1305600000>;
590 opp-peak-kBps = <40680 585 opp-peak-kBps = <4068000 32563200>;
591 }; 586 };
592 587
593 cpu7_opp6: opp-1401600000 { 588 cpu7_opp6: opp-1401600000 {
594 opp-hz = /bits/ 64 <14 589 opp-hz = /bits/ 64 <1401600000>;
595 opp-peak-kBps = <40680 590 opp-peak-kBps = <4068000 32563200>;
596 }; 591 };
597 592
598 cpu7_opp7: opp-1516800000 { 593 cpu7_opp7: opp-1516800000 {
599 opp-hz = /bits/ 64 <15 594 opp-hz = /bits/ 64 <1516800000>;
600 opp-peak-kBps = <40680 595 opp-peak-kBps = <4068000 36249600>;
601 }; 596 };
602 597
603 cpu7_opp8: opp-1632000000 { 598 cpu7_opp8: opp-1632000000 {
604 opp-hz = /bits/ 64 <16 599 opp-hz = /bits/ 64 <1632000000>;
605 opp-peak-kBps = <54120 600 opp-peak-kBps = <5412000 39321600>;
606 }; 601 };
607 602
608 cpu7_opp9: opp-1747200000 { 603 cpu7_opp9: opp-1747200000 {
609 opp-hz = /bits/ 64 <17 604 opp-hz = /bits/ 64 <1708800000>;
610 opp-peak-kBps = <54120 605 opp-peak-kBps = <5412000 42393600>;
611 }; 606 };
612 607
613 cpu7_opp10: opp-1862400000 { 608 cpu7_opp10: opp-1862400000 {
614 opp-hz = /bits/ 64 <18 609 opp-hz = /bits/ 64 <1862400000>;
615 opp-peak-kBps = <62200 610 opp-peak-kBps = <6220000 45465600>;
616 }; 611 };
617 612
618 cpu7_opp11: opp-1977600000 { 613 cpu7_opp11: opp-1977600000 {
619 opp-hz = /bits/ 64 <19 614 opp-hz = /bits/ 64 <1977600000>;
620 opp-peak-kBps = <62200 615 opp-peak-kBps = <6220000 48537600>;
621 }; 616 };
622 617
623 cpu7_opp12: opp-2073600000 { 618 cpu7_opp12: opp-2073600000 {
624 opp-hz = /bits/ 64 <20 619 opp-hz = /bits/ 64 <2073600000>;
625 opp-peak-kBps = <72160 620 opp-peak-kBps = <7216000 48537600>;
626 }; 621 };
627 622
628 cpu7_opp13: opp-2169600000 { 623 cpu7_opp13: opp-2169600000 {
629 opp-hz = /bits/ 64 <21 624 opp-hz = /bits/ 64 <2169600000>;
630 opp-peak-kBps = <72160 625 opp-peak-kBps = <7216000 51609600>;
631 }; 626 };
632 627
633 cpu7_opp14: opp-2265600000 { 628 cpu7_opp14: opp-2265600000 {
634 opp-hz = /bits/ 64 <22 629 opp-hz = /bits/ 64 <2265600000>;
635 opp-peak-kBps = <72160 630 opp-peak-kBps = <7216000 51609600>;
636 }; 631 };
637 632
638 cpu7_opp15: opp-2361600000 { 633 cpu7_opp15: opp-2361600000 {
639 opp-hz = /bits/ 64 <23 634 opp-hz = /bits/ 64 <2361600000>;
640 opp-peak-kBps = <83680 635 opp-peak-kBps = <8368000 51609600>;
641 }; 636 };
642 637
643 cpu7_opp16: opp-2457600000 { 638 cpu7_opp16: opp-2457600000 {
644 opp-hz = /bits/ 64 <24 639 opp-hz = /bits/ 64 <2457600000>;
645 opp-peak-kBps = <83680 640 opp-peak-kBps = <8368000 51609600>;
646 }; 641 };
647 642
648 cpu7_opp17: opp-2553600000 { 643 cpu7_opp17: opp-2553600000 {
649 opp-hz = /bits/ 64 <25 644 opp-hz = /bits/ 64 <2553600000>;
650 opp-peak-kBps = <83680 645 opp-peak-kBps = <8368000 51609600>;
651 }; 646 };
652 647
653 cpu7_opp18: opp-2649600000 { 648 cpu7_opp18: opp-2649600000 {
654 opp-hz = /bits/ 64 <26 649 opp-hz = /bits/ 64 <2649600000>;
655 opp-peak-kBps = <83680 650 opp-peak-kBps = <8368000 51609600>;
656 }; 651 };
657 652
658 cpu7_opp19: opp-2745600000 { 653 cpu7_opp19: opp-2745600000 {
659 opp-hz = /bits/ 64 <27 654 opp-hz = /bits/ 64 <2745600000>;
660 opp-peak-kBps = <83680 655 opp-peak-kBps = <8368000 51609600>;
661 }; 656 };
662 657
663 cpu7_opp20: opp-2841600000 { 658 cpu7_opp20: opp-2841600000 {
664 opp-hz = /bits/ 64 <28 659 opp-hz = /bits/ 64 <2841600000>;
665 opp-peak-kBps = <83680 660 opp-peak-kBps = <8368000 51609600>;
666 }; 661 };
667 }; 662 };
668 663
669 firmware { 664 firmware {
670 scm: scm { 665 scm: scm {
671 compatible = "qcom,scm 666 compatible = "qcom,scm-sm8250", "qcom,scm";
672 qcom,dload-mode = <&tc <<
673 #reset-cells = <1>; 667 #reset-cells = <1>;
674 }; 668 };
675 }; 669 };
676 670
677 memory@80000000 { 671 memory@80000000 {
678 device_type = "memory"; 672 device_type = "memory";
679 /* We expect the bootloader to 673 /* We expect the bootloader to fill in the size */
680 reg = <0x0 0x80000000 0x0 0x0> 674 reg = <0x0 0x80000000 0x0 0x0>;
681 }; 675 };
682 676
683 pmu { 677 pmu {
684 compatible = "arm,armv8-pmuv3" 678 compatible = "arm,armv8-pmuv3";
685 interrupts = <GIC_PPI 7 IRQ_TY 679 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
686 }; 680 };
687 681
688 psci { 682 psci {
689 compatible = "arm,psci-1.0"; 683 compatible = "arm,psci-1.0";
690 method = "smc"; 684 method = "smc";
691 685
692 CPU_PD0: power-domain-cpu0 { 686 CPU_PD0: power-domain-cpu0 {
693 #power-domain-cells = 687 #power-domain-cells = <0>;
694 power-domains = <&CLUS 688 power-domains = <&CLUSTER_PD>;
695 domain-idle-states = < 689 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
696 }; 690 };
697 691
698 CPU_PD1: power-domain-cpu1 { 692 CPU_PD1: power-domain-cpu1 {
699 #power-domain-cells = 693 #power-domain-cells = <0>;
700 power-domains = <&CLUS 694 power-domains = <&CLUSTER_PD>;
701 domain-idle-states = < 695 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
702 }; 696 };
703 697
704 CPU_PD2: power-domain-cpu2 { 698 CPU_PD2: power-domain-cpu2 {
705 #power-domain-cells = 699 #power-domain-cells = <0>;
706 power-domains = <&CLUS 700 power-domains = <&CLUSTER_PD>;
707 domain-idle-states = < 701 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
708 }; 702 };
709 703
710 CPU_PD3: power-domain-cpu3 { 704 CPU_PD3: power-domain-cpu3 {
711 #power-domain-cells = 705 #power-domain-cells = <0>;
712 power-domains = <&CLUS 706 power-domains = <&CLUSTER_PD>;
713 domain-idle-states = < 707 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
714 }; 708 };
715 709
716 CPU_PD4: power-domain-cpu4 { 710 CPU_PD4: power-domain-cpu4 {
717 #power-domain-cells = 711 #power-domain-cells = <0>;
718 power-domains = <&CLUS 712 power-domains = <&CLUSTER_PD>;
719 domain-idle-states = < 713 domain-idle-states = <&BIG_CPU_SLEEP_0>;
720 }; 714 };
721 715
722 CPU_PD5: power-domain-cpu5 { 716 CPU_PD5: power-domain-cpu5 {
723 #power-domain-cells = 717 #power-domain-cells = <0>;
724 power-domains = <&CLUS 718 power-domains = <&CLUSTER_PD>;
725 domain-idle-states = < 719 domain-idle-states = <&BIG_CPU_SLEEP_0>;
726 }; 720 };
727 721
728 CPU_PD6: power-domain-cpu6 { 722 CPU_PD6: power-domain-cpu6 {
729 #power-domain-cells = 723 #power-domain-cells = <0>;
730 power-domains = <&CLUS 724 power-domains = <&CLUSTER_PD>;
731 domain-idle-states = < 725 domain-idle-states = <&BIG_CPU_SLEEP_0>;
732 }; 726 };
733 727
734 CPU_PD7: power-domain-cpu7 { 728 CPU_PD7: power-domain-cpu7 {
735 #power-domain-cells = 729 #power-domain-cells = <0>;
736 power-domains = <&CLUS 730 power-domains = <&CLUSTER_PD>;
737 domain-idle-states = < 731 domain-idle-states = <&BIG_CPU_SLEEP_0>;
738 }; 732 };
739 733
740 CLUSTER_PD: power-domain-cpu-c 734 CLUSTER_PD: power-domain-cpu-cluster0 {
741 #power-domain-cells = 735 #power-domain-cells = <0>;
742 domain-idle-states = < 736 domain-idle-states = <&CLUSTER_SLEEP_0>;
743 }; 737 };
744 }; 738 };
745 739
746 qup_opp_table: opp-table-qup { 740 qup_opp_table: opp-table-qup {
747 compatible = "operating-points 741 compatible = "operating-points-v2";
748 742
749 opp-50000000 { 743 opp-50000000 {
750 opp-hz = /bits/ 64 <50 744 opp-hz = /bits/ 64 <50000000>;
751 required-opps = <&rpmh 745 required-opps = <&rpmhpd_opp_min_svs>;
752 }; 746 };
753 747
754 opp-75000000 { 748 opp-75000000 {
755 opp-hz = /bits/ 64 <75 749 opp-hz = /bits/ 64 <75000000>;
756 required-opps = <&rpmh 750 required-opps = <&rpmhpd_opp_low_svs>;
757 }; 751 };
758 752
759 opp-120000000 { 753 opp-120000000 {
760 opp-hz = /bits/ 64 <12 754 opp-hz = /bits/ 64 <120000000>;
761 required-opps = <&rpmh 755 required-opps = <&rpmhpd_opp_svs>;
762 }; 756 };
763 }; 757 };
764 758
765 reserved-memory { 759 reserved-memory {
766 #address-cells = <2>; 760 #address-cells = <2>;
767 #size-cells = <2>; 761 #size-cells = <2>;
768 ranges; 762 ranges;
769 763
770 hyp_mem: memory@80000000 { 764 hyp_mem: memory@80000000 {
771 reg = <0x0 0x80000000 765 reg = <0x0 0x80000000 0x0 0x600000>;
772 no-map; 766 no-map;
773 }; 767 };
774 768
775 xbl_aop_mem: memory@80700000 { 769 xbl_aop_mem: memory@80700000 {
776 reg = <0x0 0x80700000 770 reg = <0x0 0x80700000 0x0 0x160000>;
777 no-map; 771 no-map;
778 }; 772 };
779 773
780 cmd_db: memory@80860000 { 774 cmd_db: memory@80860000 {
781 compatible = "qcom,cmd 775 compatible = "qcom,cmd-db";
782 reg = <0x0 0x80860000 776 reg = <0x0 0x80860000 0x0 0x20000>;
783 no-map; 777 no-map;
784 }; 778 };
785 779
786 smem_mem: memory@80900000 { 780 smem_mem: memory@80900000 {
787 reg = <0x0 0x80900000 781 reg = <0x0 0x80900000 0x0 0x200000>;
788 no-map; 782 no-map;
789 }; 783 };
790 784
791 removed_mem: memory@80b00000 { 785 removed_mem: memory@80b00000 {
792 reg = <0x0 0x80b00000 786 reg = <0x0 0x80b00000 0x0 0x5300000>;
793 no-map; 787 no-map;
794 }; 788 };
795 789
796 camera_mem: memory@86200000 { 790 camera_mem: memory@86200000 {
797 reg = <0x0 0x86200000 791 reg = <0x0 0x86200000 0x0 0x500000>;
798 no-map; 792 no-map;
799 }; 793 };
800 794
801 wlan_mem: memory@86700000 { 795 wlan_mem: memory@86700000 {
802 reg = <0x0 0x86700000 796 reg = <0x0 0x86700000 0x0 0x100000>;
803 no-map; 797 no-map;
804 }; 798 };
805 799
806 ipa_fw_mem: memory@86800000 { 800 ipa_fw_mem: memory@86800000 {
807 reg = <0x0 0x86800000 801 reg = <0x0 0x86800000 0x0 0x10000>;
808 no-map; 802 no-map;
809 }; 803 };
810 804
811 ipa_gsi_mem: memory@86810000 { 805 ipa_gsi_mem: memory@86810000 {
812 reg = <0x0 0x86810000 806 reg = <0x0 0x86810000 0x0 0xa000>;
813 no-map; 807 no-map;
814 }; 808 };
815 809
816 gpu_mem: memory@8681a000 { 810 gpu_mem: memory@8681a000 {
817 reg = <0x0 0x8681a000 811 reg = <0x0 0x8681a000 0x0 0x2000>;
818 no-map; 812 no-map;
819 }; 813 };
820 814
821 npu_mem: memory@86900000 { 815 npu_mem: memory@86900000 {
822 reg = <0x0 0x86900000 816 reg = <0x0 0x86900000 0x0 0x500000>;
823 no-map; 817 no-map;
824 }; 818 };
825 819
826 video_mem: memory@86e00000 { 820 video_mem: memory@86e00000 {
827 reg = <0x0 0x86e00000 821 reg = <0x0 0x86e00000 0x0 0x500000>;
828 no-map; 822 no-map;
829 }; 823 };
830 824
831 cvp_mem: memory@87300000 { 825 cvp_mem: memory@87300000 {
832 reg = <0x0 0x87300000 826 reg = <0x0 0x87300000 0x0 0x500000>;
833 no-map; 827 no-map;
834 }; 828 };
835 829
836 cdsp_mem: memory@87800000 { 830 cdsp_mem: memory@87800000 {
837 reg = <0x0 0x87800000 831 reg = <0x0 0x87800000 0x0 0x1400000>;
838 no-map; 832 no-map;
839 }; 833 };
840 834
841 slpi_mem: memory@88c00000 { 835 slpi_mem: memory@88c00000 {
842 reg = <0x0 0x88c00000 836 reg = <0x0 0x88c00000 0x0 0x1500000>;
843 no-map; 837 no-map;
844 }; 838 };
845 839
846 adsp_mem: memory@8a100000 { 840 adsp_mem: memory@8a100000 {
847 reg = <0x0 0x8a100000 841 reg = <0x0 0x8a100000 0x0 0x1d00000>;
848 no-map; 842 no-map;
849 }; 843 };
850 844
851 spss_mem: memory@8be00000 { 845 spss_mem: memory@8be00000 {
852 reg = <0x0 0x8be00000 846 reg = <0x0 0x8be00000 0x0 0x100000>;
853 no-map; 847 no-map;
854 }; 848 };
855 849
856 cdsp_secure_heap: memory@8bf00 850 cdsp_secure_heap: memory@8bf00000 {
857 reg = <0x0 0x8bf00000 851 reg = <0x0 0x8bf00000 0x0 0x4600000>;
858 no-map; 852 no-map;
859 }; 853 };
860 }; 854 };
861 855
862 smem { 856 smem {
863 compatible = "qcom,smem"; 857 compatible = "qcom,smem";
864 memory-region = <&smem_mem>; 858 memory-region = <&smem_mem>;
865 hwlocks = <&tcsr_mutex 3>; 859 hwlocks = <&tcsr_mutex 3>;
866 }; 860 };
867 861
868 smp2p-adsp { 862 smp2p-adsp {
869 compatible = "qcom,smp2p"; 863 compatible = "qcom,smp2p";
870 qcom,smem = <443>, <429>; 864 qcom,smem = <443>, <429>;
871 interrupts-extended = <&ipcc I 865 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
872 I 866 IPCC_MPROC_SIGNAL_SMP2P
873 I 867 IRQ_TYPE_EDGE_RISING>;
874 mboxes = <&ipcc IPCC_CLIENT_LP 868 mboxes = <&ipcc IPCC_CLIENT_LPASS
875 IPCC_MPROC_SIG 869 IPCC_MPROC_SIGNAL_SMP2P>;
876 870
877 qcom,local-pid = <0>; 871 qcom,local-pid = <0>;
878 qcom,remote-pid = <2>; 872 qcom,remote-pid = <2>;
879 873
880 smp2p_adsp_out: master-kernel 874 smp2p_adsp_out: master-kernel {
881 qcom,entry-name = "mas 875 qcom,entry-name = "master-kernel";
882 #qcom,smem-state-cells 876 #qcom,smem-state-cells = <1>;
883 }; 877 };
884 878
885 smp2p_adsp_in: slave-kernel { 879 smp2p_adsp_in: slave-kernel {
886 qcom,entry-name = "sla 880 qcom,entry-name = "slave-kernel";
887 interrupt-controller; 881 interrupt-controller;
888 #interrupt-cells = <2> 882 #interrupt-cells = <2>;
889 }; 883 };
890 }; 884 };
891 885
892 smp2p-cdsp { 886 smp2p-cdsp {
893 compatible = "qcom,smp2p"; 887 compatible = "qcom,smp2p";
894 qcom,smem = <94>, <432>; 888 qcom,smem = <94>, <432>;
895 interrupts-extended = <&ipcc I 889 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
896 I 890 IPCC_MPROC_SIGNAL_SMP2P
897 I 891 IRQ_TYPE_EDGE_RISING>;
898 mboxes = <&ipcc IPCC_CLIENT_CD 892 mboxes = <&ipcc IPCC_CLIENT_CDSP
899 IPCC_MPROC_SIG 893 IPCC_MPROC_SIGNAL_SMP2P>;
900 894
901 qcom,local-pid = <0>; 895 qcom,local-pid = <0>;
902 qcom,remote-pid = <5>; 896 qcom,remote-pid = <5>;
903 897
904 smp2p_cdsp_out: master-kernel 898 smp2p_cdsp_out: master-kernel {
905 qcom,entry-name = "mas 899 qcom,entry-name = "master-kernel";
906 #qcom,smem-state-cells 900 #qcom,smem-state-cells = <1>;
907 }; 901 };
908 902
909 smp2p_cdsp_in: slave-kernel { 903 smp2p_cdsp_in: slave-kernel {
910 qcom,entry-name = "sla 904 qcom,entry-name = "slave-kernel";
911 interrupt-controller; 905 interrupt-controller;
912 #interrupt-cells = <2> 906 #interrupt-cells = <2>;
913 }; 907 };
914 }; 908 };
915 909
916 smp2p-slpi { 910 smp2p-slpi {
917 compatible = "qcom,smp2p"; 911 compatible = "qcom,smp2p";
918 qcom,smem = <481>, <430>; 912 qcom,smem = <481>, <430>;
919 interrupts-extended = <&ipcc I 913 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
920 I 914 IPCC_MPROC_SIGNAL_SMP2P
921 I 915 IRQ_TYPE_EDGE_RISING>;
922 mboxes = <&ipcc IPCC_CLIENT_SL 916 mboxes = <&ipcc IPCC_CLIENT_SLPI
923 IPCC_MPROC_SIG 917 IPCC_MPROC_SIGNAL_SMP2P>;
924 918
925 qcom,local-pid = <0>; 919 qcom,local-pid = <0>;
926 qcom,remote-pid = <3>; 920 qcom,remote-pid = <3>;
927 921
928 smp2p_slpi_out: master-kernel 922 smp2p_slpi_out: master-kernel {
929 qcom,entry-name = "mas 923 qcom,entry-name = "master-kernel";
930 #qcom,smem-state-cells 924 #qcom,smem-state-cells = <1>;
931 }; 925 };
932 926
933 smp2p_slpi_in: slave-kernel { 927 smp2p_slpi_in: slave-kernel {
934 qcom,entry-name = "sla 928 qcom,entry-name = "slave-kernel";
935 interrupt-controller; 929 interrupt-controller;
936 #interrupt-cells = <2> 930 #interrupt-cells = <2>;
937 }; 931 };
938 }; 932 };
939 933
940 soc: soc@0 { 934 soc: soc@0 {
941 #address-cells = <2>; 935 #address-cells = <2>;
942 #size-cells = <2>; 936 #size-cells = <2>;
943 ranges = <0 0 0 0 0x10 0>; 937 ranges = <0 0 0 0 0x10 0>;
944 dma-ranges = <0 0 0 0 0x10 0>; 938 dma-ranges = <0 0 0 0 0x10 0>;
945 compatible = "simple-bus"; 939 compatible = "simple-bus";
946 940
947 gcc: clock-controller@100000 { 941 gcc: clock-controller@100000 {
948 compatible = "qcom,gcc 942 compatible = "qcom,gcc-sm8250";
949 reg = <0x0 0x00100000 943 reg = <0x0 0x00100000 0x0 0x1f0000>;
950 #clock-cells = <1>; 944 #clock-cells = <1>;
951 #reset-cells = <1>; 945 #reset-cells = <1>;
952 #power-domain-cells = 946 #power-domain-cells = <1>;
953 clock-names = "bi_tcxo 947 clock-names = "bi_tcxo",
954 "bi_tcxo 948 "bi_tcxo_ao",
955 "sleep_c 949 "sleep_clk";
956 clocks = <&rpmhcc RPMH 950 clocks = <&rpmhcc RPMH_CXO_CLK>,
957 <&rpmhcc RPMH 951 <&rpmhcc RPMH_CXO_CLK_A>,
958 <&sleep_clk>; 952 <&sleep_clk>;
959 }; 953 };
960 954
961 ipcc: mailbox@408000 { 955 ipcc: mailbox@408000 {
962 compatible = "qcom,sm8 956 compatible = "qcom,sm8250-ipcc", "qcom,ipcc";
963 reg = <0 0x00408000 0 957 reg = <0 0x00408000 0 0x1000>;
964 interrupts = <GIC_SPI 958 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
965 interrupt-controller; 959 interrupt-controller;
966 #interrupt-cells = <3> 960 #interrupt-cells = <3>;
967 #mbox-cells = <2>; 961 #mbox-cells = <2>;
968 }; 962 };
969 963
970 qfprom: efuse@784000 { 964 qfprom: efuse@784000 {
971 compatible = "qcom,sm8 965 compatible = "qcom,sm8250-qfprom", "qcom,qfprom";
972 reg = <0 0x00784000 0 966 reg = <0 0x00784000 0 0x8ff>;
973 #address-cells = <1>; 967 #address-cells = <1>;
974 #size-cells = <1>; 968 #size-cells = <1>;
975 969
976 gpu_speed_bin: gpu-spe !! 970 gpu_speed_bin: gpu_speed_bin@19b {
977 reg = <0x19b 0 971 reg = <0x19b 0x1>;
978 bits = <5 3>; 972 bits = <5 3>;
979 }; 973 };
980 }; 974 };
981 975
982 rng: rng@793000 { 976 rng: rng@793000 {
983 compatible = "qcom,prn 977 compatible = "qcom,prng-ee";
984 reg = <0 0x00793000 0 978 reg = <0 0x00793000 0 0x1000>;
985 clocks = <&gcc GCC_PRN 979 clocks = <&gcc GCC_PRNG_AHB_CLK>;
986 clock-names = "core"; 980 clock-names = "core";
987 }; 981 };
988 982
989 gpi_dma2: dma-controller@80000 983 gpi_dma2: dma-controller@800000 {
990 compatible = "qcom,sm8 984 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma";
991 reg = <0 0x00800000 0 985 reg = <0 0x00800000 0 0x70000>;
992 interrupts = <GIC_SPI 986 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
993 <GIC_SPI 987 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
994 <GIC_SPI 988 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
995 <GIC_SPI 989 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
996 <GIC_SPI 990 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
997 <GIC_SPI 991 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
998 <GIC_SPI 992 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
999 <GIC_SPI 993 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
1000 <GIC_SPI 994 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
1001 <GIC_SPI 995 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>;
1002 dma-channels = <10>; 996 dma-channels = <10>;
1003 dma-channel-mask = <0 997 dma-channel-mask = <0x3f>;
1004 iommus = <&apps_smmu 998 iommus = <&apps_smmu 0x76 0x0>;
1005 #dma-cells = <3>; 999 #dma-cells = <3>;
1006 status = "disabled"; 1000 status = "disabled";
1007 }; 1001 };
1008 1002
1009 qupv3_id_2: geniqup@8c0000 { 1003 qupv3_id_2: geniqup@8c0000 {
1010 compatible = "qcom,ge 1004 compatible = "qcom,geni-se-qup";
1011 reg = <0x0 0x008c0000 1005 reg = <0x0 0x008c0000 0x0 0x6000>;
1012 clock-names = "m-ahb" 1006 clock-names = "m-ahb", "s-ahb";
1013 clocks = <&gcc GCC_QU 1007 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
1014 <&gcc GCC_QU 1008 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
1015 #address-cells = <2>; 1009 #address-cells = <2>;
1016 #size-cells = <2>; 1010 #size-cells = <2>;
1017 iommus = <&apps_smmu 1011 iommus = <&apps_smmu 0x63 0x0>;
1018 ranges; 1012 ranges;
1019 status = "disabled"; 1013 status = "disabled";
1020 1014
1021 i2c14: i2c@880000 { 1015 i2c14: i2c@880000 {
1022 compatible = 1016 compatible = "qcom,geni-i2c";
1023 reg = <0 0x00 1017 reg = <0 0x00880000 0 0x4000>;
1024 clock-names = 1018 clock-names = "se";
1025 clocks = <&gc 1019 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1026 pinctrl-names 1020 pinctrl-names = "default";
1027 pinctrl-0 = < 1021 pinctrl-0 = <&qup_i2c14_default>;
1028 interrupts = 1022 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1029 dmas = <&gpi_ 1023 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
1030 <&gpi_ 1024 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
1031 dma-names = " 1025 dma-names = "tx", "rx";
1032 power-domains <<
1033 interconnects <<
1034 <<
1035 <<
1036 interconnect- <<
1037 <<
1038 <<
1039 #address-cell 1026 #address-cells = <1>;
1040 #size-cells = 1027 #size-cells = <0>;
1041 status = "dis 1028 status = "disabled";
1042 }; 1029 };
1043 1030
1044 spi14: spi@880000 { 1031 spi14: spi@880000 {
1045 compatible = 1032 compatible = "qcom,geni-spi";
1046 reg = <0 0x00 1033 reg = <0 0x00880000 0 0x4000>;
1047 clock-names = 1034 clock-names = "se";
1048 clocks = <&gc 1035 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1049 interrupts = 1036 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1050 dmas = <&gpi_ 1037 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
1051 <&gpi_ 1038 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
1052 dma-names = " 1039 dma-names = "tx", "rx";
1053 power-domains 1040 power-domains = <&rpmhpd RPMHPD_CX>;
1054 operating-poi 1041 operating-points-v2 = <&qup_opp_table>;
1055 interconnects <<
1056 <<
1057 <<
1058 interconnect- <<
1059 <<
1060 <<
1061 #address-cell 1042 #address-cells = <1>;
1062 #size-cells = 1043 #size-cells = <0>;
1063 status = "dis 1044 status = "disabled";
1064 }; 1045 };
1065 1046
1066 i2c15: i2c@884000 { 1047 i2c15: i2c@884000 {
1067 compatible = 1048 compatible = "qcom,geni-i2c";
1068 reg = <0 0x00 1049 reg = <0 0x00884000 0 0x4000>;
1069 clock-names = 1050 clock-names = "se";
1070 clocks = <&gc 1051 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1071 pinctrl-names 1052 pinctrl-names = "default";
1072 pinctrl-0 = < 1053 pinctrl-0 = <&qup_i2c15_default>;
1073 interrupts = 1054 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1074 dmas = <&gpi_ 1055 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
1075 <&gpi_ 1056 <&gpi_dma2 1 1 QCOM_GPI_I2C>;
1076 dma-names = " 1057 dma-names = "tx", "rx";
1077 power-domains <<
1078 interconnects <<
1079 <<
1080 <<
1081 interconnect- <<
1082 <<
1083 <<
1084 #address-cell 1058 #address-cells = <1>;
1085 #size-cells = 1059 #size-cells = <0>;
1086 status = "dis 1060 status = "disabled";
1087 }; 1061 };
1088 1062
1089 spi15: spi@884000 { 1063 spi15: spi@884000 {
1090 compatible = 1064 compatible = "qcom,geni-spi";
1091 reg = <0 0x00 1065 reg = <0 0x00884000 0 0x4000>;
1092 clock-names = 1066 clock-names = "se";
1093 clocks = <&gc 1067 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1094 interrupts = 1068 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1095 dmas = <&gpi_ 1069 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
1096 <&gpi_ 1070 <&gpi_dma2 1 1 QCOM_GPI_SPI>;
1097 dma-names = " 1071 dma-names = "tx", "rx";
1098 power-domains 1072 power-domains = <&rpmhpd RPMHPD_CX>;
1099 operating-poi 1073 operating-points-v2 = <&qup_opp_table>;
1100 interconnects <<
1101 <<
1102 <<
1103 interconnect- <<
1104 <<
1105 <<
1106 #address-cell 1074 #address-cells = <1>;
1107 #size-cells = 1075 #size-cells = <0>;
1108 status = "dis 1076 status = "disabled";
1109 }; 1077 };
1110 1078
1111 i2c16: i2c@888000 { 1079 i2c16: i2c@888000 {
1112 compatible = 1080 compatible = "qcom,geni-i2c";
1113 reg = <0 0x00 1081 reg = <0 0x00888000 0 0x4000>;
1114 clock-names = 1082 clock-names = "se";
1115 clocks = <&gc 1083 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1116 pinctrl-names 1084 pinctrl-names = "default";
1117 pinctrl-0 = < 1085 pinctrl-0 = <&qup_i2c16_default>;
1118 interrupts = 1086 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1119 dmas = <&gpi_ 1087 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
1120 <&gpi_ 1088 <&gpi_dma2 1 2 QCOM_GPI_I2C>;
1121 dma-names = " 1089 dma-names = "tx", "rx";
1122 power-domains <<
1123 interconnects <<
1124 <<
1125 <<
1126 interconnect- <<
1127 <<
1128 <<
1129 #address-cell 1090 #address-cells = <1>;
1130 #size-cells = 1091 #size-cells = <0>;
1131 status = "dis 1092 status = "disabled";
1132 }; 1093 };
1133 1094
1134 spi16: spi@888000 { 1095 spi16: spi@888000 {
1135 compatible = 1096 compatible = "qcom,geni-spi";
1136 reg = <0 0x00 1097 reg = <0 0x00888000 0 0x4000>;
1137 clock-names = 1098 clock-names = "se";
1138 clocks = <&gc 1099 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1139 interrupts = 1100 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1140 dmas = <&gpi_ 1101 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
1141 <&gpi_ 1102 <&gpi_dma2 1 2 QCOM_GPI_SPI>;
1142 dma-names = " 1103 dma-names = "tx", "rx";
1143 power-domains 1104 power-domains = <&rpmhpd RPMHPD_CX>;
1144 operating-poi 1105 operating-points-v2 = <&qup_opp_table>;
1145 interconnects <<
1146 <<
1147 <<
1148 interconnect- <<
1149 <<
1150 <<
1151 #address-cell 1106 #address-cells = <1>;
1152 #size-cells = 1107 #size-cells = <0>;
1153 status = "dis 1108 status = "disabled";
1154 }; 1109 };
1155 1110
1156 i2c17: i2c@88c000 { 1111 i2c17: i2c@88c000 {
1157 compatible = 1112 compatible = "qcom,geni-i2c";
1158 reg = <0 0x00 1113 reg = <0 0x0088c000 0 0x4000>;
1159 clock-names = 1114 clock-names = "se";
1160 clocks = <&gc 1115 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1161 pinctrl-names 1116 pinctrl-names = "default";
1162 pinctrl-0 = < 1117 pinctrl-0 = <&qup_i2c17_default>;
1163 interrupts = 1118 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1164 dmas = <&gpi_ 1119 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
1165 <&gpi_ 1120 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
1166 dma-names = " 1121 dma-names = "tx", "rx";
1167 power-domains <<
1168 interconnects <<
1169 <<
1170 <<
1171 interconnect- <<
1172 <<
1173 <<
1174 #address-cell 1122 #address-cells = <1>;
1175 #size-cells = 1123 #size-cells = <0>;
1176 status = "dis 1124 status = "disabled";
1177 }; 1125 };
1178 1126
1179 spi17: spi@88c000 { 1127 spi17: spi@88c000 {
1180 compatible = 1128 compatible = "qcom,geni-spi";
1181 reg = <0 0x00 1129 reg = <0 0x0088c000 0 0x4000>;
1182 clock-names = 1130 clock-names = "se";
1183 clocks = <&gc 1131 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1184 interrupts = 1132 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1185 dmas = <&gpi_ 1133 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
1186 <&gpi_ 1134 <&gpi_dma2 1 3 QCOM_GPI_SPI>;
1187 dma-names = " 1135 dma-names = "tx", "rx";
1188 power-domains 1136 power-domains = <&rpmhpd RPMHPD_CX>;
1189 operating-poi 1137 operating-points-v2 = <&qup_opp_table>;
1190 interconnects <<
1191 <<
1192 <<
1193 interconnect- <<
1194 <<
1195 <<
1196 #address-cell 1138 #address-cells = <1>;
1197 #size-cells = 1139 #size-cells = <0>;
1198 status = "dis 1140 status = "disabled";
1199 }; 1141 };
1200 1142
1201 uart17: serial@88c000 1143 uart17: serial@88c000 {
1202 compatible = 1144 compatible = "qcom,geni-uart";
1203 reg = <0 0x00 1145 reg = <0 0x0088c000 0 0x4000>;
1204 clock-names = 1146 clock-names = "se";
1205 clocks = <&gc 1147 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1206 pinctrl-names 1148 pinctrl-names = "default";
1207 pinctrl-0 = < 1149 pinctrl-0 = <&qup_uart17_default>;
1208 interrupts = 1150 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1209 power-domains 1151 power-domains = <&rpmhpd RPMHPD_CX>;
1210 operating-poi 1152 operating-points-v2 = <&qup_opp_table>;
1211 interconnects <<
1212 <<
1213 interconnect- <<
1214 <<
1215 status = "dis 1153 status = "disabled";
1216 }; 1154 };
1217 1155
1218 i2c18: i2c@890000 { 1156 i2c18: i2c@890000 {
1219 compatible = 1157 compatible = "qcom,geni-i2c";
1220 reg = <0 0x00 1158 reg = <0 0x00890000 0 0x4000>;
1221 clock-names = 1159 clock-names = "se";
1222 clocks = <&gc 1160 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1223 pinctrl-names 1161 pinctrl-names = "default";
1224 pinctrl-0 = < 1162 pinctrl-0 = <&qup_i2c18_default>;
1225 interrupts = 1163 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1226 dmas = <&gpi_ 1164 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1227 <&gpi_ 1165 <&gpi_dma2 1 4 QCOM_GPI_I2C>;
1228 dma-names = " 1166 dma-names = "tx", "rx";
1229 power-domains <<
1230 interconnects <<
1231 <<
1232 <<
1233 interconnect- <<
1234 <<
1235 <<
1236 #address-cell 1167 #address-cells = <1>;
1237 #size-cells = 1168 #size-cells = <0>;
1238 status = "dis 1169 status = "disabled";
1239 }; 1170 };
1240 1171
1241 spi18: spi@890000 { 1172 spi18: spi@890000 {
1242 compatible = 1173 compatible = "qcom,geni-spi";
1243 reg = <0 0x00 1174 reg = <0 0x00890000 0 0x4000>;
1244 clock-names = 1175 clock-names = "se";
1245 clocks = <&gc 1176 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1246 interrupts = 1177 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1247 dmas = <&gpi_ 1178 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
1248 <&gpi_ 1179 <&gpi_dma2 1 4 QCOM_GPI_SPI>;
1249 dma-names = " 1180 dma-names = "tx", "rx";
1250 power-domains 1181 power-domains = <&rpmhpd RPMHPD_CX>;
1251 operating-poi 1182 operating-points-v2 = <&qup_opp_table>;
1252 interconnects <<
1253 <<
1254 <<
1255 interconnect- <<
1256 <<
1257 <<
1258 #address-cell 1183 #address-cells = <1>;
1259 #size-cells = 1184 #size-cells = <0>;
1260 status = "dis 1185 status = "disabled";
1261 }; 1186 };
1262 1187
1263 uart18: serial@890000 1188 uart18: serial@890000 {
1264 compatible = 1189 compatible = "qcom,geni-uart";
1265 reg = <0 0x00 1190 reg = <0 0x00890000 0 0x4000>;
1266 clock-names = 1191 clock-names = "se";
1267 clocks = <&gc 1192 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1268 pinctrl-names 1193 pinctrl-names = "default";
1269 pinctrl-0 = < 1194 pinctrl-0 = <&qup_uart18_default>;
1270 interrupts = 1195 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1271 power-domains 1196 power-domains = <&rpmhpd RPMHPD_CX>;
1272 operating-poi 1197 operating-points-v2 = <&qup_opp_table>;
1273 interconnects <<
1274 <<
1275 interconnect- <<
1276 <<
1277 status = "dis 1198 status = "disabled";
1278 }; 1199 };
1279 1200
1280 i2c19: i2c@894000 { 1201 i2c19: i2c@894000 {
1281 compatible = 1202 compatible = "qcom,geni-i2c";
1282 reg = <0 0x00 1203 reg = <0 0x00894000 0 0x4000>;
1283 clock-names = 1204 clock-names = "se";
1284 clocks = <&gc 1205 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1285 pinctrl-names 1206 pinctrl-names = "default";
1286 pinctrl-0 = < 1207 pinctrl-0 = <&qup_i2c19_default>;
1287 interrupts = 1208 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1288 dmas = <&gpi_ 1209 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1289 <&gpi_ 1210 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1290 dma-names = " 1211 dma-names = "tx", "rx";
1291 power-domains <<
1292 interconnects <<
1293 <<
1294 <<
1295 interconnect- <<
1296 <<
1297 <<
1298 #address-cell 1212 #address-cells = <1>;
1299 #size-cells = 1213 #size-cells = <0>;
1300 status = "dis 1214 status = "disabled";
1301 }; 1215 };
1302 1216
1303 spi19: spi@894000 { 1217 spi19: spi@894000 {
1304 compatible = 1218 compatible = "qcom,geni-spi";
1305 reg = <0 0x00 1219 reg = <0 0x00894000 0 0x4000>;
1306 clock-names = 1220 clock-names = "se";
1307 clocks = <&gc 1221 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1308 interrupts = 1222 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1309 dmas = <&gpi_ 1223 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1310 <&gpi_ 1224 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1311 dma-names = " 1225 dma-names = "tx", "rx";
1312 power-domains 1226 power-domains = <&rpmhpd RPMHPD_CX>;
1313 operating-poi 1227 operating-points-v2 = <&qup_opp_table>;
1314 interconnects <<
1315 <<
1316 <<
1317 interconnect- <<
1318 <<
1319 <<
1320 #address-cell 1228 #address-cells = <1>;
1321 #size-cells = 1229 #size-cells = <0>;
1322 status = "dis 1230 status = "disabled";
1323 }; 1231 };
1324 }; 1232 };
1325 1233
1326 gpi_dma0: dma-controller@9000 1234 gpi_dma0: dma-controller@900000 {
1327 compatible = "qcom,sm 1235 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma";
1328 reg = <0 0x00900000 0 1236 reg = <0 0x00900000 0 0x70000>;
1329 interrupts = <GIC_SPI 1237 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
1330 <GIC_SPI 1238 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
1331 <GIC_SPI 1239 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
1332 <GIC_SPI 1240 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
1333 <GIC_SPI 1241 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
1334 <GIC_SPI 1242 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
1335 <GIC_SPI 1243 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
1336 <GIC_SPI 1244 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
1337 <GIC_SPI 1245 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
1338 <GIC_SPI 1246 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
1339 <GIC_SPI 1247 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
1340 <GIC_SPI 1248 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
1341 <GIC_SPI 1249 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
1342 dma-channels = <15>; 1250 dma-channels = <15>;
1343 dma-channel-mask = <0 1251 dma-channel-mask = <0x7ff>;
1344 iommus = <&apps_smmu 1252 iommus = <&apps_smmu 0x5b6 0x0>;
1345 #dma-cells = <3>; 1253 #dma-cells = <3>;
1346 status = "disabled"; 1254 status = "disabled";
1347 }; 1255 };
1348 1256
1349 qupv3_id_0: geniqup@9c0000 { 1257 qupv3_id_0: geniqup@9c0000 {
1350 compatible = "qcom,ge 1258 compatible = "qcom,geni-se-qup";
1351 reg = <0x0 0x009c0000 1259 reg = <0x0 0x009c0000 0x0 0x6000>;
1352 clock-names = "m-ahb" 1260 clock-names = "m-ahb", "s-ahb";
1353 clocks = <&gcc GCC_QU 1261 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1354 <&gcc GCC_QU 1262 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1355 #address-cells = <2>; 1263 #address-cells = <2>;
1356 #size-cells = <2>; 1264 #size-cells = <2>;
1357 iommus = <&apps_smmu 1265 iommus = <&apps_smmu 0x5a3 0x0>;
1358 ranges; 1266 ranges;
1359 status = "disabled"; 1267 status = "disabled";
1360 1268
1361 i2c0: i2c@980000 { 1269 i2c0: i2c@980000 {
1362 compatible = 1270 compatible = "qcom,geni-i2c";
1363 reg = <0 0x00 1271 reg = <0 0x00980000 0 0x4000>;
1364 clock-names = 1272 clock-names = "se";
1365 clocks = <&gc 1273 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1366 pinctrl-names 1274 pinctrl-names = "default";
1367 pinctrl-0 = < 1275 pinctrl-0 = <&qup_i2c0_default>;
1368 interrupts = 1276 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1369 dmas = <&gpi_ 1277 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1370 <&gpi_ 1278 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1371 dma-names = " 1279 dma-names = "tx", "rx";
1372 power-domains <<
1373 interconnects <<
1374 <<
1375 <<
1376 interconnect- <<
1377 <<
1378 <<
1379 #address-cell 1280 #address-cells = <1>;
1380 #size-cells = 1281 #size-cells = <0>;
1381 status = "dis 1282 status = "disabled";
1382 }; 1283 };
1383 1284
1384 spi0: spi@980000 { 1285 spi0: spi@980000 {
1385 compatible = 1286 compatible = "qcom,geni-spi";
1386 reg = <0 0x00 1287 reg = <0 0x00980000 0 0x4000>;
1387 clock-names = 1288 clock-names = "se";
1388 clocks = <&gc 1289 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1389 interrupts = 1290 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1390 dmas = <&gpi_ 1291 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1391 <&gpi_ 1292 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1392 dma-names = " 1293 dma-names = "tx", "rx";
1393 power-domains 1294 power-domains = <&rpmhpd RPMHPD_CX>;
1394 operating-poi 1295 operating-points-v2 = <&qup_opp_table>;
1395 interconnects <<
1396 <<
1397 <<
1398 interconnect- <<
1399 <<
1400 <<
1401 #address-cell 1296 #address-cells = <1>;
1402 #size-cells = 1297 #size-cells = <0>;
1403 status = "dis 1298 status = "disabled";
1404 }; 1299 };
1405 1300
1406 i2c1: i2c@984000 { 1301 i2c1: i2c@984000 {
1407 compatible = 1302 compatible = "qcom,geni-i2c";
1408 reg = <0 0x00 1303 reg = <0 0x00984000 0 0x4000>;
1409 clock-names = 1304 clock-names = "se";
1410 clocks = <&gc 1305 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1411 pinctrl-names 1306 pinctrl-names = "default";
1412 pinctrl-0 = < 1307 pinctrl-0 = <&qup_i2c1_default>;
1413 interrupts = 1308 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1414 dmas = <&gpi_ 1309 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1415 <&gpi_ 1310 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1416 dma-names = " 1311 dma-names = "tx", "rx";
1417 power-domains <<
1418 interconnects <<
1419 <<
1420 <<
1421 interconnect- <<
1422 <<
1423 <<
1424 #address-cell 1312 #address-cells = <1>;
1425 #size-cells = 1313 #size-cells = <0>;
1426 status = "dis 1314 status = "disabled";
1427 }; 1315 };
1428 1316
1429 spi1: spi@984000 { 1317 spi1: spi@984000 {
1430 compatible = 1318 compatible = "qcom,geni-spi";
1431 reg = <0 0x00 1319 reg = <0 0x00984000 0 0x4000>;
1432 clock-names = 1320 clock-names = "se";
1433 clocks = <&gc 1321 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1434 interrupts = 1322 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1435 dmas = <&gpi_ 1323 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1436 <&gpi_ 1324 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1437 dma-names = " 1325 dma-names = "tx", "rx";
1438 power-domains 1326 power-domains = <&rpmhpd RPMHPD_CX>;
1439 operating-poi 1327 operating-points-v2 = <&qup_opp_table>;
1440 interconnects <<
1441 <<
1442 <<
1443 interconnect- <<
1444 <<
1445 <<
1446 #address-cell 1328 #address-cells = <1>;
1447 #size-cells = 1329 #size-cells = <0>;
1448 status = "dis 1330 status = "disabled";
1449 }; 1331 };
1450 1332
1451 i2c2: i2c@988000 { 1333 i2c2: i2c@988000 {
1452 compatible = 1334 compatible = "qcom,geni-i2c";
1453 reg = <0 0x00 1335 reg = <0 0x00988000 0 0x4000>;
1454 clock-names = 1336 clock-names = "se";
1455 clocks = <&gc 1337 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1456 pinctrl-names 1338 pinctrl-names = "default";
1457 pinctrl-0 = < 1339 pinctrl-0 = <&qup_i2c2_default>;
1458 interrupts = 1340 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1459 dmas = <&gpi_ 1341 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1460 <&gpi_ 1342 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1461 dma-names = " 1343 dma-names = "tx", "rx";
1462 power-domains <<
1463 interconnects <<
1464 <<
1465 <<
1466 interconnect- <<
1467 <<
1468 <<
1469 #address-cell 1344 #address-cells = <1>;
1470 #size-cells = 1345 #size-cells = <0>;
1471 status = "dis 1346 status = "disabled";
1472 }; 1347 };
1473 1348
1474 spi2: spi@988000 { 1349 spi2: spi@988000 {
1475 compatible = 1350 compatible = "qcom,geni-spi";
1476 reg = <0 0x00 1351 reg = <0 0x00988000 0 0x4000>;
1477 clock-names = 1352 clock-names = "se";
1478 clocks = <&gc 1353 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1479 interrupts = 1354 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1480 dmas = <&gpi_ 1355 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1481 <&gpi_ 1356 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1482 dma-names = " 1357 dma-names = "tx", "rx";
1483 power-domains 1358 power-domains = <&rpmhpd RPMHPD_CX>;
1484 operating-poi 1359 operating-points-v2 = <&qup_opp_table>;
1485 interconnects <<
1486 <<
1487 <<
1488 interconnect- <<
1489 <<
1490 <<
1491 #address-cell 1360 #address-cells = <1>;
1492 #size-cells = 1361 #size-cells = <0>;
1493 status = "dis 1362 status = "disabled";
1494 }; 1363 };
1495 1364
1496 uart2: serial@988000 1365 uart2: serial@988000 {
1497 compatible = 1366 compatible = "qcom,geni-debug-uart";
1498 reg = <0 0x00 1367 reg = <0 0x00988000 0 0x4000>;
1499 clock-names = 1368 clock-names = "se";
1500 clocks = <&gc 1369 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1501 pinctrl-names 1370 pinctrl-names = "default";
1502 pinctrl-0 = < 1371 pinctrl-0 = <&qup_uart2_default>;
1503 interrupts = 1372 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1504 power-domains 1373 power-domains = <&rpmhpd RPMHPD_CX>;
1505 operating-poi 1374 operating-points-v2 = <&qup_opp_table>;
1506 interconnects <<
1507 <<
1508 interconnect- <<
1509 <<
1510 status = "dis 1375 status = "disabled";
1511 }; 1376 };
1512 1377
1513 i2c3: i2c@98c000 { 1378 i2c3: i2c@98c000 {
1514 compatible = 1379 compatible = "qcom,geni-i2c";
1515 reg = <0 0x00 1380 reg = <0 0x0098c000 0 0x4000>;
1516 clock-names = 1381 clock-names = "se";
1517 clocks = <&gc 1382 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1518 pinctrl-names 1383 pinctrl-names = "default";
1519 pinctrl-0 = < 1384 pinctrl-0 = <&qup_i2c3_default>;
1520 interrupts = 1385 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1521 dmas = <&gpi_ 1386 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1522 <&gpi_ 1387 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1523 dma-names = " 1388 dma-names = "tx", "rx";
1524 power-domains <<
1525 interconnects <<
1526 <<
1527 <<
1528 interconnect- <<
1529 <<
1530 <<
1531 #address-cell 1389 #address-cells = <1>;
1532 #size-cells = 1390 #size-cells = <0>;
1533 status = "dis 1391 status = "disabled";
1534 }; 1392 };
1535 1393
1536 spi3: spi@98c000 { 1394 spi3: spi@98c000 {
1537 compatible = 1395 compatible = "qcom,geni-spi";
1538 reg = <0 0x00 1396 reg = <0 0x0098c000 0 0x4000>;
1539 clock-names = 1397 clock-names = "se";
1540 clocks = <&gc 1398 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1541 interrupts = 1399 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1542 dmas = <&gpi_ 1400 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1543 <&gpi_ 1401 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1544 dma-names = " 1402 dma-names = "tx", "rx";
1545 power-domains 1403 power-domains = <&rpmhpd RPMHPD_CX>;
1546 operating-poi 1404 operating-points-v2 = <&qup_opp_table>;
1547 interconnects <<
1548 <<
1549 <<
1550 interconnect- <<
1551 <<
1552 <<
1553 #address-cell 1405 #address-cells = <1>;
1554 #size-cells = 1406 #size-cells = <0>;
1555 status = "dis 1407 status = "disabled";
1556 }; 1408 };
1557 1409
1558 i2c4: i2c@990000 { 1410 i2c4: i2c@990000 {
1559 compatible = 1411 compatible = "qcom,geni-i2c";
1560 reg = <0 0x00 1412 reg = <0 0x00990000 0 0x4000>;
1561 clock-names = 1413 clock-names = "se";
1562 clocks = <&gc 1414 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1563 pinctrl-names 1415 pinctrl-names = "default";
1564 pinctrl-0 = < 1416 pinctrl-0 = <&qup_i2c4_default>;
1565 interrupts = 1417 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1566 dmas = <&gpi_ 1418 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1567 <&gpi_ 1419 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1568 dma-names = " 1420 dma-names = "tx", "rx";
1569 power-domains <<
1570 interconnects <<
1571 <<
1572 <<
1573 interconnect- <<
1574 <<
1575 <<
1576 #address-cell 1421 #address-cells = <1>;
1577 #size-cells = 1422 #size-cells = <0>;
1578 status = "dis 1423 status = "disabled";
1579 }; 1424 };
1580 1425
1581 spi4: spi@990000 { 1426 spi4: spi@990000 {
1582 compatible = 1427 compatible = "qcom,geni-spi";
1583 reg = <0 0x00 1428 reg = <0 0x00990000 0 0x4000>;
1584 clock-names = 1429 clock-names = "se";
1585 clocks = <&gc 1430 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1586 interrupts = 1431 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1587 dmas = <&gpi_ 1432 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1588 <&gpi_ 1433 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1589 dma-names = " 1434 dma-names = "tx", "rx";
1590 power-domains 1435 power-domains = <&rpmhpd RPMHPD_CX>;
1591 operating-poi 1436 operating-points-v2 = <&qup_opp_table>;
1592 interconnects <<
1593 <<
1594 <<
1595 interconnect- <<
1596 <<
1597 <<
1598 #address-cell 1437 #address-cells = <1>;
1599 #size-cells = 1438 #size-cells = <0>;
1600 status = "dis 1439 status = "disabled";
1601 }; 1440 };
1602 1441
1603 i2c5: i2c@994000 { 1442 i2c5: i2c@994000 {
1604 compatible = 1443 compatible = "qcom,geni-i2c";
1605 reg = <0 0x00 1444 reg = <0 0x00994000 0 0x4000>;
1606 clock-names = 1445 clock-names = "se";
1607 clocks = <&gc 1446 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1608 pinctrl-names 1447 pinctrl-names = "default";
1609 pinctrl-0 = < 1448 pinctrl-0 = <&qup_i2c5_default>;
1610 interrupts = 1449 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1611 dmas = <&gpi_ 1450 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1612 <&gpi_ 1451 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1613 dma-names = " 1452 dma-names = "tx", "rx";
1614 power-domains <<
1615 interconnects <<
1616 <<
1617 <<
1618 interconnect- <<
1619 <<
1620 <<
1621 #address-cell 1453 #address-cells = <1>;
1622 #size-cells = 1454 #size-cells = <0>;
1623 status = "dis 1455 status = "disabled";
1624 }; 1456 };
1625 1457
1626 spi5: spi@994000 { 1458 spi5: spi@994000 {
1627 compatible = 1459 compatible = "qcom,geni-spi";
1628 reg = <0 0x00 1460 reg = <0 0x00994000 0 0x4000>;
1629 clock-names = 1461 clock-names = "se";
1630 clocks = <&gc 1462 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1631 interrupts = 1463 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1632 dmas = <&gpi_ 1464 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1633 <&gpi_ 1465 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1634 dma-names = " 1466 dma-names = "tx", "rx";
1635 power-domains 1467 power-domains = <&rpmhpd RPMHPD_CX>;
1636 operating-poi 1468 operating-points-v2 = <&qup_opp_table>;
1637 interconnects <<
1638 <<
1639 <<
1640 interconnect- <<
1641 <<
1642 <<
1643 #address-cell 1469 #address-cells = <1>;
1644 #size-cells = 1470 #size-cells = <0>;
1645 status = "dis 1471 status = "disabled";
1646 }; 1472 };
1647 1473
1648 i2c6: i2c@998000 { 1474 i2c6: i2c@998000 {
1649 compatible = 1475 compatible = "qcom,geni-i2c";
1650 reg = <0 0x00 1476 reg = <0 0x00998000 0 0x4000>;
1651 clock-names = 1477 clock-names = "se";
1652 clocks = <&gc 1478 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1653 pinctrl-names 1479 pinctrl-names = "default";
1654 pinctrl-0 = < 1480 pinctrl-0 = <&qup_i2c6_default>;
1655 interrupts = 1481 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1656 dmas = <&gpi_ 1482 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1657 <&gpi_ 1483 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1658 dma-names = " 1484 dma-names = "tx", "rx";
1659 power-domains <<
1660 interconnects <<
1661 <<
1662 <<
1663 interconnect- <<
1664 <<
1665 <<
1666 #address-cell 1485 #address-cells = <1>;
1667 #size-cells = 1486 #size-cells = <0>;
1668 status = "dis 1487 status = "disabled";
1669 }; 1488 };
1670 1489
1671 spi6: spi@998000 { 1490 spi6: spi@998000 {
1672 compatible = 1491 compatible = "qcom,geni-spi";
1673 reg = <0 0x00 1492 reg = <0 0x00998000 0 0x4000>;
1674 clock-names = 1493 clock-names = "se";
1675 clocks = <&gc 1494 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1676 interrupts = 1495 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1677 dmas = <&gpi_ 1496 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1678 <&gpi_ 1497 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1679 dma-names = " 1498 dma-names = "tx", "rx";
1680 power-domains 1499 power-domains = <&rpmhpd RPMHPD_CX>;
1681 operating-poi 1500 operating-points-v2 = <&qup_opp_table>;
1682 interconnects <<
1683 <<
1684 <<
1685 interconnect- <<
1686 <<
1687 <<
1688 #address-cell 1501 #address-cells = <1>;
1689 #size-cells = 1502 #size-cells = <0>;
1690 status = "dis 1503 status = "disabled";
1691 }; 1504 };
1692 1505
1693 uart6: serial@998000 1506 uart6: serial@998000 {
1694 compatible = 1507 compatible = "qcom,geni-uart";
1695 reg = <0 0x00 1508 reg = <0 0x00998000 0 0x4000>;
1696 clock-names = 1509 clock-names = "se";
1697 clocks = <&gc 1510 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1698 pinctrl-names 1511 pinctrl-names = "default";
1699 pinctrl-0 = < 1512 pinctrl-0 = <&qup_uart6_default>;
1700 interrupts = 1513 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1701 power-domains 1514 power-domains = <&rpmhpd RPMHPD_CX>;
1702 operating-poi 1515 operating-points-v2 = <&qup_opp_table>;
1703 interconnects <<
1704 <<
1705 interconnect- <<
1706 <<
1707 status = "dis 1516 status = "disabled";
1708 }; 1517 };
1709 1518
1710 i2c7: i2c@99c000 { 1519 i2c7: i2c@99c000 {
1711 compatible = 1520 compatible = "qcom,geni-i2c";
1712 reg = <0 0x00 1521 reg = <0 0x0099c000 0 0x4000>;
1713 clock-names = 1522 clock-names = "se";
1714 clocks = <&gc 1523 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1715 pinctrl-names 1524 pinctrl-names = "default";
1716 pinctrl-0 = < 1525 pinctrl-0 = <&qup_i2c7_default>;
1717 interrupts = 1526 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1718 dmas = <&gpi_ 1527 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1719 <&gpi_ 1528 <&gpi_dma0 1 7 QCOM_GPI_I2C>;
1720 dma-names = " 1529 dma-names = "tx", "rx";
1721 power-domains <<
1722 interconnects <<
1723 <<
1724 <<
1725 interconnect- <<
1726 <<
1727 <<
1728 #address-cell 1530 #address-cells = <1>;
1729 #size-cells = 1531 #size-cells = <0>;
1730 status = "dis 1532 status = "disabled";
1731 }; 1533 };
1732 1534
1733 spi7: spi@99c000 { 1535 spi7: spi@99c000 {
1734 compatible = 1536 compatible = "qcom,geni-spi";
1735 reg = <0 0x00 1537 reg = <0 0x0099c000 0 0x4000>;
1736 clock-names = 1538 clock-names = "se";
1737 clocks = <&gc 1539 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1738 interrupts = 1540 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1739 dmas = <&gpi_ 1541 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1740 <&gpi_ 1542 <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1741 dma-names = " 1543 dma-names = "tx", "rx";
1742 power-domains 1544 power-domains = <&rpmhpd RPMHPD_CX>;
1743 operating-poi 1545 operating-points-v2 = <&qup_opp_table>;
1744 interconnects <<
1745 <<
1746 <<
1747 interconnect- <<
1748 <<
1749 <<
1750 #address-cell 1546 #address-cells = <1>;
1751 #size-cells = 1547 #size-cells = <0>;
1752 status = "dis 1548 status = "disabled";
1753 }; 1549 };
1754 }; 1550 };
1755 1551
1756 gpi_dma1: dma-controller@a000 1552 gpi_dma1: dma-controller@a00000 {
1757 compatible = "qcom,sm 1553 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma";
1758 reg = <0 0x00a00000 0 1554 reg = <0 0x00a00000 0 0x70000>;
1759 interrupts = <GIC_SPI 1555 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1760 <GIC_SPI 1556 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1761 <GIC_SPI 1557 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1762 <GIC_SPI 1558 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1763 <GIC_SPI 1559 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1764 <GIC_SPI 1560 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1765 <GIC_SPI 1561 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1766 <GIC_SPI 1562 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1767 <GIC_SPI 1563 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1768 <GIC_SPI 1564 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>;
1769 dma-channels = <10>; 1565 dma-channels = <10>;
1770 dma-channel-mask = <0 1566 dma-channel-mask = <0x3f>;
1771 iommus = <&apps_smmu 1567 iommus = <&apps_smmu 0x56 0x0>;
1772 #dma-cells = <3>; 1568 #dma-cells = <3>;
1773 status = "disabled"; 1569 status = "disabled";
1774 }; 1570 };
1775 1571
1776 qupv3_id_1: geniqup@ac0000 { 1572 qupv3_id_1: geniqup@ac0000 {
1777 compatible = "qcom,ge 1573 compatible = "qcom,geni-se-qup";
1778 reg = <0x0 0x00ac0000 1574 reg = <0x0 0x00ac0000 0x0 0x6000>;
1779 clock-names = "m-ahb" 1575 clock-names = "m-ahb", "s-ahb";
1780 clocks = <&gcc GCC_QU 1576 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1781 <&gcc GCC_QU 1577 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1782 #address-cells = <2>; 1578 #address-cells = <2>;
1783 #size-cells = <2>; 1579 #size-cells = <2>;
1784 iommus = <&apps_smmu 1580 iommus = <&apps_smmu 0x43 0x0>;
1785 ranges; 1581 ranges;
1786 status = "disabled"; 1582 status = "disabled";
1787 1583
1788 i2c8: i2c@a80000 { 1584 i2c8: i2c@a80000 {
1789 compatible = 1585 compatible = "qcom,geni-i2c";
1790 reg = <0 0x00 1586 reg = <0 0x00a80000 0 0x4000>;
1791 clock-names = 1587 clock-names = "se";
1792 clocks = <&gc 1588 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1793 pinctrl-names 1589 pinctrl-names = "default";
1794 pinctrl-0 = < 1590 pinctrl-0 = <&qup_i2c8_default>;
1795 interrupts = 1591 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1796 dmas = <&gpi_ 1592 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1797 <&gpi_ 1593 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1798 dma-names = " 1594 dma-names = "tx", "rx";
1799 power-domains <<
1800 interconnects <<
1801 <<
1802 <<
1803 interconnect- <<
1804 <<
1805 <<
1806 #address-cell 1595 #address-cells = <1>;
1807 #size-cells = 1596 #size-cells = <0>;
1808 status = "dis 1597 status = "disabled";
1809 }; 1598 };
1810 1599
1811 spi8: spi@a80000 { 1600 spi8: spi@a80000 {
1812 compatible = 1601 compatible = "qcom,geni-spi";
1813 reg = <0 0x00 1602 reg = <0 0x00a80000 0 0x4000>;
1814 clock-names = 1603 clock-names = "se";
1815 clocks = <&gc 1604 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1816 interrupts = 1605 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1817 dmas = <&gpi_ 1606 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1818 <&gpi_ 1607 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1819 dma-names = " 1608 dma-names = "tx", "rx";
1820 power-domains 1609 power-domains = <&rpmhpd RPMHPD_CX>;
1821 operating-poi 1610 operating-points-v2 = <&qup_opp_table>;
1822 interconnects <<
1823 <<
1824 <<
1825 interconnect- <<
1826 <<
1827 <<
1828 #address-cell 1611 #address-cells = <1>;
1829 #size-cells = 1612 #size-cells = <0>;
1830 status = "dis 1613 status = "disabled";
1831 }; 1614 };
1832 1615
1833 i2c9: i2c@a84000 { 1616 i2c9: i2c@a84000 {
1834 compatible = 1617 compatible = "qcom,geni-i2c";
1835 reg = <0 0x00 1618 reg = <0 0x00a84000 0 0x4000>;
1836 clock-names = 1619 clock-names = "se";
1837 clocks = <&gc 1620 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1838 pinctrl-names 1621 pinctrl-names = "default";
1839 pinctrl-0 = < 1622 pinctrl-0 = <&qup_i2c9_default>;
1840 interrupts = 1623 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1841 dmas = <&gpi_ 1624 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1842 <&gpi_ 1625 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1843 dma-names = " 1626 dma-names = "tx", "rx";
1844 power-domains <<
1845 interconnects <<
1846 <<
1847 <<
1848 interconnect- <<
1849 <<
1850 <<
1851 #address-cell 1627 #address-cells = <1>;
1852 #size-cells = 1628 #size-cells = <0>;
1853 status = "dis 1629 status = "disabled";
1854 }; 1630 };
1855 1631
1856 spi9: spi@a84000 { 1632 spi9: spi@a84000 {
1857 compatible = 1633 compatible = "qcom,geni-spi";
1858 reg = <0 0x00 1634 reg = <0 0x00a84000 0 0x4000>;
1859 clock-names = 1635 clock-names = "se";
1860 clocks = <&gc 1636 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1861 interrupts = 1637 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1862 dmas = <&gpi_ 1638 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1863 <&gpi_ 1639 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1864 dma-names = " 1640 dma-names = "tx", "rx";
1865 power-domains 1641 power-domains = <&rpmhpd RPMHPD_CX>;
1866 operating-poi 1642 operating-points-v2 = <&qup_opp_table>;
1867 interconnects <<
1868 <<
1869 <<
1870 interconnect- <<
1871 <<
1872 <<
1873 #address-cell 1643 #address-cells = <1>;
1874 #size-cells = 1644 #size-cells = <0>;
1875 status = "dis 1645 status = "disabled";
1876 }; 1646 };
1877 1647
1878 i2c10: i2c@a88000 { 1648 i2c10: i2c@a88000 {
1879 compatible = 1649 compatible = "qcom,geni-i2c";
1880 reg = <0 0x00 1650 reg = <0 0x00a88000 0 0x4000>;
1881 clock-names = 1651 clock-names = "se";
1882 clocks = <&gc 1652 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1883 pinctrl-names 1653 pinctrl-names = "default";
1884 pinctrl-0 = < 1654 pinctrl-0 = <&qup_i2c10_default>;
1885 interrupts = 1655 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1886 dmas = <&gpi_ 1656 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1887 <&gpi_ 1657 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1888 dma-names = " 1658 dma-names = "tx", "rx";
1889 power-domains <<
1890 interconnects <<
1891 <<
1892 <<
1893 interconnect- <<
1894 <<
1895 <<
1896 #address-cell 1659 #address-cells = <1>;
1897 #size-cells = 1660 #size-cells = <0>;
1898 status = "dis 1661 status = "disabled";
1899 }; 1662 };
1900 1663
1901 spi10: spi@a88000 { 1664 spi10: spi@a88000 {
1902 compatible = 1665 compatible = "qcom,geni-spi";
1903 reg = <0 0x00 1666 reg = <0 0x00a88000 0 0x4000>;
1904 clock-names = 1667 clock-names = "se";
1905 clocks = <&gc 1668 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1906 interrupts = 1669 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1907 dmas = <&gpi_ 1670 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1908 <&gpi_ 1671 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1909 dma-names = " 1672 dma-names = "tx", "rx";
1910 power-domains 1673 power-domains = <&rpmhpd RPMHPD_CX>;
1911 operating-poi 1674 operating-points-v2 = <&qup_opp_table>;
1912 interconnects <<
1913 <<
1914 <<
1915 interconnect- <<
1916 <<
1917 <<
1918 #address-cell 1675 #address-cells = <1>;
1919 #size-cells = 1676 #size-cells = <0>;
1920 status = "dis 1677 status = "disabled";
1921 }; 1678 };
1922 1679
1923 i2c11: i2c@a8c000 { 1680 i2c11: i2c@a8c000 {
1924 compatible = 1681 compatible = "qcom,geni-i2c";
1925 reg = <0 0x00 1682 reg = <0 0x00a8c000 0 0x4000>;
1926 clock-names = 1683 clock-names = "se";
1927 clocks = <&gc 1684 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1928 pinctrl-names 1685 pinctrl-names = "default";
1929 pinctrl-0 = < 1686 pinctrl-0 = <&qup_i2c11_default>;
1930 interrupts = 1687 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1931 dmas = <&gpi_ 1688 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1932 <&gpi_ 1689 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1933 dma-names = " 1690 dma-names = "tx", "rx";
1934 power-domains <<
1935 interconnects <<
1936 <<
1937 <<
1938 interconnect- <<
1939 <<
1940 <<
1941 #address-cell 1691 #address-cells = <1>;
1942 #size-cells = 1692 #size-cells = <0>;
1943 status = "dis 1693 status = "disabled";
1944 }; 1694 };
1945 1695
1946 spi11: spi@a8c000 { 1696 spi11: spi@a8c000 {
1947 compatible = 1697 compatible = "qcom,geni-spi";
1948 reg = <0 0x00 1698 reg = <0 0x00a8c000 0 0x4000>;
1949 clock-names = 1699 clock-names = "se";
1950 clocks = <&gc 1700 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1951 interrupts = 1701 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1952 dmas = <&gpi_ 1702 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1953 <&gpi_ 1703 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1954 dma-names = " 1704 dma-names = "tx", "rx";
1955 power-domains 1705 power-domains = <&rpmhpd RPMHPD_CX>;
1956 operating-poi 1706 operating-points-v2 = <&qup_opp_table>;
1957 interconnects <<
1958 <<
1959 <<
1960 interconnect- <<
1961 <<
1962 <<
1963 #address-cell 1707 #address-cells = <1>;
1964 #size-cells = 1708 #size-cells = <0>;
1965 status = "dis 1709 status = "disabled";
1966 }; 1710 };
1967 1711
1968 i2c12: i2c@a90000 { 1712 i2c12: i2c@a90000 {
1969 compatible = 1713 compatible = "qcom,geni-i2c";
1970 reg = <0 0x00 1714 reg = <0 0x00a90000 0 0x4000>;
1971 clock-names = 1715 clock-names = "se";
1972 clocks = <&gc 1716 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1973 pinctrl-names 1717 pinctrl-names = "default";
1974 pinctrl-0 = < 1718 pinctrl-0 = <&qup_i2c12_default>;
1975 interrupts = 1719 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1976 dmas = <&gpi_ 1720 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1977 <&gpi_ 1721 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1978 dma-names = " 1722 dma-names = "tx", "rx";
1979 power-domains <<
1980 interconnects <<
1981 <<
1982 <<
1983 interconnect- <<
1984 <<
1985 <<
1986 #address-cell 1723 #address-cells = <1>;
1987 #size-cells = 1724 #size-cells = <0>;
1988 status = "dis 1725 status = "disabled";
1989 }; 1726 };
1990 1727
1991 spi12: spi@a90000 { 1728 spi12: spi@a90000 {
1992 compatible = 1729 compatible = "qcom,geni-spi";
1993 reg = <0 0x00 1730 reg = <0 0x00a90000 0 0x4000>;
1994 clock-names = 1731 clock-names = "se";
1995 clocks = <&gc 1732 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1996 interrupts = 1733 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1997 dmas = <&gpi_ 1734 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1998 <&gpi_ 1735 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1999 dma-names = " 1736 dma-names = "tx", "rx";
2000 power-domains 1737 power-domains = <&rpmhpd RPMHPD_CX>;
2001 operating-poi 1738 operating-points-v2 = <&qup_opp_table>;
2002 interconnects <<
2003 <<
2004 <<
2005 interconnect- <<
2006 <<
2007 <<
2008 #address-cell 1739 #address-cells = <1>;
2009 #size-cells = 1740 #size-cells = <0>;
2010 status = "dis 1741 status = "disabled";
2011 }; 1742 };
2012 1743
2013 uart12: serial@a90000 1744 uart12: serial@a90000 {
2014 compatible = 1745 compatible = "qcom,geni-debug-uart";
2015 reg = <0x0 0x 1746 reg = <0x0 0x00a90000 0x0 0x4000>;
2016 clock-names = 1747 clock-names = "se";
2017 clocks = <&gc 1748 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
2018 pinctrl-names 1749 pinctrl-names = "default";
2019 pinctrl-0 = < 1750 pinctrl-0 = <&qup_uart12_default>;
2020 interrupts = 1751 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
2021 power-domains 1752 power-domains = <&rpmhpd RPMHPD_CX>;
2022 operating-poi 1753 operating-points-v2 = <&qup_opp_table>;
2023 interconnects <<
2024 <<
2025 interconnect- <<
2026 <<
2027 status = "dis 1754 status = "disabled";
2028 }; 1755 };
2029 1756
2030 i2c13: i2c@a94000 { 1757 i2c13: i2c@a94000 {
2031 compatible = 1758 compatible = "qcom,geni-i2c";
2032 reg = <0 0x00 1759 reg = <0 0x00a94000 0 0x4000>;
2033 clock-names = 1760 clock-names = "se";
2034 clocks = <&gc 1761 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2035 pinctrl-names 1762 pinctrl-names = "default";
2036 pinctrl-0 = < 1763 pinctrl-0 = <&qup_i2c13_default>;
2037 interrupts = 1764 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2038 dmas = <&gpi_ 1765 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
2039 <&gpi_ 1766 <&gpi_dma1 1 5 QCOM_GPI_I2C>;
2040 dma-names = " 1767 dma-names = "tx", "rx";
2041 power-domains <<
2042 interconnects <<
2043 <<
2044 <<
2045 interconnect- <<
2046 <<
2047 <<
2048 #address-cell 1768 #address-cells = <1>;
2049 #size-cells = 1769 #size-cells = <0>;
2050 status = "dis 1770 status = "disabled";
2051 }; 1771 };
2052 1772
2053 spi13: spi@a94000 { 1773 spi13: spi@a94000 {
2054 compatible = 1774 compatible = "qcom,geni-spi";
2055 reg = <0 0x00 1775 reg = <0 0x00a94000 0 0x4000>;
2056 clock-names = 1776 clock-names = "se";
2057 clocks = <&gc 1777 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2058 interrupts = 1778 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2059 dmas = <&gpi_ 1779 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
2060 <&gpi_ 1780 <&gpi_dma1 1 5 QCOM_GPI_SPI>;
2061 dma-names = " 1781 dma-names = "tx", "rx";
2062 power-domains 1782 power-domains = <&rpmhpd RPMHPD_CX>;
2063 operating-poi 1783 operating-points-v2 = <&qup_opp_table>;
2064 interconnects <<
2065 <<
2066 <<
2067 interconnect- <<
2068 <<
2069 <<
2070 #address-cell 1784 #address-cells = <1>;
2071 #size-cells = 1785 #size-cells = <0>;
2072 status = "dis 1786 status = "disabled";
2073 }; 1787 };
2074 }; 1788 };
2075 1789
2076 config_noc: interconnect@1500 1790 config_noc: interconnect@1500000 {
2077 compatible = "qcom,sm 1791 compatible = "qcom,sm8250-config-noc";
2078 reg = <0 0x01500000 0 1792 reg = <0 0x01500000 0 0xa580>;
2079 #interconnect-cells = 1793 #interconnect-cells = <2>;
2080 qcom,bcm-voters = <&a 1794 qcom,bcm-voters = <&apps_bcm_voter>;
2081 }; 1795 };
2082 1796
2083 system_noc: interconnect@1620 1797 system_noc: interconnect@1620000 {
2084 compatible = "qcom,sm 1798 compatible = "qcom,sm8250-system-noc";
2085 reg = <0 0x01620000 0 1799 reg = <0 0x01620000 0 0x1c200>;
2086 #interconnect-cells = 1800 #interconnect-cells = <2>;
2087 qcom,bcm-voters = <&a 1801 qcom,bcm-voters = <&apps_bcm_voter>;
2088 }; 1802 };
2089 1803
2090 mc_virt: interconnect@163d000 1804 mc_virt: interconnect@163d000 {
2091 compatible = "qcom,sm 1805 compatible = "qcom,sm8250-mc-virt";
2092 reg = <0 0x0163d000 0 1806 reg = <0 0x0163d000 0 0x1000>;
2093 #interconnect-cells = 1807 #interconnect-cells = <2>;
2094 qcom,bcm-voters = <&a 1808 qcom,bcm-voters = <&apps_bcm_voter>;
2095 }; 1809 };
2096 1810
2097 aggre1_noc: interconnect@16e0 1811 aggre1_noc: interconnect@16e0000 {
2098 compatible = "qcom,sm 1812 compatible = "qcom,sm8250-aggre1-noc";
2099 reg = <0 0x016e0000 0 1813 reg = <0 0x016e0000 0 0x1f180>;
2100 #interconnect-cells = 1814 #interconnect-cells = <2>;
2101 qcom,bcm-voters = <&a 1815 qcom,bcm-voters = <&apps_bcm_voter>;
2102 }; 1816 };
2103 1817
2104 aggre2_noc: interconnect@1700 1818 aggre2_noc: interconnect@1700000 {
2105 compatible = "qcom,sm 1819 compatible = "qcom,sm8250-aggre2-noc";
2106 reg = <0 0x01700000 0 1820 reg = <0 0x01700000 0 0x33000>;
2107 #interconnect-cells = 1821 #interconnect-cells = <2>;
2108 qcom,bcm-voters = <&a 1822 qcom,bcm-voters = <&apps_bcm_voter>;
2109 }; 1823 };
2110 1824
2111 compute_noc: interconnect@173 1825 compute_noc: interconnect@1733000 {
2112 compatible = "qcom,sm 1826 compatible = "qcom,sm8250-compute-noc";
2113 reg = <0 0x01733000 0 1827 reg = <0 0x01733000 0 0xa180>;
2114 #interconnect-cells = 1828 #interconnect-cells = <2>;
2115 qcom,bcm-voters = <&a 1829 qcom,bcm-voters = <&apps_bcm_voter>;
2116 }; 1830 };
2117 1831
2118 mmss_noc: interconnect@174000 1832 mmss_noc: interconnect@1740000 {
2119 compatible = "qcom,sm 1833 compatible = "qcom,sm8250-mmss-noc";
2120 reg = <0 0x01740000 0 1834 reg = <0 0x01740000 0 0x1f080>;
2121 #interconnect-cells = 1835 #interconnect-cells = <2>;
2122 qcom,bcm-voters = <&a 1836 qcom,bcm-voters = <&apps_bcm_voter>;
2123 }; 1837 };
2124 1838
2125 pcie0: pcie@1c00000 { !! 1839 pcie0: pci@1c00000 {
2126 compatible = "qcom,pc 1840 compatible = "qcom,pcie-sm8250";
2127 reg = <0 0x01c00000 0 1841 reg = <0 0x01c00000 0 0x3000>,
2128 <0 0x60000000 0 1842 <0 0x60000000 0 0xf1d>,
2129 <0 0x60000f20 0 1843 <0 0x60000f20 0 0xa8>,
2130 <0 0x60001000 0 1844 <0 0x60001000 0 0x1000>,
2131 <0 0x60100000 0 1845 <0 0x60100000 0 0x100000>,
2132 <0 0x01c03000 0 1846 <0 0x01c03000 0 0x1000>;
2133 reg-names = "parf", " 1847 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2134 device_type = "pci"; 1848 device_type = "pci";
2135 linux,pci-domain = <0 1849 linux,pci-domain = <0>;
2136 bus-range = <0x00 0xf 1850 bus-range = <0x00 0xff>;
2137 num-lanes = <1>; 1851 num-lanes = <1>;
2138 1852
2139 #address-cells = <3>; 1853 #address-cells = <3>;
2140 #size-cells = <2>; 1854 #size-cells = <2>;
2141 1855
2142 ranges = <0x01000000 1856 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
2143 <0x02000000 1857 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
2144 1858
2145 interrupts = <GIC_SPI 1859 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
2146 <GIC_SPI 1860 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
2147 <GIC_SPI 1861 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
2148 <GIC_SPI 1862 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
2149 <GIC_SPI 1863 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
2150 <GIC_SPI 1864 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
2151 <GIC_SPI 1865 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
2152 <GIC_SPI 1866 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2153 interrupt-names = "ms !! 1867 interrupt-names = "msi0", "msi1", "msi2", "msi3",
2154 "ms !! 1868 "msi4", "msi5", "msi6", "msi7";
2155 "ms <<
2156 "ms <<
2157 "ms <<
2158 "ms <<
2159 "ms <<
2160 "ms <<
2161 #interrupt-cells = <1 1869 #interrupt-cells = <1>;
2162 interrupt-map-mask = 1870 interrupt-map-mask = <0 0 0 0x7>;
2163 interrupt-map = <0 0 1871 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2164 <0 0 1872 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2165 <0 0 1873 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2166 <0 0 1874 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2167 1875
2168 clocks = <&gcc GCC_PC 1876 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
2169 <&gcc GCC_PC 1877 <&gcc GCC_PCIE_0_AUX_CLK>,
2170 <&gcc GCC_PC 1878 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2171 <&gcc GCC_PC 1879 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
2172 <&gcc GCC_PC 1880 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
2173 <&gcc GCC_PC 1881 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
2174 <&gcc GCC_AG 1882 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
2175 <&gcc GCC_DD 1883 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
2176 clock-names = "pipe", 1884 clock-names = "pipe",
2177 "aux", 1885 "aux",
2178 "cfg", 1886 "cfg",
2179 "bus_ma 1887 "bus_master",
2180 "bus_sl 1888 "bus_slave",
2181 "slave_ 1889 "slave_q2a",
2182 "tbu", 1890 "tbu",
2183 "ddrss_ 1891 "ddrss_sf_tbu";
2184 1892
2185 iommu-map = <0x0 &a 1893 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
2186 <0x100 &a 1894 <0x100 &apps_smmu 0x1c01 0x1>;
2187 1895
2188 resets = <&gcc GCC_PC 1896 resets = <&gcc GCC_PCIE_0_BCR>;
2189 reset-names = "pci"; 1897 reset-names = "pci";
2190 1898
2191 power-domains = <&gcc 1899 power-domains = <&gcc PCIE_0_GDSC>;
2192 1900
2193 phys = <&pcie0_phy>; !! 1901 phys = <&pcie0_lane>;
2194 phy-names = "pciephy" 1902 phy-names = "pciephy";
2195 1903
2196 perst-gpios = <&tlmm 1904 perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>;
2197 wake-gpios = <&tlmm 8 1905 wake-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
2198 1906
2199 pinctrl-names = "defa 1907 pinctrl-names = "default";
2200 pinctrl-0 = <&pcie0_d 1908 pinctrl-0 = <&pcie0_default_state>;
2201 dma-coherent; 1909 dma-coherent;
2202 1910
2203 status = "disabled"; 1911 status = "disabled";
2204 <<
2205 pcieport0: pcie@0 { <<
2206 device_type = <<
2207 reg = <0x0 0x <<
2208 bus-range = < <<
2209 <<
2210 #address-cell <<
2211 #size-cells = <<
2212 ranges; <<
2213 }; <<
2214 }; 1912 };
2215 1913
2216 pcie0_phy: phy@1c06000 { 1914 pcie0_phy: phy@1c06000 {
2217 compatible = "qcom,sm 1915 compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy";
2218 reg = <0 0x01c06000 0 !! 1916 reg = <0 0x01c06000 0 0x1c0>;
2219 !! 1917 #address-cells = <2>;
>> 1918 #size-cells = <2>;
>> 1919 ranges;
2220 clocks = <&gcc GCC_PC 1920 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2221 <&gcc GCC_PC 1921 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2222 <&gcc GCC_PC 1922 <&gcc GCC_PCIE_WIFI_CLKREF_EN>,
2223 <&gcc GCC_PC !! 1923 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
2224 <&gcc GCC_PC !! 1924 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2225 clock-names = "aux", <<
2226 "cfg_ah <<
2227 "ref", <<
2228 "refgen <<
2229 "pipe"; <<
2230 <<
2231 clock-output-names = <<
2232 #clock-cells = <0>; <<
2233 <<
2234 #phy-cells = <0>; <<
2235 1925
2236 resets = <&gcc GCC_PC 1926 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
2237 reset-names = "phy"; 1927 reset-names = "phy";
2238 1928
2239 assigned-clocks = <&g 1929 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
2240 assigned-clock-rates 1930 assigned-clock-rates = <100000000>;
2241 1931
2242 status = "disabled"; 1932 status = "disabled";
>> 1933
>> 1934 pcie0_lane: phy@1c06200 {
>> 1935 reg = <0 0x01c06200 0 0x170>, /* tx */
>> 1936 <0 0x01c06400 0 0x200>, /* rx */
>> 1937 <0 0x01c06800 0 0x1f0>, /* pcs */
>> 1938 <0 0x01c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */
>> 1939 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
>> 1940 clock-names = "pipe0";
>> 1941
>> 1942 #phy-cells = <0>;
>> 1943
>> 1944 #clock-cells = <0>;
>> 1945 clock-output-names = "pcie_0_pipe_clk";
>> 1946 };
2243 }; 1947 };
2244 1948
2245 pcie1: pcie@1c08000 { !! 1949 pcie1: pci@1c08000 {
2246 compatible = "qcom,pc 1950 compatible = "qcom,pcie-sm8250";
2247 reg = <0 0x01c08000 0 1951 reg = <0 0x01c08000 0 0x3000>,
2248 <0 0x40000000 0 1952 <0 0x40000000 0 0xf1d>,
2249 <0 0x40000f20 0 1953 <0 0x40000f20 0 0xa8>,
2250 <0 0x40001000 0 1954 <0 0x40001000 0 0x1000>,
2251 <0 0x40100000 0 1955 <0 0x40100000 0 0x100000>,
2252 <0 0x01c0b000 0 1956 <0 0x01c0b000 0 0x1000>;
2253 reg-names = "parf", " 1957 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2254 device_type = "pci"; 1958 device_type = "pci";
2255 linux,pci-domain = <1 1959 linux,pci-domain = <1>;
2256 bus-range = <0x00 0xf 1960 bus-range = <0x00 0xff>;
2257 num-lanes = <2>; 1961 num-lanes = <2>;
2258 1962
2259 #address-cells = <3>; 1963 #address-cells = <3>;
2260 #size-cells = <2>; 1964 #size-cells = <2>;
2261 1965
2262 ranges = <0x01000000 1966 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
2263 <0x02000000 1967 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
2264 1968
2265 interrupts = <GIC_SPI !! 1969 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
2266 <GIC_SPI !! 1970 interrupt-names = "msi";
2267 <GIC_SPI <<
2268 <GIC_SPI <<
2269 <GIC_SPI <<
2270 <GIC_SPI <<
2271 <GIC_SPI <<
2272 <GIC_SPI <<
2273 interrupt-names = "ms <<
2274 "ms <<
2275 "ms <<
2276 "ms <<
2277 "ms <<
2278 "ms <<
2279 "ms <<
2280 "ms <<
2281 #interrupt-cells = <1 1971 #interrupt-cells = <1>;
2282 interrupt-map-mask = 1972 interrupt-map-mask = <0 0 0 0x7>;
2283 interrupt-map = <0 0 1973 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2284 <0 0 1974 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2285 <0 0 1975 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2286 <0 0 1976 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2287 1977
2288 clocks = <&gcc GCC_PC 1978 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
2289 <&gcc GCC_PC 1979 <&gcc GCC_PCIE_1_AUX_CLK>,
2290 <&gcc GCC_PC 1980 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2291 <&gcc GCC_PC 1981 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
2292 <&gcc GCC_PC 1982 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
2293 <&gcc GCC_PC 1983 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
2294 <&gcc GCC_PC 1984 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
2295 <&gcc GCC_AG 1985 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
2296 <&gcc GCC_DD 1986 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
2297 clock-names = "pipe", 1987 clock-names = "pipe",
2298 "aux", 1988 "aux",
2299 "cfg", 1989 "cfg",
2300 "bus_ma 1990 "bus_master",
2301 "bus_sl 1991 "bus_slave",
2302 "slave_ 1992 "slave_q2a",
2303 "ref", 1993 "ref",
2304 "tbu", 1994 "tbu",
2305 "ddrss_ 1995 "ddrss_sf_tbu";
2306 1996
2307 assigned-clocks = <&g 1997 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2308 assigned-clock-rates 1998 assigned-clock-rates = <19200000>;
2309 1999
2310 iommu-map = <0x0 &a 2000 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
2311 <0x100 &a 2001 <0x100 &apps_smmu 0x1c81 0x1>;
2312 2002
2313 resets = <&gcc GCC_PC 2003 resets = <&gcc GCC_PCIE_1_BCR>;
2314 reset-names = "pci"; 2004 reset-names = "pci";
2315 2005
2316 power-domains = <&gcc 2006 power-domains = <&gcc PCIE_1_GDSC>;
2317 2007
2318 phys = <&pcie1_phy>; !! 2008 phys = <&pcie1_lane>;
2319 phy-names = "pciephy" 2009 phy-names = "pciephy";
2320 2010
2321 perst-gpios = <&tlmm 2011 perst-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>;
2322 wake-gpios = <&tlmm 8 2012 wake-gpios = <&tlmm 84 GPIO_ACTIVE_HIGH>;
2323 2013
2324 pinctrl-names = "defa 2014 pinctrl-names = "default";
2325 pinctrl-0 = <&pcie1_d 2015 pinctrl-0 = <&pcie1_default_state>;
2326 dma-coherent; 2016 dma-coherent;
2327 2017
2328 status = "disabled"; 2018 status = "disabled";
2329 <<
2330 pcie@0 { <<
2331 device_type = <<
2332 reg = <0x0 0x <<
2333 bus-range = < <<
2334 <<
2335 #address-cell <<
2336 #size-cells = <<
2337 ranges; <<
2338 }; <<
2339 }; 2019 };
2340 2020
2341 pcie1_phy: phy@1c0e000 { 2021 pcie1_phy: phy@1c0e000 {
2342 compatible = "qcom,sm 2022 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
2343 reg = <0 0x01c0e000 0 !! 2023 reg = <0 0x01c0e000 0 0x1c0>;
2344 !! 2024 #address-cells = <2>;
>> 2025 #size-cells = <2>;
>> 2026 ranges;
2345 clocks = <&gcc GCC_PC 2027 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2346 <&gcc GCC_PC 2028 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2347 <&gcc GCC_PC 2029 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
2348 <&gcc GCC_PC !! 2030 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
2349 <&gcc GCC_PC !! 2031 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2350 clock-names = "aux", <<
2351 "cfg_ah <<
2352 "ref", <<
2353 "refgen <<
2354 "pipe"; <<
2355 <<
2356 clock-output-names = <<
2357 #clock-cells = <0>; <<
2358 <<
2359 #phy-cells = <0>; <<
2360 2032
2361 resets = <&gcc GCC_PC 2033 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2362 reset-names = "phy"; 2034 reset-names = "phy";
2363 2035
2364 assigned-clocks = <&g 2036 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
2365 assigned-clock-rates 2037 assigned-clock-rates = <100000000>;
2366 2038
2367 status = "disabled"; 2039 status = "disabled";
>> 2040
>> 2041 pcie1_lane: phy@1c0e200 {
>> 2042 reg = <0 0x01c0e200 0 0x170>, /* tx0 */
>> 2043 <0 0x01c0e400 0 0x200>, /* rx0 */
>> 2044 <0 0x01c0ea00 0 0x1f0>, /* pcs */
>> 2045 <0 0x01c0e600 0 0x170>, /* tx1 */
>> 2046 <0 0x01c0e800 0 0x200>, /* rx1 */
>> 2047 <0 0x01c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */
>> 2048 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
>> 2049 clock-names = "pipe0";
>> 2050
>> 2051 #phy-cells = <0>;
>> 2052
>> 2053 #clock-cells = <0>;
>> 2054 clock-output-names = "pcie_1_pipe_clk";
>> 2055 };
2368 }; 2056 };
2369 2057
2370 pcie2: pcie@1c10000 { !! 2058 pcie2: pci@1c10000 {
2371 compatible = "qcom,pc 2059 compatible = "qcom,pcie-sm8250";
2372 reg = <0 0x01c10000 0 2060 reg = <0 0x01c10000 0 0x3000>,
2373 <0 0x64000000 0 2061 <0 0x64000000 0 0xf1d>,
2374 <0 0x64000f20 0 2062 <0 0x64000f20 0 0xa8>,
2375 <0 0x64001000 0 2063 <0 0x64001000 0 0x1000>,
2376 <0 0x64100000 0 2064 <0 0x64100000 0 0x100000>,
2377 <0 0x01c13000 0 2065 <0 0x01c13000 0 0x1000>;
2378 reg-names = "parf", " 2066 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2379 device_type = "pci"; 2067 device_type = "pci";
2380 linux,pci-domain = <2 2068 linux,pci-domain = <2>;
2381 bus-range = <0x00 0xf 2069 bus-range = <0x00 0xff>;
2382 num-lanes = <2>; 2070 num-lanes = <2>;
2383 2071
2384 #address-cells = <3>; 2072 #address-cells = <3>;
2385 #size-cells = <2>; 2073 #size-cells = <2>;
2386 2074
2387 ranges = <0x01000000 2075 ranges = <0x01000000 0x0 0x00000000 0x0 0x64200000 0x0 0x100000>,
2388 <0x02000000 2076 <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>;
2389 2077
2390 interrupts = <GIC_SPI !! 2078 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
2391 <GIC_SPI !! 2079 interrupt-names = "msi";
2392 <GIC_SPI <<
2393 <GIC_SPI <<
2394 <GIC_SPI <<
2395 <GIC_SPI <<
2396 <GIC_SPI <<
2397 <GIC_SPI <<
2398 interrupt-names = "ms <<
2399 "ms <<
2400 "ms <<
2401 "ms <<
2402 "ms <<
2403 "ms <<
2404 "ms <<
2405 "ms <<
2406 #interrupt-cells = <1 2080 #interrupt-cells = <1>;
2407 interrupt-map-mask = 2081 interrupt-map-mask = <0 0 0 0x7>;
2408 interrupt-map = <0 0 2082 interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2409 <0 0 2083 <0 0 0 2 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2410 <0 0 2084 <0 0 0 3 &intc 0 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2411 <0 0 2085 <0 0 0 4 &intc 0 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2412 2086
2413 clocks = <&gcc GCC_PC 2087 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
2414 <&gcc GCC_PC 2088 <&gcc GCC_PCIE_2_AUX_CLK>,
2415 <&gcc GCC_PC 2089 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2416 <&gcc GCC_PC 2090 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
2417 <&gcc GCC_PC 2091 <&gcc GCC_PCIE_2_SLV_AXI_CLK>,
2418 <&gcc GCC_PC 2092 <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>,
2419 <&gcc GCC_PC 2093 <&gcc GCC_PCIE_MDM_CLKREF_EN>,
2420 <&gcc GCC_AG 2094 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
2421 <&gcc GCC_DD 2095 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
2422 clock-names = "pipe", 2096 clock-names = "pipe",
2423 "aux", 2097 "aux",
2424 "cfg", 2098 "cfg",
2425 "bus_ma 2099 "bus_master",
2426 "bus_sl 2100 "bus_slave",
2427 "slave_ 2101 "slave_q2a",
2428 "ref", 2102 "ref",
2429 "tbu", 2103 "tbu",
2430 "ddrss_ 2104 "ddrss_sf_tbu";
2431 2105
2432 assigned-clocks = <&g 2106 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>;
2433 assigned-clock-rates 2107 assigned-clock-rates = <19200000>;
2434 2108
2435 iommu-map = <0x0 &a 2109 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>,
2436 <0x100 &a 2110 <0x100 &apps_smmu 0x1d01 0x1>;
2437 2111
2438 resets = <&gcc GCC_PC 2112 resets = <&gcc GCC_PCIE_2_BCR>;
2439 reset-names = "pci"; 2113 reset-names = "pci";
2440 2114
2441 power-domains = <&gcc 2115 power-domains = <&gcc PCIE_2_GDSC>;
2442 2116
2443 phys = <&pcie2_phy>; !! 2117 phys = <&pcie2_lane>;
2444 phy-names = "pciephy" 2118 phy-names = "pciephy";
2445 2119
2446 perst-gpios = <&tlmm 2120 perst-gpios = <&tlmm 85 GPIO_ACTIVE_LOW>;
2447 wake-gpios = <&tlmm 8 2121 wake-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>;
2448 2122
2449 pinctrl-names = "defa 2123 pinctrl-names = "default";
2450 pinctrl-0 = <&pcie2_d 2124 pinctrl-0 = <&pcie2_default_state>;
2451 dma-coherent; 2125 dma-coherent;
2452 2126
2453 status = "disabled"; 2127 status = "disabled";
2454 <<
2455 pcie@0 { <<
2456 device_type = <<
2457 reg = <0x0 0x <<
2458 bus-range = < <<
2459 <<
2460 #address-cell <<
2461 #size-cells = <<
2462 ranges; <<
2463 }; <<
2464 }; 2128 };
2465 2129
2466 pcie2_phy: phy@1c16000 { 2130 pcie2_phy: phy@1c16000 {
2467 compatible = "qcom,sm 2131 compatible = "qcom,sm8250-qmp-modem-pcie-phy";
2468 reg = <0 0x01c16000 0 !! 2132 reg = <0 0x01c16000 0 0x1c0>;
2469 !! 2133 #address-cells = <2>;
>> 2134 #size-cells = <2>;
>> 2135 ranges;
2470 clocks = <&gcc GCC_PC 2136 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2471 <&gcc GCC_PC 2137 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2472 <&gcc GCC_PC 2138 <&gcc GCC_PCIE_MDM_CLKREF_EN>,
2473 <&gcc GCC_PC !! 2139 <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
2474 <&gcc GCC_PC !! 2140 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2475 clock-names = "aux", <<
2476 "cfg_ah <<
2477 "ref", <<
2478 "refgen <<
2479 "pipe"; <<
2480 <<
2481 clock-output-names = <<
2482 #clock-cells = <0>; <<
2483 <<
2484 #phy-cells = <0>; <<
2485 2141
2486 resets = <&gcc GCC_PC 2142 resets = <&gcc GCC_PCIE_2_PHY_BCR>;
2487 reset-names = "phy"; 2143 reset-names = "phy";
2488 2144
2489 assigned-clocks = <&g 2145 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
2490 assigned-clock-rates 2146 assigned-clock-rates = <100000000>;
2491 2147
2492 status = "disabled"; 2148 status = "disabled";
>> 2149
>> 2150 pcie2_lane: phy@1c16200 {
>> 2151 reg = <0 0x01c16200 0 0x170>, /* tx0 */
>> 2152 <0 0x01c16400 0 0x200>, /* rx0 */
>> 2153 <0 0x01c16a00 0 0x1f0>, /* pcs */
>> 2154 <0 0x01c16600 0 0x170>, /* tx1 */
>> 2155 <0 0x01c16800 0 0x200>, /* rx1 */
>> 2156 <0 0x01c16e00 0 0xf4>; /* "pcs_com" same as pcs_misc? */
>> 2157 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
>> 2158 clock-names = "pipe0";
>> 2159
>> 2160 #phy-cells = <0>;
>> 2161
>> 2162 #clock-cells = <0>;
>> 2163 clock-output-names = "pcie_2_pipe_clk";
>> 2164 };
2493 }; 2165 };
2494 2166
2495 ufs_mem_hc: ufshc@1d84000 { 2167 ufs_mem_hc: ufshc@1d84000 {
2496 compatible = "qcom,sm 2168 compatible = "qcom,sm8250-ufshc", "qcom,ufshc",
2497 "jedec,u 2169 "jedec,ufs-2.0";
2498 reg = <0 0x01d84000 0 2170 reg = <0 0x01d84000 0 0x3000>;
2499 interrupts = <GIC_SPI 2171 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2500 phys = <&ufs_mem_phy> 2172 phys = <&ufs_mem_phy>;
2501 phy-names = "ufsphy"; 2173 phy-names = "ufsphy";
2502 lanes-per-direction = 2174 lanes-per-direction = <2>;
2503 #reset-cells = <1>; 2175 #reset-cells = <1>;
2504 resets = <&gcc GCC_UF 2176 resets = <&gcc GCC_UFS_PHY_BCR>;
2505 reset-names = "rst"; 2177 reset-names = "rst";
2506 2178
2507 power-domains = <&gcc 2179 power-domains = <&gcc UFS_PHY_GDSC>;
2508 2180
2509 iommus = <&apps_smmu 2181 iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>;
2510 2182
2511 clock-names = 2183 clock-names =
2512 "core_clk", 2184 "core_clk",
2513 "bus_aggr_clk 2185 "bus_aggr_clk",
2514 "iface_clk", 2186 "iface_clk",
2515 "core_clk_uni 2187 "core_clk_unipro",
2516 "ref_clk", 2188 "ref_clk",
2517 "tx_lane0_syn 2189 "tx_lane0_sync_clk",
2518 "rx_lane0_syn 2190 "rx_lane0_sync_clk",
2519 "rx_lane1_syn 2191 "rx_lane1_sync_clk";
2520 clocks = 2192 clocks =
2521 <&gcc GCC_UFS 2193 <&gcc GCC_UFS_PHY_AXI_CLK>,
2522 <&gcc GCC_AGG 2194 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2523 <&gcc GCC_UFS 2195 <&gcc GCC_UFS_PHY_AHB_CLK>,
2524 <&gcc GCC_UFS 2196 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2525 <&rpmhcc RPMH 2197 <&rpmhcc RPMH_CXO_CLK>,
2526 <&gcc GCC_UFS 2198 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2527 <&gcc GCC_UFS 2199 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2528 <&gcc GCC_UFS 2200 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
2529 !! 2201 freq-table-hz =
2530 operating-points-v2 = !! 2202 <37500000 300000000>,
>> 2203 <0 0>,
>> 2204 <0 0>,
>> 2205 <37500000 300000000>,
>> 2206 <0 0>,
>> 2207 <0 0>,
>> 2208 <0 0>,
>> 2209 <0 0>;
2531 2210
2532 interconnects = <&agg 2211 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI_CH0 0>,
2533 <&gem 2212 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
2534 interconnect-names = 2213 interconnect-names = "ufs-ddr", "cpu-ufs";
2535 2214
2536 status = "disabled"; 2215 status = "disabled";
2537 <<
2538 ufs_opp_table: opp-ta <<
2539 compatible = <<
2540 <<
2541 opp-37500000 <<
2542 opp-h <<
2543 <<
2544 <<
2545 <<
2546 <<
2547 <<
2548 <<
2549 <<
2550 requi <<
2551 }; <<
2552 <<
2553 opp-300000000 <<
2554 opp-h <<
2555 <<
2556 <<
2557 <<
2558 <<
2559 <<
2560 <<
2561 <<
2562 requi <<
2563 }; <<
2564 }; <<
2565 }; 2216 };
2566 2217
2567 ufs_mem_phy: phy@1d87000 { 2218 ufs_mem_phy: phy@1d87000 {
2568 compatible = "qcom,sm 2219 compatible = "qcom,sm8250-qmp-ufs-phy";
2569 reg = <0 0x01d87000 0 2220 reg = <0 0x01d87000 0 0x1000>;
2570 2221
2571 clocks = <&rpmhcc RPM <<
2572 <&gcc GCC_UF <<
2573 <&gcc GCC_UF <<
2574 clock-names = "ref", 2222 clock-names = "ref",
2575 "ref_au !! 2223 "ref_aux";
2576 "qref"; !! 2224 clocks = <&rpmhcc RPMH_CXO_CLK>,
>> 2225 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2577 2226
2578 resets = <&ufs_mem_hc 2227 resets = <&ufs_mem_hc 0>;
2579 reset-names = "ufsphy 2228 reset-names = "ufsphy";
2580 2229
2581 power-domains = <&gcc 2230 power-domains = <&gcc UFS_PHY_GDSC>;
2582 2231
2583 #phy-cells = <0>; 2232 #phy-cells = <0>;
2584 2233
2585 status = "disabled"; 2234 status = "disabled";
2586 }; 2235 };
2587 2236
2588 cryptobam: dma-controller@1dc 2237 cryptobam: dma-controller@1dc4000 {
2589 compatible = "qcom,ba 2238 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
2590 reg = <0 0x01dc4000 0 2239 reg = <0 0x01dc4000 0 0x24000>;
2591 interrupts = <GIC_SPI 2240 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
2592 #dma-cells = <1>; 2241 #dma-cells = <1>;
2593 qcom,ee = <0>; 2242 qcom,ee = <0>;
2594 qcom,controlled-remot 2243 qcom,controlled-remotely;
2595 num-channels = <8>; 2244 num-channels = <8>;
2596 qcom,num-ees = <2>; 2245 qcom,num-ees = <2>;
2597 iommus = <&apps_smmu 2246 iommus = <&apps_smmu 0x592 0x0000>,
2598 <&apps_smmu 2247 <&apps_smmu 0x598 0x0000>,
2599 <&apps_smmu 2248 <&apps_smmu 0x599 0x0000>,
2600 <&apps_smmu 2249 <&apps_smmu 0x59f 0x0000>,
2601 <&apps_smmu 2250 <&apps_smmu 0x586 0x0011>,
2602 <&apps_smmu 2251 <&apps_smmu 0x596 0x0011>;
2603 }; 2252 };
2604 2253
2605 crypto: crypto@1dfa000 { 2254 crypto: crypto@1dfa000 {
2606 compatible = "qcom,sm 2255 compatible = "qcom,sm8250-qce", "qcom,sm8150-qce", "qcom,qce";
2607 reg = <0 0x01dfa000 0 2256 reg = <0 0x01dfa000 0 0x6000>;
2608 dmas = <&cryptobam 4> 2257 dmas = <&cryptobam 4>, <&cryptobam 5>;
2609 dma-names = "rx", "tx 2258 dma-names = "rx", "tx";
2610 iommus = <&apps_smmu 2259 iommus = <&apps_smmu 0x592 0x0000>,
2611 <&apps_smmu 2260 <&apps_smmu 0x598 0x0000>,
2612 <&apps_smmu 2261 <&apps_smmu 0x599 0x0000>,
2613 <&apps_smmu 2262 <&apps_smmu 0x59f 0x0000>,
2614 <&apps_smmu 2263 <&apps_smmu 0x586 0x0011>,
2615 <&apps_smmu 2264 <&apps_smmu 0x596 0x0011>;
2616 interconnects = <&agg 2265 interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 0 &mc_virt SLAVE_EBI_CH0 0>;
2617 interconnect-names = 2266 interconnect-names = "memory";
2618 }; 2267 };
2619 2268
2620 tcsr_mutex: hwlock@1f40000 { 2269 tcsr_mutex: hwlock@1f40000 {
2621 compatible = "qcom,tc 2270 compatible = "qcom,tcsr-mutex";
2622 reg = <0x0 0x01f40000 2271 reg = <0x0 0x01f40000 0x0 0x40000>;
2623 #hwlock-cells = <1>; 2272 #hwlock-cells = <1>;
2624 }; 2273 };
2625 2274
2626 tcsr: syscon@1fc0000 { <<
2627 compatible = "qcom,sm <<
2628 reg = <0x0 0x1fc0000 <<
2629 }; <<
2630 <<
2631 wsamacro: codec@3240000 { 2275 wsamacro: codec@3240000 {
2632 compatible = "qcom,sm 2276 compatible = "qcom,sm8250-lpass-wsa-macro";
2633 reg = <0 0x03240000 0 2277 reg = <0 0x03240000 0 0x1000>;
2634 clocks = <&q6afecc LP !! 2278 clocks = <&audiocc LPASS_CDC_WSA_MCLK>,
2635 <&q6afecc LP !! 2279 <&audiocc LPASS_CDC_WSA_NPL>,
2636 <&q6afecc LP 2280 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2637 <&q6afecc LP 2281 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 2282 <&aoncc LPASS_CDC_VA_MCLK>,
2638 <&vamacro>; 2283 <&vamacro>;
2639 2284
2640 clock-names = "mclk", !! 2285 clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen";
2641 2286
2642 #clock-cells = <0>; 2287 #clock-cells = <0>;
2643 clock-output-names = 2288 clock-output-names = "mclk";
2644 #sound-dai-cells = <1 2289 #sound-dai-cells = <1>;
2645 2290
2646 pinctrl-names = "defa 2291 pinctrl-names = "default";
2647 pinctrl-0 = <&wsa_swr 2292 pinctrl-0 = <&wsa_swr_active>;
2648 2293
2649 status = "disabled"; 2294 status = "disabled";
2650 }; 2295 };
2651 2296
2652 swr0: soundwire@3250000 { !! 2297 swr0: soundwire-controller@3250000 {
2653 reg = <0 0x03250000 0 2298 reg = <0 0x03250000 0 0x2000>;
2654 compatible = "qcom,so 2299 compatible = "qcom,soundwire-v1.5.1";
2655 interrupts = <GIC_SPI 2300 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
2656 clocks = <&wsamacro>; 2301 clocks = <&wsamacro>;
2657 clock-names = "iface" 2302 clock-names = "iface";
2658 2303
2659 qcom,din-ports = <2>; 2304 qcom,din-ports = <2>;
2660 qcom,dout-ports = <6> 2305 qcom,dout-ports = <6>;
2661 2306
2662 qcom,ports-sinterval- 2307 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2663 qcom,ports-offset1 = 2308 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2664 qcom,ports-offset2 = 2309 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2665 qcom,ports-block-pack 2310 qcom,ports-block-pack-mode = /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>;
2666 2311
2667 #sound-dai-cells = <1 2312 #sound-dai-cells = <1>;
2668 #address-cells = <2>; 2313 #address-cells = <2>;
2669 #size-cells = <0>; 2314 #size-cells = <0>;
2670 2315
2671 status = "disabled"; 2316 status = "disabled";
2672 }; 2317 };
2673 2318
>> 2319 audiocc: clock-controller@3300000 {
>> 2320 compatible = "qcom,sm8250-lpass-audiocc";
>> 2321 reg = <0 0x03300000 0 0x30000>;
>> 2322 #clock-cells = <1>;
>> 2323 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 2324 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 2325 <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
>> 2326 clock-names = "core", "audio", "bus";
>> 2327 };
>> 2328
2674 vamacro: codec@3370000 { 2329 vamacro: codec@3370000 {
2675 compatible = "qcom,sm 2330 compatible = "qcom,sm8250-lpass-va-macro";
2676 reg = <0 0x03370000 0 2331 reg = <0 0x03370000 0 0x1000>;
2677 clocks = <&q6afecc LP !! 2332 clocks = <&aoncc LPASS_CDC_VA_MCLK>,
2678 <&q6afecc LPA 2333 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2679 <&q6afecc LPA 2334 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2680 2335
2681 clock-names = "mclk", 2336 clock-names = "mclk", "macro", "dcodec";
2682 2337
2683 #clock-cells = <0>; 2338 #clock-cells = <0>;
2684 clock-output-names = 2339 clock-output-names = "fsgen";
2685 #sound-dai-cells = <1 2340 #sound-dai-cells = <1>;
2686 }; 2341 };
2687 2342
2688 rxmacro: rxmacro@3200000 { 2343 rxmacro: rxmacro@3200000 {
2689 pinctrl-names = "defa 2344 pinctrl-names = "default";
2690 pinctrl-0 = <&rx_swr_ 2345 pinctrl-0 = <&rx_swr_active>;
2691 compatible = "qcom,sm 2346 compatible = "qcom,sm8250-lpass-rx-macro";
2692 reg = <0 0x03200000 0 2347 reg = <0 0x03200000 0 0x1000>;
2693 status = "disabled"; 2348 status = "disabled";
2694 2349
2695 clocks = <&q6afecc LP 2350 clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2696 <&q6afecc LPA 2351 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2697 <&q6afecc LPA 2352 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2698 <&q6afecc LPA 2353 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2699 <&vamacro>; 2354 <&vamacro>;
2700 2355
2701 clock-names = "mclk", 2356 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2702 2357
2703 #clock-cells = <0>; 2358 #clock-cells = <0>;
2704 clock-output-names = 2359 clock-output-names = "mclk";
2705 #sound-dai-cells = <1 2360 #sound-dai-cells = <1>;
2706 }; 2361 };
2707 2362
2708 swr1: soundwire@3210000 { !! 2363 swr1: soundwire-controller@3210000 {
2709 reg = <0 0x03210000 0 2364 reg = <0 0x03210000 0 0x2000>;
2710 compatible = "qcom,so 2365 compatible = "qcom,soundwire-v1.5.1";
2711 status = "disabled"; 2366 status = "disabled";
2712 interrupts = <GIC_SPI 2367 interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
2713 clocks = <&rxmacro>; 2368 clocks = <&rxmacro>;
2714 clock-names = "iface" 2369 clock-names = "iface";
2715 label = "RX"; 2370 label = "RX";
2716 qcom,din-ports = <0>; 2371 qcom,din-ports = <0>;
2717 qcom,dout-ports = <5> 2372 qcom,dout-ports = <5>;
2718 2373
2719 qcom,ports-sinterval- 2374 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
2720 qcom,ports-offset1 = 2375 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>;
2721 qcom,ports-offset2 = 2376 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
2722 qcom,ports-hstart = 2377 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
2723 qcom,ports-hstop = 2378 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
2724 qcom,ports-word-lengt 2379 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2725 qcom,ports-block-pack 2380 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
2726 qcom,ports-lane-contr 2381 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2727 qcom,ports-block-grou 2382 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
2728 2383
2729 #sound-dai-cells = <1 2384 #sound-dai-cells = <1>;
2730 #address-cells = <2>; 2385 #address-cells = <2>;
2731 #size-cells = <0>; 2386 #size-cells = <0>;
2732 }; 2387 };
2733 2388
2734 txmacro: txmacro@3220000 { 2389 txmacro: txmacro@3220000 {
2735 pinctrl-names = "defa 2390 pinctrl-names = "default";
2736 pinctrl-0 = <&tx_swr_ 2391 pinctrl-0 = <&tx_swr_active>;
2737 compatible = "qcom,sm 2392 compatible = "qcom,sm8250-lpass-tx-macro";
2738 reg = <0 0x03220000 0 2393 reg = <0 0x03220000 0 0x1000>;
2739 status = "disabled"; 2394 status = "disabled";
2740 2395
2741 clocks = <&q6afecc LP 2396 clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2742 <&q6afecc LP 2397 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2743 <&q6afecc LP 2398 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2744 <&q6afecc LP 2399 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2745 <&vamacro>; 2400 <&vamacro>;
2746 2401
2747 clock-names = "mclk", 2402 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2748 2403
2749 #clock-cells = <0>; 2404 #clock-cells = <0>;
2750 clock-output-names = 2405 clock-output-names = "mclk";
2751 #sound-dai-cells = <1 2406 #sound-dai-cells = <1>;
2752 }; 2407 };
2753 2408
2754 /* tx macro */ 2409 /* tx macro */
2755 swr2: soundwire@3230000 { !! 2410 swr2: soundwire-controller@3230000 {
2756 reg = <0 0x03230000 0 2411 reg = <0 0x03230000 0 0x2000>;
2757 compatible = "qcom,so 2412 compatible = "qcom,soundwire-v1.5.1";
2758 interrupts = <GIC_SPI 2413 interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
2759 interrupt-names = "co 2414 interrupt-names = "core";
2760 status = "disabled"; 2415 status = "disabled";
2761 2416
2762 clocks = <&txmacro>; 2417 clocks = <&txmacro>;
2763 clock-names = "iface" 2418 clock-names = "iface";
2764 label = "TX"; 2419 label = "TX";
2765 2420
2766 qcom,din-ports = <5>; 2421 qcom,din-ports = <5>;
2767 qcom,dout-ports = <0> 2422 qcom,dout-ports = <0>;
2768 qcom,ports-sinterval- 2423 qcom,ports-sinterval-low = /bits/ 8 <0xff 0x01 0x01 0x03 0x03>;
2769 qcom,ports-offset1 = 2424 qcom,ports-offset1 = /bits/ 8 <0xff 0x01 0x00 0x02 0x00>;
2770 qcom,ports-offset2 = 2425 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x00 0x00 0x00>;
2771 qcom,ports-block-pack 2426 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2772 qcom,ports-hstart = 2427 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2773 qcom,ports-hstop = 2428 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2774 qcom,ports-word-lengt 2429 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2775 qcom,ports-block-grou 2430 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2776 qcom,ports-lane-contr 2431 qcom,ports-lane-control = /bits/ 8 <0xff 0x00 0x01 0x00 0x01>;
2777 #sound-dai-cells = <1 2432 #sound-dai-cells = <1>;
2778 #address-cells = <2>; 2433 #address-cells = <2>;
2779 #size-cells = <0>; 2434 #size-cells = <0>;
2780 }; 2435 };
2781 2436
>> 2437 aoncc: clock-controller@3380000 {
>> 2438 compatible = "qcom,sm8250-lpass-aoncc";
>> 2439 reg = <0 0x03380000 0 0x40000>;
>> 2440 #clock-cells = <1>;
>> 2441 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 2442 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 2443 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
>> 2444 clock-names = "core", "audio", "bus";
>> 2445 };
>> 2446
2782 lpass_tlmm: pinctrl@33c0000 { 2447 lpass_tlmm: pinctrl@33c0000 {
2783 compatible = "qcom,sm 2448 compatible = "qcom,sm8250-lpass-lpi-pinctrl";
2784 reg = <0 0x033c0000 0 2449 reg = <0 0x033c0000 0x0 0x20000>,
2785 <0 0x03550000 0 2450 <0 0x03550000 0x0 0x10000>;
2786 gpio-controller; 2451 gpio-controller;
2787 #gpio-cells = <2>; 2452 #gpio-cells = <2>;
2788 gpio-ranges = <&lpass 2453 gpio-ranges = <&lpass_tlmm 0 0 14>;
2789 2454
2790 clocks = <&q6afecc LP 2455 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2791 <&q6afecc LPA 2456 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2792 clock-names = "core", 2457 clock-names = "core", "audio";
2793 2458
2794 wsa_swr_active: wsa-s 2459 wsa_swr_active: wsa-swr-active-state {
2795 clk-pins { 2460 clk-pins {
2796 pins 2461 pins = "gpio10";
2797 funct 2462 function = "wsa_swr_clk";
2798 drive 2463 drive-strength = <2>;
2799 slew- 2464 slew-rate = <1>;
2800 bias- 2465 bias-disable;
2801 }; 2466 };
2802 2467
2803 data-pins { 2468 data-pins {
2804 pins 2469 pins = "gpio11";
2805 funct 2470 function = "wsa_swr_data";
2806 drive 2471 drive-strength = <2>;
2807 slew- 2472 slew-rate = <1>;
2808 bias- 2473 bias-bus-hold;
2809 }; 2474 };
2810 }; 2475 };
2811 2476
2812 wsa_swr_sleep: wsa-sw 2477 wsa_swr_sleep: wsa-swr-sleep-state {
2813 clk-pins { 2478 clk-pins {
2814 pins 2479 pins = "gpio10";
2815 funct 2480 function = "wsa_swr_clk";
2816 drive 2481 drive-strength = <2>;
2817 bias- 2482 bias-pull-down;
2818 }; 2483 };
2819 2484
2820 data-pins { 2485 data-pins {
2821 pins 2486 pins = "gpio11";
2822 funct 2487 function = "wsa_swr_data";
2823 drive 2488 drive-strength = <2>;
2824 bias- 2489 bias-pull-down;
2825 }; 2490 };
2826 }; 2491 };
2827 2492
2828 dmic01_active: dmic01 2493 dmic01_active: dmic01-active-state {
2829 clk-pins { 2494 clk-pins {
2830 pins 2495 pins = "gpio6";
2831 funct 2496 function = "dmic1_clk";
2832 drive 2497 drive-strength = <8>;
2833 outpu 2498 output-high;
2834 }; 2499 };
2835 data-pins { 2500 data-pins {
2836 pins 2501 pins = "gpio7";
2837 funct 2502 function = "dmic1_data";
2838 drive 2503 drive-strength = <8>;
2839 }; 2504 };
2840 }; 2505 };
2841 2506
2842 dmic01_sleep: dmic01- 2507 dmic01_sleep: dmic01-sleep-state {
2843 clk-pins { 2508 clk-pins {
2844 pins 2509 pins = "gpio6";
2845 funct 2510 function = "dmic1_clk";
2846 drive 2511 drive-strength = <2>;
2847 bias- 2512 bias-disable;
2848 outpu 2513 output-low;
2849 }; 2514 };
2850 2515
2851 data-pins { 2516 data-pins {
2852 pins 2517 pins = "gpio7";
2853 funct 2518 function = "dmic1_data";
2854 drive 2519 drive-strength = <2>;
2855 bias- 2520 bias-pull-down;
2856 }; 2521 };
2857 }; 2522 };
2858 2523
2859 rx_swr_active: rx-swr 2524 rx_swr_active: rx-swr-active-state {
2860 clk-pins { 2525 clk-pins {
2861 pins 2526 pins = "gpio3";
2862 funct 2527 function = "swr_rx_clk";
2863 drive 2528 drive-strength = <2>;
2864 slew- 2529 slew-rate = <1>;
2865 bias- 2530 bias-disable;
2866 }; 2531 };
2867 2532
2868 data-pins { 2533 data-pins {
2869 pins 2534 pins = "gpio4", "gpio5";
2870 funct 2535 function = "swr_rx_data";
2871 drive 2536 drive-strength = <2>;
2872 slew- 2537 slew-rate = <1>;
2873 bias- 2538 bias-bus-hold;
2874 }; 2539 };
2875 }; 2540 };
2876 2541
2877 tx_swr_active: tx-swr 2542 tx_swr_active: tx-swr-active-state {
2878 clk-pins { 2543 clk-pins {
2879 pins 2544 pins = "gpio0";
2880 funct 2545 function = "swr_tx_clk";
2881 drive 2546 drive-strength = <2>;
2882 slew- 2547 slew-rate = <1>;
2883 bias- 2548 bias-disable;
2884 }; 2549 };
2885 2550
2886 data-pins { 2551 data-pins {
2887 pins 2552 pins = "gpio1", "gpio2";
2888 funct 2553 function = "swr_tx_data";
2889 drive 2554 drive-strength = <2>;
2890 slew- 2555 slew-rate = <1>;
2891 bias- 2556 bias-bus-hold;
2892 }; 2557 };
2893 }; 2558 };
2894 2559
2895 tx_swr_sleep: tx-swr- 2560 tx_swr_sleep: tx-swr-sleep-state {
2896 clk-pins { 2561 clk-pins {
2897 pins 2562 pins = "gpio0";
2898 funct 2563 function = "swr_tx_clk";
2899 drive 2564 drive-strength = <2>;
2900 bias- 2565 bias-pull-down;
2901 }; 2566 };
2902 2567
2903 data1-pins { 2568 data1-pins {
2904 pins 2569 pins = "gpio1";
2905 funct 2570 function = "swr_tx_data";
2906 drive 2571 drive-strength = <2>;
2907 bias- 2572 bias-bus-hold;
2908 }; 2573 };
2909 2574
2910 data2-pins { 2575 data2-pins {
2911 pins 2576 pins = "gpio2";
2912 funct 2577 function = "swr_tx_data";
2913 drive 2578 drive-strength = <2>;
2914 bias- 2579 bias-pull-down;
2915 }; 2580 };
2916 }; 2581 };
2917 }; 2582 };
2918 2583
2919 gpu: gpu@3d00000 { 2584 gpu: gpu@3d00000 {
2920 compatible = "qcom,ad 2585 compatible = "qcom,adreno-650.2",
2921 "qcom,ad 2586 "qcom,adreno";
2922 2587
2923 reg = <0 0x03d00000 0 2588 reg = <0 0x03d00000 0 0x40000>;
2924 reg-names = "kgsl_3d0 2589 reg-names = "kgsl_3d0_reg_memory";
2925 2590
2926 interrupts = <GIC_SPI 2591 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2927 2592
2928 iommus = <&adreno_smm 2593 iommus = <&adreno_smmu 0 0x401>;
2929 2594
2930 operating-points-v2 = 2595 operating-points-v2 = <&gpu_opp_table>;
2931 2596
2932 qcom,gmu = <&gmu>; 2597 qcom,gmu = <&gmu>;
2933 2598
2934 nvmem-cells = <&gpu_s 2599 nvmem-cells = <&gpu_speed_bin>;
2935 nvmem-cell-names = "s 2600 nvmem-cell-names = "speed_bin";
2936 #cooling-cells = <2>; <<
2937 2601
2938 status = "disabled"; 2602 status = "disabled";
2939 2603
2940 zap-shader { 2604 zap-shader {
2941 memory-region 2605 memory-region = <&gpu_mem>;
2942 }; 2606 };
2943 2607
2944 gpu_opp_table: opp-ta 2608 gpu_opp_table: opp-table {
2945 compatible = 2609 compatible = "operating-points-v2";
2946 2610
2947 opp-670000000 2611 opp-670000000 {
2948 opp-h 2612 opp-hz = /bits/ 64 <670000000>;
2949 opp-l 2613 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2950 opp-s 2614 opp-supported-hw = <0xa>;
2951 }; 2615 };
2952 2616
2953 opp-587000000 2617 opp-587000000 {
2954 opp-h 2618 opp-hz = /bits/ 64 <587000000>;
2955 opp-l 2619 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2956 opp-s 2620 opp-supported-hw = <0xb>;
2957 }; 2621 };
2958 2622
2959 opp-525000000 2623 opp-525000000 {
2960 opp-h 2624 opp-hz = /bits/ 64 <525000000>;
2961 opp-l 2625 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2962 opp-s 2626 opp-supported-hw = <0xf>;
2963 }; 2627 };
2964 2628
2965 opp-490000000 2629 opp-490000000 {
2966 opp-h 2630 opp-hz = /bits/ 64 <490000000>;
2967 opp-l 2631 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2968 opp-s 2632 opp-supported-hw = <0xf>;
2969 }; 2633 };
2970 2634
2971 opp-441600000 2635 opp-441600000 {
2972 opp-h 2636 opp-hz = /bits/ 64 <441600000>;
2973 opp-l 2637 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
2974 opp-s 2638 opp-supported-hw = <0xf>;
2975 }; 2639 };
2976 2640
2977 opp-400000000 2641 opp-400000000 {
2978 opp-h 2642 opp-hz = /bits/ 64 <400000000>;
2979 opp-l 2643 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2980 opp-s 2644 opp-supported-hw = <0xf>;
2981 }; 2645 };
2982 2646
2983 opp-305000000 2647 opp-305000000 {
2984 opp-h 2648 opp-hz = /bits/ 64 <305000000>;
2985 opp-l 2649 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2986 opp-s 2650 opp-supported-hw = <0xf>;
2987 }; 2651 };
2988 }; 2652 };
2989 }; 2653 };
2990 2654
2991 gmu: gmu@3d6a000 { 2655 gmu: gmu@3d6a000 {
2992 compatible = "qcom,ad 2656 compatible = "qcom,adreno-gmu-650.2", "qcom,adreno-gmu";
2993 2657
2994 reg = <0 0x03d6a000 0 2658 reg = <0 0x03d6a000 0 0x30000>,
2995 <0 0x3de0000 0 2659 <0 0x3de0000 0 0x10000>,
2996 <0 0xb290000 0 2660 <0 0xb290000 0 0x10000>,
2997 <0 0xb490000 0 2661 <0 0xb490000 0 0x10000>;
2998 reg-names = "gmu", "r 2662 reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq";
2999 2663
3000 interrupts = <GIC_SPI 2664 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
3001 <GIC_SPI 2665 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
3002 interrupt-names = "hf 2666 interrupt-names = "hfi", "gmu";
3003 2667
3004 clocks = <&gpucc GPU_ 2668 clocks = <&gpucc GPU_CC_AHB_CLK>,
3005 <&gpucc GPU_ 2669 <&gpucc GPU_CC_CX_GMU_CLK>,
3006 <&gpucc GPU_ 2670 <&gpucc GPU_CC_CXO_CLK>,
3007 <&gcc GCC_DD 2671 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
3008 <&gcc GCC_GP 2672 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
3009 clock-names = "ahb", 2673 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
3010 2674
3011 power-domains = <&gpu 2675 power-domains = <&gpucc GPU_CX_GDSC>,
3012 <&gpu 2676 <&gpucc GPU_GX_GDSC>;
3013 power-domain-names = 2677 power-domain-names = "cx", "gx";
3014 2678
3015 iommus = <&adreno_smm 2679 iommus = <&adreno_smmu 5 0x400>;
3016 2680
3017 operating-points-v2 = 2681 operating-points-v2 = <&gmu_opp_table>;
3018 2682
3019 status = "disabled"; 2683 status = "disabled";
3020 2684
3021 gmu_opp_table: opp-ta 2685 gmu_opp_table: opp-table {
3022 compatible = 2686 compatible = "operating-points-v2";
3023 2687
3024 opp-200000000 2688 opp-200000000 {
3025 opp-h 2689 opp-hz = /bits/ 64 <200000000>;
3026 opp-l 2690 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3027 }; 2691 };
3028 }; 2692 };
3029 }; 2693 };
3030 2694
3031 gpucc: clock-controller@3d900 2695 gpucc: clock-controller@3d90000 {
3032 compatible = "qcom,sm 2696 compatible = "qcom,sm8250-gpucc";
3033 reg = <0 0x03d90000 0 2697 reg = <0 0x03d90000 0 0x9000>;
3034 clocks = <&rpmhcc RPM 2698 clocks = <&rpmhcc RPMH_CXO_CLK>,
3035 <&gcc GCC_GP 2699 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
3036 <&gcc GCC_GP 2700 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
3037 clock-names = "bi_tcx 2701 clock-names = "bi_tcxo",
3038 "gcc_gp 2702 "gcc_gpu_gpll0_clk_src",
3039 "gcc_gp 2703 "gcc_gpu_gpll0_div_clk_src";
3040 #clock-cells = <1>; 2704 #clock-cells = <1>;
3041 #reset-cells = <1>; 2705 #reset-cells = <1>;
3042 #power-domain-cells = 2706 #power-domain-cells = <1>;
3043 }; 2707 };
3044 2708
3045 adreno_smmu: iommu@3da0000 { 2709 adreno_smmu: iommu@3da0000 {
3046 compatible = "qcom,sm 2710 compatible = "qcom,sm8250-smmu-500", "qcom,adreno-smmu",
3047 "qcom,sm 2711 "qcom,smmu-500", "arm,mmu-500";
3048 reg = <0 0x03da0000 0 2712 reg = <0 0x03da0000 0 0x10000>;
3049 #iommu-cells = <2>; 2713 #iommu-cells = <2>;
3050 #global-interrupts = 2714 #global-interrupts = <2>;
3051 interrupts = <GIC_SPI 2715 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
3052 <GIC_SPI 2716 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
3053 <GIC_SPI 2717 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
3054 <GIC_SPI 2718 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
3055 <GIC_SPI 2719 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
3056 <GIC_SPI 2720 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
3057 <GIC_SPI 2721 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
3058 <GIC_SPI 2722 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
3059 <GIC_SPI 2723 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
3060 <GIC_SPI 2724 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>;
3061 clocks = <&gpucc GPU_ 2725 clocks = <&gpucc GPU_CC_AHB_CLK>,
3062 <&gcc GCC_GP 2726 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
3063 <&gcc GCC_GP 2727 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
3064 clock-names = "ahb", 2728 clock-names = "ahb", "bus", "iface";
3065 2729
3066 power-domains = <&gpu 2730 power-domains = <&gpucc GPU_CX_GDSC>;
3067 dma-coherent; 2731 dma-coherent;
3068 }; 2732 };
3069 2733
3070 slpi: remoteproc@5c00000 { 2734 slpi: remoteproc@5c00000 {
3071 compatible = "qcom,sm 2735 compatible = "qcom,sm8250-slpi-pas";
3072 reg = <0 0x05c00000 0 2736 reg = <0 0x05c00000 0 0x4000>;
3073 2737
3074 interrupts-extended = !! 2738 interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
3075 2739 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
3076 2740 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
3077 2741 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
3078 2742 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
3079 interrupt-names = "wd 2743 interrupt-names = "wdog", "fatal", "ready",
3080 "ha 2744 "handover", "stop-ack";
3081 2745
3082 clocks = <&rpmhcc RPM 2746 clocks = <&rpmhcc RPMH_CXO_CLK>;
3083 clock-names = "xo"; 2747 clock-names = "xo";
3084 2748
3085 power-domains = <&rpm 2749 power-domains = <&rpmhpd RPMHPD_LCX>,
3086 <&rpm 2750 <&rpmhpd RPMHPD_LMX>;
3087 power-domain-names = 2751 power-domain-names = "lcx", "lmx";
3088 2752
3089 memory-region = <&slp 2753 memory-region = <&slpi_mem>;
3090 2754
3091 qcom,qmp = <&aoss_qmp 2755 qcom,qmp = <&aoss_qmp>;
3092 2756
3093 qcom,smem-states = <& 2757 qcom,smem-states = <&smp2p_slpi_out 0>;
3094 qcom,smem-state-names 2758 qcom,smem-state-names = "stop";
3095 2759
3096 status = "disabled"; 2760 status = "disabled";
3097 2761
3098 glink-edge { 2762 glink-edge {
3099 interrupts-ex 2763 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
3100 2764 IPCC_MPROC_SIGNAL_GLINK_QMP
3101 2765 IRQ_TYPE_EDGE_RISING>;
3102 mboxes = <&ip 2766 mboxes = <&ipcc IPCC_CLIENT_SLPI
3103 2767 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3104 2768
3105 label = "slpi 2769 label = "slpi";
3106 qcom,remote-p 2770 qcom,remote-pid = <3>;
3107 2771
3108 fastrpc { 2772 fastrpc {
3109 compa 2773 compatible = "qcom,fastrpc";
3110 qcom, 2774 qcom,glink-channels = "fastrpcglink-apps-dsp";
3111 label 2775 label = "sdsp";
3112 qcom, 2776 qcom,non-secure-domain;
3113 #addr 2777 #address-cells = <1>;
3114 #size 2778 #size-cells = <0>;
3115 2779
3116 compu 2780 compute-cb@1 {
3117 2781 compatible = "qcom,fastrpc-compute-cb";
3118 2782 reg = <1>;
3119 2783 iommus = <&apps_smmu 0x0541 0x0>;
3120 }; 2784 };
3121 2785
3122 compu 2786 compute-cb@2 {
3123 2787 compatible = "qcom,fastrpc-compute-cb";
3124 2788 reg = <2>;
3125 2789 iommus = <&apps_smmu 0x0542 0x0>;
3126 }; 2790 };
3127 2791
3128 compu 2792 compute-cb@3 {
3129 2793 compatible = "qcom,fastrpc-compute-cb";
3130 2794 reg = <3>;
3131 2795 iommus = <&apps_smmu 0x0543 0x0>;
3132 2796 /* note: shared-cb = <4> in downstream */
3133 }; 2797 };
3134 }; 2798 };
3135 }; 2799 };
3136 }; 2800 };
3137 2801
3138 stm@6002000 { 2802 stm@6002000 {
3139 compatible = "arm,cor 2803 compatible = "arm,coresight-stm", "arm,primecell";
3140 reg = <0 0x06002000 0 2804 reg = <0 0x06002000 0 0x1000>, <0 0x16280000 0 0x180000>;
3141 reg-names = "stm-base 2805 reg-names = "stm-base", "stm-stimulus-base";
3142 2806
3143 clocks = <&aoss_qmp>; 2807 clocks = <&aoss_qmp>;
3144 clock-names = "apb_pc 2808 clock-names = "apb_pclk";
3145 2809
3146 out-ports { 2810 out-ports {
3147 port { 2811 port {
3148 stm_o 2812 stm_out: endpoint {
3149 2813 remote-endpoint = <&funnel0_in7>;
3150 }; 2814 };
3151 }; 2815 };
3152 }; 2816 };
3153 }; 2817 };
3154 2818
3155 tpda@6004000 { 2819 tpda@6004000 {
3156 compatible = "qcom,co 2820 compatible = "qcom,coresight-tpda", "arm,primecell";
3157 reg = <0 0x06004000 0 2821 reg = <0 0x06004000 0 0x1000>;
3158 2822
3159 clocks = <&aoss_qmp>; 2823 clocks = <&aoss_qmp>;
3160 clock-names = "apb_pc 2824 clock-names = "apb_pclk";
3161 2825
3162 out-ports { 2826 out-ports {
3163 2827
3164 port { 2828 port {
3165 tpda_ 2829 tpda_out_funnel_qatb: endpoint {
3166 2830 remote-endpoint = <&funnel_qatb_in_tpda>;
3167 }; 2831 };
3168 }; 2832 };
3169 }; 2833 };
3170 2834
3171 in-ports { 2835 in-ports {
3172 #address-cell 2836 #address-cells = <1>;
3173 #size-cells = 2837 #size-cells = <0>;
3174 2838
3175 port@9 { 2839 port@9 {
3176 reg = 2840 reg = <9>;
3177 tpda_ 2841 tpda_9_in_tpdm_mm: endpoint {
3178 2842 remote-endpoint = <&tpdm_mm_out_tpda9>;
3179 }; 2843 };
3180 }; 2844 };
3181 2845
3182 port@17 { 2846 port@17 {
3183 reg = 2847 reg = <23>;
3184 tpda_ 2848 tpda_23_in_tpdm_prng: endpoint {
3185 2849 remote-endpoint = <&tpdm_prng_out_tpda_23>;
3186 }; 2850 };
3187 }; 2851 };
3188 }; 2852 };
3189 }; 2853 };
3190 2854
3191 funnel@6005000 { 2855 funnel@6005000 {
3192 compatible = "arm,cor 2856 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3193 reg = <0 0x06005000 0 2857 reg = <0 0x06005000 0 0x1000>;
3194 2858
3195 clocks = <&aoss_qmp>; 2859 clocks = <&aoss_qmp>;
3196 clock-names = "apb_pc 2860 clock-names = "apb_pclk";
3197 2861
3198 out-ports { 2862 out-ports {
3199 port { 2863 port {
3200 funne 2864 funnel_qatb_out_funnel_in0: endpoint {
3201 2865 remote-endpoint = <&funnel_in0_in_funnel_qatb>;
3202 }; 2866 };
3203 }; 2867 };
3204 }; 2868 };
3205 2869
3206 in-ports { 2870 in-ports {
3207 port { 2871 port {
3208 funne 2872 funnel_qatb_in_tpda: endpoint {
3209 2873 remote-endpoint = <&tpda_out_funnel_qatb>;
3210 }; 2874 };
3211 }; 2875 };
3212 }; 2876 };
3213 }; 2877 };
3214 2878
3215 funnel@6041000 { 2879 funnel@6041000 {
3216 compatible = "arm,cor 2880 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3217 reg = <0 0x06041000 0 2881 reg = <0 0x06041000 0 0x1000>;
3218 2882
3219 clocks = <&aoss_qmp>; 2883 clocks = <&aoss_qmp>;
3220 clock-names = "apb_pc 2884 clock-names = "apb_pclk";
3221 2885
3222 out-ports { 2886 out-ports {
3223 port { 2887 port {
3224 funne 2888 funnel_in0_out_funnel_merg: endpoint {
3225 2889 remote-endpoint = <&funnel_merg_in_funnel_in0>;
3226 }; 2890 };
3227 }; 2891 };
3228 }; 2892 };
3229 2893
3230 in-ports { 2894 in-ports {
3231 #address-cell 2895 #address-cells = <1>;
3232 #size-cells = 2896 #size-cells = <0>;
3233 2897
3234 port@6 { 2898 port@6 {
3235 reg = 2899 reg = <6>;
3236 funne 2900 funnel_in0_in_funnel_qatb: endpoint {
3237 2901 remote-endpoint = <&funnel_qatb_out_funnel_in0>;
3238 }; 2902 };
3239 }; 2903 };
3240 2904
3241 port@7 { 2905 port@7 {
3242 reg = 2906 reg = <7>;
3243 funne 2907 funnel0_in7: endpoint {
3244 2908 remote-endpoint = <&stm_out>;
3245 }; 2909 };
3246 }; 2910 };
3247 }; 2911 };
3248 }; 2912 };
3249 2913
3250 funnel@6042000 { 2914 funnel@6042000 {
3251 compatible = "arm,cor 2915 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3252 reg = <0 0x06042000 0 2916 reg = <0 0x06042000 0 0x1000>;
3253 2917
3254 clocks = <&aoss_qmp>; 2918 clocks = <&aoss_qmp>;
3255 clock-names = "apb_pc 2919 clock-names = "apb_pclk";
3256 2920
3257 out-ports { 2921 out-ports {
3258 port { 2922 port {
3259 funne 2923 funnel_in1_out_funnel_merg: endpoint {
3260 2924 remote-endpoint = <&funnel_merg_in_funnel_in1>;
3261 }; 2925 };
3262 }; 2926 };
3263 }; 2927 };
3264 2928
3265 in-ports { 2929 in-ports {
3266 #address-cell 2930 #address-cells = <1>;
3267 #size-cells = 2931 #size-cells = <0>;
3268 2932
3269 port@4 { 2933 port@4 {
3270 reg = 2934 reg = <4>;
3271 funne 2935 funnel_in1_in_funnel_apss_merg: endpoint {
3272 remot 2936 remote-endpoint = <&funnel_apss_merg_out_funnel_in1>;
3273 }; 2937 };
3274 }; 2938 };
3275 }; 2939 };
3276 }; 2940 };
3277 2941
3278 funnel@6045000 { 2942 funnel@6045000 {
3279 compatible = "arm,cor 2943 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3280 reg = <0 0x06045000 0 2944 reg = <0 0x06045000 0 0x1000>;
3281 2945
3282 clocks = <&aoss_qmp>; 2946 clocks = <&aoss_qmp>;
3283 clock-names = "apb_pc 2947 clock-names = "apb_pclk";
3284 2948
3285 out-ports { 2949 out-ports {
3286 port { 2950 port {
3287 funne 2951 funnel_merg_out_funnel_swao: endpoint {
3288 remot 2952 remote-endpoint = <&funnel_swao_in_funnel_merg>;
3289 }; 2953 };
3290 }; 2954 };
3291 }; 2955 };
3292 2956
3293 in-ports { 2957 in-ports {
3294 #address-cell 2958 #address-cells = <1>;
3295 #size-cells = 2959 #size-cells = <0>;
3296 2960
3297 port@0 { 2961 port@0 {
3298 reg = 2962 reg = <0>;
3299 funne 2963 funnel_merg_in_funnel_in0: endpoint {
3300 remot 2964 remote-endpoint = <&funnel_in0_out_funnel_merg>;
3301 }; 2965 };
3302 }; 2966 };
3303 2967
3304 port@1 { 2968 port@1 {
3305 reg = 2969 reg = <1>;
3306 funne 2970 funnel_merg_in_funnel_in1: endpoint {
3307 remot 2971 remote-endpoint = <&funnel_in1_out_funnel_merg>;
3308 }; 2972 };
3309 }; 2973 };
3310 }; 2974 };
3311 }; 2975 };
3312 2976
3313 replicator@6046000 { 2977 replicator@6046000 {
3314 compatible = "arm,cor 2978 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3315 reg = <0 0x06046000 0 2979 reg = <0 0x06046000 0 0x1000>;
3316 2980
3317 clocks = <&aoss_qmp>; 2981 clocks = <&aoss_qmp>;
3318 clock-names = "apb_pc 2982 clock-names = "apb_pclk";
3319 2983
3320 out-ports { 2984 out-ports {
3321 port { 2985 port {
3322 repli 2986 replicator_out: endpoint {
3323 2987 remote-endpoint = <&etr_in>;
3324 }; 2988 };
3325 }; 2989 };
3326 }; 2990 };
3327 2991
3328 in-ports { 2992 in-ports {
3329 port { 2993 port {
3330 repli 2994 replicator_cx_in_swao_out: endpoint {
3331 2995 remote-endpoint = <&replicator_swao_out_cx_in>;
3332 }; 2996 };
3333 }; 2997 };
3334 }; 2998 };
3335 }; 2999 };
3336 3000
3337 etr@6048000 { 3001 etr@6048000 {
3338 compatible = "arm,cor 3002 compatible = "arm,coresight-tmc", "arm,primecell";
3339 reg = <0 0x06048000 0 3003 reg = <0 0x06048000 0 0x1000>;
3340 3004
3341 clocks = <&aoss_qmp>; 3005 clocks = <&aoss_qmp>;
3342 clock-names = "apb_pc 3006 clock-names = "apb_pclk";
3343 arm,scatter-gather; 3007 arm,scatter-gather;
3344 3008
3345 in-ports { 3009 in-ports {
3346 port { 3010 port {
3347 etr_i 3011 etr_in: endpoint {
3348 3012 remote-endpoint = <&replicator_out>;
3349 }; 3013 };
3350 }; 3014 };
3351 }; 3015 };
3352 }; 3016 };
3353 3017
3354 tpdm@684c000 { 3018 tpdm@684c000 {
3355 compatible = "qcom,co 3019 compatible = "qcom,coresight-tpdm", "arm,primecell";
3356 reg = <0 0x0684c000 0 3020 reg = <0 0x0684c000 0 0x1000>;
3357 3021
3358 clocks = <&aoss_qmp>; 3022 clocks = <&aoss_qmp>;
3359 clock-names = "apb_pc 3023 clock-names = "apb_pclk";
3360 3024
3361 out-ports { 3025 out-ports {
3362 port { 3026 port {
3363 tpdm_ 3027 tpdm_prng_out_tpda_23: endpoint {
3364 3028 remote-endpoint = <&tpda_23_in_tpdm_prng>;
3365 }; 3029 };
3366 }; 3030 };
3367 }; 3031 };
3368 }; 3032 };
3369 3033
3370 funnel@6b04000 { 3034 funnel@6b04000 {
3371 compatible = "arm,cor 3035 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3372 arm,primecell-periphi 3036 arm,primecell-periphid = <0x000bb908>;
3373 3037
3374 reg = <0 0x06b04000 0 3038 reg = <0 0x06b04000 0 0x1000>;
3375 3039
3376 clocks = <&aoss_qmp>; 3040 clocks = <&aoss_qmp>;
3377 clock-names = "apb_pc 3041 clock-names = "apb_pclk";
3378 3042
3379 out-ports { 3043 out-ports {
3380 port { 3044 port {
3381 funne 3045 funnel_swao_out_etf: endpoint {
3382 3046 remote-endpoint = <&etf_in_funnel_swao_out>;
3383 }; 3047 };
3384 }; 3048 };
3385 }; 3049 };
3386 3050
3387 in-ports { 3051 in-ports {
3388 #address-cell 3052 #address-cells = <1>;
3389 #size-cells = 3053 #size-cells = <0>;
3390 3054
3391 port@7 { 3055 port@7 {
3392 reg = 3056 reg = <7>;
3393 funne 3057 funnel_swao_in_funnel_merg: endpoint {
3394 3058 remote-endpoint = <&funnel_merg_out_funnel_swao>;
3395 }; 3059 };
3396 }; 3060 };
3397 }; 3061 };
3398 }; 3062 };
3399 3063
3400 etf@6b05000 { 3064 etf@6b05000 {
3401 compatible = "arm,cor 3065 compatible = "arm,coresight-tmc", "arm,primecell";
3402 reg = <0 0x06b05000 0 3066 reg = <0 0x06b05000 0 0x1000>;
3403 3067
3404 clocks = <&aoss_qmp>; 3068 clocks = <&aoss_qmp>;
3405 clock-names = "apb_pc 3069 clock-names = "apb_pclk";
3406 3070
3407 out-ports { 3071 out-ports {
3408 port { 3072 port {
3409 etf_o 3073 etf_out: endpoint {
3410 3074 remote-endpoint = <&replicator_in>;
3411 }; 3075 };
3412 }; 3076 };
3413 }; 3077 };
3414 3078
3415 in-ports { 3079 in-ports {
3416 3080
3417 port { 3081 port {
3418 etf_i 3082 etf_in_funnel_swao_out: endpoint {
3419 3083 remote-endpoint = <&funnel_swao_out_etf>;
3420 }; 3084 };
3421 }; 3085 };
3422 }; 3086 };
3423 }; 3087 };
3424 3088
3425 replicator@6b06000 { 3089 replicator@6b06000 {
3426 compatible = "arm,cor 3090 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3427 reg = <0 0x06b06000 0 3091 reg = <0 0x06b06000 0 0x1000>;
3428 3092
3429 clocks = <&aoss_qmp>; 3093 clocks = <&aoss_qmp>;
3430 clock-names = "apb_pc 3094 clock-names = "apb_pclk";
3431 3095
3432 out-ports { 3096 out-ports {
3433 port { 3097 port {
3434 repli 3098 replicator_swao_out_cx_in: endpoint {
3435 3099 remote-endpoint = <&replicator_cx_in_swao_out>;
3436 }; 3100 };
3437 }; 3101 };
3438 }; 3102 };
3439 3103
3440 in-ports { 3104 in-ports {
3441 port { 3105 port {
3442 repli 3106 replicator_in: endpoint {
3443 3107 remote-endpoint = <&etf_out>;
3444 }; 3108 };
3445 }; 3109 };
3446 }; 3110 };
3447 }; 3111 };
3448 3112
3449 tpdm@6c08000 { 3113 tpdm@6c08000 {
3450 compatible = "qcom,co 3114 compatible = "qcom,coresight-tpdm", "arm,primecell";
3451 reg = <0 0x06c08000 0 3115 reg = <0 0x06c08000 0 0x1000>;
3452 3116
3453 clocks = <&aoss_qmp>; 3117 clocks = <&aoss_qmp>;
3454 clock-names = "apb_pc 3118 clock-names = "apb_pclk";
3455 3119
3456 out-ports { 3120 out-ports {
3457 port { 3121 port {
3458 tpdm_ 3122 tpdm_mm_out_funnel_dl_mm: endpoint {
3459 3123 remote-endpoint = <&funnel_dl_mm_in_tpdm_mm>;
3460 }; 3124 };
3461 }; 3125 };
3462 }; 3126 };
3463 }; 3127 };
3464 3128
3465 funnel@6c0b000 { 3129 funnel@6c0b000 {
3466 compatible = "arm,cor 3130 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3467 reg = <0 0x06c0b000 0 3131 reg = <0 0x06c0b000 0 0x1000>;
3468 3132
3469 clocks = <&aoss_qmp>; 3133 clocks = <&aoss_qmp>;
3470 clock-names = "apb_pc 3134 clock-names = "apb_pclk";
3471 3135
3472 out-ports { 3136 out-ports {
3473 port { 3137 port {
3474 funne 3138 funnel_dl_mm_out_funnel_dl_center: endpoint {
3475 remot 3139 remote-endpoint = <&funnel_dl_center_in_funnel_dl_mm>;
3476 }; 3140 };
3477 }; 3141 };
3478 }; 3142 };
3479 3143
3480 in-ports { 3144 in-ports {
3481 #address-cell 3145 #address-cells = <1>;
3482 #size-cells = 3146 #size-cells = <0>;
3483 3147
3484 port@3 { 3148 port@3 {
3485 reg = 3149 reg = <3>;
3486 funne 3150 funnel_dl_mm_in_tpdm_mm: endpoint {
3487 3151 remote-endpoint = <&tpdm_mm_out_funnel_dl_mm>;
3488 }; 3152 };
3489 }; 3153 };
3490 }; 3154 };
3491 }; 3155 };
3492 3156
3493 funnel@6c2d000 { 3157 funnel@6c2d000 {
3494 compatible = "arm,cor 3158 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3495 reg = <0 0x06c2d000 0 3159 reg = <0 0x06c2d000 0 0x1000>;
3496 3160
3497 clocks = <&aoss_qmp>; 3161 clocks = <&aoss_qmp>;
3498 clock-names = "apb_pc 3162 clock-names = "apb_pclk";
3499 3163
3500 out-ports { 3164 out-ports {
3501 port { 3165 port {
3502 tpdm_ 3166 tpdm_mm_out_tpda9: endpoint {
3503 3167 remote-endpoint = <&tpda_9_in_tpdm_mm>;
3504 }; 3168 };
3505 }; 3169 };
3506 }; 3170 };
3507 3171
3508 in-ports { 3172 in-ports {
3509 #address-cell 3173 #address-cells = <1>;
3510 #size-cells = 3174 #size-cells = <0>;
3511 3175
3512 port@2 { 3176 port@2 {
3513 reg = 3177 reg = <2>;
3514 funne 3178 funnel_dl_center_in_funnel_dl_mm: endpoint {
3515 remot 3179 remote-endpoint = <&funnel_dl_mm_out_funnel_dl_center>;
3516 }; 3180 };
3517 }; 3181 };
3518 }; 3182 };
3519 }; 3183 };
3520 3184
3521 etm@7040000 { 3185 etm@7040000 {
3522 compatible = "arm,cor 3186 compatible = "arm,coresight-etm4x", "arm,primecell";
3523 reg = <0 0x07040000 0 3187 reg = <0 0x07040000 0 0x1000>;
3524 3188
3525 cpu = <&CPU0>; 3189 cpu = <&CPU0>;
3526 3190
3527 clocks = <&aoss_qmp>; 3191 clocks = <&aoss_qmp>;
3528 clock-names = "apb_pc 3192 clock-names = "apb_pclk";
3529 arm,coresight-loses-c 3193 arm,coresight-loses-context-with-cpu;
3530 3194
3531 out-ports { 3195 out-ports {
3532 port { 3196 port {
3533 etm0_ 3197 etm0_out: endpoint {
3534 3198 remote-endpoint = <&apss_funnel_in0>;
3535 }; 3199 };
3536 }; 3200 };
3537 }; 3201 };
3538 }; 3202 };
3539 3203
3540 etm@7140000 { 3204 etm@7140000 {
3541 compatible = "arm,cor 3205 compatible = "arm,coresight-etm4x", "arm,primecell";
3542 reg = <0 0x07140000 0 3206 reg = <0 0x07140000 0 0x1000>;
3543 3207
3544 cpu = <&CPU1>; 3208 cpu = <&CPU1>;
3545 3209
3546 clocks = <&aoss_qmp>; 3210 clocks = <&aoss_qmp>;
3547 clock-names = "apb_pc 3211 clock-names = "apb_pclk";
3548 arm,coresight-loses-c 3212 arm,coresight-loses-context-with-cpu;
3549 3213
3550 out-ports { 3214 out-ports {
3551 port { 3215 port {
3552 etm1_ 3216 etm1_out: endpoint {
3553 3217 remote-endpoint = <&apss_funnel_in1>;
3554 }; 3218 };
3555 }; 3219 };
3556 }; 3220 };
3557 }; 3221 };
3558 3222
3559 etm@7240000 { 3223 etm@7240000 {
3560 compatible = "arm,cor 3224 compatible = "arm,coresight-etm4x", "arm,primecell";
3561 reg = <0 0x07240000 0 3225 reg = <0 0x07240000 0 0x1000>;
3562 3226
3563 cpu = <&CPU2>; 3227 cpu = <&CPU2>;
3564 3228
3565 clocks = <&aoss_qmp>; 3229 clocks = <&aoss_qmp>;
3566 clock-names = "apb_pc 3230 clock-names = "apb_pclk";
3567 arm,coresight-loses-c 3231 arm,coresight-loses-context-with-cpu;
3568 3232
3569 out-ports { 3233 out-ports {
3570 port { 3234 port {
3571 etm2_ 3235 etm2_out: endpoint {
3572 3236 remote-endpoint = <&apss_funnel_in2>;
3573 }; 3237 };
3574 }; 3238 };
3575 }; 3239 };
3576 }; 3240 };
3577 3241
3578 etm@7340000 { 3242 etm@7340000 {
3579 compatible = "arm,cor 3243 compatible = "arm,coresight-etm4x", "arm,primecell";
3580 reg = <0 0x07340000 0 3244 reg = <0 0x07340000 0 0x1000>;
3581 3245
3582 cpu = <&CPU3>; 3246 cpu = <&CPU3>;
3583 3247
3584 clocks = <&aoss_qmp>; 3248 clocks = <&aoss_qmp>;
3585 clock-names = "apb_pc 3249 clock-names = "apb_pclk";
3586 arm,coresight-loses-c 3250 arm,coresight-loses-context-with-cpu;
3587 3251
3588 out-ports { 3252 out-ports {
3589 port { 3253 port {
3590 etm3_ 3254 etm3_out: endpoint {
3591 3255 remote-endpoint = <&apss_funnel_in3>;
3592 }; 3256 };
3593 }; 3257 };
3594 }; 3258 };
3595 }; 3259 };
3596 3260
3597 etm@7440000 { 3261 etm@7440000 {
3598 compatible = "arm,cor 3262 compatible = "arm,coresight-etm4x", "arm,primecell";
3599 reg = <0 0x07440000 0 3263 reg = <0 0x07440000 0 0x1000>;
3600 3264
3601 cpu = <&CPU4>; 3265 cpu = <&CPU4>;
3602 3266
3603 clocks = <&aoss_qmp>; 3267 clocks = <&aoss_qmp>;
3604 clock-names = "apb_pc 3268 clock-names = "apb_pclk";
3605 arm,coresight-loses-c 3269 arm,coresight-loses-context-with-cpu;
3606 3270
3607 out-ports { 3271 out-ports {
3608 port { 3272 port {
3609 etm4_ 3273 etm4_out: endpoint {
3610 3274 remote-endpoint = <&apss_funnel_in4>;
3611 }; 3275 };
3612 }; 3276 };
3613 }; 3277 };
3614 }; 3278 };
3615 3279
3616 etm@7540000 { 3280 etm@7540000 {
3617 compatible = "arm,cor 3281 compatible = "arm,coresight-etm4x", "arm,primecell";
3618 reg = <0 0x07540000 0 3282 reg = <0 0x07540000 0 0x1000>;
3619 3283
3620 cpu = <&CPU5>; 3284 cpu = <&CPU5>;
3621 3285
3622 clocks = <&aoss_qmp>; 3286 clocks = <&aoss_qmp>;
3623 clock-names = "apb_pc 3287 clock-names = "apb_pclk";
3624 arm,coresight-loses-c 3288 arm,coresight-loses-context-with-cpu;
3625 3289
3626 out-ports { 3290 out-ports {
3627 port { 3291 port {
3628 etm5_ 3292 etm5_out: endpoint {
3629 3293 remote-endpoint = <&apss_funnel_in5>;
3630 }; 3294 };
3631 }; 3295 };
3632 }; 3296 };
3633 }; 3297 };
3634 3298
3635 etm@7640000 { 3299 etm@7640000 {
3636 compatible = "arm,cor 3300 compatible = "arm,coresight-etm4x", "arm,primecell";
3637 reg = <0 0x07640000 0 3301 reg = <0 0x07640000 0 0x1000>;
3638 3302
3639 cpu = <&CPU6>; 3303 cpu = <&CPU6>;
3640 3304
3641 clocks = <&aoss_qmp>; 3305 clocks = <&aoss_qmp>;
3642 clock-names = "apb_pc 3306 clock-names = "apb_pclk";
3643 arm,coresight-loses-c 3307 arm,coresight-loses-context-with-cpu;
3644 3308
3645 out-ports { 3309 out-ports {
3646 port { 3310 port {
3647 etm6_ 3311 etm6_out: endpoint {
3648 3312 remote-endpoint = <&apss_funnel_in6>;
3649 }; 3313 };
3650 }; 3314 };
3651 }; 3315 };
3652 }; 3316 };
3653 3317
3654 etm@7740000 { 3318 etm@7740000 {
3655 compatible = "arm,cor 3319 compatible = "arm,coresight-etm4x", "arm,primecell";
3656 reg = <0 0x07740000 0 3320 reg = <0 0x07740000 0 0x1000>;
3657 3321
3658 cpu = <&CPU7>; 3322 cpu = <&CPU7>;
3659 3323
3660 clocks = <&aoss_qmp>; 3324 clocks = <&aoss_qmp>;
3661 clock-names = "apb_pc 3325 clock-names = "apb_pclk";
3662 arm,coresight-loses-c 3326 arm,coresight-loses-context-with-cpu;
3663 3327
3664 out-ports { 3328 out-ports {
3665 port { 3329 port {
3666 etm7_ 3330 etm7_out: endpoint {
3667 3331 remote-endpoint = <&apss_funnel_in7>;
3668 }; 3332 };
3669 }; 3333 };
3670 }; 3334 };
3671 }; 3335 };
3672 3336
3673 funnel@7800000 { 3337 funnel@7800000 {
3674 compatible = "arm,cor 3338 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3675 reg = <0 0x07800000 0 3339 reg = <0 0x07800000 0 0x1000>;
3676 3340
3677 clocks = <&aoss_qmp>; 3341 clocks = <&aoss_qmp>;
3678 clock-names = "apb_pc 3342 clock-names = "apb_pclk";
3679 3343
3680 out-ports { 3344 out-ports {
3681 port { 3345 port {
3682 funne 3346 funnel_apss_out_funnel_apss_merg: endpoint {
3683 remot 3347 remote-endpoint = <&funnel_apss_merg_in_funnel_apss>;
3684 }; 3348 };
3685 }; 3349 };
3686 }; 3350 };
3687 3351
3688 in-ports { 3352 in-ports {
3689 #address-cell 3353 #address-cells = <1>;
3690 #size-cells = 3354 #size-cells = <0>;
3691 3355
3692 port@0 { 3356 port@0 {
3693 reg = 3357 reg = <0>;
3694 apss_ 3358 apss_funnel_in0: endpoint {
3695 3359 remote-endpoint = <&etm0_out>;
3696 }; 3360 };
3697 }; 3361 };
3698 3362
3699 port@1 { 3363 port@1 {
3700 reg = 3364 reg = <1>;
3701 apss_ 3365 apss_funnel_in1: endpoint {
3702 3366 remote-endpoint = <&etm1_out>;
3703 }; 3367 };
3704 }; 3368 };
3705 3369
3706 port@2 { 3370 port@2 {
3707 reg = 3371 reg = <2>;
3708 apss_ 3372 apss_funnel_in2: endpoint {
3709 3373 remote-endpoint = <&etm2_out>;
3710 }; 3374 };
3711 }; 3375 };
3712 3376
3713 port@3 { 3377 port@3 {
3714 reg = 3378 reg = <3>;
3715 apss_ 3379 apss_funnel_in3: endpoint {
3716 3380 remote-endpoint = <&etm3_out>;
3717 }; 3381 };
3718 }; 3382 };
3719 3383
3720 port@4 { 3384 port@4 {
3721 reg = 3385 reg = <4>;
3722 apss_ 3386 apss_funnel_in4: endpoint {
3723 3387 remote-endpoint = <&etm4_out>;
3724 }; 3388 };
3725 }; 3389 };
3726 3390
3727 port@5 { 3391 port@5 {
3728 reg = 3392 reg = <5>;
3729 apss_ 3393 apss_funnel_in5: endpoint {
3730 3394 remote-endpoint = <&etm5_out>;
3731 }; 3395 };
3732 }; 3396 };
3733 3397
3734 port@6 { 3398 port@6 {
3735 reg = 3399 reg = <6>;
3736 apss_ 3400 apss_funnel_in6: endpoint {
3737 3401 remote-endpoint = <&etm6_out>;
3738 }; 3402 };
3739 }; 3403 };
3740 3404
3741 port@7 { 3405 port@7 {
3742 reg = 3406 reg = <7>;
3743 apss_ 3407 apss_funnel_in7: endpoint {
3744 3408 remote-endpoint = <&etm7_out>;
3745 }; 3409 };
3746 }; 3410 };
3747 }; 3411 };
3748 }; 3412 };
3749 3413
3750 funnel@7810000 { 3414 funnel@7810000 {
3751 compatible = "arm,cor 3415 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3752 reg = <0 0x07810000 0 3416 reg = <0 0x07810000 0 0x1000>;
3753 3417
3754 clocks = <&aoss_qmp>; 3418 clocks = <&aoss_qmp>;
3755 clock-names = "apb_pc 3419 clock-names = "apb_pclk";
3756 3420
3757 out-ports { 3421 out-ports {
3758 port { 3422 port {
3759 funne 3423 funnel_apss_merg_out_funnel_in1: endpoint {
3760 remot 3424 remote-endpoint = <&funnel_in1_in_funnel_apss_merg>;
3761 }; 3425 };
3762 }; 3426 };
3763 }; 3427 };
3764 3428
3765 in-ports { 3429 in-ports {
3766 port { 3430 port {
3767 funne 3431 funnel_apss_merg_in_funnel_apss: endpoint {
3768 remot 3432 remote-endpoint = <&funnel_apss_out_funnel_apss_merg>;
3769 }; 3433 };
3770 }; 3434 };
3771 }; 3435 };
3772 }; 3436 };
3773 3437
3774 cdsp: remoteproc@8300000 { 3438 cdsp: remoteproc@8300000 {
3775 compatible = "qcom,sm 3439 compatible = "qcom,sm8250-cdsp-pas";
3776 reg = <0 0x08300000 0 3440 reg = <0 0x08300000 0 0x10000>;
3777 3441
3778 interrupts-extended = !! 3442 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
3779 3443 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
3780 3444 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
3781 3445 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
3782 3446 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
3783 interrupt-names = "wd 3447 interrupt-names = "wdog", "fatal", "ready",
3784 "ha 3448 "handover", "stop-ack";
3785 3449
3786 clocks = <&rpmhcc RPM 3450 clocks = <&rpmhcc RPMH_CXO_CLK>;
3787 clock-names = "xo"; 3451 clock-names = "xo";
3788 3452
3789 power-domains = <&rpm 3453 power-domains = <&rpmhpd RPMHPD_CX>;
3790 3454
3791 memory-region = <&cds 3455 memory-region = <&cdsp_mem>;
3792 3456
3793 qcom,qmp = <&aoss_qmp 3457 qcom,qmp = <&aoss_qmp>;
3794 3458
3795 qcom,smem-states = <& 3459 qcom,smem-states = <&smp2p_cdsp_out 0>;
3796 qcom,smem-state-names 3460 qcom,smem-state-names = "stop";
3797 3461
3798 status = "disabled"; 3462 status = "disabled";
3799 3463
3800 glink-edge { 3464 glink-edge {
3801 interrupts-ex 3465 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
3802 3466 IPCC_MPROC_SIGNAL_GLINK_QMP
3803 3467 IRQ_TYPE_EDGE_RISING>;
3804 mboxes = <&ip 3468 mboxes = <&ipcc IPCC_CLIENT_CDSP
3805 3469 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3806 3470
3807 label = "cdsp 3471 label = "cdsp";
3808 qcom,remote-p 3472 qcom,remote-pid = <5>;
3809 3473
3810 fastrpc { 3474 fastrpc {
3811 compa 3475 compatible = "qcom,fastrpc";
3812 qcom, 3476 qcom,glink-channels = "fastrpcglink-apps-dsp";
3813 label 3477 label = "cdsp";
3814 qcom, 3478 qcom,non-secure-domain;
3815 #addr 3479 #address-cells = <1>;
3816 #size 3480 #size-cells = <0>;
3817 3481
3818 compu 3482 compute-cb@1 {
3819 3483 compatible = "qcom,fastrpc-compute-cb";
3820 3484 reg = <1>;
3821 3485 iommus = <&apps_smmu 0x1001 0x0460>;
3822 }; 3486 };
3823 3487
3824 compu 3488 compute-cb@2 {
3825 3489 compatible = "qcom,fastrpc-compute-cb";
3826 3490 reg = <2>;
3827 3491 iommus = <&apps_smmu 0x1002 0x0460>;
3828 }; 3492 };
3829 3493
3830 compu 3494 compute-cb@3 {
3831 3495 compatible = "qcom,fastrpc-compute-cb";
3832 3496 reg = <3>;
3833 3497 iommus = <&apps_smmu 0x1003 0x0460>;
3834 }; 3498 };
3835 3499
3836 compu 3500 compute-cb@4 {
3837 3501 compatible = "qcom,fastrpc-compute-cb";
3838 3502 reg = <4>;
3839 3503 iommus = <&apps_smmu 0x1004 0x0460>;
3840 }; 3504 };
3841 3505
3842 compu 3506 compute-cb@5 {
3843 3507 compatible = "qcom,fastrpc-compute-cb";
3844 3508 reg = <5>;
3845 3509 iommus = <&apps_smmu 0x1005 0x0460>;
3846 }; 3510 };
3847 3511
3848 compu 3512 compute-cb@6 {
3849 3513 compatible = "qcom,fastrpc-compute-cb";
3850 3514 reg = <6>;
3851 3515 iommus = <&apps_smmu 0x1006 0x0460>;
3852 }; 3516 };
3853 3517
3854 compu 3518 compute-cb@7 {
3855 3519 compatible = "qcom,fastrpc-compute-cb";
3856 3520 reg = <7>;
3857 3521 iommus = <&apps_smmu 0x1007 0x0460>;
3858 }; 3522 };
3859 3523
3860 compu 3524 compute-cb@8 {
3861 3525 compatible = "qcom,fastrpc-compute-cb";
3862 3526 reg = <8>;
3863 3527 iommus = <&apps_smmu 0x1008 0x0460>;
3864 }; 3528 };
3865 3529
3866 /* no 3530 /* note: secure cb9 in downstream */
3867 }; 3531 };
3868 }; 3532 };
3869 }; 3533 };
3870 3534
3871 usb_1_hsphy: phy@88e3000 { 3535 usb_1_hsphy: phy@88e3000 {
3872 compatible = "qcom,sm 3536 compatible = "qcom,sm8250-usb-hs-phy",
3873 "qcom,us 3537 "qcom,usb-snps-hs-7nm-phy";
3874 reg = <0 0x088e3000 0 3538 reg = <0 0x088e3000 0 0x400>;
3875 status = "disabled"; 3539 status = "disabled";
3876 #phy-cells = <0>; 3540 #phy-cells = <0>;
3877 3541
3878 clocks = <&rpmhcc RPM 3542 clocks = <&rpmhcc RPMH_CXO_CLK>;
3879 clock-names = "ref"; 3543 clock-names = "ref";
3880 3544
3881 resets = <&gcc GCC_QU 3545 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3882 }; 3546 };
3883 3547
3884 usb_2_hsphy: phy@88e4000 { 3548 usb_2_hsphy: phy@88e4000 {
3885 compatible = "qcom,sm 3549 compatible = "qcom,sm8250-usb-hs-phy",
3886 "qcom,us 3550 "qcom,usb-snps-hs-7nm-phy";
3887 reg = <0 0x088e4000 0 3551 reg = <0 0x088e4000 0 0x400>;
3888 status = "disabled"; 3552 status = "disabled";
3889 #phy-cells = <0>; 3553 #phy-cells = <0>;
3890 3554
3891 clocks = <&rpmhcc RPM 3555 clocks = <&rpmhcc RPMH_CXO_CLK>;
3892 clock-names = "ref"; 3556 clock-names = "ref";
3893 3557
3894 resets = <&gcc GCC_QU 3558 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3895 }; 3559 };
3896 3560
3897 usb_1_qmpphy: phy@88e8000 { !! 3561 usb_1_qmpphy: phy@88e9000 {
3898 compatible = "qcom,sm 3562 compatible = "qcom,sm8250-qmp-usb3-dp-phy";
3899 reg = <0 0x088e8000 0 !! 3563 reg = <0 0x088e9000 0 0x200>,
>> 3564 <0 0x088e8000 0 0x40>,
>> 3565 <0 0x088ea000 0 0x200>;
3900 status = "disabled"; 3566 status = "disabled";
>> 3567 #address-cells = <2>;
>> 3568 #size-cells = <2>;
>> 3569 ranges;
3901 3570
3902 clocks = <&gcc GCC_US 3571 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
3903 <&rpmhcc RPM 3572 <&rpmhcc RPMH_CXO_CLK>,
3904 <&gcc GCC_US !! 3573 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
3905 <&gcc GCC_US !! 3574 clock-names = "aux", "ref_clk_src", "com_aux";
3906 clock-names = "aux", <<
3907 "ref", <<
3908 "com_au <<
3909 "usb3_p <<
3910 3575
3911 resets = <&gcc GCC_US 3576 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
3912 <&gcc GCC_US 3577 <&gcc GCC_USB3_PHY_PRIM_BCR>;
3913 reset-names = "phy", 3578 reset-names = "phy", "common";
3914 3579
3915 #clock-cells = <1>; !! 3580 usb_1_ssphy: usb3-phy@88e9200 {
3916 #phy-cells = <1>; !! 3581 reg = <0 0x088e9200 0 0x200>,
3917 !! 3582 <0 0x088e9400 0 0x200>,
3918 orientation-switch; !! 3583 <0 0x088e9c00 0 0x400>,
3919 !! 3584 <0 0x088e9600 0 0x200>,
3920 ports { !! 3585 <0 0x088e9800 0 0x200>,
3921 #address-cell !! 3586 <0 0x088e9a00 0 0x100>;
3922 #size-cells = !! 3587 #clock-cells = <0>;
3923 !! 3588 #phy-cells = <0>;
3924 port@0 { !! 3589 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3925 reg = !! 3590 clock-names = "pipe0";
3926 usb_1 !! 3591 clock-output-names = "usb3_phy_pipe_clk_src";
3927 }; !! 3592 };
3928 <<
3929 port@1 { <<
3930 reg = <<
3931 <<
3932 usb_1 <<
3933 <<
3934 }; <<
3935 }; <<
3936 <<
3937 port@2 { <<
3938 reg = <<
3939 3593
3940 usb_1 !! 3594 dp_phy: dp-phy@88ea200 {
3941 }; !! 3595 reg = <0 0x088ea200 0 0x200>,
>> 3596 <0 0x088ea400 0 0x200>,
>> 3597 <0 0x088eaa00 0 0x200>,
>> 3598 <0 0x088ea600 0 0x200>,
>> 3599 <0 0x088ea800 0 0x200>;
>> 3600 #phy-cells = <0>;
>> 3601 #clock-cells = <1>;
3942 }; 3602 };
3943 }; 3603 };
3944 3604
3945 usb_2_qmpphy: phy@88eb000 { 3605 usb_2_qmpphy: phy@88eb000 {
3946 compatible = "qcom,sm 3606 compatible = "qcom,sm8250-qmp-usb3-uni-phy";
3947 reg = <0 0x088eb000 0 !! 3607 reg = <0 0x088eb000 0 0x200>;
>> 3608 status = "disabled";
>> 3609 #address-cells = <2>;
>> 3610 #size-cells = <2>;
>> 3611 ranges;
3948 3612
3949 clocks = <&gcc GCC_US 3613 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
>> 3614 <&rpmhcc RPMH_CXO_CLK>,
3950 <&gcc GCC_US 3615 <&gcc GCC_USB3_SEC_CLKREF_EN>,
3951 <&gcc GCC_US !! 3616 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
3952 <&gcc GCC_US !! 3617 clock-names = "aux", "ref_clk_src", "ref", "com_aux";
3953 clock-names = "aux", <<
3954 "ref", <<
3955 "com_au <<
3956 "pipe"; <<
3957 clock-output-names = <<
3958 #clock-cells = <0>; <<
3959 #phy-cells = <0>; <<
3960 3618
3961 resets = <&gcc GCC_US !! 3619 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
3962 <&gcc GCC_US !! 3620 <&gcc GCC_USB3_PHY_SEC_BCR>;
3963 reset-names = "phy", !! 3621 reset-names = "phy", "common";
3964 "phy_ph <<
3965 3622
3966 status = "disabled"; !! 3623 usb_2_ssphy: phy@88eb200 {
>> 3624 reg = <0 0x088eb200 0 0x200>,
>> 3625 <0 0x088eb400 0 0x200>,
>> 3626 <0 0x088eb800 0 0x800>;
>> 3627 #clock-cells = <0>;
>> 3628 #phy-cells = <0>;
>> 3629 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
>> 3630 clock-names = "pipe0";
>> 3631 clock-output-names = "usb3_uni_phy_pipe_clk_src";
>> 3632 };
3967 }; 3633 };
3968 3634
3969 sdhc_2: mmc@8804000 { 3635 sdhc_2: mmc@8804000 {
3970 compatible = "qcom,sm 3636 compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
3971 reg = <0 0x08804000 0 3637 reg = <0 0x08804000 0 0x1000>;
3972 3638
3973 interrupts = <GIC_SPI 3639 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
3974 <GIC_SPI 3640 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
3975 interrupt-names = "hc 3641 interrupt-names = "hc_irq", "pwr_irq";
3976 3642
3977 clocks = <&gcc GCC_SD 3643 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3978 <&gcc GCC_SD 3644 <&gcc GCC_SDCC2_APPS_CLK>,
3979 <&rpmhcc RPM 3645 <&rpmhcc RPMH_CXO_CLK>;
3980 clock-names = "iface" 3646 clock-names = "iface", "core", "xo";
3981 iommus = <&apps_smmu 3647 iommus = <&apps_smmu 0x4a0 0x0>;
3982 qcom,dll-config = <0x 3648 qcom,dll-config = <0x0007642c>;
3983 qcom,ddr-config = <0x 3649 qcom,ddr-config = <0x80040868>;
3984 power-domains = <&rpm 3650 power-domains = <&rpmhpd RPMHPD_CX>;
3985 operating-points-v2 = 3651 operating-points-v2 = <&sdhc2_opp_table>;
3986 3652
3987 status = "disabled"; 3653 status = "disabled";
3988 3654
3989 sdhc2_opp_table: opp- 3655 sdhc2_opp_table: opp-table {
3990 compatible = 3656 compatible = "operating-points-v2";
3991 3657
3992 opp-19200000 3658 opp-19200000 {
3993 opp-h 3659 opp-hz = /bits/ 64 <19200000>;
3994 requi 3660 required-opps = <&rpmhpd_opp_min_svs>;
3995 }; 3661 };
3996 3662
3997 opp-50000000 3663 opp-50000000 {
3998 opp-h 3664 opp-hz = /bits/ 64 <50000000>;
3999 requi 3665 required-opps = <&rpmhpd_opp_low_svs>;
4000 }; 3666 };
4001 3667
4002 opp-100000000 3668 opp-100000000 {
4003 opp-h 3669 opp-hz = /bits/ 64 <100000000>;
4004 requi 3670 required-opps = <&rpmhpd_opp_svs>;
4005 }; 3671 };
4006 3672
4007 opp-202000000 3673 opp-202000000 {
4008 opp-h 3674 opp-hz = /bits/ 64 <202000000>;
4009 requi 3675 required-opps = <&rpmhpd_opp_svs_l1>;
4010 }; 3676 };
4011 }; 3677 };
4012 }; 3678 };
4013 3679
4014 pmu@9091000 { 3680 pmu@9091000 {
4015 compatible = "qcom,sm 3681 compatible = "qcom,sm8250-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
4016 reg = <0 0x09091000 0 3682 reg = <0 0x09091000 0 0x1000>;
4017 3683
4018 interrupts = <GIC_SPI 3684 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
4019 3685
4020 interconnects = <&mc_ 3686 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI_CH0 3>;
4021 3687
4022 operating-points-v2 = 3688 operating-points-v2 = <&llcc_bwmon_opp_table>;
4023 3689
4024 llcc_bwmon_opp_table: 3690 llcc_bwmon_opp_table: opp-table {
4025 compatible = 3691 compatible = "operating-points-v2";
4026 3692
4027 opp-800000 { 3693 opp-800000 {
4028 opp-p 3694 opp-peak-kBps = <(200 * 4 * 1000)>;
4029 }; 3695 };
4030 3696
4031 opp-1200000 { 3697 opp-1200000 {
4032 opp-p 3698 opp-peak-kBps = <(300 * 4 * 1000)>;
4033 }; 3699 };
4034 3700
4035 opp-1804000 { 3701 opp-1804000 {
4036 opp-p 3702 opp-peak-kBps = <(451 * 4 * 1000)>;
4037 }; 3703 };
4038 3704
4039 opp-2188000 { 3705 opp-2188000 {
4040 opp-p 3706 opp-peak-kBps = <(547 * 4 * 1000)>;
4041 }; 3707 };
4042 3708
4043 opp-2724000 { 3709 opp-2724000 {
4044 opp-p 3710 opp-peak-kBps = <(681 * 4 * 1000)>;
4045 }; 3711 };
4046 3712
4047 opp-3072000 { 3713 opp-3072000 {
4048 opp-p 3714 opp-peak-kBps = <(768 * 4 * 1000)>;
4049 }; 3715 };
4050 3716
4051 opp-4068000 { 3717 opp-4068000 {
4052 opp-p 3718 opp-peak-kBps = <(1017 * 4 * 1000)>;
4053 }; 3719 };
4054 3720
4055 /* 1353 MHz, 3721 /* 1353 MHz, LPDDR4X */
4056 3722
4057 opp-6220000 { 3723 opp-6220000 {
4058 opp-p 3724 opp-peak-kBps = <(1555 * 4 * 1000)>;
4059 }; 3725 };
4060 3726
4061 opp-7216000 { 3727 opp-7216000 {
4062 opp-p 3728 opp-peak-kBps = <(1804 * 4 * 1000)>;
4063 }; 3729 };
4064 3730
4065 opp-8368000 { 3731 opp-8368000 {
4066 opp-p 3732 opp-peak-kBps = <(2092 * 4 * 1000)>;
4067 }; 3733 };
4068 3734
4069 /* LPDDR5 */ 3735 /* LPDDR5 */
4070 opp-10944000 3736 opp-10944000 {
4071 opp-p 3737 opp-peak-kBps = <(2736 * 4 * 1000)>;
4072 }; 3738 };
4073 }; 3739 };
4074 }; 3740 };
4075 3741
4076 pmu@90b6400 { 3742 pmu@90b6400 {
4077 compatible = "qcom,sm 3743 compatible = "qcom,sm8250-cpu-bwmon", "qcom,sdm845-bwmon";
4078 reg = <0 0x090b6400 0 3744 reg = <0 0x090b6400 0 0x600>;
4079 3745
4080 interrupts = <GIC_SPI 3746 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
4081 3747
4082 interconnects = <&gem 3748 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &gem_noc SLAVE_LLCC 3>;
4083 operating-points-v2 = 3749 operating-points-v2 = <&cpu_bwmon_opp_table>;
4084 3750
4085 cpu_bwmon_opp_table: 3751 cpu_bwmon_opp_table: opp-table {
4086 compatible = 3752 compatible = "operating-points-v2";
4087 3753
4088 opp-800000 { 3754 opp-800000 {
4089 opp-p 3755 opp-peak-kBps = <(200 * 4 * 1000)>;
4090 }; 3756 };
4091 3757
4092 opp-1804000 { 3758 opp-1804000 {
4093 opp-p 3759 opp-peak-kBps = <(451 * 4 * 1000)>;
4094 }; 3760 };
4095 3761
4096 opp-2188000 { 3762 opp-2188000 {
4097 opp-p 3763 opp-peak-kBps = <(547 * 4 * 1000)>;
4098 }; 3764 };
4099 3765
4100 opp-2724000 { 3766 opp-2724000 {
4101 opp-p 3767 opp-peak-kBps = <(681 * 4 * 1000)>;
4102 }; 3768 };
4103 3769
4104 opp-3072000 { 3770 opp-3072000 {
4105 opp-p 3771 opp-peak-kBps = <(768 * 4 * 1000)>;
4106 }; 3772 };
4107 3773
4108 /* 1017MHz, 1 3774 /* 1017MHz, 1353 MHz, LPDDR4X */
4109 3775
4110 opp-6220000 { 3776 opp-6220000 {
4111 opp-p 3777 opp-peak-kBps = <(1555 * 4 * 1000)>;
4112 }; 3778 };
4113 3779
4114 opp-6832000 { 3780 opp-6832000 {
4115 opp-p 3781 opp-peak-kBps = <(1708 * 4 * 1000)>;
4116 }; 3782 };
4117 3783
4118 opp-8368000 { 3784 opp-8368000 {
4119 opp-p 3785 opp-peak-kBps = <(2092 * 4 * 1000)>;
4120 }; 3786 };
4121 3787
4122 /* 2133MHz, L 3788 /* 2133MHz, LPDDR4X */
4123 3789
4124 /* LPDDR5 */ 3790 /* LPDDR5 */
4125 opp-10944000 3791 opp-10944000 {
4126 opp-p 3792 opp-peak-kBps = <(2736 * 4 * 1000)>;
4127 }; 3793 };
4128 3794
4129 /* LPDDR5 */ 3795 /* LPDDR5 */
4130 opp-12784000 3796 opp-12784000 {
4131 opp-p 3797 opp-peak-kBps = <(3196 * 4 * 1000)>;
4132 }; 3798 };
4133 }; 3799 };
4134 }; 3800 };
4135 3801
4136 dc_noc: interconnect@90c0000 3802 dc_noc: interconnect@90c0000 {
4137 compatible = "qcom,sm 3803 compatible = "qcom,sm8250-dc-noc";
4138 reg = <0 0x090c0000 0 3804 reg = <0 0x090c0000 0 0x4200>;
4139 #interconnect-cells = 3805 #interconnect-cells = <2>;
4140 qcom,bcm-voters = <&a 3806 qcom,bcm-voters = <&apps_bcm_voter>;
4141 }; 3807 };
4142 3808
4143 gem_noc: interconnect@9100000 3809 gem_noc: interconnect@9100000 {
4144 compatible = "qcom,sm 3810 compatible = "qcom,sm8250-gem-noc";
4145 reg = <0 0x09100000 0 3811 reg = <0 0x09100000 0 0xb4000>;
4146 #interconnect-cells = 3812 #interconnect-cells = <2>;
4147 qcom,bcm-voters = <&a 3813 qcom,bcm-voters = <&apps_bcm_voter>;
4148 }; 3814 };
4149 3815
4150 npu_noc: interconnect@9990000 3816 npu_noc: interconnect@9990000 {
4151 compatible = "qcom,sm 3817 compatible = "qcom,sm8250-npu-noc";
4152 reg = <0 0x09990000 0 3818 reg = <0 0x09990000 0 0x1600>;
4153 #interconnect-cells = 3819 #interconnect-cells = <2>;
4154 qcom,bcm-voters = <&a 3820 qcom,bcm-voters = <&apps_bcm_voter>;
4155 }; 3821 };
4156 3822
4157 usb_1: usb@a6f8800 { 3823 usb_1: usb@a6f8800 {
4158 compatible = "qcom,sm 3824 compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
4159 reg = <0 0x0a6f8800 0 3825 reg = <0 0x0a6f8800 0 0x400>;
4160 status = "disabled"; 3826 status = "disabled";
4161 #address-cells = <2>; 3827 #address-cells = <2>;
4162 #size-cells = <2>; 3828 #size-cells = <2>;
4163 ranges; 3829 ranges;
4164 dma-ranges; 3830 dma-ranges;
4165 3831
4166 clocks = <&gcc GCC_CF 3832 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
4167 <&gcc GCC_US 3833 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
4168 <&gcc GCC_AG 3834 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
4169 <&gcc GCC_US 3835 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
4170 <&gcc GCC_US 3836 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4171 <&gcc GCC_US 3837 <&gcc GCC_USB3_SEC_CLKREF_EN>;
4172 clock-names = "cfg_no 3838 clock-names = "cfg_noc",
4173 "core", 3839 "core",
4174 "iface" 3840 "iface",
4175 "sleep" 3841 "sleep",
4176 "mock_u 3842 "mock_utmi",
4177 "xo"; 3843 "xo";
4178 3844
4179 assigned-clocks = <&g 3845 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4180 <&g 3846 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
4181 assigned-clock-rates 3847 assigned-clock-rates = <19200000>, <200000000>;
4182 3848
4183 interrupts-extended = !! 3849 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
4184 !! 3850 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
4185 <<
4186 3851 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
4187 !! 3852 <&pdc 14 IRQ_TYPE_EDGE_BOTH>;
4188 interrupt-names = "pw !! 3853 interrupt-names = "hs_phy_irq",
4189 "hs !! 3854 "ss_phy_irq",
4190 "dp <<
4191 "dm 3855 "dm_hs_phy_irq",
4192 "ss !! 3856 "dp_hs_phy_irq";
4193 3857
4194 power-domains = <&gcc 3858 power-domains = <&gcc USB30_PRIM_GDSC>;
4195 wakeup-source; <<
4196 3859
4197 resets = <&gcc GCC_US 3860 resets = <&gcc GCC_USB30_PRIM_BCR>;
4198 3861
4199 interconnects = <&agg 3862 interconnects = <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>,
4200 <&gem 3863 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>;
4201 interconnect-names = 3864 interconnect-names = "usb-ddr", "apps-usb";
4202 3865
4203 usb_1_dwc3: usb@a6000 3866 usb_1_dwc3: usb@a600000 {
4204 compatible = 3867 compatible = "snps,dwc3";
4205 reg = <0 0x0a 3868 reg = <0 0x0a600000 0 0xcd00>;
4206 interrupts = 3869 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
4207 iommus = <&ap 3870 iommus = <&apps_smmu 0x0 0x0>;
4208 snps,dis_u2_s 3871 snps,dis_u2_susphy_quirk;
4209 snps,dis_enbl 3872 snps,dis_enblslpm_quirk;
4210 phys = <&usb_ !! 3873 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
4211 phy-names = " 3874 phy-names = "usb2-phy", "usb3-phy";
4212 <<
4213 ports { <<
4214 #addr <<
4215 #size <<
4216 <<
4217 port@ <<
4218 <<
4219 <<
4220 <<
4221 <<
4222 }; <<
4223 <<
4224 port@ <<
4225 <<
4226 <<
4227 <<
4228 <<
4229 <<
4230 }; <<
4231 }; <<
4232 }; 3875 };
4233 }; 3876 };
4234 3877
4235 system-cache-controller@92000 3878 system-cache-controller@9200000 {
4236 compatible = "qcom,sm 3879 compatible = "qcom,sm8250-llcc";
4237 reg = <0 0x09200000 0 3880 reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>,
4238 <0 0x09300000 0 3881 <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>,
4239 <0 0x09600000 0 3882 <0 0x09600000 0 0x50000>;
4240 reg-names = "llcc0_ba 3883 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
4241 "llcc3_ba 3884 "llcc3_base", "llcc_broadcast_base";
4242 }; 3885 };
4243 3886
4244 usb_2: usb@a8f8800 { 3887 usb_2: usb@a8f8800 {
4245 compatible = "qcom,sm 3888 compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
4246 reg = <0 0x0a8f8800 0 3889 reg = <0 0x0a8f8800 0 0x400>;
4247 status = "disabled"; 3890 status = "disabled";
4248 #address-cells = <2>; 3891 #address-cells = <2>;
4249 #size-cells = <2>; 3892 #size-cells = <2>;
4250 ranges; 3893 ranges;
4251 dma-ranges; 3894 dma-ranges;
4252 3895
4253 clocks = <&gcc GCC_CF 3896 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
4254 <&gcc GCC_US 3897 <&gcc GCC_USB30_SEC_MASTER_CLK>,
4255 <&gcc GCC_AG 3898 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
4256 <&gcc GCC_US 3899 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
4257 <&gcc GCC_US 3900 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4258 <&gcc GCC_US 3901 <&gcc GCC_USB3_SEC_CLKREF_EN>;
4259 clock-names = "cfg_no 3902 clock-names = "cfg_noc",
4260 "core", 3903 "core",
4261 "iface" 3904 "iface",
4262 "sleep" 3905 "sleep",
4263 "mock_u 3906 "mock_utmi",
4264 "xo"; 3907 "xo";
4265 3908
4266 assigned-clocks = <&g 3909 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4267 <&g 3910 <&gcc GCC_USB30_SEC_MASTER_CLK>;
4268 assigned-clock-rates 3911 assigned-clock-rates = <19200000>, <200000000>;
4269 3912
4270 interrupts-extended = !! 3913 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
4271 !! 3914 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>,
4272 <<
4273 3915 <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
4274 !! 3916 <&pdc 12 IRQ_TYPE_EDGE_BOTH>;
4275 interrupt-names = "pw !! 3917 interrupt-names = "hs_phy_irq",
4276 "hs !! 3918 "ss_phy_irq",
4277 "dp <<
4278 "dm 3919 "dm_hs_phy_irq",
4279 "ss !! 3920 "dp_hs_phy_irq";
4280 3921
4281 power-domains = <&gcc 3922 power-domains = <&gcc USB30_SEC_GDSC>;
4282 wakeup-source; <<
4283 3923
4284 resets = <&gcc GCC_US 3924 resets = <&gcc GCC_USB30_SEC_BCR>;
4285 3925
4286 interconnects = <&agg 3926 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0>,
4287 <&gem 3927 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>;
4288 interconnect-names = 3928 interconnect-names = "usb-ddr", "apps-usb";
4289 3929
4290 usb_2_dwc3: usb@a8000 3930 usb_2_dwc3: usb@a800000 {
4291 compatible = 3931 compatible = "snps,dwc3";
4292 reg = <0 0x0a 3932 reg = <0 0x0a800000 0 0xcd00>;
4293 interrupts = 3933 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
4294 iommus = <&ap 3934 iommus = <&apps_smmu 0x20 0>;
4295 snps,dis_u2_s 3935 snps,dis_u2_susphy_quirk;
4296 snps,dis_enbl 3936 snps,dis_enblslpm_quirk;
4297 phys = <&usb_ !! 3937 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
4298 phy-names = " 3938 phy-names = "usb2-phy", "usb3-phy";
4299 }; 3939 };
4300 }; 3940 };
4301 3941
4302 venus: video-codec@aa00000 { 3942 venus: video-codec@aa00000 {
4303 compatible = "qcom,sm 3943 compatible = "qcom,sm8250-venus";
4304 reg = <0 0x0aa00000 0 3944 reg = <0 0x0aa00000 0 0x100000>;
4305 interrupts = <GIC_SPI 3945 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
4306 power-domains = <&vid 3946 power-domains = <&videocc MVS0C_GDSC>,
4307 <&vid 3947 <&videocc MVS0_GDSC>,
4308 <&rpm 3948 <&rpmhpd RPMHPD_MX>;
4309 power-domain-names = 3949 power-domain-names = "venus", "vcodec0", "mx";
4310 operating-points-v2 = 3950 operating-points-v2 = <&venus_opp_table>;
4311 3951
4312 clocks = <&gcc GCC_VI 3952 clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
4313 <&videocc VI 3953 <&videocc VIDEO_CC_MVS0C_CLK>,
4314 <&videocc VI 3954 <&videocc VIDEO_CC_MVS0_CLK>;
4315 clock-names = "iface" 3955 clock-names = "iface", "core", "vcodec0_core";
4316 3956
4317 interconnects = <&gem 3957 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_VENUS_CFG 0>,
4318 <&mms 3958 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI_CH0 0>;
4319 interconnect-names = 3959 interconnect-names = "cpu-cfg", "video-mem";
4320 3960
4321 iommus = <&apps_smmu 3961 iommus = <&apps_smmu 0x2100 0x0400>;
4322 memory-region = <&vid 3962 memory-region = <&video_mem>;
4323 3963
4324 resets = <&gcc GCC_VI 3964 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
4325 <&videocc VI 3965 <&videocc VIDEO_CC_MVS0C_CLK_ARES>;
4326 reset-names = "bus", 3966 reset-names = "bus", "core";
4327 3967
4328 status = "disabled"; 3968 status = "disabled";
4329 3969
4330 video-decoder { 3970 video-decoder {
4331 compatible = 3971 compatible = "venus-decoder";
4332 }; 3972 };
4333 3973
4334 video-encoder { 3974 video-encoder {
4335 compatible = 3975 compatible = "venus-encoder";
4336 }; 3976 };
4337 3977
4338 venus_opp_table: opp- 3978 venus_opp_table: opp-table {
4339 compatible = 3979 compatible = "operating-points-v2";
4340 3980
4341 opp-720000000 3981 opp-720000000 {
4342 opp-h 3982 opp-hz = /bits/ 64 <720000000>;
4343 requi 3983 required-opps = <&rpmhpd_opp_low_svs>;
4344 }; 3984 };
4345 3985
4346 opp-101400000 3986 opp-1014000000 {
4347 opp-h 3987 opp-hz = /bits/ 64 <1014000000>;
4348 requi 3988 required-opps = <&rpmhpd_opp_svs>;
4349 }; 3989 };
4350 3990
4351 opp-109800000 3991 opp-1098000000 {
4352 opp-h 3992 opp-hz = /bits/ 64 <1098000000>;
4353 requi 3993 required-opps = <&rpmhpd_opp_svs_l1>;
4354 }; 3994 };
4355 3995
4356 opp-133200000 3996 opp-1332000000 {
4357 opp-h 3997 opp-hz = /bits/ 64 <1332000000>;
4358 requi 3998 required-opps = <&rpmhpd_opp_nom>;
4359 }; 3999 };
4360 }; 4000 };
4361 }; 4001 };
4362 4002
4363 videocc: clock-controller@abf 4003 videocc: clock-controller@abf0000 {
4364 compatible = "qcom,sm 4004 compatible = "qcom,sm8250-videocc";
4365 reg = <0 0x0abf0000 0 4005 reg = <0 0x0abf0000 0 0x10000>;
4366 clocks = <&gcc GCC_VI 4006 clocks = <&gcc GCC_VIDEO_AHB_CLK>,
4367 <&rpmhcc RPM 4007 <&rpmhcc RPMH_CXO_CLK>,
4368 <&rpmhcc RPM 4008 <&rpmhcc RPMH_CXO_CLK_A>;
4369 power-domains = <&rpm 4009 power-domains = <&rpmhpd RPMHPD_MMCX>;
4370 required-opps = <&rpm 4010 required-opps = <&rpmhpd_opp_low_svs>;
4371 clock-names = "iface" 4011 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao";
4372 #clock-cells = <1>; 4012 #clock-cells = <1>;
4373 #reset-cells = <1>; 4013 #reset-cells = <1>;
4374 #power-domain-cells = 4014 #power-domain-cells = <1>;
4375 }; 4015 };
4376 4016
4377 cci0: cci@ac4f000 { 4017 cci0: cci@ac4f000 {
4378 compatible = "qcom,sm 4018 compatible = "qcom,sm8250-cci", "qcom,msm8996-cci";
4379 #address-cells = <1>; 4019 #address-cells = <1>;
4380 #size-cells = <0>; 4020 #size-cells = <0>;
4381 4021
4382 reg = <0 0x0ac4f000 0 4022 reg = <0 0x0ac4f000 0 0x1000>;
4383 interrupts = <GIC_SPI 4023 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
4384 power-domains = <&cam 4024 power-domains = <&camcc TITAN_TOP_GDSC>;
4385 4025
4386 clocks = <&camcc CAM_ 4026 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
4387 <&camcc CAM_ 4027 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4388 <&camcc CAM_ 4028 <&camcc CAM_CC_CPAS_AHB_CLK>,
4389 <&camcc CAM_ 4029 <&camcc CAM_CC_CCI_0_CLK>,
4390 <&camcc CAM_ 4030 <&camcc CAM_CC_CCI_0_CLK_SRC>;
4391 clock-names = "camnoc 4031 clock-names = "camnoc_axi",
4392 "slow_a 4032 "slow_ahb_src",
4393 "cpas_a 4033 "cpas_ahb",
4394 "cci", 4034 "cci",
4395 "cci_sr 4035 "cci_src";
4396 4036
4397 pinctrl-0 = <&cci0_de 4037 pinctrl-0 = <&cci0_default>;
4398 pinctrl-1 = <&cci0_sl 4038 pinctrl-1 = <&cci0_sleep>;
4399 pinctrl-names = "defa 4039 pinctrl-names = "default", "sleep";
4400 4040
4401 status = "disabled"; 4041 status = "disabled";
4402 4042
4403 cci0_i2c0: i2c-bus@0 4043 cci0_i2c0: i2c-bus@0 {
4404 reg = <0>; 4044 reg = <0>;
4405 clock-frequen 4045 clock-frequency = <1000000>;
4406 #address-cell 4046 #address-cells = <1>;
4407 #size-cells = 4047 #size-cells = <0>;
4408 }; 4048 };
4409 4049
4410 cci0_i2c1: i2c-bus@1 4050 cci0_i2c1: i2c-bus@1 {
4411 reg = <1>; 4051 reg = <1>;
4412 clock-frequen 4052 clock-frequency = <1000000>;
4413 #address-cell 4053 #address-cells = <1>;
4414 #size-cells = 4054 #size-cells = <0>;
4415 }; 4055 };
4416 }; 4056 };
4417 4057
4418 cci1: cci@ac50000 { 4058 cci1: cci@ac50000 {
4419 compatible = "qcom,sm 4059 compatible = "qcom,sm8250-cci", "qcom,msm8996-cci";
4420 #address-cells = <1>; 4060 #address-cells = <1>;
4421 #size-cells = <0>; 4061 #size-cells = <0>;
4422 4062
4423 reg = <0 0x0ac50000 0 4063 reg = <0 0x0ac50000 0 0x1000>;
4424 interrupts = <GIC_SPI 4064 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>;
4425 power-domains = <&cam 4065 power-domains = <&camcc TITAN_TOP_GDSC>;
4426 4066
4427 clocks = <&camcc CAM_ 4067 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
4428 <&camcc CAM_ 4068 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4429 <&camcc CAM_ 4069 <&camcc CAM_CC_CPAS_AHB_CLK>,
4430 <&camcc CAM_ 4070 <&camcc CAM_CC_CCI_1_CLK>,
4431 <&camcc CAM_ 4071 <&camcc CAM_CC_CCI_1_CLK_SRC>;
4432 clock-names = "camnoc 4072 clock-names = "camnoc_axi",
4433 "slow_a 4073 "slow_ahb_src",
4434 "cpas_a 4074 "cpas_ahb",
4435 "cci", 4075 "cci",
4436 "cci_sr 4076 "cci_src";
4437 4077
4438 pinctrl-0 = <&cci1_de 4078 pinctrl-0 = <&cci1_default>;
4439 pinctrl-1 = <&cci1_sl 4079 pinctrl-1 = <&cci1_sleep>;
4440 pinctrl-names = "defa 4080 pinctrl-names = "default", "sleep";
4441 4081
4442 status = "disabled"; 4082 status = "disabled";
4443 4083
4444 cci1_i2c0: i2c-bus@0 4084 cci1_i2c0: i2c-bus@0 {
4445 reg = <0>; 4085 reg = <0>;
4446 clock-frequen 4086 clock-frequency = <1000000>;
4447 #address-cell 4087 #address-cells = <1>;
4448 #size-cells = 4088 #size-cells = <0>;
4449 }; 4089 };
4450 4090
4451 cci1_i2c1: i2c-bus@1 4091 cci1_i2c1: i2c-bus@1 {
4452 reg = <1>; 4092 reg = <1>;
4453 clock-frequen 4093 clock-frequency = <1000000>;
4454 #address-cell 4094 #address-cells = <1>;
4455 #size-cells = 4095 #size-cells = <0>;
4456 }; 4096 };
4457 }; 4097 };
4458 4098
4459 camss: camss@ac6a000 { 4099 camss: camss@ac6a000 {
4460 compatible = "qcom,sm 4100 compatible = "qcom,sm8250-camss";
4461 status = "disabled"; 4101 status = "disabled";
4462 4102
4463 reg = <0 0x0ac6a000 0 4103 reg = <0 0x0ac6a000 0 0x2000>,
4464 <0 0x0ac6c000 0 4104 <0 0x0ac6c000 0 0x2000>,
4465 <0 0x0ac6e000 0 4105 <0 0x0ac6e000 0 0x1000>,
4466 <0 0x0ac70000 0 4106 <0 0x0ac70000 0 0x1000>,
4467 <0 0x0ac72000 0 4107 <0 0x0ac72000 0 0x1000>,
4468 <0 0x0ac74000 0 4108 <0 0x0ac74000 0 0x1000>,
4469 <0 0x0acb4000 0 4109 <0 0x0acb4000 0 0xd000>,
4470 <0 0x0acc3000 0 4110 <0 0x0acc3000 0 0xd000>,
4471 <0 0x0acd9000 0 4111 <0 0x0acd9000 0 0x2200>,
4472 <0 0x0acdb200 0 4112 <0 0x0acdb200 0 0x2200>;
4473 reg-names = "csiphy0" 4113 reg-names = "csiphy0",
4474 "csiphy1" 4114 "csiphy1",
4475 "csiphy2" 4115 "csiphy2",
4476 "csiphy3" 4116 "csiphy3",
4477 "csiphy4" 4117 "csiphy4",
4478 "csiphy5" 4118 "csiphy5",
4479 "vfe0", 4119 "vfe0",
4480 "vfe1", 4120 "vfe1",
4481 "vfe_lite 4121 "vfe_lite0",
4482 "vfe_lite 4122 "vfe_lite1";
4483 4123
4484 interrupts = <GIC_SPI 4124 interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
4485 <GIC_SPI 4125 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
4486 <GIC_SPI 4126 <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
4487 <GIC_SPI 4127 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
4488 <GIC_SPI 4128 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
4489 <GIC_SPI 4129 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
4490 <GIC_SPI 4130 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
4491 <GIC_SPI 4131 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
4492 <GIC_SPI 4132 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
4493 <GIC_SPI 4133 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
4494 <GIC_SPI 4134 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
4495 <GIC_SPI 4135 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
4496 <GIC_SPI 4136 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
4497 <GIC_SPI 4137 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
4498 interrupt-names = "cs 4138 interrupt-names = "csiphy0",
4499 "cs 4139 "csiphy1",
4500 "cs 4140 "csiphy2",
4501 "cs 4141 "csiphy3",
4502 "cs 4142 "csiphy4",
4503 "cs 4143 "csiphy5",
4504 "cs 4144 "csid0",
4505 "cs 4145 "csid1",
4506 "cs 4146 "csid2",
4507 "cs 4147 "csid3",
4508 "vf 4148 "vfe0",
4509 "vf 4149 "vfe1",
4510 "vf 4150 "vfe_lite0",
4511 "vf 4151 "vfe_lite1";
4512 4152
4513 power-domains = <&cam 4153 power-domains = <&camcc IFE_0_GDSC>,
4514 <&cam 4154 <&camcc IFE_1_GDSC>,
4515 <&cam 4155 <&camcc TITAN_TOP_GDSC>;
4516 4156
4517 clocks = <&gcc GCC_CA 4157 clocks = <&gcc GCC_CAMERA_AHB_CLK>,
4518 <&gcc GCC_CA 4158 <&gcc GCC_CAMERA_HF_AXI_CLK>,
4519 <&gcc GCC_CA 4159 <&gcc GCC_CAMERA_SF_AXI_CLK>,
4520 <&camcc CAM_ 4160 <&camcc CAM_CC_CAMNOC_AXI_CLK>,
4521 <&camcc CAM_ 4161 <&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>,
4522 <&camcc CAM_ 4162 <&camcc CAM_CC_CORE_AHB_CLK>,
4523 <&camcc CAM_ 4163 <&camcc CAM_CC_CPAS_AHB_CLK>,
4524 <&camcc CAM_ 4164 <&camcc CAM_CC_CSIPHY0_CLK>,
4525 <&camcc CAM_ 4165 <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
4526 <&camcc CAM_ 4166 <&camcc CAM_CC_CSIPHY1_CLK>,
4527 <&camcc CAM_ 4167 <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
4528 <&camcc CAM_ 4168 <&camcc CAM_CC_CSIPHY2_CLK>,
4529 <&camcc CAM_ 4169 <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
4530 <&camcc CAM_ 4170 <&camcc CAM_CC_CSIPHY3_CLK>,
4531 <&camcc CAM_ 4171 <&camcc CAM_CC_CSI3PHYTIMER_CLK>,
4532 <&camcc CAM_ 4172 <&camcc CAM_CC_CSIPHY4_CLK>,
4533 <&camcc CAM_ 4173 <&camcc CAM_CC_CSI4PHYTIMER_CLK>,
4534 <&camcc CAM_ 4174 <&camcc CAM_CC_CSIPHY5_CLK>,
4535 <&camcc CAM_ 4175 <&camcc CAM_CC_CSI5PHYTIMER_CLK>,
4536 <&camcc CAM_ 4176 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4537 <&camcc CAM_ 4177 <&camcc CAM_CC_IFE_0_AHB_CLK>,
4538 <&camcc CAM_ 4178 <&camcc CAM_CC_IFE_0_AXI_CLK>,
4539 <&camcc CAM_ 4179 <&camcc CAM_CC_IFE_0_CLK>,
4540 <&camcc CAM_ 4180 <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
4541 <&camcc CAM_ 4181 <&camcc CAM_CC_IFE_0_CSID_CLK>,
4542 <&camcc CAM_ 4182 <&camcc CAM_CC_IFE_0_AREG_CLK>,
4543 <&camcc CAM_ 4183 <&camcc CAM_CC_IFE_1_AHB_CLK>,
4544 <&camcc CAM_ 4184 <&camcc CAM_CC_IFE_1_AXI_CLK>,
4545 <&camcc CAM_ 4185 <&camcc CAM_CC_IFE_1_CLK>,
4546 <&camcc CAM_ 4186 <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
4547 <&camcc CAM_ 4187 <&camcc CAM_CC_IFE_1_CSID_CLK>,
4548 <&camcc CAM_ 4188 <&camcc CAM_CC_IFE_1_AREG_CLK>,
4549 <&camcc CAM_ 4189 <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
4550 <&camcc CAM_ 4190 <&camcc CAM_CC_IFE_LITE_AXI_CLK>,
4551 <&camcc CAM_ 4191 <&camcc CAM_CC_IFE_LITE_CLK>,
4552 <&camcc CAM_ 4192 <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
4553 <&camcc CAM_ 4193 <&camcc CAM_CC_IFE_LITE_CSID_CLK>;
4554 4194
4555 clock-names = "cam_ah 4195 clock-names = "cam_ahb_clk",
4556 "cam_hf 4196 "cam_hf_axi",
4557 "cam_sf 4197 "cam_sf_axi",
4558 "camnoc 4198 "camnoc_axi",
4559 "camnoc 4199 "camnoc_axi_src",
4560 "core_a 4200 "core_ahb",
4561 "cpas_a 4201 "cpas_ahb",
4562 "csiphy 4202 "csiphy0",
4563 "csiphy 4203 "csiphy0_timer",
4564 "csiphy 4204 "csiphy1",
4565 "csiphy 4205 "csiphy1_timer",
4566 "csiphy 4206 "csiphy2",
4567 "csiphy 4207 "csiphy2_timer",
4568 "csiphy 4208 "csiphy3",
4569 "csiphy 4209 "csiphy3_timer",
4570 "csiphy 4210 "csiphy4",
4571 "csiphy 4211 "csiphy4_timer",
4572 "csiphy 4212 "csiphy5",
4573 "csiphy 4213 "csiphy5_timer",
4574 "slow_a 4214 "slow_ahb_src",
4575 "vfe0_a 4215 "vfe0_ahb",
4576 "vfe0_a 4216 "vfe0_axi",
4577 "vfe0", 4217 "vfe0",
4578 "vfe0_c 4218 "vfe0_cphy_rx",
4579 "vfe0_c 4219 "vfe0_csid",
4580 "vfe0_a 4220 "vfe0_areg",
4581 "vfe1_a 4221 "vfe1_ahb",
4582 "vfe1_a 4222 "vfe1_axi",
4583 "vfe1", 4223 "vfe1",
4584 "vfe1_c 4224 "vfe1_cphy_rx",
4585 "vfe1_c 4225 "vfe1_csid",
4586 "vfe1_a 4226 "vfe1_areg",
4587 "vfe_li 4227 "vfe_lite_ahb",
4588 "vfe_li 4228 "vfe_lite_axi",
4589 "vfe_li 4229 "vfe_lite",
4590 "vfe_li 4230 "vfe_lite_cphy_rx",
4591 "vfe_li 4231 "vfe_lite_csid";
4592 4232
4593 iommus = <&apps_smmu 4233 iommus = <&apps_smmu 0x800 0x400>,
4594 <&apps_smmu 4234 <&apps_smmu 0x801 0x400>,
4595 <&apps_smmu 4235 <&apps_smmu 0x840 0x400>,
4596 <&apps_smmu 4236 <&apps_smmu 0x841 0x400>,
4597 <&apps_smmu 4237 <&apps_smmu 0xc00 0x400>,
4598 <&apps_smmu 4238 <&apps_smmu 0xc01 0x400>,
4599 <&apps_smmu 4239 <&apps_smmu 0xc40 0x400>,
4600 <&apps_smmu 4240 <&apps_smmu 0xc41 0x400>;
4601 4241
4602 interconnects = <&gem 4242 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_CAMERA_CFG 0>,
4603 <&mms 4243 <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI_CH0 0>,
4604 <&mms 4244 <&mmss_noc MASTER_CAMNOC_SF 0 &mc_virt SLAVE_EBI_CH0 0>,
4605 <&mms 4245 <&mmss_noc MASTER_CAMNOC_ICP 0 &mc_virt SLAVE_EBI_CH0 0>;
4606 interconnect-names = 4246 interconnect-names = "cam_ahb",
4607 4247 "cam_hf_0_mnoc",
4608 4248 "cam_sf_0_mnoc",
4609 4249 "cam_sf_icp_mnoc";
4610 4250
4611 ports { 4251 ports {
4612 #address-cell 4252 #address-cells = <1>;
4613 #size-cells = 4253 #size-cells = <0>;
4614 4254
4615 port@0 { 4255 port@0 {
4616 reg = 4256 reg = <0>;
4617 }; 4257 };
4618 4258
4619 port@1 { 4259 port@1 {
4620 reg = 4260 reg = <1>;
4621 }; 4261 };
4622 4262
4623 port@2 { 4263 port@2 {
4624 reg = 4264 reg = <2>;
4625 }; 4265 };
4626 4266
4627 port@3 { 4267 port@3 {
4628 reg = 4268 reg = <3>;
4629 }; 4269 };
4630 4270
4631 port@4 { 4271 port@4 {
4632 reg = 4272 reg = <4>;
4633 }; 4273 };
4634 4274
4635 port@5 { 4275 port@5 {
4636 reg = 4276 reg = <5>;
4637 }; 4277 };
4638 }; 4278 };
4639 }; 4279 };
4640 4280
4641 camcc: clock-controller@ad000 4281 camcc: clock-controller@ad00000 {
4642 compatible = "qcom,sm 4282 compatible = "qcom,sm8250-camcc";
4643 reg = <0 0x0ad00000 0 4283 reg = <0 0x0ad00000 0 0x10000>;
4644 clocks = <&gcc GCC_CA 4284 clocks = <&gcc GCC_CAMERA_AHB_CLK>,
4645 <&rpmhcc RPM 4285 <&rpmhcc RPMH_CXO_CLK>,
4646 <&rpmhcc RPM 4286 <&rpmhcc RPMH_CXO_CLK_A>,
4647 <&sleep_clk> 4287 <&sleep_clk>;
4648 clock-names = "iface" 4288 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
4649 power-domains = <&rpm 4289 power-domains = <&rpmhpd RPMHPD_MMCX>;
4650 required-opps = <&rpm 4290 required-opps = <&rpmhpd_opp_low_svs>;
4651 status = "disabled"; 4291 status = "disabled";
4652 #clock-cells = <1>; 4292 #clock-cells = <1>;
4653 #reset-cells = <1>; 4293 #reset-cells = <1>;
4654 #power-domain-cells = 4294 #power-domain-cells = <1>;
4655 }; 4295 };
4656 4296
4657 mdss: display-subsystem@ae000 4297 mdss: display-subsystem@ae00000 {
4658 compatible = "qcom,sm 4298 compatible = "qcom,sm8250-mdss";
4659 reg = <0 0x0ae00000 0 4299 reg = <0 0x0ae00000 0 0x1000>;
4660 reg-names = "mdss"; 4300 reg-names = "mdss";
4661 4301
4662 interconnects = <&mms 4302 interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mc_virt SLAVE_EBI_CH0 0>,
4663 <&mms 4303 <&mmss_noc MASTER_MDP_PORT1 0 &mc_virt SLAVE_EBI_CH0 0>;
4664 interconnect-names = 4304 interconnect-names = "mdp0-mem", "mdp1-mem";
4665 4305
4666 power-domains = <&dis 4306 power-domains = <&dispcc MDSS_GDSC>;
4667 4307
4668 clocks = <&dispcc DIS 4308 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4669 <&gcc GCC_DI 4309 <&gcc GCC_DISP_HF_AXI_CLK>,
4670 <&gcc GCC_DI 4310 <&gcc GCC_DISP_SF_AXI_CLK>,
4671 <&dispcc DIS 4311 <&dispcc DISP_CC_MDSS_MDP_CLK>;
4672 clock-names = "iface" 4312 clock-names = "iface", "bus", "nrt_bus", "core";
4673 4313
4674 interrupts = <GIC_SPI 4314 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
4675 interrupt-controller; 4315 interrupt-controller;
4676 #interrupt-cells = <1 4316 #interrupt-cells = <1>;
4677 4317
4678 iommus = <&apps_smmu 4318 iommus = <&apps_smmu 0x820 0x402>;
4679 4319
4680 status = "disabled"; 4320 status = "disabled";
4681 4321
4682 #address-cells = <2>; 4322 #address-cells = <2>;
4683 #size-cells = <2>; 4323 #size-cells = <2>;
4684 ranges; 4324 ranges;
4685 4325
4686 mdss_mdp: display-con 4326 mdss_mdp: display-controller@ae01000 {
4687 compatible = 4327 compatible = "qcom,sm8250-dpu";
4688 reg = <0 0x0a 4328 reg = <0 0x0ae01000 0 0x8f000>,
4689 <0 0x0a 4329 <0 0x0aeb0000 0 0x2008>;
4690 reg-names = " 4330 reg-names = "mdp", "vbif";
4691 4331
4692 clocks = <&di 4332 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4693 <&gc 4333 <&gcc GCC_DISP_HF_AXI_CLK>,
4694 <&di 4334 <&dispcc DISP_CC_MDSS_MDP_CLK>,
4695 <&di 4335 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4696 clock-names = 4336 clock-names = "iface", "bus", "core", "vsync";
4697 4337
4698 assigned-cloc 4338 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4699 assigned-cloc 4339 assigned-clock-rates = <19200000>;
4700 4340
4701 operating-poi 4341 operating-points-v2 = <&mdp_opp_table>;
4702 power-domains 4342 power-domains = <&rpmhpd RPMHPD_MMCX>;
4703 4343
4704 interrupt-par 4344 interrupt-parent = <&mdss>;
4705 interrupts = 4345 interrupts = <0>;
4706 4346
4707 ports { 4347 ports {
4708 #addr 4348 #address-cells = <1>;
4709 #size 4349 #size-cells = <0>;
4710 4350
4711 port@ 4351 port@0 {
4712 4352 reg = <0>;
4713 4353 dpu_intf1_out: endpoint {
4714 4354 remote-endpoint = <&mdss_dsi0_in>;
4715 4355 };
4716 }; 4356 };
4717 4357
4718 port@ 4358 port@1 {
4719 4359 reg = <1>;
4720 4360 dpu_intf2_out: endpoint {
4721 4361 remote-endpoint = <&mdss_dsi1_in>;
4722 4362 };
4723 }; 4363 };
4724 <<
4725 port@ <<
4726 <<
4727 <<
4728 <<
4729 <<
4730 <<
4731 }; <<
4732 }; 4364 };
4733 4365
4734 mdp_opp_table 4366 mdp_opp_table: opp-table {
4735 compa 4367 compatible = "operating-points-v2";
4736 4368
4737 opp-2 4369 opp-200000000 {
4738 4370 opp-hz = /bits/ 64 <200000000>;
4739 4371 required-opps = <&rpmhpd_opp_low_svs>;
4740 }; 4372 };
4741 4373
4742 opp-3 4374 opp-300000000 {
4743 4375 opp-hz = /bits/ 64 <300000000>;
4744 4376 required-opps = <&rpmhpd_opp_svs>;
4745 }; 4377 };
4746 4378
4747 opp-3 4379 opp-345000000 {
4748 4380 opp-hz = /bits/ 64 <345000000>;
4749 4381 required-opps = <&rpmhpd_opp_svs_l1>;
4750 }; 4382 };
4751 4383
4752 opp-4 4384 opp-460000000 {
4753 4385 opp-hz = /bits/ 64 <460000000>;
4754 4386 required-opps = <&rpmhpd_opp_nom>;
4755 }; 4387 };
4756 }; 4388 };
4757 }; 4389 };
4758 4390
4759 mdss_dp: displayport- <<
4760 compatible = <<
4761 reg = <0 0xae <<
4762 <0 0xae <<
4763 <0 0xae <<
4764 <0 0xae <<
4765 <0 0xae <<
4766 interrupt-par <<
4767 interrupts = <<
4768 clocks = <&di <<
4769 <&di <<
4770 <&di <<
4771 <&di <<
4772 <&di <<
4773 clock-names = <<
4774 <<
4775 <<
4776 <<
4777 <<
4778 <<
4779 assigned-cloc <<
4780 <<
4781 assigned-cloc <<
4782 <<
4783 <<
4784 phys = <&usb_ <<
4785 phy-names = " <<
4786 <<
4787 #sound-dai-ce <<
4788 <<
4789 operating-poi <<
4790 power-domains <<
4791 <<
4792 status = "dis <<
4793 <<
4794 ports { <<
4795 #addr <<
4796 #size <<
4797 <<
4798 port@ <<
4799 <<
4800 <<
4801 <<
4802 <<
4803 }; <<
4804 <<
4805 port@ <<
4806 <<
4807 <<
4808 <<
4809 <<
4810 }; <<
4811 }; <<
4812 <<
4813 dp_opp_table: <<
4814 compa <<
4815 <<
4816 opp-1 <<
4817 <<
4818 <<
4819 }; <<
4820 <<
4821 opp-2 <<
4822 <<
4823 <<
4824 }; <<
4825 <<
4826 opp-5 <<
4827 <<
4828 <<
4829 }; <<
4830 <<
4831 opp-8 <<
4832 <<
4833 <<
4834 }; <<
4835 }; <<
4836 }; <<
4837 <<
4838 mdss_dsi0: dsi@ae9400 4391 mdss_dsi0: dsi@ae94000 {
4839 compatible = 4392 compatible = "qcom,sm8250-dsi-ctrl",
4840 4393 "qcom,mdss-dsi-ctrl";
4841 reg = <0 0x0a 4394 reg = <0 0x0ae94000 0 0x400>;
4842 reg-names = " 4395 reg-names = "dsi_ctrl";
4843 4396
4844 interrupt-par 4397 interrupt-parent = <&mdss>;
4845 interrupts = 4398 interrupts = <4>;
4846 4399
4847 clocks = <&di 4400 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
4848 <&di 4401 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
4849 <&di 4402 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
4850 <&di 4403 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
4851 <&di 4404 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4852 <&gcc 4405 <&gcc GCC_DISP_HF_AXI_CLK>;
4853 clock-names = 4406 clock-names = "byte",
4854 4407 "byte_intf",
4855 4408 "pixel",
4856 4409 "core",
4857 4410 "iface",
4858 4411 "bus";
4859 4412
4860 assigned-cloc 4413 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
4861 assigned-cloc 4414 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
4862 4415
4863 operating-poi 4416 operating-points-v2 = <&dsi_opp_table>;
4864 power-domains 4417 power-domains = <&rpmhpd RPMHPD_MMCX>;
4865 4418
4866 phys = <&mdss 4419 phys = <&mdss_dsi0_phy>;
4867 4420
4868 status = "dis 4421 status = "disabled";
4869 4422
4870 #address-cell 4423 #address-cells = <1>;
4871 #size-cells = 4424 #size-cells = <0>;
4872 4425
4873 ports { 4426 ports {
4874 #addr 4427 #address-cells = <1>;
4875 #size 4428 #size-cells = <0>;
4876 4429
4877 port@ 4430 port@0 {
4878 4431 reg = <0>;
4879 4432 mdss_dsi0_in: endpoint {
4880 4433 remote-endpoint = <&dpu_intf1_out>;
4881 4434 };
4882 }; 4435 };
4883 4436
4884 port@ 4437 port@1 {
4885 4438 reg = <1>;
4886 4439 mdss_dsi0_out: endpoint {
4887 4440 };
4888 }; 4441 };
4889 }; 4442 };
4890 4443
4891 dsi_opp_table 4444 dsi_opp_table: opp-table {
4892 compa 4445 compatible = "operating-points-v2";
4893 4446
4894 opp-1 4447 opp-187500000 {
4895 4448 opp-hz = /bits/ 64 <187500000>;
4896 4449 required-opps = <&rpmhpd_opp_low_svs>;
4897 }; 4450 };
4898 4451
4899 opp-3 4452 opp-300000000 {
4900 4453 opp-hz = /bits/ 64 <300000000>;
4901 4454 required-opps = <&rpmhpd_opp_svs>;
4902 }; 4455 };
4903 4456
4904 opp-3 4457 opp-358000000 {
4905 4458 opp-hz = /bits/ 64 <358000000>;
4906 4459 required-opps = <&rpmhpd_opp_svs_l1>;
4907 }; 4460 };
4908 }; 4461 };
4909 }; 4462 };
4910 4463
4911 mdss_dsi0_phy: phy@ae 4464 mdss_dsi0_phy: phy@ae94400 {
4912 compatible = 4465 compatible = "qcom,dsi-phy-7nm";
4913 reg = <0 0x0a 4466 reg = <0 0x0ae94400 0 0x200>,
4914 <0 0x0a 4467 <0 0x0ae94600 0 0x280>,
4915 <0 0x0a 4468 <0 0x0ae94900 0 0x260>;
4916 reg-names = " 4469 reg-names = "dsi_phy",
4917 " 4470 "dsi_phy_lane",
4918 " 4471 "dsi_pll";
4919 4472
4920 #clock-cells 4473 #clock-cells = <1>;
4921 #phy-cells = 4474 #phy-cells = <0>;
4922 4475
4923 clocks = <&di 4476 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4924 <&rp 4477 <&rpmhcc RPMH_CXO_CLK>;
4925 clock-names = 4478 clock-names = "iface", "ref";
4926 4479
4927 status = "dis 4480 status = "disabled";
4928 }; 4481 };
4929 4482
4930 mdss_dsi1: dsi@ae9600 4483 mdss_dsi1: dsi@ae96000 {
4931 compatible = 4484 compatible = "qcom,sm8250-dsi-ctrl",
4932 4485 "qcom,mdss-dsi-ctrl";
4933 reg = <0 0x0a 4486 reg = <0 0x0ae96000 0 0x400>;
4934 reg-names = " 4487 reg-names = "dsi_ctrl";
4935 4488
4936 interrupt-par 4489 interrupt-parent = <&mdss>;
4937 interrupts = 4490 interrupts = <5>;
4938 4491
4939 clocks = <&di 4492 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
4940 <&di 4493 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
4941 <&di 4494 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
4942 <&di 4495 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
4943 <&di 4496 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4944 <&gc 4497 <&gcc GCC_DISP_HF_AXI_CLK>;
4945 clock-names = 4498 clock-names = "byte",
4946 4499 "byte_intf",
4947 4500 "pixel",
4948 4501 "core",
4949 4502 "iface",
4950 4503 "bus";
4951 4504
4952 assigned-cloc 4505 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
4953 assigned-cloc 4506 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
4954 4507
4955 operating-poi 4508 operating-points-v2 = <&dsi_opp_table>;
4956 power-domains 4509 power-domains = <&rpmhpd RPMHPD_MMCX>;
4957 4510
4958 phys = <&mdss 4511 phys = <&mdss_dsi1_phy>;
4959 4512
4960 status = "dis 4513 status = "disabled";
4961 4514
4962 #address-cell 4515 #address-cells = <1>;
4963 #size-cells = 4516 #size-cells = <0>;
4964 4517
4965 ports { 4518 ports {
4966 #addr 4519 #address-cells = <1>;
4967 #size 4520 #size-cells = <0>;
4968 4521
4969 port@ 4522 port@0 {
4970 4523 reg = <0>;
4971 4524 mdss_dsi1_in: endpoint {
4972 4525 remote-endpoint = <&dpu_intf2_out>;
4973 4526 };
4974 }; 4527 };
4975 4528
4976 port@ 4529 port@1 {
4977 4530 reg = <1>;
4978 4531 mdss_dsi1_out: endpoint {
4979 4532 };
4980 }; 4533 };
4981 }; 4534 };
4982 }; 4535 };
4983 4536
4984 mdss_dsi1_phy: phy@ae 4537 mdss_dsi1_phy: phy@ae96400 {
4985 compatible = 4538 compatible = "qcom,dsi-phy-7nm";
4986 reg = <0 0x0a 4539 reg = <0 0x0ae96400 0 0x200>,
4987 <0 0x0a 4540 <0 0x0ae96600 0 0x280>,
4988 <0 0x0a 4541 <0 0x0ae96900 0 0x260>;
4989 reg-names = " 4542 reg-names = "dsi_phy",
4990 " 4543 "dsi_phy_lane",
4991 " 4544 "dsi_pll";
4992 4545
4993 #clock-cells 4546 #clock-cells = <1>;
4994 #phy-cells = 4547 #phy-cells = <0>;
4995 4548
4996 clocks = <&di 4549 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4997 <&rp 4550 <&rpmhcc RPMH_CXO_CLK>;
4998 clock-names = 4551 clock-names = "iface", "ref";
4999 4552
5000 status = "dis 4553 status = "disabled";
5001 }; 4554 };
5002 }; 4555 };
5003 4556
5004 dispcc: clock-controller@af00 4557 dispcc: clock-controller@af00000 {
5005 compatible = "qcom,sm 4558 compatible = "qcom,sm8250-dispcc";
5006 reg = <0 0x0af00000 0 4559 reg = <0 0x0af00000 0 0x10000>;
5007 power-domains = <&rpm 4560 power-domains = <&rpmhpd RPMHPD_MMCX>;
5008 required-opps = <&rpm 4561 required-opps = <&rpmhpd_opp_low_svs>;
5009 clocks = <&rpmhcc RPM 4562 clocks = <&rpmhcc RPMH_CXO_CLK>,
5010 <&mdss_dsi0_ 4563 <&mdss_dsi0_phy 0>,
5011 <&mdss_dsi0_ 4564 <&mdss_dsi0_phy 1>,
5012 <&mdss_dsi1_ 4565 <&mdss_dsi1_phy 0>,
5013 <&mdss_dsi1_ 4566 <&mdss_dsi1_phy 1>,
5014 <&usb_1_qmpp !! 4567 <&dp_phy 0>,
5015 <&usb_1_qmpp !! 4568 <&dp_phy 1>;
5016 clock-names = "bi_tcx 4569 clock-names = "bi_tcxo",
5017 "dsi0_p 4570 "dsi0_phy_pll_out_byteclk",
5018 "dsi0_p 4571 "dsi0_phy_pll_out_dsiclk",
5019 "dsi1_p 4572 "dsi1_phy_pll_out_byteclk",
5020 "dsi1_p 4573 "dsi1_phy_pll_out_dsiclk",
5021 "dp_phy 4574 "dp_phy_pll_link_clk",
5022 "dp_phy 4575 "dp_phy_pll_vco_div_clk";
5023 #clock-cells = <1>; 4576 #clock-cells = <1>;
5024 #reset-cells = <1>; 4577 #reset-cells = <1>;
5025 #power-domain-cells = 4578 #power-domain-cells = <1>;
5026 }; 4579 };
5027 4580
5028 pdc: interrupt-controller@b22 4581 pdc: interrupt-controller@b220000 {
5029 compatible = "qcom,sm 4582 compatible = "qcom,sm8250-pdc", "qcom,pdc";
5030 reg = <0 0x0b220000 0 4583 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
5031 qcom,pdc-ranges = <0 4584 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
5032 <12 4585 <125 63 1>, <126 716 12>;
5033 #interrupt-cells = <2 4586 #interrupt-cells = <2>;
5034 interrupt-parent = <& 4587 interrupt-parent = <&intc>;
5035 interrupt-controller; 4588 interrupt-controller;
5036 }; 4589 };
5037 4590
5038 tsens0: thermal-sensor@c26300 4591 tsens0: thermal-sensor@c263000 {
5039 compatible = "qcom,sm 4592 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
5040 reg = <0 0x0c263000 0 4593 reg = <0 0x0c263000 0 0x1ff>, /* TM */
5041 <0 0x0c222000 0 4594 <0 0x0c222000 0 0x1ff>; /* SROT */
5042 #qcom,sensors = <16>; 4595 #qcom,sensors = <16>;
5043 interrupts = <GIC_SPI 4596 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
5044 <GIC_SPI 4597 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
5045 interrupt-names = "up 4598 interrupt-names = "uplow", "critical";
5046 #thermal-sensor-cells 4599 #thermal-sensor-cells = <1>;
5047 }; 4600 };
5048 4601
5049 tsens1: thermal-sensor@c26500 4602 tsens1: thermal-sensor@c265000 {
5050 compatible = "qcom,sm 4603 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
5051 reg = <0 0x0c265000 0 4604 reg = <0 0x0c265000 0 0x1ff>, /* TM */
5052 <0 0x0c223000 0 4605 <0 0x0c223000 0 0x1ff>; /* SROT */
5053 #qcom,sensors = <9>; 4606 #qcom,sensors = <9>;
5054 interrupts = <GIC_SPI 4607 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
5055 <GIC_SPI 4608 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
5056 interrupt-names = "up 4609 interrupt-names = "uplow", "critical";
5057 #thermal-sensor-cells 4610 #thermal-sensor-cells = <1>;
5058 }; 4611 };
5059 4612
5060 aoss_qmp: power-management@c3 4613 aoss_qmp: power-management@c300000 {
5061 compatible = "qcom,sm 4614 compatible = "qcom,sm8250-aoss-qmp", "qcom,aoss-qmp";
5062 reg = <0 0x0c300000 0 4615 reg = <0 0x0c300000 0 0x400>;
5063 interrupts-extended = 4616 interrupts-extended = <&ipcc IPCC_CLIENT_AOP
5064 4617 IPCC_MPROC_SIGNAL_GLINK_QMP
5065 4618 IRQ_TYPE_EDGE_RISING>;
5066 mboxes = <&ipcc IPCC_ 4619 mboxes = <&ipcc IPCC_CLIENT_AOP
5067 IPCC_ 4620 IPCC_MPROC_SIGNAL_GLINK_QMP>;
5068 4621
5069 #clock-cells = <0>; 4622 #clock-cells = <0>;
5070 }; 4623 };
5071 4624
5072 sram@c3f0000 { 4625 sram@c3f0000 {
5073 compatible = "qcom,rp 4626 compatible = "qcom,rpmh-stats";
5074 reg = <0 0x0c3f0000 0 4627 reg = <0 0x0c3f0000 0 0x400>;
5075 }; 4628 };
5076 4629
5077 spmi_bus: spmi@c440000 { 4630 spmi_bus: spmi@c440000 {
5078 compatible = "qcom,sp 4631 compatible = "qcom,spmi-pmic-arb";
5079 reg = <0x0 0x0c440000 4632 reg = <0x0 0x0c440000 0x0 0x0001100>,
5080 <0x0 0x0c600000 4633 <0x0 0x0c600000 0x0 0x2000000>,
5081 <0x0 0x0e600000 4634 <0x0 0x0e600000 0x0 0x0100000>,
5082 <0x0 0x0e700000 4635 <0x0 0x0e700000 0x0 0x00a0000>,
5083 <0x0 0x0c40a000 4636 <0x0 0x0c40a000 0x0 0x0026000>;
5084 reg-names = "core", " 4637 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
5085 interrupt-names = "pe 4638 interrupt-names = "periph_irq";
5086 interrupts-extended = 4639 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
5087 qcom,ee = <0>; 4640 qcom,ee = <0>;
5088 qcom,channel = <0>; 4641 qcom,channel = <0>;
5089 #address-cells = <2>; 4642 #address-cells = <2>;
5090 #size-cells = <0>; 4643 #size-cells = <0>;
5091 interrupt-controller; 4644 interrupt-controller;
5092 #interrupt-cells = <4 4645 #interrupt-cells = <4>;
5093 }; 4646 };
5094 4647
5095 tlmm: pinctrl@f100000 { 4648 tlmm: pinctrl@f100000 {
5096 compatible = "qcom,sm 4649 compatible = "qcom,sm8250-pinctrl";
5097 reg = <0 0x0f100000 0 4650 reg = <0 0x0f100000 0 0x300000>,
5098 <0 0x0f500000 0 4651 <0 0x0f500000 0 0x300000>,
5099 <0 0x0f900000 0 4652 <0 0x0f900000 0 0x300000>;
5100 reg-names = "west", " 4653 reg-names = "west", "south", "north";
5101 interrupts = <GIC_SPI 4654 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
5102 gpio-controller; 4655 gpio-controller;
5103 #gpio-cells = <2>; 4656 #gpio-cells = <2>;
5104 interrupt-controller; 4657 interrupt-controller;
5105 #interrupt-cells = <2 4658 #interrupt-cells = <2>;
5106 gpio-ranges = <&tlmm 4659 gpio-ranges = <&tlmm 0 0 181>;
5107 wakeup-parent = <&pdc 4660 wakeup-parent = <&pdc>;
5108 4661
5109 cam2_default: cam2-de 4662 cam2_default: cam2-default-state {
5110 rst-pins { 4663 rst-pins {
5111 pins 4664 pins = "gpio78";
5112 funct 4665 function = "gpio";
5113 drive 4666 drive-strength = <2>;
5114 bias- 4667 bias-disable;
5115 }; 4668 };
5116 4669
5117 mclk-pins { 4670 mclk-pins {
5118 pins 4671 pins = "gpio96";
5119 funct 4672 function = "cam_mclk";
5120 drive 4673 drive-strength = <16>;
5121 bias- 4674 bias-disable;
5122 }; 4675 };
5123 }; 4676 };
5124 4677
5125 cam2_suspend: cam2-su 4678 cam2_suspend: cam2-suspend-state {
5126 rst-pins { 4679 rst-pins {
5127 pins 4680 pins = "gpio78";
5128 funct 4681 function = "gpio";
5129 drive 4682 drive-strength = <2>;
5130 bias- 4683 bias-pull-down;
5131 outpu 4684 output-low;
5132 }; 4685 };
5133 4686
5134 mclk-pins { 4687 mclk-pins {
5135 pins 4688 pins = "gpio96";
5136 funct 4689 function = "cam_mclk";
5137 drive 4690 drive-strength = <2>;
5138 bias- 4691 bias-disable;
5139 }; 4692 };
5140 }; 4693 };
5141 4694
5142 cci0_default: cci0-de 4695 cci0_default: cci0-default-state {
5143 cci0_i2c0_def 4696 cci0_i2c0_default: cci0-i2c0-default-pins {
5144 /* SD 4697 /* SDA, SCL */
5145 pins 4698 pins = "gpio101", "gpio102";
5146 funct 4699 function = "cci_i2c";
5147 4700
5148 bias- 4701 bias-pull-up;
5149 drive 4702 drive-strength = <2>; /* 2 mA */
5150 }; 4703 };
5151 4704
5152 cci0_i2c1_def 4705 cci0_i2c1_default: cci0-i2c1-default-pins {
5153 /* SD 4706 /* SDA, SCL */
5154 pins 4707 pins = "gpio103", "gpio104";
5155 funct 4708 function = "cci_i2c";
5156 4709
5157 bias- 4710 bias-pull-up;
5158 drive 4711 drive-strength = <2>; /* 2 mA */
5159 }; 4712 };
5160 }; 4713 };
5161 4714
5162 cci0_sleep: cci0-slee 4715 cci0_sleep: cci0-sleep-state {
5163 cci0_i2c0_sle 4716 cci0_i2c0_sleep: cci0-i2c0-sleep-pins {
5164 /* SD 4717 /* SDA, SCL */
5165 pins 4718 pins = "gpio101", "gpio102";
5166 funct 4719 function = "cci_i2c";
5167 4720
5168 drive 4721 drive-strength = <2>; /* 2 mA */
5169 bias- 4722 bias-pull-down;
5170 }; 4723 };
5171 4724
5172 cci0_i2c1_sle 4725 cci0_i2c1_sleep: cci0-i2c1-sleep-pins {
5173 /* SD 4726 /* SDA, SCL */
5174 pins 4727 pins = "gpio103", "gpio104";
5175 funct 4728 function = "cci_i2c";
5176 4729
5177 drive 4730 drive-strength = <2>; /* 2 mA */
5178 bias- 4731 bias-pull-down;
5179 }; 4732 };
5180 }; 4733 };
5181 4734
5182 cci1_default: cci1-de 4735 cci1_default: cci1-default-state {
5183 cci1_i2c0_def 4736 cci1_i2c0_default: cci1-i2c0-default-pins {
5184 /* SD 4737 /* SDA, SCL */
5185 pins 4738 pins = "gpio105","gpio106";
5186 funct 4739 function = "cci_i2c";
5187 4740
5188 bias- 4741 bias-pull-up;
5189 drive 4742 drive-strength = <2>; /* 2 mA */
5190 }; 4743 };
5191 4744
5192 cci1_i2c1_def 4745 cci1_i2c1_default: cci1-i2c1-default-pins {
5193 /* SD 4746 /* SDA, SCL */
5194 pins 4747 pins = "gpio107","gpio108";
5195 funct 4748 function = "cci_i2c";
5196 4749
5197 bias- 4750 bias-pull-up;
5198 drive 4751 drive-strength = <2>; /* 2 mA */
5199 }; 4752 };
5200 }; 4753 };
5201 4754
5202 cci1_sleep: cci1-slee 4755 cci1_sleep: cci1-sleep-state {
5203 cci1_i2c0_sle 4756 cci1_i2c0_sleep: cci1-i2c0-sleep-pins {
5204 /* SD 4757 /* SDA, SCL */
5205 pins 4758 pins = "gpio105","gpio106";
5206 funct 4759 function = "cci_i2c";
5207 4760
5208 bias- 4761 bias-pull-down;
5209 drive 4762 drive-strength = <2>; /* 2 mA */
5210 }; 4763 };
5211 4764
5212 cci1_i2c1_sle 4765 cci1_i2c1_sleep: cci1-i2c1-sleep-pins {
5213 /* SD 4766 /* SDA, SCL */
5214 pins 4767 pins = "gpio107","gpio108";
5215 funct 4768 function = "cci_i2c";
5216 4769
5217 bias- 4770 bias-pull-down;
5218 drive 4771 drive-strength = <2>; /* 2 mA */
5219 }; 4772 };
5220 }; 4773 };
5221 4774
5222 pri_mi2s_active: pri- 4775 pri_mi2s_active: pri-mi2s-active-state {
5223 sclk-pins { 4776 sclk-pins {
5224 pins 4777 pins = "gpio138";
5225 funct 4778 function = "mi2s0_sck";
5226 drive 4779 drive-strength = <8>;
5227 bias- 4780 bias-disable;
5228 }; 4781 };
5229 4782
5230 ws-pins { 4783 ws-pins {
5231 pins 4784 pins = "gpio141";
5232 funct 4785 function = "mi2s0_ws";
5233 drive 4786 drive-strength = <8>;
5234 outpu 4787 output-high;
5235 }; 4788 };
5236 4789
5237 data0-pins { 4790 data0-pins {
5238 pins 4791 pins = "gpio139";
5239 funct 4792 function = "mi2s0_data0";
5240 drive 4793 drive-strength = <8>;
5241 bias- 4794 bias-disable;
5242 outpu 4795 output-high;
5243 }; 4796 };
5244 4797
5245 data1-pins { 4798 data1-pins {
5246 pins 4799 pins = "gpio140";
5247 funct 4800 function = "mi2s0_data1";
5248 drive 4801 drive-strength = <8>;
5249 outpu 4802 output-high;
5250 }; 4803 };
5251 }; 4804 };
5252 4805
5253 qup_i2c0_default: qup 4806 qup_i2c0_default: qup-i2c0-default-state {
5254 pins = "gpio2 4807 pins = "gpio28", "gpio29";
5255 function = "q 4808 function = "qup0";
5256 drive-strengt 4809 drive-strength = <2>;
5257 bias-disable; 4810 bias-disable;
5258 }; 4811 };
5259 4812
5260 qup_i2c1_default: qup 4813 qup_i2c1_default: qup-i2c1-default-state {
5261 pins = "gpio4 4814 pins = "gpio4", "gpio5";
5262 function = "q 4815 function = "qup1";
5263 drive-strengt 4816 drive-strength = <2>;
5264 bias-disable; 4817 bias-disable;
5265 }; 4818 };
5266 4819
5267 qup_i2c2_default: qup 4820 qup_i2c2_default: qup-i2c2-default-state {
5268 pins = "gpio1 4821 pins = "gpio115", "gpio116";
5269 function = "q 4822 function = "qup2";
5270 drive-strengt 4823 drive-strength = <2>;
5271 bias-disable; 4824 bias-disable;
5272 }; 4825 };
5273 4826
5274 qup_i2c3_default: qup 4827 qup_i2c3_default: qup-i2c3-default-state {
5275 pins = "gpio1 4828 pins = "gpio119", "gpio120";
5276 function = "q 4829 function = "qup3";
5277 drive-strengt 4830 drive-strength = <2>;
5278 bias-disable; 4831 bias-disable;
5279 }; 4832 };
5280 4833
5281 qup_i2c4_default: qup 4834 qup_i2c4_default: qup-i2c4-default-state {
5282 pins = "gpio8 4835 pins = "gpio8", "gpio9";
5283 function = "q 4836 function = "qup4";
5284 drive-strengt 4837 drive-strength = <2>;
5285 bias-disable; 4838 bias-disable;
5286 }; 4839 };
5287 4840
5288 qup_i2c5_default: qup 4841 qup_i2c5_default: qup-i2c5-default-state {
5289 pins = "gpio1 4842 pins = "gpio12", "gpio13";
5290 function = "q 4843 function = "qup5";
5291 drive-strengt 4844 drive-strength = <2>;
5292 bias-disable; 4845 bias-disable;
5293 }; 4846 };
5294 4847
5295 qup_i2c6_default: qup 4848 qup_i2c6_default: qup-i2c6-default-state {
5296 pins = "gpio1 4849 pins = "gpio16", "gpio17";
5297 function = "q 4850 function = "qup6";
5298 drive-strengt 4851 drive-strength = <2>;
5299 bias-disable; 4852 bias-disable;
5300 }; 4853 };
5301 4854
5302 qup_i2c7_default: qup 4855 qup_i2c7_default: qup-i2c7-default-state {
5303 pins = "gpio2 4856 pins = "gpio20", "gpio21";
5304 function = "q 4857 function = "qup7";
5305 drive-strengt 4858 drive-strength = <2>;
5306 bias-disable; 4859 bias-disable;
5307 }; 4860 };
5308 4861
5309 qup_i2c8_default: qup 4862 qup_i2c8_default: qup-i2c8-default-state {
5310 pins = "gpio2 4863 pins = "gpio24", "gpio25";
5311 function = "q 4864 function = "qup8";
5312 drive-strengt 4865 drive-strength = <2>;
5313 bias-disable; 4866 bias-disable;
5314 }; 4867 };
5315 4868
5316 qup_i2c9_default: qup 4869 qup_i2c9_default: qup-i2c9-default-state {
5317 pins = "gpio1 4870 pins = "gpio125", "gpio126";
5318 function = "q 4871 function = "qup9";
5319 drive-strengt 4872 drive-strength = <2>;
5320 bias-disable; 4873 bias-disable;
5321 }; 4874 };
5322 4875
5323 qup_i2c10_default: qu 4876 qup_i2c10_default: qup-i2c10-default-state {
5324 pins = "gpio1 4877 pins = "gpio129", "gpio130";
5325 function = "q 4878 function = "qup10";
5326 drive-strengt 4879 drive-strength = <2>;
5327 bias-disable; 4880 bias-disable;
5328 }; 4881 };
5329 4882
5330 qup_i2c11_default: qu 4883 qup_i2c11_default: qup-i2c11-default-state {
5331 pins = "gpio6 4884 pins = "gpio60", "gpio61";
5332 function = "q 4885 function = "qup11";
5333 drive-strengt 4886 drive-strength = <2>;
5334 bias-disable; 4887 bias-disable;
5335 }; 4888 };
5336 4889
5337 qup_i2c12_default: qu 4890 qup_i2c12_default: qup-i2c12-default-state {
5338 pins = "gpio3 4891 pins = "gpio32", "gpio33";
5339 function = "q 4892 function = "qup12";
5340 drive-strengt 4893 drive-strength = <2>;
5341 bias-disable; 4894 bias-disable;
5342 }; 4895 };
5343 4896
5344 qup_i2c13_default: qu 4897 qup_i2c13_default: qup-i2c13-default-state {
5345 pins = "gpio3 4898 pins = "gpio36", "gpio37";
5346 function = "q 4899 function = "qup13";
5347 drive-strengt 4900 drive-strength = <2>;
5348 bias-disable; 4901 bias-disable;
5349 }; 4902 };
5350 4903
5351 qup_i2c14_default: qu 4904 qup_i2c14_default: qup-i2c14-default-state {
5352 pins = "gpio4 4905 pins = "gpio40", "gpio41";
5353 function = "q 4906 function = "qup14";
5354 drive-strengt 4907 drive-strength = <2>;
5355 bias-disable; 4908 bias-disable;
5356 }; 4909 };
5357 4910
5358 qup_i2c15_default: qu 4911 qup_i2c15_default: qup-i2c15-default-state {
5359 pins = "gpio4 4912 pins = "gpio44", "gpio45";
5360 function = "q 4913 function = "qup15";
5361 drive-strengt 4914 drive-strength = <2>;
5362 bias-disable; 4915 bias-disable;
5363 }; 4916 };
5364 4917
5365 qup_i2c16_default: qu 4918 qup_i2c16_default: qup-i2c16-default-state {
5366 pins = "gpio4 4919 pins = "gpio48", "gpio49";
5367 function = "q 4920 function = "qup16";
5368 drive-strengt 4921 drive-strength = <2>;
5369 bias-disable; 4922 bias-disable;
5370 }; 4923 };
5371 4924
5372 qup_i2c17_default: qu 4925 qup_i2c17_default: qup-i2c17-default-state {
5373 pins = "gpio5 4926 pins = "gpio52", "gpio53";
5374 function = "q 4927 function = "qup17";
5375 drive-strengt 4928 drive-strength = <2>;
5376 bias-disable; 4929 bias-disable;
5377 }; 4930 };
5378 4931
5379 qup_i2c18_default: qu 4932 qup_i2c18_default: qup-i2c18-default-state {
5380 pins = "gpio5 4933 pins = "gpio56", "gpio57";
5381 function = "q 4934 function = "qup18";
5382 drive-strengt 4935 drive-strength = <2>;
5383 bias-disable; 4936 bias-disable;
5384 }; 4937 };
5385 4938
5386 qup_i2c19_default: qu 4939 qup_i2c19_default: qup-i2c19-default-state {
5387 pins = "gpio0 4940 pins = "gpio0", "gpio1";
5388 function = "q 4941 function = "qup19";
5389 drive-strengt 4942 drive-strength = <2>;
5390 bias-disable; 4943 bias-disable;
5391 }; 4944 };
5392 4945
5393 qup_spi0_cs: qup-spi0 4946 qup_spi0_cs: qup-spi0-cs-state {
5394 pins = "gpio3 4947 pins = "gpio31";
5395 function = "q 4948 function = "qup0";
5396 }; 4949 };
5397 4950
5398 qup_spi0_cs_gpio: qup 4951 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state {
5399 pins = "gpio3 4952 pins = "gpio31";
5400 function = "g 4953 function = "gpio";
5401 }; 4954 };
5402 4955
5403 qup_spi0_data_clk: qu 4956 qup_spi0_data_clk: qup-spi0-data-clk-state {
5404 pins = "gpio2 4957 pins = "gpio28", "gpio29",
5405 "gpio3 4958 "gpio30";
5406 function = "q 4959 function = "qup0";
5407 }; 4960 };
5408 4961
5409 qup_spi1_cs: qup-spi1 4962 qup_spi1_cs: qup-spi1-cs-state {
5410 pins = "gpio7 4963 pins = "gpio7";
5411 function = "q 4964 function = "qup1";
5412 }; 4965 };
5413 4966
5414 qup_spi1_cs_gpio: qup 4967 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state {
5415 pins = "gpio7 4968 pins = "gpio7";
5416 function = "g 4969 function = "gpio";
5417 }; 4970 };
5418 4971
5419 qup_spi1_data_clk: qu 4972 qup_spi1_data_clk: qup-spi1-data-clk-state {
5420 pins = "gpio4 4973 pins = "gpio4", "gpio5",
5421 "gpio6 4974 "gpio6";
5422 function = "q 4975 function = "qup1";
5423 }; 4976 };
5424 4977
5425 qup_spi2_cs: qup-spi2 4978 qup_spi2_cs: qup-spi2-cs-state {
5426 pins = "gpio1 4979 pins = "gpio118";
5427 function = "q 4980 function = "qup2";
5428 }; 4981 };
5429 4982
5430 qup_spi2_cs_gpio: qup 4983 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state {
5431 pins = "gpio1 4984 pins = "gpio118";
5432 function = "g 4985 function = "gpio";
5433 }; 4986 };
5434 4987
5435 qup_spi2_data_clk: qu 4988 qup_spi2_data_clk: qup-spi2-data-clk-state {
5436 pins = "gpio1 4989 pins = "gpio115", "gpio116",
5437 "gpio1 4990 "gpio117";
5438 function = "q 4991 function = "qup2";
5439 }; 4992 };
5440 4993
5441 qup_spi3_cs: qup-spi3 4994 qup_spi3_cs: qup-spi3-cs-state {
5442 pins = "gpio1 4995 pins = "gpio122";
5443 function = "q 4996 function = "qup3";
5444 }; 4997 };
5445 4998
5446 qup_spi3_cs_gpio: qup 4999 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state {
5447 pins = "gpio1 5000 pins = "gpio122";
5448 function = "g 5001 function = "gpio";
5449 }; 5002 };
5450 5003
5451 qup_spi3_data_clk: qu 5004 qup_spi3_data_clk: qup-spi3-data-clk-state {
5452 pins = "gpio1 5005 pins = "gpio119", "gpio120",
5453 "gpio1 5006 "gpio121";
5454 function = "q 5007 function = "qup3";
5455 }; 5008 };
5456 5009
5457 qup_spi4_cs: qup-spi4 5010 qup_spi4_cs: qup-spi4-cs-state {
5458 pins = "gpio1 5011 pins = "gpio11";
5459 function = "q 5012 function = "qup4";
5460 }; 5013 };
5461 5014
5462 qup_spi4_cs_gpio: qup 5015 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state {
5463 pins = "gpio1 5016 pins = "gpio11";
5464 function = "g 5017 function = "gpio";
5465 }; 5018 };
5466 5019
5467 qup_spi4_data_clk: qu 5020 qup_spi4_data_clk: qup-spi4-data-clk-state {
5468 pins = "gpio8 5021 pins = "gpio8", "gpio9",
5469 "gpio1 5022 "gpio10";
5470 function = "q 5023 function = "qup4";
5471 }; 5024 };
5472 5025
5473 qup_spi5_cs: qup-spi5 5026 qup_spi5_cs: qup-spi5-cs-state {
5474 pins = "gpio1 5027 pins = "gpio15";
5475 function = "q 5028 function = "qup5";
5476 }; 5029 };
5477 5030
5478 qup_spi5_cs_gpio: qup 5031 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state {
5479 pins = "gpio1 5032 pins = "gpio15";
5480 function = "g 5033 function = "gpio";
5481 }; 5034 };
5482 5035
5483 qup_spi5_data_clk: qu 5036 qup_spi5_data_clk: qup-spi5-data-clk-state {
5484 pins = "gpio1 5037 pins = "gpio12", "gpio13",
5485 "gpio1 5038 "gpio14";
5486 function = "q 5039 function = "qup5";
5487 }; 5040 };
5488 5041
5489 qup_spi6_cs: qup-spi6 5042 qup_spi6_cs: qup-spi6-cs-state {
5490 pins = "gpio1 5043 pins = "gpio19";
5491 function = "q 5044 function = "qup6";
5492 }; 5045 };
5493 5046
5494 qup_spi6_cs_gpio: qup 5047 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state {
5495 pins = "gpio1 5048 pins = "gpio19";
5496 function = "g 5049 function = "gpio";
5497 }; 5050 };
5498 5051
5499 qup_spi6_data_clk: qu 5052 qup_spi6_data_clk: qup-spi6-data-clk-state {
5500 pins = "gpio1 5053 pins = "gpio16", "gpio17",
5501 "gpio1 5054 "gpio18";
5502 function = "q 5055 function = "qup6";
5503 }; 5056 };
5504 5057
5505 qup_spi7_cs: qup-spi7 5058 qup_spi7_cs: qup-spi7-cs-state {
5506 pins = "gpio2 5059 pins = "gpio23";
5507 function = "q 5060 function = "qup7";
5508 }; 5061 };
5509 5062
5510 qup_spi7_cs_gpio: qup 5063 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state {
5511 pins = "gpio2 5064 pins = "gpio23";
5512 function = "g 5065 function = "gpio";
5513 }; 5066 };
5514 5067
5515 qup_spi7_data_clk: qu 5068 qup_spi7_data_clk: qup-spi7-data-clk-state {
5516 pins = "gpio2 5069 pins = "gpio20", "gpio21",
5517 "gpio2 5070 "gpio22";
5518 function = "q 5071 function = "qup7";
5519 }; 5072 };
5520 5073
5521 qup_spi8_cs: qup-spi8 5074 qup_spi8_cs: qup-spi8-cs-state {
5522 pins = "gpio2 5075 pins = "gpio27";
5523 function = "q 5076 function = "qup8";
5524 }; 5077 };
5525 5078
5526 qup_spi8_cs_gpio: qup 5079 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state {
5527 pins = "gpio2 5080 pins = "gpio27";
5528 function = "g 5081 function = "gpio";
5529 }; 5082 };
5530 5083
5531 qup_spi8_data_clk: qu 5084 qup_spi8_data_clk: qup-spi8-data-clk-state {
5532 pins = "gpio2 5085 pins = "gpio24", "gpio25",
5533 "gpio2 5086 "gpio26";
5534 function = "q 5087 function = "qup8";
5535 }; 5088 };
5536 5089
5537 qup_spi9_cs: qup-spi9 5090 qup_spi9_cs: qup-spi9-cs-state {
5538 pins = "gpio1 5091 pins = "gpio128";
5539 function = "q 5092 function = "qup9";
5540 }; 5093 };
5541 5094
5542 qup_spi9_cs_gpio: qup 5095 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state {
5543 pins = "gpio1 5096 pins = "gpio128";
5544 function = "g 5097 function = "gpio";
5545 }; 5098 };
5546 5099
5547 qup_spi9_data_clk: qu 5100 qup_spi9_data_clk: qup-spi9-data-clk-state {
5548 pins = "gpio1 5101 pins = "gpio125", "gpio126",
5549 "gpio1 5102 "gpio127";
5550 function = "q 5103 function = "qup9";
5551 }; 5104 };
5552 5105
5553 qup_spi10_cs: qup-spi 5106 qup_spi10_cs: qup-spi10-cs-state {
5554 pins = "gpio1 5107 pins = "gpio132";
5555 function = "q 5108 function = "qup10";
5556 }; 5109 };
5557 5110
5558 qup_spi10_cs_gpio: qu 5111 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state {
5559 pins = "gpio1 5112 pins = "gpio132";
5560 function = "g 5113 function = "gpio";
5561 }; 5114 };
5562 5115
5563 qup_spi10_data_clk: q 5116 qup_spi10_data_clk: qup-spi10-data-clk-state {
5564 pins = "gpio1 5117 pins = "gpio129", "gpio130",
5565 "gpio1 5118 "gpio131";
5566 function = "q 5119 function = "qup10";
5567 }; 5120 };
5568 5121
5569 qup_spi11_cs: qup-spi 5122 qup_spi11_cs: qup-spi11-cs-state {
5570 pins = "gpio6 5123 pins = "gpio63";
5571 function = "q 5124 function = "qup11";
5572 }; 5125 };
5573 5126
5574 qup_spi11_cs_gpio: qu 5127 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state {
5575 pins = "gpio6 5128 pins = "gpio63";
5576 function = "g 5129 function = "gpio";
5577 }; 5130 };
5578 5131
5579 qup_spi11_data_clk: q 5132 qup_spi11_data_clk: qup-spi11-data-clk-state {
5580 pins = "gpio6 5133 pins = "gpio60", "gpio61",
5581 "gpio6 5134 "gpio62";
5582 function = "q 5135 function = "qup11";
5583 }; 5136 };
5584 5137
5585 qup_spi12_cs: qup-spi 5138 qup_spi12_cs: qup-spi12-cs-state {
5586 pins = "gpio3 5139 pins = "gpio35";
5587 function = "q 5140 function = "qup12";
5588 }; 5141 };
5589 5142
5590 qup_spi12_cs_gpio: qu 5143 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state {
5591 pins = "gpio3 5144 pins = "gpio35";
5592 function = "g 5145 function = "gpio";
5593 }; 5146 };
5594 5147
5595 qup_spi12_data_clk: q 5148 qup_spi12_data_clk: qup-spi12-data-clk-state {
5596 pins = "gpio3 5149 pins = "gpio32", "gpio33",
5597 "gpio3 5150 "gpio34";
5598 function = "q 5151 function = "qup12";
5599 }; 5152 };
5600 5153
5601 qup_spi13_cs: qup-spi 5154 qup_spi13_cs: qup-spi13-cs-state {
5602 pins = "gpio3 5155 pins = "gpio39";
5603 function = "q 5156 function = "qup13";
5604 }; 5157 };
5605 5158
5606 qup_spi13_cs_gpio: qu 5159 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state {
5607 pins = "gpio3 5160 pins = "gpio39";
5608 function = "g 5161 function = "gpio";
5609 }; 5162 };
5610 5163
5611 qup_spi13_data_clk: q 5164 qup_spi13_data_clk: qup-spi13-data-clk-state {
5612 pins = "gpio3 5165 pins = "gpio36", "gpio37",
5613 "gpio3 5166 "gpio38";
5614 function = "q 5167 function = "qup13";
5615 }; 5168 };
5616 5169
5617 qup_spi14_cs: qup-spi 5170 qup_spi14_cs: qup-spi14-cs-state {
5618 pins = "gpio4 5171 pins = "gpio43";
5619 function = "q 5172 function = "qup14";
5620 }; 5173 };
5621 5174
5622 qup_spi14_cs_gpio: qu 5175 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state {
5623 pins = "gpio4 5176 pins = "gpio43";
5624 function = "g 5177 function = "gpio";
5625 }; 5178 };
5626 5179
5627 qup_spi14_data_clk: q 5180 qup_spi14_data_clk: qup-spi14-data-clk-state {
5628 pins = "gpio4 5181 pins = "gpio40", "gpio41",
5629 "gpio4 5182 "gpio42";
5630 function = "q 5183 function = "qup14";
5631 }; 5184 };
5632 5185
5633 qup_spi15_cs: qup-spi 5186 qup_spi15_cs: qup-spi15-cs-state {
5634 pins = "gpio4 5187 pins = "gpio47";
5635 function = "q 5188 function = "qup15";
5636 }; 5189 };
5637 5190
5638 qup_spi15_cs_gpio: qu 5191 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state {
5639 pins = "gpio4 5192 pins = "gpio47";
5640 function = "g 5193 function = "gpio";
5641 }; 5194 };
5642 5195
5643 qup_spi15_data_clk: q 5196 qup_spi15_data_clk: qup-spi15-data-clk-state {
5644 pins = "gpio4 5197 pins = "gpio44", "gpio45",
5645 "gpio4 5198 "gpio46";
5646 function = "q 5199 function = "qup15";
5647 }; 5200 };
5648 5201
5649 qup_spi16_cs: qup-spi 5202 qup_spi16_cs: qup-spi16-cs-state {
5650 pins = "gpio5 5203 pins = "gpio51";
5651 function = "q 5204 function = "qup16";
5652 }; 5205 };
5653 5206
5654 qup_spi16_cs_gpio: qu 5207 qup_spi16_cs_gpio: qup-spi16-cs-gpio-state {
5655 pins = "gpio5 5208 pins = "gpio51";
5656 function = "g 5209 function = "gpio";
5657 }; 5210 };
5658 5211
5659 qup_spi16_data_clk: q 5212 qup_spi16_data_clk: qup-spi16-data-clk-state {
5660 pins = "gpio4 5213 pins = "gpio48", "gpio49",
5661 "gpio5 5214 "gpio50";
5662 function = "q 5215 function = "qup16";
5663 }; 5216 };
5664 5217
5665 qup_spi17_cs: qup-spi 5218 qup_spi17_cs: qup-spi17-cs-state {
5666 pins = "gpio5 5219 pins = "gpio55";
5667 function = "q 5220 function = "qup17";
5668 }; 5221 };
5669 5222
5670 qup_spi17_cs_gpio: qu 5223 qup_spi17_cs_gpio: qup-spi17-cs-gpio-state {
5671 pins = "gpio5 5224 pins = "gpio55";
5672 function = "g 5225 function = "gpio";
5673 }; 5226 };
5674 5227
5675 qup_spi17_data_clk: q 5228 qup_spi17_data_clk: qup-spi17-data-clk-state {
5676 pins = "gpio5 5229 pins = "gpio52", "gpio53",
5677 "gpio5 5230 "gpio54";
5678 function = "q 5231 function = "qup17";
5679 }; 5232 };
5680 5233
5681 qup_spi18_cs: qup-spi 5234 qup_spi18_cs: qup-spi18-cs-state {
5682 pins = "gpio5 5235 pins = "gpio59";
5683 function = "q 5236 function = "qup18";
5684 }; 5237 };
5685 5238
5686 qup_spi18_cs_gpio: qu 5239 qup_spi18_cs_gpio: qup-spi18-cs-gpio-state {
5687 pins = "gpio5 5240 pins = "gpio59";
5688 function = "g 5241 function = "gpio";
5689 }; 5242 };
5690 5243
5691 qup_spi18_data_clk: q 5244 qup_spi18_data_clk: qup-spi18-data-clk-state {
5692 pins = "gpio5 5245 pins = "gpio56", "gpio57",
5693 "gpio5 5246 "gpio58";
5694 function = "q 5247 function = "qup18";
5695 }; 5248 };
5696 5249
5697 qup_spi19_cs: qup-spi 5250 qup_spi19_cs: qup-spi19-cs-state {
5698 pins = "gpio3 5251 pins = "gpio3";
5699 function = "q 5252 function = "qup19";
5700 }; 5253 };
5701 5254
5702 qup_spi19_cs_gpio: qu 5255 qup_spi19_cs_gpio: qup-spi19-cs-gpio-state {
5703 pins = "gpio3 5256 pins = "gpio3";
5704 function = "g 5257 function = "gpio";
5705 }; 5258 };
5706 5259
5707 qup_spi19_data_clk: q 5260 qup_spi19_data_clk: qup-spi19-data-clk-state {
5708 pins = "gpio0 5261 pins = "gpio0", "gpio1",
5709 "gpio2 5262 "gpio2";
5710 function = "q 5263 function = "qup19";
5711 }; 5264 };
5712 5265
5713 qup_uart2_default: qu 5266 qup_uart2_default: qup-uart2-default-state {
5714 pins = "gpio1 5267 pins = "gpio117", "gpio118";
5715 function = "q 5268 function = "qup2";
5716 }; 5269 };
5717 5270
5718 qup_uart6_default: qu 5271 qup_uart6_default: qup-uart6-default-state {
5719 pins = "gpio1 5272 pins = "gpio16", "gpio17", "gpio18", "gpio19";
5720 function = "q 5273 function = "qup6";
5721 }; 5274 };
5722 5275
5723 qup_uart12_default: q 5276 qup_uart12_default: qup-uart12-default-state {
5724 pins = "gpio3 5277 pins = "gpio34", "gpio35";
5725 function = "q 5278 function = "qup12";
5726 }; 5279 };
5727 5280
5728 qup_uart17_default: q 5281 qup_uart17_default: qup-uart17-default-state {
5729 pins = "gpio5 5282 pins = "gpio52", "gpio53", "gpio54", "gpio55";
5730 function = "q 5283 function = "qup17";
5731 }; 5284 };
5732 5285
5733 qup_uart18_default: q 5286 qup_uart18_default: qup-uart18-default-state {
5734 pins = "gpio5 5287 pins = "gpio58", "gpio59";
5735 function = "q 5288 function = "qup18";
5736 }; 5289 };
5737 5290
5738 tert_mi2s_active: ter 5291 tert_mi2s_active: tert-mi2s-active-state {
5739 sck-pins { 5292 sck-pins {
5740 pins 5293 pins = "gpio133";
5741 funct 5294 function = "mi2s2_sck";
5742 drive 5295 drive-strength = <8>;
5743 bias- 5296 bias-disable;
5744 }; 5297 };
5745 5298
5746 data0-pins { 5299 data0-pins {
5747 pins 5300 pins = "gpio134";
5748 funct 5301 function = "mi2s2_data0";
5749 drive 5302 drive-strength = <8>;
5750 bias- 5303 bias-disable;
5751 outpu 5304 output-high;
5752 }; 5305 };
5753 5306
5754 ws-pins { 5307 ws-pins {
5755 pins 5308 pins = "gpio135";
5756 funct 5309 function = "mi2s2_ws";
5757 drive 5310 drive-strength = <8>;
5758 outpu 5311 output-high;
5759 }; 5312 };
5760 }; 5313 };
5761 5314
5762 sdc2_sleep_state: sdc 5315 sdc2_sleep_state: sdc2-sleep-state {
5763 clk-pins { 5316 clk-pins {
5764 pins 5317 pins = "sdc2_clk";
5765 drive 5318 drive-strength = <2>;
5766 bias- 5319 bias-disable;
5767 }; 5320 };
5768 5321
5769 cmd-pins { 5322 cmd-pins {
5770 pins 5323 pins = "sdc2_cmd";
5771 drive 5324 drive-strength = <2>;
5772 bias- 5325 bias-pull-up;
5773 }; 5326 };
5774 5327
5775 data-pins { 5328 data-pins {
5776 pins 5329 pins = "sdc2_data";
5777 drive 5330 drive-strength = <2>;
5778 bias- 5331 bias-pull-up;
5779 }; 5332 };
5780 }; 5333 };
5781 5334
5782 pcie0_default_state: 5335 pcie0_default_state: pcie0-default-state {
5783 perst-pins { 5336 perst-pins {
5784 pins 5337 pins = "gpio79";
5785 funct 5338 function = "gpio";
5786 drive 5339 drive-strength = <2>;
5787 bias- 5340 bias-pull-down;
5788 }; 5341 };
5789 5342
5790 clkreq-pins { 5343 clkreq-pins {
5791 pins 5344 pins = "gpio80";
5792 funct 5345 function = "pci_e0";
5793 drive 5346 drive-strength = <2>;
5794 bias- 5347 bias-pull-up;
5795 }; 5348 };
5796 5349
5797 wake-pins { 5350 wake-pins {
5798 pins 5351 pins = "gpio81";
5799 funct 5352 function = "gpio";
5800 drive 5353 drive-strength = <2>;
5801 bias- 5354 bias-pull-up;
5802 }; 5355 };
5803 }; 5356 };
5804 5357
5805 pcie1_default_state: 5358 pcie1_default_state: pcie1-default-state {
5806 perst-pins { 5359 perst-pins {
5807 pins 5360 pins = "gpio82";
5808 funct 5361 function = "gpio";
5809 drive 5362 drive-strength = <2>;
5810 bias- 5363 bias-pull-down;
5811 }; 5364 };
5812 5365
5813 clkreq-pins { 5366 clkreq-pins {
5814 pins 5367 pins = "gpio83";
5815 funct 5368 function = "pci_e1";
5816 drive 5369 drive-strength = <2>;
5817 bias- 5370 bias-pull-up;
5818 }; 5371 };
5819 5372
5820 wake-pins { 5373 wake-pins {
5821 pins 5374 pins = "gpio84";
5822 funct 5375 function = "gpio";
5823 drive 5376 drive-strength = <2>;
5824 bias- 5377 bias-pull-up;
5825 }; 5378 };
5826 }; 5379 };
5827 5380
5828 pcie2_default_state: 5381 pcie2_default_state: pcie2-default-state {
5829 perst-pins { 5382 perst-pins {
5830 pins 5383 pins = "gpio85";
5831 funct 5384 function = "gpio";
5832 drive 5385 drive-strength = <2>;
5833 bias- 5386 bias-pull-down;
5834 }; 5387 };
5835 5388
5836 clkreq-pins { 5389 clkreq-pins {
5837 pins 5390 pins = "gpio86";
5838 funct 5391 function = "pci_e2";
5839 drive 5392 drive-strength = <2>;
5840 bias- 5393 bias-pull-up;
5841 }; 5394 };
5842 5395
5843 wake-pins { 5396 wake-pins {
5844 pins 5397 pins = "gpio87";
5845 funct 5398 function = "gpio";
5846 drive 5399 drive-strength = <2>;
5847 bias- 5400 bias-pull-up;
5848 }; 5401 };
5849 }; 5402 };
5850 }; 5403 };
5851 5404
5852 apps_smmu: iommu@15000000 { 5405 apps_smmu: iommu@15000000 {
5853 compatible = "qcom,sm 5406 compatible = "qcom,sm8250-smmu-500", "qcom,smmu-500", "arm,mmu-500";
5854 reg = <0 0x15000000 0 5407 reg = <0 0x15000000 0 0x100000>;
5855 #iommu-cells = <2>; 5408 #iommu-cells = <2>;
5856 #global-interrupts = 5409 #global-interrupts = <2>;
5857 interrupts = <GIC_SPI 5410 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
5858 <GIC_SPI 5411 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
5859 <GIC_SPI 5412 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
5860 <GIC_SPI 5413 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
5861 <GIC_SPI 5414 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
5862 <GIC_SPI 5415 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
5863 <GIC_SPI 5416 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
5864 <GIC_SPI 5417 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
5865 <GIC_SPI 5418 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
5866 <GIC_SPI 5419 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
5867 <GIC_SPI 5420 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
5868 <GIC_SPI 5421 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
5869 <GIC_SPI 5422 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
5870 <GIC_SPI 5423 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
5871 <GIC_SPI 5424 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
5872 <GIC_SPI 5425 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
5873 <GIC_SPI 5426 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
5874 <GIC_SPI 5427 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
5875 <GIC_SPI 5428 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
5876 <GIC_SPI 5429 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
5877 <GIC_SPI 5430 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
5878 <GIC_SPI 5431 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
5879 <GIC_SPI 5432 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
5880 <GIC_SPI 5433 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
5881 <GIC_SPI 5434 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
5882 <GIC_SPI 5435 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
5883 <GIC_SPI 5436 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
5884 <GIC_SPI 5437 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
5885 <GIC_SPI 5438 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
5886 <GIC_SPI 5439 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
5887 <GIC_SPI 5440 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
5888 <GIC_SPI 5441 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
5889 <GIC_SPI 5442 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
5890 <GIC_SPI 5443 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
5891 <GIC_SPI 5444 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
5892 <GIC_SPI 5445 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
5893 <GIC_SPI 5446 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
5894 <GIC_SPI 5447 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
5895 <GIC_SPI 5448 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
5896 <GIC_SPI 5449 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
5897 <GIC_SPI 5450 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
5898 <GIC_SPI 5451 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
5899 <GIC_SPI 5452 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
5900 <GIC_SPI 5453 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
5901 <GIC_SPI 5454 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
5902 <GIC_SPI 5455 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
5903 <GIC_SPI 5456 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
5904 <GIC_SPI 5457 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
5905 <GIC_SPI 5458 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
5906 <GIC_SPI 5459 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
5907 <GIC_SPI 5460 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
5908 <GIC_SPI 5461 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
5909 <GIC_SPI 5462 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
5910 <GIC_SPI 5463 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
5911 <GIC_SPI 5464 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
5912 <GIC_SPI 5465 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
5913 <GIC_SPI 5466 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
5914 <GIC_SPI 5467 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
5915 <GIC_SPI 5468 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
5916 <GIC_SPI 5469 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
5917 <GIC_SPI 5470 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
5918 <GIC_SPI 5471 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
5919 <GIC_SPI 5472 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
5920 <GIC_SPI 5473 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
5921 <GIC_SPI 5474 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
5922 <GIC_SPI 5475 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
5923 <GIC_SPI 5476 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
5924 <GIC_SPI 5477 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
5925 <GIC_SPI 5478 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
5926 <GIC_SPI 5479 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
5927 <GIC_SPI 5480 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
5928 <GIC_SPI 5481 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
5929 <GIC_SPI 5482 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
5930 <GIC_SPI 5483 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
5931 <GIC_SPI 5484 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
5932 <GIC_SPI 5485 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
5933 <GIC_SPI 5486 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
5934 <GIC_SPI 5487 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
5935 <GIC_SPI 5488 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
5936 <GIC_SPI 5489 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
5937 <GIC_SPI 5490 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
5938 <GIC_SPI 5491 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
5939 <GIC_SPI 5492 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
5940 <GIC_SPI 5493 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
5941 <GIC_SPI 5494 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
5942 <GIC_SPI 5495 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
5943 <GIC_SPI 5496 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
5944 <GIC_SPI 5497 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
5945 <GIC_SPI 5498 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
5946 <GIC_SPI 5499 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
5947 <GIC_SPI 5500 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
5948 <GIC_SPI 5501 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
5949 <GIC_SPI 5502 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
5950 <GIC_SPI 5503 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
5951 <GIC_SPI 5504 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
5952 <GIC_SPI 5505 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
5953 <GIC_SPI 5506 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
5954 <GIC_SPI 5507 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>;
5955 dma-coherent; 5508 dma-coherent;
5956 }; 5509 };
5957 5510
5958 adsp: remoteproc@17300000 { 5511 adsp: remoteproc@17300000 {
5959 compatible = "qcom,sm 5512 compatible = "qcom,sm8250-adsp-pas";
5960 reg = <0 0x17300000 0 5513 reg = <0 0x17300000 0 0x100>;
5961 5514
5962 interrupts-extended = !! 5515 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
5963 5516 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
5964 5517 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
5965 5518 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
5966 5519 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
5967 interrupt-names = "wd 5520 interrupt-names = "wdog", "fatal", "ready",
5968 "ha 5521 "handover", "stop-ack";
5969 5522
5970 clocks = <&rpmhcc RPM 5523 clocks = <&rpmhcc RPMH_CXO_CLK>;
5971 clock-names = "xo"; 5524 clock-names = "xo";
5972 5525
5973 power-domains = <&rpm 5526 power-domains = <&rpmhpd RPMHPD_LCX>,
5974 <&rpm 5527 <&rpmhpd RPMHPD_LMX>;
5975 power-domain-names = 5528 power-domain-names = "lcx", "lmx";
5976 5529
5977 memory-region = <&ads 5530 memory-region = <&adsp_mem>;
5978 5531
5979 qcom,qmp = <&aoss_qmp 5532 qcom,qmp = <&aoss_qmp>;
5980 5533
5981 qcom,smem-states = <& 5534 qcom,smem-states = <&smp2p_adsp_out 0>;
5982 qcom,smem-state-names 5535 qcom,smem-state-names = "stop";
5983 5536
5984 status = "disabled"; 5537 status = "disabled";
5985 5538
5986 glink-edge { 5539 glink-edge {
5987 interrupts-ex 5540 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
5988 5541 IPCC_MPROC_SIGNAL_GLINK_QMP
5989 5542 IRQ_TYPE_EDGE_RISING>;
5990 mboxes = <&ip 5543 mboxes = <&ipcc IPCC_CLIENT_LPASS
5991 5544 IPCC_MPROC_SIGNAL_GLINK_QMP>;
5992 5545
5993 label = "lpas 5546 label = "lpass";
5994 qcom,remote-p 5547 qcom,remote-pid = <2>;
5995 5548
5996 apr { 5549 apr {
5997 compa 5550 compatible = "qcom,apr-v2";
5998 qcom, 5551 qcom,glink-channels = "apr_audio_svc";
5999 qcom, 5552 qcom,domain = <APR_DOMAIN_ADSP>;
6000 #addr 5553 #address-cells = <1>;
6001 #size 5554 #size-cells = <0>;
6002 5555
6003 servi 5556 service@3 {
6004 5557 reg = <APR_SVC_ADSP_CORE>;
6005 5558 compatible = "qcom,q6core";
6006 5559 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6007 }; 5560 };
6008 5561
6009 q6afe 5562 q6afe: service@4 {
6010 5563 compatible = "qcom,q6afe";
6011 5564 reg = <APR_SVC_AFE>;
6012 5565 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6013 5566 q6afedai: dais {
6014 5567 compatible = "qcom,q6afe-dais";
6015 5568 #address-cells = <1>;
6016 5569 #size-cells = <0>;
6017 5570 #sound-dai-cells = <1>;
6018 5571 };
6019 5572
6020 5573 q6afecc: clock-controller {
6021 5574 compatible = "qcom,q6afe-clocks";
6022 5575 #clock-cells = <2>;
6023 5576 };
6024 }; 5577 };
6025 5578
6026 q6asm 5579 q6asm: service@7 {
6027 5580 compatible = "qcom,q6asm";
6028 5581 reg = <APR_SVC_ASM>;
6029 5582 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6030 5583 q6asmdai: dais {
6031 5584 compatible = "qcom,q6asm-dais";
6032 5585 #address-cells = <1>;
6033 5586 #size-cells = <0>;
6034 5587 #sound-dai-cells = <1>;
6035 5588 iommus = <&apps_smmu 0x1801 0x0>;
6036 5589 };
6037 }; 5590 };
6038 5591
6039 q6adm 5592 q6adm: service@8 {
6040 5593 compatible = "qcom,q6adm";
6041 5594 reg = <APR_SVC_ADM>;
6042 5595 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6043 5596 q6routing: routing {
6044 5597 compatible = "qcom,q6adm-routing";
6045 5598 #sound-dai-cells = <0>;
6046 5599 };
6047 }; 5600 };
6048 }; 5601 };
6049 5602
6050 fastrpc { 5603 fastrpc {
6051 compa 5604 compatible = "qcom,fastrpc";
6052 qcom, 5605 qcom,glink-channels = "fastrpcglink-apps-dsp";
6053 label 5606 label = "adsp";
6054 qcom, 5607 qcom,non-secure-domain;
6055 #addr 5608 #address-cells = <1>;
6056 #size 5609 #size-cells = <0>;
6057 5610
6058 compu 5611 compute-cb@3 {
6059 5612 compatible = "qcom,fastrpc-compute-cb";
6060 5613 reg = <3>;
6061 5614 iommus = <&apps_smmu 0x1803 0x0>;
6062 }; 5615 };
6063 5616
6064 compu 5617 compute-cb@4 {
6065 5618 compatible = "qcom,fastrpc-compute-cb";
6066 5619 reg = <4>;
6067 5620 iommus = <&apps_smmu 0x1804 0x0>;
6068 }; 5621 };
6069 5622
6070 compu 5623 compute-cb@5 {
6071 5624 compatible = "qcom,fastrpc-compute-cb";
6072 5625 reg = <5>;
6073 5626 iommus = <&apps_smmu 0x1805 0x0>;
6074 }; 5627 };
6075 }; 5628 };
6076 }; 5629 };
6077 }; 5630 };
6078 5631
6079 intc: interrupt-controller@17 5632 intc: interrupt-controller@17a00000 {
6080 compatible = "arm,gic 5633 compatible = "arm,gic-v3";
6081 #interrupt-cells = <3 5634 #interrupt-cells = <3>;
6082 interrupt-controller; 5635 interrupt-controller;
6083 reg = <0x0 0x17a00000 5636 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
6084 <0x0 0x17a60000 5637 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
6085 interrupts = <GIC_PPI 5638 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
6086 }; 5639 };
6087 5640
6088 watchdog@17c10000 { 5641 watchdog@17c10000 {
6089 compatible = "qcom,ap 5642 compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt";
6090 reg = <0 0x17c10000 0 5643 reg = <0 0x17c10000 0 0x1000>;
6091 clocks = <&sleep_clk> 5644 clocks = <&sleep_clk>;
6092 interrupts = <GIC_SPI 5645 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
6093 }; 5646 };
6094 5647
6095 timer@17c20000 { 5648 timer@17c20000 {
6096 #address-cells = <1>; 5649 #address-cells = <1>;
6097 #size-cells = <1>; 5650 #size-cells = <1>;
6098 ranges = <0 0 0 0x200 5651 ranges = <0 0 0 0x20000000>;
6099 compatible = "arm,arm 5652 compatible = "arm,armv7-timer-mem";
6100 reg = <0x0 0x17c20000 5653 reg = <0x0 0x17c20000 0x0 0x1000>;
6101 clock-frequency = <19 5654 clock-frequency = <19200000>;
6102 5655
6103 frame@17c21000 { 5656 frame@17c21000 {
6104 frame-number 5657 frame-number = <0>;
6105 interrupts = 5658 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
6106 5659 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
6107 reg = <0x17c2 5660 reg = <0x17c21000 0x1000>,
6108 <0x17c2 5661 <0x17c22000 0x1000>;
6109 }; 5662 };
6110 5663
6111 frame@17c23000 { 5664 frame@17c23000 {
6112 frame-number 5665 frame-number = <1>;
6113 interrupts = 5666 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
6114 reg = <0x17c2 5667 reg = <0x17c23000 0x1000>;
6115 status = "dis 5668 status = "disabled";
6116 }; 5669 };
6117 5670
6118 frame@17c25000 { 5671 frame@17c25000 {
6119 frame-number 5672 frame-number = <2>;
6120 interrupts = 5673 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
6121 reg = <0x17c2 5674 reg = <0x17c25000 0x1000>;
6122 status = "dis 5675 status = "disabled";
6123 }; 5676 };
6124 5677
6125 frame@17c27000 { 5678 frame@17c27000 {
6126 frame-number 5679 frame-number = <3>;
6127 interrupts = 5680 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
6128 reg = <0x17c2 5681 reg = <0x17c27000 0x1000>;
6129 status = "dis 5682 status = "disabled";
6130 }; 5683 };
6131 5684
6132 frame@17c29000 { 5685 frame@17c29000 {
6133 frame-number 5686 frame-number = <4>;
6134 interrupts = 5687 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
6135 reg = <0x17c2 5688 reg = <0x17c29000 0x1000>;
6136 status = "dis 5689 status = "disabled";
6137 }; 5690 };
6138 5691
6139 frame@17c2b000 { 5692 frame@17c2b000 {
6140 frame-number 5693 frame-number = <5>;
6141 interrupts = 5694 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
6142 reg = <0x17c2 5695 reg = <0x17c2b000 0x1000>;
6143 status = "dis 5696 status = "disabled";
6144 }; 5697 };
6145 5698
6146 frame@17c2d000 { 5699 frame@17c2d000 {
6147 frame-number 5700 frame-number = <6>;
6148 interrupts = 5701 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
6149 reg = <0x17c2 5702 reg = <0x17c2d000 0x1000>;
6150 status = "dis 5703 status = "disabled";
6151 }; 5704 };
6152 }; 5705 };
6153 5706
6154 apps_rsc: rsc@18200000 { 5707 apps_rsc: rsc@18200000 {
6155 label = "apps_rsc"; 5708 label = "apps_rsc";
6156 compatible = "qcom,rp 5709 compatible = "qcom,rpmh-rsc";
6157 reg = <0x0 0x18200000 5710 reg = <0x0 0x18200000 0x0 0x10000>,
6158 <0x0 0x182100 5711 <0x0 0x18210000 0x0 0x10000>,
6159 <0x0 0x182200 5712 <0x0 0x18220000 0x0 0x10000>;
6160 reg-names = "drv-0", 5713 reg-names = "drv-0", "drv-1", "drv-2";
6161 interrupts = <GIC_SPI 5714 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
6162 <GIC_SPI 5715 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
6163 <GIC_SPI 5716 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
6164 qcom,tcs-offset = <0x 5717 qcom,tcs-offset = <0xd00>;
6165 qcom,drv-id = <2>; 5718 qcom,drv-id = <2>;
6166 qcom,tcs-config = <AC 5719 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
6167 <WA 5720 <WAKE_TCS 3>, <CONTROL_TCS 1>;
6168 power-domains = <&CLU 5721 power-domains = <&CLUSTER_PD>;
6169 5722
6170 rpmhcc: clock-control 5723 rpmhcc: clock-controller {
6171 compatible = 5724 compatible = "qcom,sm8250-rpmh-clk";
6172 #clock-cells 5725 #clock-cells = <1>;
6173 clock-names = 5726 clock-names = "xo";
6174 clocks = <&xo 5727 clocks = <&xo_board>;
6175 }; 5728 };
6176 5729
6177 rpmhpd: power-control 5730 rpmhpd: power-controller {
6178 compatible = 5731 compatible = "qcom,sm8250-rpmhpd";
6179 #power-domain 5732 #power-domain-cells = <1>;
6180 operating-poi 5733 operating-points-v2 = <&rpmhpd_opp_table>;
6181 5734
6182 rpmhpd_opp_ta 5735 rpmhpd_opp_table: opp-table {
6183 compa 5736 compatible = "operating-points-v2";
6184 5737
6185 rpmhp 5738 rpmhpd_opp_ret: opp1 {
6186 5739 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
6187 }; 5740 };
6188 5741
6189 rpmhp 5742 rpmhpd_opp_min_svs: opp2 {
6190 5743 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
6191 }; 5744 };
6192 5745
6193 rpmhp 5746 rpmhpd_opp_low_svs: opp3 {
6194 5747 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
6195 }; 5748 };
6196 5749
6197 rpmhp 5750 rpmhpd_opp_svs: opp4 {
6198 5751 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
6199 }; 5752 };
6200 5753
6201 rpmhp 5754 rpmhpd_opp_svs_l1: opp5 {
6202 5755 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
6203 }; 5756 };
6204 5757
6205 rpmhp 5758 rpmhpd_opp_nom: opp6 {
6206 5759 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
6207 }; 5760 };
6208 5761
6209 rpmhp 5762 rpmhpd_opp_nom_l1: opp7 {
6210 5763 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
6211 }; 5764 };
6212 5765
6213 rpmhp 5766 rpmhpd_opp_nom_l2: opp8 {
6214 5767 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
6215 }; 5768 };
6216 5769
6217 rpmhp 5770 rpmhpd_opp_turbo: opp9 {
6218 5771 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
6219 }; 5772 };
6220 5773
6221 rpmhp 5774 rpmhpd_opp_turbo_l1: opp10 {
6222 5775 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
6223 }; 5776 };
6224 }; 5777 };
6225 }; 5778 };
6226 5779
6227 apps_bcm_voter: bcm-v 5780 apps_bcm_voter: bcm-voter {
6228 compatible = 5781 compatible = "qcom,bcm-voter";
6229 }; 5782 };
6230 }; 5783 };
6231 5784
6232 epss_l3: interconnect@1859000 5785 epss_l3: interconnect@18590000 {
6233 compatible = "qcom,sm 5786 compatible = "qcom,sm8250-epss-l3", "qcom,epss-l3";
6234 reg = <0 0x18590000 0 5787 reg = <0 0x18590000 0 0x1000>;
6235 5788
6236 clocks = <&rpmhcc RPM 5789 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
6237 clock-names = "xo", " 5790 clock-names = "xo", "alternate";
6238 5791
6239 #interconnect-cells = 5792 #interconnect-cells = <1>;
6240 }; 5793 };
6241 5794
6242 cpufreq_hw: cpufreq@18591000 5795 cpufreq_hw: cpufreq@18591000 {
6243 compatible = "qcom,sm 5796 compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss";
6244 reg = <0 0x18591000 0 5797 reg = <0 0x18591000 0 0x1000>,
6245 <0 0x18592000 0 5798 <0 0x18592000 0 0x1000>,
6246 <0 0x18593000 0 5799 <0 0x18593000 0 0x1000>;
6247 reg-names = "freq-dom 5800 reg-names = "freq-domain0", "freq-domain1",
6248 "freq-dom 5801 "freq-domain2";
6249 5802
6250 clocks = <&rpmhcc RPM 5803 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
6251 clock-names = "xo", " 5804 clock-names = "xo", "alternate";
6252 interrupts = <GIC_SPI 5805 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
6253 <GIC_SPI 5806 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
6254 <GIC_SPI 5807 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
6255 interrupt-names = "dc 5808 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
6256 #freq-domain-cells = 5809 #freq-domain-cells = <1>;
6257 #clock-cells = <1>; 5810 #clock-cells = <1>;
6258 }; 5811 };
6259 }; 5812 };
6260 5813
6261 sound: sound { 5814 sound: sound {
6262 }; 5815 };
6263 5816
6264 timer { 5817 timer {
6265 compatible = "arm,armv8-timer 5818 compatible = "arm,armv8-timer";
6266 interrupts = <GIC_PPI 13 5819 interrupts = <GIC_PPI 13
6267 (GIC_CPU_MASK 5820 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6268 <GIC_PPI 14 5821 <GIC_PPI 14
6269 (GIC_CPU_MASK 5822 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6270 <GIC_PPI 11 5823 <GIC_PPI 11
6271 (GIC_CPU_MASK 5824 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6272 <GIC_PPI 10 5825 <GIC_PPI 10
6273 (GIC_CPU_MASK 5826 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
6274 }; 5827 };
6275 5828
6276 thermal-zones { 5829 thermal-zones {
6277 cpu0-thermal { 5830 cpu0-thermal {
6278 polling-delay-passive 5831 polling-delay-passive = <250>;
>> 5832 polling-delay = <1000>;
6279 5833
6280 thermal-sensors = <&t 5834 thermal-sensors = <&tsens0 1>;
6281 5835
6282 trips { 5836 trips {
6283 cpu0_alert0: 5837 cpu0_alert0: trip-point0 {
6284 tempe 5838 temperature = <90000>;
6285 hyste 5839 hysteresis = <2000>;
6286 type 5840 type = "passive";
6287 }; 5841 };
6288 5842
6289 cpu0_alert1: 5843 cpu0_alert1: trip-point1 {
6290 tempe 5844 temperature = <95000>;
6291 hyste 5845 hysteresis = <2000>;
6292 type 5846 type = "passive";
6293 }; 5847 };
6294 5848
6295 cpu0_crit: cp 5849 cpu0_crit: cpu-crit {
6296 tempe 5850 temperature = <110000>;
6297 hyste 5851 hysteresis = <1000>;
6298 type 5852 type = "critical";
6299 }; 5853 };
6300 }; 5854 };
6301 5855
6302 cooling-maps { 5856 cooling-maps {
6303 map0 { 5857 map0 {
6304 trip 5858 trip = <&cpu0_alert0>;
6305 cooli 5859 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6306 5860 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6307 5861 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6308 5862 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6309 }; 5863 };
6310 map1 { 5864 map1 {
6311 trip 5865 trip = <&cpu0_alert1>;
6312 cooli 5866 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6313 5867 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6314 5868 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6315 5869 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6316 }; 5870 };
6317 }; 5871 };
6318 }; 5872 };
6319 5873
6320 cpu1-thermal { 5874 cpu1-thermal {
6321 polling-delay-passive 5875 polling-delay-passive = <250>;
>> 5876 polling-delay = <1000>;
6322 5877
6323 thermal-sensors = <&t 5878 thermal-sensors = <&tsens0 2>;
6324 5879
6325 trips { 5880 trips {
6326 cpu1_alert0: 5881 cpu1_alert0: trip-point0 {
6327 tempe 5882 temperature = <90000>;
6328 hyste 5883 hysteresis = <2000>;
6329 type 5884 type = "passive";
6330 }; 5885 };
6331 5886
6332 cpu1_alert1: 5887 cpu1_alert1: trip-point1 {
6333 tempe 5888 temperature = <95000>;
6334 hyste 5889 hysteresis = <2000>;
6335 type 5890 type = "passive";
6336 }; 5891 };
6337 5892
6338 cpu1_crit: cp 5893 cpu1_crit: cpu-crit {
6339 tempe 5894 temperature = <110000>;
6340 hyste 5895 hysteresis = <1000>;
6341 type 5896 type = "critical";
6342 }; 5897 };
6343 }; 5898 };
6344 5899
6345 cooling-maps { 5900 cooling-maps {
6346 map0 { 5901 map0 {
6347 trip 5902 trip = <&cpu1_alert0>;
6348 cooli 5903 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6349 5904 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6350 5905 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6351 5906 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6352 }; 5907 };
6353 map1 { 5908 map1 {
6354 trip 5909 trip = <&cpu1_alert1>;
6355 cooli 5910 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6356 5911 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6357 5912 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6358 5913 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6359 }; 5914 };
6360 }; 5915 };
6361 }; 5916 };
6362 5917
6363 cpu2-thermal { 5918 cpu2-thermal {
6364 polling-delay-passive 5919 polling-delay-passive = <250>;
>> 5920 polling-delay = <1000>;
6365 5921
6366 thermal-sensors = <&t 5922 thermal-sensors = <&tsens0 3>;
6367 5923
6368 trips { 5924 trips {
6369 cpu2_alert0: 5925 cpu2_alert0: trip-point0 {
6370 tempe 5926 temperature = <90000>;
6371 hyste 5927 hysteresis = <2000>;
6372 type 5928 type = "passive";
6373 }; 5929 };
6374 5930
6375 cpu2_alert1: 5931 cpu2_alert1: trip-point1 {
6376 tempe 5932 temperature = <95000>;
6377 hyste 5933 hysteresis = <2000>;
6378 type 5934 type = "passive";
6379 }; 5935 };
6380 5936
6381 cpu2_crit: cp 5937 cpu2_crit: cpu-crit {
6382 tempe 5938 temperature = <110000>;
6383 hyste 5939 hysteresis = <1000>;
6384 type 5940 type = "critical";
6385 }; 5941 };
6386 }; 5942 };
6387 5943
6388 cooling-maps { 5944 cooling-maps {
6389 map0 { 5945 map0 {
6390 trip 5946 trip = <&cpu2_alert0>;
6391 cooli 5947 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6392 5948 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6393 5949 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6394 5950 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6395 }; 5951 };
6396 map1 { 5952 map1 {
6397 trip 5953 trip = <&cpu2_alert1>;
6398 cooli 5954 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6399 5955 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6400 5956 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6401 5957 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6402 }; 5958 };
6403 }; 5959 };
6404 }; 5960 };
6405 5961
6406 cpu3-thermal { 5962 cpu3-thermal {
6407 polling-delay-passive 5963 polling-delay-passive = <250>;
>> 5964 polling-delay = <1000>;
6408 5965
6409 thermal-sensors = <&t 5966 thermal-sensors = <&tsens0 4>;
6410 5967
6411 trips { 5968 trips {
6412 cpu3_alert0: 5969 cpu3_alert0: trip-point0 {
6413 tempe 5970 temperature = <90000>;
6414 hyste 5971 hysteresis = <2000>;
6415 type 5972 type = "passive";
6416 }; 5973 };
6417 5974
6418 cpu3_alert1: 5975 cpu3_alert1: trip-point1 {
6419 tempe 5976 temperature = <95000>;
6420 hyste 5977 hysteresis = <2000>;
6421 type 5978 type = "passive";
6422 }; 5979 };
6423 5980
6424 cpu3_crit: cp 5981 cpu3_crit: cpu-crit {
6425 tempe 5982 temperature = <110000>;
6426 hyste 5983 hysteresis = <1000>;
6427 type 5984 type = "critical";
6428 }; 5985 };
6429 }; 5986 };
6430 5987
6431 cooling-maps { 5988 cooling-maps {
6432 map0 { 5989 map0 {
6433 trip 5990 trip = <&cpu3_alert0>;
6434 cooli 5991 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6435 5992 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6436 5993 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6437 5994 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6438 }; 5995 };
6439 map1 { 5996 map1 {
6440 trip 5997 trip = <&cpu3_alert1>;
6441 cooli 5998 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6442 5999 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6443 6000 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6444 6001 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6445 }; 6002 };
6446 }; 6003 };
6447 }; 6004 };
6448 6005
6449 cpu4-top-thermal { 6006 cpu4-top-thermal {
6450 polling-delay-passive 6007 polling-delay-passive = <250>;
>> 6008 polling-delay = <1000>;
6451 6009
6452 thermal-sensors = <&t 6010 thermal-sensors = <&tsens0 7>;
6453 6011
6454 trips { 6012 trips {
6455 cpu4_top_aler 6013 cpu4_top_alert0: trip-point0 {
6456 tempe 6014 temperature = <90000>;
6457 hyste 6015 hysteresis = <2000>;
6458 type 6016 type = "passive";
6459 }; 6017 };
6460 6018
6461 cpu4_top_aler 6019 cpu4_top_alert1: trip-point1 {
6462 tempe 6020 temperature = <95000>;
6463 hyste 6021 hysteresis = <2000>;
6464 type 6022 type = "passive";
6465 }; 6023 };
6466 6024
6467 cpu4_top_crit 6025 cpu4_top_crit: cpu-crit {
6468 tempe 6026 temperature = <110000>;
6469 hyste 6027 hysteresis = <1000>;
6470 type 6028 type = "critical";
6471 }; 6029 };
6472 }; 6030 };
6473 6031
6474 cooling-maps { 6032 cooling-maps {
6475 map0 { 6033 map0 {
6476 trip 6034 trip = <&cpu4_top_alert0>;
6477 cooli 6035 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6478 6036 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6479 6037 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6480 6038 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6481 }; 6039 };
6482 map1 { 6040 map1 {
6483 trip 6041 trip = <&cpu4_top_alert1>;
6484 cooli 6042 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6485 6043 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6486 6044 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6487 6045 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6488 }; 6046 };
6489 }; 6047 };
6490 }; 6048 };
6491 6049
6492 cpu5-top-thermal { 6050 cpu5-top-thermal {
6493 polling-delay-passive 6051 polling-delay-passive = <250>;
>> 6052 polling-delay = <1000>;
6494 6053
6495 thermal-sensors = <&t 6054 thermal-sensors = <&tsens0 8>;
6496 6055
6497 trips { 6056 trips {
6498 cpu5_top_aler 6057 cpu5_top_alert0: trip-point0 {
6499 tempe 6058 temperature = <90000>;
6500 hyste 6059 hysteresis = <2000>;
6501 type 6060 type = "passive";
6502 }; 6061 };
6503 6062
6504 cpu5_top_aler 6063 cpu5_top_alert1: trip-point1 {
6505 tempe 6064 temperature = <95000>;
6506 hyste 6065 hysteresis = <2000>;
6507 type 6066 type = "passive";
6508 }; 6067 };
6509 6068
6510 cpu5_top_crit 6069 cpu5_top_crit: cpu-crit {
6511 tempe 6070 temperature = <110000>;
6512 hyste 6071 hysteresis = <1000>;
6513 type 6072 type = "critical";
6514 }; 6073 };
6515 }; 6074 };
6516 6075
6517 cooling-maps { 6076 cooling-maps {
6518 map0 { 6077 map0 {
6519 trip 6078 trip = <&cpu5_top_alert0>;
6520 cooli 6079 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6521 6080 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6522 6081 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6523 6082 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6524 }; 6083 };
6525 map1 { 6084 map1 {
6526 trip 6085 trip = <&cpu5_top_alert1>;
6527 cooli 6086 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6528 6087 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6529 6088 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6530 6089 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6531 }; 6090 };
6532 }; 6091 };
6533 }; 6092 };
6534 6093
6535 cpu6-top-thermal { 6094 cpu6-top-thermal {
6536 polling-delay-passive 6095 polling-delay-passive = <250>;
>> 6096 polling-delay = <1000>;
6537 6097
6538 thermal-sensors = <&t 6098 thermal-sensors = <&tsens0 9>;
6539 6099
6540 trips { 6100 trips {
6541 cpu6_top_aler 6101 cpu6_top_alert0: trip-point0 {
6542 tempe 6102 temperature = <90000>;
6543 hyste 6103 hysteresis = <2000>;
6544 type 6104 type = "passive";
6545 }; 6105 };
6546 6106
6547 cpu6_top_aler 6107 cpu6_top_alert1: trip-point1 {
6548 tempe 6108 temperature = <95000>;
6549 hyste 6109 hysteresis = <2000>;
6550 type 6110 type = "passive";
6551 }; 6111 };
6552 6112
6553 cpu6_top_crit 6113 cpu6_top_crit: cpu-crit {
6554 tempe 6114 temperature = <110000>;
6555 hyste 6115 hysteresis = <1000>;
6556 type 6116 type = "critical";
6557 }; 6117 };
6558 }; 6118 };
6559 6119
6560 cooling-maps { 6120 cooling-maps {
6561 map0 { 6121 map0 {
6562 trip 6122 trip = <&cpu6_top_alert0>;
6563 cooli 6123 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6564 6124 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6565 6125 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6566 6126 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6567 }; 6127 };
6568 map1 { 6128 map1 {
6569 trip 6129 trip = <&cpu6_top_alert1>;
6570 cooli 6130 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6571 6131 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6572 6132 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6573 6133 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6574 }; 6134 };
6575 }; 6135 };
6576 }; 6136 };
6577 6137
6578 cpu7-top-thermal { 6138 cpu7-top-thermal {
6579 polling-delay-passive 6139 polling-delay-passive = <250>;
>> 6140 polling-delay = <1000>;
6580 6141
6581 thermal-sensors = <&t 6142 thermal-sensors = <&tsens0 10>;
6582 6143
6583 trips { 6144 trips {
6584 cpu7_top_aler 6145 cpu7_top_alert0: trip-point0 {
6585 tempe 6146 temperature = <90000>;
6586 hyste 6147 hysteresis = <2000>;
6587 type 6148 type = "passive";
6588 }; 6149 };
6589 6150
6590 cpu7_top_aler 6151 cpu7_top_alert1: trip-point1 {
6591 tempe 6152 temperature = <95000>;
6592 hyste 6153 hysteresis = <2000>;
6593 type 6154 type = "passive";
6594 }; 6155 };
6595 6156
6596 cpu7_top_crit 6157 cpu7_top_crit: cpu-crit {
6597 tempe 6158 temperature = <110000>;
6598 hyste 6159 hysteresis = <1000>;
6599 type 6160 type = "critical";
6600 }; 6161 };
6601 }; 6162 };
6602 6163
6603 cooling-maps { 6164 cooling-maps {
6604 map0 { 6165 map0 {
6605 trip 6166 trip = <&cpu7_top_alert0>;
6606 cooli 6167 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6607 6168 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6608 6169 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6609 6170 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6610 }; 6171 };
6611 map1 { 6172 map1 {
6612 trip 6173 trip = <&cpu7_top_alert1>;
6613 cooli 6174 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6614 6175 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6615 6176 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6616 6177 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6617 }; 6178 };
6618 }; 6179 };
6619 }; 6180 };
6620 6181
6621 cpu4-bottom-thermal { 6182 cpu4-bottom-thermal {
6622 polling-delay-passive 6183 polling-delay-passive = <250>;
>> 6184 polling-delay = <1000>;
6623 6185
6624 thermal-sensors = <&t 6186 thermal-sensors = <&tsens0 11>;
6625 6187
6626 trips { 6188 trips {
6627 cpu4_bottom_a 6189 cpu4_bottom_alert0: trip-point0 {
6628 tempe 6190 temperature = <90000>;
6629 hyste 6191 hysteresis = <2000>;
6630 type 6192 type = "passive";
6631 }; 6193 };
6632 6194
6633 cpu4_bottom_a 6195 cpu4_bottom_alert1: trip-point1 {
6634 tempe 6196 temperature = <95000>;
6635 hyste 6197 hysteresis = <2000>;
6636 type 6198 type = "passive";
6637 }; 6199 };
6638 6200
6639 cpu4_bottom_c 6201 cpu4_bottom_crit: cpu-crit {
6640 tempe 6202 temperature = <110000>;
6641 hyste 6203 hysteresis = <1000>;
6642 type 6204 type = "critical";
6643 }; 6205 };
6644 }; 6206 };
6645 6207
6646 cooling-maps { 6208 cooling-maps {
6647 map0 { 6209 map0 {
6648 trip 6210 trip = <&cpu4_bottom_alert0>;
6649 cooli 6211 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6650 6212 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6651 6213 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6652 6214 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6653 }; 6215 };
6654 map1 { 6216 map1 {
6655 trip 6217 trip = <&cpu4_bottom_alert1>;
6656 cooli 6218 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6657 6219 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6658 6220 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6659 6221 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6660 }; 6222 };
6661 }; 6223 };
6662 }; 6224 };
6663 6225
6664 cpu5-bottom-thermal { 6226 cpu5-bottom-thermal {
6665 polling-delay-passive 6227 polling-delay-passive = <250>;
>> 6228 polling-delay = <1000>;
6666 6229
6667 thermal-sensors = <&t 6230 thermal-sensors = <&tsens0 12>;
6668 6231
6669 trips { 6232 trips {
6670 cpu5_bottom_a 6233 cpu5_bottom_alert0: trip-point0 {
6671 tempe 6234 temperature = <90000>;
6672 hyste 6235 hysteresis = <2000>;
6673 type 6236 type = "passive";
6674 }; 6237 };
6675 6238
6676 cpu5_bottom_a 6239 cpu5_bottom_alert1: trip-point1 {
6677 tempe 6240 temperature = <95000>;
6678 hyste 6241 hysteresis = <2000>;
6679 type 6242 type = "passive";
6680 }; 6243 };
6681 6244
6682 cpu5_bottom_c 6245 cpu5_bottom_crit: cpu-crit {
6683 tempe 6246 temperature = <110000>;
6684 hyste 6247 hysteresis = <1000>;
6685 type 6248 type = "critical";
6686 }; 6249 };
6687 }; 6250 };
6688 6251
6689 cooling-maps { 6252 cooling-maps {
6690 map0 { 6253 map0 {
6691 trip 6254 trip = <&cpu5_bottom_alert0>;
6692 cooli 6255 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6693 6256 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6694 6257 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6695 6258 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6696 }; 6259 };
6697 map1 { 6260 map1 {
6698 trip 6261 trip = <&cpu5_bottom_alert1>;
6699 cooli 6262 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6700 6263 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6701 6264 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6702 6265 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6703 }; 6266 };
6704 }; 6267 };
6705 }; 6268 };
6706 6269
6707 cpu6-bottom-thermal { 6270 cpu6-bottom-thermal {
6708 polling-delay-passive 6271 polling-delay-passive = <250>;
>> 6272 polling-delay = <1000>;
6709 6273
6710 thermal-sensors = <&t 6274 thermal-sensors = <&tsens0 13>;
6711 6275
6712 trips { 6276 trips {
6713 cpu6_bottom_a 6277 cpu6_bottom_alert0: trip-point0 {
6714 tempe 6278 temperature = <90000>;
6715 hyste 6279 hysteresis = <2000>;
6716 type 6280 type = "passive";
6717 }; 6281 };
6718 6282
6719 cpu6_bottom_a 6283 cpu6_bottom_alert1: trip-point1 {
6720 tempe 6284 temperature = <95000>;
6721 hyste 6285 hysteresis = <2000>;
6722 type 6286 type = "passive";
6723 }; 6287 };
6724 6288
6725 cpu6_bottom_c 6289 cpu6_bottom_crit: cpu-crit {
6726 tempe 6290 temperature = <110000>;
6727 hyste 6291 hysteresis = <1000>;
6728 type 6292 type = "critical";
6729 }; 6293 };
6730 }; 6294 };
6731 6295
6732 cooling-maps { 6296 cooling-maps {
6733 map0 { 6297 map0 {
6734 trip 6298 trip = <&cpu6_bottom_alert0>;
6735 cooli 6299 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6736 6300 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6737 6301 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6738 6302 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6739 }; 6303 };
6740 map1 { 6304 map1 {
6741 trip 6305 trip = <&cpu6_bottom_alert1>;
6742 cooli 6306 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6743 6307 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6744 6308 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6745 6309 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6746 }; 6310 };
6747 }; 6311 };
6748 }; 6312 };
6749 6313
6750 cpu7-bottom-thermal { 6314 cpu7-bottom-thermal {
6751 polling-delay-passive 6315 polling-delay-passive = <250>;
>> 6316 polling-delay = <1000>;
6752 6317
6753 thermal-sensors = <&t 6318 thermal-sensors = <&tsens0 14>;
6754 6319
6755 trips { 6320 trips {
6756 cpu7_bottom_a 6321 cpu7_bottom_alert0: trip-point0 {
6757 tempe 6322 temperature = <90000>;
6758 hyste 6323 hysteresis = <2000>;
6759 type 6324 type = "passive";
6760 }; 6325 };
6761 6326
6762 cpu7_bottom_a 6327 cpu7_bottom_alert1: trip-point1 {
6763 tempe 6328 temperature = <95000>;
6764 hyste 6329 hysteresis = <2000>;
6765 type 6330 type = "passive";
6766 }; 6331 };
6767 6332
6768 cpu7_bottom_c 6333 cpu7_bottom_crit: cpu-crit {
6769 tempe 6334 temperature = <110000>;
6770 hyste 6335 hysteresis = <1000>;
6771 type 6336 type = "critical";
6772 }; 6337 };
6773 }; 6338 };
6774 6339
6775 cooling-maps { 6340 cooling-maps {
6776 map0 { 6341 map0 {
6777 trip 6342 trip = <&cpu7_bottom_alert0>;
6778 cooli 6343 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6779 6344 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6780 6345 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6781 6346 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6782 }; 6347 };
6783 map1 { 6348 map1 {
6784 trip 6349 trip = <&cpu7_bottom_alert1>;
6785 cooli 6350 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6786 6351 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6787 6352 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6788 6353 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6789 }; 6354 };
6790 }; 6355 };
6791 }; 6356 };
6792 6357
6793 aoss0-thermal { 6358 aoss0-thermal {
6794 polling-delay-passive 6359 polling-delay-passive = <250>;
>> 6360 polling-delay = <1000>;
6795 6361
6796 thermal-sensors = <&t 6362 thermal-sensors = <&tsens0 0>;
6797 6363
6798 trips { 6364 trips {
6799 aoss0_alert0: 6365 aoss0_alert0: trip-point0 {
6800 tempe 6366 temperature = <90000>;
6801 hyste 6367 hysteresis = <2000>;
6802 type 6368 type = "hot";
6803 }; 6369 };
6804 }; 6370 };
6805 }; 6371 };
6806 6372
6807 cluster0-thermal { 6373 cluster0-thermal {
6808 polling-delay-passive 6374 polling-delay-passive = <250>;
>> 6375 polling-delay = <1000>;
6809 6376
6810 thermal-sensors = <&t 6377 thermal-sensors = <&tsens0 5>;
6811 6378
6812 trips { 6379 trips {
6813 cluster0_aler 6380 cluster0_alert0: trip-point0 {
6814 tempe 6381 temperature = <90000>;
6815 hyste 6382 hysteresis = <2000>;
6816 type 6383 type = "hot";
6817 }; 6384 };
6818 cluster0_crit !! 6385 cluster0_crit: cluster0_crit {
6819 tempe 6386 temperature = <110000>;
6820 hyste 6387 hysteresis = <2000>;
6821 type 6388 type = "critical";
6822 }; 6389 };
6823 }; 6390 };
6824 }; 6391 };
6825 6392
6826 cluster1-thermal { 6393 cluster1-thermal {
6827 polling-delay-passive 6394 polling-delay-passive = <250>;
>> 6395 polling-delay = <1000>;
6828 6396
6829 thermal-sensors = <&t 6397 thermal-sensors = <&tsens0 6>;
6830 6398
6831 trips { 6399 trips {
6832 cluster1_aler 6400 cluster1_alert0: trip-point0 {
6833 tempe 6401 temperature = <90000>;
6834 hyste 6402 hysteresis = <2000>;
6835 type 6403 type = "hot";
6836 }; 6404 };
6837 cluster1_crit !! 6405 cluster1_crit: cluster1_crit {
6838 tempe 6406 temperature = <110000>;
6839 hyste 6407 hysteresis = <2000>;
6840 type 6408 type = "critical";
6841 }; 6409 };
6842 }; 6410 };
6843 }; 6411 };
6844 6412
6845 gpu-top-thermal { 6413 gpu-top-thermal {
6846 polling-delay-passive 6414 polling-delay-passive = <250>;
>> 6415 polling-delay = <1000>;
6847 6416
6848 thermal-sensors = <&t 6417 thermal-sensors = <&tsens0 15>;
6849 6418
6850 cooling-maps { <<
6851 map0 { <<
6852 trip <<
6853 cooli <<
6854 }; <<
6855 }; <<
6856 <<
6857 trips { 6419 trips {
6858 gpu_top_alert !! 6420 gpu1_alert0: trip-point0 {
6859 tempe <<
6860 hyste <<
6861 type <<
6862 }; <<
6863 <<
6864 trip-point1 { <<
6865 tempe 6421 temperature = <90000>;
6866 hyste !! 6422 hysteresis = <2000>;
6867 type 6423 type = "hot";
6868 }; 6424 };
6869 <<
6870 trip-point2 { <<
6871 tempe <<
6872 hyste <<
6873 type <<
6874 }; <<
6875 }; 6425 };
6876 }; 6426 };
6877 6427
6878 aoss1-thermal { 6428 aoss1-thermal {
6879 polling-delay-passive 6429 polling-delay-passive = <250>;
>> 6430 polling-delay = <1000>;
6880 6431
6881 thermal-sensors = <&t 6432 thermal-sensors = <&tsens1 0>;
6882 6433
6883 trips { 6434 trips {
6884 aoss1_alert0: 6435 aoss1_alert0: trip-point0 {
6885 tempe 6436 temperature = <90000>;
6886 hyste 6437 hysteresis = <2000>;
6887 type 6438 type = "hot";
6888 }; 6439 };
6889 }; 6440 };
6890 }; 6441 };
6891 6442
6892 wlan-thermal { 6443 wlan-thermal {
6893 polling-delay-passive 6444 polling-delay-passive = <250>;
>> 6445 polling-delay = <1000>;
6894 6446
6895 thermal-sensors = <&t 6447 thermal-sensors = <&tsens1 1>;
6896 6448
6897 trips { 6449 trips {
6898 wlan_alert0: 6450 wlan_alert0: trip-point0 {
6899 tempe 6451 temperature = <90000>;
6900 hyste 6452 hysteresis = <2000>;
6901 type 6453 type = "hot";
6902 }; 6454 };
6903 }; 6455 };
6904 }; 6456 };
6905 6457
6906 video-thermal { 6458 video-thermal {
6907 polling-delay-passive 6459 polling-delay-passive = <250>;
>> 6460 polling-delay = <1000>;
6908 6461
6909 thermal-sensors = <&t 6462 thermal-sensors = <&tsens1 2>;
6910 6463
6911 trips { 6464 trips {
6912 video_alert0: 6465 video_alert0: trip-point0 {
6913 tempe 6466 temperature = <90000>;
6914 hyste 6467 hysteresis = <2000>;
6915 type 6468 type = "hot";
6916 }; 6469 };
6917 }; 6470 };
6918 }; 6471 };
6919 6472
6920 mem-thermal { 6473 mem-thermal {
6921 polling-delay-passive 6474 polling-delay-passive = <250>;
>> 6475 polling-delay = <1000>;
6922 6476
6923 thermal-sensors = <&t 6477 thermal-sensors = <&tsens1 3>;
6924 6478
6925 trips { 6479 trips {
6926 mem_alert0: t 6480 mem_alert0: trip-point0 {
6927 tempe 6481 temperature = <90000>;
6928 hyste 6482 hysteresis = <2000>;
6929 type 6483 type = "hot";
6930 }; 6484 };
6931 }; 6485 };
6932 }; 6486 };
6933 6487
6934 q6-hvx-thermal { 6488 q6-hvx-thermal {
6935 polling-delay-passive 6489 polling-delay-passive = <250>;
>> 6490 polling-delay = <1000>;
6936 6491
6937 thermal-sensors = <&t 6492 thermal-sensors = <&tsens1 4>;
6938 6493
6939 trips { 6494 trips {
6940 q6_hvx_alert0 6495 q6_hvx_alert0: trip-point0 {
6941 tempe 6496 temperature = <90000>;
6942 hyste 6497 hysteresis = <2000>;
6943 type 6498 type = "hot";
6944 }; 6499 };
6945 }; 6500 };
6946 }; 6501 };
6947 6502
6948 camera-thermal { 6503 camera-thermal {
6949 polling-delay-passive 6504 polling-delay-passive = <250>;
>> 6505 polling-delay = <1000>;
6950 6506
6951 thermal-sensors = <&t 6507 thermal-sensors = <&tsens1 5>;
6952 6508
6953 trips { 6509 trips {
6954 camera_alert0 6510 camera_alert0: trip-point0 {
6955 tempe 6511 temperature = <90000>;
6956 hyste 6512 hysteresis = <2000>;
6957 type 6513 type = "hot";
6958 }; 6514 };
6959 }; 6515 };
6960 }; 6516 };
6961 6517
6962 compute-thermal { 6518 compute-thermal {
6963 polling-delay-passive 6519 polling-delay-passive = <250>;
>> 6520 polling-delay = <1000>;
6964 6521
6965 thermal-sensors = <&t 6522 thermal-sensors = <&tsens1 6>;
6966 6523
6967 trips { 6524 trips {
6968 compute_alert 6525 compute_alert0: trip-point0 {
6969 tempe 6526 temperature = <90000>;
6970 hyste 6527 hysteresis = <2000>;
6971 type 6528 type = "hot";
6972 }; 6529 };
6973 }; 6530 };
6974 }; 6531 };
6975 6532
6976 npu-thermal { 6533 npu-thermal {
6977 polling-delay-passive 6534 polling-delay-passive = <250>;
>> 6535 polling-delay = <1000>;
6978 6536
6979 thermal-sensors = <&t 6537 thermal-sensors = <&tsens1 7>;
6980 6538
6981 trips { 6539 trips {
6982 npu_alert0: t 6540 npu_alert0: trip-point0 {
6983 tempe 6541 temperature = <90000>;
6984 hyste 6542 hysteresis = <2000>;
6985 type 6543 type = "hot";
6986 }; 6544 };
6987 }; 6545 };
6988 }; 6546 };
6989 6547
6990 gpu-bottom-thermal { 6548 gpu-bottom-thermal {
6991 polling-delay-passive 6549 polling-delay-passive = <250>;
>> 6550 polling-delay = <1000>;
6992 6551
6993 thermal-sensors = <&t 6552 thermal-sensors = <&tsens1 8>;
6994 6553
6995 cooling-maps { <<
6996 map0 { <<
6997 trip <<
6998 cooli <<
6999 }; <<
7000 }; <<
7001 <<
7002 trips { 6554 trips {
7003 gpu_bottom_al !! 6555 gpu2_alert0: trip-point0 {
7004 tempe <<
7005 hyste <<
7006 type <<
7007 }; <<
7008 <<
7009 trip-point1 { <<
7010 tempe 6556 temperature = <90000>;
7011 hyste !! 6557 hysteresis = <2000>;
7012 type 6558 type = "hot";
7013 }; <<
7014 <<
7015 trip-point2 { <<
7016 tempe <<
7017 hyste <<
7018 type <<
7019 }; 6559 };
7020 }; 6560 };
7021 }; 6561 };
7022 }; 6562 };
7023 }; 6563 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.