1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * Copyright (c) 2020, The Linux Foundation. A 3 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
4 */ 4 */
5 5
6 #include <dt-bindings/interrupt-controller/arm 6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,dispcc-sm8250 7 #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
8 #include <dt-bindings/clock/qcom,gcc-sm8250.h> 8 #include <dt-bindings/clock/qcom,gcc-sm8250.h>
9 #include <dt-bindings/clock/qcom,gpucc-sm8250. 9 #include <dt-bindings/clock/qcom,gpucc-sm8250.h>
10 #include <dt-bindings/clock/qcom,rpmh.h> 10 #include <dt-bindings/clock/qcom,rpmh.h>
>> 11 #include <dt-bindings/clock/qcom,sm8250-lpass-aoncc.h>
>> 12 #include <dt-bindings/clock/qcom,sm8250-lpass-audiocc.h>
11 #include <dt-bindings/dma/qcom-gpi.h> 13 #include <dt-bindings/dma/qcom-gpi.h>
12 #include <dt-bindings/gpio/gpio.h> 14 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interconnect/qcom,osm-l3 15 #include <dt-bindings/interconnect/qcom,osm-l3.h>
14 #include <dt-bindings/interconnect/qcom,sm8250 16 #include <dt-bindings/interconnect/qcom,sm8250.h>
15 #include <dt-bindings/mailbox/qcom-ipcc.h> 17 #include <dt-bindings/mailbox/qcom-ipcc.h>
16 #include <dt-bindings/phy/phy-qcom-qmp.h> 18 #include <dt-bindings/phy/phy-qcom-qmp.h>
17 #include <dt-bindings/power/qcom-rpmpd.h> 19 #include <dt-bindings/power/qcom-rpmpd.h>
18 #include <dt-bindings/power/qcom,rpmhpd.h> 20 #include <dt-bindings/power/qcom,rpmhpd.h>
19 #include <dt-bindings/soc/qcom,apr.h> 21 #include <dt-bindings/soc/qcom,apr.h>
20 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 22 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
21 #include <dt-bindings/sound/qcom,q6afe.h> 23 #include <dt-bindings/sound/qcom,q6afe.h>
22 #include <dt-bindings/thermal/thermal.h> 24 #include <dt-bindings/thermal/thermal.h>
23 #include <dt-bindings/clock/qcom,camcc-sm8250. 25 #include <dt-bindings/clock/qcom,camcc-sm8250.h>
24 #include <dt-bindings/clock/qcom,videocc-sm825 26 #include <dt-bindings/clock/qcom,videocc-sm8250.h>
25 27
26 / { 28 / {
27 interrupt-parent = <&intc>; 29 interrupt-parent = <&intc>;
28 30
29 #address-cells = <2>; 31 #address-cells = <2>;
30 #size-cells = <2>; 32 #size-cells = <2>;
31 33
32 aliases { 34 aliases {
33 i2c0 = &i2c0; 35 i2c0 = &i2c0;
34 i2c1 = &i2c1; 36 i2c1 = &i2c1;
35 i2c2 = &i2c2; 37 i2c2 = &i2c2;
36 i2c3 = &i2c3; 38 i2c3 = &i2c3;
37 i2c4 = &i2c4; 39 i2c4 = &i2c4;
38 i2c5 = &i2c5; 40 i2c5 = &i2c5;
39 i2c6 = &i2c6; 41 i2c6 = &i2c6;
40 i2c7 = &i2c7; 42 i2c7 = &i2c7;
41 i2c8 = &i2c8; 43 i2c8 = &i2c8;
42 i2c9 = &i2c9; 44 i2c9 = &i2c9;
43 i2c10 = &i2c10; 45 i2c10 = &i2c10;
44 i2c11 = &i2c11; 46 i2c11 = &i2c11;
45 i2c12 = &i2c12; 47 i2c12 = &i2c12;
46 i2c13 = &i2c13; 48 i2c13 = &i2c13;
47 i2c14 = &i2c14; 49 i2c14 = &i2c14;
48 i2c15 = &i2c15; 50 i2c15 = &i2c15;
49 i2c16 = &i2c16; 51 i2c16 = &i2c16;
50 i2c17 = &i2c17; 52 i2c17 = &i2c17;
51 i2c18 = &i2c18; 53 i2c18 = &i2c18;
52 i2c19 = &i2c19; 54 i2c19 = &i2c19;
53 spi0 = &spi0; 55 spi0 = &spi0;
54 spi1 = &spi1; 56 spi1 = &spi1;
55 spi2 = &spi2; 57 spi2 = &spi2;
56 spi3 = &spi3; 58 spi3 = &spi3;
57 spi4 = &spi4; 59 spi4 = &spi4;
58 spi5 = &spi5; 60 spi5 = &spi5;
59 spi6 = &spi6; 61 spi6 = &spi6;
60 spi7 = &spi7; 62 spi7 = &spi7;
61 spi8 = &spi8; 63 spi8 = &spi8;
62 spi9 = &spi9; 64 spi9 = &spi9;
63 spi10 = &spi10; 65 spi10 = &spi10;
64 spi11 = &spi11; 66 spi11 = &spi11;
65 spi12 = &spi12; 67 spi12 = &spi12;
66 spi13 = &spi13; 68 spi13 = &spi13;
67 spi14 = &spi14; 69 spi14 = &spi14;
68 spi15 = &spi15; 70 spi15 = &spi15;
69 spi16 = &spi16; 71 spi16 = &spi16;
70 spi17 = &spi17; 72 spi17 = &spi17;
71 spi18 = &spi18; 73 spi18 = &spi18;
72 spi19 = &spi19; 74 spi19 = &spi19;
73 }; 75 };
74 76
75 chosen { }; 77 chosen { };
76 78
77 clocks { 79 clocks {
78 xo_board: xo-board { 80 xo_board: xo-board {
79 compatible = "fixed-cl 81 compatible = "fixed-clock";
80 #clock-cells = <0>; 82 #clock-cells = <0>;
81 clock-frequency = <384 83 clock-frequency = <38400000>;
82 clock-output-names = " 84 clock-output-names = "xo_board";
83 }; 85 };
84 86
85 sleep_clk: sleep-clk { 87 sleep_clk: sleep-clk {
86 compatible = "fixed-cl 88 compatible = "fixed-clock";
87 clock-frequency = <327 89 clock-frequency = <32768>;
88 #clock-cells = <0>; 90 #clock-cells = <0>;
89 }; 91 };
90 }; 92 };
91 93
92 cpus { 94 cpus {
93 #address-cells = <2>; 95 #address-cells = <2>;
94 #size-cells = <0>; 96 #size-cells = <0>;
95 97
96 CPU0: cpu@0 { 98 CPU0: cpu@0 {
97 device_type = "cpu"; 99 device_type = "cpu";
98 compatible = "qcom,kry 100 compatible = "qcom,kryo485";
99 reg = <0x0 0x0>; 101 reg = <0x0 0x0>;
100 clocks = <&cpufreq_hw 102 clocks = <&cpufreq_hw 0>;
101 enable-method = "psci" 103 enable-method = "psci";
102 capacity-dmips-mhz = < 104 capacity-dmips-mhz = <448>;
103 dynamic-power-coeffici 105 dynamic-power-coefficient = <105>;
104 next-level-cache = <&L 106 next-level-cache = <&L2_0>;
105 power-domains = <&CPU_ 107 power-domains = <&CPU_PD0>;
106 power-domain-names = " 108 power-domain-names = "psci";
107 qcom,freq-domain = <&c 109 qcom,freq-domain = <&cpufreq_hw 0>;
108 operating-points-v2 = 110 operating-points-v2 = <&cpu0_opp_table>;
109 interconnects = <&gem_ 111 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
110 <&epss 112 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
111 #cooling-cells = <2>; 113 #cooling-cells = <2>;
112 L2_0: l2-cache { 114 L2_0: l2-cache {
113 compatible = " 115 compatible = "cache";
114 cache-level = 116 cache-level = <2>;
115 cache-size = < 117 cache-size = <0x20000>;
116 cache-unified; 118 cache-unified;
117 next-level-cac 119 next-level-cache = <&L3_0>;
118 L3_0: l3-cache 120 L3_0: l3-cache {
119 compat 121 compatible = "cache";
120 cache- 122 cache-level = <3>;
121 cache- 123 cache-size = <0x400000>;
122 cache- 124 cache-unified;
123 }; 125 };
124 }; 126 };
125 }; 127 };
126 128
127 CPU1: cpu@100 { 129 CPU1: cpu@100 {
128 device_type = "cpu"; 130 device_type = "cpu";
129 compatible = "qcom,kry 131 compatible = "qcom,kryo485";
130 reg = <0x0 0x100>; 132 reg = <0x0 0x100>;
131 clocks = <&cpufreq_hw 133 clocks = <&cpufreq_hw 0>;
132 enable-method = "psci" 134 enable-method = "psci";
133 capacity-dmips-mhz = < 135 capacity-dmips-mhz = <448>;
134 dynamic-power-coeffici 136 dynamic-power-coefficient = <105>;
135 next-level-cache = <&L 137 next-level-cache = <&L2_100>;
136 power-domains = <&CPU_ 138 power-domains = <&CPU_PD1>;
137 power-domain-names = " 139 power-domain-names = "psci";
138 qcom,freq-domain = <&c 140 qcom,freq-domain = <&cpufreq_hw 0>;
139 operating-points-v2 = 141 operating-points-v2 = <&cpu0_opp_table>;
140 interconnects = <&gem_ 142 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
141 <&epss 143 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
142 #cooling-cells = <2>; 144 #cooling-cells = <2>;
143 L2_100: l2-cache { 145 L2_100: l2-cache {
144 compatible = " 146 compatible = "cache";
145 cache-level = 147 cache-level = <2>;
146 cache-size = < 148 cache-size = <0x20000>;
147 cache-unified; 149 cache-unified;
148 next-level-cac 150 next-level-cache = <&L3_0>;
149 }; 151 };
150 }; 152 };
151 153
152 CPU2: cpu@200 { 154 CPU2: cpu@200 {
153 device_type = "cpu"; 155 device_type = "cpu";
154 compatible = "qcom,kry 156 compatible = "qcom,kryo485";
155 reg = <0x0 0x200>; 157 reg = <0x0 0x200>;
156 clocks = <&cpufreq_hw 158 clocks = <&cpufreq_hw 0>;
157 enable-method = "psci" 159 enable-method = "psci";
158 capacity-dmips-mhz = < 160 capacity-dmips-mhz = <448>;
159 dynamic-power-coeffici 161 dynamic-power-coefficient = <105>;
160 next-level-cache = <&L 162 next-level-cache = <&L2_200>;
161 power-domains = <&CPU_ 163 power-domains = <&CPU_PD2>;
162 power-domain-names = " 164 power-domain-names = "psci";
163 qcom,freq-domain = <&c 165 qcom,freq-domain = <&cpufreq_hw 0>;
164 operating-points-v2 = 166 operating-points-v2 = <&cpu0_opp_table>;
165 interconnects = <&gem_ 167 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
166 <&epss 168 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
167 #cooling-cells = <2>; 169 #cooling-cells = <2>;
168 L2_200: l2-cache { 170 L2_200: l2-cache {
169 compatible = " 171 compatible = "cache";
170 cache-level = 172 cache-level = <2>;
171 cache-size = < 173 cache-size = <0x20000>;
172 cache-unified; 174 cache-unified;
173 next-level-cac 175 next-level-cache = <&L3_0>;
174 }; 176 };
175 }; 177 };
176 178
177 CPU3: cpu@300 { 179 CPU3: cpu@300 {
178 device_type = "cpu"; 180 device_type = "cpu";
179 compatible = "qcom,kry 181 compatible = "qcom,kryo485";
180 reg = <0x0 0x300>; 182 reg = <0x0 0x300>;
181 clocks = <&cpufreq_hw 183 clocks = <&cpufreq_hw 0>;
182 enable-method = "psci" 184 enable-method = "psci";
183 capacity-dmips-mhz = < 185 capacity-dmips-mhz = <448>;
184 dynamic-power-coeffici 186 dynamic-power-coefficient = <105>;
185 next-level-cache = <&L 187 next-level-cache = <&L2_300>;
186 power-domains = <&CPU_ 188 power-domains = <&CPU_PD3>;
187 power-domain-names = " 189 power-domain-names = "psci";
188 qcom,freq-domain = <&c 190 qcom,freq-domain = <&cpufreq_hw 0>;
189 operating-points-v2 = 191 operating-points-v2 = <&cpu0_opp_table>;
190 interconnects = <&gem_ 192 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
191 <&epss 193 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
192 #cooling-cells = <2>; 194 #cooling-cells = <2>;
193 L2_300: l2-cache { 195 L2_300: l2-cache {
194 compatible = " 196 compatible = "cache";
195 cache-level = 197 cache-level = <2>;
196 cache-size = < 198 cache-size = <0x20000>;
197 cache-unified; 199 cache-unified;
198 next-level-cac 200 next-level-cache = <&L3_0>;
199 }; 201 };
200 }; 202 };
201 203
202 CPU4: cpu@400 { 204 CPU4: cpu@400 {
203 device_type = "cpu"; 205 device_type = "cpu";
204 compatible = "qcom,kry 206 compatible = "qcom,kryo485";
205 reg = <0x0 0x400>; 207 reg = <0x0 0x400>;
206 clocks = <&cpufreq_hw 208 clocks = <&cpufreq_hw 1>;
207 enable-method = "psci" 209 enable-method = "psci";
208 capacity-dmips-mhz = < 210 capacity-dmips-mhz = <1024>;
209 dynamic-power-coeffici 211 dynamic-power-coefficient = <379>;
210 next-level-cache = <&L 212 next-level-cache = <&L2_400>;
211 power-domains = <&CPU_ 213 power-domains = <&CPU_PD4>;
212 power-domain-names = " 214 power-domain-names = "psci";
213 qcom,freq-domain = <&c 215 qcom,freq-domain = <&cpufreq_hw 1>;
214 operating-points-v2 = 216 operating-points-v2 = <&cpu4_opp_table>;
215 interconnects = <&gem_ 217 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
216 <&epss 218 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
217 #cooling-cells = <2>; 219 #cooling-cells = <2>;
218 L2_400: l2-cache { 220 L2_400: l2-cache {
219 compatible = " 221 compatible = "cache";
220 cache-level = 222 cache-level = <2>;
221 cache-size = < 223 cache-size = <0x40000>;
222 cache-unified; 224 cache-unified;
223 next-level-cac 225 next-level-cache = <&L3_0>;
224 }; 226 };
225 }; 227 };
226 228
227 CPU5: cpu@500 { 229 CPU5: cpu@500 {
228 device_type = "cpu"; 230 device_type = "cpu";
229 compatible = "qcom,kry 231 compatible = "qcom,kryo485";
230 reg = <0x0 0x500>; 232 reg = <0x0 0x500>;
231 clocks = <&cpufreq_hw 233 clocks = <&cpufreq_hw 1>;
232 enable-method = "psci" 234 enable-method = "psci";
233 capacity-dmips-mhz = < 235 capacity-dmips-mhz = <1024>;
234 dynamic-power-coeffici 236 dynamic-power-coefficient = <379>;
235 next-level-cache = <&L 237 next-level-cache = <&L2_500>;
236 power-domains = <&CPU_ 238 power-domains = <&CPU_PD5>;
237 power-domain-names = " 239 power-domain-names = "psci";
238 qcom,freq-domain = <&c 240 qcom,freq-domain = <&cpufreq_hw 1>;
239 operating-points-v2 = 241 operating-points-v2 = <&cpu4_opp_table>;
240 interconnects = <&gem_ 242 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
241 <&epss 243 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
242 #cooling-cells = <2>; 244 #cooling-cells = <2>;
243 L2_500: l2-cache { 245 L2_500: l2-cache {
244 compatible = " 246 compatible = "cache";
245 cache-level = 247 cache-level = <2>;
246 cache-size = < 248 cache-size = <0x40000>;
247 cache-unified; 249 cache-unified;
248 next-level-cac 250 next-level-cache = <&L3_0>;
249 }; 251 };
250 }; 252 };
251 253
252 CPU6: cpu@600 { 254 CPU6: cpu@600 {
253 device_type = "cpu"; 255 device_type = "cpu";
254 compatible = "qcom,kry 256 compatible = "qcom,kryo485";
255 reg = <0x0 0x600>; 257 reg = <0x0 0x600>;
256 clocks = <&cpufreq_hw 258 clocks = <&cpufreq_hw 1>;
257 enable-method = "psci" 259 enable-method = "psci";
258 capacity-dmips-mhz = < 260 capacity-dmips-mhz = <1024>;
259 dynamic-power-coeffici 261 dynamic-power-coefficient = <379>;
260 next-level-cache = <&L 262 next-level-cache = <&L2_600>;
261 power-domains = <&CPU_ 263 power-domains = <&CPU_PD6>;
262 power-domain-names = " 264 power-domain-names = "psci";
263 qcom,freq-domain = <&c 265 qcom,freq-domain = <&cpufreq_hw 1>;
264 operating-points-v2 = 266 operating-points-v2 = <&cpu4_opp_table>;
265 interconnects = <&gem_ 267 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
266 <&epss 268 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
267 #cooling-cells = <2>; 269 #cooling-cells = <2>;
268 L2_600: l2-cache { 270 L2_600: l2-cache {
269 compatible = " 271 compatible = "cache";
270 cache-level = 272 cache-level = <2>;
271 cache-size = < 273 cache-size = <0x40000>;
272 cache-unified; 274 cache-unified;
273 next-level-cac 275 next-level-cache = <&L3_0>;
274 }; 276 };
275 }; 277 };
276 278
277 CPU7: cpu@700 { 279 CPU7: cpu@700 {
278 device_type = "cpu"; 280 device_type = "cpu";
279 compatible = "qcom,kry 281 compatible = "qcom,kryo485";
280 reg = <0x0 0x700>; 282 reg = <0x0 0x700>;
281 clocks = <&cpufreq_hw 283 clocks = <&cpufreq_hw 2>;
282 enable-method = "psci" 284 enable-method = "psci";
283 capacity-dmips-mhz = < 285 capacity-dmips-mhz = <1024>;
284 dynamic-power-coeffici 286 dynamic-power-coefficient = <444>;
285 next-level-cache = <&L 287 next-level-cache = <&L2_700>;
286 power-domains = <&CPU_ 288 power-domains = <&CPU_PD7>;
287 power-domain-names = " 289 power-domain-names = "psci";
288 qcom,freq-domain = <&c 290 qcom,freq-domain = <&cpufreq_hw 2>;
289 operating-points-v2 = 291 operating-points-v2 = <&cpu7_opp_table>;
290 interconnects = <&gem_ 292 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
291 <&epss 293 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
292 #cooling-cells = <2>; 294 #cooling-cells = <2>;
293 L2_700: l2-cache { 295 L2_700: l2-cache {
294 compatible = " 296 compatible = "cache";
295 cache-level = 297 cache-level = <2>;
296 cache-size = < 298 cache-size = <0x80000>;
297 cache-unified; 299 cache-unified;
298 next-level-cac 300 next-level-cache = <&L3_0>;
299 }; 301 };
300 }; 302 };
301 303
302 cpu-map { 304 cpu-map {
303 cluster0 { 305 cluster0 {
304 core0 { 306 core0 {
305 cpu = 307 cpu = <&CPU0>;
306 }; 308 };
307 309
308 core1 { 310 core1 {
309 cpu = 311 cpu = <&CPU1>;
310 }; 312 };
311 313
312 core2 { 314 core2 {
313 cpu = 315 cpu = <&CPU2>;
314 }; 316 };
315 317
316 core3 { 318 core3 {
317 cpu = 319 cpu = <&CPU3>;
318 }; 320 };
319 321
320 core4 { 322 core4 {
321 cpu = 323 cpu = <&CPU4>;
322 }; 324 };
323 325
324 core5 { 326 core5 {
325 cpu = 327 cpu = <&CPU5>;
326 }; 328 };
327 329
328 core6 { 330 core6 {
329 cpu = 331 cpu = <&CPU6>;
330 }; 332 };
331 333
332 core7 { 334 core7 {
333 cpu = 335 cpu = <&CPU7>;
334 }; 336 };
335 }; 337 };
336 }; 338 };
337 339
338 idle-states { 340 idle-states {
339 entry-method = "psci"; 341 entry-method = "psci";
340 342
341 LITTLE_CPU_SLEEP_0: cp 343 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
342 compatible = " 344 compatible = "arm,idle-state";
343 idle-state-nam 345 idle-state-name = "silver-rail-power-collapse";
344 arm,psci-suspe 346 arm,psci-suspend-param = <0x40000004>;
345 entry-latency- 347 entry-latency-us = <360>;
346 exit-latency-u 348 exit-latency-us = <531>;
347 min-residency- 349 min-residency-us = <3934>;
348 local-timer-st 350 local-timer-stop;
349 }; 351 };
350 352
351 BIG_CPU_SLEEP_0: cpu-s 353 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
352 compatible = " 354 compatible = "arm,idle-state";
353 idle-state-nam 355 idle-state-name = "gold-rail-power-collapse";
354 arm,psci-suspe 356 arm,psci-suspend-param = <0x40000004>;
355 entry-latency- 357 entry-latency-us = <702>;
356 exit-latency-u 358 exit-latency-us = <1061>;
357 min-residency- 359 min-residency-us = <4488>;
358 local-timer-st 360 local-timer-stop;
359 }; 361 };
360 }; 362 };
361 363
362 domain-idle-states { 364 domain-idle-states {
363 CLUSTER_SLEEP_0: clust 365 CLUSTER_SLEEP_0: cluster-sleep-0 {
364 compatible = " 366 compatible = "domain-idle-state";
365 arm,psci-suspe 367 arm,psci-suspend-param = <0x4100c244>;
366 entry-latency- 368 entry-latency-us = <3264>;
367 exit-latency-u 369 exit-latency-us = <6562>;
368 min-residency- 370 min-residency-us = <9987>;
369 }; 371 };
370 }; 372 };
371 }; 373 };
372 374
373 qup_virt: interconnect-qup-virt { 375 qup_virt: interconnect-qup-virt {
374 compatible = "qcom,sm8250-qup- 376 compatible = "qcom,sm8250-qup-virt";
375 #interconnect-cells = <2>; 377 #interconnect-cells = <2>;
376 qcom,bcm-voters = <&apps_bcm_v 378 qcom,bcm-voters = <&apps_bcm_voter>;
377 }; 379 };
378 380
379 cpu0_opp_table: opp-table-cpu0 { 381 cpu0_opp_table: opp-table-cpu0 {
380 compatible = "operating-points 382 compatible = "operating-points-v2";
381 opp-shared; 383 opp-shared;
382 384
383 cpu0_opp1: opp-300000000 { 385 cpu0_opp1: opp-300000000 {
384 opp-hz = /bits/ 64 <30 386 opp-hz = /bits/ 64 <300000000>;
385 opp-peak-kBps = <80000 387 opp-peak-kBps = <800000 9600000>;
386 }; 388 };
387 389
388 cpu0_opp2: opp-403200000 { 390 cpu0_opp2: opp-403200000 {
389 opp-hz = /bits/ 64 <40 391 opp-hz = /bits/ 64 <403200000>;
390 opp-peak-kBps = <80000 392 opp-peak-kBps = <800000 9600000>;
391 }; 393 };
392 394
393 cpu0_opp3: opp-518400000 { 395 cpu0_opp3: opp-518400000 {
394 opp-hz = /bits/ 64 <51 396 opp-hz = /bits/ 64 <518400000>;
395 opp-peak-kBps = <80000 397 opp-peak-kBps = <800000 16588800>;
396 }; 398 };
397 399
398 cpu0_opp4: opp-614400000 { 400 cpu0_opp4: opp-614400000 {
399 opp-hz = /bits/ 64 <61 401 opp-hz = /bits/ 64 <614400000>;
400 opp-peak-kBps = <80000 402 opp-peak-kBps = <800000 16588800>;
401 }; 403 };
402 404
403 cpu0_opp5: opp-691200000 { 405 cpu0_opp5: opp-691200000 {
404 opp-hz = /bits/ 64 <69 406 opp-hz = /bits/ 64 <691200000>;
405 opp-peak-kBps = <80000 407 opp-peak-kBps = <800000 19660800>;
406 }; 408 };
407 409
408 cpu0_opp6: opp-787200000 { 410 cpu0_opp6: opp-787200000 {
409 opp-hz = /bits/ 64 <78 411 opp-hz = /bits/ 64 <787200000>;
410 opp-peak-kBps = <18040 412 opp-peak-kBps = <1804000 19660800>;
411 }; 413 };
412 414
413 cpu0_opp7: opp-883200000 { 415 cpu0_opp7: opp-883200000 {
414 opp-hz = /bits/ 64 <88 416 opp-hz = /bits/ 64 <883200000>;
415 opp-peak-kBps = <18040 417 opp-peak-kBps = <1804000 23347200>;
416 }; 418 };
417 419
418 cpu0_opp8: opp-979200000 { 420 cpu0_opp8: opp-979200000 {
419 opp-hz = /bits/ 64 <97 421 opp-hz = /bits/ 64 <979200000>;
420 opp-peak-kBps = <18040 422 opp-peak-kBps = <1804000 26419200>;
421 }; 423 };
422 424
423 cpu0_opp9: opp-1075200000 { 425 cpu0_opp9: opp-1075200000 {
424 opp-hz = /bits/ 64 <10 426 opp-hz = /bits/ 64 <1075200000>;
425 opp-peak-kBps = <18040 427 opp-peak-kBps = <1804000 29491200>;
426 }; 428 };
427 429
428 cpu0_opp10: opp-1171200000 { 430 cpu0_opp10: opp-1171200000 {
429 opp-hz = /bits/ 64 <11 431 opp-hz = /bits/ 64 <1171200000>;
430 opp-peak-kBps = <18040 432 opp-peak-kBps = <1804000 32563200>;
431 }; 433 };
432 434
433 cpu0_opp11: opp-1248000000 { 435 cpu0_opp11: opp-1248000000 {
434 opp-hz = /bits/ 64 <12 436 opp-hz = /bits/ 64 <1248000000>;
435 opp-peak-kBps = <18040 437 opp-peak-kBps = <1804000 36249600>;
436 }; 438 };
437 439
438 cpu0_opp12: opp-1344000000 { 440 cpu0_opp12: opp-1344000000 {
439 opp-hz = /bits/ 64 <13 441 opp-hz = /bits/ 64 <1344000000>;
440 opp-peak-kBps = <21880 442 opp-peak-kBps = <2188000 36249600>;
441 }; 443 };
442 444
443 cpu0_opp13: opp-1420800000 { 445 cpu0_opp13: opp-1420800000 {
444 opp-hz = /bits/ 64 <14 446 opp-hz = /bits/ 64 <1420800000>;
445 opp-peak-kBps = <21880 447 opp-peak-kBps = <2188000 39321600>;
446 }; 448 };
447 449
448 cpu0_opp14: opp-1516800000 { 450 cpu0_opp14: opp-1516800000 {
449 opp-hz = /bits/ 64 <15 451 opp-hz = /bits/ 64 <1516800000>;
450 opp-peak-kBps = <30720 452 opp-peak-kBps = <3072000 42393600>;
451 }; 453 };
452 454
453 cpu0_opp15: opp-1612800000 { 455 cpu0_opp15: opp-1612800000 {
454 opp-hz = /bits/ 64 <16 456 opp-hz = /bits/ 64 <1612800000>;
455 opp-peak-kBps = <30720 457 opp-peak-kBps = <3072000 42393600>;
456 }; 458 };
457 459
458 cpu0_opp16: opp-1708800000 { 460 cpu0_opp16: opp-1708800000 {
459 opp-hz = /bits/ 64 <17 461 opp-hz = /bits/ 64 <1708800000>;
460 opp-peak-kBps = <40680 462 opp-peak-kBps = <4068000 42393600>;
461 }; 463 };
462 464
463 cpu0_opp17: opp-1804800000 { 465 cpu0_opp17: opp-1804800000 {
464 opp-hz = /bits/ 64 <18 466 opp-hz = /bits/ 64 <1804800000>;
465 opp-peak-kBps = <40680 467 opp-peak-kBps = <4068000 42393600>;
466 }; 468 };
467 }; 469 };
468 470
469 cpu4_opp_table: opp-table-cpu4 { 471 cpu4_opp_table: opp-table-cpu4 {
470 compatible = "operating-points 472 compatible = "operating-points-v2";
471 opp-shared; 473 opp-shared;
472 474
473 cpu4_opp1: opp-710400000 { 475 cpu4_opp1: opp-710400000 {
474 opp-hz = /bits/ 64 <71 476 opp-hz = /bits/ 64 <710400000>;
475 opp-peak-kBps = <18040 477 opp-peak-kBps = <1804000 19660800>;
476 }; 478 };
477 479
478 cpu4_opp2: opp-825600000 { 480 cpu4_opp2: opp-825600000 {
479 opp-hz = /bits/ 64 <82 481 opp-hz = /bits/ 64 <825600000>;
480 opp-peak-kBps = <21880 482 opp-peak-kBps = <2188000 23347200>;
481 }; 483 };
482 484
483 cpu4_opp3: opp-940800000 { 485 cpu4_opp3: opp-940800000 {
484 opp-hz = /bits/ 64 <94 486 opp-hz = /bits/ 64 <940800000>;
485 opp-peak-kBps = <21880 487 opp-peak-kBps = <2188000 26419200>;
486 }; 488 };
487 489
488 cpu4_opp4: opp-1056000000 { 490 cpu4_opp4: opp-1056000000 {
489 opp-hz = /bits/ 64 <10 491 opp-hz = /bits/ 64 <1056000000>;
490 opp-peak-kBps = <30720 492 opp-peak-kBps = <3072000 26419200>;
491 }; 493 };
492 494
493 cpu4_opp5: opp-1171200000 { 495 cpu4_opp5: opp-1171200000 {
494 opp-hz = /bits/ 64 <11 496 opp-hz = /bits/ 64 <1171200000>;
495 opp-peak-kBps = <30720 497 opp-peak-kBps = <3072000 29491200>;
496 }; 498 };
497 499
498 cpu4_opp6: opp-1286400000 { 500 cpu4_opp6: opp-1286400000 {
499 opp-hz = /bits/ 64 <12 501 opp-hz = /bits/ 64 <1286400000>;
500 opp-peak-kBps = <40680 502 opp-peak-kBps = <4068000 29491200>;
501 }; 503 };
502 504
503 cpu4_opp7: opp-1382400000 { 505 cpu4_opp7: opp-1382400000 {
504 opp-hz = /bits/ 64 <13 506 opp-hz = /bits/ 64 <1382400000>;
505 opp-peak-kBps = <40680 507 opp-peak-kBps = <4068000 32563200>;
506 }; 508 };
507 509
508 cpu4_opp8: opp-1478400000 { 510 cpu4_opp8: opp-1478400000 {
509 opp-hz = /bits/ 64 <14 511 opp-hz = /bits/ 64 <1478400000>;
510 opp-peak-kBps = <40680 512 opp-peak-kBps = <4068000 32563200>;
511 }; 513 };
512 514
513 cpu4_opp9: opp-1574400000 { 515 cpu4_opp9: opp-1574400000 {
514 opp-hz = /bits/ 64 <15 516 opp-hz = /bits/ 64 <1574400000>;
515 opp-peak-kBps = <54120 517 opp-peak-kBps = <5412000 39321600>;
516 }; 518 };
517 519
518 cpu4_opp10: opp-1670400000 { 520 cpu4_opp10: opp-1670400000 {
519 opp-hz = /bits/ 64 <16 521 opp-hz = /bits/ 64 <1670400000>;
520 opp-peak-kBps = <54120 522 opp-peak-kBps = <5412000 42393600>;
521 }; 523 };
522 524
523 cpu4_opp11: opp-1766400000 { 525 cpu4_opp11: opp-1766400000 {
524 opp-hz = /bits/ 64 <17 526 opp-hz = /bits/ 64 <1766400000>;
525 opp-peak-kBps = <54120 527 opp-peak-kBps = <5412000 45465600>;
526 }; 528 };
527 529
528 cpu4_opp12: opp-1862400000 { 530 cpu4_opp12: opp-1862400000 {
529 opp-hz = /bits/ 64 <18 531 opp-hz = /bits/ 64 <1862400000>;
530 opp-peak-kBps = <62200 532 opp-peak-kBps = <6220000 45465600>;
531 }; 533 };
532 534
533 cpu4_opp13: opp-1958400000 { 535 cpu4_opp13: opp-1958400000 {
534 opp-hz = /bits/ 64 <19 536 opp-hz = /bits/ 64 <1958400000>;
535 opp-peak-kBps = <62200 537 opp-peak-kBps = <6220000 48537600>;
536 }; 538 };
537 539
538 cpu4_opp14: opp-2054400000 { 540 cpu4_opp14: opp-2054400000 {
539 opp-hz = /bits/ 64 <20 541 opp-hz = /bits/ 64 <2054400000>;
540 opp-peak-kBps = <72160 542 opp-peak-kBps = <7216000 48537600>;
541 }; 543 };
542 544
543 cpu4_opp15: opp-2150400000 { 545 cpu4_opp15: opp-2150400000 {
544 opp-hz = /bits/ 64 <21 546 opp-hz = /bits/ 64 <2150400000>;
545 opp-peak-kBps = <72160 547 opp-peak-kBps = <7216000 51609600>;
546 }; 548 };
547 549
548 cpu4_opp16: opp-2246400000 { 550 cpu4_opp16: opp-2246400000 {
549 opp-hz = /bits/ 64 <22 551 opp-hz = /bits/ 64 <2246400000>;
550 opp-peak-kBps = <72160 552 opp-peak-kBps = <7216000 51609600>;
551 }; 553 };
552 554
553 cpu4_opp17: opp-2342400000 { 555 cpu4_opp17: opp-2342400000 {
554 opp-hz = /bits/ 64 <23 556 opp-hz = /bits/ 64 <2342400000>;
555 opp-peak-kBps = <83680 557 opp-peak-kBps = <8368000 51609600>;
556 }; 558 };
557 559
558 cpu4_opp18: opp-2419200000 { 560 cpu4_opp18: opp-2419200000 {
559 opp-hz = /bits/ 64 <24 561 opp-hz = /bits/ 64 <2419200000>;
560 opp-peak-kBps = <83680 562 opp-peak-kBps = <8368000 51609600>;
561 }; 563 };
562 }; 564 };
563 565
564 cpu7_opp_table: opp-table-cpu7 { 566 cpu7_opp_table: opp-table-cpu7 {
565 compatible = "operating-points 567 compatible = "operating-points-v2";
566 opp-shared; 568 opp-shared;
567 569
568 cpu7_opp1: opp-844800000 { 570 cpu7_opp1: opp-844800000 {
569 opp-hz = /bits/ 64 <84 571 opp-hz = /bits/ 64 <844800000>;
570 opp-peak-kBps = <21880 572 opp-peak-kBps = <2188000 19660800>;
571 }; 573 };
572 574
573 cpu7_opp2: opp-960000000 { 575 cpu7_opp2: opp-960000000 {
574 opp-hz = /bits/ 64 <96 576 opp-hz = /bits/ 64 <960000000>;
575 opp-peak-kBps = <21880 577 opp-peak-kBps = <2188000 26419200>;
576 }; 578 };
577 579
578 cpu7_opp3: opp-1075200000 { 580 cpu7_opp3: opp-1075200000 {
579 opp-hz = /bits/ 64 <10 581 opp-hz = /bits/ 64 <1075200000>;
580 opp-peak-kBps = <30720 582 opp-peak-kBps = <3072000 26419200>;
581 }; 583 };
582 584
583 cpu7_opp4: opp-1190400000 { 585 cpu7_opp4: opp-1190400000 {
584 opp-hz = /bits/ 64 <11 586 opp-hz = /bits/ 64 <1190400000>;
585 opp-peak-kBps = <30720 587 opp-peak-kBps = <3072000 29491200>;
586 }; 588 };
587 589
588 cpu7_opp5: opp-1305600000 { 590 cpu7_opp5: opp-1305600000 {
589 opp-hz = /bits/ 64 <13 591 opp-hz = /bits/ 64 <1305600000>;
590 opp-peak-kBps = <40680 592 opp-peak-kBps = <4068000 32563200>;
591 }; 593 };
592 594
593 cpu7_opp6: opp-1401600000 { 595 cpu7_opp6: opp-1401600000 {
594 opp-hz = /bits/ 64 <14 596 opp-hz = /bits/ 64 <1401600000>;
595 opp-peak-kBps = <40680 597 opp-peak-kBps = <4068000 32563200>;
596 }; 598 };
597 599
598 cpu7_opp7: opp-1516800000 { 600 cpu7_opp7: opp-1516800000 {
599 opp-hz = /bits/ 64 <15 601 opp-hz = /bits/ 64 <1516800000>;
600 opp-peak-kBps = <40680 602 opp-peak-kBps = <4068000 36249600>;
601 }; 603 };
602 604
603 cpu7_opp8: opp-1632000000 { 605 cpu7_opp8: opp-1632000000 {
604 opp-hz = /bits/ 64 <16 606 opp-hz = /bits/ 64 <1632000000>;
605 opp-peak-kBps = <54120 607 opp-peak-kBps = <5412000 39321600>;
606 }; 608 };
607 609
608 cpu7_opp9: opp-1747200000 { 610 cpu7_opp9: opp-1747200000 {
609 opp-hz = /bits/ 64 <17 611 opp-hz = /bits/ 64 <1708800000>;
610 opp-peak-kBps = <54120 612 opp-peak-kBps = <5412000 42393600>;
611 }; 613 };
612 614
613 cpu7_opp10: opp-1862400000 { 615 cpu7_opp10: opp-1862400000 {
614 opp-hz = /bits/ 64 <18 616 opp-hz = /bits/ 64 <1862400000>;
615 opp-peak-kBps = <62200 617 opp-peak-kBps = <6220000 45465600>;
616 }; 618 };
617 619
618 cpu7_opp11: opp-1977600000 { 620 cpu7_opp11: opp-1977600000 {
619 opp-hz = /bits/ 64 <19 621 opp-hz = /bits/ 64 <1977600000>;
620 opp-peak-kBps = <62200 622 opp-peak-kBps = <6220000 48537600>;
621 }; 623 };
622 624
623 cpu7_opp12: opp-2073600000 { 625 cpu7_opp12: opp-2073600000 {
624 opp-hz = /bits/ 64 <20 626 opp-hz = /bits/ 64 <2073600000>;
625 opp-peak-kBps = <72160 627 opp-peak-kBps = <7216000 48537600>;
626 }; 628 };
627 629
628 cpu7_opp13: opp-2169600000 { 630 cpu7_opp13: opp-2169600000 {
629 opp-hz = /bits/ 64 <21 631 opp-hz = /bits/ 64 <2169600000>;
630 opp-peak-kBps = <72160 632 opp-peak-kBps = <7216000 51609600>;
631 }; 633 };
632 634
633 cpu7_opp14: opp-2265600000 { 635 cpu7_opp14: opp-2265600000 {
634 opp-hz = /bits/ 64 <22 636 opp-hz = /bits/ 64 <2265600000>;
635 opp-peak-kBps = <72160 637 opp-peak-kBps = <7216000 51609600>;
636 }; 638 };
637 639
638 cpu7_opp15: opp-2361600000 { 640 cpu7_opp15: opp-2361600000 {
639 opp-hz = /bits/ 64 <23 641 opp-hz = /bits/ 64 <2361600000>;
640 opp-peak-kBps = <83680 642 opp-peak-kBps = <8368000 51609600>;
641 }; 643 };
642 644
643 cpu7_opp16: opp-2457600000 { 645 cpu7_opp16: opp-2457600000 {
644 opp-hz = /bits/ 64 <24 646 opp-hz = /bits/ 64 <2457600000>;
645 opp-peak-kBps = <83680 647 opp-peak-kBps = <8368000 51609600>;
646 }; 648 };
647 649
648 cpu7_opp17: opp-2553600000 { 650 cpu7_opp17: opp-2553600000 {
649 opp-hz = /bits/ 64 <25 651 opp-hz = /bits/ 64 <2553600000>;
650 opp-peak-kBps = <83680 652 opp-peak-kBps = <8368000 51609600>;
651 }; 653 };
652 654
653 cpu7_opp18: opp-2649600000 { 655 cpu7_opp18: opp-2649600000 {
654 opp-hz = /bits/ 64 <26 656 opp-hz = /bits/ 64 <2649600000>;
655 opp-peak-kBps = <83680 657 opp-peak-kBps = <8368000 51609600>;
656 }; 658 };
657 659
658 cpu7_opp19: opp-2745600000 { 660 cpu7_opp19: opp-2745600000 {
659 opp-hz = /bits/ 64 <27 661 opp-hz = /bits/ 64 <2745600000>;
660 opp-peak-kBps = <83680 662 opp-peak-kBps = <8368000 51609600>;
661 }; 663 };
662 664
663 cpu7_opp20: opp-2841600000 { 665 cpu7_opp20: opp-2841600000 {
664 opp-hz = /bits/ 64 <28 666 opp-hz = /bits/ 64 <2841600000>;
665 opp-peak-kBps = <83680 667 opp-peak-kBps = <8368000 51609600>;
666 }; 668 };
667 }; 669 };
668 670
669 firmware { 671 firmware {
670 scm: scm { 672 scm: scm {
671 compatible = "qcom,scm 673 compatible = "qcom,scm-sm8250", "qcom,scm";
672 qcom,dload-mode = <&tc <<
673 #reset-cells = <1>; 674 #reset-cells = <1>;
674 }; 675 };
675 }; 676 };
676 677
677 memory@80000000 { 678 memory@80000000 {
678 device_type = "memory"; 679 device_type = "memory";
679 /* We expect the bootloader to 680 /* We expect the bootloader to fill in the size */
680 reg = <0x0 0x80000000 0x0 0x0> 681 reg = <0x0 0x80000000 0x0 0x0>;
681 }; 682 };
682 683
683 pmu { 684 pmu {
684 compatible = "arm,armv8-pmuv3" 685 compatible = "arm,armv8-pmuv3";
685 interrupts = <GIC_PPI 7 IRQ_TY 686 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
686 }; 687 };
687 688
688 psci { 689 psci {
689 compatible = "arm,psci-1.0"; 690 compatible = "arm,psci-1.0";
690 method = "smc"; 691 method = "smc";
691 692
692 CPU_PD0: power-domain-cpu0 { 693 CPU_PD0: power-domain-cpu0 {
693 #power-domain-cells = 694 #power-domain-cells = <0>;
694 power-domains = <&CLUS 695 power-domains = <&CLUSTER_PD>;
695 domain-idle-states = < 696 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
696 }; 697 };
697 698
698 CPU_PD1: power-domain-cpu1 { 699 CPU_PD1: power-domain-cpu1 {
699 #power-domain-cells = 700 #power-domain-cells = <0>;
700 power-domains = <&CLUS 701 power-domains = <&CLUSTER_PD>;
701 domain-idle-states = < 702 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
702 }; 703 };
703 704
704 CPU_PD2: power-domain-cpu2 { 705 CPU_PD2: power-domain-cpu2 {
705 #power-domain-cells = 706 #power-domain-cells = <0>;
706 power-domains = <&CLUS 707 power-domains = <&CLUSTER_PD>;
707 domain-idle-states = < 708 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
708 }; 709 };
709 710
710 CPU_PD3: power-domain-cpu3 { 711 CPU_PD3: power-domain-cpu3 {
711 #power-domain-cells = 712 #power-domain-cells = <0>;
712 power-domains = <&CLUS 713 power-domains = <&CLUSTER_PD>;
713 domain-idle-states = < 714 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
714 }; 715 };
715 716
716 CPU_PD4: power-domain-cpu4 { 717 CPU_PD4: power-domain-cpu4 {
717 #power-domain-cells = 718 #power-domain-cells = <0>;
718 power-domains = <&CLUS 719 power-domains = <&CLUSTER_PD>;
719 domain-idle-states = < 720 domain-idle-states = <&BIG_CPU_SLEEP_0>;
720 }; 721 };
721 722
722 CPU_PD5: power-domain-cpu5 { 723 CPU_PD5: power-domain-cpu5 {
723 #power-domain-cells = 724 #power-domain-cells = <0>;
724 power-domains = <&CLUS 725 power-domains = <&CLUSTER_PD>;
725 domain-idle-states = < 726 domain-idle-states = <&BIG_CPU_SLEEP_0>;
726 }; 727 };
727 728
728 CPU_PD6: power-domain-cpu6 { 729 CPU_PD6: power-domain-cpu6 {
729 #power-domain-cells = 730 #power-domain-cells = <0>;
730 power-domains = <&CLUS 731 power-domains = <&CLUSTER_PD>;
731 domain-idle-states = < 732 domain-idle-states = <&BIG_CPU_SLEEP_0>;
732 }; 733 };
733 734
734 CPU_PD7: power-domain-cpu7 { 735 CPU_PD7: power-domain-cpu7 {
735 #power-domain-cells = 736 #power-domain-cells = <0>;
736 power-domains = <&CLUS 737 power-domains = <&CLUSTER_PD>;
737 domain-idle-states = < 738 domain-idle-states = <&BIG_CPU_SLEEP_0>;
738 }; 739 };
739 740
740 CLUSTER_PD: power-domain-cpu-c 741 CLUSTER_PD: power-domain-cpu-cluster0 {
741 #power-domain-cells = 742 #power-domain-cells = <0>;
742 domain-idle-states = < 743 domain-idle-states = <&CLUSTER_SLEEP_0>;
743 }; 744 };
744 }; 745 };
745 746
746 qup_opp_table: opp-table-qup { 747 qup_opp_table: opp-table-qup {
747 compatible = "operating-points 748 compatible = "operating-points-v2";
748 749
749 opp-50000000 { 750 opp-50000000 {
750 opp-hz = /bits/ 64 <50 751 opp-hz = /bits/ 64 <50000000>;
751 required-opps = <&rpmh 752 required-opps = <&rpmhpd_opp_min_svs>;
752 }; 753 };
753 754
754 opp-75000000 { 755 opp-75000000 {
755 opp-hz = /bits/ 64 <75 756 opp-hz = /bits/ 64 <75000000>;
756 required-opps = <&rpmh 757 required-opps = <&rpmhpd_opp_low_svs>;
757 }; 758 };
758 759
759 opp-120000000 { 760 opp-120000000 {
760 opp-hz = /bits/ 64 <12 761 opp-hz = /bits/ 64 <120000000>;
761 required-opps = <&rpmh 762 required-opps = <&rpmhpd_opp_svs>;
762 }; 763 };
763 }; 764 };
764 765
765 reserved-memory { 766 reserved-memory {
766 #address-cells = <2>; 767 #address-cells = <2>;
767 #size-cells = <2>; 768 #size-cells = <2>;
768 ranges; 769 ranges;
769 770
770 hyp_mem: memory@80000000 { 771 hyp_mem: memory@80000000 {
771 reg = <0x0 0x80000000 772 reg = <0x0 0x80000000 0x0 0x600000>;
772 no-map; 773 no-map;
773 }; 774 };
774 775
775 xbl_aop_mem: memory@80700000 { 776 xbl_aop_mem: memory@80700000 {
776 reg = <0x0 0x80700000 777 reg = <0x0 0x80700000 0x0 0x160000>;
777 no-map; 778 no-map;
778 }; 779 };
779 780
780 cmd_db: memory@80860000 { 781 cmd_db: memory@80860000 {
781 compatible = "qcom,cmd 782 compatible = "qcom,cmd-db";
782 reg = <0x0 0x80860000 783 reg = <0x0 0x80860000 0x0 0x20000>;
783 no-map; 784 no-map;
784 }; 785 };
785 786
786 smem_mem: memory@80900000 { 787 smem_mem: memory@80900000 {
787 reg = <0x0 0x80900000 788 reg = <0x0 0x80900000 0x0 0x200000>;
788 no-map; 789 no-map;
789 }; 790 };
790 791
791 removed_mem: memory@80b00000 { 792 removed_mem: memory@80b00000 {
792 reg = <0x0 0x80b00000 793 reg = <0x0 0x80b00000 0x0 0x5300000>;
793 no-map; 794 no-map;
794 }; 795 };
795 796
796 camera_mem: memory@86200000 { 797 camera_mem: memory@86200000 {
797 reg = <0x0 0x86200000 798 reg = <0x0 0x86200000 0x0 0x500000>;
798 no-map; 799 no-map;
799 }; 800 };
800 801
801 wlan_mem: memory@86700000 { 802 wlan_mem: memory@86700000 {
802 reg = <0x0 0x86700000 803 reg = <0x0 0x86700000 0x0 0x100000>;
803 no-map; 804 no-map;
804 }; 805 };
805 806
806 ipa_fw_mem: memory@86800000 { 807 ipa_fw_mem: memory@86800000 {
807 reg = <0x0 0x86800000 808 reg = <0x0 0x86800000 0x0 0x10000>;
808 no-map; 809 no-map;
809 }; 810 };
810 811
811 ipa_gsi_mem: memory@86810000 { 812 ipa_gsi_mem: memory@86810000 {
812 reg = <0x0 0x86810000 813 reg = <0x0 0x86810000 0x0 0xa000>;
813 no-map; 814 no-map;
814 }; 815 };
815 816
816 gpu_mem: memory@8681a000 { 817 gpu_mem: memory@8681a000 {
817 reg = <0x0 0x8681a000 818 reg = <0x0 0x8681a000 0x0 0x2000>;
818 no-map; 819 no-map;
819 }; 820 };
820 821
821 npu_mem: memory@86900000 { 822 npu_mem: memory@86900000 {
822 reg = <0x0 0x86900000 823 reg = <0x0 0x86900000 0x0 0x500000>;
823 no-map; 824 no-map;
824 }; 825 };
825 826
826 video_mem: memory@86e00000 { 827 video_mem: memory@86e00000 {
827 reg = <0x0 0x86e00000 828 reg = <0x0 0x86e00000 0x0 0x500000>;
828 no-map; 829 no-map;
829 }; 830 };
830 831
831 cvp_mem: memory@87300000 { 832 cvp_mem: memory@87300000 {
832 reg = <0x0 0x87300000 833 reg = <0x0 0x87300000 0x0 0x500000>;
833 no-map; 834 no-map;
834 }; 835 };
835 836
836 cdsp_mem: memory@87800000 { 837 cdsp_mem: memory@87800000 {
837 reg = <0x0 0x87800000 838 reg = <0x0 0x87800000 0x0 0x1400000>;
838 no-map; 839 no-map;
839 }; 840 };
840 841
841 slpi_mem: memory@88c00000 { 842 slpi_mem: memory@88c00000 {
842 reg = <0x0 0x88c00000 843 reg = <0x0 0x88c00000 0x0 0x1500000>;
843 no-map; 844 no-map;
844 }; 845 };
845 846
846 adsp_mem: memory@8a100000 { 847 adsp_mem: memory@8a100000 {
847 reg = <0x0 0x8a100000 848 reg = <0x0 0x8a100000 0x0 0x1d00000>;
848 no-map; 849 no-map;
849 }; 850 };
850 851
851 spss_mem: memory@8be00000 { 852 spss_mem: memory@8be00000 {
852 reg = <0x0 0x8be00000 853 reg = <0x0 0x8be00000 0x0 0x100000>;
853 no-map; 854 no-map;
854 }; 855 };
855 856
856 cdsp_secure_heap: memory@8bf00 857 cdsp_secure_heap: memory@8bf00000 {
857 reg = <0x0 0x8bf00000 858 reg = <0x0 0x8bf00000 0x0 0x4600000>;
858 no-map; 859 no-map;
859 }; 860 };
860 }; 861 };
861 862
862 smem { 863 smem {
863 compatible = "qcom,smem"; 864 compatible = "qcom,smem";
864 memory-region = <&smem_mem>; 865 memory-region = <&smem_mem>;
865 hwlocks = <&tcsr_mutex 3>; 866 hwlocks = <&tcsr_mutex 3>;
866 }; 867 };
867 868
868 smp2p-adsp { 869 smp2p-adsp {
869 compatible = "qcom,smp2p"; 870 compatible = "qcom,smp2p";
870 qcom,smem = <443>, <429>; 871 qcom,smem = <443>, <429>;
871 interrupts-extended = <&ipcc I 872 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
872 I 873 IPCC_MPROC_SIGNAL_SMP2P
873 I 874 IRQ_TYPE_EDGE_RISING>;
874 mboxes = <&ipcc IPCC_CLIENT_LP 875 mboxes = <&ipcc IPCC_CLIENT_LPASS
875 IPCC_MPROC_SIG 876 IPCC_MPROC_SIGNAL_SMP2P>;
876 877
877 qcom,local-pid = <0>; 878 qcom,local-pid = <0>;
878 qcom,remote-pid = <2>; 879 qcom,remote-pid = <2>;
879 880
880 smp2p_adsp_out: master-kernel 881 smp2p_adsp_out: master-kernel {
881 qcom,entry-name = "mas 882 qcom,entry-name = "master-kernel";
882 #qcom,smem-state-cells 883 #qcom,smem-state-cells = <1>;
883 }; 884 };
884 885
885 smp2p_adsp_in: slave-kernel { 886 smp2p_adsp_in: slave-kernel {
886 qcom,entry-name = "sla 887 qcom,entry-name = "slave-kernel";
887 interrupt-controller; 888 interrupt-controller;
888 #interrupt-cells = <2> 889 #interrupt-cells = <2>;
889 }; 890 };
890 }; 891 };
891 892
892 smp2p-cdsp { 893 smp2p-cdsp {
893 compatible = "qcom,smp2p"; 894 compatible = "qcom,smp2p";
894 qcom,smem = <94>, <432>; 895 qcom,smem = <94>, <432>;
895 interrupts-extended = <&ipcc I 896 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
896 I 897 IPCC_MPROC_SIGNAL_SMP2P
897 I 898 IRQ_TYPE_EDGE_RISING>;
898 mboxes = <&ipcc IPCC_CLIENT_CD 899 mboxes = <&ipcc IPCC_CLIENT_CDSP
899 IPCC_MPROC_SIG 900 IPCC_MPROC_SIGNAL_SMP2P>;
900 901
901 qcom,local-pid = <0>; 902 qcom,local-pid = <0>;
902 qcom,remote-pid = <5>; 903 qcom,remote-pid = <5>;
903 904
904 smp2p_cdsp_out: master-kernel 905 smp2p_cdsp_out: master-kernel {
905 qcom,entry-name = "mas 906 qcom,entry-name = "master-kernel";
906 #qcom,smem-state-cells 907 #qcom,smem-state-cells = <1>;
907 }; 908 };
908 909
909 smp2p_cdsp_in: slave-kernel { 910 smp2p_cdsp_in: slave-kernel {
910 qcom,entry-name = "sla 911 qcom,entry-name = "slave-kernel";
911 interrupt-controller; 912 interrupt-controller;
912 #interrupt-cells = <2> 913 #interrupt-cells = <2>;
913 }; 914 };
914 }; 915 };
915 916
916 smp2p-slpi { 917 smp2p-slpi {
917 compatible = "qcom,smp2p"; 918 compatible = "qcom,smp2p";
918 qcom,smem = <481>, <430>; 919 qcom,smem = <481>, <430>;
919 interrupts-extended = <&ipcc I 920 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
920 I 921 IPCC_MPROC_SIGNAL_SMP2P
921 I 922 IRQ_TYPE_EDGE_RISING>;
922 mboxes = <&ipcc IPCC_CLIENT_SL 923 mboxes = <&ipcc IPCC_CLIENT_SLPI
923 IPCC_MPROC_SIG 924 IPCC_MPROC_SIGNAL_SMP2P>;
924 925
925 qcom,local-pid = <0>; 926 qcom,local-pid = <0>;
926 qcom,remote-pid = <3>; 927 qcom,remote-pid = <3>;
927 928
928 smp2p_slpi_out: master-kernel 929 smp2p_slpi_out: master-kernel {
929 qcom,entry-name = "mas 930 qcom,entry-name = "master-kernel";
930 #qcom,smem-state-cells 931 #qcom,smem-state-cells = <1>;
931 }; 932 };
932 933
933 smp2p_slpi_in: slave-kernel { 934 smp2p_slpi_in: slave-kernel {
934 qcom,entry-name = "sla 935 qcom,entry-name = "slave-kernel";
935 interrupt-controller; 936 interrupt-controller;
936 #interrupt-cells = <2> 937 #interrupt-cells = <2>;
937 }; 938 };
938 }; 939 };
939 940
940 soc: soc@0 { 941 soc: soc@0 {
941 #address-cells = <2>; 942 #address-cells = <2>;
942 #size-cells = <2>; 943 #size-cells = <2>;
943 ranges = <0 0 0 0 0x10 0>; 944 ranges = <0 0 0 0 0x10 0>;
944 dma-ranges = <0 0 0 0 0x10 0>; 945 dma-ranges = <0 0 0 0 0x10 0>;
945 compatible = "simple-bus"; 946 compatible = "simple-bus";
946 947
947 gcc: clock-controller@100000 { 948 gcc: clock-controller@100000 {
948 compatible = "qcom,gcc 949 compatible = "qcom,gcc-sm8250";
949 reg = <0x0 0x00100000 950 reg = <0x0 0x00100000 0x0 0x1f0000>;
950 #clock-cells = <1>; 951 #clock-cells = <1>;
951 #reset-cells = <1>; 952 #reset-cells = <1>;
952 #power-domain-cells = 953 #power-domain-cells = <1>;
953 clock-names = "bi_tcxo 954 clock-names = "bi_tcxo",
954 "bi_tcxo 955 "bi_tcxo_ao",
955 "sleep_c 956 "sleep_clk";
956 clocks = <&rpmhcc RPMH 957 clocks = <&rpmhcc RPMH_CXO_CLK>,
957 <&rpmhcc RPMH 958 <&rpmhcc RPMH_CXO_CLK_A>,
958 <&sleep_clk>; 959 <&sleep_clk>;
959 }; 960 };
960 961
961 ipcc: mailbox@408000 { 962 ipcc: mailbox@408000 {
962 compatible = "qcom,sm8 963 compatible = "qcom,sm8250-ipcc", "qcom,ipcc";
963 reg = <0 0x00408000 0 964 reg = <0 0x00408000 0 0x1000>;
964 interrupts = <GIC_SPI 965 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
965 interrupt-controller; 966 interrupt-controller;
966 #interrupt-cells = <3> 967 #interrupt-cells = <3>;
967 #mbox-cells = <2>; 968 #mbox-cells = <2>;
968 }; 969 };
969 970
970 qfprom: efuse@784000 { 971 qfprom: efuse@784000 {
971 compatible = "qcom,sm8 972 compatible = "qcom,sm8250-qfprom", "qcom,qfprom";
972 reg = <0 0x00784000 0 973 reg = <0 0x00784000 0 0x8ff>;
973 #address-cells = <1>; 974 #address-cells = <1>;
974 #size-cells = <1>; 975 #size-cells = <1>;
975 976
976 gpu_speed_bin: gpu-spe !! 977 gpu_speed_bin: gpu_speed_bin@19b {
977 reg = <0x19b 0 978 reg = <0x19b 0x1>;
978 bits = <5 3>; 979 bits = <5 3>;
979 }; 980 };
980 }; 981 };
981 982
982 rng: rng@793000 { 983 rng: rng@793000 {
983 compatible = "qcom,prn 984 compatible = "qcom,prng-ee";
984 reg = <0 0x00793000 0 985 reg = <0 0x00793000 0 0x1000>;
985 clocks = <&gcc GCC_PRN 986 clocks = <&gcc GCC_PRNG_AHB_CLK>;
986 clock-names = "core"; 987 clock-names = "core";
987 }; 988 };
988 989
989 gpi_dma2: dma-controller@80000 990 gpi_dma2: dma-controller@800000 {
990 compatible = "qcom,sm8 991 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma";
991 reg = <0 0x00800000 0 992 reg = <0 0x00800000 0 0x70000>;
992 interrupts = <GIC_SPI 993 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
993 <GIC_SPI 994 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
994 <GIC_SPI 995 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
995 <GIC_SPI 996 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
996 <GIC_SPI 997 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
997 <GIC_SPI 998 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
998 <GIC_SPI 999 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
999 <GIC_SPI 1000 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
1000 <GIC_SPI 1001 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
1001 <GIC_SPI 1002 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>;
1002 dma-channels = <10>; 1003 dma-channels = <10>;
1003 dma-channel-mask = <0 1004 dma-channel-mask = <0x3f>;
1004 iommus = <&apps_smmu 1005 iommus = <&apps_smmu 0x76 0x0>;
1005 #dma-cells = <3>; 1006 #dma-cells = <3>;
1006 status = "disabled"; 1007 status = "disabled";
1007 }; 1008 };
1008 1009
1009 qupv3_id_2: geniqup@8c0000 { 1010 qupv3_id_2: geniqup@8c0000 {
1010 compatible = "qcom,ge 1011 compatible = "qcom,geni-se-qup";
1011 reg = <0x0 0x008c0000 1012 reg = <0x0 0x008c0000 0x0 0x6000>;
1012 clock-names = "m-ahb" 1013 clock-names = "m-ahb", "s-ahb";
1013 clocks = <&gcc GCC_QU 1014 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
1014 <&gcc GCC_QU 1015 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
1015 #address-cells = <2>; 1016 #address-cells = <2>;
1016 #size-cells = <2>; 1017 #size-cells = <2>;
1017 iommus = <&apps_smmu 1018 iommus = <&apps_smmu 0x63 0x0>;
1018 ranges; 1019 ranges;
1019 status = "disabled"; 1020 status = "disabled";
1020 1021
1021 i2c14: i2c@880000 { 1022 i2c14: i2c@880000 {
1022 compatible = 1023 compatible = "qcom,geni-i2c";
1023 reg = <0 0x00 1024 reg = <0 0x00880000 0 0x4000>;
1024 clock-names = 1025 clock-names = "se";
1025 clocks = <&gc 1026 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1026 pinctrl-names 1027 pinctrl-names = "default";
1027 pinctrl-0 = < 1028 pinctrl-0 = <&qup_i2c14_default>;
1028 interrupts = 1029 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1029 dmas = <&gpi_ 1030 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
1030 <&gpi_ 1031 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
1031 dma-names = " 1032 dma-names = "tx", "rx";
1032 power-domains 1033 power-domains = <&rpmhpd SM8250_CX>;
1033 interconnects 1034 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1034 1035 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1035 1036 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1036 interconnect- 1037 interconnect-names = "qup-core",
1037 1038 "qup-config",
1038 1039 "qup-memory";
1039 #address-cell 1040 #address-cells = <1>;
1040 #size-cells = 1041 #size-cells = <0>;
1041 status = "dis 1042 status = "disabled";
1042 }; 1043 };
1043 1044
1044 spi14: spi@880000 { 1045 spi14: spi@880000 {
1045 compatible = 1046 compatible = "qcom,geni-spi";
1046 reg = <0 0x00 1047 reg = <0 0x00880000 0 0x4000>;
1047 clock-names = 1048 clock-names = "se";
1048 clocks = <&gc 1049 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1049 interrupts = 1050 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1050 dmas = <&gpi_ 1051 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
1051 <&gpi_ 1052 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
1052 dma-names = " 1053 dma-names = "tx", "rx";
1053 power-domains 1054 power-domains = <&rpmhpd RPMHPD_CX>;
1054 operating-poi 1055 operating-points-v2 = <&qup_opp_table>;
1055 interconnects 1056 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1056 1057 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1057 1058 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1058 interconnect- 1059 interconnect-names = "qup-core",
1059 1060 "qup-config",
1060 1061 "qup-memory";
1061 #address-cell 1062 #address-cells = <1>;
1062 #size-cells = 1063 #size-cells = <0>;
1063 status = "dis 1064 status = "disabled";
1064 }; 1065 };
1065 1066
1066 i2c15: i2c@884000 { 1067 i2c15: i2c@884000 {
1067 compatible = 1068 compatible = "qcom,geni-i2c";
1068 reg = <0 0x00 1069 reg = <0 0x00884000 0 0x4000>;
1069 clock-names = 1070 clock-names = "se";
1070 clocks = <&gc 1071 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1071 pinctrl-names 1072 pinctrl-names = "default";
1072 pinctrl-0 = < 1073 pinctrl-0 = <&qup_i2c15_default>;
1073 interrupts = 1074 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1074 dmas = <&gpi_ 1075 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
1075 <&gpi_ 1076 <&gpi_dma2 1 1 QCOM_GPI_I2C>;
1076 dma-names = " 1077 dma-names = "tx", "rx";
1077 power-domains 1078 power-domains = <&rpmhpd SM8250_CX>;
1078 interconnects 1079 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1079 1080 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1080 1081 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1081 interconnect- 1082 interconnect-names = "qup-core",
1082 1083 "qup-config",
1083 1084 "qup-memory";
1084 #address-cell 1085 #address-cells = <1>;
1085 #size-cells = 1086 #size-cells = <0>;
1086 status = "dis 1087 status = "disabled";
1087 }; 1088 };
1088 1089
1089 spi15: spi@884000 { 1090 spi15: spi@884000 {
1090 compatible = 1091 compatible = "qcom,geni-spi";
1091 reg = <0 0x00 1092 reg = <0 0x00884000 0 0x4000>;
1092 clock-names = 1093 clock-names = "se";
1093 clocks = <&gc 1094 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1094 interrupts = 1095 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1095 dmas = <&gpi_ 1096 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
1096 <&gpi_ 1097 <&gpi_dma2 1 1 QCOM_GPI_SPI>;
1097 dma-names = " 1098 dma-names = "tx", "rx";
1098 power-domains 1099 power-domains = <&rpmhpd RPMHPD_CX>;
1099 operating-poi 1100 operating-points-v2 = <&qup_opp_table>;
1100 interconnects 1101 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1101 1102 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1102 1103 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1103 interconnect- 1104 interconnect-names = "qup-core",
1104 1105 "qup-config",
1105 1106 "qup-memory";
1106 #address-cell 1107 #address-cells = <1>;
1107 #size-cells = 1108 #size-cells = <0>;
1108 status = "dis 1109 status = "disabled";
1109 }; 1110 };
1110 1111
1111 i2c16: i2c@888000 { 1112 i2c16: i2c@888000 {
1112 compatible = 1113 compatible = "qcom,geni-i2c";
1113 reg = <0 0x00 1114 reg = <0 0x00888000 0 0x4000>;
1114 clock-names = 1115 clock-names = "se";
1115 clocks = <&gc 1116 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1116 pinctrl-names 1117 pinctrl-names = "default";
1117 pinctrl-0 = < 1118 pinctrl-0 = <&qup_i2c16_default>;
1118 interrupts = 1119 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1119 dmas = <&gpi_ 1120 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
1120 <&gpi_ 1121 <&gpi_dma2 1 2 QCOM_GPI_I2C>;
1121 dma-names = " 1122 dma-names = "tx", "rx";
1122 power-domains 1123 power-domains = <&rpmhpd SM8250_CX>;
1123 interconnects 1124 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1124 1125 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1125 1126 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1126 interconnect- 1127 interconnect-names = "qup-core",
1127 1128 "qup-config",
1128 1129 "qup-memory";
1129 #address-cell 1130 #address-cells = <1>;
1130 #size-cells = 1131 #size-cells = <0>;
1131 status = "dis 1132 status = "disabled";
1132 }; 1133 };
1133 1134
1134 spi16: spi@888000 { 1135 spi16: spi@888000 {
1135 compatible = 1136 compatible = "qcom,geni-spi";
1136 reg = <0 0x00 1137 reg = <0 0x00888000 0 0x4000>;
1137 clock-names = 1138 clock-names = "se";
1138 clocks = <&gc 1139 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1139 interrupts = 1140 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1140 dmas = <&gpi_ 1141 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
1141 <&gpi_ 1142 <&gpi_dma2 1 2 QCOM_GPI_SPI>;
1142 dma-names = " 1143 dma-names = "tx", "rx";
1143 power-domains 1144 power-domains = <&rpmhpd RPMHPD_CX>;
1144 operating-poi 1145 operating-points-v2 = <&qup_opp_table>;
1145 interconnects 1146 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1146 1147 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1147 1148 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1148 interconnect- 1149 interconnect-names = "qup-core",
1149 1150 "qup-config",
1150 1151 "qup-memory";
1151 #address-cell 1152 #address-cells = <1>;
1152 #size-cells = 1153 #size-cells = <0>;
1153 status = "dis 1154 status = "disabled";
1154 }; 1155 };
1155 1156
1156 i2c17: i2c@88c000 { 1157 i2c17: i2c@88c000 {
1157 compatible = 1158 compatible = "qcom,geni-i2c";
1158 reg = <0 0x00 1159 reg = <0 0x0088c000 0 0x4000>;
1159 clock-names = 1160 clock-names = "se";
1160 clocks = <&gc 1161 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1161 pinctrl-names 1162 pinctrl-names = "default";
1162 pinctrl-0 = < 1163 pinctrl-0 = <&qup_i2c17_default>;
1163 interrupts = 1164 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1164 dmas = <&gpi_ 1165 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
1165 <&gpi_ 1166 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
1166 dma-names = " 1167 dma-names = "tx", "rx";
1167 power-domains 1168 power-domains = <&rpmhpd SM8250_CX>;
1168 interconnects 1169 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1169 1170 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1170 1171 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1171 interconnect- 1172 interconnect-names = "qup-core",
1172 1173 "qup-config",
1173 1174 "qup-memory";
1174 #address-cell 1175 #address-cells = <1>;
1175 #size-cells = 1176 #size-cells = <0>;
1176 status = "dis 1177 status = "disabled";
1177 }; 1178 };
1178 1179
1179 spi17: spi@88c000 { 1180 spi17: spi@88c000 {
1180 compatible = 1181 compatible = "qcom,geni-spi";
1181 reg = <0 0x00 1182 reg = <0 0x0088c000 0 0x4000>;
1182 clock-names = 1183 clock-names = "se";
1183 clocks = <&gc 1184 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1184 interrupts = 1185 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1185 dmas = <&gpi_ 1186 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
1186 <&gpi_ 1187 <&gpi_dma2 1 3 QCOM_GPI_SPI>;
1187 dma-names = " 1188 dma-names = "tx", "rx";
1188 power-domains 1189 power-domains = <&rpmhpd RPMHPD_CX>;
1189 operating-poi 1190 operating-points-v2 = <&qup_opp_table>;
1190 interconnects 1191 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1191 1192 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1192 1193 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1193 interconnect- 1194 interconnect-names = "qup-core",
1194 1195 "qup-config",
1195 1196 "qup-memory";
1196 #address-cell 1197 #address-cells = <1>;
1197 #size-cells = 1198 #size-cells = <0>;
1198 status = "dis 1199 status = "disabled";
1199 }; 1200 };
1200 1201
1201 uart17: serial@88c000 1202 uart17: serial@88c000 {
1202 compatible = 1203 compatible = "qcom,geni-uart";
1203 reg = <0 0x00 1204 reg = <0 0x0088c000 0 0x4000>;
1204 clock-names = 1205 clock-names = "se";
1205 clocks = <&gc 1206 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1206 pinctrl-names 1207 pinctrl-names = "default";
1207 pinctrl-0 = < 1208 pinctrl-0 = <&qup_uart17_default>;
1208 interrupts = 1209 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1209 power-domains 1210 power-domains = <&rpmhpd RPMHPD_CX>;
1210 operating-poi 1211 operating-points-v2 = <&qup_opp_table>;
1211 interconnects 1212 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1212 1213 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1213 interconnect- 1214 interconnect-names = "qup-core",
1214 1215 "qup-config";
1215 status = "dis 1216 status = "disabled";
1216 }; 1217 };
1217 1218
1218 i2c18: i2c@890000 { 1219 i2c18: i2c@890000 {
1219 compatible = 1220 compatible = "qcom,geni-i2c";
1220 reg = <0 0x00 1221 reg = <0 0x00890000 0 0x4000>;
1221 clock-names = 1222 clock-names = "se";
1222 clocks = <&gc 1223 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1223 pinctrl-names 1224 pinctrl-names = "default";
1224 pinctrl-0 = < 1225 pinctrl-0 = <&qup_i2c18_default>;
1225 interrupts = 1226 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1226 dmas = <&gpi_ 1227 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1227 <&gpi_ 1228 <&gpi_dma2 1 4 QCOM_GPI_I2C>;
1228 dma-names = " 1229 dma-names = "tx", "rx";
1229 power-domains 1230 power-domains = <&rpmhpd SM8250_CX>;
1230 interconnects 1231 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1231 1232 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1232 1233 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1233 interconnect- 1234 interconnect-names = "qup-core",
1234 1235 "qup-config",
1235 1236 "qup-memory";
1236 #address-cell 1237 #address-cells = <1>;
1237 #size-cells = 1238 #size-cells = <0>;
1238 status = "dis 1239 status = "disabled";
1239 }; 1240 };
1240 1241
1241 spi18: spi@890000 { 1242 spi18: spi@890000 {
1242 compatible = 1243 compatible = "qcom,geni-spi";
1243 reg = <0 0x00 1244 reg = <0 0x00890000 0 0x4000>;
1244 clock-names = 1245 clock-names = "se";
1245 clocks = <&gc 1246 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1246 interrupts = 1247 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1247 dmas = <&gpi_ 1248 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
1248 <&gpi_ 1249 <&gpi_dma2 1 4 QCOM_GPI_SPI>;
1249 dma-names = " 1250 dma-names = "tx", "rx";
1250 power-domains 1251 power-domains = <&rpmhpd RPMHPD_CX>;
1251 operating-poi 1252 operating-points-v2 = <&qup_opp_table>;
1252 interconnects 1253 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1253 1254 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1254 1255 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1255 interconnect- 1256 interconnect-names = "qup-core",
1256 1257 "qup-config",
1257 1258 "qup-memory";
1258 #address-cell 1259 #address-cells = <1>;
1259 #size-cells = 1260 #size-cells = <0>;
1260 status = "dis 1261 status = "disabled";
1261 }; 1262 };
1262 1263
1263 uart18: serial@890000 1264 uart18: serial@890000 {
1264 compatible = 1265 compatible = "qcom,geni-uart";
1265 reg = <0 0x00 1266 reg = <0 0x00890000 0 0x4000>;
1266 clock-names = 1267 clock-names = "se";
1267 clocks = <&gc 1268 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1268 pinctrl-names 1269 pinctrl-names = "default";
1269 pinctrl-0 = < 1270 pinctrl-0 = <&qup_uart18_default>;
1270 interrupts = 1271 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1271 power-domains 1272 power-domains = <&rpmhpd RPMHPD_CX>;
1272 operating-poi 1273 operating-points-v2 = <&qup_opp_table>;
1273 interconnects 1274 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1274 1275 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1275 interconnect- 1276 interconnect-names = "qup-core",
1276 1277 "qup-config";
1277 status = "dis 1278 status = "disabled";
1278 }; 1279 };
1279 1280
1280 i2c19: i2c@894000 { 1281 i2c19: i2c@894000 {
1281 compatible = 1282 compatible = "qcom,geni-i2c";
1282 reg = <0 0x00 1283 reg = <0 0x00894000 0 0x4000>;
1283 clock-names = 1284 clock-names = "se";
1284 clocks = <&gc 1285 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1285 pinctrl-names 1286 pinctrl-names = "default";
1286 pinctrl-0 = < 1287 pinctrl-0 = <&qup_i2c19_default>;
1287 interrupts = 1288 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1288 dmas = <&gpi_ 1289 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1289 <&gpi_ 1290 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1290 dma-names = " 1291 dma-names = "tx", "rx";
1291 power-domains 1292 power-domains = <&rpmhpd SM8250_CX>;
1292 interconnects 1293 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1293 1294 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1294 1295 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1295 interconnect- 1296 interconnect-names = "qup-core",
1296 1297 "qup-config",
1297 1298 "qup-memory";
1298 #address-cell 1299 #address-cells = <1>;
1299 #size-cells = 1300 #size-cells = <0>;
1300 status = "dis 1301 status = "disabled";
1301 }; 1302 };
1302 1303
1303 spi19: spi@894000 { 1304 spi19: spi@894000 {
1304 compatible = 1305 compatible = "qcom,geni-spi";
1305 reg = <0 0x00 1306 reg = <0 0x00894000 0 0x4000>;
1306 clock-names = 1307 clock-names = "se";
1307 clocks = <&gc 1308 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1308 interrupts = 1309 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1309 dmas = <&gpi_ 1310 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1310 <&gpi_ 1311 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1311 dma-names = " 1312 dma-names = "tx", "rx";
1312 power-domains 1313 power-domains = <&rpmhpd RPMHPD_CX>;
1313 operating-poi 1314 operating-points-v2 = <&qup_opp_table>;
1314 interconnects 1315 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1315 1316 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1316 1317 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1317 interconnect- 1318 interconnect-names = "qup-core",
1318 1319 "qup-config",
1319 1320 "qup-memory";
1320 #address-cell 1321 #address-cells = <1>;
1321 #size-cells = 1322 #size-cells = <0>;
1322 status = "dis 1323 status = "disabled";
1323 }; 1324 };
1324 }; 1325 };
1325 1326
1326 gpi_dma0: dma-controller@9000 1327 gpi_dma0: dma-controller@900000 {
1327 compatible = "qcom,sm 1328 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma";
1328 reg = <0 0x00900000 0 1329 reg = <0 0x00900000 0 0x70000>;
1329 interrupts = <GIC_SPI 1330 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
1330 <GIC_SPI 1331 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
1331 <GIC_SPI 1332 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
1332 <GIC_SPI 1333 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
1333 <GIC_SPI 1334 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
1334 <GIC_SPI 1335 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
1335 <GIC_SPI 1336 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
1336 <GIC_SPI 1337 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
1337 <GIC_SPI 1338 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
1338 <GIC_SPI 1339 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
1339 <GIC_SPI 1340 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
1340 <GIC_SPI 1341 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
1341 <GIC_SPI 1342 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
1342 dma-channels = <15>; 1343 dma-channels = <15>;
1343 dma-channel-mask = <0 1344 dma-channel-mask = <0x7ff>;
1344 iommus = <&apps_smmu 1345 iommus = <&apps_smmu 0x5b6 0x0>;
1345 #dma-cells = <3>; 1346 #dma-cells = <3>;
1346 status = "disabled"; 1347 status = "disabled";
1347 }; 1348 };
1348 1349
1349 qupv3_id_0: geniqup@9c0000 { 1350 qupv3_id_0: geniqup@9c0000 {
1350 compatible = "qcom,ge 1351 compatible = "qcom,geni-se-qup";
1351 reg = <0x0 0x009c0000 1352 reg = <0x0 0x009c0000 0x0 0x6000>;
1352 clock-names = "m-ahb" 1353 clock-names = "m-ahb", "s-ahb";
1353 clocks = <&gcc GCC_QU 1354 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1354 <&gcc GCC_QU 1355 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1355 #address-cells = <2>; 1356 #address-cells = <2>;
1356 #size-cells = <2>; 1357 #size-cells = <2>;
1357 iommus = <&apps_smmu 1358 iommus = <&apps_smmu 0x5a3 0x0>;
1358 ranges; 1359 ranges;
1359 status = "disabled"; 1360 status = "disabled";
1360 1361
1361 i2c0: i2c@980000 { 1362 i2c0: i2c@980000 {
1362 compatible = 1363 compatible = "qcom,geni-i2c";
1363 reg = <0 0x00 1364 reg = <0 0x00980000 0 0x4000>;
1364 clock-names = 1365 clock-names = "se";
1365 clocks = <&gc 1366 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1366 pinctrl-names 1367 pinctrl-names = "default";
1367 pinctrl-0 = < 1368 pinctrl-0 = <&qup_i2c0_default>;
1368 interrupts = 1369 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1369 dmas = <&gpi_ 1370 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1370 <&gpi_ 1371 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1371 dma-names = " 1372 dma-names = "tx", "rx";
1372 power-domains 1373 power-domains = <&rpmhpd SM8250_CX>;
1373 interconnects 1374 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1374 1375 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1375 1376 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1376 interconnect- 1377 interconnect-names = "qup-core",
1377 1378 "qup-config",
1378 1379 "qup-memory";
1379 #address-cell 1380 #address-cells = <1>;
1380 #size-cells = 1381 #size-cells = <0>;
1381 status = "dis 1382 status = "disabled";
1382 }; 1383 };
1383 1384
1384 spi0: spi@980000 { 1385 spi0: spi@980000 {
1385 compatible = 1386 compatible = "qcom,geni-spi";
1386 reg = <0 0x00 1387 reg = <0 0x00980000 0 0x4000>;
1387 clock-names = 1388 clock-names = "se";
1388 clocks = <&gc 1389 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1389 interrupts = 1390 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1390 dmas = <&gpi_ 1391 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1391 <&gpi_ 1392 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1392 dma-names = " 1393 dma-names = "tx", "rx";
1393 power-domains 1394 power-domains = <&rpmhpd RPMHPD_CX>;
1394 operating-poi 1395 operating-points-v2 = <&qup_opp_table>;
1395 interconnects 1396 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1396 1397 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1397 1398 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1398 interconnect- 1399 interconnect-names = "qup-core",
1399 1400 "qup-config",
1400 1401 "qup-memory";
1401 #address-cell 1402 #address-cells = <1>;
1402 #size-cells = 1403 #size-cells = <0>;
1403 status = "dis 1404 status = "disabled";
1404 }; 1405 };
1405 1406
1406 i2c1: i2c@984000 { 1407 i2c1: i2c@984000 {
1407 compatible = 1408 compatible = "qcom,geni-i2c";
1408 reg = <0 0x00 1409 reg = <0 0x00984000 0 0x4000>;
1409 clock-names = 1410 clock-names = "se";
1410 clocks = <&gc 1411 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1411 pinctrl-names 1412 pinctrl-names = "default";
1412 pinctrl-0 = < 1413 pinctrl-0 = <&qup_i2c1_default>;
1413 interrupts = 1414 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1414 dmas = <&gpi_ 1415 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1415 <&gpi_ 1416 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1416 dma-names = " 1417 dma-names = "tx", "rx";
1417 power-domains 1418 power-domains = <&rpmhpd SM8250_CX>;
1418 interconnects 1419 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1419 1420 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1420 1421 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1421 interconnect- 1422 interconnect-names = "qup-core",
1422 1423 "qup-config",
1423 1424 "qup-memory";
1424 #address-cell 1425 #address-cells = <1>;
1425 #size-cells = 1426 #size-cells = <0>;
1426 status = "dis 1427 status = "disabled";
1427 }; 1428 };
1428 1429
1429 spi1: spi@984000 { 1430 spi1: spi@984000 {
1430 compatible = 1431 compatible = "qcom,geni-spi";
1431 reg = <0 0x00 1432 reg = <0 0x00984000 0 0x4000>;
1432 clock-names = 1433 clock-names = "se";
1433 clocks = <&gc 1434 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1434 interrupts = 1435 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1435 dmas = <&gpi_ 1436 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1436 <&gpi_ 1437 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1437 dma-names = " 1438 dma-names = "tx", "rx";
1438 power-domains 1439 power-domains = <&rpmhpd RPMHPD_CX>;
1439 operating-poi 1440 operating-points-v2 = <&qup_opp_table>;
1440 interconnects 1441 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1441 1442 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1442 1443 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1443 interconnect- 1444 interconnect-names = "qup-core",
1444 1445 "qup-config",
1445 1446 "qup-memory";
1446 #address-cell 1447 #address-cells = <1>;
1447 #size-cells = 1448 #size-cells = <0>;
1448 status = "dis 1449 status = "disabled";
1449 }; 1450 };
1450 1451
1451 i2c2: i2c@988000 { 1452 i2c2: i2c@988000 {
1452 compatible = 1453 compatible = "qcom,geni-i2c";
1453 reg = <0 0x00 1454 reg = <0 0x00988000 0 0x4000>;
1454 clock-names = 1455 clock-names = "se";
1455 clocks = <&gc 1456 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1456 pinctrl-names 1457 pinctrl-names = "default";
1457 pinctrl-0 = < 1458 pinctrl-0 = <&qup_i2c2_default>;
1458 interrupts = 1459 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1459 dmas = <&gpi_ 1460 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1460 <&gpi_ 1461 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1461 dma-names = " 1462 dma-names = "tx", "rx";
1462 power-domains 1463 power-domains = <&rpmhpd SM8250_CX>;
1463 interconnects 1464 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1464 1465 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1465 1466 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1466 interconnect- 1467 interconnect-names = "qup-core",
1467 1468 "qup-config",
1468 1469 "qup-memory";
1469 #address-cell 1470 #address-cells = <1>;
1470 #size-cells = 1471 #size-cells = <0>;
1471 status = "dis 1472 status = "disabled";
1472 }; 1473 };
1473 1474
1474 spi2: spi@988000 { 1475 spi2: spi@988000 {
1475 compatible = 1476 compatible = "qcom,geni-spi";
1476 reg = <0 0x00 1477 reg = <0 0x00988000 0 0x4000>;
1477 clock-names = 1478 clock-names = "se";
1478 clocks = <&gc 1479 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1479 interrupts = 1480 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1480 dmas = <&gpi_ 1481 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1481 <&gpi_ 1482 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1482 dma-names = " 1483 dma-names = "tx", "rx";
1483 power-domains 1484 power-domains = <&rpmhpd RPMHPD_CX>;
1484 operating-poi 1485 operating-points-v2 = <&qup_opp_table>;
1485 interconnects 1486 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1486 1487 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1487 1488 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1488 interconnect- 1489 interconnect-names = "qup-core",
1489 1490 "qup-config",
1490 1491 "qup-memory";
1491 #address-cell 1492 #address-cells = <1>;
1492 #size-cells = 1493 #size-cells = <0>;
1493 status = "dis 1494 status = "disabled";
1494 }; 1495 };
1495 1496
1496 uart2: serial@988000 1497 uart2: serial@988000 {
1497 compatible = 1498 compatible = "qcom,geni-debug-uart";
1498 reg = <0 0x00 1499 reg = <0 0x00988000 0 0x4000>;
1499 clock-names = 1500 clock-names = "se";
1500 clocks = <&gc 1501 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1501 pinctrl-names 1502 pinctrl-names = "default";
1502 pinctrl-0 = < 1503 pinctrl-0 = <&qup_uart2_default>;
1503 interrupts = 1504 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1504 power-domains 1505 power-domains = <&rpmhpd RPMHPD_CX>;
1505 operating-poi 1506 operating-points-v2 = <&qup_opp_table>;
1506 interconnects 1507 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1507 1508 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1508 interconnect- 1509 interconnect-names = "qup-core",
1509 1510 "qup-config";
1510 status = "dis 1511 status = "disabled";
1511 }; 1512 };
1512 1513
1513 i2c3: i2c@98c000 { 1514 i2c3: i2c@98c000 {
1514 compatible = 1515 compatible = "qcom,geni-i2c";
1515 reg = <0 0x00 1516 reg = <0 0x0098c000 0 0x4000>;
1516 clock-names = 1517 clock-names = "se";
1517 clocks = <&gc 1518 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1518 pinctrl-names 1519 pinctrl-names = "default";
1519 pinctrl-0 = < 1520 pinctrl-0 = <&qup_i2c3_default>;
1520 interrupts = 1521 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1521 dmas = <&gpi_ 1522 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1522 <&gpi_ 1523 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1523 dma-names = " 1524 dma-names = "tx", "rx";
1524 power-domains 1525 power-domains = <&rpmhpd SM8250_CX>;
1525 interconnects 1526 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1526 1527 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1527 1528 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1528 interconnect- 1529 interconnect-names = "qup-core",
1529 1530 "qup-config",
1530 1531 "qup-memory";
1531 #address-cell 1532 #address-cells = <1>;
1532 #size-cells = 1533 #size-cells = <0>;
1533 status = "dis 1534 status = "disabled";
1534 }; 1535 };
1535 1536
1536 spi3: spi@98c000 { 1537 spi3: spi@98c000 {
1537 compatible = 1538 compatible = "qcom,geni-spi";
1538 reg = <0 0x00 1539 reg = <0 0x0098c000 0 0x4000>;
1539 clock-names = 1540 clock-names = "se";
1540 clocks = <&gc 1541 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1541 interrupts = 1542 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1542 dmas = <&gpi_ 1543 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1543 <&gpi_ 1544 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1544 dma-names = " 1545 dma-names = "tx", "rx";
1545 power-domains 1546 power-domains = <&rpmhpd RPMHPD_CX>;
1546 operating-poi 1547 operating-points-v2 = <&qup_opp_table>;
1547 interconnects 1548 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1548 1549 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1549 1550 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1550 interconnect- 1551 interconnect-names = "qup-core",
1551 1552 "qup-config",
1552 1553 "qup-memory";
1553 #address-cell 1554 #address-cells = <1>;
1554 #size-cells = 1555 #size-cells = <0>;
1555 status = "dis 1556 status = "disabled";
1556 }; 1557 };
1557 1558
1558 i2c4: i2c@990000 { 1559 i2c4: i2c@990000 {
1559 compatible = 1560 compatible = "qcom,geni-i2c";
1560 reg = <0 0x00 1561 reg = <0 0x00990000 0 0x4000>;
1561 clock-names = 1562 clock-names = "se";
1562 clocks = <&gc 1563 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1563 pinctrl-names 1564 pinctrl-names = "default";
1564 pinctrl-0 = < 1565 pinctrl-0 = <&qup_i2c4_default>;
1565 interrupts = 1566 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1566 dmas = <&gpi_ 1567 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1567 <&gpi_ 1568 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1568 dma-names = " 1569 dma-names = "tx", "rx";
1569 power-domains 1570 power-domains = <&rpmhpd SM8250_CX>;
1570 interconnects 1571 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1571 1572 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1572 1573 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1573 interconnect- 1574 interconnect-names = "qup-core",
1574 1575 "qup-config",
1575 1576 "qup-memory";
1576 #address-cell 1577 #address-cells = <1>;
1577 #size-cells = 1578 #size-cells = <0>;
1578 status = "dis 1579 status = "disabled";
1579 }; 1580 };
1580 1581
1581 spi4: spi@990000 { 1582 spi4: spi@990000 {
1582 compatible = 1583 compatible = "qcom,geni-spi";
1583 reg = <0 0x00 1584 reg = <0 0x00990000 0 0x4000>;
1584 clock-names = 1585 clock-names = "se";
1585 clocks = <&gc 1586 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1586 interrupts = 1587 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1587 dmas = <&gpi_ 1588 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1588 <&gpi_ 1589 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1589 dma-names = " 1590 dma-names = "tx", "rx";
1590 power-domains 1591 power-domains = <&rpmhpd RPMHPD_CX>;
1591 operating-poi 1592 operating-points-v2 = <&qup_opp_table>;
1592 interconnects 1593 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1593 1594 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1594 1595 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1595 interconnect- 1596 interconnect-names = "qup-core",
1596 1597 "qup-config",
1597 1598 "qup-memory";
1598 #address-cell 1599 #address-cells = <1>;
1599 #size-cells = 1600 #size-cells = <0>;
1600 status = "dis 1601 status = "disabled";
1601 }; 1602 };
1602 1603
1603 i2c5: i2c@994000 { 1604 i2c5: i2c@994000 {
1604 compatible = 1605 compatible = "qcom,geni-i2c";
1605 reg = <0 0x00 1606 reg = <0 0x00994000 0 0x4000>;
1606 clock-names = 1607 clock-names = "se";
1607 clocks = <&gc 1608 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1608 pinctrl-names 1609 pinctrl-names = "default";
1609 pinctrl-0 = < 1610 pinctrl-0 = <&qup_i2c5_default>;
1610 interrupts = 1611 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1611 dmas = <&gpi_ 1612 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1612 <&gpi_ 1613 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1613 dma-names = " 1614 dma-names = "tx", "rx";
1614 power-domains 1615 power-domains = <&rpmhpd SM8250_CX>;
1615 interconnects 1616 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1616 1617 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1617 1618 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1618 interconnect- 1619 interconnect-names = "qup-core",
1619 1620 "qup-config",
1620 1621 "qup-memory";
1621 #address-cell 1622 #address-cells = <1>;
1622 #size-cells = 1623 #size-cells = <0>;
1623 status = "dis 1624 status = "disabled";
1624 }; 1625 };
1625 1626
1626 spi5: spi@994000 { 1627 spi5: spi@994000 {
1627 compatible = 1628 compatible = "qcom,geni-spi";
1628 reg = <0 0x00 1629 reg = <0 0x00994000 0 0x4000>;
1629 clock-names = 1630 clock-names = "se";
1630 clocks = <&gc 1631 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1631 interrupts = 1632 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1632 dmas = <&gpi_ 1633 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1633 <&gpi_ 1634 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1634 dma-names = " 1635 dma-names = "tx", "rx";
1635 power-domains 1636 power-domains = <&rpmhpd RPMHPD_CX>;
1636 operating-poi 1637 operating-points-v2 = <&qup_opp_table>;
1637 interconnects 1638 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1638 1639 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1639 1640 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1640 interconnect- 1641 interconnect-names = "qup-core",
1641 1642 "qup-config",
1642 1643 "qup-memory";
1643 #address-cell 1644 #address-cells = <1>;
1644 #size-cells = 1645 #size-cells = <0>;
1645 status = "dis 1646 status = "disabled";
1646 }; 1647 };
1647 1648
1648 i2c6: i2c@998000 { 1649 i2c6: i2c@998000 {
1649 compatible = 1650 compatible = "qcom,geni-i2c";
1650 reg = <0 0x00 1651 reg = <0 0x00998000 0 0x4000>;
1651 clock-names = 1652 clock-names = "se";
1652 clocks = <&gc 1653 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1653 pinctrl-names 1654 pinctrl-names = "default";
1654 pinctrl-0 = < 1655 pinctrl-0 = <&qup_i2c6_default>;
1655 interrupts = 1656 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1656 dmas = <&gpi_ 1657 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1657 <&gpi_ 1658 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1658 dma-names = " 1659 dma-names = "tx", "rx";
1659 power-domains 1660 power-domains = <&rpmhpd SM8250_CX>;
1660 interconnects 1661 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1661 1662 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1662 1663 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1663 interconnect- 1664 interconnect-names = "qup-core",
1664 1665 "qup-config",
1665 1666 "qup-memory";
1666 #address-cell 1667 #address-cells = <1>;
1667 #size-cells = 1668 #size-cells = <0>;
1668 status = "dis 1669 status = "disabled";
1669 }; 1670 };
1670 1671
1671 spi6: spi@998000 { 1672 spi6: spi@998000 {
1672 compatible = 1673 compatible = "qcom,geni-spi";
1673 reg = <0 0x00 1674 reg = <0 0x00998000 0 0x4000>;
1674 clock-names = 1675 clock-names = "se";
1675 clocks = <&gc 1676 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1676 interrupts = 1677 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1677 dmas = <&gpi_ 1678 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1678 <&gpi_ 1679 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1679 dma-names = " 1680 dma-names = "tx", "rx";
1680 power-domains 1681 power-domains = <&rpmhpd RPMHPD_CX>;
1681 operating-poi 1682 operating-points-v2 = <&qup_opp_table>;
1682 interconnects 1683 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1683 1684 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1684 1685 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1685 interconnect- 1686 interconnect-names = "qup-core",
1686 1687 "qup-config",
1687 1688 "qup-memory";
1688 #address-cell 1689 #address-cells = <1>;
1689 #size-cells = 1690 #size-cells = <0>;
1690 status = "dis 1691 status = "disabled";
1691 }; 1692 };
1692 1693
1693 uart6: serial@998000 1694 uart6: serial@998000 {
1694 compatible = 1695 compatible = "qcom,geni-uart";
1695 reg = <0 0x00 1696 reg = <0 0x00998000 0 0x4000>;
1696 clock-names = 1697 clock-names = "se";
1697 clocks = <&gc 1698 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1698 pinctrl-names 1699 pinctrl-names = "default";
1699 pinctrl-0 = < 1700 pinctrl-0 = <&qup_uart6_default>;
1700 interrupts = 1701 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1701 power-domains 1702 power-domains = <&rpmhpd RPMHPD_CX>;
1702 operating-poi 1703 operating-points-v2 = <&qup_opp_table>;
1703 interconnects 1704 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1704 1705 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1705 interconnect- 1706 interconnect-names = "qup-core",
1706 1707 "qup-config";
1707 status = "dis 1708 status = "disabled";
1708 }; 1709 };
1709 1710
1710 i2c7: i2c@99c000 { 1711 i2c7: i2c@99c000 {
1711 compatible = 1712 compatible = "qcom,geni-i2c";
1712 reg = <0 0x00 1713 reg = <0 0x0099c000 0 0x4000>;
1713 clock-names = 1714 clock-names = "se";
1714 clocks = <&gc 1715 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1715 pinctrl-names 1716 pinctrl-names = "default";
1716 pinctrl-0 = < 1717 pinctrl-0 = <&qup_i2c7_default>;
1717 interrupts = 1718 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1718 dmas = <&gpi_ 1719 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1719 <&gpi_ 1720 <&gpi_dma0 1 7 QCOM_GPI_I2C>;
1720 dma-names = " 1721 dma-names = "tx", "rx";
1721 power-domains 1722 power-domains = <&rpmhpd SM8250_CX>;
1722 interconnects 1723 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1723 1724 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1724 1725 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1725 interconnect- 1726 interconnect-names = "qup-core",
1726 1727 "qup-config",
1727 1728 "qup-memory";
1728 #address-cell 1729 #address-cells = <1>;
1729 #size-cells = 1730 #size-cells = <0>;
1730 status = "dis 1731 status = "disabled";
1731 }; 1732 };
1732 1733
1733 spi7: spi@99c000 { 1734 spi7: spi@99c000 {
1734 compatible = 1735 compatible = "qcom,geni-spi";
1735 reg = <0 0x00 1736 reg = <0 0x0099c000 0 0x4000>;
1736 clock-names = 1737 clock-names = "se";
1737 clocks = <&gc 1738 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1738 interrupts = 1739 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1739 dmas = <&gpi_ 1740 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1740 <&gpi_ 1741 <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1741 dma-names = " 1742 dma-names = "tx", "rx";
1742 power-domains 1743 power-domains = <&rpmhpd RPMHPD_CX>;
1743 operating-poi 1744 operating-points-v2 = <&qup_opp_table>;
1744 interconnects 1745 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1745 1746 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1746 1747 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1747 interconnect- 1748 interconnect-names = "qup-core",
1748 1749 "qup-config",
1749 1750 "qup-memory";
1750 #address-cell 1751 #address-cells = <1>;
1751 #size-cells = 1752 #size-cells = <0>;
1752 status = "dis 1753 status = "disabled";
1753 }; 1754 };
1754 }; 1755 };
1755 1756
1756 gpi_dma1: dma-controller@a000 1757 gpi_dma1: dma-controller@a00000 {
1757 compatible = "qcom,sm 1758 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma";
1758 reg = <0 0x00a00000 0 1759 reg = <0 0x00a00000 0 0x70000>;
1759 interrupts = <GIC_SPI 1760 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1760 <GIC_SPI 1761 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1761 <GIC_SPI 1762 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1762 <GIC_SPI 1763 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1763 <GIC_SPI 1764 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1764 <GIC_SPI 1765 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1765 <GIC_SPI 1766 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1766 <GIC_SPI 1767 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1767 <GIC_SPI 1768 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1768 <GIC_SPI 1769 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>;
1769 dma-channels = <10>; 1770 dma-channels = <10>;
1770 dma-channel-mask = <0 1771 dma-channel-mask = <0x3f>;
1771 iommus = <&apps_smmu 1772 iommus = <&apps_smmu 0x56 0x0>;
1772 #dma-cells = <3>; 1773 #dma-cells = <3>;
1773 status = "disabled"; 1774 status = "disabled";
1774 }; 1775 };
1775 1776
1776 qupv3_id_1: geniqup@ac0000 { 1777 qupv3_id_1: geniqup@ac0000 {
1777 compatible = "qcom,ge 1778 compatible = "qcom,geni-se-qup";
1778 reg = <0x0 0x00ac0000 1779 reg = <0x0 0x00ac0000 0x0 0x6000>;
1779 clock-names = "m-ahb" 1780 clock-names = "m-ahb", "s-ahb";
1780 clocks = <&gcc GCC_QU 1781 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1781 <&gcc GCC_QU 1782 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1782 #address-cells = <2>; 1783 #address-cells = <2>;
1783 #size-cells = <2>; 1784 #size-cells = <2>;
1784 iommus = <&apps_smmu 1785 iommus = <&apps_smmu 0x43 0x0>;
1785 ranges; 1786 ranges;
1786 status = "disabled"; 1787 status = "disabled";
1787 1788
1788 i2c8: i2c@a80000 { 1789 i2c8: i2c@a80000 {
1789 compatible = 1790 compatible = "qcom,geni-i2c";
1790 reg = <0 0x00 1791 reg = <0 0x00a80000 0 0x4000>;
1791 clock-names = 1792 clock-names = "se";
1792 clocks = <&gc 1793 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1793 pinctrl-names 1794 pinctrl-names = "default";
1794 pinctrl-0 = < 1795 pinctrl-0 = <&qup_i2c8_default>;
1795 interrupts = 1796 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1796 dmas = <&gpi_ 1797 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1797 <&gpi_ 1798 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1798 dma-names = " 1799 dma-names = "tx", "rx";
1799 power-domains 1800 power-domains = <&rpmhpd SM8250_CX>;
1800 interconnects 1801 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1801 1802 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1802 1803 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1803 interconnect- 1804 interconnect-names = "qup-core",
1804 1805 "qup-config",
1805 1806 "qup-memory";
1806 #address-cell 1807 #address-cells = <1>;
1807 #size-cells = 1808 #size-cells = <0>;
1808 status = "dis 1809 status = "disabled";
1809 }; 1810 };
1810 1811
1811 spi8: spi@a80000 { 1812 spi8: spi@a80000 {
1812 compatible = 1813 compatible = "qcom,geni-spi";
1813 reg = <0 0x00 1814 reg = <0 0x00a80000 0 0x4000>;
1814 clock-names = 1815 clock-names = "se";
1815 clocks = <&gc 1816 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1816 interrupts = 1817 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1817 dmas = <&gpi_ 1818 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1818 <&gpi_ 1819 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1819 dma-names = " 1820 dma-names = "tx", "rx";
1820 power-domains 1821 power-domains = <&rpmhpd RPMHPD_CX>;
1821 operating-poi 1822 operating-points-v2 = <&qup_opp_table>;
1822 interconnects 1823 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1823 1824 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1824 1825 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1825 interconnect- 1826 interconnect-names = "qup-core",
1826 1827 "qup-config",
1827 1828 "qup-memory";
1828 #address-cell 1829 #address-cells = <1>;
1829 #size-cells = 1830 #size-cells = <0>;
1830 status = "dis 1831 status = "disabled";
1831 }; 1832 };
1832 1833
1833 i2c9: i2c@a84000 { 1834 i2c9: i2c@a84000 {
1834 compatible = 1835 compatible = "qcom,geni-i2c";
1835 reg = <0 0x00 1836 reg = <0 0x00a84000 0 0x4000>;
1836 clock-names = 1837 clock-names = "se";
1837 clocks = <&gc 1838 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1838 pinctrl-names 1839 pinctrl-names = "default";
1839 pinctrl-0 = < 1840 pinctrl-0 = <&qup_i2c9_default>;
1840 interrupts = 1841 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1841 dmas = <&gpi_ 1842 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1842 <&gpi_ 1843 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1843 dma-names = " 1844 dma-names = "tx", "rx";
1844 power-domains 1845 power-domains = <&rpmhpd SM8250_CX>;
1845 interconnects 1846 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1846 1847 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1847 1848 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1848 interconnect- 1849 interconnect-names = "qup-core",
1849 1850 "qup-config",
1850 1851 "qup-memory";
1851 #address-cell 1852 #address-cells = <1>;
1852 #size-cells = 1853 #size-cells = <0>;
1853 status = "dis 1854 status = "disabled";
1854 }; 1855 };
1855 1856
1856 spi9: spi@a84000 { 1857 spi9: spi@a84000 {
1857 compatible = 1858 compatible = "qcom,geni-spi";
1858 reg = <0 0x00 1859 reg = <0 0x00a84000 0 0x4000>;
1859 clock-names = 1860 clock-names = "se";
1860 clocks = <&gc 1861 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1861 interrupts = 1862 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1862 dmas = <&gpi_ 1863 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1863 <&gpi_ 1864 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1864 dma-names = " 1865 dma-names = "tx", "rx";
1865 power-domains 1866 power-domains = <&rpmhpd RPMHPD_CX>;
1866 operating-poi 1867 operating-points-v2 = <&qup_opp_table>;
1867 interconnects 1868 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1868 1869 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1869 1870 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1870 interconnect- 1871 interconnect-names = "qup-core",
1871 1872 "qup-config",
1872 1873 "qup-memory";
1873 #address-cell 1874 #address-cells = <1>;
1874 #size-cells = 1875 #size-cells = <0>;
1875 status = "dis 1876 status = "disabled";
1876 }; 1877 };
1877 1878
1878 i2c10: i2c@a88000 { 1879 i2c10: i2c@a88000 {
1879 compatible = 1880 compatible = "qcom,geni-i2c";
1880 reg = <0 0x00 1881 reg = <0 0x00a88000 0 0x4000>;
1881 clock-names = 1882 clock-names = "se";
1882 clocks = <&gc 1883 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1883 pinctrl-names 1884 pinctrl-names = "default";
1884 pinctrl-0 = < 1885 pinctrl-0 = <&qup_i2c10_default>;
1885 interrupts = 1886 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1886 dmas = <&gpi_ 1887 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1887 <&gpi_ 1888 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1888 dma-names = " 1889 dma-names = "tx", "rx";
1889 power-domains 1890 power-domains = <&rpmhpd SM8250_CX>;
1890 interconnects 1891 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1891 1892 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1892 1893 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1893 interconnect- 1894 interconnect-names = "qup-core",
1894 1895 "qup-config",
1895 1896 "qup-memory";
1896 #address-cell 1897 #address-cells = <1>;
1897 #size-cells = 1898 #size-cells = <0>;
1898 status = "dis 1899 status = "disabled";
1899 }; 1900 };
1900 1901
1901 spi10: spi@a88000 { 1902 spi10: spi@a88000 {
1902 compatible = 1903 compatible = "qcom,geni-spi";
1903 reg = <0 0x00 1904 reg = <0 0x00a88000 0 0x4000>;
1904 clock-names = 1905 clock-names = "se";
1905 clocks = <&gc 1906 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1906 interrupts = 1907 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1907 dmas = <&gpi_ 1908 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1908 <&gpi_ 1909 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1909 dma-names = " 1910 dma-names = "tx", "rx";
1910 power-domains 1911 power-domains = <&rpmhpd RPMHPD_CX>;
1911 operating-poi 1912 operating-points-v2 = <&qup_opp_table>;
1912 interconnects 1913 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1913 1914 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1914 1915 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1915 interconnect- 1916 interconnect-names = "qup-core",
1916 1917 "qup-config",
1917 1918 "qup-memory";
1918 #address-cell 1919 #address-cells = <1>;
1919 #size-cells = 1920 #size-cells = <0>;
1920 status = "dis 1921 status = "disabled";
1921 }; 1922 };
1922 1923
1923 i2c11: i2c@a8c000 { 1924 i2c11: i2c@a8c000 {
1924 compatible = 1925 compatible = "qcom,geni-i2c";
1925 reg = <0 0x00 1926 reg = <0 0x00a8c000 0 0x4000>;
1926 clock-names = 1927 clock-names = "se";
1927 clocks = <&gc 1928 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1928 pinctrl-names 1929 pinctrl-names = "default";
1929 pinctrl-0 = < 1930 pinctrl-0 = <&qup_i2c11_default>;
1930 interrupts = 1931 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1931 dmas = <&gpi_ 1932 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1932 <&gpi_ 1933 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1933 dma-names = " 1934 dma-names = "tx", "rx";
1934 power-domains 1935 power-domains = <&rpmhpd SM8250_CX>;
1935 interconnects 1936 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1936 1937 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1937 1938 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1938 interconnect- 1939 interconnect-names = "qup-core",
1939 1940 "qup-config",
1940 1941 "qup-memory";
1941 #address-cell 1942 #address-cells = <1>;
1942 #size-cells = 1943 #size-cells = <0>;
1943 status = "dis 1944 status = "disabled";
1944 }; 1945 };
1945 1946
1946 spi11: spi@a8c000 { 1947 spi11: spi@a8c000 {
1947 compatible = 1948 compatible = "qcom,geni-spi";
1948 reg = <0 0x00 1949 reg = <0 0x00a8c000 0 0x4000>;
1949 clock-names = 1950 clock-names = "se";
1950 clocks = <&gc 1951 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1951 interrupts = 1952 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1952 dmas = <&gpi_ 1953 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1953 <&gpi_ 1954 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1954 dma-names = " 1955 dma-names = "tx", "rx";
1955 power-domains 1956 power-domains = <&rpmhpd RPMHPD_CX>;
1956 operating-poi 1957 operating-points-v2 = <&qup_opp_table>;
1957 interconnects 1958 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1958 1959 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1959 1960 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1960 interconnect- 1961 interconnect-names = "qup-core",
1961 1962 "qup-config",
1962 1963 "qup-memory";
1963 #address-cell 1964 #address-cells = <1>;
1964 #size-cells = 1965 #size-cells = <0>;
1965 status = "dis 1966 status = "disabled";
1966 }; 1967 };
1967 1968
1968 i2c12: i2c@a90000 { 1969 i2c12: i2c@a90000 {
1969 compatible = 1970 compatible = "qcom,geni-i2c";
1970 reg = <0 0x00 1971 reg = <0 0x00a90000 0 0x4000>;
1971 clock-names = 1972 clock-names = "se";
1972 clocks = <&gc 1973 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1973 pinctrl-names 1974 pinctrl-names = "default";
1974 pinctrl-0 = < 1975 pinctrl-0 = <&qup_i2c12_default>;
1975 interrupts = 1976 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1976 dmas = <&gpi_ 1977 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1977 <&gpi_ 1978 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1978 dma-names = " 1979 dma-names = "tx", "rx";
1979 power-domains 1980 power-domains = <&rpmhpd SM8250_CX>;
1980 interconnects 1981 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1981 1982 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1982 1983 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1983 interconnect- 1984 interconnect-names = "qup-core",
1984 1985 "qup-config",
1985 1986 "qup-memory";
1986 #address-cell 1987 #address-cells = <1>;
1987 #size-cells = 1988 #size-cells = <0>;
1988 status = "dis 1989 status = "disabled";
1989 }; 1990 };
1990 1991
1991 spi12: spi@a90000 { 1992 spi12: spi@a90000 {
1992 compatible = 1993 compatible = "qcom,geni-spi";
1993 reg = <0 0x00 1994 reg = <0 0x00a90000 0 0x4000>;
1994 clock-names = 1995 clock-names = "se";
1995 clocks = <&gc 1996 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1996 interrupts = 1997 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1997 dmas = <&gpi_ 1998 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1998 <&gpi_ 1999 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1999 dma-names = " 2000 dma-names = "tx", "rx";
2000 power-domains 2001 power-domains = <&rpmhpd RPMHPD_CX>;
2001 operating-poi 2002 operating-points-v2 = <&qup_opp_table>;
2002 interconnects 2003 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
2003 2004 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
2004 2005 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
2005 interconnect- 2006 interconnect-names = "qup-core",
2006 2007 "qup-config",
2007 2008 "qup-memory";
2008 #address-cell 2009 #address-cells = <1>;
2009 #size-cells = 2010 #size-cells = <0>;
2010 status = "dis 2011 status = "disabled";
2011 }; 2012 };
2012 2013
2013 uart12: serial@a90000 2014 uart12: serial@a90000 {
2014 compatible = 2015 compatible = "qcom,geni-debug-uart";
2015 reg = <0x0 0x 2016 reg = <0x0 0x00a90000 0x0 0x4000>;
2016 clock-names = 2017 clock-names = "se";
2017 clocks = <&gc 2018 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
2018 pinctrl-names 2019 pinctrl-names = "default";
2019 pinctrl-0 = < 2020 pinctrl-0 = <&qup_uart12_default>;
2020 interrupts = 2021 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
2021 power-domains 2022 power-domains = <&rpmhpd RPMHPD_CX>;
2022 operating-poi 2023 operating-points-v2 = <&qup_opp_table>;
2023 interconnects 2024 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
2024 2025 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
2025 interconnect- 2026 interconnect-names = "qup-core",
2026 2027 "qup-config";
2027 status = "dis 2028 status = "disabled";
2028 }; 2029 };
2029 2030
2030 i2c13: i2c@a94000 { 2031 i2c13: i2c@a94000 {
2031 compatible = 2032 compatible = "qcom,geni-i2c";
2032 reg = <0 0x00 2033 reg = <0 0x00a94000 0 0x4000>;
2033 clock-names = 2034 clock-names = "se";
2034 clocks = <&gc 2035 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2035 pinctrl-names 2036 pinctrl-names = "default";
2036 pinctrl-0 = < 2037 pinctrl-0 = <&qup_i2c13_default>;
2037 interrupts = 2038 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2038 dmas = <&gpi_ 2039 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
2039 <&gpi_ 2040 <&gpi_dma1 1 5 QCOM_GPI_I2C>;
2040 dma-names = " 2041 dma-names = "tx", "rx";
2041 power-domains 2042 power-domains = <&rpmhpd SM8250_CX>;
2042 interconnects 2043 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
2043 2044 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
2044 2045 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
2045 interconnect- 2046 interconnect-names = "qup-core",
2046 2047 "qup-config",
2047 2048 "qup-memory";
2048 #address-cell 2049 #address-cells = <1>;
2049 #size-cells = 2050 #size-cells = <0>;
2050 status = "dis 2051 status = "disabled";
2051 }; 2052 };
2052 2053
2053 spi13: spi@a94000 { 2054 spi13: spi@a94000 {
2054 compatible = 2055 compatible = "qcom,geni-spi";
2055 reg = <0 0x00 2056 reg = <0 0x00a94000 0 0x4000>;
2056 clock-names = 2057 clock-names = "se";
2057 clocks = <&gc 2058 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2058 interrupts = 2059 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2059 dmas = <&gpi_ 2060 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
2060 <&gpi_ 2061 <&gpi_dma1 1 5 QCOM_GPI_SPI>;
2061 dma-names = " 2062 dma-names = "tx", "rx";
2062 power-domains 2063 power-domains = <&rpmhpd RPMHPD_CX>;
2063 operating-poi 2064 operating-points-v2 = <&qup_opp_table>;
2064 interconnects 2065 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
2065 2066 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
2066 2067 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
2067 interconnect- 2068 interconnect-names = "qup-core",
2068 2069 "qup-config",
2069 2070 "qup-memory";
2070 #address-cell 2071 #address-cells = <1>;
2071 #size-cells = 2072 #size-cells = <0>;
2072 status = "dis 2073 status = "disabled";
2073 }; 2074 };
2074 }; 2075 };
2075 2076
2076 config_noc: interconnect@1500 2077 config_noc: interconnect@1500000 {
2077 compatible = "qcom,sm 2078 compatible = "qcom,sm8250-config-noc";
2078 reg = <0 0x01500000 0 2079 reg = <0 0x01500000 0 0xa580>;
2079 #interconnect-cells = 2080 #interconnect-cells = <2>;
2080 qcom,bcm-voters = <&a 2081 qcom,bcm-voters = <&apps_bcm_voter>;
2081 }; 2082 };
2082 2083
2083 system_noc: interconnect@1620 2084 system_noc: interconnect@1620000 {
2084 compatible = "qcom,sm 2085 compatible = "qcom,sm8250-system-noc";
2085 reg = <0 0x01620000 0 2086 reg = <0 0x01620000 0 0x1c200>;
2086 #interconnect-cells = 2087 #interconnect-cells = <2>;
2087 qcom,bcm-voters = <&a 2088 qcom,bcm-voters = <&apps_bcm_voter>;
2088 }; 2089 };
2089 2090
2090 mc_virt: interconnect@163d000 2091 mc_virt: interconnect@163d000 {
2091 compatible = "qcom,sm 2092 compatible = "qcom,sm8250-mc-virt";
2092 reg = <0 0x0163d000 0 2093 reg = <0 0x0163d000 0 0x1000>;
2093 #interconnect-cells = 2094 #interconnect-cells = <2>;
2094 qcom,bcm-voters = <&a 2095 qcom,bcm-voters = <&apps_bcm_voter>;
2095 }; 2096 };
2096 2097
2097 aggre1_noc: interconnect@16e0 2098 aggre1_noc: interconnect@16e0000 {
2098 compatible = "qcom,sm 2099 compatible = "qcom,sm8250-aggre1-noc";
2099 reg = <0 0x016e0000 0 2100 reg = <0 0x016e0000 0 0x1f180>;
2100 #interconnect-cells = 2101 #interconnect-cells = <2>;
2101 qcom,bcm-voters = <&a 2102 qcom,bcm-voters = <&apps_bcm_voter>;
2102 }; 2103 };
2103 2104
2104 aggre2_noc: interconnect@1700 2105 aggre2_noc: interconnect@1700000 {
2105 compatible = "qcom,sm 2106 compatible = "qcom,sm8250-aggre2-noc";
2106 reg = <0 0x01700000 0 2107 reg = <0 0x01700000 0 0x33000>;
2107 #interconnect-cells = 2108 #interconnect-cells = <2>;
2108 qcom,bcm-voters = <&a 2109 qcom,bcm-voters = <&apps_bcm_voter>;
2109 }; 2110 };
2110 2111
2111 compute_noc: interconnect@173 2112 compute_noc: interconnect@1733000 {
2112 compatible = "qcom,sm 2113 compatible = "qcom,sm8250-compute-noc";
2113 reg = <0 0x01733000 0 2114 reg = <0 0x01733000 0 0xa180>;
2114 #interconnect-cells = 2115 #interconnect-cells = <2>;
2115 qcom,bcm-voters = <&a 2116 qcom,bcm-voters = <&apps_bcm_voter>;
2116 }; 2117 };
2117 2118
2118 mmss_noc: interconnect@174000 2119 mmss_noc: interconnect@1740000 {
2119 compatible = "qcom,sm 2120 compatible = "qcom,sm8250-mmss-noc";
2120 reg = <0 0x01740000 0 2121 reg = <0 0x01740000 0 0x1f080>;
2121 #interconnect-cells = 2122 #interconnect-cells = <2>;
2122 qcom,bcm-voters = <&a 2123 qcom,bcm-voters = <&apps_bcm_voter>;
2123 }; 2124 };
2124 2125
2125 pcie0: pcie@1c00000 { !! 2126 pcie0: pci@1c00000 {
2126 compatible = "qcom,pc 2127 compatible = "qcom,pcie-sm8250";
2127 reg = <0 0x01c00000 0 2128 reg = <0 0x01c00000 0 0x3000>,
2128 <0 0x60000000 0 2129 <0 0x60000000 0 0xf1d>,
2129 <0 0x60000f20 0 2130 <0 0x60000f20 0 0xa8>,
2130 <0 0x60001000 0 2131 <0 0x60001000 0 0x1000>,
2131 <0 0x60100000 0 2132 <0 0x60100000 0 0x100000>,
2132 <0 0x01c03000 0 2133 <0 0x01c03000 0 0x1000>;
2133 reg-names = "parf", " 2134 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2134 device_type = "pci"; 2135 device_type = "pci";
2135 linux,pci-domain = <0 2136 linux,pci-domain = <0>;
2136 bus-range = <0x00 0xf 2137 bus-range = <0x00 0xff>;
2137 num-lanes = <1>; 2138 num-lanes = <1>;
2138 2139
2139 #address-cells = <3>; 2140 #address-cells = <3>;
2140 #size-cells = <2>; 2141 #size-cells = <2>;
2141 2142
2142 ranges = <0x01000000 2143 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
2143 <0x02000000 2144 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
2144 2145
2145 interrupts = <GIC_SPI 2146 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
2146 <GIC_SPI 2147 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
2147 <GIC_SPI 2148 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
2148 <GIC_SPI 2149 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
2149 <GIC_SPI 2150 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
2150 <GIC_SPI 2151 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
2151 <GIC_SPI 2152 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
2152 <GIC_SPI 2153 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2153 interrupt-names = "ms !! 2154 interrupt-names = "msi0", "msi1", "msi2", "msi3",
2154 "ms !! 2155 "msi4", "msi5", "msi6", "msi7";
2155 "ms <<
2156 "ms <<
2157 "ms <<
2158 "ms <<
2159 "ms <<
2160 "ms <<
2161 #interrupt-cells = <1 2156 #interrupt-cells = <1>;
2162 interrupt-map-mask = 2157 interrupt-map-mask = <0 0 0 0x7>;
2163 interrupt-map = <0 0 2158 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2164 <0 0 2159 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2165 <0 0 2160 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2166 <0 0 2161 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2167 2162
2168 clocks = <&gcc GCC_PC 2163 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
2169 <&gcc GCC_PC 2164 <&gcc GCC_PCIE_0_AUX_CLK>,
2170 <&gcc GCC_PC 2165 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2171 <&gcc GCC_PC 2166 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
2172 <&gcc GCC_PC 2167 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
2173 <&gcc GCC_PC 2168 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
2174 <&gcc GCC_AG 2169 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
2175 <&gcc GCC_DD 2170 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
2176 clock-names = "pipe", 2171 clock-names = "pipe",
2177 "aux", 2172 "aux",
2178 "cfg", 2173 "cfg",
2179 "bus_ma 2174 "bus_master",
2180 "bus_sl 2175 "bus_slave",
2181 "slave_ 2176 "slave_q2a",
2182 "tbu", 2177 "tbu",
2183 "ddrss_ 2178 "ddrss_sf_tbu";
2184 2179
2185 iommu-map = <0x0 &a 2180 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
2186 <0x100 &a 2181 <0x100 &apps_smmu 0x1c01 0x1>;
2187 2182
2188 resets = <&gcc GCC_PC 2183 resets = <&gcc GCC_PCIE_0_BCR>;
2189 reset-names = "pci"; 2184 reset-names = "pci";
2190 2185
2191 power-domains = <&gcc 2186 power-domains = <&gcc PCIE_0_GDSC>;
2192 2187
2193 phys = <&pcie0_phy>; 2188 phys = <&pcie0_phy>;
2194 phy-names = "pciephy" 2189 phy-names = "pciephy";
2195 2190
2196 perst-gpios = <&tlmm 2191 perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>;
2197 wake-gpios = <&tlmm 8 2192 wake-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
2198 2193
2199 pinctrl-names = "defa 2194 pinctrl-names = "default";
2200 pinctrl-0 = <&pcie0_d 2195 pinctrl-0 = <&pcie0_default_state>;
2201 dma-coherent; 2196 dma-coherent;
2202 2197
2203 status = "disabled"; 2198 status = "disabled";
2204 <<
2205 pcieport0: pcie@0 { <<
2206 device_type = <<
2207 reg = <0x0 0x <<
2208 bus-range = < <<
2209 <<
2210 #address-cell <<
2211 #size-cells = <<
2212 ranges; <<
2213 }; <<
2214 }; 2199 };
2215 2200
2216 pcie0_phy: phy@1c06000 { 2201 pcie0_phy: phy@1c06000 {
2217 compatible = "qcom,sm 2202 compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy";
2218 reg = <0 0x01c06000 0 2203 reg = <0 0x01c06000 0 0x1000>;
2219 2204
2220 clocks = <&gcc GCC_PC 2205 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2221 <&gcc GCC_PC 2206 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2222 <&gcc GCC_PC 2207 <&gcc GCC_PCIE_WIFI_CLKREF_EN>,
2223 <&gcc GCC_PC 2208 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>,
2224 <&gcc GCC_PC 2209 <&gcc GCC_PCIE_0_PIPE_CLK>;
2225 clock-names = "aux", 2210 clock-names = "aux",
2226 "cfg_ah 2211 "cfg_ahb",
2227 "ref", 2212 "ref",
2228 "refgen 2213 "refgen",
2229 "pipe"; 2214 "pipe";
2230 2215
2231 clock-output-names = 2216 clock-output-names = "pcie_0_pipe_clk";
2232 #clock-cells = <0>; 2217 #clock-cells = <0>;
2233 2218
2234 #phy-cells = <0>; 2219 #phy-cells = <0>;
2235 2220
2236 resets = <&gcc GCC_PC 2221 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
2237 reset-names = "phy"; 2222 reset-names = "phy";
2238 2223
2239 assigned-clocks = <&g 2224 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
2240 assigned-clock-rates 2225 assigned-clock-rates = <100000000>;
2241 2226
2242 status = "disabled"; 2227 status = "disabled";
2243 }; 2228 };
2244 2229
2245 pcie1: pcie@1c08000 { !! 2230 pcie1: pci@1c08000 {
2246 compatible = "qcom,pc 2231 compatible = "qcom,pcie-sm8250";
2247 reg = <0 0x01c08000 0 2232 reg = <0 0x01c08000 0 0x3000>,
2248 <0 0x40000000 0 2233 <0 0x40000000 0 0xf1d>,
2249 <0 0x40000f20 0 2234 <0 0x40000f20 0 0xa8>,
2250 <0 0x40001000 0 2235 <0 0x40001000 0 0x1000>,
2251 <0 0x40100000 0 2236 <0 0x40100000 0 0x100000>,
2252 <0 0x01c0b000 0 2237 <0 0x01c0b000 0 0x1000>;
2253 reg-names = "parf", " 2238 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2254 device_type = "pci"; 2239 device_type = "pci";
2255 linux,pci-domain = <1 2240 linux,pci-domain = <1>;
2256 bus-range = <0x00 0xf 2241 bus-range = <0x00 0xff>;
2257 num-lanes = <2>; 2242 num-lanes = <2>;
2258 2243
2259 #address-cells = <3>; 2244 #address-cells = <3>;
2260 #size-cells = <2>; 2245 #size-cells = <2>;
2261 2246
2262 ranges = <0x01000000 2247 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
2263 <0x02000000 2248 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
2264 2249
2265 interrupts = <GIC_SPI !! 2250 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
2266 <GIC_SPI !! 2251 interrupt-names = "msi";
2267 <GIC_SPI <<
2268 <GIC_SPI <<
2269 <GIC_SPI <<
2270 <GIC_SPI <<
2271 <GIC_SPI <<
2272 <GIC_SPI <<
2273 interrupt-names = "ms <<
2274 "ms <<
2275 "ms <<
2276 "ms <<
2277 "ms <<
2278 "ms <<
2279 "ms <<
2280 "ms <<
2281 #interrupt-cells = <1 2252 #interrupt-cells = <1>;
2282 interrupt-map-mask = 2253 interrupt-map-mask = <0 0 0 0x7>;
2283 interrupt-map = <0 0 2254 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2284 <0 0 2255 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2285 <0 0 2256 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2286 <0 0 2257 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2287 2258
2288 clocks = <&gcc GCC_PC 2259 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
2289 <&gcc GCC_PC 2260 <&gcc GCC_PCIE_1_AUX_CLK>,
2290 <&gcc GCC_PC 2261 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2291 <&gcc GCC_PC 2262 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
2292 <&gcc GCC_PC 2263 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
2293 <&gcc GCC_PC 2264 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
2294 <&gcc GCC_PC 2265 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
2295 <&gcc GCC_AG 2266 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
2296 <&gcc GCC_DD 2267 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
2297 clock-names = "pipe", 2268 clock-names = "pipe",
2298 "aux", 2269 "aux",
2299 "cfg", 2270 "cfg",
2300 "bus_ma 2271 "bus_master",
2301 "bus_sl 2272 "bus_slave",
2302 "slave_ 2273 "slave_q2a",
2303 "ref", 2274 "ref",
2304 "tbu", 2275 "tbu",
2305 "ddrss_ 2276 "ddrss_sf_tbu";
2306 2277
2307 assigned-clocks = <&g 2278 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2308 assigned-clock-rates 2279 assigned-clock-rates = <19200000>;
2309 2280
2310 iommu-map = <0x0 &a 2281 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
2311 <0x100 &a 2282 <0x100 &apps_smmu 0x1c81 0x1>;
2312 2283
2313 resets = <&gcc GCC_PC 2284 resets = <&gcc GCC_PCIE_1_BCR>;
2314 reset-names = "pci"; 2285 reset-names = "pci";
2315 2286
2316 power-domains = <&gcc 2287 power-domains = <&gcc PCIE_1_GDSC>;
2317 2288
2318 phys = <&pcie1_phy>; 2289 phys = <&pcie1_phy>;
2319 phy-names = "pciephy" 2290 phy-names = "pciephy";
2320 2291
2321 perst-gpios = <&tlmm 2292 perst-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>;
2322 wake-gpios = <&tlmm 8 2293 wake-gpios = <&tlmm 84 GPIO_ACTIVE_HIGH>;
2323 2294
2324 pinctrl-names = "defa 2295 pinctrl-names = "default";
2325 pinctrl-0 = <&pcie1_d 2296 pinctrl-0 = <&pcie1_default_state>;
2326 dma-coherent; 2297 dma-coherent;
2327 2298
2328 status = "disabled"; 2299 status = "disabled";
2329 <<
2330 pcie@0 { <<
2331 device_type = <<
2332 reg = <0x0 0x <<
2333 bus-range = < <<
2334 <<
2335 #address-cell <<
2336 #size-cells = <<
2337 ranges; <<
2338 }; <<
2339 }; 2300 };
2340 2301
2341 pcie1_phy: phy@1c0e000 { 2302 pcie1_phy: phy@1c0e000 {
2342 compatible = "qcom,sm 2303 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
2343 reg = <0 0x01c0e000 0 2304 reg = <0 0x01c0e000 0 0x1000>;
2344 2305
2345 clocks = <&gcc GCC_PC 2306 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2346 <&gcc GCC_PC 2307 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2347 <&gcc GCC_PC 2308 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
2348 <&gcc GCC_PC 2309 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>,
2349 <&gcc GCC_PC 2310 <&gcc GCC_PCIE_1_PIPE_CLK>;
2350 clock-names = "aux", 2311 clock-names = "aux",
2351 "cfg_ah 2312 "cfg_ahb",
2352 "ref", 2313 "ref",
2353 "refgen 2314 "refgen",
2354 "pipe"; 2315 "pipe";
2355 2316
2356 clock-output-names = 2317 clock-output-names = "pcie_1_pipe_clk";
2357 #clock-cells = <0>; 2318 #clock-cells = <0>;
2358 2319
2359 #phy-cells = <0>; 2320 #phy-cells = <0>;
2360 2321
2361 resets = <&gcc GCC_PC 2322 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2362 reset-names = "phy"; 2323 reset-names = "phy";
2363 2324
2364 assigned-clocks = <&g 2325 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
2365 assigned-clock-rates 2326 assigned-clock-rates = <100000000>;
2366 2327
2367 status = "disabled"; 2328 status = "disabled";
2368 }; 2329 };
2369 2330
2370 pcie2: pcie@1c10000 { !! 2331 pcie2: pci@1c10000 {
2371 compatible = "qcom,pc 2332 compatible = "qcom,pcie-sm8250";
2372 reg = <0 0x01c10000 0 2333 reg = <0 0x01c10000 0 0x3000>,
2373 <0 0x64000000 0 2334 <0 0x64000000 0 0xf1d>,
2374 <0 0x64000f20 0 2335 <0 0x64000f20 0 0xa8>,
2375 <0 0x64001000 0 2336 <0 0x64001000 0 0x1000>,
2376 <0 0x64100000 0 2337 <0 0x64100000 0 0x100000>,
2377 <0 0x01c13000 0 2338 <0 0x01c13000 0 0x1000>;
2378 reg-names = "parf", " 2339 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2379 device_type = "pci"; 2340 device_type = "pci";
2380 linux,pci-domain = <2 2341 linux,pci-domain = <2>;
2381 bus-range = <0x00 0xf 2342 bus-range = <0x00 0xff>;
2382 num-lanes = <2>; 2343 num-lanes = <2>;
2383 2344
2384 #address-cells = <3>; 2345 #address-cells = <3>;
2385 #size-cells = <2>; 2346 #size-cells = <2>;
2386 2347
2387 ranges = <0x01000000 2348 ranges = <0x01000000 0x0 0x00000000 0x0 0x64200000 0x0 0x100000>,
2388 <0x02000000 2349 <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>;
2389 2350
2390 interrupts = <GIC_SPI !! 2351 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
2391 <GIC_SPI !! 2352 interrupt-names = "msi";
2392 <GIC_SPI <<
2393 <GIC_SPI <<
2394 <GIC_SPI <<
2395 <GIC_SPI <<
2396 <GIC_SPI <<
2397 <GIC_SPI <<
2398 interrupt-names = "ms <<
2399 "ms <<
2400 "ms <<
2401 "ms <<
2402 "ms <<
2403 "ms <<
2404 "ms <<
2405 "ms <<
2406 #interrupt-cells = <1 2353 #interrupt-cells = <1>;
2407 interrupt-map-mask = 2354 interrupt-map-mask = <0 0 0 0x7>;
2408 interrupt-map = <0 0 2355 interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2409 <0 0 2356 <0 0 0 2 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2410 <0 0 2357 <0 0 0 3 &intc 0 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2411 <0 0 2358 <0 0 0 4 &intc 0 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2412 2359
2413 clocks = <&gcc GCC_PC 2360 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
2414 <&gcc GCC_PC 2361 <&gcc GCC_PCIE_2_AUX_CLK>,
2415 <&gcc GCC_PC 2362 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2416 <&gcc GCC_PC 2363 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
2417 <&gcc GCC_PC 2364 <&gcc GCC_PCIE_2_SLV_AXI_CLK>,
2418 <&gcc GCC_PC 2365 <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>,
2419 <&gcc GCC_PC 2366 <&gcc GCC_PCIE_MDM_CLKREF_EN>,
2420 <&gcc GCC_AG 2367 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
2421 <&gcc GCC_DD 2368 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
2422 clock-names = "pipe", 2369 clock-names = "pipe",
2423 "aux", 2370 "aux",
2424 "cfg", 2371 "cfg",
2425 "bus_ma 2372 "bus_master",
2426 "bus_sl 2373 "bus_slave",
2427 "slave_ 2374 "slave_q2a",
2428 "ref", 2375 "ref",
2429 "tbu", 2376 "tbu",
2430 "ddrss_ 2377 "ddrss_sf_tbu";
2431 2378
2432 assigned-clocks = <&g 2379 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>;
2433 assigned-clock-rates 2380 assigned-clock-rates = <19200000>;
2434 2381
2435 iommu-map = <0x0 &a 2382 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>,
2436 <0x100 &a 2383 <0x100 &apps_smmu 0x1d01 0x1>;
2437 2384
2438 resets = <&gcc GCC_PC 2385 resets = <&gcc GCC_PCIE_2_BCR>;
2439 reset-names = "pci"; 2386 reset-names = "pci";
2440 2387
2441 power-domains = <&gcc 2388 power-domains = <&gcc PCIE_2_GDSC>;
2442 2389
2443 phys = <&pcie2_phy>; 2390 phys = <&pcie2_phy>;
2444 phy-names = "pciephy" 2391 phy-names = "pciephy";
2445 2392
2446 perst-gpios = <&tlmm 2393 perst-gpios = <&tlmm 85 GPIO_ACTIVE_LOW>;
2447 wake-gpios = <&tlmm 8 2394 wake-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>;
2448 2395
2449 pinctrl-names = "defa 2396 pinctrl-names = "default";
2450 pinctrl-0 = <&pcie2_d 2397 pinctrl-0 = <&pcie2_default_state>;
2451 dma-coherent; 2398 dma-coherent;
2452 2399
2453 status = "disabled"; 2400 status = "disabled";
2454 <<
2455 pcie@0 { <<
2456 device_type = <<
2457 reg = <0x0 0x <<
2458 bus-range = < <<
2459 <<
2460 #address-cell <<
2461 #size-cells = <<
2462 ranges; <<
2463 }; <<
2464 }; 2401 };
2465 2402
2466 pcie2_phy: phy@1c16000 { 2403 pcie2_phy: phy@1c16000 {
2467 compatible = "qcom,sm 2404 compatible = "qcom,sm8250-qmp-modem-pcie-phy";
2468 reg = <0 0x01c16000 0 2405 reg = <0 0x01c16000 0 0x1000>;
2469 2406
2470 clocks = <&gcc GCC_PC 2407 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2471 <&gcc GCC_PC 2408 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2472 <&gcc GCC_PC 2409 <&gcc GCC_PCIE_MDM_CLKREF_EN>,
2473 <&gcc GCC_PC 2410 <&gcc GCC_PCIE2_PHY_REFGEN_CLK>,
2474 <&gcc GCC_PC 2411 <&gcc GCC_PCIE_2_PIPE_CLK>;
2475 clock-names = "aux", 2412 clock-names = "aux",
2476 "cfg_ah 2413 "cfg_ahb",
2477 "ref", 2414 "ref",
2478 "refgen 2415 "refgen",
2479 "pipe"; 2416 "pipe";
2480 2417
2481 clock-output-names = 2418 clock-output-names = "pcie_2_pipe_clk";
2482 #clock-cells = <0>; 2419 #clock-cells = <0>;
2483 2420
2484 #phy-cells = <0>; 2421 #phy-cells = <0>;
2485 2422
2486 resets = <&gcc GCC_PC 2423 resets = <&gcc GCC_PCIE_2_PHY_BCR>;
2487 reset-names = "phy"; 2424 reset-names = "phy";
2488 2425
2489 assigned-clocks = <&g 2426 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
2490 assigned-clock-rates 2427 assigned-clock-rates = <100000000>;
2491 2428
2492 status = "disabled"; 2429 status = "disabled";
2493 }; 2430 };
2494 2431
2495 ufs_mem_hc: ufshc@1d84000 { 2432 ufs_mem_hc: ufshc@1d84000 {
2496 compatible = "qcom,sm 2433 compatible = "qcom,sm8250-ufshc", "qcom,ufshc",
2497 "jedec,u 2434 "jedec,ufs-2.0";
2498 reg = <0 0x01d84000 0 2435 reg = <0 0x01d84000 0 0x3000>;
2499 interrupts = <GIC_SPI 2436 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2500 phys = <&ufs_mem_phy> !! 2437 phys = <&ufs_mem_phy_lanes>;
2501 phy-names = "ufsphy"; 2438 phy-names = "ufsphy";
2502 lanes-per-direction = 2439 lanes-per-direction = <2>;
2503 #reset-cells = <1>; 2440 #reset-cells = <1>;
2504 resets = <&gcc GCC_UF 2441 resets = <&gcc GCC_UFS_PHY_BCR>;
2505 reset-names = "rst"; 2442 reset-names = "rst";
2506 2443
2507 power-domains = <&gcc 2444 power-domains = <&gcc UFS_PHY_GDSC>;
2508 2445
2509 iommus = <&apps_smmu 2446 iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>;
2510 2447
2511 clock-names = 2448 clock-names =
2512 "core_clk", 2449 "core_clk",
2513 "bus_aggr_clk 2450 "bus_aggr_clk",
2514 "iface_clk", 2451 "iface_clk",
2515 "core_clk_uni 2452 "core_clk_unipro",
2516 "ref_clk", 2453 "ref_clk",
2517 "tx_lane0_syn 2454 "tx_lane0_sync_clk",
2518 "rx_lane0_syn 2455 "rx_lane0_sync_clk",
2519 "rx_lane1_syn 2456 "rx_lane1_sync_clk";
2520 clocks = 2457 clocks =
2521 <&gcc GCC_UFS 2458 <&gcc GCC_UFS_PHY_AXI_CLK>,
2522 <&gcc GCC_AGG 2459 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2523 <&gcc GCC_UFS 2460 <&gcc GCC_UFS_PHY_AHB_CLK>,
2524 <&gcc GCC_UFS 2461 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2525 <&rpmhcc RPMH 2462 <&rpmhcc RPMH_CXO_CLK>,
2526 <&gcc GCC_UFS 2463 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2527 <&gcc GCC_UFS 2464 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2528 <&gcc GCC_UFS 2465 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
2529 !! 2466 freq-table-hz =
2530 operating-points-v2 = !! 2467 <37500000 300000000>,
>> 2468 <0 0>,
>> 2469 <0 0>,
>> 2470 <37500000 300000000>,
>> 2471 <0 0>,
>> 2472 <0 0>,
>> 2473 <0 0>,
>> 2474 <0 0>;
2531 2475
2532 interconnects = <&agg 2476 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI_CH0 0>,
2533 <&gem 2477 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
2534 interconnect-names = 2478 interconnect-names = "ufs-ddr", "cpu-ufs";
2535 2479
2536 status = "disabled"; 2480 status = "disabled";
2537 <<
2538 ufs_opp_table: opp-ta <<
2539 compatible = <<
2540 <<
2541 opp-37500000 <<
2542 opp-h <<
2543 <<
2544 <<
2545 <<
2546 <<
2547 <<
2548 <<
2549 <<
2550 requi <<
2551 }; <<
2552 <<
2553 opp-300000000 <<
2554 opp-h <<
2555 <<
2556 <<
2557 <<
2558 <<
2559 <<
2560 <<
2561 <<
2562 requi <<
2563 }; <<
2564 }; <<
2565 }; 2481 };
2566 2482
2567 ufs_mem_phy: phy@1d87000 { 2483 ufs_mem_phy: phy@1d87000 {
2568 compatible = "qcom,sm 2484 compatible = "qcom,sm8250-qmp-ufs-phy";
2569 reg = <0 0x01d87000 0 !! 2485 reg = <0 0x01d87000 0 0x1c0>;
2570 !! 2486 #address-cells = <2>;
2571 clocks = <&rpmhcc RPM !! 2487 #size-cells = <2>;
2572 <&gcc GCC_UF !! 2488 ranges;
2573 <&gcc GCC_UF <<
2574 clock-names = "ref", 2489 clock-names = "ref",
2575 "ref_au !! 2490 "ref_aux";
2576 "qref"; !! 2491 clocks = <&rpmhcc RPMH_CXO_CLK>,
>> 2492 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2577 2493
2578 resets = <&ufs_mem_hc 2494 resets = <&ufs_mem_hc 0>;
2579 reset-names = "ufsphy 2495 reset-names = "ufsphy";
2580 <<
2581 power-domains = <&gcc <<
2582 <<
2583 #phy-cells = <0>; <<
2584 <<
2585 status = "disabled"; 2496 status = "disabled";
>> 2497
>> 2498 ufs_mem_phy_lanes: phy@1d87400 {
>> 2499 reg = <0 0x01d87400 0 0x16c>,
>> 2500 <0 0x01d87600 0 0x200>,
>> 2501 <0 0x01d87c00 0 0x200>,
>> 2502 <0 0x01d87800 0 0x16c>,
>> 2503 <0 0x01d87a00 0 0x200>;
>> 2504 #phy-cells = <0>;
>> 2505 };
2586 }; 2506 };
2587 2507
2588 cryptobam: dma-controller@1dc 2508 cryptobam: dma-controller@1dc4000 {
2589 compatible = "qcom,ba 2509 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
2590 reg = <0 0x01dc4000 0 2510 reg = <0 0x01dc4000 0 0x24000>;
2591 interrupts = <GIC_SPI 2511 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
2592 #dma-cells = <1>; 2512 #dma-cells = <1>;
2593 qcom,ee = <0>; 2513 qcom,ee = <0>;
2594 qcom,controlled-remot 2514 qcom,controlled-remotely;
2595 num-channels = <8>; 2515 num-channels = <8>;
2596 qcom,num-ees = <2>; 2516 qcom,num-ees = <2>;
2597 iommus = <&apps_smmu 2517 iommus = <&apps_smmu 0x592 0x0000>,
2598 <&apps_smmu 2518 <&apps_smmu 0x598 0x0000>,
2599 <&apps_smmu 2519 <&apps_smmu 0x599 0x0000>,
2600 <&apps_smmu 2520 <&apps_smmu 0x59f 0x0000>,
2601 <&apps_smmu 2521 <&apps_smmu 0x586 0x0011>,
2602 <&apps_smmu 2522 <&apps_smmu 0x596 0x0011>;
2603 }; 2523 };
2604 2524
2605 crypto: crypto@1dfa000 { 2525 crypto: crypto@1dfa000 {
2606 compatible = "qcom,sm 2526 compatible = "qcom,sm8250-qce", "qcom,sm8150-qce", "qcom,qce";
2607 reg = <0 0x01dfa000 0 2527 reg = <0 0x01dfa000 0 0x6000>;
2608 dmas = <&cryptobam 4> 2528 dmas = <&cryptobam 4>, <&cryptobam 5>;
2609 dma-names = "rx", "tx 2529 dma-names = "rx", "tx";
2610 iommus = <&apps_smmu 2530 iommus = <&apps_smmu 0x592 0x0000>,
2611 <&apps_smmu 2531 <&apps_smmu 0x598 0x0000>,
2612 <&apps_smmu 2532 <&apps_smmu 0x599 0x0000>,
2613 <&apps_smmu 2533 <&apps_smmu 0x59f 0x0000>,
2614 <&apps_smmu 2534 <&apps_smmu 0x586 0x0011>,
2615 <&apps_smmu 2535 <&apps_smmu 0x596 0x0011>;
2616 interconnects = <&agg 2536 interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 0 &mc_virt SLAVE_EBI_CH0 0>;
2617 interconnect-names = 2537 interconnect-names = "memory";
2618 }; 2538 };
2619 2539
2620 tcsr_mutex: hwlock@1f40000 { 2540 tcsr_mutex: hwlock@1f40000 {
2621 compatible = "qcom,tc 2541 compatible = "qcom,tcsr-mutex";
2622 reg = <0x0 0x01f40000 2542 reg = <0x0 0x01f40000 0x0 0x40000>;
2623 #hwlock-cells = <1>; 2543 #hwlock-cells = <1>;
2624 }; 2544 };
2625 2545
2626 tcsr: syscon@1fc0000 { <<
2627 compatible = "qcom,sm <<
2628 reg = <0x0 0x1fc0000 <<
2629 }; <<
2630 <<
2631 wsamacro: codec@3240000 { 2546 wsamacro: codec@3240000 {
2632 compatible = "qcom,sm 2547 compatible = "qcom,sm8250-lpass-wsa-macro";
2633 reg = <0 0x03240000 0 2548 reg = <0 0x03240000 0 0x1000>;
2634 clocks = <&q6afecc LP !! 2549 clocks = <&audiocc LPASS_CDC_WSA_MCLK>,
2635 <&q6afecc LP !! 2550 <&audiocc LPASS_CDC_WSA_NPL>,
2636 <&q6afecc LP 2551 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2637 <&q6afecc LP 2552 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 2553 <&aoncc LPASS_CDC_VA_MCLK>,
2638 <&vamacro>; 2554 <&vamacro>;
2639 2555
2640 clock-names = "mclk", !! 2556 clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen";
2641 2557
2642 #clock-cells = <0>; 2558 #clock-cells = <0>;
2643 clock-output-names = 2559 clock-output-names = "mclk";
2644 #sound-dai-cells = <1 2560 #sound-dai-cells = <1>;
2645 2561
2646 pinctrl-names = "defa 2562 pinctrl-names = "default";
2647 pinctrl-0 = <&wsa_swr 2563 pinctrl-0 = <&wsa_swr_active>;
2648 2564
2649 status = "disabled"; 2565 status = "disabled";
2650 }; 2566 };
2651 2567
2652 swr0: soundwire@3250000 { !! 2568 swr0: soundwire-controller@3250000 {
2653 reg = <0 0x03250000 0 2569 reg = <0 0x03250000 0 0x2000>;
2654 compatible = "qcom,so 2570 compatible = "qcom,soundwire-v1.5.1";
2655 interrupts = <GIC_SPI 2571 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
2656 clocks = <&wsamacro>; 2572 clocks = <&wsamacro>;
2657 clock-names = "iface" 2573 clock-names = "iface";
2658 2574
2659 qcom,din-ports = <2>; 2575 qcom,din-ports = <2>;
2660 qcom,dout-ports = <6> 2576 qcom,dout-ports = <6>;
2661 2577
2662 qcom,ports-sinterval- 2578 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2663 qcom,ports-offset1 = 2579 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2664 qcom,ports-offset2 = 2580 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2665 qcom,ports-block-pack 2581 qcom,ports-block-pack-mode = /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>;
2666 2582
2667 #sound-dai-cells = <1 2583 #sound-dai-cells = <1>;
2668 #address-cells = <2>; 2584 #address-cells = <2>;
2669 #size-cells = <0>; 2585 #size-cells = <0>;
2670 2586
2671 status = "disabled"; 2587 status = "disabled";
2672 }; 2588 };
2673 2589
>> 2590 audiocc: clock-controller@3300000 {
>> 2591 compatible = "qcom,sm8250-lpass-audiocc";
>> 2592 reg = <0 0x03300000 0 0x30000>;
>> 2593 #clock-cells = <1>;
>> 2594 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 2595 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 2596 <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
>> 2597 clock-names = "core", "audio", "bus";
>> 2598 };
>> 2599
2674 vamacro: codec@3370000 { 2600 vamacro: codec@3370000 {
2675 compatible = "qcom,sm 2601 compatible = "qcom,sm8250-lpass-va-macro";
2676 reg = <0 0x03370000 0 2602 reg = <0 0x03370000 0 0x1000>;
2677 clocks = <&q6afecc LP !! 2603 clocks = <&aoncc LPASS_CDC_VA_MCLK>,
2678 <&q6afecc LPA 2604 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2679 <&q6afecc LPA 2605 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2680 2606
2681 clock-names = "mclk", 2607 clock-names = "mclk", "macro", "dcodec";
2682 2608
2683 #clock-cells = <0>; 2609 #clock-cells = <0>;
2684 clock-output-names = 2610 clock-output-names = "fsgen";
2685 #sound-dai-cells = <1 2611 #sound-dai-cells = <1>;
2686 }; 2612 };
2687 2613
2688 rxmacro: rxmacro@3200000 { 2614 rxmacro: rxmacro@3200000 {
2689 pinctrl-names = "defa 2615 pinctrl-names = "default";
2690 pinctrl-0 = <&rx_swr_ 2616 pinctrl-0 = <&rx_swr_active>;
2691 compatible = "qcom,sm 2617 compatible = "qcom,sm8250-lpass-rx-macro";
2692 reg = <0 0x03200000 0 2618 reg = <0 0x03200000 0 0x1000>;
2693 status = "disabled"; 2619 status = "disabled";
2694 2620
2695 clocks = <&q6afecc LP 2621 clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2696 <&q6afecc LPA 2622 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2697 <&q6afecc LPA 2623 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2698 <&q6afecc LPA 2624 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2699 <&vamacro>; 2625 <&vamacro>;
2700 2626
2701 clock-names = "mclk", 2627 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2702 2628
2703 #clock-cells = <0>; 2629 #clock-cells = <0>;
2704 clock-output-names = 2630 clock-output-names = "mclk";
2705 #sound-dai-cells = <1 2631 #sound-dai-cells = <1>;
2706 }; 2632 };
2707 2633
2708 swr1: soundwire@3210000 { !! 2634 swr1: soundwire-controller@3210000 {
2709 reg = <0 0x03210000 0 2635 reg = <0 0x03210000 0 0x2000>;
2710 compatible = "qcom,so 2636 compatible = "qcom,soundwire-v1.5.1";
2711 status = "disabled"; 2637 status = "disabled";
2712 interrupts = <GIC_SPI 2638 interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
2713 clocks = <&rxmacro>; 2639 clocks = <&rxmacro>;
2714 clock-names = "iface" 2640 clock-names = "iface";
2715 label = "RX"; 2641 label = "RX";
2716 qcom,din-ports = <0>; 2642 qcom,din-ports = <0>;
2717 qcom,dout-ports = <5> 2643 qcom,dout-ports = <5>;
2718 2644
2719 qcom,ports-sinterval- 2645 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
2720 qcom,ports-offset1 = 2646 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>;
2721 qcom,ports-offset2 = 2647 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
2722 qcom,ports-hstart = 2648 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
2723 qcom,ports-hstop = 2649 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
2724 qcom,ports-word-lengt 2650 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2725 qcom,ports-block-pack 2651 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
2726 qcom,ports-lane-contr 2652 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2727 qcom,ports-block-grou 2653 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
2728 2654
2729 #sound-dai-cells = <1 2655 #sound-dai-cells = <1>;
2730 #address-cells = <2>; 2656 #address-cells = <2>;
2731 #size-cells = <0>; 2657 #size-cells = <0>;
2732 }; 2658 };
2733 2659
2734 txmacro: txmacro@3220000 { 2660 txmacro: txmacro@3220000 {
2735 pinctrl-names = "defa 2661 pinctrl-names = "default";
2736 pinctrl-0 = <&tx_swr_ 2662 pinctrl-0 = <&tx_swr_active>;
2737 compatible = "qcom,sm 2663 compatible = "qcom,sm8250-lpass-tx-macro";
2738 reg = <0 0x03220000 0 2664 reg = <0 0x03220000 0 0x1000>;
2739 status = "disabled"; 2665 status = "disabled";
2740 2666
2741 clocks = <&q6afecc LP 2667 clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2742 <&q6afecc LP 2668 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2743 <&q6afecc LP 2669 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2744 <&q6afecc LP 2670 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2745 <&vamacro>; 2671 <&vamacro>;
2746 2672
2747 clock-names = "mclk", 2673 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2748 2674
2749 #clock-cells = <0>; 2675 #clock-cells = <0>;
2750 clock-output-names = 2676 clock-output-names = "mclk";
2751 #sound-dai-cells = <1 2677 #sound-dai-cells = <1>;
2752 }; 2678 };
2753 2679
2754 /* tx macro */ 2680 /* tx macro */
2755 swr2: soundwire@3230000 { !! 2681 swr2: soundwire-controller@3230000 {
2756 reg = <0 0x03230000 0 2682 reg = <0 0x03230000 0 0x2000>;
2757 compatible = "qcom,so 2683 compatible = "qcom,soundwire-v1.5.1";
2758 interrupts = <GIC_SPI 2684 interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
2759 interrupt-names = "co 2685 interrupt-names = "core";
2760 status = "disabled"; 2686 status = "disabled";
2761 2687
2762 clocks = <&txmacro>; 2688 clocks = <&txmacro>;
2763 clock-names = "iface" 2689 clock-names = "iface";
2764 label = "TX"; 2690 label = "TX";
2765 2691
2766 qcom,din-ports = <5>; 2692 qcom,din-ports = <5>;
2767 qcom,dout-ports = <0> 2693 qcom,dout-ports = <0>;
2768 qcom,ports-sinterval- 2694 qcom,ports-sinterval-low = /bits/ 8 <0xff 0x01 0x01 0x03 0x03>;
2769 qcom,ports-offset1 = 2695 qcom,ports-offset1 = /bits/ 8 <0xff 0x01 0x00 0x02 0x00>;
2770 qcom,ports-offset2 = 2696 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x00 0x00 0x00>;
2771 qcom,ports-block-pack 2697 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2772 qcom,ports-hstart = 2698 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2773 qcom,ports-hstop = 2699 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2774 qcom,ports-word-lengt 2700 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2775 qcom,ports-block-grou 2701 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2776 qcom,ports-lane-contr 2702 qcom,ports-lane-control = /bits/ 8 <0xff 0x00 0x01 0x00 0x01>;
2777 #sound-dai-cells = <1 2703 #sound-dai-cells = <1>;
2778 #address-cells = <2>; 2704 #address-cells = <2>;
2779 #size-cells = <0>; 2705 #size-cells = <0>;
2780 }; 2706 };
2781 2707
>> 2708 aoncc: clock-controller@3380000 {
>> 2709 compatible = "qcom,sm8250-lpass-aoncc";
>> 2710 reg = <0 0x03380000 0 0x40000>;
>> 2711 #clock-cells = <1>;
>> 2712 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 2713 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 2714 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
>> 2715 clock-names = "core", "audio", "bus";
>> 2716 };
>> 2717
2782 lpass_tlmm: pinctrl@33c0000 { 2718 lpass_tlmm: pinctrl@33c0000 {
2783 compatible = "qcom,sm 2719 compatible = "qcom,sm8250-lpass-lpi-pinctrl";
2784 reg = <0 0x033c0000 0 2720 reg = <0 0x033c0000 0x0 0x20000>,
2785 <0 0x03550000 0 2721 <0 0x03550000 0x0 0x10000>;
2786 gpio-controller; 2722 gpio-controller;
2787 #gpio-cells = <2>; 2723 #gpio-cells = <2>;
2788 gpio-ranges = <&lpass 2724 gpio-ranges = <&lpass_tlmm 0 0 14>;
2789 2725
2790 clocks = <&q6afecc LP 2726 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2791 <&q6afecc LPA 2727 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2792 clock-names = "core", 2728 clock-names = "core", "audio";
2793 2729
2794 wsa_swr_active: wsa-s 2730 wsa_swr_active: wsa-swr-active-state {
2795 clk-pins { 2731 clk-pins {
2796 pins 2732 pins = "gpio10";
2797 funct 2733 function = "wsa_swr_clk";
2798 drive 2734 drive-strength = <2>;
2799 slew- 2735 slew-rate = <1>;
2800 bias- 2736 bias-disable;
2801 }; 2737 };
2802 2738
2803 data-pins { 2739 data-pins {
2804 pins 2740 pins = "gpio11";
2805 funct 2741 function = "wsa_swr_data";
2806 drive 2742 drive-strength = <2>;
2807 slew- 2743 slew-rate = <1>;
2808 bias- 2744 bias-bus-hold;
2809 }; 2745 };
2810 }; 2746 };
2811 2747
2812 wsa_swr_sleep: wsa-sw 2748 wsa_swr_sleep: wsa-swr-sleep-state {
2813 clk-pins { 2749 clk-pins {
2814 pins 2750 pins = "gpio10";
2815 funct 2751 function = "wsa_swr_clk";
2816 drive 2752 drive-strength = <2>;
2817 bias- 2753 bias-pull-down;
2818 }; 2754 };
2819 2755
2820 data-pins { 2756 data-pins {
2821 pins 2757 pins = "gpio11";
2822 funct 2758 function = "wsa_swr_data";
2823 drive 2759 drive-strength = <2>;
2824 bias- 2760 bias-pull-down;
2825 }; 2761 };
2826 }; 2762 };
2827 2763
2828 dmic01_active: dmic01 2764 dmic01_active: dmic01-active-state {
2829 clk-pins { 2765 clk-pins {
2830 pins 2766 pins = "gpio6";
2831 funct 2767 function = "dmic1_clk";
2832 drive 2768 drive-strength = <8>;
2833 outpu 2769 output-high;
2834 }; 2770 };
2835 data-pins { 2771 data-pins {
2836 pins 2772 pins = "gpio7";
2837 funct 2773 function = "dmic1_data";
2838 drive 2774 drive-strength = <8>;
2839 }; 2775 };
2840 }; 2776 };
2841 2777
2842 dmic01_sleep: dmic01- 2778 dmic01_sleep: dmic01-sleep-state {
2843 clk-pins { 2779 clk-pins {
2844 pins 2780 pins = "gpio6";
2845 funct 2781 function = "dmic1_clk";
2846 drive 2782 drive-strength = <2>;
2847 bias- 2783 bias-disable;
2848 outpu 2784 output-low;
2849 }; 2785 };
2850 2786
2851 data-pins { 2787 data-pins {
2852 pins 2788 pins = "gpio7";
2853 funct 2789 function = "dmic1_data";
2854 drive 2790 drive-strength = <2>;
2855 bias- 2791 bias-pull-down;
2856 }; 2792 };
2857 }; 2793 };
2858 2794
2859 rx_swr_active: rx-swr 2795 rx_swr_active: rx-swr-active-state {
2860 clk-pins { 2796 clk-pins {
2861 pins 2797 pins = "gpio3";
2862 funct 2798 function = "swr_rx_clk";
2863 drive 2799 drive-strength = <2>;
2864 slew- 2800 slew-rate = <1>;
2865 bias- 2801 bias-disable;
2866 }; 2802 };
2867 2803
2868 data-pins { 2804 data-pins {
2869 pins 2805 pins = "gpio4", "gpio5";
2870 funct 2806 function = "swr_rx_data";
2871 drive 2807 drive-strength = <2>;
2872 slew- 2808 slew-rate = <1>;
2873 bias- 2809 bias-bus-hold;
2874 }; 2810 };
2875 }; 2811 };
2876 2812
2877 tx_swr_active: tx-swr 2813 tx_swr_active: tx-swr-active-state {
2878 clk-pins { 2814 clk-pins {
2879 pins 2815 pins = "gpio0";
2880 funct 2816 function = "swr_tx_clk";
2881 drive 2817 drive-strength = <2>;
2882 slew- 2818 slew-rate = <1>;
2883 bias- 2819 bias-disable;
2884 }; 2820 };
2885 2821
2886 data-pins { 2822 data-pins {
2887 pins 2823 pins = "gpio1", "gpio2";
2888 funct 2824 function = "swr_tx_data";
2889 drive 2825 drive-strength = <2>;
2890 slew- 2826 slew-rate = <1>;
2891 bias- 2827 bias-bus-hold;
2892 }; 2828 };
2893 }; 2829 };
2894 2830
2895 tx_swr_sleep: tx-swr- 2831 tx_swr_sleep: tx-swr-sleep-state {
2896 clk-pins { 2832 clk-pins {
2897 pins 2833 pins = "gpio0";
2898 funct 2834 function = "swr_tx_clk";
2899 drive 2835 drive-strength = <2>;
2900 bias- 2836 bias-pull-down;
2901 }; 2837 };
2902 2838
2903 data1-pins { 2839 data1-pins {
2904 pins 2840 pins = "gpio1";
2905 funct 2841 function = "swr_tx_data";
2906 drive 2842 drive-strength = <2>;
2907 bias- 2843 bias-bus-hold;
2908 }; 2844 };
2909 2845
2910 data2-pins { 2846 data2-pins {
2911 pins 2847 pins = "gpio2";
2912 funct 2848 function = "swr_tx_data";
2913 drive 2849 drive-strength = <2>;
2914 bias- 2850 bias-pull-down;
2915 }; 2851 };
2916 }; 2852 };
2917 }; 2853 };
2918 2854
2919 gpu: gpu@3d00000 { 2855 gpu: gpu@3d00000 {
2920 compatible = "qcom,ad 2856 compatible = "qcom,adreno-650.2",
2921 "qcom,ad 2857 "qcom,adreno";
2922 2858
2923 reg = <0 0x03d00000 0 2859 reg = <0 0x03d00000 0 0x40000>;
2924 reg-names = "kgsl_3d0 2860 reg-names = "kgsl_3d0_reg_memory";
2925 2861
2926 interrupts = <GIC_SPI 2862 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2927 2863
2928 iommus = <&adreno_smm 2864 iommus = <&adreno_smmu 0 0x401>;
2929 2865
2930 operating-points-v2 = 2866 operating-points-v2 = <&gpu_opp_table>;
2931 2867
2932 qcom,gmu = <&gmu>; 2868 qcom,gmu = <&gmu>;
2933 2869
2934 nvmem-cells = <&gpu_s 2870 nvmem-cells = <&gpu_speed_bin>;
2935 nvmem-cell-names = "s 2871 nvmem-cell-names = "speed_bin";
2936 #cooling-cells = <2>; <<
2937 2872
2938 status = "disabled"; 2873 status = "disabled";
2939 2874
2940 zap-shader { 2875 zap-shader {
2941 memory-region 2876 memory-region = <&gpu_mem>;
2942 }; 2877 };
2943 2878
2944 gpu_opp_table: opp-ta 2879 gpu_opp_table: opp-table {
2945 compatible = 2880 compatible = "operating-points-v2";
2946 2881
2947 opp-670000000 2882 opp-670000000 {
2948 opp-h 2883 opp-hz = /bits/ 64 <670000000>;
2949 opp-l 2884 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2950 opp-s 2885 opp-supported-hw = <0xa>;
2951 }; 2886 };
2952 2887
2953 opp-587000000 2888 opp-587000000 {
2954 opp-h 2889 opp-hz = /bits/ 64 <587000000>;
2955 opp-l 2890 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2956 opp-s 2891 opp-supported-hw = <0xb>;
2957 }; 2892 };
2958 2893
2959 opp-525000000 2894 opp-525000000 {
2960 opp-h 2895 opp-hz = /bits/ 64 <525000000>;
2961 opp-l 2896 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2962 opp-s 2897 opp-supported-hw = <0xf>;
2963 }; 2898 };
2964 2899
2965 opp-490000000 2900 opp-490000000 {
2966 opp-h 2901 opp-hz = /bits/ 64 <490000000>;
2967 opp-l 2902 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2968 opp-s 2903 opp-supported-hw = <0xf>;
2969 }; 2904 };
2970 2905
2971 opp-441600000 2906 opp-441600000 {
2972 opp-h 2907 opp-hz = /bits/ 64 <441600000>;
2973 opp-l 2908 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
2974 opp-s 2909 opp-supported-hw = <0xf>;
2975 }; 2910 };
2976 2911
2977 opp-400000000 2912 opp-400000000 {
2978 opp-h 2913 opp-hz = /bits/ 64 <400000000>;
2979 opp-l 2914 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2980 opp-s 2915 opp-supported-hw = <0xf>;
2981 }; 2916 };
2982 2917
2983 opp-305000000 2918 opp-305000000 {
2984 opp-h 2919 opp-hz = /bits/ 64 <305000000>;
2985 opp-l 2920 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2986 opp-s 2921 opp-supported-hw = <0xf>;
2987 }; 2922 };
2988 }; 2923 };
2989 }; 2924 };
2990 2925
2991 gmu: gmu@3d6a000 { 2926 gmu: gmu@3d6a000 {
2992 compatible = "qcom,ad 2927 compatible = "qcom,adreno-gmu-650.2", "qcom,adreno-gmu";
2993 2928
2994 reg = <0 0x03d6a000 0 2929 reg = <0 0x03d6a000 0 0x30000>,
2995 <0 0x3de0000 0 2930 <0 0x3de0000 0 0x10000>,
2996 <0 0xb290000 0 2931 <0 0xb290000 0 0x10000>,
2997 <0 0xb490000 0 2932 <0 0xb490000 0 0x10000>;
2998 reg-names = "gmu", "r 2933 reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq";
2999 2934
3000 interrupts = <GIC_SPI 2935 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
3001 <GIC_SPI 2936 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
3002 interrupt-names = "hf 2937 interrupt-names = "hfi", "gmu";
3003 2938
3004 clocks = <&gpucc GPU_ 2939 clocks = <&gpucc GPU_CC_AHB_CLK>,
3005 <&gpucc GPU_ 2940 <&gpucc GPU_CC_CX_GMU_CLK>,
3006 <&gpucc GPU_ 2941 <&gpucc GPU_CC_CXO_CLK>,
3007 <&gcc GCC_DD 2942 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
3008 <&gcc GCC_GP 2943 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
3009 clock-names = "ahb", 2944 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
3010 2945
3011 power-domains = <&gpu 2946 power-domains = <&gpucc GPU_CX_GDSC>,
3012 <&gpu 2947 <&gpucc GPU_GX_GDSC>;
3013 power-domain-names = 2948 power-domain-names = "cx", "gx";
3014 2949
3015 iommus = <&adreno_smm 2950 iommus = <&adreno_smmu 5 0x400>;
3016 2951
3017 operating-points-v2 = 2952 operating-points-v2 = <&gmu_opp_table>;
3018 2953
3019 status = "disabled"; 2954 status = "disabled";
3020 2955
3021 gmu_opp_table: opp-ta 2956 gmu_opp_table: opp-table {
3022 compatible = 2957 compatible = "operating-points-v2";
3023 2958
3024 opp-200000000 2959 opp-200000000 {
3025 opp-h 2960 opp-hz = /bits/ 64 <200000000>;
3026 opp-l 2961 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3027 }; 2962 };
3028 }; 2963 };
3029 }; 2964 };
3030 2965
3031 gpucc: clock-controller@3d900 2966 gpucc: clock-controller@3d90000 {
3032 compatible = "qcom,sm 2967 compatible = "qcom,sm8250-gpucc";
3033 reg = <0 0x03d90000 0 2968 reg = <0 0x03d90000 0 0x9000>;
3034 clocks = <&rpmhcc RPM 2969 clocks = <&rpmhcc RPMH_CXO_CLK>,
3035 <&gcc GCC_GP 2970 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
3036 <&gcc GCC_GP 2971 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
3037 clock-names = "bi_tcx 2972 clock-names = "bi_tcxo",
3038 "gcc_gp 2973 "gcc_gpu_gpll0_clk_src",
3039 "gcc_gp 2974 "gcc_gpu_gpll0_div_clk_src";
3040 #clock-cells = <1>; 2975 #clock-cells = <1>;
3041 #reset-cells = <1>; 2976 #reset-cells = <1>;
3042 #power-domain-cells = 2977 #power-domain-cells = <1>;
3043 }; 2978 };
3044 2979
3045 adreno_smmu: iommu@3da0000 { 2980 adreno_smmu: iommu@3da0000 {
3046 compatible = "qcom,sm 2981 compatible = "qcom,sm8250-smmu-500", "qcom,adreno-smmu",
3047 "qcom,sm 2982 "qcom,smmu-500", "arm,mmu-500";
3048 reg = <0 0x03da0000 0 2983 reg = <0 0x03da0000 0 0x10000>;
3049 #iommu-cells = <2>; 2984 #iommu-cells = <2>;
3050 #global-interrupts = 2985 #global-interrupts = <2>;
3051 interrupts = <GIC_SPI 2986 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
3052 <GIC_SPI 2987 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
3053 <GIC_SPI 2988 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
3054 <GIC_SPI 2989 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
3055 <GIC_SPI 2990 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
3056 <GIC_SPI 2991 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
3057 <GIC_SPI 2992 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
3058 <GIC_SPI 2993 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
3059 <GIC_SPI 2994 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
3060 <GIC_SPI 2995 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>;
3061 clocks = <&gpucc GPU_ 2996 clocks = <&gpucc GPU_CC_AHB_CLK>,
3062 <&gcc GCC_GP 2997 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
3063 <&gcc GCC_GP 2998 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
3064 clock-names = "ahb", 2999 clock-names = "ahb", "bus", "iface";
3065 3000
3066 power-domains = <&gpu 3001 power-domains = <&gpucc GPU_CX_GDSC>;
3067 dma-coherent; 3002 dma-coherent;
3068 }; 3003 };
3069 3004
3070 slpi: remoteproc@5c00000 { 3005 slpi: remoteproc@5c00000 {
3071 compatible = "qcom,sm 3006 compatible = "qcom,sm8250-slpi-pas";
3072 reg = <0 0x05c00000 0 3007 reg = <0 0x05c00000 0 0x4000>;
3073 3008
3074 interrupts-extended = !! 3009 interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
3075 3010 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
3076 3011 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
3077 3012 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
3078 3013 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
3079 interrupt-names = "wd 3014 interrupt-names = "wdog", "fatal", "ready",
3080 "ha 3015 "handover", "stop-ack";
3081 3016
3082 clocks = <&rpmhcc RPM 3017 clocks = <&rpmhcc RPMH_CXO_CLK>;
3083 clock-names = "xo"; 3018 clock-names = "xo";
3084 3019
3085 power-domains = <&rpm 3020 power-domains = <&rpmhpd RPMHPD_LCX>,
3086 <&rpm 3021 <&rpmhpd RPMHPD_LMX>;
3087 power-domain-names = 3022 power-domain-names = "lcx", "lmx";
3088 3023
3089 memory-region = <&slp 3024 memory-region = <&slpi_mem>;
3090 3025
3091 qcom,qmp = <&aoss_qmp 3026 qcom,qmp = <&aoss_qmp>;
3092 3027
3093 qcom,smem-states = <& 3028 qcom,smem-states = <&smp2p_slpi_out 0>;
3094 qcom,smem-state-names 3029 qcom,smem-state-names = "stop";
3095 3030
3096 status = "disabled"; 3031 status = "disabled";
3097 3032
3098 glink-edge { 3033 glink-edge {
3099 interrupts-ex 3034 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
3100 3035 IPCC_MPROC_SIGNAL_GLINK_QMP
3101 3036 IRQ_TYPE_EDGE_RISING>;
3102 mboxes = <&ip 3037 mboxes = <&ipcc IPCC_CLIENT_SLPI
3103 3038 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3104 3039
3105 label = "slpi 3040 label = "slpi";
3106 qcom,remote-p 3041 qcom,remote-pid = <3>;
3107 3042
3108 fastrpc { 3043 fastrpc {
3109 compa 3044 compatible = "qcom,fastrpc";
3110 qcom, 3045 qcom,glink-channels = "fastrpcglink-apps-dsp";
3111 label 3046 label = "sdsp";
3112 qcom, 3047 qcom,non-secure-domain;
3113 #addr 3048 #address-cells = <1>;
3114 #size 3049 #size-cells = <0>;
3115 3050
3116 compu 3051 compute-cb@1 {
3117 3052 compatible = "qcom,fastrpc-compute-cb";
3118 3053 reg = <1>;
3119 3054 iommus = <&apps_smmu 0x0541 0x0>;
3120 }; 3055 };
3121 3056
3122 compu 3057 compute-cb@2 {
3123 3058 compatible = "qcom,fastrpc-compute-cb";
3124 3059 reg = <2>;
3125 3060 iommus = <&apps_smmu 0x0542 0x0>;
3126 }; 3061 };
3127 3062
3128 compu 3063 compute-cb@3 {
3129 3064 compatible = "qcom,fastrpc-compute-cb";
3130 3065 reg = <3>;
3131 3066 iommus = <&apps_smmu 0x0543 0x0>;
3132 3067 /* note: shared-cb = <4> in downstream */
3133 }; 3068 };
3134 }; 3069 };
3135 }; 3070 };
3136 }; 3071 };
3137 3072
3138 stm@6002000 { 3073 stm@6002000 {
3139 compatible = "arm,cor 3074 compatible = "arm,coresight-stm", "arm,primecell";
3140 reg = <0 0x06002000 0 3075 reg = <0 0x06002000 0 0x1000>, <0 0x16280000 0 0x180000>;
3141 reg-names = "stm-base 3076 reg-names = "stm-base", "stm-stimulus-base";
3142 3077
3143 clocks = <&aoss_qmp>; 3078 clocks = <&aoss_qmp>;
3144 clock-names = "apb_pc 3079 clock-names = "apb_pclk";
3145 3080
3146 out-ports { 3081 out-ports {
3147 port { 3082 port {
3148 stm_o 3083 stm_out: endpoint {
3149 3084 remote-endpoint = <&funnel0_in7>;
3150 }; 3085 };
3151 }; 3086 };
3152 }; 3087 };
3153 }; 3088 };
3154 3089
3155 tpda@6004000 { 3090 tpda@6004000 {
3156 compatible = "qcom,co 3091 compatible = "qcom,coresight-tpda", "arm,primecell";
3157 reg = <0 0x06004000 0 3092 reg = <0 0x06004000 0 0x1000>;
3158 3093
3159 clocks = <&aoss_qmp>; 3094 clocks = <&aoss_qmp>;
3160 clock-names = "apb_pc 3095 clock-names = "apb_pclk";
3161 3096
3162 out-ports { 3097 out-ports {
3163 3098
3164 port { 3099 port {
3165 tpda_ 3100 tpda_out_funnel_qatb: endpoint {
3166 3101 remote-endpoint = <&funnel_qatb_in_tpda>;
3167 }; 3102 };
3168 }; 3103 };
3169 }; 3104 };
3170 3105
3171 in-ports { 3106 in-ports {
3172 #address-cell 3107 #address-cells = <1>;
3173 #size-cells = 3108 #size-cells = <0>;
3174 3109
3175 port@9 { 3110 port@9 {
3176 reg = 3111 reg = <9>;
3177 tpda_ 3112 tpda_9_in_tpdm_mm: endpoint {
3178 3113 remote-endpoint = <&tpdm_mm_out_tpda9>;
3179 }; 3114 };
3180 }; 3115 };
3181 3116
3182 port@17 { 3117 port@17 {
3183 reg = 3118 reg = <23>;
3184 tpda_ 3119 tpda_23_in_tpdm_prng: endpoint {
3185 3120 remote-endpoint = <&tpdm_prng_out_tpda_23>;
3186 }; 3121 };
3187 }; 3122 };
3188 }; 3123 };
3189 }; 3124 };
3190 3125
3191 funnel@6005000 { 3126 funnel@6005000 {
3192 compatible = "arm,cor 3127 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3193 reg = <0 0x06005000 0 3128 reg = <0 0x06005000 0 0x1000>;
3194 3129
3195 clocks = <&aoss_qmp>; 3130 clocks = <&aoss_qmp>;
3196 clock-names = "apb_pc 3131 clock-names = "apb_pclk";
3197 3132
3198 out-ports { 3133 out-ports {
3199 port { 3134 port {
3200 funne 3135 funnel_qatb_out_funnel_in0: endpoint {
3201 3136 remote-endpoint = <&funnel_in0_in_funnel_qatb>;
3202 }; 3137 };
3203 }; 3138 };
3204 }; 3139 };
3205 3140
3206 in-ports { 3141 in-ports {
3207 port { 3142 port {
3208 funne 3143 funnel_qatb_in_tpda: endpoint {
3209 3144 remote-endpoint = <&tpda_out_funnel_qatb>;
3210 }; 3145 };
3211 }; 3146 };
3212 }; 3147 };
3213 }; 3148 };
3214 3149
3215 funnel@6041000 { 3150 funnel@6041000 {
3216 compatible = "arm,cor 3151 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3217 reg = <0 0x06041000 0 3152 reg = <0 0x06041000 0 0x1000>;
3218 3153
3219 clocks = <&aoss_qmp>; 3154 clocks = <&aoss_qmp>;
3220 clock-names = "apb_pc 3155 clock-names = "apb_pclk";
3221 3156
3222 out-ports { 3157 out-ports {
3223 port { 3158 port {
3224 funne 3159 funnel_in0_out_funnel_merg: endpoint {
3225 3160 remote-endpoint = <&funnel_merg_in_funnel_in0>;
3226 }; 3161 };
3227 }; 3162 };
3228 }; 3163 };
3229 3164
3230 in-ports { 3165 in-ports {
3231 #address-cell 3166 #address-cells = <1>;
3232 #size-cells = 3167 #size-cells = <0>;
3233 3168
3234 port@6 { 3169 port@6 {
3235 reg = 3170 reg = <6>;
3236 funne 3171 funnel_in0_in_funnel_qatb: endpoint {
3237 3172 remote-endpoint = <&funnel_qatb_out_funnel_in0>;
3238 }; 3173 };
3239 }; 3174 };
3240 3175
3241 port@7 { 3176 port@7 {
3242 reg = 3177 reg = <7>;
3243 funne 3178 funnel0_in7: endpoint {
3244 3179 remote-endpoint = <&stm_out>;
3245 }; 3180 };
3246 }; 3181 };
3247 }; 3182 };
3248 }; 3183 };
3249 3184
3250 funnel@6042000 { 3185 funnel@6042000 {
3251 compatible = "arm,cor 3186 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3252 reg = <0 0x06042000 0 3187 reg = <0 0x06042000 0 0x1000>;
3253 3188
3254 clocks = <&aoss_qmp>; 3189 clocks = <&aoss_qmp>;
3255 clock-names = "apb_pc 3190 clock-names = "apb_pclk";
3256 3191
3257 out-ports { 3192 out-ports {
3258 port { 3193 port {
3259 funne 3194 funnel_in1_out_funnel_merg: endpoint {
3260 3195 remote-endpoint = <&funnel_merg_in_funnel_in1>;
3261 }; 3196 };
3262 }; 3197 };
3263 }; 3198 };
3264 3199
3265 in-ports { 3200 in-ports {
3266 #address-cell 3201 #address-cells = <1>;
3267 #size-cells = 3202 #size-cells = <0>;
3268 3203
3269 port@4 { 3204 port@4 {
3270 reg = 3205 reg = <4>;
3271 funne 3206 funnel_in1_in_funnel_apss_merg: endpoint {
3272 remot 3207 remote-endpoint = <&funnel_apss_merg_out_funnel_in1>;
3273 }; 3208 };
3274 }; 3209 };
3275 }; 3210 };
3276 }; 3211 };
3277 3212
3278 funnel@6045000 { 3213 funnel@6045000 {
3279 compatible = "arm,cor 3214 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3280 reg = <0 0x06045000 0 3215 reg = <0 0x06045000 0 0x1000>;
3281 3216
3282 clocks = <&aoss_qmp>; 3217 clocks = <&aoss_qmp>;
3283 clock-names = "apb_pc 3218 clock-names = "apb_pclk";
3284 3219
3285 out-ports { 3220 out-ports {
3286 port { 3221 port {
3287 funne 3222 funnel_merg_out_funnel_swao: endpoint {
3288 remot 3223 remote-endpoint = <&funnel_swao_in_funnel_merg>;
3289 }; 3224 };
3290 }; 3225 };
3291 }; 3226 };
3292 3227
3293 in-ports { 3228 in-ports {
3294 #address-cell 3229 #address-cells = <1>;
3295 #size-cells = 3230 #size-cells = <0>;
3296 3231
3297 port@0 { 3232 port@0 {
3298 reg = 3233 reg = <0>;
3299 funne 3234 funnel_merg_in_funnel_in0: endpoint {
3300 remot 3235 remote-endpoint = <&funnel_in0_out_funnel_merg>;
3301 }; 3236 };
3302 }; 3237 };
3303 3238
3304 port@1 { 3239 port@1 {
3305 reg = 3240 reg = <1>;
3306 funne 3241 funnel_merg_in_funnel_in1: endpoint {
3307 remot 3242 remote-endpoint = <&funnel_in1_out_funnel_merg>;
3308 }; 3243 };
3309 }; 3244 };
3310 }; 3245 };
3311 }; 3246 };
3312 3247
3313 replicator@6046000 { 3248 replicator@6046000 {
3314 compatible = "arm,cor 3249 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3315 reg = <0 0x06046000 0 3250 reg = <0 0x06046000 0 0x1000>;
3316 3251
3317 clocks = <&aoss_qmp>; 3252 clocks = <&aoss_qmp>;
3318 clock-names = "apb_pc 3253 clock-names = "apb_pclk";
3319 3254
3320 out-ports { 3255 out-ports {
3321 port { 3256 port {
3322 repli 3257 replicator_out: endpoint {
3323 3258 remote-endpoint = <&etr_in>;
3324 }; 3259 };
3325 }; 3260 };
3326 }; 3261 };
3327 3262
3328 in-ports { 3263 in-ports {
3329 port { 3264 port {
3330 repli 3265 replicator_cx_in_swao_out: endpoint {
3331 3266 remote-endpoint = <&replicator_swao_out_cx_in>;
3332 }; 3267 };
3333 }; 3268 };
3334 }; 3269 };
3335 }; 3270 };
3336 3271
3337 etr@6048000 { 3272 etr@6048000 {
3338 compatible = "arm,cor 3273 compatible = "arm,coresight-tmc", "arm,primecell";
3339 reg = <0 0x06048000 0 3274 reg = <0 0x06048000 0 0x1000>;
3340 3275
3341 clocks = <&aoss_qmp>; 3276 clocks = <&aoss_qmp>;
3342 clock-names = "apb_pc 3277 clock-names = "apb_pclk";
3343 arm,scatter-gather; 3278 arm,scatter-gather;
3344 3279
3345 in-ports { 3280 in-ports {
3346 port { 3281 port {
3347 etr_i 3282 etr_in: endpoint {
3348 3283 remote-endpoint = <&replicator_out>;
3349 }; 3284 };
3350 }; 3285 };
3351 }; 3286 };
3352 }; 3287 };
3353 3288
3354 tpdm@684c000 { 3289 tpdm@684c000 {
3355 compatible = "qcom,co 3290 compatible = "qcom,coresight-tpdm", "arm,primecell";
3356 reg = <0 0x0684c000 0 3291 reg = <0 0x0684c000 0 0x1000>;
3357 3292
3358 clocks = <&aoss_qmp>; 3293 clocks = <&aoss_qmp>;
3359 clock-names = "apb_pc 3294 clock-names = "apb_pclk";
3360 3295
3361 out-ports { 3296 out-ports {
3362 port { 3297 port {
3363 tpdm_ 3298 tpdm_prng_out_tpda_23: endpoint {
3364 3299 remote-endpoint = <&tpda_23_in_tpdm_prng>;
3365 }; 3300 };
3366 }; 3301 };
3367 }; 3302 };
3368 }; 3303 };
3369 3304
3370 funnel@6b04000 { 3305 funnel@6b04000 {
3371 compatible = "arm,cor 3306 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3372 arm,primecell-periphi 3307 arm,primecell-periphid = <0x000bb908>;
3373 3308
3374 reg = <0 0x06b04000 0 3309 reg = <0 0x06b04000 0 0x1000>;
3375 3310
3376 clocks = <&aoss_qmp>; 3311 clocks = <&aoss_qmp>;
3377 clock-names = "apb_pc 3312 clock-names = "apb_pclk";
3378 3313
3379 out-ports { 3314 out-ports {
3380 port { 3315 port {
3381 funne 3316 funnel_swao_out_etf: endpoint {
3382 3317 remote-endpoint = <&etf_in_funnel_swao_out>;
3383 }; 3318 };
3384 }; 3319 };
3385 }; 3320 };
3386 3321
3387 in-ports { 3322 in-ports {
3388 #address-cell 3323 #address-cells = <1>;
3389 #size-cells = 3324 #size-cells = <0>;
3390 3325
3391 port@7 { 3326 port@7 {
3392 reg = 3327 reg = <7>;
3393 funne 3328 funnel_swao_in_funnel_merg: endpoint {
3394 3329 remote-endpoint = <&funnel_merg_out_funnel_swao>;
3395 }; 3330 };
3396 }; 3331 };
3397 }; 3332 };
3398 }; 3333 };
3399 3334
3400 etf@6b05000 { 3335 etf@6b05000 {
3401 compatible = "arm,cor 3336 compatible = "arm,coresight-tmc", "arm,primecell";
3402 reg = <0 0x06b05000 0 3337 reg = <0 0x06b05000 0 0x1000>;
3403 3338
3404 clocks = <&aoss_qmp>; 3339 clocks = <&aoss_qmp>;
3405 clock-names = "apb_pc 3340 clock-names = "apb_pclk";
3406 3341
3407 out-ports { 3342 out-ports {
3408 port { 3343 port {
3409 etf_o 3344 etf_out: endpoint {
3410 3345 remote-endpoint = <&replicator_in>;
3411 }; 3346 };
3412 }; 3347 };
3413 }; 3348 };
3414 3349
3415 in-ports { 3350 in-ports {
3416 3351
3417 port { 3352 port {
3418 etf_i 3353 etf_in_funnel_swao_out: endpoint {
3419 3354 remote-endpoint = <&funnel_swao_out_etf>;
3420 }; 3355 };
3421 }; 3356 };
3422 }; 3357 };
3423 }; 3358 };
3424 3359
3425 replicator@6b06000 { 3360 replicator@6b06000 {
3426 compatible = "arm,cor 3361 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3427 reg = <0 0x06b06000 0 3362 reg = <0 0x06b06000 0 0x1000>;
3428 3363
3429 clocks = <&aoss_qmp>; 3364 clocks = <&aoss_qmp>;
3430 clock-names = "apb_pc 3365 clock-names = "apb_pclk";
3431 3366
3432 out-ports { 3367 out-ports {
3433 port { 3368 port {
3434 repli 3369 replicator_swao_out_cx_in: endpoint {
3435 3370 remote-endpoint = <&replicator_cx_in_swao_out>;
3436 }; 3371 };
3437 }; 3372 };
3438 }; 3373 };
3439 3374
3440 in-ports { 3375 in-ports {
3441 port { 3376 port {
3442 repli 3377 replicator_in: endpoint {
3443 3378 remote-endpoint = <&etf_out>;
3444 }; 3379 };
3445 }; 3380 };
3446 }; 3381 };
3447 }; 3382 };
3448 3383
3449 tpdm@6c08000 { 3384 tpdm@6c08000 {
3450 compatible = "qcom,co 3385 compatible = "qcom,coresight-tpdm", "arm,primecell";
3451 reg = <0 0x06c08000 0 3386 reg = <0 0x06c08000 0 0x1000>;
3452 3387
3453 clocks = <&aoss_qmp>; 3388 clocks = <&aoss_qmp>;
3454 clock-names = "apb_pc 3389 clock-names = "apb_pclk";
3455 3390
3456 out-ports { 3391 out-ports {
3457 port { 3392 port {
3458 tpdm_ 3393 tpdm_mm_out_funnel_dl_mm: endpoint {
3459 3394 remote-endpoint = <&funnel_dl_mm_in_tpdm_mm>;
3460 }; 3395 };
3461 }; 3396 };
3462 }; 3397 };
3463 }; 3398 };
3464 3399
3465 funnel@6c0b000 { 3400 funnel@6c0b000 {
3466 compatible = "arm,cor 3401 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3467 reg = <0 0x06c0b000 0 3402 reg = <0 0x06c0b000 0 0x1000>;
3468 3403
3469 clocks = <&aoss_qmp>; 3404 clocks = <&aoss_qmp>;
3470 clock-names = "apb_pc 3405 clock-names = "apb_pclk";
3471 3406
3472 out-ports { 3407 out-ports {
3473 port { 3408 port {
3474 funne 3409 funnel_dl_mm_out_funnel_dl_center: endpoint {
3475 remot 3410 remote-endpoint = <&funnel_dl_center_in_funnel_dl_mm>;
3476 }; 3411 };
3477 }; 3412 };
3478 }; 3413 };
3479 3414
3480 in-ports { 3415 in-ports {
3481 #address-cell 3416 #address-cells = <1>;
3482 #size-cells = 3417 #size-cells = <0>;
3483 3418
3484 port@3 { 3419 port@3 {
3485 reg = 3420 reg = <3>;
3486 funne 3421 funnel_dl_mm_in_tpdm_mm: endpoint {
3487 3422 remote-endpoint = <&tpdm_mm_out_funnel_dl_mm>;
3488 }; 3423 };
3489 }; 3424 };
3490 }; 3425 };
3491 }; 3426 };
3492 3427
3493 funnel@6c2d000 { 3428 funnel@6c2d000 {
3494 compatible = "arm,cor 3429 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3495 reg = <0 0x06c2d000 0 3430 reg = <0 0x06c2d000 0 0x1000>;
3496 3431
3497 clocks = <&aoss_qmp>; 3432 clocks = <&aoss_qmp>;
3498 clock-names = "apb_pc 3433 clock-names = "apb_pclk";
3499 3434
3500 out-ports { 3435 out-ports {
3501 port { 3436 port {
3502 tpdm_ 3437 tpdm_mm_out_tpda9: endpoint {
3503 3438 remote-endpoint = <&tpda_9_in_tpdm_mm>;
3504 }; 3439 };
3505 }; 3440 };
3506 }; 3441 };
3507 3442
3508 in-ports { 3443 in-ports {
3509 #address-cell 3444 #address-cells = <1>;
3510 #size-cells = 3445 #size-cells = <0>;
3511 3446
3512 port@2 { 3447 port@2 {
3513 reg = 3448 reg = <2>;
3514 funne 3449 funnel_dl_center_in_funnel_dl_mm: endpoint {
3515 remot 3450 remote-endpoint = <&funnel_dl_mm_out_funnel_dl_center>;
3516 }; 3451 };
3517 }; 3452 };
3518 }; 3453 };
3519 }; 3454 };
3520 3455
3521 etm@7040000 { 3456 etm@7040000 {
3522 compatible = "arm,cor 3457 compatible = "arm,coresight-etm4x", "arm,primecell";
3523 reg = <0 0x07040000 0 3458 reg = <0 0x07040000 0 0x1000>;
3524 3459
3525 cpu = <&CPU0>; 3460 cpu = <&CPU0>;
3526 3461
3527 clocks = <&aoss_qmp>; 3462 clocks = <&aoss_qmp>;
3528 clock-names = "apb_pc 3463 clock-names = "apb_pclk";
3529 arm,coresight-loses-c 3464 arm,coresight-loses-context-with-cpu;
3530 3465
3531 out-ports { 3466 out-ports {
3532 port { 3467 port {
3533 etm0_ 3468 etm0_out: endpoint {
3534 3469 remote-endpoint = <&apss_funnel_in0>;
3535 }; 3470 };
3536 }; 3471 };
3537 }; 3472 };
3538 }; 3473 };
3539 3474
3540 etm@7140000 { 3475 etm@7140000 {
3541 compatible = "arm,cor 3476 compatible = "arm,coresight-etm4x", "arm,primecell";
3542 reg = <0 0x07140000 0 3477 reg = <0 0x07140000 0 0x1000>;
3543 3478
3544 cpu = <&CPU1>; 3479 cpu = <&CPU1>;
3545 3480
3546 clocks = <&aoss_qmp>; 3481 clocks = <&aoss_qmp>;
3547 clock-names = "apb_pc 3482 clock-names = "apb_pclk";
3548 arm,coresight-loses-c 3483 arm,coresight-loses-context-with-cpu;
3549 3484
3550 out-ports { 3485 out-ports {
3551 port { 3486 port {
3552 etm1_ 3487 etm1_out: endpoint {
3553 3488 remote-endpoint = <&apss_funnel_in1>;
3554 }; 3489 };
3555 }; 3490 };
3556 }; 3491 };
3557 }; 3492 };
3558 3493
3559 etm@7240000 { 3494 etm@7240000 {
3560 compatible = "arm,cor 3495 compatible = "arm,coresight-etm4x", "arm,primecell";
3561 reg = <0 0x07240000 0 3496 reg = <0 0x07240000 0 0x1000>;
3562 3497
3563 cpu = <&CPU2>; 3498 cpu = <&CPU2>;
3564 3499
3565 clocks = <&aoss_qmp>; 3500 clocks = <&aoss_qmp>;
3566 clock-names = "apb_pc 3501 clock-names = "apb_pclk";
3567 arm,coresight-loses-c 3502 arm,coresight-loses-context-with-cpu;
3568 3503
3569 out-ports { 3504 out-ports {
3570 port { 3505 port {
3571 etm2_ 3506 etm2_out: endpoint {
3572 3507 remote-endpoint = <&apss_funnel_in2>;
3573 }; 3508 };
3574 }; 3509 };
3575 }; 3510 };
3576 }; 3511 };
3577 3512
3578 etm@7340000 { 3513 etm@7340000 {
3579 compatible = "arm,cor 3514 compatible = "arm,coresight-etm4x", "arm,primecell";
3580 reg = <0 0x07340000 0 3515 reg = <0 0x07340000 0 0x1000>;
3581 3516
3582 cpu = <&CPU3>; 3517 cpu = <&CPU3>;
3583 3518
3584 clocks = <&aoss_qmp>; 3519 clocks = <&aoss_qmp>;
3585 clock-names = "apb_pc 3520 clock-names = "apb_pclk";
3586 arm,coresight-loses-c 3521 arm,coresight-loses-context-with-cpu;
3587 3522
3588 out-ports { 3523 out-ports {
3589 port { 3524 port {
3590 etm3_ 3525 etm3_out: endpoint {
3591 3526 remote-endpoint = <&apss_funnel_in3>;
3592 }; 3527 };
3593 }; 3528 };
3594 }; 3529 };
3595 }; 3530 };
3596 3531
3597 etm@7440000 { 3532 etm@7440000 {
3598 compatible = "arm,cor 3533 compatible = "arm,coresight-etm4x", "arm,primecell";
3599 reg = <0 0x07440000 0 3534 reg = <0 0x07440000 0 0x1000>;
3600 3535
3601 cpu = <&CPU4>; 3536 cpu = <&CPU4>;
3602 3537
3603 clocks = <&aoss_qmp>; 3538 clocks = <&aoss_qmp>;
3604 clock-names = "apb_pc 3539 clock-names = "apb_pclk";
3605 arm,coresight-loses-c 3540 arm,coresight-loses-context-with-cpu;
3606 3541
3607 out-ports { 3542 out-ports {
3608 port { 3543 port {
3609 etm4_ 3544 etm4_out: endpoint {
3610 3545 remote-endpoint = <&apss_funnel_in4>;
3611 }; 3546 };
3612 }; 3547 };
3613 }; 3548 };
3614 }; 3549 };
3615 3550
3616 etm@7540000 { 3551 etm@7540000 {
3617 compatible = "arm,cor 3552 compatible = "arm,coresight-etm4x", "arm,primecell";
3618 reg = <0 0x07540000 0 3553 reg = <0 0x07540000 0 0x1000>;
3619 3554
3620 cpu = <&CPU5>; 3555 cpu = <&CPU5>;
3621 3556
3622 clocks = <&aoss_qmp>; 3557 clocks = <&aoss_qmp>;
3623 clock-names = "apb_pc 3558 clock-names = "apb_pclk";
3624 arm,coresight-loses-c 3559 arm,coresight-loses-context-with-cpu;
3625 3560
3626 out-ports { 3561 out-ports {
3627 port { 3562 port {
3628 etm5_ 3563 etm5_out: endpoint {
3629 3564 remote-endpoint = <&apss_funnel_in5>;
3630 }; 3565 };
3631 }; 3566 };
3632 }; 3567 };
3633 }; 3568 };
3634 3569
3635 etm@7640000 { 3570 etm@7640000 {
3636 compatible = "arm,cor 3571 compatible = "arm,coresight-etm4x", "arm,primecell";
3637 reg = <0 0x07640000 0 3572 reg = <0 0x07640000 0 0x1000>;
3638 3573
3639 cpu = <&CPU6>; 3574 cpu = <&CPU6>;
3640 3575
3641 clocks = <&aoss_qmp>; 3576 clocks = <&aoss_qmp>;
3642 clock-names = "apb_pc 3577 clock-names = "apb_pclk";
3643 arm,coresight-loses-c 3578 arm,coresight-loses-context-with-cpu;
3644 3579
3645 out-ports { 3580 out-ports {
3646 port { 3581 port {
3647 etm6_ 3582 etm6_out: endpoint {
3648 3583 remote-endpoint = <&apss_funnel_in6>;
3649 }; 3584 };
3650 }; 3585 };
3651 }; 3586 };
3652 }; 3587 };
3653 3588
3654 etm@7740000 { 3589 etm@7740000 {
3655 compatible = "arm,cor 3590 compatible = "arm,coresight-etm4x", "arm,primecell";
3656 reg = <0 0x07740000 0 3591 reg = <0 0x07740000 0 0x1000>;
3657 3592
3658 cpu = <&CPU7>; 3593 cpu = <&CPU7>;
3659 3594
3660 clocks = <&aoss_qmp>; 3595 clocks = <&aoss_qmp>;
3661 clock-names = "apb_pc 3596 clock-names = "apb_pclk";
3662 arm,coresight-loses-c 3597 arm,coresight-loses-context-with-cpu;
3663 3598
3664 out-ports { 3599 out-ports {
3665 port { 3600 port {
3666 etm7_ 3601 etm7_out: endpoint {
3667 3602 remote-endpoint = <&apss_funnel_in7>;
3668 }; 3603 };
3669 }; 3604 };
3670 }; 3605 };
3671 }; 3606 };
3672 3607
3673 funnel@7800000 { 3608 funnel@7800000 {
3674 compatible = "arm,cor 3609 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3675 reg = <0 0x07800000 0 3610 reg = <0 0x07800000 0 0x1000>;
3676 3611
3677 clocks = <&aoss_qmp>; 3612 clocks = <&aoss_qmp>;
3678 clock-names = "apb_pc 3613 clock-names = "apb_pclk";
3679 3614
3680 out-ports { 3615 out-ports {
3681 port { 3616 port {
3682 funne 3617 funnel_apss_out_funnel_apss_merg: endpoint {
3683 remot 3618 remote-endpoint = <&funnel_apss_merg_in_funnel_apss>;
3684 }; 3619 };
3685 }; 3620 };
3686 }; 3621 };
3687 3622
3688 in-ports { 3623 in-ports {
3689 #address-cell 3624 #address-cells = <1>;
3690 #size-cells = 3625 #size-cells = <0>;
3691 3626
3692 port@0 { 3627 port@0 {
3693 reg = 3628 reg = <0>;
3694 apss_ 3629 apss_funnel_in0: endpoint {
3695 3630 remote-endpoint = <&etm0_out>;
3696 }; 3631 };
3697 }; 3632 };
3698 3633
3699 port@1 { 3634 port@1 {
3700 reg = 3635 reg = <1>;
3701 apss_ 3636 apss_funnel_in1: endpoint {
3702 3637 remote-endpoint = <&etm1_out>;
3703 }; 3638 };
3704 }; 3639 };
3705 3640
3706 port@2 { 3641 port@2 {
3707 reg = 3642 reg = <2>;
3708 apss_ 3643 apss_funnel_in2: endpoint {
3709 3644 remote-endpoint = <&etm2_out>;
3710 }; 3645 };
3711 }; 3646 };
3712 3647
3713 port@3 { 3648 port@3 {
3714 reg = 3649 reg = <3>;
3715 apss_ 3650 apss_funnel_in3: endpoint {
3716 3651 remote-endpoint = <&etm3_out>;
3717 }; 3652 };
3718 }; 3653 };
3719 3654
3720 port@4 { 3655 port@4 {
3721 reg = 3656 reg = <4>;
3722 apss_ 3657 apss_funnel_in4: endpoint {
3723 3658 remote-endpoint = <&etm4_out>;
3724 }; 3659 };
3725 }; 3660 };
3726 3661
3727 port@5 { 3662 port@5 {
3728 reg = 3663 reg = <5>;
3729 apss_ 3664 apss_funnel_in5: endpoint {
3730 3665 remote-endpoint = <&etm5_out>;
3731 }; 3666 };
3732 }; 3667 };
3733 3668
3734 port@6 { 3669 port@6 {
3735 reg = 3670 reg = <6>;
3736 apss_ 3671 apss_funnel_in6: endpoint {
3737 3672 remote-endpoint = <&etm6_out>;
3738 }; 3673 };
3739 }; 3674 };
3740 3675
3741 port@7 { 3676 port@7 {
3742 reg = 3677 reg = <7>;
3743 apss_ 3678 apss_funnel_in7: endpoint {
3744 3679 remote-endpoint = <&etm7_out>;
3745 }; 3680 };
3746 }; 3681 };
3747 }; 3682 };
3748 }; 3683 };
3749 3684
3750 funnel@7810000 { 3685 funnel@7810000 {
3751 compatible = "arm,cor 3686 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3752 reg = <0 0x07810000 0 3687 reg = <0 0x07810000 0 0x1000>;
3753 3688
3754 clocks = <&aoss_qmp>; 3689 clocks = <&aoss_qmp>;
3755 clock-names = "apb_pc 3690 clock-names = "apb_pclk";
3756 3691
3757 out-ports { 3692 out-ports {
3758 port { 3693 port {
3759 funne 3694 funnel_apss_merg_out_funnel_in1: endpoint {
3760 remot 3695 remote-endpoint = <&funnel_in1_in_funnel_apss_merg>;
3761 }; 3696 };
3762 }; 3697 };
3763 }; 3698 };
3764 3699
3765 in-ports { 3700 in-ports {
3766 port { 3701 port {
3767 funne 3702 funnel_apss_merg_in_funnel_apss: endpoint {
3768 remot 3703 remote-endpoint = <&funnel_apss_out_funnel_apss_merg>;
3769 }; 3704 };
3770 }; 3705 };
3771 }; 3706 };
3772 }; 3707 };
3773 3708
3774 cdsp: remoteproc@8300000 { 3709 cdsp: remoteproc@8300000 {
3775 compatible = "qcom,sm 3710 compatible = "qcom,sm8250-cdsp-pas";
3776 reg = <0 0x08300000 0 3711 reg = <0 0x08300000 0 0x10000>;
3777 3712
3778 interrupts-extended = !! 3713 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
3779 3714 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
3780 3715 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
3781 3716 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
3782 3717 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
3783 interrupt-names = "wd 3718 interrupt-names = "wdog", "fatal", "ready",
3784 "ha 3719 "handover", "stop-ack";
3785 3720
3786 clocks = <&rpmhcc RPM 3721 clocks = <&rpmhcc RPMH_CXO_CLK>;
3787 clock-names = "xo"; 3722 clock-names = "xo";
3788 3723
3789 power-domains = <&rpm 3724 power-domains = <&rpmhpd RPMHPD_CX>;
3790 3725
3791 memory-region = <&cds 3726 memory-region = <&cdsp_mem>;
3792 3727
3793 qcom,qmp = <&aoss_qmp 3728 qcom,qmp = <&aoss_qmp>;
3794 3729
3795 qcom,smem-states = <& 3730 qcom,smem-states = <&smp2p_cdsp_out 0>;
3796 qcom,smem-state-names 3731 qcom,smem-state-names = "stop";
3797 3732
3798 status = "disabled"; 3733 status = "disabled";
3799 3734
3800 glink-edge { 3735 glink-edge {
3801 interrupts-ex 3736 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
3802 3737 IPCC_MPROC_SIGNAL_GLINK_QMP
3803 3738 IRQ_TYPE_EDGE_RISING>;
3804 mboxes = <&ip 3739 mboxes = <&ipcc IPCC_CLIENT_CDSP
3805 3740 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3806 3741
3807 label = "cdsp 3742 label = "cdsp";
3808 qcom,remote-p 3743 qcom,remote-pid = <5>;
3809 3744
3810 fastrpc { 3745 fastrpc {
3811 compa 3746 compatible = "qcom,fastrpc";
3812 qcom, 3747 qcom,glink-channels = "fastrpcglink-apps-dsp";
3813 label 3748 label = "cdsp";
3814 qcom, 3749 qcom,non-secure-domain;
3815 #addr 3750 #address-cells = <1>;
3816 #size 3751 #size-cells = <0>;
3817 3752
3818 compu 3753 compute-cb@1 {
3819 3754 compatible = "qcom,fastrpc-compute-cb";
3820 3755 reg = <1>;
3821 3756 iommus = <&apps_smmu 0x1001 0x0460>;
3822 }; 3757 };
3823 3758
3824 compu 3759 compute-cb@2 {
3825 3760 compatible = "qcom,fastrpc-compute-cb";
3826 3761 reg = <2>;
3827 3762 iommus = <&apps_smmu 0x1002 0x0460>;
3828 }; 3763 };
3829 3764
3830 compu 3765 compute-cb@3 {
3831 3766 compatible = "qcom,fastrpc-compute-cb";
3832 3767 reg = <3>;
3833 3768 iommus = <&apps_smmu 0x1003 0x0460>;
3834 }; 3769 };
3835 3770
3836 compu 3771 compute-cb@4 {
3837 3772 compatible = "qcom,fastrpc-compute-cb";
3838 3773 reg = <4>;
3839 3774 iommus = <&apps_smmu 0x1004 0x0460>;
3840 }; 3775 };
3841 3776
3842 compu 3777 compute-cb@5 {
3843 3778 compatible = "qcom,fastrpc-compute-cb";
3844 3779 reg = <5>;
3845 3780 iommus = <&apps_smmu 0x1005 0x0460>;
3846 }; 3781 };
3847 3782
3848 compu 3783 compute-cb@6 {
3849 3784 compatible = "qcom,fastrpc-compute-cb";
3850 3785 reg = <6>;
3851 3786 iommus = <&apps_smmu 0x1006 0x0460>;
3852 }; 3787 };
3853 3788
3854 compu 3789 compute-cb@7 {
3855 3790 compatible = "qcom,fastrpc-compute-cb";
3856 3791 reg = <7>;
3857 3792 iommus = <&apps_smmu 0x1007 0x0460>;
3858 }; 3793 };
3859 3794
3860 compu 3795 compute-cb@8 {
3861 3796 compatible = "qcom,fastrpc-compute-cb";
3862 3797 reg = <8>;
3863 3798 iommus = <&apps_smmu 0x1008 0x0460>;
3864 }; 3799 };
3865 3800
3866 /* no 3801 /* note: secure cb9 in downstream */
3867 }; 3802 };
3868 }; 3803 };
3869 }; 3804 };
3870 3805
3871 usb_1_hsphy: phy@88e3000 { 3806 usb_1_hsphy: phy@88e3000 {
3872 compatible = "qcom,sm 3807 compatible = "qcom,sm8250-usb-hs-phy",
3873 "qcom,us 3808 "qcom,usb-snps-hs-7nm-phy";
3874 reg = <0 0x088e3000 0 3809 reg = <0 0x088e3000 0 0x400>;
3875 status = "disabled"; 3810 status = "disabled";
3876 #phy-cells = <0>; 3811 #phy-cells = <0>;
3877 3812
3878 clocks = <&rpmhcc RPM 3813 clocks = <&rpmhcc RPMH_CXO_CLK>;
3879 clock-names = "ref"; 3814 clock-names = "ref";
3880 3815
3881 resets = <&gcc GCC_QU 3816 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3882 }; 3817 };
3883 3818
3884 usb_2_hsphy: phy@88e4000 { 3819 usb_2_hsphy: phy@88e4000 {
3885 compatible = "qcom,sm 3820 compatible = "qcom,sm8250-usb-hs-phy",
3886 "qcom,us 3821 "qcom,usb-snps-hs-7nm-phy";
3887 reg = <0 0x088e4000 0 3822 reg = <0 0x088e4000 0 0x400>;
3888 status = "disabled"; 3823 status = "disabled";
3889 #phy-cells = <0>; 3824 #phy-cells = <0>;
3890 3825
3891 clocks = <&rpmhcc RPM 3826 clocks = <&rpmhcc RPMH_CXO_CLK>;
3892 clock-names = "ref"; 3827 clock-names = "ref";
3893 3828
3894 resets = <&gcc GCC_QU 3829 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3895 }; 3830 };
3896 3831
3897 usb_1_qmpphy: phy@88e8000 { 3832 usb_1_qmpphy: phy@88e8000 {
3898 compatible = "qcom,sm 3833 compatible = "qcom,sm8250-qmp-usb3-dp-phy";
3899 reg = <0 0x088e8000 0 3834 reg = <0 0x088e8000 0 0x3000>;
3900 status = "disabled"; 3835 status = "disabled";
3901 3836
3902 clocks = <&gcc GCC_US 3837 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
3903 <&rpmhcc RPM 3838 <&rpmhcc RPMH_CXO_CLK>,
3904 <&gcc GCC_US 3839 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
3905 <&gcc GCC_US 3840 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3906 clock-names = "aux", 3841 clock-names = "aux",
3907 "ref", 3842 "ref",
3908 "com_au 3843 "com_aux",
3909 "usb3_p 3844 "usb3_pipe";
3910 3845
3911 resets = <&gcc GCC_US 3846 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
3912 <&gcc GCC_US 3847 <&gcc GCC_USB3_PHY_PRIM_BCR>;
3913 reset-names = "phy", 3848 reset-names = "phy", "common";
3914 3849
3915 #clock-cells = <1>; 3850 #clock-cells = <1>;
3916 #phy-cells = <1>; 3851 #phy-cells = <1>;
3917 3852
3918 orientation-switch; <<
3919 <<
3920 ports { 3853 ports {
3921 #address-cell 3854 #address-cells = <1>;
3922 #size-cells = 3855 #size-cells = <0>;
3923 3856
3924 port@0 { 3857 port@0 {
3925 reg = 3858 reg = <0>;
3926 usb_1 3859 usb_1_qmpphy_out: endpoint {};
3927 }; 3860 };
3928 3861
3929 port@1 { 3862 port@1 {
3930 reg = 3863 reg = <1>;
3931 <<
3932 usb_1 <<
3933 <<
3934 }; <<
3935 }; 3864 };
3936 3865
3937 port@2 { 3866 port@2 {
3938 reg = 3867 reg = <2>;
3939 3868
3940 usb_1 3869 usb_1_qmpphy_dp_in: endpoint {};
3941 }; 3870 };
3942 }; 3871 };
3943 }; 3872 };
3944 3873
3945 usb_2_qmpphy: phy@88eb000 { 3874 usb_2_qmpphy: phy@88eb000 {
3946 compatible = "qcom,sm 3875 compatible = "qcom,sm8250-qmp-usb3-uni-phy";
3947 reg = <0 0x088eb000 0 !! 3876 reg = <0 0x088eb000 0 0x200>;
>> 3877 status = "disabled";
>> 3878 #address-cells = <2>;
>> 3879 #size-cells = <2>;
>> 3880 ranges;
3948 3881
3949 clocks = <&gcc GCC_US 3882 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
>> 3883 <&rpmhcc RPMH_CXO_CLK>,
3950 <&gcc GCC_US 3884 <&gcc GCC_USB3_SEC_CLKREF_EN>,
3951 <&gcc GCC_US !! 3885 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
3952 <&gcc GCC_US !! 3886 clock-names = "aux", "ref_clk_src", "ref", "com_aux";
3953 clock-names = "aux", <<
3954 "ref", <<
3955 "com_au <<
3956 "pipe"; <<
3957 clock-output-names = <<
3958 #clock-cells = <0>; <<
3959 #phy-cells = <0>; <<
3960 3887
3961 resets = <&gcc GCC_US !! 3888 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
3962 <&gcc GCC_US !! 3889 <&gcc GCC_USB3_PHY_SEC_BCR>;
3963 reset-names = "phy", !! 3890 reset-names = "phy", "common";
3964 "phy_ph <<
3965 3891
3966 status = "disabled"; !! 3892 usb_2_ssphy: phy@88eb200 {
>> 3893 reg = <0 0x088eb200 0 0x200>,
>> 3894 <0 0x088eb400 0 0x200>,
>> 3895 <0 0x088eb800 0 0x800>;
>> 3896 #clock-cells = <0>;
>> 3897 #phy-cells = <0>;
>> 3898 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
>> 3899 clock-names = "pipe0";
>> 3900 clock-output-names = "usb3_uni_phy_pipe_clk_src";
>> 3901 };
3967 }; 3902 };
3968 3903
3969 sdhc_2: mmc@8804000 { 3904 sdhc_2: mmc@8804000 {
3970 compatible = "qcom,sm 3905 compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
3971 reg = <0 0x08804000 0 3906 reg = <0 0x08804000 0 0x1000>;
3972 3907
3973 interrupts = <GIC_SPI 3908 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
3974 <GIC_SPI 3909 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
3975 interrupt-names = "hc 3910 interrupt-names = "hc_irq", "pwr_irq";
3976 3911
3977 clocks = <&gcc GCC_SD 3912 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3978 <&gcc GCC_SD 3913 <&gcc GCC_SDCC2_APPS_CLK>,
3979 <&rpmhcc RPM 3914 <&rpmhcc RPMH_CXO_CLK>;
3980 clock-names = "iface" 3915 clock-names = "iface", "core", "xo";
3981 iommus = <&apps_smmu 3916 iommus = <&apps_smmu 0x4a0 0x0>;
3982 qcom,dll-config = <0x 3917 qcom,dll-config = <0x0007642c>;
3983 qcom,ddr-config = <0x 3918 qcom,ddr-config = <0x80040868>;
3984 power-domains = <&rpm 3919 power-domains = <&rpmhpd RPMHPD_CX>;
3985 operating-points-v2 = 3920 operating-points-v2 = <&sdhc2_opp_table>;
3986 3921
3987 status = "disabled"; 3922 status = "disabled";
3988 3923
3989 sdhc2_opp_table: opp- 3924 sdhc2_opp_table: opp-table {
3990 compatible = 3925 compatible = "operating-points-v2";
3991 3926
3992 opp-19200000 3927 opp-19200000 {
3993 opp-h 3928 opp-hz = /bits/ 64 <19200000>;
3994 requi 3929 required-opps = <&rpmhpd_opp_min_svs>;
3995 }; 3930 };
3996 3931
3997 opp-50000000 3932 opp-50000000 {
3998 opp-h 3933 opp-hz = /bits/ 64 <50000000>;
3999 requi 3934 required-opps = <&rpmhpd_opp_low_svs>;
4000 }; 3935 };
4001 3936
4002 opp-100000000 3937 opp-100000000 {
4003 opp-h 3938 opp-hz = /bits/ 64 <100000000>;
4004 requi 3939 required-opps = <&rpmhpd_opp_svs>;
4005 }; 3940 };
4006 3941
4007 opp-202000000 3942 opp-202000000 {
4008 opp-h 3943 opp-hz = /bits/ 64 <202000000>;
4009 requi 3944 required-opps = <&rpmhpd_opp_svs_l1>;
4010 }; 3945 };
4011 }; 3946 };
4012 }; 3947 };
4013 3948
4014 pmu@9091000 { 3949 pmu@9091000 {
4015 compatible = "qcom,sm 3950 compatible = "qcom,sm8250-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
4016 reg = <0 0x09091000 0 3951 reg = <0 0x09091000 0 0x1000>;
4017 3952
4018 interrupts = <GIC_SPI 3953 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
4019 3954
4020 interconnects = <&mc_ 3955 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI_CH0 3>;
4021 3956
4022 operating-points-v2 = 3957 operating-points-v2 = <&llcc_bwmon_opp_table>;
4023 3958
4024 llcc_bwmon_opp_table: 3959 llcc_bwmon_opp_table: opp-table {
4025 compatible = 3960 compatible = "operating-points-v2";
4026 3961
4027 opp-800000 { 3962 opp-800000 {
4028 opp-p 3963 opp-peak-kBps = <(200 * 4 * 1000)>;
4029 }; 3964 };
4030 3965
4031 opp-1200000 { 3966 opp-1200000 {
4032 opp-p 3967 opp-peak-kBps = <(300 * 4 * 1000)>;
4033 }; 3968 };
4034 3969
4035 opp-1804000 { 3970 opp-1804000 {
4036 opp-p 3971 opp-peak-kBps = <(451 * 4 * 1000)>;
4037 }; 3972 };
4038 3973
4039 opp-2188000 { 3974 opp-2188000 {
4040 opp-p 3975 opp-peak-kBps = <(547 * 4 * 1000)>;
4041 }; 3976 };
4042 3977
4043 opp-2724000 { 3978 opp-2724000 {
4044 opp-p 3979 opp-peak-kBps = <(681 * 4 * 1000)>;
4045 }; 3980 };
4046 3981
4047 opp-3072000 { 3982 opp-3072000 {
4048 opp-p 3983 opp-peak-kBps = <(768 * 4 * 1000)>;
4049 }; 3984 };
4050 3985
4051 opp-4068000 { 3986 opp-4068000 {
4052 opp-p 3987 opp-peak-kBps = <(1017 * 4 * 1000)>;
4053 }; 3988 };
4054 3989
4055 /* 1353 MHz, 3990 /* 1353 MHz, LPDDR4X */
4056 3991
4057 opp-6220000 { 3992 opp-6220000 {
4058 opp-p 3993 opp-peak-kBps = <(1555 * 4 * 1000)>;
4059 }; 3994 };
4060 3995
4061 opp-7216000 { 3996 opp-7216000 {
4062 opp-p 3997 opp-peak-kBps = <(1804 * 4 * 1000)>;
4063 }; 3998 };
4064 3999
4065 opp-8368000 { 4000 opp-8368000 {
4066 opp-p 4001 opp-peak-kBps = <(2092 * 4 * 1000)>;
4067 }; 4002 };
4068 4003
4069 /* LPDDR5 */ 4004 /* LPDDR5 */
4070 opp-10944000 4005 opp-10944000 {
4071 opp-p 4006 opp-peak-kBps = <(2736 * 4 * 1000)>;
4072 }; 4007 };
4073 }; 4008 };
4074 }; 4009 };
4075 4010
4076 pmu@90b6400 { 4011 pmu@90b6400 {
4077 compatible = "qcom,sm 4012 compatible = "qcom,sm8250-cpu-bwmon", "qcom,sdm845-bwmon";
4078 reg = <0 0x090b6400 0 4013 reg = <0 0x090b6400 0 0x600>;
4079 4014
4080 interrupts = <GIC_SPI 4015 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
4081 4016
4082 interconnects = <&gem 4017 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &gem_noc SLAVE_LLCC 3>;
4083 operating-points-v2 = 4018 operating-points-v2 = <&cpu_bwmon_opp_table>;
4084 4019
4085 cpu_bwmon_opp_table: 4020 cpu_bwmon_opp_table: opp-table {
4086 compatible = 4021 compatible = "operating-points-v2";
4087 4022
4088 opp-800000 { 4023 opp-800000 {
4089 opp-p 4024 opp-peak-kBps = <(200 * 4 * 1000)>;
4090 }; 4025 };
4091 4026
4092 opp-1804000 { 4027 opp-1804000 {
4093 opp-p 4028 opp-peak-kBps = <(451 * 4 * 1000)>;
4094 }; 4029 };
4095 4030
4096 opp-2188000 { 4031 opp-2188000 {
4097 opp-p 4032 opp-peak-kBps = <(547 * 4 * 1000)>;
4098 }; 4033 };
4099 4034
4100 opp-2724000 { 4035 opp-2724000 {
4101 opp-p 4036 opp-peak-kBps = <(681 * 4 * 1000)>;
4102 }; 4037 };
4103 4038
4104 opp-3072000 { 4039 opp-3072000 {
4105 opp-p 4040 opp-peak-kBps = <(768 * 4 * 1000)>;
4106 }; 4041 };
4107 4042
4108 /* 1017MHz, 1 4043 /* 1017MHz, 1353 MHz, LPDDR4X */
4109 4044
4110 opp-6220000 { 4045 opp-6220000 {
4111 opp-p 4046 opp-peak-kBps = <(1555 * 4 * 1000)>;
4112 }; 4047 };
4113 4048
4114 opp-6832000 { 4049 opp-6832000 {
4115 opp-p 4050 opp-peak-kBps = <(1708 * 4 * 1000)>;
4116 }; 4051 };
4117 4052
4118 opp-8368000 { 4053 opp-8368000 {
4119 opp-p 4054 opp-peak-kBps = <(2092 * 4 * 1000)>;
4120 }; 4055 };
4121 4056
4122 /* 2133MHz, L 4057 /* 2133MHz, LPDDR4X */
4123 4058
4124 /* LPDDR5 */ 4059 /* LPDDR5 */
4125 opp-10944000 4060 opp-10944000 {
4126 opp-p 4061 opp-peak-kBps = <(2736 * 4 * 1000)>;
4127 }; 4062 };
4128 4063
4129 /* LPDDR5 */ 4064 /* LPDDR5 */
4130 opp-12784000 4065 opp-12784000 {
4131 opp-p 4066 opp-peak-kBps = <(3196 * 4 * 1000)>;
4132 }; 4067 };
4133 }; 4068 };
4134 }; 4069 };
4135 4070
4136 dc_noc: interconnect@90c0000 4071 dc_noc: interconnect@90c0000 {
4137 compatible = "qcom,sm 4072 compatible = "qcom,sm8250-dc-noc";
4138 reg = <0 0x090c0000 0 4073 reg = <0 0x090c0000 0 0x4200>;
4139 #interconnect-cells = 4074 #interconnect-cells = <2>;
4140 qcom,bcm-voters = <&a 4075 qcom,bcm-voters = <&apps_bcm_voter>;
4141 }; 4076 };
4142 4077
4143 gem_noc: interconnect@9100000 4078 gem_noc: interconnect@9100000 {
4144 compatible = "qcom,sm 4079 compatible = "qcom,sm8250-gem-noc";
4145 reg = <0 0x09100000 0 4080 reg = <0 0x09100000 0 0xb4000>;
4146 #interconnect-cells = 4081 #interconnect-cells = <2>;
4147 qcom,bcm-voters = <&a 4082 qcom,bcm-voters = <&apps_bcm_voter>;
4148 }; 4083 };
4149 4084
4150 npu_noc: interconnect@9990000 4085 npu_noc: interconnect@9990000 {
4151 compatible = "qcom,sm 4086 compatible = "qcom,sm8250-npu-noc";
4152 reg = <0 0x09990000 0 4087 reg = <0 0x09990000 0 0x1600>;
4153 #interconnect-cells = 4088 #interconnect-cells = <2>;
4154 qcom,bcm-voters = <&a 4089 qcom,bcm-voters = <&apps_bcm_voter>;
4155 }; 4090 };
4156 4091
4157 usb_1: usb@a6f8800 { 4092 usb_1: usb@a6f8800 {
4158 compatible = "qcom,sm 4093 compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
4159 reg = <0 0x0a6f8800 0 4094 reg = <0 0x0a6f8800 0 0x400>;
4160 status = "disabled"; 4095 status = "disabled";
4161 #address-cells = <2>; 4096 #address-cells = <2>;
4162 #size-cells = <2>; 4097 #size-cells = <2>;
4163 ranges; 4098 ranges;
4164 dma-ranges; 4099 dma-ranges;
4165 4100
4166 clocks = <&gcc GCC_CF 4101 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
4167 <&gcc GCC_US 4102 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
4168 <&gcc GCC_AG 4103 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
4169 <&gcc GCC_US 4104 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
4170 <&gcc GCC_US 4105 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4171 <&gcc GCC_US 4106 <&gcc GCC_USB3_SEC_CLKREF_EN>;
4172 clock-names = "cfg_no 4107 clock-names = "cfg_noc",
4173 "core", 4108 "core",
4174 "iface" 4109 "iface",
4175 "sleep" 4110 "sleep",
4176 "mock_u 4111 "mock_utmi",
4177 "xo"; 4112 "xo";
4178 4113
4179 assigned-clocks = <&g 4114 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4180 <&g 4115 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
4181 assigned-clock-rates 4116 assigned-clock-rates = <19200000>, <200000000>;
4182 4117
4183 interrupts-extended = !! 4118 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
4184 !! 4119 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
4185 <<
4186 4120 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
4187 !! 4121 <&pdc 14 IRQ_TYPE_EDGE_BOTH>;
4188 interrupt-names = "pw !! 4122 interrupt-names = "hs_phy_irq",
4189 "hs !! 4123 "ss_phy_irq",
4190 "dp <<
4191 "dm 4124 "dm_hs_phy_irq",
4192 "ss !! 4125 "dp_hs_phy_irq";
4193 4126
4194 power-domains = <&gcc 4127 power-domains = <&gcc USB30_PRIM_GDSC>;
4195 wakeup-source; <<
4196 4128
4197 resets = <&gcc GCC_US 4129 resets = <&gcc GCC_USB30_PRIM_BCR>;
4198 4130
4199 interconnects = <&agg 4131 interconnects = <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>,
4200 <&gem 4132 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>;
4201 interconnect-names = 4133 interconnect-names = "usb-ddr", "apps-usb";
4202 4134
4203 usb_1_dwc3: usb@a6000 4135 usb_1_dwc3: usb@a600000 {
4204 compatible = 4136 compatible = "snps,dwc3";
4205 reg = <0 0x0a 4137 reg = <0 0x0a600000 0 0xcd00>;
4206 interrupts = 4138 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
4207 iommus = <&ap 4139 iommus = <&apps_smmu 0x0 0x0>;
4208 snps,dis_u2_s 4140 snps,dis_u2_susphy_quirk;
4209 snps,dis_enbl 4141 snps,dis_enblslpm_quirk;
4210 phys = <&usb_ 4142 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
4211 phy-names = " 4143 phy-names = "usb2-phy", "usb3-phy";
4212 4144
4213 ports { !! 4145 port {
4214 #addr !! 4146 usb_1_role_switch_out: endpoint {};
4215 #size <<
4216 <<
4217 port@ <<
4218 <<
4219 <<
4220 <<
4221 <<
4222 }; <<
4223 <<
4224 port@ <<
4225 <<
4226 <<
4227 <<
4228 <<
4229 <<
4230 }; <<
4231 }; 4147 };
4232 }; 4148 };
4233 }; 4149 };
4234 4150
4235 system-cache-controller@92000 4151 system-cache-controller@9200000 {
4236 compatible = "qcom,sm 4152 compatible = "qcom,sm8250-llcc";
4237 reg = <0 0x09200000 0 4153 reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>,
4238 <0 0x09300000 0 4154 <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>,
4239 <0 0x09600000 0 4155 <0 0x09600000 0 0x50000>;
4240 reg-names = "llcc0_ba 4156 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
4241 "llcc3_ba 4157 "llcc3_base", "llcc_broadcast_base";
4242 }; 4158 };
4243 4159
4244 usb_2: usb@a8f8800 { 4160 usb_2: usb@a8f8800 {
4245 compatible = "qcom,sm 4161 compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
4246 reg = <0 0x0a8f8800 0 4162 reg = <0 0x0a8f8800 0 0x400>;
4247 status = "disabled"; 4163 status = "disabled";
4248 #address-cells = <2>; 4164 #address-cells = <2>;
4249 #size-cells = <2>; 4165 #size-cells = <2>;
4250 ranges; 4166 ranges;
4251 dma-ranges; 4167 dma-ranges;
4252 4168
4253 clocks = <&gcc GCC_CF 4169 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
4254 <&gcc GCC_US 4170 <&gcc GCC_USB30_SEC_MASTER_CLK>,
4255 <&gcc GCC_AG 4171 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
4256 <&gcc GCC_US 4172 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
4257 <&gcc GCC_US 4173 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4258 <&gcc GCC_US 4174 <&gcc GCC_USB3_SEC_CLKREF_EN>;
4259 clock-names = "cfg_no 4175 clock-names = "cfg_noc",
4260 "core", 4176 "core",
4261 "iface" 4177 "iface",
4262 "sleep" 4178 "sleep",
4263 "mock_u 4179 "mock_utmi",
4264 "xo"; 4180 "xo";
4265 4181
4266 assigned-clocks = <&g 4182 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4267 <&g 4183 <&gcc GCC_USB30_SEC_MASTER_CLK>;
4268 assigned-clock-rates 4184 assigned-clock-rates = <19200000>, <200000000>;
4269 4185
4270 interrupts-extended = !! 4186 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
4271 !! 4187 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>,
4272 <<
4273 4188 <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
4274 !! 4189 <&pdc 12 IRQ_TYPE_EDGE_BOTH>;
4275 interrupt-names = "pw !! 4190 interrupt-names = "hs_phy_irq",
4276 "hs !! 4191 "ss_phy_irq",
4277 "dp <<
4278 "dm 4192 "dm_hs_phy_irq",
4279 "ss !! 4193 "dp_hs_phy_irq";
4280 4194
4281 power-domains = <&gcc 4195 power-domains = <&gcc USB30_SEC_GDSC>;
4282 wakeup-source; <<
4283 4196
4284 resets = <&gcc GCC_US 4197 resets = <&gcc GCC_USB30_SEC_BCR>;
4285 4198
4286 interconnects = <&agg 4199 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0>,
4287 <&gem 4200 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>;
4288 interconnect-names = 4201 interconnect-names = "usb-ddr", "apps-usb";
4289 4202
4290 usb_2_dwc3: usb@a8000 4203 usb_2_dwc3: usb@a800000 {
4291 compatible = 4204 compatible = "snps,dwc3";
4292 reg = <0 0x0a 4205 reg = <0 0x0a800000 0 0xcd00>;
4293 interrupts = 4206 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
4294 iommus = <&ap 4207 iommus = <&apps_smmu 0x20 0>;
4295 snps,dis_u2_s 4208 snps,dis_u2_susphy_quirk;
4296 snps,dis_enbl 4209 snps,dis_enblslpm_quirk;
4297 phys = <&usb_ !! 4210 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
4298 phy-names = " 4211 phy-names = "usb2-phy", "usb3-phy";
4299 }; 4212 };
4300 }; 4213 };
4301 4214
4302 venus: video-codec@aa00000 { 4215 venus: video-codec@aa00000 {
4303 compatible = "qcom,sm 4216 compatible = "qcom,sm8250-venus";
4304 reg = <0 0x0aa00000 0 4217 reg = <0 0x0aa00000 0 0x100000>;
4305 interrupts = <GIC_SPI 4218 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
4306 power-domains = <&vid 4219 power-domains = <&videocc MVS0C_GDSC>,
4307 <&vid 4220 <&videocc MVS0_GDSC>,
4308 <&rpm 4221 <&rpmhpd RPMHPD_MX>;
4309 power-domain-names = 4222 power-domain-names = "venus", "vcodec0", "mx";
4310 operating-points-v2 = 4223 operating-points-v2 = <&venus_opp_table>;
4311 4224
4312 clocks = <&gcc GCC_VI 4225 clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
4313 <&videocc VI 4226 <&videocc VIDEO_CC_MVS0C_CLK>,
4314 <&videocc VI 4227 <&videocc VIDEO_CC_MVS0_CLK>;
4315 clock-names = "iface" 4228 clock-names = "iface", "core", "vcodec0_core";
4316 4229
4317 interconnects = <&gem 4230 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_VENUS_CFG 0>,
4318 <&mms 4231 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI_CH0 0>;
4319 interconnect-names = 4232 interconnect-names = "cpu-cfg", "video-mem";
4320 4233
4321 iommus = <&apps_smmu 4234 iommus = <&apps_smmu 0x2100 0x0400>;
4322 memory-region = <&vid 4235 memory-region = <&video_mem>;
4323 4236
4324 resets = <&gcc GCC_VI 4237 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
4325 <&videocc VI 4238 <&videocc VIDEO_CC_MVS0C_CLK_ARES>;
4326 reset-names = "bus", 4239 reset-names = "bus", "core";
4327 4240
4328 status = "disabled"; 4241 status = "disabled";
4329 4242
4330 video-decoder { 4243 video-decoder {
4331 compatible = 4244 compatible = "venus-decoder";
4332 }; 4245 };
4333 4246
4334 video-encoder { 4247 video-encoder {
4335 compatible = 4248 compatible = "venus-encoder";
4336 }; 4249 };
4337 4250
4338 venus_opp_table: opp- 4251 venus_opp_table: opp-table {
4339 compatible = 4252 compatible = "operating-points-v2";
4340 4253
4341 opp-720000000 4254 opp-720000000 {
4342 opp-h 4255 opp-hz = /bits/ 64 <720000000>;
4343 requi 4256 required-opps = <&rpmhpd_opp_low_svs>;
4344 }; 4257 };
4345 4258
4346 opp-101400000 4259 opp-1014000000 {
4347 opp-h 4260 opp-hz = /bits/ 64 <1014000000>;
4348 requi 4261 required-opps = <&rpmhpd_opp_svs>;
4349 }; 4262 };
4350 4263
4351 opp-109800000 4264 opp-1098000000 {
4352 opp-h 4265 opp-hz = /bits/ 64 <1098000000>;
4353 requi 4266 required-opps = <&rpmhpd_opp_svs_l1>;
4354 }; 4267 };
4355 4268
4356 opp-133200000 4269 opp-1332000000 {
4357 opp-h 4270 opp-hz = /bits/ 64 <1332000000>;
4358 requi 4271 required-opps = <&rpmhpd_opp_nom>;
4359 }; 4272 };
4360 }; 4273 };
4361 }; 4274 };
4362 4275
4363 videocc: clock-controller@abf 4276 videocc: clock-controller@abf0000 {
4364 compatible = "qcom,sm 4277 compatible = "qcom,sm8250-videocc";
4365 reg = <0 0x0abf0000 0 4278 reg = <0 0x0abf0000 0 0x10000>;
4366 clocks = <&gcc GCC_VI 4279 clocks = <&gcc GCC_VIDEO_AHB_CLK>,
4367 <&rpmhcc RPM 4280 <&rpmhcc RPMH_CXO_CLK>,
4368 <&rpmhcc RPM 4281 <&rpmhcc RPMH_CXO_CLK_A>;
4369 power-domains = <&rpm 4282 power-domains = <&rpmhpd RPMHPD_MMCX>;
4370 required-opps = <&rpm 4283 required-opps = <&rpmhpd_opp_low_svs>;
4371 clock-names = "iface" 4284 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao";
4372 #clock-cells = <1>; 4285 #clock-cells = <1>;
4373 #reset-cells = <1>; 4286 #reset-cells = <1>;
4374 #power-domain-cells = 4287 #power-domain-cells = <1>;
4375 }; 4288 };
4376 4289
4377 cci0: cci@ac4f000 { 4290 cci0: cci@ac4f000 {
4378 compatible = "qcom,sm 4291 compatible = "qcom,sm8250-cci", "qcom,msm8996-cci";
4379 #address-cells = <1>; 4292 #address-cells = <1>;
4380 #size-cells = <0>; 4293 #size-cells = <0>;
4381 4294
4382 reg = <0 0x0ac4f000 0 4295 reg = <0 0x0ac4f000 0 0x1000>;
4383 interrupts = <GIC_SPI 4296 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
4384 power-domains = <&cam 4297 power-domains = <&camcc TITAN_TOP_GDSC>;
4385 4298
4386 clocks = <&camcc CAM_ 4299 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
4387 <&camcc CAM_ 4300 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4388 <&camcc CAM_ 4301 <&camcc CAM_CC_CPAS_AHB_CLK>,
4389 <&camcc CAM_ 4302 <&camcc CAM_CC_CCI_0_CLK>,
4390 <&camcc CAM_ 4303 <&camcc CAM_CC_CCI_0_CLK_SRC>;
4391 clock-names = "camnoc 4304 clock-names = "camnoc_axi",
4392 "slow_a 4305 "slow_ahb_src",
4393 "cpas_a 4306 "cpas_ahb",
4394 "cci", 4307 "cci",
4395 "cci_sr 4308 "cci_src";
4396 4309
4397 pinctrl-0 = <&cci0_de 4310 pinctrl-0 = <&cci0_default>;
4398 pinctrl-1 = <&cci0_sl 4311 pinctrl-1 = <&cci0_sleep>;
4399 pinctrl-names = "defa 4312 pinctrl-names = "default", "sleep";
4400 4313
4401 status = "disabled"; 4314 status = "disabled";
4402 4315
4403 cci0_i2c0: i2c-bus@0 4316 cci0_i2c0: i2c-bus@0 {
4404 reg = <0>; 4317 reg = <0>;
4405 clock-frequen 4318 clock-frequency = <1000000>;
4406 #address-cell 4319 #address-cells = <1>;
4407 #size-cells = 4320 #size-cells = <0>;
4408 }; 4321 };
4409 4322
4410 cci0_i2c1: i2c-bus@1 4323 cci0_i2c1: i2c-bus@1 {
4411 reg = <1>; 4324 reg = <1>;
4412 clock-frequen 4325 clock-frequency = <1000000>;
4413 #address-cell 4326 #address-cells = <1>;
4414 #size-cells = 4327 #size-cells = <0>;
4415 }; 4328 };
4416 }; 4329 };
4417 4330
4418 cci1: cci@ac50000 { 4331 cci1: cci@ac50000 {
4419 compatible = "qcom,sm 4332 compatible = "qcom,sm8250-cci", "qcom,msm8996-cci";
4420 #address-cells = <1>; 4333 #address-cells = <1>;
4421 #size-cells = <0>; 4334 #size-cells = <0>;
4422 4335
4423 reg = <0 0x0ac50000 0 4336 reg = <0 0x0ac50000 0 0x1000>;
4424 interrupts = <GIC_SPI 4337 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>;
4425 power-domains = <&cam 4338 power-domains = <&camcc TITAN_TOP_GDSC>;
4426 4339
4427 clocks = <&camcc CAM_ 4340 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
4428 <&camcc CAM_ 4341 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4429 <&camcc CAM_ 4342 <&camcc CAM_CC_CPAS_AHB_CLK>,
4430 <&camcc CAM_ 4343 <&camcc CAM_CC_CCI_1_CLK>,
4431 <&camcc CAM_ 4344 <&camcc CAM_CC_CCI_1_CLK_SRC>;
4432 clock-names = "camnoc 4345 clock-names = "camnoc_axi",
4433 "slow_a 4346 "slow_ahb_src",
4434 "cpas_a 4347 "cpas_ahb",
4435 "cci", 4348 "cci",
4436 "cci_sr 4349 "cci_src";
4437 4350
4438 pinctrl-0 = <&cci1_de 4351 pinctrl-0 = <&cci1_default>;
4439 pinctrl-1 = <&cci1_sl 4352 pinctrl-1 = <&cci1_sleep>;
4440 pinctrl-names = "defa 4353 pinctrl-names = "default", "sleep";
4441 4354
4442 status = "disabled"; 4355 status = "disabled";
4443 4356
4444 cci1_i2c0: i2c-bus@0 4357 cci1_i2c0: i2c-bus@0 {
4445 reg = <0>; 4358 reg = <0>;
4446 clock-frequen 4359 clock-frequency = <1000000>;
4447 #address-cell 4360 #address-cells = <1>;
4448 #size-cells = 4361 #size-cells = <0>;
4449 }; 4362 };
4450 4363
4451 cci1_i2c1: i2c-bus@1 4364 cci1_i2c1: i2c-bus@1 {
4452 reg = <1>; 4365 reg = <1>;
4453 clock-frequen 4366 clock-frequency = <1000000>;
4454 #address-cell 4367 #address-cells = <1>;
4455 #size-cells = 4368 #size-cells = <0>;
4456 }; 4369 };
4457 }; 4370 };
4458 4371
4459 camss: camss@ac6a000 { 4372 camss: camss@ac6a000 {
4460 compatible = "qcom,sm 4373 compatible = "qcom,sm8250-camss";
4461 status = "disabled"; 4374 status = "disabled";
4462 4375
4463 reg = <0 0x0ac6a000 0 4376 reg = <0 0x0ac6a000 0 0x2000>,
4464 <0 0x0ac6c000 0 4377 <0 0x0ac6c000 0 0x2000>,
4465 <0 0x0ac6e000 0 4378 <0 0x0ac6e000 0 0x1000>,
4466 <0 0x0ac70000 0 4379 <0 0x0ac70000 0 0x1000>,
4467 <0 0x0ac72000 0 4380 <0 0x0ac72000 0 0x1000>,
4468 <0 0x0ac74000 0 4381 <0 0x0ac74000 0 0x1000>,
4469 <0 0x0acb4000 0 4382 <0 0x0acb4000 0 0xd000>,
4470 <0 0x0acc3000 0 4383 <0 0x0acc3000 0 0xd000>,
4471 <0 0x0acd9000 0 4384 <0 0x0acd9000 0 0x2200>,
4472 <0 0x0acdb200 0 4385 <0 0x0acdb200 0 0x2200>;
4473 reg-names = "csiphy0" 4386 reg-names = "csiphy0",
4474 "csiphy1" 4387 "csiphy1",
4475 "csiphy2" 4388 "csiphy2",
4476 "csiphy3" 4389 "csiphy3",
4477 "csiphy4" 4390 "csiphy4",
4478 "csiphy5" 4391 "csiphy5",
4479 "vfe0", 4392 "vfe0",
4480 "vfe1", 4393 "vfe1",
4481 "vfe_lite 4394 "vfe_lite0",
4482 "vfe_lite 4395 "vfe_lite1";
4483 4396
4484 interrupts = <GIC_SPI 4397 interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
4485 <GIC_SPI 4398 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
4486 <GIC_SPI 4399 <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
4487 <GIC_SPI 4400 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
4488 <GIC_SPI 4401 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
4489 <GIC_SPI 4402 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
4490 <GIC_SPI 4403 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
4491 <GIC_SPI 4404 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
4492 <GIC_SPI 4405 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
4493 <GIC_SPI 4406 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
4494 <GIC_SPI 4407 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
4495 <GIC_SPI 4408 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
4496 <GIC_SPI 4409 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
4497 <GIC_SPI 4410 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
4498 interrupt-names = "cs 4411 interrupt-names = "csiphy0",
4499 "cs 4412 "csiphy1",
4500 "cs 4413 "csiphy2",
4501 "cs 4414 "csiphy3",
4502 "cs 4415 "csiphy4",
4503 "cs 4416 "csiphy5",
4504 "cs 4417 "csid0",
4505 "cs 4418 "csid1",
4506 "cs 4419 "csid2",
4507 "cs 4420 "csid3",
4508 "vf 4421 "vfe0",
4509 "vf 4422 "vfe1",
4510 "vf 4423 "vfe_lite0",
4511 "vf 4424 "vfe_lite1";
4512 4425
4513 power-domains = <&cam 4426 power-domains = <&camcc IFE_0_GDSC>,
4514 <&cam 4427 <&camcc IFE_1_GDSC>,
4515 <&cam 4428 <&camcc TITAN_TOP_GDSC>;
4516 4429
4517 clocks = <&gcc GCC_CA 4430 clocks = <&gcc GCC_CAMERA_AHB_CLK>,
4518 <&gcc GCC_CA 4431 <&gcc GCC_CAMERA_HF_AXI_CLK>,
4519 <&gcc GCC_CA 4432 <&gcc GCC_CAMERA_SF_AXI_CLK>,
4520 <&camcc CAM_ 4433 <&camcc CAM_CC_CAMNOC_AXI_CLK>,
4521 <&camcc CAM_ 4434 <&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>,
4522 <&camcc CAM_ 4435 <&camcc CAM_CC_CORE_AHB_CLK>,
4523 <&camcc CAM_ 4436 <&camcc CAM_CC_CPAS_AHB_CLK>,
4524 <&camcc CAM_ 4437 <&camcc CAM_CC_CSIPHY0_CLK>,
4525 <&camcc CAM_ 4438 <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
4526 <&camcc CAM_ 4439 <&camcc CAM_CC_CSIPHY1_CLK>,
4527 <&camcc CAM_ 4440 <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
4528 <&camcc CAM_ 4441 <&camcc CAM_CC_CSIPHY2_CLK>,
4529 <&camcc CAM_ 4442 <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
4530 <&camcc CAM_ 4443 <&camcc CAM_CC_CSIPHY3_CLK>,
4531 <&camcc CAM_ 4444 <&camcc CAM_CC_CSI3PHYTIMER_CLK>,
4532 <&camcc CAM_ 4445 <&camcc CAM_CC_CSIPHY4_CLK>,
4533 <&camcc CAM_ 4446 <&camcc CAM_CC_CSI4PHYTIMER_CLK>,
4534 <&camcc CAM_ 4447 <&camcc CAM_CC_CSIPHY5_CLK>,
4535 <&camcc CAM_ 4448 <&camcc CAM_CC_CSI5PHYTIMER_CLK>,
4536 <&camcc CAM_ 4449 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4537 <&camcc CAM_ 4450 <&camcc CAM_CC_IFE_0_AHB_CLK>,
4538 <&camcc CAM_ 4451 <&camcc CAM_CC_IFE_0_AXI_CLK>,
4539 <&camcc CAM_ 4452 <&camcc CAM_CC_IFE_0_CLK>,
4540 <&camcc CAM_ 4453 <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
4541 <&camcc CAM_ 4454 <&camcc CAM_CC_IFE_0_CSID_CLK>,
4542 <&camcc CAM_ 4455 <&camcc CAM_CC_IFE_0_AREG_CLK>,
4543 <&camcc CAM_ 4456 <&camcc CAM_CC_IFE_1_AHB_CLK>,
4544 <&camcc CAM_ 4457 <&camcc CAM_CC_IFE_1_AXI_CLK>,
4545 <&camcc CAM_ 4458 <&camcc CAM_CC_IFE_1_CLK>,
4546 <&camcc CAM_ 4459 <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
4547 <&camcc CAM_ 4460 <&camcc CAM_CC_IFE_1_CSID_CLK>,
4548 <&camcc CAM_ 4461 <&camcc CAM_CC_IFE_1_AREG_CLK>,
4549 <&camcc CAM_ 4462 <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
4550 <&camcc CAM_ 4463 <&camcc CAM_CC_IFE_LITE_AXI_CLK>,
4551 <&camcc CAM_ 4464 <&camcc CAM_CC_IFE_LITE_CLK>,
4552 <&camcc CAM_ 4465 <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
4553 <&camcc CAM_ 4466 <&camcc CAM_CC_IFE_LITE_CSID_CLK>;
4554 4467
4555 clock-names = "cam_ah 4468 clock-names = "cam_ahb_clk",
4556 "cam_hf 4469 "cam_hf_axi",
4557 "cam_sf 4470 "cam_sf_axi",
4558 "camnoc 4471 "camnoc_axi",
4559 "camnoc 4472 "camnoc_axi_src",
4560 "core_a 4473 "core_ahb",
4561 "cpas_a 4474 "cpas_ahb",
4562 "csiphy 4475 "csiphy0",
4563 "csiphy 4476 "csiphy0_timer",
4564 "csiphy 4477 "csiphy1",
4565 "csiphy 4478 "csiphy1_timer",
4566 "csiphy 4479 "csiphy2",
4567 "csiphy 4480 "csiphy2_timer",
4568 "csiphy 4481 "csiphy3",
4569 "csiphy 4482 "csiphy3_timer",
4570 "csiphy 4483 "csiphy4",
4571 "csiphy 4484 "csiphy4_timer",
4572 "csiphy 4485 "csiphy5",
4573 "csiphy 4486 "csiphy5_timer",
4574 "slow_a 4487 "slow_ahb_src",
4575 "vfe0_a 4488 "vfe0_ahb",
4576 "vfe0_a 4489 "vfe0_axi",
4577 "vfe0", 4490 "vfe0",
4578 "vfe0_c 4491 "vfe0_cphy_rx",
4579 "vfe0_c 4492 "vfe0_csid",
4580 "vfe0_a 4493 "vfe0_areg",
4581 "vfe1_a 4494 "vfe1_ahb",
4582 "vfe1_a 4495 "vfe1_axi",
4583 "vfe1", 4496 "vfe1",
4584 "vfe1_c 4497 "vfe1_cphy_rx",
4585 "vfe1_c 4498 "vfe1_csid",
4586 "vfe1_a 4499 "vfe1_areg",
4587 "vfe_li 4500 "vfe_lite_ahb",
4588 "vfe_li 4501 "vfe_lite_axi",
4589 "vfe_li 4502 "vfe_lite",
4590 "vfe_li 4503 "vfe_lite_cphy_rx",
4591 "vfe_li 4504 "vfe_lite_csid";
4592 4505
4593 iommus = <&apps_smmu 4506 iommus = <&apps_smmu 0x800 0x400>,
4594 <&apps_smmu 4507 <&apps_smmu 0x801 0x400>,
4595 <&apps_smmu 4508 <&apps_smmu 0x840 0x400>,
4596 <&apps_smmu 4509 <&apps_smmu 0x841 0x400>,
4597 <&apps_smmu 4510 <&apps_smmu 0xc00 0x400>,
4598 <&apps_smmu 4511 <&apps_smmu 0xc01 0x400>,
4599 <&apps_smmu 4512 <&apps_smmu 0xc40 0x400>,
4600 <&apps_smmu 4513 <&apps_smmu 0xc41 0x400>;
4601 4514
4602 interconnects = <&gem 4515 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_CAMERA_CFG 0>,
4603 <&mms 4516 <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI_CH0 0>,
4604 <&mms 4517 <&mmss_noc MASTER_CAMNOC_SF 0 &mc_virt SLAVE_EBI_CH0 0>,
4605 <&mms 4518 <&mmss_noc MASTER_CAMNOC_ICP 0 &mc_virt SLAVE_EBI_CH0 0>;
4606 interconnect-names = 4519 interconnect-names = "cam_ahb",
4607 4520 "cam_hf_0_mnoc",
4608 4521 "cam_sf_0_mnoc",
4609 4522 "cam_sf_icp_mnoc";
4610 4523
4611 ports { 4524 ports {
4612 #address-cell 4525 #address-cells = <1>;
4613 #size-cells = 4526 #size-cells = <0>;
4614 4527
4615 port@0 { 4528 port@0 {
4616 reg = 4529 reg = <0>;
4617 }; 4530 };
4618 4531
4619 port@1 { 4532 port@1 {
4620 reg = 4533 reg = <1>;
4621 }; 4534 };
4622 4535
4623 port@2 { 4536 port@2 {
4624 reg = 4537 reg = <2>;
4625 }; 4538 };
4626 4539
4627 port@3 { 4540 port@3 {
4628 reg = 4541 reg = <3>;
4629 }; 4542 };
4630 4543
4631 port@4 { 4544 port@4 {
4632 reg = 4545 reg = <4>;
4633 }; 4546 };
4634 4547
4635 port@5 { 4548 port@5 {
4636 reg = 4549 reg = <5>;
4637 }; 4550 };
4638 }; 4551 };
4639 }; 4552 };
4640 4553
4641 camcc: clock-controller@ad000 4554 camcc: clock-controller@ad00000 {
4642 compatible = "qcom,sm 4555 compatible = "qcom,sm8250-camcc";
4643 reg = <0 0x0ad00000 0 4556 reg = <0 0x0ad00000 0 0x10000>;
4644 clocks = <&gcc GCC_CA 4557 clocks = <&gcc GCC_CAMERA_AHB_CLK>,
4645 <&rpmhcc RPM 4558 <&rpmhcc RPMH_CXO_CLK>,
4646 <&rpmhcc RPM 4559 <&rpmhcc RPMH_CXO_CLK_A>,
4647 <&sleep_clk> 4560 <&sleep_clk>;
4648 clock-names = "iface" 4561 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
4649 power-domains = <&rpm 4562 power-domains = <&rpmhpd RPMHPD_MMCX>;
4650 required-opps = <&rpm 4563 required-opps = <&rpmhpd_opp_low_svs>;
4651 status = "disabled"; 4564 status = "disabled";
4652 #clock-cells = <1>; 4565 #clock-cells = <1>;
4653 #reset-cells = <1>; 4566 #reset-cells = <1>;
4654 #power-domain-cells = 4567 #power-domain-cells = <1>;
4655 }; 4568 };
4656 4569
4657 mdss: display-subsystem@ae000 4570 mdss: display-subsystem@ae00000 {
4658 compatible = "qcom,sm 4571 compatible = "qcom,sm8250-mdss";
4659 reg = <0 0x0ae00000 0 4572 reg = <0 0x0ae00000 0 0x1000>;
4660 reg-names = "mdss"; 4573 reg-names = "mdss";
4661 4574
4662 interconnects = <&mms 4575 interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mc_virt SLAVE_EBI_CH0 0>,
4663 <&mms 4576 <&mmss_noc MASTER_MDP_PORT1 0 &mc_virt SLAVE_EBI_CH0 0>;
4664 interconnect-names = 4577 interconnect-names = "mdp0-mem", "mdp1-mem";
4665 4578
4666 power-domains = <&dis 4579 power-domains = <&dispcc MDSS_GDSC>;
4667 4580
4668 clocks = <&dispcc DIS 4581 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4669 <&gcc GCC_DI 4582 <&gcc GCC_DISP_HF_AXI_CLK>,
4670 <&gcc GCC_DI 4583 <&gcc GCC_DISP_SF_AXI_CLK>,
4671 <&dispcc DIS 4584 <&dispcc DISP_CC_MDSS_MDP_CLK>;
4672 clock-names = "iface" 4585 clock-names = "iface", "bus", "nrt_bus", "core";
4673 4586
4674 interrupts = <GIC_SPI 4587 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
4675 interrupt-controller; 4588 interrupt-controller;
4676 #interrupt-cells = <1 4589 #interrupt-cells = <1>;
4677 4590
4678 iommus = <&apps_smmu 4591 iommus = <&apps_smmu 0x820 0x402>;
4679 4592
4680 status = "disabled"; 4593 status = "disabled";
4681 4594
4682 #address-cells = <2>; 4595 #address-cells = <2>;
4683 #size-cells = <2>; 4596 #size-cells = <2>;
4684 ranges; 4597 ranges;
4685 4598
4686 mdss_mdp: display-con 4599 mdss_mdp: display-controller@ae01000 {
4687 compatible = 4600 compatible = "qcom,sm8250-dpu";
4688 reg = <0 0x0a 4601 reg = <0 0x0ae01000 0 0x8f000>,
4689 <0 0x0a 4602 <0 0x0aeb0000 0 0x2008>;
4690 reg-names = " 4603 reg-names = "mdp", "vbif";
4691 4604
4692 clocks = <&di 4605 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4693 <&gc 4606 <&gcc GCC_DISP_HF_AXI_CLK>,
4694 <&di 4607 <&dispcc DISP_CC_MDSS_MDP_CLK>,
4695 <&di 4608 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4696 clock-names = 4609 clock-names = "iface", "bus", "core", "vsync";
4697 4610
4698 assigned-cloc 4611 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4699 assigned-cloc 4612 assigned-clock-rates = <19200000>;
4700 4613
4701 operating-poi 4614 operating-points-v2 = <&mdp_opp_table>;
4702 power-domains 4615 power-domains = <&rpmhpd RPMHPD_MMCX>;
4703 4616
4704 interrupt-par 4617 interrupt-parent = <&mdss>;
4705 interrupts = 4618 interrupts = <0>;
4706 4619
4707 ports { 4620 ports {
4708 #addr 4621 #address-cells = <1>;
4709 #size 4622 #size-cells = <0>;
4710 4623
4711 port@ 4624 port@0 {
4712 4625 reg = <0>;
4713 4626 dpu_intf1_out: endpoint {
4714 4627 remote-endpoint = <&mdss_dsi0_in>;
4715 4628 };
4716 }; 4629 };
4717 4630
4718 port@ 4631 port@1 {
4719 4632 reg = <1>;
4720 4633 dpu_intf2_out: endpoint {
4721 4634 remote-endpoint = <&mdss_dsi1_in>;
4722 4635 };
4723 }; 4636 };
4724 4637
4725 port@ 4638 port@2 {
4726 4639 reg = <2>;
4727 4640
4728 4641 dpu_intf0_out: endpoint {
4729 4642 remote-endpoint = <&mdss_dp_in>;
4730 4643 };
4731 }; 4644 };
4732 }; 4645 };
4733 4646
4734 mdp_opp_table 4647 mdp_opp_table: opp-table {
4735 compa 4648 compatible = "operating-points-v2";
4736 4649
4737 opp-2 4650 opp-200000000 {
4738 4651 opp-hz = /bits/ 64 <200000000>;
4739 4652 required-opps = <&rpmhpd_opp_low_svs>;
4740 }; 4653 };
4741 4654
4742 opp-3 4655 opp-300000000 {
4743 4656 opp-hz = /bits/ 64 <300000000>;
4744 4657 required-opps = <&rpmhpd_opp_svs>;
4745 }; 4658 };
4746 4659
4747 opp-3 4660 opp-345000000 {
4748 4661 opp-hz = /bits/ 64 <345000000>;
4749 4662 required-opps = <&rpmhpd_opp_svs_l1>;
4750 }; 4663 };
4751 4664
4752 opp-4 4665 opp-460000000 {
4753 4666 opp-hz = /bits/ 64 <460000000>;
4754 4667 required-opps = <&rpmhpd_opp_nom>;
4755 }; 4668 };
4756 }; 4669 };
4757 }; 4670 };
4758 4671
4759 mdss_dp: displayport- 4672 mdss_dp: displayport-controller@ae90000 {
4760 compatible = 4673 compatible = "qcom,sm8250-dp", "qcom,sm8350-dp";
4761 reg = <0 0xae 4674 reg = <0 0xae90000 0 0x200>,
4762 <0 0xae 4675 <0 0xae90200 0 0x200>,
4763 <0 0xae 4676 <0 0xae90400 0 0x600>,
4764 <0 0xae 4677 <0 0xae91000 0 0x400>,
4765 <0 0xae 4678 <0 0xae91400 0 0x400>;
4766 interrupt-par 4679 interrupt-parent = <&mdss>;
4767 interrupts = 4680 interrupts = <12>;
4768 clocks = <&di 4681 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4769 <&di 4682 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
4770 <&di 4683 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
4771 <&di 4684 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
4772 <&di 4685 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
4773 clock-names = 4686 clock-names = "core_iface",
4774 4687 "core_aux",
4775 4688 "ctrl_link",
4776 4689 "ctrl_link_iface",
4777 4690 "stream_pixel";
4778 4691
4779 assigned-cloc 4692 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
4780 4693 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
4781 assigned-cloc 4694 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4782 4695 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
4783 4696
4784 phys = <&usb_ 4697 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
4785 phy-names = " 4698 phy-names = "dp";
4786 4699
4787 #sound-dai-ce 4700 #sound-dai-cells = <0>;
4788 4701
4789 operating-poi 4702 operating-points-v2 = <&dp_opp_table>;
4790 power-domains 4703 power-domains = <&rpmhpd SM8250_MMCX>;
4791 4704
4792 status = "dis 4705 status = "disabled";
4793 4706
4794 ports { 4707 ports {
4795 #addr 4708 #address-cells = <1>;
4796 #size 4709 #size-cells = <0>;
4797 4710
4798 port@ 4711 port@0 {
4799 4712 reg = <0>;
4800 4713 mdss_dp_in: endpoint {
4801 4714 remote-endpoint = <&dpu_intf0_out>;
4802 4715 };
4803 }; 4716 };
4804 4717
4805 port@ 4718 port@1 {
4806 4719 reg = <1>;
4807 4720
4808 4721 mdss_dp_out: endpoint {
4809 4722 };
4810 }; 4723 };
4811 }; 4724 };
4812 4725
4813 dp_opp_table: 4726 dp_opp_table: opp-table {
4814 compa 4727 compatible = "operating-points-v2";
4815 4728
4816 opp-1 4729 opp-160000000 {
4817 4730 opp-hz = /bits/ 64 <160000000>;
4818 4731 required-opps = <&rpmhpd_opp_low_svs>;
4819 }; 4732 };
4820 4733
4821 opp-2 4734 opp-270000000 {
4822 4735 opp-hz = /bits/ 64 <270000000>;
4823 4736 required-opps = <&rpmhpd_opp_svs>;
4824 }; 4737 };
4825 4738
4826 opp-5 4739 opp-540000000 {
4827 4740 opp-hz = /bits/ 64 <540000000>;
4828 4741 required-opps = <&rpmhpd_opp_svs_l1>;
4829 }; 4742 };
4830 4743
4831 opp-8 4744 opp-810000000 {
4832 4745 opp-hz = /bits/ 64 <810000000>;
4833 4746 required-opps = <&rpmhpd_opp_nom>;
4834 }; 4747 };
4835 }; 4748 };
4836 }; 4749 };
4837 4750
4838 mdss_dsi0: dsi@ae9400 4751 mdss_dsi0: dsi@ae94000 {
4839 compatible = 4752 compatible = "qcom,sm8250-dsi-ctrl",
4840 4753 "qcom,mdss-dsi-ctrl";
4841 reg = <0 0x0a 4754 reg = <0 0x0ae94000 0 0x400>;
4842 reg-names = " 4755 reg-names = "dsi_ctrl";
4843 4756
4844 interrupt-par 4757 interrupt-parent = <&mdss>;
4845 interrupts = 4758 interrupts = <4>;
4846 4759
4847 clocks = <&di 4760 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
4848 <&di 4761 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
4849 <&di 4762 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
4850 <&di 4763 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
4851 <&di 4764 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4852 <&gcc 4765 <&gcc GCC_DISP_HF_AXI_CLK>;
4853 clock-names = 4766 clock-names = "byte",
4854 4767 "byte_intf",
4855 4768 "pixel",
4856 4769 "core",
4857 4770 "iface",
4858 4771 "bus";
4859 4772
4860 assigned-cloc 4773 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
4861 assigned-cloc 4774 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
4862 4775
4863 operating-poi 4776 operating-points-v2 = <&dsi_opp_table>;
4864 power-domains 4777 power-domains = <&rpmhpd RPMHPD_MMCX>;
4865 4778
4866 phys = <&mdss 4779 phys = <&mdss_dsi0_phy>;
4867 4780
4868 status = "dis 4781 status = "disabled";
4869 4782
4870 #address-cell 4783 #address-cells = <1>;
4871 #size-cells = 4784 #size-cells = <0>;
4872 4785
4873 ports { 4786 ports {
4874 #addr 4787 #address-cells = <1>;
4875 #size 4788 #size-cells = <0>;
4876 4789
4877 port@ 4790 port@0 {
4878 4791 reg = <0>;
4879 4792 mdss_dsi0_in: endpoint {
4880 4793 remote-endpoint = <&dpu_intf1_out>;
4881 4794 };
4882 }; 4795 };
4883 4796
4884 port@ 4797 port@1 {
4885 4798 reg = <1>;
4886 4799 mdss_dsi0_out: endpoint {
4887 4800 };
4888 }; 4801 };
4889 }; 4802 };
4890 4803
4891 dsi_opp_table 4804 dsi_opp_table: opp-table {
4892 compa 4805 compatible = "operating-points-v2";
4893 4806
4894 opp-1 4807 opp-187500000 {
4895 4808 opp-hz = /bits/ 64 <187500000>;
4896 4809 required-opps = <&rpmhpd_opp_low_svs>;
4897 }; 4810 };
4898 4811
4899 opp-3 4812 opp-300000000 {
4900 4813 opp-hz = /bits/ 64 <300000000>;
4901 4814 required-opps = <&rpmhpd_opp_svs>;
4902 }; 4815 };
4903 4816
4904 opp-3 4817 opp-358000000 {
4905 4818 opp-hz = /bits/ 64 <358000000>;
4906 4819 required-opps = <&rpmhpd_opp_svs_l1>;
4907 }; 4820 };
4908 }; 4821 };
4909 }; 4822 };
4910 4823
4911 mdss_dsi0_phy: phy@ae 4824 mdss_dsi0_phy: phy@ae94400 {
4912 compatible = 4825 compatible = "qcom,dsi-phy-7nm";
4913 reg = <0 0x0a 4826 reg = <0 0x0ae94400 0 0x200>,
4914 <0 0x0a 4827 <0 0x0ae94600 0 0x280>,
4915 <0 0x0a 4828 <0 0x0ae94900 0 0x260>;
4916 reg-names = " 4829 reg-names = "dsi_phy",
4917 " 4830 "dsi_phy_lane",
4918 " 4831 "dsi_pll";
4919 4832
4920 #clock-cells 4833 #clock-cells = <1>;
4921 #phy-cells = 4834 #phy-cells = <0>;
4922 4835
4923 clocks = <&di 4836 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4924 <&rp 4837 <&rpmhcc RPMH_CXO_CLK>;
4925 clock-names = 4838 clock-names = "iface", "ref";
4926 4839
4927 status = "dis 4840 status = "disabled";
4928 }; 4841 };
4929 4842
4930 mdss_dsi1: dsi@ae9600 4843 mdss_dsi1: dsi@ae96000 {
4931 compatible = 4844 compatible = "qcom,sm8250-dsi-ctrl",
4932 4845 "qcom,mdss-dsi-ctrl";
4933 reg = <0 0x0a 4846 reg = <0 0x0ae96000 0 0x400>;
4934 reg-names = " 4847 reg-names = "dsi_ctrl";
4935 4848
4936 interrupt-par 4849 interrupt-parent = <&mdss>;
4937 interrupts = 4850 interrupts = <5>;
4938 4851
4939 clocks = <&di 4852 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
4940 <&di 4853 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
4941 <&di 4854 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
4942 <&di 4855 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
4943 <&di 4856 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4944 <&gc 4857 <&gcc GCC_DISP_HF_AXI_CLK>;
4945 clock-names = 4858 clock-names = "byte",
4946 4859 "byte_intf",
4947 4860 "pixel",
4948 4861 "core",
4949 4862 "iface",
4950 4863 "bus";
4951 4864
4952 assigned-cloc 4865 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
4953 assigned-cloc 4866 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
4954 4867
4955 operating-poi 4868 operating-points-v2 = <&dsi_opp_table>;
4956 power-domains 4869 power-domains = <&rpmhpd RPMHPD_MMCX>;
4957 4870
4958 phys = <&mdss 4871 phys = <&mdss_dsi1_phy>;
4959 4872
4960 status = "dis 4873 status = "disabled";
4961 4874
4962 #address-cell 4875 #address-cells = <1>;
4963 #size-cells = 4876 #size-cells = <0>;
4964 4877
4965 ports { 4878 ports {
4966 #addr 4879 #address-cells = <1>;
4967 #size 4880 #size-cells = <0>;
4968 4881
4969 port@ 4882 port@0 {
4970 4883 reg = <0>;
4971 4884 mdss_dsi1_in: endpoint {
4972 4885 remote-endpoint = <&dpu_intf2_out>;
4973 4886 };
4974 }; 4887 };
4975 4888
4976 port@ 4889 port@1 {
4977 4890 reg = <1>;
4978 4891 mdss_dsi1_out: endpoint {
4979 4892 };
4980 }; 4893 };
4981 }; 4894 };
4982 }; 4895 };
4983 4896
4984 mdss_dsi1_phy: phy@ae 4897 mdss_dsi1_phy: phy@ae96400 {
4985 compatible = 4898 compatible = "qcom,dsi-phy-7nm";
4986 reg = <0 0x0a 4899 reg = <0 0x0ae96400 0 0x200>,
4987 <0 0x0a 4900 <0 0x0ae96600 0 0x280>,
4988 <0 0x0a 4901 <0 0x0ae96900 0 0x260>;
4989 reg-names = " 4902 reg-names = "dsi_phy",
4990 " 4903 "dsi_phy_lane",
4991 " 4904 "dsi_pll";
4992 4905
4993 #clock-cells 4906 #clock-cells = <1>;
4994 #phy-cells = 4907 #phy-cells = <0>;
4995 4908
4996 clocks = <&di 4909 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4997 <&rp 4910 <&rpmhcc RPMH_CXO_CLK>;
4998 clock-names = 4911 clock-names = "iface", "ref";
4999 4912
5000 status = "dis 4913 status = "disabled";
5001 }; 4914 };
5002 }; 4915 };
5003 4916
5004 dispcc: clock-controller@af00 4917 dispcc: clock-controller@af00000 {
5005 compatible = "qcom,sm 4918 compatible = "qcom,sm8250-dispcc";
5006 reg = <0 0x0af00000 0 4919 reg = <0 0x0af00000 0 0x10000>;
5007 power-domains = <&rpm 4920 power-domains = <&rpmhpd RPMHPD_MMCX>;
5008 required-opps = <&rpm 4921 required-opps = <&rpmhpd_opp_low_svs>;
5009 clocks = <&rpmhcc RPM 4922 clocks = <&rpmhcc RPMH_CXO_CLK>,
5010 <&mdss_dsi0_ 4923 <&mdss_dsi0_phy 0>,
5011 <&mdss_dsi0_ 4924 <&mdss_dsi0_phy 1>,
5012 <&mdss_dsi1_ 4925 <&mdss_dsi1_phy 0>,
5013 <&mdss_dsi1_ 4926 <&mdss_dsi1_phy 1>,
5014 <&usb_1_qmpp 4927 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
5015 <&usb_1_qmpp 4928 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
5016 clock-names = "bi_tcx 4929 clock-names = "bi_tcxo",
5017 "dsi0_p 4930 "dsi0_phy_pll_out_byteclk",
5018 "dsi0_p 4931 "dsi0_phy_pll_out_dsiclk",
5019 "dsi1_p 4932 "dsi1_phy_pll_out_byteclk",
5020 "dsi1_p 4933 "dsi1_phy_pll_out_dsiclk",
5021 "dp_phy 4934 "dp_phy_pll_link_clk",
5022 "dp_phy 4935 "dp_phy_pll_vco_div_clk";
5023 #clock-cells = <1>; 4936 #clock-cells = <1>;
5024 #reset-cells = <1>; 4937 #reset-cells = <1>;
5025 #power-domain-cells = 4938 #power-domain-cells = <1>;
5026 }; 4939 };
5027 4940
5028 pdc: interrupt-controller@b22 4941 pdc: interrupt-controller@b220000 {
5029 compatible = "qcom,sm 4942 compatible = "qcom,sm8250-pdc", "qcom,pdc";
5030 reg = <0 0x0b220000 0 4943 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
5031 qcom,pdc-ranges = <0 4944 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
5032 <12 4945 <125 63 1>, <126 716 12>;
5033 #interrupt-cells = <2 4946 #interrupt-cells = <2>;
5034 interrupt-parent = <& 4947 interrupt-parent = <&intc>;
5035 interrupt-controller; 4948 interrupt-controller;
5036 }; 4949 };
5037 4950
5038 tsens0: thermal-sensor@c26300 4951 tsens0: thermal-sensor@c263000 {
5039 compatible = "qcom,sm 4952 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
5040 reg = <0 0x0c263000 0 4953 reg = <0 0x0c263000 0 0x1ff>, /* TM */
5041 <0 0x0c222000 0 4954 <0 0x0c222000 0 0x1ff>; /* SROT */
5042 #qcom,sensors = <16>; 4955 #qcom,sensors = <16>;
5043 interrupts = <GIC_SPI 4956 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
5044 <GIC_SPI 4957 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
5045 interrupt-names = "up 4958 interrupt-names = "uplow", "critical";
5046 #thermal-sensor-cells 4959 #thermal-sensor-cells = <1>;
5047 }; 4960 };
5048 4961
5049 tsens1: thermal-sensor@c26500 4962 tsens1: thermal-sensor@c265000 {
5050 compatible = "qcom,sm 4963 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
5051 reg = <0 0x0c265000 0 4964 reg = <0 0x0c265000 0 0x1ff>, /* TM */
5052 <0 0x0c223000 0 4965 <0 0x0c223000 0 0x1ff>; /* SROT */
5053 #qcom,sensors = <9>; 4966 #qcom,sensors = <9>;
5054 interrupts = <GIC_SPI 4967 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
5055 <GIC_SPI 4968 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
5056 interrupt-names = "up 4969 interrupt-names = "uplow", "critical";
5057 #thermal-sensor-cells 4970 #thermal-sensor-cells = <1>;
5058 }; 4971 };
5059 4972
5060 aoss_qmp: power-management@c3 4973 aoss_qmp: power-management@c300000 {
5061 compatible = "qcom,sm 4974 compatible = "qcom,sm8250-aoss-qmp", "qcom,aoss-qmp";
5062 reg = <0 0x0c300000 0 4975 reg = <0 0x0c300000 0 0x400>;
5063 interrupts-extended = 4976 interrupts-extended = <&ipcc IPCC_CLIENT_AOP
5064 4977 IPCC_MPROC_SIGNAL_GLINK_QMP
5065 4978 IRQ_TYPE_EDGE_RISING>;
5066 mboxes = <&ipcc IPCC_ 4979 mboxes = <&ipcc IPCC_CLIENT_AOP
5067 IPCC_ 4980 IPCC_MPROC_SIGNAL_GLINK_QMP>;
5068 4981
5069 #clock-cells = <0>; 4982 #clock-cells = <0>;
5070 }; 4983 };
5071 4984
5072 sram@c3f0000 { 4985 sram@c3f0000 {
5073 compatible = "qcom,rp 4986 compatible = "qcom,rpmh-stats";
5074 reg = <0 0x0c3f0000 0 4987 reg = <0 0x0c3f0000 0 0x400>;
5075 }; 4988 };
5076 4989
5077 spmi_bus: spmi@c440000 { 4990 spmi_bus: spmi@c440000 {
5078 compatible = "qcom,sp 4991 compatible = "qcom,spmi-pmic-arb";
5079 reg = <0x0 0x0c440000 4992 reg = <0x0 0x0c440000 0x0 0x0001100>,
5080 <0x0 0x0c600000 4993 <0x0 0x0c600000 0x0 0x2000000>,
5081 <0x0 0x0e600000 4994 <0x0 0x0e600000 0x0 0x0100000>,
5082 <0x0 0x0e700000 4995 <0x0 0x0e700000 0x0 0x00a0000>,
5083 <0x0 0x0c40a000 4996 <0x0 0x0c40a000 0x0 0x0026000>;
5084 reg-names = "core", " 4997 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
5085 interrupt-names = "pe 4998 interrupt-names = "periph_irq";
5086 interrupts-extended = 4999 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
5087 qcom,ee = <0>; 5000 qcom,ee = <0>;
5088 qcom,channel = <0>; 5001 qcom,channel = <0>;
5089 #address-cells = <2>; 5002 #address-cells = <2>;
5090 #size-cells = <0>; 5003 #size-cells = <0>;
5091 interrupt-controller; 5004 interrupt-controller;
5092 #interrupt-cells = <4 5005 #interrupt-cells = <4>;
5093 }; 5006 };
5094 5007
5095 tlmm: pinctrl@f100000 { 5008 tlmm: pinctrl@f100000 {
5096 compatible = "qcom,sm 5009 compatible = "qcom,sm8250-pinctrl";
5097 reg = <0 0x0f100000 0 5010 reg = <0 0x0f100000 0 0x300000>,
5098 <0 0x0f500000 0 5011 <0 0x0f500000 0 0x300000>,
5099 <0 0x0f900000 0 5012 <0 0x0f900000 0 0x300000>;
5100 reg-names = "west", " 5013 reg-names = "west", "south", "north";
5101 interrupts = <GIC_SPI 5014 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
5102 gpio-controller; 5015 gpio-controller;
5103 #gpio-cells = <2>; 5016 #gpio-cells = <2>;
5104 interrupt-controller; 5017 interrupt-controller;
5105 #interrupt-cells = <2 5018 #interrupt-cells = <2>;
5106 gpio-ranges = <&tlmm 5019 gpio-ranges = <&tlmm 0 0 181>;
5107 wakeup-parent = <&pdc 5020 wakeup-parent = <&pdc>;
5108 5021
5109 cam2_default: cam2-de 5022 cam2_default: cam2-default-state {
5110 rst-pins { 5023 rst-pins {
5111 pins 5024 pins = "gpio78";
5112 funct 5025 function = "gpio";
5113 drive 5026 drive-strength = <2>;
5114 bias- 5027 bias-disable;
5115 }; 5028 };
5116 5029
5117 mclk-pins { 5030 mclk-pins {
5118 pins 5031 pins = "gpio96";
5119 funct 5032 function = "cam_mclk";
5120 drive 5033 drive-strength = <16>;
5121 bias- 5034 bias-disable;
5122 }; 5035 };
5123 }; 5036 };
5124 5037
5125 cam2_suspend: cam2-su 5038 cam2_suspend: cam2-suspend-state {
5126 rst-pins { 5039 rst-pins {
5127 pins 5040 pins = "gpio78";
5128 funct 5041 function = "gpio";
5129 drive 5042 drive-strength = <2>;
5130 bias- 5043 bias-pull-down;
5131 outpu 5044 output-low;
5132 }; 5045 };
5133 5046
5134 mclk-pins { 5047 mclk-pins {
5135 pins 5048 pins = "gpio96";
5136 funct 5049 function = "cam_mclk";
5137 drive 5050 drive-strength = <2>;
5138 bias- 5051 bias-disable;
5139 }; 5052 };
5140 }; 5053 };
5141 5054
5142 cci0_default: cci0-de 5055 cci0_default: cci0-default-state {
5143 cci0_i2c0_def 5056 cci0_i2c0_default: cci0-i2c0-default-pins {
5144 /* SD 5057 /* SDA, SCL */
5145 pins 5058 pins = "gpio101", "gpio102";
5146 funct 5059 function = "cci_i2c";
5147 5060
5148 bias- 5061 bias-pull-up;
5149 drive 5062 drive-strength = <2>; /* 2 mA */
5150 }; 5063 };
5151 5064
5152 cci0_i2c1_def 5065 cci0_i2c1_default: cci0-i2c1-default-pins {
5153 /* SD 5066 /* SDA, SCL */
5154 pins 5067 pins = "gpio103", "gpio104";
5155 funct 5068 function = "cci_i2c";
5156 5069
5157 bias- 5070 bias-pull-up;
5158 drive 5071 drive-strength = <2>; /* 2 mA */
5159 }; 5072 };
5160 }; 5073 };
5161 5074
5162 cci0_sleep: cci0-slee 5075 cci0_sleep: cci0-sleep-state {
5163 cci0_i2c0_sle 5076 cci0_i2c0_sleep: cci0-i2c0-sleep-pins {
5164 /* SD 5077 /* SDA, SCL */
5165 pins 5078 pins = "gpio101", "gpio102";
5166 funct 5079 function = "cci_i2c";
5167 5080
5168 drive 5081 drive-strength = <2>; /* 2 mA */
5169 bias- 5082 bias-pull-down;
5170 }; 5083 };
5171 5084
5172 cci0_i2c1_sle 5085 cci0_i2c1_sleep: cci0-i2c1-sleep-pins {
5173 /* SD 5086 /* SDA, SCL */
5174 pins 5087 pins = "gpio103", "gpio104";
5175 funct 5088 function = "cci_i2c";
5176 5089
5177 drive 5090 drive-strength = <2>; /* 2 mA */
5178 bias- 5091 bias-pull-down;
5179 }; 5092 };
5180 }; 5093 };
5181 5094
5182 cci1_default: cci1-de 5095 cci1_default: cci1-default-state {
5183 cci1_i2c0_def 5096 cci1_i2c0_default: cci1-i2c0-default-pins {
5184 /* SD 5097 /* SDA, SCL */
5185 pins 5098 pins = "gpio105","gpio106";
5186 funct 5099 function = "cci_i2c";
5187 5100
5188 bias- 5101 bias-pull-up;
5189 drive 5102 drive-strength = <2>; /* 2 mA */
5190 }; 5103 };
5191 5104
5192 cci1_i2c1_def 5105 cci1_i2c1_default: cci1-i2c1-default-pins {
5193 /* SD 5106 /* SDA, SCL */
5194 pins 5107 pins = "gpio107","gpio108";
5195 funct 5108 function = "cci_i2c";
5196 5109
5197 bias- 5110 bias-pull-up;
5198 drive 5111 drive-strength = <2>; /* 2 mA */
5199 }; 5112 };
5200 }; 5113 };
5201 5114
5202 cci1_sleep: cci1-slee 5115 cci1_sleep: cci1-sleep-state {
5203 cci1_i2c0_sle 5116 cci1_i2c0_sleep: cci1-i2c0-sleep-pins {
5204 /* SD 5117 /* SDA, SCL */
5205 pins 5118 pins = "gpio105","gpio106";
5206 funct 5119 function = "cci_i2c";
5207 5120
5208 bias- 5121 bias-pull-down;
5209 drive 5122 drive-strength = <2>; /* 2 mA */
5210 }; 5123 };
5211 5124
5212 cci1_i2c1_sle 5125 cci1_i2c1_sleep: cci1-i2c1-sleep-pins {
5213 /* SD 5126 /* SDA, SCL */
5214 pins 5127 pins = "gpio107","gpio108";
5215 funct 5128 function = "cci_i2c";
5216 5129
5217 bias- 5130 bias-pull-down;
5218 drive 5131 drive-strength = <2>; /* 2 mA */
5219 }; 5132 };
5220 }; 5133 };
5221 5134
5222 pri_mi2s_active: pri- 5135 pri_mi2s_active: pri-mi2s-active-state {
5223 sclk-pins { 5136 sclk-pins {
5224 pins 5137 pins = "gpio138";
5225 funct 5138 function = "mi2s0_sck";
5226 drive 5139 drive-strength = <8>;
5227 bias- 5140 bias-disable;
5228 }; 5141 };
5229 5142
5230 ws-pins { 5143 ws-pins {
5231 pins 5144 pins = "gpio141";
5232 funct 5145 function = "mi2s0_ws";
5233 drive 5146 drive-strength = <8>;
5234 outpu 5147 output-high;
5235 }; 5148 };
5236 5149
5237 data0-pins { 5150 data0-pins {
5238 pins 5151 pins = "gpio139";
5239 funct 5152 function = "mi2s0_data0";
5240 drive 5153 drive-strength = <8>;
5241 bias- 5154 bias-disable;
5242 outpu 5155 output-high;
5243 }; 5156 };
5244 5157
5245 data1-pins { 5158 data1-pins {
5246 pins 5159 pins = "gpio140";
5247 funct 5160 function = "mi2s0_data1";
5248 drive 5161 drive-strength = <8>;
5249 outpu 5162 output-high;
5250 }; 5163 };
5251 }; 5164 };
5252 5165
5253 qup_i2c0_default: qup 5166 qup_i2c0_default: qup-i2c0-default-state {
5254 pins = "gpio2 5167 pins = "gpio28", "gpio29";
5255 function = "q 5168 function = "qup0";
5256 drive-strengt 5169 drive-strength = <2>;
5257 bias-disable; 5170 bias-disable;
5258 }; 5171 };
5259 5172
5260 qup_i2c1_default: qup 5173 qup_i2c1_default: qup-i2c1-default-state {
5261 pins = "gpio4 5174 pins = "gpio4", "gpio5";
5262 function = "q 5175 function = "qup1";
5263 drive-strengt 5176 drive-strength = <2>;
5264 bias-disable; 5177 bias-disable;
5265 }; 5178 };
5266 5179
5267 qup_i2c2_default: qup 5180 qup_i2c2_default: qup-i2c2-default-state {
5268 pins = "gpio1 5181 pins = "gpio115", "gpio116";
5269 function = "q 5182 function = "qup2";
5270 drive-strengt 5183 drive-strength = <2>;
5271 bias-disable; 5184 bias-disable;
5272 }; 5185 };
5273 5186
5274 qup_i2c3_default: qup 5187 qup_i2c3_default: qup-i2c3-default-state {
5275 pins = "gpio1 5188 pins = "gpio119", "gpio120";
5276 function = "q 5189 function = "qup3";
5277 drive-strengt 5190 drive-strength = <2>;
5278 bias-disable; 5191 bias-disable;
5279 }; 5192 };
5280 5193
5281 qup_i2c4_default: qup 5194 qup_i2c4_default: qup-i2c4-default-state {
5282 pins = "gpio8 5195 pins = "gpio8", "gpio9";
5283 function = "q 5196 function = "qup4";
5284 drive-strengt 5197 drive-strength = <2>;
5285 bias-disable; 5198 bias-disable;
5286 }; 5199 };
5287 5200
5288 qup_i2c5_default: qup 5201 qup_i2c5_default: qup-i2c5-default-state {
5289 pins = "gpio1 5202 pins = "gpio12", "gpio13";
5290 function = "q 5203 function = "qup5";
5291 drive-strengt 5204 drive-strength = <2>;
5292 bias-disable; 5205 bias-disable;
5293 }; 5206 };
5294 5207
5295 qup_i2c6_default: qup 5208 qup_i2c6_default: qup-i2c6-default-state {
5296 pins = "gpio1 5209 pins = "gpio16", "gpio17";
5297 function = "q 5210 function = "qup6";
5298 drive-strengt 5211 drive-strength = <2>;
5299 bias-disable; 5212 bias-disable;
5300 }; 5213 };
5301 5214
5302 qup_i2c7_default: qup 5215 qup_i2c7_default: qup-i2c7-default-state {
5303 pins = "gpio2 5216 pins = "gpio20", "gpio21";
5304 function = "q 5217 function = "qup7";
5305 drive-strengt 5218 drive-strength = <2>;
5306 bias-disable; 5219 bias-disable;
5307 }; 5220 };
5308 5221
5309 qup_i2c8_default: qup 5222 qup_i2c8_default: qup-i2c8-default-state {
5310 pins = "gpio2 5223 pins = "gpio24", "gpio25";
5311 function = "q 5224 function = "qup8";
5312 drive-strengt 5225 drive-strength = <2>;
5313 bias-disable; 5226 bias-disable;
5314 }; 5227 };
5315 5228
5316 qup_i2c9_default: qup 5229 qup_i2c9_default: qup-i2c9-default-state {
5317 pins = "gpio1 5230 pins = "gpio125", "gpio126";
5318 function = "q 5231 function = "qup9";
5319 drive-strengt 5232 drive-strength = <2>;
5320 bias-disable; 5233 bias-disable;
5321 }; 5234 };
5322 5235
5323 qup_i2c10_default: qu 5236 qup_i2c10_default: qup-i2c10-default-state {
5324 pins = "gpio1 5237 pins = "gpio129", "gpio130";
5325 function = "q 5238 function = "qup10";
5326 drive-strengt 5239 drive-strength = <2>;
5327 bias-disable; 5240 bias-disable;
5328 }; 5241 };
5329 5242
5330 qup_i2c11_default: qu 5243 qup_i2c11_default: qup-i2c11-default-state {
5331 pins = "gpio6 5244 pins = "gpio60", "gpio61";
5332 function = "q 5245 function = "qup11";
5333 drive-strengt 5246 drive-strength = <2>;
5334 bias-disable; 5247 bias-disable;
5335 }; 5248 };
5336 5249
5337 qup_i2c12_default: qu 5250 qup_i2c12_default: qup-i2c12-default-state {
5338 pins = "gpio3 5251 pins = "gpio32", "gpio33";
5339 function = "q 5252 function = "qup12";
5340 drive-strengt 5253 drive-strength = <2>;
5341 bias-disable; 5254 bias-disable;
5342 }; 5255 };
5343 5256
5344 qup_i2c13_default: qu 5257 qup_i2c13_default: qup-i2c13-default-state {
5345 pins = "gpio3 5258 pins = "gpio36", "gpio37";
5346 function = "q 5259 function = "qup13";
5347 drive-strengt 5260 drive-strength = <2>;
5348 bias-disable; 5261 bias-disable;
5349 }; 5262 };
5350 5263
5351 qup_i2c14_default: qu 5264 qup_i2c14_default: qup-i2c14-default-state {
5352 pins = "gpio4 5265 pins = "gpio40", "gpio41";
5353 function = "q 5266 function = "qup14";
5354 drive-strengt 5267 drive-strength = <2>;
5355 bias-disable; 5268 bias-disable;
5356 }; 5269 };
5357 5270
5358 qup_i2c15_default: qu 5271 qup_i2c15_default: qup-i2c15-default-state {
5359 pins = "gpio4 5272 pins = "gpio44", "gpio45";
5360 function = "q 5273 function = "qup15";
5361 drive-strengt 5274 drive-strength = <2>;
5362 bias-disable; 5275 bias-disable;
5363 }; 5276 };
5364 5277
5365 qup_i2c16_default: qu 5278 qup_i2c16_default: qup-i2c16-default-state {
5366 pins = "gpio4 5279 pins = "gpio48", "gpio49";
5367 function = "q 5280 function = "qup16";
5368 drive-strengt 5281 drive-strength = <2>;
5369 bias-disable; 5282 bias-disable;
5370 }; 5283 };
5371 5284
5372 qup_i2c17_default: qu 5285 qup_i2c17_default: qup-i2c17-default-state {
5373 pins = "gpio5 5286 pins = "gpio52", "gpio53";
5374 function = "q 5287 function = "qup17";
5375 drive-strengt 5288 drive-strength = <2>;
5376 bias-disable; 5289 bias-disable;
5377 }; 5290 };
5378 5291
5379 qup_i2c18_default: qu 5292 qup_i2c18_default: qup-i2c18-default-state {
5380 pins = "gpio5 5293 pins = "gpio56", "gpio57";
5381 function = "q 5294 function = "qup18";
5382 drive-strengt 5295 drive-strength = <2>;
5383 bias-disable; 5296 bias-disable;
5384 }; 5297 };
5385 5298
5386 qup_i2c19_default: qu 5299 qup_i2c19_default: qup-i2c19-default-state {
5387 pins = "gpio0 5300 pins = "gpio0", "gpio1";
5388 function = "q 5301 function = "qup19";
5389 drive-strengt 5302 drive-strength = <2>;
5390 bias-disable; 5303 bias-disable;
5391 }; 5304 };
5392 5305
5393 qup_spi0_cs: qup-spi0 5306 qup_spi0_cs: qup-spi0-cs-state {
5394 pins = "gpio3 5307 pins = "gpio31";
5395 function = "q 5308 function = "qup0";
5396 }; 5309 };
5397 5310
5398 qup_spi0_cs_gpio: qup 5311 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state {
5399 pins = "gpio3 5312 pins = "gpio31";
5400 function = "g 5313 function = "gpio";
5401 }; 5314 };
5402 5315
5403 qup_spi0_data_clk: qu 5316 qup_spi0_data_clk: qup-spi0-data-clk-state {
5404 pins = "gpio2 5317 pins = "gpio28", "gpio29",
5405 "gpio3 5318 "gpio30";
5406 function = "q 5319 function = "qup0";
5407 }; 5320 };
5408 5321
5409 qup_spi1_cs: qup-spi1 5322 qup_spi1_cs: qup-spi1-cs-state {
5410 pins = "gpio7 5323 pins = "gpio7";
5411 function = "q 5324 function = "qup1";
5412 }; 5325 };
5413 5326
5414 qup_spi1_cs_gpio: qup 5327 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state {
5415 pins = "gpio7 5328 pins = "gpio7";
5416 function = "g 5329 function = "gpio";
5417 }; 5330 };
5418 5331
5419 qup_spi1_data_clk: qu 5332 qup_spi1_data_clk: qup-spi1-data-clk-state {
5420 pins = "gpio4 5333 pins = "gpio4", "gpio5",
5421 "gpio6 5334 "gpio6";
5422 function = "q 5335 function = "qup1";
5423 }; 5336 };
5424 5337
5425 qup_spi2_cs: qup-spi2 5338 qup_spi2_cs: qup-spi2-cs-state {
5426 pins = "gpio1 5339 pins = "gpio118";
5427 function = "q 5340 function = "qup2";
5428 }; 5341 };
5429 5342
5430 qup_spi2_cs_gpio: qup 5343 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state {
5431 pins = "gpio1 5344 pins = "gpio118";
5432 function = "g 5345 function = "gpio";
5433 }; 5346 };
5434 5347
5435 qup_spi2_data_clk: qu 5348 qup_spi2_data_clk: qup-spi2-data-clk-state {
5436 pins = "gpio1 5349 pins = "gpio115", "gpio116",
5437 "gpio1 5350 "gpio117";
5438 function = "q 5351 function = "qup2";
5439 }; 5352 };
5440 5353
5441 qup_spi3_cs: qup-spi3 5354 qup_spi3_cs: qup-spi3-cs-state {
5442 pins = "gpio1 5355 pins = "gpio122";
5443 function = "q 5356 function = "qup3";
5444 }; 5357 };
5445 5358
5446 qup_spi3_cs_gpio: qup 5359 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state {
5447 pins = "gpio1 5360 pins = "gpio122";
5448 function = "g 5361 function = "gpio";
5449 }; 5362 };
5450 5363
5451 qup_spi3_data_clk: qu 5364 qup_spi3_data_clk: qup-spi3-data-clk-state {
5452 pins = "gpio1 5365 pins = "gpio119", "gpio120",
5453 "gpio1 5366 "gpio121";
5454 function = "q 5367 function = "qup3";
5455 }; 5368 };
5456 5369
5457 qup_spi4_cs: qup-spi4 5370 qup_spi4_cs: qup-spi4-cs-state {
5458 pins = "gpio1 5371 pins = "gpio11";
5459 function = "q 5372 function = "qup4";
5460 }; 5373 };
5461 5374
5462 qup_spi4_cs_gpio: qup 5375 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state {
5463 pins = "gpio1 5376 pins = "gpio11";
5464 function = "g 5377 function = "gpio";
5465 }; 5378 };
5466 5379
5467 qup_spi4_data_clk: qu 5380 qup_spi4_data_clk: qup-spi4-data-clk-state {
5468 pins = "gpio8 5381 pins = "gpio8", "gpio9",
5469 "gpio1 5382 "gpio10";
5470 function = "q 5383 function = "qup4";
5471 }; 5384 };
5472 5385
5473 qup_spi5_cs: qup-spi5 5386 qup_spi5_cs: qup-spi5-cs-state {
5474 pins = "gpio1 5387 pins = "gpio15";
5475 function = "q 5388 function = "qup5";
5476 }; 5389 };
5477 5390
5478 qup_spi5_cs_gpio: qup 5391 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state {
5479 pins = "gpio1 5392 pins = "gpio15";
5480 function = "g 5393 function = "gpio";
5481 }; 5394 };
5482 5395
5483 qup_spi5_data_clk: qu 5396 qup_spi5_data_clk: qup-spi5-data-clk-state {
5484 pins = "gpio1 5397 pins = "gpio12", "gpio13",
5485 "gpio1 5398 "gpio14";
5486 function = "q 5399 function = "qup5";
5487 }; 5400 };
5488 5401
5489 qup_spi6_cs: qup-spi6 5402 qup_spi6_cs: qup-spi6-cs-state {
5490 pins = "gpio1 5403 pins = "gpio19";
5491 function = "q 5404 function = "qup6";
5492 }; 5405 };
5493 5406
5494 qup_spi6_cs_gpio: qup 5407 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state {
5495 pins = "gpio1 5408 pins = "gpio19";
5496 function = "g 5409 function = "gpio";
5497 }; 5410 };
5498 5411
5499 qup_spi6_data_clk: qu 5412 qup_spi6_data_clk: qup-spi6-data-clk-state {
5500 pins = "gpio1 5413 pins = "gpio16", "gpio17",
5501 "gpio1 5414 "gpio18";
5502 function = "q 5415 function = "qup6";
5503 }; 5416 };
5504 5417
5505 qup_spi7_cs: qup-spi7 5418 qup_spi7_cs: qup-spi7-cs-state {
5506 pins = "gpio2 5419 pins = "gpio23";
5507 function = "q 5420 function = "qup7";
5508 }; 5421 };
5509 5422
5510 qup_spi7_cs_gpio: qup 5423 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state {
5511 pins = "gpio2 5424 pins = "gpio23";
5512 function = "g 5425 function = "gpio";
5513 }; 5426 };
5514 5427
5515 qup_spi7_data_clk: qu 5428 qup_spi7_data_clk: qup-spi7-data-clk-state {
5516 pins = "gpio2 5429 pins = "gpio20", "gpio21",
5517 "gpio2 5430 "gpio22";
5518 function = "q 5431 function = "qup7";
5519 }; 5432 };
5520 5433
5521 qup_spi8_cs: qup-spi8 5434 qup_spi8_cs: qup-spi8-cs-state {
5522 pins = "gpio2 5435 pins = "gpio27";
5523 function = "q 5436 function = "qup8";
5524 }; 5437 };
5525 5438
5526 qup_spi8_cs_gpio: qup 5439 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state {
5527 pins = "gpio2 5440 pins = "gpio27";
5528 function = "g 5441 function = "gpio";
5529 }; 5442 };
5530 5443
5531 qup_spi8_data_clk: qu 5444 qup_spi8_data_clk: qup-spi8-data-clk-state {
5532 pins = "gpio2 5445 pins = "gpio24", "gpio25",
5533 "gpio2 5446 "gpio26";
5534 function = "q 5447 function = "qup8";
5535 }; 5448 };
5536 5449
5537 qup_spi9_cs: qup-spi9 5450 qup_spi9_cs: qup-spi9-cs-state {
5538 pins = "gpio1 5451 pins = "gpio128";
5539 function = "q 5452 function = "qup9";
5540 }; 5453 };
5541 5454
5542 qup_spi9_cs_gpio: qup 5455 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state {
5543 pins = "gpio1 5456 pins = "gpio128";
5544 function = "g 5457 function = "gpio";
5545 }; 5458 };
5546 5459
5547 qup_spi9_data_clk: qu 5460 qup_spi9_data_clk: qup-spi9-data-clk-state {
5548 pins = "gpio1 5461 pins = "gpio125", "gpio126",
5549 "gpio1 5462 "gpio127";
5550 function = "q 5463 function = "qup9";
5551 }; 5464 };
5552 5465
5553 qup_spi10_cs: qup-spi 5466 qup_spi10_cs: qup-spi10-cs-state {
5554 pins = "gpio1 5467 pins = "gpio132";
5555 function = "q 5468 function = "qup10";
5556 }; 5469 };
5557 5470
5558 qup_spi10_cs_gpio: qu 5471 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state {
5559 pins = "gpio1 5472 pins = "gpio132";
5560 function = "g 5473 function = "gpio";
5561 }; 5474 };
5562 5475
5563 qup_spi10_data_clk: q 5476 qup_spi10_data_clk: qup-spi10-data-clk-state {
5564 pins = "gpio1 5477 pins = "gpio129", "gpio130",
5565 "gpio1 5478 "gpio131";
5566 function = "q 5479 function = "qup10";
5567 }; 5480 };
5568 5481
5569 qup_spi11_cs: qup-spi 5482 qup_spi11_cs: qup-spi11-cs-state {
5570 pins = "gpio6 5483 pins = "gpio63";
5571 function = "q 5484 function = "qup11";
5572 }; 5485 };
5573 5486
5574 qup_spi11_cs_gpio: qu 5487 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state {
5575 pins = "gpio6 5488 pins = "gpio63";
5576 function = "g 5489 function = "gpio";
5577 }; 5490 };
5578 5491
5579 qup_spi11_data_clk: q 5492 qup_spi11_data_clk: qup-spi11-data-clk-state {
5580 pins = "gpio6 5493 pins = "gpio60", "gpio61",
5581 "gpio6 5494 "gpio62";
5582 function = "q 5495 function = "qup11";
5583 }; 5496 };
5584 5497
5585 qup_spi12_cs: qup-spi 5498 qup_spi12_cs: qup-spi12-cs-state {
5586 pins = "gpio3 5499 pins = "gpio35";
5587 function = "q 5500 function = "qup12";
5588 }; 5501 };
5589 5502
5590 qup_spi12_cs_gpio: qu 5503 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state {
5591 pins = "gpio3 5504 pins = "gpio35";
5592 function = "g 5505 function = "gpio";
5593 }; 5506 };
5594 5507
5595 qup_spi12_data_clk: q 5508 qup_spi12_data_clk: qup-spi12-data-clk-state {
5596 pins = "gpio3 5509 pins = "gpio32", "gpio33",
5597 "gpio3 5510 "gpio34";
5598 function = "q 5511 function = "qup12";
5599 }; 5512 };
5600 5513
5601 qup_spi13_cs: qup-spi 5514 qup_spi13_cs: qup-spi13-cs-state {
5602 pins = "gpio3 5515 pins = "gpio39";
5603 function = "q 5516 function = "qup13";
5604 }; 5517 };
5605 5518
5606 qup_spi13_cs_gpio: qu 5519 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state {
5607 pins = "gpio3 5520 pins = "gpio39";
5608 function = "g 5521 function = "gpio";
5609 }; 5522 };
5610 5523
5611 qup_spi13_data_clk: q 5524 qup_spi13_data_clk: qup-spi13-data-clk-state {
5612 pins = "gpio3 5525 pins = "gpio36", "gpio37",
5613 "gpio3 5526 "gpio38";
5614 function = "q 5527 function = "qup13";
5615 }; 5528 };
5616 5529
5617 qup_spi14_cs: qup-spi 5530 qup_spi14_cs: qup-spi14-cs-state {
5618 pins = "gpio4 5531 pins = "gpio43";
5619 function = "q 5532 function = "qup14";
5620 }; 5533 };
5621 5534
5622 qup_spi14_cs_gpio: qu 5535 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state {
5623 pins = "gpio4 5536 pins = "gpio43";
5624 function = "g 5537 function = "gpio";
5625 }; 5538 };
5626 5539
5627 qup_spi14_data_clk: q 5540 qup_spi14_data_clk: qup-spi14-data-clk-state {
5628 pins = "gpio4 5541 pins = "gpio40", "gpio41",
5629 "gpio4 5542 "gpio42";
5630 function = "q 5543 function = "qup14";
5631 }; 5544 };
5632 5545
5633 qup_spi15_cs: qup-spi 5546 qup_spi15_cs: qup-spi15-cs-state {
5634 pins = "gpio4 5547 pins = "gpio47";
5635 function = "q 5548 function = "qup15";
5636 }; 5549 };
5637 5550
5638 qup_spi15_cs_gpio: qu 5551 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state {
5639 pins = "gpio4 5552 pins = "gpio47";
5640 function = "g 5553 function = "gpio";
5641 }; 5554 };
5642 5555
5643 qup_spi15_data_clk: q 5556 qup_spi15_data_clk: qup-spi15-data-clk-state {
5644 pins = "gpio4 5557 pins = "gpio44", "gpio45",
5645 "gpio4 5558 "gpio46";
5646 function = "q 5559 function = "qup15";
5647 }; 5560 };
5648 5561
5649 qup_spi16_cs: qup-spi 5562 qup_spi16_cs: qup-spi16-cs-state {
5650 pins = "gpio5 5563 pins = "gpio51";
5651 function = "q 5564 function = "qup16";
5652 }; 5565 };
5653 5566
5654 qup_spi16_cs_gpio: qu 5567 qup_spi16_cs_gpio: qup-spi16-cs-gpio-state {
5655 pins = "gpio5 5568 pins = "gpio51";
5656 function = "g 5569 function = "gpio";
5657 }; 5570 };
5658 5571
5659 qup_spi16_data_clk: q 5572 qup_spi16_data_clk: qup-spi16-data-clk-state {
5660 pins = "gpio4 5573 pins = "gpio48", "gpio49",
5661 "gpio5 5574 "gpio50";
5662 function = "q 5575 function = "qup16";
5663 }; 5576 };
5664 5577
5665 qup_spi17_cs: qup-spi 5578 qup_spi17_cs: qup-spi17-cs-state {
5666 pins = "gpio5 5579 pins = "gpio55";
5667 function = "q 5580 function = "qup17";
5668 }; 5581 };
5669 5582
5670 qup_spi17_cs_gpio: qu 5583 qup_spi17_cs_gpio: qup-spi17-cs-gpio-state {
5671 pins = "gpio5 5584 pins = "gpio55";
5672 function = "g 5585 function = "gpio";
5673 }; 5586 };
5674 5587
5675 qup_spi17_data_clk: q 5588 qup_spi17_data_clk: qup-spi17-data-clk-state {
5676 pins = "gpio5 5589 pins = "gpio52", "gpio53",
5677 "gpio5 5590 "gpio54";
5678 function = "q 5591 function = "qup17";
5679 }; 5592 };
5680 5593
5681 qup_spi18_cs: qup-spi 5594 qup_spi18_cs: qup-spi18-cs-state {
5682 pins = "gpio5 5595 pins = "gpio59";
5683 function = "q 5596 function = "qup18";
5684 }; 5597 };
5685 5598
5686 qup_spi18_cs_gpio: qu 5599 qup_spi18_cs_gpio: qup-spi18-cs-gpio-state {
5687 pins = "gpio5 5600 pins = "gpio59";
5688 function = "g 5601 function = "gpio";
5689 }; 5602 };
5690 5603
5691 qup_spi18_data_clk: q 5604 qup_spi18_data_clk: qup-spi18-data-clk-state {
5692 pins = "gpio5 5605 pins = "gpio56", "gpio57",
5693 "gpio5 5606 "gpio58";
5694 function = "q 5607 function = "qup18";
5695 }; 5608 };
5696 5609
5697 qup_spi19_cs: qup-spi 5610 qup_spi19_cs: qup-spi19-cs-state {
5698 pins = "gpio3 5611 pins = "gpio3";
5699 function = "q 5612 function = "qup19";
5700 }; 5613 };
5701 5614
5702 qup_spi19_cs_gpio: qu 5615 qup_spi19_cs_gpio: qup-spi19-cs-gpio-state {
5703 pins = "gpio3 5616 pins = "gpio3";
5704 function = "g 5617 function = "gpio";
5705 }; 5618 };
5706 5619
5707 qup_spi19_data_clk: q 5620 qup_spi19_data_clk: qup-spi19-data-clk-state {
5708 pins = "gpio0 5621 pins = "gpio0", "gpio1",
5709 "gpio2 5622 "gpio2";
5710 function = "q 5623 function = "qup19";
5711 }; 5624 };
5712 5625
5713 qup_uart2_default: qu 5626 qup_uart2_default: qup-uart2-default-state {
5714 pins = "gpio1 5627 pins = "gpio117", "gpio118";
5715 function = "q 5628 function = "qup2";
5716 }; 5629 };
5717 5630
5718 qup_uart6_default: qu 5631 qup_uart6_default: qup-uart6-default-state {
5719 pins = "gpio1 5632 pins = "gpio16", "gpio17", "gpio18", "gpio19";
5720 function = "q 5633 function = "qup6";
5721 }; 5634 };
5722 5635
5723 qup_uart12_default: q 5636 qup_uart12_default: qup-uart12-default-state {
5724 pins = "gpio3 5637 pins = "gpio34", "gpio35";
5725 function = "q 5638 function = "qup12";
5726 }; 5639 };
5727 5640
5728 qup_uart17_default: q 5641 qup_uart17_default: qup-uart17-default-state {
5729 pins = "gpio5 5642 pins = "gpio52", "gpio53", "gpio54", "gpio55";
5730 function = "q 5643 function = "qup17";
5731 }; 5644 };
5732 5645
5733 qup_uart18_default: q 5646 qup_uart18_default: qup-uart18-default-state {
5734 pins = "gpio5 5647 pins = "gpio58", "gpio59";
5735 function = "q 5648 function = "qup18";
5736 }; 5649 };
5737 5650
5738 tert_mi2s_active: ter 5651 tert_mi2s_active: tert-mi2s-active-state {
5739 sck-pins { 5652 sck-pins {
5740 pins 5653 pins = "gpio133";
5741 funct 5654 function = "mi2s2_sck";
5742 drive 5655 drive-strength = <8>;
5743 bias- 5656 bias-disable;
5744 }; 5657 };
5745 5658
5746 data0-pins { 5659 data0-pins {
5747 pins 5660 pins = "gpio134";
5748 funct 5661 function = "mi2s2_data0";
5749 drive 5662 drive-strength = <8>;
5750 bias- 5663 bias-disable;
5751 outpu 5664 output-high;
5752 }; 5665 };
5753 5666
5754 ws-pins { 5667 ws-pins {
5755 pins 5668 pins = "gpio135";
5756 funct 5669 function = "mi2s2_ws";
5757 drive 5670 drive-strength = <8>;
5758 outpu 5671 output-high;
5759 }; 5672 };
5760 }; 5673 };
5761 5674
5762 sdc2_sleep_state: sdc 5675 sdc2_sleep_state: sdc2-sleep-state {
5763 clk-pins { 5676 clk-pins {
5764 pins 5677 pins = "sdc2_clk";
5765 drive 5678 drive-strength = <2>;
5766 bias- 5679 bias-disable;
5767 }; 5680 };
5768 5681
5769 cmd-pins { 5682 cmd-pins {
5770 pins 5683 pins = "sdc2_cmd";
5771 drive 5684 drive-strength = <2>;
5772 bias- 5685 bias-pull-up;
5773 }; 5686 };
5774 5687
5775 data-pins { 5688 data-pins {
5776 pins 5689 pins = "sdc2_data";
5777 drive 5690 drive-strength = <2>;
5778 bias- 5691 bias-pull-up;
5779 }; 5692 };
5780 }; 5693 };
5781 5694
5782 pcie0_default_state: 5695 pcie0_default_state: pcie0-default-state {
5783 perst-pins { 5696 perst-pins {
5784 pins 5697 pins = "gpio79";
5785 funct 5698 function = "gpio";
5786 drive 5699 drive-strength = <2>;
5787 bias- 5700 bias-pull-down;
5788 }; 5701 };
5789 5702
5790 clkreq-pins { 5703 clkreq-pins {
5791 pins 5704 pins = "gpio80";
5792 funct 5705 function = "pci_e0";
5793 drive 5706 drive-strength = <2>;
5794 bias- 5707 bias-pull-up;
5795 }; 5708 };
5796 5709
5797 wake-pins { 5710 wake-pins {
5798 pins 5711 pins = "gpio81";
5799 funct 5712 function = "gpio";
5800 drive 5713 drive-strength = <2>;
5801 bias- 5714 bias-pull-up;
5802 }; 5715 };
5803 }; 5716 };
5804 5717
5805 pcie1_default_state: 5718 pcie1_default_state: pcie1-default-state {
5806 perst-pins { 5719 perst-pins {
5807 pins 5720 pins = "gpio82";
5808 funct 5721 function = "gpio";
5809 drive 5722 drive-strength = <2>;
5810 bias- 5723 bias-pull-down;
5811 }; 5724 };
5812 5725
5813 clkreq-pins { 5726 clkreq-pins {
5814 pins 5727 pins = "gpio83";
5815 funct 5728 function = "pci_e1";
5816 drive 5729 drive-strength = <2>;
5817 bias- 5730 bias-pull-up;
5818 }; 5731 };
5819 5732
5820 wake-pins { 5733 wake-pins {
5821 pins 5734 pins = "gpio84";
5822 funct 5735 function = "gpio";
5823 drive 5736 drive-strength = <2>;
5824 bias- 5737 bias-pull-up;
5825 }; 5738 };
5826 }; 5739 };
5827 5740
5828 pcie2_default_state: 5741 pcie2_default_state: pcie2-default-state {
5829 perst-pins { 5742 perst-pins {
5830 pins 5743 pins = "gpio85";
5831 funct 5744 function = "gpio";
5832 drive 5745 drive-strength = <2>;
5833 bias- 5746 bias-pull-down;
5834 }; 5747 };
5835 5748
5836 clkreq-pins { 5749 clkreq-pins {
5837 pins 5750 pins = "gpio86";
5838 funct 5751 function = "pci_e2";
5839 drive 5752 drive-strength = <2>;
5840 bias- 5753 bias-pull-up;
5841 }; 5754 };
5842 5755
5843 wake-pins { 5756 wake-pins {
5844 pins 5757 pins = "gpio87";
5845 funct 5758 function = "gpio";
5846 drive 5759 drive-strength = <2>;
5847 bias- 5760 bias-pull-up;
5848 }; 5761 };
5849 }; 5762 };
5850 }; 5763 };
5851 5764
5852 apps_smmu: iommu@15000000 { 5765 apps_smmu: iommu@15000000 {
5853 compatible = "qcom,sm 5766 compatible = "qcom,sm8250-smmu-500", "qcom,smmu-500", "arm,mmu-500";
5854 reg = <0 0x15000000 0 5767 reg = <0 0x15000000 0 0x100000>;
5855 #iommu-cells = <2>; 5768 #iommu-cells = <2>;
5856 #global-interrupts = 5769 #global-interrupts = <2>;
5857 interrupts = <GIC_SPI 5770 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
5858 <GIC_SPI 5771 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
5859 <GIC_SPI 5772 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
5860 <GIC_SPI 5773 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
5861 <GIC_SPI 5774 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
5862 <GIC_SPI 5775 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
5863 <GIC_SPI 5776 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
5864 <GIC_SPI 5777 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
5865 <GIC_SPI 5778 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
5866 <GIC_SPI 5779 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
5867 <GIC_SPI 5780 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
5868 <GIC_SPI 5781 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
5869 <GIC_SPI 5782 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
5870 <GIC_SPI 5783 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
5871 <GIC_SPI 5784 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
5872 <GIC_SPI 5785 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
5873 <GIC_SPI 5786 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
5874 <GIC_SPI 5787 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
5875 <GIC_SPI 5788 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
5876 <GIC_SPI 5789 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
5877 <GIC_SPI 5790 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
5878 <GIC_SPI 5791 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
5879 <GIC_SPI 5792 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
5880 <GIC_SPI 5793 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
5881 <GIC_SPI 5794 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
5882 <GIC_SPI 5795 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
5883 <GIC_SPI 5796 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
5884 <GIC_SPI 5797 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
5885 <GIC_SPI 5798 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
5886 <GIC_SPI 5799 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
5887 <GIC_SPI 5800 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
5888 <GIC_SPI 5801 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
5889 <GIC_SPI 5802 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
5890 <GIC_SPI 5803 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
5891 <GIC_SPI 5804 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
5892 <GIC_SPI 5805 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
5893 <GIC_SPI 5806 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
5894 <GIC_SPI 5807 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
5895 <GIC_SPI 5808 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
5896 <GIC_SPI 5809 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
5897 <GIC_SPI 5810 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
5898 <GIC_SPI 5811 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
5899 <GIC_SPI 5812 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
5900 <GIC_SPI 5813 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
5901 <GIC_SPI 5814 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
5902 <GIC_SPI 5815 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
5903 <GIC_SPI 5816 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
5904 <GIC_SPI 5817 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
5905 <GIC_SPI 5818 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
5906 <GIC_SPI 5819 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
5907 <GIC_SPI 5820 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
5908 <GIC_SPI 5821 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
5909 <GIC_SPI 5822 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
5910 <GIC_SPI 5823 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
5911 <GIC_SPI 5824 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
5912 <GIC_SPI 5825 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
5913 <GIC_SPI 5826 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
5914 <GIC_SPI 5827 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
5915 <GIC_SPI 5828 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
5916 <GIC_SPI 5829 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
5917 <GIC_SPI 5830 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
5918 <GIC_SPI 5831 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
5919 <GIC_SPI 5832 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
5920 <GIC_SPI 5833 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
5921 <GIC_SPI 5834 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
5922 <GIC_SPI 5835 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
5923 <GIC_SPI 5836 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
5924 <GIC_SPI 5837 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
5925 <GIC_SPI 5838 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
5926 <GIC_SPI 5839 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
5927 <GIC_SPI 5840 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
5928 <GIC_SPI 5841 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
5929 <GIC_SPI 5842 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
5930 <GIC_SPI 5843 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
5931 <GIC_SPI 5844 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
5932 <GIC_SPI 5845 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
5933 <GIC_SPI 5846 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
5934 <GIC_SPI 5847 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
5935 <GIC_SPI 5848 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
5936 <GIC_SPI 5849 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
5937 <GIC_SPI 5850 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
5938 <GIC_SPI 5851 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
5939 <GIC_SPI 5852 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
5940 <GIC_SPI 5853 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
5941 <GIC_SPI 5854 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
5942 <GIC_SPI 5855 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
5943 <GIC_SPI 5856 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
5944 <GIC_SPI 5857 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
5945 <GIC_SPI 5858 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
5946 <GIC_SPI 5859 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
5947 <GIC_SPI 5860 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
5948 <GIC_SPI 5861 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
5949 <GIC_SPI 5862 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
5950 <GIC_SPI 5863 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
5951 <GIC_SPI 5864 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
5952 <GIC_SPI 5865 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
5953 <GIC_SPI 5866 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
5954 <GIC_SPI 5867 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>;
5955 dma-coherent; 5868 dma-coherent;
5956 }; 5869 };
5957 5870
5958 adsp: remoteproc@17300000 { 5871 adsp: remoteproc@17300000 {
5959 compatible = "qcom,sm 5872 compatible = "qcom,sm8250-adsp-pas";
5960 reg = <0 0x17300000 0 5873 reg = <0 0x17300000 0 0x100>;
5961 5874
5962 interrupts-extended = !! 5875 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
5963 5876 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
5964 5877 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
5965 5878 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
5966 5879 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
5967 interrupt-names = "wd 5880 interrupt-names = "wdog", "fatal", "ready",
5968 "ha 5881 "handover", "stop-ack";
5969 5882
5970 clocks = <&rpmhcc RPM 5883 clocks = <&rpmhcc RPMH_CXO_CLK>;
5971 clock-names = "xo"; 5884 clock-names = "xo";
5972 5885
5973 power-domains = <&rpm 5886 power-domains = <&rpmhpd RPMHPD_LCX>,
5974 <&rpm 5887 <&rpmhpd RPMHPD_LMX>;
5975 power-domain-names = 5888 power-domain-names = "lcx", "lmx";
5976 5889
5977 memory-region = <&ads 5890 memory-region = <&adsp_mem>;
5978 5891
5979 qcom,qmp = <&aoss_qmp 5892 qcom,qmp = <&aoss_qmp>;
5980 5893
5981 qcom,smem-states = <& 5894 qcom,smem-states = <&smp2p_adsp_out 0>;
5982 qcom,smem-state-names 5895 qcom,smem-state-names = "stop";
5983 5896
5984 status = "disabled"; 5897 status = "disabled";
5985 5898
5986 glink-edge { 5899 glink-edge {
5987 interrupts-ex 5900 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
5988 5901 IPCC_MPROC_SIGNAL_GLINK_QMP
5989 5902 IRQ_TYPE_EDGE_RISING>;
5990 mboxes = <&ip 5903 mboxes = <&ipcc IPCC_CLIENT_LPASS
5991 5904 IPCC_MPROC_SIGNAL_GLINK_QMP>;
5992 5905
5993 label = "lpas 5906 label = "lpass";
5994 qcom,remote-p 5907 qcom,remote-pid = <2>;
5995 5908
5996 apr { 5909 apr {
5997 compa 5910 compatible = "qcom,apr-v2";
5998 qcom, 5911 qcom,glink-channels = "apr_audio_svc";
5999 qcom, 5912 qcom,domain = <APR_DOMAIN_ADSP>;
6000 #addr 5913 #address-cells = <1>;
6001 #size 5914 #size-cells = <0>;
6002 5915
6003 servi 5916 service@3 {
6004 5917 reg = <APR_SVC_ADSP_CORE>;
6005 5918 compatible = "qcom,q6core";
6006 5919 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6007 }; 5920 };
6008 5921
6009 q6afe 5922 q6afe: service@4 {
6010 5923 compatible = "qcom,q6afe";
6011 5924 reg = <APR_SVC_AFE>;
6012 5925 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6013 5926 q6afedai: dais {
6014 5927 compatible = "qcom,q6afe-dais";
6015 5928 #address-cells = <1>;
6016 5929 #size-cells = <0>;
6017 5930 #sound-dai-cells = <1>;
6018 5931 };
6019 5932
6020 5933 q6afecc: clock-controller {
6021 5934 compatible = "qcom,q6afe-clocks";
6022 5935 #clock-cells = <2>;
6023 5936 };
6024 }; 5937 };
6025 5938
6026 q6asm 5939 q6asm: service@7 {
6027 5940 compatible = "qcom,q6asm";
6028 5941 reg = <APR_SVC_ASM>;
6029 5942 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6030 5943 q6asmdai: dais {
6031 5944 compatible = "qcom,q6asm-dais";
6032 5945 #address-cells = <1>;
6033 5946 #size-cells = <0>;
6034 5947 #sound-dai-cells = <1>;
6035 5948 iommus = <&apps_smmu 0x1801 0x0>;
6036 5949 };
6037 }; 5950 };
6038 5951
6039 q6adm 5952 q6adm: service@8 {
6040 5953 compatible = "qcom,q6adm";
6041 5954 reg = <APR_SVC_ADM>;
6042 5955 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6043 5956 q6routing: routing {
6044 5957 compatible = "qcom,q6adm-routing";
6045 5958 #sound-dai-cells = <0>;
6046 5959 };
6047 }; 5960 };
6048 }; 5961 };
6049 5962
6050 fastrpc { 5963 fastrpc {
6051 compa 5964 compatible = "qcom,fastrpc";
6052 qcom, 5965 qcom,glink-channels = "fastrpcglink-apps-dsp";
6053 label 5966 label = "adsp";
6054 qcom, 5967 qcom,non-secure-domain;
6055 #addr 5968 #address-cells = <1>;
6056 #size 5969 #size-cells = <0>;
6057 5970
6058 compu 5971 compute-cb@3 {
6059 5972 compatible = "qcom,fastrpc-compute-cb";
6060 5973 reg = <3>;
6061 5974 iommus = <&apps_smmu 0x1803 0x0>;
6062 }; 5975 };
6063 5976
6064 compu 5977 compute-cb@4 {
6065 5978 compatible = "qcom,fastrpc-compute-cb";
6066 5979 reg = <4>;
6067 5980 iommus = <&apps_smmu 0x1804 0x0>;
6068 }; 5981 };
6069 5982
6070 compu 5983 compute-cb@5 {
6071 5984 compatible = "qcom,fastrpc-compute-cb";
6072 5985 reg = <5>;
6073 5986 iommus = <&apps_smmu 0x1805 0x0>;
6074 }; 5987 };
6075 }; 5988 };
6076 }; 5989 };
6077 }; 5990 };
6078 5991
6079 intc: interrupt-controller@17 5992 intc: interrupt-controller@17a00000 {
6080 compatible = "arm,gic 5993 compatible = "arm,gic-v3";
6081 #interrupt-cells = <3 5994 #interrupt-cells = <3>;
6082 interrupt-controller; 5995 interrupt-controller;
6083 reg = <0x0 0x17a00000 5996 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
6084 <0x0 0x17a60000 5997 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
6085 interrupts = <GIC_PPI 5998 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
6086 }; 5999 };
6087 6000
6088 watchdog@17c10000 { 6001 watchdog@17c10000 {
6089 compatible = "qcom,ap 6002 compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt";
6090 reg = <0 0x17c10000 0 6003 reg = <0 0x17c10000 0 0x1000>;
6091 clocks = <&sleep_clk> 6004 clocks = <&sleep_clk>;
6092 interrupts = <GIC_SPI 6005 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
6093 }; 6006 };
6094 6007
6095 timer@17c20000 { 6008 timer@17c20000 {
6096 #address-cells = <1>; 6009 #address-cells = <1>;
6097 #size-cells = <1>; 6010 #size-cells = <1>;
6098 ranges = <0 0 0 0x200 6011 ranges = <0 0 0 0x20000000>;
6099 compatible = "arm,arm 6012 compatible = "arm,armv7-timer-mem";
6100 reg = <0x0 0x17c20000 6013 reg = <0x0 0x17c20000 0x0 0x1000>;
6101 clock-frequency = <19 6014 clock-frequency = <19200000>;
6102 6015
6103 frame@17c21000 { 6016 frame@17c21000 {
6104 frame-number 6017 frame-number = <0>;
6105 interrupts = 6018 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
6106 6019 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
6107 reg = <0x17c2 6020 reg = <0x17c21000 0x1000>,
6108 <0x17c2 6021 <0x17c22000 0x1000>;
6109 }; 6022 };
6110 6023
6111 frame@17c23000 { 6024 frame@17c23000 {
6112 frame-number 6025 frame-number = <1>;
6113 interrupts = 6026 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
6114 reg = <0x17c2 6027 reg = <0x17c23000 0x1000>;
6115 status = "dis 6028 status = "disabled";
6116 }; 6029 };
6117 6030
6118 frame@17c25000 { 6031 frame@17c25000 {
6119 frame-number 6032 frame-number = <2>;
6120 interrupts = 6033 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
6121 reg = <0x17c2 6034 reg = <0x17c25000 0x1000>;
6122 status = "dis 6035 status = "disabled";
6123 }; 6036 };
6124 6037
6125 frame@17c27000 { 6038 frame@17c27000 {
6126 frame-number 6039 frame-number = <3>;
6127 interrupts = 6040 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
6128 reg = <0x17c2 6041 reg = <0x17c27000 0x1000>;
6129 status = "dis 6042 status = "disabled";
6130 }; 6043 };
6131 6044
6132 frame@17c29000 { 6045 frame@17c29000 {
6133 frame-number 6046 frame-number = <4>;
6134 interrupts = 6047 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
6135 reg = <0x17c2 6048 reg = <0x17c29000 0x1000>;
6136 status = "dis 6049 status = "disabled";
6137 }; 6050 };
6138 6051
6139 frame@17c2b000 { 6052 frame@17c2b000 {
6140 frame-number 6053 frame-number = <5>;
6141 interrupts = 6054 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
6142 reg = <0x17c2 6055 reg = <0x17c2b000 0x1000>;
6143 status = "dis 6056 status = "disabled";
6144 }; 6057 };
6145 6058
6146 frame@17c2d000 { 6059 frame@17c2d000 {
6147 frame-number 6060 frame-number = <6>;
6148 interrupts = 6061 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
6149 reg = <0x17c2 6062 reg = <0x17c2d000 0x1000>;
6150 status = "dis 6063 status = "disabled";
6151 }; 6064 };
6152 }; 6065 };
6153 6066
6154 apps_rsc: rsc@18200000 { 6067 apps_rsc: rsc@18200000 {
6155 label = "apps_rsc"; 6068 label = "apps_rsc";
6156 compatible = "qcom,rp 6069 compatible = "qcom,rpmh-rsc";
6157 reg = <0x0 0x18200000 6070 reg = <0x0 0x18200000 0x0 0x10000>,
6158 <0x0 0x182100 6071 <0x0 0x18210000 0x0 0x10000>,
6159 <0x0 0x182200 6072 <0x0 0x18220000 0x0 0x10000>;
6160 reg-names = "drv-0", 6073 reg-names = "drv-0", "drv-1", "drv-2";
6161 interrupts = <GIC_SPI 6074 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
6162 <GIC_SPI 6075 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
6163 <GIC_SPI 6076 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
6164 qcom,tcs-offset = <0x 6077 qcom,tcs-offset = <0xd00>;
6165 qcom,drv-id = <2>; 6078 qcom,drv-id = <2>;
6166 qcom,tcs-config = <AC 6079 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
6167 <WA 6080 <WAKE_TCS 3>, <CONTROL_TCS 1>;
6168 power-domains = <&CLU 6081 power-domains = <&CLUSTER_PD>;
6169 6082
6170 rpmhcc: clock-control 6083 rpmhcc: clock-controller {
6171 compatible = 6084 compatible = "qcom,sm8250-rpmh-clk";
6172 #clock-cells 6085 #clock-cells = <1>;
6173 clock-names = 6086 clock-names = "xo";
6174 clocks = <&xo 6087 clocks = <&xo_board>;
6175 }; 6088 };
6176 6089
6177 rpmhpd: power-control 6090 rpmhpd: power-controller {
6178 compatible = 6091 compatible = "qcom,sm8250-rpmhpd";
6179 #power-domain 6092 #power-domain-cells = <1>;
6180 operating-poi 6093 operating-points-v2 = <&rpmhpd_opp_table>;
6181 6094
6182 rpmhpd_opp_ta 6095 rpmhpd_opp_table: opp-table {
6183 compa 6096 compatible = "operating-points-v2";
6184 6097
6185 rpmhp 6098 rpmhpd_opp_ret: opp1 {
6186 6099 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
6187 }; 6100 };
6188 6101
6189 rpmhp 6102 rpmhpd_opp_min_svs: opp2 {
6190 6103 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
6191 }; 6104 };
6192 6105
6193 rpmhp 6106 rpmhpd_opp_low_svs: opp3 {
6194 6107 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
6195 }; 6108 };
6196 6109
6197 rpmhp 6110 rpmhpd_opp_svs: opp4 {
6198 6111 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
6199 }; 6112 };
6200 6113
6201 rpmhp 6114 rpmhpd_opp_svs_l1: opp5 {
6202 6115 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
6203 }; 6116 };
6204 6117
6205 rpmhp 6118 rpmhpd_opp_nom: opp6 {
6206 6119 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
6207 }; 6120 };
6208 6121
6209 rpmhp 6122 rpmhpd_opp_nom_l1: opp7 {
6210 6123 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
6211 }; 6124 };
6212 6125
6213 rpmhp 6126 rpmhpd_opp_nom_l2: opp8 {
6214 6127 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
6215 }; 6128 };
6216 6129
6217 rpmhp 6130 rpmhpd_opp_turbo: opp9 {
6218 6131 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
6219 }; 6132 };
6220 6133
6221 rpmhp 6134 rpmhpd_opp_turbo_l1: opp10 {
6222 6135 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
6223 }; 6136 };
6224 }; 6137 };
6225 }; 6138 };
6226 6139
6227 apps_bcm_voter: bcm-v 6140 apps_bcm_voter: bcm-voter {
6228 compatible = 6141 compatible = "qcom,bcm-voter";
6229 }; 6142 };
6230 }; 6143 };
6231 6144
6232 epss_l3: interconnect@1859000 6145 epss_l3: interconnect@18590000 {
6233 compatible = "qcom,sm 6146 compatible = "qcom,sm8250-epss-l3", "qcom,epss-l3";
6234 reg = <0 0x18590000 0 6147 reg = <0 0x18590000 0 0x1000>;
6235 6148
6236 clocks = <&rpmhcc RPM 6149 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
6237 clock-names = "xo", " 6150 clock-names = "xo", "alternate";
6238 6151
6239 #interconnect-cells = 6152 #interconnect-cells = <1>;
6240 }; 6153 };
6241 6154
6242 cpufreq_hw: cpufreq@18591000 6155 cpufreq_hw: cpufreq@18591000 {
6243 compatible = "qcom,sm 6156 compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss";
6244 reg = <0 0x18591000 0 6157 reg = <0 0x18591000 0 0x1000>,
6245 <0 0x18592000 0 6158 <0 0x18592000 0 0x1000>,
6246 <0 0x18593000 0 6159 <0 0x18593000 0 0x1000>;
6247 reg-names = "freq-dom 6160 reg-names = "freq-domain0", "freq-domain1",
6248 "freq-dom 6161 "freq-domain2";
6249 6162
6250 clocks = <&rpmhcc RPM 6163 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
6251 clock-names = "xo", " 6164 clock-names = "xo", "alternate";
6252 interrupts = <GIC_SPI 6165 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
6253 <GIC_SPI 6166 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
6254 <GIC_SPI 6167 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
6255 interrupt-names = "dc 6168 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
6256 #freq-domain-cells = 6169 #freq-domain-cells = <1>;
6257 #clock-cells = <1>; 6170 #clock-cells = <1>;
6258 }; 6171 };
6259 }; 6172 };
6260 6173
6261 sound: sound { 6174 sound: sound {
6262 }; 6175 };
6263 6176
6264 timer { 6177 timer {
6265 compatible = "arm,armv8-timer 6178 compatible = "arm,armv8-timer";
6266 interrupts = <GIC_PPI 13 6179 interrupts = <GIC_PPI 13
6267 (GIC_CPU_MASK 6180 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6268 <GIC_PPI 14 6181 <GIC_PPI 14
6269 (GIC_CPU_MASK 6182 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6270 <GIC_PPI 11 6183 <GIC_PPI 11
6271 (GIC_CPU_MASK 6184 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6272 <GIC_PPI 10 6185 <GIC_PPI 10
6273 (GIC_CPU_MASK 6186 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
6274 }; 6187 };
6275 6188
6276 thermal-zones { 6189 thermal-zones {
6277 cpu0-thermal { 6190 cpu0-thermal {
6278 polling-delay-passive 6191 polling-delay-passive = <250>;
>> 6192 polling-delay = <1000>;
6279 6193
6280 thermal-sensors = <&t 6194 thermal-sensors = <&tsens0 1>;
6281 6195
6282 trips { 6196 trips {
6283 cpu0_alert0: 6197 cpu0_alert0: trip-point0 {
6284 tempe 6198 temperature = <90000>;
6285 hyste 6199 hysteresis = <2000>;
6286 type 6200 type = "passive";
6287 }; 6201 };
6288 6202
6289 cpu0_alert1: 6203 cpu0_alert1: trip-point1 {
6290 tempe 6204 temperature = <95000>;
6291 hyste 6205 hysteresis = <2000>;
6292 type 6206 type = "passive";
6293 }; 6207 };
6294 6208
6295 cpu0_crit: cp 6209 cpu0_crit: cpu-crit {
6296 tempe 6210 temperature = <110000>;
6297 hyste 6211 hysteresis = <1000>;
6298 type 6212 type = "critical";
6299 }; 6213 };
6300 }; 6214 };
6301 6215
6302 cooling-maps { 6216 cooling-maps {
6303 map0 { 6217 map0 {
6304 trip 6218 trip = <&cpu0_alert0>;
6305 cooli 6219 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6306 6220 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6307 6221 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6308 6222 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6309 }; 6223 };
6310 map1 { 6224 map1 {
6311 trip 6225 trip = <&cpu0_alert1>;
6312 cooli 6226 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6313 6227 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6314 6228 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6315 6229 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6316 }; 6230 };
6317 }; 6231 };
6318 }; 6232 };
6319 6233
6320 cpu1-thermal { 6234 cpu1-thermal {
6321 polling-delay-passive 6235 polling-delay-passive = <250>;
>> 6236 polling-delay = <1000>;
6322 6237
6323 thermal-sensors = <&t 6238 thermal-sensors = <&tsens0 2>;
6324 6239
6325 trips { 6240 trips {
6326 cpu1_alert0: 6241 cpu1_alert0: trip-point0 {
6327 tempe 6242 temperature = <90000>;
6328 hyste 6243 hysteresis = <2000>;
6329 type 6244 type = "passive";
6330 }; 6245 };
6331 6246
6332 cpu1_alert1: 6247 cpu1_alert1: trip-point1 {
6333 tempe 6248 temperature = <95000>;
6334 hyste 6249 hysteresis = <2000>;
6335 type 6250 type = "passive";
6336 }; 6251 };
6337 6252
6338 cpu1_crit: cp 6253 cpu1_crit: cpu-crit {
6339 tempe 6254 temperature = <110000>;
6340 hyste 6255 hysteresis = <1000>;
6341 type 6256 type = "critical";
6342 }; 6257 };
6343 }; 6258 };
6344 6259
6345 cooling-maps { 6260 cooling-maps {
6346 map0 { 6261 map0 {
6347 trip 6262 trip = <&cpu1_alert0>;
6348 cooli 6263 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6349 6264 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6350 6265 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6351 6266 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6352 }; 6267 };
6353 map1 { 6268 map1 {
6354 trip 6269 trip = <&cpu1_alert1>;
6355 cooli 6270 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6356 6271 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6357 6272 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6358 6273 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6359 }; 6274 };
6360 }; 6275 };
6361 }; 6276 };
6362 6277
6363 cpu2-thermal { 6278 cpu2-thermal {
6364 polling-delay-passive 6279 polling-delay-passive = <250>;
>> 6280 polling-delay = <1000>;
6365 6281
6366 thermal-sensors = <&t 6282 thermal-sensors = <&tsens0 3>;
6367 6283
6368 trips { 6284 trips {
6369 cpu2_alert0: 6285 cpu2_alert0: trip-point0 {
6370 tempe 6286 temperature = <90000>;
6371 hyste 6287 hysteresis = <2000>;
6372 type 6288 type = "passive";
6373 }; 6289 };
6374 6290
6375 cpu2_alert1: 6291 cpu2_alert1: trip-point1 {
6376 tempe 6292 temperature = <95000>;
6377 hyste 6293 hysteresis = <2000>;
6378 type 6294 type = "passive";
6379 }; 6295 };
6380 6296
6381 cpu2_crit: cp 6297 cpu2_crit: cpu-crit {
6382 tempe 6298 temperature = <110000>;
6383 hyste 6299 hysteresis = <1000>;
6384 type 6300 type = "critical";
6385 }; 6301 };
6386 }; 6302 };
6387 6303
6388 cooling-maps { 6304 cooling-maps {
6389 map0 { 6305 map0 {
6390 trip 6306 trip = <&cpu2_alert0>;
6391 cooli 6307 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6392 6308 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6393 6309 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6394 6310 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6395 }; 6311 };
6396 map1 { 6312 map1 {
6397 trip 6313 trip = <&cpu2_alert1>;
6398 cooli 6314 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6399 6315 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6400 6316 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6401 6317 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6402 }; 6318 };
6403 }; 6319 };
6404 }; 6320 };
6405 6321
6406 cpu3-thermal { 6322 cpu3-thermal {
6407 polling-delay-passive 6323 polling-delay-passive = <250>;
>> 6324 polling-delay = <1000>;
6408 6325
6409 thermal-sensors = <&t 6326 thermal-sensors = <&tsens0 4>;
6410 6327
6411 trips { 6328 trips {
6412 cpu3_alert0: 6329 cpu3_alert0: trip-point0 {
6413 tempe 6330 temperature = <90000>;
6414 hyste 6331 hysteresis = <2000>;
6415 type 6332 type = "passive";
6416 }; 6333 };
6417 6334
6418 cpu3_alert1: 6335 cpu3_alert1: trip-point1 {
6419 tempe 6336 temperature = <95000>;
6420 hyste 6337 hysteresis = <2000>;
6421 type 6338 type = "passive";
6422 }; 6339 };
6423 6340
6424 cpu3_crit: cp 6341 cpu3_crit: cpu-crit {
6425 tempe 6342 temperature = <110000>;
6426 hyste 6343 hysteresis = <1000>;
6427 type 6344 type = "critical";
6428 }; 6345 };
6429 }; 6346 };
6430 6347
6431 cooling-maps { 6348 cooling-maps {
6432 map0 { 6349 map0 {
6433 trip 6350 trip = <&cpu3_alert0>;
6434 cooli 6351 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6435 6352 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6436 6353 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6437 6354 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6438 }; 6355 };
6439 map1 { 6356 map1 {
6440 trip 6357 trip = <&cpu3_alert1>;
6441 cooli 6358 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6442 6359 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6443 6360 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6444 6361 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6445 }; 6362 };
6446 }; 6363 };
6447 }; 6364 };
6448 6365
6449 cpu4-top-thermal { 6366 cpu4-top-thermal {
6450 polling-delay-passive 6367 polling-delay-passive = <250>;
>> 6368 polling-delay = <1000>;
6451 6369
6452 thermal-sensors = <&t 6370 thermal-sensors = <&tsens0 7>;
6453 6371
6454 trips { 6372 trips {
6455 cpu4_top_aler 6373 cpu4_top_alert0: trip-point0 {
6456 tempe 6374 temperature = <90000>;
6457 hyste 6375 hysteresis = <2000>;
6458 type 6376 type = "passive";
6459 }; 6377 };
6460 6378
6461 cpu4_top_aler 6379 cpu4_top_alert1: trip-point1 {
6462 tempe 6380 temperature = <95000>;
6463 hyste 6381 hysteresis = <2000>;
6464 type 6382 type = "passive";
6465 }; 6383 };
6466 6384
6467 cpu4_top_crit 6385 cpu4_top_crit: cpu-crit {
6468 tempe 6386 temperature = <110000>;
6469 hyste 6387 hysteresis = <1000>;
6470 type 6388 type = "critical";
6471 }; 6389 };
6472 }; 6390 };
6473 6391
6474 cooling-maps { 6392 cooling-maps {
6475 map0 { 6393 map0 {
6476 trip 6394 trip = <&cpu4_top_alert0>;
6477 cooli 6395 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6478 6396 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6479 6397 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6480 6398 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6481 }; 6399 };
6482 map1 { 6400 map1 {
6483 trip 6401 trip = <&cpu4_top_alert1>;
6484 cooli 6402 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6485 6403 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6486 6404 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6487 6405 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6488 }; 6406 };
6489 }; 6407 };
6490 }; 6408 };
6491 6409
6492 cpu5-top-thermal { 6410 cpu5-top-thermal {
6493 polling-delay-passive 6411 polling-delay-passive = <250>;
>> 6412 polling-delay = <1000>;
6494 6413
6495 thermal-sensors = <&t 6414 thermal-sensors = <&tsens0 8>;
6496 6415
6497 trips { 6416 trips {
6498 cpu5_top_aler 6417 cpu5_top_alert0: trip-point0 {
6499 tempe 6418 temperature = <90000>;
6500 hyste 6419 hysteresis = <2000>;
6501 type 6420 type = "passive";
6502 }; 6421 };
6503 6422
6504 cpu5_top_aler 6423 cpu5_top_alert1: trip-point1 {
6505 tempe 6424 temperature = <95000>;
6506 hyste 6425 hysteresis = <2000>;
6507 type 6426 type = "passive";
6508 }; 6427 };
6509 6428
6510 cpu5_top_crit 6429 cpu5_top_crit: cpu-crit {
6511 tempe 6430 temperature = <110000>;
6512 hyste 6431 hysteresis = <1000>;
6513 type 6432 type = "critical";
6514 }; 6433 };
6515 }; 6434 };
6516 6435
6517 cooling-maps { 6436 cooling-maps {
6518 map0 { 6437 map0 {
6519 trip 6438 trip = <&cpu5_top_alert0>;
6520 cooli 6439 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6521 6440 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6522 6441 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6523 6442 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6524 }; 6443 };
6525 map1 { 6444 map1 {
6526 trip 6445 trip = <&cpu5_top_alert1>;
6527 cooli 6446 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6528 6447 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6529 6448 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6530 6449 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6531 }; 6450 };
6532 }; 6451 };
6533 }; 6452 };
6534 6453
6535 cpu6-top-thermal { 6454 cpu6-top-thermal {
6536 polling-delay-passive 6455 polling-delay-passive = <250>;
>> 6456 polling-delay = <1000>;
6537 6457
6538 thermal-sensors = <&t 6458 thermal-sensors = <&tsens0 9>;
6539 6459
6540 trips { 6460 trips {
6541 cpu6_top_aler 6461 cpu6_top_alert0: trip-point0 {
6542 tempe 6462 temperature = <90000>;
6543 hyste 6463 hysteresis = <2000>;
6544 type 6464 type = "passive";
6545 }; 6465 };
6546 6466
6547 cpu6_top_aler 6467 cpu6_top_alert1: trip-point1 {
6548 tempe 6468 temperature = <95000>;
6549 hyste 6469 hysteresis = <2000>;
6550 type 6470 type = "passive";
6551 }; 6471 };
6552 6472
6553 cpu6_top_crit 6473 cpu6_top_crit: cpu-crit {
6554 tempe 6474 temperature = <110000>;
6555 hyste 6475 hysteresis = <1000>;
6556 type 6476 type = "critical";
6557 }; 6477 };
6558 }; 6478 };
6559 6479
6560 cooling-maps { 6480 cooling-maps {
6561 map0 { 6481 map0 {
6562 trip 6482 trip = <&cpu6_top_alert0>;
6563 cooli 6483 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6564 6484 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6565 6485 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6566 6486 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6567 }; 6487 };
6568 map1 { 6488 map1 {
6569 trip 6489 trip = <&cpu6_top_alert1>;
6570 cooli 6490 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6571 6491 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6572 6492 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6573 6493 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6574 }; 6494 };
6575 }; 6495 };
6576 }; 6496 };
6577 6497
6578 cpu7-top-thermal { 6498 cpu7-top-thermal {
6579 polling-delay-passive 6499 polling-delay-passive = <250>;
>> 6500 polling-delay = <1000>;
6580 6501
6581 thermal-sensors = <&t 6502 thermal-sensors = <&tsens0 10>;
6582 6503
6583 trips { 6504 trips {
6584 cpu7_top_aler 6505 cpu7_top_alert0: trip-point0 {
6585 tempe 6506 temperature = <90000>;
6586 hyste 6507 hysteresis = <2000>;
6587 type 6508 type = "passive";
6588 }; 6509 };
6589 6510
6590 cpu7_top_aler 6511 cpu7_top_alert1: trip-point1 {
6591 tempe 6512 temperature = <95000>;
6592 hyste 6513 hysteresis = <2000>;
6593 type 6514 type = "passive";
6594 }; 6515 };
6595 6516
6596 cpu7_top_crit 6517 cpu7_top_crit: cpu-crit {
6597 tempe 6518 temperature = <110000>;
6598 hyste 6519 hysteresis = <1000>;
6599 type 6520 type = "critical";
6600 }; 6521 };
6601 }; 6522 };
6602 6523
6603 cooling-maps { 6524 cooling-maps {
6604 map0 { 6525 map0 {
6605 trip 6526 trip = <&cpu7_top_alert0>;
6606 cooli 6527 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6607 6528 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6608 6529 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6609 6530 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6610 }; 6531 };
6611 map1 { 6532 map1 {
6612 trip 6533 trip = <&cpu7_top_alert1>;
6613 cooli 6534 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6614 6535 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6615 6536 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6616 6537 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6617 }; 6538 };
6618 }; 6539 };
6619 }; 6540 };
6620 6541
6621 cpu4-bottom-thermal { 6542 cpu4-bottom-thermal {
6622 polling-delay-passive 6543 polling-delay-passive = <250>;
>> 6544 polling-delay = <1000>;
6623 6545
6624 thermal-sensors = <&t 6546 thermal-sensors = <&tsens0 11>;
6625 6547
6626 trips { 6548 trips {
6627 cpu4_bottom_a 6549 cpu4_bottom_alert0: trip-point0 {
6628 tempe 6550 temperature = <90000>;
6629 hyste 6551 hysteresis = <2000>;
6630 type 6552 type = "passive";
6631 }; 6553 };
6632 6554
6633 cpu4_bottom_a 6555 cpu4_bottom_alert1: trip-point1 {
6634 tempe 6556 temperature = <95000>;
6635 hyste 6557 hysteresis = <2000>;
6636 type 6558 type = "passive";
6637 }; 6559 };
6638 6560
6639 cpu4_bottom_c 6561 cpu4_bottom_crit: cpu-crit {
6640 tempe 6562 temperature = <110000>;
6641 hyste 6563 hysteresis = <1000>;
6642 type 6564 type = "critical";
6643 }; 6565 };
6644 }; 6566 };
6645 6567
6646 cooling-maps { 6568 cooling-maps {
6647 map0 { 6569 map0 {
6648 trip 6570 trip = <&cpu4_bottom_alert0>;
6649 cooli 6571 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6650 6572 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6651 6573 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6652 6574 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6653 }; 6575 };
6654 map1 { 6576 map1 {
6655 trip 6577 trip = <&cpu4_bottom_alert1>;
6656 cooli 6578 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6657 6579 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6658 6580 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6659 6581 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6660 }; 6582 };
6661 }; 6583 };
6662 }; 6584 };
6663 6585
6664 cpu5-bottom-thermal { 6586 cpu5-bottom-thermal {
6665 polling-delay-passive 6587 polling-delay-passive = <250>;
>> 6588 polling-delay = <1000>;
6666 6589
6667 thermal-sensors = <&t 6590 thermal-sensors = <&tsens0 12>;
6668 6591
6669 trips { 6592 trips {
6670 cpu5_bottom_a 6593 cpu5_bottom_alert0: trip-point0 {
6671 tempe 6594 temperature = <90000>;
6672 hyste 6595 hysteresis = <2000>;
6673 type 6596 type = "passive";
6674 }; 6597 };
6675 6598
6676 cpu5_bottom_a 6599 cpu5_bottom_alert1: trip-point1 {
6677 tempe 6600 temperature = <95000>;
6678 hyste 6601 hysteresis = <2000>;
6679 type 6602 type = "passive";
6680 }; 6603 };
6681 6604
6682 cpu5_bottom_c 6605 cpu5_bottom_crit: cpu-crit {
6683 tempe 6606 temperature = <110000>;
6684 hyste 6607 hysteresis = <1000>;
6685 type 6608 type = "critical";
6686 }; 6609 };
6687 }; 6610 };
6688 6611
6689 cooling-maps { 6612 cooling-maps {
6690 map0 { 6613 map0 {
6691 trip 6614 trip = <&cpu5_bottom_alert0>;
6692 cooli 6615 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6693 6616 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6694 6617 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6695 6618 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6696 }; 6619 };
6697 map1 { 6620 map1 {
6698 trip 6621 trip = <&cpu5_bottom_alert1>;
6699 cooli 6622 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6700 6623 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6701 6624 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6702 6625 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6703 }; 6626 };
6704 }; 6627 };
6705 }; 6628 };
6706 6629
6707 cpu6-bottom-thermal { 6630 cpu6-bottom-thermal {
6708 polling-delay-passive 6631 polling-delay-passive = <250>;
>> 6632 polling-delay = <1000>;
6709 6633
6710 thermal-sensors = <&t 6634 thermal-sensors = <&tsens0 13>;
6711 6635
6712 trips { 6636 trips {
6713 cpu6_bottom_a 6637 cpu6_bottom_alert0: trip-point0 {
6714 tempe 6638 temperature = <90000>;
6715 hyste 6639 hysteresis = <2000>;
6716 type 6640 type = "passive";
6717 }; 6641 };
6718 6642
6719 cpu6_bottom_a 6643 cpu6_bottom_alert1: trip-point1 {
6720 tempe 6644 temperature = <95000>;
6721 hyste 6645 hysteresis = <2000>;
6722 type 6646 type = "passive";
6723 }; 6647 };
6724 6648
6725 cpu6_bottom_c 6649 cpu6_bottom_crit: cpu-crit {
6726 tempe 6650 temperature = <110000>;
6727 hyste 6651 hysteresis = <1000>;
6728 type 6652 type = "critical";
6729 }; 6653 };
6730 }; 6654 };
6731 6655
6732 cooling-maps { 6656 cooling-maps {
6733 map0 { 6657 map0 {
6734 trip 6658 trip = <&cpu6_bottom_alert0>;
6735 cooli 6659 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6736 6660 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6737 6661 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6738 6662 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6739 }; 6663 };
6740 map1 { 6664 map1 {
6741 trip 6665 trip = <&cpu6_bottom_alert1>;
6742 cooli 6666 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6743 6667 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6744 6668 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6745 6669 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6746 }; 6670 };
6747 }; 6671 };
6748 }; 6672 };
6749 6673
6750 cpu7-bottom-thermal { 6674 cpu7-bottom-thermal {
6751 polling-delay-passive 6675 polling-delay-passive = <250>;
>> 6676 polling-delay = <1000>;
6752 6677
6753 thermal-sensors = <&t 6678 thermal-sensors = <&tsens0 14>;
6754 6679
6755 trips { 6680 trips {
6756 cpu7_bottom_a 6681 cpu7_bottom_alert0: trip-point0 {
6757 tempe 6682 temperature = <90000>;
6758 hyste 6683 hysteresis = <2000>;
6759 type 6684 type = "passive";
6760 }; 6685 };
6761 6686
6762 cpu7_bottom_a 6687 cpu7_bottom_alert1: trip-point1 {
6763 tempe 6688 temperature = <95000>;
6764 hyste 6689 hysteresis = <2000>;
6765 type 6690 type = "passive";
6766 }; 6691 };
6767 6692
6768 cpu7_bottom_c 6693 cpu7_bottom_crit: cpu-crit {
6769 tempe 6694 temperature = <110000>;
6770 hyste 6695 hysteresis = <1000>;
6771 type 6696 type = "critical";
6772 }; 6697 };
6773 }; 6698 };
6774 6699
6775 cooling-maps { 6700 cooling-maps {
6776 map0 { 6701 map0 {
6777 trip 6702 trip = <&cpu7_bottom_alert0>;
6778 cooli 6703 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6779 6704 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6780 6705 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6781 6706 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6782 }; 6707 };
6783 map1 { 6708 map1 {
6784 trip 6709 trip = <&cpu7_bottom_alert1>;
6785 cooli 6710 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6786 6711 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6787 6712 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6788 6713 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6789 }; 6714 };
6790 }; 6715 };
6791 }; 6716 };
6792 6717
6793 aoss0-thermal { 6718 aoss0-thermal {
6794 polling-delay-passive 6719 polling-delay-passive = <250>;
>> 6720 polling-delay = <1000>;
6795 6721
6796 thermal-sensors = <&t 6722 thermal-sensors = <&tsens0 0>;
6797 6723
6798 trips { 6724 trips {
6799 aoss0_alert0: 6725 aoss0_alert0: trip-point0 {
6800 tempe 6726 temperature = <90000>;
6801 hyste 6727 hysteresis = <2000>;
6802 type 6728 type = "hot";
6803 }; 6729 };
6804 }; 6730 };
6805 }; 6731 };
6806 6732
6807 cluster0-thermal { 6733 cluster0-thermal {
6808 polling-delay-passive 6734 polling-delay-passive = <250>;
>> 6735 polling-delay = <1000>;
6809 6736
6810 thermal-sensors = <&t 6737 thermal-sensors = <&tsens0 5>;
6811 6738
6812 trips { 6739 trips {
6813 cluster0_aler 6740 cluster0_alert0: trip-point0 {
6814 tempe 6741 temperature = <90000>;
6815 hyste 6742 hysteresis = <2000>;
6816 type 6743 type = "hot";
6817 }; 6744 };
6818 cluster0_crit !! 6745 cluster0_crit: cluster0_crit {
6819 tempe 6746 temperature = <110000>;
6820 hyste 6747 hysteresis = <2000>;
6821 type 6748 type = "critical";
6822 }; 6749 };
6823 }; 6750 };
6824 }; 6751 };
6825 6752
6826 cluster1-thermal { 6753 cluster1-thermal {
6827 polling-delay-passive 6754 polling-delay-passive = <250>;
>> 6755 polling-delay = <1000>;
6828 6756
6829 thermal-sensors = <&t 6757 thermal-sensors = <&tsens0 6>;
6830 6758
6831 trips { 6759 trips {
6832 cluster1_aler 6760 cluster1_alert0: trip-point0 {
6833 tempe 6761 temperature = <90000>;
6834 hyste 6762 hysteresis = <2000>;
6835 type 6763 type = "hot";
6836 }; 6764 };
6837 cluster1_crit !! 6765 cluster1_crit: cluster1_crit {
6838 tempe 6766 temperature = <110000>;
6839 hyste 6767 hysteresis = <2000>;
6840 type 6768 type = "critical";
6841 }; 6769 };
6842 }; 6770 };
6843 }; 6771 };
6844 6772
6845 gpu-top-thermal { 6773 gpu-top-thermal {
6846 polling-delay-passive 6774 polling-delay-passive = <250>;
>> 6775 polling-delay = <1000>;
6847 6776
6848 thermal-sensors = <&t 6777 thermal-sensors = <&tsens0 15>;
6849 6778
6850 cooling-maps { <<
6851 map0 { <<
6852 trip <<
6853 cooli <<
6854 }; <<
6855 }; <<
6856 <<
6857 trips { 6779 trips {
6858 gpu_top_alert !! 6780 gpu1_alert0: trip-point0 {
6859 tempe <<
6860 hyste <<
6861 type <<
6862 }; <<
6863 <<
6864 trip-point1 { <<
6865 tempe 6781 temperature = <90000>;
6866 hyste !! 6782 hysteresis = <2000>;
6867 type 6783 type = "hot";
6868 }; 6784 };
6869 <<
6870 trip-point2 { <<
6871 tempe <<
6872 hyste <<
6873 type <<
6874 }; <<
6875 }; 6785 };
6876 }; 6786 };
6877 6787
6878 aoss1-thermal { 6788 aoss1-thermal {
6879 polling-delay-passive 6789 polling-delay-passive = <250>;
>> 6790 polling-delay = <1000>;
6880 6791
6881 thermal-sensors = <&t 6792 thermal-sensors = <&tsens1 0>;
6882 6793
6883 trips { 6794 trips {
6884 aoss1_alert0: 6795 aoss1_alert0: trip-point0 {
6885 tempe 6796 temperature = <90000>;
6886 hyste 6797 hysteresis = <2000>;
6887 type 6798 type = "hot";
6888 }; 6799 };
6889 }; 6800 };
6890 }; 6801 };
6891 6802
6892 wlan-thermal { 6803 wlan-thermal {
6893 polling-delay-passive 6804 polling-delay-passive = <250>;
>> 6805 polling-delay = <1000>;
6894 6806
6895 thermal-sensors = <&t 6807 thermal-sensors = <&tsens1 1>;
6896 6808
6897 trips { 6809 trips {
6898 wlan_alert0: 6810 wlan_alert0: trip-point0 {
6899 tempe 6811 temperature = <90000>;
6900 hyste 6812 hysteresis = <2000>;
6901 type 6813 type = "hot";
6902 }; 6814 };
6903 }; 6815 };
6904 }; 6816 };
6905 6817
6906 video-thermal { 6818 video-thermal {
6907 polling-delay-passive 6819 polling-delay-passive = <250>;
>> 6820 polling-delay = <1000>;
6908 6821
6909 thermal-sensors = <&t 6822 thermal-sensors = <&tsens1 2>;
6910 6823
6911 trips { 6824 trips {
6912 video_alert0: 6825 video_alert0: trip-point0 {
6913 tempe 6826 temperature = <90000>;
6914 hyste 6827 hysteresis = <2000>;
6915 type 6828 type = "hot";
6916 }; 6829 };
6917 }; 6830 };
6918 }; 6831 };
6919 6832
6920 mem-thermal { 6833 mem-thermal {
6921 polling-delay-passive 6834 polling-delay-passive = <250>;
>> 6835 polling-delay = <1000>;
6922 6836
6923 thermal-sensors = <&t 6837 thermal-sensors = <&tsens1 3>;
6924 6838
6925 trips { 6839 trips {
6926 mem_alert0: t 6840 mem_alert0: trip-point0 {
6927 tempe 6841 temperature = <90000>;
6928 hyste 6842 hysteresis = <2000>;
6929 type 6843 type = "hot";
6930 }; 6844 };
6931 }; 6845 };
6932 }; 6846 };
6933 6847
6934 q6-hvx-thermal { 6848 q6-hvx-thermal {
6935 polling-delay-passive 6849 polling-delay-passive = <250>;
>> 6850 polling-delay = <1000>;
6936 6851
6937 thermal-sensors = <&t 6852 thermal-sensors = <&tsens1 4>;
6938 6853
6939 trips { 6854 trips {
6940 q6_hvx_alert0 6855 q6_hvx_alert0: trip-point0 {
6941 tempe 6856 temperature = <90000>;
6942 hyste 6857 hysteresis = <2000>;
6943 type 6858 type = "hot";
6944 }; 6859 };
6945 }; 6860 };
6946 }; 6861 };
6947 6862
6948 camera-thermal { 6863 camera-thermal {
6949 polling-delay-passive 6864 polling-delay-passive = <250>;
>> 6865 polling-delay = <1000>;
6950 6866
6951 thermal-sensors = <&t 6867 thermal-sensors = <&tsens1 5>;
6952 6868
6953 trips { 6869 trips {
6954 camera_alert0 6870 camera_alert0: trip-point0 {
6955 tempe 6871 temperature = <90000>;
6956 hyste 6872 hysteresis = <2000>;
6957 type 6873 type = "hot";
6958 }; 6874 };
6959 }; 6875 };
6960 }; 6876 };
6961 6877
6962 compute-thermal { 6878 compute-thermal {
6963 polling-delay-passive 6879 polling-delay-passive = <250>;
>> 6880 polling-delay = <1000>;
6964 6881
6965 thermal-sensors = <&t 6882 thermal-sensors = <&tsens1 6>;
6966 6883
6967 trips { 6884 trips {
6968 compute_alert 6885 compute_alert0: trip-point0 {
6969 tempe 6886 temperature = <90000>;
6970 hyste 6887 hysteresis = <2000>;
6971 type 6888 type = "hot";
6972 }; 6889 };
6973 }; 6890 };
6974 }; 6891 };
6975 6892
6976 npu-thermal { 6893 npu-thermal {
6977 polling-delay-passive 6894 polling-delay-passive = <250>;
>> 6895 polling-delay = <1000>;
6978 6896
6979 thermal-sensors = <&t 6897 thermal-sensors = <&tsens1 7>;
6980 6898
6981 trips { 6899 trips {
6982 npu_alert0: t 6900 npu_alert0: trip-point0 {
6983 tempe 6901 temperature = <90000>;
6984 hyste 6902 hysteresis = <2000>;
6985 type 6903 type = "hot";
6986 }; 6904 };
6987 }; 6905 };
6988 }; 6906 };
6989 6907
6990 gpu-bottom-thermal { 6908 gpu-bottom-thermal {
6991 polling-delay-passive 6909 polling-delay-passive = <250>;
>> 6910 polling-delay = <1000>;
6992 6911
6993 thermal-sensors = <&t 6912 thermal-sensors = <&tsens1 8>;
6994 6913
6995 cooling-maps { <<
6996 map0 { <<
6997 trip <<
6998 cooli <<
6999 }; <<
7000 }; <<
7001 <<
7002 trips { 6914 trips {
7003 gpu_bottom_al !! 6915 gpu2_alert0: trip-point0 {
7004 tempe <<
7005 hyste <<
7006 type <<
7007 }; <<
7008 <<
7009 trip-point1 { <<
7010 tempe 6916 temperature = <90000>;
7011 hyste !! 6917 hysteresis = <2000>;
7012 type 6918 type = "hot";
7013 }; <<
7014 <<
7015 trip-point2 { <<
7016 tempe <<
7017 hyste <<
7018 type <<
7019 }; 6919 };
7020 }; 6920 };
7021 }; 6921 };
7022 }; 6922 };
7023 }; 6923 };
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