1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * Copyright (c) 2020, The Linux Foundation. A 3 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
4 */ 4 */
5 5
6 #include <dt-bindings/interrupt-controller/arm 6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,dispcc-sm8250 7 #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
8 #include <dt-bindings/clock/qcom,gcc-sm8250.h> 8 #include <dt-bindings/clock/qcom,gcc-sm8250.h>
9 #include <dt-bindings/clock/qcom,gpucc-sm8250. 9 #include <dt-bindings/clock/qcom,gpucc-sm8250.h>
10 #include <dt-bindings/clock/qcom,rpmh.h> 10 #include <dt-bindings/clock/qcom,rpmh.h>
>> 11 #include <dt-bindings/clock/qcom,sm8250-lpass-aoncc.h>
>> 12 #include <dt-bindings/clock/qcom,sm8250-lpass-audiocc.h>
11 #include <dt-bindings/dma/qcom-gpi.h> 13 #include <dt-bindings/dma/qcom-gpi.h>
12 #include <dt-bindings/gpio/gpio.h> 14 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interconnect/qcom,osm-l3 15 #include <dt-bindings/interconnect/qcom,osm-l3.h>
14 #include <dt-bindings/interconnect/qcom,sm8250 16 #include <dt-bindings/interconnect/qcom,sm8250.h>
15 #include <dt-bindings/mailbox/qcom-ipcc.h> 17 #include <dt-bindings/mailbox/qcom-ipcc.h>
16 #include <dt-bindings/phy/phy-qcom-qmp.h> 18 #include <dt-bindings/phy/phy-qcom-qmp.h>
17 #include <dt-bindings/power/qcom-rpmpd.h> 19 #include <dt-bindings/power/qcom-rpmpd.h>
18 #include <dt-bindings/power/qcom,rpmhpd.h> 20 #include <dt-bindings/power/qcom,rpmhpd.h>
19 #include <dt-bindings/soc/qcom,apr.h> 21 #include <dt-bindings/soc/qcom,apr.h>
20 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 22 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
21 #include <dt-bindings/sound/qcom,q6afe.h> 23 #include <dt-bindings/sound/qcom,q6afe.h>
22 #include <dt-bindings/thermal/thermal.h> 24 #include <dt-bindings/thermal/thermal.h>
23 #include <dt-bindings/clock/qcom,camcc-sm8250. 25 #include <dt-bindings/clock/qcom,camcc-sm8250.h>
24 #include <dt-bindings/clock/qcom,videocc-sm825 26 #include <dt-bindings/clock/qcom,videocc-sm8250.h>
25 27
26 / { 28 / {
27 interrupt-parent = <&intc>; 29 interrupt-parent = <&intc>;
28 30
29 #address-cells = <2>; 31 #address-cells = <2>;
30 #size-cells = <2>; 32 #size-cells = <2>;
31 33
32 aliases { 34 aliases {
33 i2c0 = &i2c0; 35 i2c0 = &i2c0;
34 i2c1 = &i2c1; 36 i2c1 = &i2c1;
35 i2c2 = &i2c2; 37 i2c2 = &i2c2;
36 i2c3 = &i2c3; 38 i2c3 = &i2c3;
37 i2c4 = &i2c4; 39 i2c4 = &i2c4;
38 i2c5 = &i2c5; 40 i2c5 = &i2c5;
39 i2c6 = &i2c6; 41 i2c6 = &i2c6;
40 i2c7 = &i2c7; 42 i2c7 = &i2c7;
41 i2c8 = &i2c8; 43 i2c8 = &i2c8;
42 i2c9 = &i2c9; 44 i2c9 = &i2c9;
43 i2c10 = &i2c10; 45 i2c10 = &i2c10;
44 i2c11 = &i2c11; 46 i2c11 = &i2c11;
45 i2c12 = &i2c12; 47 i2c12 = &i2c12;
46 i2c13 = &i2c13; 48 i2c13 = &i2c13;
47 i2c14 = &i2c14; 49 i2c14 = &i2c14;
48 i2c15 = &i2c15; 50 i2c15 = &i2c15;
49 i2c16 = &i2c16; 51 i2c16 = &i2c16;
50 i2c17 = &i2c17; 52 i2c17 = &i2c17;
51 i2c18 = &i2c18; 53 i2c18 = &i2c18;
52 i2c19 = &i2c19; 54 i2c19 = &i2c19;
53 spi0 = &spi0; 55 spi0 = &spi0;
54 spi1 = &spi1; 56 spi1 = &spi1;
55 spi2 = &spi2; 57 spi2 = &spi2;
56 spi3 = &spi3; 58 spi3 = &spi3;
57 spi4 = &spi4; 59 spi4 = &spi4;
58 spi5 = &spi5; 60 spi5 = &spi5;
59 spi6 = &spi6; 61 spi6 = &spi6;
60 spi7 = &spi7; 62 spi7 = &spi7;
61 spi8 = &spi8; 63 spi8 = &spi8;
62 spi9 = &spi9; 64 spi9 = &spi9;
63 spi10 = &spi10; 65 spi10 = &spi10;
64 spi11 = &spi11; 66 spi11 = &spi11;
65 spi12 = &spi12; 67 spi12 = &spi12;
66 spi13 = &spi13; 68 spi13 = &spi13;
67 spi14 = &spi14; 69 spi14 = &spi14;
68 spi15 = &spi15; 70 spi15 = &spi15;
69 spi16 = &spi16; 71 spi16 = &spi16;
70 spi17 = &spi17; 72 spi17 = &spi17;
71 spi18 = &spi18; 73 spi18 = &spi18;
72 spi19 = &spi19; 74 spi19 = &spi19;
73 }; 75 };
74 76
75 chosen { }; 77 chosen { };
76 78
77 clocks { 79 clocks {
78 xo_board: xo-board { 80 xo_board: xo-board {
79 compatible = "fixed-cl 81 compatible = "fixed-clock";
80 #clock-cells = <0>; 82 #clock-cells = <0>;
81 clock-frequency = <384 83 clock-frequency = <38400000>;
82 clock-output-names = " 84 clock-output-names = "xo_board";
83 }; 85 };
84 86
85 sleep_clk: sleep-clk { 87 sleep_clk: sleep-clk {
86 compatible = "fixed-cl 88 compatible = "fixed-clock";
87 clock-frequency = <327 89 clock-frequency = <32768>;
88 #clock-cells = <0>; 90 #clock-cells = <0>;
89 }; 91 };
90 }; 92 };
91 93
92 cpus { 94 cpus {
93 #address-cells = <2>; 95 #address-cells = <2>;
94 #size-cells = <0>; 96 #size-cells = <0>;
95 97
96 CPU0: cpu@0 { 98 CPU0: cpu@0 {
97 device_type = "cpu"; 99 device_type = "cpu";
98 compatible = "qcom,kry 100 compatible = "qcom,kryo485";
99 reg = <0x0 0x0>; 101 reg = <0x0 0x0>;
100 clocks = <&cpufreq_hw 102 clocks = <&cpufreq_hw 0>;
101 enable-method = "psci" 103 enable-method = "psci";
102 capacity-dmips-mhz = < 104 capacity-dmips-mhz = <448>;
103 dynamic-power-coeffici 105 dynamic-power-coefficient = <105>;
104 next-level-cache = <&L 106 next-level-cache = <&L2_0>;
105 power-domains = <&CPU_ 107 power-domains = <&CPU_PD0>;
106 power-domain-names = " 108 power-domain-names = "psci";
107 qcom,freq-domain = <&c 109 qcom,freq-domain = <&cpufreq_hw 0>;
108 operating-points-v2 = 110 operating-points-v2 = <&cpu0_opp_table>;
109 interconnects = <&gem_ 111 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
110 <&epss 112 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
111 #cooling-cells = <2>; 113 #cooling-cells = <2>;
112 L2_0: l2-cache { 114 L2_0: l2-cache {
113 compatible = " 115 compatible = "cache";
114 cache-level = 116 cache-level = <2>;
115 cache-size = < 117 cache-size = <0x20000>;
116 cache-unified; 118 cache-unified;
117 next-level-cac 119 next-level-cache = <&L3_0>;
118 L3_0: l3-cache 120 L3_0: l3-cache {
119 compat 121 compatible = "cache";
120 cache- 122 cache-level = <3>;
121 cache- 123 cache-size = <0x400000>;
122 cache- 124 cache-unified;
123 }; 125 };
124 }; 126 };
125 }; 127 };
126 128
127 CPU1: cpu@100 { 129 CPU1: cpu@100 {
128 device_type = "cpu"; 130 device_type = "cpu";
129 compatible = "qcom,kry 131 compatible = "qcom,kryo485";
130 reg = <0x0 0x100>; 132 reg = <0x0 0x100>;
131 clocks = <&cpufreq_hw 133 clocks = <&cpufreq_hw 0>;
132 enable-method = "psci" 134 enable-method = "psci";
133 capacity-dmips-mhz = < 135 capacity-dmips-mhz = <448>;
134 dynamic-power-coeffici 136 dynamic-power-coefficient = <105>;
135 next-level-cache = <&L 137 next-level-cache = <&L2_100>;
136 power-domains = <&CPU_ 138 power-domains = <&CPU_PD1>;
137 power-domain-names = " 139 power-domain-names = "psci";
138 qcom,freq-domain = <&c 140 qcom,freq-domain = <&cpufreq_hw 0>;
139 operating-points-v2 = 141 operating-points-v2 = <&cpu0_opp_table>;
140 interconnects = <&gem_ 142 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
141 <&epss 143 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
142 #cooling-cells = <2>; 144 #cooling-cells = <2>;
143 L2_100: l2-cache { 145 L2_100: l2-cache {
144 compatible = " 146 compatible = "cache";
145 cache-level = 147 cache-level = <2>;
146 cache-size = < 148 cache-size = <0x20000>;
147 cache-unified; 149 cache-unified;
148 next-level-cac 150 next-level-cache = <&L3_0>;
149 }; 151 };
150 }; 152 };
151 153
152 CPU2: cpu@200 { 154 CPU2: cpu@200 {
153 device_type = "cpu"; 155 device_type = "cpu";
154 compatible = "qcom,kry 156 compatible = "qcom,kryo485";
155 reg = <0x0 0x200>; 157 reg = <0x0 0x200>;
156 clocks = <&cpufreq_hw 158 clocks = <&cpufreq_hw 0>;
157 enable-method = "psci" 159 enable-method = "psci";
158 capacity-dmips-mhz = < 160 capacity-dmips-mhz = <448>;
159 dynamic-power-coeffici 161 dynamic-power-coefficient = <105>;
160 next-level-cache = <&L 162 next-level-cache = <&L2_200>;
161 power-domains = <&CPU_ 163 power-domains = <&CPU_PD2>;
162 power-domain-names = " 164 power-domain-names = "psci";
163 qcom,freq-domain = <&c 165 qcom,freq-domain = <&cpufreq_hw 0>;
164 operating-points-v2 = 166 operating-points-v2 = <&cpu0_opp_table>;
165 interconnects = <&gem_ 167 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
166 <&epss 168 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
167 #cooling-cells = <2>; 169 #cooling-cells = <2>;
168 L2_200: l2-cache { 170 L2_200: l2-cache {
169 compatible = " 171 compatible = "cache";
170 cache-level = 172 cache-level = <2>;
171 cache-size = < 173 cache-size = <0x20000>;
172 cache-unified; 174 cache-unified;
173 next-level-cac 175 next-level-cache = <&L3_0>;
174 }; 176 };
175 }; 177 };
176 178
177 CPU3: cpu@300 { 179 CPU3: cpu@300 {
178 device_type = "cpu"; 180 device_type = "cpu";
179 compatible = "qcom,kry 181 compatible = "qcom,kryo485";
180 reg = <0x0 0x300>; 182 reg = <0x0 0x300>;
181 clocks = <&cpufreq_hw 183 clocks = <&cpufreq_hw 0>;
182 enable-method = "psci" 184 enable-method = "psci";
183 capacity-dmips-mhz = < 185 capacity-dmips-mhz = <448>;
184 dynamic-power-coeffici 186 dynamic-power-coefficient = <105>;
185 next-level-cache = <&L 187 next-level-cache = <&L2_300>;
186 power-domains = <&CPU_ 188 power-domains = <&CPU_PD3>;
187 power-domain-names = " 189 power-domain-names = "psci";
188 qcom,freq-domain = <&c 190 qcom,freq-domain = <&cpufreq_hw 0>;
189 operating-points-v2 = 191 operating-points-v2 = <&cpu0_opp_table>;
190 interconnects = <&gem_ 192 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
191 <&epss 193 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
192 #cooling-cells = <2>; 194 #cooling-cells = <2>;
193 L2_300: l2-cache { 195 L2_300: l2-cache {
194 compatible = " 196 compatible = "cache";
195 cache-level = 197 cache-level = <2>;
196 cache-size = < 198 cache-size = <0x20000>;
197 cache-unified; 199 cache-unified;
198 next-level-cac 200 next-level-cache = <&L3_0>;
199 }; 201 };
200 }; 202 };
201 203
202 CPU4: cpu@400 { 204 CPU4: cpu@400 {
203 device_type = "cpu"; 205 device_type = "cpu";
204 compatible = "qcom,kry 206 compatible = "qcom,kryo485";
205 reg = <0x0 0x400>; 207 reg = <0x0 0x400>;
206 clocks = <&cpufreq_hw 208 clocks = <&cpufreq_hw 1>;
207 enable-method = "psci" 209 enable-method = "psci";
208 capacity-dmips-mhz = < 210 capacity-dmips-mhz = <1024>;
209 dynamic-power-coeffici 211 dynamic-power-coefficient = <379>;
210 next-level-cache = <&L 212 next-level-cache = <&L2_400>;
211 power-domains = <&CPU_ 213 power-domains = <&CPU_PD4>;
212 power-domain-names = " 214 power-domain-names = "psci";
213 qcom,freq-domain = <&c 215 qcom,freq-domain = <&cpufreq_hw 1>;
214 operating-points-v2 = 216 operating-points-v2 = <&cpu4_opp_table>;
215 interconnects = <&gem_ 217 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
216 <&epss 218 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
217 #cooling-cells = <2>; 219 #cooling-cells = <2>;
218 L2_400: l2-cache { 220 L2_400: l2-cache {
219 compatible = " 221 compatible = "cache";
220 cache-level = 222 cache-level = <2>;
221 cache-size = < 223 cache-size = <0x40000>;
222 cache-unified; 224 cache-unified;
223 next-level-cac 225 next-level-cache = <&L3_0>;
224 }; 226 };
225 }; 227 };
226 228
227 CPU5: cpu@500 { 229 CPU5: cpu@500 {
228 device_type = "cpu"; 230 device_type = "cpu";
229 compatible = "qcom,kry 231 compatible = "qcom,kryo485";
230 reg = <0x0 0x500>; 232 reg = <0x0 0x500>;
231 clocks = <&cpufreq_hw 233 clocks = <&cpufreq_hw 1>;
232 enable-method = "psci" 234 enable-method = "psci";
233 capacity-dmips-mhz = < 235 capacity-dmips-mhz = <1024>;
234 dynamic-power-coeffici 236 dynamic-power-coefficient = <379>;
235 next-level-cache = <&L 237 next-level-cache = <&L2_500>;
236 power-domains = <&CPU_ 238 power-domains = <&CPU_PD5>;
237 power-domain-names = " 239 power-domain-names = "psci";
238 qcom,freq-domain = <&c 240 qcom,freq-domain = <&cpufreq_hw 1>;
239 operating-points-v2 = 241 operating-points-v2 = <&cpu4_opp_table>;
240 interconnects = <&gem_ 242 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
241 <&epss 243 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
242 #cooling-cells = <2>; 244 #cooling-cells = <2>;
243 L2_500: l2-cache { 245 L2_500: l2-cache {
244 compatible = " 246 compatible = "cache";
245 cache-level = 247 cache-level = <2>;
246 cache-size = < 248 cache-size = <0x40000>;
247 cache-unified; 249 cache-unified;
248 next-level-cac 250 next-level-cache = <&L3_0>;
249 }; 251 };
250 }; 252 };
251 253
252 CPU6: cpu@600 { 254 CPU6: cpu@600 {
253 device_type = "cpu"; 255 device_type = "cpu";
254 compatible = "qcom,kry 256 compatible = "qcom,kryo485";
255 reg = <0x0 0x600>; 257 reg = <0x0 0x600>;
256 clocks = <&cpufreq_hw 258 clocks = <&cpufreq_hw 1>;
257 enable-method = "psci" 259 enable-method = "psci";
258 capacity-dmips-mhz = < 260 capacity-dmips-mhz = <1024>;
259 dynamic-power-coeffici 261 dynamic-power-coefficient = <379>;
260 next-level-cache = <&L 262 next-level-cache = <&L2_600>;
261 power-domains = <&CPU_ 263 power-domains = <&CPU_PD6>;
262 power-domain-names = " 264 power-domain-names = "psci";
263 qcom,freq-domain = <&c 265 qcom,freq-domain = <&cpufreq_hw 1>;
264 operating-points-v2 = 266 operating-points-v2 = <&cpu4_opp_table>;
265 interconnects = <&gem_ 267 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
266 <&epss 268 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
267 #cooling-cells = <2>; 269 #cooling-cells = <2>;
268 L2_600: l2-cache { 270 L2_600: l2-cache {
269 compatible = " 271 compatible = "cache";
270 cache-level = 272 cache-level = <2>;
271 cache-size = < 273 cache-size = <0x40000>;
272 cache-unified; 274 cache-unified;
273 next-level-cac 275 next-level-cache = <&L3_0>;
274 }; 276 };
275 }; 277 };
276 278
277 CPU7: cpu@700 { 279 CPU7: cpu@700 {
278 device_type = "cpu"; 280 device_type = "cpu";
279 compatible = "qcom,kry 281 compatible = "qcom,kryo485";
280 reg = <0x0 0x700>; 282 reg = <0x0 0x700>;
281 clocks = <&cpufreq_hw 283 clocks = <&cpufreq_hw 2>;
282 enable-method = "psci" 284 enable-method = "psci";
283 capacity-dmips-mhz = < 285 capacity-dmips-mhz = <1024>;
284 dynamic-power-coeffici 286 dynamic-power-coefficient = <444>;
285 next-level-cache = <&L 287 next-level-cache = <&L2_700>;
286 power-domains = <&CPU_ 288 power-domains = <&CPU_PD7>;
287 power-domain-names = " 289 power-domain-names = "psci";
288 qcom,freq-domain = <&c 290 qcom,freq-domain = <&cpufreq_hw 2>;
289 operating-points-v2 = 291 operating-points-v2 = <&cpu7_opp_table>;
290 interconnects = <&gem_ 292 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
291 <&epss 293 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
292 #cooling-cells = <2>; 294 #cooling-cells = <2>;
293 L2_700: l2-cache { 295 L2_700: l2-cache {
294 compatible = " 296 compatible = "cache";
295 cache-level = 297 cache-level = <2>;
296 cache-size = < 298 cache-size = <0x80000>;
297 cache-unified; 299 cache-unified;
298 next-level-cac 300 next-level-cache = <&L3_0>;
299 }; 301 };
300 }; 302 };
301 303
302 cpu-map { 304 cpu-map {
303 cluster0 { 305 cluster0 {
304 core0 { 306 core0 {
305 cpu = 307 cpu = <&CPU0>;
306 }; 308 };
307 309
308 core1 { 310 core1 {
309 cpu = 311 cpu = <&CPU1>;
310 }; 312 };
311 313
312 core2 { 314 core2 {
313 cpu = 315 cpu = <&CPU2>;
314 }; 316 };
315 317
316 core3 { 318 core3 {
317 cpu = 319 cpu = <&CPU3>;
318 }; 320 };
319 321
320 core4 { 322 core4 {
321 cpu = 323 cpu = <&CPU4>;
322 }; 324 };
323 325
324 core5 { 326 core5 {
325 cpu = 327 cpu = <&CPU5>;
326 }; 328 };
327 329
328 core6 { 330 core6 {
329 cpu = 331 cpu = <&CPU6>;
330 }; 332 };
331 333
332 core7 { 334 core7 {
333 cpu = 335 cpu = <&CPU7>;
334 }; 336 };
335 }; 337 };
336 }; 338 };
337 339
338 idle-states { 340 idle-states {
339 entry-method = "psci"; 341 entry-method = "psci";
340 342
341 LITTLE_CPU_SLEEP_0: cp 343 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
342 compatible = " 344 compatible = "arm,idle-state";
343 idle-state-nam 345 idle-state-name = "silver-rail-power-collapse";
344 arm,psci-suspe 346 arm,psci-suspend-param = <0x40000004>;
345 entry-latency- 347 entry-latency-us = <360>;
346 exit-latency-u 348 exit-latency-us = <531>;
347 min-residency- 349 min-residency-us = <3934>;
348 local-timer-st 350 local-timer-stop;
349 }; 351 };
350 352
351 BIG_CPU_SLEEP_0: cpu-s 353 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
352 compatible = " 354 compatible = "arm,idle-state";
353 idle-state-nam 355 idle-state-name = "gold-rail-power-collapse";
354 arm,psci-suspe 356 arm,psci-suspend-param = <0x40000004>;
355 entry-latency- 357 entry-latency-us = <702>;
356 exit-latency-u 358 exit-latency-us = <1061>;
357 min-residency- 359 min-residency-us = <4488>;
358 local-timer-st 360 local-timer-stop;
359 }; 361 };
360 }; 362 };
361 363
362 domain-idle-states { 364 domain-idle-states {
363 CLUSTER_SLEEP_0: clust 365 CLUSTER_SLEEP_0: cluster-sleep-0 {
364 compatible = " 366 compatible = "domain-idle-state";
365 arm,psci-suspe 367 arm,psci-suspend-param = <0x4100c244>;
366 entry-latency- 368 entry-latency-us = <3264>;
367 exit-latency-u 369 exit-latency-us = <6562>;
368 min-residency- 370 min-residency-us = <9987>;
369 }; 371 };
370 }; 372 };
371 }; 373 };
372 374
373 qup_virt: interconnect-qup-virt { 375 qup_virt: interconnect-qup-virt {
374 compatible = "qcom,sm8250-qup- 376 compatible = "qcom,sm8250-qup-virt";
375 #interconnect-cells = <2>; 377 #interconnect-cells = <2>;
376 qcom,bcm-voters = <&apps_bcm_v 378 qcom,bcm-voters = <&apps_bcm_voter>;
377 }; 379 };
378 380
379 cpu0_opp_table: opp-table-cpu0 { 381 cpu0_opp_table: opp-table-cpu0 {
380 compatible = "operating-points 382 compatible = "operating-points-v2";
381 opp-shared; 383 opp-shared;
382 384
383 cpu0_opp1: opp-300000000 { 385 cpu0_opp1: opp-300000000 {
384 opp-hz = /bits/ 64 <30 386 opp-hz = /bits/ 64 <300000000>;
385 opp-peak-kBps = <80000 387 opp-peak-kBps = <800000 9600000>;
386 }; 388 };
387 389
388 cpu0_opp2: opp-403200000 { 390 cpu0_opp2: opp-403200000 {
389 opp-hz = /bits/ 64 <40 391 opp-hz = /bits/ 64 <403200000>;
390 opp-peak-kBps = <80000 392 opp-peak-kBps = <800000 9600000>;
391 }; 393 };
392 394
393 cpu0_opp3: opp-518400000 { 395 cpu0_opp3: opp-518400000 {
394 opp-hz = /bits/ 64 <51 396 opp-hz = /bits/ 64 <518400000>;
395 opp-peak-kBps = <80000 397 opp-peak-kBps = <800000 16588800>;
396 }; 398 };
397 399
398 cpu0_opp4: opp-614400000 { 400 cpu0_opp4: opp-614400000 {
399 opp-hz = /bits/ 64 <61 401 opp-hz = /bits/ 64 <614400000>;
400 opp-peak-kBps = <80000 402 opp-peak-kBps = <800000 16588800>;
401 }; 403 };
402 404
403 cpu0_opp5: opp-691200000 { 405 cpu0_opp5: opp-691200000 {
404 opp-hz = /bits/ 64 <69 406 opp-hz = /bits/ 64 <691200000>;
405 opp-peak-kBps = <80000 407 opp-peak-kBps = <800000 19660800>;
406 }; 408 };
407 409
408 cpu0_opp6: opp-787200000 { 410 cpu0_opp6: opp-787200000 {
409 opp-hz = /bits/ 64 <78 411 opp-hz = /bits/ 64 <787200000>;
410 opp-peak-kBps = <18040 412 opp-peak-kBps = <1804000 19660800>;
411 }; 413 };
412 414
413 cpu0_opp7: opp-883200000 { 415 cpu0_opp7: opp-883200000 {
414 opp-hz = /bits/ 64 <88 416 opp-hz = /bits/ 64 <883200000>;
415 opp-peak-kBps = <18040 417 opp-peak-kBps = <1804000 23347200>;
416 }; 418 };
417 419
418 cpu0_opp8: opp-979200000 { 420 cpu0_opp8: opp-979200000 {
419 opp-hz = /bits/ 64 <97 421 opp-hz = /bits/ 64 <979200000>;
420 opp-peak-kBps = <18040 422 opp-peak-kBps = <1804000 26419200>;
421 }; 423 };
422 424
423 cpu0_opp9: opp-1075200000 { 425 cpu0_opp9: opp-1075200000 {
424 opp-hz = /bits/ 64 <10 426 opp-hz = /bits/ 64 <1075200000>;
425 opp-peak-kBps = <18040 427 opp-peak-kBps = <1804000 29491200>;
426 }; 428 };
427 429
428 cpu0_opp10: opp-1171200000 { 430 cpu0_opp10: opp-1171200000 {
429 opp-hz = /bits/ 64 <11 431 opp-hz = /bits/ 64 <1171200000>;
430 opp-peak-kBps = <18040 432 opp-peak-kBps = <1804000 32563200>;
431 }; 433 };
432 434
433 cpu0_opp11: opp-1248000000 { 435 cpu0_opp11: opp-1248000000 {
434 opp-hz = /bits/ 64 <12 436 opp-hz = /bits/ 64 <1248000000>;
435 opp-peak-kBps = <18040 437 opp-peak-kBps = <1804000 36249600>;
436 }; 438 };
437 439
438 cpu0_opp12: opp-1344000000 { 440 cpu0_opp12: opp-1344000000 {
439 opp-hz = /bits/ 64 <13 441 opp-hz = /bits/ 64 <1344000000>;
440 opp-peak-kBps = <21880 442 opp-peak-kBps = <2188000 36249600>;
441 }; 443 };
442 444
443 cpu0_opp13: opp-1420800000 { 445 cpu0_opp13: opp-1420800000 {
444 opp-hz = /bits/ 64 <14 446 opp-hz = /bits/ 64 <1420800000>;
445 opp-peak-kBps = <21880 447 opp-peak-kBps = <2188000 39321600>;
446 }; 448 };
447 449
448 cpu0_opp14: opp-1516800000 { 450 cpu0_opp14: opp-1516800000 {
449 opp-hz = /bits/ 64 <15 451 opp-hz = /bits/ 64 <1516800000>;
450 opp-peak-kBps = <30720 452 opp-peak-kBps = <3072000 42393600>;
451 }; 453 };
452 454
453 cpu0_opp15: opp-1612800000 { 455 cpu0_opp15: opp-1612800000 {
454 opp-hz = /bits/ 64 <16 456 opp-hz = /bits/ 64 <1612800000>;
455 opp-peak-kBps = <30720 457 opp-peak-kBps = <3072000 42393600>;
456 }; 458 };
457 459
458 cpu0_opp16: opp-1708800000 { 460 cpu0_opp16: opp-1708800000 {
459 opp-hz = /bits/ 64 <17 461 opp-hz = /bits/ 64 <1708800000>;
460 opp-peak-kBps = <40680 462 opp-peak-kBps = <4068000 42393600>;
461 }; 463 };
462 464
463 cpu0_opp17: opp-1804800000 { 465 cpu0_opp17: opp-1804800000 {
464 opp-hz = /bits/ 64 <18 466 opp-hz = /bits/ 64 <1804800000>;
465 opp-peak-kBps = <40680 467 opp-peak-kBps = <4068000 42393600>;
466 }; 468 };
467 }; 469 };
468 470
469 cpu4_opp_table: opp-table-cpu4 { 471 cpu4_opp_table: opp-table-cpu4 {
470 compatible = "operating-points 472 compatible = "operating-points-v2";
471 opp-shared; 473 opp-shared;
472 474
473 cpu4_opp1: opp-710400000 { 475 cpu4_opp1: opp-710400000 {
474 opp-hz = /bits/ 64 <71 476 opp-hz = /bits/ 64 <710400000>;
475 opp-peak-kBps = <18040 477 opp-peak-kBps = <1804000 19660800>;
476 }; 478 };
477 479
478 cpu4_opp2: opp-825600000 { 480 cpu4_opp2: opp-825600000 {
479 opp-hz = /bits/ 64 <82 481 opp-hz = /bits/ 64 <825600000>;
480 opp-peak-kBps = <21880 482 opp-peak-kBps = <2188000 23347200>;
481 }; 483 };
482 484
483 cpu4_opp3: opp-940800000 { 485 cpu4_opp3: opp-940800000 {
484 opp-hz = /bits/ 64 <94 486 opp-hz = /bits/ 64 <940800000>;
485 opp-peak-kBps = <21880 487 opp-peak-kBps = <2188000 26419200>;
486 }; 488 };
487 489
488 cpu4_opp4: opp-1056000000 { 490 cpu4_opp4: opp-1056000000 {
489 opp-hz = /bits/ 64 <10 491 opp-hz = /bits/ 64 <1056000000>;
490 opp-peak-kBps = <30720 492 opp-peak-kBps = <3072000 26419200>;
491 }; 493 };
492 494
493 cpu4_opp5: opp-1171200000 { 495 cpu4_opp5: opp-1171200000 {
494 opp-hz = /bits/ 64 <11 496 opp-hz = /bits/ 64 <1171200000>;
495 opp-peak-kBps = <30720 497 opp-peak-kBps = <3072000 29491200>;
496 }; 498 };
497 499
498 cpu4_opp6: opp-1286400000 { 500 cpu4_opp6: opp-1286400000 {
499 opp-hz = /bits/ 64 <12 501 opp-hz = /bits/ 64 <1286400000>;
500 opp-peak-kBps = <40680 502 opp-peak-kBps = <4068000 29491200>;
501 }; 503 };
502 504
503 cpu4_opp7: opp-1382400000 { 505 cpu4_opp7: opp-1382400000 {
504 opp-hz = /bits/ 64 <13 506 opp-hz = /bits/ 64 <1382400000>;
505 opp-peak-kBps = <40680 507 opp-peak-kBps = <4068000 32563200>;
506 }; 508 };
507 509
508 cpu4_opp8: opp-1478400000 { 510 cpu4_opp8: opp-1478400000 {
509 opp-hz = /bits/ 64 <14 511 opp-hz = /bits/ 64 <1478400000>;
510 opp-peak-kBps = <40680 512 opp-peak-kBps = <4068000 32563200>;
511 }; 513 };
512 514
513 cpu4_opp9: opp-1574400000 { 515 cpu4_opp9: opp-1574400000 {
514 opp-hz = /bits/ 64 <15 516 opp-hz = /bits/ 64 <1574400000>;
515 opp-peak-kBps = <54120 517 opp-peak-kBps = <5412000 39321600>;
516 }; 518 };
517 519
518 cpu4_opp10: opp-1670400000 { 520 cpu4_opp10: opp-1670400000 {
519 opp-hz = /bits/ 64 <16 521 opp-hz = /bits/ 64 <1670400000>;
520 opp-peak-kBps = <54120 522 opp-peak-kBps = <5412000 42393600>;
521 }; 523 };
522 524
523 cpu4_opp11: opp-1766400000 { 525 cpu4_opp11: opp-1766400000 {
524 opp-hz = /bits/ 64 <17 526 opp-hz = /bits/ 64 <1766400000>;
525 opp-peak-kBps = <54120 527 opp-peak-kBps = <5412000 45465600>;
526 }; 528 };
527 529
528 cpu4_opp12: opp-1862400000 { 530 cpu4_opp12: opp-1862400000 {
529 opp-hz = /bits/ 64 <18 531 opp-hz = /bits/ 64 <1862400000>;
530 opp-peak-kBps = <62200 532 opp-peak-kBps = <6220000 45465600>;
531 }; 533 };
532 534
533 cpu4_opp13: opp-1958400000 { 535 cpu4_opp13: opp-1958400000 {
534 opp-hz = /bits/ 64 <19 536 opp-hz = /bits/ 64 <1958400000>;
535 opp-peak-kBps = <62200 537 opp-peak-kBps = <6220000 48537600>;
536 }; 538 };
537 539
538 cpu4_opp14: opp-2054400000 { 540 cpu4_opp14: opp-2054400000 {
539 opp-hz = /bits/ 64 <20 541 opp-hz = /bits/ 64 <2054400000>;
540 opp-peak-kBps = <72160 542 opp-peak-kBps = <7216000 48537600>;
541 }; 543 };
542 544
543 cpu4_opp15: opp-2150400000 { 545 cpu4_opp15: opp-2150400000 {
544 opp-hz = /bits/ 64 <21 546 opp-hz = /bits/ 64 <2150400000>;
545 opp-peak-kBps = <72160 547 opp-peak-kBps = <7216000 51609600>;
546 }; 548 };
547 549
548 cpu4_opp16: opp-2246400000 { 550 cpu4_opp16: opp-2246400000 {
549 opp-hz = /bits/ 64 <22 551 opp-hz = /bits/ 64 <2246400000>;
550 opp-peak-kBps = <72160 552 opp-peak-kBps = <7216000 51609600>;
551 }; 553 };
552 554
553 cpu4_opp17: opp-2342400000 { 555 cpu4_opp17: opp-2342400000 {
554 opp-hz = /bits/ 64 <23 556 opp-hz = /bits/ 64 <2342400000>;
555 opp-peak-kBps = <83680 557 opp-peak-kBps = <8368000 51609600>;
556 }; 558 };
557 559
558 cpu4_opp18: opp-2419200000 { 560 cpu4_opp18: opp-2419200000 {
559 opp-hz = /bits/ 64 <24 561 opp-hz = /bits/ 64 <2419200000>;
560 opp-peak-kBps = <83680 562 opp-peak-kBps = <8368000 51609600>;
561 }; 563 };
562 }; 564 };
563 565
564 cpu7_opp_table: opp-table-cpu7 { 566 cpu7_opp_table: opp-table-cpu7 {
565 compatible = "operating-points 567 compatible = "operating-points-v2";
566 opp-shared; 568 opp-shared;
567 569
568 cpu7_opp1: opp-844800000 { 570 cpu7_opp1: opp-844800000 {
569 opp-hz = /bits/ 64 <84 571 opp-hz = /bits/ 64 <844800000>;
570 opp-peak-kBps = <21880 572 opp-peak-kBps = <2188000 19660800>;
571 }; 573 };
572 574
573 cpu7_opp2: opp-960000000 { 575 cpu7_opp2: opp-960000000 {
574 opp-hz = /bits/ 64 <96 576 opp-hz = /bits/ 64 <960000000>;
575 opp-peak-kBps = <21880 577 opp-peak-kBps = <2188000 26419200>;
576 }; 578 };
577 579
578 cpu7_opp3: opp-1075200000 { 580 cpu7_opp3: opp-1075200000 {
579 opp-hz = /bits/ 64 <10 581 opp-hz = /bits/ 64 <1075200000>;
580 opp-peak-kBps = <30720 582 opp-peak-kBps = <3072000 26419200>;
581 }; 583 };
582 584
583 cpu7_opp4: opp-1190400000 { 585 cpu7_opp4: opp-1190400000 {
584 opp-hz = /bits/ 64 <11 586 opp-hz = /bits/ 64 <1190400000>;
585 opp-peak-kBps = <30720 587 opp-peak-kBps = <3072000 29491200>;
586 }; 588 };
587 589
588 cpu7_opp5: opp-1305600000 { 590 cpu7_opp5: opp-1305600000 {
589 opp-hz = /bits/ 64 <13 591 opp-hz = /bits/ 64 <1305600000>;
590 opp-peak-kBps = <40680 592 opp-peak-kBps = <4068000 32563200>;
591 }; 593 };
592 594
593 cpu7_opp6: opp-1401600000 { 595 cpu7_opp6: opp-1401600000 {
594 opp-hz = /bits/ 64 <14 596 opp-hz = /bits/ 64 <1401600000>;
595 opp-peak-kBps = <40680 597 opp-peak-kBps = <4068000 32563200>;
596 }; 598 };
597 599
598 cpu7_opp7: opp-1516800000 { 600 cpu7_opp7: opp-1516800000 {
599 opp-hz = /bits/ 64 <15 601 opp-hz = /bits/ 64 <1516800000>;
600 opp-peak-kBps = <40680 602 opp-peak-kBps = <4068000 36249600>;
601 }; 603 };
602 604
603 cpu7_opp8: opp-1632000000 { 605 cpu7_opp8: opp-1632000000 {
604 opp-hz = /bits/ 64 <16 606 opp-hz = /bits/ 64 <1632000000>;
605 opp-peak-kBps = <54120 607 opp-peak-kBps = <5412000 39321600>;
606 }; 608 };
607 609
608 cpu7_opp9: opp-1747200000 { 610 cpu7_opp9: opp-1747200000 {
609 opp-hz = /bits/ 64 <17 611 opp-hz = /bits/ 64 <1708800000>;
610 opp-peak-kBps = <54120 612 opp-peak-kBps = <5412000 42393600>;
611 }; 613 };
612 614
613 cpu7_opp10: opp-1862400000 { 615 cpu7_opp10: opp-1862400000 {
614 opp-hz = /bits/ 64 <18 616 opp-hz = /bits/ 64 <1862400000>;
615 opp-peak-kBps = <62200 617 opp-peak-kBps = <6220000 45465600>;
616 }; 618 };
617 619
618 cpu7_opp11: opp-1977600000 { 620 cpu7_opp11: opp-1977600000 {
619 opp-hz = /bits/ 64 <19 621 opp-hz = /bits/ 64 <1977600000>;
620 opp-peak-kBps = <62200 622 opp-peak-kBps = <6220000 48537600>;
621 }; 623 };
622 624
623 cpu7_opp12: opp-2073600000 { 625 cpu7_opp12: opp-2073600000 {
624 opp-hz = /bits/ 64 <20 626 opp-hz = /bits/ 64 <2073600000>;
625 opp-peak-kBps = <72160 627 opp-peak-kBps = <7216000 48537600>;
626 }; 628 };
627 629
628 cpu7_opp13: opp-2169600000 { 630 cpu7_opp13: opp-2169600000 {
629 opp-hz = /bits/ 64 <21 631 opp-hz = /bits/ 64 <2169600000>;
630 opp-peak-kBps = <72160 632 opp-peak-kBps = <7216000 51609600>;
631 }; 633 };
632 634
633 cpu7_opp14: opp-2265600000 { 635 cpu7_opp14: opp-2265600000 {
634 opp-hz = /bits/ 64 <22 636 opp-hz = /bits/ 64 <2265600000>;
635 opp-peak-kBps = <72160 637 opp-peak-kBps = <7216000 51609600>;
636 }; 638 };
637 639
638 cpu7_opp15: opp-2361600000 { 640 cpu7_opp15: opp-2361600000 {
639 opp-hz = /bits/ 64 <23 641 opp-hz = /bits/ 64 <2361600000>;
640 opp-peak-kBps = <83680 642 opp-peak-kBps = <8368000 51609600>;
641 }; 643 };
642 644
643 cpu7_opp16: opp-2457600000 { 645 cpu7_opp16: opp-2457600000 {
644 opp-hz = /bits/ 64 <24 646 opp-hz = /bits/ 64 <2457600000>;
645 opp-peak-kBps = <83680 647 opp-peak-kBps = <8368000 51609600>;
646 }; 648 };
647 649
648 cpu7_opp17: opp-2553600000 { 650 cpu7_opp17: opp-2553600000 {
649 opp-hz = /bits/ 64 <25 651 opp-hz = /bits/ 64 <2553600000>;
650 opp-peak-kBps = <83680 652 opp-peak-kBps = <8368000 51609600>;
651 }; 653 };
652 654
653 cpu7_opp18: opp-2649600000 { 655 cpu7_opp18: opp-2649600000 {
654 opp-hz = /bits/ 64 <26 656 opp-hz = /bits/ 64 <2649600000>;
655 opp-peak-kBps = <83680 657 opp-peak-kBps = <8368000 51609600>;
656 }; 658 };
657 659
658 cpu7_opp19: opp-2745600000 { 660 cpu7_opp19: opp-2745600000 {
659 opp-hz = /bits/ 64 <27 661 opp-hz = /bits/ 64 <2745600000>;
660 opp-peak-kBps = <83680 662 opp-peak-kBps = <8368000 51609600>;
661 }; 663 };
662 664
663 cpu7_opp20: opp-2841600000 { 665 cpu7_opp20: opp-2841600000 {
664 opp-hz = /bits/ 64 <28 666 opp-hz = /bits/ 64 <2841600000>;
665 opp-peak-kBps = <83680 667 opp-peak-kBps = <8368000 51609600>;
666 }; 668 };
667 }; 669 };
668 670
669 firmware { 671 firmware {
670 scm: scm { 672 scm: scm {
671 compatible = "qcom,scm 673 compatible = "qcom,scm-sm8250", "qcom,scm";
672 qcom,dload-mode = <&tc 674 qcom,dload-mode = <&tcsr 0x13000>;
673 #reset-cells = <1>; 675 #reset-cells = <1>;
674 }; 676 };
675 }; 677 };
676 678
677 memory@80000000 { 679 memory@80000000 {
678 device_type = "memory"; 680 device_type = "memory";
679 /* We expect the bootloader to 681 /* We expect the bootloader to fill in the size */
680 reg = <0x0 0x80000000 0x0 0x0> 682 reg = <0x0 0x80000000 0x0 0x0>;
681 }; 683 };
682 684
683 pmu { 685 pmu {
684 compatible = "arm,armv8-pmuv3" 686 compatible = "arm,armv8-pmuv3";
685 interrupts = <GIC_PPI 7 IRQ_TY 687 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
686 }; 688 };
687 689
688 psci { 690 psci {
689 compatible = "arm,psci-1.0"; 691 compatible = "arm,psci-1.0";
690 method = "smc"; 692 method = "smc";
691 693
692 CPU_PD0: power-domain-cpu0 { 694 CPU_PD0: power-domain-cpu0 {
693 #power-domain-cells = 695 #power-domain-cells = <0>;
694 power-domains = <&CLUS 696 power-domains = <&CLUSTER_PD>;
695 domain-idle-states = < 697 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
696 }; 698 };
697 699
698 CPU_PD1: power-domain-cpu1 { 700 CPU_PD1: power-domain-cpu1 {
699 #power-domain-cells = 701 #power-domain-cells = <0>;
700 power-domains = <&CLUS 702 power-domains = <&CLUSTER_PD>;
701 domain-idle-states = < 703 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
702 }; 704 };
703 705
704 CPU_PD2: power-domain-cpu2 { 706 CPU_PD2: power-domain-cpu2 {
705 #power-domain-cells = 707 #power-domain-cells = <0>;
706 power-domains = <&CLUS 708 power-domains = <&CLUSTER_PD>;
707 domain-idle-states = < 709 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
708 }; 710 };
709 711
710 CPU_PD3: power-domain-cpu3 { 712 CPU_PD3: power-domain-cpu3 {
711 #power-domain-cells = 713 #power-domain-cells = <0>;
712 power-domains = <&CLUS 714 power-domains = <&CLUSTER_PD>;
713 domain-idle-states = < 715 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
714 }; 716 };
715 717
716 CPU_PD4: power-domain-cpu4 { 718 CPU_PD4: power-domain-cpu4 {
717 #power-domain-cells = 719 #power-domain-cells = <0>;
718 power-domains = <&CLUS 720 power-domains = <&CLUSTER_PD>;
719 domain-idle-states = < 721 domain-idle-states = <&BIG_CPU_SLEEP_0>;
720 }; 722 };
721 723
722 CPU_PD5: power-domain-cpu5 { 724 CPU_PD5: power-domain-cpu5 {
723 #power-domain-cells = 725 #power-domain-cells = <0>;
724 power-domains = <&CLUS 726 power-domains = <&CLUSTER_PD>;
725 domain-idle-states = < 727 domain-idle-states = <&BIG_CPU_SLEEP_0>;
726 }; 728 };
727 729
728 CPU_PD6: power-domain-cpu6 { 730 CPU_PD6: power-domain-cpu6 {
729 #power-domain-cells = 731 #power-domain-cells = <0>;
730 power-domains = <&CLUS 732 power-domains = <&CLUSTER_PD>;
731 domain-idle-states = < 733 domain-idle-states = <&BIG_CPU_SLEEP_0>;
732 }; 734 };
733 735
734 CPU_PD7: power-domain-cpu7 { 736 CPU_PD7: power-domain-cpu7 {
735 #power-domain-cells = 737 #power-domain-cells = <0>;
736 power-domains = <&CLUS 738 power-domains = <&CLUSTER_PD>;
737 domain-idle-states = < 739 domain-idle-states = <&BIG_CPU_SLEEP_0>;
738 }; 740 };
739 741
740 CLUSTER_PD: power-domain-cpu-c 742 CLUSTER_PD: power-domain-cpu-cluster0 {
741 #power-domain-cells = 743 #power-domain-cells = <0>;
742 domain-idle-states = < 744 domain-idle-states = <&CLUSTER_SLEEP_0>;
743 }; 745 };
744 }; 746 };
745 747
746 qup_opp_table: opp-table-qup { 748 qup_opp_table: opp-table-qup {
747 compatible = "operating-points 749 compatible = "operating-points-v2";
748 750
749 opp-50000000 { 751 opp-50000000 {
750 opp-hz = /bits/ 64 <50 752 opp-hz = /bits/ 64 <50000000>;
751 required-opps = <&rpmh 753 required-opps = <&rpmhpd_opp_min_svs>;
752 }; 754 };
753 755
754 opp-75000000 { 756 opp-75000000 {
755 opp-hz = /bits/ 64 <75 757 opp-hz = /bits/ 64 <75000000>;
756 required-opps = <&rpmh 758 required-opps = <&rpmhpd_opp_low_svs>;
757 }; 759 };
758 760
759 opp-120000000 { 761 opp-120000000 {
760 opp-hz = /bits/ 64 <12 762 opp-hz = /bits/ 64 <120000000>;
761 required-opps = <&rpmh 763 required-opps = <&rpmhpd_opp_svs>;
762 }; 764 };
763 }; 765 };
764 766
765 reserved-memory { 767 reserved-memory {
766 #address-cells = <2>; 768 #address-cells = <2>;
767 #size-cells = <2>; 769 #size-cells = <2>;
768 ranges; 770 ranges;
769 771
770 hyp_mem: memory@80000000 { 772 hyp_mem: memory@80000000 {
771 reg = <0x0 0x80000000 773 reg = <0x0 0x80000000 0x0 0x600000>;
772 no-map; 774 no-map;
773 }; 775 };
774 776
775 xbl_aop_mem: memory@80700000 { 777 xbl_aop_mem: memory@80700000 {
776 reg = <0x0 0x80700000 778 reg = <0x0 0x80700000 0x0 0x160000>;
777 no-map; 779 no-map;
778 }; 780 };
779 781
780 cmd_db: memory@80860000 { 782 cmd_db: memory@80860000 {
781 compatible = "qcom,cmd 783 compatible = "qcom,cmd-db";
782 reg = <0x0 0x80860000 784 reg = <0x0 0x80860000 0x0 0x20000>;
783 no-map; 785 no-map;
784 }; 786 };
785 787
786 smem_mem: memory@80900000 { 788 smem_mem: memory@80900000 {
787 reg = <0x0 0x80900000 789 reg = <0x0 0x80900000 0x0 0x200000>;
788 no-map; 790 no-map;
789 }; 791 };
790 792
791 removed_mem: memory@80b00000 { 793 removed_mem: memory@80b00000 {
792 reg = <0x0 0x80b00000 794 reg = <0x0 0x80b00000 0x0 0x5300000>;
793 no-map; 795 no-map;
794 }; 796 };
795 797
796 camera_mem: memory@86200000 { 798 camera_mem: memory@86200000 {
797 reg = <0x0 0x86200000 799 reg = <0x0 0x86200000 0x0 0x500000>;
798 no-map; 800 no-map;
799 }; 801 };
800 802
801 wlan_mem: memory@86700000 { 803 wlan_mem: memory@86700000 {
802 reg = <0x0 0x86700000 804 reg = <0x0 0x86700000 0x0 0x100000>;
803 no-map; 805 no-map;
804 }; 806 };
805 807
806 ipa_fw_mem: memory@86800000 { 808 ipa_fw_mem: memory@86800000 {
807 reg = <0x0 0x86800000 809 reg = <0x0 0x86800000 0x0 0x10000>;
808 no-map; 810 no-map;
809 }; 811 };
810 812
811 ipa_gsi_mem: memory@86810000 { 813 ipa_gsi_mem: memory@86810000 {
812 reg = <0x0 0x86810000 814 reg = <0x0 0x86810000 0x0 0xa000>;
813 no-map; 815 no-map;
814 }; 816 };
815 817
816 gpu_mem: memory@8681a000 { 818 gpu_mem: memory@8681a000 {
817 reg = <0x0 0x8681a000 819 reg = <0x0 0x8681a000 0x0 0x2000>;
818 no-map; 820 no-map;
819 }; 821 };
820 822
821 npu_mem: memory@86900000 { 823 npu_mem: memory@86900000 {
822 reg = <0x0 0x86900000 824 reg = <0x0 0x86900000 0x0 0x500000>;
823 no-map; 825 no-map;
824 }; 826 };
825 827
826 video_mem: memory@86e00000 { 828 video_mem: memory@86e00000 {
827 reg = <0x0 0x86e00000 829 reg = <0x0 0x86e00000 0x0 0x500000>;
828 no-map; 830 no-map;
829 }; 831 };
830 832
831 cvp_mem: memory@87300000 { 833 cvp_mem: memory@87300000 {
832 reg = <0x0 0x87300000 834 reg = <0x0 0x87300000 0x0 0x500000>;
833 no-map; 835 no-map;
834 }; 836 };
835 837
836 cdsp_mem: memory@87800000 { 838 cdsp_mem: memory@87800000 {
837 reg = <0x0 0x87800000 839 reg = <0x0 0x87800000 0x0 0x1400000>;
838 no-map; 840 no-map;
839 }; 841 };
840 842
841 slpi_mem: memory@88c00000 { 843 slpi_mem: memory@88c00000 {
842 reg = <0x0 0x88c00000 844 reg = <0x0 0x88c00000 0x0 0x1500000>;
843 no-map; 845 no-map;
844 }; 846 };
845 847
846 adsp_mem: memory@8a100000 { 848 adsp_mem: memory@8a100000 {
847 reg = <0x0 0x8a100000 849 reg = <0x0 0x8a100000 0x0 0x1d00000>;
848 no-map; 850 no-map;
849 }; 851 };
850 852
851 spss_mem: memory@8be00000 { 853 spss_mem: memory@8be00000 {
852 reg = <0x0 0x8be00000 854 reg = <0x0 0x8be00000 0x0 0x100000>;
853 no-map; 855 no-map;
854 }; 856 };
855 857
856 cdsp_secure_heap: memory@8bf00 858 cdsp_secure_heap: memory@8bf00000 {
857 reg = <0x0 0x8bf00000 859 reg = <0x0 0x8bf00000 0x0 0x4600000>;
858 no-map; 860 no-map;
859 }; 861 };
860 }; 862 };
861 863
862 smem { 864 smem {
863 compatible = "qcom,smem"; 865 compatible = "qcom,smem";
864 memory-region = <&smem_mem>; 866 memory-region = <&smem_mem>;
865 hwlocks = <&tcsr_mutex 3>; 867 hwlocks = <&tcsr_mutex 3>;
866 }; 868 };
867 869
868 smp2p-adsp { 870 smp2p-adsp {
869 compatible = "qcom,smp2p"; 871 compatible = "qcom,smp2p";
870 qcom,smem = <443>, <429>; 872 qcom,smem = <443>, <429>;
871 interrupts-extended = <&ipcc I 873 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
872 I 874 IPCC_MPROC_SIGNAL_SMP2P
873 I 875 IRQ_TYPE_EDGE_RISING>;
874 mboxes = <&ipcc IPCC_CLIENT_LP 876 mboxes = <&ipcc IPCC_CLIENT_LPASS
875 IPCC_MPROC_SIG 877 IPCC_MPROC_SIGNAL_SMP2P>;
876 878
877 qcom,local-pid = <0>; 879 qcom,local-pid = <0>;
878 qcom,remote-pid = <2>; 880 qcom,remote-pid = <2>;
879 881
880 smp2p_adsp_out: master-kernel 882 smp2p_adsp_out: master-kernel {
881 qcom,entry-name = "mas 883 qcom,entry-name = "master-kernel";
882 #qcom,smem-state-cells 884 #qcom,smem-state-cells = <1>;
883 }; 885 };
884 886
885 smp2p_adsp_in: slave-kernel { 887 smp2p_adsp_in: slave-kernel {
886 qcom,entry-name = "sla 888 qcom,entry-name = "slave-kernel";
887 interrupt-controller; 889 interrupt-controller;
888 #interrupt-cells = <2> 890 #interrupt-cells = <2>;
889 }; 891 };
890 }; 892 };
891 893
892 smp2p-cdsp { 894 smp2p-cdsp {
893 compatible = "qcom,smp2p"; 895 compatible = "qcom,smp2p";
894 qcom,smem = <94>, <432>; 896 qcom,smem = <94>, <432>;
895 interrupts-extended = <&ipcc I 897 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
896 I 898 IPCC_MPROC_SIGNAL_SMP2P
897 I 899 IRQ_TYPE_EDGE_RISING>;
898 mboxes = <&ipcc IPCC_CLIENT_CD 900 mboxes = <&ipcc IPCC_CLIENT_CDSP
899 IPCC_MPROC_SIG 901 IPCC_MPROC_SIGNAL_SMP2P>;
900 902
901 qcom,local-pid = <0>; 903 qcom,local-pid = <0>;
902 qcom,remote-pid = <5>; 904 qcom,remote-pid = <5>;
903 905
904 smp2p_cdsp_out: master-kernel 906 smp2p_cdsp_out: master-kernel {
905 qcom,entry-name = "mas 907 qcom,entry-name = "master-kernel";
906 #qcom,smem-state-cells 908 #qcom,smem-state-cells = <1>;
907 }; 909 };
908 910
909 smp2p_cdsp_in: slave-kernel { 911 smp2p_cdsp_in: slave-kernel {
910 qcom,entry-name = "sla 912 qcom,entry-name = "slave-kernel";
911 interrupt-controller; 913 interrupt-controller;
912 #interrupt-cells = <2> 914 #interrupt-cells = <2>;
913 }; 915 };
914 }; 916 };
915 917
916 smp2p-slpi { 918 smp2p-slpi {
917 compatible = "qcom,smp2p"; 919 compatible = "qcom,smp2p";
918 qcom,smem = <481>, <430>; 920 qcom,smem = <481>, <430>;
919 interrupts-extended = <&ipcc I 921 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
920 I 922 IPCC_MPROC_SIGNAL_SMP2P
921 I 923 IRQ_TYPE_EDGE_RISING>;
922 mboxes = <&ipcc IPCC_CLIENT_SL 924 mboxes = <&ipcc IPCC_CLIENT_SLPI
923 IPCC_MPROC_SIG 925 IPCC_MPROC_SIGNAL_SMP2P>;
924 926
925 qcom,local-pid = <0>; 927 qcom,local-pid = <0>;
926 qcom,remote-pid = <3>; 928 qcom,remote-pid = <3>;
927 929
928 smp2p_slpi_out: master-kernel 930 smp2p_slpi_out: master-kernel {
929 qcom,entry-name = "mas 931 qcom,entry-name = "master-kernel";
930 #qcom,smem-state-cells 932 #qcom,smem-state-cells = <1>;
931 }; 933 };
932 934
933 smp2p_slpi_in: slave-kernel { 935 smp2p_slpi_in: slave-kernel {
934 qcom,entry-name = "sla 936 qcom,entry-name = "slave-kernel";
935 interrupt-controller; 937 interrupt-controller;
936 #interrupt-cells = <2> 938 #interrupt-cells = <2>;
937 }; 939 };
938 }; 940 };
939 941
940 soc: soc@0 { 942 soc: soc@0 {
941 #address-cells = <2>; 943 #address-cells = <2>;
942 #size-cells = <2>; 944 #size-cells = <2>;
943 ranges = <0 0 0 0 0x10 0>; 945 ranges = <0 0 0 0 0x10 0>;
944 dma-ranges = <0 0 0 0 0x10 0>; 946 dma-ranges = <0 0 0 0 0x10 0>;
945 compatible = "simple-bus"; 947 compatible = "simple-bus";
946 948
947 gcc: clock-controller@100000 { 949 gcc: clock-controller@100000 {
948 compatible = "qcom,gcc 950 compatible = "qcom,gcc-sm8250";
949 reg = <0x0 0x00100000 951 reg = <0x0 0x00100000 0x0 0x1f0000>;
950 #clock-cells = <1>; 952 #clock-cells = <1>;
951 #reset-cells = <1>; 953 #reset-cells = <1>;
952 #power-domain-cells = 954 #power-domain-cells = <1>;
953 clock-names = "bi_tcxo 955 clock-names = "bi_tcxo",
954 "bi_tcxo 956 "bi_tcxo_ao",
955 "sleep_c 957 "sleep_clk";
956 clocks = <&rpmhcc RPMH 958 clocks = <&rpmhcc RPMH_CXO_CLK>,
957 <&rpmhcc RPMH 959 <&rpmhcc RPMH_CXO_CLK_A>,
958 <&sleep_clk>; 960 <&sleep_clk>;
959 }; 961 };
960 962
961 ipcc: mailbox@408000 { 963 ipcc: mailbox@408000 {
962 compatible = "qcom,sm8 964 compatible = "qcom,sm8250-ipcc", "qcom,ipcc";
963 reg = <0 0x00408000 0 965 reg = <0 0x00408000 0 0x1000>;
964 interrupts = <GIC_SPI 966 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
965 interrupt-controller; 967 interrupt-controller;
966 #interrupt-cells = <3> 968 #interrupt-cells = <3>;
967 #mbox-cells = <2>; 969 #mbox-cells = <2>;
968 }; 970 };
969 971
970 qfprom: efuse@784000 { 972 qfprom: efuse@784000 {
971 compatible = "qcom,sm8 973 compatible = "qcom,sm8250-qfprom", "qcom,qfprom";
972 reg = <0 0x00784000 0 974 reg = <0 0x00784000 0 0x8ff>;
973 #address-cells = <1>; 975 #address-cells = <1>;
974 #size-cells = <1>; 976 #size-cells = <1>;
975 977
976 gpu_speed_bin: gpu-spe 978 gpu_speed_bin: gpu-speed-bin@19b {
977 reg = <0x19b 0 979 reg = <0x19b 0x1>;
978 bits = <5 3>; 980 bits = <5 3>;
979 }; 981 };
980 }; 982 };
981 983
982 rng: rng@793000 { 984 rng: rng@793000 {
983 compatible = "qcom,prn 985 compatible = "qcom,prng-ee";
984 reg = <0 0x00793000 0 986 reg = <0 0x00793000 0 0x1000>;
985 clocks = <&gcc GCC_PRN 987 clocks = <&gcc GCC_PRNG_AHB_CLK>;
986 clock-names = "core"; 988 clock-names = "core";
987 }; 989 };
988 990
989 gpi_dma2: dma-controller@80000 991 gpi_dma2: dma-controller@800000 {
990 compatible = "qcom,sm8 992 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma";
991 reg = <0 0x00800000 0 993 reg = <0 0x00800000 0 0x70000>;
992 interrupts = <GIC_SPI 994 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
993 <GIC_SPI 995 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
994 <GIC_SPI 996 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
995 <GIC_SPI 997 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
996 <GIC_SPI 998 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
997 <GIC_SPI 999 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
998 <GIC_SPI 1000 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
999 <GIC_SPI 1001 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
1000 <GIC_SPI 1002 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
1001 <GIC_SPI 1003 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>;
1002 dma-channels = <10>; 1004 dma-channels = <10>;
1003 dma-channel-mask = <0 1005 dma-channel-mask = <0x3f>;
1004 iommus = <&apps_smmu 1006 iommus = <&apps_smmu 0x76 0x0>;
1005 #dma-cells = <3>; 1007 #dma-cells = <3>;
1006 status = "disabled"; 1008 status = "disabled";
1007 }; 1009 };
1008 1010
1009 qupv3_id_2: geniqup@8c0000 { 1011 qupv3_id_2: geniqup@8c0000 {
1010 compatible = "qcom,ge 1012 compatible = "qcom,geni-se-qup";
1011 reg = <0x0 0x008c0000 1013 reg = <0x0 0x008c0000 0x0 0x6000>;
1012 clock-names = "m-ahb" 1014 clock-names = "m-ahb", "s-ahb";
1013 clocks = <&gcc GCC_QU 1015 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
1014 <&gcc GCC_QU 1016 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
1015 #address-cells = <2>; 1017 #address-cells = <2>;
1016 #size-cells = <2>; 1018 #size-cells = <2>;
1017 iommus = <&apps_smmu 1019 iommus = <&apps_smmu 0x63 0x0>;
1018 ranges; 1020 ranges;
1019 status = "disabled"; 1021 status = "disabled";
1020 1022
1021 i2c14: i2c@880000 { 1023 i2c14: i2c@880000 {
1022 compatible = 1024 compatible = "qcom,geni-i2c";
1023 reg = <0 0x00 1025 reg = <0 0x00880000 0 0x4000>;
1024 clock-names = 1026 clock-names = "se";
1025 clocks = <&gc 1027 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1026 pinctrl-names 1028 pinctrl-names = "default";
1027 pinctrl-0 = < 1029 pinctrl-0 = <&qup_i2c14_default>;
1028 interrupts = 1030 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1029 dmas = <&gpi_ 1031 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
1030 <&gpi_ 1032 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
1031 dma-names = " 1033 dma-names = "tx", "rx";
1032 power-domains 1034 power-domains = <&rpmhpd SM8250_CX>;
1033 interconnects 1035 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1034 1036 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1035 1037 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1036 interconnect- 1038 interconnect-names = "qup-core",
1037 1039 "qup-config",
1038 1040 "qup-memory";
1039 #address-cell 1041 #address-cells = <1>;
1040 #size-cells = 1042 #size-cells = <0>;
1041 status = "dis 1043 status = "disabled";
1042 }; 1044 };
1043 1045
1044 spi14: spi@880000 { 1046 spi14: spi@880000 {
1045 compatible = 1047 compatible = "qcom,geni-spi";
1046 reg = <0 0x00 1048 reg = <0 0x00880000 0 0x4000>;
1047 clock-names = 1049 clock-names = "se";
1048 clocks = <&gc 1050 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1049 interrupts = 1051 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1050 dmas = <&gpi_ 1052 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
1051 <&gpi_ 1053 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
1052 dma-names = " 1054 dma-names = "tx", "rx";
1053 power-domains 1055 power-domains = <&rpmhpd RPMHPD_CX>;
1054 operating-poi 1056 operating-points-v2 = <&qup_opp_table>;
1055 interconnects 1057 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1056 1058 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1057 1059 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1058 interconnect- 1060 interconnect-names = "qup-core",
1059 1061 "qup-config",
1060 1062 "qup-memory";
1061 #address-cell 1063 #address-cells = <1>;
1062 #size-cells = 1064 #size-cells = <0>;
1063 status = "dis 1065 status = "disabled";
1064 }; 1066 };
1065 1067
1066 i2c15: i2c@884000 { 1068 i2c15: i2c@884000 {
1067 compatible = 1069 compatible = "qcom,geni-i2c";
1068 reg = <0 0x00 1070 reg = <0 0x00884000 0 0x4000>;
1069 clock-names = 1071 clock-names = "se";
1070 clocks = <&gc 1072 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1071 pinctrl-names 1073 pinctrl-names = "default";
1072 pinctrl-0 = < 1074 pinctrl-0 = <&qup_i2c15_default>;
1073 interrupts = 1075 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1074 dmas = <&gpi_ 1076 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
1075 <&gpi_ 1077 <&gpi_dma2 1 1 QCOM_GPI_I2C>;
1076 dma-names = " 1078 dma-names = "tx", "rx";
1077 power-domains 1079 power-domains = <&rpmhpd SM8250_CX>;
1078 interconnects 1080 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1079 1081 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1080 1082 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1081 interconnect- 1083 interconnect-names = "qup-core",
1082 1084 "qup-config",
1083 1085 "qup-memory";
1084 #address-cell 1086 #address-cells = <1>;
1085 #size-cells = 1087 #size-cells = <0>;
1086 status = "dis 1088 status = "disabled";
1087 }; 1089 };
1088 1090
1089 spi15: spi@884000 { 1091 spi15: spi@884000 {
1090 compatible = 1092 compatible = "qcom,geni-spi";
1091 reg = <0 0x00 1093 reg = <0 0x00884000 0 0x4000>;
1092 clock-names = 1094 clock-names = "se";
1093 clocks = <&gc 1095 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1094 interrupts = 1096 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1095 dmas = <&gpi_ 1097 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
1096 <&gpi_ 1098 <&gpi_dma2 1 1 QCOM_GPI_SPI>;
1097 dma-names = " 1099 dma-names = "tx", "rx";
1098 power-domains 1100 power-domains = <&rpmhpd RPMHPD_CX>;
1099 operating-poi 1101 operating-points-v2 = <&qup_opp_table>;
1100 interconnects 1102 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1101 1103 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1102 1104 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1103 interconnect- 1105 interconnect-names = "qup-core",
1104 1106 "qup-config",
1105 1107 "qup-memory";
1106 #address-cell 1108 #address-cells = <1>;
1107 #size-cells = 1109 #size-cells = <0>;
1108 status = "dis 1110 status = "disabled";
1109 }; 1111 };
1110 1112
1111 i2c16: i2c@888000 { 1113 i2c16: i2c@888000 {
1112 compatible = 1114 compatible = "qcom,geni-i2c";
1113 reg = <0 0x00 1115 reg = <0 0x00888000 0 0x4000>;
1114 clock-names = 1116 clock-names = "se";
1115 clocks = <&gc 1117 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1116 pinctrl-names 1118 pinctrl-names = "default";
1117 pinctrl-0 = < 1119 pinctrl-0 = <&qup_i2c16_default>;
1118 interrupts = 1120 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1119 dmas = <&gpi_ 1121 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
1120 <&gpi_ 1122 <&gpi_dma2 1 2 QCOM_GPI_I2C>;
1121 dma-names = " 1123 dma-names = "tx", "rx";
1122 power-domains 1124 power-domains = <&rpmhpd SM8250_CX>;
1123 interconnects 1125 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1124 1126 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1125 1127 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1126 interconnect- 1128 interconnect-names = "qup-core",
1127 1129 "qup-config",
1128 1130 "qup-memory";
1129 #address-cell 1131 #address-cells = <1>;
1130 #size-cells = 1132 #size-cells = <0>;
1131 status = "dis 1133 status = "disabled";
1132 }; 1134 };
1133 1135
1134 spi16: spi@888000 { 1136 spi16: spi@888000 {
1135 compatible = 1137 compatible = "qcom,geni-spi";
1136 reg = <0 0x00 1138 reg = <0 0x00888000 0 0x4000>;
1137 clock-names = 1139 clock-names = "se";
1138 clocks = <&gc 1140 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1139 interrupts = 1141 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1140 dmas = <&gpi_ 1142 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
1141 <&gpi_ 1143 <&gpi_dma2 1 2 QCOM_GPI_SPI>;
1142 dma-names = " 1144 dma-names = "tx", "rx";
1143 power-domains 1145 power-domains = <&rpmhpd RPMHPD_CX>;
1144 operating-poi 1146 operating-points-v2 = <&qup_opp_table>;
1145 interconnects 1147 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1146 1148 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1147 1149 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1148 interconnect- 1150 interconnect-names = "qup-core",
1149 1151 "qup-config",
1150 1152 "qup-memory";
1151 #address-cell 1153 #address-cells = <1>;
1152 #size-cells = 1154 #size-cells = <0>;
1153 status = "dis 1155 status = "disabled";
1154 }; 1156 };
1155 1157
1156 i2c17: i2c@88c000 { 1158 i2c17: i2c@88c000 {
1157 compatible = 1159 compatible = "qcom,geni-i2c";
1158 reg = <0 0x00 1160 reg = <0 0x0088c000 0 0x4000>;
1159 clock-names = 1161 clock-names = "se";
1160 clocks = <&gc 1162 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1161 pinctrl-names 1163 pinctrl-names = "default";
1162 pinctrl-0 = < 1164 pinctrl-0 = <&qup_i2c17_default>;
1163 interrupts = 1165 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1164 dmas = <&gpi_ 1166 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
1165 <&gpi_ 1167 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
1166 dma-names = " 1168 dma-names = "tx", "rx";
1167 power-domains 1169 power-domains = <&rpmhpd SM8250_CX>;
1168 interconnects 1170 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1169 1171 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1170 1172 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1171 interconnect- 1173 interconnect-names = "qup-core",
1172 1174 "qup-config",
1173 1175 "qup-memory";
1174 #address-cell 1176 #address-cells = <1>;
1175 #size-cells = 1177 #size-cells = <0>;
1176 status = "dis 1178 status = "disabled";
1177 }; 1179 };
1178 1180
1179 spi17: spi@88c000 { 1181 spi17: spi@88c000 {
1180 compatible = 1182 compatible = "qcom,geni-spi";
1181 reg = <0 0x00 1183 reg = <0 0x0088c000 0 0x4000>;
1182 clock-names = 1184 clock-names = "se";
1183 clocks = <&gc 1185 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1184 interrupts = 1186 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1185 dmas = <&gpi_ 1187 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
1186 <&gpi_ 1188 <&gpi_dma2 1 3 QCOM_GPI_SPI>;
1187 dma-names = " 1189 dma-names = "tx", "rx";
1188 power-domains 1190 power-domains = <&rpmhpd RPMHPD_CX>;
1189 operating-poi 1191 operating-points-v2 = <&qup_opp_table>;
1190 interconnects 1192 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1191 1193 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1192 1194 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1193 interconnect- 1195 interconnect-names = "qup-core",
1194 1196 "qup-config",
1195 1197 "qup-memory";
1196 #address-cell 1198 #address-cells = <1>;
1197 #size-cells = 1199 #size-cells = <0>;
1198 status = "dis 1200 status = "disabled";
1199 }; 1201 };
1200 1202
1201 uart17: serial@88c000 1203 uart17: serial@88c000 {
1202 compatible = 1204 compatible = "qcom,geni-uart";
1203 reg = <0 0x00 1205 reg = <0 0x0088c000 0 0x4000>;
1204 clock-names = 1206 clock-names = "se";
1205 clocks = <&gc 1207 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1206 pinctrl-names 1208 pinctrl-names = "default";
1207 pinctrl-0 = < 1209 pinctrl-0 = <&qup_uart17_default>;
1208 interrupts = 1210 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1209 power-domains 1211 power-domains = <&rpmhpd RPMHPD_CX>;
1210 operating-poi 1212 operating-points-v2 = <&qup_opp_table>;
1211 interconnects 1213 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1212 1214 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1213 interconnect- 1215 interconnect-names = "qup-core",
1214 1216 "qup-config";
1215 status = "dis 1217 status = "disabled";
1216 }; 1218 };
1217 1219
1218 i2c18: i2c@890000 { 1220 i2c18: i2c@890000 {
1219 compatible = 1221 compatible = "qcom,geni-i2c";
1220 reg = <0 0x00 1222 reg = <0 0x00890000 0 0x4000>;
1221 clock-names = 1223 clock-names = "se";
1222 clocks = <&gc 1224 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1223 pinctrl-names 1225 pinctrl-names = "default";
1224 pinctrl-0 = < 1226 pinctrl-0 = <&qup_i2c18_default>;
1225 interrupts = 1227 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1226 dmas = <&gpi_ 1228 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1227 <&gpi_ 1229 <&gpi_dma2 1 4 QCOM_GPI_I2C>;
1228 dma-names = " 1230 dma-names = "tx", "rx";
1229 power-domains 1231 power-domains = <&rpmhpd SM8250_CX>;
1230 interconnects 1232 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1231 1233 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1232 1234 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1233 interconnect- 1235 interconnect-names = "qup-core",
1234 1236 "qup-config",
1235 1237 "qup-memory";
1236 #address-cell 1238 #address-cells = <1>;
1237 #size-cells = 1239 #size-cells = <0>;
1238 status = "dis 1240 status = "disabled";
1239 }; 1241 };
1240 1242
1241 spi18: spi@890000 { 1243 spi18: spi@890000 {
1242 compatible = 1244 compatible = "qcom,geni-spi";
1243 reg = <0 0x00 1245 reg = <0 0x00890000 0 0x4000>;
1244 clock-names = 1246 clock-names = "se";
1245 clocks = <&gc 1247 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1246 interrupts = 1248 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1247 dmas = <&gpi_ 1249 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
1248 <&gpi_ 1250 <&gpi_dma2 1 4 QCOM_GPI_SPI>;
1249 dma-names = " 1251 dma-names = "tx", "rx";
1250 power-domains 1252 power-domains = <&rpmhpd RPMHPD_CX>;
1251 operating-poi 1253 operating-points-v2 = <&qup_opp_table>;
1252 interconnects 1254 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1253 1255 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1254 1256 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1255 interconnect- 1257 interconnect-names = "qup-core",
1256 1258 "qup-config",
1257 1259 "qup-memory";
1258 #address-cell 1260 #address-cells = <1>;
1259 #size-cells = 1261 #size-cells = <0>;
1260 status = "dis 1262 status = "disabled";
1261 }; 1263 };
1262 1264
1263 uart18: serial@890000 1265 uart18: serial@890000 {
1264 compatible = 1266 compatible = "qcom,geni-uart";
1265 reg = <0 0x00 1267 reg = <0 0x00890000 0 0x4000>;
1266 clock-names = 1268 clock-names = "se";
1267 clocks = <&gc 1269 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1268 pinctrl-names 1270 pinctrl-names = "default";
1269 pinctrl-0 = < 1271 pinctrl-0 = <&qup_uart18_default>;
1270 interrupts = 1272 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1271 power-domains 1273 power-domains = <&rpmhpd RPMHPD_CX>;
1272 operating-poi 1274 operating-points-v2 = <&qup_opp_table>;
1273 interconnects 1275 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1274 1276 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1275 interconnect- 1277 interconnect-names = "qup-core",
1276 1278 "qup-config";
1277 status = "dis 1279 status = "disabled";
1278 }; 1280 };
1279 1281
1280 i2c19: i2c@894000 { 1282 i2c19: i2c@894000 {
1281 compatible = 1283 compatible = "qcom,geni-i2c";
1282 reg = <0 0x00 1284 reg = <0 0x00894000 0 0x4000>;
1283 clock-names = 1285 clock-names = "se";
1284 clocks = <&gc 1286 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1285 pinctrl-names 1287 pinctrl-names = "default";
1286 pinctrl-0 = < 1288 pinctrl-0 = <&qup_i2c19_default>;
1287 interrupts = 1289 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1288 dmas = <&gpi_ 1290 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1289 <&gpi_ 1291 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1290 dma-names = " 1292 dma-names = "tx", "rx";
1291 power-domains 1293 power-domains = <&rpmhpd SM8250_CX>;
1292 interconnects 1294 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1293 1295 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1294 1296 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1295 interconnect- 1297 interconnect-names = "qup-core",
1296 1298 "qup-config",
1297 1299 "qup-memory";
1298 #address-cell 1300 #address-cells = <1>;
1299 #size-cells = 1301 #size-cells = <0>;
1300 status = "dis 1302 status = "disabled";
1301 }; 1303 };
1302 1304
1303 spi19: spi@894000 { 1305 spi19: spi@894000 {
1304 compatible = 1306 compatible = "qcom,geni-spi";
1305 reg = <0 0x00 1307 reg = <0 0x00894000 0 0x4000>;
1306 clock-names = 1308 clock-names = "se";
1307 clocks = <&gc 1309 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1308 interrupts = 1310 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1309 dmas = <&gpi_ 1311 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1310 <&gpi_ 1312 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1311 dma-names = " 1313 dma-names = "tx", "rx";
1312 power-domains 1314 power-domains = <&rpmhpd RPMHPD_CX>;
1313 operating-poi 1315 operating-points-v2 = <&qup_opp_table>;
1314 interconnects 1316 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1315 1317 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1316 1318 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1317 interconnect- 1319 interconnect-names = "qup-core",
1318 1320 "qup-config",
1319 1321 "qup-memory";
1320 #address-cell 1322 #address-cells = <1>;
1321 #size-cells = 1323 #size-cells = <0>;
1322 status = "dis 1324 status = "disabled";
1323 }; 1325 };
1324 }; 1326 };
1325 1327
1326 gpi_dma0: dma-controller@9000 1328 gpi_dma0: dma-controller@900000 {
1327 compatible = "qcom,sm 1329 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma";
1328 reg = <0 0x00900000 0 1330 reg = <0 0x00900000 0 0x70000>;
1329 interrupts = <GIC_SPI 1331 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
1330 <GIC_SPI 1332 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
1331 <GIC_SPI 1333 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
1332 <GIC_SPI 1334 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
1333 <GIC_SPI 1335 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
1334 <GIC_SPI 1336 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
1335 <GIC_SPI 1337 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
1336 <GIC_SPI 1338 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
1337 <GIC_SPI 1339 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
1338 <GIC_SPI 1340 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
1339 <GIC_SPI 1341 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
1340 <GIC_SPI 1342 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
1341 <GIC_SPI 1343 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
1342 dma-channels = <15>; 1344 dma-channels = <15>;
1343 dma-channel-mask = <0 1345 dma-channel-mask = <0x7ff>;
1344 iommus = <&apps_smmu 1346 iommus = <&apps_smmu 0x5b6 0x0>;
1345 #dma-cells = <3>; 1347 #dma-cells = <3>;
1346 status = "disabled"; 1348 status = "disabled";
1347 }; 1349 };
1348 1350
1349 qupv3_id_0: geniqup@9c0000 { 1351 qupv3_id_0: geniqup@9c0000 {
1350 compatible = "qcom,ge 1352 compatible = "qcom,geni-se-qup";
1351 reg = <0x0 0x009c0000 1353 reg = <0x0 0x009c0000 0x0 0x6000>;
1352 clock-names = "m-ahb" 1354 clock-names = "m-ahb", "s-ahb";
1353 clocks = <&gcc GCC_QU 1355 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1354 <&gcc GCC_QU 1356 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1355 #address-cells = <2>; 1357 #address-cells = <2>;
1356 #size-cells = <2>; 1358 #size-cells = <2>;
1357 iommus = <&apps_smmu 1359 iommus = <&apps_smmu 0x5a3 0x0>;
1358 ranges; 1360 ranges;
1359 status = "disabled"; 1361 status = "disabled";
1360 1362
1361 i2c0: i2c@980000 { 1363 i2c0: i2c@980000 {
1362 compatible = 1364 compatible = "qcom,geni-i2c";
1363 reg = <0 0x00 1365 reg = <0 0x00980000 0 0x4000>;
1364 clock-names = 1366 clock-names = "se";
1365 clocks = <&gc 1367 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1366 pinctrl-names 1368 pinctrl-names = "default";
1367 pinctrl-0 = < 1369 pinctrl-0 = <&qup_i2c0_default>;
1368 interrupts = 1370 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1369 dmas = <&gpi_ 1371 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1370 <&gpi_ 1372 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1371 dma-names = " 1373 dma-names = "tx", "rx";
1372 power-domains 1374 power-domains = <&rpmhpd SM8250_CX>;
1373 interconnects 1375 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1374 1376 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1375 1377 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1376 interconnect- 1378 interconnect-names = "qup-core",
1377 1379 "qup-config",
1378 1380 "qup-memory";
1379 #address-cell 1381 #address-cells = <1>;
1380 #size-cells = 1382 #size-cells = <0>;
1381 status = "dis 1383 status = "disabled";
1382 }; 1384 };
1383 1385
1384 spi0: spi@980000 { 1386 spi0: spi@980000 {
1385 compatible = 1387 compatible = "qcom,geni-spi";
1386 reg = <0 0x00 1388 reg = <0 0x00980000 0 0x4000>;
1387 clock-names = 1389 clock-names = "se";
1388 clocks = <&gc 1390 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1389 interrupts = 1391 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1390 dmas = <&gpi_ 1392 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1391 <&gpi_ 1393 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1392 dma-names = " 1394 dma-names = "tx", "rx";
1393 power-domains 1395 power-domains = <&rpmhpd RPMHPD_CX>;
1394 operating-poi 1396 operating-points-v2 = <&qup_opp_table>;
1395 interconnects 1397 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1396 1398 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1397 1399 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1398 interconnect- 1400 interconnect-names = "qup-core",
1399 1401 "qup-config",
1400 1402 "qup-memory";
1401 #address-cell 1403 #address-cells = <1>;
1402 #size-cells = 1404 #size-cells = <0>;
1403 status = "dis 1405 status = "disabled";
1404 }; 1406 };
1405 1407
1406 i2c1: i2c@984000 { 1408 i2c1: i2c@984000 {
1407 compatible = 1409 compatible = "qcom,geni-i2c";
1408 reg = <0 0x00 1410 reg = <0 0x00984000 0 0x4000>;
1409 clock-names = 1411 clock-names = "se";
1410 clocks = <&gc 1412 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1411 pinctrl-names 1413 pinctrl-names = "default";
1412 pinctrl-0 = < 1414 pinctrl-0 = <&qup_i2c1_default>;
1413 interrupts = 1415 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1414 dmas = <&gpi_ 1416 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1415 <&gpi_ 1417 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1416 dma-names = " 1418 dma-names = "tx", "rx";
1417 power-domains 1419 power-domains = <&rpmhpd SM8250_CX>;
1418 interconnects 1420 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1419 1421 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1420 1422 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1421 interconnect- 1423 interconnect-names = "qup-core",
1422 1424 "qup-config",
1423 1425 "qup-memory";
1424 #address-cell 1426 #address-cells = <1>;
1425 #size-cells = 1427 #size-cells = <0>;
1426 status = "dis 1428 status = "disabled";
1427 }; 1429 };
1428 1430
1429 spi1: spi@984000 { 1431 spi1: spi@984000 {
1430 compatible = 1432 compatible = "qcom,geni-spi";
1431 reg = <0 0x00 1433 reg = <0 0x00984000 0 0x4000>;
1432 clock-names = 1434 clock-names = "se";
1433 clocks = <&gc 1435 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1434 interrupts = 1436 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1435 dmas = <&gpi_ 1437 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1436 <&gpi_ 1438 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1437 dma-names = " 1439 dma-names = "tx", "rx";
1438 power-domains 1440 power-domains = <&rpmhpd RPMHPD_CX>;
1439 operating-poi 1441 operating-points-v2 = <&qup_opp_table>;
1440 interconnects 1442 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1441 1443 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1442 1444 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1443 interconnect- 1445 interconnect-names = "qup-core",
1444 1446 "qup-config",
1445 1447 "qup-memory";
1446 #address-cell 1448 #address-cells = <1>;
1447 #size-cells = 1449 #size-cells = <0>;
1448 status = "dis 1450 status = "disabled";
1449 }; 1451 };
1450 1452
1451 i2c2: i2c@988000 { 1453 i2c2: i2c@988000 {
1452 compatible = 1454 compatible = "qcom,geni-i2c";
1453 reg = <0 0x00 1455 reg = <0 0x00988000 0 0x4000>;
1454 clock-names = 1456 clock-names = "se";
1455 clocks = <&gc 1457 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1456 pinctrl-names 1458 pinctrl-names = "default";
1457 pinctrl-0 = < 1459 pinctrl-0 = <&qup_i2c2_default>;
1458 interrupts = 1460 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1459 dmas = <&gpi_ 1461 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1460 <&gpi_ 1462 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1461 dma-names = " 1463 dma-names = "tx", "rx";
1462 power-domains 1464 power-domains = <&rpmhpd SM8250_CX>;
1463 interconnects 1465 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1464 1466 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1465 1467 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1466 interconnect- 1468 interconnect-names = "qup-core",
1467 1469 "qup-config",
1468 1470 "qup-memory";
1469 #address-cell 1471 #address-cells = <1>;
1470 #size-cells = 1472 #size-cells = <0>;
1471 status = "dis 1473 status = "disabled";
1472 }; 1474 };
1473 1475
1474 spi2: spi@988000 { 1476 spi2: spi@988000 {
1475 compatible = 1477 compatible = "qcom,geni-spi";
1476 reg = <0 0x00 1478 reg = <0 0x00988000 0 0x4000>;
1477 clock-names = 1479 clock-names = "se";
1478 clocks = <&gc 1480 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1479 interrupts = 1481 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1480 dmas = <&gpi_ 1482 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1481 <&gpi_ 1483 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1482 dma-names = " 1484 dma-names = "tx", "rx";
1483 power-domains 1485 power-domains = <&rpmhpd RPMHPD_CX>;
1484 operating-poi 1486 operating-points-v2 = <&qup_opp_table>;
1485 interconnects 1487 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1486 1488 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1487 1489 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1488 interconnect- 1490 interconnect-names = "qup-core",
1489 1491 "qup-config",
1490 1492 "qup-memory";
1491 #address-cell 1493 #address-cells = <1>;
1492 #size-cells = 1494 #size-cells = <0>;
1493 status = "dis 1495 status = "disabled";
1494 }; 1496 };
1495 1497
1496 uart2: serial@988000 1498 uart2: serial@988000 {
1497 compatible = 1499 compatible = "qcom,geni-debug-uart";
1498 reg = <0 0x00 1500 reg = <0 0x00988000 0 0x4000>;
1499 clock-names = 1501 clock-names = "se";
1500 clocks = <&gc 1502 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1501 pinctrl-names 1503 pinctrl-names = "default";
1502 pinctrl-0 = < 1504 pinctrl-0 = <&qup_uart2_default>;
1503 interrupts = 1505 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1504 power-domains 1506 power-domains = <&rpmhpd RPMHPD_CX>;
1505 operating-poi 1507 operating-points-v2 = <&qup_opp_table>;
1506 interconnects 1508 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1507 1509 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1508 interconnect- 1510 interconnect-names = "qup-core",
1509 1511 "qup-config";
1510 status = "dis 1512 status = "disabled";
1511 }; 1513 };
1512 1514
1513 i2c3: i2c@98c000 { 1515 i2c3: i2c@98c000 {
1514 compatible = 1516 compatible = "qcom,geni-i2c";
1515 reg = <0 0x00 1517 reg = <0 0x0098c000 0 0x4000>;
1516 clock-names = 1518 clock-names = "se";
1517 clocks = <&gc 1519 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1518 pinctrl-names 1520 pinctrl-names = "default";
1519 pinctrl-0 = < 1521 pinctrl-0 = <&qup_i2c3_default>;
1520 interrupts = 1522 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1521 dmas = <&gpi_ 1523 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1522 <&gpi_ 1524 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1523 dma-names = " 1525 dma-names = "tx", "rx";
1524 power-domains 1526 power-domains = <&rpmhpd SM8250_CX>;
1525 interconnects 1527 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1526 1528 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1527 1529 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1528 interconnect- 1530 interconnect-names = "qup-core",
1529 1531 "qup-config",
1530 1532 "qup-memory";
1531 #address-cell 1533 #address-cells = <1>;
1532 #size-cells = 1534 #size-cells = <0>;
1533 status = "dis 1535 status = "disabled";
1534 }; 1536 };
1535 1537
1536 spi3: spi@98c000 { 1538 spi3: spi@98c000 {
1537 compatible = 1539 compatible = "qcom,geni-spi";
1538 reg = <0 0x00 1540 reg = <0 0x0098c000 0 0x4000>;
1539 clock-names = 1541 clock-names = "se";
1540 clocks = <&gc 1542 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1541 interrupts = 1543 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1542 dmas = <&gpi_ 1544 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1543 <&gpi_ 1545 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1544 dma-names = " 1546 dma-names = "tx", "rx";
1545 power-domains 1547 power-domains = <&rpmhpd RPMHPD_CX>;
1546 operating-poi 1548 operating-points-v2 = <&qup_opp_table>;
1547 interconnects 1549 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1548 1550 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1549 1551 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1550 interconnect- 1552 interconnect-names = "qup-core",
1551 1553 "qup-config",
1552 1554 "qup-memory";
1553 #address-cell 1555 #address-cells = <1>;
1554 #size-cells = 1556 #size-cells = <0>;
1555 status = "dis 1557 status = "disabled";
1556 }; 1558 };
1557 1559
1558 i2c4: i2c@990000 { 1560 i2c4: i2c@990000 {
1559 compatible = 1561 compatible = "qcom,geni-i2c";
1560 reg = <0 0x00 1562 reg = <0 0x00990000 0 0x4000>;
1561 clock-names = 1563 clock-names = "se";
1562 clocks = <&gc 1564 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1563 pinctrl-names 1565 pinctrl-names = "default";
1564 pinctrl-0 = < 1566 pinctrl-0 = <&qup_i2c4_default>;
1565 interrupts = 1567 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1566 dmas = <&gpi_ 1568 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1567 <&gpi_ 1569 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1568 dma-names = " 1570 dma-names = "tx", "rx";
1569 power-domains 1571 power-domains = <&rpmhpd SM8250_CX>;
1570 interconnects 1572 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1571 1573 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1572 1574 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1573 interconnect- 1575 interconnect-names = "qup-core",
1574 1576 "qup-config",
1575 1577 "qup-memory";
1576 #address-cell 1578 #address-cells = <1>;
1577 #size-cells = 1579 #size-cells = <0>;
1578 status = "dis 1580 status = "disabled";
1579 }; 1581 };
1580 1582
1581 spi4: spi@990000 { 1583 spi4: spi@990000 {
1582 compatible = 1584 compatible = "qcom,geni-spi";
1583 reg = <0 0x00 1585 reg = <0 0x00990000 0 0x4000>;
1584 clock-names = 1586 clock-names = "se";
1585 clocks = <&gc 1587 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1586 interrupts = 1588 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1587 dmas = <&gpi_ 1589 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1588 <&gpi_ 1590 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1589 dma-names = " 1591 dma-names = "tx", "rx";
1590 power-domains 1592 power-domains = <&rpmhpd RPMHPD_CX>;
1591 operating-poi 1593 operating-points-v2 = <&qup_opp_table>;
1592 interconnects 1594 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1593 1595 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1594 1596 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1595 interconnect- 1597 interconnect-names = "qup-core",
1596 1598 "qup-config",
1597 1599 "qup-memory";
1598 #address-cell 1600 #address-cells = <1>;
1599 #size-cells = 1601 #size-cells = <0>;
1600 status = "dis 1602 status = "disabled";
1601 }; 1603 };
1602 1604
1603 i2c5: i2c@994000 { 1605 i2c5: i2c@994000 {
1604 compatible = 1606 compatible = "qcom,geni-i2c";
1605 reg = <0 0x00 1607 reg = <0 0x00994000 0 0x4000>;
1606 clock-names = 1608 clock-names = "se";
1607 clocks = <&gc 1609 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1608 pinctrl-names 1610 pinctrl-names = "default";
1609 pinctrl-0 = < 1611 pinctrl-0 = <&qup_i2c5_default>;
1610 interrupts = 1612 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1611 dmas = <&gpi_ 1613 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1612 <&gpi_ 1614 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1613 dma-names = " 1615 dma-names = "tx", "rx";
1614 power-domains 1616 power-domains = <&rpmhpd SM8250_CX>;
1615 interconnects 1617 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1616 1618 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1617 1619 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1618 interconnect- 1620 interconnect-names = "qup-core",
1619 1621 "qup-config",
1620 1622 "qup-memory";
1621 #address-cell 1623 #address-cells = <1>;
1622 #size-cells = 1624 #size-cells = <0>;
1623 status = "dis 1625 status = "disabled";
1624 }; 1626 };
1625 1627
1626 spi5: spi@994000 { 1628 spi5: spi@994000 {
1627 compatible = 1629 compatible = "qcom,geni-spi";
1628 reg = <0 0x00 1630 reg = <0 0x00994000 0 0x4000>;
1629 clock-names = 1631 clock-names = "se";
1630 clocks = <&gc 1632 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1631 interrupts = 1633 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1632 dmas = <&gpi_ 1634 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1633 <&gpi_ 1635 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1634 dma-names = " 1636 dma-names = "tx", "rx";
1635 power-domains 1637 power-domains = <&rpmhpd RPMHPD_CX>;
1636 operating-poi 1638 operating-points-v2 = <&qup_opp_table>;
1637 interconnects 1639 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1638 1640 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1639 1641 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1640 interconnect- 1642 interconnect-names = "qup-core",
1641 1643 "qup-config",
1642 1644 "qup-memory";
1643 #address-cell 1645 #address-cells = <1>;
1644 #size-cells = 1646 #size-cells = <0>;
1645 status = "dis 1647 status = "disabled";
1646 }; 1648 };
1647 1649
1648 i2c6: i2c@998000 { 1650 i2c6: i2c@998000 {
1649 compatible = 1651 compatible = "qcom,geni-i2c";
1650 reg = <0 0x00 1652 reg = <0 0x00998000 0 0x4000>;
1651 clock-names = 1653 clock-names = "se";
1652 clocks = <&gc 1654 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1653 pinctrl-names 1655 pinctrl-names = "default";
1654 pinctrl-0 = < 1656 pinctrl-0 = <&qup_i2c6_default>;
1655 interrupts = 1657 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1656 dmas = <&gpi_ 1658 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1657 <&gpi_ 1659 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1658 dma-names = " 1660 dma-names = "tx", "rx";
1659 power-domains 1661 power-domains = <&rpmhpd SM8250_CX>;
1660 interconnects 1662 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1661 1663 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1662 1664 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1663 interconnect- 1665 interconnect-names = "qup-core",
1664 1666 "qup-config",
1665 1667 "qup-memory";
1666 #address-cell 1668 #address-cells = <1>;
1667 #size-cells = 1669 #size-cells = <0>;
1668 status = "dis 1670 status = "disabled";
1669 }; 1671 };
1670 1672
1671 spi6: spi@998000 { 1673 spi6: spi@998000 {
1672 compatible = 1674 compatible = "qcom,geni-spi";
1673 reg = <0 0x00 1675 reg = <0 0x00998000 0 0x4000>;
1674 clock-names = 1676 clock-names = "se";
1675 clocks = <&gc 1677 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1676 interrupts = 1678 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1677 dmas = <&gpi_ 1679 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1678 <&gpi_ 1680 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1679 dma-names = " 1681 dma-names = "tx", "rx";
1680 power-domains 1682 power-domains = <&rpmhpd RPMHPD_CX>;
1681 operating-poi 1683 operating-points-v2 = <&qup_opp_table>;
1682 interconnects 1684 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1683 1685 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1684 1686 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1685 interconnect- 1687 interconnect-names = "qup-core",
1686 1688 "qup-config",
1687 1689 "qup-memory";
1688 #address-cell 1690 #address-cells = <1>;
1689 #size-cells = 1691 #size-cells = <0>;
1690 status = "dis 1692 status = "disabled";
1691 }; 1693 };
1692 1694
1693 uart6: serial@998000 1695 uart6: serial@998000 {
1694 compatible = 1696 compatible = "qcom,geni-uart";
1695 reg = <0 0x00 1697 reg = <0 0x00998000 0 0x4000>;
1696 clock-names = 1698 clock-names = "se";
1697 clocks = <&gc 1699 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1698 pinctrl-names 1700 pinctrl-names = "default";
1699 pinctrl-0 = < 1701 pinctrl-0 = <&qup_uart6_default>;
1700 interrupts = 1702 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1701 power-domains 1703 power-domains = <&rpmhpd RPMHPD_CX>;
1702 operating-poi 1704 operating-points-v2 = <&qup_opp_table>;
1703 interconnects 1705 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1704 1706 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1705 interconnect- 1707 interconnect-names = "qup-core",
1706 1708 "qup-config";
1707 status = "dis 1709 status = "disabled";
1708 }; 1710 };
1709 1711
1710 i2c7: i2c@99c000 { 1712 i2c7: i2c@99c000 {
1711 compatible = 1713 compatible = "qcom,geni-i2c";
1712 reg = <0 0x00 1714 reg = <0 0x0099c000 0 0x4000>;
1713 clock-names = 1715 clock-names = "se";
1714 clocks = <&gc 1716 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1715 pinctrl-names 1717 pinctrl-names = "default";
1716 pinctrl-0 = < 1718 pinctrl-0 = <&qup_i2c7_default>;
1717 interrupts = 1719 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1718 dmas = <&gpi_ 1720 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1719 <&gpi_ 1721 <&gpi_dma0 1 7 QCOM_GPI_I2C>;
1720 dma-names = " 1722 dma-names = "tx", "rx";
1721 power-domains 1723 power-domains = <&rpmhpd SM8250_CX>;
1722 interconnects 1724 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1723 1725 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1724 1726 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1725 interconnect- 1727 interconnect-names = "qup-core",
1726 1728 "qup-config",
1727 1729 "qup-memory";
1728 #address-cell 1730 #address-cells = <1>;
1729 #size-cells = 1731 #size-cells = <0>;
1730 status = "dis 1732 status = "disabled";
1731 }; 1733 };
1732 1734
1733 spi7: spi@99c000 { 1735 spi7: spi@99c000 {
1734 compatible = 1736 compatible = "qcom,geni-spi";
1735 reg = <0 0x00 1737 reg = <0 0x0099c000 0 0x4000>;
1736 clock-names = 1738 clock-names = "se";
1737 clocks = <&gc 1739 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1738 interrupts = 1740 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1739 dmas = <&gpi_ 1741 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1740 <&gpi_ 1742 <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1741 dma-names = " 1743 dma-names = "tx", "rx";
1742 power-domains 1744 power-domains = <&rpmhpd RPMHPD_CX>;
1743 operating-poi 1745 operating-points-v2 = <&qup_opp_table>;
1744 interconnects 1746 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1745 1747 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1746 1748 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1747 interconnect- 1749 interconnect-names = "qup-core",
1748 1750 "qup-config",
1749 1751 "qup-memory";
1750 #address-cell 1752 #address-cells = <1>;
1751 #size-cells = 1753 #size-cells = <0>;
1752 status = "dis 1754 status = "disabled";
1753 }; 1755 };
1754 }; 1756 };
1755 1757
1756 gpi_dma1: dma-controller@a000 1758 gpi_dma1: dma-controller@a00000 {
1757 compatible = "qcom,sm 1759 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma";
1758 reg = <0 0x00a00000 0 1760 reg = <0 0x00a00000 0 0x70000>;
1759 interrupts = <GIC_SPI 1761 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1760 <GIC_SPI 1762 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1761 <GIC_SPI 1763 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1762 <GIC_SPI 1764 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1763 <GIC_SPI 1765 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1764 <GIC_SPI 1766 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1765 <GIC_SPI 1767 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1766 <GIC_SPI 1768 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1767 <GIC_SPI 1769 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1768 <GIC_SPI 1770 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>;
1769 dma-channels = <10>; 1771 dma-channels = <10>;
1770 dma-channel-mask = <0 1772 dma-channel-mask = <0x3f>;
1771 iommus = <&apps_smmu 1773 iommus = <&apps_smmu 0x56 0x0>;
1772 #dma-cells = <3>; 1774 #dma-cells = <3>;
1773 status = "disabled"; 1775 status = "disabled";
1774 }; 1776 };
1775 1777
1776 qupv3_id_1: geniqup@ac0000 { 1778 qupv3_id_1: geniqup@ac0000 {
1777 compatible = "qcom,ge 1779 compatible = "qcom,geni-se-qup";
1778 reg = <0x0 0x00ac0000 1780 reg = <0x0 0x00ac0000 0x0 0x6000>;
1779 clock-names = "m-ahb" 1781 clock-names = "m-ahb", "s-ahb";
1780 clocks = <&gcc GCC_QU 1782 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1781 <&gcc GCC_QU 1783 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1782 #address-cells = <2>; 1784 #address-cells = <2>;
1783 #size-cells = <2>; 1785 #size-cells = <2>;
1784 iommus = <&apps_smmu 1786 iommus = <&apps_smmu 0x43 0x0>;
1785 ranges; 1787 ranges;
1786 status = "disabled"; 1788 status = "disabled";
1787 1789
1788 i2c8: i2c@a80000 { 1790 i2c8: i2c@a80000 {
1789 compatible = 1791 compatible = "qcom,geni-i2c";
1790 reg = <0 0x00 1792 reg = <0 0x00a80000 0 0x4000>;
1791 clock-names = 1793 clock-names = "se";
1792 clocks = <&gc 1794 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1793 pinctrl-names 1795 pinctrl-names = "default";
1794 pinctrl-0 = < 1796 pinctrl-0 = <&qup_i2c8_default>;
1795 interrupts = 1797 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1796 dmas = <&gpi_ 1798 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1797 <&gpi_ 1799 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1798 dma-names = " 1800 dma-names = "tx", "rx";
1799 power-domains 1801 power-domains = <&rpmhpd SM8250_CX>;
1800 interconnects 1802 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1801 1803 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1802 1804 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1803 interconnect- 1805 interconnect-names = "qup-core",
1804 1806 "qup-config",
1805 1807 "qup-memory";
1806 #address-cell 1808 #address-cells = <1>;
1807 #size-cells = 1809 #size-cells = <0>;
1808 status = "dis 1810 status = "disabled";
1809 }; 1811 };
1810 1812
1811 spi8: spi@a80000 { 1813 spi8: spi@a80000 {
1812 compatible = 1814 compatible = "qcom,geni-spi";
1813 reg = <0 0x00 1815 reg = <0 0x00a80000 0 0x4000>;
1814 clock-names = 1816 clock-names = "se";
1815 clocks = <&gc 1817 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1816 interrupts = 1818 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1817 dmas = <&gpi_ 1819 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1818 <&gpi_ 1820 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1819 dma-names = " 1821 dma-names = "tx", "rx";
1820 power-domains 1822 power-domains = <&rpmhpd RPMHPD_CX>;
1821 operating-poi 1823 operating-points-v2 = <&qup_opp_table>;
1822 interconnects 1824 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1823 1825 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1824 1826 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1825 interconnect- 1827 interconnect-names = "qup-core",
1826 1828 "qup-config",
1827 1829 "qup-memory";
1828 #address-cell 1830 #address-cells = <1>;
1829 #size-cells = 1831 #size-cells = <0>;
1830 status = "dis 1832 status = "disabled";
1831 }; 1833 };
1832 1834
1833 i2c9: i2c@a84000 { 1835 i2c9: i2c@a84000 {
1834 compatible = 1836 compatible = "qcom,geni-i2c";
1835 reg = <0 0x00 1837 reg = <0 0x00a84000 0 0x4000>;
1836 clock-names = 1838 clock-names = "se";
1837 clocks = <&gc 1839 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1838 pinctrl-names 1840 pinctrl-names = "default";
1839 pinctrl-0 = < 1841 pinctrl-0 = <&qup_i2c9_default>;
1840 interrupts = 1842 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1841 dmas = <&gpi_ 1843 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1842 <&gpi_ 1844 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1843 dma-names = " 1845 dma-names = "tx", "rx";
1844 power-domains 1846 power-domains = <&rpmhpd SM8250_CX>;
1845 interconnects 1847 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1846 1848 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1847 1849 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1848 interconnect- 1850 interconnect-names = "qup-core",
1849 1851 "qup-config",
1850 1852 "qup-memory";
1851 #address-cell 1853 #address-cells = <1>;
1852 #size-cells = 1854 #size-cells = <0>;
1853 status = "dis 1855 status = "disabled";
1854 }; 1856 };
1855 1857
1856 spi9: spi@a84000 { 1858 spi9: spi@a84000 {
1857 compatible = 1859 compatible = "qcom,geni-spi";
1858 reg = <0 0x00 1860 reg = <0 0x00a84000 0 0x4000>;
1859 clock-names = 1861 clock-names = "se";
1860 clocks = <&gc 1862 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1861 interrupts = 1863 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1862 dmas = <&gpi_ 1864 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1863 <&gpi_ 1865 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1864 dma-names = " 1866 dma-names = "tx", "rx";
1865 power-domains 1867 power-domains = <&rpmhpd RPMHPD_CX>;
1866 operating-poi 1868 operating-points-v2 = <&qup_opp_table>;
1867 interconnects 1869 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1868 1870 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1869 1871 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1870 interconnect- 1872 interconnect-names = "qup-core",
1871 1873 "qup-config",
1872 1874 "qup-memory";
1873 #address-cell 1875 #address-cells = <1>;
1874 #size-cells = 1876 #size-cells = <0>;
1875 status = "dis 1877 status = "disabled";
1876 }; 1878 };
1877 1879
1878 i2c10: i2c@a88000 { 1880 i2c10: i2c@a88000 {
1879 compatible = 1881 compatible = "qcom,geni-i2c";
1880 reg = <0 0x00 1882 reg = <0 0x00a88000 0 0x4000>;
1881 clock-names = 1883 clock-names = "se";
1882 clocks = <&gc 1884 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1883 pinctrl-names 1885 pinctrl-names = "default";
1884 pinctrl-0 = < 1886 pinctrl-0 = <&qup_i2c10_default>;
1885 interrupts = 1887 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1886 dmas = <&gpi_ 1888 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1887 <&gpi_ 1889 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1888 dma-names = " 1890 dma-names = "tx", "rx";
1889 power-domains 1891 power-domains = <&rpmhpd SM8250_CX>;
1890 interconnects 1892 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1891 1893 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1892 1894 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1893 interconnect- 1895 interconnect-names = "qup-core",
1894 1896 "qup-config",
1895 1897 "qup-memory";
1896 #address-cell 1898 #address-cells = <1>;
1897 #size-cells = 1899 #size-cells = <0>;
1898 status = "dis 1900 status = "disabled";
1899 }; 1901 };
1900 1902
1901 spi10: spi@a88000 { 1903 spi10: spi@a88000 {
1902 compatible = 1904 compatible = "qcom,geni-spi";
1903 reg = <0 0x00 1905 reg = <0 0x00a88000 0 0x4000>;
1904 clock-names = 1906 clock-names = "se";
1905 clocks = <&gc 1907 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1906 interrupts = 1908 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1907 dmas = <&gpi_ 1909 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1908 <&gpi_ 1910 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1909 dma-names = " 1911 dma-names = "tx", "rx";
1910 power-domains 1912 power-domains = <&rpmhpd RPMHPD_CX>;
1911 operating-poi 1913 operating-points-v2 = <&qup_opp_table>;
1912 interconnects 1914 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1913 1915 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1914 1916 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1915 interconnect- 1917 interconnect-names = "qup-core",
1916 1918 "qup-config",
1917 1919 "qup-memory";
1918 #address-cell 1920 #address-cells = <1>;
1919 #size-cells = 1921 #size-cells = <0>;
1920 status = "dis 1922 status = "disabled";
1921 }; 1923 };
1922 1924
1923 i2c11: i2c@a8c000 { 1925 i2c11: i2c@a8c000 {
1924 compatible = 1926 compatible = "qcom,geni-i2c";
1925 reg = <0 0x00 1927 reg = <0 0x00a8c000 0 0x4000>;
1926 clock-names = 1928 clock-names = "se";
1927 clocks = <&gc 1929 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1928 pinctrl-names 1930 pinctrl-names = "default";
1929 pinctrl-0 = < 1931 pinctrl-0 = <&qup_i2c11_default>;
1930 interrupts = 1932 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1931 dmas = <&gpi_ 1933 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1932 <&gpi_ 1934 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1933 dma-names = " 1935 dma-names = "tx", "rx";
1934 power-domains 1936 power-domains = <&rpmhpd SM8250_CX>;
1935 interconnects 1937 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1936 1938 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1937 1939 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1938 interconnect- 1940 interconnect-names = "qup-core",
1939 1941 "qup-config",
1940 1942 "qup-memory";
1941 #address-cell 1943 #address-cells = <1>;
1942 #size-cells = 1944 #size-cells = <0>;
1943 status = "dis 1945 status = "disabled";
1944 }; 1946 };
1945 1947
1946 spi11: spi@a8c000 { 1948 spi11: spi@a8c000 {
1947 compatible = 1949 compatible = "qcom,geni-spi";
1948 reg = <0 0x00 1950 reg = <0 0x00a8c000 0 0x4000>;
1949 clock-names = 1951 clock-names = "se";
1950 clocks = <&gc 1952 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1951 interrupts = 1953 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1952 dmas = <&gpi_ 1954 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1953 <&gpi_ 1955 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1954 dma-names = " 1956 dma-names = "tx", "rx";
1955 power-domains 1957 power-domains = <&rpmhpd RPMHPD_CX>;
1956 operating-poi 1958 operating-points-v2 = <&qup_opp_table>;
1957 interconnects 1959 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1958 1960 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1959 1961 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1960 interconnect- 1962 interconnect-names = "qup-core",
1961 1963 "qup-config",
1962 1964 "qup-memory";
1963 #address-cell 1965 #address-cells = <1>;
1964 #size-cells = 1966 #size-cells = <0>;
1965 status = "dis 1967 status = "disabled";
1966 }; 1968 };
1967 1969
1968 i2c12: i2c@a90000 { 1970 i2c12: i2c@a90000 {
1969 compatible = 1971 compatible = "qcom,geni-i2c";
1970 reg = <0 0x00 1972 reg = <0 0x00a90000 0 0x4000>;
1971 clock-names = 1973 clock-names = "se";
1972 clocks = <&gc 1974 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1973 pinctrl-names 1975 pinctrl-names = "default";
1974 pinctrl-0 = < 1976 pinctrl-0 = <&qup_i2c12_default>;
1975 interrupts = 1977 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1976 dmas = <&gpi_ 1978 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1977 <&gpi_ 1979 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1978 dma-names = " 1980 dma-names = "tx", "rx";
1979 power-domains 1981 power-domains = <&rpmhpd SM8250_CX>;
1980 interconnects 1982 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1981 1983 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1982 1984 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1983 interconnect- 1985 interconnect-names = "qup-core",
1984 1986 "qup-config",
1985 1987 "qup-memory";
1986 #address-cell 1988 #address-cells = <1>;
1987 #size-cells = 1989 #size-cells = <0>;
1988 status = "dis 1990 status = "disabled";
1989 }; 1991 };
1990 1992
1991 spi12: spi@a90000 { 1993 spi12: spi@a90000 {
1992 compatible = 1994 compatible = "qcom,geni-spi";
1993 reg = <0 0x00 1995 reg = <0 0x00a90000 0 0x4000>;
1994 clock-names = 1996 clock-names = "se";
1995 clocks = <&gc 1997 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1996 interrupts = 1998 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1997 dmas = <&gpi_ 1999 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1998 <&gpi_ 2000 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1999 dma-names = " 2001 dma-names = "tx", "rx";
2000 power-domains 2002 power-domains = <&rpmhpd RPMHPD_CX>;
2001 operating-poi 2003 operating-points-v2 = <&qup_opp_table>;
2002 interconnects 2004 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
2003 2005 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
2004 2006 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
2005 interconnect- 2007 interconnect-names = "qup-core",
2006 2008 "qup-config",
2007 2009 "qup-memory";
2008 #address-cell 2010 #address-cells = <1>;
2009 #size-cells = 2011 #size-cells = <0>;
2010 status = "dis 2012 status = "disabled";
2011 }; 2013 };
2012 2014
2013 uart12: serial@a90000 2015 uart12: serial@a90000 {
2014 compatible = 2016 compatible = "qcom,geni-debug-uart";
2015 reg = <0x0 0x 2017 reg = <0x0 0x00a90000 0x0 0x4000>;
2016 clock-names = 2018 clock-names = "se";
2017 clocks = <&gc 2019 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
2018 pinctrl-names 2020 pinctrl-names = "default";
2019 pinctrl-0 = < 2021 pinctrl-0 = <&qup_uart12_default>;
2020 interrupts = 2022 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
2021 power-domains 2023 power-domains = <&rpmhpd RPMHPD_CX>;
2022 operating-poi 2024 operating-points-v2 = <&qup_opp_table>;
2023 interconnects 2025 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
2024 2026 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
2025 interconnect- 2027 interconnect-names = "qup-core",
2026 2028 "qup-config";
2027 status = "dis 2029 status = "disabled";
2028 }; 2030 };
2029 2031
2030 i2c13: i2c@a94000 { 2032 i2c13: i2c@a94000 {
2031 compatible = 2033 compatible = "qcom,geni-i2c";
2032 reg = <0 0x00 2034 reg = <0 0x00a94000 0 0x4000>;
2033 clock-names = 2035 clock-names = "se";
2034 clocks = <&gc 2036 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2035 pinctrl-names 2037 pinctrl-names = "default";
2036 pinctrl-0 = < 2038 pinctrl-0 = <&qup_i2c13_default>;
2037 interrupts = 2039 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2038 dmas = <&gpi_ 2040 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
2039 <&gpi_ 2041 <&gpi_dma1 1 5 QCOM_GPI_I2C>;
2040 dma-names = " 2042 dma-names = "tx", "rx";
2041 power-domains 2043 power-domains = <&rpmhpd SM8250_CX>;
2042 interconnects 2044 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
2043 2045 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
2044 2046 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
2045 interconnect- 2047 interconnect-names = "qup-core",
2046 2048 "qup-config",
2047 2049 "qup-memory";
2048 #address-cell 2050 #address-cells = <1>;
2049 #size-cells = 2051 #size-cells = <0>;
2050 status = "dis 2052 status = "disabled";
2051 }; 2053 };
2052 2054
2053 spi13: spi@a94000 { 2055 spi13: spi@a94000 {
2054 compatible = 2056 compatible = "qcom,geni-spi";
2055 reg = <0 0x00 2057 reg = <0 0x00a94000 0 0x4000>;
2056 clock-names = 2058 clock-names = "se";
2057 clocks = <&gc 2059 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2058 interrupts = 2060 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2059 dmas = <&gpi_ 2061 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
2060 <&gpi_ 2062 <&gpi_dma1 1 5 QCOM_GPI_SPI>;
2061 dma-names = " 2063 dma-names = "tx", "rx";
2062 power-domains 2064 power-domains = <&rpmhpd RPMHPD_CX>;
2063 operating-poi 2065 operating-points-v2 = <&qup_opp_table>;
2064 interconnects 2066 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
2065 2067 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
2066 2068 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
2067 interconnect- 2069 interconnect-names = "qup-core",
2068 2070 "qup-config",
2069 2071 "qup-memory";
2070 #address-cell 2072 #address-cells = <1>;
2071 #size-cells = 2073 #size-cells = <0>;
2072 status = "dis 2074 status = "disabled";
2073 }; 2075 };
2074 }; 2076 };
2075 2077
2076 config_noc: interconnect@1500 2078 config_noc: interconnect@1500000 {
2077 compatible = "qcom,sm 2079 compatible = "qcom,sm8250-config-noc";
2078 reg = <0 0x01500000 0 2080 reg = <0 0x01500000 0 0xa580>;
2079 #interconnect-cells = 2081 #interconnect-cells = <2>;
2080 qcom,bcm-voters = <&a 2082 qcom,bcm-voters = <&apps_bcm_voter>;
2081 }; 2083 };
2082 2084
2083 system_noc: interconnect@1620 2085 system_noc: interconnect@1620000 {
2084 compatible = "qcom,sm 2086 compatible = "qcom,sm8250-system-noc";
2085 reg = <0 0x01620000 0 2087 reg = <0 0x01620000 0 0x1c200>;
2086 #interconnect-cells = 2088 #interconnect-cells = <2>;
2087 qcom,bcm-voters = <&a 2089 qcom,bcm-voters = <&apps_bcm_voter>;
2088 }; 2090 };
2089 2091
2090 mc_virt: interconnect@163d000 2092 mc_virt: interconnect@163d000 {
2091 compatible = "qcom,sm 2093 compatible = "qcom,sm8250-mc-virt";
2092 reg = <0 0x0163d000 0 2094 reg = <0 0x0163d000 0 0x1000>;
2093 #interconnect-cells = 2095 #interconnect-cells = <2>;
2094 qcom,bcm-voters = <&a 2096 qcom,bcm-voters = <&apps_bcm_voter>;
2095 }; 2097 };
2096 2098
2097 aggre1_noc: interconnect@16e0 2099 aggre1_noc: interconnect@16e0000 {
2098 compatible = "qcom,sm 2100 compatible = "qcom,sm8250-aggre1-noc";
2099 reg = <0 0x016e0000 0 2101 reg = <0 0x016e0000 0 0x1f180>;
2100 #interconnect-cells = 2102 #interconnect-cells = <2>;
2101 qcom,bcm-voters = <&a 2103 qcom,bcm-voters = <&apps_bcm_voter>;
2102 }; 2104 };
2103 2105
2104 aggre2_noc: interconnect@1700 2106 aggre2_noc: interconnect@1700000 {
2105 compatible = "qcom,sm 2107 compatible = "qcom,sm8250-aggre2-noc";
2106 reg = <0 0x01700000 0 2108 reg = <0 0x01700000 0 0x33000>;
2107 #interconnect-cells = 2109 #interconnect-cells = <2>;
2108 qcom,bcm-voters = <&a 2110 qcom,bcm-voters = <&apps_bcm_voter>;
2109 }; 2111 };
2110 2112
2111 compute_noc: interconnect@173 2113 compute_noc: interconnect@1733000 {
2112 compatible = "qcom,sm 2114 compatible = "qcom,sm8250-compute-noc";
2113 reg = <0 0x01733000 0 2115 reg = <0 0x01733000 0 0xa180>;
2114 #interconnect-cells = 2116 #interconnect-cells = <2>;
2115 qcom,bcm-voters = <&a 2117 qcom,bcm-voters = <&apps_bcm_voter>;
2116 }; 2118 };
2117 2119
2118 mmss_noc: interconnect@174000 2120 mmss_noc: interconnect@1740000 {
2119 compatible = "qcom,sm 2121 compatible = "qcom,sm8250-mmss-noc";
2120 reg = <0 0x01740000 0 2122 reg = <0 0x01740000 0 0x1f080>;
2121 #interconnect-cells = 2123 #interconnect-cells = <2>;
2122 qcom,bcm-voters = <&a 2124 qcom,bcm-voters = <&apps_bcm_voter>;
2123 }; 2125 };
2124 2126
2125 pcie0: pcie@1c00000 { 2127 pcie0: pcie@1c00000 {
2126 compatible = "qcom,pc 2128 compatible = "qcom,pcie-sm8250";
2127 reg = <0 0x01c00000 0 2129 reg = <0 0x01c00000 0 0x3000>,
2128 <0 0x60000000 0 2130 <0 0x60000000 0 0xf1d>,
2129 <0 0x60000f20 0 2131 <0 0x60000f20 0 0xa8>,
2130 <0 0x60001000 0 2132 <0 0x60001000 0 0x1000>,
2131 <0 0x60100000 0 2133 <0 0x60100000 0 0x100000>,
2132 <0 0x01c03000 0 2134 <0 0x01c03000 0 0x1000>;
2133 reg-names = "parf", " 2135 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2134 device_type = "pci"; 2136 device_type = "pci";
2135 linux,pci-domain = <0 2137 linux,pci-domain = <0>;
2136 bus-range = <0x00 0xf 2138 bus-range = <0x00 0xff>;
2137 num-lanes = <1>; 2139 num-lanes = <1>;
2138 2140
2139 #address-cells = <3>; 2141 #address-cells = <3>;
2140 #size-cells = <2>; 2142 #size-cells = <2>;
2141 2143
2142 ranges = <0x01000000 2144 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
2143 <0x02000000 2145 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
2144 2146
2145 interrupts = <GIC_SPI 2147 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
2146 <GIC_SPI 2148 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
2147 <GIC_SPI 2149 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
2148 <GIC_SPI 2150 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
2149 <GIC_SPI 2151 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
2150 <GIC_SPI 2152 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
2151 <GIC_SPI 2153 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
2152 <GIC_SPI 2154 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2153 interrupt-names = "ms 2155 interrupt-names = "msi0",
2154 "ms 2156 "msi1",
2155 "ms 2157 "msi2",
2156 "ms 2158 "msi3",
2157 "ms 2159 "msi4",
2158 "ms 2160 "msi5",
2159 "ms 2161 "msi6",
2160 "ms 2162 "msi7";
2161 #interrupt-cells = <1 2163 #interrupt-cells = <1>;
2162 interrupt-map-mask = 2164 interrupt-map-mask = <0 0 0 0x7>;
2163 interrupt-map = <0 0 2165 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2164 <0 0 2166 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2165 <0 0 2167 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2166 <0 0 2168 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2167 2169
2168 clocks = <&gcc GCC_PC 2170 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
2169 <&gcc GCC_PC 2171 <&gcc GCC_PCIE_0_AUX_CLK>,
2170 <&gcc GCC_PC 2172 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2171 <&gcc GCC_PC 2173 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
2172 <&gcc GCC_PC 2174 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
2173 <&gcc GCC_PC 2175 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
2174 <&gcc GCC_AG 2176 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
2175 <&gcc GCC_DD 2177 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
2176 clock-names = "pipe", 2178 clock-names = "pipe",
2177 "aux", 2179 "aux",
2178 "cfg", 2180 "cfg",
2179 "bus_ma 2181 "bus_master",
2180 "bus_sl 2182 "bus_slave",
2181 "slave_ 2183 "slave_q2a",
2182 "tbu", 2184 "tbu",
2183 "ddrss_ 2185 "ddrss_sf_tbu";
2184 2186
2185 iommu-map = <0x0 &a 2187 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
2186 <0x100 &a 2188 <0x100 &apps_smmu 0x1c01 0x1>;
2187 2189
2188 resets = <&gcc GCC_PC 2190 resets = <&gcc GCC_PCIE_0_BCR>;
2189 reset-names = "pci"; 2191 reset-names = "pci";
2190 2192
2191 power-domains = <&gcc 2193 power-domains = <&gcc PCIE_0_GDSC>;
2192 2194
2193 phys = <&pcie0_phy>; 2195 phys = <&pcie0_phy>;
2194 phy-names = "pciephy" 2196 phy-names = "pciephy";
2195 2197
2196 perst-gpios = <&tlmm 2198 perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>;
2197 wake-gpios = <&tlmm 8 2199 wake-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
2198 2200
2199 pinctrl-names = "defa 2201 pinctrl-names = "default";
2200 pinctrl-0 = <&pcie0_d 2202 pinctrl-0 = <&pcie0_default_state>;
2201 dma-coherent; 2203 dma-coherent;
2202 2204
2203 status = "disabled"; 2205 status = "disabled";
2204 <<
2205 pcieport0: pcie@0 { <<
2206 device_type = <<
2207 reg = <0x0 0x <<
2208 bus-range = < <<
2209 <<
2210 #address-cell <<
2211 #size-cells = <<
2212 ranges; <<
2213 }; <<
2214 }; 2206 };
2215 2207
2216 pcie0_phy: phy@1c06000 { 2208 pcie0_phy: phy@1c06000 {
2217 compatible = "qcom,sm 2209 compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy";
2218 reg = <0 0x01c06000 0 2210 reg = <0 0x01c06000 0 0x1000>;
2219 2211
2220 clocks = <&gcc GCC_PC 2212 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2221 <&gcc GCC_PC 2213 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2222 <&gcc GCC_PC 2214 <&gcc GCC_PCIE_WIFI_CLKREF_EN>,
2223 <&gcc GCC_PC 2215 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>,
2224 <&gcc GCC_PC 2216 <&gcc GCC_PCIE_0_PIPE_CLK>;
2225 clock-names = "aux", 2217 clock-names = "aux",
2226 "cfg_ah 2218 "cfg_ahb",
2227 "ref", 2219 "ref",
2228 "refgen 2220 "refgen",
2229 "pipe"; 2221 "pipe";
2230 2222
2231 clock-output-names = 2223 clock-output-names = "pcie_0_pipe_clk";
2232 #clock-cells = <0>; 2224 #clock-cells = <0>;
2233 2225
2234 #phy-cells = <0>; 2226 #phy-cells = <0>;
2235 2227
2236 resets = <&gcc GCC_PC 2228 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
2237 reset-names = "phy"; 2229 reset-names = "phy";
2238 2230
2239 assigned-clocks = <&g 2231 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
2240 assigned-clock-rates 2232 assigned-clock-rates = <100000000>;
2241 2233
2242 status = "disabled"; 2234 status = "disabled";
2243 }; 2235 };
2244 2236
2245 pcie1: pcie@1c08000 { 2237 pcie1: pcie@1c08000 {
2246 compatible = "qcom,pc 2238 compatible = "qcom,pcie-sm8250";
2247 reg = <0 0x01c08000 0 2239 reg = <0 0x01c08000 0 0x3000>,
2248 <0 0x40000000 0 2240 <0 0x40000000 0 0xf1d>,
2249 <0 0x40000f20 0 2241 <0 0x40000f20 0 0xa8>,
2250 <0 0x40001000 0 2242 <0 0x40001000 0 0x1000>,
2251 <0 0x40100000 0 2243 <0 0x40100000 0 0x100000>,
2252 <0 0x01c0b000 0 2244 <0 0x01c0b000 0 0x1000>;
2253 reg-names = "parf", " 2245 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2254 device_type = "pci"; 2246 device_type = "pci";
2255 linux,pci-domain = <1 2247 linux,pci-domain = <1>;
2256 bus-range = <0x00 0xf 2248 bus-range = <0x00 0xff>;
2257 num-lanes = <2>; 2249 num-lanes = <2>;
2258 2250
2259 #address-cells = <3>; 2251 #address-cells = <3>;
2260 #size-cells = <2>; 2252 #size-cells = <2>;
2261 2253
2262 ranges = <0x01000000 2254 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
2263 <0x02000000 2255 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
2264 2256
2265 interrupts = <GIC_SPI 2257 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
2266 <GIC_SPI 2258 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
2267 <GIC_SPI 2259 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
2268 <GIC_SPI 2260 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
2269 <GIC_SPI 2261 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
2270 <GIC_SPI 2262 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
2271 <GIC_SPI 2263 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
2272 <GIC_SPI 2264 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
2273 interrupt-names = "ms 2265 interrupt-names = "msi0",
2274 "ms 2266 "msi1",
2275 "ms 2267 "msi2",
2276 "ms 2268 "msi3",
2277 "ms 2269 "msi4",
2278 "ms 2270 "msi5",
2279 "ms 2271 "msi6",
2280 "ms 2272 "msi7";
2281 #interrupt-cells = <1 2273 #interrupt-cells = <1>;
2282 interrupt-map-mask = 2274 interrupt-map-mask = <0 0 0 0x7>;
2283 interrupt-map = <0 0 2275 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2284 <0 0 2276 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2285 <0 0 2277 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2286 <0 0 2278 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2287 2279
2288 clocks = <&gcc GCC_PC 2280 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
2289 <&gcc GCC_PC 2281 <&gcc GCC_PCIE_1_AUX_CLK>,
2290 <&gcc GCC_PC 2282 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2291 <&gcc GCC_PC 2283 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
2292 <&gcc GCC_PC 2284 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
2293 <&gcc GCC_PC 2285 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
2294 <&gcc GCC_PC 2286 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
2295 <&gcc GCC_AG 2287 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
2296 <&gcc GCC_DD 2288 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
2297 clock-names = "pipe", 2289 clock-names = "pipe",
2298 "aux", 2290 "aux",
2299 "cfg", 2291 "cfg",
2300 "bus_ma 2292 "bus_master",
2301 "bus_sl 2293 "bus_slave",
2302 "slave_ 2294 "slave_q2a",
2303 "ref", 2295 "ref",
2304 "tbu", 2296 "tbu",
2305 "ddrss_ 2297 "ddrss_sf_tbu";
2306 2298
2307 assigned-clocks = <&g 2299 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2308 assigned-clock-rates 2300 assigned-clock-rates = <19200000>;
2309 2301
2310 iommu-map = <0x0 &a 2302 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
2311 <0x100 &a 2303 <0x100 &apps_smmu 0x1c81 0x1>;
2312 2304
2313 resets = <&gcc GCC_PC 2305 resets = <&gcc GCC_PCIE_1_BCR>;
2314 reset-names = "pci"; 2306 reset-names = "pci";
2315 2307
2316 power-domains = <&gcc 2308 power-domains = <&gcc PCIE_1_GDSC>;
2317 2309
2318 phys = <&pcie1_phy>; 2310 phys = <&pcie1_phy>;
2319 phy-names = "pciephy" 2311 phy-names = "pciephy";
2320 2312
2321 perst-gpios = <&tlmm 2313 perst-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>;
2322 wake-gpios = <&tlmm 8 2314 wake-gpios = <&tlmm 84 GPIO_ACTIVE_HIGH>;
2323 2315
2324 pinctrl-names = "defa 2316 pinctrl-names = "default";
2325 pinctrl-0 = <&pcie1_d 2317 pinctrl-0 = <&pcie1_default_state>;
2326 dma-coherent; 2318 dma-coherent;
2327 2319
2328 status = "disabled"; 2320 status = "disabled";
2329 <<
2330 pcie@0 { <<
2331 device_type = <<
2332 reg = <0x0 0x <<
2333 bus-range = < <<
2334 <<
2335 #address-cell <<
2336 #size-cells = <<
2337 ranges; <<
2338 }; <<
2339 }; 2321 };
2340 2322
2341 pcie1_phy: phy@1c0e000 { 2323 pcie1_phy: phy@1c0e000 {
2342 compatible = "qcom,sm 2324 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
2343 reg = <0 0x01c0e000 0 2325 reg = <0 0x01c0e000 0 0x1000>;
2344 2326
2345 clocks = <&gcc GCC_PC 2327 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2346 <&gcc GCC_PC 2328 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2347 <&gcc GCC_PC 2329 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
2348 <&gcc GCC_PC 2330 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>,
2349 <&gcc GCC_PC 2331 <&gcc GCC_PCIE_1_PIPE_CLK>;
2350 clock-names = "aux", 2332 clock-names = "aux",
2351 "cfg_ah 2333 "cfg_ahb",
2352 "ref", 2334 "ref",
2353 "refgen 2335 "refgen",
2354 "pipe"; 2336 "pipe";
2355 2337
2356 clock-output-names = 2338 clock-output-names = "pcie_1_pipe_clk";
2357 #clock-cells = <0>; 2339 #clock-cells = <0>;
2358 2340
2359 #phy-cells = <0>; 2341 #phy-cells = <0>;
2360 2342
2361 resets = <&gcc GCC_PC 2343 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2362 reset-names = "phy"; 2344 reset-names = "phy";
2363 2345
2364 assigned-clocks = <&g 2346 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
2365 assigned-clock-rates 2347 assigned-clock-rates = <100000000>;
2366 2348
2367 status = "disabled"; 2349 status = "disabled";
2368 }; 2350 };
2369 2351
2370 pcie2: pcie@1c10000 { 2352 pcie2: pcie@1c10000 {
2371 compatible = "qcom,pc 2353 compatible = "qcom,pcie-sm8250";
2372 reg = <0 0x01c10000 0 2354 reg = <0 0x01c10000 0 0x3000>,
2373 <0 0x64000000 0 2355 <0 0x64000000 0 0xf1d>,
2374 <0 0x64000f20 0 2356 <0 0x64000f20 0 0xa8>,
2375 <0 0x64001000 0 2357 <0 0x64001000 0 0x1000>,
2376 <0 0x64100000 0 2358 <0 0x64100000 0 0x100000>,
2377 <0 0x01c13000 0 2359 <0 0x01c13000 0 0x1000>;
2378 reg-names = "parf", " 2360 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2379 device_type = "pci"; 2361 device_type = "pci";
2380 linux,pci-domain = <2 2362 linux,pci-domain = <2>;
2381 bus-range = <0x00 0xf 2363 bus-range = <0x00 0xff>;
2382 num-lanes = <2>; 2364 num-lanes = <2>;
2383 2365
2384 #address-cells = <3>; 2366 #address-cells = <3>;
2385 #size-cells = <2>; 2367 #size-cells = <2>;
2386 2368
2387 ranges = <0x01000000 2369 ranges = <0x01000000 0x0 0x00000000 0x0 0x64200000 0x0 0x100000>,
2388 <0x02000000 2370 <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>;
2389 2371
2390 interrupts = <GIC_SPI 2372 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
2391 <GIC_SPI 2373 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
2392 <GIC_SPI 2374 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
2393 <GIC_SPI 2375 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
2394 <GIC_SPI 2376 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
2395 <GIC_SPI 2377 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
2396 <GIC_SPI 2378 <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
2397 <GIC_SPI 2379 <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>;
2398 interrupt-names = "ms 2380 interrupt-names = "msi0",
2399 "ms 2381 "msi1",
2400 "ms 2382 "msi2",
2401 "ms 2383 "msi3",
2402 "ms 2384 "msi4",
2403 "ms 2385 "msi5",
2404 "ms 2386 "msi6",
2405 "ms 2387 "msi7";
2406 #interrupt-cells = <1 2388 #interrupt-cells = <1>;
2407 interrupt-map-mask = 2389 interrupt-map-mask = <0 0 0 0x7>;
2408 interrupt-map = <0 0 2390 interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2409 <0 0 2391 <0 0 0 2 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2410 <0 0 2392 <0 0 0 3 &intc 0 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2411 <0 0 2393 <0 0 0 4 &intc 0 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2412 2394
2413 clocks = <&gcc GCC_PC 2395 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
2414 <&gcc GCC_PC 2396 <&gcc GCC_PCIE_2_AUX_CLK>,
2415 <&gcc GCC_PC 2397 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2416 <&gcc GCC_PC 2398 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
2417 <&gcc GCC_PC 2399 <&gcc GCC_PCIE_2_SLV_AXI_CLK>,
2418 <&gcc GCC_PC 2400 <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>,
2419 <&gcc GCC_PC 2401 <&gcc GCC_PCIE_MDM_CLKREF_EN>,
2420 <&gcc GCC_AG 2402 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
2421 <&gcc GCC_DD 2403 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
2422 clock-names = "pipe", 2404 clock-names = "pipe",
2423 "aux", 2405 "aux",
2424 "cfg", 2406 "cfg",
2425 "bus_ma 2407 "bus_master",
2426 "bus_sl 2408 "bus_slave",
2427 "slave_ 2409 "slave_q2a",
2428 "ref", 2410 "ref",
2429 "tbu", 2411 "tbu",
2430 "ddrss_ 2412 "ddrss_sf_tbu";
2431 2413
2432 assigned-clocks = <&g 2414 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>;
2433 assigned-clock-rates 2415 assigned-clock-rates = <19200000>;
2434 2416
2435 iommu-map = <0x0 &a 2417 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>,
2436 <0x100 &a 2418 <0x100 &apps_smmu 0x1d01 0x1>;
2437 2419
2438 resets = <&gcc GCC_PC 2420 resets = <&gcc GCC_PCIE_2_BCR>;
2439 reset-names = "pci"; 2421 reset-names = "pci";
2440 2422
2441 power-domains = <&gcc 2423 power-domains = <&gcc PCIE_2_GDSC>;
2442 2424
2443 phys = <&pcie2_phy>; 2425 phys = <&pcie2_phy>;
2444 phy-names = "pciephy" 2426 phy-names = "pciephy";
2445 2427
2446 perst-gpios = <&tlmm 2428 perst-gpios = <&tlmm 85 GPIO_ACTIVE_LOW>;
2447 wake-gpios = <&tlmm 8 2429 wake-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>;
2448 2430
2449 pinctrl-names = "defa 2431 pinctrl-names = "default";
2450 pinctrl-0 = <&pcie2_d 2432 pinctrl-0 = <&pcie2_default_state>;
2451 dma-coherent; 2433 dma-coherent;
2452 2434
2453 status = "disabled"; 2435 status = "disabled";
2454 <<
2455 pcie@0 { <<
2456 device_type = <<
2457 reg = <0x0 0x <<
2458 bus-range = < <<
2459 <<
2460 #address-cell <<
2461 #size-cells = <<
2462 ranges; <<
2463 }; <<
2464 }; 2436 };
2465 2437
2466 pcie2_phy: phy@1c16000 { 2438 pcie2_phy: phy@1c16000 {
2467 compatible = "qcom,sm 2439 compatible = "qcom,sm8250-qmp-modem-pcie-phy";
2468 reg = <0 0x01c16000 0 2440 reg = <0 0x01c16000 0 0x1000>;
2469 2441
2470 clocks = <&gcc GCC_PC 2442 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2471 <&gcc GCC_PC 2443 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2472 <&gcc GCC_PC 2444 <&gcc GCC_PCIE_MDM_CLKREF_EN>,
2473 <&gcc GCC_PC 2445 <&gcc GCC_PCIE2_PHY_REFGEN_CLK>,
2474 <&gcc GCC_PC 2446 <&gcc GCC_PCIE_2_PIPE_CLK>;
2475 clock-names = "aux", 2447 clock-names = "aux",
2476 "cfg_ah 2448 "cfg_ahb",
2477 "ref", 2449 "ref",
2478 "refgen 2450 "refgen",
2479 "pipe"; 2451 "pipe";
2480 2452
2481 clock-output-names = 2453 clock-output-names = "pcie_2_pipe_clk";
2482 #clock-cells = <0>; 2454 #clock-cells = <0>;
2483 2455
2484 #phy-cells = <0>; 2456 #phy-cells = <0>;
2485 2457
2486 resets = <&gcc GCC_PC 2458 resets = <&gcc GCC_PCIE_2_PHY_BCR>;
2487 reset-names = "phy"; 2459 reset-names = "phy";
2488 2460
2489 assigned-clocks = <&g 2461 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
2490 assigned-clock-rates 2462 assigned-clock-rates = <100000000>;
2491 2463
2492 status = "disabled"; 2464 status = "disabled";
2493 }; 2465 };
2494 2466
2495 ufs_mem_hc: ufshc@1d84000 { 2467 ufs_mem_hc: ufshc@1d84000 {
2496 compatible = "qcom,sm 2468 compatible = "qcom,sm8250-ufshc", "qcom,ufshc",
2497 "jedec,u 2469 "jedec,ufs-2.0";
2498 reg = <0 0x01d84000 0 2470 reg = <0 0x01d84000 0 0x3000>;
2499 interrupts = <GIC_SPI 2471 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2500 phys = <&ufs_mem_phy> 2472 phys = <&ufs_mem_phy>;
2501 phy-names = "ufsphy"; 2473 phy-names = "ufsphy";
2502 lanes-per-direction = 2474 lanes-per-direction = <2>;
2503 #reset-cells = <1>; 2475 #reset-cells = <1>;
2504 resets = <&gcc GCC_UF 2476 resets = <&gcc GCC_UFS_PHY_BCR>;
2505 reset-names = "rst"; 2477 reset-names = "rst";
2506 2478
2507 power-domains = <&gcc 2479 power-domains = <&gcc UFS_PHY_GDSC>;
2508 2480
2509 iommus = <&apps_smmu 2481 iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>;
2510 2482
2511 clock-names = 2483 clock-names =
2512 "core_clk", 2484 "core_clk",
2513 "bus_aggr_clk 2485 "bus_aggr_clk",
2514 "iface_clk", 2486 "iface_clk",
2515 "core_clk_uni 2487 "core_clk_unipro",
2516 "ref_clk", 2488 "ref_clk",
2517 "tx_lane0_syn 2489 "tx_lane0_sync_clk",
2518 "rx_lane0_syn 2490 "rx_lane0_sync_clk",
2519 "rx_lane1_syn 2491 "rx_lane1_sync_clk";
2520 clocks = 2492 clocks =
2521 <&gcc GCC_UFS 2493 <&gcc GCC_UFS_PHY_AXI_CLK>,
2522 <&gcc GCC_AGG 2494 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2523 <&gcc GCC_UFS 2495 <&gcc GCC_UFS_PHY_AHB_CLK>,
2524 <&gcc GCC_UFS 2496 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2525 <&rpmhcc RPMH 2497 <&rpmhcc RPMH_CXO_CLK>,
2526 <&gcc GCC_UFS 2498 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2527 <&gcc GCC_UFS 2499 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2528 <&gcc GCC_UFS 2500 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
2529 2501
2530 operating-points-v2 = 2502 operating-points-v2 = <&ufs_opp_table>;
2531 2503
2532 interconnects = <&agg 2504 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI_CH0 0>,
2533 <&gem 2505 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
2534 interconnect-names = 2506 interconnect-names = "ufs-ddr", "cpu-ufs";
2535 2507
2536 status = "disabled"; 2508 status = "disabled";
2537 2509
2538 ufs_opp_table: opp-ta 2510 ufs_opp_table: opp-table {
2539 compatible = 2511 compatible = "operating-points-v2";
2540 2512
2541 opp-37500000 2513 opp-37500000 {
2542 opp-h 2514 opp-hz = /bits/ 64 <37500000>,
2543 2515 /bits/ 64 <0>,
2544 2516 /bits/ 64 <0>,
2545 2517 /bits/ 64 <37500000>,
2546 2518 /bits/ 64 <0>,
2547 2519 /bits/ 64 <0>,
2548 2520 /bits/ 64 <0>,
2549 2521 /bits/ 64 <0>;
2550 requi 2522 required-opps = <&rpmhpd_opp_low_svs>;
2551 }; 2523 };
2552 2524
2553 opp-300000000 2525 opp-300000000 {
2554 opp-h 2526 opp-hz = /bits/ 64 <300000000>,
2555 2527 /bits/ 64 <0>,
2556 2528 /bits/ 64 <0>,
2557 2529 /bits/ 64 <300000000>,
2558 2530 /bits/ 64 <0>,
2559 2531 /bits/ 64 <0>,
2560 2532 /bits/ 64 <0>,
2561 2533 /bits/ 64 <0>;
2562 requi 2534 required-opps = <&rpmhpd_opp_nom>;
2563 }; 2535 };
2564 }; 2536 };
2565 }; 2537 };
2566 2538
2567 ufs_mem_phy: phy@1d87000 { 2539 ufs_mem_phy: phy@1d87000 {
2568 compatible = "qcom,sm 2540 compatible = "qcom,sm8250-qmp-ufs-phy";
2569 reg = <0 0x01d87000 0 2541 reg = <0 0x01d87000 0 0x1000>;
2570 2542
2571 clocks = <&rpmhcc RPM 2543 clocks = <&rpmhcc RPMH_CXO_CLK>,
2572 <&gcc GCC_UF 2544 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
2573 <&gcc GCC_UF 2545 <&gcc GCC_UFS_1X_CLKREF_EN>;
2574 clock-names = "ref", 2546 clock-names = "ref",
2575 "ref_au 2547 "ref_aux",
2576 "qref"; 2548 "qref";
2577 2549
2578 resets = <&ufs_mem_hc 2550 resets = <&ufs_mem_hc 0>;
2579 reset-names = "ufsphy 2551 reset-names = "ufsphy";
2580 2552
2581 power-domains = <&gcc <<
2582 <<
2583 #phy-cells = <0>; 2553 #phy-cells = <0>;
2584 2554
2585 status = "disabled"; 2555 status = "disabled";
2586 }; 2556 };
2587 2557
2588 cryptobam: dma-controller@1dc 2558 cryptobam: dma-controller@1dc4000 {
2589 compatible = "qcom,ba 2559 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
2590 reg = <0 0x01dc4000 0 2560 reg = <0 0x01dc4000 0 0x24000>;
2591 interrupts = <GIC_SPI 2561 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
2592 #dma-cells = <1>; 2562 #dma-cells = <1>;
2593 qcom,ee = <0>; 2563 qcom,ee = <0>;
2594 qcom,controlled-remot 2564 qcom,controlled-remotely;
2595 num-channels = <8>; 2565 num-channels = <8>;
2596 qcom,num-ees = <2>; 2566 qcom,num-ees = <2>;
2597 iommus = <&apps_smmu 2567 iommus = <&apps_smmu 0x592 0x0000>,
2598 <&apps_smmu 2568 <&apps_smmu 0x598 0x0000>,
2599 <&apps_smmu 2569 <&apps_smmu 0x599 0x0000>,
2600 <&apps_smmu 2570 <&apps_smmu 0x59f 0x0000>,
2601 <&apps_smmu 2571 <&apps_smmu 0x586 0x0011>,
2602 <&apps_smmu 2572 <&apps_smmu 0x596 0x0011>;
2603 }; 2573 };
2604 2574
2605 crypto: crypto@1dfa000 { 2575 crypto: crypto@1dfa000 {
2606 compatible = "qcom,sm 2576 compatible = "qcom,sm8250-qce", "qcom,sm8150-qce", "qcom,qce";
2607 reg = <0 0x01dfa000 0 2577 reg = <0 0x01dfa000 0 0x6000>;
2608 dmas = <&cryptobam 4> 2578 dmas = <&cryptobam 4>, <&cryptobam 5>;
2609 dma-names = "rx", "tx 2579 dma-names = "rx", "tx";
2610 iommus = <&apps_smmu 2580 iommus = <&apps_smmu 0x592 0x0000>,
2611 <&apps_smmu 2581 <&apps_smmu 0x598 0x0000>,
2612 <&apps_smmu 2582 <&apps_smmu 0x599 0x0000>,
2613 <&apps_smmu 2583 <&apps_smmu 0x59f 0x0000>,
2614 <&apps_smmu 2584 <&apps_smmu 0x586 0x0011>,
2615 <&apps_smmu 2585 <&apps_smmu 0x596 0x0011>;
2616 interconnects = <&agg 2586 interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 0 &mc_virt SLAVE_EBI_CH0 0>;
2617 interconnect-names = 2587 interconnect-names = "memory";
2618 }; 2588 };
2619 2589
2620 tcsr_mutex: hwlock@1f40000 { 2590 tcsr_mutex: hwlock@1f40000 {
2621 compatible = "qcom,tc 2591 compatible = "qcom,tcsr-mutex";
2622 reg = <0x0 0x01f40000 2592 reg = <0x0 0x01f40000 0x0 0x40000>;
2623 #hwlock-cells = <1>; 2593 #hwlock-cells = <1>;
2624 }; 2594 };
2625 2595
2626 tcsr: syscon@1fc0000 { 2596 tcsr: syscon@1fc0000 {
2627 compatible = "qcom,sm 2597 compatible = "qcom,sm8250-tcsr", "syscon";
2628 reg = <0x0 0x1fc0000 2598 reg = <0x0 0x1fc0000 0x0 0x30000>;
2629 }; 2599 };
2630 2600
2631 wsamacro: codec@3240000 { 2601 wsamacro: codec@3240000 {
2632 compatible = "qcom,sm 2602 compatible = "qcom,sm8250-lpass-wsa-macro";
2633 reg = <0 0x03240000 0 2603 reg = <0 0x03240000 0 0x1000>;
2634 clocks = <&q6afecc LP !! 2604 clocks = <&audiocc LPASS_CDC_WSA_MCLK>,
2635 <&q6afecc LP !! 2605 <&audiocc LPASS_CDC_WSA_NPL>,
2636 <&q6afecc LP 2606 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2637 <&q6afecc LP 2607 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 2608 <&aoncc LPASS_CDC_VA_MCLK>,
2638 <&vamacro>; 2609 <&vamacro>;
2639 2610
2640 clock-names = "mclk", !! 2611 clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen";
2641 2612
2642 #clock-cells = <0>; 2613 #clock-cells = <0>;
2643 clock-output-names = 2614 clock-output-names = "mclk";
2644 #sound-dai-cells = <1 2615 #sound-dai-cells = <1>;
2645 2616
2646 pinctrl-names = "defa 2617 pinctrl-names = "default";
2647 pinctrl-0 = <&wsa_swr 2618 pinctrl-0 = <&wsa_swr_active>;
2648 2619
2649 status = "disabled"; 2620 status = "disabled";
2650 }; 2621 };
2651 2622
2652 swr0: soundwire@3250000 { 2623 swr0: soundwire@3250000 {
2653 reg = <0 0x03250000 0 2624 reg = <0 0x03250000 0 0x2000>;
2654 compatible = "qcom,so 2625 compatible = "qcom,soundwire-v1.5.1";
2655 interrupts = <GIC_SPI 2626 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
2656 clocks = <&wsamacro>; 2627 clocks = <&wsamacro>;
2657 clock-names = "iface" 2628 clock-names = "iface";
2658 2629
2659 qcom,din-ports = <2>; 2630 qcom,din-ports = <2>;
2660 qcom,dout-ports = <6> 2631 qcom,dout-ports = <6>;
2661 2632
2662 qcom,ports-sinterval- 2633 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2663 qcom,ports-offset1 = 2634 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2664 qcom,ports-offset2 = 2635 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2665 qcom,ports-block-pack 2636 qcom,ports-block-pack-mode = /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>;
2666 2637
2667 #sound-dai-cells = <1 2638 #sound-dai-cells = <1>;
2668 #address-cells = <2>; 2639 #address-cells = <2>;
2669 #size-cells = <0>; 2640 #size-cells = <0>;
2670 2641
2671 status = "disabled"; 2642 status = "disabled";
2672 }; 2643 };
2673 2644
>> 2645 audiocc: clock-controller@3300000 {
>> 2646 compatible = "qcom,sm8250-lpass-audiocc";
>> 2647 reg = <0 0x03300000 0 0x30000>;
>> 2648 #clock-cells = <1>;
>> 2649 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 2650 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 2651 <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
>> 2652 clock-names = "core", "audio", "bus";
>> 2653 };
>> 2654
2674 vamacro: codec@3370000 { 2655 vamacro: codec@3370000 {
2675 compatible = "qcom,sm 2656 compatible = "qcom,sm8250-lpass-va-macro";
2676 reg = <0 0x03370000 0 2657 reg = <0 0x03370000 0 0x1000>;
2677 clocks = <&q6afecc LP !! 2658 clocks = <&aoncc LPASS_CDC_VA_MCLK>,
2678 <&q6afecc LPA 2659 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2679 <&q6afecc LPA 2660 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2680 2661
2681 clock-names = "mclk", 2662 clock-names = "mclk", "macro", "dcodec";
2682 2663
2683 #clock-cells = <0>; 2664 #clock-cells = <0>;
2684 clock-output-names = 2665 clock-output-names = "fsgen";
2685 #sound-dai-cells = <1 2666 #sound-dai-cells = <1>;
2686 }; 2667 };
2687 2668
2688 rxmacro: rxmacro@3200000 { 2669 rxmacro: rxmacro@3200000 {
2689 pinctrl-names = "defa 2670 pinctrl-names = "default";
2690 pinctrl-0 = <&rx_swr_ 2671 pinctrl-0 = <&rx_swr_active>;
2691 compatible = "qcom,sm 2672 compatible = "qcom,sm8250-lpass-rx-macro";
2692 reg = <0 0x03200000 0 2673 reg = <0 0x03200000 0 0x1000>;
2693 status = "disabled"; 2674 status = "disabled";
2694 2675
2695 clocks = <&q6afecc LP 2676 clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2696 <&q6afecc LPA 2677 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2697 <&q6afecc LPA 2678 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2698 <&q6afecc LPA 2679 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2699 <&vamacro>; 2680 <&vamacro>;
2700 2681
2701 clock-names = "mclk", 2682 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2702 2683
2703 #clock-cells = <0>; 2684 #clock-cells = <0>;
2704 clock-output-names = 2685 clock-output-names = "mclk";
2705 #sound-dai-cells = <1 2686 #sound-dai-cells = <1>;
2706 }; 2687 };
2707 2688
2708 swr1: soundwire@3210000 { 2689 swr1: soundwire@3210000 {
2709 reg = <0 0x03210000 0 2690 reg = <0 0x03210000 0 0x2000>;
2710 compatible = "qcom,so 2691 compatible = "qcom,soundwire-v1.5.1";
2711 status = "disabled"; 2692 status = "disabled";
2712 interrupts = <GIC_SPI 2693 interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
2713 clocks = <&rxmacro>; 2694 clocks = <&rxmacro>;
2714 clock-names = "iface" 2695 clock-names = "iface";
2715 label = "RX"; 2696 label = "RX";
2716 qcom,din-ports = <0>; 2697 qcom,din-ports = <0>;
2717 qcom,dout-ports = <5> 2698 qcom,dout-ports = <5>;
2718 2699
2719 qcom,ports-sinterval- 2700 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
2720 qcom,ports-offset1 = 2701 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>;
2721 qcom,ports-offset2 = 2702 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
2722 qcom,ports-hstart = 2703 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
2723 qcom,ports-hstop = 2704 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
2724 qcom,ports-word-lengt 2705 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2725 qcom,ports-block-pack 2706 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
2726 qcom,ports-lane-contr 2707 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2727 qcom,ports-block-grou 2708 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
2728 2709
2729 #sound-dai-cells = <1 2710 #sound-dai-cells = <1>;
2730 #address-cells = <2>; 2711 #address-cells = <2>;
2731 #size-cells = <0>; 2712 #size-cells = <0>;
2732 }; 2713 };
2733 2714
2734 txmacro: txmacro@3220000 { 2715 txmacro: txmacro@3220000 {
2735 pinctrl-names = "defa 2716 pinctrl-names = "default";
2736 pinctrl-0 = <&tx_swr_ 2717 pinctrl-0 = <&tx_swr_active>;
2737 compatible = "qcom,sm 2718 compatible = "qcom,sm8250-lpass-tx-macro";
2738 reg = <0 0x03220000 0 2719 reg = <0 0x03220000 0 0x1000>;
2739 status = "disabled"; 2720 status = "disabled";
2740 2721
2741 clocks = <&q6afecc LP 2722 clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2742 <&q6afecc LP 2723 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2743 <&q6afecc LP 2724 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2744 <&q6afecc LP 2725 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2745 <&vamacro>; 2726 <&vamacro>;
2746 2727
2747 clock-names = "mclk", 2728 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2748 2729
2749 #clock-cells = <0>; 2730 #clock-cells = <0>;
2750 clock-output-names = 2731 clock-output-names = "mclk";
2751 #sound-dai-cells = <1 2732 #sound-dai-cells = <1>;
2752 }; 2733 };
2753 2734
2754 /* tx macro */ 2735 /* tx macro */
2755 swr2: soundwire@3230000 { 2736 swr2: soundwire@3230000 {
2756 reg = <0 0x03230000 0 2737 reg = <0 0x03230000 0 0x2000>;
2757 compatible = "qcom,so 2738 compatible = "qcom,soundwire-v1.5.1";
2758 interrupts = <GIC_SPI 2739 interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
2759 interrupt-names = "co 2740 interrupt-names = "core";
2760 status = "disabled"; 2741 status = "disabled";
2761 2742
2762 clocks = <&txmacro>; 2743 clocks = <&txmacro>;
2763 clock-names = "iface" 2744 clock-names = "iface";
2764 label = "TX"; 2745 label = "TX";
2765 2746
2766 qcom,din-ports = <5>; 2747 qcom,din-ports = <5>;
2767 qcom,dout-ports = <0> 2748 qcom,dout-ports = <0>;
2768 qcom,ports-sinterval- 2749 qcom,ports-sinterval-low = /bits/ 8 <0xff 0x01 0x01 0x03 0x03>;
2769 qcom,ports-offset1 = 2750 qcom,ports-offset1 = /bits/ 8 <0xff 0x01 0x00 0x02 0x00>;
2770 qcom,ports-offset2 = 2751 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x00 0x00 0x00>;
2771 qcom,ports-block-pack 2752 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2772 qcom,ports-hstart = 2753 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2773 qcom,ports-hstop = 2754 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2774 qcom,ports-word-lengt 2755 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2775 qcom,ports-block-grou 2756 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2776 qcom,ports-lane-contr 2757 qcom,ports-lane-control = /bits/ 8 <0xff 0x00 0x01 0x00 0x01>;
2777 #sound-dai-cells = <1 2758 #sound-dai-cells = <1>;
2778 #address-cells = <2>; 2759 #address-cells = <2>;
2779 #size-cells = <0>; 2760 #size-cells = <0>;
2780 }; 2761 };
2781 2762
>> 2763 aoncc: clock-controller@3380000 {
>> 2764 compatible = "qcom,sm8250-lpass-aoncc";
>> 2765 reg = <0 0x03380000 0 0x40000>;
>> 2766 #clock-cells = <1>;
>> 2767 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 2768 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 2769 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
>> 2770 clock-names = "core", "audio", "bus";
>> 2771 };
>> 2772
2782 lpass_tlmm: pinctrl@33c0000 { 2773 lpass_tlmm: pinctrl@33c0000 {
2783 compatible = "qcom,sm 2774 compatible = "qcom,sm8250-lpass-lpi-pinctrl";
2784 reg = <0 0x033c0000 0 2775 reg = <0 0x033c0000 0x0 0x20000>,
2785 <0 0x03550000 0 2776 <0 0x03550000 0x0 0x10000>;
2786 gpio-controller; 2777 gpio-controller;
2787 #gpio-cells = <2>; 2778 #gpio-cells = <2>;
2788 gpio-ranges = <&lpass 2779 gpio-ranges = <&lpass_tlmm 0 0 14>;
2789 2780
2790 clocks = <&q6afecc LP 2781 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2791 <&q6afecc LPA 2782 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2792 clock-names = "core", 2783 clock-names = "core", "audio";
2793 2784
2794 wsa_swr_active: wsa-s 2785 wsa_swr_active: wsa-swr-active-state {
2795 clk-pins { 2786 clk-pins {
2796 pins 2787 pins = "gpio10";
2797 funct 2788 function = "wsa_swr_clk";
2798 drive 2789 drive-strength = <2>;
2799 slew- 2790 slew-rate = <1>;
2800 bias- 2791 bias-disable;
2801 }; 2792 };
2802 2793
2803 data-pins { 2794 data-pins {
2804 pins 2795 pins = "gpio11";
2805 funct 2796 function = "wsa_swr_data";
2806 drive 2797 drive-strength = <2>;
2807 slew- 2798 slew-rate = <1>;
2808 bias- 2799 bias-bus-hold;
2809 }; 2800 };
2810 }; 2801 };
2811 2802
2812 wsa_swr_sleep: wsa-sw 2803 wsa_swr_sleep: wsa-swr-sleep-state {
2813 clk-pins { 2804 clk-pins {
2814 pins 2805 pins = "gpio10";
2815 funct 2806 function = "wsa_swr_clk";
2816 drive 2807 drive-strength = <2>;
2817 bias- 2808 bias-pull-down;
2818 }; 2809 };
2819 2810
2820 data-pins { 2811 data-pins {
2821 pins 2812 pins = "gpio11";
2822 funct 2813 function = "wsa_swr_data";
2823 drive 2814 drive-strength = <2>;
2824 bias- 2815 bias-pull-down;
2825 }; 2816 };
2826 }; 2817 };
2827 2818
2828 dmic01_active: dmic01 2819 dmic01_active: dmic01-active-state {
2829 clk-pins { 2820 clk-pins {
2830 pins 2821 pins = "gpio6";
2831 funct 2822 function = "dmic1_clk";
2832 drive 2823 drive-strength = <8>;
2833 outpu 2824 output-high;
2834 }; 2825 };
2835 data-pins { 2826 data-pins {
2836 pins 2827 pins = "gpio7";
2837 funct 2828 function = "dmic1_data";
2838 drive 2829 drive-strength = <8>;
2839 }; 2830 };
2840 }; 2831 };
2841 2832
2842 dmic01_sleep: dmic01- 2833 dmic01_sleep: dmic01-sleep-state {
2843 clk-pins { 2834 clk-pins {
2844 pins 2835 pins = "gpio6";
2845 funct 2836 function = "dmic1_clk";
2846 drive 2837 drive-strength = <2>;
2847 bias- 2838 bias-disable;
2848 outpu 2839 output-low;
2849 }; 2840 };
2850 2841
2851 data-pins { 2842 data-pins {
2852 pins 2843 pins = "gpio7";
2853 funct 2844 function = "dmic1_data";
2854 drive 2845 drive-strength = <2>;
2855 bias- 2846 bias-pull-down;
2856 }; 2847 };
2857 }; 2848 };
2858 2849
2859 rx_swr_active: rx-swr 2850 rx_swr_active: rx-swr-active-state {
2860 clk-pins { 2851 clk-pins {
2861 pins 2852 pins = "gpio3";
2862 funct 2853 function = "swr_rx_clk";
2863 drive 2854 drive-strength = <2>;
2864 slew- 2855 slew-rate = <1>;
2865 bias- 2856 bias-disable;
2866 }; 2857 };
2867 2858
2868 data-pins { 2859 data-pins {
2869 pins 2860 pins = "gpio4", "gpio5";
2870 funct 2861 function = "swr_rx_data";
2871 drive 2862 drive-strength = <2>;
2872 slew- 2863 slew-rate = <1>;
2873 bias- 2864 bias-bus-hold;
2874 }; 2865 };
2875 }; 2866 };
2876 2867
2877 tx_swr_active: tx-swr 2868 tx_swr_active: tx-swr-active-state {
2878 clk-pins { 2869 clk-pins {
2879 pins 2870 pins = "gpio0";
2880 funct 2871 function = "swr_tx_clk";
2881 drive 2872 drive-strength = <2>;
2882 slew- 2873 slew-rate = <1>;
2883 bias- 2874 bias-disable;
2884 }; 2875 };
2885 2876
2886 data-pins { 2877 data-pins {
2887 pins 2878 pins = "gpio1", "gpio2";
2888 funct 2879 function = "swr_tx_data";
2889 drive 2880 drive-strength = <2>;
2890 slew- 2881 slew-rate = <1>;
2891 bias- 2882 bias-bus-hold;
2892 }; 2883 };
2893 }; 2884 };
2894 2885
2895 tx_swr_sleep: tx-swr- 2886 tx_swr_sleep: tx-swr-sleep-state {
2896 clk-pins { 2887 clk-pins {
2897 pins 2888 pins = "gpio0";
2898 funct 2889 function = "swr_tx_clk";
2899 drive 2890 drive-strength = <2>;
2900 bias- 2891 bias-pull-down;
2901 }; 2892 };
2902 2893
2903 data1-pins { 2894 data1-pins {
2904 pins 2895 pins = "gpio1";
2905 funct 2896 function = "swr_tx_data";
2906 drive 2897 drive-strength = <2>;
2907 bias- 2898 bias-bus-hold;
2908 }; 2899 };
2909 2900
2910 data2-pins { 2901 data2-pins {
2911 pins 2902 pins = "gpio2";
2912 funct 2903 function = "swr_tx_data";
2913 drive 2904 drive-strength = <2>;
2914 bias- 2905 bias-pull-down;
2915 }; 2906 };
2916 }; 2907 };
2917 }; 2908 };
2918 2909
2919 gpu: gpu@3d00000 { 2910 gpu: gpu@3d00000 {
2920 compatible = "qcom,ad 2911 compatible = "qcom,adreno-650.2",
2921 "qcom,ad 2912 "qcom,adreno";
2922 2913
2923 reg = <0 0x03d00000 0 2914 reg = <0 0x03d00000 0 0x40000>;
2924 reg-names = "kgsl_3d0 2915 reg-names = "kgsl_3d0_reg_memory";
2925 2916
2926 interrupts = <GIC_SPI 2917 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2927 2918
2928 iommus = <&adreno_smm 2919 iommus = <&adreno_smmu 0 0x401>;
2929 2920
2930 operating-points-v2 = 2921 operating-points-v2 = <&gpu_opp_table>;
2931 2922
2932 qcom,gmu = <&gmu>; 2923 qcom,gmu = <&gmu>;
2933 2924
2934 nvmem-cells = <&gpu_s 2925 nvmem-cells = <&gpu_speed_bin>;
2935 nvmem-cell-names = "s 2926 nvmem-cell-names = "speed_bin";
2936 #cooling-cells = <2>; 2927 #cooling-cells = <2>;
2937 2928
2938 status = "disabled"; 2929 status = "disabled";
2939 2930
2940 zap-shader { 2931 zap-shader {
2941 memory-region 2932 memory-region = <&gpu_mem>;
2942 }; 2933 };
2943 2934
2944 gpu_opp_table: opp-ta 2935 gpu_opp_table: opp-table {
2945 compatible = 2936 compatible = "operating-points-v2";
2946 2937
2947 opp-670000000 2938 opp-670000000 {
2948 opp-h 2939 opp-hz = /bits/ 64 <670000000>;
2949 opp-l 2940 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2950 opp-s 2941 opp-supported-hw = <0xa>;
2951 }; 2942 };
2952 2943
2953 opp-587000000 2944 opp-587000000 {
2954 opp-h 2945 opp-hz = /bits/ 64 <587000000>;
2955 opp-l 2946 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2956 opp-s 2947 opp-supported-hw = <0xb>;
2957 }; 2948 };
2958 2949
2959 opp-525000000 2950 opp-525000000 {
2960 opp-h 2951 opp-hz = /bits/ 64 <525000000>;
2961 opp-l 2952 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2962 opp-s 2953 opp-supported-hw = <0xf>;
2963 }; 2954 };
2964 2955
2965 opp-490000000 2956 opp-490000000 {
2966 opp-h 2957 opp-hz = /bits/ 64 <490000000>;
2967 opp-l 2958 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2968 opp-s 2959 opp-supported-hw = <0xf>;
2969 }; 2960 };
2970 2961
2971 opp-441600000 2962 opp-441600000 {
2972 opp-h 2963 opp-hz = /bits/ 64 <441600000>;
2973 opp-l 2964 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
2974 opp-s 2965 opp-supported-hw = <0xf>;
2975 }; 2966 };
2976 2967
2977 opp-400000000 2968 opp-400000000 {
2978 opp-h 2969 opp-hz = /bits/ 64 <400000000>;
2979 opp-l 2970 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2980 opp-s 2971 opp-supported-hw = <0xf>;
2981 }; 2972 };
2982 2973
2983 opp-305000000 2974 opp-305000000 {
2984 opp-h 2975 opp-hz = /bits/ 64 <305000000>;
2985 opp-l 2976 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2986 opp-s 2977 opp-supported-hw = <0xf>;
2987 }; 2978 };
2988 }; 2979 };
2989 }; 2980 };
2990 2981
2991 gmu: gmu@3d6a000 { 2982 gmu: gmu@3d6a000 {
2992 compatible = "qcom,ad 2983 compatible = "qcom,adreno-gmu-650.2", "qcom,adreno-gmu";
2993 2984
2994 reg = <0 0x03d6a000 0 2985 reg = <0 0x03d6a000 0 0x30000>,
2995 <0 0x3de0000 0 2986 <0 0x3de0000 0 0x10000>,
2996 <0 0xb290000 0 2987 <0 0xb290000 0 0x10000>,
2997 <0 0xb490000 0 2988 <0 0xb490000 0 0x10000>;
2998 reg-names = "gmu", "r 2989 reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq";
2999 2990
3000 interrupts = <GIC_SPI 2991 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
3001 <GIC_SPI 2992 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
3002 interrupt-names = "hf 2993 interrupt-names = "hfi", "gmu";
3003 2994
3004 clocks = <&gpucc GPU_ 2995 clocks = <&gpucc GPU_CC_AHB_CLK>,
3005 <&gpucc GPU_ 2996 <&gpucc GPU_CC_CX_GMU_CLK>,
3006 <&gpucc GPU_ 2997 <&gpucc GPU_CC_CXO_CLK>,
3007 <&gcc GCC_DD 2998 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
3008 <&gcc GCC_GP 2999 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
3009 clock-names = "ahb", 3000 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
3010 3001
3011 power-domains = <&gpu 3002 power-domains = <&gpucc GPU_CX_GDSC>,
3012 <&gpu 3003 <&gpucc GPU_GX_GDSC>;
3013 power-domain-names = 3004 power-domain-names = "cx", "gx";
3014 3005
3015 iommus = <&adreno_smm 3006 iommus = <&adreno_smmu 5 0x400>;
3016 3007
3017 operating-points-v2 = 3008 operating-points-v2 = <&gmu_opp_table>;
3018 3009
3019 status = "disabled"; 3010 status = "disabled";
3020 3011
3021 gmu_opp_table: opp-ta 3012 gmu_opp_table: opp-table {
3022 compatible = 3013 compatible = "operating-points-v2";
3023 3014
3024 opp-200000000 3015 opp-200000000 {
3025 opp-h 3016 opp-hz = /bits/ 64 <200000000>;
3026 opp-l 3017 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3027 }; 3018 };
3028 }; 3019 };
3029 }; 3020 };
3030 3021
3031 gpucc: clock-controller@3d900 3022 gpucc: clock-controller@3d90000 {
3032 compatible = "qcom,sm 3023 compatible = "qcom,sm8250-gpucc";
3033 reg = <0 0x03d90000 0 3024 reg = <0 0x03d90000 0 0x9000>;
3034 clocks = <&rpmhcc RPM 3025 clocks = <&rpmhcc RPMH_CXO_CLK>,
3035 <&gcc GCC_GP 3026 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
3036 <&gcc GCC_GP 3027 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
3037 clock-names = "bi_tcx 3028 clock-names = "bi_tcxo",
3038 "gcc_gp 3029 "gcc_gpu_gpll0_clk_src",
3039 "gcc_gp 3030 "gcc_gpu_gpll0_div_clk_src";
3040 #clock-cells = <1>; 3031 #clock-cells = <1>;
3041 #reset-cells = <1>; 3032 #reset-cells = <1>;
3042 #power-domain-cells = 3033 #power-domain-cells = <1>;
3043 }; 3034 };
3044 3035
3045 adreno_smmu: iommu@3da0000 { 3036 adreno_smmu: iommu@3da0000 {
3046 compatible = "qcom,sm 3037 compatible = "qcom,sm8250-smmu-500", "qcom,adreno-smmu",
3047 "qcom,sm 3038 "qcom,smmu-500", "arm,mmu-500";
3048 reg = <0 0x03da0000 0 3039 reg = <0 0x03da0000 0 0x10000>;
3049 #iommu-cells = <2>; 3040 #iommu-cells = <2>;
3050 #global-interrupts = 3041 #global-interrupts = <2>;
3051 interrupts = <GIC_SPI 3042 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
3052 <GIC_SPI 3043 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
3053 <GIC_SPI 3044 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
3054 <GIC_SPI 3045 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
3055 <GIC_SPI 3046 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
3056 <GIC_SPI 3047 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
3057 <GIC_SPI 3048 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
3058 <GIC_SPI 3049 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
3059 <GIC_SPI 3050 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
3060 <GIC_SPI 3051 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>;
3061 clocks = <&gpucc GPU_ 3052 clocks = <&gpucc GPU_CC_AHB_CLK>,
3062 <&gcc GCC_GP 3053 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
3063 <&gcc GCC_GP 3054 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
3064 clock-names = "ahb", 3055 clock-names = "ahb", "bus", "iface";
3065 3056
3066 power-domains = <&gpu 3057 power-domains = <&gpucc GPU_CX_GDSC>;
3067 dma-coherent; 3058 dma-coherent;
3068 }; 3059 };
3069 3060
3070 slpi: remoteproc@5c00000 { 3061 slpi: remoteproc@5c00000 {
3071 compatible = "qcom,sm 3062 compatible = "qcom,sm8250-slpi-pas";
3072 reg = <0 0x05c00000 0 3063 reg = <0 0x05c00000 0 0x4000>;
3073 3064
3074 interrupts-extended = 3065 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>,
3075 3066 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
3076 3067 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
3077 3068 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
3078 3069 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
3079 interrupt-names = "wd 3070 interrupt-names = "wdog", "fatal", "ready",
3080 "ha 3071 "handover", "stop-ack";
3081 3072
3082 clocks = <&rpmhcc RPM 3073 clocks = <&rpmhcc RPMH_CXO_CLK>;
3083 clock-names = "xo"; 3074 clock-names = "xo";
3084 3075
3085 power-domains = <&rpm 3076 power-domains = <&rpmhpd RPMHPD_LCX>,
3086 <&rpm 3077 <&rpmhpd RPMHPD_LMX>;
3087 power-domain-names = 3078 power-domain-names = "lcx", "lmx";
3088 3079
3089 memory-region = <&slp 3080 memory-region = <&slpi_mem>;
3090 3081
3091 qcom,qmp = <&aoss_qmp 3082 qcom,qmp = <&aoss_qmp>;
3092 3083
3093 qcom,smem-states = <& 3084 qcom,smem-states = <&smp2p_slpi_out 0>;
3094 qcom,smem-state-names 3085 qcom,smem-state-names = "stop";
3095 3086
3096 status = "disabled"; 3087 status = "disabled";
3097 3088
3098 glink-edge { 3089 glink-edge {
3099 interrupts-ex 3090 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
3100 3091 IPCC_MPROC_SIGNAL_GLINK_QMP
3101 3092 IRQ_TYPE_EDGE_RISING>;
3102 mboxes = <&ip 3093 mboxes = <&ipcc IPCC_CLIENT_SLPI
3103 3094 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3104 3095
3105 label = "slpi 3096 label = "slpi";
3106 qcom,remote-p 3097 qcom,remote-pid = <3>;
3107 3098
3108 fastrpc { 3099 fastrpc {
3109 compa 3100 compatible = "qcom,fastrpc";
3110 qcom, 3101 qcom,glink-channels = "fastrpcglink-apps-dsp";
3111 label 3102 label = "sdsp";
3112 qcom, 3103 qcom,non-secure-domain;
3113 #addr 3104 #address-cells = <1>;
3114 #size 3105 #size-cells = <0>;
3115 3106
3116 compu 3107 compute-cb@1 {
3117 3108 compatible = "qcom,fastrpc-compute-cb";
3118 3109 reg = <1>;
3119 3110 iommus = <&apps_smmu 0x0541 0x0>;
3120 }; 3111 };
3121 3112
3122 compu 3113 compute-cb@2 {
3123 3114 compatible = "qcom,fastrpc-compute-cb";
3124 3115 reg = <2>;
3125 3116 iommus = <&apps_smmu 0x0542 0x0>;
3126 }; 3117 };
3127 3118
3128 compu 3119 compute-cb@3 {
3129 3120 compatible = "qcom,fastrpc-compute-cb";
3130 3121 reg = <3>;
3131 3122 iommus = <&apps_smmu 0x0543 0x0>;
3132 3123 /* note: shared-cb = <4> in downstream */
3133 }; 3124 };
3134 }; 3125 };
3135 }; 3126 };
3136 }; 3127 };
3137 3128
3138 stm@6002000 { 3129 stm@6002000 {
3139 compatible = "arm,cor 3130 compatible = "arm,coresight-stm", "arm,primecell";
3140 reg = <0 0x06002000 0 3131 reg = <0 0x06002000 0 0x1000>, <0 0x16280000 0 0x180000>;
3141 reg-names = "stm-base 3132 reg-names = "stm-base", "stm-stimulus-base";
3142 3133
3143 clocks = <&aoss_qmp>; 3134 clocks = <&aoss_qmp>;
3144 clock-names = "apb_pc 3135 clock-names = "apb_pclk";
3145 3136
3146 out-ports { 3137 out-ports {
3147 port { 3138 port {
3148 stm_o 3139 stm_out: endpoint {
3149 3140 remote-endpoint = <&funnel0_in7>;
3150 }; 3141 };
3151 }; 3142 };
3152 }; 3143 };
3153 }; 3144 };
3154 3145
3155 tpda@6004000 { 3146 tpda@6004000 {
3156 compatible = "qcom,co 3147 compatible = "qcom,coresight-tpda", "arm,primecell";
3157 reg = <0 0x06004000 0 3148 reg = <0 0x06004000 0 0x1000>;
3158 3149
3159 clocks = <&aoss_qmp>; 3150 clocks = <&aoss_qmp>;
3160 clock-names = "apb_pc 3151 clock-names = "apb_pclk";
3161 3152
3162 out-ports { 3153 out-ports {
3163 3154
3164 port { 3155 port {
3165 tpda_ 3156 tpda_out_funnel_qatb: endpoint {
3166 3157 remote-endpoint = <&funnel_qatb_in_tpda>;
3167 }; 3158 };
3168 }; 3159 };
3169 }; 3160 };
3170 3161
3171 in-ports { 3162 in-ports {
3172 #address-cell 3163 #address-cells = <1>;
3173 #size-cells = 3164 #size-cells = <0>;
3174 3165
3175 port@9 { 3166 port@9 {
3176 reg = 3167 reg = <9>;
3177 tpda_ 3168 tpda_9_in_tpdm_mm: endpoint {
3178 3169 remote-endpoint = <&tpdm_mm_out_tpda9>;
3179 }; 3170 };
3180 }; 3171 };
3181 3172
3182 port@17 { 3173 port@17 {
3183 reg = 3174 reg = <23>;
3184 tpda_ 3175 tpda_23_in_tpdm_prng: endpoint {
3185 3176 remote-endpoint = <&tpdm_prng_out_tpda_23>;
3186 }; 3177 };
3187 }; 3178 };
3188 }; 3179 };
3189 }; 3180 };
3190 3181
3191 funnel@6005000 { 3182 funnel@6005000 {
3192 compatible = "arm,cor 3183 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3193 reg = <0 0x06005000 0 3184 reg = <0 0x06005000 0 0x1000>;
3194 3185
3195 clocks = <&aoss_qmp>; 3186 clocks = <&aoss_qmp>;
3196 clock-names = "apb_pc 3187 clock-names = "apb_pclk";
3197 3188
3198 out-ports { 3189 out-ports {
3199 port { 3190 port {
3200 funne 3191 funnel_qatb_out_funnel_in0: endpoint {
3201 3192 remote-endpoint = <&funnel_in0_in_funnel_qatb>;
3202 }; 3193 };
3203 }; 3194 };
3204 }; 3195 };
3205 3196
3206 in-ports { 3197 in-ports {
3207 port { 3198 port {
3208 funne 3199 funnel_qatb_in_tpda: endpoint {
3209 3200 remote-endpoint = <&tpda_out_funnel_qatb>;
3210 }; 3201 };
3211 }; 3202 };
3212 }; 3203 };
3213 }; 3204 };
3214 3205
3215 funnel@6041000 { 3206 funnel@6041000 {
3216 compatible = "arm,cor 3207 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3217 reg = <0 0x06041000 0 3208 reg = <0 0x06041000 0 0x1000>;
3218 3209
3219 clocks = <&aoss_qmp>; 3210 clocks = <&aoss_qmp>;
3220 clock-names = "apb_pc 3211 clock-names = "apb_pclk";
3221 3212
3222 out-ports { 3213 out-ports {
3223 port { 3214 port {
3224 funne 3215 funnel_in0_out_funnel_merg: endpoint {
3225 3216 remote-endpoint = <&funnel_merg_in_funnel_in0>;
3226 }; 3217 };
3227 }; 3218 };
3228 }; 3219 };
3229 3220
3230 in-ports { 3221 in-ports {
3231 #address-cell 3222 #address-cells = <1>;
3232 #size-cells = 3223 #size-cells = <0>;
3233 3224
3234 port@6 { 3225 port@6 {
3235 reg = 3226 reg = <6>;
3236 funne 3227 funnel_in0_in_funnel_qatb: endpoint {
3237 3228 remote-endpoint = <&funnel_qatb_out_funnel_in0>;
3238 }; 3229 };
3239 }; 3230 };
3240 3231
3241 port@7 { 3232 port@7 {
3242 reg = 3233 reg = <7>;
3243 funne 3234 funnel0_in7: endpoint {
3244 3235 remote-endpoint = <&stm_out>;
3245 }; 3236 };
3246 }; 3237 };
3247 }; 3238 };
3248 }; 3239 };
3249 3240
3250 funnel@6042000 { 3241 funnel@6042000 {
3251 compatible = "arm,cor 3242 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3252 reg = <0 0x06042000 0 3243 reg = <0 0x06042000 0 0x1000>;
3253 3244
3254 clocks = <&aoss_qmp>; 3245 clocks = <&aoss_qmp>;
3255 clock-names = "apb_pc 3246 clock-names = "apb_pclk";
3256 3247
3257 out-ports { 3248 out-ports {
3258 port { 3249 port {
3259 funne 3250 funnel_in1_out_funnel_merg: endpoint {
3260 3251 remote-endpoint = <&funnel_merg_in_funnel_in1>;
3261 }; 3252 };
3262 }; 3253 };
3263 }; 3254 };
3264 3255
3265 in-ports { 3256 in-ports {
3266 #address-cell 3257 #address-cells = <1>;
3267 #size-cells = 3258 #size-cells = <0>;
3268 3259
3269 port@4 { 3260 port@4 {
3270 reg = 3261 reg = <4>;
3271 funne 3262 funnel_in1_in_funnel_apss_merg: endpoint {
3272 remot 3263 remote-endpoint = <&funnel_apss_merg_out_funnel_in1>;
3273 }; 3264 };
3274 }; 3265 };
3275 }; 3266 };
3276 }; 3267 };
3277 3268
3278 funnel@6045000 { 3269 funnel@6045000 {
3279 compatible = "arm,cor 3270 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3280 reg = <0 0x06045000 0 3271 reg = <0 0x06045000 0 0x1000>;
3281 3272
3282 clocks = <&aoss_qmp>; 3273 clocks = <&aoss_qmp>;
3283 clock-names = "apb_pc 3274 clock-names = "apb_pclk";
3284 3275
3285 out-ports { 3276 out-ports {
3286 port { 3277 port {
3287 funne 3278 funnel_merg_out_funnel_swao: endpoint {
3288 remot 3279 remote-endpoint = <&funnel_swao_in_funnel_merg>;
3289 }; 3280 };
3290 }; 3281 };
3291 }; 3282 };
3292 3283
3293 in-ports { 3284 in-ports {
3294 #address-cell 3285 #address-cells = <1>;
3295 #size-cells = 3286 #size-cells = <0>;
3296 3287
3297 port@0 { 3288 port@0 {
3298 reg = 3289 reg = <0>;
3299 funne 3290 funnel_merg_in_funnel_in0: endpoint {
3300 remot 3291 remote-endpoint = <&funnel_in0_out_funnel_merg>;
3301 }; 3292 };
3302 }; 3293 };
3303 3294
3304 port@1 { 3295 port@1 {
3305 reg = 3296 reg = <1>;
3306 funne 3297 funnel_merg_in_funnel_in1: endpoint {
3307 remot 3298 remote-endpoint = <&funnel_in1_out_funnel_merg>;
3308 }; 3299 };
3309 }; 3300 };
3310 }; 3301 };
3311 }; 3302 };
3312 3303
3313 replicator@6046000 { 3304 replicator@6046000 {
3314 compatible = "arm,cor 3305 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3315 reg = <0 0x06046000 0 3306 reg = <0 0x06046000 0 0x1000>;
3316 3307
3317 clocks = <&aoss_qmp>; 3308 clocks = <&aoss_qmp>;
3318 clock-names = "apb_pc 3309 clock-names = "apb_pclk";
3319 3310
3320 out-ports { 3311 out-ports {
3321 port { 3312 port {
3322 repli 3313 replicator_out: endpoint {
3323 3314 remote-endpoint = <&etr_in>;
3324 }; 3315 };
3325 }; 3316 };
3326 }; 3317 };
3327 3318
3328 in-ports { 3319 in-ports {
3329 port { 3320 port {
3330 repli 3321 replicator_cx_in_swao_out: endpoint {
3331 3322 remote-endpoint = <&replicator_swao_out_cx_in>;
3332 }; 3323 };
3333 }; 3324 };
3334 }; 3325 };
3335 }; 3326 };
3336 3327
3337 etr@6048000 { 3328 etr@6048000 {
3338 compatible = "arm,cor 3329 compatible = "arm,coresight-tmc", "arm,primecell";
3339 reg = <0 0x06048000 0 3330 reg = <0 0x06048000 0 0x1000>;
3340 3331
3341 clocks = <&aoss_qmp>; 3332 clocks = <&aoss_qmp>;
3342 clock-names = "apb_pc 3333 clock-names = "apb_pclk";
3343 arm,scatter-gather; 3334 arm,scatter-gather;
3344 3335
3345 in-ports { 3336 in-ports {
3346 port { 3337 port {
3347 etr_i 3338 etr_in: endpoint {
3348 3339 remote-endpoint = <&replicator_out>;
3349 }; 3340 };
3350 }; 3341 };
3351 }; 3342 };
3352 }; 3343 };
3353 3344
3354 tpdm@684c000 { 3345 tpdm@684c000 {
3355 compatible = "qcom,co 3346 compatible = "qcom,coresight-tpdm", "arm,primecell";
3356 reg = <0 0x0684c000 0 3347 reg = <0 0x0684c000 0 0x1000>;
3357 3348
3358 clocks = <&aoss_qmp>; 3349 clocks = <&aoss_qmp>;
3359 clock-names = "apb_pc 3350 clock-names = "apb_pclk";
3360 3351
3361 out-ports { 3352 out-ports {
3362 port { 3353 port {
3363 tpdm_ 3354 tpdm_prng_out_tpda_23: endpoint {
3364 3355 remote-endpoint = <&tpda_23_in_tpdm_prng>;
3365 }; 3356 };
3366 }; 3357 };
3367 }; 3358 };
3368 }; 3359 };
3369 3360
3370 funnel@6b04000 { 3361 funnel@6b04000 {
3371 compatible = "arm,cor 3362 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3372 arm,primecell-periphi 3363 arm,primecell-periphid = <0x000bb908>;
3373 3364
3374 reg = <0 0x06b04000 0 3365 reg = <0 0x06b04000 0 0x1000>;
3375 3366
3376 clocks = <&aoss_qmp>; 3367 clocks = <&aoss_qmp>;
3377 clock-names = "apb_pc 3368 clock-names = "apb_pclk";
3378 3369
3379 out-ports { 3370 out-ports {
3380 port { 3371 port {
3381 funne 3372 funnel_swao_out_etf: endpoint {
3382 3373 remote-endpoint = <&etf_in_funnel_swao_out>;
3383 }; 3374 };
3384 }; 3375 };
3385 }; 3376 };
3386 3377
3387 in-ports { 3378 in-ports {
3388 #address-cell 3379 #address-cells = <1>;
3389 #size-cells = 3380 #size-cells = <0>;
3390 3381
3391 port@7 { 3382 port@7 {
3392 reg = 3383 reg = <7>;
3393 funne 3384 funnel_swao_in_funnel_merg: endpoint {
3394 3385 remote-endpoint = <&funnel_merg_out_funnel_swao>;
3395 }; 3386 };
3396 }; 3387 };
3397 }; 3388 };
3398 }; 3389 };
3399 3390
3400 etf@6b05000 { 3391 etf@6b05000 {
3401 compatible = "arm,cor 3392 compatible = "arm,coresight-tmc", "arm,primecell";
3402 reg = <0 0x06b05000 0 3393 reg = <0 0x06b05000 0 0x1000>;
3403 3394
3404 clocks = <&aoss_qmp>; 3395 clocks = <&aoss_qmp>;
3405 clock-names = "apb_pc 3396 clock-names = "apb_pclk";
3406 3397
3407 out-ports { 3398 out-ports {
3408 port { 3399 port {
3409 etf_o 3400 etf_out: endpoint {
3410 3401 remote-endpoint = <&replicator_in>;
3411 }; 3402 };
3412 }; 3403 };
3413 }; 3404 };
3414 3405
3415 in-ports { 3406 in-ports {
3416 3407
3417 port { 3408 port {
3418 etf_i 3409 etf_in_funnel_swao_out: endpoint {
3419 3410 remote-endpoint = <&funnel_swao_out_etf>;
3420 }; 3411 };
3421 }; 3412 };
3422 }; 3413 };
3423 }; 3414 };
3424 3415
3425 replicator@6b06000 { 3416 replicator@6b06000 {
3426 compatible = "arm,cor 3417 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3427 reg = <0 0x06b06000 0 3418 reg = <0 0x06b06000 0 0x1000>;
3428 3419
3429 clocks = <&aoss_qmp>; 3420 clocks = <&aoss_qmp>;
3430 clock-names = "apb_pc 3421 clock-names = "apb_pclk";
3431 3422
3432 out-ports { 3423 out-ports {
3433 port { 3424 port {
3434 repli 3425 replicator_swao_out_cx_in: endpoint {
3435 3426 remote-endpoint = <&replicator_cx_in_swao_out>;
3436 }; 3427 };
3437 }; 3428 };
3438 }; 3429 };
3439 3430
3440 in-ports { 3431 in-ports {
3441 port { 3432 port {
3442 repli 3433 replicator_in: endpoint {
3443 3434 remote-endpoint = <&etf_out>;
3444 }; 3435 };
3445 }; 3436 };
3446 }; 3437 };
3447 }; 3438 };
3448 3439
3449 tpdm@6c08000 { 3440 tpdm@6c08000 {
3450 compatible = "qcom,co 3441 compatible = "qcom,coresight-tpdm", "arm,primecell";
3451 reg = <0 0x06c08000 0 3442 reg = <0 0x06c08000 0 0x1000>;
3452 3443
3453 clocks = <&aoss_qmp>; 3444 clocks = <&aoss_qmp>;
3454 clock-names = "apb_pc 3445 clock-names = "apb_pclk";
3455 3446
3456 out-ports { 3447 out-ports {
3457 port { 3448 port {
3458 tpdm_ 3449 tpdm_mm_out_funnel_dl_mm: endpoint {
3459 3450 remote-endpoint = <&funnel_dl_mm_in_tpdm_mm>;
3460 }; 3451 };
3461 }; 3452 };
3462 }; 3453 };
3463 }; 3454 };
3464 3455
3465 funnel@6c0b000 { 3456 funnel@6c0b000 {
3466 compatible = "arm,cor 3457 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3467 reg = <0 0x06c0b000 0 3458 reg = <0 0x06c0b000 0 0x1000>;
3468 3459
3469 clocks = <&aoss_qmp>; 3460 clocks = <&aoss_qmp>;
3470 clock-names = "apb_pc 3461 clock-names = "apb_pclk";
3471 3462
3472 out-ports { 3463 out-ports {
3473 port { 3464 port {
3474 funne 3465 funnel_dl_mm_out_funnel_dl_center: endpoint {
3475 remot 3466 remote-endpoint = <&funnel_dl_center_in_funnel_dl_mm>;
3476 }; 3467 };
3477 }; 3468 };
3478 }; 3469 };
3479 3470
3480 in-ports { 3471 in-ports {
3481 #address-cell 3472 #address-cells = <1>;
3482 #size-cells = 3473 #size-cells = <0>;
3483 3474
3484 port@3 { 3475 port@3 {
3485 reg = 3476 reg = <3>;
3486 funne 3477 funnel_dl_mm_in_tpdm_mm: endpoint {
3487 3478 remote-endpoint = <&tpdm_mm_out_funnel_dl_mm>;
3488 }; 3479 };
3489 }; 3480 };
3490 }; 3481 };
3491 }; 3482 };
3492 3483
3493 funnel@6c2d000 { 3484 funnel@6c2d000 {
3494 compatible = "arm,cor 3485 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3495 reg = <0 0x06c2d000 0 3486 reg = <0 0x06c2d000 0 0x1000>;
3496 3487
3497 clocks = <&aoss_qmp>; 3488 clocks = <&aoss_qmp>;
3498 clock-names = "apb_pc 3489 clock-names = "apb_pclk";
3499 3490
3500 out-ports { 3491 out-ports {
3501 port { 3492 port {
3502 tpdm_ 3493 tpdm_mm_out_tpda9: endpoint {
3503 3494 remote-endpoint = <&tpda_9_in_tpdm_mm>;
3504 }; 3495 };
3505 }; 3496 };
3506 }; 3497 };
3507 3498
3508 in-ports { 3499 in-ports {
3509 #address-cell 3500 #address-cells = <1>;
3510 #size-cells = 3501 #size-cells = <0>;
3511 3502
3512 port@2 { 3503 port@2 {
3513 reg = 3504 reg = <2>;
3514 funne 3505 funnel_dl_center_in_funnel_dl_mm: endpoint {
3515 remot 3506 remote-endpoint = <&funnel_dl_mm_out_funnel_dl_center>;
3516 }; 3507 };
3517 }; 3508 };
3518 }; 3509 };
3519 }; 3510 };
3520 3511
3521 etm@7040000 { 3512 etm@7040000 {
3522 compatible = "arm,cor 3513 compatible = "arm,coresight-etm4x", "arm,primecell";
3523 reg = <0 0x07040000 0 3514 reg = <0 0x07040000 0 0x1000>;
3524 3515
3525 cpu = <&CPU0>; 3516 cpu = <&CPU0>;
3526 3517
3527 clocks = <&aoss_qmp>; 3518 clocks = <&aoss_qmp>;
3528 clock-names = "apb_pc 3519 clock-names = "apb_pclk";
3529 arm,coresight-loses-c 3520 arm,coresight-loses-context-with-cpu;
3530 3521
3531 out-ports { 3522 out-ports {
3532 port { 3523 port {
3533 etm0_ 3524 etm0_out: endpoint {
3534 3525 remote-endpoint = <&apss_funnel_in0>;
3535 }; 3526 };
3536 }; 3527 };
3537 }; 3528 };
3538 }; 3529 };
3539 3530
3540 etm@7140000 { 3531 etm@7140000 {
3541 compatible = "arm,cor 3532 compatible = "arm,coresight-etm4x", "arm,primecell";
3542 reg = <0 0x07140000 0 3533 reg = <0 0x07140000 0 0x1000>;
3543 3534
3544 cpu = <&CPU1>; 3535 cpu = <&CPU1>;
3545 3536
3546 clocks = <&aoss_qmp>; 3537 clocks = <&aoss_qmp>;
3547 clock-names = "apb_pc 3538 clock-names = "apb_pclk";
3548 arm,coresight-loses-c 3539 arm,coresight-loses-context-with-cpu;
3549 3540
3550 out-ports { 3541 out-ports {
3551 port { 3542 port {
3552 etm1_ 3543 etm1_out: endpoint {
3553 3544 remote-endpoint = <&apss_funnel_in1>;
3554 }; 3545 };
3555 }; 3546 };
3556 }; 3547 };
3557 }; 3548 };
3558 3549
3559 etm@7240000 { 3550 etm@7240000 {
3560 compatible = "arm,cor 3551 compatible = "arm,coresight-etm4x", "arm,primecell";
3561 reg = <0 0x07240000 0 3552 reg = <0 0x07240000 0 0x1000>;
3562 3553
3563 cpu = <&CPU2>; 3554 cpu = <&CPU2>;
3564 3555
3565 clocks = <&aoss_qmp>; 3556 clocks = <&aoss_qmp>;
3566 clock-names = "apb_pc 3557 clock-names = "apb_pclk";
3567 arm,coresight-loses-c 3558 arm,coresight-loses-context-with-cpu;
3568 3559
3569 out-ports { 3560 out-ports {
3570 port { 3561 port {
3571 etm2_ 3562 etm2_out: endpoint {
3572 3563 remote-endpoint = <&apss_funnel_in2>;
3573 }; 3564 };
3574 }; 3565 };
3575 }; 3566 };
3576 }; 3567 };
3577 3568
3578 etm@7340000 { 3569 etm@7340000 {
3579 compatible = "arm,cor 3570 compatible = "arm,coresight-etm4x", "arm,primecell";
3580 reg = <0 0x07340000 0 3571 reg = <0 0x07340000 0 0x1000>;
3581 3572
3582 cpu = <&CPU3>; 3573 cpu = <&CPU3>;
3583 3574
3584 clocks = <&aoss_qmp>; 3575 clocks = <&aoss_qmp>;
3585 clock-names = "apb_pc 3576 clock-names = "apb_pclk";
3586 arm,coresight-loses-c 3577 arm,coresight-loses-context-with-cpu;
3587 3578
3588 out-ports { 3579 out-ports {
3589 port { 3580 port {
3590 etm3_ 3581 etm3_out: endpoint {
3591 3582 remote-endpoint = <&apss_funnel_in3>;
3592 }; 3583 };
3593 }; 3584 };
3594 }; 3585 };
3595 }; 3586 };
3596 3587
3597 etm@7440000 { 3588 etm@7440000 {
3598 compatible = "arm,cor 3589 compatible = "arm,coresight-etm4x", "arm,primecell";
3599 reg = <0 0x07440000 0 3590 reg = <0 0x07440000 0 0x1000>;
3600 3591
3601 cpu = <&CPU4>; 3592 cpu = <&CPU4>;
3602 3593
3603 clocks = <&aoss_qmp>; 3594 clocks = <&aoss_qmp>;
3604 clock-names = "apb_pc 3595 clock-names = "apb_pclk";
3605 arm,coresight-loses-c 3596 arm,coresight-loses-context-with-cpu;
3606 3597
3607 out-ports { 3598 out-ports {
3608 port { 3599 port {
3609 etm4_ 3600 etm4_out: endpoint {
3610 3601 remote-endpoint = <&apss_funnel_in4>;
3611 }; 3602 };
3612 }; 3603 };
3613 }; 3604 };
3614 }; 3605 };
3615 3606
3616 etm@7540000 { 3607 etm@7540000 {
3617 compatible = "arm,cor 3608 compatible = "arm,coresight-etm4x", "arm,primecell";
3618 reg = <0 0x07540000 0 3609 reg = <0 0x07540000 0 0x1000>;
3619 3610
3620 cpu = <&CPU5>; 3611 cpu = <&CPU5>;
3621 3612
3622 clocks = <&aoss_qmp>; 3613 clocks = <&aoss_qmp>;
3623 clock-names = "apb_pc 3614 clock-names = "apb_pclk";
3624 arm,coresight-loses-c 3615 arm,coresight-loses-context-with-cpu;
3625 3616
3626 out-ports { 3617 out-ports {
3627 port { 3618 port {
3628 etm5_ 3619 etm5_out: endpoint {
3629 3620 remote-endpoint = <&apss_funnel_in5>;
3630 }; 3621 };
3631 }; 3622 };
3632 }; 3623 };
3633 }; 3624 };
3634 3625
3635 etm@7640000 { 3626 etm@7640000 {
3636 compatible = "arm,cor 3627 compatible = "arm,coresight-etm4x", "arm,primecell";
3637 reg = <0 0x07640000 0 3628 reg = <0 0x07640000 0 0x1000>;
3638 3629
3639 cpu = <&CPU6>; 3630 cpu = <&CPU6>;
3640 3631
3641 clocks = <&aoss_qmp>; 3632 clocks = <&aoss_qmp>;
3642 clock-names = "apb_pc 3633 clock-names = "apb_pclk";
3643 arm,coresight-loses-c 3634 arm,coresight-loses-context-with-cpu;
3644 3635
3645 out-ports { 3636 out-ports {
3646 port { 3637 port {
3647 etm6_ 3638 etm6_out: endpoint {
3648 3639 remote-endpoint = <&apss_funnel_in6>;
3649 }; 3640 };
3650 }; 3641 };
3651 }; 3642 };
3652 }; 3643 };
3653 3644
3654 etm@7740000 { 3645 etm@7740000 {
3655 compatible = "arm,cor 3646 compatible = "arm,coresight-etm4x", "arm,primecell";
3656 reg = <0 0x07740000 0 3647 reg = <0 0x07740000 0 0x1000>;
3657 3648
3658 cpu = <&CPU7>; 3649 cpu = <&CPU7>;
3659 3650
3660 clocks = <&aoss_qmp>; 3651 clocks = <&aoss_qmp>;
3661 clock-names = "apb_pc 3652 clock-names = "apb_pclk";
3662 arm,coresight-loses-c 3653 arm,coresight-loses-context-with-cpu;
3663 3654
3664 out-ports { 3655 out-ports {
3665 port { 3656 port {
3666 etm7_ 3657 etm7_out: endpoint {
3667 3658 remote-endpoint = <&apss_funnel_in7>;
3668 }; 3659 };
3669 }; 3660 };
3670 }; 3661 };
3671 }; 3662 };
3672 3663
3673 funnel@7800000 { 3664 funnel@7800000 {
3674 compatible = "arm,cor 3665 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3675 reg = <0 0x07800000 0 3666 reg = <0 0x07800000 0 0x1000>;
3676 3667
3677 clocks = <&aoss_qmp>; 3668 clocks = <&aoss_qmp>;
3678 clock-names = "apb_pc 3669 clock-names = "apb_pclk";
3679 3670
3680 out-ports { 3671 out-ports {
3681 port { 3672 port {
3682 funne 3673 funnel_apss_out_funnel_apss_merg: endpoint {
3683 remot 3674 remote-endpoint = <&funnel_apss_merg_in_funnel_apss>;
3684 }; 3675 };
3685 }; 3676 };
3686 }; 3677 };
3687 3678
3688 in-ports { 3679 in-ports {
3689 #address-cell 3680 #address-cells = <1>;
3690 #size-cells = 3681 #size-cells = <0>;
3691 3682
3692 port@0 { 3683 port@0 {
3693 reg = 3684 reg = <0>;
3694 apss_ 3685 apss_funnel_in0: endpoint {
3695 3686 remote-endpoint = <&etm0_out>;
3696 }; 3687 };
3697 }; 3688 };
3698 3689
3699 port@1 { 3690 port@1 {
3700 reg = 3691 reg = <1>;
3701 apss_ 3692 apss_funnel_in1: endpoint {
3702 3693 remote-endpoint = <&etm1_out>;
3703 }; 3694 };
3704 }; 3695 };
3705 3696
3706 port@2 { 3697 port@2 {
3707 reg = 3698 reg = <2>;
3708 apss_ 3699 apss_funnel_in2: endpoint {
3709 3700 remote-endpoint = <&etm2_out>;
3710 }; 3701 };
3711 }; 3702 };
3712 3703
3713 port@3 { 3704 port@3 {
3714 reg = 3705 reg = <3>;
3715 apss_ 3706 apss_funnel_in3: endpoint {
3716 3707 remote-endpoint = <&etm3_out>;
3717 }; 3708 };
3718 }; 3709 };
3719 3710
3720 port@4 { 3711 port@4 {
3721 reg = 3712 reg = <4>;
3722 apss_ 3713 apss_funnel_in4: endpoint {
3723 3714 remote-endpoint = <&etm4_out>;
3724 }; 3715 };
3725 }; 3716 };
3726 3717
3727 port@5 { 3718 port@5 {
3728 reg = 3719 reg = <5>;
3729 apss_ 3720 apss_funnel_in5: endpoint {
3730 3721 remote-endpoint = <&etm5_out>;
3731 }; 3722 };
3732 }; 3723 };
3733 3724
3734 port@6 { 3725 port@6 {
3735 reg = 3726 reg = <6>;
3736 apss_ 3727 apss_funnel_in6: endpoint {
3737 3728 remote-endpoint = <&etm6_out>;
3738 }; 3729 };
3739 }; 3730 };
3740 3731
3741 port@7 { 3732 port@7 {
3742 reg = 3733 reg = <7>;
3743 apss_ 3734 apss_funnel_in7: endpoint {
3744 3735 remote-endpoint = <&etm7_out>;
3745 }; 3736 };
3746 }; 3737 };
3747 }; 3738 };
3748 }; 3739 };
3749 3740
3750 funnel@7810000 { 3741 funnel@7810000 {
3751 compatible = "arm,cor 3742 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3752 reg = <0 0x07810000 0 3743 reg = <0 0x07810000 0 0x1000>;
3753 3744
3754 clocks = <&aoss_qmp>; 3745 clocks = <&aoss_qmp>;
3755 clock-names = "apb_pc 3746 clock-names = "apb_pclk";
3756 3747
3757 out-ports { 3748 out-ports {
3758 port { 3749 port {
3759 funne 3750 funnel_apss_merg_out_funnel_in1: endpoint {
3760 remot 3751 remote-endpoint = <&funnel_in1_in_funnel_apss_merg>;
3761 }; 3752 };
3762 }; 3753 };
3763 }; 3754 };
3764 3755
3765 in-ports { 3756 in-ports {
3766 port { 3757 port {
3767 funne 3758 funnel_apss_merg_in_funnel_apss: endpoint {
3768 remot 3759 remote-endpoint = <&funnel_apss_out_funnel_apss_merg>;
3769 }; 3760 };
3770 }; 3761 };
3771 }; 3762 };
3772 }; 3763 };
3773 3764
3774 cdsp: remoteproc@8300000 { 3765 cdsp: remoteproc@8300000 {
3775 compatible = "qcom,sm 3766 compatible = "qcom,sm8250-cdsp-pas";
3776 reg = <0 0x08300000 0 3767 reg = <0 0x08300000 0 0x10000>;
3777 3768
3778 interrupts-extended = 3769 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
3779 3770 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
3780 3771 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
3781 3772 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
3782 3773 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
3783 interrupt-names = "wd 3774 interrupt-names = "wdog", "fatal", "ready",
3784 "ha 3775 "handover", "stop-ack";
3785 3776
3786 clocks = <&rpmhcc RPM 3777 clocks = <&rpmhcc RPMH_CXO_CLK>;
3787 clock-names = "xo"; 3778 clock-names = "xo";
3788 3779
3789 power-domains = <&rpm 3780 power-domains = <&rpmhpd RPMHPD_CX>;
3790 3781
3791 memory-region = <&cds 3782 memory-region = <&cdsp_mem>;
3792 3783
3793 qcom,qmp = <&aoss_qmp 3784 qcom,qmp = <&aoss_qmp>;
3794 3785
3795 qcom,smem-states = <& 3786 qcom,smem-states = <&smp2p_cdsp_out 0>;
3796 qcom,smem-state-names 3787 qcom,smem-state-names = "stop";
3797 3788
3798 status = "disabled"; 3789 status = "disabled";
3799 3790
3800 glink-edge { 3791 glink-edge {
3801 interrupts-ex 3792 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
3802 3793 IPCC_MPROC_SIGNAL_GLINK_QMP
3803 3794 IRQ_TYPE_EDGE_RISING>;
3804 mboxes = <&ip 3795 mboxes = <&ipcc IPCC_CLIENT_CDSP
3805 3796 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3806 3797
3807 label = "cdsp 3798 label = "cdsp";
3808 qcom,remote-p 3799 qcom,remote-pid = <5>;
3809 3800
3810 fastrpc { 3801 fastrpc {
3811 compa 3802 compatible = "qcom,fastrpc";
3812 qcom, 3803 qcom,glink-channels = "fastrpcglink-apps-dsp";
3813 label 3804 label = "cdsp";
3814 qcom, 3805 qcom,non-secure-domain;
3815 #addr 3806 #address-cells = <1>;
3816 #size 3807 #size-cells = <0>;
3817 3808
3818 compu 3809 compute-cb@1 {
3819 3810 compatible = "qcom,fastrpc-compute-cb";
3820 3811 reg = <1>;
3821 3812 iommus = <&apps_smmu 0x1001 0x0460>;
3822 }; 3813 };
3823 3814
3824 compu 3815 compute-cb@2 {
3825 3816 compatible = "qcom,fastrpc-compute-cb";
3826 3817 reg = <2>;
3827 3818 iommus = <&apps_smmu 0x1002 0x0460>;
3828 }; 3819 };
3829 3820
3830 compu 3821 compute-cb@3 {
3831 3822 compatible = "qcom,fastrpc-compute-cb";
3832 3823 reg = <3>;
3833 3824 iommus = <&apps_smmu 0x1003 0x0460>;
3834 }; 3825 };
3835 3826
3836 compu 3827 compute-cb@4 {
3837 3828 compatible = "qcom,fastrpc-compute-cb";
3838 3829 reg = <4>;
3839 3830 iommus = <&apps_smmu 0x1004 0x0460>;
3840 }; 3831 };
3841 3832
3842 compu 3833 compute-cb@5 {
3843 3834 compatible = "qcom,fastrpc-compute-cb";
3844 3835 reg = <5>;
3845 3836 iommus = <&apps_smmu 0x1005 0x0460>;
3846 }; 3837 };
3847 3838
3848 compu 3839 compute-cb@6 {
3849 3840 compatible = "qcom,fastrpc-compute-cb";
3850 3841 reg = <6>;
3851 3842 iommus = <&apps_smmu 0x1006 0x0460>;
3852 }; 3843 };
3853 3844
3854 compu 3845 compute-cb@7 {
3855 3846 compatible = "qcom,fastrpc-compute-cb";
3856 3847 reg = <7>;
3857 3848 iommus = <&apps_smmu 0x1007 0x0460>;
3858 }; 3849 };
3859 3850
3860 compu 3851 compute-cb@8 {
3861 3852 compatible = "qcom,fastrpc-compute-cb";
3862 3853 reg = <8>;
3863 3854 iommus = <&apps_smmu 0x1008 0x0460>;
3864 }; 3855 };
3865 3856
3866 /* no 3857 /* note: secure cb9 in downstream */
3867 }; 3858 };
3868 }; 3859 };
3869 }; 3860 };
3870 3861
3871 usb_1_hsphy: phy@88e3000 { 3862 usb_1_hsphy: phy@88e3000 {
3872 compatible = "qcom,sm 3863 compatible = "qcom,sm8250-usb-hs-phy",
3873 "qcom,us 3864 "qcom,usb-snps-hs-7nm-phy";
3874 reg = <0 0x088e3000 0 3865 reg = <0 0x088e3000 0 0x400>;
3875 status = "disabled"; 3866 status = "disabled";
3876 #phy-cells = <0>; 3867 #phy-cells = <0>;
3877 3868
3878 clocks = <&rpmhcc RPM 3869 clocks = <&rpmhcc RPMH_CXO_CLK>;
3879 clock-names = "ref"; 3870 clock-names = "ref";
3880 3871
3881 resets = <&gcc GCC_QU 3872 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3882 }; 3873 };
3883 3874
3884 usb_2_hsphy: phy@88e4000 { 3875 usb_2_hsphy: phy@88e4000 {
3885 compatible = "qcom,sm 3876 compatible = "qcom,sm8250-usb-hs-phy",
3886 "qcom,us 3877 "qcom,usb-snps-hs-7nm-phy";
3887 reg = <0 0x088e4000 0 3878 reg = <0 0x088e4000 0 0x400>;
3888 status = "disabled"; 3879 status = "disabled";
3889 #phy-cells = <0>; 3880 #phy-cells = <0>;
3890 3881
3891 clocks = <&rpmhcc RPM 3882 clocks = <&rpmhcc RPMH_CXO_CLK>;
3892 clock-names = "ref"; 3883 clock-names = "ref";
3893 3884
3894 resets = <&gcc GCC_QU 3885 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3895 }; 3886 };
3896 3887
3897 usb_1_qmpphy: phy@88e8000 { 3888 usb_1_qmpphy: phy@88e8000 {
3898 compatible = "qcom,sm 3889 compatible = "qcom,sm8250-qmp-usb3-dp-phy";
3899 reg = <0 0x088e8000 0 3890 reg = <0 0x088e8000 0 0x3000>;
3900 status = "disabled"; 3891 status = "disabled";
3901 3892
3902 clocks = <&gcc GCC_US 3893 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
3903 <&rpmhcc RPM 3894 <&rpmhcc RPMH_CXO_CLK>,
3904 <&gcc GCC_US 3895 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
3905 <&gcc GCC_US 3896 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3906 clock-names = "aux", 3897 clock-names = "aux",
3907 "ref", 3898 "ref",
3908 "com_au 3899 "com_aux",
3909 "usb3_p 3900 "usb3_pipe";
3910 3901
3911 resets = <&gcc GCC_US 3902 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
3912 <&gcc GCC_US 3903 <&gcc GCC_USB3_PHY_PRIM_BCR>;
3913 reset-names = "phy", 3904 reset-names = "phy", "common";
3914 3905
3915 #clock-cells = <1>; 3906 #clock-cells = <1>;
3916 #phy-cells = <1>; 3907 #phy-cells = <1>;
3917 3908
3918 orientation-switch; <<
3919 <<
3920 ports { 3909 ports {
3921 #address-cell 3910 #address-cells = <1>;
3922 #size-cells = 3911 #size-cells = <0>;
3923 3912
3924 port@0 { 3913 port@0 {
3925 reg = 3914 reg = <0>;
3926 usb_1 3915 usb_1_qmpphy_out: endpoint {};
3927 }; 3916 };
3928 3917
3929 port@1 { 3918 port@1 {
3930 reg = 3919 reg = <1>;
3931 <<
3932 usb_1 <<
3933 <<
3934 }; <<
3935 }; 3920 };
3936 3921
3937 port@2 { 3922 port@2 {
3938 reg = 3923 reg = <2>;
3939 3924
3940 usb_1 3925 usb_1_qmpphy_dp_in: endpoint {};
3941 }; 3926 };
3942 }; 3927 };
3943 }; 3928 };
3944 3929
3945 usb_2_qmpphy: phy@88eb000 { 3930 usb_2_qmpphy: phy@88eb000 {
3946 compatible = "qcom,sm 3931 compatible = "qcom,sm8250-qmp-usb3-uni-phy";
3947 reg = <0 0x088eb000 0 3932 reg = <0 0x088eb000 0 0x1000>;
3948 3933
3949 clocks = <&gcc GCC_US 3934 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
3950 <&gcc GCC_US 3935 <&gcc GCC_USB3_SEC_CLKREF_EN>,
3951 <&gcc GCC_US 3936 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
3952 <&gcc GCC_US 3937 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
3953 clock-names = "aux", 3938 clock-names = "aux",
3954 "ref", 3939 "ref",
3955 "com_au 3940 "com_aux",
3956 "pipe"; 3941 "pipe";
3957 clock-output-names = 3942 clock-output-names = "usb3_uni_phy_pipe_clk_src";
3958 #clock-cells = <0>; 3943 #clock-cells = <0>;
3959 #phy-cells = <0>; 3944 #phy-cells = <0>;
3960 3945
3961 resets = <&gcc GCC_US 3946 resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
3962 <&gcc GCC_US 3947 <&gcc GCC_USB3PHY_PHY_SEC_BCR>;
3963 reset-names = "phy", 3948 reset-names = "phy",
3964 "phy_ph 3949 "phy_phy";
3965 3950
3966 status = "disabled"; 3951 status = "disabled";
3967 }; 3952 };
3968 3953
3969 sdhc_2: mmc@8804000 { 3954 sdhc_2: mmc@8804000 {
3970 compatible = "qcom,sm 3955 compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
3971 reg = <0 0x08804000 0 3956 reg = <0 0x08804000 0 0x1000>;
3972 3957
3973 interrupts = <GIC_SPI 3958 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
3974 <GIC_SPI 3959 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
3975 interrupt-names = "hc 3960 interrupt-names = "hc_irq", "pwr_irq";
3976 3961
3977 clocks = <&gcc GCC_SD 3962 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3978 <&gcc GCC_SD 3963 <&gcc GCC_SDCC2_APPS_CLK>,
3979 <&rpmhcc RPM 3964 <&rpmhcc RPMH_CXO_CLK>;
3980 clock-names = "iface" 3965 clock-names = "iface", "core", "xo";
3981 iommus = <&apps_smmu 3966 iommus = <&apps_smmu 0x4a0 0x0>;
3982 qcom,dll-config = <0x 3967 qcom,dll-config = <0x0007642c>;
3983 qcom,ddr-config = <0x 3968 qcom,ddr-config = <0x80040868>;
3984 power-domains = <&rpm 3969 power-domains = <&rpmhpd RPMHPD_CX>;
3985 operating-points-v2 = 3970 operating-points-v2 = <&sdhc2_opp_table>;
3986 3971
3987 status = "disabled"; 3972 status = "disabled";
3988 3973
3989 sdhc2_opp_table: opp- 3974 sdhc2_opp_table: opp-table {
3990 compatible = 3975 compatible = "operating-points-v2";
3991 3976
3992 opp-19200000 3977 opp-19200000 {
3993 opp-h 3978 opp-hz = /bits/ 64 <19200000>;
3994 requi 3979 required-opps = <&rpmhpd_opp_min_svs>;
3995 }; 3980 };
3996 3981
3997 opp-50000000 3982 opp-50000000 {
3998 opp-h 3983 opp-hz = /bits/ 64 <50000000>;
3999 requi 3984 required-opps = <&rpmhpd_opp_low_svs>;
4000 }; 3985 };
4001 3986
4002 opp-100000000 3987 opp-100000000 {
4003 opp-h 3988 opp-hz = /bits/ 64 <100000000>;
4004 requi 3989 required-opps = <&rpmhpd_opp_svs>;
4005 }; 3990 };
4006 3991
4007 opp-202000000 3992 opp-202000000 {
4008 opp-h 3993 opp-hz = /bits/ 64 <202000000>;
4009 requi 3994 required-opps = <&rpmhpd_opp_svs_l1>;
4010 }; 3995 };
4011 }; 3996 };
4012 }; 3997 };
4013 3998
4014 pmu@9091000 { 3999 pmu@9091000 {
4015 compatible = "qcom,sm 4000 compatible = "qcom,sm8250-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
4016 reg = <0 0x09091000 0 4001 reg = <0 0x09091000 0 0x1000>;
4017 4002
4018 interrupts = <GIC_SPI 4003 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
4019 4004
4020 interconnects = <&mc_ 4005 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI_CH0 3>;
4021 4006
4022 operating-points-v2 = 4007 operating-points-v2 = <&llcc_bwmon_opp_table>;
4023 4008
4024 llcc_bwmon_opp_table: 4009 llcc_bwmon_opp_table: opp-table {
4025 compatible = 4010 compatible = "operating-points-v2";
4026 4011
4027 opp-800000 { 4012 opp-800000 {
4028 opp-p 4013 opp-peak-kBps = <(200 * 4 * 1000)>;
4029 }; 4014 };
4030 4015
4031 opp-1200000 { 4016 opp-1200000 {
4032 opp-p 4017 opp-peak-kBps = <(300 * 4 * 1000)>;
4033 }; 4018 };
4034 4019
4035 opp-1804000 { 4020 opp-1804000 {
4036 opp-p 4021 opp-peak-kBps = <(451 * 4 * 1000)>;
4037 }; 4022 };
4038 4023
4039 opp-2188000 { 4024 opp-2188000 {
4040 opp-p 4025 opp-peak-kBps = <(547 * 4 * 1000)>;
4041 }; 4026 };
4042 4027
4043 opp-2724000 { 4028 opp-2724000 {
4044 opp-p 4029 opp-peak-kBps = <(681 * 4 * 1000)>;
4045 }; 4030 };
4046 4031
4047 opp-3072000 { 4032 opp-3072000 {
4048 opp-p 4033 opp-peak-kBps = <(768 * 4 * 1000)>;
4049 }; 4034 };
4050 4035
4051 opp-4068000 { 4036 opp-4068000 {
4052 opp-p 4037 opp-peak-kBps = <(1017 * 4 * 1000)>;
4053 }; 4038 };
4054 4039
4055 /* 1353 MHz, 4040 /* 1353 MHz, LPDDR4X */
4056 4041
4057 opp-6220000 { 4042 opp-6220000 {
4058 opp-p 4043 opp-peak-kBps = <(1555 * 4 * 1000)>;
4059 }; 4044 };
4060 4045
4061 opp-7216000 { 4046 opp-7216000 {
4062 opp-p 4047 opp-peak-kBps = <(1804 * 4 * 1000)>;
4063 }; 4048 };
4064 4049
4065 opp-8368000 { 4050 opp-8368000 {
4066 opp-p 4051 opp-peak-kBps = <(2092 * 4 * 1000)>;
4067 }; 4052 };
4068 4053
4069 /* LPDDR5 */ 4054 /* LPDDR5 */
4070 opp-10944000 4055 opp-10944000 {
4071 opp-p 4056 opp-peak-kBps = <(2736 * 4 * 1000)>;
4072 }; 4057 };
4073 }; 4058 };
4074 }; 4059 };
4075 4060
4076 pmu@90b6400 { 4061 pmu@90b6400 {
4077 compatible = "qcom,sm 4062 compatible = "qcom,sm8250-cpu-bwmon", "qcom,sdm845-bwmon";
4078 reg = <0 0x090b6400 0 4063 reg = <0 0x090b6400 0 0x600>;
4079 4064
4080 interrupts = <GIC_SPI 4065 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
4081 4066
4082 interconnects = <&gem 4067 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &gem_noc SLAVE_LLCC 3>;
4083 operating-points-v2 = 4068 operating-points-v2 = <&cpu_bwmon_opp_table>;
4084 4069
4085 cpu_bwmon_opp_table: 4070 cpu_bwmon_opp_table: opp-table {
4086 compatible = 4071 compatible = "operating-points-v2";
4087 4072
4088 opp-800000 { 4073 opp-800000 {
4089 opp-p 4074 opp-peak-kBps = <(200 * 4 * 1000)>;
4090 }; 4075 };
4091 4076
4092 opp-1804000 { 4077 opp-1804000 {
4093 opp-p 4078 opp-peak-kBps = <(451 * 4 * 1000)>;
4094 }; 4079 };
4095 4080
4096 opp-2188000 { 4081 opp-2188000 {
4097 opp-p 4082 opp-peak-kBps = <(547 * 4 * 1000)>;
4098 }; 4083 };
4099 4084
4100 opp-2724000 { 4085 opp-2724000 {
4101 opp-p 4086 opp-peak-kBps = <(681 * 4 * 1000)>;
4102 }; 4087 };
4103 4088
4104 opp-3072000 { 4089 opp-3072000 {
4105 opp-p 4090 opp-peak-kBps = <(768 * 4 * 1000)>;
4106 }; 4091 };
4107 4092
4108 /* 1017MHz, 1 4093 /* 1017MHz, 1353 MHz, LPDDR4X */
4109 4094
4110 opp-6220000 { 4095 opp-6220000 {
4111 opp-p 4096 opp-peak-kBps = <(1555 * 4 * 1000)>;
4112 }; 4097 };
4113 4098
4114 opp-6832000 { 4099 opp-6832000 {
4115 opp-p 4100 opp-peak-kBps = <(1708 * 4 * 1000)>;
4116 }; 4101 };
4117 4102
4118 opp-8368000 { 4103 opp-8368000 {
4119 opp-p 4104 opp-peak-kBps = <(2092 * 4 * 1000)>;
4120 }; 4105 };
4121 4106
4122 /* 2133MHz, L 4107 /* 2133MHz, LPDDR4X */
4123 4108
4124 /* LPDDR5 */ 4109 /* LPDDR5 */
4125 opp-10944000 4110 opp-10944000 {
4126 opp-p 4111 opp-peak-kBps = <(2736 * 4 * 1000)>;
4127 }; 4112 };
4128 4113
4129 /* LPDDR5 */ 4114 /* LPDDR5 */
4130 opp-12784000 4115 opp-12784000 {
4131 opp-p 4116 opp-peak-kBps = <(3196 * 4 * 1000)>;
4132 }; 4117 };
4133 }; 4118 };
4134 }; 4119 };
4135 4120
4136 dc_noc: interconnect@90c0000 4121 dc_noc: interconnect@90c0000 {
4137 compatible = "qcom,sm 4122 compatible = "qcom,sm8250-dc-noc";
4138 reg = <0 0x090c0000 0 4123 reg = <0 0x090c0000 0 0x4200>;
4139 #interconnect-cells = 4124 #interconnect-cells = <2>;
4140 qcom,bcm-voters = <&a 4125 qcom,bcm-voters = <&apps_bcm_voter>;
4141 }; 4126 };
4142 4127
4143 gem_noc: interconnect@9100000 4128 gem_noc: interconnect@9100000 {
4144 compatible = "qcom,sm 4129 compatible = "qcom,sm8250-gem-noc";
4145 reg = <0 0x09100000 0 4130 reg = <0 0x09100000 0 0xb4000>;
4146 #interconnect-cells = 4131 #interconnect-cells = <2>;
4147 qcom,bcm-voters = <&a 4132 qcom,bcm-voters = <&apps_bcm_voter>;
4148 }; 4133 };
4149 4134
4150 npu_noc: interconnect@9990000 4135 npu_noc: interconnect@9990000 {
4151 compatible = "qcom,sm 4136 compatible = "qcom,sm8250-npu-noc";
4152 reg = <0 0x09990000 0 4137 reg = <0 0x09990000 0 0x1600>;
4153 #interconnect-cells = 4138 #interconnect-cells = <2>;
4154 qcom,bcm-voters = <&a 4139 qcom,bcm-voters = <&apps_bcm_voter>;
4155 }; 4140 };
4156 4141
4157 usb_1: usb@a6f8800 { 4142 usb_1: usb@a6f8800 {
4158 compatible = "qcom,sm 4143 compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
4159 reg = <0 0x0a6f8800 0 4144 reg = <0 0x0a6f8800 0 0x400>;
4160 status = "disabled"; 4145 status = "disabled";
4161 #address-cells = <2>; 4146 #address-cells = <2>;
4162 #size-cells = <2>; 4147 #size-cells = <2>;
4163 ranges; 4148 ranges;
4164 dma-ranges; 4149 dma-ranges;
4165 4150
4166 clocks = <&gcc GCC_CF 4151 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
4167 <&gcc GCC_US 4152 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
4168 <&gcc GCC_AG 4153 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
4169 <&gcc GCC_US 4154 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
4170 <&gcc GCC_US 4155 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4171 <&gcc GCC_US 4156 <&gcc GCC_USB3_SEC_CLKREF_EN>;
4172 clock-names = "cfg_no 4157 clock-names = "cfg_noc",
4173 "core", 4158 "core",
4174 "iface" 4159 "iface",
4175 "sleep" 4160 "sleep",
4176 "mock_u 4161 "mock_utmi",
4177 "xo"; 4162 "xo";
4178 4163
4179 assigned-clocks = <&g 4164 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4180 <&g 4165 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
4181 assigned-clock-rates 4166 assigned-clock-rates = <19200000>, <200000000>;
4182 4167
4183 interrupts-extended = 4168 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
4184 4169 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
4185 4170 <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
4186 4171 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
4187 4172 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
4188 interrupt-names = "pw 4173 interrupt-names = "pwr_event",
4189 "hs 4174 "hs_phy_irq",
4190 "dp 4175 "dp_hs_phy_irq",
4191 "dm 4176 "dm_hs_phy_irq",
4192 "ss 4177 "ss_phy_irq";
4193 4178
4194 power-domains = <&gcc 4179 power-domains = <&gcc USB30_PRIM_GDSC>;
4195 wakeup-source; 4180 wakeup-source;
4196 4181
4197 resets = <&gcc GCC_US 4182 resets = <&gcc GCC_USB30_PRIM_BCR>;
4198 4183
4199 interconnects = <&agg 4184 interconnects = <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>,
4200 <&gem 4185 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>;
4201 interconnect-names = 4186 interconnect-names = "usb-ddr", "apps-usb";
4202 4187
4203 usb_1_dwc3: usb@a6000 4188 usb_1_dwc3: usb@a600000 {
4204 compatible = 4189 compatible = "snps,dwc3";
4205 reg = <0 0x0a 4190 reg = <0 0x0a600000 0 0xcd00>;
4206 interrupts = 4191 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
4207 iommus = <&ap 4192 iommus = <&apps_smmu 0x0 0x0>;
4208 snps,dis_u2_s 4193 snps,dis_u2_susphy_quirk;
4209 snps,dis_enbl 4194 snps,dis_enblslpm_quirk;
4210 phys = <&usb_ 4195 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
4211 phy-names = " 4196 phy-names = "usb2-phy", "usb3-phy";
4212 4197
4213 ports { !! 4198 port {
4214 #addr !! 4199 usb_1_role_switch_out: endpoint {};
4215 #size <<
4216 <<
4217 port@ <<
4218 <<
4219 <<
4220 <<
4221 <<
4222 }; <<
4223 <<
4224 port@ <<
4225 <<
4226 <<
4227 <<
4228 <<
4229 <<
4230 }; <<
4231 }; 4200 };
4232 }; 4201 };
4233 }; 4202 };
4234 4203
4235 system-cache-controller@92000 4204 system-cache-controller@9200000 {
4236 compatible = "qcom,sm 4205 compatible = "qcom,sm8250-llcc";
4237 reg = <0 0x09200000 0 4206 reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>,
4238 <0 0x09300000 0 4207 <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>,
4239 <0 0x09600000 0 4208 <0 0x09600000 0 0x50000>;
4240 reg-names = "llcc0_ba 4209 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
4241 "llcc3_ba 4210 "llcc3_base", "llcc_broadcast_base";
4242 }; 4211 };
4243 4212
4244 usb_2: usb@a8f8800 { 4213 usb_2: usb@a8f8800 {
4245 compatible = "qcom,sm 4214 compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
4246 reg = <0 0x0a8f8800 0 4215 reg = <0 0x0a8f8800 0 0x400>;
4247 status = "disabled"; 4216 status = "disabled";
4248 #address-cells = <2>; 4217 #address-cells = <2>;
4249 #size-cells = <2>; 4218 #size-cells = <2>;
4250 ranges; 4219 ranges;
4251 dma-ranges; 4220 dma-ranges;
4252 4221
4253 clocks = <&gcc GCC_CF 4222 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
4254 <&gcc GCC_US 4223 <&gcc GCC_USB30_SEC_MASTER_CLK>,
4255 <&gcc GCC_AG 4224 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
4256 <&gcc GCC_US 4225 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
4257 <&gcc GCC_US 4226 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4258 <&gcc GCC_US 4227 <&gcc GCC_USB3_SEC_CLKREF_EN>;
4259 clock-names = "cfg_no 4228 clock-names = "cfg_noc",
4260 "core", 4229 "core",
4261 "iface" 4230 "iface",
4262 "sleep" 4231 "sleep",
4263 "mock_u 4232 "mock_utmi",
4264 "xo"; 4233 "xo";
4265 4234
4266 assigned-clocks = <&g 4235 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4267 <&g 4236 <&gcc GCC_USB30_SEC_MASTER_CLK>;
4268 assigned-clock-rates 4237 assigned-clock-rates = <19200000>, <200000000>;
4269 4238
4270 interrupts-extended = 4239 interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
4271 4240 <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
4272 4241 <&pdc 12 IRQ_TYPE_EDGE_BOTH>,
4273 4242 <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
4274 4243 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>;
4275 interrupt-names = "pw 4244 interrupt-names = "pwr_event",
4276 "hs 4245 "hs_phy_irq",
4277 "dp 4246 "dp_hs_phy_irq",
4278 "dm 4247 "dm_hs_phy_irq",
4279 "ss 4248 "ss_phy_irq";
4280 4249
4281 power-domains = <&gcc 4250 power-domains = <&gcc USB30_SEC_GDSC>;
4282 wakeup-source; 4251 wakeup-source;
4283 4252
4284 resets = <&gcc GCC_US 4253 resets = <&gcc GCC_USB30_SEC_BCR>;
4285 4254
4286 interconnects = <&agg 4255 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0>,
4287 <&gem 4256 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>;
4288 interconnect-names = 4257 interconnect-names = "usb-ddr", "apps-usb";
4289 4258
4290 usb_2_dwc3: usb@a8000 4259 usb_2_dwc3: usb@a800000 {
4291 compatible = 4260 compatible = "snps,dwc3";
4292 reg = <0 0x0a 4261 reg = <0 0x0a800000 0 0xcd00>;
4293 interrupts = 4262 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
4294 iommus = <&ap 4263 iommus = <&apps_smmu 0x20 0>;
4295 snps,dis_u2_s 4264 snps,dis_u2_susphy_quirk;
4296 snps,dis_enbl 4265 snps,dis_enblslpm_quirk;
4297 phys = <&usb_ 4266 phys = <&usb_2_hsphy>, <&usb_2_qmpphy>;
4298 phy-names = " 4267 phy-names = "usb2-phy", "usb3-phy";
4299 }; 4268 };
4300 }; 4269 };
4301 4270
4302 venus: video-codec@aa00000 { 4271 venus: video-codec@aa00000 {
4303 compatible = "qcom,sm 4272 compatible = "qcom,sm8250-venus";
4304 reg = <0 0x0aa00000 0 4273 reg = <0 0x0aa00000 0 0x100000>;
4305 interrupts = <GIC_SPI 4274 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
4306 power-domains = <&vid 4275 power-domains = <&videocc MVS0C_GDSC>,
4307 <&vid 4276 <&videocc MVS0_GDSC>,
4308 <&rpm 4277 <&rpmhpd RPMHPD_MX>;
4309 power-domain-names = 4278 power-domain-names = "venus", "vcodec0", "mx";
4310 operating-points-v2 = 4279 operating-points-v2 = <&venus_opp_table>;
4311 4280
4312 clocks = <&gcc GCC_VI 4281 clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
4313 <&videocc VI 4282 <&videocc VIDEO_CC_MVS0C_CLK>,
4314 <&videocc VI 4283 <&videocc VIDEO_CC_MVS0_CLK>;
4315 clock-names = "iface" 4284 clock-names = "iface", "core", "vcodec0_core";
4316 4285
4317 interconnects = <&gem 4286 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_VENUS_CFG 0>,
4318 <&mms 4287 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI_CH0 0>;
4319 interconnect-names = 4288 interconnect-names = "cpu-cfg", "video-mem";
4320 4289
4321 iommus = <&apps_smmu 4290 iommus = <&apps_smmu 0x2100 0x0400>;
4322 memory-region = <&vid 4291 memory-region = <&video_mem>;
4323 4292
4324 resets = <&gcc GCC_VI 4293 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
4325 <&videocc VI 4294 <&videocc VIDEO_CC_MVS0C_CLK_ARES>;
4326 reset-names = "bus", 4295 reset-names = "bus", "core";
4327 4296
4328 status = "disabled"; 4297 status = "disabled";
4329 4298
4330 video-decoder { 4299 video-decoder {
4331 compatible = 4300 compatible = "venus-decoder";
4332 }; 4301 };
4333 4302
4334 video-encoder { 4303 video-encoder {
4335 compatible = 4304 compatible = "venus-encoder";
4336 }; 4305 };
4337 4306
4338 venus_opp_table: opp- 4307 venus_opp_table: opp-table {
4339 compatible = 4308 compatible = "operating-points-v2";
4340 4309
4341 opp-720000000 4310 opp-720000000 {
4342 opp-h 4311 opp-hz = /bits/ 64 <720000000>;
4343 requi 4312 required-opps = <&rpmhpd_opp_low_svs>;
4344 }; 4313 };
4345 4314
4346 opp-101400000 4315 opp-1014000000 {
4347 opp-h 4316 opp-hz = /bits/ 64 <1014000000>;
4348 requi 4317 required-opps = <&rpmhpd_opp_svs>;
4349 }; 4318 };
4350 4319
4351 opp-109800000 4320 opp-1098000000 {
4352 opp-h 4321 opp-hz = /bits/ 64 <1098000000>;
4353 requi 4322 required-opps = <&rpmhpd_opp_svs_l1>;
4354 }; 4323 };
4355 4324
4356 opp-133200000 4325 opp-1332000000 {
4357 opp-h 4326 opp-hz = /bits/ 64 <1332000000>;
4358 requi 4327 required-opps = <&rpmhpd_opp_nom>;
4359 }; 4328 };
4360 }; 4329 };
4361 }; 4330 };
4362 4331
4363 videocc: clock-controller@abf 4332 videocc: clock-controller@abf0000 {
4364 compatible = "qcom,sm 4333 compatible = "qcom,sm8250-videocc";
4365 reg = <0 0x0abf0000 0 4334 reg = <0 0x0abf0000 0 0x10000>;
4366 clocks = <&gcc GCC_VI 4335 clocks = <&gcc GCC_VIDEO_AHB_CLK>,
4367 <&rpmhcc RPM 4336 <&rpmhcc RPMH_CXO_CLK>,
4368 <&rpmhcc RPM 4337 <&rpmhcc RPMH_CXO_CLK_A>;
4369 power-domains = <&rpm 4338 power-domains = <&rpmhpd RPMHPD_MMCX>;
4370 required-opps = <&rpm 4339 required-opps = <&rpmhpd_opp_low_svs>;
4371 clock-names = "iface" 4340 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao";
4372 #clock-cells = <1>; 4341 #clock-cells = <1>;
4373 #reset-cells = <1>; 4342 #reset-cells = <1>;
4374 #power-domain-cells = 4343 #power-domain-cells = <1>;
4375 }; 4344 };
4376 4345
4377 cci0: cci@ac4f000 { 4346 cci0: cci@ac4f000 {
4378 compatible = "qcom,sm 4347 compatible = "qcom,sm8250-cci", "qcom,msm8996-cci";
4379 #address-cells = <1>; 4348 #address-cells = <1>;
4380 #size-cells = <0>; 4349 #size-cells = <0>;
4381 4350
4382 reg = <0 0x0ac4f000 0 4351 reg = <0 0x0ac4f000 0 0x1000>;
4383 interrupts = <GIC_SPI 4352 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
4384 power-domains = <&cam 4353 power-domains = <&camcc TITAN_TOP_GDSC>;
4385 4354
4386 clocks = <&camcc CAM_ 4355 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
4387 <&camcc CAM_ 4356 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4388 <&camcc CAM_ 4357 <&camcc CAM_CC_CPAS_AHB_CLK>,
4389 <&camcc CAM_ 4358 <&camcc CAM_CC_CCI_0_CLK>,
4390 <&camcc CAM_ 4359 <&camcc CAM_CC_CCI_0_CLK_SRC>;
4391 clock-names = "camnoc 4360 clock-names = "camnoc_axi",
4392 "slow_a 4361 "slow_ahb_src",
4393 "cpas_a 4362 "cpas_ahb",
4394 "cci", 4363 "cci",
4395 "cci_sr 4364 "cci_src";
4396 4365
4397 pinctrl-0 = <&cci0_de 4366 pinctrl-0 = <&cci0_default>;
4398 pinctrl-1 = <&cci0_sl 4367 pinctrl-1 = <&cci0_sleep>;
4399 pinctrl-names = "defa 4368 pinctrl-names = "default", "sleep";
4400 4369
4401 status = "disabled"; 4370 status = "disabled";
4402 4371
4403 cci0_i2c0: i2c-bus@0 4372 cci0_i2c0: i2c-bus@0 {
4404 reg = <0>; 4373 reg = <0>;
4405 clock-frequen 4374 clock-frequency = <1000000>;
4406 #address-cell 4375 #address-cells = <1>;
4407 #size-cells = 4376 #size-cells = <0>;
4408 }; 4377 };
4409 4378
4410 cci0_i2c1: i2c-bus@1 4379 cci0_i2c1: i2c-bus@1 {
4411 reg = <1>; 4380 reg = <1>;
4412 clock-frequen 4381 clock-frequency = <1000000>;
4413 #address-cell 4382 #address-cells = <1>;
4414 #size-cells = 4383 #size-cells = <0>;
4415 }; 4384 };
4416 }; 4385 };
4417 4386
4418 cci1: cci@ac50000 { 4387 cci1: cci@ac50000 {
4419 compatible = "qcom,sm 4388 compatible = "qcom,sm8250-cci", "qcom,msm8996-cci";
4420 #address-cells = <1>; 4389 #address-cells = <1>;
4421 #size-cells = <0>; 4390 #size-cells = <0>;
4422 4391
4423 reg = <0 0x0ac50000 0 4392 reg = <0 0x0ac50000 0 0x1000>;
4424 interrupts = <GIC_SPI 4393 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>;
4425 power-domains = <&cam 4394 power-domains = <&camcc TITAN_TOP_GDSC>;
4426 4395
4427 clocks = <&camcc CAM_ 4396 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
4428 <&camcc CAM_ 4397 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4429 <&camcc CAM_ 4398 <&camcc CAM_CC_CPAS_AHB_CLK>,
4430 <&camcc CAM_ 4399 <&camcc CAM_CC_CCI_1_CLK>,
4431 <&camcc CAM_ 4400 <&camcc CAM_CC_CCI_1_CLK_SRC>;
4432 clock-names = "camnoc 4401 clock-names = "camnoc_axi",
4433 "slow_a 4402 "slow_ahb_src",
4434 "cpas_a 4403 "cpas_ahb",
4435 "cci", 4404 "cci",
4436 "cci_sr 4405 "cci_src";
4437 4406
4438 pinctrl-0 = <&cci1_de 4407 pinctrl-0 = <&cci1_default>;
4439 pinctrl-1 = <&cci1_sl 4408 pinctrl-1 = <&cci1_sleep>;
4440 pinctrl-names = "defa 4409 pinctrl-names = "default", "sleep";
4441 4410
4442 status = "disabled"; 4411 status = "disabled";
4443 4412
4444 cci1_i2c0: i2c-bus@0 4413 cci1_i2c0: i2c-bus@0 {
4445 reg = <0>; 4414 reg = <0>;
4446 clock-frequen 4415 clock-frequency = <1000000>;
4447 #address-cell 4416 #address-cells = <1>;
4448 #size-cells = 4417 #size-cells = <0>;
4449 }; 4418 };
4450 4419
4451 cci1_i2c1: i2c-bus@1 4420 cci1_i2c1: i2c-bus@1 {
4452 reg = <1>; 4421 reg = <1>;
4453 clock-frequen 4422 clock-frequency = <1000000>;
4454 #address-cell 4423 #address-cells = <1>;
4455 #size-cells = 4424 #size-cells = <0>;
4456 }; 4425 };
4457 }; 4426 };
4458 4427
4459 camss: camss@ac6a000 { 4428 camss: camss@ac6a000 {
4460 compatible = "qcom,sm 4429 compatible = "qcom,sm8250-camss";
4461 status = "disabled"; 4430 status = "disabled";
4462 4431
4463 reg = <0 0x0ac6a000 0 4432 reg = <0 0x0ac6a000 0 0x2000>,
4464 <0 0x0ac6c000 0 4433 <0 0x0ac6c000 0 0x2000>,
4465 <0 0x0ac6e000 0 4434 <0 0x0ac6e000 0 0x1000>,
4466 <0 0x0ac70000 0 4435 <0 0x0ac70000 0 0x1000>,
4467 <0 0x0ac72000 0 4436 <0 0x0ac72000 0 0x1000>,
4468 <0 0x0ac74000 0 4437 <0 0x0ac74000 0 0x1000>,
4469 <0 0x0acb4000 0 4438 <0 0x0acb4000 0 0xd000>,
4470 <0 0x0acc3000 0 4439 <0 0x0acc3000 0 0xd000>,
4471 <0 0x0acd9000 0 4440 <0 0x0acd9000 0 0x2200>,
4472 <0 0x0acdb200 0 4441 <0 0x0acdb200 0 0x2200>;
4473 reg-names = "csiphy0" 4442 reg-names = "csiphy0",
4474 "csiphy1" 4443 "csiphy1",
4475 "csiphy2" 4444 "csiphy2",
4476 "csiphy3" 4445 "csiphy3",
4477 "csiphy4" 4446 "csiphy4",
4478 "csiphy5" 4447 "csiphy5",
4479 "vfe0", 4448 "vfe0",
4480 "vfe1", 4449 "vfe1",
4481 "vfe_lite 4450 "vfe_lite0",
4482 "vfe_lite 4451 "vfe_lite1";
4483 4452
4484 interrupts = <GIC_SPI 4453 interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
4485 <GIC_SPI 4454 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
4486 <GIC_SPI 4455 <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
4487 <GIC_SPI 4456 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
4488 <GIC_SPI 4457 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
4489 <GIC_SPI 4458 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
4490 <GIC_SPI 4459 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
4491 <GIC_SPI 4460 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
4492 <GIC_SPI 4461 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
4493 <GIC_SPI 4462 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
4494 <GIC_SPI 4463 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
4495 <GIC_SPI 4464 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
4496 <GIC_SPI 4465 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
4497 <GIC_SPI 4466 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
4498 interrupt-names = "cs 4467 interrupt-names = "csiphy0",
4499 "cs 4468 "csiphy1",
4500 "cs 4469 "csiphy2",
4501 "cs 4470 "csiphy3",
4502 "cs 4471 "csiphy4",
4503 "cs 4472 "csiphy5",
4504 "cs 4473 "csid0",
4505 "cs 4474 "csid1",
4506 "cs 4475 "csid2",
4507 "cs 4476 "csid3",
4508 "vf 4477 "vfe0",
4509 "vf 4478 "vfe1",
4510 "vf 4479 "vfe_lite0",
4511 "vf 4480 "vfe_lite1";
4512 4481
4513 power-domains = <&cam 4482 power-domains = <&camcc IFE_0_GDSC>,
4514 <&cam 4483 <&camcc IFE_1_GDSC>,
4515 <&cam 4484 <&camcc TITAN_TOP_GDSC>;
4516 4485
4517 clocks = <&gcc GCC_CA 4486 clocks = <&gcc GCC_CAMERA_AHB_CLK>,
4518 <&gcc GCC_CA 4487 <&gcc GCC_CAMERA_HF_AXI_CLK>,
4519 <&gcc GCC_CA 4488 <&gcc GCC_CAMERA_SF_AXI_CLK>,
4520 <&camcc CAM_ 4489 <&camcc CAM_CC_CAMNOC_AXI_CLK>,
4521 <&camcc CAM_ 4490 <&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>,
4522 <&camcc CAM_ 4491 <&camcc CAM_CC_CORE_AHB_CLK>,
4523 <&camcc CAM_ 4492 <&camcc CAM_CC_CPAS_AHB_CLK>,
4524 <&camcc CAM_ 4493 <&camcc CAM_CC_CSIPHY0_CLK>,
4525 <&camcc CAM_ 4494 <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
4526 <&camcc CAM_ 4495 <&camcc CAM_CC_CSIPHY1_CLK>,
4527 <&camcc CAM_ 4496 <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
4528 <&camcc CAM_ 4497 <&camcc CAM_CC_CSIPHY2_CLK>,
4529 <&camcc CAM_ 4498 <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
4530 <&camcc CAM_ 4499 <&camcc CAM_CC_CSIPHY3_CLK>,
4531 <&camcc CAM_ 4500 <&camcc CAM_CC_CSI3PHYTIMER_CLK>,
4532 <&camcc CAM_ 4501 <&camcc CAM_CC_CSIPHY4_CLK>,
4533 <&camcc CAM_ 4502 <&camcc CAM_CC_CSI4PHYTIMER_CLK>,
4534 <&camcc CAM_ 4503 <&camcc CAM_CC_CSIPHY5_CLK>,
4535 <&camcc CAM_ 4504 <&camcc CAM_CC_CSI5PHYTIMER_CLK>,
4536 <&camcc CAM_ 4505 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4537 <&camcc CAM_ 4506 <&camcc CAM_CC_IFE_0_AHB_CLK>,
4538 <&camcc CAM_ 4507 <&camcc CAM_CC_IFE_0_AXI_CLK>,
4539 <&camcc CAM_ 4508 <&camcc CAM_CC_IFE_0_CLK>,
4540 <&camcc CAM_ 4509 <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
4541 <&camcc CAM_ 4510 <&camcc CAM_CC_IFE_0_CSID_CLK>,
4542 <&camcc CAM_ 4511 <&camcc CAM_CC_IFE_0_AREG_CLK>,
4543 <&camcc CAM_ 4512 <&camcc CAM_CC_IFE_1_AHB_CLK>,
4544 <&camcc CAM_ 4513 <&camcc CAM_CC_IFE_1_AXI_CLK>,
4545 <&camcc CAM_ 4514 <&camcc CAM_CC_IFE_1_CLK>,
4546 <&camcc CAM_ 4515 <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
4547 <&camcc CAM_ 4516 <&camcc CAM_CC_IFE_1_CSID_CLK>,
4548 <&camcc CAM_ 4517 <&camcc CAM_CC_IFE_1_AREG_CLK>,
4549 <&camcc CAM_ 4518 <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
4550 <&camcc CAM_ 4519 <&camcc CAM_CC_IFE_LITE_AXI_CLK>,
4551 <&camcc CAM_ 4520 <&camcc CAM_CC_IFE_LITE_CLK>,
4552 <&camcc CAM_ 4521 <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
4553 <&camcc CAM_ 4522 <&camcc CAM_CC_IFE_LITE_CSID_CLK>;
4554 4523
4555 clock-names = "cam_ah 4524 clock-names = "cam_ahb_clk",
4556 "cam_hf 4525 "cam_hf_axi",
4557 "cam_sf 4526 "cam_sf_axi",
4558 "camnoc 4527 "camnoc_axi",
4559 "camnoc 4528 "camnoc_axi_src",
4560 "core_a 4529 "core_ahb",
4561 "cpas_a 4530 "cpas_ahb",
4562 "csiphy 4531 "csiphy0",
4563 "csiphy 4532 "csiphy0_timer",
4564 "csiphy 4533 "csiphy1",
4565 "csiphy 4534 "csiphy1_timer",
4566 "csiphy 4535 "csiphy2",
4567 "csiphy 4536 "csiphy2_timer",
4568 "csiphy 4537 "csiphy3",
4569 "csiphy 4538 "csiphy3_timer",
4570 "csiphy 4539 "csiphy4",
4571 "csiphy 4540 "csiphy4_timer",
4572 "csiphy 4541 "csiphy5",
4573 "csiphy 4542 "csiphy5_timer",
4574 "slow_a 4543 "slow_ahb_src",
4575 "vfe0_a 4544 "vfe0_ahb",
4576 "vfe0_a 4545 "vfe0_axi",
4577 "vfe0", 4546 "vfe0",
4578 "vfe0_c 4547 "vfe0_cphy_rx",
4579 "vfe0_c 4548 "vfe0_csid",
4580 "vfe0_a 4549 "vfe0_areg",
4581 "vfe1_a 4550 "vfe1_ahb",
4582 "vfe1_a 4551 "vfe1_axi",
4583 "vfe1", 4552 "vfe1",
4584 "vfe1_c 4553 "vfe1_cphy_rx",
4585 "vfe1_c 4554 "vfe1_csid",
4586 "vfe1_a 4555 "vfe1_areg",
4587 "vfe_li 4556 "vfe_lite_ahb",
4588 "vfe_li 4557 "vfe_lite_axi",
4589 "vfe_li 4558 "vfe_lite",
4590 "vfe_li 4559 "vfe_lite_cphy_rx",
4591 "vfe_li 4560 "vfe_lite_csid";
4592 4561
4593 iommus = <&apps_smmu 4562 iommus = <&apps_smmu 0x800 0x400>,
4594 <&apps_smmu 4563 <&apps_smmu 0x801 0x400>,
4595 <&apps_smmu 4564 <&apps_smmu 0x840 0x400>,
4596 <&apps_smmu 4565 <&apps_smmu 0x841 0x400>,
4597 <&apps_smmu 4566 <&apps_smmu 0xc00 0x400>,
4598 <&apps_smmu 4567 <&apps_smmu 0xc01 0x400>,
4599 <&apps_smmu 4568 <&apps_smmu 0xc40 0x400>,
4600 <&apps_smmu 4569 <&apps_smmu 0xc41 0x400>;
4601 4570
4602 interconnects = <&gem 4571 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_CAMERA_CFG 0>,
4603 <&mms 4572 <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI_CH0 0>,
4604 <&mms 4573 <&mmss_noc MASTER_CAMNOC_SF 0 &mc_virt SLAVE_EBI_CH0 0>,
4605 <&mms 4574 <&mmss_noc MASTER_CAMNOC_ICP 0 &mc_virt SLAVE_EBI_CH0 0>;
4606 interconnect-names = 4575 interconnect-names = "cam_ahb",
4607 4576 "cam_hf_0_mnoc",
4608 4577 "cam_sf_0_mnoc",
4609 4578 "cam_sf_icp_mnoc";
4610 4579
4611 ports { 4580 ports {
4612 #address-cell 4581 #address-cells = <1>;
4613 #size-cells = 4582 #size-cells = <0>;
4614 4583
4615 port@0 { 4584 port@0 {
4616 reg = 4585 reg = <0>;
4617 }; 4586 };
4618 4587
4619 port@1 { 4588 port@1 {
4620 reg = 4589 reg = <1>;
4621 }; 4590 };
4622 4591
4623 port@2 { 4592 port@2 {
4624 reg = 4593 reg = <2>;
4625 }; 4594 };
4626 4595
4627 port@3 { 4596 port@3 {
4628 reg = 4597 reg = <3>;
4629 }; 4598 };
4630 4599
4631 port@4 { 4600 port@4 {
4632 reg = 4601 reg = <4>;
4633 }; 4602 };
4634 4603
4635 port@5 { 4604 port@5 {
4636 reg = 4605 reg = <5>;
4637 }; 4606 };
4638 }; 4607 };
4639 }; 4608 };
4640 4609
4641 camcc: clock-controller@ad000 4610 camcc: clock-controller@ad00000 {
4642 compatible = "qcom,sm 4611 compatible = "qcom,sm8250-camcc";
4643 reg = <0 0x0ad00000 0 4612 reg = <0 0x0ad00000 0 0x10000>;
4644 clocks = <&gcc GCC_CA 4613 clocks = <&gcc GCC_CAMERA_AHB_CLK>,
4645 <&rpmhcc RPM 4614 <&rpmhcc RPMH_CXO_CLK>,
4646 <&rpmhcc RPM 4615 <&rpmhcc RPMH_CXO_CLK_A>,
4647 <&sleep_clk> 4616 <&sleep_clk>;
4648 clock-names = "iface" 4617 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
4649 power-domains = <&rpm 4618 power-domains = <&rpmhpd RPMHPD_MMCX>;
4650 required-opps = <&rpm 4619 required-opps = <&rpmhpd_opp_low_svs>;
4651 status = "disabled"; 4620 status = "disabled";
4652 #clock-cells = <1>; 4621 #clock-cells = <1>;
4653 #reset-cells = <1>; 4622 #reset-cells = <1>;
4654 #power-domain-cells = 4623 #power-domain-cells = <1>;
4655 }; 4624 };
4656 4625
4657 mdss: display-subsystem@ae000 4626 mdss: display-subsystem@ae00000 {
4658 compatible = "qcom,sm 4627 compatible = "qcom,sm8250-mdss";
4659 reg = <0 0x0ae00000 0 4628 reg = <0 0x0ae00000 0 0x1000>;
4660 reg-names = "mdss"; 4629 reg-names = "mdss";
4661 4630
4662 interconnects = <&mms 4631 interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mc_virt SLAVE_EBI_CH0 0>,
4663 <&mms 4632 <&mmss_noc MASTER_MDP_PORT1 0 &mc_virt SLAVE_EBI_CH0 0>;
4664 interconnect-names = 4633 interconnect-names = "mdp0-mem", "mdp1-mem";
4665 4634
4666 power-domains = <&dis 4635 power-domains = <&dispcc MDSS_GDSC>;
4667 4636
4668 clocks = <&dispcc DIS 4637 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4669 <&gcc GCC_DI 4638 <&gcc GCC_DISP_HF_AXI_CLK>,
4670 <&gcc GCC_DI 4639 <&gcc GCC_DISP_SF_AXI_CLK>,
4671 <&dispcc DIS 4640 <&dispcc DISP_CC_MDSS_MDP_CLK>;
4672 clock-names = "iface" 4641 clock-names = "iface", "bus", "nrt_bus", "core";
4673 4642
4674 interrupts = <GIC_SPI 4643 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
4675 interrupt-controller; 4644 interrupt-controller;
4676 #interrupt-cells = <1 4645 #interrupt-cells = <1>;
4677 4646
4678 iommus = <&apps_smmu 4647 iommus = <&apps_smmu 0x820 0x402>;
4679 4648
4680 status = "disabled"; 4649 status = "disabled";
4681 4650
4682 #address-cells = <2>; 4651 #address-cells = <2>;
4683 #size-cells = <2>; 4652 #size-cells = <2>;
4684 ranges; 4653 ranges;
4685 4654
4686 mdss_mdp: display-con 4655 mdss_mdp: display-controller@ae01000 {
4687 compatible = 4656 compatible = "qcom,sm8250-dpu";
4688 reg = <0 0x0a 4657 reg = <0 0x0ae01000 0 0x8f000>,
4689 <0 0x0a 4658 <0 0x0aeb0000 0 0x2008>;
4690 reg-names = " 4659 reg-names = "mdp", "vbif";
4691 4660
4692 clocks = <&di 4661 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4693 <&gc 4662 <&gcc GCC_DISP_HF_AXI_CLK>,
4694 <&di 4663 <&dispcc DISP_CC_MDSS_MDP_CLK>,
4695 <&di 4664 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4696 clock-names = 4665 clock-names = "iface", "bus", "core", "vsync";
4697 4666
4698 assigned-cloc 4667 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4699 assigned-cloc 4668 assigned-clock-rates = <19200000>;
4700 4669
4701 operating-poi 4670 operating-points-v2 = <&mdp_opp_table>;
4702 power-domains 4671 power-domains = <&rpmhpd RPMHPD_MMCX>;
4703 4672
4704 interrupt-par 4673 interrupt-parent = <&mdss>;
4705 interrupts = 4674 interrupts = <0>;
4706 4675
4707 ports { 4676 ports {
4708 #addr 4677 #address-cells = <1>;
4709 #size 4678 #size-cells = <0>;
4710 4679
4711 port@ 4680 port@0 {
4712 4681 reg = <0>;
4713 4682 dpu_intf1_out: endpoint {
4714 4683 remote-endpoint = <&mdss_dsi0_in>;
4715 4684 };
4716 }; 4685 };
4717 4686
4718 port@ 4687 port@1 {
4719 4688 reg = <1>;
4720 4689 dpu_intf2_out: endpoint {
4721 4690 remote-endpoint = <&mdss_dsi1_in>;
4722 4691 };
4723 }; 4692 };
4724 4693
4725 port@ 4694 port@2 {
4726 4695 reg = <2>;
4727 4696
4728 4697 dpu_intf0_out: endpoint {
4729 4698 remote-endpoint = <&mdss_dp_in>;
4730 4699 };
4731 }; 4700 };
4732 }; 4701 };
4733 4702
4734 mdp_opp_table 4703 mdp_opp_table: opp-table {
4735 compa 4704 compatible = "operating-points-v2";
4736 4705
4737 opp-2 4706 opp-200000000 {
4738 4707 opp-hz = /bits/ 64 <200000000>;
4739 4708 required-opps = <&rpmhpd_opp_low_svs>;
4740 }; 4709 };
4741 4710
4742 opp-3 4711 opp-300000000 {
4743 4712 opp-hz = /bits/ 64 <300000000>;
4744 4713 required-opps = <&rpmhpd_opp_svs>;
4745 }; 4714 };
4746 4715
4747 opp-3 4716 opp-345000000 {
4748 4717 opp-hz = /bits/ 64 <345000000>;
4749 4718 required-opps = <&rpmhpd_opp_svs_l1>;
4750 }; 4719 };
4751 4720
4752 opp-4 4721 opp-460000000 {
4753 4722 opp-hz = /bits/ 64 <460000000>;
4754 4723 required-opps = <&rpmhpd_opp_nom>;
4755 }; 4724 };
4756 }; 4725 };
4757 }; 4726 };
4758 4727
4759 mdss_dp: displayport- 4728 mdss_dp: displayport-controller@ae90000 {
4760 compatible = 4729 compatible = "qcom,sm8250-dp", "qcom,sm8350-dp";
4761 reg = <0 0xae 4730 reg = <0 0xae90000 0 0x200>,
4762 <0 0xae 4731 <0 0xae90200 0 0x200>,
4763 <0 0xae 4732 <0 0xae90400 0 0x600>,
4764 <0 0xae 4733 <0 0xae91000 0 0x400>,
4765 <0 0xae 4734 <0 0xae91400 0 0x400>;
4766 interrupt-par 4735 interrupt-parent = <&mdss>;
4767 interrupts = 4736 interrupts = <12>;
4768 clocks = <&di 4737 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4769 <&di 4738 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
4770 <&di 4739 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
4771 <&di 4740 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
4772 <&di 4741 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
4773 clock-names = 4742 clock-names = "core_iface",
4774 4743 "core_aux",
4775 4744 "ctrl_link",
4776 4745 "ctrl_link_iface",
4777 4746 "stream_pixel";
4778 4747
4779 assigned-cloc 4748 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
4780 4749 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
4781 assigned-cloc 4750 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4782 4751 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
4783 4752
4784 phys = <&usb_ 4753 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
4785 phy-names = " 4754 phy-names = "dp";
4786 4755
4787 #sound-dai-ce 4756 #sound-dai-cells = <0>;
4788 4757
4789 operating-poi 4758 operating-points-v2 = <&dp_opp_table>;
4790 power-domains 4759 power-domains = <&rpmhpd SM8250_MMCX>;
4791 4760
4792 status = "dis 4761 status = "disabled";
4793 4762
4794 ports { 4763 ports {
4795 #addr 4764 #address-cells = <1>;
4796 #size 4765 #size-cells = <0>;
4797 4766
4798 port@ 4767 port@0 {
4799 4768 reg = <0>;
4800 4769 mdss_dp_in: endpoint {
4801 4770 remote-endpoint = <&dpu_intf0_out>;
4802 4771 };
4803 }; 4772 };
4804 4773
4805 port@ 4774 port@1 {
4806 4775 reg = <1>;
4807 4776
4808 4777 mdss_dp_out: endpoint {
4809 4778 };
4810 }; 4779 };
4811 }; 4780 };
4812 4781
4813 dp_opp_table: 4782 dp_opp_table: opp-table {
4814 compa 4783 compatible = "operating-points-v2";
4815 4784
4816 opp-1 4785 opp-160000000 {
4817 4786 opp-hz = /bits/ 64 <160000000>;
4818 4787 required-opps = <&rpmhpd_opp_low_svs>;
4819 }; 4788 };
4820 4789
4821 opp-2 4790 opp-270000000 {
4822 4791 opp-hz = /bits/ 64 <270000000>;
4823 4792 required-opps = <&rpmhpd_opp_svs>;
4824 }; 4793 };
4825 4794
4826 opp-5 4795 opp-540000000 {
4827 4796 opp-hz = /bits/ 64 <540000000>;
4828 4797 required-opps = <&rpmhpd_opp_svs_l1>;
4829 }; 4798 };
4830 4799
4831 opp-8 4800 opp-810000000 {
4832 4801 opp-hz = /bits/ 64 <810000000>;
4833 4802 required-opps = <&rpmhpd_opp_nom>;
4834 }; 4803 };
4835 }; 4804 };
4836 }; 4805 };
4837 4806
4838 mdss_dsi0: dsi@ae9400 4807 mdss_dsi0: dsi@ae94000 {
4839 compatible = 4808 compatible = "qcom,sm8250-dsi-ctrl",
4840 4809 "qcom,mdss-dsi-ctrl";
4841 reg = <0 0x0a 4810 reg = <0 0x0ae94000 0 0x400>;
4842 reg-names = " 4811 reg-names = "dsi_ctrl";
4843 4812
4844 interrupt-par 4813 interrupt-parent = <&mdss>;
4845 interrupts = 4814 interrupts = <4>;
4846 4815
4847 clocks = <&di 4816 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
4848 <&di 4817 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
4849 <&di 4818 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
4850 <&di 4819 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
4851 <&di 4820 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4852 <&gcc 4821 <&gcc GCC_DISP_HF_AXI_CLK>;
4853 clock-names = 4822 clock-names = "byte",
4854 4823 "byte_intf",
4855 4824 "pixel",
4856 4825 "core",
4857 4826 "iface",
4858 4827 "bus";
4859 4828
4860 assigned-cloc 4829 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
4861 assigned-cloc 4830 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
4862 4831
4863 operating-poi 4832 operating-points-v2 = <&dsi_opp_table>;
4864 power-domains 4833 power-domains = <&rpmhpd RPMHPD_MMCX>;
4865 4834
4866 phys = <&mdss 4835 phys = <&mdss_dsi0_phy>;
4867 4836
4868 status = "dis 4837 status = "disabled";
4869 4838
4870 #address-cell 4839 #address-cells = <1>;
4871 #size-cells = 4840 #size-cells = <0>;
4872 4841
4873 ports { 4842 ports {
4874 #addr 4843 #address-cells = <1>;
4875 #size 4844 #size-cells = <0>;
4876 4845
4877 port@ 4846 port@0 {
4878 4847 reg = <0>;
4879 4848 mdss_dsi0_in: endpoint {
4880 4849 remote-endpoint = <&dpu_intf1_out>;
4881 4850 };
4882 }; 4851 };
4883 4852
4884 port@ 4853 port@1 {
4885 4854 reg = <1>;
4886 4855 mdss_dsi0_out: endpoint {
4887 4856 };
4888 }; 4857 };
4889 }; 4858 };
4890 4859
4891 dsi_opp_table 4860 dsi_opp_table: opp-table {
4892 compa 4861 compatible = "operating-points-v2";
4893 4862
4894 opp-1 4863 opp-187500000 {
4895 4864 opp-hz = /bits/ 64 <187500000>;
4896 4865 required-opps = <&rpmhpd_opp_low_svs>;
4897 }; 4866 };
4898 4867
4899 opp-3 4868 opp-300000000 {
4900 4869 opp-hz = /bits/ 64 <300000000>;
4901 4870 required-opps = <&rpmhpd_opp_svs>;
4902 }; 4871 };
4903 4872
4904 opp-3 4873 opp-358000000 {
4905 4874 opp-hz = /bits/ 64 <358000000>;
4906 4875 required-opps = <&rpmhpd_opp_svs_l1>;
4907 }; 4876 };
4908 }; 4877 };
4909 }; 4878 };
4910 4879
4911 mdss_dsi0_phy: phy@ae 4880 mdss_dsi0_phy: phy@ae94400 {
4912 compatible = 4881 compatible = "qcom,dsi-phy-7nm";
4913 reg = <0 0x0a 4882 reg = <0 0x0ae94400 0 0x200>,
4914 <0 0x0a 4883 <0 0x0ae94600 0 0x280>,
4915 <0 0x0a 4884 <0 0x0ae94900 0 0x260>;
4916 reg-names = " 4885 reg-names = "dsi_phy",
4917 " 4886 "dsi_phy_lane",
4918 " 4887 "dsi_pll";
4919 4888
4920 #clock-cells 4889 #clock-cells = <1>;
4921 #phy-cells = 4890 #phy-cells = <0>;
4922 4891
4923 clocks = <&di 4892 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4924 <&rp 4893 <&rpmhcc RPMH_CXO_CLK>;
4925 clock-names = 4894 clock-names = "iface", "ref";
4926 4895
4927 status = "dis 4896 status = "disabled";
4928 }; 4897 };
4929 4898
4930 mdss_dsi1: dsi@ae9600 4899 mdss_dsi1: dsi@ae96000 {
4931 compatible = 4900 compatible = "qcom,sm8250-dsi-ctrl",
4932 4901 "qcom,mdss-dsi-ctrl";
4933 reg = <0 0x0a 4902 reg = <0 0x0ae96000 0 0x400>;
4934 reg-names = " 4903 reg-names = "dsi_ctrl";
4935 4904
4936 interrupt-par 4905 interrupt-parent = <&mdss>;
4937 interrupts = 4906 interrupts = <5>;
4938 4907
4939 clocks = <&di 4908 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
4940 <&di 4909 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
4941 <&di 4910 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
4942 <&di 4911 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
4943 <&di 4912 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4944 <&gc 4913 <&gcc GCC_DISP_HF_AXI_CLK>;
4945 clock-names = 4914 clock-names = "byte",
4946 4915 "byte_intf",
4947 4916 "pixel",
4948 4917 "core",
4949 4918 "iface",
4950 4919 "bus";
4951 4920
4952 assigned-cloc 4921 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
4953 assigned-cloc 4922 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
4954 4923
4955 operating-poi 4924 operating-points-v2 = <&dsi_opp_table>;
4956 power-domains 4925 power-domains = <&rpmhpd RPMHPD_MMCX>;
4957 4926
4958 phys = <&mdss 4927 phys = <&mdss_dsi1_phy>;
4959 4928
4960 status = "dis 4929 status = "disabled";
4961 4930
4962 #address-cell 4931 #address-cells = <1>;
4963 #size-cells = 4932 #size-cells = <0>;
4964 4933
4965 ports { 4934 ports {
4966 #addr 4935 #address-cells = <1>;
4967 #size 4936 #size-cells = <0>;
4968 4937
4969 port@ 4938 port@0 {
4970 4939 reg = <0>;
4971 4940 mdss_dsi1_in: endpoint {
4972 4941 remote-endpoint = <&dpu_intf2_out>;
4973 4942 };
4974 }; 4943 };
4975 4944
4976 port@ 4945 port@1 {
4977 4946 reg = <1>;
4978 4947 mdss_dsi1_out: endpoint {
4979 4948 };
4980 }; 4949 };
4981 }; 4950 };
4982 }; 4951 };
4983 4952
4984 mdss_dsi1_phy: phy@ae 4953 mdss_dsi1_phy: phy@ae96400 {
4985 compatible = 4954 compatible = "qcom,dsi-phy-7nm";
4986 reg = <0 0x0a 4955 reg = <0 0x0ae96400 0 0x200>,
4987 <0 0x0a 4956 <0 0x0ae96600 0 0x280>,
4988 <0 0x0a 4957 <0 0x0ae96900 0 0x260>;
4989 reg-names = " 4958 reg-names = "dsi_phy",
4990 " 4959 "dsi_phy_lane",
4991 " 4960 "dsi_pll";
4992 4961
4993 #clock-cells 4962 #clock-cells = <1>;
4994 #phy-cells = 4963 #phy-cells = <0>;
4995 4964
4996 clocks = <&di 4965 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4997 <&rp 4966 <&rpmhcc RPMH_CXO_CLK>;
4998 clock-names = 4967 clock-names = "iface", "ref";
4999 4968
5000 status = "dis 4969 status = "disabled";
5001 }; 4970 };
5002 }; 4971 };
5003 4972
5004 dispcc: clock-controller@af00 4973 dispcc: clock-controller@af00000 {
5005 compatible = "qcom,sm 4974 compatible = "qcom,sm8250-dispcc";
5006 reg = <0 0x0af00000 0 4975 reg = <0 0x0af00000 0 0x10000>;
5007 power-domains = <&rpm 4976 power-domains = <&rpmhpd RPMHPD_MMCX>;
5008 required-opps = <&rpm 4977 required-opps = <&rpmhpd_opp_low_svs>;
5009 clocks = <&rpmhcc RPM 4978 clocks = <&rpmhcc RPMH_CXO_CLK>,
5010 <&mdss_dsi0_ 4979 <&mdss_dsi0_phy 0>,
5011 <&mdss_dsi0_ 4980 <&mdss_dsi0_phy 1>,
5012 <&mdss_dsi1_ 4981 <&mdss_dsi1_phy 0>,
5013 <&mdss_dsi1_ 4982 <&mdss_dsi1_phy 1>,
5014 <&usb_1_qmpp 4983 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
5015 <&usb_1_qmpp 4984 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
5016 clock-names = "bi_tcx 4985 clock-names = "bi_tcxo",
5017 "dsi0_p 4986 "dsi0_phy_pll_out_byteclk",
5018 "dsi0_p 4987 "dsi0_phy_pll_out_dsiclk",
5019 "dsi1_p 4988 "dsi1_phy_pll_out_byteclk",
5020 "dsi1_p 4989 "dsi1_phy_pll_out_dsiclk",
5021 "dp_phy 4990 "dp_phy_pll_link_clk",
5022 "dp_phy 4991 "dp_phy_pll_vco_div_clk";
5023 #clock-cells = <1>; 4992 #clock-cells = <1>;
5024 #reset-cells = <1>; 4993 #reset-cells = <1>;
5025 #power-domain-cells = 4994 #power-domain-cells = <1>;
5026 }; 4995 };
5027 4996
5028 pdc: interrupt-controller@b22 4997 pdc: interrupt-controller@b220000 {
5029 compatible = "qcom,sm 4998 compatible = "qcom,sm8250-pdc", "qcom,pdc";
5030 reg = <0 0x0b220000 0 4999 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
5031 qcom,pdc-ranges = <0 5000 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
5032 <12 5001 <125 63 1>, <126 716 12>;
5033 #interrupt-cells = <2 5002 #interrupt-cells = <2>;
5034 interrupt-parent = <& 5003 interrupt-parent = <&intc>;
5035 interrupt-controller; 5004 interrupt-controller;
5036 }; 5005 };
5037 5006
5038 tsens0: thermal-sensor@c26300 5007 tsens0: thermal-sensor@c263000 {
5039 compatible = "qcom,sm 5008 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
5040 reg = <0 0x0c263000 0 5009 reg = <0 0x0c263000 0 0x1ff>, /* TM */
5041 <0 0x0c222000 0 5010 <0 0x0c222000 0 0x1ff>; /* SROT */
5042 #qcom,sensors = <16>; 5011 #qcom,sensors = <16>;
5043 interrupts = <GIC_SPI 5012 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
5044 <GIC_SPI 5013 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
5045 interrupt-names = "up 5014 interrupt-names = "uplow", "critical";
5046 #thermal-sensor-cells 5015 #thermal-sensor-cells = <1>;
5047 }; 5016 };
5048 5017
5049 tsens1: thermal-sensor@c26500 5018 tsens1: thermal-sensor@c265000 {
5050 compatible = "qcom,sm 5019 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
5051 reg = <0 0x0c265000 0 5020 reg = <0 0x0c265000 0 0x1ff>, /* TM */
5052 <0 0x0c223000 0 5021 <0 0x0c223000 0 0x1ff>; /* SROT */
5053 #qcom,sensors = <9>; 5022 #qcom,sensors = <9>;
5054 interrupts = <GIC_SPI 5023 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
5055 <GIC_SPI 5024 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
5056 interrupt-names = "up 5025 interrupt-names = "uplow", "critical";
5057 #thermal-sensor-cells 5026 #thermal-sensor-cells = <1>;
5058 }; 5027 };
5059 5028
5060 aoss_qmp: power-management@c3 5029 aoss_qmp: power-management@c300000 {
5061 compatible = "qcom,sm 5030 compatible = "qcom,sm8250-aoss-qmp", "qcom,aoss-qmp";
5062 reg = <0 0x0c300000 0 5031 reg = <0 0x0c300000 0 0x400>;
5063 interrupts-extended = 5032 interrupts-extended = <&ipcc IPCC_CLIENT_AOP
5064 5033 IPCC_MPROC_SIGNAL_GLINK_QMP
5065 5034 IRQ_TYPE_EDGE_RISING>;
5066 mboxes = <&ipcc IPCC_ 5035 mboxes = <&ipcc IPCC_CLIENT_AOP
5067 IPCC_ 5036 IPCC_MPROC_SIGNAL_GLINK_QMP>;
5068 5037
5069 #clock-cells = <0>; 5038 #clock-cells = <0>;
5070 }; 5039 };
5071 5040
5072 sram@c3f0000 { 5041 sram@c3f0000 {
5073 compatible = "qcom,rp 5042 compatible = "qcom,rpmh-stats";
5074 reg = <0 0x0c3f0000 0 5043 reg = <0 0x0c3f0000 0 0x400>;
5075 }; 5044 };
5076 5045
5077 spmi_bus: spmi@c440000 { 5046 spmi_bus: spmi@c440000 {
5078 compatible = "qcom,sp 5047 compatible = "qcom,spmi-pmic-arb";
5079 reg = <0x0 0x0c440000 5048 reg = <0x0 0x0c440000 0x0 0x0001100>,
5080 <0x0 0x0c600000 5049 <0x0 0x0c600000 0x0 0x2000000>,
5081 <0x0 0x0e600000 5050 <0x0 0x0e600000 0x0 0x0100000>,
5082 <0x0 0x0e700000 5051 <0x0 0x0e700000 0x0 0x00a0000>,
5083 <0x0 0x0c40a000 5052 <0x0 0x0c40a000 0x0 0x0026000>;
5084 reg-names = "core", " 5053 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
5085 interrupt-names = "pe 5054 interrupt-names = "periph_irq";
5086 interrupts-extended = 5055 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
5087 qcom,ee = <0>; 5056 qcom,ee = <0>;
5088 qcom,channel = <0>; 5057 qcom,channel = <0>;
5089 #address-cells = <2>; 5058 #address-cells = <2>;
5090 #size-cells = <0>; 5059 #size-cells = <0>;
5091 interrupt-controller; 5060 interrupt-controller;
5092 #interrupt-cells = <4 5061 #interrupt-cells = <4>;
5093 }; 5062 };
5094 5063
5095 tlmm: pinctrl@f100000 { 5064 tlmm: pinctrl@f100000 {
5096 compatible = "qcom,sm 5065 compatible = "qcom,sm8250-pinctrl";
5097 reg = <0 0x0f100000 0 5066 reg = <0 0x0f100000 0 0x300000>,
5098 <0 0x0f500000 0 5067 <0 0x0f500000 0 0x300000>,
5099 <0 0x0f900000 0 5068 <0 0x0f900000 0 0x300000>;
5100 reg-names = "west", " 5069 reg-names = "west", "south", "north";
5101 interrupts = <GIC_SPI 5070 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
5102 gpio-controller; 5071 gpio-controller;
5103 #gpio-cells = <2>; 5072 #gpio-cells = <2>;
5104 interrupt-controller; 5073 interrupt-controller;
5105 #interrupt-cells = <2 5074 #interrupt-cells = <2>;
5106 gpio-ranges = <&tlmm 5075 gpio-ranges = <&tlmm 0 0 181>;
5107 wakeup-parent = <&pdc 5076 wakeup-parent = <&pdc>;
5108 5077
5109 cam2_default: cam2-de 5078 cam2_default: cam2-default-state {
5110 rst-pins { 5079 rst-pins {
5111 pins 5080 pins = "gpio78";
5112 funct 5081 function = "gpio";
5113 drive 5082 drive-strength = <2>;
5114 bias- 5083 bias-disable;
5115 }; 5084 };
5116 5085
5117 mclk-pins { 5086 mclk-pins {
5118 pins 5087 pins = "gpio96";
5119 funct 5088 function = "cam_mclk";
5120 drive 5089 drive-strength = <16>;
5121 bias- 5090 bias-disable;
5122 }; 5091 };
5123 }; 5092 };
5124 5093
5125 cam2_suspend: cam2-su 5094 cam2_suspend: cam2-suspend-state {
5126 rst-pins { 5095 rst-pins {
5127 pins 5096 pins = "gpio78";
5128 funct 5097 function = "gpio";
5129 drive 5098 drive-strength = <2>;
5130 bias- 5099 bias-pull-down;
5131 outpu 5100 output-low;
5132 }; 5101 };
5133 5102
5134 mclk-pins { 5103 mclk-pins {
5135 pins 5104 pins = "gpio96";
5136 funct 5105 function = "cam_mclk";
5137 drive 5106 drive-strength = <2>;
5138 bias- 5107 bias-disable;
5139 }; 5108 };
5140 }; 5109 };
5141 5110
5142 cci0_default: cci0-de 5111 cci0_default: cci0-default-state {
5143 cci0_i2c0_def 5112 cci0_i2c0_default: cci0-i2c0-default-pins {
5144 /* SD 5113 /* SDA, SCL */
5145 pins 5114 pins = "gpio101", "gpio102";
5146 funct 5115 function = "cci_i2c";
5147 5116
5148 bias- 5117 bias-pull-up;
5149 drive 5118 drive-strength = <2>; /* 2 mA */
5150 }; 5119 };
5151 5120
5152 cci0_i2c1_def 5121 cci0_i2c1_default: cci0-i2c1-default-pins {
5153 /* SD 5122 /* SDA, SCL */
5154 pins 5123 pins = "gpio103", "gpio104";
5155 funct 5124 function = "cci_i2c";
5156 5125
5157 bias- 5126 bias-pull-up;
5158 drive 5127 drive-strength = <2>; /* 2 mA */
5159 }; 5128 };
5160 }; 5129 };
5161 5130
5162 cci0_sleep: cci0-slee 5131 cci0_sleep: cci0-sleep-state {
5163 cci0_i2c0_sle 5132 cci0_i2c0_sleep: cci0-i2c0-sleep-pins {
5164 /* SD 5133 /* SDA, SCL */
5165 pins 5134 pins = "gpio101", "gpio102";
5166 funct 5135 function = "cci_i2c";
5167 5136
5168 drive 5137 drive-strength = <2>; /* 2 mA */
5169 bias- 5138 bias-pull-down;
5170 }; 5139 };
5171 5140
5172 cci0_i2c1_sle 5141 cci0_i2c1_sleep: cci0-i2c1-sleep-pins {
5173 /* SD 5142 /* SDA, SCL */
5174 pins 5143 pins = "gpio103", "gpio104";
5175 funct 5144 function = "cci_i2c";
5176 5145
5177 drive 5146 drive-strength = <2>; /* 2 mA */
5178 bias- 5147 bias-pull-down;
5179 }; 5148 };
5180 }; 5149 };
5181 5150
5182 cci1_default: cci1-de 5151 cci1_default: cci1-default-state {
5183 cci1_i2c0_def 5152 cci1_i2c0_default: cci1-i2c0-default-pins {
5184 /* SD 5153 /* SDA, SCL */
5185 pins 5154 pins = "gpio105","gpio106";
5186 funct 5155 function = "cci_i2c";
5187 5156
5188 bias- 5157 bias-pull-up;
5189 drive 5158 drive-strength = <2>; /* 2 mA */
5190 }; 5159 };
5191 5160
5192 cci1_i2c1_def 5161 cci1_i2c1_default: cci1-i2c1-default-pins {
5193 /* SD 5162 /* SDA, SCL */
5194 pins 5163 pins = "gpio107","gpio108";
5195 funct 5164 function = "cci_i2c";
5196 5165
5197 bias- 5166 bias-pull-up;
5198 drive 5167 drive-strength = <2>; /* 2 mA */
5199 }; 5168 };
5200 }; 5169 };
5201 5170
5202 cci1_sleep: cci1-slee 5171 cci1_sleep: cci1-sleep-state {
5203 cci1_i2c0_sle 5172 cci1_i2c0_sleep: cci1-i2c0-sleep-pins {
5204 /* SD 5173 /* SDA, SCL */
5205 pins 5174 pins = "gpio105","gpio106";
5206 funct 5175 function = "cci_i2c";
5207 5176
5208 bias- 5177 bias-pull-down;
5209 drive 5178 drive-strength = <2>; /* 2 mA */
5210 }; 5179 };
5211 5180
5212 cci1_i2c1_sle 5181 cci1_i2c1_sleep: cci1-i2c1-sleep-pins {
5213 /* SD 5182 /* SDA, SCL */
5214 pins 5183 pins = "gpio107","gpio108";
5215 funct 5184 function = "cci_i2c";
5216 5185
5217 bias- 5186 bias-pull-down;
5218 drive 5187 drive-strength = <2>; /* 2 mA */
5219 }; 5188 };
5220 }; 5189 };
5221 5190
5222 pri_mi2s_active: pri- 5191 pri_mi2s_active: pri-mi2s-active-state {
5223 sclk-pins { 5192 sclk-pins {
5224 pins 5193 pins = "gpio138";
5225 funct 5194 function = "mi2s0_sck";
5226 drive 5195 drive-strength = <8>;
5227 bias- 5196 bias-disable;
5228 }; 5197 };
5229 5198
5230 ws-pins { 5199 ws-pins {
5231 pins 5200 pins = "gpio141";
5232 funct 5201 function = "mi2s0_ws";
5233 drive 5202 drive-strength = <8>;
5234 outpu 5203 output-high;
5235 }; 5204 };
5236 5205
5237 data0-pins { 5206 data0-pins {
5238 pins 5207 pins = "gpio139";
5239 funct 5208 function = "mi2s0_data0";
5240 drive 5209 drive-strength = <8>;
5241 bias- 5210 bias-disable;
5242 outpu 5211 output-high;
5243 }; 5212 };
5244 5213
5245 data1-pins { 5214 data1-pins {
5246 pins 5215 pins = "gpio140";
5247 funct 5216 function = "mi2s0_data1";
5248 drive 5217 drive-strength = <8>;
5249 outpu 5218 output-high;
5250 }; 5219 };
5251 }; 5220 };
5252 5221
5253 qup_i2c0_default: qup 5222 qup_i2c0_default: qup-i2c0-default-state {
5254 pins = "gpio2 5223 pins = "gpio28", "gpio29";
5255 function = "q 5224 function = "qup0";
5256 drive-strengt 5225 drive-strength = <2>;
5257 bias-disable; 5226 bias-disable;
5258 }; 5227 };
5259 5228
5260 qup_i2c1_default: qup 5229 qup_i2c1_default: qup-i2c1-default-state {
5261 pins = "gpio4 5230 pins = "gpio4", "gpio5";
5262 function = "q 5231 function = "qup1";
5263 drive-strengt 5232 drive-strength = <2>;
5264 bias-disable; 5233 bias-disable;
5265 }; 5234 };
5266 5235
5267 qup_i2c2_default: qup 5236 qup_i2c2_default: qup-i2c2-default-state {
5268 pins = "gpio1 5237 pins = "gpio115", "gpio116";
5269 function = "q 5238 function = "qup2";
5270 drive-strengt 5239 drive-strength = <2>;
5271 bias-disable; 5240 bias-disable;
5272 }; 5241 };
5273 5242
5274 qup_i2c3_default: qup 5243 qup_i2c3_default: qup-i2c3-default-state {
5275 pins = "gpio1 5244 pins = "gpio119", "gpio120";
5276 function = "q 5245 function = "qup3";
5277 drive-strengt 5246 drive-strength = <2>;
5278 bias-disable; 5247 bias-disable;
5279 }; 5248 };
5280 5249
5281 qup_i2c4_default: qup 5250 qup_i2c4_default: qup-i2c4-default-state {
5282 pins = "gpio8 5251 pins = "gpio8", "gpio9";
5283 function = "q 5252 function = "qup4";
5284 drive-strengt 5253 drive-strength = <2>;
5285 bias-disable; 5254 bias-disable;
5286 }; 5255 };
5287 5256
5288 qup_i2c5_default: qup 5257 qup_i2c5_default: qup-i2c5-default-state {
5289 pins = "gpio1 5258 pins = "gpio12", "gpio13";
5290 function = "q 5259 function = "qup5";
5291 drive-strengt 5260 drive-strength = <2>;
5292 bias-disable; 5261 bias-disable;
5293 }; 5262 };
5294 5263
5295 qup_i2c6_default: qup 5264 qup_i2c6_default: qup-i2c6-default-state {
5296 pins = "gpio1 5265 pins = "gpio16", "gpio17";
5297 function = "q 5266 function = "qup6";
5298 drive-strengt 5267 drive-strength = <2>;
5299 bias-disable; 5268 bias-disable;
5300 }; 5269 };
5301 5270
5302 qup_i2c7_default: qup 5271 qup_i2c7_default: qup-i2c7-default-state {
5303 pins = "gpio2 5272 pins = "gpio20", "gpio21";
5304 function = "q 5273 function = "qup7";
5305 drive-strengt 5274 drive-strength = <2>;
5306 bias-disable; 5275 bias-disable;
5307 }; 5276 };
5308 5277
5309 qup_i2c8_default: qup 5278 qup_i2c8_default: qup-i2c8-default-state {
5310 pins = "gpio2 5279 pins = "gpio24", "gpio25";
5311 function = "q 5280 function = "qup8";
5312 drive-strengt 5281 drive-strength = <2>;
5313 bias-disable; 5282 bias-disable;
5314 }; 5283 };
5315 5284
5316 qup_i2c9_default: qup 5285 qup_i2c9_default: qup-i2c9-default-state {
5317 pins = "gpio1 5286 pins = "gpio125", "gpio126";
5318 function = "q 5287 function = "qup9";
5319 drive-strengt 5288 drive-strength = <2>;
5320 bias-disable; 5289 bias-disable;
5321 }; 5290 };
5322 5291
5323 qup_i2c10_default: qu 5292 qup_i2c10_default: qup-i2c10-default-state {
5324 pins = "gpio1 5293 pins = "gpio129", "gpio130";
5325 function = "q 5294 function = "qup10";
5326 drive-strengt 5295 drive-strength = <2>;
5327 bias-disable; 5296 bias-disable;
5328 }; 5297 };
5329 5298
5330 qup_i2c11_default: qu 5299 qup_i2c11_default: qup-i2c11-default-state {
5331 pins = "gpio6 5300 pins = "gpio60", "gpio61";
5332 function = "q 5301 function = "qup11";
5333 drive-strengt 5302 drive-strength = <2>;
5334 bias-disable; 5303 bias-disable;
5335 }; 5304 };
5336 5305
5337 qup_i2c12_default: qu 5306 qup_i2c12_default: qup-i2c12-default-state {
5338 pins = "gpio3 5307 pins = "gpio32", "gpio33";
5339 function = "q 5308 function = "qup12";
5340 drive-strengt 5309 drive-strength = <2>;
5341 bias-disable; 5310 bias-disable;
5342 }; 5311 };
5343 5312
5344 qup_i2c13_default: qu 5313 qup_i2c13_default: qup-i2c13-default-state {
5345 pins = "gpio3 5314 pins = "gpio36", "gpio37";
5346 function = "q 5315 function = "qup13";
5347 drive-strengt 5316 drive-strength = <2>;
5348 bias-disable; 5317 bias-disable;
5349 }; 5318 };
5350 5319
5351 qup_i2c14_default: qu 5320 qup_i2c14_default: qup-i2c14-default-state {
5352 pins = "gpio4 5321 pins = "gpio40", "gpio41";
5353 function = "q 5322 function = "qup14";
5354 drive-strengt 5323 drive-strength = <2>;
5355 bias-disable; 5324 bias-disable;
5356 }; 5325 };
5357 5326
5358 qup_i2c15_default: qu 5327 qup_i2c15_default: qup-i2c15-default-state {
5359 pins = "gpio4 5328 pins = "gpio44", "gpio45";
5360 function = "q 5329 function = "qup15";
5361 drive-strengt 5330 drive-strength = <2>;
5362 bias-disable; 5331 bias-disable;
5363 }; 5332 };
5364 5333
5365 qup_i2c16_default: qu 5334 qup_i2c16_default: qup-i2c16-default-state {
5366 pins = "gpio4 5335 pins = "gpio48", "gpio49";
5367 function = "q 5336 function = "qup16";
5368 drive-strengt 5337 drive-strength = <2>;
5369 bias-disable; 5338 bias-disable;
5370 }; 5339 };
5371 5340
5372 qup_i2c17_default: qu 5341 qup_i2c17_default: qup-i2c17-default-state {
5373 pins = "gpio5 5342 pins = "gpio52", "gpio53";
5374 function = "q 5343 function = "qup17";
5375 drive-strengt 5344 drive-strength = <2>;
5376 bias-disable; 5345 bias-disable;
5377 }; 5346 };
5378 5347
5379 qup_i2c18_default: qu 5348 qup_i2c18_default: qup-i2c18-default-state {
5380 pins = "gpio5 5349 pins = "gpio56", "gpio57";
5381 function = "q 5350 function = "qup18";
5382 drive-strengt 5351 drive-strength = <2>;
5383 bias-disable; 5352 bias-disable;
5384 }; 5353 };
5385 5354
5386 qup_i2c19_default: qu 5355 qup_i2c19_default: qup-i2c19-default-state {
5387 pins = "gpio0 5356 pins = "gpio0", "gpio1";
5388 function = "q 5357 function = "qup19";
5389 drive-strengt 5358 drive-strength = <2>;
5390 bias-disable; 5359 bias-disable;
5391 }; 5360 };
5392 5361
5393 qup_spi0_cs: qup-spi0 5362 qup_spi0_cs: qup-spi0-cs-state {
5394 pins = "gpio3 5363 pins = "gpio31";
5395 function = "q 5364 function = "qup0";
5396 }; 5365 };
5397 5366
5398 qup_spi0_cs_gpio: qup 5367 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state {
5399 pins = "gpio3 5368 pins = "gpio31";
5400 function = "g 5369 function = "gpio";
5401 }; 5370 };
5402 5371
5403 qup_spi0_data_clk: qu 5372 qup_spi0_data_clk: qup-spi0-data-clk-state {
5404 pins = "gpio2 5373 pins = "gpio28", "gpio29",
5405 "gpio3 5374 "gpio30";
5406 function = "q 5375 function = "qup0";
5407 }; 5376 };
5408 5377
5409 qup_spi1_cs: qup-spi1 5378 qup_spi1_cs: qup-spi1-cs-state {
5410 pins = "gpio7 5379 pins = "gpio7";
5411 function = "q 5380 function = "qup1";
5412 }; 5381 };
5413 5382
5414 qup_spi1_cs_gpio: qup 5383 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state {
5415 pins = "gpio7 5384 pins = "gpio7";
5416 function = "g 5385 function = "gpio";
5417 }; 5386 };
5418 5387
5419 qup_spi1_data_clk: qu 5388 qup_spi1_data_clk: qup-spi1-data-clk-state {
5420 pins = "gpio4 5389 pins = "gpio4", "gpio5",
5421 "gpio6 5390 "gpio6";
5422 function = "q 5391 function = "qup1";
5423 }; 5392 };
5424 5393
5425 qup_spi2_cs: qup-spi2 5394 qup_spi2_cs: qup-spi2-cs-state {
5426 pins = "gpio1 5395 pins = "gpio118";
5427 function = "q 5396 function = "qup2";
5428 }; 5397 };
5429 5398
5430 qup_spi2_cs_gpio: qup 5399 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state {
5431 pins = "gpio1 5400 pins = "gpio118";
5432 function = "g 5401 function = "gpio";
5433 }; 5402 };
5434 5403
5435 qup_spi2_data_clk: qu 5404 qup_spi2_data_clk: qup-spi2-data-clk-state {
5436 pins = "gpio1 5405 pins = "gpio115", "gpio116",
5437 "gpio1 5406 "gpio117";
5438 function = "q 5407 function = "qup2";
5439 }; 5408 };
5440 5409
5441 qup_spi3_cs: qup-spi3 5410 qup_spi3_cs: qup-spi3-cs-state {
5442 pins = "gpio1 5411 pins = "gpio122";
5443 function = "q 5412 function = "qup3";
5444 }; 5413 };
5445 5414
5446 qup_spi3_cs_gpio: qup 5415 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state {
5447 pins = "gpio1 5416 pins = "gpio122";
5448 function = "g 5417 function = "gpio";
5449 }; 5418 };
5450 5419
5451 qup_spi3_data_clk: qu 5420 qup_spi3_data_clk: qup-spi3-data-clk-state {
5452 pins = "gpio1 5421 pins = "gpio119", "gpio120",
5453 "gpio1 5422 "gpio121";
5454 function = "q 5423 function = "qup3";
5455 }; 5424 };
5456 5425
5457 qup_spi4_cs: qup-spi4 5426 qup_spi4_cs: qup-spi4-cs-state {
5458 pins = "gpio1 5427 pins = "gpio11";
5459 function = "q 5428 function = "qup4";
5460 }; 5429 };
5461 5430
5462 qup_spi4_cs_gpio: qup 5431 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state {
5463 pins = "gpio1 5432 pins = "gpio11";
5464 function = "g 5433 function = "gpio";
5465 }; 5434 };
5466 5435
5467 qup_spi4_data_clk: qu 5436 qup_spi4_data_clk: qup-spi4-data-clk-state {
5468 pins = "gpio8 5437 pins = "gpio8", "gpio9",
5469 "gpio1 5438 "gpio10";
5470 function = "q 5439 function = "qup4";
5471 }; 5440 };
5472 5441
5473 qup_spi5_cs: qup-spi5 5442 qup_spi5_cs: qup-spi5-cs-state {
5474 pins = "gpio1 5443 pins = "gpio15";
5475 function = "q 5444 function = "qup5";
5476 }; 5445 };
5477 5446
5478 qup_spi5_cs_gpio: qup 5447 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state {
5479 pins = "gpio1 5448 pins = "gpio15";
5480 function = "g 5449 function = "gpio";
5481 }; 5450 };
5482 5451
5483 qup_spi5_data_clk: qu 5452 qup_spi5_data_clk: qup-spi5-data-clk-state {
5484 pins = "gpio1 5453 pins = "gpio12", "gpio13",
5485 "gpio1 5454 "gpio14";
5486 function = "q 5455 function = "qup5";
5487 }; 5456 };
5488 5457
5489 qup_spi6_cs: qup-spi6 5458 qup_spi6_cs: qup-spi6-cs-state {
5490 pins = "gpio1 5459 pins = "gpio19";
5491 function = "q 5460 function = "qup6";
5492 }; 5461 };
5493 5462
5494 qup_spi6_cs_gpio: qup 5463 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state {
5495 pins = "gpio1 5464 pins = "gpio19";
5496 function = "g 5465 function = "gpio";
5497 }; 5466 };
5498 5467
5499 qup_spi6_data_clk: qu 5468 qup_spi6_data_clk: qup-spi6-data-clk-state {
5500 pins = "gpio1 5469 pins = "gpio16", "gpio17",
5501 "gpio1 5470 "gpio18";
5502 function = "q 5471 function = "qup6";
5503 }; 5472 };
5504 5473
5505 qup_spi7_cs: qup-spi7 5474 qup_spi7_cs: qup-spi7-cs-state {
5506 pins = "gpio2 5475 pins = "gpio23";
5507 function = "q 5476 function = "qup7";
5508 }; 5477 };
5509 5478
5510 qup_spi7_cs_gpio: qup 5479 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state {
5511 pins = "gpio2 5480 pins = "gpio23";
5512 function = "g 5481 function = "gpio";
5513 }; 5482 };
5514 5483
5515 qup_spi7_data_clk: qu 5484 qup_spi7_data_clk: qup-spi7-data-clk-state {
5516 pins = "gpio2 5485 pins = "gpio20", "gpio21",
5517 "gpio2 5486 "gpio22";
5518 function = "q 5487 function = "qup7";
5519 }; 5488 };
5520 5489
5521 qup_spi8_cs: qup-spi8 5490 qup_spi8_cs: qup-spi8-cs-state {
5522 pins = "gpio2 5491 pins = "gpio27";
5523 function = "q 5492 function = "qup8";
5524 }; 5493 };
5525 5494
5526 qup_spi8_cs_gpio: qup 5495 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state {
5527 pins = "gpio2 5496 pins = "gpio27";
5528 function = "g 5497 function = "gpio";
5529 }; 5498 };
5530 5499
5531 qup_spi8_data_clk: qu 5500 qup_spi8_data_clk: qup-spi8-data-clk-state {
5532 pins = "gpio2 5501 pins = "gpio24", "gpio25",
5533 "gpio2 5502 "gpio26";
5534 function = "q 5503 function = "qup8";
5535 }; 5504 };
5536 5505
5537 qup_spi9_cs: qup-spi9 5506 qup_spi9_cs: qup-spi9-cs-state {
5538 pins = "gpio1 5507 pins = "gpio128";
5539 function = "q 5508 function = "qup9";
5540 }; 5509 };
5541 5510
5542 qup_spi9_cs_gpio: qup 5511 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state {
5543 pins = "gpio1 5512 pins = "gpio128";
5544 function = "g 5513 function = "gpio";
5545 }; 5514 };
5546 5515
5547 qup_spi9_data_clk: qu 5516 qup_spi9_data_clk: qup-spi9-data-clk-state {
5548 pins = "gpio1 5517 pins = "gpio125", "gpio126",
5549 "gpio1 5518 "gpio127";
5550 function = "q 5519 function = "qup9";
5551 }; 5520 };
5552 5521
5553 qup_spi10_cs: qup-spi 5522 qup_spi10_cs: qup-spi10-cs-state {
5554 pins = "gpio1 5523 pins = "gpio132";
5555 function = "q 5524 function = "qup10";
5556 }; 5525 };
5557 5526
5558 qup_spi10_cs_gpio: qu 5527 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state {
5559 pins = "gpio1 5528 pins = "gpio132";
5560 function = "g 5529 function = "gpio";
5561 }; 5530 };
5562 5531
5563 qup_spi10_data_clk: q 5532 qup_spi10_data_clk: qup-spi10-data-clk-state {
5564 pins = "gpio1 5533 pins = "gpio129", "gpio130",
5565 "gpio1 5534 "gpio131";
5566 function = "q 5535 function = "qup10";
5567 }; 5536 };
5568 5537
5569 qup_spi11_cs: qup-spi 5538 qup_spi11_cs: qup-spi11-cs-state {
5570 pins = "gpio6 5539 pins = "gpio63";
5571 function = "q 5540 function = "qup11";
5572 }; 5541 };
5573 5542
5574 qup_spi11_cs_gpio: qu 5543 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state {
5575 pins = "gpio6 5544 pins = "gpio63";
5576 function = "g 5545 function = "gpio";
5577 }; 5546 };
5578 5547
5579 qup_spi11_data_clk: q 5548 qup_spi11_data_clk: qup-spi11-data-clk-state {
5580 pins = "gpio6 5549 pins = "gpio60", "gpio61",
5581 "gpio6 5550 "gpio62";
5582 function = "q 5551 function = "qup11";
5583 }; 5552 };
5584 5553
5585 qup_spi12_cs: qup-spi 5554 qup_spi12_cs: qup-spi12-cs-state {
5586 pins = "gpio3 5555 pins = "gpio35";
5587 function = "q 5556 function = "qup12";
5588 }; 5557 };
5589 5558
5590 qup_spi12_cs_gpio: qu 5559 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state {
5591 pins = "gpio3 5560 pins = "gpio35";
5592 function = "g 5561 function = "gpio";
5593 }; 5562 };
5594 5563
5595 qup_spi12_data_clk: q 5564 qup_spi12_data_clk: qup-spi12-data-clk-state {
5596 pins = "gpio3 5565 pins = "gpio32", "gpio33",
5597 "gpio3 5566 "gpio34";
5598 function = "q 5567 function = "qup12";
5599 }; 5568 };
5600 5569
5601 qup_spi13_cs: qup-spi 5570 qup_spi13_cs: qup-spi13-cs-state {
5602 pins = "gpio3 5571 pins = "gpio39";
5603 function = "q 5572 function = "qup13";
5604 }; 5573 };
5605 5574
5606 qup_spi13_cs_gpio: qu 5575 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state {
5607 pins = "gpio3 5576 pins = "gpio39";
5608 function = "g 5577 function = "gpio";
5609 }; 5578 };
5610 5579
5611 qup_spi13_data_clk: q 5580 qup_spi13_data_clk: qup-spi13-data-clk-state {
5612 pins = "gpio3 5581 pins = "gpio36", "gpio37",
5613 "gpio3 5582 "gpio38";
5614 function = "q 5583 function = "qup13";
5615 }; 5584 };
5616 5585
5617 qup_spi14_cs: qup-spi 5586 qup_spi14_cs: qup-spi14-cs-state {
5618 pins = "gpio4 5587 pins = "gpio43";
5619 function = "q 5588 function = "qup14";
5620 }; 5589 };
5621 5590
5622 qup_spi14_cs_gpio: qu 5591 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state {
5623 pins = "gpio4 5592 pins = "gpio43";
5624 function = "g 5593 function = "gpio";
5625 }; 5594 };
5626 5595
5627 qup_spi14_data_clk: q 5596 qup_spi14_data_clk: qup-spi14-data-clk-state {
5628 pins = "gpio4 5597 pins = "gpio40", "gpio41",
5629 "gpio4 5598 "gpio42";
5630 function = "q 5599 function = "qup14";
5631 }; 5600 };
5632 5601
5633 qup_spi15_cs: qup-spi 5602 qup_spi15_cs: qup-spi15-cs-state {
5634 pins = "gpio4 5603 pins = "gpio47";
5635 function = "q 5604 function = "qup15";
5636 }; 5605 };
5637 5606
5638 qup_spi15_cs_gpio: qu 5607 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state {
5639 pins = "gpio4 5608 pins = "gpio47";
5640 function = "g 5609 function = "gpio";
5641 }; 5610 };
5642 5611
5643 qup_spi15_data_clk: q 5612 qup_spi15_data_clk: qup-spi15-data-clk-state {
5644 pins = "gpio4 5613 pins = "gpio44", "gpio45",
5645 "gpio4 5614 "gpio46";
5646 function = "q 5615 function = "qup15";
5647 }; 5616 };
5648 5617
5649 qup_spi16_cs: qup-spi 5618 qup_spi16_cs: qup-spi16-cs-state {
5650 pins = "gpio5 5619 pins = "gpio51";
5651 function = "q 5620 function = "qup16";
5652 }; 5621 };
5653 5622
5654 qup_spi16_cs_gpio: qu 5623 qup_spi16_cs_gpio: qup-spi16-cs-gpio-state {
5655 pins = "gpio5 5624 pins = "gpio51";
5656 function = "g 5625 function = "gpio";
5657 }; 5626 };
5658 5627
5659 qup_spi16_data_clk: q 5628 qup_spi16_data_clk: qup-spi16-data-clk-state {
5660 pins = "gpio4 5629 pins = "gpio48", "gpio49",
5661 "gpio5 5630 "gpio50";
5662 function = "q 5631 function = "qup16";
5663 }; 5632 };
5664 5633
5665 qup_spi17_cs: qup-spi 5634 qup_spi17_cs: qup-spi17-cs-state {
5666 pins = "gpio5 5635 pins = "gpio55";
5667 function = "q 5636 function = "qup17";
5668 }; 5637 };
5669 5638
5670 qup_spi17_cs_gpio: qu 5639 qup_spi17_cs_gpio: qup-spi17-cs-gpio-state {
5671 pins = "gpio5 5640 pins = "gpio55";
5672 function = "g 5641 function = "gpio";
5673 }; 5642 };
5674 5643
5675 qup_spi17_data_clk: q 5644 qup_spi17_data_clk: qup-spi17-data-clk-state {
5676 pins = "gpio5 5645 pins = "gpio52", "gpio53",
5677 "gpio5 5646 "gpio54";
5678 function = "q 5647 function = "qup17";
5679 }; 5648 };
5680 5649
5681 qup_spi18_cs: qup-spi 5650 qup_spi18_cs: qup-spi18-cs-state {
5682 pins = "gpio5 5651 pins = "gpio59";
5683 function = "q 5652 function = "qup18";
5684 }; 5653 };
5685 5654
5686 qup_spi18_cs_gpio: qu 5655 qup_spi18_cs_gpio: qup-spi18-cs-gpio-state {
5687 pins = "gpio5 5656 pins = "gpio59";
5688 function = "g 5657 function = "gpio";
5689 }; 5658 };
5690 5659
5691 qup_spi18_data_clk: q 5660 qup_spi18_data_clk: qup-spi18-data-clk-state {
5692 pins = "gpio5 5661 pins = "gpio56", "gpio57",
5693 "gpio5 5662 "gpio58";
5694 function = "q 5663 function = "qup18";
5695 }; 5664 };
5696 5665
5697 qup_spi19_cs: qup-spi 5666 qup_spi19_cs: qup-spi19-cs-state {
5698 pins = "gpio3 5667 pins = "gpio3";
5699 function = "q 5668 function = "qup19";
5700 }; 5669 };
5701 5670
5702 qup_spi19_cs_gpio: qu 5671 qup_spi19_cs_gpio: qup-spi19-cs-gpio-state {
5703 pins = "gpio3 5672 pins = "gpio3";
5704 function = "g 5673 function = "gpio";
5705 }; 5674 };
5706 5675
5707 qup_spi19_data_clk: q 5676 qup_spi19_data_clk: qup-spi19-data-clk-state {
5708 pins = "gpio0 5677 pins = "gpio0", "gpio1",
5709 "gpio2 5678 "gpio2";
5710 function = "q 5679 function = "qup19";
5711 }; 5680 };
5712 5681
5713 qup_uart2_default: qu 5682 qup_uart2_default: qup-uart2-default-state {
5714 pins = "gpio1 5683 pins = "gpio117", "gpio118";
5715 function = "q 5684 function = "qup2";
5716 }; 5685 };
5717 5686
5718 qup_uart6_default: qu 5687 qup_uart6_default: qup-uart6-default-state {
5719 pins = "gpio1 5688 pins = "gpio16", "gpio17", "gpio18", "gpio19";
5720 function = "q 5689 function = "qup6";
5721 }; 5690 };
5722 5691
5723 qup_uart12_default: q 5692 qup_uart12_default: qup-uart12-default-state {
5724 pins = "gpio3 5693 pins = "gpio34", "gpio35";
5725 function = "q 5694 function = "qup12";
5726 }; 5695 };
5727 5696
5728 qup_uart17_default: q 5697 qup_uart17_default: qup-uart17-default-state {
5729 pins = "gpio5 5698 pins = "gpio52", "gpio53", "gpio54", "gpio55";
5730 function = "q 5699 function = "qup17";
5731 }; 5700 };
5732 5701
5733 qup_uart18_default: q 5702 qup_uart18_default: qup-uart18-default-state {
5734 pins = "gpio5 5703 pins = "gpio58", "gpio59";
5735 function = "q 5704 function = "qup18";
5736 }; 5705 };
5737 5706
5738 tert_mi2s_active: ter 5707 tert_mi2s_active: tert-mi2s-active-state {
5739 sck-pins { 5708 sck-pins {
5740 pins 5709 pins = "gpio133";
5741 funct 5710 function = "mi2s2_sck";
5742 drive 5711 drive-strength = <8>;
5743 bias- 5712 bias-disable;
5744 }; 5713 };
5745 5714
5746 data0-pins { 5715 data0-pins {
5747 pins 5716 pins = "gpio134";
5748 funct 5717 function = "mi2s2_data0";
5749 drive 5718 drive-strength = <8>;
5750 bias- 5719 bias-disable;
5751 outpu 5720 output-high;
5752 }; 5721 };
5753 5722
5754 ws-pins { 5723 ws-pins {
5755 pins 5724 pins = "gpio135";
5756 funct 5725 function = "mi2s2_ws";
5757 drive 5726 drive-strength = <8>;
5758 outpu 5727 output-high;
5759 }; 5728 };
5760 }; 5729 };
5761 5730
5762 sdc2_sleep_state: sdc 5731 sdc2_sleep_state: sdc2-sleep-state {
5763 clk-pins { 5732 clk-pins {
5764 pins 5733 pins = "sdc2_clk";
5765 drive 5734 drive-strength = <2>;
5766 bias- 5735 bias-disable;
5767 }; 5736 };
5768 5737
5769 cmd-pins { 5738 cmd-pins {
5770 pins 5739 pins = "sdc2_cmd";
5771 drive 5740 drive-strength = <2>;
5772 bias- 5741 bias-pull-up;
5773 }; 5742 };
5774 5743
5775 data-pins { 5744 data-pins {
5776 pins 5745 pins = "sdc2_data";
5777 drive 5746 drive-strength = <2>;
5778 bias- 5747 bias-pull-up;
5779 }; 5748 };
5780 }; 5749 };
5781 5750
5782 pcie0_default_state: 5751 pcie0_default_state: pcie0-default-state {
5783 perst-pins { 5752 perst-pins {
5784 pins 5753 pins = "gpio79";
5785 funct 5754 function = "gpio";
5786 drive 5755 drive-strength = <2>;
5787 bias- 5756 bias-pull-down;
5788 }; 5757 };
5789 5758
5790 clkreq-pins { 5759 clkreq-pins {
5791 pins 5760 pins = "gpio80";
5792 funct 5761 function = "pci_e0";
5793 drive 5762 drive-strength = <2>;
5794 bias- 5763 bias-pull-up;
5795 }; 5764 };
5796 5765
5797 wake-pins { 5766 wake-pins {
5798 pins 5767 pins = "gpio81";
5799 funct 5768 function = "gpio";
5800 drive 5769 drive-strength = <2>;
5801 bias- 5770 bias-pull-up;
5802 }; 5771 };
5803 }; 5772 };
5804 5773
5805 pcie1_default_state: 5774 pcie1_default_state: pcie1-default-state {
5806 perst-pins { 5775 perst-pins {
5807 pins 5776 pins = "gpio82";
5808 funct 5777 function = "gpio";
5809 drive 5778 drive-strength = <2>;
5810 bias- 5779 bias-pull-down;
5811 }; 5780 };
5812 5781
5813 clkreq-pins { 5782 clkreq-pins {
5814 pins 5783 pins = "gpio83";
5815 funct 5784 function = "pci_e1";
5816 drive 5785 drive-strength = <2>;
5817 bias- 5786 bias-pull-up;
5818 }; 5787 };
5819 5788
5820 wake-pins { 5789 wake-pins {
5821 pins 5790 pins = "gpio84";
5822 funct 5791 function = "gpio";
5823 drive 5792 drive-strength = <2>;
5824 bias- 5793 bias-pull-up;
5825 }; 5794 };
5826 }; 5795 };
5827 5796
5828 pcie2_default_state: 5797 pcie2_default_state: pcie2-default-state {
5829 perst-pins { 5798 perst-pins {
5830 pins 5799 pins = "gpio85";
5831 funct 5800 function = "gpio";
5832 drive 5801 drive-strength = <2>;
5833 bias- 5802 bias-pull-down;
5834 }; 5803 };
5835 5804
5836 clkreq-pins { 5805 clkreq-pins {
5837 pins 5806 pins = "gpio86";
5838 funct 5807 function = "pci_e2";
5839 drive 5808 drive-strength = <2>;
5840 bias- 5809 bias-pull-up;
5841 }; 5810 };
5842 5811
5843 wake-pins { 5812 wake-pins {
5844 pins 5813 pins = "gpio87";
5845 funct 5814 function = "gpio";
5846 drive 5815 drive-strength = <2>;
5847 bias- 5816 bias-pull-up;
5848 }; 5817 };
5849 }; 5818 };
5850 }; 5819 };
5851 5820
5852 apps_smmu: iommu@15000000 { 5821 apps_smmu: iommu@15000000 {
5853 compatible = "qcom,sm 5822 compatible = "qcom,sm8250-smmu-500", "qcom,smmu-500", "arm,mmu-500";
5854 reg = <0 0x15000000 0 5823 reg = <0 0x15000000 0 0x100000>;
5855 #iommu-cells = <2>; 5824 #iommu-cells = <2>;
5856 #global-interrupts = 5825 #global-interrupts = <2>;
5857 interrupts = <GIC_SPI 5826 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
5858 <GIC_SPI 5827 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
5859 <GIC_SPI 5828 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
5860 <GIC_SPI 5829 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
5861 <GIC_SPI 5830 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
5862 <GIC_SPI 5831 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
5863 <GIC_SPI 5832 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
5864 <GIC_SPI 5833 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
5865 <GIC_SPI 5834 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
5866 <GIC_SPI 5835 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
5867 <GIC_SPI 5836 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
5868 <GIC_SPI 5837 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
5869 <GIC_SPI 5838 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
5870 <GIC_SPI 5839 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
5871 <GIC_SPI 5840 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
5872 <GIC_SPI 5841 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
5873 <GIC_SPI 5842 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
5874 <GIC_SPI 5843 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
5875 <GIC_SPI 5844 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
5876 <GIC_SPI 5845 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
5877 <GIC_SPI 5846 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
5878 <GIC_SPI 5847 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
5879 <GIC_SPI 5848 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
5880 <GIC_SPI 5849 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
5881 <GIC_SPI 5850 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
5882 <GIC_SPI 5851 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
5883 <GIC_SPI 5852 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
5884 <GIC_SPI 5853 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
5885 <GIC_SPI 5854 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
5886 <GIC_SPI 5855 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
5887 <GIC_SPI 5856 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
5888 <GIC_SPI 5857 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
5889 <GIC_SPI 5858 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
5890 <GIC_SPI 5859 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
5891 <GIC_SPI 5860 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
5892 <GIC_SPI 5861 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
5893 <GIC_SPI 5862 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
5894 <GIC_SPI 5863 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
5895 <GIC_SPI 5864 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
5896 <GIC_SPI 5865 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
5897 <GIC_SPI 5866 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
5898 <GIC_SPI 5867 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
5899 <GIC_SPI 5868 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
5900 <GIC_SPI 5869 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
5901 <GIC_SPI 5870 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
5902 <GIC_SPI 5871 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
5903 <GIC_SPI 5872 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
5904 <GIC_SPI 5873 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
5905 <GIC_SPI 5874 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
5906 <GIC_SPI 5875 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
5907 <GIC_SPI 5876 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
5908 <GIC_SPI 5877 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
5909 <GIC_SPI 5878 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
5910 <GIC_SPI 5879 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
5911 <GIC_SPI 5880 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
5912 <GIC_SPI 5881 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
5913 <GIC_SPI 5882 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
5914 <GIC_SPI 5883 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
5915 <GIC_SPI 5884 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
5916 <GIC_SPI 5885 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
5917 <GIC_SPI 5886 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
5918 <GIC_SPI 5887 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
5919 <GIC_SPI 5888 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
5920 <GIC_SPI 5889 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
5921 <GIC_SPI 5890 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
5922 <GIC_SPI 5891 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
5923 <GIC_SPI 5892 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
5924 <GIC_SPI 5893 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
5925 <GIC_SPI 5894 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
5926 <GIC_SPI 5895 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
5927 <GIC_SPI 5896 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
5928 <GIC_SPI 5897 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
5929 <GIC_SPI 5898 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
5930 <GIC_SPI 5899 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
5931 <GIC_SPI 5900 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
5932 <GIC_SPI 5901 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
5933 <GIC_SPI 5902 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
5934 <GIC_SPI 5903 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
5935 <GIC_SPI 5904 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
5936 <GIC_SPI 5905 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
5937 <GIC_SPI 5906 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
5938 <GIC_SPI 5907 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
5939 <GIC_SPI 5908 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
5940 <GIC_SPI 5909 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
5941 <GIC_SPI 5910 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
5942 <GIC_SPI 5911 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
5943 <GIC_SPI 5912 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
5944 <GIC_SPI 5913 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
5945 <GIC_SPI 5914 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
5946 <GIC_SPI 5915 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
5947 <GIC_SPI 5916 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
5948 <GIC_SPI 5917 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
5949 <GIC_SPI 5918 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
5950 <GIC_SPI 5919 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
5951 <GIC_SPI 5920 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
5952 <GIC_SPI 5921 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
5953 <GIC_SPI 5922 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
5954 <GIC_SPI 5923 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>;
5955 dma-coherent; 5924 dma-coherent;
5956 }; 5925 };
5957 5926
5958 adsp: remoteproc@17300000 { 5927 adsp: remoteproc@17300000 {
5959 compatible = "qcom,sm 5928 compatible = "qcom,sm8250-adsp-pas";
5960 reg = <0 0x17300000 0 5929 reg = <0 0x17300000 0 0x100>;
5961 5930
5962 interrupts-extended = 5931 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
5963 5932 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
5964 5933 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
5965 5934 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
5966 5935 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
5967 interrupt-names = "wd 5936 interrupt-names = "wdog", "fatal", "ready",
5968 "ha 5937 "handover", "stop-ack";
5969 5938
5970 clocks = <&rpmhcc RPM 5939 clocks = <&rpmhcc RPMH_CXO_CLK>;
5971 clock-names = "xo"; 5940 clock-names = "xo";
5972 5941
5973 power-domains = <&rpm 5942 power-domains = <&rpmhpd RPMHPD_LCX>,
5974 <&rpm 5943 <&rpmhpd RPMHPD_LMX>;
5975 power-domain-names = 5944 power-domain-names = "lcx", "lmx";
5976 5945
5977 memory-region = <&ads 5946 memory-region = <&adsp_mem>;
5978 5947
5979 qcom,qmp = <&aoss_qmp 5948 qcom,qmp = <&aoss_qmp>;
5980 5949
5981 qcom,smem-states = <& 5950 qcom,smem-states = <&smp2p_adsp_out 0>;
5982 qcom,smem-state-names 5951 qcom,smem-state-names = "stop";
5983 5952
5984 status = "disabled"; 5953 status = "disabled";
5985 5954
5986 glink-edge { 5955 glink-edge {
5987 interrupts-ex 5956 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
5988 5957 IPCC_MPROC_SIGNAL_GLINK_QMP
5989 5958 IRQ_TYPE_EDGE_RISING>;
5990 mboxes = <&ip 5959 mboxes = <&ipcc IPCC_CLIENT_LPASS
5991 5960 IPCC_MPROC_SIGNAL_GLINK_QMP>;
5992 5961
5993 label = "lpas 5962 label = "lpass";
5994 qcom,remote-p 5963 qcom,remote-pid = <2>;
5995 5964
5996 apr { 5965 apr {
5997 compa 5966 compatible = "qcom,apr-v2";
5998 qcom, 5967 qcom,glink-channels = "apr_audio_svc";
5999 qcom, 5968 qcom,domain = <APR_DOMAIN_ADSP>;
6000 #addr 5969 #address-cells = <1>;
6001 #size 5970 #size-cells = <0>;
6002 5971
6003 servi 5972 service@3 {
6004 5973 reg = <APR_SVC_ADSP_CORE>;
6005 5974 compatible = "qcom,q6core";
6006 5975 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6007 }; 5976 };
6008 5977
6009 q6afe 5978 q6afe: service@4 {
6010 5979 compatible = "qcom,q6afe";
6011 5980 reg = <APR_SVC_AFE>;
6012 5981 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6013 5982 q6afedai: dais {
6014 5983 compatible = "qcom,q6afe-dais";
6015 5984 #address-cells = <1>;
6016 5985 #size-cells = <0>;
6017 5986 #sound-dai-cells = <1>;
6018 5987 };
6019 5988
6020 5989 q6afecc: clock-controller {
6021 5990 compatible = "qcom,q6afe-clocks";
6022 5991 #clock-cells = <2>;
6023 5992 };
6024 }; 5993 };
6025 5994
6026 q6asm 5995 q6asm: service@7 {
6027 5996 compatible = "qcom,q6asm";
6028 5997 reg = <APR_SVC_ASM>;
6029 5998 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6030 5999 q6asmdai: dais {
6031 6000 compatible = "qcom,q6asm-dais";
6032 6001 #address-cells = <1>;
6033 6002 #size-cells = <0>;
6034 6003 #sound-dai-cells = <1>;
6035 6004 iommus = <&apps_smmu 0x1801 0x0>;
6036 6005 };
6037 }; 6006 };
6038 6007
6039 q6adm 6008 q6adm: service@8 {
6040 6009 compatible = "qcom,q6adm";
6041 6010 reg = <APR_SVC_ADM>;
6042 6011 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6043 6012 q6routing: routing {
6044 6013 compatible = "qcom,q6adm-routing";
6045 6014 #sound-dai-cells = <0>;
6046 6015 };
6047 }; 6016 };
6048 }; 6017 };
6049 6018
6050 fastrpc { 6019 fastrpc {
6051 compa 6020 compatible = "qcom,fastrpc";
6052 qcom, 6021 qcom,glink-channels = "fastrpcglink-apps-dsp";
6053 label 6022 label = "adsp";
6054 qcom, 6023 qcom,non-secure-domain;
6055 #addr 6024 #address-cells = <1>;
6056 #size 6025 #size-cells = <0>;
6057 6026
6058 compu 6027 compute-cb@3 {
6059 6028 compatible = "qcom,fastrpc-compute-cb";
6060 6029 reg = <3>;
6061 6030 iommus = <&apps_smmu 0x1803 0x0>;
6062 }; 6031 };
6063 6032
6064 compu 6033 compute-cb@4 {
6065 6034 compatible = "qcom,fastrpc-compute-cb";
6066 6035 reg = <4>;
6067 6036 iommus = <&apps_smmu 0x1804 0x0>;
6068 }; 6037 };
6069 6038
6070 compu 6039 compute-cb@5 {
6071 6040 compatible = "qcom,fastrpc-compute-cb";
6072 6041 reg = <5>;
6073 6042 iommus = <&apps_smmu 0x1805 0x0>;
6074 }; 6043 };
6075 }; 6044 };
6076 }; 6045 };
6077 }; 6046 };
6078 6047
6079 intc: interrupt-controller@17 6048 intc: interrupt-controller@17a00000 {
6080 compatible = "arm,gic 6049 compatible = "arm,gic-v3";
6081 #interrupt-cells = <3 6050 #interrupt-cells = <3>;
6082 interrupt-controller; 6051 interrupt-controller;
6083 reg = <0x0 0x17a00000 6052 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
6084 <0x0 0x17a60000 6053 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
6085 interrupts = <GIC_PPI 6054 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
6086 }; 6055 };
6087 6056
6088 watchdog@17c10000 { 6057 watchdog@17c10000 {
6089 compatible = "qcom,ap 6058 compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt";
6090 reg = <0 0x17c10000 0 6059 reg = <0 0x17c10000 0 0x1000>;
6091 clocks = <&sleep_clk> 6060 clocks = <&sleep_clk>;
6092 interrupts = <GIC_SPI 6061 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
6093 }; 6062 };
6094 6063
6095 timer@17c20000 { 6064 timer@17c20000 {
6096 #address-cells = <1>; 6065 #address-cells = <1>;
6097 #size-cells = <1>; 6066 #size-cells = <1>;
6098 ranges = <0 0 0 0x200 6067 ranges = <0 0 0 0x20000000>;
6099 compatible = "arm,arm 6068 compatible = "arm,armv7-timer-mem";
6100 reg = <0x0 0x17c20000 6069 reg = <0x0 0x17c20000 0x0 0x1000>;
6101 clock-frequency = <19 6070 clock-frequency = <19200000>;
6102 6071
6103 frame@17c21000 { 6072 frame@17c21000 {
6104 frame-number 6073 frame-number = <0>;
6105 interrupts = 6074 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
6106 6075 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
6107 reg = <0x17c2 6076 reg = <0x17c21000 0x1000>,
6108 <0x17c2 6077 <0x17c22000 0x1000>;
6109 }; 6078 };
6110 6079
6111 frame@17c23000 { 6080 frame@17c23000 {
6112 frame-number 6081 frame-number = <1>;
6113 interrupts = 6082 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
6114 reg = <0x17c2 6083 reg = <0x17c23000 0x1000>;
6115 status = "dis 6084 status = "disabled";
6116 }; 6085 };
6117 6086
6118 frame@17c25000 { 6087 frame@17c25000 {
6119 frame-number 6088 frame-number = <2>;
6120 interrupts = 6089 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
6121 reg = <0x17c2 6090 reg = <0x17c25000 0x1000>;
6122 status = "dis 6091 status = "disabled";
6123 }; 6092 };
6124 6093
6125 frame@17c27000 { 6094 frame@17c27000 {
6126 frame-number 6095 frame-number = <3>;
6127 interrupts = 6096 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
6128 reg = <0x17c2 6097 reg = <0x17c27000 0x1000>;
6129 status = "dis 6098 status = "disabled";
6130 }; 6099 };
6131 6100
6132 frame@17c29000 { 6101 frame@17c29000 {
6133 frame-number 6102 frame-number = <4>;
6134 interrupts = 6103 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
6135 reg = <0x17c2 6104 reg = <0x17c29000 0x1000>;
6136 status = "dis 6105 status = "disabled";
6137 }; 6106 };
6138 6107
6139 frame@17c2b000 { 6108 frame@17c2b000 {
6140 frame-number 6109 frame-number = <5>;
6141 interrupts = 6110 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
6142 reg = <0x17c2 6111 reg = <0x17c2b000 0x1000>;
6143 status = "dis 6112 status = "disabled";
6144 }; 6113 };
6145 6114
6146 frame@17c2d000 { 6115 frame@17c2d000 {
6147 frame-number 6116 frame-number = <6>;
6148 interrupts = 6117 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
6149 reg = <0x17c2 6118 reg = <0x17c2d000 0x1000>;
6150 status = "dis 6119 status = "disabled";
6151 }; 6120 };
6152 }; 6121 };
6153 6122
6154 apps_rsc: rsc@18200000 { 6123 apps_rsc: rsc@18200000 {
6155 label = "apps_rsc"; 6124 label = "apps_rsc";
6156 compatible = "qcom,rp 6125 compatible = "qcom,rpmh-rsc";
6157 reg = <0x0 0x18200000 6126 reg = <0x0 0x18200000 0x0 0x10000>,
6158 <0x0 0x182100 6127 <0x0 0x18210000 0x0 0x10000>,
6159 <0x0 0x182200 6128 <0x0 0x18220000 0x0 0x10000>;
6160 reg-names = "drv-0", 6129 reg-names = "drv-0", "drv-1", "drv-2";
6161 interrupts = <GIC_SPI 6130 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
6162 <GIC_SPI 6131 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
6163 <GIC_SPI 6132 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
6164 qcom,tcs-offset = <0x 6133 qcom,tcs-offset = <0xd00>;
6165 qcom,drv-id = <2>; 6134 qcom,drv-id = <2>;
6166 qcom,tcs-config = <AC 6135 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
6167 <WA 6136 <WAKE_TCS 3>, <CONTROL_TCS 1>;
6168 power-domains = <&CLU 6137 power-domains = <&CLUSTER_PD>;
6169 6138
6170 rpmhcc: clock-control 6139 rpmhcc: clock-controller {
6171 compatible = 6140 compatible = "qcom,sm8250-rpmh-clk";
6172 #clock-cells 6141 #clock-cells = <1>;
6173 clock-names = 6142 clock-names = "xo";
6174 clocks = <&xo 6143 clocks = <&xo_board>;
6175 }; 6144 };
6176 6145
6177 rpmhpd: power-control 6146 rpmhpd: power-controller {
6178 compatible = 6147 compatible = "qcom,sm8250-rpmhpd";
6179 #power-domain 6148 #power-domain-cells = <1>;
6180 operating-poi 6149 operating-points-v2 = <&rpmhpd_opp_table>;
6181 6150
6182 rpmhpd_opp_ta 6151 rpmhpd_opp_table: opp-table {
6183 compa 6152 compatible = "operating-points-v2";
6184 6153
6185 rpmhp 6154 rpmhpd_opp_ret: opp1 {
6186 6155 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
6187 }; 6156 };
6188 6157
6189 rpmhp 6158 rpmhpd_opp_min_svs: opp2 {
6190 6159 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
6191 }; 6160 };
6192 6161
6193 rpmhp 6162 rpmhpd_opp_low_svs: opp3 {
6194 6163 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
6195 }; 6164 };
6196 6165
6197 rpmhp 6166 rpmhpd_opp_svs: opp4 {
6198 6167 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
6199 }; 6168 };
6200 6169
6201 rpmhp 6170 rpmhpd_opp_svs_l1: opp5 {
6202 6171 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
6203 }; 6172 };
6204 6173
6205 rpmhp 6174 rpmhpd_opp_nom: opp6 {
6206 6175 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
6207 }; 6176 };
6208 6177
6209 rpmhp 6178 rpmhpd_opp_nom_l1: opp7 {
6210 6179 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
6211 }; 6180 };
6212 6181
6213 rpmhp 6182 rpmhpd_opp_nom_l2: opp8 {
6214 6183 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
6215 }; 6184 };
6216 6185
6217 rpmhp 6186 rpmhpd_opp_turbo: opp9 {
6218 6187 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
6219 }; 6188 };
6220 6189
6221 rpmhp 6190 rpmhpd_opp_turbo_l1: opp10 {
6222 6191 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
6223 }; 6192 };
6224 }; 6193 };
6225 }; 6194 };
6226 6195
6227 apps_bcm_voter: bcm-v 6196 apps_bcm_voter: bcm-voter {
6228 compatible = 6197 compatible = "qcom,bcm-voter";
6229 }; 6198 };
6230 }; 6199 };
6231 6200
6232 epss_l3: interconnect@1859000 6201 epss_l3: interconnect@18590000 {
6233 compatible = "qcom,sm 6202 compatible = "qcom,sm8250-epss-l3", "qcom,epss-l3";
6234 reg = <0 0x18590000 0 6203 reg = <0 0x18590000 0 0x1000>;
6235 6204
6236 clocks = <&rpmhcc RPM 6205 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
6237 clock-names = "xo", " 6206 clock-names = "xo", "alternate";
6238 6207
6239 #interconnect-cells = 6208 #interconnect-cells = <1>;
6240 }; 6209 };
6241 6210
6242 cpufreq_hw: cpufreq@18591000 6211 cpufreq_hw: cpufreq@18591000 {
6243 compatible = "qcom,sm 6212 compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss";
6244 reg = <0 0x18591000 0 6213 reg = <0 0x18591000 0 0x1000>,
6245 <0 0x18592000 0 6214 <0 0x18592000 0 0x1000>,
6246 <0 0x18593000 0 6215 <0 0x18593000 0 0x1000>;
6247 reg-names = "freq-dom 6216 reg-names = "freq-domain0", "freq-domain1",
6248 "freq-dom 6217 "freq-domain2";
6249 6218
6250 clocks = <&rpmhcc RPM 6219 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
6251 clock-names = "xo", " 6220 clock-names = "xo", "alternate";
6252 interrupts = <GIC_SPI 6221 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
6253 <GIC_SPI 6222 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
6254 <GIC_SPI 6223 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
6255 interrupt-names = "dc 6224 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
6256 #freq-domain-cells = 6225 #freq-domain-cells = <1>;
6257 #clock-cells = <1>; 6226 #clock-cells = <1>;
6258 }; 6227 };
6259 }; 6228 };
6260 6229
6261 sound: sound { 6230 sound: sound {
6262 }; 6231 };
6263 6232
6264 timer { 6233 timer {
6265 compatible = "arm,armv8-timer 6234 compatible = "arm,armv8-timer";
6266 interrupts = <GIC_PPI 13 6235 interrupts = <GIC_PPI 13
6267 (GIC_CPU_MASK 6236 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6268 <GIC_PPI 14 6237 <GIC_PPI 14
6269 (GIC_CPU_MASK 6238 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6270 <GIC_PPI 11 6239 <GIC_PPI 11
6271 (GIC_CPU_MASK 6240 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6272 <GIC_PPI 10 6241 <GIC_PPI 10
6273 (GIC_CPU_MASK 6242 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
6274 }; 6243 };
6275 6244
6276 thermal-zones { 6245 thermal-zones {
6277 cpu0-thermal { 6246 cpu0-thermal {
6278 polling-delay-passive 6247 polling-delay-passive = <250>;
>> 6248 polling-delay = <1000>;
6279 6249
6280 thermal-sensors = <&t 6250 thermal-sensors = <&tsens0 1>;
6281 6251
6282 trips { 6252 trips {
6283 cpu0_alert0: 6253 cpu0_alert0: trip-point0 {
6284 tempe 6254 temperature = <90000>;
6285 hyste 6255 hysteresis = <2000>;
6286 type 6256 type = "passive";
6287 }; 6257 };
6288 6258
6289 cpu0_alert1: 6259 cpu0_alert1: trip-point1 {
6290 tempe 6260 temperature = <95000>;
6291 hyste 6261 hysteresis = <2000>;
6292 type 6262 type = "passive";
6293 }; 6263 };
6294 6264
6295 cpu0_crit: cp 6265 cpu0_crit: cpu-crit {
6296 tempe 6266 temperature = <110000>;
6297 hyste 6267 hysteresis = <1000>;
6298 type 6268 type = "critical";
6299 }; 6269 };
6300 }; 6270 };
6301 6271
6302 cooling-maps { 6272 cooling-maps {
6303 map0 { 6273 map0 {
6304 trip 6274 trip = <&cpu0_alert0>;
6305 cooli 6275 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6306 6276 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6307 6277 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6308 6278 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6309 }; 6279 };
6310 map1 { 6280 map1 {
6311 trip 6281 trip = <&cpu0_alert1>;
6312 cooli 6282 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6313 6283 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6314 6284 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6315 6285 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6316 }; 6286 };
6317 }; 6287 };
6318 }; 6288 };
6319 6289
6320 cpu1-thermal { 6290 cpu1-thermal {
6321 polling-delay-passive 6291 polling-delay-passive = <250>;
>> 6292 polling-delay = <1000>;
6322 6293
6323 thermal-sensors = <&t 6294 thermal-sensors = <&tsens0 2>;
6324 6295
6325 trips { 6296 trips {
6326 cpu1_alert0: 6297 cpu1_alert0: trip-point0 {
6327 tempe 6298 temperature = <90000>;
6328 hyste 6299 hysteresis = <2000>;
6329 type 6300 type = "passive";
6330 }; 6301 };
6331 6302
6332 cpu1_alert1: 6303 cpu1_alert1: trip-point1 {
6333 tempe 6304 temperature = <95000>;
6334 hyste 6305 hysteresis = <2000>;
6335 type 6306 type = "passive";
6336 }; 6307 };
6337 6308
6338 cpu1_crit: cp 6309 cpu1_crit: cpu-crit {
6339 tempe 6310 temperature = <110000>;
6340 hyste 6311 hysteresis = <1000>;
6341 type 6312 type = "critical";
6342 }; 6313 };
6343 }; 6314 };
6344 6315
6345 cooling-maps { 6316 cooling-maps {
6346 map0 { 6317 map0 {
6347 trip 6318 trip = <&cpu1_alert0>;
6348 cooli 6319 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6349 6320 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6350 6321 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6351 6322 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6352 }; 6323 };
6353 map1 { 6324 map1 {
6354 trip 6325 trip = <&cpu1_alert1>;
6355 cooli 6326 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6356 6327 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6357 6328 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6358 6329 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6359 }; 6330 };
6360 }; 6331 };
6361 }; 6332 };
6362 6333
6363 cpu2-thermal { 6334 cpu2-thermal {
6364 polling-delay-passive 6335 polling-delay-passive = <250>;
>> 6336 polling-delay = <1000>;
6365 6337
6366 thermal-sensors = <&t 6338 thermal-sensors = <&tsens0 3>;
6367 6339
6368 trips { 6340 trips {
6369 cpu2_alert0: 6341 cpu2_alert0: trip-point0 {
6370 tempe 6342 temperature = <90000>;
6371 hyste 6343 hysteresis = <2000>;
6372 type 6344 type = "passive";
6373 }; 6345 };
6374 6346
6375 cpu2_alert1: 6347 cpu2_alert1: trip-point1 {
6376 tempe 6348 temperature = <95000>;
6377 hyste 6349 hysteresis = <2000>;
6378 type 6350 type = "passive";
6379 }; 6351 };
6380 6352
6381 cpu2_crit: cp 6353 cpu2_crit: cpu-crit {
6382 tempe 6354 temperature = <110000>;
6383 hyste 6355 hysteresis = <1000>;
6384 type 6356 type = "critical";
6385 }; 6357 };
6386 }; 6358 };
6387 6359
6388 cooling-maps { 6360 cooling-maps {
6389 map0 { 6361 map0 {
6390 trip 6362 trip = <&cpu2_alert0>;
6391 cooli 6363 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6392 6364 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6393 6365 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6394 6366 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6395 }; 6367 };
6396 map1 { 6368 map1 {
6397 trip 6369 trip = <&cpu2_alert1>;
6398 cooli 6370 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6399 6371 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6400 6372 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6401 6373 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6402 }; 6374 };
6403 }; 6375 };
6404 }; 6376 };
6405 6377
6406 cpu3-thermal { 6378 cpu3-thermal {
6407 polling-delay-passive 6379 polling-delay-passive = <250>;
>> 6380 polling-delay = <1000>;
6408 6381
6409 thermal-sensors = <&t 6382 thermal-sensors = <&tsens0 4>;
6410 6383
6411 trips { 6384 trips {
6412 cpu3_alert0: 6385 cpu3_alert0: trip-point0 {
6413 tempe 6386 temperature = <90000>;
6414 hyste 6387 hysteresis = <2000>;
6415 type 6388 type = "passive";
6416 }; 6389 };
6417 6390
6418 cpu3_alert1: 6391 cpu3_alert1: trip-point1 {
6419 tempe 6392 temperature = <95000>;
6420 hyste 6393 hysteresis = <2000>;
6421 type 6394 type = "passive";
6422 }; 6395 };
6423 6396
6424 cpu3_crit: cp 6397 cpu3_crit: cpu-crit {
6425 tempe 6398 temperature = <110000>;
6426 hyste 6399 hysteresis = <1000>;
6427 type 6400 type = "critical";
6428 }; 6401 };
6429 }; 6402 };
6430 6403
6431 cooling-maps { 6404 cooling-maps {
6432 map0 { 6405 map0 {
6433 trip 6406 trip = <&cpu3_alert0>;
6434 cooli 6407 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6435 6408 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6436 6409 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6437 6410 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6438 }; 6411 };
6439 map1 { 6412 map1 {
6440 trip 6413 trip = <&cpu3_alert1>;
6441 cooli 6414 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6442 6415 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6443 6416 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6444 6417 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6445 }; 6418 };
6446 }; 6419 };
6447 }; 6420 };
6448 6421
6449 cpu4-top-thermal { 6422 cpu4-top-thermal {
6450 polling-delay-passive 6423 polling-delay-passive = <250>;
>> 6424 polling-delay = <1000>;
6451 6425
6452 thermal-sensors = <&t 6426 thermal-sensors = <&tsens0 7>;
6453 6427
6454 trips { 6428 trips {
6455 cpu4_top_aler 6429 cpu4_top_alert0: trip-point0 {
6456 tempe 6430 temperature = <90000>;
6457 hyste 6431 hysteresis = <2000>;
6458 type 6432 type = "passive";
6459 }; 6433 };
6460 6434
6461 cpu4_top_aler 6435 cpu4_top_alert1: trip-point1 {
6462 tempe 6436 temperature = <95000>;
6463 hyste 6437 hysteresis = <2000>;
6464 type 6438 type = "passive";
6465 }; 6439 };
6466 6440
6467 cpu4_top_crit 6441 cpu4_top_crit: cpu-crit {
6468 tempe 6442 temperature = <110000>;
6469 hyste 6443 hysteresis = <1000>;
6470 type 6444 type = "critical";
6471 }; 6445 };
6472 }; 6446 };
6473 6447
6474 cooling-maps { 6448 cooling-maps {
6475 map0 { 6449 map0 {
6476 trip 6450 trip = <&cpu4_top_alert0>;
6477 cooli 6451 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6478 6452 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6479 6453 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6480 6454 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6481 }; 6455 };
6482 map1 { 6456 map1 {
6483 trip 6457 trip = <&cpu4_top_alert1>;
6484 cooli 6458 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6485 6459 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6486 6460 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6487 6461 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6488 }; 6462 };
6489 }; 6463 };
6490 }; 6464 };
6491 6465
6492 cpu5-top-thermal { 6466 cpu5-top-thermal {
6493 polling-delay-passive 6467 polling-delay-passive = <250>;
>> 6468 polling-delay = <1000>;
6494 6469
6495 thermal-sensors = <&t 6470 thermal-sensors = <&tsens0 8>;
6496 6471
6497 trips { 6472 trips {
6498 cpu5_top_aler 6473 cpu5_top_alert0: trip-point0 {
6499 tempe 6474 temperature = <90000>;
6500 hyste 6475 hysteresis = <2000>;
6501 type 6476 type = "passive";
6502 }; 6477 };
6503 6478
6504 cpu5_top_aler 6479 cpu5_top_alert1: trip-point1 {
6505 tempe 6480 temperature = <95000>;
6506 hyste 6481 hysteresis = <2000>;
6507 type 6482 type = "passive";
6508 }; 6483 };
6509 6484
6510 cpu5_top_crit 6485 cpu5_top_crit: cpu-crit {
6511 tempe 6486 temperature = <110000>;
6512 hyste 6487 hysteresis = <1000>;
6513 type 6488 type = "critical";
6514 }; 6489 };
6515 }; 6490 };
6516 6491
6517 cooling-maps { 6492 cooling-maps {
6518 map0 { 6493 map0 {
6519 trip 6494 trip = <&cpu5_top_alert0>;
6520 cooli 6495 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6521 6496 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6522 6497 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6523 6498 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6524 }; 6499 };
6525 map1 { 6500 map1 {
6526 trip 6501 trip = <&cpu5_top_alert1>;
6527 cooli 6502 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6528 6503 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6529 6504 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6530 6505 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6531 }; 6506 };
6532 }; 6507 };
6533 }; 6508 };
6534 6509
6535 cpu6-top-thermal { 6510 cpu6-top-thermal {
6536 polling-delay-passive 6511 polling-delay-passive = <250>;
>> 6512 polling-delay = <1000>;
6537 6513
6538 thermal-sensors = <&t 6514 thermal-sensors = <&tsens0 9>;
6539 6515
6540 trips { 6516 trips {
6541 cpu6_top_aler 6517 cpu6_top_alert0: trip-point0 {
6542 tempe 6518 temperature = <90000>;
6543 hyste 6519 hysteresis = <2000>;
6544 type 6520 type = "passive";
6545 }; 6521 };
6546 6522
6547 cpu6_top_aler 6523 cpu6_top_alert1: trip-point1 {
6548 tempe 6524 temperature = <95000>;
6549 hyste 6525 hysteresis = <2000>;
6550 type 6526 type = "passive";
6551 }; 6527 };
6552 6528
6553 cpu6_top_crit 6529 cpu6_top_crit: cpu-crit {
6554 tempe 6530 temperature = <110000>;
6555 hyste 6531 hysteresis = <1000>;
6556 type 6532 type = "critical";
6557 }; 6533 };
6558 }; 6534 };
6559 6535
6560 cooling-maps { 6536 cooling-maps {
6561 map0 { 6537 map0 {
6562 trip 6538 trip = <&cpu6_top_alert0>;
6563 cooli 6539 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6564 6540 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6565 6541 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6566 6542 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6567 }; 6543 };
6568 map1 { 6544 map1 {
6569 trip 6545 trip = <&cpu6_top_alert1>;
6570 cooli 6546 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6571 6547 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6572 6548 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6573 6549 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6574 }; 6550 };
6575 }; 6551 };
6576 }; 6552 };
6577 6553
6578 cpu7-top-thermal { 6554 cpu7-top-thermal {
6579 polling-delay-passive 6555 polling-delay-passive = <250>;
>> 6556 polling-delay = <1000>;
6580 6557
6581 thermal-sensors = <&t 6558 thermal-sensors = <&tsens0 10>;
6582 6559
6583 trips { 6560 trips {
6584 cpu7_top_aler 6561 cpu7_top_alert0: trip-point0 {
6585 tempe 6562 temperature = <90000>;
6586 hyste 6563 hysteresis = <2000>;
6587 type 6564 type = "passive";
6588 }; 6565 };
6589 6566
6590 cpu7_top_aler 6567 cpu7_top_alert1: trip-point1 {
6591 tempe 6568 temperature = <95000>;
6592 hyste 6569 hysteresis = <2000>;
6593 type 6570 type = "passive";
6594 }; 6571 };
6595 6572
6596 cpu7_top_crit 6573 cpu7_top_crit: cpu-crit {
6597 tempe 6574 temperature = <110000>;
6598 hyste 6575 hysteresis = <1000>;
6599 type 6576 type = "critical";
6600 }; 6577 };
6601 }; 6578 };
6602 6579
6603 cooling-maps { 6580 cooling-maps {
6604 map0 { 6581 map0 {
6605 trip 6582 trip = <&cpu7_top_alert0>;
6606 cooli 6583 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6607 6584 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6608 6585 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6609 6586 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6610 }; 6587 };
6611 map1 { 6588 map1 {
6612 trip 6589 trip = <&cpu7_top_alert1>;
6613 cooli 6590 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6614 6591 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6615 6592 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6616 6593 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6617 }; 6594 };
6618 }; 6595 };
6619 }; 6596 };
6620 6597
6621 cpu4-bottom-thermal { 6598 cpu4-bottom-thermal {
6622 polling-delay-passive 6599 polling-delay-passive = <250>;
>> 6600 polling-delay = <1000>;
6623 6601
6624 thermal-sensors = <&t 6602 thermal-sensors = <&tsens0 11>;
6625 6603
6626 trips { 6604 trips {
6627 cpu4_bottom_a 6605 cpu4_bottom_alert0: trip-point0 {
6628 tempe 6606 temperature = <90000>;
6629 hyste 6607 hysteresis = <2000>;
6630 type 6608 type = "passive";
6631 }; 6609 };
6632 6610
6633 cpu4_bottom_a 6611 cpu4_bottom_alert1: trip-point1 {
6634 tempe 6612 temperature = <95000>;
6635 hyste 6613 hysteresis = <2000>;
6636 type 6614 type = "passive";
6637 }; 6615 };
6638 6616
6639 cpu4_bottom_c 6617 cpu4_bottom_crit: cpu-crit {
6640 tempe 6618 temperature = <110000>;
6641 hyste 6619 hysteresis = <1000>;
6642 type 6620 type = "critical";
6643 }; 6621 };
6644 }; 6622 };
6645 6623
6646 cooling-maps { 6624 cooling-maps {
6647 map0 { 6625 map0 {
6648 trip 6626 trip = <&cpu4_bottom_alert0>;
6649 cooli 6627 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6650 6628 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6651 6629 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6652 6630 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6653 }; 6631 };
6654 map1 { 6632 map1 {
6655 trip 6633 trip = <&cpu4_bottom_alert1>;
6656 cooli 6634 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6657 6635 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6658 6636 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6659 6637 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6660 }; 6638 };
6661 }; 6639 };
6662 }; 6640 };
6663 6641
6664 cpu5-bottom-thermal { 6642 cpu5-bottom-thermal {
6665 polling-delay-passive 6643 polling-delay-passive = <250>;
>> 6644 polling-delay = <1000>;
6666 6645
6667 thermal-sensors = <&t 6646 thermal-sensors = <&tsens0 12>;
6668 6647
6669 trips { 6648 trips {
6670 cpu5_bottom_a 6649 cpu5_bottom_alert0: trip-point0 {
6671 tempe 6650 temperature = <90000>;
6672 hyste 6651 hysteresis = <2000>;
6673 type 6652 type = "passive";
6674 }; 6653 };
6675 6654
6676 cpu5_bottom_a 6655 cpu5_bottom_alert1: trip-point1 {
6677 tempe 6656 temperature = <95000>;
6678 hyste 6657 hysteresis = <2000>;
6679 type 6658 type = "passive";
6680 }; 6659 };
6681 6660
6682 cpu5_bottom_c 6661 cpu5_bottom_crit: cpu-crit {
6683 tempe 6662 temperature = <110000>;
6684 hyste 6663 hysteresis = <1000>;
6685 type 6664 type = "critical";
6686 }; 6665 };
6687 }; 6666 };
6688 6667
6689 cooling-maps { 6668 cooling-maps {
6690 map0 { 6669 map0 {
6691 trip 6670 trip = <&cpu5_bottom_alert0>;
6692 cooli 6671 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6693 6672 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6694 6673 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6695 6674 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6696 }; 6675 };
6697 map1 { 6676 map1 {
6698 trip 6677 trip = <&cpu5_bottom_alert1>;
6699 cooli 6678 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6700 6679 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6701 6680 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6702 6681 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6703 }; 6682 };
6704 }; 6683 };
6705 }; 6684 };
6706 6685
6707 cpu6-bottom-thermal { 6686 cpu6-bottom-thermal {
6708 polling-delay-passive 6687 polling-delay-passive = <250>;
>> 6688 polling-delay = <1000>;
6709 6689
6710 thermal-sensors = <&t 6690 thermal-sensors = <&tsens0 13>;
6711 6691
6712 trips { 6692 trips {
6713 cpu6_bottom_a 6693 cpu6_bottom_alert0: trip-point0 {
6714 tempe 6694 temperature = <90000>;
6715 hyste 6695 hysteresis = <2000>;
6716 type 6696 type = "passive";
6717 }; 6697 };
6718 6698
6719 cpu6_bottom_a 6699 cpu6_bottom_alert1: trip-point1 {
6720 tempe 6700 temperature = <95000>;
6721 hyste 6701 hysteresis = <2000>;
6722 type 6702 type = "passive";
6723 }; 6703 };
6724 6704
6725 cpu6_bottom_c 6705 cpu6_bottom_crit: cpu-crit {
6726 tempe 6706 temperature = <110000>;
6727 hyste 6707 hysteresis = <1000>;
6728 type 6708 type = "critical";
6729 }; 6709 };
6730 }; 6710 };
6731 6711
6732 cooling-maps { 6712 cooling-maps {
6733 map0 { 6713 map0 {
6734 trip 6714 trip = <&cpu6_bottom_alert0>;
6735 cooli 6715 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6736 6716 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6737 6717 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6738 6718 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6739 }; 6719 };
6740 map1 { 6720 map1 {
6741 trip 6721 trip = <&cpu6_bottom_alert1>;
6742 cooli 6722 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6743 6723 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6744 6724 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6745 6725 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6746 }; 6726 };
6747 }; 6727 };
6748 }; 6728 };
6749 6729
6750 cpu7-bottom-thermal { 6730 cpu7-bottom-thermal {
6751 polling-delay-passive 6731 polling-delay-passive = <250>;
>> 6732 polling-delay = <1000>;
6752 6733
6753 thermal-sensors = <&t 6734 thermal-sensors = <&tsens0 14>;
6754 6735
6755 trips { 6736 trips {
6756 cpu7_bottom_a 6737 cpu7_bottom_alert0: trip-point0 {
6757 tempe 6738 temperature = <90000>;
6758 hyste 6739 hysteresis = <2000>;
6759 type 6740 type = "passive";
6760 }; 6741 };
6761 6742
6762 cpu7_bottom_a 6743 cpu7_bottom_alert1: trip-point1 {
6763 tempe 6744 temperature = <95000>;
6764 hyste 6745 hysteresis = <2000>;
6765 type 6746 type = "passive";
6766 }; 6747 };
6767 6748
6768 cpu7_bottom_c 6749 cpu7_bottom_crit: cpu-crit {
6769 tempe 6750 temperature = <110000>;
6770 hyste 6751 hysteresis = <1000>;
6771 type 6752 type = "critical";
6772 }; 6753 };
6773 }; 6754 };
6774 6755
6775 cooling-maps { 6756 cooling-maps {
6776 map0 { 6757 map0 {
6777 trip 6758 trip = <&cpu7_bottom_alert0>;
6778 cooli 6759 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6779 6760 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6780 6761 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6781 6762 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6782 }; 6763 };
6783 map1 { 6764 map1 {
6784 trip 6765 trip = <&cpu7_bottom_alert1>;
6785 cooli 6766 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6786 6767 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6787 6768 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6788 6769 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6789 }; 6770 };
6790 }; 6771 };
6791 }; 6772 };
6792 6773
6793 aoss0-thermal { 6774 aoss0-thermal {
6794 polling-delay-passive 6775 polling-delay-passive = <250>;
>> 6776 polling-delay = <1000>;
6795 6777
6796 thermal-sensors = <&t 6778 thermal-sensors = <&tsens0 0>;
6797 6779
6798 trips { 6780 trips {
6799 aoss0_alert0: 6781 aoss0_alert0: trip-point0 {
6800 tempe 6782 temperature = <90000>;
6801 hyste 6783 hysteresis = <2000>;
6802 type 6784 type = "hot";
6803 }; 6785 };
6804 }; 6786 };
6805 }; 6787 };
6806 6788
6807 cluster0-thermal { 6789 cluster0-thermal {
6808 polling-delay-passive 6790 polling-delay-passive = <250>;
>> 6791 polling-delay = <1000>;
6809 6792
6810 thermal-sensors = <&t 6793 thermal-sensors = <&tsens0 5>;
6811 6794
6812 trips { 6795 trips {
6813 cluster0_aler 6796 cluster0_alert0: trip-point0 {
6814 tempe 6797 temperature = <90000>;
6815 hyste 6798 hysteresis = <2000>;
6816 type 6799 type = "hot";
6817 }; 6800 };
6818 cluster0_crit 6801 cluster0_crit: cluster0-crit {
6819 tempe 6802 temperature = <110000>;
6820 hyste 6803 hysteresis = <2000>;
6821 type 6804 type = "critical";
6822 }; 6805 };
6823 }; 6806 };
6824 }; 6807 };
6825 6808
6826 cluster1-thermal { 6809 cluster1-thermal {
6827 polling-delay-passive 6810 polling-delay-passive = <250>;
>> 6811 polling-delay = <1000>;
6828 6812
6829 thermal-sensors = <&t 6813 thermal-sensors = <&tsens0 6>;
6830 6814
6831 trips { 6815 trips {
6832 cluster1_aler 6816 cluster1_alert0: trip-point0 {
6833 tempe 6817 temperature = <90000>;
6834 hyste 6818 hysteresis = <2000>;
6835 type 6819 type = "hot";
6836 }; 6820 };
6837 cluster1_crit 6821 cluster1_crit: cluster1-crit {
6838 tempe 6822 temperature = <110000>;
6839 hyste 6823 hysteresis = <2000>;
6840 type 6824 type = "critical";
6841 }; 6825 };
6842 }; 6826 };
6843 }; 6827 };
6844 6828
6845 gpu-top-thermal { 6829 gpu-top-thermal {
6846 polling-delay-passive 6830 polling-delay-passive = <250>;
>> 6831 polling-delay = <1000>;
6847 6832
6848 thermal-sensors = <&t 6833 thermal-sensors = <&tsens0 15>;
6849 6834
6850 cooling-maps { 6835 cooling-maps {
6851 map0 { 6836 map0 {
6852 trip 6837 trip = <&gpu_top_alert0>;
6853 cooli 6838 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6854 }; 6839 };
6855 }; 6840 };
6856 6841
6857 trips { 6842 trips {
6858 gpu_top_alert 6843 gpu_top_alert0: trip-point0 {
6859 tempe <<
6860 hyste <<
6861 type <<
6862 }; <<
6863 <<
6864 trip-point1 { <<
6865 tempe 6844 temperature = <90000>;
6866 hyste !! 6845 hysteresis = <2000>;
6867 type 6846 type = "hot";
6868 }; 6847 };
6869 <<
6870 trip-point2 { <<
6871 tempe <<
6872 hyste <<
6873 type <<
6874 }; <<
6875 }; 6848 };
6876 }; 6849 };
6877 6850
6878 aoss1-thermal { 6851 aoss1-thermal {
6879 polling-delay-passive 6852 polling-delay-passive = <250>;
>> 6853 polling-delay = <1000>;
6880 6854
6881 thermal-sensors = <&t 6855 thermal-sensors = <&tsens1 0>;
6882 6856
6883 trips { 6857 trips {
6884 aoss1_alert0: 6858 aoss1_alert0: trip-point0 {
6885 tempe 6859 temperature = <90000>;
6886 hyste 6860 hysteresis = <2000>;
6887 type 6861 type = "hot";
6888 }; 6862 };
6889 }; 6863 };
6890 }; 6864 };
6891 6865
6892 wlan-thermal { 6866 wlan-thermal {
6893 polling-delay-passive 6867 polling-delay-passive = <250>;
>> 6868 polling-delay = <1000>;
6894 6869
6895 thermal-sensors = <&t 6870 thermal-sensors = <&tsens1 1>;
6896 6871
6897 trips { 6872 trips {
6898 wlan_alert0: 6873 wlan_alert0: trip-point0 {
6899 tempe 6874 temperature = <90000>;
6900 hyste 6875 hysteresis = <2000>;
6901 type 6876 type = "hot";
6902 }; 6877 };
6903 }; 6878 };
6904 }; 6879 };
6905 6880
6906 video-thermal { 6881 video-thermal {
6907 polling-delay-passive 6882 polling-delay-passive = <250>;
>> 6883 polling-delay = <1000>;
6908 6884
6909 thermal-sensors = <&t 6885 thermal-sensors = <&tsens1 2>;
6910 6886
6911 trips { 6887 trips {
6912 video_alert0: 6888 video_alert0: trip-point0 {
6913 tempe 6889 temperature = <90000>;
6914 hyste 6890 hysteresis = <2000>;
6915 type 6891 type = "hot";
6916 }; 6892 };
6917 }; 6893 };
6918 }; 6894 };
6919 6895
6920 mem-thermal { 6896 mem-thermal {
6921 polling-delay-passive 6897 polling-delay-passive = <250>;
>> 6898 polling-delay = <1000>;
6922 6899
6923 thermal-sensors = <&t 6900 thermal-sensors = <&tsens1 3>;
6924 6901
6925 trips { 6902 trips {
6926 mem_alert0: t 6903 mem_alert0: trip-point0 {
6927 tempe 6904 temperature = <90000>;
6928 hyste 6905 hysteresis = <2000>;
6929 type 6906 type = "hot";
6930 }; 6907 };
6931 }; 6908 };
6932 }; 6909 };
6933 6910
6934 q6-hvx-thermal { 6911 q6-hvx-thermal {
6935 polling-delay-passive 6912 polling-delay-passive = <250>;
>> 6913 polling-delay = <1000>;
6936 6914
6937 thermal-sensors = <&t 6915 thermal-sensors = <&tsens1 4>;
6938 6916
6939 trips { 6917 trips {
6940 q6_hvx_alert0 6918 q6_hvx_alert0: trip-point0 {
6941 tempe 6919 temperature = <90000>;
6942 hyste 6920 hysteresis = <2000>;
6943 type 6921 type = "hot";
6944 }; 6922 };
6945 }; 6923 };
6946 }; 6924 };
6947 6925
6948 camera-thermal { 6926 camera-thermal {
6949 polling-delay-passive 6927 polling-delay-passive = <250>;
>> 6928 polling-delay = <1000>;
6950 6929
6951 thermal-sensors = <&t 6930 thermal-sensors = <&tsens1 5>;
6952 6931
6953 trips { 6932 trips {
6954 camera_alert0 6933 camera_alert0: trip-point0 {
6955 tempe 6934 temperature = <90000>;
6956 hyste 6935 hysteresis = <2000>;
6957 type 6936 type = "hot";
6958 }; 6937 };
6959 }; 6938 };
6960 }; 6939 };
6961 6940
6962 compute-thermal { 6941 compute-thermal {
6963 polling-delay-passive 6942 polling-delay-passive = <250>;
>> 6943 polling-delay = <1000>;
6964 6944
6965 thermal-sensors = <&t 6945 thermal-sensors = <&tsens1 6>;
6966 6946
6967 trips { 6947 trips {
6968 compute_alert 6948 compute_alert0: trip-point0 {
6969 tempe 6949 temperature = <90000>;
6970 hyste 6950 hysteresis = <2000>;
6971 type 6951 type = "hot";
6972 }; 6952 };
6973 }; 6953 };
6974 }; 6954 };
6975 6955
6976 npu-thermal { 6956 npu-thermal {
6977 polling-delay-passive 6957 polling-delay-passive = <250>;
>> 6958 polling-delay = <1000>;
6978 6959
6979 thermal-sensors = <&t 6960 thermal-sensors = <&tsens1 7>;
6980 6961
6981 trips { 6962 trips {
6982 npu_alert0: t 6963 npu_alert0: trip-point0 {
6983 tempe 6964 temperature = <90000>;
6984 hyste 6965 hysteresis = <2000>;
6985 type 6966 type = "hot";
6986 }; 6967 };
6987 }; 6968 };
6988 }; 6969 };
6989 6970
6990 gpu-bottom-thermal { 6971 gpu-bottom-thermal {
6991 polling-delay-passive 6972 polling-delay-passive = <250>;
>> 6973 polling-delay = <1000>;
6992 6974
6993 thermal-sensors = <&t 6975 thermal-sensors = <&tsens1 8>;
6994 6976
6995 cooling-maps { 6977 cooling-maps {
6996 map0 { 6978 map0 {
6997 trip 6979 trip = <&gpu_bottom_alert0>;
6998 cooli 6980 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6999 }; 6981 };
7000 }; 6982 };
7001 6983
7002 trips { 6984 trips {
7003 gpu_bottom_al 6985 gpu_bottom_alert0: trip-point0 {
7004 tempe <<
7005 hyste <<
7006 type <<
7007 }; <<
7008 <<
7009 trip-point1 { <<
7010 tempe 6986 temperature = <90000>;
7011 hyste !! 6987 hysteresis = <2000>;
7012 type 6988 type = "hot";
7013 }; <<
7014 <<
7015 trip-point2 { <<
7016 tempe <<
7017 hyste <<
7018 type <<
7019 }; 6989 };
7020 }; 6990 };
7021 }; 6991 };
7022 }; 6992 };
7023 }; 6993 };
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