1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * Copyright (c) 2021, Linaro Limited 3 * Copyright (c) 2021, Linaro Limited
4 */ 4 */
5 5
6 #include <dt-bindings/interrupt-controller/arm 6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-sm8450.h> 7 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
8 #include <dt-bindings/clock/qcom,rpmh.h> 8 #include <dt-bindings/clock/qcom,rpmh.h>
9 #include <dt-bindings/clock/qcom,sm8450-camcc. <<
10 #include <dt-bindings/clock/qcom,sm8450-dispcc <<
11 #include <dt-bindings/clock/qcom,sm8450-gpucc. <<
12 #include <dt-bindings/clock/qcom,sm8450-videoc <<
13 #include <dt-bindings/dma/qcom-gpi.h> <<
14 #include <dt-bindings/firmware/qcom,scm.h> <<
15 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/mailbox/qcom-ipcc.h> 10 #include <dt-bindings/mailbox/qcom-ipcc.h>
17 #include <dt-bindings/phy/phy-qcom-qmp.h> <<
18 #include <dt-bindings/power/qcom,rpmhpd.h> <<
19 #include <dt-bindings/power/qcom-rpmpd.h> 11 #include <dt-bindings/power/qcom-rpmpd.h>
20 #include <dt-bindings/interconnect/qcom,icc.h> <<
21 #include <dt-bindings/interconnect/qcom,sm8450 12 #include <dt-bindings/interconnect/qcom,sm8450.h>
22 #include <dt-bindings/reset/qcom,sm8450-gpucc. <<
23 #include <dt-bindings/soc/qcom,gpr.h> <<
24 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 13 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
25 #include <dt-bindings/sound/qcom,q6dsp-lpass-p <<
26 #include <dt-bindings/thermal/thermal.h> <<
27 14
28 / { 15 / {
29 interrupt-parent = <&intc>; 16 interrupt-parent = <&intc>;
30 17
31 #address-cells = <2>; 18 #address-cells = <2>;
32 #size-cells = <2>; 19 #size-cells = <2>;
33 20
34 chosen { }; 21 chosen { };
35 22
36 clocks { 23 clocks {
37 xo_board: xo-board { 24 xo_board: xo-board {
38 compatible = "fixed-cl 25 compatible = "fixed-clock";
39 #clock-cells = <0>; 26 #clock-cells = <0>;
40 clock-frequency = <768 27 clock-frequency = <76800000>;
41 }; 28 };
42 29
43 sleep_clk: sleep-clk { 30 sleep_clk: sleep-clk {
44 compatible = "fixed-cl 31 compatible = "fixed-clock";
45 #clock-cells = <0>; 32 #clock-cells = <0>;
46 clock-frequency = <320 33 clock-frequency = <32000>;
47 }; 34 };
48 }; 35 };
49 36
50 cpus { 37 cpus {
51 #address-cells = <2>; 38 #address-cells = <2>;
52 #size-cells = <0>; 39 #size-cells = <0>;
53 40
54 CPU0: cpu@0 { 41 CPU0: cpu@0 {
55 device_type = "cpu"; 42 device_type = "cpu";
56 compatible = "qcom,kry 43 compatible = "qcom,kryo780";
57 reg = <0x0 0x0>; 44 reg = <0x0 0x0>;
58 enable-method = "psci" 45 enable-method = "psci";
59 next-level-cache = <&L 46 next-level-cache = <&L2_0>;
60 power-domains = <&CPU_ 47 power-domains = <&CPU_PD0>;
61 power-domain-names = " 48 power-domain-names = "psci";
62 qcom,freq-domain = <&c 49 qcom,freq-domain = <&cpufreq_hw 0>;
63 #cooling-cells = <2>; <<
64 clocks = <&cpufreq_hw <<
65 L2_0: l2-cache { 50 L2_0: l2-cache {
66 compatible = " !! 51 compatible = "cache";
67 cache-level = !! 52 next-level-cache = <&L3_0>;
68 cache-unified; <<
69 next-level-cac <<
70 L3_0: l3-cache 53 L3_0: l3-cache {
71 compat !! 54 compatible = "cache";
72 cache- <<
73 cache- <<
74 }; 55 };
75 }; 56 };
76 }; 57 };
77 58
78 CPU1: cpu@100 { 59 CPU1: cpu@100 {
79 device_type = "cpu"; 60 device_type = "cpu";
80 compatible = "qcom,kry 61 compatible = "qcom,kryo780";
81 reg = <0x0 0x100>; 62 reg = <0x0 0x100>;
82 enable-method = "psci" 63 enable-method = "psci";
83 next-level-cache = <&L 64 next-level-cache = <&L2_100>;
84 power-domains = <&CPU_ 65 power-domains = <&CPU_PD1>;
85 power-domain-names = " 66 power-domain-names = "psci";
86 qcom,freq-domain = <&c 67 qcom,freq-domain = <&cpufreq_hw 0>;
87 #cooling-cells = <2>; <<
88 clocks = <&cpufreq_hw <<
89 L2_100: l2-cache { 68 L2_100: l2-cache {
90 compatible = " !! 69 compatible = "cache";
91 cache-level = !! 70 next-level-cache = <&L3_0>;
92 cache-unified; <<
93 next-level-cac <<
94 }; 71 };
95 }; 72 };
96 73
97 CPU2: cpu@200 { 74 CPU2: cpu@200 {
98 device_type = "cpu"; 75 device_type = "cpu";
99 compatible = "qcom,kry 76 compatible = "qcom,kryo780";
100 reg = <0x0 0x200>; 77 reg = <0x0 0x200>;
101 enable-method = "psci" 78 enable-method = "psci";
102 next-level-cache = <&L 79 next-level-cache = <&L2_200>;
103 power-domains = <&CPU_ 80 power-domains = <&CPU_PD2>;
104 power-domain-names = " 81 power-domain-names = "psci";
105 qcom,freq-domain = <&c 82 qcom,freq-domain = <&cpufreq_hw 0>;
106 #cooling-cells = <2>; <<
107 clocks = <&cpufreq_hw <<
108 L2_200: l2-cache { 83 L2_200: l2-cache {
109 compatible = " !! 84 compatible = "cache";
110 cache-level = !! 85 next-level-cache = <&L3_0>;
111 cache-unified; <<
112 next-level-cac <<
113 }; 86 };
114 }; 87 };
115 88
116 CPU3: cpu@300 { 89 CPU3: cpu@300 {
117 device_type = "cpu"; 90 device_type = "cpu";
118 compatible = "qcom,kry 91 compatible = "qcom,kryo780";
119 reg = <0x0 0x300>; 92 reg = <0x0 0x300>;
120 enable-method = "psci" 93 enable-method = "psci";
121 next-level-cache = <&L 94 next-level-cache = <&L2_300>;
122 power-domains = <&CPU_ 95 power-domains = <&CPU_PD3>;
123 power-domain-names = " 96 power-domain-names = "psci";
124 qcom,freq-domain = <&c 97 qcom,freq-domain = <&cpufreq_hw 0>;
125 #cooling-cells = <2>; <<
126 clocks = <&cpufreq_hw <<
127 L2_300: l2-cache { 98 L2_300: l2-cache {
128 compatible = " !! 99 compatible = "cache";
129 cache-level = !! 100 next-level-cache = <&L3_0>;
130 cache-unified; <<
131 next-level-cac <<
132 }; 101 };
133 }; 102 };
134 103
135 CPU4: cpu@400 { 104 CPU4: cpu@400 {
136 device_type = "cpu"; 105 device_type = "cpu";
137 compatible = "qcom,kry 106 compatible = "qcom,kryo780";
138 reg = <0x0 0x400>; 107 reg = <0x0 0x400>;
139 enable-method = "psci" 108 enable-method = "psci";
140 next-level-cache = <&L 109 next-level-cache = <&L2_400>;
141 power-domains = <&CPU_ 110 power-domains = <&CPU_PD4>;
142 power-domain-names = " 111 power-domain-names = "psci";
143 qcom,freq-domain = <&c 112 qcom,freq-domain = <&cpufreq_hw 1>;
144 #cooling-cells = <2>; <<
145 clocks = <&cpufreq_hw <<
146 L2_400: l2-cache { 113 L2_400: l2-cache {
147 compatible = " !! 114 compatible = "cache";
148 cache-level = !! 115 next-level-cache = <&L3_0>;
149 cache-unified; <<
150 next-level-cac <<
151 }; 116 };
152 }; 117 };
153 118
154 CPU5: cpu@500 { 119 CPU5: cpu@500 {
155 device_type = "cpu"; 120 device_type = "cpu";
156 compatible = "qcom,kry 121 compatible = "qcom,kryo780";
157 reg = <0x0 0x500>; 122 reg = <0x0 0x500>;
158 enable-method = "psci" 123 enable-method = "psci";
159 next-level-cache = <&L 124 next-level-cache = <&L2_500>;
160 power-domains = <&CPU_ 125 power-domains = <&CPU_PD5>;
161 power-domain-names = " 126 power-domain-names = "psci";
162 qcom,freq-domain = <&c 127 qcom,freq-domain = <&cpufreq_hw 1>;
163 #cooling-cells = <2>; <<
164 clocks = <&cpufreq_hw <<
165 L2_500: l2-cache { 128 L2_500: l2-cache {
166 compatible = " !! 129 compatible = "cache";
167 cache-level = !! 130 next-level-cache = <&L3_0>;
168 cache-unified; <<
169 next-level-cac <<
170 }; 131 };
>> 132
171 }; 133 };
172 134
173 CPU6: cpu@600 { 135 CPU6: cpu@600 {
174 device_type = "cpu"; 136 device_type = "cpu";
175 compatible = "qcom,kry 137 compatible = "qcom,kryo780";
176 reg = <0x0 0x600>; 138 reg = <0x0 0x600>;
177 enable-method = "psci" 139 enable-method = "psci";
178 next-level-cache = <&L 140 next-level-cache = <&L2_600>;
179 power-domains = <&CPU_ 141 power-domains = <&CPU_PD6>;
180 power-domain-names = " 142 power-domain-names = "psci";
181 qcom,freq-domain = <&c 143 qcom,freq-domain = <&cpufreq_hw 1>;
182 #cooling-cells = <2>; <<
183 clocks = <&cpufreq_hw <<
184 L2_600: l2-cache { 144 L2_600: l2-cache {
185 compatible = " !! 145 compatible = "cache";
186 cache-level = !! 146 next-level-cache = <&L3_0>;
187 cache-unified; <<
188 next-level-cac <<
189 }; 147 };
190 }; 148 };
191 149
192 CPU7: cpu@700 { 150 CPU7: cpu@700 {
193 device_type = "cpu"; 151 device_type = "cpu";
194 compatible = "qcom,kry 152 compatible = "qcom,kryo780";
195 reg = <0x0 0x700>; 153 reg = <0x0 0x700>;
196 enable-method = "psci" 154 enable-method = "psci";
197 next-level-cache = <&L 155 next-level-cache = <&L2_700>;
198 power-domains = <&CPU_ 156 power-domains = <&CPU_PD7>;
199 power-domain-names = " 157 power-domain-names = "psci";
200 qcom,freq-domain = <&c 158 qcom,freq-domain = <&cpufreq_hw 2>;
201 #cooling-cells = <2>; <<
202 clocks = <&cpufreq_hw <<
203 L2_700: l2-cache { 159 L2_700: l2-cache {
204 compatible = " !! 160 compatible = "cache";
205 cache-level = !! 161 next-level-cache = <&L3_0>;
206 cache-unified; <<
207 next-level-cac <<
208 }; 162 };
209 }; 163 };
210 164
211 cpu-map { 165 cpu-map {
212 cluster0 { 166 cluster0 {
213 core0 { 167 core0 {
214 cpu = 168 cpu = <&CPU0>;
215 }; 169 };
216 170
217 core1 { 171 core1 {
218 cpu = 172 cpu = <&CPU1>;
219 }; 173 };
220 174
221 core2 { 175 core2 {
222 cpu = 176 cpu = <&CPU2>;
223 }; 177 };
224 178
225 core3 { 179 core3 {
226 cpu = 180 cpu = <&CPU3>;
227 }; 181 };
228 182
229 core4 { 183 core4 {
230 cpu = 184 cpu = <&CPU4>;
231 }; 185 };
232 186
233 core5 { 187 core5 {
234 cpu = 188 cpu = <&CPU5>;
235 }; 189 };
236 190
237 core6 { 191 core6 {
238 cpu = 192 cpu = <&CPU6>;
239 }; 193 };
240 194
241 core7 { 195 core7 {
242 cpu = 196 cpu = <&CPU7>;
243 }; 197 };
244 }; 198 };
245 }; 199 };
246 200
247 idle-states { 201 idle-states {
248 entry-method = "psci"; 202 entry-method = "psci";
249 203
250 LITTLE_CPU_SLEEP_0: cp 204 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
251 compatible = " 205 compatible = "arm,idle-state";
252 idle-state-nam 206 idle-state-name = "silver-rail-power-collapse";
253 arm,psci-suspe 207 arm,psci-suspend-param = <0x40000004>;
254 entry-latency- 208 entry-latency-us = <800>;
255 exit-latency-u 209 exit-latency-us = <750>;
256 min-residency- 210 min-residency-us = <4090>;
257 local-timer-st 211 local-timer-stop;
258 }; 212 };
259 213
260 BIG_CPU_SLEEP_0: cpu-s 214 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
261 compatible = " 215 compatible = "arm,idle-state";
262 idle-state-nam 216 idle-state-name = "gold-rail-power-collapse";
263 arm,psci-suspe 217 arm,psci-suspend-param = <0x40000004>;
264 entry-latency- 218 entry-latency-us = <600>;
265 exit-latency-u 219 exit-latency-us = <1550>;
266 min-residency- 220 min-residency-us = <4791>;
267 local-timer-st 221 local-timer-stop;
268 }; 222 };
269 }; 223 };
270 224
271 domain-idle-states { 225 domain-idle-states {
272 CLUSTER_SLEEP_0: clust 226 CLUSTER_SLEEP_0: cluster-sleep-0 {
273 compatible = " 227 compatible = "domain-idle-state";
>> 228 idle-state-name = "cluster-l3-off";
274 arm,psci-suspe 229 arm,psci-suspend-param = <0x41000044>;
275 entry-latency- 230 entry-latency-us = <1050>;
276 exit-latency-u 231 exit-latency-us = <2500>;
277 min-residency- 232 min-residency-us = <5309>;
>> 233 local-timer-stop;
278 }; 234 };
279 235
280 CLUSTER_SLEEP_1: clust 236 CLUSTER_SLEEP_1: cluster-sleep-1 {
281 compatible = " 237 compatible = "domain-idle-state";
>> 238 idle-state-name = "cluster-power-collapse";
282 arm,psci-suspe 239 arm,psci-suspend-param = <0x4100c344>;
283 entry-latency- 240 entry-latency-us = <2700>;
284 exit-latency-u 241 exit-latency-us = <3500>;
285 min-residency- 242 min-residency-us = <13959>;
>> 243 local-timer-stop;
286 }; 244 };
287 }; 245 };
288 }; 246 };
289 247
290 firmware { 248 firmware {
291 scm: scm { 249 scm: scm {
292 compatible = "qcom,scm 250 compatible = "qcom,scm-sm8450", "qcom,scm";
293 qcom,dload-mode = <&tc <<
294 interconnects = <&aggr <<
295 #reset-cells = <1>; 251 #reset-cells = <1>;
296 }; 252 };
297 }; 253 };
298 254
299 clk_virt: interconnect-0 { !! 255 clk_virt: interconnect@0 {
300 compatible = "qcom,sm8450-clk- 256 compatible = "qcom,sm8450-clk-virt";
301 #interconnect-cells = <2>; 257 #interconnect-cells = <2>;
302 qcom,bcm-voters = <&apps_bcm_v 258 qcom,bcm-voters = <&apps_bcm_voter>;
303 }; 259 };
304 260
305 mc_virt: interconnect-1 { !! 261 mc_virt: interconnect@1 {
306 compatible = "qcom,sm8450-mc-v 262 compatible = "qcom,sm8450-mc-virt";
307 #interconnect-cells = <2>; 263 #interconnect-cells = <2>;
308 qcom,bcm-voters = <&apps_bcm_v 264 qcom,bcm-voters = <&apps_bcm_voter>;
309 }; 265 };
310 266
311 memory@a0000000 { 267 memory@a0000000 {
312 device_type = "memory"; 268 device_type = "memory";
313 /* We expect the bootloader to 269 /* We expect the bootloader to fill in the size */
314 reg = <0x0 0xa0000000 0x0 0x0> 270 reg = <0x0 0xa0000000 0x0 0x0>;
315 }; 271 };
316 272
317 pmu { 273 pmu {
318 compatible = "arm,armv8-pmuv3" 274 compatible = "arm,armv8-pmuv3";
319 interrupts = <GIC_PPI 7 IRQ_TY 275 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
320 }; 276 };
321 277
322 psci { 278 psci {
323 compatible = "arm,psci-1.0"; 279 compatible = "arm,psci-1.0";
324 method = "smc"; 280 method = "smc";
325 281
326 CPU_PD0: power-domain-cpu0 { !! 282 CPU_PD0: cpu0 {
327 #power-domain-cells = 283 #power-domain-cells = <0>;
328 power-domains = <&CLUS 284 power-domains = <&CLUSTER_PD>;
329 domain-idle-states = < 285 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
330 }; 286 };
331 287
332 CPU_PD1: power-domain-cpu1 { !! 288 CPU_PD1: cpu1 {
333 #power-domain-cells = 289 #power-domain-cells = <0>;
334 power-domains = <&CLUS 290 power-domains = <&CLUSTER_PD>;
335 domain-idle-states = < 291 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
336 }; 292 };
337 293
338 CPU_PD2: power-domain-cpu2 { !! 294 CPU_PD2: cpu2 {
339 #power-domain-cells = 295 #power-domain-cells = <0>;
340 power-domains = <&CLUS 296 power-domains = <&CLUSTER_PD>;
341 domain-idle-states = < 297 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
342 }; 298 };
343 299
344 CPU_PD3: power-domain-cpu3 { !! 300 CPU_PD3: cpu3 {
345 #power-domain-cells = 301 #power-domain-cells = <0>;
346 power-domains = <&CLUS 302 power-domains = <&CLUSTER_PD>;
347 domain-idle-states = < 303 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
348 }; 304 };
349 305
350 CPU_PD4: power-domain-cpu4 { !! 306 CPU_PD4: cpu4 {
351 #power-domain-cells = 307 #power-domain-cells = <0>;
352 power-domains = <&CLUS 308 power-domains = <&CLUSTER_PD>;
353 domain-idle-states = < 309 domain-idle-states = <&BIG_CPU_SLEEP_0>;
354 }; 310 };
355 311
356 CPU_PD5: power-domain-cpu5 { !! 312 CPU_PD5: cpu5 {
357 #power-domain-cells = 313 #power-domain-cells = <0>;
358 power-domains = <&CLUS 314 power-domains = <&CLUSTER_PD>;
359 domain-idle-states = < 315 domain-idle-states = <&BIG_CPU_SLEEP_0>;
360 }; 316 };
361 317
362 CPU_PD6: power-domain-cpu6 { !! 318 CPU_PD6: cpu6 {
363 #power-domain-cells = 319 #power-domain-cells = <0>;
364 power-domains = <&CLUS 320 power-domains = <&CLUSTER_PD>;
365 domain-idle-states = < 321 domain-idle-states = <&BIG_CPU_SLEEP_0>;
366 }; 322 };
367 323
368 CPU_PD7: power-domain-cpu7 { !! 324 CPU_PD7: cpu7 {
369 #power-domain-cells = 325 #power-domain-cells = <0>;
370 power-domains = <&CLUS 326 power-domains = <&CLUSTER_PD>;
371 domain-idle-states = < 327 domain-idle-states = <&BIG_CPU_SLEEP_0>;
372 }; 328 };
373 329
374 CLUSTER_PD: power-domain-cpu-c !! 330 CLUSTER_PD: cpu-cluster0 {
375 #power-domain-cells = 331 #power-domain-cells = <0>;
376 domain-idle-states = < 332 domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>;
377 }; 333 };
378 }; 334 };
379 335
380 qup_opp_table_100mhz: opp-table-qup { <<
381 compatible = "operating-points <<
382 <<
383 opp-50000000 { <<
384 opp-hz = /bits/ 64 <50 <<
385 required-opps = <&rpmh <<
386 }; <<
387 <<
388 opp-75000000 { <<
389 opp-hz = /bits/ 64 <75 <<
390 required-opps = <&rpmh <<
391 }; <<
392 <<
393 opp-100000000 { <<
394 opp-hz = /bits/ 64 <10 <<
395 required-opps = <&rpmh <<
396 }; <<
397 }; <<
398 <<
399 reserved_memory: reserved-memory { 336 reserved_memory: reserved-memory {
400 #address-cells = <2>; 337 #address-cells = <2>;
401 #size-cells = <2>; 338 #size-cells = <2>;
402 ranges; 339 ranges;
403 340
404 hyp_mem: memory@80000000 { 341 hyp_mem: memory@80000000 {
405 reg = <0x0 0x80000000 342 reg = <0x0 0x80000000 0x0 0x600000>;
406 no-map; 343 no-map;
407 }; 344 };
408 345
409 xbl_dt_log_mem: memory@8060000 346 xbl_dt_log_mem: memory@80600000 {
410 reg = <0x0 0x80600000 347 reg = <0x0 0x80600000 0x0 0x40000>;
411 no-map; 348 no-map;
412 }; 349 };
413 350
414 xbl_ramdump_mem: memory@806400 351 xbl_ramdump_mem: memory@80640000 {
415 reg = <0x0 0x80640000 352 reg = <0x0 0x80640000 0x0 0x180000>;
416 no-map; 353 no-map;
417 }; 354 };
418 355
419 xbl_sc_mem: memory@807c0000 { 356 xbl_sc_mem: memory@807c0000 {
420 reg = <0x0 0x807c0000 357 reg = <0x0 0x807c0000 0x0 0x40000>;
421 no-map; 358 no-map;
422 }; 359 };
423 360
424 aop_image_mem: memory@80800000 361 aop_image_mem: memory@80800000 {
425 reg = <0x0 0x80800000 362 reg = <0x0 0x80800000 0x0 0x60000>;
426 no-map; 363 no-map;
427 }; 364 };
428 365
429 aop_cmd_db_mem: memory@8086000 366 aop_cmd_db_mem: memory@80860000 {
430 compatible = "qcom,cmd 367 compatible = "qcom,cmd-db";
431 reg = <0x0 0x80860000 368 reg = <0x0 0x80860000 0x0 0x20000>;
432 no-map; 369 no-map;
433 }; 370 };
434 371
435 aop_config_mem: memory@8088000 372 aop_config_mem: memory@80880000 {
436 reg = <0x0 0x80880000 373 reg = <0x0 0x80880000 0x0 0x20000>;
437 no-map; 374 no-map;
438 }; 375 };
439 376
440 tme_crash_dump_mem: memory@808 377 tme_crash_dump_mem: memory@808a0000 {
441 reg = <0x0 0x808a0000 378 reg = <0x0 0x808a0000 0x0 0x40000>;
442 no-map; 379 no-map;
443 }; 380 };
444 381
445 tme_log_mem: memory@808e0000 { 382 tme_log_mem: memory@808e0000 {
446 reg = <0x0 0x808e0000 383 reg = <0x0 0x808e0000 0x0 0x4000>;
447 no-map; 384 no-map;
448 }; 385 };
449 386
450 uefi_log_mem: memory@808e4000 387 uefi_log_mem: memory@808e4000 {
451 reg = <0x0 0x808e4000 388 reg = <0x0 0x808e4000 0x0 0x10000>;
452 no-map; 389 no-map;
453 }; 390 };
454 391
455 /* secdata region can be reuse 392 /* secdata region can be reused by apps */
456 smem: memory@80900000 { 393 smem: memory@80900000 {
457 compatible = "qcom,sme 394 compatible = "qcom,smem";
458 reg = <0x0 0x80900000 395 reg = <0x0 0x80900000 0x0 0x200000>;
459 hwlocks = <&tcsr_mutex 396 hwlocks = <&tcsr_mutex 3>;
460 no-map; 397 no-map;
461 }; 398 };
462 399
463 cpucp_fw_mem: memory@80b00000 400 cpucp_fw_mem: memory@80b00000 {
464 reg = <0x0 0x80b00000 401 reg = <0x0 0x80b00000 0x0 0x100000>;
465 no-map; 402 no-map;
466 }; 403 };
467 404
468 cdsp_secure_heap: memory@80c00 405 cdsp_secure_heap: memory@80c00000 {
469 reg = <0x0 0x80c00000 406 reg = <0x0 0x80c00000 0x0 0x4600000>;
470 no-map; 407 no-map;
471 }; 408 };
472 409
>> 410 camera_mem: memory@85200000 {
>> 411 reg = <0x0 0x85200000 0x0 0x500000>;
>> 412 no-map;
>> 413 };
>> 414
473 video_mem: memory@85700000 { 415 video_mem: memory@85700000 {
474 reg = <0x0 0x85700000 416 reg = <0x0 0x85700000 0x0 0x700000>;
475 no-map; 417 no-map;
476 }; 418 };
477 419
478 adsp_mem: memory@85e00000 { 420 adsp_mem: memory@85e00000 {
479 reg = <0x0 0x85e00000 421 reg = <0x0 0x85e00000 0x0 0x2100000>;
480 no-map; 422 no-map;
481 }; 423 };
482 424
483 slpi_mem: memory@88000000 { 425 slpi_mem: memory@88000000 {
484 reg = <0x0 0x88000000 426 reg = <0x0 0x88000000 0x0 0x1900000>;
485 no-map; 427 no-map;
486 }; 428 };
487 429
488 cdsp_mem: memory@89900000 { 430 cdsp_mem: memory@89900000 {
489 reg = <0x0 0x89900000 431 reg = <0x0 0x89900000 0x0 0x2000000>;
490 no-map; 432 no-map;
491 }; 433 };
492 434
493 ipa_fw_mem: memory@8b900000 { 435 ipa_fw_mem: memory@8b900000 {
494 reg = <0x0 0x8b900000 436 reg = <0x0 0x8b900000 0x0 0x10000>;
495 no-map; 437 no-map;
496 }; 438 };
497 439
498 ipa_gsi_mem: memory@8b910000 { 440 ipa_gsi_mem: memory@8b910000 {
499 reg = <0x0 0x8b910000 441 reg = <0x0 0x8b910000 0x0 0xa000>;
500 no-map; 442 no-map;
501 }; 443 };
502 444
503 gpu_micro_code_mem: memory@8b9 445 gpu_micro_code_mem: memory@8b91a000 {
504 reg = <0x0 0x8b91a000 446 reg = <0x0 0x8b91a000 0x0 0x2000>;
505 no-map; 447 no-map;
506 }; 448 };
507 449
508 spss_region_mem: memory@8ba000 450 spss_region_mem: memory@8ba00000 {
509 reg = <0x0 0x8ba00000 451 reg = <0x0 0x8ba00000 0x0 0x180000>;
510 no-map; 452 no-map;
511 }; 453 };
512 454
513 /* First part of the "SPU secu 455 /* First part of the "SPU secure shared memory" region */
514 spu_tz_shared_mem: memory@8bb8 456 spu_tz_shared_mem: memory@8bb80000 {
515 reg = <0x0 0x8bb80000 457 reg = <0x0 0x8bb80000 0x0 0x60000>;
516 no-map; 458 no-map;
517 }; 459 };
518 460
519 /* Second part of the "SPU sec 461 /* Second part of the "SPU secure shared memory" region */
520 spu_modem_shared_mem: memory@8 462 spu_modem_shared_mem: memory@8bbe0000 {
521 reg = <0x0 0x8bbe0000 463 reg = <0x0 0x8bbe0000 0x0 0x20000>;
522 no-map; 464 no-map;
523 }; 465 };
524 466
525 mpss_mem: memory@8bc00000 { 467 mpss_mem: memory@8bc00000 {
526 reg = <0x0 0x8bc00000 468 reg = <0x0 0x8bc00000 0x0 0x13200000>;
527 no-map; 469 no-map;
528 }; 470 };
529 471
530 cvp_mem: memory@9ee00000 { 472 cvp_mem: memory@9ee00000 {
531 reg = <0x0 0x9ee00000 473 reg = <0x0 0x9ee00000 0x0 0x700000>;
532 no-map; 474 no-map;
533 }; 475 };
534 476
535 camera_mem: memory@9f500000 { <<
536 reg = <0x0 0x9f500000 <<
537 no-map; <<
538 }; <<
539 <<
540 rmtfs_mem: memory@9fd00000 { 477 rmtfs_mem: memory@9fd00000 {
541 compatible = "qcom,rmt 478 compatible = "qcom,rmtfs-mem";
542 reg = <0x0 0x9fd00000 479 reg = <0x0 0x9fd00000 0x0 0x280000>;
543 no-map; 480 no-map;
544 481
545 qcom,client-id = <1>; 482 qcom,client-id = <1>;
546 qcom,vmid = <QCOM_SCM_ !! 483 qcom,vmid = <15>;
547 }; <<
548 <<
549 xbl_sc_mem2: memory@a6e00000 { <<
550 reg = <0x0 0xa6e00000 <<
551 no-map; <<
552 }; 484 };
553 485
554 global_sync_mem: memory@a6f000 486 global_sync_mem: memory@a6f00000 {
555 reg = <0x0 0xa6f00000 487 reg = <0x0 0xa6f00000 0x0 0x100000>;
556 no-map; 488 no-map;
557 }; 489 };
558 490
559 /* uefi region can be reused b 491 /* uefi region can be reused by APPS */
560 492
561 /* Linux kernel image is loade 493 /* Linux kernel image is loaded at 0xa0000000 */
562 494
563 oem_vm_mem: memory@bb000000 { 495 oem_vm_mem: memory@bb000000 {
564 reg = <0x0 0xbb000000 496 reg = <0x0 0xbb000000 0x0 0x5000000>;
565 no-map; 497 no-map;
566 }; 498 };
567 499
568 mte_mem: memory@c0000000 { 500 mte_mem: memory@c0000000 {
569 reg = <0x0 0xc0000000 501 reg = <0x0 0xc0000000 0x0 0x20000000>;
570 no-map; 502 no-map;
571 }; 503 };
572 504
573 qheebsp_reserved_mem: memory@e 505 qheebsp_reserved_mem: memory@e0000000 {
574 reg = <0x0 0xe0000000 506 reg = <0x0 0xe0000000 0x0 0x600000>;
575 no-map; 507 no-map;
576 }; 508 };
577 509
578 cpusys_vm_mem: memory@e0600000 510 cpusys_vm_mem: memory@e0600000 {
579 reg = <0x0 0xe0600000 511 reg = <0x0 0xe0600000 0x0 0x400000>;
580 no-map; 512 no-map;
581 }; 513 };
582 514
583 hyp_reserved_mem: memory@e0a00 515 hyp_reserved_mem: memory@e0a00000 {
584 reg = <0x0 0xe0a00000 516 reg = <0x0 0xe0a00000 0x0 0x100000>;
585 no-map; 517 no-map;
586 }; 518 };
587 519
588 trust_ui_vm_mem: memory@e0b000 520 trust_ui_vm_mem: memory@e0b00000 {
589 reg = <0x0 0xe0b00000 521 reg = <0x0 0xe0b00000 0x0 0x4af3000>;
590 no-map; 522 no-map;
591 }; 523 };
592 524
593 trust_ui_vm_qrtr: memory@e55f3 525 trust_ui_vm_qrtr: memory@e55f3000 {
594 reg = <0x0 0xe55f3000 526 reg = <0x0 0xe55f3000 0x0 0x9000>;
595 no-map; 527 no-map;
596 }; 528 };
597 529
598 trust_ui_vm_vblk0_ring: memory 530 trust_ui_vm_vblk0_ring: memory@e55fc000 {
599 reg = <0x0 0xe55fc000 531 reg = <0x0 0xe55fc000 0x0 0x4000>;
600 no-map; 532 no-map;
601 }; 533 };
602 534
603 trust_ui_vm_swiotlb: memory@e5 535 trust_ui_vm_swiotlb: memory@e5600000 {
604 reg = <0x0 0xe5600000 536 reg = <0x0 0xe5600000 0x0 0x100000>;
605 no-map; 537 no-map;
606 }; 538 };
607 539
608 tz_stat_mem: memory@e8800000 { 540 tz_stat_mem: memory@e8800000 {
609 reg = <0x0 0xe8800000 541 reg = <0x0 0xe8800000 0x0 0x100000>;
610 no-map; 542 no-map;
611 }; 543 };
612 544
613 tags_mem: memory@e8900000 { 545 tags_mem: memory@e8900000 {
614 reg = <0x0 0xe8900000 546 reg = <0x0 0xe8900000 0x0 0x1200000>;
615 no-map; 547 no-map;
616 }; 548 };
617 549
618 qtee_mem: memory@e9b00000 { 550 qtee_mem: memory@e9b00000 {
619 reg = <0x0 0xe9b00000 551 reg = <0x0 0xe9b00000 0x0 0x500000>;
620 no-map; 552 no-map;
621 }; 553 };
622 554
623 trusted_apps_mem: memory@ea000 555 trusted_apps_mem: memory@ea000000 {
624 reg = <0x0 0xea000000 556 reg = <0x0 0xea000000 0x0 0x3900000>;
625 no-map; 557 no-map;
626 }; 558 };
627 559
628 trusted_apps_ext_mem: memory@e 560 trusted_apps_ext_mem: memory@ed900000 {
629 reg = <0x0 0xed900000 561 reg = <0x0 0xed900000 0x0 0x3b00000>;
630 no-map; 562 no-map;
631 }; 563 };
632 }; 564 };
633 565
634 smp2p-adsp { 566 smp2p-adsp {
635 compatible = "qcom,smp2p"; 567 compatible = "qcom,smp2p";
636 qcom,smem = <443>, <429>; 568 qcom,smem = <443>, <429>;
637 interrupts-extended = <&ipcc I 569 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
638 I 570 IPCC_MPROC_SIGNAL_SMP2P
639 I 571 IRQ_TYPE_EDGE_RISING>;
640 mboxes = <&ipcc IPCC_CLIENT_LP 572 mboxes = <&ipcc IPCC_CLIENT_LPASS
641 IPCC_MPROC_SIG 573 IPCC_MPROC_SIGNAL_SMP2P>;
642 574
643 qcom,local-pid = <0>; 575 qcom,local-pid = <0>;
644 qcom,remote-pid = <2>; 576 qcom,remote-pid = <2>;
645 577
646 smp2p_adsp_out: master-kernel 578 smp2p_adsp_out: master-kernel {
647 qcom,entry-name = "mas 579 qcom,entry-name = "master-kernel";
648 #qcom,smem-state-cells 580 #qcom,smem-state-cells = <1>;
649 }; 581 };
650 582
651 smp2p_adsp_in: slave-kernel { 583 smp2p_adsp_in: slave-kernel {
652 qcom,entry-name = "sla 584 qcom,entry-name = "slave-kernel";
653 interrupt-controller; 585 interrupt-controller;
654 #interrupt-cells = <2> 586 #interrupt-cells = <2>;
655 }; 587 };
656 }; 588 };
657 589
658 smp2p-cdsp { 590 smp2p-cdsp {
659 compatible = "qcom,smp2p"; 591 compatible = "qcom,smp2p";
660 qcom,smem = <94>, <432>; 592 qcom,smem = <94>, <432>;
661 interrupts-extended = <&ipcc I 593 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
662 I 594 IPCC_MPROC_SIGNAL_SMP2P
663 I 595 IRQ_TYPE_EDGE_RISING>;
664 mboxes = <&ipcc IPCC_CLIENT_CD 596 mboxes = <&ipcc IPCC_CLIENT_CDSP
665 IPCC_MPROC_SIG 597 IPCC_MPROC_SIGNAL_SMP2P>;
666 598
667 qcom,local-pid = <0>; 599 qcom,local-pid = <0>;
668 qcom,remote-pid = <5>; 600 qcom,remote-pid = <5>;
669 601
670 smp2p_cdsp_out: master-kernel 602 smp2p_cdsp_out: master-kernel {
671 qcom,entry-name = "mas 603 qcom,entry-name = "master-kernel";
672 #qcom,smem-state-cells 604 #qcom,smem-state-cells = <1>;
673 }; 605 };
674 606
675 smp2p_cdsp_in: slave-kernel { 607 smp2p_cdsp_in: slave-kernel {
676 qcom,entry-name = "sla 608 qcom,entry-name = "slave-kernel";
677 interrupt-controller; 609 interrupt-controller;
678 #interrupt-cells = <2> 610 #interrupt-cells = <2>;
679 }; 611 };
680 }; 612 };
681 613
682 smp2p-modem { 614 smp2p-modem {
683 compatible = "qcom,smp2p"; 615 compatible = "qcom,smp2p";
684 qcom,smem = <435>, <428>; 616 qcom,smem = <435>, <428>;
685 interrupts-extended = <&ipcc I 617 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
686 I 618 IPCC_MPROC_SIGNAL_SMP2P
687 I 619 IRQ_TYPE_EDGE_RISING>;
688 mboxes = <&ipcc IPCC_CLIENT_MP 620 mboxes = <&ipcc IPCC_CLIENT_MPSS
689 IPCC_MPROC_SIG 621 IPCC_MPROC_SIGNAL_SMP2P>;
690 622
691 qcom,local-pid = <0>; 623 qcom,local-pid = <0>;
692 qcom,remote-pid = <1>; 624 qcom,remote-pid = <1>;
693 625
694 smp2p_modem_out: master-kernel 626 smp2p_modem_out: master-kernel {
695 qcom,entry-name = "mas 627 qcom,entry-name = "master-kernel";
696 #qcom,smem-state-cells 628 #qcom,smem-state-cells = <1>;
697 }; 629 };
698 630
699 smp2p_modem_in: slave-kernel { 631 smp2p_modem_in: slave-kernel {
700 qcom,entry-name = "sla 632 qcom,entry-name = "slave-kernel";
701 interrupt-controller; 633 interrupt-controller;
702 #interrupt-cells = <2> 634 #interrupt-cells = <2>;
703 }; 635 };
704 636
705 ipa_smp2p_out: ipa-ap-to-modem 637 ipa_smp2p_out: ipa-ap-to-modem {
706 qcom,entry-name = "ipa 638 qcom,entry-name = "ipa";
707 #qcom,smem-state-cells 639 #qcom,smem-state-cells = <1>;
708 }; 640 };
709 641
710 ipa_smp2p_in: ipa-modem-to-ap 642 ipa_smp2p_in: ipa-modem-to-ap {
711 qcom,entry-name = "ipa 643 qcom,entry-name = "ipa";
712 interrupt-controller; 644 interrupt-controller;
713 #interrupt-cells = <2> 645 #interrupt-cells = <2>;
714 }; 646 };
715 }; 647 };
716 648
717 smp2p-slpi { 649 smp2p-slpi {
718 compatible = "qcom,smp2p"; 650 compatible = "qcom,smp2p";
719 qcom,smem = <481>, <430>; 651 qcom,smem = <481>, <430>;
720 interrupts-extended = <&ipcc I 652 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
721 I 653 IPCC_MPROC_SIGNAL_SMP2P
722 I 654 IRQ_TYPE_EDGE_RISING>;
723 mboxes = <&ipcc IPCC_CLIENT_SL 655 mboxes = <&ipcc IPCC_CLIENT_SLPI
724 IPCC_MPROC_SIG 656 IPCC_MPROC_SIGNAL_SMP2P>;
725 657
726 qcom,local-pid = <0>; 658 qcom,local-pid = <0>;
727 qcom,remote-pid = <3>; 659 qcom,remote-pid = <3>;
728 660
729 smp2p_slpi_out: master-kernel 661 smp2p_slpi_out: master-kernel {
730 qcom,entry-name = "mas 662 qcom,entry-name = "master-kernel";
731 #qcom,smem-state-cells 663 #qcom,smem-state-cells = <1>;
732 }; 664 };
733 665
734 smp2p_slpi_in: slave-kernel { 666 smp2p_slpi_in: slave-kernel {
735 qcom,entry-name = "sla 667 qcom,entry-name = "slave-kernel";
736 interrupt-controller; 668 interrupt-controller;
737 #interrupt-cells = <2> 669 #interrupt-cells = <2>;
738 }; 670 };
739 }; 671 };
740 672
741 soc: soc@0 { 673 soc: soc@0 {
742 #address-cells = <2>; 674 #address-cells = <2>;
743 #size-cells = <2>; 675 #size-cells = <2>;
744 ranges = <0 0 0 0 0x10 0>; 676 ranges = <0 0 0 0 0x10 0>;
745 dma-ranges = <0 0 0 0 0x10 0>; 677 dma-ranges = <0 0 0 0 0x10 0>;
746 compatible = "simple-bus"; 678 compatible = "simple-bus";
747 679
748 gcc: clock-controller@100000 { 680 gcc: clock-controller@100000 {
749 compatible = "qcom,gcc 681 compatible = "qcom,gcc-sm8450";
750 reg = <0x0 0x00100000 682 reg = <0x0 0x00100000 0x0 0x1f4200>;
751 #clock-cells = <1>; 683 #clock-cells = <1>;
752 #reset-cells = <1>; 684 #reset-cells = <1>;
753 #power-domain-cells = 685 #power-domain-cells = <1>;
754 clocks = <&rpmhcc RPMH !! 686 clock-names = "bi_tcxo", "sleep_clk";
755 <&sleep_clk>, !! 687 clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
756 <&pcie0_phy>, <<
757 <&pcie1_phy Q <<
758 <&pcie1_phy Q <<
759 <&ufs_mem_phy <<
760 <&ufs_mem_phy <<
761 <&ufs_mem_phy <<
762 <&usb_1_qmpph <<
763 clock-names = "bi_tcxo <<
764 "sleep_c <<
765 "pcie_0_ <<
766 "pcie_1_ <<
767 "pcie_1_ <<
768 "ufs_phy <<
769 "ufs_phy <<
770 "ufs_phy <<
771 "usb3_ph <<
772 }; <<
773 <<
774 gpi_dma2: dma-controller@80000 <<
775 compatible = "qcom,sm8 <<
776 #dma-cells = <3>; <<
777 reg = <0 0x00800000 0 <<
778 interrupts = <GIC_SPI <<
779 <GIC_SPI <<
780 <GIC_SPI <<
781 <GIC_SPI <<
782 <GIC_SPI <<
783 <GIC_SPI <<
784 <GIC_SPI <<
785 <GIC_SPI <<
786 <GIC_SPI <<
787 <GIC_SPI <<
788 <GIC_SPI <<
789 <GIC_SPI <<
790 dma-channels = <12>; <<
791 dma-channel-mask = <0x <<
792 iommus = <&apps_smmu 0 <<
793 status = "disabled"; <<
794 }; <<
795 <<
796 qupv3_id_2: geniqup@8c0000 { <<
797 compatible = "qcom,gen <<
798 reg = <0x0 0x008c0000 <<
799 clock-names = "m-ahb", <<
800 clocks = <&gcc GCC_QUP <<
801 <&gcc GCC_QUP <<
802 iommus = <&apps_smmu 0 <<
803 #address-cells = <2>; <<
804 #size-cells = <2>; <<
805 ranges; <<
806 status = "disabled"; <<
807 <<
808 i2c15: i2c@880000 { <<
809 compatible = " <<
810 reg = <0x0 0x0 <<
811 clock-names = <<
812 clocks = <&gcc <<
813 pinctrl-names <<
814 pinctrl-0 = <& <<
815 interrupts = < <<
816 #address-cells <<
817 #size-cells = <<
818 interconnects <<
819 <<
820 <<
821 interconnect-n <<
822 dmas = <&gpi_d <<
823 <&gpi_d <<
824 dma-names = "t <<
825 status = "disa <<
826 }; <<
827 <<
828 spi15: spi@880000 { <<
829 compatible = " <<
830 reg = <0x0 0x0 <<
831 clock-names = <<
832 clocks = <&gcc <<
833 interrupts = < <<
834 pinctrl-names <<
835 pinctrl-0 = <& <<
836 interconnects <<
837 <<
838 interconnect-n <<
839 dmas = <&gpi_d <<
840 <&gpi_d <<
841 dma-names = "t <<
842 #address-cells <<
843 #size-cells = <<
844 status = "disa <<
845 }; <<
846 <<
847 i2c16: i2c@884000 { <<
848 compatible = " <<
849 reg = <0x0 0x0 <<
850 clock-names = <<
851 clocks = <&gcc <<
852 pinctrl-names <<
853 pinctrl-0 = <& <<
854 interrupts = < <<
855 #address-cells <<
856 #size-cells = <<
857 interconnects <<
858 <<
859 <<
860 interconnect-n <<
861 dmas = <&gpi_d <<
862 <&gpi_d <<
863 dma-names = "t <<
864 status = "disa <<
865 }; <<
866 <<
867 spi16: spi@884000 { <<
868 compatible = " <<
869 reg = <0x0 0x0 <<
870 clock-names = <<
871 clocks = <&gcc <<
872 interrupts = < <<
873 pinctrl-names <<
874 pinctrl-0 = <& <<
875 interconnects <<
876 <<
877 interconnect-n <<
878 dmas = <&gpi_d <<
879 <&gpi_d <<
880 dma-names = "t <<
881 #address-cells <<
882 #size-cells = <<
883 status = "disa <<
884 }; <<
885 <<
886 i2c17: i2c@888000 { <<
887 compatible = " <<
888 reg = <0x0 0x0 <<
889 clock-names = <<
890 clocks = <&gcc <<
891 pinctrl-names <<
892 pinctrl-0 = <& <<
893 interrupts = < <<
894 #address-cells <<
895 #size-cells = <<
896 interconnects <<
897 <<
898 <<
899 interconnect-n <<
900 dmas = <&gpi_d <<
901 <&gpi_d <<
902 dma-names = "t <<
903 status = "disa <<
904 }; <<
905 <<
906 spi17: spi@888000 { <<
907 compatible = " <<
908 reg = <0x0 0x0 <<
909 clock-names = <<
910 clocks = <&gcc <<
911 interrupts = < <<
912 pinctrl-names <<
913 pinctrl-0 = <& <<
914 interconnects <<
915 <<
916 interconnect-n <<
917 dmas = <&gpi_d <<
918 <&gpi_d <<
919 dma-names = "t <<
920 #address-cells <<
921 #size-cells = <<
922 status = "disa <<
923 }; <<
924 <<
925 i2c18: i2c@88c000 { <<
926 compatible = " <<
927 reg = <0x0 0x0 <<
928 clock-names = <<
929 clocks = <&gcc <<
930 pinctrl-names <<
931 pinctrl-0 = <& <<
932 interrupts = < <<
933 #address-cells <<
934 #size-cells = <<
935 interconnects <<
936 <<
937 <<
938 interconnect-n <<
939 dmas = <&gpi_d <<
940 <&gpi_d <<
941 dma-names = "t <<
942 status = "disa <<
943 }; <<
944 <<
945 spi18: spi@88c000 { <<
946 compatible = " <<
947 reg = <0 0x008 <<
948 clock-names = <<
949 clocks = <&gcc <<
950 interrupts = < <<
951 pinctrl-names <<
952 pinctrl-0 = <& <<
953 interconnects <<
954 <<
955 interconnect-n <<
956 dmas = <&gpi_d <<
957 <&gpi_d <<
958 dma-names = "t <<
959 #address-cells <<
960 #size-cells = <<
961 status = "disa <<
962 }; <<
963 <<
964 i2c19: i2c@890000 { <<
965 compatible = " <<
966 reg = <0x0 0x0 <<
967 clock-names = <<
968 clocks = <&gcc <<
969 pinctrl-names <<
970 pinctrl-0 = <& <<
971 interrupts = < <<
972 #address-cells <<
973 #size-cells = <<
974 interconnects <<
975 <<
976 <<
977 interconnect-n <<
978 dmas = <&gpi_d <<
979 <&gpi_d <<
980 dma-names = "t <<
981 status = "disa <<
982 }; <<
983 <<
984 spi19: spi@890000 { <<
985 compatible = " <<
986 reg = <0 0x008 <<
987 clock-names = <<
988 clocks = <&gcc <<
989 interrupts = < <<
990 pinctrl-names <<
991 pinctrl-0 = <& <<
992 interconnects <<
993 <<
994 interconnect-n <<
995 dmas = <&gpi_d <<
996 <&gpi_d <<
997 dma-names = "t <<
998 #address-cells <<
999 #size-cells = <<
1000 status = "dis <<
1001 }; <<
1002 <<
1003 i2c20: i2c@894000 { <<
1004 compatible = <<
1005 reg = <0x0 0x <<
1006 clock-names = <<
1007 clocks = <&gc <<
1008 pinctrl-names <<
1009 pinctrl-0 = < <<
1010 interrupts = <<
1011 #address-cell <<
1012 #size-cells = <<
1013 interconnects <<
1014 <<
1015 <<
1016 interconnect- <<
1017 dmas = <&gpi_ <<
1018 <&gpi_ <<
1019 dma-names = " <<
1020 status = "dis <<
1021 }; <<
1022 <<
1023 uart20: serial@894000 <<
1024 compatible = <<
1025 reg = <0 0x00 <<
1026 clock-names = <<
1027 clocks = <&gc <<
1028 pinctrl-names <<
1029 pinctrl-0 = < <<
1030 interrupts = <<
1031 interconnects <<
1032 <<
1033 <<
1034 <<
1035 interconnect- <<
1036 <<
1037 status = "dis <<
1038 }; <<
1039 <<
1040 spi20: spi@894000 { <<
1041 compatible = <<
1042 reg = <0 0x00 <<
1043 clock-names = <<
1044 clocks = <&gc <<
1045 interrupts = <<
1046 pinctrl-names <<
1047 pinctrl-0 = < <<
1048 interconnects <<
1049 <<
1050 interconnect- <<
1051 dmas = <&gpi_ <<
1052 <&gpi_ <<
1053 dma-names = " <<
1054 #address-cell <<
1055 #size-cells = <<
1056 status = "dis <<
1057 }; <<
1058 <<
1059 i2c21: i2c@898000 { <<
1060 compatible = <<
1061 reg = <0x0 0x <<
1062 clock-names = <<
1063 clocks = <&gc <<
1064 pinctrl-names <<
1065 pinctrl-0 = < <<
1066 interrupts = <<
1067 #address-cell <<
1068 #size-cells = <<
1069 interconnects <<
1070 <<
1071 <<
1072 interconnect- <<
1073 dmas = <&gpi_ <<
1074 <&gpi_ <<
1075 dma-names = " <<
1076 status = "dis <<
1077 }; <<
1078 <<
1079 spi21: spi@898000 { <<
1080 compatible = <<
1081 reg = <0 0x00 <<
1082 clock-names = <<
1083 clocks = <&gc <<
1084 interrupts = <<
1085 pinctrl-names <<
1086 pinctrl-0 = < <<
1087 interconnects <<
1088 <<
1089 interconnect- <<
1090 dmas = <&gpi_ <<
1091 <&gpi_ <<
1092 dma-names = " <<
1093 #address-cell <<
1094 #size-cells = <<
1095 status = "dis <<
1096 }; <<
1097 }; <<
1098 <<
1099 gpi_dma0: dma-controller@9000 <<
1100 compatible = "qcom,sm <<
1101 #dma-cells = <3>; <<
1102 reg = <0 0x00900000 0 <<
1103 interrupts = <GIC_SPI <<
1104 <GIC_SPI <<
1105 <GIC_SPI <<
1106 <GIC_SPI <<
1107 <GIC_SPI <<
1108 <GIC_SPI <<
1109 <GIC_SPI <<
1110 <GIC_SPI <<
1111 <GIC_SPI <<
1112 <GIC_SPI <<
1113 <GIC_SPI <<
1114 <GIC_SPI <<
1115 dma-channels = <12>; <<
1116 dma-channel-mask = <0 <<
1117 iommus = <&apps_smmu <<
1118 status = "disabled"; <<
1119 }; 688 };
1120 689
1121 qupv3_id_0: geniqup@9c0000 { 690 qupv3_id_0: geniqup@9c0000 {
1122 compatible = "qcom,ge 691 compatible = "qcom,geni-se-qup";
1123 reg = <0x0 0x009c0000 692 reg = <0x0 0x009c0000 0x0 0x2000>;
1124 clock-names = "m-ahb" 693 clock-names = "m-ahb", "s-ahb";
1125 clocks = <&gcc GCC_QU 694 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1126 <&gcc GCC_QU 695 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1127 iommus = <&apps_smmu 696 iommus = <&apps_smmu 0x5a3 0x0>;
1128 interconnects = <&clk 697 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>;
1129 interconnect-names = 698 interconnect-names = "qup-core";
1130 #address-cells = <2>; 699 #address-cells = <2>;
1131 #size-cells = <2>; 700 #size-cells = <2>;
1132 ranges; 701 ranges;
1133 status = "disabled"; 702 status = "disabled";
1134 703
1135 i2c0: i2c@980000 { <<
1136 compatible = <<
1137 reg = <0x0 0x <<
1138 clock-names = <<
1139 clocks = <&gc <<
1140 pinctrl-names <<
1141 pinctrl-0 = < <<
1142 interrupts = <<
1143 #address-cell <<
1144 #size-cells = <<
1145 interconnects <<
1146 <<
1147 <<
1148 interconnect- <<
1149 dmas = <&gpi_ <<
1150 <&gpi_ <<
1151 dma-names = " <<
1152 status = "dis <<
1153 }; <<
1154 <<
1155 spi0: spi@980000 { <<
1156 compatible = <<
1157 reg = <0x0 0x <<
1158 clock-names = <<
1159 clocks = <&gc <<
1160 interrupts = <<
1161 pinctrl-names <<
1162 pinctrl-0 = < <<
1163 power-domains <<
1164 operating-poi <<
1165 interconnects <<
1166 <<
1167 <<
1168 interconnect- <<
1169 dmas = <&gpi_ <<
1170 <&gpi_ <<
1171 dma-names = " <<
1172 #address-cell <<
1173 #size-cells = <<
1174 status = "dis <<
1175 }; <<
1176 <<
1177 i2c1: i2c@984000 { <<
1178 compatible = <<
1179 reg = <0x0 0x <<
1180 clock-names = <<
1181 clocks = <&gc <<
1182 pinctrl-names <<
1183 pinctrl-0 = < <<
1184 interrupts = <<
1185 #address-cell <<
1186 #size-cells = <<
1187 interconnects <<
1188 <<
1189 <<
1190 interconnect- <<
1191 dmas = <&gpi_ <<
1192 <&gpi_ <<
1193 dma-names = " <<
1194 status = "dis <<
1195 }; <<
1196 <<
1197 spi1: spi@984000 { <<
1198 compatible = <<
1199 reg = <0x0 0x <<
1200 clock-names = <<
1201 clocks = <&gc <<
1202 interrupts = <<
1203 pinctrl-names <<
1204 pinctrl-0 = < <<
1205 interconnects <<
1206 <<
1207 <<
1208 interconnect- <<
1209 dmas = <&gpi_ <<
1210 <&gpi_ <<
1211 dma-names = " <<
1212 #address-cell <<
1213 #size-cells = <<
1214 status = "dis <<
1215 }; <<
1216 <<
1217 i2c2: i2c@988000 { <<
1218 compatible = <<
1219 reg = <0x0 0x <<
1220 clock-names = <<
1221 clocks = <&gc <<
1222 pinctrl-names <<
1223 pinctrl-0 = < <<
1224 interrupts = <<
1225 #address-cell <<
1226 #size-cells = <<
1227 interconnects <<
1228 <<
1229 <<
1230 interconnect- <<
1231 dmas = <&gpi_ <<
1232 <&gpi_ <<
1233 dma-names = " <<
1234 status = "dis <<
1235 }; <<
1236 <<
1237 spi2: spi@988000 { <<
1238 compatible = <<
1239 reg = <0x0 0x <<
1240 clock-names = <<
1241 clocks = <&gc <<
1242 interrupts = <<
1243 pinctrl-names <<
1244 pinctrl-0 = < <<
1245 interconnects <<
1246 <<
1247 <<
1248 interconnect- <<
1249 dmas = <&gpi_ <<
1250 <&gpi_ <<
1251 dma-names = " <<
1252 #address-cell <<
1253 #size-cells = <<
1254 status = "dis <<
1255 }; <<
1256 <<
1257 <<
1258 i2c3: i2c@98c000 { <<
1259 compatible = <<
1260 reg = <0x0 0x <<
1261 clock-names = <<
1262 clocks = <&gc <<
1263 pinctrl-names <<
1264 pinctrl-0 = < <<
1265 interrupts = <<
1266 #address-cell <<
1267 #size-cells = <<
1268 interconnects <<
1269 <<
1270 <<
1271 interconnect- <<
1272 dmas = <&gpi_ <<
1273 <&gpi_ <<
1274 dma-names = " <<
1275 status = "dis <<
1276 }; <<
1277 <<
1278 spi3: spi@98c000 { <<
1279 compatible = <<
1280 reg = <0x0 0x <<
1281 clock-names = <<
1282 clocks = <&gc <<
1283 interrupts = <<
1284 pinctrl-names <<
1285 pinctrl-0 = < <<
1286 interconnects <<
1287 <<
1288 <<
1289 interconnect- <<
1290 dmas = <&gpi_ <<
1291 <&gpi_ <<
1292 dma-names = " <<
1293 #address-cell <<
1294 #size-cells = <<
1295 status = "dis <<
1296 }; <<
1297 <<
1298 i2c4: i2c@990000 { <<
1299 compatible = <<
1300 reg = <0x0 0x <<
1301 clock-names = <<
1302 clocks = <&gc <<
1303 pinctrl-names <<
1304 pinctrl-0 = < <<
1305 interrupts = <<
1306 #address-cell <<
1307 #size-cells = <<
1308 interconnects <<
1309 <<
1310 <<
1311 interconnect- <<
1312 dmas = <&gpi_ <<
1313 <&gpi_ <<
1314 dma-names = " <<
1315 status = "dis <<
1316 }; <<
1317 <<
1318 spi4: spi@990000 { <<
1319 compatible = <<
1320 reg = <0x0 0x <<
1321 clock-names = <<
1322 clocks = <&gc <<
1323 interrupts = <<
1324 pinctrl-names <<
1325 pinctrl-0 = < <<
1326 power-domains <<
1327 operating-poi <<
1328 interconnects <<
1329 <<
1330 <<
1331 interconnect- <<
1332 dmas = <&gpi_ <<
1333 <&gpi_ <<
1334 dma-names = " <<
1335 #address-cell <<
1336 #size-cells = <<
1337 status = "dis <<
1338 }; <<
1339 <<
1340 i2c5: i2c@994000 { <<
1341 compatible = <<
1342 reg = <0x0 0x <<
1343 clock-names = <<
1344 clocks = <&gc <<
1345 pinctrl-names <<
1346 pinctrl-0 = < <<
1347 interrupts = <<
1348 #address-cell <<
1349 #size-cells = <<
1350 interconnects <<
1351 <<
1352 <<
1353 interconnect- <<
1354 dmas = <&gpi_ <<
1355 <&gpi_ <<
1356 dma-names = " <<
1357 status = "dis <<
1358 }; <<
1359 <<
1360 spi5: spi@994000 { <<
1361 compatible = <<
1362 reg = <0x0 0x <<
1363 clock-names = <<
1364 clocks = <&gc <<
1365 interrupts = <<
1366 pinctrl-names <<
1367 pinctrl-0 = < <<
1368 interconnects <<
1369 <<
1370 <<
1371 interconnect- <<
1372 dmas = <&gpi_ <<
1373 <&gpi_ <<
1374 dma-names = " <<
1375 #address-cell <<
1376 #size-cells = <<
1377 status = "dis <<
1378 }; <<
1379 <<
1380 <<
1381 i2c6: i2c@998000 { <<
1382 compatible = <<
1383 reg = <0x0 0x <<
1384 clock-names = <<
1385 clocks = <&gc <<
1386 pinctrl-names <<
1387 pinctrl-0 = < <<
1388 interrupts = <<
1389 #address-cell <<
1390 #size-cells = <<
1391 interconnects <<
1392 <<
1393 <<
1394 interconnect- <<
1395 dmas = <&gpi_ <<
1396 <&gpi_ <<
1397 dma-names = " <<
1398 status = "dis <<
1399 }; <<
1400 <<
1401 spi6: spi@998000 { <<
1402 compatible = <<
1403 reg = <0x0 0x <<
1404 clock-names = <<
1405 clocks = <&gc <<
1406 interrupts = <<
1407 pinctrl-names <<
1408 pinctrl-0 = < <<
1409 interconnects <<
1410 <<
1411 <<
1412 interconnect- <<
1413 dmas = <&gpi_ <<
1414 <&gpi_ <<
1415 dma-names = " <<
1416 #address-cell <<
1417 #size-cells = <<
1418 status = "dis <<
1419 }; <<
1420 <<
1421 uart7: serial@99c000 704 uart7: serial@99c000 {
1422 compatible = 705 compatible = "qcom,geni-debug-uart";
1423 reg = <0 0x00 706 reg = <0 0x0099c000 0 0x4000>;
1424 clock-names = 707 clock-names = "se";
1425 clocks = <&gc 708 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1426 pinctrl-names 709 pinctrl-names = "default";
1427 pinctrl-0 = < 710 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>;
1428 interrupts = 711 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1429 interconnects !! 712 #address-cells = <1>;
1430 !! 713 #size-cells = <0>;
1431 <<
1432 <<
1433 interconnect- <<
1434 <<
1435 status = "dis 714 status = "disabled";
1436 }; 715 };
1437 }; 716 };
1438 717
1439 gpi_dma1: dma-controller@a000 <<
1440 compatible = "qcom,sm <<
1441 #dma-cells = <3>; <<
1442 reg = <0 0x00a00000 0 <<
1443 interrupts = <GIC_SPI <<
1444 <GIC_SPI <<
1445 <GIC_SPI <<
1446 <GIC_SPI <<
1447 <GIC_SPI <<
1448 <GIC_SPI <<
1449 <GIC_SPI <<
1450 <GIC_SPI <<
1451 <GIC_SPI <<
1452 <GIC_SPI <<
1453 <GIC_SPI <<
1454 <GIC_SPI <<
1455 dma-channels = <12>; <<
1456 dma-channel-mask = <0 <<
1457 iommus = <&apps_smmu <<
1458 status = "disabled"; <<
1459 }; <<
1460 <<
1461 qupv3_id_1: geniqup@ac0000 { 718 qupv3_id_1: geniqup@ac0000 {
1462 compatible = "qcom,ge 719 compatible = "qcom,geni-se-qup";
1463 reg = <0x0 0x00ac0000 720 reg = <0x0 0x00ac0000 0x0 0x6000>;
1464 clock-names = "m-ahb" 721 clock-names = "m-ahb", "s-ahb";
1465 clocks = <&gcc GCC_QU 722 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1466 <&gcc GCC_QU 723 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1467 iommus = <&apps_smmu 724 iommus = <&apps_smmu 0x43 0x0>;
1468 interconnects = <&clk 725 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>;
1469 interconnect-names = 726 interconnect-names = "qup-core";
1470 #address-cells = <2>; 727 #address-cells = <2>;
1471 #size-cells = <2>; 728 #size-cells = <2>;
1472 ranges; 729 ranges;
1473 status = "disabled"; 730 status = "disabled";
1474 731
1475 i2c8: i2c@a80000 { <<
1476 compatible = <<
1477 reg = <0x0 0x <<
1478 clock-names = <<
1479 clocks = <&gc <<
1480 pinctrl-names <<
1481 pinctrl-0 = < <<
1482 interrupts = <<
1483 #address-cell <<
1484 #size-cells = <<
1485 interconnects <<
1486 <<
1487 <<
1488 interconnect- <<
1489 dmas = <&gpi_ <<
1490 <&gpi_ <<
1491 dma-names = " <<
1492 status = "dis <<
1493 }; <<
1494 <<
1495 spi8: spi@a80000 { <<
1496 compatible = <<
1497 reg = <0x0 0x <<
1498 clock-names = <<
1499 clocks = <&gc <<
1500 interrupts = <<
1501 pinctrl-names <<
1502 pinctrl-0 = < <<
1503 interconnects <<
1504 <<
1505 <<
1506 interconnect- <<
1507 dmas = <&gpi_ <<
1508 <&gpi_ <<
1509 dma-names = " <<
1510 #address-cell <<
1511 #size-cells = <<
1512 status = "dis <<
1513 }; <<
1514 <<
1515 i2c9: i2c@a84000 { <<
1516 compatible = <<
1517 reg = <0x0 0x <<
1518 clock-names = <<
1519 clocks = <&gc <<
1520 pinctrl-names <<
1521 pinctrl-0 = < <<
1522 interrupts = <<
1523 #address-cell <<
1524 #size-cells = <<
1525 interconnects <<
1526 <<
1527 <<
1528 interconnect- <<
1529 dmas = <&gpi_ <<
1530 <&gpi_ <<
1531 dma-names = " <<
1532 status = "dis <<
1533 }; <<
1534 <<
1535 spi9: spi@a84000 { <<
1536 compatible = <<
1537 reg = <0x0 0x <<
1538 clock-names = <<
1539 clocks = <&gc <<
1540 interrupts = <<
1541 pinctrl-names <<
1542 pinctrl-0 = < <<
1543 interconnects <<
1544 <<
1545 <<
1546 interconnect- <<
1547 dmas = <&gpi_ <<
1548 <&gpi_ <<
1549 dma-names = " <<
1550 #address-cell <<
1551 #size-cells = <<
1552 status = "dis <<
1553 }; <<
1554 <<
1555 i2c10: i2c@a88000 { <<
1556 compatible = <<
1557 reg = <0x0 0x <<
1558 clock-names = <<
1559 clocks = <&gc <<
1560 pinctrl-names <<
1561 pinctrl-0 = < <<
1562 interrupts = <<
1563 #address-cell <<
1564 #size-cells = <<
1565 interconnects <<
1566 <<
1567 <<
1568 interconnect- <<
1569 dmas = <&gpi_ <<
1570 <&gpi_ <<
1571 dma-names = " <<
1572 status = "dis <<
1573 }; <<
1574 <<
1575 spi10: spi@a88000 { <<
1576 compatible = <<
1577 reg = <0x0 0x <<
1578 clock-names = <<
1579 clocks = <&gc <<
1580 interrupts = <<
1581 pinctrl-names <<
1582 pinctrl-0 = < <<
1583 interconnects <<
1584 <<
1585 <<
1586 interconnect- <<
1587 dmas = <&gpi_ <<
1588 <&gpi_ <<
1589 dma-names = " <<
1590 #address-cell <<
1591 #size-cells = <<
1592 status = "dis <<
1593 }; <<
1594 <<
1595 i2c11: i2c@a8c000 { <<
1596 compatible = <<
1597 reg = <0x0 0x <<
1598 clock-names = <<
1599 clocks = <&gc <<
1600 pinctrl-names <<
1601 pinctrl-0 = < <<
1602 interrupts = <<
1603 #address-cell <<
1604 #size-cells = <<
1605 interconnects <<
1606 <<
1607 <<
1608 interconnect- <<
1609 dmas = <&gpi_ <<
1610 <&gpi_ <<
1611 dma-names = " <<
1612 status = "dis <<
1613 }; <<
1614 <<
1615 spi11: spi@a8c000 { <<
1616 compatible = <<
1617 reg = <0x0 0x <<
1618 clock-names = <<
1619 clocks = <&gc <<
1620 interrupts = <<
1621 pinctrl-names <<
1622 pinctrl-0 = < <<
1623 interconnects <<
1624 <<
1625 <<
1626 interconnect- <<
1627 dmas = <&gpi_ <<
1628 <&gpi_ <<
1629 dma-names = " <<
1630 #address-cell <<
1631 #size-cells = <<
1632 status = "dis <<
1633 }; <<
1634 <<
1635 i2c12: i2c@a90000 { <<
1636 compatible = <<
1637 reg = <0x0 0x <<
1638 clock-names = <<
1639 clocks = <&gc <<
1640 pinctrl-names <<
1641 pinctrl-0 = < <<
1642 interrupts = <<
1643 #address-cell <<
1644 #size-cells = <<
1645 interconnects <<
1646 <<
1647 <<
1648 interconnect- <<
1649 dmas = <&gpi_ <<
1650 <&gpi_ <<
1651 dma-names = " <<
1652 status = "dis <<
1653 }; <<
1654 <<
1655 spi12: spi@a90000 { <<
1656 compatible = <<
1657 reg = <0x0 0x <<
1658 clock-names = <<
1659 clocks = <&gc <<
1660 interrupts = <<
1661 pinctrl-names <<
1662 pinctrl-0 = < <<
1663 interconnects <<
1664 <<
1665 <<
1666 interconnect- <<
1667 dmas = <&gpi_ <<
1668 <&gpi_ <<
1669 dma-names = " <<
1670 #address-cell <<
1671 #size-cells = <<
1672 status = "dis <<
1673 }; <<
1674 <<
1675 i2c13: i2c@a94000 { 732 i2c13: i2c@a94000 {
1676 compatible = 733 compatible = "qcom,geni-i2c";
1677 reg = <0 0x00 734 reg = <0 0x00a94000 0 0x4000>;
1678 clock-names = 735 clock-names = "se";
1679 clocks = <&gc 736 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1680 pinctrl-names 737 pinctrl-names = "default";
1681 pinctrl-0 = < 738 pinctrl-0 = <&qup_i2c13_data_clk>;
1682 interrupts = 739 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1683 interconnects <<
1684 <<
1685 <<
1686 interconnect- <<
1687 dmas = <&gpi_ <<
1688 <&gpi_ <<
1689 dma-names = " <<
1690 #address-cell <<
1691 #size-cells = <<
1692 status = "dis <<
1693 }; <<
1694 <<
1695 spi13: spi@a94000 { <<
1696 compatible = <<
1697 reg = <0x0 0x <<
1698 clock-names = <<
1699 clocks = <&gc <<
1700 interrupts = <<
1701 pinctrl-names <<
1702 pinctrl-0 = < <<
1703 interconnects <<
1704 <<
1705 <<
1706 interconnect- <<
1707 dmas = <&gpi_ <<
1708 <&gpi_ <<
1709 dma-names = " <<
1710 #address-cell 740 #address-cells = <1>;
1711 #size-cells = 741 #size-cells = <0>;
1712 status = "dis 742 status = "disabled";
1713 }; 743 };
1714 744
1715 i2c14: i2c@a98000 { 745 i2c14: i2c@a98000 {
1716 compatible = 746 compatible = "qcom,geni-i2c";
1717 reg = <0 0x00 747 reg = <0 0x00a98000 0 0x4000>;
1718 clock-names = 748 clock-names = "se";
1719 clocks = <&gc 749 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1720 pinctrl-names 750 pinctrl-names = "default";
1721 pinctrl-0 = < 751 pinctrl-0 = <&qup_i2c14_data_clk>;
1722 interrupts = 752 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
1723 interconnects <<
1724 <<
1725 <<
1726 interconnect- <<
1727 dmas = <&gpi_ <<
1728 <&gpi_ <<
1729 dma-names = " <<
1730 #address-cell 753 #address-cells = <1>;
1731 #size-cells = 754 #size-cells = <0>;
1732 status = "dis 755 status = "disabled";
1733 }; 756 };
1734 <<
1735 spi14: spi@a98000 { <<
1736 compatible = <<
1737 reg = <0x0 0x <<
1738 clock-names = <<
1739 clocks = <&gc <<
1740 interrupts = <<
1741 pinctrl-names <<
1742 pinctrl-0 = < <<
1743 interconnects <<
1744 <<
1745 <<
1746 interconnect- <<
1747 dmas = <&gpi_ <<
1748 <&gpi_ <<
1749 dma-names = " <<
1750 #address-cell <<
1751 #size-cells = <<
1752 status = "dis <<
1753 }; <<
1754 }; <<
1755 <<
1756 rng: rng@10c3000 { <<
1757 compatible = "qcom,sm <<
1758 reg = <0 0x010c3000 0 <<
1759 }; <<
1760 <<
1761 pcie0: pcie@1c00000 { <<
1762 compatible = "qcom,pc <<
1763 reg = <0 0x01c00000 0 <<
1764 <0 0x60000000 0 <<
1765 <0 0x60000f20 0 <<
1766 <0 0x60001000 0 <<
1767 <0 0x60100000 0 <<
1768 reg-names = "parf", " <<
1769 device_type = "pci"; <<
1770 linux,pci-domain = <0 <<
1771 bus-range = <0x00 0xf <<
1772 num-lanes = <1>; <<
1773 <<
1774 #address-cells = <3>; <<
1775 #size-cells = <2>; <<
1776 <<
1777 ranges = <0x01000000 <<
1778 <0x02000000 <<
1779 <<
1780 msi-map = <0x0 &gic_i <<
1781 <0x100 &gic <<
1782 msi-map-mask = <0xff0 <<
1783 interrupts = <GIC_SPI <<
1784 <GIC_SPI <<
1785 <GIC_SPI <<
1786 <GIC_SPI <<
1787 <GIC_SPI <<
1788 <GIC_SPI <<
1789 <GIC_SPI <<
1790 <GIC_SPI <<
1791 interrupt-names = "ms <<
1792 "ms <<
1793 "ms <<
1794 "ms <<
1795 "ms <<
1796 "ms <<
1797 "ms <<
1798 "ms <<
1799 #interrupt-cells = <1 <<
1800 interrupt-map-mask = <<
1801 interrupt-map = <0 0 <<
1802 <0 0 <<
1803 <0 0 <<
1804 <0 0 <<
1805 <<
1806 interconnects = <&pci <<
1807 &mc_ <<
1808 <&gem <<
1809 &con <<
1810 interconnect-names = <<
1811 <<
1812 clocks = <&gcc GCC_PC <<
1813 <&gcc GCC_PC <<
1814 <&pcie0_phy> <<
1815 <&rpmhcc RPM <<
1816 <&gcc GCC_PC <<
1817 <&gcc GCC_PC <<
1818 <&gcc GCC_PC <<
1819 <&gcc GCC_PC <<
1820 <&gcc GCC_PC <<
1821 <&gcc GCC_DD <<
1822 <&gcc GCC_AG <<
1823 <&gcc GCC_AG <<
1824 clock-names = "pipe", <<
1825 "pipe_m <<
1826 "phy_pi <<
1827 "ref", <<
1828 "aux", <<
1829 "cfg", <<
1830 "bus_ma <<
1831 "bus_sl <<
1832 "slave_ <<
1833 "ddrss_ <<
1834 "aggre0 <<
1835 "aggre1 <<
1836 <<
1837 iommu-map = <0x0 &a <<
1838 <0x100 &a <<
1839 <<
1840 resets = <&gcc GCC_PC <<
1841 reset-names = "pci"; <<
1842 <<
1843 power-domains = <&gcc <<
1844 <<
1845 phys = <&pcie0_phy>; <<
1846 phy-names = "pciephy" <<
1847 <<
1848 perst-gpios = <&tlmm <<
1849 wake-gpios = <&tlmm 9 <<
1850 <<
1851 pinctrl-names = "defa <<
1852 pinctrl-0 = <&pcie0_d <<
1853 <<
1854 operating-points-v2 = <<
1855 <<
1856 status = "disabled"; <<
1857 <<
1858 pcie0_opp_table: opp- <<
1859 compatible = <<
1860 <<
1861 /* GEN 1 x1 * <<
1862 opp-2500000 { <<
1863 opp-h <<
1864 requi <<
1865 opp-p <<
1866 }; <<
1867 <<
1868 /* GEN 2 x1 * <<
1869 opp-5000000 { <<
1870 opp-h <<
1871 requi <<
1872 opp-p <<
1873 }; <<
1874 <<
1875 /* GEN 3 x1 * <<
1876 opp-8000000 { <<
1877 opp-h <<
1878 requi <<
1879 opp-p <<
1880 }; <<
1881 }; <<
1882 <<
1883 pcie@0 { <<
1884 device_type = <<
1885 reg = <0x0 0x <<
1886 bus-range = < <<
1887 <<
1888 #address-cell <<
1889 #size-cells = <<
1890 ranges; <<
1891 }; <<
1892 }; <<
1893 <<
1894 pcie0_phy: phy@1c06000 { <<
1895 compatible = "qcom,sm <<
1896 reg = <0 0x01c06000 0 <<
1897 <<
1898 clocks = <&gcc GCC_PC <<
1899 <&gcc GCC_PC <<
1900 <&gcc GCC_PC <<
1901 <&gcc GCC_PC <<
1902 <&gcc GCC_PC <<
1903 clock-names = "aux", <<
1904 "cfg_ah <<
1905 "ref", <<
1906 "rchng" <<
1907 "pipe"; <<
1908 <<
1909 clock-output-names = <<
1910 #clock-cells = <0>; <<
1911 <<
1912 #phy-cells = <0>; <<
1913 <<
1914 resets = <&gcc GCC_PC <<
1915 reset-names = "phy"; <<
1916 <<
1917 assigned-clocks = <&g <<
1918 assigned-clock-rates <<
1919 <<
1920 status = "disabled"; <<
1921 }; <<
1922 <<
1923 pcie1: pcie@1c08000 { <<
1924 compatible = "qcom,pc <<
1925 reg = <0 0x01c08000 0 <<
1926 <0 0x40000000 0 <<
1927 <0 0x40000f20 0 <<
1928 <0 0x40001000 0 <<
1929 <0 0x40100000 0 <<
1930 reg-names = "parf", " <<
1931 device_type = "pci"; <<
1932 linux,pci-domain = <1 <<
1933 bus-range = <0x00 0xf <<
1934 num-lanes = <2>; <<
1935 <<
1936 #address-cells = <3>; <<
1937 #size-cells = <2>; <<
1938 <<
1939 ranges = <0x01000000 <<
1940 <0x02000000 <<
1941 <<
1942 msi-map = <0x0 &gic_i <<
1943 <0x100 &gic <<
1944 msi-map-mask = <0xff0 <<
1945 interrupts = <GIC_SPI <<
1946 <GIC_SPI <<
1947 <GIC_SPI <<
1948 <GIC_SPI <<
1949 <GIC_SPI <<
1950 <GIC_SPI <<
1951 <GIC_SPI <<
1952 <GIC_SPI <<
1953 interrupt-names = "ms <<
1954 "ms <<
1955 "ms <<
1956 "ms <<
1957 "ms <<
1958 "ms <<
1959 "ms <<
1960 "ms <<
1961 #interrupt-cells = <1 <<
1962 interrupt-map-mask = <<
1963 interrupt-map = <0 0 <<
1964 <0 0 <<
1965 <0 0 <<
1966 <0 0 <<
1967 <<
1968 interconnects = <&pci <<
1969 &mc_ <<
1970 <&gem <<
1971 &con <<
1972 interconnect-names = <<
1973 <<
1974 clocks = <&gcc GCC_PC <<
1975 <&gcc GCC_PC <<
1976 <&pcie1_phy <<
1977 <&rpmhcc RPM <<
1978 <&gcc GCC_PC <<
1979 <&gcc GCC_PC <<
1980 <&gcc GCC_PC <<
1981 <&gcc GCC_PC <<
1982 <&gcc GCC_PC <<
1983 <&gcc GCC_DD <<
1984 <&gcc GCC_AG <<
1985 clock-names = "pipe", <<
1986 "pipe_m <<
1987 "phy_pi <<
1988 "ref", <<
1989 "aux", <<
1990 "cfg", <<
1991 "bus_ma <<
1992 "bus_sl <<
1993 "slave_ <<
1994 "ddrss_ <<
1995 "aggre1 <<
1996 <<
1997 iommu-map = <0x0 &a <<
1998 <0x100 &a <<
1999 <<
2000 resets = <&gcc GCC_PC <<
2001 reset-names = "pci"; <<
2002 <<
2003 power-domains = <&gcc <<
2004 <<
2005 phys = <&pcie1_phy>; <<
2006 phy-names = "pciephy" <<
2007 <<
2008 perst-gpios = <&tlmm <<
2009 wake-gpios = <&tlmm 9 <<
2010 <<
2011 pinctrl-names = "defa <<
2012 pinctrl-0 = <&pcie1_d <<
2013 <<
2014 operating-points-v2 = <<
2015 <<
2016 status = "disabled"; <<
2017 <<
2018 pcie1_opp_table: opp- <<
2019 compatible = <<
2020 <<
2021 /* GEN 1 x1 * <<
2022 opp-2500000 { <<
2023 opp-h <<
2024 requi <<
2025 opp-p <<
2026 }; <<
2027 <<
2028 /* GEN 1 x2 a <<
2029 opp-5000000 { <<
2030 opp-h <<
2031 requi <<
2032 opp-p <<
2033 }; <<
2034 <<
2035 /* GEN 2 x2 * <<
2036 opp-10000000 <<
2037 opp-h <<
2038 requi <<
2039 opp-p <<
2040 }; <<
2041 <<
2042 /* GEN 3 x1 * <<
2043 opp-8000000 { <<
2044 opp-h <<
2045 requi <<
2046 opp-p <<
2047 }; <<
2048 <<
2049 /* GEN 3 x2 a <<
2050 opp-16000000 <<
2051 opp-h <<
2052 requi <<
2053 opp-p <<
2054 }; <<
2055 <<
2056 /* GEN 4 x2 * <<
2057 opp-32000000 <<
2058 opp-h <<
2059 requi <<
2060 opp-p <<
2061 }; <<
2062 }; <<
2063 <<
2064 pcie@0 { <<
2065 device_type = <<
2066 reg = <0x0 0x <<
2067 bus-range = < <<
2068 <<
2069 #address-cell <<
2070 #size-cells = <<
2071 ranges; <<
2072 }; <<
2073 }; <<
2074 <<
2075 pcie1_phy: phy@1c0e000 { <<
2076 compatible = "qcom,sm <<
2077 reg = <0 0x01c0e000 0 <<
2078 <<
2079 clocks = <&gcc GCC_PC <<
2080 <&gcc GCC_PC <<
2081 <&gcc GCC_PC <<
2082 <&gcc GCC_PC <<
2083 <&gcc GCC_PC <<
2084 clock-names = "aux", <<
2085 "cfg_ah <<
2086 "ref", <<
2087 "rchng" <<
2088 "pipe"; <<
2089 <<
2090 clock-output-names = <<
2091 #clock-cells = <1>; <<
2092 <<
2093 #phy-cells = <0>; <<
2094 <<
2095 resets = <&gcc GCC_PC <<
2096 reset-names = "phy"; <<
2097 <<
2098 assigned-clocks = <&g <<
2099 assigned-clock-rates <<
2100 <<
2101 status = "disabled"; <<
2102 }; 757 };
2103 758
2104 config_noc: interconnect@1500 759 config_noc: interconnect@1500000 {
2105 compatible = "qcom,sm 760 compatible = "qcom,sm8450-config-noc";
2106 reg = <0 0x01500000 0 761 reg = <0 0x01500000 0 0x1c000>;
2107 #interconnect-cells = 762 #interconnect-cells = <2>;
2108 qcom,bcm-voters = <&a 763 qcom,bcm-voters = <&apps_bcm_voter>;
2109 }; 764 };
2110 765
2111 system_noc: interconnect@1680 766 system_noc: interconnect@1680000 {
2112 compatible = "qcom,sm 767 compatible = "qcom,sm8450-system-noc";
2113 reg = <0 0x01680000 0 768 reg = <0 0x01680000 0 0x1e200>;
2114 #interconnect-cells = 769 #interconnect-cells = <2>;
2115 qcom,bcm-voters = <&a 770 qcom,bcm-voters = <&apps_bcm_voter>;
2116 }; 771 };
2117 772
2118 pcie_noc: interconnect@16c000 773 pcie_noc: interconnect@16c0000 {
2119 compatible = "qcom,sm 774 compatible = "qcom,sm8450-pcie-anoc";
2120 reg = <0 0x016c0000 0 775 reg = <0 0x016c0000 0 0xe280>;
2121 #interconnect-cells = 776 #interconnect-cells = <2>;
2122 qcom,bcm-voters = <&a 777 qcom,bcm-voters = <&apps_bcm_voter>;
2123 }; 778 };
2124 779
2125 aggre1_noc: interconnect@16e0 780 aggre1_noc: interconnect@16e0000 {
2126 compatible = "qcom,sm 781 compatible = "qcom,sm8450-aggre1-noc";
2127 reg = <0 0x016e0000 0 782 reg = <0 0x016e0000 0 0x1c080>;
2128 #interconnect-cells = 783 #interconnect-cells = <2>;
2129 clocks = <&gcc GCC_AG 784 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2130 <&gcc GCC_AG 785 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
2131 qcom,bcm-voters = <&a 786 qcom,bcm-voters = <&apps_bcm_voter>;
2132 }; 787 };
2133 788
2134 aggre2_noc: interconnect@1700 789 aggre2_noc: interconnect@1700000 {
2135 compatible = "qcom,sm 790 compatible = "qcom,sm8450-aggre2-noc";
2136 reg = <0 0x01700000 0 791 reg = <0 0x01700000 0 0x31080>;
2137 #interconnect-cells = 792 #interconnect-cells = <2>;
2138 qcom,bcm-voters = <&a 793 qcom,bcm-voters = <&apps_bcm_voter>;
2139 clocks = <&gcc GCC_AG 794 clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
2140 <&gcc GCC_AG 795 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
2141 <&gcc GCC_AG 796 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2142 <&rpmhcc RPM 797 <&rpmhcc RPMH_IPA_CLK>;
2143 }; 798 };
2144 799
2145 mmss_noc: interconnect@174000 800 mmss_noc: interconnect@1740000 {
2146 compatible = "qcom,sm 801 compatible = "qcom,sm8450-mmss-noc";
2147 reg = <0 0x01740000 0 802 reg = <0 0x01740000 0 0x1f080>;
2148 #interconnect-cells = 803 #interconnect-cells = <2>;
2149 qcom,bcm-voters = <&a 804 qcom,bcm-voters = <&apps_bcm_voter>;
2150 }; 805 };
2151 806
2152 tcsr_mutex: hwlock@1f40000 { 807 tcsr_mutex: hwlock@1f40000 {
2153 compatible = "qcom,tc 808 compatible = "qcom,tcsr-mutex";
2154 reg = <0x0 0x01f40000 809 reg = <0x0 0x01f40000 0x0 0x40000>;
2155 #hwlock-cells = <1>; 810 #hwlock-cells = <1>;
2156 }; 811 };
2157 812
2158 tcsr: syscon@1fc0000 { <<
2159 compatible = "qcom,sm <<
2160 reg = <0x0 0x1fc0000 <<
2161 }; <<
2162 <<
2163 gpu: gpu@3d00000 { <<
2164 compatible = "qcom,ad <<
2165 reg = <0x0 0x03d00000 <<
2166 <0x0 0x03d9e000 <<
2167 <0x0 0x03d61000 <<
2168 reg-names = "kgsl_3d0 <<
2169 "cx_mem", <<
2170 "cx_dbgc" <<
2171 <<
2172 interrupts = <GIC_SPI <<
2173 <<
2174 iommus = <&adreno_smm <<
2175 <&adreno_smm <<
2176 <<
2177 operating-points-v2 = <<
2178 <<
2179 qcom,gmu = <&gmu>; <<
2180 #cooling-cells = <2>; <<
2181 <<
2182 status = "disabled"; <<
2183 <<
2184 zap-shader { <<
2185 memory-region <<
2186 }; <<
2187 <<
2188 gpu_opp_table: opp-ta <<
2189 compatible = <<
2190 <<
2191 opp-818000000 <<
2192 opp-h <<
2193 opp-l <<
2194 }; <<
2195 <<
2196 opp-791000000 <<
2197 opp-h <<
2198 opp-l <<
2199 }; <<
2200 <<
2201 opp-734000000 <<
2202 opp-h <<
2203 opp-l <<
2204 }; <<
2205 <<
2206 opp-640000000 <<
2207 opp-h <<
2208 opp-l <<
2209 }; <<
2210 <<
2211 opp-599000000 <<
2212 opp-h <<
2213 opp-l <<
2214 }; <<
2215 <<
2216 opp-545000000 <<
2217 opp-h <<
2218 opp-l <<
2219 }; <<
2220 <<
2221 opp-492000000 <<
2222 opp-h <<
2223 opp-l <<
2224 }; <<
2225 <<
2226 opp-421000000 <<
2227 opp-h <<
2228 opp-l <<
2229 }; <<
2230 <<
2231 opp-350000000 <<
2232 opp-h <<
2233 opp-l <<
2234 }; <<
2235 <<
2236 opp-317000000 <<
2237 opp-h <<
2238 opp-l <<
2239 }; <<
2240 <<
2241 opp-285000000 <<
2242 opp-h <<
2243 opp-l <<
2244 }; <<
2245 <<
2246 opp-220000000 <<
2247 opp-h <<
2248 opp-l <<
2249 }; <<
2250 }; <<
2251 }; <<
2252 <<
2253 gmu: gmu@3d6a000 { <<
2254 compatible = "qcom,ad <<
2255 reg = <0x0 0x03d6a000 <<
2256 <0x0 0x03d50000 <<
2257 <0x0 0x0b290000 <<
2258 reg-names = "gmu", "r <<
2259 <<
2260 interrupts = <GIC_SPI <<
2261 <GIC_SPI <<
2262 interrupt-names = "hf <<
2263 <<
2264 clocks = <&gpucc GPU_ <<
2265 <&gpucc GPU_ <<
2266 <&gpucc GPU_ <<
2267 <&gcc GCC_DD <<
2268 <&gcc GCC_GP <<
2269 <&gpucc GPU_ <<
2270 <&gpucc GPU_ <<
2271 clock-names = "ahb", <<
2272 "gmu", <<
2273 "cxo", <<
2274 "axi", <<
2275 "memnoc <<
2276 "hub", <<
2277 "demet" <<
2278 <<
2279 power-domains = <&gpu <<
2280 <&gpu <<
2281 power-domain-names = <<
2282 <<
2283 <<
2284 iommus = <&adreno_smm <<
2285 <<
2286 qcom,qmp = <&aoss_qmp <<
2287 <<
2288 operating-points-v2 = <<
2289 <<
2290 gmu_opp_table: opp-ta <<
2291 compatible = <<
2292 <<
2293 opp-500000000 <<
2294 opp-h <<
2295 opp-l <<
2296 }; <<
2297 <<
2298 opp-200000000 <<
2299 opp-h <<
2300 opp-l <<
2301 }; <<
2302 }; <<
2303 }; <<
2304 <<
2305 gpucc: clock-controller@3d900 <<
2306 compatible = "qcom,sm <<
2307 reg = <0x0 0x03d90000 <<
2308 clocks = <&rpmhcc RPM <<
2309 <&gcc GCC_GP <<
2310 <&gcc GCC_GP <<
2311 #clock-cells = <1>; <<
2312 #reset-cells = <1>; <<
2313 #power-domain-cells = <<
2314 }; <<
2315 <<
2316 adreno_smmu: iommu@3da0000 { <<
2317 compatible = "qcom,sm <<
2318 "qcom,sm <<
2319 reg = <0x0 0x03da0000 <<
2320 #iommu-cells = <2>; <<
2321 #global-interrupts = <<
2322 interrupts = <GIC_SPI <<
2323 <GIC_SPI <<
2324 <GIC_SPI <<
2325 <GIC_SPI <<
2326 <GIC_SPI <<
2327 <GIC_SPI <<
2328 <GIC_SPI <<
2329 <GIC_SPI <<
2330 <GIC_SPI <<
2331 <GIC_SPI <<
2332 <GIC_SPI <<
2333 <GIC_SPI <<
2334 <GIC_SPI <<
2335 <GIC_SPI <<
2336 <GIC_SPI <<
2337 <GIC_SPI <<
2338 <GIC_SPI <<
2339 <GIC_SPI <<
2340 <GIC_SPI <<
2341 <GIC_SPI <<
2342 <GIC_SPI <<
2343 <GIC_SPI <<
2344 <GIC_SPI <<
2345 <GIC_SPI <<
2346 <GIC_SPI <<
2347 <GIC_SPI <<
2348 clocks = <&gpucc GPU_ <<
2349 <&gpucc GPU_ <<
2350 <&gpucc GPU_ <<
2351 <&gcc GCC_GP <<
2352 <&gcc GCC_GP <<
2353 <&gpucc GPU_ <<
2354 clock-names = "gmu", <<
2355 "hub", <<
2356 "hlos", <<
2357 "bus", <<
2358 "iface" <<
2359 "ahb"; <<
2360 power-domains = <&gpu <<
2361 dma-coherent; <<
2362 }; <<
2363 <<
2364 usb_1_hsphy: phy@88e3000 { 813 usb_1_hsphy: phy@88e3000 {
2365 compatible = "qcom,sm 814 compatible = "qcom,sm8450-usb-hs-phy",
2366 "qcom,us 815 "qcom,usb-snps-hs-7nm-phy";
2367 reg = <0 0x088e3000 0 816 reg = <0 0x088e3000 0 0x400>;
2368 status = "disabled"; 817 status = "disabled";
2369 #phy-cells = <0>; 818 #phy-cells = <0>;
2370 819
2371 clocks = <&rpmhcc RPM 820 clocks = <&rpmhcc RPMH_CXO_CLK>;
2372 clock-names = "ref"; 821 clock-names = "ref";
2373 822
2374 resets = <&gcc GCC_QU 823 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2375 }; 824 };
2376 825
2377 usb_1_qmpphy: phy@88e8000 { !! 826 usb_1_qmpphy: phy-wrapper@88e9000 {
2378 compatible = "qcom,sm !! 827 compatible = "qcom,sm8450-qmp-usb3-phy";
2379 reg = <0 0x088e8000 0 !! 828 reg = <0 0x088e9000 0 0x200>,
>> 829 <0 0x088e8000 0 0x20>;
>> 830 status = "disabled";
>> 831 #address-cells = <2>;
>> 832 #size-cells = <2>;
>> 833 ranges;
2380 834
2381 clocks = <&gcc GCC_US 835 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2382 <&rpmhcc RPM 836 <&rpmhcc RPMH_CXO_CLK>,
2383 <&gcc GCC_US !! 837 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
2384 <&gcc GCC_US !! 838 clock-names = "aux", "ref_clk_src", "com_aux";
2385 clock-names = "aux", <<
2386 839
2387 resets = <&gcc GCC_US 840 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
2388 <&gcc GCC_US 841 <&gcc GCC_USB3_PHY_PRIM_BCR>;
2389 reset-names = "phy", 842 reset-names = "phy", "common";
2390 843
2391 #clock-cells = <1>; !! 844 usb_1_ssphy: phy@88e9200 {
2392 #phy-cells = <1>; !! 845 reg = <0 0x088e9200 0 0x200>,
2393 !! 846 <0 0x088e9400 0 0x200>,
2394 orientation-switch; !! 847 <0 0x088e9c00 0 0x400>,
2395 !! 848 <0 0x088e9600 0 0x200>,
2396 status = "disabled"; !! 849 <0 0x088e9800 0 0x200>,
2397 !! 850 <0 0x088e9a00 0 0x100>;
2398 ports { !! 851 #phy-cells = <0>;
2399 #address-cell !! 852 #clock-cells = <1>;
2400 #size-cells = !! 853 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2401 !! 854 clock-names = "pipe0";
2402 port@0 { !! 855 clock-output-names = "usb3_phy_pipe_clk_src";
2403 reg = <<
2404 <<
2405 usb_1 <<
2406 }; <<
2407 }; <<
2408 <<
2409 port@1 { <<
2410 reg = <<
2411 <<
2412 usb_1 <<
2413 <<
2414 }; <<
2415 }; <<
2416 <<
2417 port@2 { <<
2418 reg = <<
2419 <<
2420 usb_1 <<
2421 <<
2422 }; <<
2423 }; <<
2424 }; 856 };
2425 }; 857 };
2426 858
2427 remoteproc_slpi: remoteproc@2 859 remoteproc_slpi: remoteproc@2400000 {
2428 compatible = "qcom,sm 860 compatible = "qcom,sm8450-slpi-pas";
2429 reg = <0 0x02400000 0 861 reg = <0 0x02400000 0 0x4000>;
2430 862
2431 interrupts-extended = !! 863 interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
2432 864 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
2433 865 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
2434 866 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
2435 867 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
2436 interrupt-names = "wd 868 interrupt-names = "wdog", "fatal", "ready",
2437 "ha 869 "handover", "stop-ack";
2438 870
2439 clocks = <&rpmhcc RPM 871 clocks = <&rpmhcc RPMH_CXO_CLK>;
2440 clock-names = "xo"; 872 clock-names = "xo";
2441 873
2442 power-domains = <&rpm !! 874 power-domains = <&rpmhpd SM8450_LCX>,
2443 <&rpm !! 875 <&rpmhpd SM8450_LMX>;
2444 power-domain-names = 876 power-domain-names = "lcx", "lmx";
2445 877
2446 memory-region = <&slp 878 memory-region = <&slpi_mem>;
2447 879
2448 qcom,qmp = <&aoss_qmp 880 qcom,qmp = <&aoss_qmp>;
2449 881
2450 qcom,smem-states = <& 882 qcom,smem-states = <&smp2p_slpi_out 0>;
2451 qcom,smem-state-names 883 qcom,smem-state-names = "stop";
2452 884
2453 status = "disabled"; 885 status = "disabled";
2454 886
2455 glink-edge { 887 glink-edge {
2456 interrupts-ex 888 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
2457 889 IPCC_MPROC_SIGNAL_GLINK_QMP
2458 890 IRQ_TYPE_EDGE_RISING>;
2459 mboxes = <&ip 891 mboxes = <&ipcc IPCC_CLIENT_SLPI
2460 892 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2461 893
2462 label = "slpi 894 label = "slpi";
2463 qcom,remote-p 895 qcom,remote-pid = <3>;
2464 <<
2465 fastrpc { <<
2466 compa <<
2467 qcom, <<
2468 label <<
2469 qcom, <<
2470 #addr <<
2471 #size <<
2472 <<
2473 compu <<
2474 <<
2475 <<
2476 <<
2477 }; <<
2478 <<
2479 compu <<
2480 <<
2481 <<
2482 <<
2483 }; <<
2484 <<
2485 compu <<
2486 <<
2487 <<
2488 <<
2489 <<
2490 }; <<
2491 }; <<
2492 }; 896 };
2493 }; 897 };
2494 898
2495 wsa2macro: codec@31e0000 { <<
2496 compatible = "qcom,sm <<
2497 reg = <0 0x031e0000 0 <<
2498 clocks = <&q6prmcc LP <<
2499 <&q6prmcc LP <<
2500 <&q6prmcc LP <<
2501 <&q6prmcc LP <<
2502 <&vamacro>; <<
2503 clock-names = "mclk", <<
2504 <<
2505 #clock-cells = <0>; <<
2506 clock-output-names = <<
2507 #sound-dai-cells = <1 <<
2508 }; <<
2509 <<
2510 swr4: soundwire@31f0000 { <<
2511 compatible = "qcom,so <<
2512 reg = <0 0x031f0000 0 <<
2513 interrupts = <GIC_SPI <<
2514 clocks = <&wsa2macro> <<
2515 clock-names = "iface" <<
2516 label = "WSA2"; <<
2517 <<
2518 pinctrl-0 = <&wsa2_sw <<
2519 pinctrl-names = "defa <<
2520 <<
2521 qcom,din-ports = <2>; <<
2522 qcom,dout-ports = <6> <<
2523 <<
2524 qcom,ports-sinterval- <<
2525 qcom,ports-offset1 = <<
2526 qcom,ports-offset2 = <<
2527 qcom,ports-hstart = <<
2528 qcom,ports-hstop = <<
2529 qcom,ports-word-lengt <<
2530 qcom,ports-block-pack <<
2531 qcom,ports-block-grou <<
2532 qcom,ports-lane-contr <<
2533 <<
2534 #address-cells = <2>; <<
2535 #size-cells = <0>; <<
2536 #sound-dai-cells = <1 <<
2537 status = "disabled"; <<
2538 }; <<
2539 <<
2540 rxmacro: codec@3200000 { <<
2541 compatible = "qcom,sm <<
2542 reg = <0 0x03200000 0 <<
2543 clocks = <&q6prmcc LP <<
2544 <&q6prmcc LP <<
2545 <&q6prmcc LP <<
2546 <&q6prmcc LP <<
2547 <&vamacro>; <<
2548 clock-names = "mclk", <<
2549 <<
2550 #clock-cells = <0>; <<
2551 clock-output-names = <<
2552 #sound-dai-cells = <1 <<
2553 }; <<
2554 <<
2555 swr1: soundwire@3210000 { <<
2556 compatible = "qcom,so <<
2557 reg = <0 0x03210000 0 <<
2558 interrupts = <GIC_SPI <<
2559 clocks = <&rxmacro>; <<
2560 clock-names = "iface" <<
2561 label = "RX"; <<
2562 qcom,din-ports = <0>; <<
2563 qcom,dout-ports = <5> <<
2564 <<
2565 pinctrl-0 = <&rx_swr_ <<
2566 pinctrl-names = "defa <<
2567 <<
2568 qcom,ports-sinterval- <<
2569 qcom,ports-offset1 = <<
2570 qcom,ports-offset2 = <<
2571 qcom,ports-hstart = <<
2572 qcom,ports-hstop = <<
2573 qcom,ports-word-lengt <<
2574 qcom,ports-block-pack <<
2575 qcom,ports-block-grou <<
2576 qcom,ports-lane-contr <<
2577 <<
2578 #address-cells = <2>; <<
2579 #size-cells = <0>; <<
2580 #sound-dai-cells = <1 <<
2581 status = "disabled"; <<
2582 }; <<
2583 <<
2584 txmacro: codec@3220000 { <<
2585 compatible = "qcom,sm <<
2586 reg = <0 0x03220000 0 <<
2587 clocks = <&q6prmcc LP <<
2588 <&q6prmcc LP <<
2589 <&q6prmcc LP <<
2590 <&q6prmcc LP <<
2591 <&vamacro>; <<
2592 clock-names = "mclk", <<
2593 <<
2594 #clock-cells = <0>; <<
2595 clock-output-names = <<
2596 #sound-dai-cells = <1 <<
2597 }; <<
2598 <<
2599 wsamacro: codec@3240000 { <<
2600 compatible = "qcom,sm <<
2601 reg = <0 0x03240000 0 <<
2602 clocks = <&q6prmcc LP <<
2603 <&q6prmcc LP <<
2604 <&q6prmcc LP <<
2605 <&q6prmcc LP <<
2606 <&vamacro>; <<
2607 clock-names = "mclk", <<
2608 <<
2609 #clock-cells = <0>; <<
2610 clock-output-names = <<
2611 #sound-dai-cells = <1 <<
2612 }; <<
2613 <<
2614 swr0: soundwire@3250000 { <<
2615 compatible = "qcom,so <<
2616 reg = <0 0x03250000 0 <<
2617 interrupts = <GIC_SPI <<
2618 clocks = <&wsamacro>; <<
2619 clock-names = "iface" <<
2620 label = "WSA"; <<
2621 <<
2622 pinctrl-0 = <&wsa_swr <<
2623 pinctrl-names = "defa <<
2624 <<
2625 qcom,din-ports = <2>; <<
2626 qcom,dout-ports = <6> <<
2627 <<
2628 qcom,ports-sinterval- <<
2629 qcom,ports-offset1 = <<
2630 qcom,ports-offset2 = <<
2631 qcom,ports-hstart = <<
2632 qcom,ports-hstop = <<
2633 qcom,ports-word-lengt <<
2634 qcom,ports-block-pack <<
2635 qcom,ports-block-grou <<
2636 qcom,ports-lane-contr <<
2637 <<
2638 #address-cells = <2>; <<
2639 #size-cells = <0>; <<
2640 #sound-dai-cells = <1 <<
2641 status = "disabled"; <<
2642 }; <<
2643 <<
2644 swr2: soundwire@33b0000 { <<
2645 compatible = "qcom,so <<
2646 reg = <0 0x033b0000 0 <<
2647 interrupts = <GIC_SPI <<
2648 <GIC_SPI <<
2649 interrupt-names = "co <<
2650 <<
2651 clocks = <&txmacro>; <<
2652 clock-names = "iface" <<
2653 label = "TX"; <<
2654 <<
2655 pinctrl-0 = <&tx_swr_ <<
2656 pinctrl-names = "defa <<
2657 <<
2658 qcom,din-ports = <4>; <<
2659 qcom,dout-ports = <0> <<
2660 qcom,ports-sinterval- <<
2661 qcom,ports-offset1 = <<
2662 qcom,ports-offset2 = <<
2663 qcom,ports-hstart = <<
2664 qcom,ports-hstop = <<
2665 qcom,ports-word-lengt <<
2666 qcom,ports-block-pack <<
2667 qcom,ports-block-grou <<
2668 qcom,ports-lane-contr <<
2669 <<
2670 #address-cells = <2>; <<
2671 #size-cells = <0>; <<
2672 #sound-dai-cells = <1 <<
2673 status = "disabled"; <<
2674 }; <<
2675 <<
2676 vamacro: codec@33f0000 { <<
2677 compatible = "qcom,sm <<
2678 reg = <0 0x033f0000 0 <<
2679 clocks = <&q6prmcc LP <<
2680 <&q6prmcc LP <<
2681 <&q6prmcc LP <<
2682 <&q6prmcc LP <<
2683 clock-names = "mclk", <<
2684 <<
2685 #clock-cells = <0>; <<
2686 clock-output-names = <<
2687 #sound-dai-cells = <1 <<
2688 status = "disabled"; <<
2689 }; <<
2690 <<
2691 remoteproc_adsp: remoteproc@3 899 remoteproc_adsp: remoteproc@30000000 {
2692 compatible = "qcom,sm 900 compatible = "qcom,sm8450-adsp-pas";
2693 reg = <0 0x30000000 0 !! 901 reg = <0 0x030000000 0 0x100>;
2694 902
2695 interrupts-extended = !! 903 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
2696 904 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
2697 905 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
2698 906 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
2699 907 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
2700 interrupt-names = "wd 908 interrupt-names = "wdog", "fatal", "ready",
2701 "ha 909 "handover", "stop-ack";
2702 910
2703 clocks = <&rpmhcc RPM 911 clocks = <&rpmhcc RPMH_CXO_CLK>;
2704 clock-names = "xo"; 912 clock-names = "xo";
2705 913
2706 power-domains = <&rpm !! 914 power-domains = <&rpmhpd SM8450_LCX>,
2707 <&rpm !! 915 <&rpmhpd SM8450_LMX>;
2708 power-domain-names = 916 power-domain-names = "lcx", "lmx";
2709 917
2710 memory-region = <&ads 918 memory-region = <&adsp_mem>;
2711 919
2712 qcom,qmp = <&aoss_qmp 920 qcom,qmp = <&aoss_qmp>;
2713 921
2714 qcom,smem-states = <& 922 qcom,smem-states = <&smp2p_adsp_out 0>;
2715 qcom,smem-state-names 923 qcom,smem-state-names = "stop";
2716 924
2717 status = "disabled"; 925 status = "disabled";
2718 926
2719 remoteproc_adsp_glink 927 remoteproc_adsp_glink: glink-edge {
2720 interrupts-ex 928 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
2721 929 IPCC_MPROC_SIGNAL_GLINK_QMP
2722 930 IRQ_TYPE_EDGE_RISING>;
2723 mboxes = <&ip 931 mboxes = <&ipcc IPCC_CLIENT_LPASS
2724 932 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2725 933
2726 label = "lpas 934 label = "lpass";
2727 qcom,remote-p 935 qcom,remote-pid = <2>;
2728 <<
2729 gpr { <<
2730 compa <<
2731 qcom, <<
2732 qcom, <<
2733 qcom, <<
2734 #addr <<
2735 #size <<
2736 <<
2737 q6apm <<
2738 <<
2739 <<
2740 <<
2741 <<
2742 <<
2743 <<
2744 <<
2745 <<
2746 <<
2747 <<
2748 <<
2749 <<
2750 <<
2751 <<
2752 <<
2753 }; <<
2754 <<
2755 q6prm <<
2756 <<
2757 <<
2758 <<
2759 <<
2760 <<
2761 <<
2762 <<
2763 <<
2764 <<
2765 }; <<
2766 }; <<
2767 <<
2768 fastrpc { <<
2769 compa <<
2770 qcom, <<
2771 label <<
2772 qcom, <<
2773 #addr <<
2774 #size <<
2775 <<
2776 compu <<
2777 <<
2778 <<
2779 <<
2780 }; <<
2781 <<
2782 compu <<
2783 <<
2784 <<
2785 <<
2786 }; <<
2787 <<
2788 compu <<
2789 <<
2790 <<
2791 <<
2792 }; <<
2793 }; <<
2794 }; 936 };
2795 }; 937 };
2796 938
2797 remoteproc_cdsp: remoteproc@3 939 remoteproc_cdsp: remoteproc@32300000 {
2798 compatible = "qcom,sm 940 compatible = "qcom,sm8450-cdsp-pas";
2799 reg = <0 0x32300000 0 !! 941 reg = <0 0x032300000 0 0x1400000>;
2800 942
2801 interrupts-extended = !! 943 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
2802 944 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
2803 945 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
2804 946 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
2805 947 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
2806 interrupt-names = "wd 948 interrupt-names = "wdog", "fatal", "ready",
2807 "ha 949 "handover", "stop-ack";
2808 950
2809 clocks = <&rpmhcc RPM 951 clocks = <&rpmhcc RPMH_CXO_CLK>;
2810 clock-names = "xo"; 952 clock-names = "xo";
2811 953
2812 power-domains = <&rpm !! 954 power-domains = <&rpmhpd SM8450_CX>,
2813 <&rpm !! 955 <&rpmhpd SM8450_MXC>;
2814 power-domain-names = 956 power-domain-names = "cx", "mxc";
2815 957
2816 memory-region = <&cds 958 memory-region = <&cdsp_mem>;
2817 959
2818 qcom,qmp = <&aoss_qmp 960 qcom,qmp = <&aoss_qmp>;
2819 961
2820 qcom,smem-states = <& 962 qcom,smem-states = <&smp2p_cdsp_out 0>;
2821 qcom,smem-state-names 963 qcom,smem-state-names = "stop";
2822 964
2823 status = "disabled"; 965 status = "disabled";
2824 966
2825 glink-edge { 967 glink-edge {
2826 interrupts-ex 968 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
2827 969 IPCC_MPROC_SIGNAL_GLINK_QMP
2828 970 IRQ_TYPE_EDGE_RISING>;
2829 mboxes = <&ip 971 mboxes = <&ipcc IPCC_CLIENT_CDSP
2830 972 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2831 973
2832 label = "cdsp 974 label = "cdsp";
2833 qcom,remote-p 975 qcom,remote-pid = <5>;
2834 <<
2835 fastrpc { <<
2836 compa <<
2837 qcom, <<
2838 label <<
2839 qcom, <<
2840 #addr <<
2841 #size <<
2842 <<
2843 compu <<
2844 <<
2845 <<
2846 <<
2847 <<
2848 }; <<
2849 <<
2850 compu <<
2851 <<
2852 <<
2853 <<
2854 <<
2855 }; <<
2856 <<
2857 compu <<
2858 <<
2859 <<
2860 <<
2861 <<
2862 }; <<
2863 <<
2864 compu <<
2865 <<
2866 <<
2867 <<
2868 <<
2869 }; <<
2870 <<
2871 compu <<
2872 <<
2873 <<
2874 <<
2875 <<
2876 }; <<
2877 <<
2878 compu <<
2879 <<
2880 <<
2881 <<
2882 <<
2883 }; <<
2884 <<
2885 compu <<
2886 <<
2887 <<
2888 <<
2889 <<
2890 }; <<
2891 <<
2892 compu <<
2893 <<
2894 <<
2895 <<
2896 <<
2897 }; <<
2898 <<
2899 /* no <<
2900 }; <<
2901 }; 976 };
2902 }; 977 };
2903 978
2904 remoteproc_mpss: remoteproc@4 979 remoteproc_mpss: remoteproc@4080000 {
2905 compatible = "qcom,sm 980 compatible = "qcom,sm8450-mpss-pas";
2906 reg = <0x0 0x04080000 981 reg = <0x0 0x04080000 0x0 0x4040>;
2907 982
2908 interrupts-extended = !! 983 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
2909 984 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
2910 985 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
2911 986 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
2912 987 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>,
2913 988 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>;
2914 interrupt-names = "wd 989 interrupt-names = "wdog", "fatal", "ready", "handover",
2915 "st 990 "stop-ack", "shutdown-ack";
2916 991
2917 clocks = <&rpmhcc RPM 992 clocks = <&rpmhcc RPMH_CXO_CLK>;
2918 clock-names = "xo"; 993 clock-names = "xo";
2919 994
2920 power-domains = <&rpm !! 995 power-domains = <&rpmhpd 0>,
2921 <&rpm !! 996 <&rpmhpd 12>;
2922 power-domain-names = 997 power-domain-names = "cx", "mss";
2923 998
2924 memory-region = <&mps 999 memory-region = <&mpss_mem>;
2925 1000
2926 qcom,qmp = <&aoss_qmp 1001 qcom,qmp = <&aoss_qmp>;
2927 1002
2928 qcom,smem-states = <& 1003 qcom,smem-states = <&smp2p_modem_out 0>;
2929 qcom,smem-state-names 1004 qcom,smem-state-names = "stop";
2930 1005
2931 status = "disabled"; 1006 status = "disabled";
2932 1007
2933 glink-edge { 1008 glink-edge {
2934 interrupts-ex 1009 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
2935 1010 IPCC_MPROC_SIGNAL_GLINK_QMP
2936 1011 IRQ_TYPE_EDGE_RISING>;
2937 mboxes = <&ip 1012 mboxes = <&ipcc IPCC_CLIENT_MPSS
2938 1013 IPCC_MPROC_SIGNAL_GLINK_QMP>;
>> 1014 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
2939 label = "mode 1015 label = "modem";
2940 qcom,remote-p 1016 qcom,remote-pid = <1>;
2941 }; 1017 };
2942 }; 1018 };
2943 1019
2944 videocc: clock-controller@aaf <<
2945 compatible = "qcom,sm <<
2946 reg = <0 0x0aaf0000 0 <<
2947 clocks = <&rpmhcc RPM <<
2948 <&gcc GCC_VI <<
2949 power-domains = <&rpm <<
2950 required-opps = <&rpm <<
2951 #clock-cells = <1>; <<
2952 #reset-cells = <1>; <<
2953 #power-domain-cells = <<
2954 }; <<
2955 <<
2956 cci0: cci@ac15000 { <<
2957 compatible = "qcom,sm <<
2958 reg = <0 0x0ac15000 0 <<
2959 interrupts = <GIC_SPI <<
2960 power-domains = <&cam <<
2961 <<
2962 clocks = <&camcc CAM_ <<
2963 <&camcc CAM_ <<
2964 <&camcc CAM_ <<
2965 <&camcc CAM_ <<
2966 <&camcc CAM_ <<
2967 clock-names = "camnoc <<
2968 "slow_a <<
2969 "cpas_a <<
2970 "cci", <<
2971 "cci_sr <<
2972 pinctrl-0 = <&cci0_de <<
2973 pinctrl-1 = <&cci0_sl <<
2974 pinctrl-names = "defa <<
2975 <<
2976 status = "disabled"; <<
2977 #address-cells = <1>; <<
2978 #size-cells = <0>; <<
2979 <<
2980 cci0_i2c0: i2c-bus@0 <<
2981 reg = <0>; <<
2982 clock-frequen <<
2983 #address-cell <<
2984 #size-cells = <<
2985 }; <<
2986 <<
2987 cci0_i2c1: i2c-bus@1 <<
2988 reg = <1>; <<
2989 clock-frequen <<
2990 #address-cell <<
2991 #size-cells = <<
2992 }; <<
2993 }; <<
2994 <<
2995 cci1: cci@ac16000 { <<
2996 compatible = "qcom,sm <<
2997 reg = <0 0x0ac16000 0 <<
2998 interrupts = <GIC_SPI <<
2999 power-domains = <&cam <<
3000 <<
3001 clocks = <&camcc CAM_ <<
3002 <&camcc CAM_ <<
3003 <&camcc CAM_ <<
3004 <&camcc CAM_ <<
3005 <&camcc CAM_ <<
3006 clock-names = "camnoc <<
3007 "slow_a <<
3008 "cpas_a <<
3009 "cci", <<
3010 "cci_sr <<
3011 pinctrl-0 = <&cci2_de <<
3012 pinctrl-1 = <&cci2_sl <<
3013 pinctrl-names = "defa <<
3014 <<
3015 status = "disabled"; <<
3016 #address-cells = <1>; <<
3017 #size-cells = <0>; <<
3018 <<
3019 cci1_i2c0: i2c-bus@0 <<
3020 reg = <0>; <<
3021 clock-frequen <<
3022 #address-cell <<
3023 #size-cells = <<
3024 }; <<
3025 <<
3026 cci1_i2c1: i2c-bus@1 <<
3027 reg = <1>; <<
3028 clock-frequen <<
3029 #address-cell <<
3030 #size-cells = <<
3031 }; <<
3032 }; <<
3033 <<
3034 camcc: clock-controller@ade00 <<
3035 compatible = "qcom,sm <<
3036 reg = <0 0x0ade0000 0 <<
3037 clocks = <&gcc GCC_CA <<
3038 <&rpmhcc RPM <<
3039 <&rpmhcc RPM <<
3040 <&sleep_clk> <<
3041 power-domains = <&rpm <<
3042 required-opps = <&rpm <<
3043 #clock-cells = <1>; <<
3044 #reset-cells = <1>; <<
3045 #power-domain-cells = <<
3046 status = "disabled"; <<
3047 }; <<
3048 <<
3049 mdss: display-subsystem@ae000 <<
3050 compatible = "qcom,sm <<
3051 reg = <0 0x0ae00000 0 <<
3052 reg-names = "mdss"; <<
3053 <<
3054 /* same path used twi <<
3055 interconnects = <&mms <<
3056 <&mms <<
3057 <&gem <<
3058 &con <<
3059 interconnect-names = <<
3060 <<
3061 <<
3062 <<
3063 resets = <&dispcc DIS <<
3064 <<
3065 power-domains = <&dis <<
3066 <<
3067 clocks = <&dispcc DIS <<
3068 <&gcc GCC_DI <<
3069 <&gcc GCC_DI <<
3070 <&dispcc DIS <<
3071 <<
3072 interrupts = <GIC_SPI <<
3073 interrupt-controller; <<
3074 #interrupt-cells = <1 <<
3075 <<
3076 iommus = <&apps_smmu <<
3077 <<
3078 #address-cells = <2>; <<
3079 #size-cells = <2>; <<
3080 ranges; <<
3081 <<
3082 status = "disabled"; <<
3083 <<
3084 mdss_mdp: display-con <<
3085 compatible = <<
3086 reg = <0 0x0a <<
3087 <0 0x0a <<
3088 reg-names = " <<
3089 <<
3090 clocks = <&gc <<
3091 <&gcc <<
3092 <&dis <<
3093 <&dis <<
3094 <&dis <<
3095 <&dis <<
3096 clock-names = <<
3097 <<
3098 <<
3099 <<
3100 <<
3101 <<
3102 <<
3103 assigned-cloc <<
3104 assigned-cloc <<
3105 <<
3106 operating-poi <<
3107 power-domains <<
3108 <<
3109 interrupt-par <<
3110 interrupts = <<
3111 <<
3112 ports { <<
3113 #addr <<
3114 #size <<
3115 <<
3116 port@ <<
3117 <<
3118 <<
3119 <<
3120 <<
3121 }; <<
3122 <<
3123 port@ <<
3124 <<
3125 <<
3126 <<
3127 <<
3128 }; <<
3129 <<
3130 port@ <<
3131 <<
3132 <<
3133 <<
3134 <<
3135 }; <<
3136 }; <<
3137 <<
3138 mdp_opp_table <<
3139 compa <<
3140 <<
3141 opp-1 <<
3142 <<
3143 <<
3144 }; <<
3145 <<
3146 opp-2 <<
3147 <<
3148 <<
3149 }; <<
3150 <<
3151 opp-3 <<
3152 <<
3153 <<
3154 }; <<
3155 <<
3156 opp-3 <<
3157 <<
3158 <<
3159 }; <<
3160 <<
3161 opp-5 <<
3162 <<
3163 <<
3164 }; <<
3165 }; <<
3166 }; <<
3167 <<
3168 mdss_dp0: displayport <<
3169 compatible = <<
3170 reg = <0 0xae <<
3171 <0 0xae <<
3172 <0 0xae <<
3173 <0 0xae <<
3174 <0 0xae <<
3175 interrupt-par <<
3176 interrupts = <<
3177 clocks = <&di <<
3178 <&di <<
3179 <&di <<
3180 <&di <<
3181 <&di <<
3182 clock-names = <<
3183 <<
3184 <<
3185 <<
3186 <<
3187 <<
3188 assigned-cloc <<
3189 <<
3190 assigned-cloc <<
3191 <<
3192 <<
3193 phys = <&usb_ <<
3194 phy-names = " <<
3195 <<
3196 #sound-dai-ce <<
3197 <<
3198 operating-poi <<
3199 power-domains <<
3200 <<
3201 status = "dis <<
3202 <<
3203 ports { <<
3204 #addr <<
3205 #size <<
3206 <<
3207 port@ <<
3208 <<
3209 <<
3210 <<
3211 <<
3212 }; <<
3213 <<
3214 port@ <<
3215 <<
3216 <<
3217 <<
3218 <<
3219 <<
3220 }; <<
3221 }; <<
3222 <<
3223 dp_opp_table: <<
3224 compa <<
3225 <<
3226 opp-1 <<
3227 <<
3228 <<
3229 }; <<
3230 <<
3231 opp-2 <<
3232 <<
3233 <<
3234 }; <<
3235 <<
3236 opp-5 <<
3237 <<
3238 <<
3239 }; <<
3240 <<
3241 opp-8 <<
3242 <<
3243 <<
3244 }; <<
3245 }; <<
3246 }; <<
3247 <<
3248 mdss_dsi0: dsi@ae9400 <<
3249 compatible = <<
3250 reg = <0 0x0a <<
3251 reg-names = " <<
3252 <<
3253 interrupt-par <<
3254 interrupts = <<
3255 <<
3256 clocks = <&di <<
3257 <&di <<
3258 <&di <<
3259 <&di <<
3260 <&di <<
3261 <&gcc <<
3262 clock-names = <<
3263 <<
3264 <<
3265 <<
3266 <<
3267 <<
3268 <<
3269 assigned-cloc <<
3270 assigned-cloc <<
3271 <<
3272 operating-poi <<
3273 power-domains <<
3274 <<
3275 phys = <&mdss <<
3276 phy-names = " <<
3277 <<
3278 #address-cell <<
3279 #size-cells = <<
3280 <<
3281 status = "dis <<
3282 <<
3283 ports { <<
3284 #addr <<
3285 #size <<
3286 <<
3287 port@ <<
3288 <<
3289 <<
3290 <<
3291 <<
3292 }; <<
3293 <<
3294 port@ <<
3295 <<
3296 <<
3297 <<
3298 }; <<
3299 }; <<
3300 <<
3301 mdss_dsi_opp_ <<
3302 compa <<
3303 <<
3304 opp-1 <<
3305 <<
3306 <<
3307 }; <<
3308 <<
3309 opp-3 <<
3310 <<
3311 <<
3312 }; <<
3313 <<
3314 opp-3 <<
3315 <<
3316 <<
3317 }; <<
3318 }; <<
3319 }; <<
3320 <<
3321 mdss_dsi0_phy: phy@ae <<
3322 compatible = <<
3323 reg = <0 0x0a <<
3324 <0 0x0a <<
3325 <0 0x0a <<
3326 reg-names = " <<
3327 " <<
3328 " <<
3329 <<
3330 #clock-cells <<
3331 #phy-cells = <<
3332 <<
3333 clocks = <&di <<
3334 <&rp <<
3335 clock-names = <<
3336 <<
3337 status = "dis <<
3338 }; <<
3339 <<
3340 mdss_dsi1: dsi@ae9600 <<
3341 compatible = <<
3342 reg = <0 0x0a <<
3343 reg-names = " <<
3344 <<
3345 interrupt-par <<
3346 interrupts = <<
3347 <<
3348 clocks = <&di <<
3349 <&di <<
3350 <&di <<
3351 <&di <<
3352 <&di <<
3353 <&gc <<
3354 clock-names = <<
3355 <<
3356 <<
3357 <<
3358 <<
3359 <<
3360 <<
3361 assigned-cloc <<
3362 assigned-cloc <<
3363 <<
3364 operating-poi <<
3365 power-domains <<
3366 <<
3367 phys = <&mdss <<
3368 phy-names = " <<
3369 <<
3370 #address-cell <<
3371 #size-cells = <<
3372 <<
3373 status = "dis <<
3374 <<
3375 ports { <<
3376 #addr <<
3377 #size <<
3378 <<
3379 port@ <<
3380 <<
3381 <<
3382 <<
3383 <<
3384 }; <<
3385 <<
3386 port@ <<
3387 <<
3388 <<
3389 <<
3390 }; <<
3391 }; <<
3392 }; <<
3393 <<
3394 mdss_dsi1_phy: phy@ae <<
3395 compatible = <<
3396 reg = <0 0x0a <<
3397 <0 0x0a <<
3398 <0 0x0a <<
3399 reg-names = " <<
3400 " <<
3401 " <<
3402 <<
3403 #clock-cells <<
3404 #phy-cells = <<
3405 <<
3406 clocks = <&di <<
3407 <&rp <<
3408 clock-names = <<
3409 <<
3410 status = "dis <<
3411 }; <<
3412 }; <<
3413 <<
3414 dispcc: clock-controller@af00 <<
3415 compatible = "qcom,sm <<
3416 reg = <0 0x0af00000 0 <<
3417 clocks = <&rpmhcc RPM <<
3418 <&rpmhcc RPM <<
3419 <&gcc GCC_DI <<
3420 <&sleep_clk> <<
3421 <&mdss_dsi0_ <<
3422 <&mdss_dsi0_ <<
3423 <&mdss_dsi1_ <<
3424 <&mdss_dsi1_ <<
3425 <&usb_1_qmpp <<
3426 <&usb_1_qmpp <<
3427 <0>, /* dp1 <<
3428 <0>, <<
3429 <0>, /* dp2 <<
3430 <0>, <<
3431 <0>, /* dp3 <<
3432 <0>; <<
3433 power-domains = <&rpm <<
3434 required-opps = <&rpm <<
3435 #clock-cells = <1>; <<
3436 #reset-cells = <1>; <<
3437 #power-domain-cells = <<
3438 status = "disabled"; <<
3439 }; <<
3440 <<
3441 pdc: interrupt-controller@b22 1020 pdc: interrupt-controller@b220000 {
3442 compatible = "qcom,sm 1021 compatible = "qcom,sm8450-pdc", "qcom,pdc";
3443 reg = <0 0x0b220000 0 1022 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
3444 qcom,pdc-ranges = <0 1023 qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>,
3445 <94 1024 <94 609 31>, <125 63 1>, <126 716 12>;
3446 #interrupt-cells = <2 1025 #interrupt-cells = <2>;
3447 interrupt-parent = <& 1026 interrupt-parent = <&intc>;
3448 interrupt-controller; 1027 interrupt-controller;
3449 }; 1028 };
3450 1029
3451 tsens0: thermal-sensor@c26300 !! 1030 aoss_qmp: power-controller@c300000 {
3452 compatible = "qcom,sm <<
3453 reg = <0 0x0c263000 0 <<
3454 <0 0x0c222000 0 <<
3455 #qcom,sensors = <16>; <<
3456 interrupts = <GIC_SPI <<
3457 <GIC_SPI <<
3458 interrupt-names = "up <<
3459 #thermal-sensor-cells <<
3460 }; <<
3461 <<
3462 tsens1: thermal-sensor@c26500 <<
3463 compatible = "qcom,sm <<
3464 reg = <0 0x0c265000 0 <<
3465 <0 0x0c223000 0 <<
3466 #qcom,sensors = <16>; <<
3467 interrupts = <GIC_SPI <<
3468 <GIC_SPI <<
3469 interrupt-names = "up <<
3470 #thermal-sensor-cells <<
3471 }; <<
3472 <<
3473 aoss_qmp: power-management@c3 <<
3474 compatible = "qcom,sm 1031 compatible = "qcom,sm8450-aoss-qmp", "qcom,aoss-qmp";
3475 reg = <0 0x0c300000 0 1032 reg = <0 0x0c300000 0 0x400>;
3476 interrupts-extended = 1033 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
3477 1034 IRQ_TYPE_EDGE_RISING>;
3478 mboxes = <&ipcc IPCC_ 1035 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
3479 1036
3480 #clock-cells = <0>; 1037 #clock-cells = <0>;
3481 }; 1038 };
3482 1039
3483 sram@c3f0000 { <<
3484 compatible = "qcom,rp <<
3485 reg = <0 0x0c3f0000 0 <<
3486 }; <<
3487 <<
3488 spmi_bus: spmi@c400000 { <<
3489 compatible = "qcom,sp <<
3490 reg = <0 0x0c400000 0 <<
3491 <0 0x0c500000 0 <<
3492 <0 0x0c440000 0 <<
3493 <0 0x0c4c0000 0 <<
3494 <0 0x0c42d000 0 <<
3495 reg-names = "core", <<
3496 "chnls", <<
3497 "obsrvr", <<
3498 "intr", <<
3499 "cnfg"; <<
3500 interrupt-names = "pe <<
3501 interrupts-extended = <<
3502 qcom,ee = <0>; <<
3503 qcom,channel = <0>; <<
3504 interrupt-controller; <<
3505 #interrupt-cells = <4 <<
3506 #address-cells = <2>; <<
3507 #size-cells = <0>; <<
3508 }; <<
3509 <<
3510 ipcc: mailbox@ed18000 { 1040 ipcc: mailbox@ed18000 {
3511 compatible = "qcom,sm 1041 compatible = "qcom,sm8450-ipcc", "qcom,ipcc";
3512 reg = <0 0x0ed18000 0 1042 reg = <0 0x0ed18000 0 0x1000>;
3513 interrupts = <GIC_SPI 1043 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
3514 interrupt-controller; 1044 interrupt-controller;
3515 #interrupt-cells = <3 1045 #interrupt-cells = <3>;
3516 #mbox-cells = <2>; 1046 #mbox-cells = <2>;
3517 }; 1047 };
3518 1048
3519 tlmm: pinctrl@f100000 { 1049 tlmm: pinctrl@f100000 {
3520 compatible = "qcom,sm 1050 compatible = "qcom,sm8450-tlmm";
3521 reg = <0 0x0f100000 0 1051 reg = <0 0x0f100000 0 0x300000>;
3522 interrupts = <GIC_SPI 1052 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
3523 gpio-controller; 1053 gpio-controller;
3524 #gpio-cells = <2>; 1054 #gpio-cells = <2>;
3525 interrupt-controller; 1055 interrupt-controller;
3526 #interrupt-cells = <2 1056 #interrupt-cells = <2>;
3527 gpio-ranges = <&tlmm 1057 gpio-ranges = <&tlmm 0 0 211>;
3528 wakeup-parent = <&pdc 1058 wakeup-parent = <&pdc>;
3529 1059
3530 sdc2_default_state: s !! 1060 qup_i2c13_data_clk: qup-i2c13-data-clk {
3531 clk-pins { <<
3532 pins <<
3533 drive <<
3534 bias- <<
3535 }; <<
3536 <<
3537 cmd-pins { <<
3538 pins <<
3539 drive <<
3540 bias- <<
3541 }; <<
3542 <<
3543 data-pins { <<
3544 pins <<
3545 drive <<
3546 bias- <<
3547 }; <<
3548 }; <<
3549 <<
3550 sdc2_sleep_state: sdc <<
3551 clk-pins { <<
3552 pins <<
3553 drive <<
3554 bias- <<
3555 }; <<
3556 <<
3557 cmd-pins { <<
3558 pins <<
3559 drive <<
3560 bias- <<
3561 }; <<
3562 <<
3563 data-pins { <<
3564 pins <<
3565 drive <<
3566 bias- <<
3567 }; <<
3568 }; <<
3569 <<
3570 cci0_default: cci0-de <<
3571 /* SDA, SCL * <<
3572 pins = "gpio1 <<
3573 function = "c <<
3574 drive-strengt <<
3575 bias-pull-up; <<
3576 }; <<
3577 <<
3578 cci0_sleep: cci0-slee <<
3579 /* SDA, SCL * <<
3580 pins = "gpio1 <<
3581 function = "c <<
3582 drive-strengt <<
3583 bias-pull-dow <<
3584 }; <<
3585 <<
3586 cci1_default: cci1-de <<
3587 /* SDA, SCL * <<
3588 pins = "gpio1 <<
3589 function = "c <<
3590 drive-strengt <<
3591 bias-pull-up; <<
3592 }; <<
3593 <<
3594 cci1_sleep: cci1-slee <<
3595 /* SDA, SCL * <<
3596 pins = "gpio1 <<
3597 function = "c <<
3598 drive-strengt <<
3599 bias-pull-dow <<
3600 }; <<
3601 <<
3602 cci2_default: cci2-de <<
3603 /* SDA, SCL * <<
3604 pins = "gpio1 <<
3605 function = "c <<
3606 drive-strengt <<
3607 bias-pull-up; <<
3608 }; <<
3609 <<
3610 cci2_sleep: cci2-slee <<
3611 /* SDA, SCL * <<
3612 pins = "gpio1 <<
3613 function = "c <<
3614 drive-strengt <<
3615 bias-pull-dow <<
3616 }; <<
3617 <<
3618 cci3_default: cci3-de <<
3619 /* SDA, SCL * <<
3620 pins = "gpio2 <<
3621 function = "c <<
3622 drive-strengt <<
3623 bias-pull-up; <<
3624 }; <<
3625 <<
3626 cci3_sleep: cci3-slee <<
3627 /* SDA, SCL * <<
3628 pins = "gpio2 <<
3629 function = "c <<
3630 drive-strengt <<
3631 bias-pull-dow <<
3632 }; <<
3633 <<
3634 pcie0_default_state: <<
3635 perst-pins { <<
3636 pins <<
3637 funct <<
3638 drive <<
3639 bias- <<
3640 }; <<
3641 <<
3642 clkreq-pins { <<
3643 pins <<
3644 funct <<
3645 drive <<
3646 bias- <<
3647 }; <<
3648 <<
3649 wake-pins { <<
3650 pins <<
3651 funct <<
3652 drive <<
3653 bias- <<
3654 }; <<
3655 }; <<
3656 <<
3657 pcie1_default_state: <<
3658 perst-pins { <<
3659 pins <<
3660 funct <<
3661 drive <<
3662 bias- <<
3663 }; <<
3664 <<
3665 clkreq-pins { <<
3666 pins <<
3667 funct <<
3668 drive <<
3669 bias- <<
3670 }; <<
3671 <<
3672 wake-pins { <<
3673 pins <<
3674 funct <<
3675 drive <<
3676 bias- <<
3677 }; <<
3678 }; <<
3679 <<
3680 qup_i2c0_data_clk: qu <<
3681 pins = "gpio0 <<
3682 function = "q <<
3683 }; <<
3684 <<
3685 qup_i2c1_data_clk: qu <<
3686 pins = "gpio4 <<
3687 function = "q <<
3688 }; <<
3689 <<
3690 qup_i2c2_data_clk: qu <<
3691 pins = "gpio8 <<
3692 function = "q <<
3693 }; <<
3694 <<
3695 qup_i2c3_data_clk: qu <<
3696 pins = "gpio1 <<
3697 function = "q <<
3698 }; <<
3699 <<
3700 qup_i2c4_data_clk: qu <<
3701 pins = "gpio1 <<
3702 function = "q <<
3703 }; <<
3704 <<
3705 qup_i2c5_data_clk: qu <<
3706 pins = "gpio2 <<
3707 function = "q <<
3708 }; <<
3709 <<
3710 qup_i2c6_data_clk: qu <<
3711 pins = "gpio2 <<
3712 function = "q <<
3713 }; <<
3714 <<
3715 qup_i2c8_data_clk: qu <<
3716 pins = "gpio2 <<
3717 function = "q <<
3718 }; <<
3719 <<
3720 qup_i2c9_data_clk: qu <<
3721 pins = "gpio3 <<
3722 function = "q <<
3723 }; <<
3724 <<
3725 qup_i2c10_data_clk: q <<
3726 pins = "gpio3 <<
3727 function = "q <<
3728 }; <<
3729 <<
3730 qup_i2c11_data_clk: q <<
3731 pins = "gpio4 <<
3732 function = "q <<
3733 }; <<
3734 <<
3735 qup_i2c12_data_clk: q <<
3736 pins = "gpio4 <<
3737 function = "q <<
3738 }; <<
3739 <<
3740 qup_i2c13_data_clk: q <<
3741 pins = "gpio4 1061 pins = "gpio48", "gpio49";
3742 function = "q 1062 function = "qup13";
3743 drive-strengt 1063 drive-strength = <2>;
3744 bias-pull-up; 1064 bias-pull-up;
3745 }; 1065 };
3746 1066
3747 qup_i2c14_data_clk: q !! 1067 qup_i2c14_data_clk: qup-i2c14-data-clk {
3748 pins = "gpio5 1068 pins = "gpio52", "gpio53";
3749 function = "q 1069 function = "qup14";
3750 drive-strengt 1070 drive-strength = <2>;
3751 bias-pull-up; 1071 bias-pull-up;
3752 }; 1072 };
3753 1073
3754 qup_i2c15_data_clk: q !! 1074 qup_uart7_rx: qup-uart7-rx {
3755 pins = "gpio5 <<
3756 function = "q <<
3757 }; <<
3758 <<
3759 qup_i2c16_data_clk: q <<
3760 pins = "gpio6 <<
3761 function = "q <<
3762 }; <<
3763 <<
3764 qup_i2c17_data_clk: q <<
3765 pins = "gpio6 <<
3766 function = "q <<
3767 }; <<
3768 <<
3769 qup_i2c18_data_clk: q <<
3770 pins = "gpio6 <<
3771 function = "q <<
3772 }; <<
3773 <<
3774 qup_i2c19_data_clk: q <<
3775 pins = "gpio7 <<
3776 function = "q <<
3777 }; <<
3778 <<
3779 qup_i2c20_data_clk: q <<
3780 pins = "gpio7 <<
3781 function = "q <<
3782 }; <<
3783 <<
3784 qup_i2c21_data_clk: q <<
3785 pins = "gpio8 <<
3786 function = "q <<
3787 }; <<
3788 <<
3789 qup_spi0_cs: qup-spi0 <<
3790 pins = "gpio3 <<
3791 function = "q <<
3792 }; <<
3793 <<
3794 qup_spi0_data_clk: qu <<
3795 pins = "gpio0 <<
3796 function = "q <<
3797 }; <<
3798 <<
3799 qup_spi1_cs: qup-spi1 <<
3800 pins = "gpio7 <<
3801 function = "q <<
3802 }; <<
3803 <<
3804 qup_spi1_data_clk: qu <<
3805 pins = "gpio4 <<
3806 function = "q <<
3807 }; <<
3808 <<
3809 qup_spi2_cs: qup-spi2 <<
3810 pins = "gpio1 <<
3811 function = "q <<
3812 }; <<
3813 <<
3814 qup_spi2_data_clk: qu <<
3815 pins = "gpio8 <<
3816 function = "q <<
3817 }; <<
3818 <<
3819 qup_spi3_cs: qup-spi3 <<
3820 pins = "gpio1 <<
3821 function = "q <<
3822 }; <<
3823 <<
3824 qup_spi3_data_clk: qu <<
3825 pins = "gpio1 <<
3826 function = "q <<
3827 }; <<
3828 <<
3829 qup_spi4_cs: qup-spi4 <<
3830 pins = "gpio1 <<
3831 function = "q <<
3832 drive-strengt <<
3833 bias-disable; <<
3834 }; <<
3835 <<
3836 qup_spi4_data_clk: qu <<
3837 pins = "gpio1 <<
3838 function = "q <<
3839 }; <<
3840 <<
3841 qup_spi5_cs: qup-spi5 <<
3842 pins = "gpio8 <<
3843 function = "q <<
3844 }; <<
3845 <<
3846 qup_spi5_data_clk: qu <<
3847 pins = "gpio2 <<
3848 function = "q <<
3849 }; <<
3850 <<
3851 qup_spi6_cs: qup-spi6 <<
3852 pins = "gpio2 <<
3853 function = "q <<
3854 }; <<
3855 <<
3856 qup_spi6_data_clk: qu <<
3857 pins = "gpio2 <<
3858 function = "q <<
3859 }; <<
3860 <<
3861 qup_spi8_cs: qup-spi8 <<
3862 pins = "gpio3 <<
3863 function = "q <<
3864 }; <<
3865 <<
3866 qup_spi8_data_clk: qu <<
3867 pins = "gpio2 <<
3868 function = "q <<
3869 }; <<
3870 <<
3871 qup_spi9_cs: qup-spi9 <<
3872 pins = "gpio3 <<
3873 function = "q <<
3874 }; <<
3875 <<
3876 qup_spi9_data_clk: qu <<
3877 pins = "gpio3 <<
3878 function = "q <<
3879 }; <<
3880 <<
3881 qup_spi10_cs: qup-spi <<
3882 pins = "gpio3 <<
3883 function = "q <<
3884 }; <<
3885 <<
3886 qup_spi10_data_clk: q <<
3887 pins = "gpio3 <<
3888 function = "q <<
3889 }; <<
3890 <<
3891 qup_spi11_cs: qup-spi <<
3892 pins = "gpio4 <<
3893 function = "q <<
3894 }; <<
3895 <<
3896 qup_spi11_data_clk: q <<
3897 pins = "gpio4 <<
3898 function = "q <<
3899 }; <<
3900 <<
3901 qup_spi12_cs: qup-spi <<
3902 pins = "gpio4 <<
3903 function = "q <<
3904 }; <<
3905 <<
3906 qup_spi12_data_clk: q <<
3907 pins = "gpio4 <<
3908 function = "q <<
3909 }; <<
3910 <<
3911 qup_spi13_cs: qup-spi <<
3912 pins = "gpio5 <<
3913 function = "q <<
3914 }; <<
3915 <<
3916 qup_spi13_data_clk: q <<
3917 pins = "gpio4 <<
3918 function = "q <<
3919 }; <<
3920 <<
3921 qup_spi14_cs: qup-spi <<
3922 pins = "gpio5 <<
3923 function = "q <<
3924 }; <<
3925 <<
3926 qup_spi14_data_clk: q <<
3927 pins = "gpio5 <<
3928 function = "q <<
3929 }; <<
3930 <<
3931 qup_spi15_cs: qup-spi <<
3932 pins = "gpio5 <<
3933 function = "q <<
3934 }; <<
3935 <<
3936 qup_spi15_data_clk: q <<
3937 pins = "gpio5 <<
3938 function = "q <<
3939 }; <<
3940 <<
3941 qup_spi16_cs: qup-spi <<
3942 pins = "gpio6 <<
3943 function = "q <<
3944 }; <<
3945 <<
3946 qup_spi16_data_clk: q <<
3947 pins = "gpio6 <<
3948 function = "q <<
3949 }; <<
3950 <<
3951 qup_spi17_cs: qup-spi <<
3952 pins = "gpio6 <<
3953 function = "q <<
3954 }; <<
3955 <<
3956 qup_spi17_data_clk: q <<
3957 pins = "gpio6 <<
3958 function = "q <<
3959 }; <<
3960 <<
3961 qup_spi18_cs: qup-spi <<
3962 pins = "gpio7 <<
3963 function = "q <<
3964 drive-strengt <<
3965 bias-disable; <<
3966 }; <<
3967 <<
3968 qup_spi18_data_clk: q <<
3969 pins = "gpio6 <<
3970 function = "q <<
3971 drive-strengt <<
3972 bias-disable; <<
3973 }; <<
3974 <<
3975 qup_spi19_cs: qup-spi <<
3976 pins = "gpio7 <<
3977 function = "q <<
3978 drive-strengt <<
3979 bias-disable; <<
3980 }; <<
3981 <<
3982 qup_spi19_data_clk: q <<
3983 pins = "gpio7 <<
3984 function = "q <<
3985 drive-strengt <<
3986 bias-disable; <<
3987 }; <<
3988 <<
3989 qup_spi20_cs: qup-spi <<
3990 pins = "gpio7 <<
3991 function = "q <<
3992 }; <<
3993 <<
3994 qup_spi20_data_clk: q <<
3995 pins = "gpio7 <<
3996 function = "q <<
3997 }; <<
3998 <<
3999 qup_spi21_cs: qup-spi <<
4000 pins = "gpio8 <<
4001 function = "q <<
4002 }; <<
4003 <<
4004 qup_spi21_data_clk: q <<
4005 pins = "gpio8 <<
4006 function = "q <<
4007 }; <<
4008 <<
4009 qup_uart7_rx: qup-uar <<
4010 pins = "gpio2 1075 pins = "gpio26";
4011 function = "q 1076 function = "qup7";
4012 drive-strengt 1077 drive-strength = <2>;
4013 bias-disable; 1078 bias-disable;
4014 }; 1079 };
4015 1080
4016 qup_uart7_tx: qup-uar !! 1081 qup_uart7_tx: qup-uart7-tx {
4017 pins = "gpio2 1082 pins = "gpio27";
4018 function = "q 1083 function = "qup7";
4019 drive-strengt 1084 drive-strength = <2>;
4020 bias-disable; 1085 bias-disable;
4021 }; 1086 };
4022 <<
4023 qup_uart20_default: q <<
4024 pins = "gpio7 <<
4025 function = "q <<
4026 }; <<
4027 }; <<
4028 <<
4029 lpass_tlmm: pinctrl@3440000 { <<
4030 compatible = "qcom,sm <<
4031 reg = <0 0x03440000 0 <<
4032 <0 0x034d0000 0 <<
4033 gpio-controller; <<
4034 #gpio-cells = <2>; <<
4035 gpio-ranges = <&lpass <<
4036 <<
4037 clocks = <&q6prmcc LP <<
4038 <&q6prmcc LP <<
4039 clock-names = "core", <<
4040 <<
4041 tx_swr_active: tx-swr <<
4042 clk-pins { <<
4043 pins <<
4044 funct <<
4045 drive <<
4046 slew- <<
4047 bias- <<
4048 }; <<
4049 <<
4050 data-pins { <<
4051 pins <<
4052 funct <<
4053 drive <<
4054 slew- <<
4055 bias- <<
4056 }; <<
4057 }; <<
4058 <<
4059 rx_swr_active: rx-swr <<
4060 clk-pins { <<
4061 pins <<
4062 funct <<
4063 drive <<
4064 slew- <<
4065 bias- <<
4066 }; <<
4067 <<
4068 data-pins { <<
4069 pins <<
4070 funct <<
4071 drive <<
4072 slew- <<
4073 bias- <<
4074 }; <<
4075 }; <<
4076 <<
4077 dmic01_default: dmic0 <<
4078 clk-pins { <<
4079 pins <<
4080 funct <<
4081 drive <<
4082 outpu <<
4083 }; <<
4084 <<
4085 data-pins { <<
4086 pins <<
4087 funct <<
4088 drive <<
4089 }; <<
4090 }; <<
4091 <<
4092 dmic23_default: dmic2 <<
4093 clk-pins { <<
4094 pins <<
4095 funct <<
4096 drive <<
4097 outpu <<
4098 }; <<
4099 <<
4100 data-pins { <<
4101 pins <<
4102 funct <<
4103 drive <<
4104 }; <<
4105 }; <<
4106 <<
4107 wsa_swr_active: wsa-s <<
4108 clk-pins { <<
4109 pins <<
4110 funct <<
4111 drive <<
4112 slew- <<
4113 bias- <<
4114 }; <<
4115 <<
4116 data-pins { <<
4117 pins <<
4118 funct <<
4119 drive <<
4120 slew- <<
4121 bias- <<
4122 }; <<
4123 }; <<
4124 <<
4125 wsa2_swr_active: wsa2 <<
4126 clk-pins { <<
4127 pins <<
4128 funct <<
4129 drive <<
4130 slew- <<
4131 bias- <<
4132 }; <<
4133 <<
4134 data-pins { <<
4135 pins <<
4136 funct <<
4137 drive <<
4138 slew- <<
4139 bias- <<
4140 }; <<
4141 }; <<
4142 }; <<
4143 <<
4144 sram@146aa000 { <<
4145 compatible = "qcom,sm <<
4146 reg = <0 0x146aa000 0 <<
4147 ranges = <0 0 0x146aa <<
4148 <<
4149 #address-cells = <1>; <<
4150 #size-cells = <1>; <<
4151 <<
4152 pil-reloc@94c { <<
4153 compatible = <<
4154 reg = <0x94c <<
4155 }; <<
4156 }; 1087 };
4157 1088
4158 apps_smmu: iommu@15000000 { 1089 apps_smmu: iommu@15000000 {
4159 compatible = "qcom,sm 1090 compatible = "qcom,sm8450-smmu-500", "arm,mmu-500";
4160 reg = <0 0x15000000 0 1091 reg = <0 0x15000000 0 0x100000>;
4161 #iommu-cells = <2>; 1092 #iommu-cells = <2>;
4162 #global-interrupts = 1093 #global-interrupts = <1>;
4163 interrupts = <GIC_SPI !! 1094 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
4164 <GIC_SPI !! 1095 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
4165 <GIC_SPI !! 1096 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
4166 <GIC_SPI !! 1097 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
4167 <GIC_SPI !! 1098 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
4168 <GIC_SPI !! 1099 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
4169 <GIC_SPI !! 1100 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
4170 <GIC_SPI !! 1101 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
4171 <GIC_SPI !! 1102 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
4172 <GIC_SPI !! 1103 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
4173 <GIC_SPI !! 1104 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
4174 <GIC_SPI !! 1105 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
4175 <GIC_SPI !! 1106 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
4176 <GIC_SPI !! 1107 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
4177 <GIC_SPI !! 1108 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
4178 <GIC_SPI !! 1109 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
4179 <GIC_SPI !! 1110 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
4180 <GIC_SPI !! 1111 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
4181 <GIC_SPI !! 1112 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
4182 <GIC_SPI !! 1113 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
4183 <GIC_SPI !! 1114 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
4184 <GIC_SPI !! 1115 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
4185 <GIC_SPI !! 1116 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
4186 <GIC_SPI !! 1117 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
4187 <GIC_SPI !! 1118 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
4188 <GIC_SPI !! 1119 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
4189 <GIC_SPI !! 1120 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
4190 <GIC_SPI !! 1121 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
4191 <GIC_SPI !! 1122 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
4192 <GIC_SPI !! 1123 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
4193 <GIC_SPI !! 1124 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
4194 <GIC_SPI !! 1125 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
4195 <GIC_SPI !! 1126 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
4196 <GIC_SPI !! 1127 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
4197 <GIC_SPI !! 1128 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
4198 <GIC_SPI !! 1129 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
4199 <GIC_SPI !! 1130 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
4200 <GIC_SPI !! 1131 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
4201 <GIC_SPI !! 1132 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
4202 <GIC_SPI !! 1133 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
4203 <GIC_SPI !! 1134 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
4204 <GIC_SPI !! 1135 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
4205 <GIC_SPI !! 1136 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
4206 <GIC_SPI !! 1137 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
4207 <GIC_SPI !! 1138 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
4208 <GIC_SPI !! 1139 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
4209 <GIC_SPI !! 1140 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
4210 <GIC_SPI !! 1141 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
4211 <GIC_SPI !! 1142 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
4212 <GIC_SPI !! 1143 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
4213 <GIC_SPI !! 1144 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
4214 <GIC_SPI !! 1145 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
4215 <GIC_SPI !! 1146 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
4216 <GIC_SPI !! 1147 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
4217 <GIC_SPI !! 1148 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
4218 <GIC_SPI !! 1149 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
4219 <GIC_SPI !! 1150 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
4220 <GIC_SPI !! 1151 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
4221 <GIC_SPI !! 1152 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
4222 <GIC_SPI !! 1153 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
4223 <GIC_SPI !! 1154 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
4224 <GIC_SPI !! 1155 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
4225 <GIC_SPI !! 1156 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
4226 <GIC_SPI !! 1157 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
4227 <GIC_SPI !! 1158 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
4228 <GIC_SPI !! 1159 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
4229 <GIC_SPI !! 1160 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
4230 <GIC_SPI !! 1161 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
4231 <GIC_SPI !! 1162 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
4232 <GIC_SPI !! 1163 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
4233 <GIC_SPI !! 1164 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
4234 <GIC_SPI !! 1165 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
4235 <GIC_SPI !! 1166 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
4236 <GIC_SPI !! 1167 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
4237 <GIC_SPI !! 1168 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
4238 <GIC_SPI !! 1169 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
4239 <GIC_SPI !! 1170 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
4240 <GIC_SPI !! 1171 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
4241 <GIC_SPI !! 1172 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
4242 <GIC_SPI !! 1173 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
4243 <GIC_SPI !! 1174 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
4244 <GIC_SPI !! 1175 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
4245 <GIC_SPI !! 1176 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
4246 <GIC_SPI !! 1177 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
4247 <GIC_SPI !! 1178 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
4248 <GIC_SPI !! 1179 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
4249 <GIC_SPI !! 1180 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
4250 <GIC_SPI !! 1181 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
4251 <GIC_SPI !! 1182 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
4252 <GIC_SPI !! 1183 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
4253 <GIC_SPI !! 1184 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
4254 <GIC_SPI !! 1185 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
4255 <GIC_SPI !! 1186 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
4256 <GIC_SPI !! 1187 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
4257 <GIC_SPI !! 1188 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
4258 <GIC_SPI !! 1189 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
4259 <GIC_SPI !! 1190 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>;
4260 }; 1191 };
4261 1192
4262 intc: interrupt-controller@17 1193 intc: interrupt-controller@17100000 {
4263 compatible = "arm,gic 1194 compatible = "arm,gic-v3";
4264 #interrupt-cells = <3 1195 #interrupt-cells = <3>;
4265 interrupt-controller; 1196 interrupt-controller;
4266 #redistributor-region 1197 #redistributor-regions = <1>;
4267 redistributor-stride 1198 redistributor-stride = <0x0 0x40000>;
4268 reg = <0x0 0x17100000 1199 reg = <0x0 0x17100000 0x0 0x10000>, /* GICD */
4269 <0x0 0x17180000 1200 <0x0 0x17180000 0x0 0x200000>; /* GICR * 8 */
4270 interrupts = <GIC_PPI 1201 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
4271 #address-cells = <2>; <<
4272 #size-cells = <2>; <<
4273 ranges; <<
4274 <<
4275 gic_its: msi-controll <<
4276 compatible = <<
4277 reg = <0x0 0x <<
4278 msi-controlle <<
4279 #msi-cells = <<
4280 }; <<
4281 }; 1202 };
4282 1203
4283 timer@17420000 { 1204 timer@17420000 {
4284 compatible = "arm,arm 1205 compatible = "arm,armv7-timer-mem";
4285 #address-cells = <1>; 1206 #address-cells = <1>;
4286 #size-cells = <1>; 1207 #size-cells = <1>;
4287 ranges = <0 0 0 0x200 1208 ranges = <0 0 0 0x20000000>;
4288 reg = <0x0 0x17420000 1209 reg = <0x0 0x17420000 0x0 0x1000>;
4289 clock-frequency = <19 1210 clock-frequency = <19200000>;
4290 1211
4291 frame@17421000 { 1212 frame@17421000 {
4292 frame-number 1213 frame-number = <0>;
4293 interrupts = 1214 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
4294 1215 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
4295 reg = <0x1742 1216 reg = <0x17421000 0x1000>,
4296 <0x1742 1217 <0x17422000 0x1000>;
4297 }; 1218 };
4298 1219
4299 frame@17423000 { 1220 frame@17423000 {
4300 frame-number 1221 frame-number = <1>;
4301 interrupts = 1222 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
4302 reg = <0x1742 1223 reg = <0x17423000 0x1000>;
4303 status = "dis 1224 status = "disabled";
4304 }; 1225 };
4305 1226
4306 frame@17425000 { 1227 frame@17425000 {
4307 frame-number 1228 frame-number = <2>;
4308 interrupts = 1229 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
4309 reg = <0x1742 1230 reg = <0x17425000 0x1000>;
4310 status = "dis 1231 status = "disabled";
4311 }; 1232 };
4312 1233
4313 frame@17427000 { 1234 frame@17427000 {
4314 frame-number 1235 frame-number = <3>;
4315 interrupts = 1236 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
4316 reg = <0x1742 1237 reg = <0x17427000 0x1000>;
4317 status = "dis 1238 status = "disabled";
4318 }; 1239 };
4319 1240
4320 frame@17429000 { 1241 frame@17429000 {
4321 frame-number 1242 frame-number = <4>;
4322 interrupts = 1243 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
4323 reg = <0x1742 1244 reg = <0x17429000 0x1000>;
4324 status = "dis 1245 status = "disabled";
4325 }; 1246 };
4326 1247
4327 frame@1742b000 { 1248 frame@1742b000 {
4328 frame-number 1249 frame-number = <5>;
4329 interrupts = 1250 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
4330 reg = <0x1742 1251 reg = <0x1742b000 0x1000>;
4331 status = "dis 1252 status = "disabled";
4332 }; 1253 };
4333 1254
4334 frame@1742d000 { 1255 frame@1742d000 {
4335 frame-number 1256 frame-number = <6>;
4336 interrupts = 1257 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
4337 reg = <0x1742 1258 reg = <0x1742d000 0x1000>;
4338 status = "dis 1259 status = "disabled";
4339 }; 1260 };
4340 }; 1261 };
4341 1262
4342 apps_rsc: rsc@17a00000 { 1263 apps_rsc: rsc@17a00000 {
4343 label = "apps_rsc"; 1264 label = "apps_rsc";
4344 compatible = "qcom,rp 1265 compatible = "qcom,rpmh-rsc";
4345 reg = <0x0 0x17a00000 1266 reg = <0x0 0x17a00000 0x0 0x10000>,
4346 <0x0 0x17a10000 1267 <0x0 0x17a10000 0x0 0x10000>,
4347 <0x0 0x17a20000 1268 <0x0 0x17a20000 0x0 0x10000>,
4348 <0x0 0x17a30000 1269 <0x0 0x17a30000 0x0 0x10000>;
4349 reg-names = "drv-0", 1270 reg-names = "drv-0", "drv-1", "drv-2", "drv-3";
4350 interrupts = <GIC_SPI 1271 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
4351 <GIC_SPI 1272 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
4352 <GIC_SPI 1273 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
4353 qcom,tcs-offset = <0x 1274 qcom,tcs-offset = <0xd00>;
4354 qcom,drv-id = <2>; 1275 qcom,drv-id = <2>;
4355 qcom,tcs-config = <AC 1276 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
4356 <WA 1277 <WAKE_TCS 2>, <CONTROL_TCS 0>;
4357 power-domains = <&CLU <<
4358 1278
4359 apps_bcm_voter: bcm-v 1279 apps_bcm_voter: bcm-voter {
4360 compatible = 1280 compatible = "qcom,bcm-voter";
4361 }; 1281 };
4362 1282
4363 rpmhcc: clock-control 1283 rpmhcc: clock-controller {
4364 compatible = 1284 compatible = "qcom,sm8450-rpmh-clk";
4365 #clock-cells 1285 #clock-cells = <1>;
4366 clock-names = 1286 clock-names = "xo";
4367 clocks = <&xo 1287 clocks = <&xo_board>;
4368 }; 1288 };
4369 1289
4370 rpmhpd: power-control 1290 rpmhpd: power-controller {
4371 compatible = 1291 compatible = "qcom,sm8450-rpmhpd";
4372 #power-domain 1292 #power-domain-cells = <1>;
4373 operating-poi 1293 operating-points-v2 = <&rpmhpd_opp_table>;
4374 1294
4375 rpmhpd_opp_ta 1295 rpmhpd_opp_table: opp-table {
4376 compa 1296 compatible = "operating-points-v2";
4377 1297
4378 rpmhp 1298 rpmhpd_opp_ret: opp1 {
4379 1299 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4380 }; 1300 };
4381 1301
4382 rpmhp 1302 rpmhpd_opp_min_svs: opp2 {
4383 1303 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4384 }; 1304 };
4385 1305
4386 rpmhp !! 1306 rpmhpd_opp_low_svs: opp3 {
4387 <<
4388 }; <<
4389 <<
4390 rpmhp <<
4391 1307 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4392 }; 1308 };
4393 1309
4394 rpmhp !! 1310 rpmhpd_opp_svs: opp4 {
4395 <<
4396 }; <<
4397 <<
4398 rpmhp <<
4399 1311 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4400 }; 1312 };
4401 1313
4402 rpmhp !! 1314 rpmhpd_opp_svs_l1: opp5 {
4403 <<
4404 }; <<
4405 <<
4406 rpmhp <<
4407 1315 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4408 }; 1316 };
4409 1317
4410 rpmhp !! 1318 rpmhpd_opp_nom: opp6 {
4411 <<
4412 }; <<
4413 <<
4414 rpmhp <<
4415 1319 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4416 }; 1320 };
4417 1321
4418 rpmhp !! 1322 rpmhpd_opp_nom_l1: opp7 {
4419 1323 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4420 }; 1324 };
4421 1325
4422 rpmhp !! 1326 rpmhpd_opp_nom_l2: opp8 {
4423 1327 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4424 }; 1328 };
4425 1329
4426 rpmhp !! 1330 rpmhpd_opp_turbo: opp9 {
4427 1331 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4428 }; 1332 };
4429 1333
4430 rpmhp !! 1334 rpmhpd_opp_turbo_l1: opp10 {
4431 1335 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4432 }; 1336 };
4433 }; 1337 };
4434 }; 1338 };
4435 }; 1339 };
4436 1340
4437 cpufreq_hw: cpufreq@17d91000 1341 cpufreq_hw: cpufreq@17d91000 {
4438 compatible = "qcom,sm 1342 compatible = "qcom,sm8450-cpufreq-epss", "qcom,cpufreq-epss";
4439 reg = <0 0x17d91000 0 1343 reg = <0 0x17d91000 0 0x1000>,
4440 <0 0x17d92000 0 1344 <0 0x17d92000 0 0x1000>,
4441 <0 0x17d93000 0 1345 <0 0x17d93000 0 0x1000>;
4442 reg-names = "freq-dom 1346 reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
4443 clocks = <&rpmhcc RPM 1347 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
4444 clock-names = "xo", " 1348 clock-names = "xo", "alternate";
4445 interrupts = <GIC_SPI 1349 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
4446 <GIC_SPI 1350 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
4447 <GIC_SPI 1351 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
4448 interrupt-names = "dc 1352 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
4449 #freq-domain-cells = 1353 #freq-domain-cells = <1>;
4450 #clock-cells = <1>; <<
4451 }; 1354 };
4452 1355
4453 gem_noc: interconnect@1910000 1356 gem_noc: interconnect@19100000 {
4454 compatible = "qcom,sm 1357 compatible = "qcom,sm8450-gem-noc";
4455 reg = <0 0x19100000 0 1358 reg = <0 0x19100000 0 0xbb800>;
4456 #interconnect-cells = 1359 #interconnect-cells = <2>;
4457 qcom,bcm-voters = <&a 1360 qcom,bcm-voters = <&apps_bcm_voter>;
4458 }; 1361 };
4459 1362
4460 system-cache-controller@19200 1363 system-cache-controller@19200000 {
4461 compatible = "qcom,sm 1364 compatible = "qcom,sm8450-llcc";
4462 reg = <0 0x19200000 0 !! 1365 reg = <0 0x19200000 0 0x580000>, <0 0x19a00000 0 0x80000>;
4463 <0 0x19300000 0 !! 1366 reg-names = "llcc_base", "llcc_broadcast_base";
4464 <0 0x19a00000 0 <<
4465 reg-names = "llcc0_ba <<
4466 "llcc3_ba <<
4467 "llcc_bro <<
4468 interrupts = <GIC_SPI 1367 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
4469 }; 1368 };
4470 1369
4471 ufs_mem_hc: ufshc@1d84000 { 1370 ufs_mem_hc: ufshc@1d84000 {
4472 compatible = "qcom,sm 1371 compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
4473 "jedec,u 1372 "jedec,ufs-2.0";
4474 reg = <0 0x01d84000 0 1373 reg = <0 0x01d84000 0 0x3000>;
4475 interrupts = <GIC_SPI 1374 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
4476 phys = <&ufs_mem_phy> !! 1375 phys = <&ufs_mem_phy_lanes>;
4477 phy-names = "ufsphy"; 1376 phy-names = "ufsphy";
4478 lanes-per-direction = 1377 lanes-per-direction = <2>;
4479 #reset-cells = <1>; 1378 #reset-cells = <1>;
4480 resets = <&gcc GCC_UF 1379 resets = <&gcc GCC_UFS_PHY_BCR>;
4481 reset-names = "rst"; 1380 reset-names = "rst";
4482 1381
4483 power-domains = <&gcc 1382 power-domains = <&gcc UFS_PHY_GDSC>;
4484 1383
4485 iommus = <&apps_smmu 1384 iommus = <&apps_smmu 0xe0 0x0>;
4486 dma-coherent; <<
4487 1385
4488 interconnects = <&agg 1386 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>,
4489 <&gem 1387 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
4490 interconnect-names = 1388 interconnect-names = "ufs-ddr", "cpu-ufs";
4491 clock-names = 1389 clock-names =
4492 "core_clk", 1390 "core_clk",
4493 "bus_aggr_clk 1391 "bus_aggr_clk",
4494 "iface_clk", 1392 "iface_clk",
4495 "core_clk_uni 1393 "core_clk_unipro",
4496 "ref_clk", 1394 "ref_clk",
4497 "tx_lane0_syn 1395 "tx_lane0_sync_clk",
4498 "rx_lane0_syn 1396 "rx_lane0_sync_clk",
4499 "rx_lane1_syn 1397 "rx_lane1_sync_clk";
4500 clocks = 1398 clocks =
4501 <&gcc GCC_UFS 1399 <&gcc GCC_UFS_PHY_AXI_CLK>,
4502 <&gcc GCC_AGG 1400 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
4503 <&gcc GCC_UFS 1401 <&gcc GCC_UFS_PHY_AHB_CLK>,
4504 <&gcc GCC_UFS 1402 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
4505 <&rpmhcc RPMH 1403 <&rpmhcc RPMH_CXO_CLK>,
4506 <&gcc GCC_UFS 1404 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
4507 <&gcc GCC_UFS 1405 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
4508 <&gcc GCC_UFS 1406 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
4509 freq-table-hz = 1407 freq-table-hz =
4510 <75000000 300 1408 <75000000 300000000>,
4511 <0 0>, 1409 <0 0>,
4512 <0 0>, 1410 <0 0>,
4513 <75000000 300 1411 <75000000 300000000>,
4514 <75000000 300 1412 <75000000 300000000>,
4515 <0 0>, 1413 <0 0>,
4516 <0 0>, 1414 <0 0>,
4517 <0 0>; 1415 <0 0>;
4518 qcom,ice = <&ice>; <<
4519 <<
4520 status = "disabled"; 1416 status = "disabled";
4521 }; 1417 };
4522 1418
4523 ufs_mem_phy: phy@1d87000 { 1419 ufs_mem_phy: phy@1d87000 {
4524 compatible = "qcom,sm 1420 compatible = "qcom,sm8450-qmp-ufs-phy";
4525 reg = <0 0x01d87000 0 !! 1421 reg = <0 0x01d87000 0 0xe10>;
4526 !! 1422 #address-cells = <2>;
>> 1423 #size-cells = <2>;
>> 1424 ranges;
4527 clock-names = "ref", 1425 clock-names = "ref", "ref_aux", "qref";
4528 clocks = <&rpmhcc RPM 1426 clocks = <&rpmhcc RPMH_CXO_CLK>,
4529 <&gcc GCC_UF 1427 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
4530 <&gcc GCC_UF 1428 <&gcc GCC_UFS_0_CLKREF_EN>;
4531 1429
4532 power-domains = <&gcc <<
4533 <<
4534 resets = <&ufs_mem_hc 1430 resets = <&ufs_mem_hc 0>;
4535 reset-names = "ufsphy 1431 reset-names = "ufsphy";
4536 <<
4537 #clock-cells = <1>; <<
4538 #phy-cells = <0>; <<
4539 <<
4540 status = "disabled"; 1432 status = "disabled";
4541 }; <<
4542 1433
4543 ice: crypto@1d88000 { !! 1434 ufs_mem_phy_lanes: lanes@1d87400 {
4544 compatible = "qcom,sm !! 1435 reg = <0 0x01d87400 0 0x108>,
4545 "qcom,in !! 1436 <0 0x01d87600 0 0x1e0>,
4546 reg = <0 0x01d88000 0 !! 1437 <0 0x01d87c00 0 0x1dc>,
4547 clocks = <&gcc GCC_UF !! 1438 <0 0x01d87800 0 0x108>,
4548 }; !! 1439 <0 0x01d87a00 0 0x1e0>;
4549 !! 1440 #phy-cells = <0>;
4550 cryptobam: dma-controller@1dc !! 1441 #clock-cells = <0>;
4551 compatible = "qcom,ba <<
4552 reg = <0 0x01dc4000 0 <<
4553 interrupts = <GIC_SPI <<
4554 #dma-cells = <1>; <<
4555 qcom,ee = <0>; <<
4556 qcom,controlled-remot <<
4557 iommus = <&apps_smmu <<
4558 <&apps_smmu <<
4559 <&apps_smmu <<
4560 <&apps_smmu <<
4561 <&apps_smmu <<
4562 }; <<
4563 <<
4564 crypto: crypto@1dfa000 { <<
4565 compatible = "qcom,sm <<
4566 reg = <0 0x01dfa000 0 <<
4567 dmas = <&cryptobam 4> <<
4568 dma-names = "rx", "tx <<
4569 iommus = <&apps_smmu <<
4570 <&apps_smmu <<
4571 <&apps_smmu <<
4572 <&apps_smmu <<
4573 <&apps_smmu <<
4574 interconnects = <&agg <<
4575 interconnect-names = <<
4576 }; <<
4577 <<
4578 sdhc_2: mmc@8804000 { <<
4579 compatible = "qcom,sm <<
4580 reg = <0 0x08804000 0 <<
4581 <<
4582 interrupts = <GIC_SPI <<
4583 <GIC_SPI <<
4584 interrupt-names = "hc <<
4585 <<
4586 clocks = <&gcc GCC_SD <<
4587 <&gcc GCC_SD <<
4588 <&rpmhcc RPM <<
4589 clock-names = "iface" <<
4590 resets = <&gcc GCC_SD <<
4591 interconnects = <&agg <<
4592 <&gem <<
4593 interconnect-names = <<
4594 iommus = <&apps_smmu <<
4595 power-domains = <&rpm <<
4596 operating-points-v2 = <<
4597 bus-width = <4>; <<
4598 dma-coherent; <<
4599 <<
4600 /* Forbid SDR104/SDR5 <<
4601 sdhci-caps-mask = <0x <<
4602 <<
4603 status = "disabled"; <<
4604 <<
4605 sdhc2_opp_table: opp- <<
4606 compatible = <<
4607 <<
4608 opp-100000000 <<
4609 opp-h <<
4610 requi <<
4611 }; <<
4612 <<
4613 opp-202000000 <<
4614 opp-h <<
4615 requi <<
4616 }; <<
4617 }; 1442 };
4618 }; 1443 };
4619 1444
4620 usb_1: usb@a6f8800 { 1445 usb_1: usb@a6f8800 {
4621 compatible = "qcom,sm 1446 compatible = "qcom,sm8450-dwc3", "qcom,dwc3";
4622 reg = <0 0x0a6f8800 0 1447 reg = <0 0x0a6f8800 0 0x400>;
4623 status = "disabled"; 1448 status = "disabled";
4624 #address-cells = <2>; 1449 #address-cells = <2>;
4625 #size-cells = <2>; 1450 #size-cells = <2>;
4626 ranges; 1451 ranges;
4627 1452
4628 clocks = <&gcc GCC_CF 1453 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
4629 <&gcc GCC_US 1454 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
4630 <&gcc GCC_AG 1455 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
4631 <&gcc GCC_US <<
4632 <&gcc GCC_US 1456 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
>> 1457 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
4633 <&gcc GCC_US 1458 <&gcc GCC_USB3_0_CLKREF_EN>;
4634 clock-names = "cfg_no !! 1459 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
4635 "core", !! 1460 "sleep", "xo";
4636 "iface" <<
4637 "sleep" <<
4638 "mock_u <<
4639 "xo"; <<
4640 1461
4641 assigned-clocks = <&g 1462 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4642 <&g 1463 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
4643 assigned-clock-rates 1464 assigned-clock-rates = <19200000>, <200000000>;
4644 1465
4645 interrupts-extended = 1466 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
4646 <<
4647 1467 <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
4648 1468 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
4649 1469 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
4650 interrupt-names = "pw !! 1470 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
4651 "hs !! 1471 "dm_hs_phy_irq", "ss_phy_irq";
4652 "dp <<
4653 "dm <<
4654 "ss <<
4655 1472
4656 power-domains = <&gcc 1473 power-domains = <&gcc USB30_PRIM_GDSC>;
4657 1474
4658 resets = <&gcc GCC_US 1475 resets = <&gcc GCC_USB30_PRIM_BCR>;
4659 1476
4660 interconnects = <&agg <<
4661 <&gem <<
4662 interconnect-names = <<
4663 <<
4664 usb_1_dwc3: usb@a6000 1477 usb_1_dwc3: usb@a600000 {
4665 compatible = 1478 compatible = "snps,dwc3";
4666 reg = <0 0x0a 1479 reg = <0 0x0a600000 0 0xcd00>;
4667 interrupts = 1480 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
4668 iommus = <&ap 1481 iommus = <&apps_smmu 0x0 0x0>;
4669 snps,dis_u2_s 1482 snps,dis_u2_susphy_quirk;
4670 snps,dis_enbl 1483 snps,dis_enblslpm_quirk;
4671 phys = <&usb_ !! 1484 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
4672 phy-names = " 1485 phy-names = "usb2-phy", "usb3-phy";
4673 <<
4674 ports { <<
4675 #addr <<
4676 #size <<
4677 <<
4678 port@ <<
4679 <<
4680 <<
4681 <<
4682 <<
4683 }; <<
4684 <<
4685 port@ <<
4686 <<
4687 <<
4688 <<
4689 <<
4690 <<
4691 }; <<
4692 }; <<
4693 }; 1486 };
4694 }; 1487 };
4695 1488
4696 nsp_noc: interconnect@320c000 1489 nsp_noc: interconnect@320c0000 {
4697 compatible = "qcom,sm 1490 compatible = "qcom,sm8450-nsp-noc";
4698 reg = <0 0x320c0000 0 1491 reg = <0 0x320c0000 0 0x10000>;
4699 #interconnect-cells = 1492 #interconnect-cells = <2>;
4700 qcom,bcm-voters = <&a 1493 qcom,bcm-voters = <&apps_bcm_voter>;
4701 }; 1494 };
4702 1495
4703 lpass_ag_noc: interconnect@3c 1496 lpass_ag_noc: interconnect@3c40000 {
4704 compatible = "qcom,sm 1497 compatible = "qcom,sm8450-lpass-ag-noc";
4705 reg = <0 0x03c40000 0 !! 1498 reg = <0 0x3c40000 0 0x17200>;
4706 #interconnect-cells = 1499 #interconnect-cells = <2>;
4707 qcom,bcm-voters = <&a 1500 qcom,bcm-voters = <&apps_bcm_voter>;
4708 }; <<
4709 }; <<
4710 <<
4711 sound: sound { <<
4712 }; <<
4713 <<
4714 thermal-zones { <<
4715 aoss0-thermal { <<
4716 thermal-sensors = <&t <<
4717 <<
4718 trips { <<
4719 thermal-engin <<
4720 tempe <<
4721 hyste <<
4722 type <<
4723 }; <<
4724 <<
4725 reset-mon-cfg <<
4726 tempe <<
4727 hyste <<
4728 type <<
4729 }; <<
4730 }; <<
4731 }; <<
4732 <<
4733 cpuss0-thermal { <<
4734 thermal-sensors = <&t <<
4735 <<
4736 trips { <<
4737 thermal-engin <<
4738 tempe <<
4739 hyste <<
4740 type <<
4741 }; <<
4742 <<
4743 reset-mon-cfg <<
4744 tempe <<
4745 hyste <<
4746 type <<
4747 }; <<
4748 }; <<
4749 }; <<
4750 <<
4751 cpuss1-thermal { <<
4752 thermal-sensors = <&t <<
4753 <<
4754 trips { <<
4755 thermal-engin <<
4756 tempe <<
4757 hyste <<
4758 type <<
4759 }; <<
4760 <<
4761 reset-mon-cfg <<
4762 tempe <<
4763 hyste <<
4764 type <<
4765 }; <<
4766 }; <<
4767 }; <<
4768 <<
4769 cpuss3-thermal { <<
4770 thermal-sensors = <&t <<
4771 <<
4772 trips { <<
4773 thermal-engin <<
4774 tempe <<
4775 hyste <<
4776 type <<
4777 }; <<
4778 <<
4779 reset-mon-cfg <<
4780 tempe <<
4781 hyste <<
4782 type <<
4783 }; <<
4784 }; <<
4785 }; <<
4786 <<
4787 cpuss4-thermal { <<
4788 thermal-sensors = <&t <<
4789 <<
4790 trips { <<
4791 thermal-engin <<
4792 tempe <<
4793 hyste <<
4794 type <<
4795 }; <<
4796 <<
4797 reset-mon-cfg <<
4798 tempe <<
4799 hyste <<
4800 type <<
4801 }; <<
4802 }; <<
4803 }; <<
4804 <<
4805 cpu4-top-thermal { <<
4806 thermal-sensors = <&t <<
4807 <<
4808 trips { <<
4809 cpu4_top_aler <<
4810 tempe <<
4811 hyste <<
4812 type <<
4813 }; <<
4814 <<
4815 cpu4_top_aler <<
4816 tempe <<
4817 hyste <<
4818 type <<
4819 }; <<
4820 <<
4821 cpu4_top_crit <<
4822 tempe <<
4823 hyste <<
4824 type <<
4825 }; <<
4826 }; <<
4827 }; <<
4828 <<
4829 cpu4-bottom-thermal { <<
4830 thermal-sensors = <&t <<
4831 <<
4832 trips { <<
4833 cpu4_bottom_a <<
4834 tempe <<
4835 hyste <<
4836 type <<
4837 }; <<
4838 <<
4839 cpu4_bottom_a <<
4840 tempe <<
4841 hyste <<
4842 type <<
4843 }; <<
4844 <<
4845 cpu4_bottom_c <<
4846 tempe <<
4847 hyste <<
4848 type <<
4849 }; <<
4850 }; <<
4851 }; <<
4852 <<
4853 cpu5-top-thermal { <<
4854 thermal-sensors = <&t <<
4855 <<
4856 trips { <<
4857 cpu5_top_aler <<
4858 tempe <<
4859 hyste <<
4860 type <<
4861 }; <<
4862 <<
4863 cpu5_top_aler <<
4864 tempe <<
4865 hyste <<
4866 type <<
4867 }; <<
4868 <<
4869 cpu5_top_crit <<
4870 tempe <<
4871 hyste <<
4872 type <<
4873 }; <<
4874 }; <<
4875 }; <<
4876 <<
4877 cpu5-bottom-thermal { <<
4878 thermal-sensors = <&t <<
4879 <<
4880 trips { <<
4881 cpu5_bottom_a <<
4882 tempe <<
4883 hyste <<
4884 type <<
4885 }; <<
4886 <<
4887 cpu5_bottom_a <<
4888 tempe <<
4889 hyste <<
4890 type <<
4891 }; <<
4892 <<
4893 cpu5_bottom_c <<
4894 tempe <<
4895 hyste <<
4896 type <<
4897 }; <<
4898 }; <<
4899 }; <<
4900 <<
4901 cpu6-top-thermal { <<
4902 thermal-sensors = <&t <<
4903 <<
4904 trips { <<
4905 cpu6_top_aler <<
4906 tempe <<
4907 hyste <<
4908 type <<
4909 }; <<
4910 <<
4911 cpu6_top_aler <<
4912 tempe <<
4913 hyste <<
4914 type <<
4915 }; <<
4916 <<
4917 cpu6_top_crit <<
4918 tempe <<
4919 hyste <<
4920 type <<
4921 }; <<
4922 }; <<
4923 }; <<
4924 <<
4925 cpu6-bottom-thermal { <<
4926 thermal-sensors = <&t <<
4927 <<
4928 trips { <<
4929 cpu6_bottom_a <<
4930 tempe <<
4931 hyste <<
4932 type <<
4933 }; <<
4934 <<
4935 cpu6_bottom_a <<
4936 tempe <<
4937 hyste <<
4938 type <<
4939 }; <<
4940 <<
4941 cpu6_bottom_c <<
4942 tempe <<
4943 hyste <<
4944 type <<
4945 }; <<
4946 }; <<
4947 }; <<
4948 <<
4949 cpu7-top-thermal { <<
4950 thermal-sensors = <&t <<
4951 <<
4952 trips { <<
4953 cpu7_top_aler <<
4954 tempe <<
4955 hyste <<
4956 type <<
4957 }; <<
4958 <<
4959 cpu7_top_aler <<
4960 tempe <<
4961 hyste <<
4962 type <<
4963 }; <<
4964 <<
4965 cpu7_top_crit <<
4966 tempe <<
4967 hyste <<
4968 type <<
4969 }; <<
4970 }; <<
4971 }; <<
4972 <<
4973 cpu7-middle-thermal { <<
4974 thermal-sensors = <&t <<
4975 <<
4976 trips { <<
4977 cpu7_middle_a <<
4978 tempe <<
4979 hyste <<
4980 type <<
4981 }; <<
4982 <<
4983 cpu7_middle_a <<
4984 tempe <<
4985 hyste <<
4986 type <<
4987 }; <<
4988 <<
4989 cpu7_middle_c <<
4990 tempe <<
4991 hyste <<
4992 type <<
4993 }; <<
4994 }; <<
4995 }; <<
4996 <<
4997 cpu7-bottom-thermal { <<
4998 thermal-sensors = <&t <<
4999 <<
5000 trips { <<
5001 cpu7_bottom_a <<
5002 tempe <<
5003 hyste <<
5004 type <<
5005 }; <<
5006 <<
5007 cpu7_bottom_a <<
5008 tempe <<
5009 hyste <<
5010 type <<
5011 }; <<
5012 <<
5013 cpu7_bottom_c <<
5014 tempe <<
5015 hyste <<
5016 type <<
5017 }; <<
5018 }; <<
5019 }; <<
5020 <<
5021 gpu-top-thermal { <<
5022 polling-delay-passive <<
5023 <<
5024 thermal-sensors = <&t <<
5025 <<
5026 cooling-maps { <<
5027 map0 { <<
5028 trip <<
5029 cooli <<
5030 }; <<
5031 }; <<
5032 <<
5033 trips { <<
5034 gpu_top_alert <<
5035 tempe <<
5036 hyste <<
5037 type <<
5038 }; <<
5039 <<
5040 trip-point1 { <<
5041 tempe <<
5042 hyste <<
5043 type <<
5044 }; <<
5045 <<
5046 trip-point2 { <<
5047 tempe <<
5048 hyste <<
5049 type <<
5050 }; <<
5051 }; <<
5052 }; <<
5053 <<
5054 gpu-bottom-thermal { <<
5055 polling-delay-passive <<
5056 <<
5057 thermal-sensors = <&t <<
5058 <<
5059 cooling-maps { <<
5060 map0 { <<
5061 trip <<
5062 cooli <<
5063 }; <<
5064 }; <<
5065 <<
5066 trips { <<
5067 gpu_bottom_al <<
5068 tempe <<
5069 hyste <<
5070 type <<
5071 }; <<
5072 <<
5073 trip-point1 { <<
5074 tempe <<
5075 hyste <<
5076 type <<
5077 }; <<
5078 <<
5079 trip-point2 { <<
5080 tempe <<
5081 hyste <<
5082 type <<
5083 }; <<
5084 }; <<
5085 }; <<
5086 <<
5087 aoss1-thermal { <<
5088 thermal-sensors = <&t <<
5089 <<
5090 trips { <<
5091 thermal-engin <<
5092 tempe <<
5093 hyste <<
5094 type <<
5095 }; <<
5096 <<
5097 reset-mon-cfg <<
5098 tempe <<
5099 hyste <<
5100 type <<
5101 }; <<
5102 }; <<
5103 }; <<
5104 <<
5105 cpu0-thermal { <<
5106 thermal-sensors = <&t <<
5107 <<
5108 trips { <<
5109 cpu0_alert0: <<
5110 tempe <<
5111 hyste <<
5112 type <<
5113 }; <<
5114 <<
5115 cpu0_alert1: <<
5116 tempe <<
5117 hyste <<
5118 type <<
5119 }; <<
5120 <<
5121 cpu0_crit: cp <<
5122 tempe <<
5123 hyste <<
5124 type <<
5125 }; <<
5126 }; <<
5127 }; <<
5128 <<
5129 cpu1-thermal { <<
5130 thermal-sensors = <&t <<
5131 <<
5132 trips { <<
5133 cpu1_alert0: <<
5134 tempe <<
5135 hyste <<
5136 type <<
5137 }; <<
5138 <<
5139 cpu1_alert1: <<
5140 tempe <<
5141 hyste <<
5142 type <<
5143 }; <<
5144 <<
5145 cpu1_crit: cp <<
5146 tempe <<
5147 hyste <<
5148 type <<
5149 }; <<
5150 }; <<
5151 }; <<
5152 <<
5153 cpu2-thermal { <<
5154 thermal-sensors = <&t <<
5155 <<
5156 trips { <<
5157 cpu2_alert0: <<
5158 tempe <<
5159 hyste <<
5160 type <<
5161 }; <<
5162 <<
5163 cpu2_alert1: <<
5164 tempe <<
5165 hyste <<
5166 type <<
5167 }; <<
5168 <<
5169 cpu2_crit: cp <<
5170 tempe <<
5171 hyste <<
5172 type <<
5173 }; <<
5174 }; <<
5175 }; <<
5176 <<
5177 cpu3-thermal { <<
5178 thermal-sensors = <&t <<
5179 <<
5180 trips { <<
5181 cpu3_alert0: <<
5182 tempe <<
5183 hyste <<
5184 type <<
5185 }; <<
5186 <<
5187 cpu3_alert1: <<
5188 tempe <<
5189 hyste <<
5190 type <<
5191 }; <<
5192 <<
5193 cpu3_crit: cp <<
5194 tempe <<
5195 hyste <<
5196 type <<
5197 }; <<
5198 }; <<
5199 }; <<
5200 <<
5201 cdsp0-thermal { <<
5202 polling-delay-passive <<
5203 <<
5204 thermal-sensors = <&t <<
5205 <<
5206 trips { <<
5207 thermal-engin <<
5208 tempe <<
5209 hyste <<
5210 type <<
5211 }; <<
5212 <<
5213 thermal-hal-c <<
5214 tempe <<
5215 hyste <<
5216 type <<
5217 }; <<
5218 <<
5219 reset-mon-cfg <<
5220 tempe <<
5221 hyste <<
5222 type <<
5223 }; <<
5224 <<
5225 cdsp_0_config <<
5226 tempe <<
5227 hyste <<
5228 type <<
5229 }; <<
5230 }; <<
5231 }; <<
5232 <<
5233 cdsp1-thermal { <<
5234 polling-delay-passive <<
5235 <<
5236 thermal-sensors = <&t <<
5237 <<
5238 trips { <<
5239 thermal-engin <<
5240 tempe <<
5241 hyste <<
5242 type <<
5243 }; <<
5244 <<
5245 thermal-hal-c <<
5246 tempe <<
5247 hyste <<
5248 type <<
5249 }; <<
5250 <<
5251 reset-mon-cfg <<
5252 tempe <<
5253 hyste <<
5254 type <<
5255 }; <<
5256 <<
5257 cdsp_1_config <<
5258 tempe <<
5259 hyste <<
5260 type <<
5261 }; <<
5262 }; <<
5263 }; <<
5264 <<
5265 cdsp2-thermal { <<
5266 polling-delay-passive <<
5267 <<
5268 thermal-sensors = <&t <<
5269 <<
5270 trips { <<
5271 thermal-engin <<
5272 tempe <<
5273 hyste <<
5274 type <<
5275 }; <<
5276 <<
5277 thermal-hal-c <<
5278 tempe <<
5279 hyste <<
5280 type <<
5281 }; <<
5282 <<
5283 reset-mon-cfg <<
5284 tempe <<
5285 hyste <<
5286 type <<
5287 }; <<
5288 <<
5289 cdsp_2_config <<
5290 tempe <<
5291 hyste <<
5292 type <<
5293 }; <<
5294 }; <<
5295 }; <<
5296 <<
5297 video-thermal { <<
5298 thermal-sensors = <&t <<
5299 <<
5300 trips { <<
5301 thermal-engin <<
5302 tempe <<
5303 hyste <<
5304 type <<
5305 }; <<
5306 <<
5307 reset-mon-cfg <<
5308 tempe <<
5309 hyste <<
5310 type <<
5311 }; <<
5312 }; <<
5313 }; <<
5314 <<
5315 mem-thermal { <<
5316 polling-delay-passive <<
5317 <<
5318 thermal-sensors = <&t <<
5319 <<
5320 trips { <<
5321 thermal-engin <<
5322 tempe <<
5323 hyste <<
5324 type <<
5325 }; <<
5326 <<
5327 ddr_config0: <<
5328 tempe <<
5329 hyste <<
5330 type <<
5331 }; <<
5332 <<
5333 reset-mon-cfg <<
5334 tempe <<
5335 hyste <<
5336 type <<
5337 }; <<
5338 }; <<
5339 }; <<
5340 <<
5341 modem0-thermal { <<
5342 thermal-sensors = <&t <<
5343 <<
5344 trips { <<
5345 thermal-engin <<
5346 tempe <<
5347 hyste <<
5348 type <<
5349 }; <<
5350 <<
5351 mdmss0_config <<
5352 tempe <<
5353 hyste <<
5354 type <<
5355 }; <<
5356 <<
5357 mdmss0_config <<
5358 tempe <<
5359 hyste <<
5360 type <<
5361 }; <<
5362 <<
5363 reset-mon-cfg <<
5364 tempe <<
5365 hyste <<
5366 type <<
5367 }; <<
5368 }; <<
5369 }; <<
5370 <<
5371 modem1-thermal { <<
5372 thermal-sensors = <&t <<
5373 <<
5374 trips { <<
5375 thermal-engin <<
5376 tempe <<
5377 hyste <<
5378 type <<
5379 }; <<
5380 <<
5381 mdmss1_config <<
5382 tempe <<
5383 hyste <<
5384 type <<
5385 }; <<
5386 <<
5387 mdmss1_config <<
5388 tempe <<
5389 hyste <<
5390 type <<
5391 }; <<
5392 <<
5393 reset-mon-cfg <<
5394 tempe <<
5395 hyste <<
5396 type <<
5397 }; <<
5398 }; <<
5399 }; <<
5400 <<
5401 modem2-thermal { <<
5402 thermal-sensors = <&t <<
5403 <<
5404 trips { <<
5405 thermal-engin <<
5406 tempe <<
5407 hyste <<
5408 type <<
5409 }; <<
5410 <<
5411 mdmss2_config <<
5412 tempe <<
5413 hyste <<
5414 type <<
5415 }; <<
5416 <<
5417 mdmss2_config <<
5418 tempe <<
5419 hyste <<
5420 type <<
5421 }; <<
5422 <<
5423 reset-mon-cfg <<
5424 tempe <<
5425 hyste <<
5426 type <<
5427 }; <<
5428 }; <<
5429 }; <<
5430 <<
5431 modem3-thermal { <<
5432 thermal-sensors = <&t <<
5433 <<
5434 trips { <<
5435 thermal-engin <<
5436 tempe <<
5437 hyste <<
5438 type <<
5439 }; <<
5440 <<
5441 mdmss3_config <<
5442 tempe <<
5443 hyste <<
5444 type <<
5445 }; <<
5446 <<
5447 mdmss3_config <<
5448 tempe <<
5449 hyste <<
5450 type <<
5451 }; <<
5452 <<
5453 reset-mon-cfg <<
5454 tempe <<
5455 hyste <<
5456 type <<
5457 }; <<
5458 }; <<
5459 }; <<
5460 <<
5461 camera0-thermal { <<
5462 thermal-sensors = <&t <<
5463 <<
5464 trips { <<
5465 thermal-engin <<
5466 tempe <<
5467 hyste <<
5468 type <<
5469 }; <<
5470 <<
5471 reset-mon-cfg <<
5472 tempe <<
5473 hyste <<
5474 type <<
5475 }; <<
5476 }; <<
5477 }; <<
5478 <<
5479 camera1-thermal { <<
5480 thermal-sensors = <&t <<
5481 <<
5482 trips { <<
5483 thermal-engin <<
5484 tempe <<
5485 hyste <<
5486 type <<
5487 }; <<
5488 <<
5489 reset-mon-cfg <<
5490 tempe <<
5491 hyste <<
5492 type <<
5493 }; <<
5494 }; <<
5495 }; 1501 };
5496 }; 1502 };
5497 1503
5498 timer { 1504 timer {
5499 compatible = "arm,armv8-timer 1505 compatible = "arm,armv8-timer";
5500 interrupts = <GIC_PPI 13 (GIC 1506 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5501 <GIC_PPI 14 (GIC 1507 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5502 <GIC_PPI 11 (GIC 1508 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5503 <GIC_PPI 10 (GIC 1509 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
5504 clock-frequency = <19200000>; 1510 clock-frequency = <19200000>;
5505 }; 1511 };
5506 }; 1512 };
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