1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * Copyright (c) 2021, Linaro Limited 3 * Copyright (c) 2021, Linaro Limited
4 */ 4 */
5 5
6 #include <dt-bindings/interrupt-controller/arm 6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-sm8450.h> 7 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
8 #include <dt-bindings/clock/qcom,rpmh.h> 8 #include <dt-bindings/clock/qcom,rpmh.h>
9 #include <dt-bindings/clock/qcom,sm8450-camcc. <<
10 #include <dt-bindings/clock/qcom,sm8450-dispcc <<
11 #include <dt-bindings/clock/qcom,sm8450-gpucc. <<
12 #include <dt-bindings/clock/qcom,sm8450-videoc <<
13 #include <dt-bindings/dma/qcom-gpi.h> 9 #include <dt-bindings/dma/qcom-gpi.h>
14 #include <dt-bindings/firmware/qcom,scm.h> <<
15 #include <dt-bindings/gpio/gpio.h> 10 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/mailbox/qcom-ipcc.h> 11 #include <dt-bindings/mailbox/qcom-ipcc.h>
17 #include <dt-bindings/phy/phy-qcom-qmp.h> <<
18 #include <dt-bindings/power/qcom,rpmhpd.h> <<
19 #include <dt-bindings/power/qcom-rpmpd.h> 12 #include <dt-bindings/power/qcom-rpmpd.h>
20 #include <dt-bindings/interconnect/qcom,icc.h> <<
21 #include <dt-bindings/interconnect/qcom,sm8450 13 #include <dt-bindings/interconnect/qcom,sm8450.h>
22 #include <dt-bindings/reset/qcom,sm8450-gpucc. <<
23 #include <dt-bindings/soc/qcom,gpr.h> <<
24 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 14 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
25 #include <dt-bindings/sound/qcom,q6dsp-lpass-p <<
26 #include <dt-bindings/thermal/thermal.h> 15 #include <dt-bindings/thermal/thermal.h>
27 16
28 / { 17 / {
29 interrupt-parent = <&intc>; 18 interrupt-parent = <&intc>;
30 19
31 #address-cells = <2>; 20 #address-cells = <2>;
32 #size-cells = <2>; 21 #size-cells = <2>;
33 22
34 chosen { }; 23 chosen { };
35 24
36 clocks { 25 clocks {
37 xo_board: xo-board { 26 xo_board: xo-board {
38 compatible = "fixed-cl 27 compatible = "fixed-clock";
39 #clock-cells = <0>; 28 #clock-cells = <0>;
40 clock-frequency = <768 29 clock-frequency = <76800000>;
41 }; 30 };
42 31
43 sleep_clk: sleep-clk { 32 sleep_clk: sleep-clk {
44 compatible = "fixed-cl 33 compatible = "fixed-clock";
45 #clock-cells = <0>; 34 #clock-cells = <0>;
46 clock-frequency = <320 35 clock-frequency = <32000>;
47 }; 36 };
48 }; 37 };
49 38
50 cpus { 39 cpus {
51 #address-cells = <2>; 40 #address-cells = <2>;
52 #size-cells = <0>; 41 #size-cells = <0>;
53 42
54 CPU0: cpu@0 { 43 CPU0: cpu@0 {
55 device_type = "cpu"; 44 device_type = "cpu";
56 compatible = "qcom,kry 45 compatible = "qcom,kryo780";
57 reg = <0x0 0x0>; 46 reg = <0x0 0x0>;
58 enable-method = "psci" 47 enable-method = "psci";
59 next-level-cache = <&L 48 next-level-cache = <&L2_0>;
60 power-domains = <&CPU_ 49 power-domains = <&CPU_PD0>;
61 power-domain-names = " 50 power-domain-names = "psci";
62 qcom,freq-domain = <&c 51 qcom,freq-domain = <&cpufreq_hw 0>;
63 #cooling-cells = <2>; 52 #cooling-cells = <2>;
64 clocks = <&cpufreq_hw <<
65 L2_0: l2-cache { 53 L2_0: l2-cache {
66 compatible = " !! 54 compatible = "cache";
67 cache-level = !! 55 next-level-cache = <&L3_0>;
68 cache-unified; <<
69 next-level-cac <<
70 L3_0: l3-cache 56 L3_0: l3-cache {
71 compat !! 57 compatible = "cache";
72 cache- <<
73 cache- <<
74 }; 58 };
75 }; 59 };
76 }; 60 };
77 61
78 CPU1: cpu@100 { 62 CPU1: cpu@100 {
79 device_type = "cpu"; 63 device_type = "cpu";
80 compatible = "qcom,kry 64 compatible = "qcom,kryo780";
81 reg = <0x0 0x100>; 65 reg = <0x0 0x100>;
82 enable-method = "psci" 66 enable-method = "psci";
83 next-level-cache = <&L 67 next-level-cache = <&L2_100>;
84 power-domains = <&CPU_ 68 power-domains = <&CPU_PD1>;
85 power-domain-names = " 69 power-domain-names = "psci";
86 qcom,freq-domain = <&c 70 qcom,freq-domain = <&cpufreq_hw 0>;
87 #cooling-cells = <2>; 71 #cooling-cells = <2>;
88 clocks = <&cpufreq_hw <<
89 L2_100: l2-cache { 72 L2_100: l2-cache {
90 compatible = " !! 73 compatible = "cache";
91 cache-level = !! 74 next-level-cache = <&L3_0>;
92 cache-unified; <<
93 next-level-cac <<
94 }; 75 };
95 }; 76 };
96 77
97 CPU2: cpu@200 { 78 CPU2: cpu@200 {
98 device_type = "cpu"; 79 device_type = "cpu";
99 compatible = "qcom,kry 80 compatible = "qcom,kryo780";
100 reg = <0x0 0x200>; 81 reg = <0x0 0x200>;
101 enable-method = "psci" 82 enable-method = "psci";
102 next-level-cache = <&L 83 next-level-cache = <&L2_200>;
103 power-domains = <&CPU_ 84 power-domains = <&CPU_PD2>;
104 power-domain-names = " 85 power-domain-names = "psci";
105 qcom,freq-domain = <&c 86 qcom,freq-domain = <&cpufreq_hw 0>;
106 #cooling-cells = <2>; 87 #cooling-cells = <2>;
107 clocks = <&cpufreq_hw <<
108 L2_200: l2-cache { 88 L2_200: l2-cache {
109 compatible = " !! 89 compatible = "cache";
110 cache-level = !! 90 next-level-cache = <&L3_0>;
111 cache-unified; <<
112 next-level-cac <<
113 }; 91 };
114 }; 92 };
115 93
116 CPU3: cpu@300 { 94 CPU3: cpu@300 {
117 device_type = "cpu"; 95 device_type = "cpu";
118 compatible = "qcom,kry 96 compatible = "qcom,kryo780";
119 reg = <0x0 0x300>; 97 reg = <0x0 0x300>;
120 enable-method = "psci" 98 enable-method = "psci";
121 next-level-cache = <&L 99 next-level-cache = <&L2_300>;
122 power-domains = <&CPU_ 100 power-domains = <&CPU_PD3>;
123 power-domain-names = " 101 power-domain-names = "psci";
124 qcom,freq-domain = <&c 102 qcom,freq-domain = <&cpufreq_hw 0>;
125 #cooling-cells = <2>; 103 #cooling-cells = <2>;
126 clocks = <&cpufreq_hw <<
127 L2_300: l2-cache { 104 L2_300: l2-cache {
128 compatible = " !! 105 compatible = "cache";
129 cache-level = !! 106 next-level-cache = <&L3_0>;
130 cache-unified; <<
131 next-level-cac <<
132 }; 107 };
133 }; 108 };
134 109
135 CPU4: cpu@400 { 110 CPU4: cpu@400 {
136 device_type = "cpu"; 111 device_type = "cpu";
137 compatible = "qcom,kry 112 compatible = "qcom,kryo780";
138 reg = <0x0 0x400>; 113 reg = <0x0 0x400>;
139 enable-method = "psci" 114 enable-method = "psci";
140 next-level-cache = <&L 115 next-level-cache = <&L2_400>;
141 power-domains = <&CPU_ 116 power-domains = <&CPU_PD4>;
142 power-domain-names = " 117 power-domain-names = "psci";
143 qcom,freq-domain = <&c 118 qcom,freq-domain = <&cpufreq_hw 1>;
144 #cooling-cells = <2>; 119 #cooling-cells = <2>;
145 clocks = <&cpufreq_hw <<
146 L2_400: l2-cache { 120 L2_400: l2-cache {
147 compatible = " !! 121 compatible = "cache";
148 cache-level = !! 122 next-level-cache = <&L3_0>;
149 cache-unified; <<
150 next-level-cac <<
151 }; 123 };
152 }; 124 };
153 125
154 CPU5: cpu@500 { 126 CPU5: cpu@500 {
155 device_type = "cpu"; 127 device_type = "cpu";
156 compatible = "qcom,kry 128 compatible = "qcom,kryo780";
157 reg = <0x0 0x500>; 129 reg = <0x0 0x500>;
158 enable-method = "psci" 130 enable-method = "psci";
159 next-level-cache = <&L 131 next-level-cache = <&L2_500>;
160 power-domains = <&CPU_ 132 power-domains = <&CPU_PD5>;
161 power-domain-names = " 133 power-domain-names = "psci";
162 qcom,freq-domain = <&c 134 qcom,freq-domain = <&cpufreq_hw 1>;
163 #cooling-cells = <2>; 135 #cooling-cells = <2>;
164 clocks = <&cpufreq_hw <<
165 L2_500: l2-cache { 136 L2_500: l2-cache {
166 compatible = " !! 137 compatible = "cache";
167 cache-level = !! 138 next-level-cache = <&L3_0>;
168 cache-unified; <<
169 next-level-cac <<
170 }; 139 };
>> 140
171 }; 141 };
172 142
173 CPU6: cpu@600 { 143 CPU6: cpu@600 {
174 device_type = "cpu"; 144 device_type = "cpu";
175 compatible = "qcom,kry 145 compatible = "qcom,kryo780";
176 reg = <0x0 0x600>; 146 reg = <0x0 0x600>;
177 enable-method = "psci" 147 enable-method = "psci";
178 next-level-cache = <&L 148 next-level-cache = <&L2_600>;
179 power-domains = <&CPU_ 149 power-domains = <&CPU_PD6>;
180 power-domain-names = " 150 power-domain-names = "psci";
181 qcom,freq-domain = <&c 151 qcom,freq-domain = <&cpufreq_hw 1>;
182 #cooling-cells = <2>; 152 #cooling-cells = <2>;
183 clocks = <&cpufreq_hw <<
184 L2_600: l2-cache { 153 L2_600: l2-cache {
185 compatible = " !! 154 compatible = "cache";
186 cache-level = !! 155 next-level-cache = <&L3_0>;
187 cache-unified; <<
188 next-level-cac <<
189 }; 156 };
190 }; 157 };
191 158
192 CPU7: cpu@700 { 159 CPU7: cpu@700 {
193 device_type = "cpu"; 160 device_type = "cpu";
194 compatible = "qcom,kry 161 compatible = "qcom,kryo780";
195 reg = <0x0 0x700>; 162 reg = <0x0 0x700>;
196 enable-method = "psci" 163 enable-method = "psci";
197 next-level-cache = <&L 164 next-level-cache = <&L2_700>;
198 power-domains = <&CPU_ 165 power-domains = <&CPU_PD7>;
199 power-domain-names = " 166 power-domain-names = "psci";
200 qcom,freq-domain = <&c 167 qcom,freq-domain = <&cpufreq_hw 2>;
201 #cooling-cells = <2>; 168 #cooling-cells = <2>;
202 clocks = <&cpufreq_hw <<
203 L2_700: l2-cache { 169 L2_700: l2-cache {
204 compatible = " !! 170 compatible = "cache";
205 cache-level = !! 171 next-level-cache = <&L3_0>;
206 cache-unified; <<
207 next-level-cac <<
208 }; 172 };
209 }; 173 };
210 174
211 cpu-map { 175 cpu-map {
212 cluster0 { 176 cluster0 {
213 core0 { 177 core0 {
214 cpu = 178 cpu = <&CPU0>;
215 }; 179 };
216 180
217 core1 { 181 core1 {
218 cpu = 182 cpu = <&CPU1>;
219 }; 183 };
220 184
221 core2 { 185 core2 {
222 cpu = 186 cpu = <&CPU2>;
223 }; 187 };
224 188
225 core3 { 189 core3 {
226 cpu = 190 cpu = <&CPU3>;
227 }; 191 };
228 192
229 core4 { 193 core4 {
230 cpu = 194 cpu = <&CPU4>;
231 }; 195 };
232 196
233 core5 { 197 core5 {
234 cpu = 198 cpu = <&CPU5>;
235 }; 199 };
236 200
237 core6 { 201 core6 {
238 cpu = 202 cpu = <&CPU6>;
239 }; 203 };
240 204
241 core7 { 205 core7 {
242 cpu = 206 cpu = <&CPU7>;
243 }; 207 };
244 }; 208 };
245 }; 209 };
246 210
247 idle-states { 211 idle-states {
248 entry-method = "psci"; 212 entry-method = "psci";
249 213
250 LITTLE_CPU_SLEEP_0: cp 214 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
251 compatible = " 215 compatible = "arm,idle-state";
252 idle-state-nam 216 idle-state-name = "silver-rail-power-collapse";
253 arm,psci-suspe 217 arm,psci-suspend-param = <0x40000004>;
254 entry-latency- 218 entry-latency-us = <800>;
255 exit-latency-u 219 exit-latency-us = <750>;
256 min-residency- 220 min-residency-us = <4090>;
257 local-timer-st 221 local-timer-stop;
258 }; 222 };
259 223
260 BIG_CPU_SLEEP_0: cpu-s 224 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
261 compatible = " 225 compatible = "arm,idle-state";
262 idle-state-nam 226 idle-state-name = "gold-rail-power-collapse";
263 arm,psci-suspe 227 arm,psci-suspend-param = <0x40000004>;
264 entry-latency- 228 entry-latency-us = <600>;
265 exit-latency-u 229 exit-latency-us = <1550>;
266 min-residency- 230 min-residency-us = <4791>;
267 local-timer-st 231 local-timer-stop;
268 }; 232 };
269 }; 233 };
270 234
271 domain-idle-states { 235 domain-idle-states {
272 CLUSTER_SLEEP_0: clust 236 CLUSTER_SLEEP_0: cluster-sleep-0 {
273 compatible = " 237 compatible = "domain-idle-state";
>> 238 idle-state-name = "cluster-l3-off";
274 arm,psci-suspe 239 arm,psci-suspend-param = <0x41000044>;
275 entry-latency- 240 entry-latency-us = <1050>;
276 exit-latency-u 241 exit-latency-us = <2500>;
277 min-residency- 242 min-residency-us = <5309>;
>> 243 local-timer-stop;
278 }; 244 };
279 245
280 CLUSTER_SLEEP_1: clust 246 CLUSTER_SLEEP_1: cluster-sleep-1 {
281 compatible = " 247 compatible = "domain-idle-state";
>> 248 idle-state-name = "cluster-power-collapse";
282 arm,psci-suspe 249 arm,psci-suspend-param = <0x4100c344>;
283 entry-latency- 250 entry-latency-us = <2700>;
284 exit-latency-u 251 exit-latency-us = <3500>;
285 min-residency- 252 min-residency-us = <13959>;
>> 253 local-timer-stop;
286 }; 254 };
287 }; 255 };
288 }; 256 };
289 257
290 firmware { 258 firmware {
291 scm: scm { 259 scm: scm {
292 compatible = "qcom,scm 260 compatible = "qcom,scm-sm8450", "qcom,scm";
293 qcom,dload-mode = <&tc <<
294 interconnects = <&aggr <<
295 #reset-cells = <1>; 261 #reset-cells = <1>;
296 }; 262 };
297 }; 263 };
298 264
299 clk_virt: interconnect-0 { !! 265 clk_virt: interconnect@0 {
300 compatible = "qcom,sm8450-clk- 266 compatible = "qcom,sm8450-clk-virt";
301 #interconnect-cells = <2>; 267 #interconnect-cells = <2>;
302 qcom,bcm-voters = <&apps_bcm_v 268 qcom,bcm-voters = <&apps_bcm_voter>;
303 }; 269 };
304 270
305 mc_virt: interconnect-1 { !! 271 mc_virt: interconnect@1 {
306 compatible = "qcom,sm8450-mc-v 272 compatible = "qcom,sm8450-mc-virt";
307 #interconnect-cells = <2>; 273 #interconnect-cells = <2>;
308 qcom,bcm-voters = <&apps_bcm_v 274 qcom,bcm-voters = <&apps_bcm_voter>;
309 }; 275 };
310 276
311 memory@a0000000 { 277 memory@a0000000 {
312 device_type = "memory"; 278 device_type = "memory";
313 /* We expect the bootloader to 279 /* We expect the bootloader to fill in the size */
314 reg = <0x0 0xa0000000 0x0 0x0> 280 reg = <0x0 0xa0000000 0x0 0x0>;
315 }; 281 };
316 282
317 pmu { 283 pmu {
318 compatible = "arm,armv8-pmuv3" 284 compatible = "arm,armv8-pmuv3";
319 interrupts = <GIC_PPI 7 IRQ_TY 285 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
320 }; 286 };
321 287
322 psci { 288 psci {
323 compatible = "arm,psci-1.0"; 289 compatible = "arm,psci-1.0";
324 method = "smc"; 290 method = "smc";
325 291
326 CPU_PD0: power-domain-cpu0 { !! 292 CPU_PD0: cpu0 {
327 #power-domain-cells = 293 #power-domain-cells = <0>;
328 power-domains = <&CLUS 294 power-domains = <&CLUSTER_PD>;
329 domain-idle-states = < 295 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
330 }; 296 };
331 297
332 CPU_PD1: power-domain-cpu1 { !! 298 CPU_PD1: cpu1 {
333 #power-domain-cells = 299 #power-domain-cells = <0>;
334 power-domains = <&CLUS 300 power-domains = <&CLUSTER_PD>;
335 domain-idle-states = < 301 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
336 }; 302 };
337 303
338 CPU_PD2: power-domain-cpu2 { !! 304 CPU_PD2: cpu2 {
339 #power-domain-cells = 305 #power-domain-cells = <0>;
340 power-domains = <&CLUS 306 power-domains = <&CLUSTER_PD>;
341 domain-idle-states = < 307 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
342 }; 308 };
343 309
344 CPU_PD3: power-domain-cpu3 { !! 310 CPU_PD3: cpu3 {
345 #power-domain-cells = 311 #power-domain-cells = <0>;
346 power-domains = <&CLUS 312 power-domains = <&CLUSTER_PD>;
347 domain-idle-states = < 313 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
348 }; 314 };
349 315
350 CPU_PD4: power-domain-cpu4 { !! 316 CPU_PD4: cpu4 {
351 #power-domain-cells = 317 #power-domain-cells = <0>;
352 power-domains = <&CLUS 318 power-domains = <&CLUSTER_PD>;
353 domain-idle-states = < 319 domain-idle-states = <&BIG_CPU_SLEEP_0>;
354 }; 320 };
355 321
356 CPU_PD5: power-domain-cpu5 { !! 322 CPU_PD5: cpu5 {
357 #power-domain-cells = 323 #power-domain-cells = <0>;
358 power-domains = <&CLUS 324 power-domains = <&CLUSTER_PD>;
359 domain-idle-states = < 325 domain-idle-states = <&BIG_CPU_SLEEP_0>;
360 }; 326 };
361 327
362 CPU_PD6: power-domain-cpu6 { !! 328 CPU_PD6: cpu6 {
363 #power-domain-cells = 329 #power-domain-cells = <0>;
364 power-domains = <&CLUS 330 power-domains = <&CLUSTER_PD>;
365 domain-idle-states = < 331 domain-idle-states = <&BIG_CPU_SLEEP_0>;
366 }; 332 };
367 333
368 CPU_PD7: power-domain-cpu7 { !! 334 CPU_PD7: cpu7 {
369 #power-domain-cells = 335 #power-domain-cells = <0>;
370 power-domains = <&CLUS 336 power-domains = <&CLUSTER_PD>;
371 domain-idle-states = < 337 domain-idle-states = <&BIG_CPU_SLEEP_0>;
372 }; 338 };
373 339
374 CLUSTER_PD: power-domain-cpu-c !! 340 CLUSTER_PD: cpu-cluster0 {
375 #power-domain-cells = 341 #power-domain-cells = <0>;
376 domain-idle-states = < 342 domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>;
377 }; 343 };
378 }; 344 };
379 345
380 qup_opp_table_100mhz: opp-table-qup { !! 346 qup_opp_table_100mhz: qup-100mhz-opp-table {
381 compatible = "operating-points 347 compatible = "operating-points-v2";
382 348
383 opp-50000000 { 349 opp-50000000 {
384 opp-hz = /bits/ 64 <50 350 opp-hz = /bits/ 64 <50000000>;
385 required-opps = <&rpmh 351 required-opps = <&rpmhpd_opp_min_svs>;
386 }; 352 };
387 353
388 opp-75000000 { 354 opp-75000000 {
389 opp-hz = /bits/ 64 <75 355 opp-hz = /bits/ 64 <75000000>;
390 required-opps = <&rpmh 356 required-opps = <&rpmhpd_opp_low_svs>;
391 }; 357 };
392 358
393 opp-100000000 { 359 opp-100000000 {
394 opp-hz = /bits/ 64 <10 360 opp-hz = /bits/ 64 <100000000>;
395 required-opps = <&rpmh 361 required-opps = <&rpmhpd_opp_svs>;
396 }; 362 };
397 }; 363 };
398 364
399 reserved_memory: reserved-memory { 365 reserved_memory: reserved-memory {
400 #address-cells = <2>; 366 #address-cells = <2>;
401 #size-cells = <2>; 367 #size-cells = <2>;
402 ranges; 368 ranges;
403 369
404 hyp_mem: memory@80000000 { 370 hyp_mem: memory@80000000 {
405 reg = <0x0 0x80000000 371 reg = <0x0 0x80000000 0x0 0x600000>;
406 no-map; 372 no-map;
407 }; 373 };
408 374
409 xbl_dt_log_mem: memory@8060000 375 xbl_dt_log_mem: memory@80600000 {
410 reg = <0x0 0x80600000 376 reg = <0x0 0x80600000 0x0 0x40000>;
411 no-map; 377 no-map;
412 }; 378 };
413 379
414 xbl_ramdump_mem: memory@806400 380 xbl_ramdump_mem: memory@80640000 {
415 reg = <0x0 0x80640000 381 reg = <0x0 0x80640000 0x0 0x180000>;
416 no-map; 382 no-map;
417 }; 383 };
418 384
419 xbl_sc_mem: memory@807c0000 { 385 xbl_sc_mem: memory@807c0000 {
420 reg = <0x0 0x807c0000 386 reg = <0x0 0x807c0000 0x0 0x40000>;
421 no-map; 387 no-map;
422 }; 388 };
423 389
424 aop_image_mem: memory@80800000 390 aop_image_mem: memory@80800000 {
425 reg = <0x0 0x80800000 391 reg = <0x0 0x80800000 0x0 0x60000>;
426 no-map; 392 no-map;
427 }; 393 };
428 394
429 aop_cmd_db_mem: memory@8086000 395 aop_cmd_db_mem: memory@80860000 {
430 compatible = "qcom,cmd 396 compatible = "qcom,cmd-db";
431 reg = <0x0 0x80860000 397 reg = <0x0 0x80860000 0x0 0x20000>;
432 no-map; 398 no-map;
433 }; 399 };
434 400
435 aop_config_mem: memory@8088000 401 aop_config_mem: memory@80880000 {
436 reg = <0x0 0x80880000 402 reg = <0x0 0x80880000 0x0 0x20000>;
437 no-map; 403 no-map;
438 }; 404 };
439 405
440 tme_crash_dump_mem: memory@808 406 tme_crash_dump_mem: memory@808a0000 {
441 reg = <0x0 0x808a0000 407 reg = <0x0 0x808a0000 0x0 0x40000>;
442 no-map; 408 no-map;
443 }; 409 };
444 410
445 tme_log_mem: memory@808e0000 { 411 tme_log_mem: memory@808e0000 {
446 reg = <0x0 0x808e0000 412 reg = <0x0 0x808e0000 0x0 0x4000>;
447 no-map; 413 no-map;
448 }; 414 };
449 415
450 uefi_log_mem: memory@808e4000 416 uefi_log_mem: memory@808e4000 {
451 reg = <0x0 0x808e4000 417 reg = <0x0 0x808e4000 0x0 0x10000>;
452 no-map; 418 no-map;
453 }; 419 };
454 420
455 /* secdata region can be reuse 421 /* secdata region can be reused by apps */
456 smem: memory@80900000 { 422 smem: memory@80900000 {
457 compatible = "qcom,sme 423 compatible = "qcom,smem";
458 reg = <0x0 0x80900000 424 reg = <0x0 0x80900000 0x0 0x200000>;
459 hwlocks = <&tcsr_mutex 425 hwlocks = <&tcsr_mutex 3>;
460 no-map; 426 no-map;
461 }; 427 };
462 428
463 cpucp_fw_mem: memory@80b00000 429 cpucp_fw_mem: memory@80b00000 {
464 reg = <0x0 0x80b00000 430 reg = <0x0 0x80b00000 0x0 0x100000>;
465 no-map; 431 no-map;
466 }; 432 };
467 433
468 cdsp_secure_heap: memory@80c00 434 cdsp_secure_heap: memory@80c00000 {
469 reg = <0x0 0x80c00000 435 reg = <0x0 0x80c00000 0x0 0x4600000>;
470 no-map; 436 no-map;
471 }; 437 };
472 438
>> 439 camera_mem: memory@85200000 {
>> 440 reg = <0x0 0x85200000 0x0 0x500000>;
>> 441 no-map;
>> 442 };
>> 443
473 video_mem: memory@85700000 { 444 video_mem: memory@85700000 {
474 reg = <0x0 0x85700000 445 reg = <0x0 0x85700000 0x0 0x700000>;
475 no-map; 446 no-map;
476 }; 447 };
477 448
478 adsp_mem: memory@85e00000 { 449 adsp_mem: memory@85e00000 {
479 reg = <0x0 0x85e00000 450 reg = <0x0 0x85e00000 0x0 0x2100000>;
480 no-map; 451 no-map;
481 }; 452 };
482 453
483 slpi_mem: memory@88000000 { 454 slpi_mem: memory@88000000 {
484 reg = <0x0 0x88000000 455 reg = <0x0 0x88000000 0x0 0x1900000>;
485 no-map; 456 no-map;
486 }; 457 };
487 458
488 cdsp_mem: memory@89900000 { 459 cdsp_mem: memory@89900000 {
489 reg = <0x0 0x89900000 460 reg = <0x0 0x89900000 0x0 0x2000000>;
490 no-map; 461 no-map;
491 }; 462 };
492 463
493 ipa_fw_mem: memory@8b900000 { 464 ipa_fw_mem: memory@8b900000 {
494 reg = <0x0 0x8b900000 465 reg = <0x0 0x8b900000 0x0 0x10000>;
495 no-map; 466 no-map;
496 }; 467 };
497 468
498 ipa_gsi_mem: memory@8b910000 { 469 ipa_gsi_mem: memory@8b910000 {
499 reg = <0x0 0x8b910000 470 reg = <0x0 0x8b910000 0x0 0xa000>;
500 no-map; 471 no-map;
501 }; 472 };
502 473
503 gpu_micro_code_mem: memory@8b9 474 gpu_micro_code_mem: memory@8b91a000 {
504 reg = <0x0 0x8b91a000 475 reg = <0x0 0x8b91a000 0x0 0x2000>;
505 no-map; 476 no-map;
506 }; 477 };
507 478
508 spss_region_mem: memory@8ba000 479 spss_region_mem: memory@8ba00000 {
509 reg = <0x0 0x8ba00000 480 reg = <0x0 0x8ba00000 0x0 0x180000>;
510 no-map; 481 no-map;
511 }; 482 };
512 483
513 /* First part of the "SPU secu 484 /* First part of the "SPU secure shared memory" region */
514 spu_tz_shared_mem: memory@8bb8 485 spu_tz_shared_mem: memory@8bb80000 {
515 reg = <0x0 0x8bb80000 486 reg = <0x0 0x8bb80000 0x0 0x60000>;
516 no-map; 487 no-map;
517 }; 488 };
518 489
519 /* Second part of the "SPU sec 490 /* Second part of the "SPU secure shared memory" region */
520 spu_modem_shared_mem: memory@8 491 spu_modem_shared_mem: memory@8bbe0000 {
521 reg = <0x0 0x8bbe0000 492 reg = <0x0 0x8bbe0000 0x0 0x20000>;
522 no-map; 493 no-map;
523 }; 494 };
524 495
525 mpss_mem: memory@8bc00000 { 496 mpss_mem: memory@8bc00000 {
526 reg = <0x0 0x8bc00000 497 reg = <0x0 0x8bc00000 0x0 0x13200000>;
527 no-map; 498 no-map;
528 }; 499 };
529 500
530 cvp_mem: memory@9ee00000 { 501 cvp_mem: memory@9ee00000 {
531 reg = <0x0 0x9ee00000 502 reg = <0x0 0x9ee00000 0x0 0x700000>;
532 no-map; 503 no-map;
533 }; 504 };
534 505
535 camera_mem: memory@9f500000 { <<
536 reg = <0x0 0x9f500000 <<
537 no-map; <<
538 }; <<
539 <<
540 rmtfs_mem: memory@9fd00000 { 506 rmtfs_mem: memory@9fd00000 {
541 compatible = "qcom,rmt 507 compatible = "qcom,rmtfs-mem";
542 reg = <0x0 0x9fd00000 508 reg = <0x0 0x9fd00000 0x0 0x280000>;
543 no-map; 509 no-map;
544 510
545 qcom,client-id = <1>; 511 qcom,client-id = <1>;
546 qcom,vmid = <QCOM_SCM_ !! 512 qcom,vmid = <15>;
547 }; <<
548 <<
549 xbl_sc_mem2: memory@a6e00000 { <<
550 reg = <0x0 0xa6e00000 <<
551 no-map; <<
552 }; 513 };
553 514
554 global_sync_mem: memory@a6f000 515 global_sync_mem: memory@a6f00000 {
555 reg = <0x0 0xa6f00000 516 reg = <0x0 0xa6f00000 0x0 0x100000>;
556 no-map; 517 no-map;
557 }; 518 };
558 519
559 /* uefi region can be reused b 520 /* uefi region can be reused by APPS */
560 521
561 /* Linux kernel image is loade 522 /* Linux kernel image is loaded at 0xa0000000 */
562 523
563 oem_vm_mem: memory@bb000000 { 524 oem_vm_mem: memory@bb000000 {
564 reg = <0x0 0xbb000000 525 reg = <0x0 0xbb000000 0x0 0x5000000>;
565 no-map; 526 no-map;
566 }; 527 };
567 528
568 mte_mem: memory@c0000000 { 529 mte_mem: memory@c0000000 {
569 reg = <0x0 0xc0000000 530 reg = <0x0 0xc0000000 0x0 0x20000000>;
570 no-map; 531 no-map;
571 }; 532 };
572 533
573 qheebsp_reserved_mem: memory@e 534 qheebsp_reserved_mem: memory@e0000000 {
574 reg = <0x0 0xe0000000 535 reg = <0x0 0xe0000000 0x0 0x600000>;
575 no-map; 536 no-map;
576 }; 537 };
577 538
578 cpusys_vm_mem: memory@e0600000 539 cpusys_vm_mem: memory@e0600000 {
579 reg = <0x0 0xe0600000 540 reg = <0x0 0xe0600000 0x0 0x400000>;
580 no-map; 541 no-map;
581 }; 542 };
582 543
583 hyp_reserved_mem: memory@e0a00 544 hyp_reserved_mem: memory@e0a00000 {
584 reg = <0x0 0xe0a00000 545 reg = <0x0 0xe0a00000 0x0 0x100000>;
585 no-map; 546 no-map;
586 }; 547 };
587 548
588 trust_ui_vm_mem: memory@e0b000 549 trust_ui_vm_mem: memory@e0b00000 {
589 reg = <0x0 0xe0b00000 550 reg = <0x0 0xe0b00000 0x0 0x4af3000>;
590 no-map; 551 no-map;
591 }; 552 };
592 553
593 trust_ui_vm_qrtr: memory@e55f3 554 trust_ui_vm_qrtr: memory@e55f3000 {
594 reg = <0x0 0xe55f3000 555 reg = <0x0 0xe55f3000 0x0 0x9000>;
595 no-map; 556 no-map;
596 }; 557 };
597 558
598 trust_ui_vm_vblk0_ring: memory 559 trust_ui_vm_vblk0_ring: memory@e55fc000 {
599 reg = <0x0 0xe55fc000 560 reg = <0x0 0xe55fc000 0x0 0x4000>;
600 no-map; 561 no-map;
601 }; 562 };
602 563
603 trust_ui_vm_swiotlb: memory@e5 564 trust_ui_vm_swiotlb: memory@e5600000 {
604 reg = <0x0 0xe5600000 565 reg = <0x0 0xe5600000 0x0 0x100000>;
605 no-map; 566 no-map;
606 }; 567 };
607 568
608 tz_stat_mem: memory@e8800000 { 569 tz_stat_mem: memory@e8800000 {
609 reg = <0x0 0xe8800000 570 reg = <0x0 0xe8800000 0x0 0x100000>;
610 no-map; 571 no-map;
611 }; 572 };
612 573
613 tags_mem: memory@e8900000 { 574 tags_mem: memory@e8900000 {
614 reg = <0x0 0xe8900000 575 reg = <0x0 0xe8900000 0x0 0x1200000>;
615 no-map; 576 no-map;
616 }; 577 };
617 578
618 qtee_mem: memory@e9b00000 { 579 qtee_mem: memory@e9b00000 {
619 reg = <0x0 0xe9b00000 580 reg = <0x0 0xe9b00000 0x0 0x500000>;
620 no-map; 581 no-map;
621 }; 582 };
622 583
623 trusted_apps_mem: memory@ea000 584 trusted_apps_mem: memory@ea000000 {
624 reg = <0x0 0xea000000 585 reg = <0x0 0xea000000 0x0 0x3900000>;
625 no-map; 586 no-map;
626 }; 587 };
627 588
628 trusted_apps_ext_mem: memory@e 589 trusted_apps_ext_mem: memory@ed900000 {
629 reg = <0x0 0xed900000 590 reg = <0x0 0xed900000 0x0 0x3b00000>;
630 no-map; 591 no-map;
631 }; 592 };
632 }; 593 };
633 594
634 smp2p-adsp { 595 smp2p-adsp {
635 compatible = "qcom,smp2p"; 596 compatible = "qcom,smp2p";
636 qcom,smem = <443>, <429>; 597 qcom,smem = <443>, <429>;
637 interrupts-extended = <&ipcc I 598 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
638 I 599 IPCC_MPROC_SIGNAL_SMP2P
639 I 600 IRQ_TYPE_EDGE_RISING>;
640 mboxes = <&ipcc IPCC_CLIENT_LP 601 mboxes = <&ipcc IPCC_CLIENT_LPASS
641 IPCC_MPROC_SIG 602 IPCC_MPROC_SIGNAL_SMP2P>;
642 603
643 qcom,local-pid = <0>; 604 qcom,local-pid = <0>;
644 qcom,remote-pid = <2>; 605 qcom,remote-pid = <2>;
645 606
646 smp2p_adsp_out: master-kernel 607 smp2p_adsp_out: master-kernel {
647 qcom,entry-name = "mas 608 qcom,entry-name = "master-kernel";
648 #qcom,smem-state-cells 609 #qcom,smem-state-cells = <1>;
649 }; 610 };
650 611
651 smp2p_adsp_in: slave-kernel { 612 smp2p_adsp_in: slave-kernel {
652 qcom,entry-name = "sla 613 qcom,entry-name = "slave-kernel";
653 interrupt-controller; 614 interrupt-controller;
654 #interrupt-cells = <2> 615 #interrupt-cells = <2>;
655 }; 616 };
656 }; 617 };
657 618
658 smp2p-cdsp { 619 smp2p-cdsp {
659 compatible = "qcom,smp2p"; 620 compatible = "qcom,smp2p";
660 qcom,smem = <94>, <432>; 621 qcom,smem = <94>, <432>;
661 interrupts-extended = <&ipcc I 622 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
662 I 623 IPCC_MPROC_SIGNAL_SMP2P
663 I 624 IRQ_TYPE_EDGE_RISING>;
664 mboxes = <&ipcc IPCC_CLIENT_CD 625 mboxes = <&ipcc IPCC_CLIENT_CDSP
665 IPCC_MPROC_SIG 626 IPCC_MPROC_SIGNAL_SMP2P>;
666 627
667 qcom,local-pid = <0>; 628 qcom,local-pid = <0>;
668 qcom,remote-pid = <5>; 629 qcom,remote-pid = <5>;
669 630
670 smp2p_cdsp_out: master-kernel 631 smp2p_cdsp_out: master-kernel {
671 qcom,entry-name = "mas 632 qcom,entry-name = "master-kernel";
672 #qcom,smem-state-cells 633 #qcom,smem-state-cells = <1>;
673 }; 634 };
674 635
675 smp2p_cdsp_in: slave-kernel { 636 smp2p_cdsp_in: slave-kernel {
676 qcom,entry-name = "sla 637 qcom,entry-name = "slave-kernel";
677 interrupt-controller; 638 interrupt-controller;
678 #interrupt-cells = <2> 639 #interrupt-cells = <2>;
679 }; 640 };
680 }; 641 };
681 642
682 smp2p-modem { 643 smp2p-modem {
683 compatible = "qcom,smp2p"; 644 compatible = "qcom,smp2p";
684 qcom,smem = <435>, <428>; 645 qcom,smem = <435>, <428>;
685 interrupts-extended = <&ipcc I 646 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
686 I 647 IPCC_MPROC_SIGNAL_SMP2P
687 I 648 IRQ_TYPE_EDGE_RISING>;
688 mboxes = <&ipcc IPCC_CLIENT_MP 649 mboxes = <&ipcc IPCC_CLIENT_MPSS
689 IPCC_MPROC_SIG 650 IPCC_MPROC_SIGNAL_SMP2P>;
690 651
691 qcom,local-pid = <0>; 652 qcom,local-pid = <0>;
692 qcom,remote-pid = <1>; 653 qcom,remote-pid = <1>;
693 654
694 smp2p_modem_out: master-kernel 655 smp2p_modem_out: master-kernel {
695 qcom,entry-name = "mas 656 qcom,entry-name = "master-kernel";
696 #qcom,smem-state-cells 657 #qcom,smem-state-cells = <1>;
697 }; 658 };
698 659
699 smp2p_modem_in: slave-kernel { 660 smp2p_modem_in: slave-kernel {
700 qcom,entry-name = "sla 661 qcom,entry-name = "slave-kernel";
701 interrupt-controller; 662 interrupt-controller;
702 #interrupt-cells = <2> 663 #interrupt-cells = <2>;
703 }; 664 };
704 665
705 ipa_smp2p_out: ipa-ap-to-modem 666 ipa_smp2p_out: ipa-ap-to-modem {
706 qcom,entry-name = "ipa 667 qcom,entry-name = "ipa";
707 #qcom,smem-state-cells 668 #qcom,smem-state-cells = <1>;
708 }; 669 };
709 670
710 ipa_smp2p_in: ipa-modem-to-ap 671 ipa_smp2p_in: ipa-modem-to-ap {
711 qcom,entry-name = "ipa 672 qcom,entry-name = "ipa";
712 interrupt-controller; 673 interrupt-controller;
713 #interrupt-cells = <2> 674 #interrupt-cells = <2>;
714 }; 675 };
715 }; 676 };
716 677
717 smp2p-slpi { 678 smp2p-slpi {
718 compatible = "qcom,smp2p"; 679 compatible = "qcom,smp2p";
719 qcom,smem = <481>, <430>; 680 qcom,smem = <481>, <430>;
720 interrupts-extended = <&ipcc I 681 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
721 I 682 IPCC_MPROC_SIGNAL_SMP2P
722 I 683 IRQ_TYPE_EDGE_RISING>;
723 mboxes = <&ipcc IPCC_CLIENT_SL 684 mboxes = <&ipcc IPCC_CLIENT_SLPI
724 IPCC_MPROC_SIG 685 IPCC_MPROC_SIGNAL_SMP2P>;
725 686
726 qcom,local-pid = <0>; 687 qcom,local-pid = <0>;
727 qcom,remote-pid = <3>; 688 qcom,remote-pid = <3>;
728 689
729 smp2p_slpi_out: master-kernel 690 smp2p_slpi_out: master-kernel {
730 qcom,entry-name = "mas 691 qcom,entry-name = "master-kernel";
731 #qcom,smem-state-cells 692 #qcom,smem-state-cells = <1>;
732 }; 693 };
733 694
734 smp2p_slpi_in: slave-kernel { 695 smp2p_slpi_in: slave-kernel {
735 qcom,entry-name = "sla 696 qcom,entry-name = "slave-kernel";
736 interrupt-controller; 697 interrupt-controller;
737 #interrupt-cells = <2> 698 #interrupt-cells = <2>;
738 }; 699 };
739 }; 700 };
740 701
741 soc: soc@0 { 702 soc: soc@0 {
742 #address-cells = <2>; 703 #address-cells = <2>;
743 #size-cells = <2>; 704 #size-cells = <2>;
744 ranges = <0 0 0 0 0x10 0>; 705 ranges = <0 0 0 0 0x10 0>;
745 dma-ranges = <0 0 0 0 0x10 0>; 706 dma-ranges = <0 0 0 0 0x10 0>;
746 compatible = "simple-bus"; 707 compatible = "simple-bus";
747 708
748 gcc: clock-controller@100000 { 709 gcc: clock-controller@100000 {
749 compatible = "qcom,gcc 710 compatible = "qcom,gcc-sm8450";
750 reg = <0x0 0x00100000 711 reg = <0x0 0x00100000 0x0 0x1f4200>;
751 #clock-cells = <1>; 712 #clock-cells = <1>;
752 #reset-cells = <1>; 713 #reset-cells = <1>;
753 #power-domain-cells = 714 #power-domain-cells = <1>;
754 clocks = <&rpmhcc RPMH 715 clocks = <&rpmhcc RPMH_CXO_CLK>,
755 <&sleep_clk>, !! 716 <&pcie0_lane>,
756 <&pcie0_phy>, !! 717 <&pcie1_lane>,
757 <&pcie1_phy Q !! 718 <&sleep_clk>;
758 <&pcie1_phy Q <<
759 <&ufs_mem_phy <<
760 <&ufs_mem_phy <<
761 <&ufs_mem_phy <<
762 <&usb_1_qmpph <<
763 clock-names = "bi_tcxo 719 clock-names = "bi_tcxo",
764 "sleep_c <<
765 "pcie_0_ 720 "pcie_0_pipe_clk",
766 "pcie_1_ 721 "pcie_1_pipe_clk",
767 "pcie_1_ !! 722 "sleep_clk";
768 "ufs_phy <<
769 "ufs_phy <<
770 "ufs_phy <<
771 "usb3_ph <<
772 }; 723 };
773 724
774 gpi_dma2: dma-controller@80000 725 gpi_dma2: dma-controller@800000 {
775 compatible = "qcom,sm8 !! 726 compatible = "qcom,sm8450-gpi-dma";
776 #dma-cells = <3>; 727 #dma-cells = <3>;
777 reg = <0 0x00800000 0 !! 728 reg = <0 0x800000 0 0x60000>;
778 interrupts = <GIC_SPI 729 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
779 <GIC_SPI 730 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
780 <GIC_SPI 731 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
781 <GIC_SPI 732 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
782 <GIC_SPI 733 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
783 <GIC_SPI 734 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
784 <GIC_SPI 735 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
785 <GIC_SPI 736 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
786 <GIC_SPI 737 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
787 <GIC_SPI 738 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
788 <GIC_SPI 739 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
789 <GIC_SPI 740 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
790 dma-channels = <12>; 741 dma-channels = <12>;
791 dma-channel-mask = <0x 742 dma-channel-mask = <0x7e>;
792 iommus = <&apps_smmu 0 743 iommus = <&apps_smmu 0x496 0x0>;
793 status = "disabled"; 744 status = "disabled";
794 }; 745 };
795 746
796 qupv3_id_2: geniqup@8c0000 { 747 qupv3_id_2: geniqup@8c0000 {
797 compatible = "qcom,gen 748 compatible = "qcom,geni-se-qup";
798 reg = <0x0 0x008c0000 749 reg = <0x0 0x008c0000 0x0 0x2000>;
799 clock-names = "m-ahb", 750 clock-names = "m-ahb", "s-ahb";
800 clocks = <&gcc GCC_QUP 751 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
801 <&gcc GCC_QUP 752 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
802 iommus = <&apps_smmu 0 753 iommus = <&apps_smmu 0x483 0x0>;
803 #address-cells = <2>; 754 #address-cells = <2>;
804 #size-cells = <2>; 755 #size-cells = <2>;
805 ranges; 756 ranges;
806 status = "disabled"; 757 status = "disabled";
807 758
808 i2c15: i2c@880000 { 759 i2c15: i2c@880000 {
809 compatible = " 760 compatible = "qcom,geni-i2c";
810 reg = <0x0 0x0 761 reg = <0x0 0x00880000 0x0 0x4000>;
811 clock-names = 762 clock-names = "se";
812 clocks = <&gcc 763 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
813 pinctrl-names 764 pinctrl-names = "default";
814 pinctrl-0 = <& 765 pinctrl-0 = <&qup_i2c15_data_clk>;
815 interrupts = < 766 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
816 #address-cells 767 #address-cells = <1>;
817 #size-cells = 768 #size-cells = <0>;
818 interconnects 769 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
819 770 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
820 771 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
821 interconnect-n 772 interconnect-names = "qup-core", "qup-config", "qup-memory";
822 dmas = <&gpi_d 773 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
823 <&gpi_d 774 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
824 dma-names = "t 775 dma-names = "tx", "rx";
825 status = "disa 776 status = "disabled";
826 }; 777 };
827 778
828 spi15: spi@880000 { 779 spi15: spi@880000 {
829 compatible = " 780 compatible = "qcom,geni-spi";
830 reg = <0x0 0x0 781 reg = <0x0 0x00880000 0x0 0x4000>;
831 clock-names = 782 clock-names = "se";
832 clocks = <&gcc 783 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
833 interrupts = < 784 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
834 pinctrl-names 785 pinctrl-names = "default";
835 pinctrl-0 = <& 786 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
>> 787 spi-max-frequency = <50000000>;
836 interconnects 788 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
837 789 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
838 interconnect-n 790 interconnect-names = "qup-core", "qup-config";
839 dmas = <&gpi_d 791 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
840 <&gpi_d 792 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
841 dma-names = "t 793 dma-names = "tx", "rx";
842 #address-cells 794 #address-cells = <1>;
843 #size-cells = 795 #size-cells = <0>;
844 status = "disa 796 status = "disabled";
845 }; 797 };
846 798
847 i2c16: i2c@884000 { 799 i2c16: i2c@884000 {
848 compatible = " 800 compatible = "qcom,geni-i2c";
849 reg = <0x0 0x0 801 reg = <0x0 0x00884000 0x0 0x4000>;
850 clock-names = 802 clock-names = "se";
851 clocks = <&gcc 803 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
852 pinctrl-names 804 pinctrl-names = "default";
853 pinctrl-0 = <& 805 pinctrl-0 = <&qup_i2c16_data_clk>;
854 interrupts = < 806 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
855 #address-cells 807 #address-cells = <1>;
856 #size-cells = 808 #size-cells = <0>;
857 interconnects 809 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
858 810 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
859 811 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
860 interconnect-n 812 interconnect-names = "qup-core", "qup-config", "qup-memory";
861 dmas = <&gpi_d 813 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
862 <&gpi_d 814 <&gpi_dma2 1 1 QCOM_GPI_I2C>;
863 dma-names = "t 815 dma-names = "tx", "rx";
864 status = "disa 816 status = "disabled";
865 }; 817 };
866 818
867 spi16: spi@884000 { 819 spi16: spi@884000 {
868 compatible = " 820 compatible = "qcom,geni-spi";
869 reg = <0x0 0x0 821 reg = <0x0 0x00884000 0x0 0x4000>;
870 clock-names = 822 clock-names = "se";
871 clocks = <&gcc 823 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
872 interrupts = < 824 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
873 pinctrl-names 825 pinctrl-names = "default";
874 pinctrl-0 = <& 826 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>;
>> 827 spi-max-frequency = <50000000>;
875 interconnects 828 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
876 829 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
877 interconnect-n 830 interconnect-names = "qup-core", "qup-config";
878 dmas = <&gpi_d 831 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
879 <&gpi_d 832 <&gpi_dma2 1 1 QCOM_GPI_SPI>;
880 dma-names = "t 833 dma-names = "tx", "rx";
881 #address-cells 834 #address-cells = <1>;
882 #size-cells = 835 #size-cells = <0>;
883 status = "disa 836 status = "disabled";
884 }; 837 };
885 838
886 i2c17: i2c@888000 { 839 i2c17: i2c@888000 {
887 compatible = " 840 compatible = "qcom,geni-i2c";
888 reg = <0x0 0x0 841 reg = <0x0 0x00888000 0x0 0x4000>;
889 clock-names = 842 clock-names = "se";
890 clocks = <&gcc 843 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
891 pinctrl-names 844 pinctrl-names = "default";
892 pinctrl-0 = <& 845 pinctrl-0 = <&qup_i2c17_data_clk>;
893 interrupts = < 846 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
894 #address-cells 847 #address-cells = <1>;
895 #size-cells = 848 #size-cells = <0>;
896 interconnects 849 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
897 850 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
898 851 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
899 interconnect-n 852 interconnect-names = "qup-core", "qup-config", "qup-memory";
900 dmas = <&gpi_d 853 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
901 <&gpi_d 854 <&gpi_dma2 1 2 QCOM_GPI_I2C>;
902 dma-names = "t 855 dma-names = "tx", "rx";
903 status = "disa 856 status = "disabled";
904 }; 857 };
905 858
906 spi17: spi@888000 { 859 spi17: spi@888000 {
907 compatible = " 860 compatible = "qcom,geni-spi";
908 reg = <0x0 0x0 861 reg = <0x0 0x00888000 0x0 0x4000>;
909 clock-names = 862 clock-names = "se";
910 clocks = <&gcc 863 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
911 interrupts = < 864 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
912 pinctrl-names 865 pinctrl-names = "default";
913 pinctrl-0 = <& 866 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>;
>> 867 spi-max-frequency = <50000000>;
914 interconnects 868 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
915 869 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
916 interconnect-n 870 interconnect-names = "qup-core", "qup-config";
917 dmas = <&gpi_d 871 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
918 <&gpi_d 872 <&gpi_dma2 1 2 QCOM_GPI_SPI>;
919 dma-names = "t 873 dma-names = "tx", "rx";
920 #address-cells 874 #address-cells = <1>;
921 #size-cells = 875 #size-cells = <0>;
922 status = "disa 876 status = "disabled";
923 }; 877 };
924 878
925 i2c18: i2c@88c000 { 879 i2c18: i2c@88c000 {
926 compatible = " 880 compatible = "qcom,geni-i2c";
927 reg = <0x0 0x0 881 reg = <0x0 0x0088c000 0x0 0x4000>;
928 clock-names = 882 clock-names = "se";
929 clocks = <&gcc 883 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
930 pinctrl-names 884 pinctrl-names = "default";
931 pinctrl-0 = <& 885 pinctrl-0 = <&qup_i2c18_data_clk>;
932 interrupts = < 886 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
933 #address-cells 887 #address-cells = <1>;
934 #size-cells = 888 #size-cells = <0>;
935 interconnects 889 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
936 890 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
937 891 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
938 interconnect-n 892 interconnect-names = "qup-core", "qup-config", "qup-memory";
939 dmas = <&gpi_d 893 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
940 <&gpi_d 894 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
941 dma-names = "t 895 dma-names = "tx", "rx";
942 status = "disa 896 status = "disabled";
943 }; 897 };
944 898
945 spi18: spi@88c000 { 899 spi18: spi@88c000 {
946 compatible = " 900 compatible = "qcom,geni-spi";
947 reg = <0 0x008 901 reg = <0 0x0088c000 0 0x4000>;
948 clock-names = 902 clock-names = "se";
949 clocks = <&gcc 903 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
950 interrupts = < 904 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
951 pinctrl-names 905 pinctrl-names = "default";
952 pinctrl-0 = <& 906 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>;
>> 907 spi-max-frequency = <50000000>;
953 interconnects 908 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
954 909 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
955 interconnect-n 910 interconnect-names = "qup-core", "qup-config";
956 dmas = <&gpi_d 911 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
957 <&gpi_d 912 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
958 dma-names = "t 913 dma-names = "tx", "rx";
959 #address-cells 914 #address-cells = <1>;
960 #size-cells = 915 #size-cells = <0>;
961 status = "disa 916 status = "disabled";
962 }; 917 };
963 918
964 i2c19: i2c@890000 { 919 i2c19: i2c@890000 {
965 compatible = " 920 compatible = "qcom,geni-i2c";
966 reg = <0x0 0x0 921 reg = <0x0 0x00890000 0x0 0x4000>;
967 clock-names = 922 clock-names = "se";
968 clocks = <&gcc 923 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
969 pinctrl-names 924 pinctrl-names = "default";
970 pinctrl-0 = <& 925 pinctrl-0 = <&qup_i2c19_data_clk>;
971 interrupts = < 926 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
972 #address-cells 927 #address-cells = <1>;
973 #size-cells = 928 #size-cells = <0>;
974 interconnects 929 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
975 930 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
976 931 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
977 interconnect-n 932 interconnect-names = "qup-core", "qup-config", "qup-memory";
978 dmas = <&gpi_d 933 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
979 <&gpi_d 934 <&gpi_dma2 1 4 QCOM_GPI_I2C>;
980 dma-names = "t 935 dma-names = "tx", "rx";
981 status = "disa 936 status = "disabled";
982 }; 937 };
983 938
984 spi19: spi@890000 { 939 spi19: spi@890000 {
985 compatible = " 940 compatible = "qcom,geni-spi";
986 reg = <0 0x008 941 reg = <0 0x00890000 0 0x4000>;
987 clock-names = 942 clock-names = "se";
988 clocks = <&gcc 943 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
989 interrupts = < 944 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
990 pinctrl-names 945 pinctrl-names = "default";
991 pinctrl-0 = <& 946 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>;
>> 947 spi-max-frequency = <50000000>;
992 interconnects 948 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
993 949 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
994 interconnect-n 950 interconnect-names = "qup-core", "qup-config";
995 dmas = <&gpi_d 951 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
996 <&gpi_d 952 <&gpi_dma2 1 4 QCOM_GPI_I2C>;
997 dma-names = "t 953 dma-names = "tx", "rx";
998 #address-cells 954 #address-cells = <1>;
999 #size-cells = 955 #size-cells = <0>;
1000 status = "dis 956 status = "disabled";
1001 }; 957 };
1002 958
1003 i2c20: i2c@894000 { 959 i2c20: i2c@894000 {
1004 compatible = 960 compatible = "qcom,geni-i2c";
1005 reg = <0x0 0x 961 reg = <0x0 0x00894000 0x0 0x4000>;
1006 clock-names = 962 clock-names = "se";
1007 clocks = <&gc 963 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1008 pinctrl-names 964 pinctrl-names = "default";
1009 pinctrl-0 = < 965 pinctrl-0 = <&qup_i2c20_data_clk>;
1010 interrupts = 966 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1011 #address-cell 967 #address-cells = <1>;
1012 #size-cells = 968 #size-cells = <0>;
1013 interconnects 969 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1014 970 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1015 971 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1016 interconnect- 972 interconnect-names = "qup-core", "qup-config", "qup-memory";
1017 dmas = <&gpi_ 973 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1018 <&gpi_ 974 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1019 dma-names = " 975 dma-names = "tx", "rx";
1020 status = "dis 976 status = "disabled";
1021 }; 977 };
1022 978
1023 uart20: serial@894000 <<
1024 compatible = <<
1025 reg = <0 0x00 <<
1026 clock-names = <<
1027 clocks = <&gc <<
1028 pinctrl-names <<
1029 pinctrl-0 = < <<
1030 interrupts = <<
1031 interconnects <<
1032 <<
1033 <<
1034 <<
1035 interconnect- <<
1036 <<
1037 status = "dis <<
1038 }; <<
1039 <<
1040 spi20: spi@894000 { 979 spi20: spi@894000 {
1041 compatible = 980 compatible = "qcom,geni-spi";
1042 reg = <0 0x00 981 reg = <0 0x00894000 0 0x4000>;
1043 clock-names = 982 clock-names = "se";
1044 clocks = <&gc 983 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1045 interrupts = 984 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1046 pinctrl-names 985 pinctrl-names = "default";
1047 pinctrl-0 = < 986 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>;
>> 987 spi-max-frequency = <50000000>;
1048 interconnects 988 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1049 989 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
1050 interconnect- 990 interconnect-names = "qup-core", "qup-config";
1051 dmas = <&gpi_ 991 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1052 <&gpi_ 992 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1053 dma-names = " 993 dma-names = "tx", "rx";
1054 #address-cell 994 #address-cells = <1>;
1055 #size-cells = 995 #size-cells = <0>;
1056 status = "dis 996 status = "disabled";
1057 }; 997 };
1058 998
1059 i2c21: i2c@898000 { 999 i2c21: i2c@898000 {
1060 compatible = 1000 compatible = "qcom,geni-i2c";
1061 reg = <0x0 0x 1001 reg = <0x0 0x00898000 0x0 0x4000>;
1062 clock-names = 1002 clock-names = "se";
1063 clocks = <&gc 1003 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1064 pinctrl-names 1004 pinctrl-names = "default";
1065 pinctrl-0 = < 1005 pinctrl-0 = <&qup_i2c21_data_clk>;
1066 interrupts = 1006 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
1067 #address-cell 1007 #address-cells = <1>;
1068 #size-cells = 1008 #size-cells = <0>;
1069 interconnects 1009 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1070 1010 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1071 1011 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1072 interconnect- 1012 interconnect-names = "qup-core", "qup-config", "qup-memory";
1073 dmas = <&gpi_ 1013 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>,
1074 <&gpi_ 1014 <&gpi_dma2 1 6 QCOM_GPI_I2C>;
1075 dma-names = " 1015 dma-names = "tx", "rx";
1076 status = "dis 1016 status = "disabled";
1077 }; 1017 };
1078 1018
1079 spi21: spi@898000 { 1019 spi21: spi@898000 {
1080 compatible = 1020 compatible = "qcom,geni-spi";
1081 reg = <0 0x00 1021 reg = <0 0x00898000 0 0x4000>;
1082 clock-names = 1022 clock-names = "se";
1083 clocks = <&gc 1023 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1084 interrupts = 1024 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
1085 pinctrl-names 1025 pinctrl-names = "default";
1086 pinctrl-0 = < 1026 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>;
>> 1027 spi-max-frequency = <50000000>;
1087 interconnects 1028 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1088 1029 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
1089 interconnect- 1030 interconnect-names = "qup-core", "qup-config";
1090 dmas = <&gpi_ 1031 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>,
1091 <&gpi_ 1032 <&gpi_dma2 1 6 QCOM_GPI_SPI>;
1092 dma-names = " 1033 dma-names = "tx", "rx";
1093 #address-cell 1034 #address-cells = <1>;
1094 #size-cells = 1035 #size-cells = <0>;
1095 status = "dis 1036 status = "disabled";
1096 }; 1037 };
1097 }; 1038 };
1098 1039
1099 gpi_dma0: dma-controller@9000 1040 gpi_dma0: dma-controller@900000 {
1100 compatible = "qcom,sm !! 1041 compatible = "qcom,sm8450-gpi-dma";
1101 #dma-cells = <3>; 1042 #dma-cells = <3>;
1102 reg = <0 0x00900000 0 !! 1043 reg = <0 0x900000 0 0x60000>;
1103 interrupts = <GIC_SPI 1044 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
1104 <GIC_SPI 1045 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
1105 <GIC_SPI 1046 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
1106 <GIC_SPI 1047 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
1107 <GIC_SPI 1048 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
1108 <GIC_SPI 1049 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
1109 <GIC_SPI 1050 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
1110 <GIC_SPI 1051 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
1111 <GIC_SPI 1052 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
1112 <GIC_SPI 1053 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
1113 <GIC_SPI 1054 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
1114 <GIC_SPI 1055 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
1115 dma-channels = <12>; 1056 dma-channels = <12>;
1116 dma-channel-mask = <0 1057 dma-channel-mask = <0x7e>;
1117 iommus = <&apps_smmu 1058 iommus = <&apps_smmu 0x5b6 0x0>;
1118 status = "disabled"; 1059 status = "disabled";
1119 }; 1060 };
1120 1061
1121 qupv3_id_0: geniqup@9c0000 { 1062 qupv3_id_0: geniqup@9c0000 {
1122 compatible = "qcom,ge 1063 compatible = "qcom,geni-se-qup";
1123 reg = <0x0 0x009c0000 1064 reg = <0x0 0x009c0000 0x0 0x2000>;
1124 clock-names = "m-ahb" 1065 clock-names = "m-ahb", "s-ahb";
1125 clocks = <&gcc GCC_QU 1066 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1126 <&gcc GCC_QU 1067 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1127 iommus = <&apps_smmu 1068 iommus = <&apps_smmu 0x5a3 0x0>;
1128 interconnects = <&clk 1069 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>;
1129 interconnect-names = 1070 interconnect-names = "qup-core";
1130 #address-cells = <2>; 1071 #address-cells = <2>;
1131 #size-cells = <2>; 1072 #size-cells = <2>;
1132 ranges; 1073 ranges;
1133 status = "disabled"; 1074 status = "disabled";
1134 1075
1135 i2c0: i2c@980000 { 1076 i2c0: i2c@980000 {
1136 compatible = 1077 compatible = "qcom,geni-i2c";
1137 reg = <0x0 0x 1078 reg = <0x0 0x00980000 0x0 0x4000>;
1138 clock-names = 1079 clock-names = "se";
1139 clocks = <&gc 1080 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1140 pinctrl-names 1081 pinctrl-names = "default";
1141 pinctrl-0 = < 1082 pinctrl-0 = <&qup_i2c0_data_clk>;
1142 interrupts = 1083 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1143 #address-cell 1084 #address-cells = <1>;
1144 #size-cells = 1085 #size-cells = <0>;
1145 interconnects 1086 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1146 1087 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1147 1088 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1148 interconnect- 1089 interconnect-names = "qup-core", "qup-config", "qup-memory";
1149 dmas = <&gpi_ 1090 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1150 <&gpi_ 1091 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1151 dma-names = " 1092 dma-names = "tx", "rx";
1152 status = "dis 1093 status = "disabled";
1153 }; 1094 };
1154 1095
1155 spi0: spi@980000 { 1096 spi0: spi@980000 {
1156 compatible = 1097 compatible = "qcom,geni-spi";
1157 reg = <0x0 0x 1098 reg = <0x0 0x00980000 0x0 0x4000>;
1158 clock-names = 1099 clock-names = "se";
1159 clocks = <&gc 1100 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1160 interrupts = 1101 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1161 pinctrl-names 1102 pinctrl-names = "default";
1162 pinctrl-0 = < 1103 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1163 power-domains !! 1104 power-domains = <&rpmhpd SM8450_CX>;
1164 operating-poi 1105 operating-points-v2 = <&qup_opp_table_100mhz>;
1165 interconnects 1106 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1166 1107 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1167 1108 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1168 interconnect- 1109 interconnect-names = "qup-core", "qup-config", "qup-memory";
1169 dmas = <&gpi_ 1110 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1170 <&gpi_ 1111 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1171 dma-names = " 1112 dma-names = "tx", "rx";
1172 #address-cell 1113 #address-cells = <1>;
1173 #size-cells = 1114 #size-cells = <0>;
1174 status = "dis 1115 status = "disabled";
1175 }; 1116 };
1176 1117
1177 i2c1: i2c@984000 { 1118 i2c1: i2c@984000 {
1178 compatible = 1119 compatible = "qcom,geni-i2c";
1179 reg = <0x0 0x 1120 reg = <0x0 0x00984000 0x0 0x4000>;
1180 clock-names = 1121 clock-names = "se";
1181 clocks = <&gc 1122 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1182 pinctrl-names 1123 pinctrl-names = "default";
1183 pinctrl-0 = < 1124 pinctrl-0 = <&qup_i2c1_data_clk>;
1184 interrupts = 1125 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1185 #address-cell 1126 #address-cells = <1>;
1186 #size-cells = 1127 #size-cells = <0>;
1187 interconnects 1128 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1188 1129 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1189 1130 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1190 interconnect- 1131 interconnect-names = "qup-core", "qup-config", "qup-memory";
1191 dmas = <&gpi_ 1132 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1192 <&gpi_ 1133 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1193 dma-names = " 1134 dma-names = "tx", "rx";
1194 status = "dis 1135 status = "disabled";
1195 }; 1136 };
1196 1137
1197 spi1: spi@984000 { 1138 spi1: spi@984000 {
1198 compatible = 1139 compatible = "qcom,geni-spi";
1199 reg = <0x0 0x 1140 reg = <0x0 0x00984000 0x0 0x4000>;
1200 clock-names = 1141 clock-names = "se";
1201 clocks = <&gc 1142 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1202 interrupts = 1143 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1203 pinctrl-names 1144 pinctrl-names = "default";
1204 pinctrl-0 = < 1145 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1205 interconnects 1146 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1206 1147 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1207 1148 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1208 interconnect- 1149 interconnect-names = "qup-core", "qup-config", "qup-memory";
1209 dmas = <&gpi_ 1150 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1210 <&gpi_ 1151 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1211 dma-names = " 1152 dma-names = "tx", "rx";
1212 #address-cell 1153 #address-cells = <1>;
1213 #size-cells = 1154 #size-cells = <0>;
1214 status = "dis 1155 status = "disabled";
1215 }; 1156 };
1216 1157
1217 i2c2: i2c@988000 { 1158 i2c2: i2c@988000 {
1218 compatible = 1159 compatible = "qcom,geni-i2c";
1219 reg = <0x0 0x 1160 reg = <0x0 0x00988000 0x0 0x4000>;
1220 clock-names = 1161 clock-names = "se";
1221 clocks = <&gc 1162 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1222 pinctrl-names 1163 pinctrl-names = "default";
1223 pinctrl-0 = < 1164 pinctrl-0 = <&qup_i2c2_data_clk>;
1224 interrupts = 1165 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1225 #address-cell 1166 #address-cells = <1>;
1226 #size-cells = 1167 #size-cells = <0>;
1227 interconnects 1168 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1228 1169 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1229 1170 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1230 interconnect- 1171 interconnect-names = "qup-core", "qup-config", "qup-memory";
1231 dmas = <&gpi_ 1172 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1232 <&gpi_ 1173 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1233 dma-names = " 1174 dma-names = "tx", "rx";
1234 status = "dis 1175 status = "disabled";
1235 }; 1176 };
1236 1177
1237 spi2: spi@988000 { 1178 spi2: spi@988000 {
1238 compatible = 1179 compatible = "qcom,geni-spi";
1239 reg = <0x0 0x 1180 reg = <0x0 0x00988000 0x0 0x4000>;
1240 clock-names = 1181 clock-names = "se";
1241 clocks = <&gc 1182 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1242 interrupts = 1183 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1243 pinctrl-names 1184 pinctrl-names = "default";
1244 pinctrl-0 = < 1185 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1245 interconnects 1186 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1246 1187 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1247 1188 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1248 interconnect- 1189 interconnect-names = "qup-core", "qup-config", "qup-memory";
1249 dmas = <&gpi_ 1190 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1250 <&gpi_ 1191 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1251 dma-names = " 1192 dma-names = "tx", "rx";
1252 #address-cell 1193 #address-cells = <1>;
1253 #size-cells = 1194 #size-cells = <0>;
1254 status = "dis 1195 status = "disabled";
1255 }; 1196 };
1256 1197
1257 1198
1258 i2c3: i2c@98c000 { 1199 i2c3: i2c@98c000 {
1259 compatible = 1200 compatible = "qcom,geni-i2c";
1260 reg = <0x0 0x 1201 reg = <0x0 0x0098c000 0x0 0x4000>;
1261 clock-names = 1202 clock-names = "se";
1262 clocks = <&gc 1203 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1263 pinctrl-names 1204 pinctrl-names = "default";
1264 pinctrl-0 = < 1205 pinctrl-0 = <&qup_i2c3_data_clk>;
1265 interrupts = 1206 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1266 #address-cell 1207 #address-cells = <1>;
1267 #size-cells = 1208 #size-cells = <0>;
1268 interconnects 1209 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1269 1210 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1270 1211 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1271 interconnect- 1212 interconnect-names = "qup-core", "qup-config", "qup-memory";
1272 dmas = <&gpi_ 1213 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1273 <&gpi_ 1214 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1274 dma-names = " 1215 dma-names = "tx", "rx";
1275 status = "dis 1216 status = "disabled";
1276 }; 1217 };
1277 1218
1278 spi3: spi@98c000 { 1219 spi3: spi@98c000 {
1279 compatible = 1220 compatible = "qcom,geni-spi";
1280 reg = <0x0 0x 1221 reg = <0x0 0x0098c000 0x0 0x4000>;
1281 clock-names = 1222 clock-names = "se";
1282 clocks = <&gc 1223 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1283 interrupts = 1224 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1284 pinctrl-names 1225 pinctrl-names = "default";
1285 pinctrl-0 = < 1226 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1286 interconnects 1227 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1287 1228 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1288 1229 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1289 interconnect- 1230 interconnect-names = "qup-core", "qup-config", "qup-memory";
1290 dmas = <&gpi_ 1231 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1291 <&gpi_ 1232 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1292 dma-names = " 1233 dma-names = "tx", "rx";
1293 #address-cell 1234 #address-cells = <1>;
1294 #size-cells = 1235 #size-cells = <0>;
1295 status = "dis 1236 status = "disabled";
1296 }; 1237 };
1297 1238
1298 i2c4: i2c@990000 { 1239 i2c4: i2c@990000 {
1299 compatible = 1240 compatible = "qcom,geni-i2c";
1300 reg = <0x0 0x 1241 reg = <0x0 0x00990000 0x0 0x4000>;
1301 clock-names = 1242 clock-names = "se";
1302 clocks = <&gc 1243 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1303 pinctrl-names 1244 pinctrl-names = "default";
1304 pinctrl-0 = < 1245 pinctrl-0 = <&qup_i2c4_data_clk>;
1305 interrupts = 1246 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1306 #address-cell 1247 #address-cells = <1>;
1307 #size-cells = 1248 #size-cells = <0>;
1308 interconnects 1249 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1309 1250 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1310 1251 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1311 interconnect- 1252 interconnect-names = "qup-core", "qup-config", "qup-memory";
1312 dmas = <&gpi_ 1253 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1313 <&gpi_ 1254 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1314 dma-names = " 1255 dma-names = "tx", "rx";
1315 status = "dis 1256 status = "disabled";
1316 }; 1257 };
1317 1258
1318 spi4: spi@990000 { 1259 spi4: spi@990000 {
1319 compatible = 1260 compatible = "qcom,geni-spi";
1320 reg = <0x0 0x 1261 reg = <0x0 0x00990000 0x0 0x4000>;
1321 clock-names = 1262 clock-names = "se";
1322 clocks = <&gc 1263 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1323 interrupts = 1264 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1324 pinctrl-names 1265 pinctrl-names = "default";
1325 pinctrl-0 = < 1266 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1326 power-domains !! 1267 power-domains = <&rpmhpd SM8450_CX>;
1327 operating-poi 1268 operating-points-v2 = <&qup_opp_table_100mhz>;
1328 interconnects 1269 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1329 1270 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1330 1271 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1331 interconnect- 1272 interconnect-names = "qup-core", "qup-config", "qup-memory";
1332 dmas = <&gpi_ 1273 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1333 <&gpi_ 1274 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1334 dma-names = " 1275 dma-names = "tx", "rx";
1335 #address-cell 1276 #address-cells = <1>;
1336 #size-cells = 1277 #size-cells = <0>;
1337 status = "dis 1278 status = "disabled";
1338 }; 1279 };
1339 1280
1340 i2c5: i2c@994000 { 1281 i2c5: i2c@994000 {
1341 compatible = 1282 compatible = "qcom,geni-i2c";
1342 reg = <0x0 0x 1283 reg = <0x0 0x00994000 0x0 0x4000>;
1343 clock-names = 1284 clock-names = "se";
1344 clocks = <&gc 1285 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1345 pinctrl-names 1286 pinctrl-names = "default";
1346 pinctrl-0 = < 1287 pinctrl-0 = <&qup_i2c5_data_clk>;
1347 interrupts = 1288 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1348 #address-cell 1289 #address-cells = <1>;
1349 #size-cells = 1290 #size-cells = <0>;
1350 interconnects 1291 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1351 1292 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1352 1293 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1353 interconnect- 1294 interconnect-names = "qup-core", "qup-config", "qup-memory";
1354 dmas = <&gpi_ 1295 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1355 <&gpi_ 1296 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1356 dma-names = " 1297 dma-names = "tx", "rx";
1357 status = "dis 1298 status = "disabled";
1358 }; 1299 };
1359 1300
1360 spi5: spi@994000 { 1301 spi5: spi@994000 {
1361 compatible = 1302 compatible = "qcom,geni-spi";
1362 reg = <0x0 0x 1303 reg = <0x0 0x00994000 0x0 0x4000>;
1363 clock-names = 1304 clock-names = "se";
1364 clocks = <&gc 1305 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1365 interrupts = 1306 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1366 pinctrl-names 1307 pinctrl-names = "default";
1367 pinctrl-0 = < 1308 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1368 interconnects 1309 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1369 1310 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1370 1311 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1371 interconnect- 1312 interconnect-names = "qup-core", "qup-config", "qup-memory";
1372 dmas = <&gpi_ 1313 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1373 <&gpi_ 1314 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1374 dma-names = " 1315 dma-names = "tx", "rx";
1375 #address-cell 1316 #address-cells = <1>;
1376 #size-cells = 1317 #size-cells = <0>;
1377 status = "dis 1318 status = "disabled";
1378 }; 1319 };
1379 1320
1380 1321
1381 i2c6: i2c@998000 { 1322 i2c6: i2c@998000 {
1382 compatible = 1323 compatible = "qcom,geni-i2c";
1383 reg = <0x0 0x !! 1324 reg = <0x0 0x998000 0x0 0x4000>;
1384 clock-names = 1325 clock-names = "se";
1385 clocks = <&gc 1326 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1386 pinctrl-names 1327 pinctrl-names = "default";
1387 pinctrl-0 = < 1328 pinctrl-0 = <&qup_i2c6_data_clk>;
1388 interrupts = 1329 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1389 #address-cell 1330 #address-cells = <1>;
1390 #size-cells = 1331 #size-cells = <0>;
1391 interconnects 1332 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1392 1333 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1393 1334 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1394 interconnect- 1335 interconnect-names = "qup-core", "qup-config", "qup-memory";
1395 dmas = <&gpi_ 1336 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1396 <&gpi_ 1337 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1397 dma-names = " 1338 dma-names = "tx", "rx";
1398 status = "dis 1339 status = "disabled";
1399 }; 1340 };
1400 1341
1401 spi6: spi@998000 { 1342 spi6: spi@998000 {
1402 compatible = 1343 compatible = "qcom,geni-spi";
1403 reg = <0x0 0x !! 1344 reg = <0x0 0x998000 0x0 0x4000>;
1404 clock-names = 1345 clock-names = "se";
1405 clocks = <&gc 1346 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1406 interrupts = 1347 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1407 pinctrl-names 1348 pinctrl-names = "default";
1408 pinctrl-0 = < 1349 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1409 interconnects 1350 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1410 1351 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1411 1352 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1412 interconnect- 1353 interconnect-names = "qup-core", "qup-config", "qup-memory";
1413 dmas = <&gpi_ 1354 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1414 <&gpi_ 1355 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1415 dma-names = " 1356 dma-names = "tx", "rx";
1416 #address-cell 1357 #address-cells = <1>;
1417 #size-cells = 1358 #size-cells = <0>;
1418 status = "dis 1359 status = "disabled";
1419 }; 1360 };
1420 1361
1421 uart7: serial@99c000 1362 uart7: serial@99c000 {
1422 compatible = 1363 compatible = "qcom,geni-debug-uart";
1423 reg = <0 0x00 1364 reg = <0 0x0099c000 0 0x4000>;
1424 clock-names = 1365 clock-names = "se";
1425 clocks = <&gc 1366 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1426 pinctrl-names 1367 pinctrl-names = "default";
1427 pinctrl-0 = < 1368 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>;
1428 interrupts = 1369 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1429 interconnects !! 1370 #address-cells = <1>;
1430 !! 1371 #size-cells = <0>;
1431 <<
1432 <<
1433 interconnect- <<
1434 <<
1435 status = "dis 1372 status = "disabled";
1436 }; 1373 };
1437 }; 1374 };
1438 1375
1439 gpi_dma1: dma-controller@a000 1376 gpi_dma1: dma-controller@a00000 {
1440 compatible = "qcom,sm !! 1377 compatible = "qcom,sm8450-gpi-dma";
1441 #dma-cells = <3>; 1378 #dma-cells = <3>;
1442 reg = <0 0x00a00000 0 !! 1379 reg = <0 0xa00000 0 0x60000>;
1443 interrupts = <GIC_SPI 1380 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1444 <GIC_SPI 1381 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1445 <GIC_SPI 1382 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1446 <GIC_SPI 1383 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1447 <GIC_SPI 1384 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1448 <GIC_SPI 1385 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1449 <GIC_SPI 1386 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1450 <GIC_SPI 1387 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1451 <GIC_SPI 1388 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1452 <GIC_SPI 1389 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1453 <GIC_SPI 1390 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1454 <GIC_SPI 1391 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
1455 dma-channels = <12>; 1392 dma-channels = <12>;
1456 dma-channel-mask = <0 1393 dma-channel-mask = <0x7e>;
1457 iommus = <&apps_smmu 1394 iommus = <&apps_smmu 0x56 0x0>;
1458 status = "disabled"; 1395 status = "disabled";
1459 }; 1396 };
1460 1397
1461 qupv3_id_1: geniqup@ac0000 { 1398 qupv3_id_1: geniqup@ac0000 {
1462 compatible = "qcom,ge 1399 compatible = "qcom,geni-se-qup";
1463 reg = <0x0 0x00ac0000 1400 reg = <0x0 0x00ac0000 0x0 0x6000>;
1464 clock-names = "m-ahb" 1401 clock-names = "m-ahb", "s-ahb";
1465 clocks = <&gcc GCC_QU 1402 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1466 <&gcc GCC_QU 1403 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1467 iommus = <&apps_smmu 1404 iommus = <&apps_smmu 0x43 0x0>;
1468 interconnects = <&clk 1405 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>;
1469 interconnect-names = 1406 interconnect-names = "qup-core";
1470 #address-cells = <2>; 1407 #address-cells = <2>;
1471 #size-cells = <2>; 1408 #size-cells = <2>;
1472 ranges; 1409 ranges;
1473 status = "disabled"; 1410 status = "disabled";
1474 1411
1475 i2c8: i2c@a80000 { 1412 i2c8: i2c@a80000 {
1476 compatible = 1413 compatible = "qcom,geni-i2c";
1477 reg = <0x0 0x 1414 reg = <0x0 0x00a80000 0x0 0x4000>;
1478 clock-names = 1415 clock-names = "se";
1479 clocks = <&gc 1416 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1480 pinctrl-names 1417 pinctrl-names = "default";
1481 pinctrl-0 = < 1418 pinctrl-0 = <&qup_i2c8_data_clk>;
1482 interrupts = 1419 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1483 #address-cell 1420 #address-cells = <1>;
1484 #size-cells = 1421 #size-cells = <0>;
1485 interconnects 1422 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1486 1423 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1487 1424 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1488 interconnect- 1425 interconnect-names = "qup-core", "qup-config", "qup-memory";
1489 dmas = <&gpi_ 1426 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1490 <&gpi_ 1427 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1491 dma-names = " 1428 dma-names = "tx", "rx";
1492 status = "dis 1429 status = "disabled";
1493 }; 1430 };
1494 1431
1495 spi8: spi@a80000 { 1432 spi8: spi@a80000 {
1496 compatible = 1433 compatible = "qcom,geni-spi";
1497 reg = <0x0 0x 1434 reg = <0x0 0x00a80000 0x0 0x4000>;
1498 clock-names = 1435 clock-names = "se";
1499 clocks = <&gc 1436 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1500 interrupts = 1437 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1501 pinctrl-names 1438 pinctrl-names = "default";
1502 pinctrl-0 = < 1439 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1503 interconnects 1440 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1504 1441 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1505 1442 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1506 interconnect- 1443 interconnect-names = "qup-core", "qup-config", "qup-memory";
1507 dmas = <&gpi_ 1444 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1508 <&gpi_ 1445 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1509 dma-names = " 1446 dma-names = "tx", "rx";
1510 #address-cell 1447 #address-cells = <1>;
1511 #size-cells = 1448 #size-cells = <0>;
1512 status = "dis 1449 status = "disabled";
1513 }; 1450 };
1514 1451
1515 i2c9: i2c@a84000 { 1452 i2c9: i2c@a84000 {
1516 compatible = 1453 compatible = "qcom,geni-i2c";
1517 reg = <0x0 0x 1454 reg = <0x0 0x00a84000 0x0 0x4000>;
1518 clock-names = 1455 clock-names = "se";
1519 clocks = <&gc 1456 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1520 pinctrl-names 1457 pinctrl-names = "default";
1521 pinctrl-0 = < 1458 pinctrl-0 = <&qup_i2c9_data_clk>;
1522 interrupts = 1459 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1523 #address-cell 1460 #address-cells = <1>;
1524 #size-cells = 1461 #size-cells = <0>;
1525 interconnects 1462 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1526 1463 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1527 1464 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1528 interconnect- 1465 interconnect-names = "qup-core", "qup-config", "qup-memory";
1529 dmas = <&gpi_ 1466 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1530 <&gpi_ 1467 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1531 dma-names = " 1468 dma-names = "tx", "rx";
1532 status = "dis 1469 status = "disabled";
1533 }; 1470 };
1534 1471
1535 spi9: spi@a84000 { 1472 spi9: spi@a84000 {
1536 compatible = 1473 compatible = "qcom,geni-spi";
1537 reg = <0x0 0x 1474 reg = <0x0 0x00a84000 0x0 0x4000>;
1538 clock-names = 1475 clock-names = "se";
1539 clocks = <&gc 1476 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1540 interrupts = 1477 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1541 pinctrl-names 1478 pinctrl-names = "default";
1542 pinctrl-0 = < 1479 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1543 interconnects 1480 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1544 1481 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1545 1482 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1546 interconnect- 1483 interconnect-names = "qup-core", "qup-config", "qup-memory";
1547 dmas = <&gpi_ 1484 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1548 <&gpi_ 1485 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1549 dma-names = " 1486 dma-names = "tx", "rx";
1550 #address-cell 1487 #address-cells = <1>;
1551 #size-cells = 1488 #size-cells = <0>;
1552 status = "dis 1489 status = "disabled";
1553 }; 1490 };
1554 1491
1555 i2c10: i2c@a88000 { 1492 i2c10: i2c@a88000 {
1556 compatible = 1493 compatible = "qcom,geni-i2c";
1557 reg = <0x0 0x 1494 reg = <0x0 0x00a88000 0x0 0x4000>;
1558 clock-names = 1495 clock-names = "se";
1559 clocks = <&gc 1496 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1560 pinctrl-names 1497 pinctrl-names = "default";
1561 pinctrl-0 = < 1498 pinctrl-0 = <&qup_i2c10_data_clk>;
1562 interrupts = 1499 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1563 #address-cell 1500 #address-cells = <1>;
1564 #size-cells = 1501 #size-cells = <0>;
1565 interconnects 1502 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1566 1503 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1567 1504 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1568 interconnect- 1505 interconnect-names = "qup-core", "qup-config", "qup-memory";
1569 dmas = <&gpi_ 1506 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1570 <&gpi_ 1507 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1571 dma-names = " 1508 dma-names = "tx", "rx";
1572 status = "dis 1509 status = "disabled";
1573 }; 1510 };
1574 1511
1575 spi10: spi@a88000 { 1512 spi10: spi@a88000 {
1576 compatible = 1513 compatible = "qcom,geni-spi";
1577 reg = <0x0 0x 1514 reg = <0x0 0x00a88000 0x0 0x4000>;
1578 clock-names = 1515 clock-names = "se";
1579 clocks = <&gc 1516 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1580 interrupts = 1517 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1581 pinctrl-names 1518 pinctrl-names = "default";
1582 pinctrl-0 = < 1519 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1583 interconnects 1520 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1584 1521 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1585 1522 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1586 interconnect- 1523 interconnect-names = "qup-core", "qup-config", "qup-memory";
1587 dmas = <&gpi_ 1524 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1588 <&gpi_ 1525 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1589 dma-names = " 1526 dma-names = "tx", "rx";
1590 #address-cell 1527 #address-cells = <1>;
1591 #size-cells = 1528 #size-cells = <0>;
1592 status = "dis 1529 status = "disabled";
1593 }; 1530 };
1594 1531
1595 i2c11: i2c@a8c000 { 1532 i2c11: i2c@a8c000 {
1596 compatible = 1533 compatible = "qcom,geni-i2c";
1597 reg = <0x0 0x 1534 reg = <0x0 0x00a8c000 0x0 0x4000>;
1598 clock-names = 1535 clock-names = "se";
1599 clocks = <&gc 1536 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1600 pinctrl-names 1537 pinctrl-names = "default";
1601 pinctrl-0 = < 1538 pinctrl-0 = <&qup_i2c11_data_clk>;
1602 interrupts = 1539 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1603 #address-cell 1540 #address-cells = <1>;
1604 #size-cells = 1541 #size-cells = <0>;
1605 interconnects 1542 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1606 1543 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1607 1544 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1608 interconnect- 1545 interconnect-names = "qup-core", "qup-config", "qup-memory";
1609 dmas = <&gpi_ 1546 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1610 <&gpi_ 1547 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1611 dma-names = " 1548 dma-names = "tx", "rx";
1612 status = "dis 1549 status = "disabled";
1613 }; 1550 };
1614 1551
1615 spi11: spi@a8c000 { 1552 spi11: spi@a8c000 {
1616 compatible = 1553 compatible = "qcom,geni-spi";
1617 reg = <0x0 0x 1554 reg = <0x0 0x00a8c000 0x0 0x4000>;
1618 clock-names = 1555 clock-names = "se";
1619 clocks = <&gc 1556 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1620 interrupts = 1557 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1621 pinctrl-names 1558 pinctrl-names = "default";
1622 pinctrl-0 = < 1559 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1623 interconnects 1560 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1624 1561 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1625 1562 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1626 interconnect- 1563 interconnect-names = "qup-core", "qup-config", "qup-memory";
1627 dmas = <&gpi_ 1564 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1628 <&gpi_ 1565 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1629 dma-names = " 1566 dma-names = "tx", "rx";
1630 #address-cell 1567 #address-cells = <1>;
1631 #size-cells = 1568 #size-cells = <0>;
1632 status = "dis 1569 status = "disabled";
1633 }; 1570 };
1634 1571
1635 i2c12: i2c@a90000 { 1572 i2c12: i2c@a90000 {
1636 compatible = 1573 compatible = "qcom,geni-i2c";
1637 reg = <0x0 0x 1574 reg = <0x0 0x00a90000 0x0 0x4000>;
1638 clock-names = 1575 clock-names = "se";
1639 clocks = <&gc 1576 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1640 pinctrl-names 1577 pinctrl-names = "default";
1641 pinctrl-0 = < 1578 pinctrl-0 = <&qup_i2c12_data_clk>;
1642 interrupts = 1579 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1643 #address-cell 1580 #address-cells = <1>;
1644 #size-cells = 1581 #size-cells = <0>;
1645 interconnects 1582 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1646 1583 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1647 1584 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1648 interconnect- 1585 interconnect-names = "qup-core", "qup-config", "qup-memory";
1649 dmas = <&gpi_ 1586 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1650 <&gpi_ 1587 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1651 dma-names = " 1588 dma-names = "tx", "rx";
1652 status = "dis 1589 status = "disabled";
1653 }; 1590 };
1654 1591
1655 spi12: spi@a90000 { 1592 spi12: spi@a90000 {
1656 compatible = 1593 compatible = "qcom,geni-spi";
1657 reg = <0x0 0x 1594 reg = <0x0 0x00a90000 0x0 0x4000>;
1658 clock-names = 1595 clock-names = "se";
1659 clocks = <&gc 1596 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1660 interrupts = 1597 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1661 pinctrl-names 1598 pinctrl-names = "default";
1662 pinctrl-0 = < 1599 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1663 interconnects 1600 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1664 1601 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1665 1602 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1666 interconnect- 1603 interconnect-names = "qup-core", "qup-config", "qup-memory";
1667 dmas = <&gpi_ 1604 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1668 <&gpi_ 1605 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1669 dma-names = " 1606 dma-names = "tx", "rx";
1670 #address-cell 1607 #address-cells = <1>;
1671 #size-cells = 1608 #size-cells = <0>;
1672 status = "dis 1609 status = "disabled";
1673 }; 1610 };
1674 1611
1675 i2c13: i2c@a94000 { 1612 i2c13: i2c@a94000 {
1676 compatible = 1613 compatible = "qcom,geni-i2c";
1677 reg = <0 0x00 1614 reg = <0 0x00a94000 0 0x4000>;
1678 clock-names = 1615 clock-names = "se";
1679 clocks = <&gc 1616 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1680 pinctrl-names 1617 pinctrl-names = "default";
1681 pinctrl-0 = < 1618 pinctrl-0 = <&qup_i2c13_data_clk>;
1682 interrupts = 1619 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1683 interconnects 1620 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1684 1621 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1685 1622 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1686 interconnect- 1623 interconnect-names = "qup-core", "qup-config", "qup-memory";
1687 dmas = <&gpi_ 1624 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1688 <&gpi_ 1625 <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1689 dma-names = " 1626 dma-names = "tx", "rx";
1690 #address-cell 1627 #address-cells = <1>;
1691 #size-cells = 1628 #size-cells = <0>;
1692 status = "dis 1629 status = "disabled";
1693 }; 1630 };
1694 1631
1695 spi13: spi@a94000 { 1632 spi13: spi@a94000 {
1696 compatible = 1633 compatible = "qcom,geni-spi";
1697 reg = <0x0 0x 1634 reg = <0x0 0x00a94000 0x0 0x4000>;
1698 clock-names = 1635 clock-names = "se";
1699 clocks = <&gc 1636 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1700 interrupts = 1637 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1701 pinctrl-names 1638 pinctrl-names = "default";
1702 pinctrl-0 = < 1639 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1703 interconnects 1640 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1704 1641 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1705 1642 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1706 interconnect- 1643 interconnect-names = "qup-core", "qup-config", "qup-memory";
1707 dmas = <&gpi_ 1644 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1708 <&gpi_ 1645 <&gpi_dma1 1 5 QCOM_GPI_SPI>;
1709 dma-names = " 1646 dma-names = "tx", "rx";
1710 #address-cell 1647 #address-cells = <1>;
1711 #size-cells = 1648 #size-cells = <0>;
1712 status = "dis 1649 status = "disabled";
1713 }; 1650 };
1714 1651
1715 i2c14: i2c@a98000 { 1652 i2c14: i2c@a98000 {
1716 compatible = 1653 compatible = "qcom,geni-i2c";
1717 reg = <0 0x00 1654 reg = <0 0x00a98000 0 0x4000>;
1718 clock-names = 1655 clock-names = "se";
1719 clocks = <&gc 1656 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1720 pinctrl-names 1657 pinctrl-names = "default";
1721 pinctrl-0 = < 1658 pinctrl-0 = <&qup_i2c14_data_clk>;
1722 interrupts = 1659 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
1723 interconnects 1660 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1724 1661 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1725 1662 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1726 interconnect- 1663 interconnect-names = "qup-core", "qup-config", "qup-memory";
1727 dmas = <&gpi_ 1664 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
1728 <&gpi_ 1665 <&gpi_dma1 1 6 QCOM_GPI_I2C>;
1729 dma-names = " 1666 dma-names = "tx", "rx";
1730 #address-cell 1667 #address-cells = <1>;
1731 #size-cells = 1668 #size-cells = <0>;
1732 status = "dis 1669 status = "disabled";
1733 }; 1670 };
1734 1671
1735 spi14: spi@a98000 { 1672 spi14: spi@a98000 {
1736 compatible = 1673 compatible = "qcom,geni-spi";
1737 reg = <0x0 0x 1674 reg = <0x0 0x00a98000 0x0 0x4000>;
1738 clock-names = 1675 clock-names = "se";
1739 clocks = <&gc 1676 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1740 interrupts = 1677 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
1741 pinctrl-names 1678 pinctrl-names = "default";
1742 pinctrl-0 = < 1679 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
1743 interconnects 1680 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1744 1681 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1745 1682 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1746 interconnect- 1683 interconnect-names = "qup-core", "qup-config", "qup-memory";
1747 dmas = <&gpi_ 1684 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
1748 <&gpi_ 1685 <&gpi_dma1 1 6 QCOM_GPI_SPI>;
1749 dma-names = " 1686 dma-names = "tx", "rx";
1750 #address-cell 1687 #address-cells = <1>;
1751 #size-cells = 1688 #size-cells = <0>;
1752 status = "dis 1689 status = "disabled";
1753 }; 1690 };
1754 }; 1691 };
1755 1692
1756 rng: rng@10c3000 { !! 1693 pcie0: pci@1c00000 {
1757 compatible = "qcom,sm <<
1758 reg = <0 0x010c3000 0 <<
1759 }; <<
1760 <<
1761 pcie0: pcie@1c00000 { <<
1762 compatible = "qcom,pc 1694 compatible = "qcom,pcie-sm8450-pcie0";
1763 reg = <0 0x01c00000 0 1695 reg = <0 0x01c00000 0 0x3000>,
1764 <0 0x60000000 0 1696 <0 0x60000000 0 0xf1d>,
1765 <0 0x60000f20 0 1697 <0 0x60000f20 0 0xa8>,
1766 <0 0x60001000 0 1698 <0 0x60001000 0 0x1000>,
1767 <0 0x60100000 0 1699 <0 0x60100000 0 0x100000>;
1768 reg-names = "parf", " 1700 reg-names = "parf", "dbi", "elbi", "atu", "config";
1769 device_type = "pci"; 1701 device_type = "pci";
1770 linux,pci-domain = <0 1702 linux,pci-domain = <0>;
1771 bus-range = <0x00 0xf 1703 bus-range = <0x00 0xff>;
1772 num-lanes = <1>; 1704 num-lanes = <1>;
1773 1705
1774 #address-cells = <3>; 1706 #address-cells = <3>;
1775 #size-cells = <2>; 1707 #size-cells = <2>;
1776 1708
1777 ranges = <0x01000000 !! 1709 ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
1778 <0x02000000 !! 1710 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>;
1779 1711
1780 msi-map = <0x0 &gic_i !! 1712 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
1781 <0x100 &gic !! 1713 interrupt-names = "msi";
1782 msi-map-mask = <0xff0 <<
1783 interrupts = <GIC_SPI <<
1784 <GIC_SPI <<
1785 <GIC_SPI <<
1786 <GIC_SPI <<
1787 <GIC_SPI <<
1788 <GIC_SPI <<
1789 <GIC_SPI <<
1790 <GIC_SPI <<
1791 interrupt-names = "ms <<
1792 "ms <<
1793 "ms <<
1794 "ms <<
1795 "ms <<
1796 "ms <<
1797 "ms <<
1798 "ms <<
1799 #interrupt-cells = <1 1714 #interrupt-cells = <1>;
1800 interrupt-map-mask = 1715 interrupt-map-mask = <0 0 0 0x7>;
1801 interrupt-map = <0 0 1716 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1802 <0 0 1717 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1803 <0 0 1718 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1804 <0 0 1719 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1805 1720
1806 interconnects = <&pci <<
1807 &mc_ <<
1808 <&gem <<
1809 &con <<
1810 interconnect-names = <<
1811 <<
1812 clocks = <&gcc GCC_PC 1721 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1813 <&gcc GCC_PC 1722 <&gcc GCC_PCIE_0_PIPE_CLK_SRC>,
1814 <&pcie0_phy> !! 1723 <&pcie0_lane>,
1815 <&rpmhcc RPM 1724 <&rpmhcc RPMH_CXO_CLK>,
1816 <&gcc GCC_PC 1725 <&gcc GCC_PCIE_0_AUX_CLK>,
1817 <&gcc GCC_PC 1726 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1818 <&gcc GCC_PC 1727 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1819 <&gcc GCC_PC 1728 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1820 <&gcc GCC_PC 1729 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
1821 <&gcc GCC_DD 1730 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1822 <&gcc GCC_AG 1731 <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
1823 <&gcc GCC_AG 1732 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
1824 clock-names = "pipe", 1733 clock-names = "pipe",
1825 "pipe_m 1734 "pipe_mux",
1826 "phy_pi 1735 "phy_pipe",
1827 "ref", 1736 "ref",
1828 "aux", 1737 "aux",
1829 "cfg", 1738 "cfg",
1830 "bus_ma 1739 "bus_master",
1831 "bus_sl 1740 "bus_slave",
1832 "slave_ 1741 "slave_q2a",
1833 "ddrss_ 1742 "ddrss_sf_tbu",
1834 "aggre0 1743 "aggre0",
1835 "aggre1 1744 "aggre1";
1836 1745
>> 1746 iommus = <&apps_smmu 0x1c00 0x7f>;
1837 iommu-map = <0x0 &a 1747 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
1838 <0x100 &a 1748 <0x100 &apps_smmu 0x1c01 0x1>;
1839 1749
1840 resets = <&gcc GCC_PC 1750 resets = <&gcc GCC_PCIE_0_BCR>;
1841 reset-names = "pci"; 1751 reset-names = "pci";
1842 1752
1843 power-domains = <&gcc 1753 power-domains = <&gcc PCIE_0_GDSC>;
>> 1754 power-domain-names = "gdsc";
1844 1755
1845 phys = <&pcie0_phy>; !! 1756 phys = <&pcie0_lane>;
1846 phy-names = "pciephy" 1757 phy-names = "pciephy";
1847 1758
1848 perst-gpios = <&tlmm 1759 perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
1849 wake-gpios = <&tlmm 9 1760 wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
1850 1761
1851 pinctrl-names = "defa 1762 pinctrl-names = "default";
1852 pinctrl-0 = <&pcie0_d 1763 pinctrl-0 = <&pcie0_default_state>;
1853 1764
1854 operating-points-v2 = <<
1855 <<
1856 status = "disabled"; 1765 status = "disabled";
1857 <<
1858 pcie0_opp_table: opp- <<
1859 compatible = <<
1860 <<
1861 /* GEN 1 x1 * <<
1862 opp-2500000 { <<
1863 opp-h <<
1864 requi <<
1865 opp-p <<
1866 }; <<
1867 <<
1868 /* GEN 2 x1 * <<
1869 opp-5000000 { <<
1870 opp-h <<
1871 requi <<
1872 opp-p <<
1873 }; <<
1874 <<
1875 /* GEN 3 x1 * <<
1876 opp-8000000 { <<
1877 opp-h <<
1878 requi <<
1879 opp-p <<
1880 }; <<
1881 }; <<
1882 <<
1883 pcie@0 { <<
1884 device_type = <<
1885 reg = <0x0 0x <<
1886 bus-range = < <<
1887 <<
1888 #address-cell <<
1889 #size-cells = <<
1890 ranges; <<
1891 }; <<
1892 }; 1766 };
1893 1767
1894 pcie0_phy: phy@1c06000 { 1768 pcie0_phy: phy@1c06000 {
1895 compatible = "qcom,sm 1769 compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy";
1896 reg = <0 0x01c06000 0 !! 1770 reg = <0 0x01c06000 0 0x200>;
1897 !! 1771 #address-cells = <2>;
>> 1772 #size-cells = <2>;
>> 1773 ranges;
1898 clocks = <&gcc GCC_PC 1774 clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
1899 <&gcc GCC_PC 1775 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1900 <&gcc GCC_PC 1776 <&gcc GCC_PCIE_0_CLKREF_EN>,
1901 <&gcc GCC_PC !! 1777 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
1902 <&gcc GCC_PC !! 1778 clock-names = "aux", "cfg_ahb", "ref", "refgen";
1903 clock-names = "aux", <<
1904 "cfg_ah <<
1905 "ref", <<
1906 "rchng" <<
1907 "pipe"; <<
1908 <<
1909 clock-output-names = <<
1910 #clock-cells = <0>; <<
1911 <<
1912 #phy-cells = <0>; <<
1913 1779
1914 resets = <&gcc GCC_PC 1780 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1915 reset-names = "phy"; 1781 reset-names = "phy";
1916 1782
1917 assigned-clocks = <&g 1783 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
1918 assigned-clock-rates 1784 assigned-clock-rates = <100000000>;
1919 1785
1920 status = "disabled"; 1786 status = "disabled";
>> 1787
>> 1788 pcie0_lane: phy@1c06200 {
>> 1789 reg = <0 0x1c06e00 0 0x200>, /* tx */
>> 1790 <0 0x1c07000 0 0x200>, /* rx */
>> 1791 <0 0x1c06200 0 0x200>, /* pcs */
>> 1792 <0 0x1c06600 0 0x200>; /* pcs_pcie */
>> 1793 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
>> 1794 clock-names = "pipe0";
>> 1795
>> 1796 #clock-cells = <0>;
>> 1797 #phy-cells = <0>;
>> 1798 clock-output-names = "pcie_0_pipe_clk";
>> 1799 };
1921 }; 1800 };
1922 1801
1923 pcie1: pcie@1c08000 { !! 1802 pcie1: pci@1c08000 {
1924 compatible = "qcom,pc 1803 compatible = "qcom,pcie-sm8450-pcie1";
1925 reg = <0 0x01c08000 0 1804 reg = <0 0x01c08000 0 0x3000>,
1926 <0 0x40000000 0 1805 <0 0x40000000 0 0xf1d>,
1927 <0 0x40000f20 0 1806 <0 0x40000f20 0 0xa8>,
1928 <0 0x40001000 0 1807 <0 0x40001000 0 0x1000>,
1929 <0 0x40100000 0 1808 <0 0x40100000 0 0x100000>;
1930 reg-names = "parf", " 1809 reg-names = "parf", "dbi", "elbi", "atu", "config";
1931 device_type = "pci"; 1810 device_type = "pci";
1932 linux,pci-domain = <1 1811 linux,pci-domain = <1>;
1933 bus-range = <0x00 0xf 1812 bus-range = <0x00 0xff>;
1934 num-lanes = <2>; 1813 num-lanes = <2>;
1935 1814
1936 #address-cells = <3>; 1815 #address-cells = <3>;
1937 #size-cells = <2>; 1816 #size-cells = <2>;
1938 1817
1939 ranges = <0x01000000 !! 1818 ranges = <0x01000000 0x0 0x40200000 0 0x40200000 0x0 0x100000>,
1940 <0x02000000 !! 1819 <0x02000000 0x0 0x40300000 0 0x40300000 0x0 0x1fd00000>;
1941 1820
1942 msi-map = <0x0 &gic_i !! 1821 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
1943 <0x100 &gic !! 1822 interrupt-names = "msi";
1944 msi-map-mask = <0xff0 <<
1945 interrupts = <GIC_SPI <<
1946 <GIC_SPI <<
1947 <GIC_SPI <<
1948 <GIC_SPI <<
1949 <GIC_SPI <<
1950 <GIC_SPI <<
1951 <GIC_SPI <<
1952 <GIC_SPI <<
1953 interrupt-names = "ms <<
1954 "ms <<
1955 "ms <<
1956 "ms <<
1957 "ms <<
1958 "ms <<
1959 "ms <<
1960 "ms <<
1961 #interrupt-cells = <1 1823 #interrupt-cells = <1>;
1962 interrupt-map-mask = 1824 interrupt-map-mask = <0 0 0 0x7>;
1963 interrupt-map = <0 0 1825 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1964 <0 0 1826 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1965 <0 0 1827 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1966 <0 0 1828 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1967 1829
1968 interconnects = <&pci <<
1969 &mc_ <<
1970 <&gem <<
1971 &con <<
1972 interconnect-names = <<
1973 <<
1974 clocks = <&gcc GCC_PC 1830 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1975 <&gcc GCC_PC 1831 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>,
1976 <&pcie1_phy !! 1832 <&pcie1_lane>,
1977 <&rpmhcc RPM 1833 <&rpmhcc RPMH_CXO_CLK>,
1978 <&gcc GCC_PC 1834 <&gcc GCC_PCIE_1_AUX_CLK>,
1979 <&gcc GCC_PC 1835 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1980 <&gcc GCC_PC 1836 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1981 <&gcc GCC_PC 1837 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
1982 <&gcc GCC_PC 1838 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
1983 <&gcc GCC_DD 1839 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1984 <&gcc GCC_AG 1840 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
1985 clock-names = "pipe", 1841 clock-names = "pipe",
1986 "pipe_m 1842 "pipe_mux",
1987 "phy_pi 1843 "phy_pipe",
1988 "ref", 1844 "ref",
1989 "aux", 1845 "aux",
1990 "cfg", 1846 "cfg",
1991 "bus_ma 1847 "bus_master",
1992 "bus_sl 1848 "bus_slave",
1993 "slave_ 1849 "slave_q2a",
1994 "ddrss_ 1850 "ddrss_sf_tbu",
1995 "aggre1 1851 "aggre1";
1996 1852
>> 1853 iommus = <&apps_smmu 0x1c80 0x7f>;
1997 iommu-map = <0x0 &a 1854 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
1998 <0x100 &a 1855 <0x100 &apps_smmu 0x1c81 0x1>;
1999 1856
2000 resets = <&gcc GCC_PC 1857 resets = <&gcc GCC_PCIE_1_BCR>;
2001 reset-names = "pci"; 1858 reset-names = "pci";
2002 1859
2003 power-domains = <&gcc 1860 power-domains = <&gcc PCIE_1_GDSC>;
>> 1861 power-domain-names = "gdsc";
2004 1862
2005 phys = <&pcie1_phy>; !! 1863 phys = <&pcie1_lane>;
2006 phy-names = "pciephy" 1864 phy-names = "pciephy";
2007 1865
2008 perst-gpios = <&tlmm !! 1866 perst-gpio = <&tlmm 97 GPIO_ACTIVE_LOW>;
2009 wake-gpios = <&tlmm 9 !! 1867 enable-gpio = <&tlmm 99 GPIO_ACTIVE_HIGH>;
2010 1868
2011 pinctrl-names = "defa 1869 pinctrl-names = "default";
2012 pinctrl-0 = <&pcie1_d 1870 pinctrl-0 = <&pcie1_default_state>;
2013 1871
2014 operating-points-v2 = <<
2015 <<
2016 status = "disabled"; 1872 status = "disabled";
2017 <<
2018 pcie1_opp_table: opp- <<
2019 compatible = <<
2020 <<
2021 /* GEN 1 x1 * <<
2022 opp-2500000 { <<
2023 opp-h <<
2024 requi <<
2025 opp-p <<
2026 }; <<
2027 <<
2028 /* GEN 1 x2 a <<
2029 opp-5000000 { <<
2030 opp-h <<
2031 requi <<
2032 opp-p <<
2033 }; <<
2034 <<
2035 /* GEN 2 x2 * <<
2036 opp-10000000 <<
2037 opp-h <<
2038 requi <<
2039 opp-p <<
2040 }; <<
2041 <<
2042 /* GEN 3 x1 * <<
2043 opp-8000000 { <<
2044 opp-h <<
2045 requi <<
2046 opp-p <<
2047 }; <<
2048 <<
2049 /* GEN 3 x2 a <<
2050 opp-16000000 <<
2051 opp-h <<
2052 requi <<
2053 opp-p <<
2054 }; <<
2055 <<
2056 /* GEN 4 x2 * <<
2057 opp-32000000 <<
2058 opp-h <<
2059 requi <<
2060 opp-p <<
2061 }; <<
2062 }; <<
2063 <<
2064 pcie@0 { <<
2065 device_type = <<
2066 reg = <0x0 0x <<
2067 bus-range = < <<
2068 <<
2069 #address-cell <<
2070 #size-cells = <<
2071 ranges; <<
2072 }; <<
2073 }; 1873 };
2074 1874
2075 pcie1_phy: phy@1c0e000 { !! 1875 pcie1_phy: phy@1c0f000 {
2076 compatible = "qcom,sm 1876 compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy";
2077 reg = <0 0x01c0e000 0 !! 1877 reg = <0 0x01c0f000 0 0x200>;
2078 !! 1878 #address-cells = <2>;
>> 1879 #size-cells = <2>;
>> 1880 ranges;
2079 clocks = <&gcc GCC_PC 1881 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>,
2080 <&gcc GCC_PC 1882 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2081 <&gcc GCC_PC 1883 <&gcc GCC_PCIE_1_CLKREF_EN>,
2082 <&gcc GCC_PC !! 1884 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
2083 <&gcc GCC_PC !! 1885 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2084 clock-names = "aux", <<
2085 "cfg_ah <<
2086 "ref", <<
2087 "rchng" <<
2088 "pipe"; <<
2089 <<
2090 clock-output-names = <<
2091 #clock-cells = <1>; <<
2092 <<
2093 #phy-cells = <0>; <<
2094 1886
2095 resets = <&gcc GCC_PC 1887 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2096 reset-names = "phy"; 1888 reset-names = "phy";
2097 1889
2098 assigned-clocks = <&g 1890 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
2099 assigned-clock-rates 1891 assigned-clock-rates = <100000000>;
2100 1892
2101 status = "disabled"; 1893 status = "disabled";
>> 1894
>> 1895 pcie1_lane: phy@1c0e000 {
>> 1896 reg = <0 0x1c0e000 0 0x200>, /* tx */
>> 1897 <0 0x1c0e200 0 0x300>, /* rx */
>> 1898 <0 0x1c0f200 0 0x200>, /* pcs */
>> 1899 <0 0x1c0e800 0 0x200>, /* tx */
>> 1900 <0 0x1c0ea00 0 0x300>, /* rx */
>> 1901 <0 0x1c0f400 0 0xc00>; /* pcs_pcie */
>> 1902 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
>> 1903 clock-names = "pipe0";
>> 1904
>> 1905 #clock-cells = <0>;
>> 1906 #phy-cells = <0>;
>> 1907 clock-output-names = "pcie_1_pipe_clk";
>> 1908 };
2102 }; 1909 };
2103 1910
2104 config_noc: interconnect@1500 1911 config_noc: interconnect@1500000 {
2105 compatible = "qcom,sm 1912 compatible = "qcom,sm8450-config-noc";
2106 reg = <0 0x01500000 0 1913 reg = <0 0x01500000 0 0x1c000>;
2107 #interconnect-cells = 1914 #interconnect-cells = <2>;
2108 qcom,bcm-voters = <&a 1915 qcom,bcm-voters = <&apps_bcm_voter>;
2109 }; 1916 };
2110 1917
2111 system_noc: interconnect@1680 1918 system_noc: interconnect@1680000 {
2112 compatible = "qcom,sm 1919 compatible = "qcom,sm8450-system-noc";
2113 reg = <0 0x01680000 0 1920 reg = <0 0x01680000 0 0x1e200>;
2114 #interconnect-cells = 1921 #interconnect-cells = <2>;
2115 qcom,bcm-voters = <&a 1922 qcom,bcm-voters = <&apps_bcm_voter>;
2116 }; 1923 };
2117 1924
2118 pcie_noc: interconnect@16c000 1925 pcie_noc: interconnect@16c0000 {
2119 compatible = "qcom,sm 1926 compatible = "qcom,sm8450-pcie-anoc";
2120 reg = <0 0x016c0000 0 1927 reg = <0 0x016c0000 0 0xe280>;
2121 #interconnect-cells = 1928 #interconnect-cells = <2>;
2122 qcom,bcm-voters = <&a 1929 qcom,bcm-voters = <&apps_bcm_voter>;
2123 }; 1930 };
2124 1931
2125 aggre1_noc: interconnect@16e0 1932 aggre1_noc: interconnect@16e0000 {
2126 compatible = "qcom,sm 1933 compatible = "qcom,sm8450-aggre1-noc";
2127 reg = <0 0x016e0000 0 1934 reg = <0 0x016e0000 0 0x1c080>;
2128 #interconnect-cells = 1935 #interconnect-cells = <2>;
2129 clocks = <&gcc GCC_AG 1936 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2130 <&gcc GCC_AG 1937 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
2131 qcom,bcm-voters = <&a 1938 qcom,bcm-voters = <&apps_bcm_voter>;
2132 }; 1939 };
2133 1940
2134 aggre2_noc: interconnect@1700 1941 aggre2_noc: interconnect@1700000 {
2135 compatible = "qcom,sm 1942 compatible = "qcom,sm8450-aggre2-noc";
2136 reg = <0 0x01700000 0 1943 reg = <0 0x01700000 0 0x31080>;
2137 #interconnect-cells = 1944 #interconnect-cells = <2>;
2138 qcom,bcm-voters = <&a 1945 qcom,bcm-voters = <&apps_bcm_voter>;
2139 clocks = <&gcc GCC_AG 1946 clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
2140 <&gcc GCC_AG 1947 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
2141 <&gcc GCC_AG 1948 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2142 <&rpmhcc RPM 1949 <&rpmhcc RPMH_IPA_CLK>;
2143 }; 1950 };
2144 1951
2145 mmss_noc: interconnect@174000 1952 mmss_noc: interconnect@1740000 {
2146 compatible = "qcom,sm 1953 compatible = "qcom,sm8450-mmss-noc";
2147 reg = <0 0x01740000 0 1954 reg = <0 0x01740000 0 0x1f080>;
2148 #interconnect-cells = 1955 #interconnect-cells = <2>;
2149 qcom,bcm-voters = <&a 1956 qcom,bcm-voters = <&apps_bcm_voter>;
2150 }; 1957 };
2151 1958
2152 tcsr_mutex: hwlock@1f40000 { 1959 tcsr_mutex: hwlock@1f40000 {
2153 compatible = "qcom,tc 1960 compatible = "qcom,tcsr-mutex";
2154 reg = <0x0 0x01f40000 1961 reg = <0x0 0x01f40000 0x0 0x40000>;
2155 #hwlock-cells = <1>; 1962 #hwlock-cells = <1>;
2156 }; 1963 };
2157 1964
2158 tcsr: syscon@1fc0000 { <<
2159 compatible = "qcom,sm <<
2160 reg = <0x0 0x1fc0000 <<
2161 }; <<
2162 <<
2163 gpu: gpu@3d00000 { <<
2164 compatible = "qcom,ad <<
2165 reg = <0x0 0x03d00000 <<
2166 <0x0 0x03d9e000 <<
2167 <0x0 0x03d61000 <<
2168 reg-names = "kgsl_3d0 <<
2169 "cx_mem", <<
2170 "cx_dbgc" <<
2171 <<
2172 interrupts = <GIC_SPI <<
2173 <<
2174 iommus = <&adreno_smm <<
2175 <&adreno_smm <<
2176 <<
2177 operating-points-v2 = <<
2178 <<
2179 qcom,gmu = <&gmu>; <<
2180 #cooling-cells = <2>; <<
2181 <<
2182 status = "disabled"; <<
2183 <<
2184 zap-shader { <<
2185 memory-region <<
2186 }; <<
2187 <<
2188 gpu_opp_table: opp-ta <<
2189 compatible = <<
2190 <<
2191 opp-818000000 <<
2192 opp-h <<
2193 opp-l <<
2194 }; <<
2195 <<
2196 opp-791000000 <<
2197 opp-h <<
2198 opp-l <<
2199 }; <<
2200 <<
2201 opp-734000000 <<
2202 opp-h <<
2203 opp-l <<
2204 }; <<
2205 <<
2206 opp-640000000 <<
2207 opp-h <<
2208 opp-l <<
2209 }; <<
2210 <<
2211 opp-599000000 <<
2212 opp-h <<
2213 opp-l <<
2214 }; <<
2215 <<
2216 opp-545000000 <<
2217 opp-h <<
2218 opp-l <<
2219 }; <<
2220 <<
2221 opp-492000000 <<
2222 opp-h <<
2223 opp-l <<
2224 }; <<
2225 <<
2226 opp-421000000 <<
2227 opp-h <<
2228 opp-l <<
2229 }; <<
2230 <<
2231 opp-350000000 <<
2232 opp-h <<
2233 opp-l <<
2234 }; <<
2235 <<
2236 opp-317000000 <<
2237 opp-h <<
2238 opp-l <<
2239 }; <<
2240 <<
2241 opp-285000000 <<
2242 opp-h <<
2243 opp-l <<
2244 }; <<
2245 <<
2246 opp-220000000 <<
2247 opp-h <<
2248 opp-l <<
2249 }; <<
2250 }; <<
2251 }; <<
2252 <<
2253 gmu: gmu@3d6a000 { <<
2254 compatible = "qcom,ad <<
2255 reg = <0x0 0x03d6a000 <<
2256 <0x0 0x03d50000 <<
2257 <0x0 0x0b290000 <<
2258 reg-names = "gmu", "r <<
2259 <<
2260 interrupts = <GIC_SPI <<
2261 <GIC_SPI <<
2262 interrupt-names = "hf <<
2263 <<
2264 clocks = <&gpucc GPU_ <<
2265 <&gpucc GPU_ <<
2266 <&gpucc GPU_ <<
2267 <&gcc GCC_DD <<
2268 <&gcc GCC_GP <<
2269 <&gpucc GPU_ <<
2270 <&gpucc GPU_ <<
2271 clock-names = "ahb", <<
2272 "gmu", <<
2273 "cxo", <<
2274 "axi", <<
2275 "memnoc <<
2276 "hub", <<
2277 "demet" <<
2278 <<
2279 power-domains = <&gpu <<
2280 <&gpu <<
2281 power-domain-names = <<
2282 <<
2283 <<
2284 iommus = <&adreno_smm <<
2285 <<
2286 qcom,qmp = <&aoss_qmp <<
2287 <<
2288 operating-points-v2 = <<
2289 <<
2290 gmu_opp_table: opp-ta <<
2291 compatible = <<
2292 <<
2293 opp-500000000 <<
2294 opp-h <<
2295 opp-l <<
2296 }; <<
2297 <<
2298 opp-200000000 <<
2299 opp-h <<
2300 opp-l <<
2301 }; <<
2302 }; <<
2303 }; <<
2304 <<
2305 gpucc: clock-controller@3d900 <<
2306 compatible = "qcom,sm <<
2307 reg = <0x0 0x03d90000 <<
2308 clocks = <&rpmhcc RPM <<
2309 <&gcc GCC_GP <<
2310 <&gcc GCC_GP <<
2311 #clock-cells = <1>; <<
2312 #reset-cells = <1>; <<
2313 #power-domain-cells = <<
2314 }; <<
2315 <<
2316 adreno_smmu: iommu@3da0000 { <<
2317 compatible = "qcom,sm <<
2318 "qcom,sm <<
2319 reg = <0x0 0x03da0000 <<
2320 #iommu-cells = <2>; <<
2321 #global-interrupts = <<
2322 interrupts = <GIC_SPI <<
2323 <GIC_SPI <<
2324 <GIC_SPI <<
2325 <GIC_SPI <<
2326 <GIC_SPI <<
2327 <GIC_SPI <<
2328 <GIC_SPI <<
2329 <GIC_SPI <<
2330 <GIC_SPI <<
2331 <GIC_SPI <<
2332 <GIC_SPI <<
2333 <GIC_SPI <<
2334 <GIC_SPI <<
2335 <GIC_SPI <<
2336 <GIC_SPI <<
2337 <GIC_SPI <<
2338 <GIC_SPI <<
2339 <GIC_SPI <<
2340 <GIC_SPI <<
2341 <GIC_SPI <<
2342 <GIC_SPI <<
2343 <GIC_SPI <<
2344 <GIC_SPI <<
2345 <GIC_SPI <<
2346 <GIC_SPI <<
2347 <GIC_SPI <<
2348 clocks = <&gpucc GPU_ <<
2349 <&gpucc GPU_ <<
2350 <&gpucc GPU_ <<
2351 <&gcc GCC_GP <<
2352 <&gcc GCC_GP <<
2353 <&gpucc GPU_ <<
2354 clock-names = "gmu", <<
2355 "hub", <<
2356 "hlos", <<
2357 "bus", <<
2358 "iface" <<
2359 "ahb"; <<
2360 power-domains = <&gpu <<
2361 dma-coherent; <<
2362 }; <<
2363 <<
2364 usb_1_hsphy: phy@88e3000 { 1965 usb_1_hsphy: phy@88e3000 {
2365 compatible = "qcom,sm 1966 compatible = "qcom,sm8450-usb-hs-phy",
2366 "qcom,us 1967 "qcom,usb-snps-hs-7nm-phy";
2367 reg = <0 0x088e3000 0 1968 reg = <0 0x088e3000 0 0x400>;
2368 status = "disabled"; 1969 status = "disabled";
2369 #phy-cells = <0>; 1970 #phy-cells = <0>;
2370 1971
2371 clocks = <&rpmhcc RPM 1972 clocks = <&rpmhcc RPMH_CXO_CLK>;
2372 clock-names = "ref"; 1973 clock-names = "ref";
2373 1974
2374 resets = <&gcc GCC_QU 1975 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2375 }; 1976 };
2376 1977
2377 usb_1_qmpphy: phy@88e8000 { !! 1978 usb_1_qmpphy: phy-wrapper@88e9000 {
2378 compatible = "qcom,sm !! 1979 compatible = "qcom,sm8450-qmp-usb3-phy";
2379 reg = <0 0x088e8000 0 !! 1980 reg = <0 0x088e9000 0 0x200>,
>> 1981 <0 0x088e8000 0 0x20>;
>> 1982 status = "disabled";
>> 1983 #address-cells = <2>;
>> 1984 #size-cells = <2>;
>> 1985 ranges;
2380 1986
2381 clocks = <&gcc GCC_US 1987 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2382 <&rpmhcc RPM 1988 <&rpmhcc RPMH_CXO_CLK>,
2383 <&gcc GCC_US !! 1989 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
2384 <&gcc GCC_US !! 1990 clock-names = "aux", "ref_clk_src", "com_aux";
2385 clock-names = "aux", <<
2386 1991
2387 resets = <&gcc GCC_US 1992 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
2388 <&gcc GCC_US 1993 <&gcc GCC_USB3_PHY_PRIM_BCR>;
2389 reset-names = "phy", 1994 reset-names = "phy", "common";
2390 1995
2391 #clock-cells = <1>; !! 1996 usb_1_ssphy: phy@88e9200 {
2392 #phy-cells = <1>; !! 1997 reg = <0 0x088e9200 0 0x200>,
2393 !! 1998 <0 0x088e9400 0 0x200>,
2394 orientation-switch; !! 1999 <0 0x088e9c00 0 0x400>,
2395 !! 2000 <0 0x088e9600 0 0x200>,
2396 status = "disabled"; !! 2001 <0 0x088e9800 0 0x200>,
2397 !! 2002 <0 0x088e9a00 0 0x100>;
2398 ports { !! 2003 #phy-cells = <0>;
2399 #address-cell !! 2004 #clock-cells = <1>;
2400 #size-cells = !! 2005 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2401 !! 2006 clock-names = "pipe0";
2402 port@0 { !! 2007 clock-output-names = "usb3_phy_pipe_clk_src";
2403 reg = <<
2404 <<
2405 usb_1 <<
2406 }; <<
2407 }; <<
2408 <<
2409 port@1 { <<
2410 reg = <<
2411 <<
2412 usb_1 <<
2413 <<
2414 }; <<
2415 }; <<
2416 <<
2417 port@2 { <<
2418 reg = <<
2419 <<
2420 usb_1 <<
2421 <<
2422 }; <<
2423 }; <<
2424 }; 2008 };
2425 }; 2009 };
2426 2010
2427 remoteproc_slpi: remoteproc@2 2011 remoteproc_slpi: remoteproc@2400000 {
2428 compatible = "qcom,sm 2012 compatible = "qcom,sm8450-slpi-pas";
2429 reg = <0 0x02400000 0 2013 reg = <0 0x02400000 0 0x4000>;
2430 2014
2431 interrupts-extended = !! 2015 interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
2432 2016 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
2433 2017 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
2434 2018 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
2435 2019 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
2436 interrupt-names = "wd 2020 interrupt-names = "wdog", "fatal", "ready",
2437 "ha 2021 "handover", "stop-ack";
2438 2022
2439 clocks = <&rpmhcc RPM 2023 clocks = <&rpmhcc RPMH_CXO_CLK>;
2440 clock-names = "xo"; 2024 clock-names = "xo";
2441 2025
2442 power-domains = <&rpm !! 2026 power-domains = <&rpmhpd SM8450_LCX>,
2443 <&rpm !! 2027 <&rpmhpd SM8450_LMX>;
2444 power-domain-names = 2028 power-domain-names = "lcx", "lmx";
2445 2029
2446 memory-region = <&slp 2030 memory-region = <&slpi_mem>;
2447 2031
2448 qcom,qmp = <&aoss_qmp 2032 qcom,qmp = <&aoss_qmp>;
2449 2033
2450 qcom,smem-states = <& 2034 qcom,smem-states = <&smp2p_slpi_out 0>;
2451 qcom,smem-state-names 2035 qcom,smem-state-names = "stop";
2452 2036
2453 status = "disabled"; 2037 status = "disabled";
2454 2038
2455 glink-edge { 2039 glink-edge {
2456 interrupts-ex 2040 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
2457 2041 IPCC_MPROC_SIGNAL_GLINK_QMP
2458 2042 IRQ_TYPE_EDGE_RISING>;
2459 mboxes = <&ip 2043 mboxes = <&ipcc IPCC_CLIENT_SLPI
2460 2044 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2461 2045
2462 label = "slpi 2046 label = "slpi";
2463 qcom,remote-p 2047 qcom,remote-pid = <3>;
2464 2048
2465 fastrpc { 2049 fastrpc {
2466 compa 2050 compatible = "qcom,fastrpc";
2467 qcom, 2051 qcom,glink-channels = "fastrpcglink-apps-dsp";
2468 label 2052 label = "sdsp";
2469 qcom, <<
2470 #addr 2053 #address-cells = <1>;
2471 #size 2054 #size-cells = <0>;
2472 2055
2473 compu 2056 compute-cb@1 {
2474 2057 compatible = "qcom,fastrpc-compute-cb";
2475 2058 reg = <1>;
2476 2059 iommus = <&apps_smmu 0x0541 0x0>;
2477 }; 2060 };
2478 2061
2479 compu 2062 compute-cb@2 {
2480 2063 compatible = "qcom,fastrpc-compute-cb";
2481 2064 reg = <2>;
2482 2065 iommus = <&apps_smmu 0x0542 0x0>;
2483 }; 2066 };
2484 2067
2485 compu 2068 compute-cb@3 {
2486 2069 compatible = "qcom,fastrpc-compute-cb";
2487 2070 reg = <3>;
2488 2071 iommus = <&apps_smmu 0x0543 0x0>;
2489 2072 /* note: shared-cb = <4> in downstream */
2490 }; 2073 };
2491 }; 2074 };
2492 }; 2075 };
2493 }; 2076 };
2494 2077
2495 wsa2macro: codec@31e0000 { <<
2496 compatible = "qcom,sm <<
2497 reg = <0 0x031e0000 0 <<
2498 clocks = <&q6prmcc LP <<
2499 <&q6prmcc LP <<
2500 <&q6prmcc LP <<
2501 <&q6prmcc LP <<
2502 <&vamacro>; <<
2503 clock-names = "mclk", <<
2504 <<
2505 #clock-cells = <0>; <<
2506 clock-output-names = <<
2507 #sound-dai-cells = <1 <<
2508 }; <<
2509 <<
2510 swr4: soundwire@31f0000 { <<
2511 compatible = "qcom,so <<
2512 reg = <0 0x031f0000 0 <<
2513 interrupts = <GIC_SPI <<
2514 clocks = <&wsa2macro> <<
2515 clock-names = "iface" <<
2516 label = "WSA2"; <<
2517 <<
2518 pinctrl-0 = <&wsa2_sw <<
2519 pinctrl-names = "defa <<
2520 <<
2521 qcom,din-ports = <2>; <<
2522 qcom,dout-ports = <6> <<
2523 <<
2524 qcom,ports-sinterval- <<
2525 qcom,ports-offset1 = <<
2526 qcom,ports-offset2 = <<
2527 qcom,ports-hstart = <<
2528 qcom,ports-hstop = <<
2529 qcom,ports-word-lengt <<
2530 qcom,ports-block-pack <<
2531 qcom,ports-block-grou <<
2532 qcom,ports-lane-contr <<
2533 <<
2534 #address-cells = <2>; <<
2535 #size-cells = <0>; <<
2536 #sound-dai-cells = <1 <<
2537 status = "disabled"; <<
2538 }; <<
2539 <<
2540 rxmacro: codec@3200000 { <<
2541 compatible = "qcom,sm <<
2542 reg = <0 0x03200000 0 <<
2543 clocks = <&q6prmcc LP <<
2544 <&q6prmcc LP <<
2545 <&q6prmcc LP <<
2546 <&q6prmcc LP <<
2547 <&vamacro>; <<
2548 clock-names = "mclk", <<
2549 <<
2550 #clock-cells = <0>; <<
2551 clock-output-names = <<
2552 #sound-dai-cells = <1 <<
2553 }; <<
2554 <<
2555 swr1: soundwire@3210000 { <<
2556 compatible = "qcom,so <<
2557 reg = <0 0x03210000 0 <<
2558 interrupts = <GIC_SPI <<
2559 clocks = <&rxmacro>; <<
2560 clock-names = "iface" <<
2561 label = "RX"; <<
2562 qcom,din-ports = <0>; <<
2563 qcom,dout-ports = <5> <<
2564 <<
2565 pinctrl-0 = <&rx_swr_ <<
2566 pinctrl-names = "defa <<
2567 <<
2568 qcom,ports-sinterval- <<
2569 qcom,ports-offset1 = <<
2570 qcom,ports-offset2 = <<
2571 qcom,ports-hstart = <<
2572 qcom,ports-hstop = <<
2573 qcom,ports-word-lengt <<
2574 qcom,ports-block-pack <<
2575 qcom,ports-block-grou <<
2576 qcom,ports-lane-contr <<
2577 <<
2578 #address-cells = <2>; <<
2579 #size-cells = <0>; <<
2580 #sound-dai-cells = <1 <<
2581 status = "disabled"; <<
2582 }; <<
2583 <<
2584 txmacro: codec@3220000 { <<
2585 compatible = "qcom,sm <<
2586 reg = <0 0x03220000 0 <<
2587 clocks = <&q6prmcc LP <<
2588 <&q6prmcc LP <<
2589 <&q6prmcc LP <<
2590 <&q6prmcc LP <<
2591 <&vamacro>; <<
2592 clock-names = "mclk", <<
2593 <<
2594 #clock-cells = <0>; <<
2595 clock-output-names = <<
2596 #sound-dai-cells = <1 <<
2597 }; <<
2598 <<
2599 wsamacro: codec@3240000 { <<
2600 compatible = "qcom,sm <<
2601 reg = <0 0x03240000 0 <<
2602 clocks = <&q6prmcc LP <<
2603 <&q6prmcc LP <<
2604 <&q6prmcc LP <<
2605 <&q6prmcc LP <<
2606 <&vamacro>; <<
2607 clock-names = "mclk", <<
2608 <<
2609 #clock-cells = <0>; <<
2610 clock-output-names = <<
2611 #sound-dai-cells = <1 <<
2612 }; <<
2613 <<
2614 swr0: soundwire@3250000 { <<
2615 compatible = "qcom,so <<
2616 reg = <0 0x03250000 0 <<
2617 interrupts = <GIC_SPI <<
2618 clocks = <&wsamacro>; <<
2619 clock-names = "iface" <<
2620 label = "WSA"; <<
2621 <<
2622 pinctrl-0 = <&wsa_swr <<
2623 pinctrl-names = "defa <<
2624 <<
2625 qcom,din-ports = <2>; <<
2626 qcom,dout-ports = <6> <<
2627 <<
2628 qcom,ports-sinterval- <<
2629 qcom,ports-offset1 = <<
2630 qcom,ports-offset2 = <<
2631 qcom,ports-hstart = <<
2632 qcom,ports-hstop = <<
2633 qcom,ports-word-lengt <<
2634 qcom,ports-block-pack <<
2635 qcom,ports-block-grou <<
2636 qcom,ports-lane-contr <<
2637 <<
2638 #address-cells = <2>; <<
2639 #size-cells = <0>; <<
2640 #sound-dai-cells = <1 <<
2641 status = "disabled"; <<
2642 }; <<
2643 <<
2644 swr2: soundwire@33b0000 { <<
2645 compatible = "qcom,so <<
2646 reg = <0 0x033b0000 0 <<
2647 interrupts = <GIC_SPI <<
2648 <GIC_SPI <<
2649 interrupt-names = "co <<
2650 <<
2651 clocks = <&txmacro>; <<
2652 clock-names = "iface" <<
2653 label = "TX"; <<
2654 <<
2655 pinctrl-0 = <&tx_swr_ <<
2656 pinctrl-names = "defa <<
2657 <<
2658 qcom,din-ports = <4>; <<
2659 qcom,dout-ports = <0> <<
2660 qcom,ports-sinterval- <<
2661 qcom,ports-offset1 = <<
2662 qcom,ports-offset2 = <<
2663 qcom,ports-hstart = <<
2664 qcom,ports-hstop = <<
2665 qcom,ports-word-lengt <<
2666 qcom,ports-block-pack <<
2667 qcom,ports-block-grou <<
2668 qcom,ports-lane-contr <<
2669 <<
2670 #address-cells = <2>; <<
2671 #size-cells = <0>; <<
2672 #sound-dai-cells = <1 <<
2673 status = "disabled"; <<
2674 }; <<
2675 <<
2676 vamacro: codec@33f0000 { <<
2677 compatible = "qcom,sm <<
2678 reg = <0 0x033f0000 0 <<
2679 clocks = <&q6prmcc LP <<
2680 <&q6prmcc LP <<
2681 <&q6prmcc LP <<
2682 <&q6prmcc LP <<
2683 clock-names = "mclk", <<
2684 <<
2685 #clock-cells = <0>; <<
2686 clock-output-names = <<
2687 #sound-dai-cells = <1 <<
2688 status = "disabled"; <<
2689 }; <<
2690 <<
2691 remoteproc_adsp: remoteproc@3 2078 remoteproc_adsp: remoteproc@30000000 {
2692 compatible = "qcom,sm 2079 compatible = "qcom,sm8450-adsp-pas";
2693 reg = <0 0x30000000 0 !! 2080 reg = <0 0x030000000 0 0x100>;
2694 2081
2695 interrupts-extended = !! 2082 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
2696 2083 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
2697 2084 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
2698 2085 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
2699 2086 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
2700 interrupt-names = "wd 2087 interrupt-names = "wdog", "fatal", "ready",
2701 "ha 2088 "handover", "stop-ack";
2702 2089
2703 clocks = <&rpmhcc RPM 2090 clocks = <&rpmhcc RPMH_CXO_CLK>;
2704 clock-names = "xo"; 2091 clock-names = "xo";
2705 2092
2706 power-domains = <&rpm !! 2093 power-domains = <&rpmhpd SM8450_LCX>,
2707 <&rpm !! 2094 <&rpmhpd SM8450_LMX>;
2708 power-domain-names = 2095 power-domain-names = "lcx", "lmx";
2709 2096
2710 memory-region = <&ads 2097 memory-region = <&adsp_mem>;
2711 2098
2712 qcom,qmp = <&aoss_qmp 2099 qcom,qmp = <&aoss_qmp>;
2713 2100
2714 qcom,smem-states = <& 2101 qcom,smem-states = <&smp2p_adsp_out 0>;
2715 qcom,smem-state-names 2102 qcom,smem-state-names = "stop";
2716 2103
2717 status = "disabled"; 2104 status = "disabled";
2718 2105
2719 remoteproc_adsp_glink 2106 remoteproc_adsp_glink: glink-edge {
2720 interrupts-ex 2107 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
2721 2108 IPCC_MPROC_SIGNAL_GLINK_QMP
2722 2109 IRQ_TYPE_EDGE_RISING>;
2723 mboxes = <&ip 2110 mboxes = <&ipcc IPCC_CLIENT_LPASS
2724 2111 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2725 2112
2726 label = "lpas 2113 label = "lpass";
2727 qcom,remote-p 2114 qcom,remote-pid = <2>;
2728 2115
2729 gpr { <<
2730 compa <<
2731 qcom, <<
2732 qcom, <<
2733 qcom, <<
2734 #addr <<
2735 #size <<
2736 <<
2737 q6apm <<
2738 <<
2739 <<
2740 <<
2741 <<
2742 <<
2743 <<
2744 <<
2745 <<
2746 <<
2747 <<
2748 <<
2749 <<
2750 <<
2751 <<
2752 <<
2753 }; <<
2754 <<
2755 q6prm <<
2756 <<
2757 <<
2758 <<
2759 <<
2760 <<
2761 <<
2762 <<
2763 <<
2764 <<
2765 }; <<
2766 }; <<
2767 <<
2768 fastrpc { 2116 fastrpc {
2769 compa 2117 compatible = "qcom,fastrpc";
2770 qcom, 2118 qcom,glink-channels = "fastrpcglink-apps-dsp";
2771 label 2119 label = "adsp";
2772 qcom, <<
2773 #addr 2120 #address-cells = <1>;
2774 #size 2121 #size-cells = <0>;
2775 2122
2776 compu 2123 compute-cb@3 {
2777 2124 compatible = "qcom,fastrpc-compute-cb";
2778 2125 reg = <3>;
2779 2126 iommus = <&apps_smmu 0x1803 0x0>;
2780 }; 2127 };
2781 2128
2782 compu 2129 compute-cb@4 {
2783 2130 compatible = "qcom,fastrpc-compute-cb";
2784 2131 reg = <4>;
2785 2132 iommus = <&apps_smmu 0x1804 0x0>;
2786 }; 2133 };
2787 2134
2788 compu 2135 compute-cb@5 {
2789 2136 compatible = "qcom,fastrpc-compute-cb";
2790 2137 reg = <5>;
2791 2138 iommus = <&apps_smmu 0x1805 0x0>;
2792 }; 2139 };
2793 }; 2140 };
2794 }; 2141 };
2795 }; 2142 };
2796 2143
2797 remoteproc_cdsp: remoteproc@3 2144 remoteproc_cdsp: remoteproc@32300000 {
2798 compatible = "qcom,sm 2145 compatible = "qcom,sm8450-cdsp-pas";
2799 reg = <0 0x32300000 0 !! 2146 reg = <0 0x032300000 0 0x1400000>;
2800 2147
2801 interrupts-extended = !! 2148 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
2802 2149 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
2803 2150 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
2804 2151 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
2805 2152 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
2806 interrupt-names = "wd 2153 interrupt-names = "wdog", "fatal", "ready",
2807 "ha 2154 "handover", "stop-ack";
2808 2155
2809 clocks = <&rpmhcc RPM 2156 clocks = <&rpmhcc RPMH_CXO_CLK>;
2810 clock-names = "xo"; 2157 clock-names = "xo";
2811 2158
2812 power-domains = <&rpm !! 2159 power-domains = <&rpmhpd SM8450_CX>,
2813 <&rpm !! 2160 <&rpmhpd SM8450_MXC>;
2814 power-domain-names = 2161 power-domain-names = "cx", "mxc";
2815 2162
2816 memory-region = <&cds 2163 memory-region = <&cdsp_mem>;
2817 2164
2818 qcom,qmp = <&aoss_qmp 2165 qcom,qmp = <&aoss_qmp>;
2819 2166
2820 qcom,smem-states = <& 2167 qcom,smem-states = <&smp2p_cdsp_out 0>;
2821 qcom,smem-state-names 2168 qcom,smem-state-names = "stop";
2822 2169
2823 status = "disabled"; 2170 status = "disabled";
2824 2171
2825 glink-edge { 2172 glink-edge {
2826 interrupts-ex 2173 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
2827 2174 IPCC_MPROC_SIGNAL_GLINK_QMP
2828 2175 IRQ_TYPE_EDGE_RISING>;
2829 mboxes = <&ip 2176 mboxes = <&ipcc IPCC_CLIENT_CDSP
2830 2177 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2831 2178
2832 label = "cdsp 2179 label = "cdsp";
2833 qcom,remote-p 2180 qcom,remote-pid = <5>;
2834 2181
2835 fastrpc { 2182 fastrpc {
2836 compa 2183 compatible = "qcom,fastrpc";
2837 qcom, 2184 qcom,glink-channels = "fastrpcglink-apps-dsp";
2838 label 2185 label = "cdsp";
2839 qcom, <<
2840 #addr 2186 #address-cells = <1>;
2841 #size 2187 #size-cells = <0>;
2842 2188
2843 compu 2189 compute-cb@1 {
2844 2190 compatible = "qcom,fastrpc-compute-cb";
2845 2191 reg = <1>;
2846 2192 iommus = <&apps_smmu 0x2161 0x0400>,
2847 2193 <&apps_smmu 0x1021 0x1420>;
2848 }; 2194 };
2849 2195
2850 compu 2196 compute-cb@2 {
2851 2197 compatible = "qcom,fastrpc-compute-cb";
2852 2198 reg = <2>;
2853 2199 iommus = <&apps_smmu 0x2162 0x0400>,
2854 2200 <&apps_smmu 0x1022 0x1420>;
2855 }; 2201 };
2856 2202
2857 compu 2203 compute-cb@3 {
2858 2204 compatible = "qcom,fastrpc-compute-cb";
2859 2205 reg = <3>;
2860 2206 iommus = <&apps_smmu 0x2163 0x0400>,
2861 2207 <&apps_smmu 0x1023 0x1420>;
2862 }; 2208 };
2863 2209
2864 compu 2210 compute-cb@4 {
2865 2211 compatible = "qcom,fastrpc-compute-cb";
2866 2212 reg = <4>;
2867 2213 iommus = <&apps_smmu 0x2164 0x0400>,
2868 2214 <&apps_smmu 0x1024 0x1420>;
2869 }; 2215 };
2870 2216
2871 compu 2217 compute-cb@5 {
2872 2218 compatible = "qcom,fastrpc-compute-cb";
2873 2219 reg = <5>;
2874 2220 iommus = <&apps_smmu 0x2165 0x0400>,
2875 2221 <&apps_smmu 0x1025 0x1420>;
2876 }; 2222 };
2877 2223
2878 compu 2224 compute-cb@6 {
2879 2225 compatible = "qcom,fastrpc-compute-cb";
2880 2226 reg = <6>;
2881 2227 iommus = <&apps_smmu 0x2166 0x0400>,
2882 2228 <&apps_smmu 0x1026 0x1420>;
2883 }; 2229 };
2884 2230
2885 compu 2231 compute-cb@7 {
2886 2232 compatible = "qcom,fastrpc-compute-cb";
2887 2233 reg = <7>;
2888 2234 iommus = <&apps_smmu 0x2167 0x0400>,
2889 2235 <&apps_smmu 0x1027 0x1420>;
2890 }; 2236 };
2891 2237
2892 compu 2238 compute-cb@8 {
2893 2239 compatible = "qcom,fastrpc-compute-cb";
2894 2240 reg = <8>;
2895 2241 iommus = <&apps_smmu 0x2168 0x0400>,
2896 2242 <&apps_smmu 0x1028 0x1420>;
2897 }; 2243 };
2898 2244
2899 /* no 2245 /* note: secure cb9 in downstream */
2900 }; 2246 };
2901 }; 2247 };
2902 }; 2248 };
2903 2249
2904 remoteproc_mpss: remoteproc@4 2250 remoteproc_mpss: remoteproc@4080000 {
2905 compatible = "qcom,sm 2251 compatible = "qcom,sm8450-mpss-pas";
2906 reg = <0x0 0x04080000 2252 reg = <0x0 0x04080000 0x0 0x4040>;
2907 2253
2908 interrupts-extended = !! 2254 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
2909 2255 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
2910 2256 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
2911 2257 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
2912 2258 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>,
2913 2259 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>;
2914 interrupt-names = "wd 2260 interrupt-names = "wdog", "fatal", "ready", "handover",
2915 "st 2261 "stop-ack", "shutdown-ack";
2916 2262
2917 clocks = <&rpmhcc RPM 2263 clocks = <&rpmhcc RPMH_CXO_CLK>;
2918 clock-names = "xo"; 2264 clock-names = "xo";
2919 2265
2920 power-domains = <&rpm !! 2266 power-domains = <&rpmhpd 0>,
2921 <&rpm !! 2267 <&rpmhpd 12>;
2922 power-domain-names = 2268 power-domain-names = "cx", "mss";
2923 2269
2924 memory-region = <&mps 2270 memory-region = <&mpss_mem>;
2925 2271
2926 qcom,qmp = <&aoss_qmp 2272 qcom,qmp = <&aoss_qmp>;
2927 2273
2928 qcom,smem-states = <& 2274 qcom,smem-states = <&smp2p_modem_out 0>;
2929 qcom,smem-state-names 2275 qcom,smem-state-names = "stop";
2930 2276
2931 status = "disabled"; 2277 status = "disabled";
2932 2278
2933 glink-edge { 2279 glink-edge {
2934 interrupts-ex 2280 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
2935 2281 IPCC_MPROC_SIGNAL_GLINK_QMP
2936 2282 IRQ_TYPE_EDGE_RISING>;
2937 mboxes = <&ip 2283 mboxes = <&ipcc IPCC_CLIENT_MPSS
2938 2284 IPCC_MPROC_SIGNAL_GLINK_QMP>;
>> 2285 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
2939 label = "mode 2286 label = "modem";
2940 qcom,remote-p 2287 qcom,remote-pid = <1>;
2941 }; 2288 };
2942 }; 2289 };
2943 2290
2944 videocc: clock-controller@aaf <<
2945 compatible = "qcom,sm <<
2946 reg = <0 0x0aaf0000 0 <<
2947 clocks = <&rpmhcc RPM <<
2948 <&gcc GCC_VI <<
2949 power-domains = <&rpm <<
2950 required-opps = <&rpm <<
2951 #clock-cells = <1>; <<
2952 #reset-cells = <1>; <<
2953 #power-domain-cells = <<
2954 }; <<
2955 <<
2956 cci0: cci@ac15000 { <<
2957 compatible = "qcom,sm <<
2958 reg = <0 0x0ac15000 0 <<
2959 interrupts = <GIC_SPI <<
2960 power-domains = <&cam <<
2961 <<
2962 clocks = <&camcc CAM_ <<
2963 <&camcc CAM_ <<
2964 <&camcc CAM_ <<
2965 <&camcc CAM_ <<
2966 <&camcc CAM_ <<
2967 clock-names = "camnoc <<
2968 "slow_a <<
2969 "cpas_a <<
2970 "cci", <<
2971 "cci_sr <<
2972 pinctrl-0 = <&cci0_de <<
2973 pinctrl-1 = <&cci0_sl <<
2974 pinctrl-names = "defa <<
2975 <<
2976 status = "disabled"; <<
2977 #address-cells = <1>; <<
2978 #size-cells = <0>; <<
2979 <<
2980 cci0_i2c0: i2c-bus@0 <<
2981 reg = <0>; <<
2982 clock-frequen <<
2983 #address-cell <<
2984 #size-cells = <<
2985 }; <<
2986 <<
2987 cci0_i2c1: i2c-bus@1 <<
2988 reg = <1>; <<
2989 clock-frequen <<
2990 #address-cell <<
2991 #size-cells = <<
2992 }; <<
2993 }; <<
2994 <<
2995 cci1: cci@ac16000 { <<
2996 compatible = "qcom,sm <<
2997 reg = <0 0x0ac16000 0 <<
2998 interrupts = <GIC_SPI <<
2999 power-domains = <&cam <<
3000 <<
3001 clocks = <&camcc CAM_ <<
3002 <&camcc CAM_ <<
3003 <&camcc CAM_ <<
3004 <&camcc CAM_ <<
3005 <&camcc CAM_ <<
3006 clock-names = "camnoc <<
3007 "slow_a <<
3008 "cpas_a <<
3009 "cci", <<
3010 "cci_sr <<
3011 pinctrl-0 = <&cci2_de <<
3012 pinctrl-1 = <&cci2_sl <<
3013 pinctrl-names = "defa <<
3014 <<
3015 status = "disabled"; <<
3016 #address-cells = <1>; <<
3017 #size-cells = <0>; <<
3018 <<
3019 cci1_i2c0: i2c-bus@0 <<
3020 reg = <0>; <<
3021 clock-frequen <<
3022 #address-cell <<
3023 #size-cells = <<
3024 }; <<
3025 <<
3026 cci1_i2c1: i2c-bus@1 <<
3027 reg = <1>; <<
3028 clock-frequen <<
3029 #address-cell <<
3030 #size-cells = <<
3031 }; <<
3032 }; <<
3033 <<
3034 camcc: clock-controller@ade00 <<
3035 compatible = "qcom,sm <<
3036 reg = <0 0x0ade0000 0 <<
3037 clocks = <&gcc GCC_CA <<
3038 <&rpmhcc RPM <<
3039 <&rpmhcc RPM <<
3040 <&sleep_clk> <<
3041 power-domains = <&rpm <<
3042 required-opps = <&rpm <<
3043 #clock-cells = <1>; <<
3044 #reset-cells = <1>; <<
3045 #power-domain-cells = <<
3046 status = "disabled"; <<
3047 }; <<
3048 <<
3049 mdss: display-subsystem@ae000 <<
3050 compatible = "qcom,sm <<
3051 reg = <0 0x0ae00000 0 <<
3052 reg-names = "mdss"; <<
3053 <<
3054 /* same path used twi <<
3055 interconnects = <&mms <<
3056 <&mms <<
3057 <&gem <<
3058 &con <<
3059 interconnect-names = <<
3060 <<
3061 <<
3062 <<
3063 resets = <&dispcc DIS <<
3064 <<
3065 power-domains = <&dis <<
3066 <<
3067 clocks = <&dispcc DIS <<
3068 <&gcc GCC_DI <<
3069 <&gcc GCC_DI <<
3070 <&dispcc DIS <<
3071 <<
3072 interrupts = <GIC_SPI <<
3073 interrupt-controller; <<
3074 #interrupt-cells = <1 <<
3075 <<
3076 iommus = <&apps_smmu <<
3077 <<
3078 #address-cells = <2>; <<
3079 #size-cells = <2>; <<
3080 ranges; <<
3081 <<
3082 status = "disabled"; <<
3083 <<
3084 mdss_mdp: display-con <<
3085 compatible = <<
3086 reg = <0 0x0a <<
3087 <0 0x0a <<
3088 reg-names = " <<
3089 <<
3090 clocks = <&gc <<
3091 <&gcc <<
3092 <&dis <<
3093 <&dis <<
3094 <&dis <<
3095 <&dis <<
3096 clock-names = <<
3097 <<
3098 <<
3099 <<
3100 <<
3101 <<
3102 <<
3103 assigned-cloc <<
3104 assigned-cloc <<
3105 <<
3106 operating-poi <<
3107 power-domains <<
3108 <<
3109 interrupt-par <<
3110 interrupts = <<
3111 <<
3112 ports { <<
3113 #addr <<
3114 #size <<
3115 <<
3116 port@ <<
3117 <<
3118 <<
3119 <<
3120 <<
3121 }; <<
3122 <<
3123 port@ <<
3124 <<
3125 <<
3126 <<
3127 <<
3128 }; <<
3129 <<
3130 port@ <<
3131 <<
3132 <<
3133 <<
3134 <<
3135 }; <<
3136 }; <<
3137 <<
3138 mdp_opp_table <<
3139 compa <<
3140 <<
3141 opp-1 <<
3142 <<
3143 <<
3144 }; <<
3145 <<
3146 opp-2 <<
3147 <<
3148 <<
3149 }; <<
3150 <<
3151 opp-3 <<
3152 <<
3153 <<
3154 }; <<
3155 <<
3156 opp-3 <<
3157 <<
3158 <<
3159 }; <<
3160 <<
3161 opp-5 <<
3162 <<
3163 <<
3164 }; <<
3165 }; <<
3166 }; <<
3167 <<
3168 mdss_dp0: displayport <<
3169 compatible = <<
3170 reg = <0 0xae <<
3171 <0 0xae <<
3172 <0 0xae <<
3173 <0 0xae <<
3174 <0 0xae <<
3175 interrupt-par <<
3176 interrupts = <<
3177 clocks = <&di <<
3178 <&di <<
3179 <&di <<
3180 <&di <<
3181 <&di <<
3182 clock-names = <<
3183 <<
3184 <<
3185 <<
3186 <<
3187 <<
3188 assigned-cloc <<
3189 <<
3190 assigned-cloc <<
3191 <<
3192 <<
3193 phys = <&usb_ <<
3194 phy-names = " <<
3195 <<
3196 #sound-dai-ce <<
3197 <<
3198 operating-poi <<
3199 power-domains <<
3200 <<
3201 status = "dis <<
3202 <<
3203 ports { <<
3204 #addr <<
3205 #size <<
3206 <<
3207 port@ <<
3208 <<
3209 <<
3210 <<
3211 <<
3212 }; <<
3213 <<
3214 port@ <<
3215 <<
3216 <<
3217 <<
3218 <<
3219 <<
3220 }; <<
3221 }; <<
3222 <<
3223 dp_opp_table: <<
3224 compa <<
3225 <<
3226 opp-1 <<
3227 <<
3228 <<
3229 }; <<
3230 <<
3231 opp-2 <<
3232 <<
3233 <<
3234 }; <<
3235 <<
3236 opp-5 <<
3237 <<
3238 <<
3239 }; <<
3240 <<
3241 opp-8 <<
3242 <<
3243 <<
3244 }; <<
3245 }; <<
3246 }; <<
3247 <<
3248 mdss_dsi0: dsi@ae9400 <<
3249 compatible = <<
3250 reg = <0 0x0a <<
3251 reg-names = " <<
3252 <<
3253 interrupt-par <<
3254 interrupts = <<
3255 <<
3256 clocks = <&di <<
3257 <&di <<
3258 <&di <<
3259 <&di <<
3260 <&di <<
3261 <&gcc <<
3262 clock-names = <<
3263 <<
3264 <<
3265 <<
3266 <<
3267 <<
3268 <<
3269 assigned-cloc <<
3270 assigned-cloc <<
3271 <<
3272 operating-poi <<
3273 power-domains <<
3274 <<
3275 phys = <&mdss <<
3276 phy-names = " <<
3277 <<
3278 #address-cell <<
3279 #size-cells = <<
3280 <<
3281 status = "dis <<
3282 <<
3283 ports { <<
3284 #addr <<
3285 #size <<
3286 <<
3287 port@ <<
3288 <<
3289 <<
3290 <<
3291 <<
3292 }; <<
3293 <<
3294 port@ <<
3295 <<
3296 <<
3297 <<
3298 }; <<
3299 }; <<
3300 <<
3301 mdss_dsi_opp_ <<
3302 compa <<
3303 <<
3304 opp-1 <<
3305 <<
3306 <<
3307 }; <<
3308 <<
3309 opp-3 <<
3310 <<
3311 <<
3312 }; <<
3313 <<
3314 opp-3 <<
3315 <<
3316 <<
3317 }; <<
3318 }; <<
3319 }; <<
3320 <<
3321 mdss_dsi0_phy: phy@ae <<
3322 compatible = <<
3323 reg = <0 0x0a <<
3324 <0 0x0a <<
3325 <0 0x0a <<
3326 reg-names = " <<
3327 " <<
3328 " <<
3329 <<
3330 #clock-cells <<
3331 #phy-cells = <<
3332 <<
3333 clocks = <&di <<
3334 <&rp <<
3335 clock-names = <<
3336 <<
3337 status = "dis <<
3338 }; <<
3339 <<
3340 mdss_dsi1: dsi@ae9600 <<
3341 compatible = <<
3342 reg = <0 0x0a <<
3343 reg-names = " <<
3344 <<
3345 interrupt-par <<
3346 interrupts = <<
3347 <<
3348 clocks = <&di <<
3349 <&di <<
3350 <&di <<
3351 <&di <<
3352 <&di <<
3353 <&gc <<
3354 clock-names = <<
3355 <<
3356 <<
3357 <<
3358 <<
3359 <<
3360 <<
3361 assigned-cloc <<
3362 assigned-cloc <<
3363 <<
3364 operating-poi <<
3365 power-domains <<
3366 <<
3367 phys = <&mdss <<
3368 phy-names = " <<
3369 <<
3370 #address-cell <<
3371 #size-cells = <<
3372 <<
3373 status = "dis <<
3374 <<
3375 ports { <<
3376 #addr <<
3377 #size <<
3378 <<
3379 port@ <<
3380 <<
3381 <<
3382 <<
3383 <<
3384 }; <<
3385 <<
3386 port@ <<
3387 <<
3388 <<
3389 <<
3390 }; <<
3391 }; <<
3392 }; <<
3393 <<
3394 mdss_dsi1_phy: phy@ae <<
3395 compatible = <<
3396 reg = <0 0x0a <<
3397 <0 0x0a <<
3398 <0 0x0a <<
3399 reg-names = " <<
3400 " <<
3401 " <<
3402 <<
3403 #clock-cells <<
3404 #phy-cells = <<
3405 <<
3406 clocks = <&di <<
3407 <&rp <<
3408 clock-names = <<
3409 <<
3410 status = "dis <<
3411 }; <<
3412 }; <<
3413 <<
3414 dispcc: clock-controller@af00 <<
3415 compatible = "qcom,sm <<
3416 reg = <0 0x0af00000 0 <<
3417 clocks = <&rpmhcc RPM <<
3418 <&rpmhcc RPM <<
3419 <&gcc GCC_DI <<
3420 <&sleep_clk> <<
3421 <&mdss_dsi0_ <<
3422 <&mdss_dsi0_ <<
3423 <&mdss_dsi1_ <<
3424 <&mdss_dsi1_ <<
3425 <&usb_1_qmpp <<
3426 <&usb_1_qmpp <<
3427 <0>, /* dp1 <<
3428 <0>, <<
3429 <0>, /* dp2 <<
3430 <0>, <<
3431 <0>, /* dp3 <<
3432 <0>; <<
3433 power-domains = <&rpm <<
3434 required-opps = <&rpm <<
3435 #clock-cells = <1>; <<
3436 #reset-cells = <1>; <<
3437 #power-domain-cells = <<
3438 status = "disabled"; <<
3439 }; <<
3440 <<
3441 pdc: interrupt-controller@b22 2291 pdc: interrupt-controller@b220000 {
3442 compatible = "qcom,sm 2292 compatible = "qcom,sm8450-pdc", "qcom,pdc";
3443 reg = <0 0x0b220000 0 2293 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
3444 qcom,pdc-ranges = <0 2294 qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>,
3445 <94 2295 <94 609 31>, <125 63 1>, <126 716 12>;
3446 #interrupt-cells = <2 2296 #interrupt-cells = <2>;
3447 interrupt-parent = <& 2297 interrupt-parent = <&intc>;
3448 interrupt-controller; 2298 interrupt-controller;
3449 }; 2299 };
3450 2300
3451 tsens0: thermal-sensor@c26300 2301 tsens0: thermal-sensor@c263000 {
3452 compatible = "qcom,sm 2302 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2";
3453 reg = <0 0x0c263000 0 2303 reg = <0 0x0c263000 0 0x1000>, /* TM */
3454 <0 0x0c222000 0 2304 <0 0x0c222000 0 0x1000>; /* SROT */
3455 #qcom,sensors = <16>; 2305 #qcom,sensors = <16>;
3456 interrupts = <GIC_SPI 2306 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
3457 <GIC_SPI 2307 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
3458 interrupt-names = "up 2308 interrupt-names = "uplow", "critical";
3459 #thermal-sensor-cells 2309 #thermal-sensor-cells = <1>;
3460 }; 2310 };
3461 2311
3462 tsens1: thermal-sensor@c26500 2312 tsens1: thermal-sensor@c265000 {
3463 compatible = "qcom,sm 2313 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2";
3464 reg = <0 0x0c265000 0 2314 reg = <0 0x0c265000 0 0x1000>, /* TM */
3465 <0 0x0c223000 0 2315 <0 0x0c223000 0 0x1000>; /* SROT */
3466 #qcom,sensors = <16>; 2316 #qcom,sensors = <16>;
3467 interrupts = <GIC_SPI 2317 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
3468 <GIC_SPI 2318 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
3469 interrupt-names = "up 2319 interrupt-names = "uplow", "critical";
3470 #thermal-sensor-cells 2320 #thermal-sensor-cells = <1>;
3471 }; 2321 };
3472 2322
3473 aoss_qmp: power-management@c3 !! 2323 aoss_qmp: power-controller@c300000 {
3474 compatible = "qcom,sm 2324 compatible = "qcom,sm8450-aoss-qmp", "qcom,aoss-qmp";
3475 reg = <0 0x0c300000 0 2325 reg = <0 0x0c300000 0 0x400>;
3476 interrupts-extended = 2326 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
3477 2327 IRQ_TYPE_EDGE_RISING>;
3478 mboxes = <&ipcc IPCC_ 2328 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
3479 2329
3480 #clock-cells = <0>; 2330 #clock-cells = <0>;
3481 }; 2331 };
3482 2332
3483 sram@c3f0000 { <<
3484 compatible = "qcom,rp <<
3485 reg = <0 0x0c3f0000 0 <<
3486 }; <<
3487 <<
3488 spmi_bus: spmi@c400000 { <<
3489 compatible = "qcom,sp <<
3490 reg = <0 0x0c400000 0 <<
3491 <0 0x0c500000 0 <<
3492 <0 0x0c440000 0 <<
3493 <0 0x0c4c0000 0 <<
3494 <0 0x0c42d000 0 <<
3495 reg-names = "core", <<
3496 "chnls", <<
3497 "obsrvr", <<
3498 "intr", <<
3499 "cnfg"; <<
3500 interrupt-names = "pe <<
3501 interrupts-extended = <<
3502 qcom,ee = <0>; <<
3503 qcom,channel = <0>; <<
3504 interrupt-controller; <<
3505 #interrupt-cells = <4 <<
3506 #address-cells = <2>; <<
3507 #size-cells = <0>; <<
3508 }; <<
3509 <<
3510 ipcc: mailbox@ed18000 { 2333 ipcc: mailbox@ed18000 {
3511 compatible = "qcom,sm 2334 compatible = "qcom,sm8450-ipcc", "qcom,ipcc";
3512 reg = <0 0x0ed18000 0 2335 reg = <0 0x0ed18000 0 0x1000>;
3513 interrupts = <GIC_SPI 2336 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
3514 interrupt-controller; 2337 interrupt-controller;
3515 #interrupt-cells = <3 2338 #interrupt-cells = <3>;
3516 #mbox-cells = <2>; 2339 #mbox-cells = <2>;
3517 }; 2340 };
3518 2341
3519 tlmm: pinctrl@f100000 { 2342 tlmm: pinctrl@f100000 {
3520 compatible = "qcom,sm 2343 compatible = "qcom,sm8450-tlmm";
3521 reg = <0 0x0f100000 0 2344 reg = <0 0x0f100000 0 0x300000>;
3522 interrupts = <GIC_SPI 2345 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
3523 gpio-controller; 2346 gpio-controller;
3524 #gpio-cells = <2>; 2347 #gpio-cells = <2>;
3525 interrupt-controller; 2348 interrupt-controller;
3526 #interrupt-cells = <2 2349 #interrupt-cells = <2>;
3527 gpio-ranges = <&tlmm 2350 gpio-ranges = <&tlmm 0 0 211>;
3528 wakeup-parent = <&pdc 2351 wakeup-parent = <&pdc>;
3529 2352
3530 sdc2_default_state: s <<
3531 clk-pins { <<
3532 pins <<
3533 drive <<
3534 bias- <<
3535 }; <<
3536 <<
3537 cmd-pins { <<
3538 pins <<
3539 drive <<
3540 bias- <<
3541 }; <<
3542 <<
3543 data-pins { <<
3544 pins <<
3545 drive <<
3546 bias- <<
3547 }; <<
3548 }; <<
3549 <<
3550 sdc2_sleep_state: sdc <<
3551 clk-pins { <<
3552 pins <<
3553 drive <<
3554 bias- <<
3555 }; <<
3556 <<
3557 cmd-pins { <<
3558 pins <<
3559 drive <<
3560 bias- <<
3561 }; <<
3562 <<
3563 data-pins { <<
3564 pins <<
3565 drive <<
3566 bias- <<
3567 }; <<
3568 }; <<
3569 <<
3570 cci0_default: cci0-de <<
3571 /* SDA, SCL * <<
3572 pins = "gpio1 <<
3573 function = "c <<
3574 drive-strengt <<
3575 bias-pull-up; <<
3576 }; <<
3577 <<
3578 cci0_sleep: cci0-slee <<
3579 /* SDA, SCL * <<
3580 pins = "gpio1 <<
3581 function = "c <<
3582 drive-strengt <<
3583 bias-pull-dow <<
3584 }; <<
3585 <<
3586 cci1_default: cci1-de <<
3587 /* SDA, SCL * <<
3588 pins = "gpio1 <<
3589 function = "c <<
3590 drive-strengt <<
3591 bias-pull-up; <<
3592 }; <<
3593 <<
3594 cci1_sleep: cci1-slee <<
3595 /* SDA, SCL * <<
3596 pins = "gpio1 <<
3597 function = "c <<
3598 drive-strengt <<
3599 bias-pull-dow <<
3600 }; <<
3601 <<
3602 cci2_default: cci2-de <<
3603 /* SDA, SCL * <<
3604 pins = "gpio1 <<
3605 function = "c <<
3606 drive-strengt <<
3607 bias-pull-up; <<
3608 }; <<
3609 <<
3610 cci2_sleep: cci2-slee <<
3611 /* SDA, SCL * <<
3612 pins = "gpio1 <<
3613 function = "c <<
3614 drive-strengt <<
3615 bias-pull-dow <<
3616 }; <<
3617 <<
3618 cci3_default: cci3-de <<
3619 /* SDA, SCL * <<
3620 pins = "gpio2 <<
3621 function = "c <<
3622 drive-strengt <<
3623 bias-pull-up; <<
3624 }; <<
3625 <<
3626 cci3_sleep: cci3-slee <<
3627 /* SDA, SCL * <<
3628 pins = "gpio2 <<
3629 function = "c <<
3630 drive-strengt <<
3631 bias-pull-dow <<
3632 }; <<
3633 <<
3634 pcie0_default_state: 2353 pcie0_default_state: pcie0-default-state {
3635 perst-pins { !! 2354 perst {
3636 pins 2355 pins = "gpio94";
3637 funct 2356 function = "gpio";
3638 drive 2357 drive-strength = <2>;
3639 bias- 2358 bias-pull-down;
3640 }; 2359 };
3641 2360
3642 clkreq-pins { !! 2361 clkreq {
3643 pins 2362 pins = "gpio95";
3644 funct 2363 function = "pcie0_clkreqn";
3645 drive 2364 drive-strength = <2>;
3646 bias- 2365 bias-pull-up;
3647 }; 2366 };
3648 2367
3649 wake-pins { !! 2368 wake {
3650 pins 2369 pins = "gpio96";
3651 funct 2370 function = "gpio";
3652 drive 2371 drive-strength = <2>;
3653 bias- 2372 bias-pull-up;
3654 }; 2373 };
3655 }; 2374 };
3656 2375
3657 pcie1_default_state: 2376 pcie1_default_state: pcie1-default-state {
3658 perst-pins { !! 2377 perst {
3659 pins 2378 pins = "gpio97";
3660 funct 2379 function = "gpio";
3661 drive 2380 drive-strength = <2>;
3662 bias- 2381 bias-pull-down;
3663 }; 2382 };
3664 2383
3665 clkreq-pins { !! 2384 clkreq {
3666 pins 2385 pins = "gpio98";
3667 funct 2386 function = "pcie1_clkreqn";
3668 drive 2387 drive-strength = <2>;
3669 bias- 2388 bias-pull-up;
3670 }; 2389 };
3671 2390
3672 wake-pins { !! 2391 wake {
3673 pins 2392 pins = "gpio99";
3674 funct 2393 function = "gpio";
3675 drive 2394 drive-strength = <2>;
3676 bias- 2395 bias-pull-up;
3677 }; 2396 };
3678 }; 2397 };
3679 2398
3680 qup_i2c0_data_clk: qu !! 2399 qup_i2c0_data_clk: qup-i2c0-data-clk {
3681 pins = "gpio0 2400 pins = "gpio0", "gpio1";
3682 function = "q 2401 function = "qup0";
3683 }; 2402 };
3684 2403
3685 qup_i2c1_data_clk: qu !! 2404 qup_i2c1_data_clk: qup-i2c1-data-clk {
3686 pins = "gpio4 2405 pins = "gpio4", "gpio5";
3687 function = "q 2406 function = "qup1";
3688 }; 2407 };
3689 2408
3690 qup_i2c2_data_clk: qu !! 2409 qup_i2c2_data_clk: qup-i2c2-data-clk {
3691 pins = "gpio8 2410 pins = "gpio8", "gpio9";
3692 function = "q 2411 function = "qup2";
3693 }; 2412 };
3694 2413
3695 qup_i2c3_data_clk: qu !! 2414 qup_i2c3_data_clk: qup-i2c3-data-clk {
3696 pins = "gpio1 2415 pins = "gpio12", "gpio13";
3697 function = "q 2416 function = "qup3";
3698 }; 2417 };
3699 2418
3700 qup_i2c4_data_clk: qu !! 2419 qup_i2c4_data_clk: qup-i2c4-data-clk {
3701 pins = "gpio1 2420 pins = "gpio16", "gpio17";
3702 function = "q 2421 function = "qup4";
3703 }; 2422 };
3704 2423
3705 qup_i2c5_data_clk: qu !! 2424 qup_i2c5_data_clk: qup-i2c5-data-clk {
3706 pins = "gpio2 2425 pins = "gpio206", "gpio207";
3707 function = "q 2426 function = "qup5";
3708 }; 2427 };
3709 2428
3710 qup_i2c6_data_clk: qu !! 2429 qup_i2c6_data_clk: qup-i2c6-data-clk {
3711 pins = "gpio2 2430 pins = "gpio20", "gpio21";
3712 function = "q 2431 function = "qup6";
3713 }; 2432 };
3714 2433
3715 qup_i2c8_data_clk: qu !! 2434 qup_i2c8_data_clk: qup-i2c8-data-clk {
3716 pins = "gpio2 2435 pins = "gpio28", "gpio29";
3717 function = "q 2436 function = "qup8";
3718 }; 2437 };
3719 2438
3720 qup_i2c9_data_clk: qu !! 2439 qup_i2c9_data_clk: qup-i2c9-data-clk {
3721 pins = "gpio3 2440 pins = "gpio32", "gpio33";
3722 function = "q 2441 function = "qup9";
3723 }; 2442 };
3724 2443
3725 qup_i2c10_data_clk: q !! 2444 qup_i2c10_data_clk: qup-i2c10-data-clk {
3726 pins = "gpio3 2445 pins = "gpio36", "gpio37";
3727 function = "q 2446 function = "qup10";
3728 }; 2447 };
3729 2448
3730 qup_i2c11_data_clk: q !! 2449 qup_i2c11_data_clk: qup-i2c11-data-clk {
3731 pins = "gpio4 2450 pins = "gpio40", "gpio41";
3732 function = "q 2451 function = "qup11";
3733 }; 2452 };
3734 2453
3735 qup_i2c12_data_clk: q !! 2454 qup_i2c12_data_clk: qup-i2c12-data-clk {
3736 pins = "gpio4 2455 pins = "gpio44", "gpio45";
3737 function = "q 2456 function = "qup12";
3738 }; 2457 };
3739 2458
3740 qup_i2c13_data_clk: q !! 2459 qup_i2c13_data_clk: qup-i2c13-data-clk {
3741 pins = "gpio4 2460 pins = "gpio48", "gpio49";
3742 function = "q 2461 function = "qup13";
3743 drive-strengt 2462 drive-strength = <2>;
3744 bias-pull-up; 2463 bias-pull-up;
3745 }; 2464 };
3746 2465
3747 qup_i2c14_data_clk: q !! 2466 qup_i2c14_data_clk: qup-i2c14-data-clk {
3748 pins = "gpio5 2467 pins = "gpio52", "gpio53";
3749 function = "q 2468 function = "qup14";
3750 drive-strengt 2469 drive-strength = <2>;
3751 bias-pull-up; 2470 bias-pull-up;
3752 }; 2471 };
3753 2472
3754 qup_i2c15_data_clk: q !! 2473 qup_i2c15_data_clk: qup-i2c15-data-clk {
3755 pins = "gpio5 2474 pins = "gpio56", "gpio57";
3756 function = "q 2475 function = "qup15";
3757 }; 2476 };
3758 2477
3759 qup_i2c16_data_clk: q !! 2478 qup_i2c16_data_clk: qup-i2c16-data-clk {
3760 pins = "gpio6 2479 pins = "gpio60", "gpio61";
3761 function = "q 2480 function = "qup16";
3762 }; 2481 };
3763 2482
3764 qup_i2c17_data_clk: q !! 2483 qup_i2c17_data_clk: qup-i2c17-data-clk {
3765 pins = "gpio6 2484 pins = "gpio64", "gpio65";
3766 function = "q 2485 function = "qup17";
3767 }; 2486 };
3768 2487
3769 qup_i2c18_data_clk: q !! 2488 qup_i2c18_data_clk: qup-i2c18-data-clk {
3770 pins = "gpio6 2489 pins = "gpio68", "gpio69";
3771 function = "q 2490 function = "qup18";
3772 }; 2491 };
3773 2492
3774 qup_i2c19_data_clk: q !! 2493 qup_i2c19_data_clk: qup-i2c19-data-clk {
3775 pins = "gpio7 2494 pins = "gpio72", "gpio73";
3776 function = "q 2495 function = "qup19";
3777 }; 2496 };
3778 2497
3779 qup_i2c20_data_clk: q !! 2498 qup_i2c20_data_clk: qup-i2c20-data-clk {
3780 pins = "gpio7 2499 pins = "gpio76", "gpio77";
3781 function = "q 2500 function = "qup20";
3782 }; 2501 };
3783 2502
3784 qup_i2c21_data_clk: q !! 2503 qup_i2c21_data_clk: qup-i2c21-data-clk {
3785 pins = "gpio8 2504 pins = "gpio80", "gpio81";
3786 function = "q 2505 function = "qup21";
3787 }; 2506 };
3788 2507
3789 qup_spi0_cs: qup-spi0 !! 2508 qup_spi0_cs: qup-spi0-cs {
3790 pins = "gpio3 2509 pins = "gpio3";
3791 function = "q 2510 function = "qup0";
3792 }; 2511 };
3793 2512
3794 qup_spi0_data_clk: qu !! 2513 qup_spi0_data_clk: qup-spi0-data-clk {
3795 pins = "gpio0 2514 pins = "gpio0", "gpio1", "gpio2";
3796 function = "q 2515 function = "qup0";
3797 }; 2516 };
3798 2517
3799 qup_spi1_cs: qup-spi1 !! 2518 qup_spi1_cs: qup-spi1-cs {
3800 pins = "gpio7 2519 pins = "gpio7";
3801 function = "q 2520 function = "qup1";
3802 }; 2521 };
3803 2522
3804 qup_spi1_data_clk: qu !! 2523 qup_spi1_data_clk: qup-spi1-data-clk {
3805 pins = "gpio4 2524 pins = "gpio4", "gpio5", "gpio6";
3806 function = "q 2525 function = "qup1";
3807 }; 2526 };
3808 2527
3809 qup_spi2_cs: qup-spi2 !! 2528 qup_spi2_cs: qup-spi2-cs {
3810 pins = "gpio1 2529 pins = "gpio11";
3811 function = "q 2530 function = "qup2";
3812 }; 2531 };
3813 2532
3814 qup_spi2_data_clk: qu !! 2533 qup_spi2_data_clk: qup-spi2-data-clk {
3815 pins = "gpio8 2534 pins = "gpio8", "gpio9", "gpio10";
3816 function = "q 2535 function = "qup2";
3817 }; 2536 };
3818 2537
3819 qup_spi3_cs: qup-spi3 !! 2538 qup_spi3_cs: qup-spi3-cs {
3820 pins = "gpio1 2539 pins = "gpio15";
3821 function = "q 2540 function = "qup3";
3822 }; 2541 };
3823 2542
3824 qup_spi3_data_clk: qu !! 2543 qup_spi3_data_clk: qup-spi3-data-clk {
3825 pins = "gpio1 2544 pins = "gpio12", "gpio13", "gpio14";
3826 function = "q 2545 function = "qup3";
3827 }; 2546 };
3828 2547
3829 qup_spi4_cs: qup-spi4 !! 2548 qup_spi4_cs: qup-spi4-cs {
3830 pins = "gpio1 2549 pins = "gpio19";
3831 function = "q 2550 function = "qup4";
3832 drive-strengt 2551 drive-strength = <6>;
3833 bias-disable; 2552 bias-disable;
3834 }; 2553 };
3835 2554
3836 qup_spi4_data_clk: qu !! 2555 qup_spi4_data_clk: qup-spi4-data-clk {
3837 pins = "gpio1 2556 pins = "gpio16", "gpio17", "gpio18";
3838 function = "q 2557 function = "qup4";
3839 }; 2558 };
3840 2559
3841 qup_spi5_cs: qup-spi5 !! 2560 qup_spi5_cs: qup-spi5-cs {
3842 pins = "gpio8 2561 pins = "gpio85";
3843 function = "q 2562 function = "qup5";
3844 }; 2563 };
3845 2564
3846 qup_spi5_data_clk: qu !! 2565 qup_spi5_data_clk: qup-spi5-data-clk {
3847 pins = "gpio2 2566 pins = "gpio206", "gpio207", "gpio84";
3848 function = "q 2567 function = "qup5";
3849 }; 2568 };
3850 2569
3851 qup_spi6_cs: qup-spi6 !! 2570 qup_spi6_cs: qup-spi6-cs {
3852 pins = "gpio2 2571 pins = "gpio23";
3853 function = "q 2572 function = "qup6";
3854 }; 2573 };
3855 2574
3856 qup_spi6_data_clk: qu !! 2575 qup_spi6_data_clk: qup-spi6-data-clk {
3857 pins = "gpio2 2576 pins = "gpio20", "gpio21", "gpio22";
3858 function = "q 2577 function = "qup6";
3859 }; 2578 };
3860 2579
3861 qup_spi8_cs: qup-spi8 !! 2580 qup_spi8_cs: qup-spi8-cs {
3862 pins = "gpio3 2581 pins = "gpio31";
3863 function = "q 2582 function = "qup8";
3864 }; 2583 };
3865 2584
3866 qup_spi8_data_clk: qu !! 2585 qup_spi8_data_clk: qup-spi8-data-clk {
3867 pins = "gpio2 2586 pins = "gpio28", "gpio29", "gpio30";
3868 function = "q 2587 function = "qup8";
3869 }; 2588 };
3870 2589
3871 qup_spi9_cs: qup-spi9 !! 2590 qup_spi9_cs: qup-spi9-cs {
3872 pins = "gpio3 2591 pins = "gpio35";
3873 function = "q 2592 function = "qup9";
3874 }; 2593 };
3875 2594
3876 qup_spi9_data_clk: qu !! 2595 qup_spi9_data_clk: qup-spi9-data-clk {
3877 pins = "gpio3 2596 pins = "gpio32", "gpio33", "gpio34";
3878 function = "q 2597 function = "qup9";
3879 }; 2598 };
3880 2599
3881 qup_spi10_cs: qup-spi !! 2600 qup_spi10_cs: qup-spi10-cs {
3882 pins = "gpio3 2601 pins = "gpio39";
3883 function = "q 2602 function = "qup10";
3884 }; 2603 };
3885 2604
3886 qup_spi10_data_clk: q !! 2605 qup_spi10_data_clk: qup-spi10-data-clk {
3887 pins = "gpio3 2606 pins = "gpio36", "gpio37", "gpio38";
3888 function = "q 2607 function = "qup10";
3889 }; 2608 };
3890 2609
3891 qup_spi11_cs: qup-spi !! 2610 qup_spi11_cs: qup-spi11-cs {
3892 pins = "gpio4 2611 pins = "gpio43";
3893 function = "q 2612 function = "qup11";
3894 }; 2613 };
3895 2614
3896 qup_spi11_data_clk: q !! 2615 qup_spi11_data_clk: qup-spi11-data-clk {
3897 pins = "gpio4 2616 pins = "gpio40", "gpio41", "gpio42";
3898 function = "q 2617 function = "qup11";
3899 }; 2618 };
3900 2619
3901 qup_spi12_cs: qup-spi !! 2620 qup_spi12_cs: qup-spi12-cs {
3902 pins = "gpio4 2621 pins = "gpio47";
3903 function = "q 2622 function = "qup12";
3904 }; 2623 };
3905 2624
3906 qup_spi12_data_clk: q !! 2625 qup_spi12_data_clk: qup-spi12-data-clk {
3907 pins = "gpio4 2626 pins = "gpio44", "gpio45", "gpio46";
3908 function = "q 2627 function = "qup12";
3909 }; 2628 };
3910 2629
3911 qup_spi13_cs: qup-spi !! 2630 qup_spi13_cs: qup-spi13-cs {
3912 pins = "gpio5 2631 pins = "gpio51";
3913 function = "q 2632 function = "qup13";
3914 }; 2633 };
3915 2634
3916 qup_spi13_data_clk: q !! 2635 qup_spi13_data_clk: qup-spi13-data-clk {
3917 pins = "gpio4 2636 pins = "gpio48", "gpio49", "gpio50";
3918 function = "q 2637 function = "qup13";
3919 }; 2638 };
3920 2639
3921 qup_spi14_cs: qup-spi !! 2640 qup_spi14_cs: qup-spi14-cs {
3922 pins = "gpio5 2641 pins = "gpio55";
3923 function = "q 2642 function = "qup14";
3924 }; 2643 };
3925 2644
3926 qup_spi14_data_clk: q !! 2645 qup_spi14_data_clk: qup-spi14-data-clk {
3927 pins = "gpio5 2646 pins = "gpio52", "gpio53", "gpio54";
3928 function = "q 2647 function = "qup14";
3929 }; 2648 };
3930 2649
3931 qup_spi15_cs: qup-spi !! 2650 qup_spi15_cs: qup-spi15-cs {
3932 pins = "gpio5 2651 pins = "gpio59";
3933 function = "q 2652 function = "qup15";
3934 }; 2653 };
3935 2654
3936 qup_spi15_data_clk: q !! 2655 qup_spi15_data_clk: qup-spi15-data-clk {
3937 pins = "gpio5 2656 pins = "gpio56", "gpio57", "gpio58";
3938 function = "q 2657 function = "qup15";
3939 }; 2658 };
3940 2659
3941 qup_spi16_cs: qup-spi !! 2660 qup_spi16_cs: qup-spi16-cs {
3942 pins = "gpio6 2661 pins = "gpio63";
3943 function = "q 2662 function = "qup16";
3944 }; 2663 };
3945 2664
3946 qup_spi16_data_clk: q !! 2665 qup_spi16_data_clk: qup-spi16-data-clk {
3947 pins = "gpio6 2666 pins = "gpio60", "gpio61", "gpio62";
3948 function = "q 2667 function = "qup16";
3949 }; 2668 };
3950 2669
3951 qup_spi17_cs: qup-spi !! 2670 qup_spi17_cs: qup-spi17-cs {
3952 pins = "gpio6 2671 pins = "gpio67";
3953 function = "q 2672 function = "qup17";
3954 }; 2673 };
3955 2674
3956 qup_spi17_data_clk: q !! 2675 qup_spi17_data_clk: qup-spi17-data-clk {
3957 pins = "gpio6 2676 pins = "gpio64", "gpio65", "gpio66";
3958 function = "q 2677 function = "qup17";
3959 }; 2678 };
3960 2679
3961 qup_spi18_cs: qup-spi !! 2680 qup_spi18_cs: qup-spi18-cs {
3962 pins = "gpio7 2681 pins = "gpio71";
3963 function = "q 2682 function = "qup18";
3964 drive-strengt 2683 drive-strength = <6>;
3965 bias-disable; 2684 bias-disable;
3966 }; 2685 };
3967 2686
3968 qup_spi18_data_clk: q !! 2687 qup_spi18_data_clk: qup-spi18-data-clk {
3969 pins = "gpio6 2688 pins = "gpio68", "gpio69", "gpio70";
3970 function = "q 2689 function = "qup18";
3971 drive-strengt 2690 drive-strength = <6>;
3972 bias-disable; 2691 bias-disable;
3973 }; 2692 };
3974 2693
3975 qup_spi19_cs: qup-spi !! 2694 qup_spi19_cs: qup-spi19-cs {
3976 pins = "gpio7 2695 pins = "gpio75";
3977 function = "q 2696 function = "qup19";
3978 drive-strengt 2697 drive-strength = <6>;
3979 bias-disable; 2698 bias-disable;
3980 }; 2699 };
3981 2700
3982 qup_spi19_data_clk: q !! 2701 qup_spi19_data_clk: qup-spi19-data-clk {
3983 pins = "gpio7 2702 pins = "gpio72", "gpio73", "gpio74";
3984 function = "q 2703 function = "qup19";
3985 drive-strengt 2704 drive-strength = <6>;
3986 bias-disable; 2705 bias-disable;
3987 }; 2706 };
3988 2707
3989 qup_spi20_cs: qup-spi !! 2708 qup_spi20_cs: qup-spi20-cs {
3990 pins = "gpio7 2709 pins = "gpio79";
3991 function = "q 2710 function = "qup20";
3992 }; 2711 };
3993 2712
3994 qup_spi20_data_clk: q !! 2713 qup_spi20_data_clk: qup-spi20-data-clk {
3995 pins = "gpio7 2714 pins = "gpio76", "gpio77", "gpio78";
3996 function = "q 2715 function = "qup20";
3997 }; 2716 };
3998 2717
3999 qup_spi21_cs: qup-spi !! 2718 qup_spi21_cs: qup-spi21-cs {
4000 pins = "gpio8 2719 pins = "gpio83";
4001 function = "q 2720 function = "qup21";
4002 }; 2721 };
4003 2722
4004 qup_spi21_data_clk: q !! 2723 qup_spi21_data_clk: qup-spi21-data-clk {
4005 pins = "gpio8 2724 pins = "gpio80", "gpio81", "gpio82";
4006 function = "q 2725 function = "qup21";
4007 }; 2726 };
4008 2727
4009 qup_uart7_rx: qup-uar !! 2728 qup_uart7_rx: qup-uart7-rx {
4010 pins = "gpio2 2729 pins = "gpio26";
4011 function = "q 2730 function = "qup7";
4012 drive-strengt 2731 drive-strength = <2>;
4013 bias-disable; 2732 bias-disable;
4014 }; 2733 };
4015 2734
4016 qup_uart7_tx: qup-uar !! 2735 qup_uart7_tx: qup-uart7-tx {
4017 pins = "gpio2 2736 pins = "gpio27";
4018 function = "q 2737 function = "qup7";
4019 drive-strengt 2738 drive-strength = <2>;
4020 bias-disable; 2739 bias-disable;
4021 }; 2740 };
4022 <<
4023 qup_uart20_default: q <<
4024 pins = "gpio7 <<
4025 function = "q <<
4026 }; <<
4027 }; <<
4028 <<
4029 lpass_tlmm: pinctrl@3440000 { <<
4030 compatible = "qcom,sm <<
4031 reg = <0 0x03440000 0 <<
4032 <0 0x034d0000 0 <<
4033 gpio-controller; <<
4034 #gpio-cells = <2>; <<
4035 gpio-ranges = <&lpass <<
4036 <<
4037 clocks = <&q6prmcc LP <<
4038 <&q6prmcc LP <<
4039 clock-names = "core", <<
4040 <<
4041 tx_swr_active: tx-swr <<
4042 clk-pins { <<
4043 pins <<
4044 funct <<
4045 drive <<
4046 slew- <<
4047 bias- <<
4048 }; <<
4049 <<
4050 data-pins { <<
4051 pins <<
4052 funct <<
4053 drive <<
4054 slew- <<
4055 bias- <<
4056 }; <<
4057 }; <<
4058 <<
4059 rx_swr_active: rx-swr <<
4060 clk-pins { <<
4061 pins <<
4062 funct <<
4063 drive <<
4064 slew- <<
4065 bias- <<
4066 }; <<
4067 <<
4068 data-pins { <<
4069 pins <<
4070 funct <<
4071 drive <<
4072 slew- <<
4073 bias- <<
4074 }; <<
4075 }; <<
4076 <<
4077 dmic01_default: dmic0 <<
4078 clk-pins { <<
4079 pins <<
4080 funct <<
4081 drive <<
4082 outpu <<
4083 }; <<
4084 <<
4085 data-pins { <<
4086 pins <<
4087 funct <<
4088 drive <<
4089 }; <<
4090 }; <<
4091 <<
4092 dmic23_default: dmic2 <<
4093 clk-pins { <<
4094 pins <<
4095 funct <<
4096 drive <<
4097 outpu <<
4098 }; <<
4099 <<
4100 data-pins { <<
4101 pins <<
4102 funct <<
4103 drive <<
4104 }; <<
4105 }; <<
4106 <<
4107 wsa_swr_active: wsa-s <<
4108 clk-pins { <<
4109 pins <<
4110 funct <<
4111 drive <<
4112 slew- <<
4113 bias- <<
4114 }; <<
4115 <<
4116 data-pins { <<
4117 pins <<
4118 funct <<
4119 drive <<
4120 slew- <<
4121 bias- <<
4122 }; <<
4123 }; <<
4124 <<
4125 wsa2_swr_active: wsa2 <<
4126 clk-pins { <<
4127 pins <<
4128 funct <<
4129 drive <<
4130 slew- <<
4131 bias- <<
4132 }; <<
4133 <<
4134 data-pins { <<
4135 pins <<
4136 funct <<
4137 drive <<
4138 slew- <<
4139 bias- <<
4140 }; <<
4141 }; <<
4142 }; <<
4143 <<
4144 sram@146aa000 { <<
4145 compatible = "qcom,sm <<
4146 reg = <0 0x146aa000 0 <<
4147 ranges = <0 0 0x146aa <<
4148 <<
4149 #address-cells = <1>; <<
4150 #size-cells = <1>; <<
4151 <<
4152 pil-reloc@94c { <<
4153 compatible = <<
4154 reg = <0x94c <<
4155 }; <<
4156 }; 2741 };
4157 2742
4158 apps_smmu: iommu@15000000 { 2743 apps_smmu: iommu@15000000 {
4159 compatible = "qcom,sm 2744 compatible = "qcom,sm8450-smmu-500", "arm,mmu-500";
4160 reg = <0 0x15000000 0 2745 reg = <0 0x15000000 0 0x100000>;
4161 #iommu-cells = <2>; 2746 #iommu-cells = <2>;
4162 #global-interrupts = 2747 #global-interrupts = <1>;
4163 interrupts = <GIC_SPI !! 2748 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
4164 <GIC_SPI !! 2749 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
4165 <GIC_SPI !! 2750 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
4166 <GIC_SPI !! 2751 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
4167 <GIC_SPI !! 2752 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
4168 <GIC_SPI !! 2753 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
4169 <GIC_SPI !! 2754 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
4170 <GIC_SPI !! 2755 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
4171 <GIC_SPI !! 2756 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
4172 <GIC_SPI !! 2757 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
4173 <GIC_SPI !! 2758 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
4174 <GIC_SPI !! 2759 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
4175 <GIC_SPI !! 2760 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
4176 <GIC_SPI !! 2761 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
4177 <GIC_SPI !! 2762 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
4178 <GIC_SPI !! 2763 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
4179 <GIC_SPI !! 2764 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
4180 <GIC_SPI !! 2765 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
4181 <GIC_SPI !! 2766 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
4182 <GIC_SPI !! 2767 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
4183 <GIC_SPI !! 2768 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
4184 <GIC_SPI !! 2769 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
4185 <GIC_SPI !! 2770 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
4186 <GIC_SPI !! 2771 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
4187 <GIC_SPI !! 2772 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
4188 <GIC_SPI !! 2773 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
4189 <GIC_SPI !! 2774 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
4190 <GIC_SPI !! 2775 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
4191 <GIC_SPI !! 2776 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
4192 <GIC_SPI !! 2777 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
4193 <GIC_SPI !! 2778 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
4194 <GIC_SPI !! 2779 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
4195 <GIC_SPI !! 2780 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
4196 <GIC_SPI !! 2781 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
4197 <GIC_SPI !! 2782 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
4198 <GIC_SPI !! 2783 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
4199 <GIC_SPI !! 2784 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
4200 <GIC_SPI !! 2785 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
4201 <GIC_SPI !! 2786 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
4202 <GIC_SPI !! 2787 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
4203 <GIC_SPI !! 2788 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
4204 <GIC_SPI !! 2789 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
4205 <GIC_SPI !! 2790 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
4206 <GIC_SPI !! 2791 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
4207 <GIC_SPI !! 2792 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
4208 <GIC_SPI !! 2793 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
4209 <GIC_SPI !! 2794 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
4210 <GIC_SPI !! 2795 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
4211 <GIC_SPI !! 2796 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
4212 <GIC_SPI !! 2797 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
4213 <GIC_SPI !! 2798 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
4214 <GIC_SPI !! 2799 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
4215 <GIC_SPI !! 2800 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
4216 <GIC_SPI !! 2801 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
4217 <GIC_SPI !! 2802 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
4218 <GIC_SPI !! 2803 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
4219 <GIC_SPI !! 2804 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
4220 <GIC_SPI !! 2805 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
4221 <GIC_SPI !! 2806 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
4222 <GIC_SPI !! 2807 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
4223 <GIC_SPI !! 2808 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
4224 <GIC_SPI !! 2809 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
4225 <GIC_SPI !! 2810 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
4226 <GIC_SPI !! 2811 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
4227 <GIC_SPI !! 2812 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
4228 <GIC_SPI !! 2813 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
4229 <GIC_SPI !! 2814 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
4230 <GIC_SPI !! 2815 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
4231 <GIC_SPI !! 2816 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
4232 <GIC_SPI !! 2817 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
4233 <GIC_SPI !! 2818 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
4234 <GIC_SPI !! 2819 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
4235 <GIC_SPI !! 2820 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
4236 <GIC_SPI !! 2821 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
4237 <GIC_SPI !! 2822 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
4238 <GIC_SPI !! 2823 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
4239 <GIC_SPI !! 2824 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
4240 <GIC_SPI !! 2825 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
4241 <GIC_SPI !! 2826 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
4242 <GIC_SPI !! 2827 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
4243 <GIC_SPI !! 2828 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
4244 <GIC_SPI !! 2829 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
4245 <GIC_SPI !! 2830 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
4246 <GIC_SPI !! 2831 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
4247 <GIC_SPI !! 2832 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
4248 <GIC_SPI !! 2833 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
4249 <GIC_SPI !! 2834 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
4250 <GIC_SPI !! 2835 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
4251 <GIC_SPI !! 2836 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
4252 <GIC_SPI !! 2837 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
4253 <GIC_SPI !! 2838 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
4254 <GIC_SPI !! 2839 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
4255 <GIC_SPI !! 2840 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
4256 <GIC_SPI !! 2841 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
4257 <GIC_SPI !! 2842 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
4258 <GIC_SPI !! 2843 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
4259 <GIC_SPI !! 2844 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>;
4260 }; 2845 };
4261 2846
4262 intc: interrupt-controller@17 2847 intc: interrupt-controller@17100000 {
4263 compatible = "arm,gic 2848 compatible = "arm,gic-v3";
4264 #interrupt-cells = <3 2849 #interrupt-cells = <3>;
4265 interrupt-controller; 2850 interrupt-controller;
4266 #redistributor-region 2851 #redistributor-regions = <1>;
4267 redistributor-stride 2852 redistributor-stride = <0x0 0x40000>;
4268 reg = <0x0 0x17100000 2853 reg = <0x0 0x17100000 0x0 0x10000>, /* GICD */
4269 <0x0 0x17180000 2854 <0x0 0x17180000 0x0 0x200000>; /* GICR * 8 */
4270 interrupts = <GIC_PPI 2855 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
4271 #address-cells = <2>; 2856 #address-cells = <2>;
4272 #size-cells = <2>; 2857 #size-cells = <2>;
4273 ranges; 2858 ranges;
4274 2859
4275 gic_its: msi-controll 2860 gic_its: msi-controller@17140000 {
4276 compatible = 2861 compatible = "arm,gic-v3-its";
4277 reg = <0x0 0x 2862 reg = <0x0 0x17140000 0x0 0x20000>;
4278 msi-controlle 2863 msi-controller;
4279 #msi-cells = 2864 #msi-cells = <1>;
4280 }; 2865 };
4281 }; 2866 };
4282 2867
4283 timer@17420000 { 2868 timer@17420000 {
4284 compatible = "arm,arm 2869 compatible = "arm,armv7-timer-mem";
4285 #address-cells = <1>; 2870 #address-cells = <1>;
4286 #size-cells = <1>; 2871 #size-cells = <1>;
4287 ranges = <0 0 0 0x200 2872 ranges = <0 0 0 0x20000000>;
4288 reg = <0x0 0x17420000 2873 reg = <0x0 0x17420000 0x0 0x1000>;
4289 clock-frequency = <19 2874 clock-frequency = <19200000>;
4290 2875
4291 frame@17421000 { 2876 frame@17421000 {
4292 frame-number 2877 frame-number = <0>;
4293 interrupts = 2878 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
4294 2879 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
4295 reg = <0x1742 2880 reg = <0x17421000 0x1000>,
4296 <0x1742 2881 <0x17422000 0x1000>;
4297 }; 2882 };
4298 2883
4299 frame@17423000 { 2884 frame@17423000 {
4300 frame-number 2885 frame-number = <1>;
4301 interrupts = 2886 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
4302 reg = <0x1742 2887 reg = <0x17423000 0x1000>;
4303 status = "dis 2888 status = "disabled";
4304 }; 2889 };
4305 2890
4306 frame@17425000 { 2891 frame@17425000 {
4307 frame-number 2892 frame-number = <2>;
4308 interrupts = 2893 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
4309 reg = <0x1742 2894 reg = <0x17425000 0x1000>;
4310 status = "dis 2895 status = "disabled";
4311 }; 2896 };
4312 2897
4313 frame@17427000 { 2898 frame@17427000 {
4314 frame-number 2899 frame-number = <3>;
4315 interrupts = 2900 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
4316 reg = <0x1742 2901 reg = <0x17427000 0x1000>;
4317 status = "dis 2902 status = "disabled";
4318 }; 2903 };
4319 2904
4320 frame@17429000 { 2905 frame@17429000 {
4321 frame-number 2906 frame-number = <4>;
4322 interrupts = 2907 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
4323 reg = <0x1742 2908 reg = <0x17429000 0x1000>;
4324 status = "dis 2909 status = "disabled";
4325 }; 2910 };
4326 2911
4327 frame@1742b000 { 2912 frame@1742b000 {
4328 frame-number 2913 frame-number = <5>;
4329 interrupts = 2914 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
4330 reg = <0x1742 2915 reg = <0x1742b000 0x1000>;
4331 status = "dis 2916 status = "disabled";
4332 }; 2917 };
4333 2918
4334 frame@1742d000 { 2919 frame@1742d000 {
4335 frame-number 2920 frame-number = <6>;
4336 interrupts = 2921 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
4337 reg = <0x1742 2922 reg = <0x1742d000 0x1000>;
4338 status = "dis 2923 status = "disabled";
4339 }; 2924 };
4340 }; 2925 };
4341 2926
4342 apps_rsc: rsc@17a00000 { 2927 apps_rsc: rsc@17a00000 {
4343 label = "apps_rsc"; 2928 label = "apps_rsc";
4344 compatible = "qcom,rp 2929 compatible = "qcom,rpmh-rsc";
4345 reg = <0x0 0x17a00000 2930 reg = <0x0 0x17a00000 0x0 0x10000>,
4346 <0x0 0x17a10000 2931 <0x0 0x17a10000 0x0 0x10000>,
4347 <0x0 0x17a20000 2932 <0x0 0x17a20000 0x0 0x10000>,
4348 <0x0 0x17a30000 2933 <0x0 0x17a30000 0x0 0x10000>;
4349 reg-names = "drv-0", 2934 reg-names = "drv-0", "drv-1", "drv-2", "drv-3";
4350 interrupts = <GIC_SPI 2935 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
4351 <GIC_SPI 2936 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
4352 <GIC_SPI 2937 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
4353 qcom,tcs-offset = <0x 2938 qcom,tcs-offset = <0xd00>;
4354 qcom,drv-id = <2>; 2939 qcom,drv-id = <2>;
4355 qcom,tcs-config = <AC 2940 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
4356 <WA 2941 <WAKE_TCS 2>, <CONTROL_TCS 0>;
4357 power-domains = <&CLU <<
4358 2942
4359 apps_bcm_voter: bcm-v 2943 apps_bcm_voter: bcm-voter {
4360 compatible = 2944 compatible = "qcom,bcm-voter";
4361 }; 2945 };
4362 2946
4363 rpmhcc: clock-control 2947 rpmhcc: clock-controller {
4364 compatible = 2948 compatible = "qcom,sm8450-rpmh-clk";
4365 #clock-cells 2949 #clock-cells = <1>;
4366 clock-names = 2950 clock-names = "xo";
4367 clocks = <&xo 2951 clocks = <&xo_board>;
4368 }; 2952 };
4369 2953
4370 rpmhpd: power-control 2954 rpmhpd: power-controller {
4371 compatible = 2955 compatible = "qcom,sm8450-rpmhpd";
4372 #power-domain 2956 #power-domain-cells = <1>;
4373 operating-poi 2957 operating-points-v2 = <&rpmhpd_opp_table>;
4374 2958
4375 rpmhpd_opp_ta 2959 rpmhpd_opp_table: opp-table {
4376 compa 2960 compatible = "operating-points-v2";
4377 2961
4378 rpmhp 2962 rpmhpd_opp_ret: opp1 {
4379 2963 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4380 }; 2964 };
4381 2965
4382 rpmhp 2966 rpmhpd_opp_min_svs: opp2 {
4383 2967 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4384 }; 2968 };
4385 2969
4386 rpmhp !! 2970 rpmhpd_opp_low_svs: opp3 {
4387 <<
4388 }; <<
4389 <<
4390 rpmhp <<
4391 2971 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4392 }; 2972 };
4393 2973
4394 rpmhp !! 2974 rpmhpd_opp_svs: opp4 {
4395 <<
4396 }; <<
4397 <<
4398 rpmhp <<
4399 2975 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4400 }; 2976 };
4401 2977
4402 rpmhp !! 2978 rpmhpd_opp_svs_l1: opp5 {
4403 <<
4404 }; <<
4405 <<
4406 rpmhp <<
4407 2979 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4408 }; 2980 };
4409 2981
4410 rpmhp !! 2982 rpmhpd_opp_nom: opp6 {
4411 <<
4412 }; <<
4413 <<
4414 rpmhp <<
4415 2983 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4416 }; 2984 };
4417 2985
4418 rpmhp !! 2986 rpmhpd_opp_nom_l1: opp7 {
4419 2987 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4420 }; 2988 };
4421 2989
4422 rpmhp !! 2990 rpmhpd_opp_nom_l2: opp8 {
4423 2991 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4424 }; 2992 };
4425 2993
4426 rpmhp !! 2994 rpmhpd_opp_turbo: opp9 {
4427 2995 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4428 }; 2996 };
4429 2997
4430 rpmhp !! 2998 rpmhpd_opp_turbo_l1: opp10 {
4431 2999 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4432 }; 3000 };
4433 }; 3001 };
4434 }; 3002 };
4435 }; 3003 };
4436 3004
4437 cpufreq_hw: cpufreq@17d91000 3005 cpufreq_hw: cpufreq@17d91000 {
4438 compatible = "qcom,sm 3006 compatible = "qcom,sm8450-cpufreq-epss", "qcom,cpufreq-epss";
4439 reg = <0 0x17d91000 0 3007 reg = <0 0x17d91000 0 0x1000>,
4440 <0 0x17d92000 0 3008 <0 0x17d92000 0 0x1000>,
4441 <0 0x17d93000 0 3009 <0 0x17d93000 0 0x1000>;
4442 reg-names = "freq-dom 3010 reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
4443 clocks = <&rpmhcc RPM 3011 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
4444 clock-names = "xo", " 3012 clock-names = "xo", "alternate";
4445 interrupts = <GIC_SPI 3013 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
4446 <GIC_SPI 3014 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
4447 <GIC_SPI 3015 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
4448 interrupt-names = "dc 3016 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
4449 #freq-domain-cells = 3017 #freq-domain-cells = <1>;
4450 #clock-cells = <1>; <<
4451 }; 3018 };
4452 3019
4453 gem_noc: interconnect@1910000 3020 gem_noc: interconnect@19100000 {
4454 compatible = "qcom,sm 3021 compatible = "qcom,sm8450-gem-noc";
4455 reg = <0 0x19100000 0 3022 reg = <0 0x19100000 0 0xbb800>;
4456 #interconnect-cells = 3023 #interconnect-cells = <2>;
4457 qcom,bcm-voters = <&a 3024 qcom,bcm-voters = <&apps_bcm_voter>;
4458 }; 3025 };
4459 3026
4460 system-cache-controller@19200 3027 system-cache-controller@19200000 {
4461 compatible = "qcom,sm 3028 compatible = "qcom,sm8450-llcc";
4462 reg = <0 0x19200000 0 !! 3029 reg = <0 0x19200000 0 0x580000>, <0 0x19a00000 0 0x80000>;
4463 <0 0x19300000 0 !! 3030 reg-names = "llcc_base", "llcc_broadcast_base";
4464 <0 0x19a00000 0 <<
4465 reg-names = "llcc0_ba <<
4466 "llcc3_ba <<
4467 "llcc_bro <<
4468 interrupts = <GIC_SPI 3031 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
4469 }; 3032 };
4470 3033
4471 ufs_mem_hc: ufshc@1d84000 { 3034 ufs_mem_hc: ufshc@1d84000 {
4472 compatible = "qcom,sm 3035 compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
4473 "jedec,u 3036 "jedec,ufs-2.0";
4474 reg = <0 0x01d84000 0 3037 reg = <0 0x01d84000 0 0x3000>;
4475 interrupts = <GIC_SPI 3038 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
4476 phys = <&ufs_mem_phy> !! 3039 phys = <&ufs_mem_phy_lanes>;
4477 phy-names = "ufsphy"; 3040 phy-names = "ufsphy";
4478 lanes-per-direction = 3041 lanes-per-direction = <2>;
4479 #reset-cells = <1>; 3042 #reset-cells = <1>;
4480 resets = <&gcc GCC_UF 3043 resets = <&gcc GCC_UFS_PHY_BCR>;
4481 reset-names = "rst"; 3044 reset-names = "rst";
4482 3045
4483 power-domains = <&gcc 3046 power-domains = <&gcc UFS_PHY_GDSC>;
4484 3047
4485 iommus = <&apps_smmu 3048 iommus = <&apps_smmu 0xe0 0x0>;
4486 dma-coherent; <<
4487 3049
4488 interconnects = <&agg 3050 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>,
4489 <&gem 3051 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
4490 interconnect-names = 3052 interconnect-names = "ufs-ddr", "cpu-ufs";
4491 clock-names = 3053 clock-names =
4492 "core_clk", 3054 "core_clk",
4493 "bus_aggr_clk 3055 "bus_aggr_clk",
4494 "iface_clk", 3056 "iface_clk",
4495 "core_clk_uni 3057 "core_clk_unipro",
4496 "ref_clk", 3058 "ref_clk",
4497 "tx_lane0_syn 3059 "tx_lane0_sync_clk",
4498 "rx_lane0_syn 3060 "rx_lane0_sync_clk",
4499 "rx_lane1_syn 3061 "rx_lane1_sync_clk";
4500 clocks = 3062 clocks =
4501 <&gcc GCC_UFS 3063 <&gcc GCC_UFS_PHY_AXI_CLK>,
4502 <&gcc GCC_AGG 3064 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
4503 <&gcc GCC_UFS 3065 <&gcc GCC_UFS_PHY_AHB_CLK>,
4504 <&gcc GCC_UFS 3066 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
4505 <&rpmhcc RPMH 3067 <&rpmhcc RPMH_CXO_CLK>,
4506 <&gcc GCC_UFS 3068 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
4507 <&gcc GCC_UFS 3069 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
4508 <&gcc GCC_UFS 3070 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
4509 freq-table-hz = 3071 freq-table-hz =
4510 <75000000 300 3072 <75000000 300000000>,
4511 <0 0>, 3073 <0 0>,
4512 <0 0>, 3074 <0 0>,
4513 <75000000 300 3075 <75000000 300000000>,
4514 <75000000 300 3076 <75000000 300000000>,
4515 <0 0>, 3077 <0 0>,
4516 <0 0>, 3078 <0 0>,
4517 <0 0>; 3079 <0 0>;
4518 qcom,ice = <&ice>; <<
4519 <<
4520 status = "disabled"; 3080 status = "disabled";
4521 }; 3081 };
4522 3082
4523 ufs_mem_phy: phy@1d87000 { 3083 ufs_mem_phy: phy@1d87000 {
4524 compatible = "qcom,sm 3084 compatible = "qcom,sm8450-qmp-ufs-phy";
4525 reg = <0 0x01d87000 0 !! 3085 reg = <0 0x01d87000 0 0xe10>;
4526 !! 3086 #address-cells = <2>;
>> 3087 #size-cells = <2>;
>> 3088 ranges;
4527 clock-names = "ref", 3089 clock-names = "ref", "ref_aux", "qref";
4528 clocks = <&rpmhcc RPM 3090 clocks = <&rpmhcc RPMH_CXO_CLK>,
4529 <&gcc GCC_UF 3091 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
4530 <&gcc GCC_UF 3092 <&gcc GCC_UFS_0_CLKREF_EN>;
4531 3093
4532 power-domains = <&gcc <<
4533 <<
4534 resets = <&ufs_mem_hc 3094 resets = <&ufs_mem_hc 0>;
4535 reset-names = "ufsphy 3095 reset-names = "ufsphy";
4536 <<
4537 #clock-cells = <1>; <<
4538 #phy-cells = <0>; <<
4539 <<
4540 status = "disabled"; <<
4541 }; <<
4542 <<
4543 ice: crypto@1d88000 { <<
4544 compatible = "qcom,sm <<
4545 "qcom,in <<
4546 reg = <0 0x01d88000 0 <<
4547 clocks = <&gcc GCC_UF <<
4548 }; <<
4549 <<
4550 cryptobam: dma-controller@1dc <<
4551 compatible = "qcom,ba <<
4552 reg = <0 0x01dc4000 0 <<
4553 interrupts = <GIC_SPI <<
4554 #dma-cells = <1>; <<
4555 qcom,ee = <0>; <<
4556 qcom,controlled-remot <<
4557 iommus = <&apps_smmu <<
4558 <&apps_smmu <<
4559 <&apps_smmu <<
4560 <&apps_smmu <<
4561 <&apps_smmu <<
4562 }; <<
4563 <<
4564 crypto: crypto@1dfa000 { <<
4565 compatible = "qcom,sm <<
4566 reg = <0 0x01dfa000 0 <<
4567 dmas = <&cryptobam 4> <<
4568 dma-names = "rx", "tx <<
4569 iommus = <&apps_smmu <<
4570 <&apps_smmu <<
4571 <&apps_smmu <<
4572 <&apps_smmu <<
4573 <&apps_smmu <<
4574 interconnects = <&agg <<
4575 interconnect-names = <<
4576 }; <<
4577 <<
4578 sdhc_2: mmc@8804000 { <<
4579 compatible = "qcom,sm <<
4580 reg = <0 0x08804000 0 <<
4581 <<
4582 interrupts = <GIC_SPI <<
4583 <GIC_SPI <<
4584 interrupt-names = "hc <<
4585 <<
4586 clocks = <&gcc GCC_SD <<
4587 <&gcc GCC_SD <<
4588 <&rpmhcc RPM <<
4589 clock-names = "iface" <<
4590 resets = <&gcc GCC_SD <<
4591 interconnects = <&agg <<
4592 <&gem <<
4593 interconnect-names = <<
4594 iommus = <&apps_smmu <<
4595 power-domains = <&rpm <<
4596 operating-points-v2 = <<
4597 bus-width = <4>; <<
4598 dma-coherent; <<
4599 <<
4600 /* Forbid SDR104/SDR5 <<
4601 sdhci-caps-mask = <0x <<
4602 <<
4603 status = "disabled"; 3096 status = "disabled";
4604 3097
4605 sdhc2_opp_table: opp- !! 3098 ufs_mem_phy_lanes: phy@1d87400 {
4606 compatible = !! 3099 reg = <0 0x01d87400 0 0x108>,
4607 !! 3100 <0 0x01d87600 0 0x1e0>,
4608 opp-100000000 !! 3101 <0 0x01d87c00 0 0x1dc>,
4609 opp-h !! 3102 <0 0x01d87800 0 0x108>,
4610 requi !! 3103 <0 0x01d87a00 0 0x1e0>;
4611 }; !! 3104 #phy-cells = <0>;
4612 !! 3105 #clock-cells = <0>;
4613 opp-202000000 <<
4614 opp-h <<
4615 requi <<
4616 }; <<
4617 }; 3106 };
4618 }; 3107 };
4619 3108
4620 usb_1: usb@a6f8800 { 3109 usb_1: usb@a6f8800 {
4621 compatible = "qcom,sm 3110 compatible = "qcom,sm8450-dwc3", "qcom,dwc3";
4622 reg = <0 0x0a6f8800 0 3111 reg = <0 0x0a6f8800 0 0x400>;
4623 status = "disabled"; 3112 status = "disabled";
4624 #address-cells = <2>; 3113 #address-cells = <2>;
4625 #size-cells = <2>; 3114 #size-cells = <2>;
4626 ranges; 3115 ranges;
4627 3116
4628 clocks = <&gcc GCC_CF 3117 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
4629 <&gcc GCC_US 3118 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
4630 <&gcc GCC_AG 3119 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
4631 <&gcc GCC_US 3120 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
4632 <&gcc GCC_US 3121 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4633 <&gcc GCC_US 3122 <&gcc GCC_USB3_0_CLKREF_EN>;
4634 clock-names = "cfg_no 3123 clock-names = "cfg_noc",
4635 "core", 3124 "core",
4636 "iface" 3125 "iface",
4637 "sleep" 3126 "sleep",
4638 "mock_u 3127 "mock_utmi",
4639 "xo"; 3128 "xo";
4640 3129
4641 assigned-clocks = <&g 3130 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4642 <&g 3131 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
4643 assigned-clock-rates 3132 assigned-clock-rates = <19200000>, <200000000>;
4644 3133
4645 interrupts-extended = 3134 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
4646 !! 3135 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
4647 <<
4648 3136 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
4649 !! 3137 <&pdc 14 IRQ_TYPE_EDGE_BOTH>;
4650 interrupt-names = "pw !! 3138 interrupt-names = "hs_phy_irq",
4651 "hs !! 3139 "ss_phy_irq",
4652 "dp <<
4653 "dm 3140 "dm_hs_phy_irq",
4654 "ss !! 3141 "dp_hs_phy_irq";
4655 3142
4656 power-domains = <&gcc 3143 power-domains = <&gcc USB30_PRIM_GDSC>;
4657 3144
4658 resets = <&gcc GCC_US 3145 resets = <&gcc GCC_USB30_PRIM_BCR>;
4659 3146
4660 interconnects = <&agg <<
4661 <&gem <<
4662 interconnect-names = <<
4663 <<
4664 usb_1_dwc3: usb@a6000 3147 usb_1_dwc3: usb@a600000 {
4665 compatible = 3148 compatible = "snps,dwc3";
4666 reg = <0 0x0a 3149 reg = <0 0x0a600000 0 0xcd00>;
4667 interrupts = 3150 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
4668 iommus = <&ap 3151 iommus = <&apps_smmu 0x0 0x0>;
4669 snps,dis_u2_s 3152 snps,dis_u2_susphy_quirk;
4670 snps,dis_enbl 3153 snps,dis_enblslpm_quirk;
4671 phys = <&usb_ !! 3154 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
4672 phy-names = " 3155 phy-names = "usb2-phy", "usb3-phy";
4673 <<
4674 ports { <<
4675 #addr <<
4676 #size <<
4677 <<
4678 port@ <<
4679 <<
4680 <<
4681 <<
4682 <<
4683 }; <<
4684 <<
4685 port@ <<
4686 <<
4687 <<
4688 <<
4689 <<
4690 <<
4691 }; <<
4692 }; <<
4693 }; 3156 };
4694 }; 3157 };
4695 3158
4696 nsp_noc: interconnect@320c000 3159 nsp_noc: interconnect@320c0000 {
4697 compatible = "qcom,sm 3160 compatible = "qcom,sm8450-nsp-noc";
4698 reg = <0 0x320c0000 0 3161 reg = <0 0x320c0000 0 0x10000>;
4699 #interconnect-cells = 3162 #interconnect-cells = <2>;
4700 qcom,bcm-voters = <&a 3163 qcom,bcm-voters = <&apps_bcm_voter>;
4701 }; 3164 };
4702 3165
4703 lpass_ag_noc: interconnect@3c 3166 lpass_ag_noc: interconnect@3c40000 {
4704 compatible = "qcom,sm 3167 compatible = "qcom,sm8450-lpass-ag-noc";
4705 reg = <0 0x03c40000 0 !! 3168 reg = <0 0x3c40000 0 0x17200>;
4706 #interconnect-cells = 3169 #interconnect-cells = <2>;
4707 qcom,bcm-voters = <&a 3170 qcom,bcm-voters = <&apps_bcm_voter>;
4708 }; 3171 };
4709 }; 3172 };
4710 3173
4711 sound: sound { <<
4712 }; <<
4713 <<
4714 thermal-zones { 3174 thermal-zones {
4715 aoss0-thermal { 3175 aoss0-thermal {
>> 3176 polling-delay-passive = <0>;
>> 3177 polling-delay = <0>;
4716 thermal-sensors = <&t 3178 thermal-sensors = <&tsens0 0>;
4717 3179
4718 trips { 3180 trips {
4719 thermal-engin 3181 thermal-engine-config {
4720 tempe 3182 temperature = <125000>;
4721 hyste 3183 hysteresis = <1000>;
4722 type 3184 type = "passive";
4723 }; 3185 };
4724 3186
4725 reset-mon-cfg 3187 reset-mon-cfg {
4726 tempe 3188 temperature = <115000>;
4727 hyste 3189 hysteresis = <5000>;
4728 type 3190 type = "passive";
4729 }; 3191 };
4730 }; 3192 };
4731 }; 3193 };
4732 3194
4733 cpuss0-thermal { 3195 cpuss0-thermal {
>> 3196 polling-delay-passive = <0>;
>> 3197 polling-delay = <0>;
4734 thermal-sensors = <&t 3198 thermal-sensors = <&tsens0 1>;
4735 3199
4736 trips { 3200 trips {
4737 thermal-engin 3201 thermal-engine-config {
4738 tempe 3202 temperature = <125000>;
4739 hyste 3203 hysteresis = <1000>;
4740 type 3204 type = "passive";
4741 }; 3205 };
4742 3206
4743 reset-mon-cfg 3207 reset-mon-cfg {
4744 tempe 3208 temperature = <115000>;
4745 hyste 3209 hysteresis = <5000>;
4746 type 3210 type = "passive";
4747 }; 3211 };
4748 }; 3212 };
4749 }; 3213 };
4750 3214
4751 cpuss1-thermal { 3215 cpuss1-thermal {
>> 3216 polling-delay-passive = <0>;
>> 3217 polling-delay = <0>;
4752 thermal-sensors = <&t 3218 thermal-sensors = <&tsens0 2>;
4753 3219
4754 trips { 3220 trips {
4755 thermal-engin 3221 thermal-engine-config {
4756 tempe 3222 temperature = <125000>;
4757 hyste 3223 hysteresis = <1000>;
4758 type 3224 type = "passive";
4759 }; 3225 };
4760 3226
4761 reset-mon-cfg 3227 reset-mon-cfg {
4762 tempe 3228 temperature = <115000>;
4763 hyste 3229 hysteresis = <5000>;
4764 type 3230 type = "passive";
4765 }; 3231 };
4766 }; 3232 };
4767 }; 3233 };
4768 3234
4769 cpuss3-thermal { 3235 cpuss3-thermal {
>> 3236 polling-delay-passive = <0>;
>> 3237 polling-delay = <0>;
4770 thermal-sensors = <&t 3238 thermal-sensors = <&tsens0 3>;
4771 3239
4772 trips { 3240 trips {
4773 thermal-engin 3241 thermal-engine-config {
4774 tempe 3242 temperature = <125000>;
4775 hyste 3243 hysteresis = <1000>;
4776 type 3244 type = "passive";
4777 }; 3245 };
4778 3246
4779 reset-mon-cfg 3247 reset-mon-cfg {
4780 tempe 3248 temperature = <115000>;
4781 hyste 3249 hysteresis = <5000>;
4782 type 3250 type = "passive";
4783 }; 3251 };
4784 }; 3252 };
4785 }; 3253 };
4786 3254
4787 cpuss4-thermal { 3255 cpuss4-thermal {
>> 3256 polling-delay-passive = <0>;
>> 3257 polling-delay = <0>;
4788 thermal-sensors = <&t 3258 thermal-sensors = <&tsens0 4>;
4789 3259
4790 trips { 3260 trips {
4791 thermal-engin 3261 thermal-engine-config {
4792 tempe 3262 temperature = <125000>;
4793 hyste 3263 hysteresis = <1000>;
4794 type 3264 type = "passive";
4795 }; 3265 };
4796 3266
4797 reset-mon-cfg 3267 reset-mon-cfg {
4798 tempe 3268 temperature = <115000>;
4799 hyste 3269 hysteresis = <5000>;
4800 type 3270 type = "passive";
4801 }; 3271 };
4802 }; 3272 };
4803 }; 3273 };
4804 3274
4805 cpu4-top-thermal { 3275 cpu4-top-thermal {
>> 3276 polling-delay-passive = <0>;
>> 3277 polling-delay = <0>;
4806 thermal-sensors = <&t 3278 thermal-sensors = <&tsens0 5>;
4807 3279
4808 trips { 3280 trips {
4809 cpu4_top_aler 3281 cpu4_top_alert0: trip-point0 {
4810 tempe 3282 temperature = <90000>;
4811 hyste 3283 hysteresis = <2000>;
4812 type 3284 type = "passive";
4813 }; 3285 };
4814 3286
4815 cpu4_top_aler 3287 cpu4_top_alert1: trip-point1 {
4816 tempe 3288 temperature = <95000>;
4817 hyste 3289 hysteresis = <2000>;
4818 type 3290 type = "passive";
4819 }; 3291 };
4820 3292
4821 cpu4_top_crit !! 3293 cpu4_top_crit: cpu_crit {
4822 tempe 3294 temperature = <110000>;
4823 hyste 3295 hysteresis = <1000>;
4824 type 3296 type = "critical";
4825 }; 3297 };
4826 }; 3298 };
4827 }; 3299 };
4828 3300
4829 cpu4-bottom-thermal { 3301 cpu4-bottom-thermal {
>> 3302 polling-delay-passive = <0>;
>> 3303 polling-delay = <0>;
4830 thermal-sensors = <&t 3304 thermal-sensors = <&tsens0 6>;
4831 3305
4832 trips { 3306 trips {
4833 cpu4_bottom_a 3307 cpu4_bottom_alert0: trip-point0 {
4834 tempe 3308 temperature = <90000>;
4835 hyste 3309 hysteresis = <2000>;
4836 type 3310 type = "passive";
4837 }; 3311 };
4838 3312
4839 cpu4_bottom_a 3313 cpu4_bottom_alert1: trip-point1 {
4840 tempe 3314 temperature = <95000>;
4841 hyste 3315 hysteresis = <2000>;
4842 type 3316 type = "passive";
4843 }; 3317 };
4844 3318
4845 cpu4_bottom_c !! 3319 cpu4_bottom_crit: cpu_crit {
4846 tempe 3320 temperature = <110000>;
4847 hyste 3321 hysteresis = <1000>;
4848 type 3322 type = "critical";
4849 }; 3323 };
4850 }; 3324 };
4851 }; 3325 };
4852 3326
4853 cpu5-top-thermal { 3327 cpu5-top-thermal {
>> 3328 polling-delay-passive = <0>;
>> 3329 polling-delay = <0>;
4854 thermal-sensors = <&t 3330 thermal-sensors = <&tsens0 7>;
4855 3331
4856 trips { 3332 trips {
4857 cpu5_top_aler 3333 cpu5_top_alert0: trip-point0 {
4858 tempe 3334 temperature = <90000>;
4859 hyste 3335 hysteresis = <2000>;
4860 type 3336 type = "passive";
4861 }; 3337 };
4862 3338
4863 cpu5_top_aler 3339 cpu5_top_alert1: trip-point1 {
4864 tempe 3340 temperature = <95000>;
4865 hyste 3341 hysteresis = <2000>;
4866 type 3342 type = "passive";
4867 }; 3343 };
4868 3344
4869 cpu5_top_crit !! 3345 cpu5_top_crit: cpu_crit {
4870 tempe 3346 temperature = <110000>;
4871 hyste 3347 hysteresis = <1000>;
4872 type 3348 type = "critical";
4873 }; 3349 };
4874 }; 3350 };
4875 }; 3351 };
4876 3352
4877 cpu5-bottom-thermal { 3353 cpu5-bottom-thermal {
>> 3354 polling-delay-passive = <0>;
>> 3355 polling-delay = <0>;
4878 thermal-sensors = <&t 3356 thermal-sensors = <&tsens0 8>;
4879 3357
4880 trips { 3358 trips {
4881 cpu5_bottom_a 3359 cpu5_bottom_alert0: trip-point0 {
4882 tempe 3360 temperature = <90000>;
4883 hyste 3361 hysteresis = <2000>;
4884 type 3362 type = "passive";
4885 }; 3363 };
4886 3364
4887 cpu5_bottom_a 3365 cpu5_bottom_alert1: trip-point1 {
4888 tempe 3366 temperature = <95000>;
4889 hyste 3367 hysteresis = <2000>;
4890 type 3368 type = "passive";
4891 }; 3369 };
4892 3370
4893 cpu5_bottom_c !! 3371 cpu5_bottom_crit: cpu_crit {
4894 tempe 3372 temperature = <110000>;
4895 hyste 3373 hysteresis = <1000>;
4896 type 3374 type = "critical";
4897 }; 3375 };
4898 }; 3376 };
4899 }; 3377 };
4900 3378
4901 cpu6-top-thermal { 3379 cpu6-top-thermal {
>> 3380 polling-delay-passive = <0>;
>> 3381 polling-delay = <0>;
4902 thermal-sensors = <&t 3382 thermal-sensors = <&tsens0 9>;
4903 3383
4904 trips { 3384 trips {
4905 cpu6_top_aler 3385 cpu6_top_alert0: trip-point0 {
4906 tempe 3386 temperature = <90000>;
4907 hyste 3387 hysteresis = <2000>;
4908 type 3388 type = "passive";
4909 }; 3389 };
4910 3390
4911 cpu6_top_aler 3391 cpu6_top_alert1: trip-point1 {
4912 tempe 3392 temperature = <95000>;
4913 hyste 3393 hysteresis = <2000>;
4914 type 3394 type = "passive";
4915 }; 3395 };
4916 3396
4917 cpu6_top_crit !! 3397 cpu6_top_crit: cpu_crit {
4918 tempe 3398 temperature = <110000>;
4919 hyste 3399 hysteresis = <1000>;
4920 type 3400 type = "critical";
4921 }; 3401 };
4922 }; 3402 };
4923 }; 3403 };
4924 3404
4925 cpu6-bottom-thermal { 3405 cpu6-bottom-thermal {
>> 3406 polling-delay-passive = <0>;
>> 3407 polling-delay = <0>;
4926 thermal-sensors = <&t 3408 thermal-sensors = <&tsens0 10>;
4927 3409
4928 trips { 3410 trips {
4929 cpu6_bottom_a 3411 cpu6_bottom_alert0: trip-point0 {
4930 tempe 3412 temperature = <90000>;
4931 hyste 3413 hysteresis = <2000>;
4932 type 3414 type = "passive";
4933 }; 3415 };
4934 3416
4935 cpu6_bottom_a 3417 cpu6_bottom_alert1: trip-point1 {
4936 tempe 3418 temperature = <95000>;
4937 hyste 3419 hysteresis = <2000>;
4938 type 3420 type = "passive";
4939 }; 3421 };
4940 3422
4941 cpu6_bottom_c !! 3423 cpu6_bottom_crit: cpu_crit {
4942 tempe 3424 temperature = <110000>;
4943 hyste 3425 hysteresis = <1000>;
4944 type 3426 type = "critical";
4945 }; 3427 };
4946 }; 3428 };
4947 }; 3429 };
4948 3430
4949 cpu7-top-thermal { 3431 cpu7-top-thermal {
>> 3432 polling-delay-passive = <0>;
>> 3433 polling-delay = <0>;
4950 thermal-sensors = <&t 3434 thermal-sensors = <&tsens0 11>;
4951 3435
4952 trips { 3436 trips {
4953 cpu7_top_aler 3437 cpu7_top_alert0: trip-point0 {
4954 tempe 3438 temperature = <90000>;
4955 hyste 3439 hysteresis = <2000>;
4956 type 3440 type = "passive";
4957 }; 3441 };
4958 3442
4959 cpu7_top_aler 3443 cpu7_top_alert1: trip-point1 {
4960 tempe 3444 temperature = <95000>;
4961 hyste 3445 hysteresis = <2000>;
4962 type 3446 type = "passive";
4963 }; 3447 };
4964 3448
4965 cpu7_top_crit !! 3449 cpu7_top_crit: cpu_crit {
4966 tempe 3450 temperature = <110000>;
4967 hyste 3451 hysteresis = <1000>;
4968 type 3452 type = "critical";
4969 }; 3453 };
4970 }; 3454 };
4971 }; 3455 };
4972 3456
4973 cpu7-middle-thermal { 3457 cpu7-middle-thermal {
>> 3458 polling-delay-passive = <0>;
>> 3459 polling-delay = <0>;
4974 thermal-sensors = <&t 3460 thermal-sensors = <&tsens0 12>;
4975 3461
4976 trips { 3462 trips {
4977 cpu7_middle_a 3463 cpu7_middle_alert0: trip-point0 {
4978 tempe 3464 temperature = <90000>;
4979 hyste 3465 hysteresis = <2000>;
4980 type 3466 type = "passive";
4981 }; 3467 };
4982 3468
4983 cpu7_middle_a 3469 cpu7_middle_alert1: trip-point1 {
4984 tempe 3470 temperature = <95000>;
4985 hyste 3471 hysteresis = <2000>;
4986 type 3472 type = "passive";
4987 }; 3473 };
4988 3474
4989 cpu7_middle_c !! 3475 cpu7_middle_crit: cpu_crit {
4990 tempe 3476 temperature = <110000>;
4991 hyste 3477 hysteresis = <1000>;
4992 type 3478 type = "critical";
4993 }; 3479 };
4994 }; 3480 };
4995 }; 3481 };
4996 3482
4997 cpu7-bottom-thermal { 3483 cpu7-bottom-thermal {
>> 3484 polling-delay-passive = <0>;
>> 3485 polling-delay = <0>;
4998 thermal-sensors = <&t 3486 thermal-sensors = <&tsens0 13>;
4999 3487
5000 trips { 3488 trips {
5001 cpu7_bottom_a 3489 cpu7_bottom_alert0: trip-point0 {
5002 tempe 3490 temperature = <90000>;
5003 hyste 3491 hysteresis = <2000>;
5004 type 3492 type = "passive";
5005 }; 3493 };
5006 3494
5007 cpu7_bottom_a 3495 cpu7_bottom_alert1: trip-point1 {
5008 tempe 3496 temperature = <95000>;
5009 hyste 3497 hysteresis = <2000>;
5010 type 3498 type = "passive";
5011 }; 3499 };
5012 3500
5013 cpu7_bottom_c !! 3501 cpu7_bottom_crit: cpu_crit {
5014 tempe 3502 temperature = <110000>;
5015 hyste 3503 hysteresis = <1000>;
5016 type 3504 type = "critical";
5017 }; 3505 };
5018 }; 3506 };
5019 }; 3507 };
5020 3508
5021 gpu-top-thermal { 3509 gpu-top-thermal {
5022 polling-delay-passive 3510 polling-delay-passive = <10>;
5023 !! 3511 polling-delay = <0>;
5024 thermal-sensors = <&t 3512 thermal-sensors = <&tsens0 14>;
5025 3513
5026 cooling-maps { <<
5027 map0 { <<
5028 trip <<
5029 cooli <<
5030 }; <<
5031 }; <<
5032 <<
5033 trips { 3514 trips {
5034 gpu_top_alert !! 3515 thermal-engine-config {
5035 tempe !! 3516 temperature = <125000>;
5036 hyste 3517 hysteresis = <1000>;
5037 type 3518 type = "passive";
5038 }; 3519 };
5039 3520
5040 trip-point1 { !! 3521 thermal-hal-config {
5041 tempe !! 3522 temperature = <125000>;
5042 hyste 3523 hysteresis = <1000>;
5043 type !! 3524 type = "passive";
5044 }; 3525 };
5045 3526
5046 trip-point2 { !! 3527 reset-mon-cfg {
5047 tempe !! 3528 temperature = <115000>;
5048 hyste !! 3529 hysteresis = <5000>;
5049 type !! 3530 type = "passive";
>> 3531 };
>> 3532
>> 3533 gpu0_tj_cfg: tj_cfg {
>> 3534 temperature = <95000>;
>> 3535 hysteresis = <5000>;
>> 3536 type = "passive";
5050 }; 3537 };
5051 }; 3538 };
5052 }; 3539 };
5053 3540
5054 gpu-bottom-thermal { 3541 gpu-bottom-thermal {
5055 polling-delay-passive 3542 polling-delay-passive = <10>;
5056 !! 3543 polling-delay = <0>;
5057 thermal-sensors = <&t 3544 thermal-sensors = <&tsens0 15>;
5058 3545
5059 cooling-maps { <<
5060 map0 { <<
5061 trip <<
5062 cooli <<
5063 }; <<
5064 }; <<
5065 <<
5066 trips { 3546 trips {
5067 gpu_bottom_al !! 3547 thermal-engine-config {
5068 tempe !! 3548 temperature = <125000>;
5069 hyste 3549 hysteresis = <1000>;
5070 type 3550 type = "passive";
5071 }; 3551 };
5072 3552
5073 trip-point1 { !! 3553 thermal-hal-config {
5074 tempe !! 3554 temperature = <125000>;
5075 hyste 3555 hysteresis = <1000>;
5076 type !! 3556 type = "passive";
5077 }; 3557 };
5078 3558
5079 trip-point2 { !! 3559 reset-mon-cfg {
5080 tempe !! 3560 temperature = <115000>;
5081 hyste !! 3561 hysteresis = <5000>;
5082 type !! 3562 type = "passive";
>> 3563 };
>> 3564
>> 3565 gpu1_tj_cfg: tj_cfg {
>> 3566 temperature = <95000>;
>> 3567 hysteresis = <5000>;
>> 3568 type = "passive";
5083 }; 3569 };
5084 }; 3570 };
5085 }; 3571 };
5086 3572
5087 aoss1-thermal { 3573 aoss1-thermal {
>> 3574 polling-delay-passive = <0>;
>> 3575 polling-delay = <0>;
5088 thermal-sensors = <&t 3576 thermal-sensors = <&tsens1 0>;
5089 3577
5090 trips { 3578 trips {
5091 thermal-engin 3579 thermal-engine-config {
5092 tempe 3580 temperature = <125000>;
5093 hyste 3581 hysteresis = <1000>;
5094 type 3582 type = "passive";
5095 }; 3583 };
5096 3584
5097 reset-mon-cfg 3585 reset-mon-cfg {
5098 tempe 3586 temperature = <115000>;
5099 hyste 3587 hysteresis = <5000>;
5100 type 3588 type = "passive";
5101 }; 3589 };
5102 }; 3590 };
5103 }; 3591 };
5104 3592
5105 cpu0-thermal { 3593 cpu0-thermal {
>> 3594 polling-delay-passive = <0>;
>> 3595 polling-delay = <0>;
5106 thermal-sensors = <&t 3596 thermal-sensors = <&tsens1 1>;
5107 3597
5108 trips { 3598 trips {
5109 cpu0_alert0: 3599 cpu0_alert0: trip-point0 {
5110 tempe 3600 temperature = <90000>;
5111 hyste 3601 hysteresis = <2000>;
5112 type 3602 type = "passive";
5113 }; 3603 };
5114 3604
5115 cpu0_alert1: 3605 cpu0_alert1: trip-point1 {
5116 tempe 3606 temperature = <95000>;
5117 hyste 3607 hysteresis = <2000>;
5118 type 3608 type = "passive";
5119 }; 3609 };
5120 3610
5121 cpu0_crit: cp !! 3611 cpu0_crit: cpu_crit {
5122 tempe 3612 temperature = <110000>;
5123 hyste 3613 hysteresis = <1000>;
5124 type 3614 type = "critical";
5125 }; 3615 };
5126 }; 3616 };
5127 }; 3617 };
5128 3618
5129 cpu1-thermal { 3619 cpu1-thermal {
>> 3620 polling-delay-passive = <0>;
>> 3621 polling-delay = <0>;
5130 thermal-sensors = <&t 3622 thermal-sensors = <&tsens1 2>;
5131 3623
5132 trips { 3624 trips {
5133 cpu1_alert0: 3625 cpu1_alert0: trip-point0 {
5134 tempe 3626 temperature = <90000>;
5135 hyste 3627 hysteresis = <2000>;
5136 type 3628 type = "passive";
5137 }; 3629 };
5138 3630
5139 cpu1_alert1: 3631 cpu1_alert1: trip-point1 {
5140 tempe 3632 temperature = <95000>;
5141 hyste 3633 hysteresis = <2000>;
5142 type 3634 type = "passive";
5143 }; 3635 };
5144 3636
5145 cpu1_crit: cp !! 3637 cpu1_crit: cpu_crit {
5146 tempe 3638 temperature = <110000>;
5147 hyste 3639 hysteresis = <1000>;
5148 type 3640 type = "critical";
5149 }; 3641 };
5150 }; 3642 };
5151 }; 3643 };
5152 3644
5153 cpu2-thermal { 3645 cpu2-thermal {
>> 3646 polling-delay-passive = <0>;
>> 3647 polling-delay = <0>;
5154 thermal-sensors = <&t 3648 thermal-sensors = <&tsens1 3>;
5155 3649
5156 trips { 3650 trips {
5157 cpu2_alert0: 3651 cpu2_alert0: trip-point0 {
5158 tempe 3652 temperature = <90000>;
5159 hyste 3653 hysteresis = <2000>;
5160 type 3654 type = "passive";
5161 }; 3655 };
5162 3656
5163 cpu2_alert1: 3657 cpu2_alert1: trip-point1 {
5164 tempe 3658 temperature = <95000>;
5165 hyste 3659 hysteresis = <2000>;
5166 type 3660 type = "passive";
5167 }; 3661 };
5168 3662
5169 cpu2_crit: cp !! 3663 cpu2_crit: cpu_crit {
5170 tempe 3664 temperature = <110000>;
5171 hyste 3665 hysteresis = <1000>;
5172 type 3666 type = "critical";
5173 }; 3667 };
5174 }; 3668 };
5175 }; 3669 };
5176 3670
5177 cpu3-thermal { 3671 cpu3-thermal {
>> 3672 polling-delay-passive = <0>;
>> 3673 polling-delay = <0>;
5178 thermal-sensors = <&t 3674 thermal-sensors = <&tsens1 4>;
5179 3675
5180 trips { 3676 trips {
5181 cpu3_alert0: 3677 cpu3_alert0: trip-point0 {
5182 tempe 3678 temperature = <90000>;
5183 hyste 3679 hysteresis = <2000>;
5184 type 3680 type = "passive";
5185 }; 3681 };
5186 3682
5187 cpu3_alert1: 3683 cpu3_alert1: trip-point1 {
5188 tempe 3684 temperature = <95000>;
5189 hyste 3685 hysteresis = <2000>;
5190 type 3686 type = "passive";
5191 }; 3687 };
5192 3688
5193 cpu3_crit: cp !! 3689 cpu3_crit: cpu_crit {
5194 tempe 3690 temperature = <110000>;
5195 hyste 3691 hysteresis = <1000>;
5196 type 3692 type = "critical";
5197 }; 3693 };
5198 }; 3694 };
5199 }; 3695 };
5200 3696
5201 cdsp0-thermal { 3697 cdsp0-thermal {
5202 polling-delay-passive 3698 polling-delay-passive = <10>;
5203 !! 3699 polling-delay = <0>;
5204 thermal-sensors = <&t 3700 thermal-sensors = <&tsens1 5>;
5205 3701
5206 trips { 3702 trips {
5207 thermal-engin 3703 thermal-engine-config {
5208 tempe 3704 temperature = <125000>;
5209 hyste 3705 hysteresis = <1000>;
5210 type 3706 type = "passive";
5211 }; 3707 };
5212 3708
5213 thermal-hal-c 3709 thermal-hal-config {
5214 tempe 3710 temperature = <125000>;
5215 hyste 3711 hysteresis = <1000>;
5216 type 3712 type = "passive";
5217 }; 3713 };
5218 3714
5219 reset-mon-cfg 3715 reset-mon-cfg {
5220 tempe 3716 temperature = <115000>;
5221 hyste 3717 hysteresis = <5000>;
5222 type 3718 type = "passive";
5223 }; 3719 };
5224 3720
5225 cdsp_0_config 3721 cdsp_0_config: junction-config {
5226 tempe 3722 temperature = <95000>;
5227 hyste 3723 hysteresis = <5000>;
5228 type 3724 type = "passive";
5229 }; 3725 };
5230 }; 3726 };
5231 }; 3727 };
5232 3728
5233 cdsp1-thermal { 3729 cdsp1-thermal {
5234 polling-delay-passive 3730 polling-delay-passive = <10>;
5235 !! 3731 polling-delay = <0>;
5236 thermal-sensors = <&t 3732 thermal-sensors = <&tsens1 6>;
5237 3733
5238 trips { 3734 trips {
5239 thermal-engin 3735 thermal-engine-config {
5240 tempe 3736 temperature = <125000>;
5241 hyste 3737 hysteresis = <1000>;
5242 type 3738 type = "passive";
5243 }; 3739 };
5244 3740
5245 thermal-hal-c 3741 thermal-hal-config {
5246 tempe 3742 temperature = <125000>;
5247 hyste 3743 hysteresis = <1000>;
5248 type 3744 type = "passive";
5249 }; 3745 };
5250 3746
5251 reset-mon-cfg 3747 reset-mon-cfg {
5252 tempe 3748 temperature = <115000>;
5253 hyste 3749 hysteresis = <5000>;
5254 type 3750 type = "passive";
5255 }; 3751 };
5256 3752
5257 cdsp_1_config 3753 cdsp_1_config: junction-config {
5258 tempe 3754 temperature = <95000>;
5259 hyste 3755 hysteresis = <5000>;
5260 type 3756 type = "passive";
5261 }; 3757 };
5262 }; 3758 };
5263 }; 3759 };
5264 3760
5265 cdsp2-thermal { 3761 cdsp2-thermal {
5266 polling-delay-passive 3762 polling-delay-passive = <10>;
5267 !! 3763 polling-delay = <0>;
5268 thermal-sensors = <&t 3764 thermal-sensors = <&tsens1 7>;
5269 3765
5270 trips { 3766 trips {
5271 thermal-engin 3767 thermal-engine-config {
5272 tempe 3768 temperature = <125000>;
5273 hyste 3769 hysteresis = <1000>;
5274 type 3770 type = "passive";
5275 }; 3771 };
5276 3772
5277 thermal-hal-c 3773 thermal-hal-config {
5278 tempe 3774 temperature = <125000>;
5279 hyste 3775 hysteresis = <1000>;
5280 type 3776 type = "passive";
5281 }; 3777 };
5282 3778
5283 reset-mon-cfg 3779 reset-mon-cfg {
5284 tempe 3780 temperature = <115000>;
5285 hyste 3781 hysteresis = <5000>;
5286 type 3782 type = "passive";
5287 }; 3783 };
5288 3784
5289 cdsp_2_config 3785 cdsp_2_config: junction-config {
5290 tempe 3786 temperature = <95000>;
5291 hyste 3787 hysteresis = <5000>;
5292 type 3788 type = "passive";
5293 }; 3789 };
5294 }; 3790 };
5295 }; 3791 };
5296 3792
5297 video-thermal { 3793 video-thermal {
>> 3794 polling-delay-passive = <0>;
>> 3795 polling-delay = <0>;
5298 thermal-sensors = <&t 3796 thermal-sensors = <&tsens1 8>;
5299 3797
5300 trips { 3798 trips {
5301 thermal-engin 3799 thermal-engine-config {
5302 tempe 3800 temperature = <125000>;
5303 hyste 3801 hysteresis = <1000>;
5304 type 3802 type = "passive";
5305 }; 3803 };
5306 3804
5307 reset-mon-cfg 3805 reset-mon-cfg {
5308 tempe 3806 temperature = <115000>;
5309 hyste 3807 hysteresis = <5000>;
5310 type 3808 type = "passive";
5311 }; 3809 };
5312 }; 3810 };
5313 }; 3811 };
5314 3812
5315 mem-thermal { 3813 mem-thermal {
5316 polling-delay-passive 3814 polling-delay-passive = <10>;
5317 !! 3815 polling-delay = <0>;
5318 thermal-sensors = <&t 3816 thermal-sensors = <&tsens1 9>;
5319 3817
5320 trips { 3818 trips {
5321 thermal-engin 3819 thermal-engine-config {
5322 tempe 3820 temperature = <125000>;
5323 hyste 3821 hysteresis = <1000>;
5324 type 3822 type = "passive";
5325 }; 3823 };
5326 3824
5327 ddr_config0: 3825 ddr_config0: ddr0-config {
5328 tempe 3826 temperature = <90000>;
5329 hyste 3827 hysteresis = <5000>;
5330 type 3828 type = "passive";
5331 }; 3829 };
5332 3830
5333 reset-mon-cfg 3831 reset-mon-cfg {
5334 tempe 3832 temperature = <115000>;
5335 hyste 3833 hysteresis = <5000>;
5336 type 3834 type = "passive";
5337 }; 3835 };
5338 }; 3836 };
5339 }; 3837 };
5340 3838
5341 modem0-thermal { 3839 modem0-thermal {
>> 3840 polling-delay-passive = <0>;
>> 3841 polling-delay = <0>;
5342 thermal-sensors = <&t 3842 thermal-sensors = <&tsens1 10>;
5343 3843
5344 trips { 3844 trips {
5345 thermal-engin 3845 thermal-engine-config {
5346 tempe 3846 temperature = <125000>;
5347 hyste 3847 hysteresis = <1000>;
5348 type 3848 type = "passive";
5349 }; 3849 };
5350 3850
5351 mdmss0_config 3851 mdmss0_config0: mdmss0-config0 {
5352 tempe 3852 temperature = <102000>;
5353 hyste 3853 hysteresis = <3000>;
5354 type 3854 type = "passive";
5355 }; 3855 };
5356 3856
5357 mdmss0_config 3857 mdmss0_config1: mdmss0-config1 {
5358 tempe 3858 temperature = <105000>;
5359 hyste 3859 hysteresis = <3000>;
5360 type 3860 type = "passive";
5361 }; 3861 };
5362 3862
5363 reset-mon-cfg 3863 reset-mon-cfg {
5364 tempe 3864 temperature = <115000>;
5365 hyste 3865 hysteresis = <5000>;
5366 type 3866 type = "passive";
5367 }; 3867 };
5368 }; 3868 };
5369 }; 3869 };
5370 3870
5371 modem1-thermal { 3871 modem1-thermal {
>> 3872 polling-delay-passive = <0>;
>> 3873 polling-delay = <0>;
5372 thermal-sensors = <&t 3874 thermal-sensors = <&tsens1 11>;
5373 3875
5374 trips { 3876 trips {
5375 thermal-engin 3877 thermal-engine-config {
5376 tempe 3878 temperature = <125000>;
5377 hyste 3879 hysteresis = <1000>;
5378 type 3880 type = "passive";
5379 }; 3881 };
5380 3882
5381 mdmss1_config 3883 mdmss1_config0: mdmss1-config0 {
5382 tempe 3884 temperature = <102000>;
5383 hyste 3885 hysteresis = <3000>;
5384 type 3886 type = "passive";
5385 }; 3887 };
5386 3888
5387 mdmss1_config 3889 mdmss1_config1: mdmss1-config1 {
5388 tempe 3890 temperature = <105000>;
5389 hyste 3891 hysteresis = <3000>;
5390 type 3892 type = "passive";
5391 }; 3893 };
5392 3894
5393 reset-mon-cfg 3895 reset-mon-cfg {
5394 tempe 3896 temperature = <115000>;
5395 hyste 3897 hysteresis = <5000>;
5396 type 3898 type = "passive";
5397 }; 3899 };
5398 }; 3900 };
5399 }; 3901 };
5400 3902
5401 modem2-thermal { 3903 modem2-thermal {
>> 3904 polling-delay-passive = <0>;
>> 3905 polling-delay = <0>;
5402 thermal-sensors = <&t 3906 thermal-sensors = <&tsens1 12>;
5403 3907
5404 trips { 3908 trips {
5405 thermal-engin 3909 thermal-engine-config {
5406 tempe 3910 temperature = <125000>;
5407 hyste 3911 hysteresis = <1000>;
5408 type 3912 type = "passive";
5409 }; 3913 };
5410 3914
5411 mdmss2_config 3915 mdmss2_config0: mdmss2-config0 {
5412 tempe 3916 temperature = <102000>;
5413 hyste 3917 hysteresis = <3000>;
5414 type 3918 type = "passive";
5415 }; 3919 };
5416 3920
5417 mdmss2_config 3921 mdmss2_config1: mdmss2-config1 {
5418 tempe 3922 temperature = <105000>;
5419 hyste 3923 hysteresis = <3000>;
5420 type 3924 type = "passive";
5421 }; 3925 };
5422 3926
5423 reset-mon-cfg 3927 reset-mon-cfg {
5424 tempe 3928 temperature = <115000>;
5425 hyste 3929 hysteresis = <5000>;
5426 type 3930 type = "passive";
5427 }; 3931 };
5428 }; 3932 };
5429 }; 3933 };
5430 3934
5431 modem3-thermal { 3935 modem3-thermal {
>> 3936 polling-delay-passive = <0>;
>> 3937 polling-delay = <0>;
5432 thermal-sensors = <&t 3938 thermal-sensors = <&tsens1 13>;
5433 3939
5434 trips { 3940 trips {
5435 thermal-engin 3941 thermal-engine-config {
5436 tempe 3942 temperature = <125000>;
5437 hyste 3943 hysteresis = <1000>;
5438 type 3944 type = "passive";
5439 }; 3945 };
5440 3946
5441 mdmss3_config 3947 mdmss3_config0: mdmss3-config0 {
5442 tempe 3948 temperature = <102000>;
5443 hyste 3949 hysteresis = <3000>;
5444 type 3950 type = "passive";
5445 }; 3951 };
5446 3952
5447 mdmss3_config 3953 mdmss3_config1: mdmss3-config1 {
5448 tempe 3954 temperature = <105000>;
5449 hyste 3955 hysteresis = <3000>;
5450 type 3956 type = "passive";
5451 }; 3957 };
5452 3958
5453 reset-mon-cfg 3959 reset-mon-cfg {
5454 tempe 3960 temperature = <115000>;
5455 hyste 3961 hysteresis = <5000>;
5456 type 3962 type = "passive";
5457 }; 3963 };
5458 }; 3964 };
5459 }; 3965 };
5460 3966
5461 camera0-thermal { 3967 camera0-thermal {
>> 3968 polling-delay-passive = <0>;
>> 3969 polling-delay = <0>;
5462 thermal-sensors = <&t 3970 thermal-sensors = <&tsens1 14>;
5463 3971
5464 trips { 3972 trips {
5465 thermal-engin 3973 thermal-engine-config {
5466 tempe 3974 temperature = <125000>;
5467 hyste 3975 hysteresis = <1000>;
5468 type 3976 type = "passive";
5469 }; 3977 };
5470 3978
5471 reset-mon-cfg 3979 reset-mon-cfg {
5472 tempe 3980 temperature = <115000>;
5473 hyste 3981 hysteresis = <5000>;
5474 type 3982 type = "passive";
5475 }; 3983 };
5476 }; 3984 };
5477 }; 3985 };
5478 3986
5479 camera1-thermal { 3987 camera1-thermal {
>> 3988 polling-delay-passive = <0>;
>> 3989 polling-delay = <0>;
5480 thermal-sensors = <&t 3990 thermal-sensors = <&tsens1 15>;
5481 3991
5482 trips { 3992 trips {
5483 thermal-engin 3993 thermal-engine-config {
5484 tempe 3994 temperature = <125000>;
5485 hyste 3995 hysteresis = <1000>;
5486 type 3996 type = "passive";
5487 }; 3997 };
5488 3998
5489 reset-mon-cfg 3999 reset-mon-cfg {
5490 tempe 4000 temperature = <115000>;
5491 hyste 4001 hysteresis = <5000>;
5492 type 4002 type = "passive";
5493 }; 4003 };
5494 }; 4004 };
5495 }; 4005 };
5496 }; 4006 };
5497 4007
5498 timer { 4008 timer {
5499 compatible = "arm,armv8-timer 4009 compatible = "arm,armv8-timer";
5500 interrupts = <GIC_PPI 13 (GIC 4010 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5501 <GIC_PPI 14 (GIC 4011 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5502 <GIC_PPI 11 (GIC 4012 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5503 <GIC_PPI 10 (GIC 4013 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
5504 clock-frequency = <19200000>; 4014 clock-frequency = <19200000>;
5505 }; 4015 };
5506 }; 4016 };
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