1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * Copyright (c) 2021, Linaro Limited 3 * Copyright (c) 2021, Linaro Limited
4 */ 4 */
5 5
6 #include <dt-bindings/interrupt-controller/arm 6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-sm8450.h> 7 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
8 #include <dt-bindings/clock/qcom,rpmh.h> 8 #include <dt-bindings/clock/qcom,rpmh.h>
9 #include <dt-bindings/clock/qcom,sm8450-camcc. 9 #include <dt-bindings/clock/qcom,sm8450-camcc.h>
10 #include <dt-bindings/clock/qcom,sm8450-dispcc <<
11 #include <dt-bindings/clock/qcom,sm8450-gpucc. <<
12 #include <dt-bindings/clock/qcom,sm8450-videoc <<
13 #include <dt-bindings/dma/qcom-gpi.h> 10 #include <dt-bindings/dma/qcom-gpi.h>
14 #include <dt-bindings/firmware/qcom,scm.h> <<
15 #include <dt-bindings/gpio/gpio.h> 11 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/mailbox/qcom-ipcc.h> 12 #include <dt-bindings/mailbox/qcom-ipcc.h>
17 #include <dt-bindings/phy/phy-qcom-qmp.h> <<
18 #include <dt-bindings/power/qcom,rpmhpd.h> <<
19 #include <dt-bindings/power/qcom-rpmpd.h> 13 #include <dt-bindings/power/qcom-rpmpd.h>
20 #include <dt-bindings/interconnect/qcom,icc.h> <<
21 #include <dt-bindings/interconnect/qcom,sm8450 14 #include <dt-bindings/interconnect/qcom,sm8450.h>
22 #include <dt-bindings/reset/qcom,sm8450-gpucc. <<
23 #include <dt-bindings/soc/qcom,gpr.h> <<
24 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 15 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
25 #include <dt-bindings/sound/qcom,q6dsp-lpass-p <<
26 #include <dt-bindings/thermal/thermal.h> 16 #include <dt-bindings/thermal/thermal.h>
27 17
28 / { 18 / {
29 interrupt-parent = <&intc>; 19 interrupt-parent = <&intc>;
30 20
31 #address-cells = <2>; 21 #address-cells = <2>;
32 #size-cells = <2>; 22 #size-cells = <2>;
33 23
34 chosen { }; 24 chosen { };
35 25
36 clocks { 26 clocks {
37 xo_board: xo-board { 27 xo_board: xo-board {
38 compatible = "fixed-cl 28 compatible = "fixed-clock";
39 #clock-cells = <0>; 29 #clock-cells = <0>;
40 clock-frequency = <768 30 clock-frequency = <76800000>;
41 }; 31 };
42 32
43 sleep_clk: sleep-clk { 33 sleep_clk: sleep-clk {
44 compatible = "fixed-cl 34 compatible = "fixed-clock";
45 #clock-cells = <0>; 35 #clock-cells = <0>;
46 clock-frequency = <320 36 clock-frequency = <32000>;
47 }; 37 };
48 }; 38 };
49 39
50 cpus { 40 cpus {
51 #address-cells = <2>; 41 #address-cells = <2>;
52 #size-cells = <0>; 42 #size-cells = <0>;
53 43
54 CPU0: cpu@0 { 44 CPU0: cpu@0 {
55 device_type = "cpu"; 45 device_type = "cpu";
56 compatible = "qcom,kry 46 compatible = "qcom,kryo780";
57 reg = <0x0 0x0>; 47 reg = <0x0 0x0>;
58 enable-method = "psci" 48 enable-method = "psci";
59 next-level-cache = <&L 49 next-level-cache = <&L2_0>;
60 power-domains = <&CPU_ 50 power-domains = <&CPU_PD0>;
61 power-domain-names = " 51 power-domain-names = "psci";
62 qcom,freq-domain = <&c 52 qcom,freq-domain = <&cpufreq_hw 0>;
63 #cooling-cells = <2>; 53 #cooling-cells = <2>;
64 clocks = <&cpufreq_hw <<
65 L2_0: l2-cache { 54 L2_0: l2-cache {
66 compatible = " !! 55 compatible = "cache";
67 cache-level = !! 56 next-level-cache = <&L3_0>;
68 cache-unified; <<
69 next-level-cac <<
70 L3_0: l3-cache 57 L3_0: l3-cache {
71 compat !! 58 compatible = "cache";
72 cache- <<
73 cache- <<
74 }; 59 };
75 }; 60 };
76 }; 61 };
77 62
78 CPU1: cpu@100 { 63 CPU1: cpu@100 {
79 device_type = "cpu"; 64 device_type = "cpu";
80 compatible = "qcom,kry 65 compatible = "qcom,kryo780";
81 reg = <0x0 0x100>; 66 reg = <0x0 0x100>;
82 enable-method = "psci" 67 enable-method = "psci";
83 next-level-cache = <&L 68 next-level-cache = <&L2_100>;
84 power-domains = <&CPU_ 69 power-domains = <&CPU_PD1>;
85 power-domain-names = " 70 power-domain-names = "psci";
86 qcom,freq-domain = <&c 71 qcom,freq-domain = <&cpufreq_hw 0>;
87 #cooling-cells = <2>; 72 #cooling-cells = <2>;
88 clocks = <&cpufreq_hw <<
89 L2_100: l2-cache { 73 L2_100: l2-cache {
90 compatible = " !! 74 compatible = "cache";
91 cache-level = !! 75 next-level-cache = <&L3_0>;
92 cache-unified; <<
93 next-level-cac <<
94 }; 76 };
95 }; 77 };
96 78
97 CPU2: cpu@200 { 79 CPU2: cpu@200 {
98 device_type = "cpu"; 80 device_type = "cpu";
99 compatible = "qcom,kry 81 compatible = "qcom,kryo780";
100 reg = <0x0 0x200>; 82 reg = <0x0 0x200>;
101 enable-method = "psci" 83 enable-method = "psci";
102 next-level-cache = <&L 84 next-level-cache = <&L2_200>;
103 power-domains = <&CPU_ 85 power-domains = <&CPU_PD2>;
104 power-domain-names = " 86 power-domain-names = "psci";
105 qcom,freq-domain = <&c 87 qcom,freq-domain = <&cpufreq_hw 0>;
106 #cooling-cells = <2>; 88 #cooling-cells = <2>;
107 clocks = <&cpufreq_hw <<
108 L2_200: l2-cache { 89 L2_200: l2-cache {
109 compatible = " !! 90 compatible = "cache";
110 cache-level = !! 91 next-level-cache = <&L3_0>;
111 cache-unified; <<
112 next-level-cac <<
113 }; 92 };
114 }; 93 };
115 94
116 CPU3: cpu@300 { 95 CPU3: cpu@300 {
117 device_type = "cpu"; 96 device_type = "cpu";
118 compatible = "qcom,kry 97 compatible = "qcom,kryo780";
119 reg = <0x0 0x300>; 98 reg = <0x0 0x300>;
120 enable-method = "psci" 99 enable-method = "psci";
121 next-level-cache = <&L 100 next-level-cache = <&L2_300>;
122 power-domains = <&CPU_ 101 power-domains = <&CPU_PD3>;
123 power-domain-names = " 102 power-domain-names = "psci";
124 qcom,freq-domain = <&c 103 qcom,freq-domain = <&cpufreq_hw 0>;
125 #cooling-cells = <2>; 104 #cooling-cells = <2>;
126 clocks = <&cpufreq_hw <<
127 L2_300: l2-cache { 105 L2_300: l2-cache {
128 compatible = " !! 106 compatible = "cache";
129 cache-level = !! 107 next-level-cache = <&L3_0>;
130 cache-unified; <<
131 next-level-cac <<
132 }; 108 };
133 }; 109 };
134 110
135 CPU4: cpu@400 { 111 CPU4: cpu@400 {
136 device_type = "cpu"; 112 device_type = "cpu";
137 compatible = "qcom,kry 113 compatible = "qcom,kryo780";
138 reg = <0x0 0x400>; 114 reg = <0x0 0x400>;
139 enable-method = "psci" 115 enable-method = "psci";
140 next-level-cache = <&L 116 next-level-cache = <&L2_400>;
141 power-domains = <&CPU_ 117 power-domains = <&CPU_PD4>;
142 power-domain-names = " 118 power-domain-names = "psci";
143 qcom,freq-domain = <&c 119 qcom,freq-domain = <&cpufreq_hw 1>;
144 #cooling-cells = <2>; 120 #cooling-cells = <2>;
145 clocks = <&cpufreq_hw <<
146 L2_400: l2-cache { 121 L2_400: l2-cache {
147 compatible = " !! 122 compatible = "cache";
148 cache-level = !! 123 next-level-cache = <&L3_0>;
149 cache-unified; <<
150 next-level-cac <<
151 }; 124 };
152 }; 125 };
153 126
154 CPU5: cpu@500 { 127 CPU5: cpu@500 {
155 device_type = "cpu"; 128 device_type = "cpu";
156 compatible = "qcom,kry 129 compatible = "qcom,kryo780";
157 reg = <0x0 0x500>; 130 reg = <0x0 0x500>;
158 enable-method = "psci" 131 enable-method = "psci";
159 next-level-cache = <&L 132 next-level-cache = <&L2_500>;
160 power-domains = <&CPU_ 133 power-domains = <&CPU_PD5>;
161 power-domain-names = " 134 power-domain-names = "psci";
162 qcom,freq-domain = <&c 135 qcom,freq-domain = <&cpufreq_hw 1>;
163 #cooling-cells = <2>; 136 #cooling-cells = <2>;
164 clocks = <&cpufreq_hw <<
165 L2_500: l2-cache { 137 L2_500: l2-cache {
166 compatible = " !! 138 compatible = "cache";
167 cache-level = !! 139 next-level-cache = <&L3_0>;
168 cache-unified; <<
169 next-level-cac <<
170 }; 140 };
>> 141
171 }; 142 };
172 143
173 CPU6: cpu@600 { 144 CPU6: cpu@600 {
174 device_type = "cpu"; 145 device_type = "cpu";
175 compatible = "qcom,kry 146 compatible = "qcom,kryo780";
176 reg = <0x0 0x600>; 147 reg = <0x0 0x600>;
177 enable-method = "psci" 148 enable-method = "psci";
178 next-level-cache = <&L 149 next-level-cache = <&L2_600>;
179 power-domains = <&CPU_ 150 power-domains = <&CPU_PD6>;
180 power-domain-names = " 151 power-domain-names = "psci";
181 qcom,freq-domain = <&c 152 qcom,freq-domain = <&cpufreq_hw 1>;
182 #cooling-cells = <2>; 153 #cooling-cells = <2>;
183 clocks = <&cpufreq_hw <<
184 L2_600: l2-cache { 154 L2_600: l2-cache {
185 compatible = " !! 155 compatible = "cache";
186 cache-level = !! 156 next-level-cache = <&L3_0>;
187 cache-unified; <<
188 next-level-cac <<
189 }; 157 };
190 }; 158 };
191 159
192 CPU7: cpu@700 { 160 CPU7: cpu@700 {
193 device_type = "cpu"; 161 device_type = "cpu";
194 compatible = "qcom,kry 162 compatible = "qcom,kryo780";
195 reg = <0x0 0x700>; 163 reg = <0x0 0x700>;
196 enable-method = "psci" 164 enable-method = "psci";
197 next-level-cache = <&L 165 next-level-cache = <&L2_700>;
198 power-domains = <&CPU_ 166 power-domains = <&CPU_PD7>;
199 power-domain-names = " 167 power-domain-names = "psci";
200 qcom,freq-domain = <&c 168 qcom,freq-domain = <&cpufreq_hw 2>;
201 #cooling-cells = <2>; 169 #cooling-cells = <2>;
202 clocks = <&cpufreq_hw <<
203 L2_700: l2-cache { 170 L2_700: l2-cache {
204 compatible = " !! 171 compatible = "cache";
205 cache-level = !! 172 next-level-cache = <&L3_0>;
206 cache-unified; <<
207 next-level-cac <<
208 }; 173 };
209 }; 174 };
210 175
211 cpu-map { 176 cpu-map {
212 cluster0 { 177 cluster0 {
213 core0 { 178 core0 {
214 cpu = 179 cpu = <&CPU0>;
215 }; 180 };
216 181
217 core1 { 182 core1 {
218 cpu = 183 cpu = <&CPU1>;
219 }; 184 };
220 185
221 core2 { 186 core2 {
222 cpu = 187 cpu = <&CPU2>;
223 }; 188 };
224 189
225 core3 { 190 core3 {
226 cpu = 191 cpu = <&CPU3>;
227 }; 192 };
228 193
229 core4 { 194 core4 {
230 cpu = 195 cpu = <&CPU4>;
231 }; 196 };
232 197
233 core5 { 198 core5 {
234 cpu = 199 cpu = <&CPU5>;
235 }; 200 };
236 201
237 core6 { 202 core6 {
238 cpu = 203 cpu = <&CPU6>;
239 }; 204 };
240 205
241 core7 { 206 core7 {
242 cpu = 207 cpu = <&CPU7>;
243 }; 208 };
244 }; 209 };
245 }; 210 };
246 211
247 idle-states { 212 idle-states {
248 entry-method = "psci"; 213 entry-method = "psci";
249 214
250 LITTLE_CPU_SLEEP_0: cp 215 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
251 compatible = " 216 compatible = "arm,idle-state";
252 idle-state-nam 217 idle-state-name = "silver-rail-power-collapse";
253 arm,psci-suspe 218 arm,psci-suspend-param = <0x40000004>;
254 entry-latency- 219 entry-latency-us = <800>;
255 exit-latency-u 220 exit-latency-us = <750>;
256 min-residency- 221 min-residency-us = <4090>;
257 local-timer-st 222 local-timer-stop;
258 }; 223 };
259 224
260 BIG_CPU_SLEEP_0: cpu-s 225 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
261 compatible = " 226 compatible = "arm,idle-state";
262 idle-state-nam 227 idle-state-name = "gold-rail-power-collapse";
263 arm,psci-suspe 228 arm,psci-suspend-param = <0x40000004>;
264 entry-latency- 229 entry-latency-us = <600>;
265 exit-latency-u 230 exit-latency-us = <1550>;
266 min-residency- 231 min-residency-us = <4791>;
267 local-timer-st 232 local-timer-stop;
268 }; 233 };
269 }; 234 };
270 235
271 domain-idle-states { 236 domain-idle-states {
272 CLUSTER_SLEEP_0: clust 237 CLUSTER_SLEEP_0: cluster-sleep-0 {
273 compatible = " 238 compatible = "domain-idle-state";
>> 239 idle-state-name = "cluster-l3-off";
274 arm,psci-suspe 240 arm,psci-suspend-param = <0x41000044>;
275 entry-latency- 241 entry-latency-us = <1050>;
276 exit-latency-u 242 exit-latency-us = <2500>;
277 min-residency- 243 min-residency-us = <5309>;
>> 244 local-timer-stop;
278 }; 245 };
279 246
280 CLUSTER_SLEEP_1: clust 247 CLUSTER_SLEEP_1: cluster-sleep-1 {
281 compatible = " 248 compatible = "domain-idle-state";
>> 249 idle-state-name = "cluster-power-collapse";
282 arm,psci-suspe 250 arm,psci-suspend-param = <0x4100c344>;
283 entry-latency- 251 entry-latency-us = <2700>;
284 exit-latency-u 252 exit-latency-us = <3500>;
285 min-residency- 253 min-residency-us = <13959>;
>> 254 local-timer-stop;
286 }; 255 };
287 }; 256 };
288 }; 257 };
289 258
290 firmware { 259 firmware {
291 scm: scm { 260 scm: scm {
292 compatible = "qcom,scm 261 compatible = "qcom,scm-sm8450", "qcom,scm";
293 qcom,dload-mode = <&tc <<
294 interconnects = <&aggr 262 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
295 #reset-cells = <1>; 263 #reset-cells = <1>;
296 }; 264 };
297 }; 265 };
298 266
299 clk_virt: interconnect-0 { 267 clk_virt: interconnect-0 {
300 compatible = "qcom,sm8450-clk- 268 compatible = "qcom,sm8450-clk-virt";
301 #interconnect-cells = <2>; 269 #interconnect-cells = <2>;
302 qcom,bcm-voters = <&apps_bcm_v 270 qcom,bcm-voters = <&apps_bcm_voter>;
303 }; 271 };
304 272
305 mc_virt: interconnect-1 { 273 mc_virt: interconnect-1 {
306 compatible = "qcom,sm8450-mc-v 274 compatible = "qcom,sm8450-mc-virt";
307 #interconnect-cells = <2>; 275 #interconnect-cells = <2>;
308 qcom,bcm-voters = <&apps_bcm_v 276 qcom,bcm-voters = <&apps_bcm_voter>;
309 }; 277 };
310 278
311 memory@a0000000 { 279 memory@a0000000 {
312 device_type = "memory"; 280 device_type = "memory";
313 /* We expect the bootloader to 281 /* We expect the bootloader to fill in the size */
314 reg = <0x0 0xa0000000 0x0 0x0> 282 reg = <0x0 0xa0000000 0x0 0x0>;
315 }; 283 };
316 284
317 pmu { 285 pmu {
318 compatible = "arm,armv8-pmuv3" 286 compatible = "arm,armv8-pmuv3";
319 interrupts = <GIC_PPI 7 IRQ_TY 287 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
320 }; 288 };
321 289
322 psci { 290 psci {
323 compatible = "arm,psci-1.0"; 291 compatible = "arm,psci-1.0";
324 method = "smc"; 292 method = "smc";
325 293
326 CPU_PD0: power-domain-cpu0 { !! 294 CPU_PD0: cpu0 {
327 #power-domain-cells = 295 #power-domain-cells = <0>;
328 power-domains = <&CLUS 296 power-domains = <&CLUSTER_PD>;
329 domain-idle-states = < 297 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
330 }; 298 };
331 299
332 CPU_PD1: power-domain-cpu1 { !! 300 CPU_PD1: cpu1 {
333 #power-domain-cells = 301 #power-domain-cells = <0>;
334 power-domains = <&CLUS 302 power-domains = <&CLUSTER_PD>;
335 domain-idle-states = < 303 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
336 }; 304 };
337 305
338 CPU_PD2: power-domain-cpu2 { !! 306 CPU_PD2: cpu2 {
339 #power-domain-cells = 307 #power-domain-cells = <0>;
340 power-domains = <&CLUS 308 power-domains = <&CLUSTER_PD>;
341 domain-idle-states = < 309 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
342 }; 310 };
343 311
344 CPU_PD3: power-domain-cpu3 { !! 312 CPU_PD3: cpu3 {
345 #power-domain-cells = 313 #power-domain-cells = <0>;
346 power-domains = <&CLUS 314 power-domains = <&CLUSTER_PD>;
347 domain-idle-states = < 315 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
348 }; 316 };
349 317
350 CPU_PD4: power-domain-cpu4 { !! 318 CPU_PD4: cpu4 {
351 #power-domain-cells = 319 #power-domain-cells = <0>;
352 power-domains = <&CLUS 320 power-domains = <&CLUSTER_PD>;
353 domain-idle-states = < 321 domain-idle-states = <&BIG_CPU_SLEEP_0>;
354 }; 322 };
355 323
356 CPU_PD5: power-domain-cpu5 { !! 324 CPU_PD5: cpu5 {
357 #power-domain-cells = 325 #power-domain-cells = <0>;
358 power-domains = <&CLUS 326 power-domains = <&CLUSTER_PD>;
359 domain-idle-states = < 327 domain-idle-states = <&BIG_CPU_SLEEP_0>;
360 }; 328 };
361 329
362 CPU_PD6: power-domain-cpu6 { !! 330 CPU_PD6: cpu6 {
363 #power-domain-cells = 331 #power-domain-cells = <0>;
364 power-domains = <&CLUS 332 power-domains = <&CLUSTER_PD>;
365 domain-idle-states = < 333 domain-idle-states = <&BIG_CPU_SLEEP_0>;
366 }; 334 };
367 335
368 CPU_PD7: power-domain-cpu7 { !! 336 CPU_PD7: cpu7 {
369 #power-domain-cells = 337 #power-domain-cells = <0>;
370 power-domains = <&CLUS 338 power-domains = <&CLUSTER_PD>;
371 domain-idle-states = < 339 domain-idle-states = <&BIG_CPU_SLEEP_0>;
372 }; 340 };
373 341
374 CLUSTER_PD: power-domain-cpu-c !! 342 CLUSTER_PD: cpu-cluster0 {
375 #power-domain-cells = 343 #power-domain-cells = <0>;
376 domain-idle-states = < 344 domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>;
377 }; 345 };
378 }; 346 };
379 347
380 qup_opp_table_100mhz: opp-table-qup { 348 qup_opp_table_100mhz: opp-table-qup {
381 compatible = "operating-points 349 compatible = "operating-points-v2";
382 350
383 opp-50000000 { 351 opp-50000000 {
384 opp-hz = /bits/ 64 <50 352 opp-hz = /bits/ 64 <50000000>;
385 required-opps = <&rpmh 353 required-opps = <&rpmhpd_opp_min_svs>;
386 }; 354 };
387 355
388 opp-75000000 { 356 opp-75000000 {
389 opp-hz = /bits/ 64 <75 357 opp-hz = /bits/ 64 <75000000>;
390 required-opps = <&rpmh 358 required-opps = <&rpmhpd_opp_low_svs>;
391 }; 359 };
392 360
393 opp-100000000 { 361 opp-100000000 {
394 opp-hz = /bits/ 64 <10 362 opp-hz = /bits/ 64 <100000000>;
395 required-opps = <&rpmh 363 required-opps = <&rpmhpd_opp_svs>;
396 }; 364 };
397 }; 365 };
398 366
399 reserved_memory: reserved-memory { 367 reserved_memory: reserved-memory {
400 #address-cells = <2>; 368 #address-cells = <2>;
401 #size-cells = <2>; 369 #size-cells = <2>;
402 ranges; 370 ranges;
403 371
404 hyp_mem: memory@80000000 { 372 hyp_mem: memory@80000000 {
405 reg = <0x0 0x80000000 373 reg = <0x0 0x80000000 0x0 0x600000>;
406 no-map; 374 no-map;
407 }; 375 };
408 376
409 xbl_dt_log_mem: memory@8060000 377 xbl_dt_log_mem: memory@80600000 {
410 reg = <0x0 0x80600000 378 reg = <0x0 0x80600000 0x0 0x40000>;
411 no-map; 379 no-map;
412 }; 380 };
413 381
414 xbl_ramdump_mem: memory@806400 382 xbl_ramdump_mem: memory@80640000 {
415 reg = <0x0 0x80640000 383 reg = <0x0 0x80640000 0x0 0x180000>;
416 no-map; 384 no-map;
417 }; 385 };
418 386
419 xbl_sc_mem: memory@807c0000 { 387 xbl_sc_mem: memory@807c0000 {
420 reg = <0x0 0x807c0000 388 reg = <0x0 0x807c0000 0x0 0x40000>;
421 no-map; 389 no-map;
422 }; 390 };
423 391
424 aop_image_mem: memory@80800000 392 aop_image_mem: memory@80800000 {
425 reg = <0x0 0x80800000 393 reg = <0x0 0x80800000 0x0 0x60000>;
426 no-map; 394 no-map;
427 }; 395 };
428 396
429 aop_cmd_db_mem: memory@8086000 397 aop_cmd_db_mem: memory@80860000 {
430 compatible = "qcom,cmd 398 compatible = "qcom,cmd-db";
431 reg = <0x0 0x80860000 399 reg = <0x0 0x80860000 0x0 0x20000>;
432 no-map; 400 no-map;
433 }; 401 };
434 402
435 aop_config_mem: memory@8088000 403 aop_config_mem: memory@80880000 {
436 reg = <0x0 0x80880000 404 reg = <0x0 0x80880000 0x0 0x20000>;
437 no-map; 405 no-map;
438 }; 406 };
439 407
440 tme_crash_dump_mem: memory@808 408 tme_crash_dump_mem: memory@808a0000 {
441 reg = <0x0 0x808a0000 409 reg = <0x0 0x808a0000 0x0 0x40000>;
442 no-map; 410 no-map;
443 }; 411 };
444 412
445 tme_log_mem: memory@808e0000 { 413 tme_log_mem: memory@808e0000 {
446 reg = <0x0 0x808e0000 414 reg = <0x0 0x808e0000 0x0 0x4000>;
447 no-map; 415 no-map;
448 }; 416 };
449 417
450 uefi_log_mem: memory@808e4000 418 uefi_log_mem: memory@808e4000 {
451 reg = <0x0 0x808e4000 419 reg = <0x0 0x808e4000 0x0 0x10000>;
452 no-map; 420 no-map;
453 }; 421 };
454 422
455 /* secdata region can be reuse 423 /* secdata region can be reused by apps */
456 smem: memory@80900000 { 424 smem: memory@80900000 {
457 compatible = "qcom,sme 425 compatible = "qcom,smem";
458 reg = <0x0 0x80900000 426 reg = <0x0 0x80900000 0x0 0x200000>;
459 hwlocks = <&tcsr_mutex 427 hwlocks = <&tcsr_mutex 3>;
460 no-map; 428 no-map;
461 }; 429 };
462 430
463 cpucp_fw_mem: memory@80b00000 431 cpucp_fw_mem: memory@80b00000 {
464 reg = <0x0 0x80b00000 432 reg = <0x0 0x80b00000 0x0 0x100000>;
465 no-map; 433 no-map;
466 }; 434 };
467 435
468 cdsp_secure_heap: memory@80c00 436 cdsp_secure_heap: memory@80c00000 {
469 reg = <0x0 0x80c00000 437 reg = <0x0 0x80c00000 0x0 0x4600000>;
470 no-map; 438 no-map;
471 }; 439 };
472 440
>> 441 camera_mem: memory@85200000 {
>> 442 reg = <0x0 0x85200000 0x0 0x500000>;
>> 443 no-map;
>> 444 };
>> 445
473 video_mem: memory@85700000 { 446 video_mem: memory@85700000 {
474 reg = <0x0 0x85700000 447 reg = <0x0 0x85700000 0x0 0x700000>;
475 no-map; 448 no-map;
476 }; 449 };
477 450
478 adsp_mem: memory@85e00000 { 451 adsp_mem: memory@85e00000 {
479 reg = <0x0 0x85e00000 452 reg = <0x0 0x85e00000 0x0 0x2100000>;
480 no-map; 453 no-map;
481 }; 454 };
482 455
483 slpi_mem: memory@88000000 { 456 slpi_mem: memory@88000000 {
484 reg = <0x0 0x88000000 457 reg = <0x0 0x88000000 0x0 0x1900000>;
485 no-map; 458 no-map;
486 }; 459 };
487 460
488 cdsp_mem: memory@89900000 { 461 cdsp_mem: memory@89900000 {
489 reg = <0x0 0x89900000 462 reg = <0x0 0x89900000 0x0 0x2000000>;
490 no-map; 463 no-map;
491 }; 464 };
492 465
493 ipa_fw_mem: memory@8b900000 { 466 ipa_fw_mem: memory@8b900000 {
494 reg = <0x0 0x8b900000 467 reg = <0x0 0x8b900000 0x0 0x10000>;
495 no-map; 468 no-map;
496 }; 469 };
497 470
498 ipa_gsi_mem: memory@8b910000 { 471 ipa_gsi_mem: memory@8b910000 {
499 reg = <0x0 0x8b910000 472 reg = <0x0 0x8b910000 0x0 0xa000>;
500 no-map; 473 no-map;
501 }; 474 };
502 475
503 gpu_micro_code_mem: memory@8b9 476 gpu_micro_code_mem: memory@8b91a000 {
504 reg = <0x0 0x8b91a000 477 reg = <0x0 0x8b91a000 0x0 0x2000>;
505 no-map; 478 no-map;
506 }; 479 };
507 480
508 spss_region_mem: memory@8ba000 481 spss_region_mem: memory@8ba00000 {
509 reg = <0x0 0x8ba00000 482 reg = <0x0 0x8ba00000 0x0 0x180000>;
510 no-map; 483 no-map;
511 }; 484 };
512 485
513 /* First part of the "SPU secu 486 /* First part of the "SPU secure shared memory" region */
514 spu_tz_shared_mem: memory@8bb8 487 spu_tz_shared_mem: memory@8bb80000 {
515 reg = <0x0 0x8bb80000 488 reg = <0x0 0x8bb80000 0x0 0x60000>;
516 no-map; 489 no-map;
517 }; 490 };
518 491
519 /* Second part of the "SPU sec 492 /* Second part of the "SPU secure shared memory" region */
520 spu_modem_shared_mem: memory@8 493 spu_modem_shared_mem: memory@8bbe0000 {
521 reg = <0x0 0x8bbe0000 494 reg = <0x0 0x8bbe0000 0x0 0x20000>;
522 no-map; 495 no-map;
523 }; 496 };
524 497
525 mpss_mem: memory@8bc00000 { 498 mpss_mem: memory@8bc00000 {
526 reg = <0x0 0x8bc00000 499 reg = <0x0 0x8bc00000 0x0 0x13200000>;
527 no-map; 500 no-map;
528 }; 501 };
529 502
530 cvp_mem: memory@9ee00000 { 503 cvp_mem: memory@9ee00000 {
531 reg = <0x0 0x9ee00000 504 reg = <0x0 0x9ee00000 0x0 0x700000>;
532 no-map; 505 no-map;
533 }; 506 };
534 507
535 camera_mem: memory@9f500000 { <<
536 reg = <0x0 0x9f500000 <<
537 no-map; <<
538 }; <<
539 <<
540 rmtfs_mem: memory@9fd00000 { 508 rmtfs_mem: memory@9fd00000 {
541 compatible = "qcom,rmt 509 compatible = "qcom,rmtfs-mem";
542 reg = <0x0 0x9fd00000 510 reg = <0x0 0x9fd00000 0x0 0x280000>;
543 no-map; 511 no-map;
544 512
545 qcom,client-id = <1>; 513 qcom,client-id = <1>;
546 qcom,vmid = <QCOM_SCM_ !! 514 qcom,vmid = <15>;
547 }; <<
548 <<
549 xbl_sc_mem2: memory@a6e00000 { <<
550 reg = <0x0 0xa6e00000 <<
551 no-map; <<
552 }; 515 };
553 516
554 global_sync_mem: memory@a6f000 517 global_sync_mem: memory@a6f00000 {
555 reg = <0x0 0xa6f00000 518 reg = <0x0 0xa6f00000 0x0 0x100000>;
556 no-map; 519 no-map;
557 }; 520 };
558 521
559 /* uefi region can be reused b 522 /* uefi region can be reused by APPS */
560 523
561 /* Linux kernel image is loade 524 /* Linux kernel image is loaded at 0xa0000000 */
562 525
563 oem_vm_mem: memory@bb000000 { 526 oem_vm_mem: memory@bb000000 {
564 reg = <0x0 0xbb000000 527 reg = <0x0 0xbb000000 0x0 0x5000000>;
565 no-map; 528 no-map;
566 }; 529 };
567 530
568 mte_mem: memory@c0000000 { 531 mte_mem: memory@c0000000 {
569 reg = <0x0 0xc0000000 532 reg = <0x0 0xc0000000 0x0 0x20000000>;
570 no-map; 533 no-map;
571 }; 534 };
572 535
573 qheebsp_reserved_mem: memory@e 536 qheebsp_reserved_mem: memory@e0000000 {
574 reg = <0x0 0xe0000000 537 reg = <0x0 0xe0000000 0x0 0x600000>;
575 no-map; 538 no-map;
576 }; 539 };
577 540
578 cpusys_vm_mem: memory@e0600000 541 cpusys_vm_mem: memory@e0600000 {
579 reg = <0x0 0xe0600000 542 reg = <0x0 0xe0600000 0x0 0x400000>;
580 no-map; 543 no-map;
581 }; 544 };
582 545
583 hyp_reserved_mem: memory@e0a00 546 hyp_reserved_mem: memory@e0a00000 {
584 reg = <0x0 0xe0a00000 547 reg = <0x0 0xe0a00000 0x0 0x100000>;
585 no-map; 548 no-map;
586 }; 549 };
587 550
588 trust_ui_vm_mem: memory@e0b000 551 trust_ui_vm_mem: memory@e0b00000 {
589 reg = <0x0 0xe0b00000 552 reg = <0x0 0xe0b00000 0x0 0x4af3000>;
590 no-map; 553 no-map;
591 }; 554 };
592 555
593 trust_ui_vm_qrtr: memory@e55f3 556 trust_ui_vm_qrtr: memory@e55f3000 {
594 reg = <0x0 0xe55f3000 557 reg = <0x0 0xe55f3000 0x0 0x9000>;
595 no-map; 558 no-map;
596 }; 559 };
597 560
598 trust_ui_vm_vblk0_ring: memory 561 trust_ui_vm_vblk0_ring: memory@e55fc000 {
599 reg = <0x0 0xe55fc000 562 reg = <0x0 0xe55fc000 0x0 0x4000>;
600 no-map; 563 no-map;
601 }; 564 };
602 565
603 trust_ui_vm_swiotlb: memory@e5 566 trust_ui_vm_swiotlb: memory@e5600000 {
604 reg = <0x0 0xe5600000 567 reg = <0x0 0xe5600000 0x0 0x100000>;
605 no-map; 568 no-map;
606 }; 569 };
607 570
608 tz_stat_mem: memory@e8800000 { 571 tz_stat_mem: memory@e8800000 {
609 reg = <0x0 0xe8800000 572 reg = <0x0 0xe8800000 0x0 0x100000>;
610 no-map; 573 no-map;
611 }; 574 };
612 575
613 tags_mem: memory@e8900000 { 576 tags_mem: memory@e8900000 {
614 reg = <0x0 0xe8900000 577 reg = <0x0 0xe8900000 0x0 0x1200000>;
615 no-map; 578 no-map;
616 }; 579 };
617 580
618 qtee_mem: memory@e9b00000 { 581 qtee_mem: memory@e9b00000 {
619 reg = <0x0 0xe9b00000 582 reg = <0x0 0xe9b00000 0x0 0x500000>;
620 no-map; 583 no-map;
621 }; 584 };
622 585
623 trusted_apps_mem: memory@ea000 586 trusted_apps_mem: memory@ea000000 {
624 reg = <0x0 0xea000000 587 reg = <0x0 0xea000000 0x0 0x3900000>;
625 no-map; 588 no-map;
626 }; 589 };
627 590
628 trusted_apps_ext_mem: memory@e 591 trusted_apps_ext_mem: memory@ed900000 {
629 reg = <0x0 0xed900000 592 reg = <0x0 0xed900000 0x0 0x3b00000>;
630 no-map; 593 no-map;
631 }; 594 };
632 }; 595 };
633 596
634 smp2p-adsp { 597 smp2p-adsp {
635 compatible = "qcom,smp2p"; 598 compatible = "qcom,smp2p";
636 qcom,smem = <443>, <429>; 599 qcom,smem = <443>, <429>;
637 interrupts-extended = <&ipcc I 600 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
638 I 601 IPCC_MPROC_SIGNAL_SMP2P
639 I 602 IRQ_TYPE_EDGE_RISING>;
640 mboxes = <&ipcc IPCC_CLIENT_LP 603 mboxes = <&ipcc IPCC_CLIENT_LPASS
641 IPCC_MPROC_SIG 604 IPCC_MPROC_SIGNAL_SMP2P>;
642 605
643 qcom,local-pid = <0>; 606 qcom,local-pid = <0>;
644 qcom,remote-pid = <2>; 607 qcom,remote-pid = <2>;
645 608
646 smp2p_adsp_out: master-kernel 609 smp2p_adsp_out: master-kernel {
647 qcom,entry-name = "mas 610 qcom,entry-name = "master-kernel";
648 #qcom,smem-state-cells 611 #qcom,smem-state-cells = <1>;
649 }; 612 };
650 613
651 smp2p_adsp_in: slave-kernel { 614 smp2p_adsp_in: slave-kernel {
652 qcom,entry-name = "sla 615 qcom,entry-name = "slave-kernel";
653 interrupt-controller; 616 interrupt-controller;
654 #interrupt-cells = <2> 617 #interrupt-cells = <2>;
655 }; 618 };
656 }; 619 };
657 620
658 smp2p-cdsp { 621 smp2p-cdsp {
659 compatible = "qcom,smp2p"; 622 compatible = "qcom,smp2p";
660 qcom,smem = <94>, <432>; 623 qcom,smem = <94>, <432>;
661 interrupts-extended = <&ipcc I 624 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
662 I 625 IPCC_MPROC_SIGNAL_SMP2P
663 I 626 IRQ_TYPE_EDGE_RISING>;
664 mboxes = <&ipcc IPCC_CLIENT_CD 627 mboxes = <&ipcc IPCC_CLIENT_CDSP
665 IPCC_MPROC_SIG 628 IPCC_MPROC_SIGNAL_SMP2P>;
666 629
667 qcom,local-pid = <0>; 630 qcom,local-pid = <0>;
668 qcom,remote-pid = <5>; 631 qcom,remote-pid = <5>;
669 632
670 smp2p_cdsp_out: master-kernel 633 smp2p_cdsp_out: master-kernel {
671 qcom,entry-name = "mas 634 qcom,entry-name = "master-kernel";
672 #qcom,smem-state-cells 635 #qcom,smem-state-cells = <1>;
673 }; 636 };
674 637
675 smp2p_cdsp_in: slave-kernel { 638 smp2p_cdsp_in: slave-kernel {
676 qcom,entry-name = "sla 639 qcom,entry-name = "slave-kernel";
677 interrupt-controller; 640 interrupt-controller;
678 #interrupt-cells = <2> 641 #interrupt-cells = <2>;
679 }; 642 };
680 }; 643 };
681 644
682 smp2p-modem { 645 smp2p-modem {
683 compatible = "qcom,smp2p"; 646 compatible = "qcom,smp2p";
684 qcom,smem = <435>, <428>; 647 qcom,smem = <435>, <428>;
685 interrupts-extended = <&ipcc I 648 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
686 I 649 IPCC_MPROC_SIGNAL_SMP2P
687 I 650 IRQ_TYPE_EDGE_RISING>;
688 mboxes = <&ipcc IPCC_CLIENT_MP 651 mboxes = <&ipcc IPCC_CLIENT_MPSS
689 IPCC_MPROC_SIG 652 IPCC_MPROC_SIGNAL_SMP2P>;
690 653
691 qcom,local-pid = <0>; 654 qcom,local-pid = <0>;
692 qcom,remote-pid = <1>; 655 qcom,remote-pid = <1>;
693 656
694 smp2p_modem_out: master-kernel 657 smp2p_modem_out: master-kernel {
695 qcom,entry-name = "mas 658 qcom,entry-name = "master-kernel";
696 #qcom,smem-state-cells 659 #qcom,smem-state-cells = <1>;
697 }; 660 };
698 661
699 smp2p_modem_in: slave-kernel { 662 smp2p_modem_in: slave-kernel {
700 qcom,entry-name = "sla 663 qcom,entry-name = "slave-kernel";
701 interrupt-controller; 664 interrupt-controller;
702 #interrupt-cells = <2> 665 #interrupt-cells = <2>;
703 }; 666 };
704 667
705 ipa_smp2p_out: ipa-ap-to-modem 668 ipa_smp2p_out: ipa-ap-to-modem {
706 qcom,entry-name = "ipa 669 qcom,entry-name = "ipa";
707 #qcom,smem-state-cells 670 #qcom,smem-state-cells = <1>;
708 }; 671 };
709 672
710 ipa_smp2p_in: ipa-modem-to-ap 673 ipa_smp2p_in: ipa-modem-to-ap {
711 qcom,entry-name = "ipa 674 qcom,entry-name = "ipa";
712 interrupt-controller; 675 interrupt-controller;
713 #interrupt-cells = <2> 676 #interrupt-cells = <2>;
714 }; 677 };
715 }; 678 };
716 679
717 smp2p-slpi { 680 smp2p-slpi {
718 compatible = "qcom,smp2p"; 681 compatible = "qcom,smp2p";
719 qcom,smem = <481>, <430>; 682 qcom,smem = <481>, <430>;
720 interrupts-extended = <&ipcc I 683 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
721 I 684 IPCC_MPROC_SIGNAL_SMP2P
722 I 685 IRQ_TYPE_EDGE_RISING>;
723 mboxes = <&ipcc IPCC_CLIENT_SL 686 mboxes = <&ipcc IPCC_CLIENT_SLPI
724 IPCC_MPROC_SIG 687 IPCC_MPROC_SIGNAL_SMP2P>;
725 688
726 qcom,local-pid = <0>; 689 qcom,local-pid = <0>;
727 qcom,remote-pid = <3>; 690 qcom,remote-pid = <3>;
728 691
729 smp2p_slpi_out: master-kernel 692 smp2p_slpi_out: master-kernel {
730 qcom,entry-name = "mas 693 qcom,entry-name = "master-kernel";
731 #qcom,smem-state-cells 694 #qcom,smem-state-cells = <1>;
732 }; 695 };
733 696
734 smp2p_slpi_in: slave-kernel { 697 smp2p_slpi_in: slave-kernel {
735 qcom,entry-name = "sla 698 qcom,entry-name = "slave-kernel";
736 interrupt-controller; 699 interrupt-controller;
737 #interrupt-cells = <2> 700 #interrupt-cells = <2>;
738 }; 701 };
739 }; 702 };
740 703
741 soc: soc@0 { 704 soc: soc@0 {
742 #address-cells = <2>; 705 #address-cells = <2>;
743 #size-cells = <2>; 706 #size-cells = <2>;
744 ranges = <0 0 0 0 0x10 0>; 707 ranges = <0 0 0 0 0x10 0>;
745 dma-ranges = <0 0 0 0 0x10 0>; 708 dma-ranges = <0 0 0 0 0x10 0>;
746 compatible = "simple-bus"; 709 compatible = "simple-bus";
747 710
748 gcc: clock-controller@100000 { 711 gcc: clock-controller@100000 {
749 compatible = "qcom,gcc 712 compatible = "qcom,gcc-sm8450";
750 reg = <0x0 0x00100000 713 reg = <0x0 0x00100000 0x0 0x1f4200>;
751 #clock-cells = <1>; 714 #clock-cells = <1>;
752 #reset-cells = <1>; 715 #reset-cells = <1>;
753 #power-domain-cells = 716 #power-domain-cells = <1>;
754 clocks = <&rpmhcc RPMH 717 clocks = <&rpmhcc RPMH_CXO_CLK>,
755 <&sleep_clk>, !! 718 <&pcie0_lane>,
756 <&pcie0_phy>, !! 719 <&pcie1_lane>,
757 <&pcie1_phy Q !! 720 <&sleep_clk>;
758 <&pcie1_phy Q <<
759 <&ufs_mem_phy <<
760 <&ufs_mem_phy <<
761 <&ufs_mem_phy <<
762 <&usb_1_qmpph <<
763 clock-names = "bi_tcxo 721 clock-names = "bi_tcxo",
764 "sleep_c <<
765 "pcie_0_ 722 "pcie_0_pipe_clk",
766 "pcie_1_ 723 "pcie_1_pipe_clk",
767 "pcie_1_ !! 724 "sleep_clk";
768 "ufs_phy <<
769 "ufs_phy <<
770 "ufs_phy <<
771 "usb3_ph <<
772 }; 725 };
773 726
774 gpi_dma2: dma-controller@80000 727 gpi_dma2: dma-controller@800000 {
775 compatible = "qcom,sm8 !! 728 compatible = "qcom,sm8450-gpi-dma";
776 #dma-cells = <3>; 729 #dma-cells = <3>;
777 reg = <0 0x00800000 0 !! 730 reg = <0 0x800000 0 0x60000>;
778 interrupts = <GIC_SPI 731 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
779 <GIC_SPI 732 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
780 <GIC_SPI 733 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
781 <GIC_SPI 734 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
782 <GIC_SPI 735 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
783 <GIC_SPI 736 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
784 <GIC_SPI 737 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
785 <GIC_SPI 738 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
786 <GIC_SPI 739 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
787 <GIC_SPI 740 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
788 <GIC_SPI 741 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
789 <GIC_SPI 742 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
790 dma-channels = <12>; 743 dma-channels = <12>;
791 dma-channel-mask = <0x 744 dma-channel-mask = <0x7e>;
792 iommus = <&apps_smmu 0 745 iommus = <&apps_smmu 0x496 0x0>;
793 status = "disabled"; 746 status = "disabled";
794 }; 747 };
795 748
796 qupv3_id_2: geniqup@8c0000 { 749 qupv3_id_2: geniqup@8c0000 {
797 compatible = "qcom,gen 750 compatible = "qcom,geni-se-qup";
798 reg = <0x0 0x008c0000 751 reg = <0x0 0x008c0000 0x0 0x2000>;
799 clock-names = "m-ahb", 752 clock-names = "m-ahb", "s-ahb";
800 clocks = <&gcc GCC_QUP 753 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
801 <&gcc GCC_QUP 754 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
802 iommus = <&apps_smmu 0 755 iommus = <&apps_smmu 0x483 0x0>;
803 #address-cells = <2>; 756 #address-cells = <2>;
804 #size-cells = <2>; 757 #size-cells = <2>;
805 ranges; 758 ranges;
806 status = "disabled"; 759 status = "disabled";
807 760
808 i2c15: i2c@880000 { 761 i2c15: i2c@880000 {
809 compatible = " 762 compatible = "qcom,geni-i2c";
810 reg = <0x0 0x0 763 reg = <0x0 0x00880000 0x0 0x4000>;
811 clock-names = 764 clock-names = "se";
812 clocks = <&gcc 765 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
813 pinctrl-names 766 pinctrl-names = "default";
814 pinctrl-0 = <& 767 pinctrl-0 = <&qup_i2c15_data_clk>;
815 interrupts = < 768 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
816 #address-cells 769 #address-cells = <1>;
817 #size-cells = 770 #size-cells = <0>;
818 interconnects 771 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
819 772 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
820 773 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
821 interconnect-n 774 interconnect-names = "qup-core", "qup-config", "qup-memory";
822 dmas = <&gpi_d 775 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
823 <&gpi_d 776 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
824 dma-names = "t 777 dma-names = "tx", "rx";
825 status = "disa 778 status = "disabled";
826 }; 779 };
827 780
828 spi15: spi@880000 { 781 spi15: spi@880000 {
829 compatible = " 782 compatible = "qcom,geni-spi";
830 reg = <0x0 0x0 783 reg = <0x0 0x00880000 0x0 0x4000>;
831 clock-names = 784 clock-names = "se";
832 clocks = <&gcc 785 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
833 interrupts = < 786 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
834 pinctrl-names 787 pinctrl-names = "default";
835 pinctrl-0 = <& 788 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
>> 789 spi-max-frequency = <50000000>;
836 interconnects 790 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
837 791 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
838 interconnect-n 792 interconnect-names = "qup-core", "qup-config";
839 dmas = <&gpi_d 793 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
840 <&gpi_d 794 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
841 dma-names = "t 795 dma-names = "tx", "rx";
842 #address-cells 796 #address-cells = <1>;
843 #size-cells = 797 #size-cells = <0>;
844 status = "disa 798 status = "disabled";
845 }; 799 };
846 800
847 i2c16: i2c@884000 { 801 i2c16: i2c@884000 {
848 compatible = " 802 compatible = "qcom,geni-i2c";
849 reg = <0x0 0x0 803 reg = <0x0 0x00884000 0x0 0x4000>;
850 clock-names = 804 clock-names = "se";
851 clocks = <&gcc 805 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
852 pinctrl-names 806 pinctrl-names = "default";
853 pinctrl-0 = <& 807 pinctrl-0 = <&qup_i2c16_data_clk>;
854 interrupts = < 808 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
855 #address-cells 809 #address-cells = <1>;
856 #size-cells = 810 #size-cells = <0>;
857 interconnects 811 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
858 812 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
859 813 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
860 interconnect-n 814 interconnect-names = "qup-core", "qup-config", "qup-memory";
861 dmas = <&gpi_d 815 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
862 <&gpi_d 816 <&gpi_dma2 1 1 QCOM_GPI_I2C>;
863 dma-names = "t 817 dma-names = "tx", "rx";
864 status = "disa 818 status = "disabled";
865 }; 819 };
866 820
867 spi16: spi@884000 { 821 spi16: spi@884000 {
868 compatible = " 822 compatible = "qcom,geni-spi";
869 reg = <0x0 0x0 823 reg = <0x0 0x00884000 0x0 0x4000>;
870 clock-names = 824 clock-names = "se";
871 clocks = <&gcc 825 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
872 interrupts = < 826 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
873 pinctrl-names 827 pinctrl-names = "default";
874 pinctrl-0 = <& 828 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>;
>> 829 spi-max-frequency = <50000000>;
875 interconnects 830 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
876 831 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
877 interconnect-n 832 interconnect-names = "qup-core", "qup-config";
878 dmas = <&gpi_d 833 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
879 <&gpi_d 834 <&gpi_dma2 1 1 QCOM_GPI_SPI>;
880 dma-names = "t 835 dma-names = "tx", "rx";
881 #address-cells 836 #address-cells = <1>;
882 #size-cells = 837 #size-cells = <0>;
883 status = "disa 838 status = "disabled";
884 }; 839 };
885 840
886 i2c17: i2c@888000 { 841 i2c17: i2c@888000 {
887 compatible = " 842 compatible = "qcom,geni-i2c";
888 reg = <0x0 0x0 843 reg = <0x0 0x00888000 0x0 0x4000>;
889 clock-names = 844 clock-names = "se";
890 clocks = <&gcc 845 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
891 pinctrl-names 846 pinctrl-names = "default";
892 pinctrl-0 = <& 847 pinctrl-0 = <&qup_i2c17_data_clk>;
893 interrupts = < 848 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
894 #address-cells 849 #address-cells = <1>;
895 #size-cells = 850 #size-cells = <0>;
896 interconnects 851 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
897 852 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
898 853 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
899 interconnect-n 854 interconnect-names = "qup-core", "qup-config", "qup-memory";
900 dmas = <&gpi_d 855 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
901 <&gpi_d 856 <&gpi_dma2 1 2 QCOM_GPI_I2C>;
902 dma-names = "t 857 dma-names = "tx", "rx";
903 status = "disa 858 status = "disabled";
904 }; 859 };
905 860
906 spi17: spi@888000 { 861 spi17: spi@888000 {
907 compatible = " 862 compatible = "qcom,geni-spi";
908 reg = <0x0 0x0 863 reg = <0x0 0x00888000 0x0 0x4000>;
909 clock-names = 864 clock-names = "se";
910 clocks = <&gcc 865 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
911 interrupts = < 866 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
912 pinctrl-names 867 pinctrl-names = "default";
913 pinctrl-0 = <& 868 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>;
>> 869 spi-max-frequency = <50000000>;
914 interconnects 870 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
915 871 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
916 interconnect-n 872 interconnect-names = "qup-core", "qup-config";
917 dmas = <&gpi_d 873 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
918 <&gpi_d 874 <&gpi_dma2 1 2 QCOM_GPI_SPI>;
919 dma-names = "t 875 dma-names = "tx", "rx";
920 #address-cells 876 #address-cells = <1>;
921 #size-cells = 877 #size-cells = <0>;
922 status = "disa 878 status = "disabled";
923 }; 879 };
924 880
925 i2c18: i2c@88c000 { 881 i2c18: i2c@88c000 {
926 compatible = " 882 compatible = "qcom,geni-i2c";
927 reg = <0x0 0x0 883 reg = <0x0 0x0088c000 0x0 0x4000>;
928 clock-names = 884 clock-names = "se";
929 clocks = <&gcc 885 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
930 pinctrl-names 886 pinctrl-names = "default";
931 pinctrl-0 = <& 887 pinctrl-0 = <&qup_i2c18_data_clk>;
932 interrupts = < 888 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
933 #address-cells 889 #address-cells = <1>;
934 #size-cells = 890 #size-cells = <0>;
935 interconnects 891 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
936 892 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
937 893 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
938 interconnect-n 894 interconnect-names = "qup-core", "qup-config", "qup-memory";
939 dmas = <&gpi_d 895 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
940 <&gpi_d 896 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
941 dma-names = "t 897 dma-names = "tx", "rx";
942 status = "disa 898 status = "disabled";
943 }; 899 };
944 900
945 spi18: spi@88c000 { 901 spi18: spi@88c000 {
946 compatible = " 902 compatible = "qcom,geni-spi";
947 reg = <0 0x008 903 reg = <0 0x0088c000 0 0x4000>;
948 clock-names = 904 clock-names = "se";
949 clocks = <&gcc 905 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
950 interrupts = < 906 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
951 pinctrl-names 907 pinctrl-names = "default";
952 pinctrl-0 = <& 908 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>;
>> 909 spi-max-frequency = <50000000>;
953 interconnects 910 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
954 911 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
955 interconnect-n 912 interconnect-names = "qup-core", "qup-config";
956 dmas = <&gpi_d 913 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
957 <&gpi_d 914 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
958 dma-names = "t 915 dma-names = "tx", "rx";
959 #address-cells 916 #address-cells = <1>;
960 #size-cells = 917 #size-cells = <0>;
961 status = "disa 918 status = "disabled";
962 }; 919 };
963 920
964 i2c19: i2c@890000 { 921 i2c19: i2c@890000 {
965 compatible = " 922 compatible = "qcom,geni-i2c";
966 reg = <0x0 0x0 923 reg = <0x0 0x00890000 0x0 0x4000>;
967 clock-names = 924 clock-names = "se";
968 clocks = <&gcc 925 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
969 pinctrl-names 926 pinctrl-names = "default";
970 pinctrl-0 = <& 927 pinctrl-0 = <&qup_i2c19_data_clk>;
971 interrupts = < 928 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
972 #address-cells 929 #address-cells = <1>;
973 #size-cells = 930 #size-cells = <0>;
974 interconnects 931 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
975 932 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
976 933 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
977 interconnect-n 934 interconnect-names = "qup-core", "qup-config", "qup-memory";
978 dmas = <&gpi_d 935 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
979 <&gpi_d 936 <&gpi_dma2 1 4 QCOM_GPI_I2C>;
980 dma-names = "t 937 dma-names = "tx", "rx";
981 status = "disa 938 status = "disabled";
982 }; 939 };
983 940
984 spi19: spi@890000 { 941 spi19: spi@890000 {
985 compatible = " 942 compatible = "qcom,geni-spi";
986 reg = <0 0x008 943 reg = <0 0x00890000 0 0x4000>;
987 clock-names = 944 clock-names = "se";
988 clocks = <&gcc 945 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
989 interrupts = < 946 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
990 pinctrl-names 947 pinctrl-names = "default";
991 pinctrl-0 = <& 948 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>;
>> 949 spi-max-frequency = <50000000>;
992 interconnects 950 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
993 951 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
994 interconnect-n 952 interconnect-names = "qup-core", "qup-config";
995 dmas = <&gpi_d 953 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
996 <&gpi_d 954 <&gpi_dma2 1 4 QCOM_GPI_I2C>;
997 dma-names = "t 955 dma-names = "tx", "rx";
998 #address-cells 956 #address-cells = <1>;
999 #size-cells = 957 #size-cells = <0>;
1000 status = "dis 958 status = "disabled";
1001 }; 959 };
1002 960
1003 i2c20: i2c@894000 { 961 i2c20: i2c@894000 {
1004 compatible = 962 compatible = "qcom,geni-i2c";
1005 reg = <0x0 0x 963 reg = <0x0 0x00894000 0x0 0x4000>;
1006 clock-names = 964 clock-names = "se";
1007 clocks = <&gc 965 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1008 pinctrl-names 966 pinctrl-names = "default";
1009 pinctrl-0 = < 967 pinctrl-0 = <&qup_i2c20_data_clk>;
1010 interrupts = 968 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1011 #address-cell 969 #address-cells = <1>;
1012 #size-cells = 970 #size-cells = <0>;
1013 interconnects 971 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1014 972 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1015 973 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1016 interconnect- 974 interconnect-names = "qup-core", "qup-config", "qup-memory";
1017 dmas = <&gpi_ 975 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1018 <&gpi_ 976 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1019 dma-names = " 977 dma-names = "tx", "rx";
1020 status = "dis 978 status = "disabled";
1021 }; 979 };
1022 980
1023 uart20: serial@894000 981 uart20: serial@894000 {
1024 compatible = 982 compatible = "qcom,geni-uart";
1025 reg = <0 0x00 983 reg = <0 0x00894000 0 0x4000>;
1026 clock-names = 984 clock-names = "se";
1027 clocks = <&gc 985 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1028 pinctrl-names 986 pinctrl-names = "default";
1029 pinctrl-0 = < 987 pinctrl-0 = <&qup_uart20_default>;
1030 interrupts = 988 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1031 interconnects !! 989 #address-cells = <1>;
1032 !! 990 #size-cells = <0>;
1033 <<
1034 <<
1035 interconnect- <<
1036 <<
1037 status = "dis 991 status = "disabled";
1038 }; 992 };
1039 993
1040 spi20: spi@894000 { 994 spi20: spi@894000 {
1041 compatible = 995 compatible = "qcom,geni-spi";
1042 reg = <0 0x00 996 reg = <0 0x00894000 0 0x4000>;
1043 clock-names = 997 clock-names = "se";
1044 clocks = <&gc 998 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1045 interrupts = 999 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1046 pinctrl-names 1000 pinctrl-names = "default";
1047 pinctrl-0 = < 1001 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>;
>> 1002 spi-max-frequency = <50000000>;
1048 interconnects 1003 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1049 1004 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
1050 interconnect- 1005 interconnect-names = "qup-core", "qup-config";
1051 dmas = <&gpi_ 1006 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1052 <&gpi_ 1007 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1053 dma-names = " 1008 dma-names = "tx", "rx";
1054 #address-cell 1009 #address-cells = <1>;
1055 #size-cells = 1010 #size-cells = <0>;
1056 status = "dis 1011 status = "disabled";
1057 }; 1012 };
1058 1013
1059 i2c21: i2c@898000 { 1014 i2c21: i2c@898000 {
1060 compatible = 1015 compatible = "qcom,geni-i2c";
1061 reg = <0x0 0x 1016 reg = <0x0 0x00898000 0x0 0x4000>;
1062 clock-names = 1017 clock-names = "se";
1063 clocks = <&gc 1018 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1064 pinctrl-names 1019 pinctrl-names = "default";
1065 pinctrl-0 = < 1020 pinctrl-0 = <&qup_i2c21_data_clk>;
1066 interrupts = 1021 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
1067 #address-cell 1022 #address-cells = <1>;
1068 #size-cells = 1023 #size-cells = <0>;
1069 interconnects 1024 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1070 1025 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1071 1026 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1072 interconnect- 1027 interconnect-names = "qup-core", "qup-config", "qup-memory";
1073 dmas = <&gpi_ 1028 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>,
1074 <&gpi_ 1029 <&gpi_dma2 1 6 QCOM_GPI_I2C>;
1075 dma-names = " 1030 dma-names = "tx", "rx";
1076 status = "dis 1031 status = "disabled";
1077 }; 1032 };
1078 1033
1079 spi21: spi@898000 { 1034 spi21: spi@898000 {
1080 compatible = 1035 compatible = "qcom,geni-spi";
1081 reg = <0 0x00 1036 reg = <0 0x00898000 0 0x4000>;
1082 clock-names = 1037 clock-names = "se";
1083 clocks = <&gc 1038 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1084 interrupts = 1039 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
1085 pinctrl-names 1040 pinctrl-names = "default";
1086 pinctrl-0 = < 1041 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>;
>> 1042 spi-max-frequency = <50000000>;
1087 interconnects 1043 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1088 1044 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
1089 interconnect- 1045 interconnect-names = "qup-core", "qup-config";
1090 dmas = <&gpi_ 1046 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>,
1091 <&gpi_ 1047 <&gpi_dma2 1 6 QCOM_GPI_SPI>;
1092 dma-names = " 1048 dma-names = "tx", "rx";
1093 #address-cell 1049 #address-cells = <1>;
1094 #size-cells = 1050 #size-cells = <0>;
1095 status = "dis 1051 status = "disabled";
1096 }; 1052 };
1097 }; 1053 };
1098 1054
1099 gpi_dma0: dma-controller@9000 1055 gpi_dma0: dma-controller@900000 {
1100 compatible = "qcom,sm !! 1056 compatible = "qcom,sm8450-gpi-dma";
1101 #dma-cells = <3>; 1057 #dma-cells = <3>;
1102 reg = <0 0x00900000 0 !! 1058 reg = <0 0x900000 0 0x60000>;
1103 interrupts = <GIC_SPI 1059 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
1104 <GIC_SPI 1060 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
1105 <GIC_SPI 1061 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
1106 <GIC_SPI 1062 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
1107 <GIC_SPI 1063 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
1108 <GIC_SPI 1064 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
1109 <GIC_SPI 1065 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
1110 <GIC_SPI 1066 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
1111 <GIC_SPI 1067 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
1112 <GIC_SPI 1068 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
1113 <GIC_SPI 1069 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
1114 <GIC_SPI 1070 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
1115 dma-channels = <12>; 1071 dma-channels = <12>;
1116 dma-channel-mask = <0 1072 dma-channel-mask = <0x7e>;
1117 iommus = <&apps_smmu 1073 iommus = <&apps_smmu 0x5b6 0x0>;
1118 status = "disabled"; 1074 status = "disabled";
1119 }; 1075 };
1120 1076
1121 qupv3_id_0: geniqup@9c0000 { 1077 qupv3_id_0: geniqup@9c0000 {
1122 compatible = "qcom,ge 1078 compatible = "qcom,geni-se-qup";
1123 reg = <0x0 0x009c0000 1079 reg = <0x0 0x009c0000 0x0 0x2000>;
1124 clock-names = "m-ahb" 1080 clock-names = "m-ahb", "s-ahb";
1125 clocks = <&gcc GCC_QU 1081 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1126 <&gcc GCC_QU 1082 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1127 iommus = <&apps_smmu 1083 iommus = <&apps_smmu 0x5a3 0x0>;
1128 interconnects = <&clk 1084 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>;
1129 interconnect-names = 1085 interconnect-names = "qup-core";
1130 #address-cells = <2>; 1086 #address-cells = <2>;
1131 #size-cells = <2>; 1087 #size-cells = <2>;
1132 ranges; 1088 ranges;
1133 status = "disabled"; 1089 status = "disabled";
1134 1090
1135 i2c0: i2c@980000 { 1091 i2c0: i2c@980000 {
1136 compatible = 1092 compatible = "qcom,geni-i2c";
1137 reg = <0x0 0x 1093 reg = <0x0 0x00980000 0x0 0x4000>;
1138 clock-names = 1094 clock-names = "se";
1139 clocks = <&gc 1095 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1140 pinctrl-names 1096 pinctrl-names = "default";
1141 pinctrl-0 = < 1097 pinctrl-0 = <&qup_i2c0_data_clk>;
1142 interrupts = 1098 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1143 #address-cell 1099 #address-cells = <1>;
1144 #size-cells = 1100 #size-cells = <0>;
1145 interconnects 1101 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1146 1102 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1147 1103 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1148 interconnect- 1104 interconnect-names = "qup-core", "qup-config", "qup-memory";
1149 dmas = <&gpi_ 1105 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1150 <&gpi_ 1106 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1151 dma-names = " 1107 dma-names = "tx", "rx";
1152 status = "dis 1108 status = "disabled";
1153 }; 1109 };
1154 1110
1155 spi0: spi@980000 { 1111 spi0: spi@980000 {
1156 compatible = 1112 compatible = "qcom,geni-spi";
1157 reg = <0x0 0x 1113 reg = <0x0 0x00980000 0x0 0x4000>;
1158 clock-names = 1114 clock-names = "se";
1159 clocks = <&gc 1115 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1160 interrupts = 1116 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1161 pinctrl-names 1117 pinctrl-names = "default";
1162 pinctrl-0 = < 1118 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1163 power-domains !! 1119 power-domains = <&rpmhpd SM8450_CX>;
1164 operating-poi 1120 operating-points-v2 = <&qup_opp_table_100mhz>;
1165 interconnects 1121 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1166 1122 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1167 1123 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1168 interconnect- 1124 interconnect-names = "qup-core", "qup-config", "qup-memory";
1169 dmas = <&gpi_ 1125 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1170 <&gpi_ 1126 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1171 dma-names = " 1127 dma-names = "tx", "rx";
1172 #address-cell 1128 #address-cells = <1>;
1173 #size-cells = 1129 #size-cells = <0>;
1174 status = "dis 1130 status = "disabled";
1175 }; 1131 };
1176 1132
1177 i2c1: i2c@984000 { 1133 i2c1: i2c@984000 {
1178 compatible = 1134 compatible = "qcom,geni-i2c";
1179 reg = <0x0 0x 1135 reg = <0x0 0x00984000 0x0 0x4000>;
1180 clock-names = 1136 clock-names = "se";
1181 clocks = <&gc 1137 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1182 pinctrl-names 1138 pinctrl-names = "default";
1183 pinctrl-0 = < 1139 pinctrl-0 = <&qup_i2c1_data_clk>;
1184 interrupts = 1140 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1185 #address-cell 1141 #address-cells = <1>;
1186 #size-cells = 1142 #size-cells = <0>;
1187 interconnects 1143 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1188 1144 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1189 1145 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1190 interconnect- 1146 interconnect-names = "qup-core", "qup-config", "qup-memory";
1191 dmas = <&gpi_ 1147 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1192 <&gpi_ 1148 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1193 dma-names = " 1149 dma-names = "tx", "rx";
1194 status = "dis 1150 status = "disabled";
1195 }; 1151 };
1196 1152
1197 spi1: spi@984000 { 1153 spi1: spi@984000 {
1198 compatible = 1154 compatible = "qcom,geni-spi";
1199 reg = <0x0 0x 1155 reg = <0x0 0x00984000 0x0 0x4000>;
1200 clock-names = 1156 clock-names = "se";
1201 clocks = <&gc 1157 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1202 interrupts = 1158 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1203 pinctrl-names 1159 pinctrl-names = "default";
1204 pinctrl-0 = < 1160 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1205 interconnects 1161 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1206 1162 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1207 1163 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1208 interconnect- 1164 interconnect-names = "qup-core", "qup-config", "qup-memory";
1209 dmas = <&gpi_ 1165 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1210 <&gpi_ 1166 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1211 dma-names = " 1167 dma-names = "tx", "rx";
1212 #address-cell 1168 #address-cells = <1>;
1213 #size-cells = 1169 #size-cells = <0>;
1214 status = "dis 1170 status = "disabled";
1215 }; 1171 };
1216 1172
1217 i2c2: i2c@988000 { 1173 i2c2: i2c@988000 {
1218 compatible = 1174 compatible = "qcom,geni-i2c";
1219 reg = <0x0 0x 1175 reg = <0x0 0x00988000 0x0 0x4000>;
1220 clock-names = 1176 clock-names = "se";
1221 clocks = <&gc 1177 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1222 pinctrl-names 1178 pinctrl-names = "default";
1223 pinctrl-0 = < 1179 pinctrl-0 = <&qup_i2c2_data_clk>;
1224 interrupts = 1180 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1225 #address-cell 1181 #address-cells = <1>;
1226 #size-cells = 1182 #size-cells = <0>;
1227 interconnects 1183 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1228 1184 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1229 1185 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1230 interconnect- 1186 interconnect-names = "qup-core", "qup-config", "qup-memory";
1231 dmas = <&gpi_ 1187 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1232 <&gpi_ 1188 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1233 dma-names = " 1189 dma-names = "tx", "rx";
1234 status = "dis 1190 status = "disabled";
1235 }; 1191 };
1236 1192
1237 spi2: spi@988000 { 1193 spi2: spi@988000 {
1238 compatible = 1194 compatible = "qcom,geni-spi";
1239 reg = <0x0 0x 1195 reg = <0x0 0x00988000 0x0 0x4000>;
1240 clock-names = 1196 clock-names = "se";
1241 clocks = <&gc 1197 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1242 interrupts = 1198 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1243 pinctrl-names 1199 pinctrl-names = "default";
1244 pinctrl-0 = < 1200 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1245 interconnects 1201 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1246 1202 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1247 1203 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1248 interconnect- 1204 interconnect-names = "qup-core", "qup-config", "qup-memory";
1249 dmas = <&gpi_ 1205 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1250 <&gpi_ 1206 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1251 dma-names = " 1207 dma-names = "tx", "rx";
1252 #address-cell 1208 #address-cells = <1>;
1253 #size-cells = 1209 #size-cells = <0>;
1254 status = "dis 1210 status = "disabled";
1255 }; 1211 };
1256 1212
1257 1213
1258 i2c3: i2c@98c000 { 1214 i2c3: i2c@98c000 {
1259 compatible = 1215 compatible = "qcom,geni-i2c";
1260 reg = <0x0 0x 1216 reg = <0x0 0x0098c000 0x0 0x4000>;
1261 clock-names = 1217 clock-names = "se";
1262 clocks = <&gc 1218 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1263 pinctrl-names 1219 pinctrl-names = "default";
1264 pinctrl-0 = < 1220 pinctrl-0 = <&qup_i2c3_data_clk>;
1265 interrupts = 1221 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1266 #address-cell 1222 #address-cells = <1>;
1267 #size-cells = 1223 #size-cells = <0>;
1268 interconnects 1224 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1269 1225 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1270 1226 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1271 interconnect- 1227 interconnect-names = "qup-core", "qup-config", "qup-memory";
1272 dmas = <&gpi_ 1228 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1273 <&gpi_ 1229 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1274 dma-names = " 1230 dma-names = "tx", "rx";
1275 status = "dis 1231 status = "disabled";
1276 }; 1232 };
1277 1233
1278 spi3: spi@98c000 { 1234 spi3: spi@98c000 {
1279 compatible = 1235 compatible = "qcom,geni-spi";
1280 reg = <0x0 0x 1236 reg = <0x0 0x0098c000 0x0 0x4000>;
1281 clock-names = 1237 clock-names = "se";
1282 clocks = <&gc 1238 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1283 interrupts = 1239 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1284 pinctrl-names 1240 pinctrl-names = "default";
1285 pinctrl-0 = < 1241 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1286 interconnects 1242 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1287 1243 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1288 1244 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1289 interconnect- 1245 interconnect-names = "qup-core", "qup-config", "qup-memory";
1290 dmas = <&gpi_ 1246 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1291 <&gpi_ 1247 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1292 dma-names = " 1248 dma-names = "tx", "rx";
1293 #address-cell 1249 #address-cells = <1>;
1294 #size-cells = 1250 #size-cells = <0>;
1295 status = "dis 1251 status = "disabled";
1296 }; 1252 };
1297 1253
1298 i2c4: i2c@990000 { 1254 i2c4: i2c@990000 {
1299 compatible = 1255 compatible = "qcom,geni-i2c";
1300 reg = <0x0 0x 1256 reg = <0x0 0x00990000 0x0 0x4000>;
1301 clock-names = 1257 clock-names = "se";
1302 clocks = <&gc 1258 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1303 pinctrl-names 1259 pinctrl-names = "default";
1304 pinctrl-0 = < 1260 pinctrl-0 = <&qup_i2c4_data_clk>;
1305 interrupts = 1261 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1306 #address-cell 1262 #address-cells = <1>;
1307 #size-cells = 1263 #size-cells = <0>;
1308 interconnects 1264 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1309 1265 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1310 1266 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1311 interconnect- 1267 interconnect-names = "qup-core", "qup-config", "qup-memory";
1312 dmas = <&gpi_ 1268 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1313 <&gpi_ 1269 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1314 dma-names = " 1270 dma-names = "tx", "rx";
1315 status = "dis 1271 status = "disabled";
1316 }; 1272 };
1317 1273
1318 spi4: spi@990000 { 1274 spi4: spi@990000 {
1319 compatible = 1275 compatible = "qcom,geni-spi";
1320 reg = <0x0 0x 1276 reg = <0x0 0x00990000 0x0 0x4000>;
1321 clock-names = 1277 clock-names = "se";
1322 clocks = <&gc 1278 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1323 interrupts = 1279 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1324 pinctrl-names 1280 pinctrl-names = "default";
1325 pinctrl-0 = < 1281 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1326 power-domains !! 1282 power-domains = <&rpmhpd SM8450_CX>;
1327 operating-poi 1283 operating-points-v2 = <&qup_opp_table_100mhz>;
1328 interconnects 1284 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1329 1285 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1330 1286 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1331 interconnect- 1287 interconnect-names = "qup-core", "qup-config", "qup-memory";
1332 dmas = <&gpi_ 1288 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1333 <&gpi_ 1289 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1334 dma-names = " 1290 dma-names = "tx", "rx";
1335 #address-cell 1291 #address-cells = <1>;
1336 #size-cells = 1292 #size-cells = <0>;
1337 status = "dis 1293 status = "disabled";
1338 }; 1294 };
1339 1295
1340 i2c5: i2c@994000 { 1296 i2c5: i2c@994000 {
1341 compatible = 1297 compatible = "qcom,geni-i2c";
1342 reg = <0x0 0x 1298 reg = <0x0 0x00994000 0x0 0x4000>;
1343 clock-names = 1299 clock-names = "se";
1344 clocks = <&gc 1300 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1345 pinctrl-names 1301 pinctrl-names = "default";
1346 pinctrl-0 = < 1302 pinctrl-0 = <&qup_i2c5_data_clk>;
1347 interrupts = 1303 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1348 #address-cell 1304 #address-cells = <1>;
1349 #size-cells = 1305 #size-cells = <0>;
1350 interconnects 1306 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1351 1307 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1352 1308 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1353 interconnect- 1309 interconnect-names = "qup-core", "qup-config", "qup-memory";
1354 dmas = <&gpi_ 1310 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1355 <&gpi_ 1311 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1356 dma-names = " 1312 dma-names = "tx", "rx";
1357 status = "dis 1313 status = "disabled";
1358 }; 1314 };
1359 1315
1360 spi5: spi@994000 { 1316 spi5: spi@994000 {
1361 compatible = 1317 compatible = "qcom,geni-spi";
1362 reg = <0x0 0x 1318 reg = <0x0 0x00994000 0x0 0x4000>;
1363 clock-names = 1319 clock-names = "se";
1364 clocks = <&gc 1320 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1365 interrupts = 1321 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1366 pinctrl-names 1322 pinctrl-names = "default";
1367 pinctrl-0 = < 1323 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1368 interconnects 1324 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1369 1325 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1370 1326 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1371 interconnect- 1327 interconnect-names = "qup-core", "qup-config", "qup-memory";
1372 dmas = <&gpi_ 1328 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1373 <&gpi_ 1329 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1374 dma-names = " 1330 dma-names = "tx", "rx";
1375 #address-cell 1331 #address-cells = <1>;
1376 #size-cells = 1332 #size-cells = <0>;
1377 status = "dis 1333 status = "disabled";
1378 }; 1334 };
1379 1335
1380 1336
1381 i2c6: i2c@998000 { 1337 i2c6: i2c@998000 {
1382 compatible = 1338 compatible = "qcom,geni-i2c";
1383 reg = <0x0 0x !! 1339 reg = <0x0 0x998000 0x0 0x4000>;
1384 clock-names = 1340 clock-names = "se";
1385 clocks = <&gc 1341 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1386 pinctrl-names 1342 pinctrl-names = "default";
1387 pinctrl-0 = < 1343 pinctrl-0 = <&qup_i2c6_data_clk>;
1388 interrupts = 1344 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1389 #address-cell 1345 #address-cells = <1>;
1390 #size-cells = 1346 #size-cells = <0>;
1391 interconnects 1347 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1392 1348 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1393 1349 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1394 interconnect- 1350 interconnect-names = "qup-core", "qup-config", "qup-memory";
1395 dmas = <&gpi_ 1351 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1396 <&gpi_ 1352 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1397 dma-names = " 1353 dma-names = "tx", "rx";
1398 status = "dis 1354 status = "disabled";
1399 }; 1355 };
1400 1356
1401 spi6: spi@998000 { 1357 spi6: spi@998000 {
1402 compatible = 1358 compatible = "qcom,geni-spi";
1403 reg = <0x0 0x !! 1359 reg = <0x0 0x998000 0x0 0x4000>;
1404 clock-names = 1360 clock-names = "se";
1405 clocks = <&gc 1361 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1406 interrupts = 1362 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1407 pinctrl-names 1363 pinctrl-names = "default";
1408 pinctrl-0 = < 1364 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1409 interconnects 1365 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1410 1366 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1411 1367 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1412 interconnect- 1368 interconnect-names = "qup-core", "qup-config", "qup-memory";
1413 dmas = <&gpi_ 1369 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1414 <&gpi_ 1370 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1415 dma-names = " 1371 dma-names = "tx", "rx";
1416 #address-cell 1372 #address-cells = <1>;
1417 #size-cells = 1373 #size-cells = <0>;
1418 status = "dis 1374 status = "disabled";
1419 }; 1375 };
1420 1376
1421 uart7: serial@99c000 1377 uart7: serial@99c000 {
1422 compatible = 1378 compatible = "qcom,geni-debug-uart";
1423 reg = <0 0x00 1379 reg = <0 0x0099c000 0 0x4000>;
1424 clock-names = 1380 clock-names = "se";
1425 clocks = <&gc 1381 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1426 pinctrl-names 1382 pinctrl-names = "default";
1427 pinctrl-0 = < 1383 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>;
1428 interrupts = 1384 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1429 interconnects !! 1385 #address-cells = <1>;
1430 !! 1386 #size-cells = <0>;
1431 <<
1432 <<
1433 interconnect- <<
1434 <<
1435 status = "dis 1387 status = "disabled";
1436 }; 1388 };
1437 }; 1389 };
1438 1390
1439 gpi_dma1: dma-controller@a000 1391 gpi_dma1: dma-controller@a00000 {
1440 compatible = "qcom,sm !! 1392 compatible = "qcom,sm8450-gpi-dma";
1441 #dma-cells = <3>; 1393 #dma-cells = <3>;
1442 reg = <0 0x00a00000 0 !! 1394 reg = <0 0xa00000 0 0x60000>;
1443 interrupts = <GIC_SPI 1395 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1444 <GIC_SPI 1396 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1445 <GIC_SPI 1397 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1446 <GIC_SPI 1398 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1447 <GIC_SPI 1399 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1448 <GIC_SPI 1400 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1449 <GIC_SPI 1401 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1450 <GIC_SPI 1402 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1451 <GIC_SPI 1403 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1452 <GIC_SPI 1404 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1453 <GIC_SPI 1405 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1454 <GIC_SPI 1406 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
1455 dma-channels = <12>; 1407 dma-channels = <12>;
1456 dma-channel-mask = <0 1408 dma-channel-mask = <0x7e>;
1457 iommus = <&apps_smmu 1409 iommus = <&apps_smmu 0x56 0x0>;
1458 status = "disabled"; 1410 status = "disabled";
1459 }; 1411 };
1460 1412
1461 qupv3_id_1: geniqup@ac0000 { 1413 qupv3_id_1: geniqup@ac0000 {
1462 compatible = "qcom,ge 1414 compatible = "qcom,geni-se-qup";
1463 reg = <0x0 0x00ac0000 1415 reg = <0x0 0x00ac0000 0x0 0x6000>;
1464 clock-names = "m-ahb" 1416 clock-names = "m-ahb", "s-ahb";
1465 clocks = <&gcc GCC_QU 1417 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1466 <&gcc GCC_QU 1418 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1467 iommus = <&apps_smmu 1419 iommus = <&apps_smmu 0x43 0x0>;
1468 interconnects = <&clk 1420 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>;
1469 interconnect-names = 1421 interconnect-names = "qup-core";
1470 #address-cells = <2>; 1422 #address-cells = <2>;
1471 #size-cells = <2>; 1423 #size-cells = <2>;
1472 ranges; 1424 ranges;
1473 status = "disabled"; 1425 status = "disabled";
1474 1426
1475 i2c8: i2c@a80000 { 1427 i2c8: i2c@a80000 {
1476 compatible = 1428 compatible = "qcom,geni-i2c";
1477 reg = <0x0 0x 1429 reg = <0x0 0x00a80000 0x0 0x4000>;
1478 clock-names = 1430 clock-names = "se";
1479 clocks = <&gc 1431 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1480 pinctrl-names 1432 pinctrl-names = "default";
1481 pinctrl-0 = < 1433 pinctrl-0 = <&qup_i2c8_data_clk>;
1482 interrupts = 1434 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1483 #address-cell 1435 #address-cells = <1>;
1484 #size-cells = 1436 #size-cells = <0>;
1485 interconnects 1437 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1486 1438 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1487 1439 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1488 interconnect- 1440 interconnect-names = "qup-core", "qup-config", "qup-memory";
1489 dmas = <&gpi_ 1441 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1490 <&gpi_ 1442 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1491 dma-names = " 1443 dma-names = "tx", "rx";
1492 status = "dis 1444 status = "disabled";
1493 }; 1445 };
1494 1446
1495 spi8: spi@a80000 { 1447 spi8: spi@a80000 {
1496 compatible = 1448 compatible = "qcom,geni-spi";
1497 reg = <0x0 0x 1449 reg = <0x0 0x00a80000 0x0 0x4000>;
1498 clock-names = 1450 clock-names = "se";
1499 clocks = <&gc 1451 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1500 interrupts = 1452 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1501 pinctrl-names 1453 pinctrl-names = "default";
1502 pinctrl-0 = < 1454 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1503 interconnects 1455 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1504 1456 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1505 1457 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1506 interconnect- 1458 interconnect-names = "qup-core", "qup-config", "qup-memory";
1507 dmas = <&gpi_ 1459 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1508 <&gpi_ 1460 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1509 dma-names = " 1461 dma-names = "tx", "rx";
1510 #address-cell 1462 #address-cells = <1>;
1511 #size-cells = 1463 #size-cells = <0>;
1512 status = "dis 1464 status = "disabled";
1513 }; 1465 };
1514 1466
1515 i2c9: i2c@a84000 { 1467 i2c9: i2c@a84000 {
1516 compatible = 1468 compatible = "qcom,geni-i2c";
1517 reg = <0x0 0x 1469 reg = <0x0 0x00a84000 0x0 0x4000>;
1518 clock-names = 1470 clock-names = "se";
1519 clocks = <&gc 1471 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1520 pinctrl-names 1472 pinctrl-names = "default";
1521 pinctrl-0 = < 1473 pinctrl-0 = <&qup_i2c9_data_clk>;
1522 interrupts = 1474 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1523 #address-cell 1475 #address-cells = <1>;
1524 #size-cells = 1476 #size-cells = <0>;
1525 interconnects 1477 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1526 1478 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1527 1479 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1528 interconnect- 1480 interconnect-names = "qup-core", "qup-config", "qup-memory";
1529 dmas = <&gpi_ 1481 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1530 <&gpi_ 1482 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1531 dma-names = " 1483 dma-names = "tx", "rx";
1532 status = "dis 1484 status = "disabled";
1533 }; 1485 };
1534 1486
1535 spi9: spi@a84000 { 1487 spi9: spi@a84000 {
1536 compatible = 1488 compatible = "qcom,geni-spi";
1537 reg = <0x0 0x 1489 reg = <0x0 0x00a84000 0x0 0x4000>;
1538 clock-names = 1490 clock-names = "se";
1539 clocks = <&gc 1491 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1540 interrupts = 1492 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1541 pinctrl-names 1493 pinctrl-names = "default";
1542 pinctrl-0 = < 1494 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1543 interconnects 1495 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1544 1496 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1545 1497 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1546 interconnect- 1498 interconnect-names = "qup-core", "qup-config", "qup-memory";
1547 dmas = <&gpi_ 1499 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1548 <&gpi_ 1500 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1549 dma-names = " 1501 dma-names = "tx", "rx";
1550 #address-cell 1502 #address-cells = <1>;
1551 #size-cells = 1503 #size-cells = <0>;
1552 status = "dis 1504 status = "disabled";
1553 }; 1505 };
1554 1506
1555 i2c10: i2c@a88000 { 1507 i2c10: i2c@a88000 {
1556 compatible = 1508 compatible = "qcom,geni-i2c";
1557 reg = <0x0 0x 1509 reg = <0x0 0x00a88000 0x0 0x4000>;
1558 clock-names = 1510 clock-names = "se";
1559 clocks = <&gc 1511 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1560 pinctrl-names 1512 pinctrl-names = "default";
1561 pinctrl-0 = < 1513 pinctrl-0 = <&qup_i2c10_data_clk>;
1562 interrupts = 1514 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1563 #address-cell 1515 #address-cells = <1>;
1564 #size-cells = 1516 #size-cells = <0>;
1565 interconnects 1517 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1566 1518 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1567 1519 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1568 interconnect- 1520 interconnect-names = "qup-core", "qup-config", "qup-memory";
1569 dmas = <&gpi_ 1521 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1570 <&gpi_ 1522 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1571 dma-names = " 1523 dma-names = "tx", "rx";
1572 status = "dis 1524 status = "disabled";
1573 }; 1525 };
1574 1526
1575 spi10: spi@a88000 { 1527 spi10: spi@a88000 {
1576 compatible = 1528 compatible = "qcom,geni-spi";
1577 reg = <0x0 0x 1529 reg = <0x0 0x00a88000 0x0 0x4000>;
1578 clock-names = 1530 clock-names = "se";
1579 clocks = <&gc 1531 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1580 interrupts = 1532 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1581 pinctrl-names 1533 pinctrl-names = "default";
1582 pinctrl-0 = < 1534 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1583 interconnects 1535 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1584 1536 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1585 1537 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1586 interconnect- 1538 interconnect-names = "qup-core", "qup-config", "qup-memory";
1587 dmas = <&gpi_ 1539 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1588 <&gpi_ 1540 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1589 dma-names = " 1541 dma-names = "tx", "rx";
1590 #address-cell 1542 #address-cells = <1>;
1591 #size-cells = 1543 #size-cells = <0>;
1592 status = "dis 1544 status = "disabled";
1593 }; 1545 };
1594 1546
1595 i2c11: i2c@a8c000 { 1547 i2c11: i2c@a8c000 {
1596 compatible = 1548 compatible = "qcom,geni-i2c";
1597 reg = <0x0 0x 1549 reg = <0x0 0x00a8c000 0x0 0x4000>;
1598 clock-names = 1550 clock-names = "se";
1599 clocks = <&gc 1551 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1600 pinctrl-names 1552 pinctrl-names = "default";
1601 pinctrl-0 = < 1553 pinctrl-0 = <&qup_i2c11_data_clk>;
1602 interrupts = 1554 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1603 #address-cell 1555 #address-cells = <1>;
1604 #size-cells = 1556 #size-cells = <0>;
1605 interconnects 1557 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1606 1558 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1607 1559 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1608 interconnect- 1560 interconnect-names = "qup-core", "qup-config", "qup-memory";
1609 dmas = <&gpi_ 1561 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1610 <&gpi_ 1562 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1611 dma-names = " 1563 dma-names = "tx", "rx";
1612 status = "dis 1564 status = "disabled";
1613 }; 1565 };
1614 1566
1615 spi11: spi@a8c000 { 1567 spi11: spi@a8c000 {
1616 compatible = 1568 compatible = "qcom,geni-spi";
1617 reg = <0x0 0x 1569 reg = <0x0 0x00a8c000 0x0 0x4000>;
1618 clock-names = 1570 clock-names = "se";
1619 clocks = <&gc 1571 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1620 interrupts = 1572 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1621 pinctrl-names 1573 pinctrl-names = "default";
1622 pinctrl-0 = < 1574 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1623 interconnects 1575 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1624 1576 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1625 1577 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1626 interconnect- 1578 interconnect-names = "qup-core", "qup-config", "qup-memory";
1627 dmas = <&gpi_ 1579 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1628 <&gpi_ 1580 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1629 dma-names = " 1581 dma-names = "tx", "rx";
1630 #address-cell 1582 #address-cells = <1>;
1631 #size-cells = 1583 #size-cells = <0>;
1632 status = "dis 1584 status = "disabled";
1633 }; 1585 };
1634 1586
1635 i2c12: i2c@a90000 { 1587 i2c12: i2c@a90000 {
1636 compatible = 1588 compatible = "qcom,geni-i2c";
1637 reg = <0x0 0x 1589 reg = <0x0 0x00a90000 0x0 0x4000>;
1638 clock-names = 1590 clock-names = "se";
1639 clocks = <&gc 1591 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1640 pinctrl-names 1592 pinctrl-names = "default";
1641 pinctrl-0 = < 1593 pinctrl-0 = <&qup_i2c12_data_clk>;
1642 interrupts = 1594 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1643 #address-cell 1595 #address-cells = <1>;
1644 #size-cells = 1596 #size-cells = <0>;
1645 interconnects 1597 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1646 1598 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1647 1599 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1648 interconnect- 1600 interconnect-names = "qup-core", "qup-config", "qup-memory";
1649 dmas = <&gpi_ 1601 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1650 <&gpi_ 1602 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1651 dma-names = " 1603 dma-names = "tx", "rx";
1652 status = "dis 1604 status = "disabled";
1653 }; 1605 };
1654 1606
1655 spi12: spi@a90000 { 1607 spi12: spi@a90000 {
1656 compatible = 1608 compatible = "qcom,geni-spi";
1657 reg = <0x0 0x 1609 reg = <0x0 0x00a90000 0x0 0x4000>;
1658 clock-names = 1610 clock-names = "se";
1659 clocks = <&gc 1611 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1660 interrupts = 1612 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1661 pinctrl-names 1613 pinctrl-names = "default";
1662 pinctrl-0 = < 1614 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1663 interconnects 1615 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1664 1616 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1665 1617 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1666 interconnect- 1618 interconnect-names = "qup-core", "qup-config", "qup-memory";
1667 dmas = <&gpi_ 1619 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1668 <&gpi_ 1620 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1669 dma-names = " 1621 dma-names = "tx", "rx";
1670 #address-cell 1622 #address-cells = <1>;
1671 #size-cells = 1623 #size-cells = <0>;
1672 status = "dis 1624 status = "disabled";
1673 }; 1625 };
1674 1626
1675 i2c13: i2c@a94000 { 1627 i2c13: i2c@a94000 {
1676 compatible = 1628 compatible = "qcom,geni-i2c";
1677 reg = <0 0x00 1629 reg = <0 0x00a94000 0 0x4000>;
1678 clock-names = 1630 clock-names = "se";
1679 clocks = <&gc 1631 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1680 pinctrl-names 1632 pinctrl-names = "default";
1681 pinctrl-0 = < 1633 pinctrl-0 = <&qup_i2c13_data_clk>;
1682 interrupts = 1634 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1683 interconnects 1635 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1684 1636 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1685 1637 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1686 interconnect- 1638 interconnect-names = "qup-core", "qup-config", "qup-memory";
1687 dmas = <&gpi_ 1639 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1688 <&gpi_ 1640 <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1689 dma-names = " 1641 dma-names = "tx", "rx";
1690 #address-cell 1642 #address-cells = <1>;
1691 #size-cells = 1643 #size-cells = <0>;
1692 status = "dis 1644 status = "disabled";
1693 }; 1645 };
1694 1646
1695 spi13: spi@a94000 { 1647 spi13: spi@a94000 {
1696 compatible = 1648 compatible = "qcom,geni-spi";
1697 reg = <0x0 0x 1649 reg = <0x0 0x00a94000 0x0 0x4000>;
1698 clock-names = 1650 clock-names = "se";
1699 clocks = <&gc 1651 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1700 interrupts = 1652 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1701 pinctrl-names 1653 pinctrl-names = "default";
1702 pinctrl-0 = < 1654 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1703 interconnects 1655 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1704 1656 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1705 1657 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1706 interconnect- 1658 interconnect-names = "qup-core", "qup-config", "qup-memory";
1707 dmas = <&gpi_ 1659 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1708 <&gpi_ 1660 <&gpi_dma1 1 5 QCOM_GPI_SPI>;
1709 dma-names = " 1661 dma-names = "tx", "rx";
1710 #address-cell 1662 #address-cells = <1>;
1711 #size-cells = 1663 #size-cells = <0>;
1712 status = "dis 1664 status = "disabled";
1713 }; 1665 };
1714 1666
1715 i2c14: i2c@a98000 { 1667 i2c14: i2c@a98000 {
1716 compatible = 1668 compatible = "qcom,geni-i2c";
1717 reg = <0 0x00 1669 reg = <0 0x00a98000 0 0x4000>;
1718 clock-names = 1670 clock-names = "se";
1719 clocks = <&gc 1671 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1720 pinctrl-names 1672 pinctrl-names = "default";
1721 pinctrl-0 = < 1673 pinctrl-0 = <&qup_i2c14_data_clk>;
1722 interrupts = 1674 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
1723 interconnects 1675 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1724 1676 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1725 1677 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1726 interconnect- 1678 interconnect-names = "qup-core", "qup-config", "qup-memory";
1727 dmas = <&gpi_ 1679 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
1728 <&gpi_ 1680 <&gpi_dma1 1 6 QCOM_GPI_I2C>;
1729 dma-names = " 1681 dma-names = "tx", "rx";
1730 #address-cell 1682 #address-cells = <1>;
1731 #size-cells = 1683 #size-cells = <0>;
1732 status = "dis 1684 status = "disabled";
1733 }; 1685 };
1734 1686
1735 spi14: spi@a98000 { 1687 spi14: spi@a98000 {
1736 compatible = 1688 compatible = "qcom,geni-spi";
1737 reg = <0x0 0x 1689 reg = <0x0 0x00a98000 0x0 0x4000>;
1738 clock-names = 1690 clock-names = "se";
1739 clocks = <&gc 1691 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1740 interrupts = 1692 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
1741 pinctrl-names 1693 pinctrl-names = "default";
1742 pinctrl-0 = < 1694 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
1743 interconnects 1695 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1744 1696 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1745 1697 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1746 interconnect- 1698 interconnect-names = "qup-core", "qup-config", "qup-memory";
1747 dmas = <&gpi_ 1699 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
1748 <&gpi_ 1700 <&gpi_dma1 1 6 QCOM_GPI_SPI>;
1749 dma-names = " 1701 dma-names = "tx", "rx";
1750 #address-cell 1702 #address-cells = <1>;
1751 #size-cells = 1703 #size-cells = <0>;
1752 status = "dis 1704 status = "disabled";
1753 }; 1705 };
1754 }; 1706 };
1755 1707
1756 rng: rng@10c3000 { !! 1708 pcie0: pci@1c00000 {
1757 compatible = "qcom,sm <<
1758 reg = <0 0x010c3000 0 <<
1759 }; <<
1760 <<
1761 pcie0: pcie@1c00000 { <<
1762 compatible = "qcom,pc 1709 compatible = "qcom,pcie-sm8450-pcie0";
1763 reg = <0 0x01c00000 0 1710 reg = <0 0x01c00000 0 0x3000>,
1764 <0 0x60000000 0 1711 <0 0x60000000 0 0xf1d>,
1765 <0 0x60000f20 0 1712 <0 0x60000f20 0 0xa8>,
1766 <0 0x60001000 0 1713 <0 0x60001000 0 0x1000>,
1767 <0 0x60100000 0 1714 <0 0x60100000 0 0x100000>;
1768 reg-names = "parf", " 1715 reg-names = "parf", "dbi", "elbi", "atu", "config";
1769 device_type = "pci"; 1716 device_type = "pci";
1770 linux,pci-domain = <0 1717 linux,pci-domain = <0>;
1771 bus-range = <0x00 0xf 1718 bus-range = <0x00 0xff>;
1772 num-lanes = <1>; 1719 num-lanes = <1>;
1773 1720
1774 #address-cells = <3>; 1721 #address-cells = <3>;
1775 #size-cells = <2>; 1722 #size-cells = <2>;
1776 1723
1777 ranges = <0x01000000 !! 1724 ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
1778 <0x02000000 !! 1725 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>;
1779 1726
1780 msi-map = <0x0 &gic_i !! 1727 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
1781 <0x100 &gic !! 1728 interrupt-names = "msi";
1782 msi-map-mask = <0xff0 <<
1783 interrupts = <GIC_SPI <<
1784 <GIC_SPI <<
1785 <GIC_SPI <<
1786 <GIC_SPI <<
1787 <GIC_SPI <<
1788 <GIC_SPI <<
1789 <GIC_SPI <<
1790 <GIC_SPI <<
1791 interrupt-names = "ms <<
1792 "ms <<
1793 "ms <<
1794 "ms <<
1795 "ms <<
1796 "ms <<
1797 "ms <<
1798 "ms <<
1799 #interrupt-cells = <1 1729 #interrupt-cells = <1>;
1800 interrupt-map-mask = 1730 interrupt-map-mask = <0 0 0 0x7>;
1801 interrupt-map = <0 0 1731 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1802 <0 0 1732 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1803 <0 0 1733 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1804 <0 0 1734 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1805 1735
1806 interconnects = <&pci <<
1807 &mc_ <<
1808 <&gem <<
1809 &con <<
1810 interconnect-names = <<
1811 <<
1812 clocks = <&gcc GCC_PC 1736 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1813 <&gcc GCC_PC 1737 <&gcc GCC_PCIE_0_PIPE_CLK_SRC>,
1814 <&pcie0_phy> !! 1738 <&pcie0_lane>,
1815 <&rpmhcc RPM 1739 <&rpmhcc RPMH_CXO_CLK>,
1816 <&gcc GCC_PC 1740 <&gcc GCC_PCIE_0_AUX_CLK>,
1817 <&gcc GCC_PC 1741 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1818 <&gcc GCC_PC 1742 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1819 <&gcc GCC_PC 1743 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1820 <&gcc GCC_PC 1744 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
1821 <&gcc GCC_DD 1745 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1822 <&gcc GCC_AG 1746 <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
1823 <&gcc GCC_AG 1747 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
1824 clock-names = "pipe", 1748 clock-names = "pipe",
1825 "pipe_m 1749 "pipe_mux",
1826 "phy_pi 1750 "phy_pipe",
1827 "ref", 1751 "ref",
1828 "aux", 1752 "aux",
1829 "cfg", 1753 "cfg",
1830 "bus_ma 1754 "bus_master",
1831 "bus_sl 1755 "bus_slave",
1832 "slave_ 1756 "slave_q2a",
1833 "ddrss_ 1757 "ddrss_sf_tbu",
1834 "aggre0 1758 "aggre0",
1835 "aggre1 1759 "aggre1";
1836 1760
>> 1761 iommus = <&apps_smmu 0x1c00 0x7f>;
1837 iommu-map = <0x0 &a 1762 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
1838 <0x100 &a 1763 <0x100 &apps_smmu 0x1c01 0x1>;
1839 1764
1840 resets = <&gcc GCC_PC 1765 resets = <&gcc GCC_PCIE_0_BCR>;
1841 reset-names = "pci"; 1766 reset-names = "pci";
1842 1767
1843 power-domains = <&gcc 1768 power-domains = <&gcc PCIE_0_GDSC>;
>> 1769 power-domain-names = "gdsc";
1844 1770
1845 phys = <&pcie0_phy>; !! 1771 phys = <&pcie0_lane>;
1846 phy-names = "pciephy" 1772 phy-names = "pciephy";
1847 1773
1848 perst-gpios = <&tlmm 1774 perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
1849 wake-gpios = <&tlmm 9 1775 wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
1850 1776
1851 pinctrl-names = "defa 1777 pinctrl-names = "default";
1852 pinctrl-0 = <&pcie0_d 1778 pinctrl-0 = <&pcie0_default_state>;
1853 1779
1854 operating-points-v2 = <<
1855 <<
1856 status = "disabled"; 1780 status = "disabled";
1857 <<
1858 pcie0_opp_table: opp- <<
1859 compatible = <<
1860 <<
1861 /* GEN 1 x1 * <<
1862 opp-2500000 { <<
1863 opp-h <<
1864 requi <<
1865 opp-p <<
1866 }; <<
1867 <<
1868 /* GEN 2 x1 * <<
1869 opp-5000000 { <<
1870 opp-h <<
1871 requi <<
1872 opp-p <<
1873 }; <<
1874 <<
1875 /* GEN 3 x1 * <<
1876 opp-8000000 { <<
1877 opp-h <<
1878 requi <<
1879 opp-p <<
1880 }; <<
1881 }; <<
1882 <<
1883 pcie@0 { <<
1884 device_type = <<
1885 reg = <0x0 0x <<
1886 bus-range = < <<
1887 <<
1888 #address-cell <<
1889 #size-cells = <<
1890 ranges; <<
1891 }; <<
1892 }; 1781 };
1893 1782
1894 pcie0_phy: phy@1c06000 { 1783 pcie0_phy: phy@1c06000 {
1895 compatible = "qcom,sm 1784 compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy";
1896 reg = <0 0x01c06000 0 !! 1785 reg = <0 0x01c06000 0 0x200>;
1897 !! 1786 #address-cells = <2>;
>> 1787 #size-cells = <2>;
>> 1788 ranges;
1898 clocks = <&gcc GCC_PC 1789 clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
1899 <&gcc GCC_PC 1790 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1900 <&gcc GCC_PC 1791 <&gcc GCC_PCIE_0_CLKREF_EN>,
1901 <&gcc GCC_PC !! 1792 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
1902 <&gcc GCC_PC !! 1793 clock-names = "aux", "cfg_ahb", "ref", "refgen";
1903 clock-names = "aux", <<
1904 "cfg_ah <<
1905 "ref", <<
1906 "rchng" <<
1907 "pipe"; <<
1908 <<
1909 clock-output-names = <<
1910 #clock-cells = <0>; <<
1911 <<
1912 #phy-cells = <0>; <<
1913 1794
1914 resets = <&gcc GCC_PC 1795 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1915 reset-names = "phy"; 1796 reset-names = "phy";
1916 1797
1917 assigned-clocks = <&g 1798 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
1918 assigned-clock-rates 1799 assigned-clock-rates = <100000000>;
1919 1800
1920 status = "disabled"; 1801 status = "disabled";
>> 1802
>> 1803 pcie0_lane: phy@1c06200 {
>> 1804 reg = <0 0x1c06e00 0 0x200>, /* tx */
>> 1805 <0 0x1c07000 0 0x200>, /* rx */
>> 1806 <0 0x1c06200 0 0x200>, /* pcs */
>> 1807 <0 0x1c06600 0 0x200>; /* pcs_pcie */
>> 1808 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
>> 1809 clock-names = "pipe0";
>> 1810
>> 1811 #clock-cells = <0>;
>> 1812 #phy-cells = <0>;
>> 1813 clock-output-names = "pcie_0_pipe_clk";
>> 1814 };
1921 }; 1815 };
1922 1816
1923 pcie1: pcie@1c08000 { !! 1817 pcie1: pci@1c08000 {
1924 compatible = "qcom,pc 1818 compatible = "qcom,pcie-sm8450-pcie1";
1925 reg = <0 0x01c08000 0 1819 reg = <0 0x01c08000 0 0x3000>,
1926 <0 0x40000000 0 1820 <0 0x40000000 0 0xf1d>,
1927 <0 0x40000f20 0 1821 <0 0x40000f20 0 0xa8>,
1928 <0 0x40001000 0 1822 <0 0x40001000 0 0x1000>,
1929 <0 0x40100000 0 1823 <0 0x40100000 0 0x100000>;
1930 reg-names = "parf", " 1824 reg-names = "parf", "dbi", "elbi", "atu", "config";
1931 device_type = "pci"; 1825 device_type = "pci";
1932 linux,pci-domain = <1 1826 linux,pci-domain = <1>;
1933 bus-range = <0x00 0xf 1827 bus-range = <0x00 0xff>;
1934 num-lanes = <2>; 1828 num-lanes = <2>;
1935 1829
1936 #address-cells = <3>; 1830 #address-cells = <3>;
1937 #size-cells = <2>; 1831 #size-cells = <2>;
1938 1832
1939 ranges = <0x01000000 !! 1833 ranges = <0x01000000 0x0 0x40200000 0 0x40200000 0x0 0x100000>,
1940 <0x02000000 !! 1834 <0x02000000 0x0 0x40300000 0 0x40300000 0x0 0x1fd00000>;
1941 1835
1942 msi-map = <0x0 &gic_i !! 1836 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
1943 <0x100 &gic !! 1837 interrupt-names = "msi";
1944 msi-map-mask = <0xff0 <<
1945 interrupts = <GIC_SPI <<
1946 <GIC_SPI <<
1947 <GIC_SPI <<
1948 <GIC_SPI <<
1949 <GIC_SPI <<
1950 <GIC_SPI <<
1951 <GIC_SPI <<
1952 <GIC_SPI <<
1953 interrupt-names = "ms <<
1954 "ms <<
1955 "ms <<
1956 "ms <<
1957 "ms <<
1958 "ms <<
1959 "ms <<
1960 "ms <<
1961 #interrupt-cells = <1 1838 #interrupt-cells = <1>;
1962 interrupt-map-mask = 1839 interrupt-map-mask = <0 0 0 0x7>;
1963 interrupt-map = <0 0 1840 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1964 <0 0 1841 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1965 <0 0 1842 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1966 <0 0 1843 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1967 1844
1968 interconnects = <&pci <<
1969 &mc_ <<
1970 <&gem <<
1971 &con <<
1972 interconnect-names = <<
1973 <<
1974 clocks = <&gcc GCC_PC 1845 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1975 <&gcc GCC_PC 1846 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>,
1976 <&pcie1_phy !! 1847 <&pcie1_lane>,
1977 <&rpmhcc RPM 1848 <&rpmhcc RPMH_CXO_CLK>,
1978 <&gcc GCC_PC 1849 <&gcc GCC_PCIE_1_AUX_CLK>,
1979 <&gcc GCC_PC 1850 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1980 <&gcc GCC_PC 1851 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1981 <&gcc GCC_PC 1852 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
1982 <&gcc GCC_PC 1853 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
1983 <&gcc GCC_DD 1854 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1984 <&gcc GCC_AG 1855 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
1985 clock-names = "pipe", 1856 clock-names = "pipe",
1986 "pipe_m 1857 "pipe_mux",
1987 "phy_pi 1858 "phy_pipe",
1988 "ref", 1859 "ref",
1989 "aux", 1860 "aux",
1990 "cfg", 1861 "cfg",
1991 "bus_ma 1862 "bus_master",
1992 "bus_sl 1863 "bus_slave",
1993 "slave_ 1864 "slave_q2a",
1994 "ddrss_ 1865 "ddrss_sf_tbu",
1995 "aggre1 1866 "aggre1";
1996 1867
>> 1868 iommus = <&apps_smmu 0x1c80 0x7f>;
1997 iommu-map = <0x0 &a 1869 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
1998 <0x100 &a 1870 <0x100 &apps_smmu 0x1c81 0x1>;
1999 1871
2000 resets = <&gcc GCC_PC 1872 resets = <&gcc GCC_PCIE_1_BCR>;
2001 reset-names = "pci"; 1873 reset-names = "pci";
2002 1874
2003 power-domains = <&gcc 1875 power-domains = <&gcc PCIE_1_GDSC>;
>> 1876 power-domain-names = "gdsc";
2004 1877
2005 phys = <&pcie1_phy>; !! 1878 phys = <&pcie1_lane>;
2006 phy-names = "pciephy" 1879 phy-names = "pciephy";
2007 1880
2008 perst-gpios = <&tlmm !! 1881 perst-gpio = <&tlmm 97 GPIO_ACTIVE_LOW>;
2009 wake-gpios = <&tlmm 9 !! 1882 enable-gpio = <&tlmm 99 GPIO_ACTIVE_HIGH>;
2010 1883
2011 pinctrl-names = "defa 1884 pinctrl-names = "default";
2012 pinctrl-0 = <&pcie1_d 1885 pinctrl-0 = <&pcie1_default_state>;
2013 1886
2014 operating-points-v2 = <<
2015 <<
2016 status = "disabled"; 1887 status = "disabled";
2017 <<
2018 pcie1_opp_table: opp- <<
2019 compatible = <<
2020 <<
2021 /* GEN 1 x1 * <<
2022 opp-2500000 { <<
2023 opp-h <<
2024 requi <<
2025 opp-p <<
2026 }; <<
2027 <<
2028 /* GEN 1 x2 a <<
2029 opp-5000000 { <<
2030 opp-h <<
2031 requi <<
2032 opp-p <<
2033 }; <<
2034 <<
2035 /* GEN 2 x2 * <<
2036 opp-10000000 <<
2037 opp-h <<
2038 requi <<
2039 opp-p <<
2040 }; <<
2041 <<
2042 /* GEN 3 x1 * <<
2043 opp-8000000 { <<
2044 opp-h <<
2045 requi <<
2046 opp-p <<
2047 }; <<
2048 <<
2049 /* GEN 3 x2 a <<
2050 opp-16000000 <<
2051 opp-h <<
2052 requi <<
2053 opp-p <<
2054 }; <<
2055 <<
2056 /* GEN 4 x2 * <<
2057 opp-32000000 <<
2058 opp-h <<
2059 requi <<
2060 opp-p <<
2061 }; <<
2062 }; <<
2063 <<
2064 pcie@0 { <<
2065 device_type = <<
2066 reg = <0x0 0x <<
2067 bus-range = < <<
2068 <<
2069 #address-cell <<
2070 #size-cells = <<
2071 ranges; <<
2072 }; <<
2073 }; 1888 };
2074 1889
2075 pcie1_phy: phy@1c0e000 { !! 1890 pcie1_phy: phy@1c0f000 {
2076 compatible = "qcom,sm 1891 compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy";
2077 reg = <0 0x01c0e000 0 !! 1892 reg = <0 0x01c0f000 0 0x200>;
2078 !! 1893 #address-cells = <2>;
>> 1894 #size-cells = <2>;
>> 1895 ranges;
2079 clocks = <&gcc GCC_PC 1896 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>,
2080 <&gcc GCC_PC 1897 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2081 <&gcc GCC_PC 1898 <&gcc GCC_PCIE_1_CLKREF_EN>,
2082 <&gcc GCC_PC !! 1899 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
2083 <&gcc GCC_PC !! 1900 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2084 clock-names = "aux", <<
2085 "cfg_ah <<
2086 "ref", <<
2087 "rchng" <<
2088 "pipe"; <<
2089 <<
2090 clock-output-names = <<
2091 #clock-cells = <1>; <<
2092 <<
2093 #phy-cells = <0>; <<
2094 1901
2095 resets = <&gcc GCC_PC 1902 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2096 reset-names = "phy"; 1903 reset-names = "phy";
2097 1904
2098 assigned-clocks = <&g 1905 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
2099 assigned-clock-rates 1906 assigned-clock-rates = <100000000>;
2100 1907
2101 status = "disabled"; 1908 status = "disabled";
>> 1909
>> 1910 pcie1_lane: phy@1c0e000 {
>> 1911 reg = <0 0x1c0e000 0 0x200>, /* tx */
>> 1912 <0 0x1c0e200 0 0x300>, /* rx */
>> 1913 <0 0x1c0f200 0 0x200>, /* pcs */
>> 1914 <0 0x1c0e800 0 0x200>, /* tx */
>> 1915 <0 0x1c0ea00 0 0x300>, /* rx */
>> 1916 <0 0x1c0f400 0 0xc00>; /* pcs_pcie */
>> 1917 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
>> 1918 clock-names = "pipe0";
>> 1919
>> 1920 #clock-cells = <0>;
>> 1921 #phy-cells = <0>;
>> 1922 clock-output-names = "pcie_1_pipe_clk";
>> 1923 };
2102 }; 1924 };
2103 1925
2104 config_noc: interconnect@1500 1926 config_noc: interconnect@1500000 {
2105 compatible = "qcom,sm 1927 compatible = "qcom,sm8450-config-noc";
2106 reg = <0 0x01500000 0 1928 reg = <0 0x01500000 0 0x1c000>;
2107 #interconnect-cells = 1929 #interconnect-cells = <2>;
2108 qcom,bcm-voters = <&a 1930 qcom,bcm-voters = <&apps_bcm_voter>;
2109 }; 1931 };
2110 1932
2111 system_noc: interconnect@1680 1933 system_noc: interconnect@1680000 {
2112 compatible = "qcom,sm 1934 compatible = "qcom,sm8450-system-noc";
2113 reg = <0 0x01680000 0 1935 reg = <0 0x01680000 0 0x1e200>;
2114 #interconnect-cells = 1936 #interconnect-cells = <2>;
2115 qcom,bcm-voters = <&a 1937 qcom,bcm-voters = <&apps_bcm_voter>;
2116 }; 1938 };
2117 1939
2118 pcie_noc: interconnect@16c000 1940 pcie_noc: interconnect@16c0000 {
2119 compatible = "qcom,sm 1941 compatible = "qcom,sm8450-pcie-anoc";
2120 reg = <0 0x016c0000 0 1942 reg = <0 0x016c0000 0 0xe280>;
2121 #interconnect-cells = 1943 #interconnect-cells = <2>;
2122 qcom,bcm-voters = <&a 1944 qcom,bcm-voters = <&apps_bcm_voter>;
2123 }; 1945 };
2124 1946
2125 aggre1_noc: interconnect@16e0 1947 aggre1_noc: interconnect@16e0000 {
2126 compatible = "qcom,sm 1948 compatible = "qcom,sm8450-aggre1-noc";
2127 reg = <0 0x016e0000 0 1949 reg = <0 0x016e0000 0 0x1c080>;
2128 #interconnect-cells = 1950 #interconnect-cells = <2>;
2129 clocks = <&gcc GCC_AG 1951 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2130 <&gcc GCC_AG 1952 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
2131 qcom,bcm-voters = <&a 1953 qcom,bcm-voters = <&apps_bcm_voter>;
2132 }; 1954 };
2133 1955
2134 aggre2_noc: interconnect@1700 1956 aggre2_noc: interconnect@1700000 {
2135 compatible = "qcom,sm 1957 compatible = "qcom,sm8450-aggre2-noc";
2136 reg = <0 0x01700000 0 1958 reg = <0 0x01700000 0 0x31080>;
2137 #interconnect-cells = 1959 #interconnect-cells = <2>;
2138 qcom,bcm-voters = <&a 1960 qcom,bcm-voters = <&apps_bcm_voter>;
2139 clocks = <&gcc GCC_AG 1961 clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
2140 <&gcc GCC_AG 1962 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
2141 <&gcc GCC_AG 1963 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2142 <&rpmhcc RPM 1964 <&rpmhcc RPMH_IPA_CLK>;
2143 }; 1965 };
2144 1966
2145 mmss_noc: interconnect@174000 1967 mmss_noc: interconnect@1740000 {
2146 compatible = "qcom,sm 1968 compatible = "qcom,sm8450-mmss-noc";
2147 reg = <0 0x01740000 0 1969 reg = <0 0x01740000 0 0x1f080>;
2148 #interconnect-cells = 1970 #interconnect-cells = <2>;
2149 qcom,bcm-voters = <&a 1971 qcom,bcm-voters = <&apps_bcm_voter>;
2150 }; 1972 };
2151 1973
2152 tcsr_mutex: hwlock@1f40000 { 1974 tcsr_mutex: hwlock@1f40000 {
2153 compatible = "qcom,tc 1975 compatible = "qcom,tcsr-mutex";
2154 reg = <0x0 0x01f40000 1976 reg = <0x0 0x01f40000 0x0 0x40000>;
2155 #hwlock-cells = <1>; 1977 #hwlock-cells = <1>;
2156 }; 1978 };
2157 1979
2158 tcsr: syscon@1fc0000 { <<
2159 compatible = "qcom,sm <<
2160 reg = <0x0 0x1fc0000 <<
2161 }; <<
2162 <<
2163 gpu: gpu@3d00000 { <<
2164 compatible = "qcom,ad <<
2165 reg = <0x0 0x03d00000 <<
2166 <0x0 0x03d9e000 <<
2167 <0x0 0x03d61000 <<
2168 reg-names = "kgsl_3d0 <<
2169 "cx_mem", <<
2170 "cx_dbgc" <<
2171 <<
2172 interrupts = <GIC_SPI <<
2173 <<
2174 iommus = <&adreno_smm <<
2175 <&adreno_smm <<
2176 <<
2177 operating-points-v2 = <<
2178 <<
2179 qcom,gmu = <&gmu>; <<
2180 #cooling-cells = <2>; <<
2181 <<
2182 status = "disabled"; <<
2183 <<
2184 zap-shader { <<
2185 memory-region <<
2186 }; <<
2187 <<
2188 gpu_opp_table: opp-ta <<
2189 compatible = <<
2190 <<
2191 opp-818000000 <<
2192 opp-h <<
2193 opp-l <<
2194 }; <<
2195 <<
2196 opp-791000000 <<
2197 opp-h <<
2198 opp-l <<
2199 }; <<
2200 <<
2201 opp-734000000 <<
2202 opp-h <<
2203 opp-l <<
2204 }; <<
2205 <<
2206 opp-640000000 <<
2207 opp-h <<
2208 opp-l <<
2209 }; <<
2210 <<
2211 opp-599000000 <<
2212 opp-h <<
2213 opp-l <<
2214 }; <<
2215 <<
2216 opp-545000000 <<
2217 opp-h <<
2218 opp-l <<
2219 }; <<
2220 <<
2221 opp-492000000 <<
2222 opp-h <<
2223 opp-l <<
2224 }; <<
2225 <<
2226 opp-421000000 <<
2227 opp-h <<
2228 opp-l <<
2229 }; <<
2230 <<
2231 opp-350000000 <<
2232 opp-h <<
2233 opp-l <<
2234 }; <<
2235 <<
2236 opp-317000000 <<
2237 opp-h <<
2238 opp-l <<
2239 }; <<
2240 <<
2241 opp-285000000 <<
2242 opp-h <<
2243 opp-l <<
2244 }; <<
2245 <<
2246 opp-220000000 <<
2247 opp-h <<
2248 opp-l <<
2249 }; <<
2250 }; <<
2251 }; <<
2252 <<
2253 gmu: gmu@3d6a000 { <<
2254 compatible = "qcom,ad <<
2255 reg = <0x0 0x03d6a000 <<
2256 <0x0 0x03d50000 <<
2257 <0x0 0x0b290000 <<
2258 reg-names = "gmu", "r <<
2259 <<
2260 interrupts = <GIC_SPI <<
2261 <GIC_SPI <<
2262 interrupt-names = "hf <<
2263 <<
2264 clocks = <&gpucc GPU_ <<
2265 <&gpucc GPU_ <<
2266 <&gpucc GPU_ <<
2267 <&gcc GCC_DD <<
2268 <&gcc GCC_GP <<
2269 <&gpucc GPU_ <<
2270 <&gpucc GPU_ <<
2271 clock-names = "ahb", <<
2272 "gmu", <<
2273 "cxo", <<
2274 "axi", <<
2275 "memnoc <<
2276 "hub", <<
2277 "demet" <<
2278 <<
2279 power-domains = <&gpu <<
2280 <&gpu <<
2281 power-domain-names = <<
2282 <<
2283 <<
2284 iommus = <&adreno_smm <<
2285 <<
2286 qcom,qmp = <&aoss_qmp <<
2287 <<
2288 operating-points-v2 = <<
2289 <<
2290 gmu_opp_table: opp-ta <<
2291 compatible = <<
2292 <<
2293 opp-500000000 <<
2294 opp-h <<
2295 opp-l <<
2296 }; <<
2297 <<
2298 opp-200000000 <<
2299 opp-h <<
2300 opp-l <<
2301 }; <<
2302 }; <<
2303 }; <<
2304 <<
2305 gpucc: clock-controller@3d900 <<
2306 compatible = "qcom,sm <<
2307 reg = <0x0 0x03d90000 <<
2308 clocks = <&rpmhcc RPM <<
2309 <&gcc GCC_GP <<
2310 <&gcc GCC_GP <<
2311 #clock-cells = <1>; <<
2312 #reset-cells = <1>; <<
2313 #power-domain-cells = <<
2314 }; <<
2315 <<
2316 adreno_smmu: iommu@3da0000 { <<
2317 compatible = "qcom,sm <<
2318 "qcom,sm <<
2319 reg = <0x0 0x03da0000 <<
2320 #iommu-cells = <2>; <<
2321 #global-interrupts = <<
2322 interrupts = <GIC_SPI <<
2323 <GIC_SPI <<
2324 <GIC_SPI <<
2325 <GIC_SPI <<
2326 <GIC_SPI <<
2327 <GIC_SPI <<
2328 <GIC_SPI <<
2329 <GIC_SPI <<
2330 <GIC_SPI <<
2331 <GIC_SPI <<
2332 <GIC_SPI <<
2333 <GIC_SPI <<
2334 <GIC_SPI <<
2335 <GIC_SPI <<
2336 <GIC_SPI <<
2337 <GIC_SPI <<
2338 <GIC_SPI <<
2339 <GIC_SPI <<
2340 <GIC_SPI <<
2341 <GIC_SPI <<
2342 <GIC_SPI <<
2343 <GIC_SPI <<
2344 <GIC_SPI <<
2345 <GIC_SPI <<
2346 <GIC_SPI <<
2347 <GIC_SPI <<
2348 clocks = <&gpucc GPU_ <<
2349 <&gpucc GPU_ <<
2350 <&gpucc GPU_ <<
2351 <&gcc GCC_GP <<
2352 <&gcc GCC_GP <<
2353 <&gpucc GPU_ <<
2354 clock-names = "gmu", <<
2355 "hub", <<
2356 "hlos", <<
2357 "bus", <<
2358 "iface" <<
2359 "ahb"; <<
2360 power-domains = <&gpu <<
2361 dma-coherent; <<
2362 }; <<
2363 <<
2364 usb_1_hsphy: phy@88e3000 { 1980 usb_1_hsphy: phy@88e3000 {
2365 compatible = "qcom,sm 1981 compatible = "qcom,sm8450-usb-hs-phy",
2366 "qcom,us 1982 "qcom,usb-snps-hs-7nm-phy";
2367 reg = <0 0x088e3000 0 1983 reg = <0 0x088e3000 0 0x400>;
2368 status = "disabled"; 1984 status = "disabled";
2369 #phy-cells = <0>; 1985 #phy-cells = <0>;
2370 1986
2371 clocks = <&rpmhcc RPM 1987 clocks = <&rpmhcc RPMH_CXO_CLK>;
2372 clock-names = "ref"; 1988 clock-names = "ref";
2373 1989
2374 resets = <&gcc GCC_QU 1990 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2375 }; 1991 };
2376 1992
2377 usb_1_qmpphy: phy@88e8000 { !! 1993 usb_1_qmpphy: phy-wrapper@88e9000 {
2378 compatible = "qcom,sm !! 1994 compatible = "qcom,sm8450-qmp-usb3-phy";
2379 reg = <0 0x088e8000 0 !! 1995 reg = <0 0x088e9000 0 0x200>,
>> 1996 <0 0x088e8000 0 0x20>;
>> 1997 status = "disabled";
>> 1998 #address-cells = <2>;
>> 1999 #size-cells = <2>;
>> 2000 ranges;
2380 2001
2381 clocks = <&gcc GCC_US 2002 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2382 <&rpmhcc RPM 2003 <&rpmhcc RPMH_CXO_CLK>,
2383 <&gcc GCC_US !! 2004 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
2384 <&gcc GCC_US !! 2005 clock-names = "aux", "ref_clk_src", "com_aux";
2385 clock-names = "aux", <<
2386 2006
2387 resets = <&gcc GCC_US 2007 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
2388 <&gcc GCC_US 2008 <&gcc GCC_USB3_PHY_PRIM_BCR>;
2389 reset-names = "phy", 2009 reset-names = "phy", "common";
2390 2010
2391 #clock-cells = <1>; !! 2011 usb_1_ssphy: phy@88e9200 {
2392 #phy-cells = <1>; !! 2012 reg = <0 0x088e9200 0 0x200>,
2393 !! 2013 <0 0x088e9400 0 0x200>,
2394 orientation-switch; !! 2014 <0 0x088e9c00 0 0x400>,
2395 !! 2015 <0 0x088e9600 0 0x200>,
2396 status = "disabled"; !! 2016 <0 0x088e9800 0 0x200>,
2397 !! 2017 <0 0x088e9a00 0 0x100>;
2398 ports { !! 2018 #phy-cells = <0>;
2399 #address-cell !! 2019 #clock-cells = <0>;
2400 #size-cells = !! 2020 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2401 !! 2021 clock-names = "pipe0";
2402 port@0 { !! 2022 clock-output-names = "usb3_phy_pipe_clk_src";
2403 reg = <<
2404 <<
2405 usb_1 <<
2406 }; <<
2407 }; <<
2408 <<
2409 port@1 { <<
2410 reg = <<
2411 <<
2412 usb_1 <<
2413 <<
2414 }; <<
2415 }; <<
2416 <<
2417 port@2 { <<
2418 reg = <<
2419 <<
2420 usb_1 <<
2421 <<
2422 }; <<
2423 }; <<
2424 }; 2023 };
2425 }; 2024 };
2426 2025
2427 remoteproc_slpi: remoteproc@2 2026 remoteproc_slpi: remoteproc@2400000 {
2428 compatible = "qcom,sm 2027 compatible = "qcom,sm8450-slpi-pas";
2429 reg = <0 0x02400000 0 2028 reg = <0 0x02400000 0 0x4000>;
2430 2029
2431 interrupts-extended = 2030 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>,
2432 2031 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
2433 2032 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
2434 2033 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
2435 2034 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
2436 interrupt-names = "wd 2035 interrupt-names = "wdog", "fatal", "ready",
2437 "ha 2036 "handover", "stop-ack";
2438 2037
2439 clocks = <&rpmhcc RPM 2038 clocks = <&rpmhcc RPMH_CXO_CLK>;
2440 clock-names = "xo"; 2039 clock-names = "xo";
2441 2040
2442 power-domains = <&rpm !! 2041 power-domains = <&rpmhpd SM8450_LCX>,
2443 <&rpm !! 2042 <&rpmhpd SM8450_LMX>;
2444 power-domain-names = 2043 power-domain-names = "lcx", "lmx";
2445 2044
2446 memory-region = <&slp 2045 memory-region = <&slpi_mem>;
2447 2046
2448 qcom,qmp = <&aoss_qmp 2047 qcom,qmp = <&aoss_qmp>;
2449 2048
2450 qcom,smem-states = <& 2049 qcom,smem-states = <&smp2p_slpi_out 0>;
2451 qcom,smem-state-names 2050 qcom,smem-state-names = "stop";
2452 2051
2453 status = "disabled"; 2052 status = "disabled";
2454 2053
2455 glink-edge { 2054 glink-edge {
2456 interrupts-ex 2055 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
2457 2056 IPCC_MPROC_SIGNAL_GLINK_QMP
2458 2057 IRQ_TYPE_EDGE_RISING>;
2459 mboxes = <&ip 2058 mboxes = <&ipcc IPCC_CLIENT_SLPI
2460 2059 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2461 2060
2462 label = "slpi 2061 label = "slpi";
2463 qcom,remote-p 2062 qcom,remote-pid = <3>;
2464 2063
2465 fastrpc { 2064 fastrpc {
2466 compa 2065 compatible = "qcom,fastrpc";
2467 qcom, 2066 qcom,glink-channels = "fastrpcglink-apps-dsp";
2468 label 2067 label = "sdsp";
2469 qcom, <<
2470 #addr 2068 #address-cells = <1>;
2471 #size 2069 #size-cells = <0>;
2472 2070
2473 compu 2071 compute-cb@1 {
2474 2072 compatible = "qcom,fastrpc-compute-cb";
2475 2073 reg = <1>;
2476 2074 iommus = <&apps_smmu 0x0541 0x0>;
2477 }; 2075 };
2478 2076
2479 compu 2077 compute-cb@2 {
2480 2078 compatible = "qcom,fastrpc-compute-cb";
2481 2079 reg = <2>;
2482 2080 iommus = <&apps_smmu 0x0542 0x0>;
2483 }; 2081 };
2484 2082
2485 compu 2083 compute-cb@3 {
2486 2084 compatible = "qcom,fastrpc-compute-cb";
2487 2085 reg = <3>;
2488 2086 iommus = <&apps_smmu 0x0543 0x0>;
2489 2087 /* note: shared-cb = <4> in downstream */
2490 }; 2088 };
2491 }; 2089 };
2492 }; 2090 };
2493 }; 2091 };
2494 2092
2495 wsa2macro: codec@31e0000 { <<
2496 compatible = "qcom,sm <<
2497 reg = <0 0x031e0000 0 <<
2498 clocks = <&q6prmcc LP <<
2499 <&q6prmcc LP <<
2500 <&q6prmcc LP <<
2501 <&q6prmcc LP <<
2502 <&vamacro>; <<
2503 clock-names = "mclk", <<
2504 <<
2505 #clock-cells = <0>; <<
2506 clock-output-names = <<
2507 #sound-dai-cells = <1 <<
2508 }; <<
2509 <<
2510 swr4: soundwire@31f0000 { <<
2511 compatible = "qcom,so <<
2512 reg = <0 0x031f0000 0 <<
2513 interrupts = <GIC_SPI <<
2514 clocks = <&wsa2macro> <<
2515 clock-names = "iface" <<
2516 label = "WSA2"; <<
2517 <<
2518 pinctrl-0 = <&wsa2_sw <<
2519 pinctrl-names = "defa <<
2520 <<
2521 qcom,din-ports = <2>; <<
2522 qcom,dout-ports = <6> <<
2523 <<
2524 qcom,ports-sinterval- <<
2525 qcom,ports-offset1 = <<
2526 qcom,ports-offset2 = <<
2527 qcom,ports-hstart = <<
2528 qcom,ports-hstop = <<
2529 qcom,ports-word-lengt <<
2530 qcom,ports-block-pack <<
2531 qcom,ports-block-grou <<
2532 qcom,ports-lane-contr <<
2533 <<
2534 #address-cells = <2>; <<
2535 #size-cells = <0>; <<
2536 #sound-dai-cells = <1 <<
2537 status = "disabled"; <<
2538 }; <<
2539 <<
2540 rxmacro: codec@3200000 { <<
2541 compatible = "qcom,sm <<
2542 reg = <0 0x03200000 0 <<
2543 clocks = <&q6prmcc LP <<
2544 <&q6prmcc LP <<
2545 <&q6prmcc LP <<
2546 <&q6prmcc LP <<
2547 <&vamacro>; <<
2548 clock-names = "mclk", <<
2549 <<
2550 #clock-cells = <0>; <<
2551 clock-output-names = <<
2552 #sound-dai-cells = <1 <<
2553 }; <<
2554 <<
2555 swr1: soundwire@3210000 { <<
2556 compatible = "qcom,so <<
2557 reg = <0 0x03210000 0 <<
2558 interrupts = <GIC_SPI <<
2559 clocks = <&rxmacro>; <<
2560 clock-names = "iface" <<
2561 label = "RX"; <<
2562 qcom,din-ports = <0>; <<
2563 qcom,dout-ports = <5> <<
2564 <<
2565 pinctrl-0 = <&rx_swr_ <<
2566 pinctrl-names = "defa <<
2567 <<
2568 qcom,ports-sinterval- <<
2569 qcom,ports-offset1 = <<
2570 qcom,ports-offset2 = <<
2571 qcom,ports-hstart = <<
2572 qcom,ports-hstop = <<
2573 qcom,ports-word-lengt <<
2574 qcom,ports-block-pack <<
2575 qcom,ports-block-grou <<
2576 qcom,ports-lane-contr <<
2577 <<
2578 #address-cells = <2>; <<
2579 #size-cells = <0>; <<
2580 #sound-dai-cells = <1 <<
2581 status = "disabled"; <<
2582 }; <<
2583 <<
2584 txmacro: codec@3220000 { <<
2585 compatible = "qcom,sm <<
2586 reg = <0 0x03220000 0 <<
2587 clocks = <&q6prmcc LP <<
2588 <&q6prmcc LP <<
2589 <&q6prmcc LP <<
2590 <&q6prmcc LP <<
2591 <&vamacro>; <<
2592 clock-names = "mclk", <<
2593 <<
2594 #clock-cells = <0>; <<
2595 clock-output-names = <<
2596 #sound-dai-cells = <1 <<
2597 }; <<
2598 <<
2599 wsamacro: codec@3240000 { <<
2600 compatible = "qcom,sm <<
2601 reg = <0 0x03240000 0 <<
2602 clocks = <&q6prmcc LP <<
2603 <&q6prmcc LP <<
2604 <&q6prmcc LP <<
2605 <&q6prmcc LP <<
2606 <&vamacro>; <<
2607 clock-names = "mclk", <<
2608 <<
2609 #clock-cells = <0>; <<
2610 clock-output-names = <<
2611 #sound-dai-cells = <1 <<
2612 }; <<
2613 <<
2614 swr0: soundwire@3250000 { <<
2615 compatible = "qcom,so <<
2616 reg = <0 0x03250000 0 <<
2617 interrupts = <GIC_SPI <<
2618 clocks = <&wsamacro>; <<
2619 clock-names = "iface" <<
2620 label = "WSA"; <<
2621 <<
2622 pinctrl-0 = <&wsa_swr <<
2623 pinctrl-names = "defa <<
2624 <<
2625 qcom,din-ports = <2>; <<
2626 qcom,dout-ports = <6> <<
2627 <<
2628 qcom,ports-sinterval- <<
2629 qcom,ports-offset1 = <<
2630 qcom,ports-offset2 = <<
2631 qcom,ports-hstart = <<
2632 qcom,ports-hstop = <<
2633 qcom,ports-word-lengt <<
2634 qcom,ports-block-pack <<
2635 qcom,ports-block-grou <<
2636 qcom,ports-lane-contr <<
2637 <<
2638 #address-cells = <2>; <<
2639 #size-cells = <0>; <<
2640 #sound-dai-cells = <1 <<
2641 status = "disabled"; <<
2642 }; <<
2643 <<
2644 swr2: soundwire@33b0000 { <<
2645 compatible = "qcom,so <<
2646 reg = <0 0x033b0000 0 <<
2647 interrupts = <GIC_SPI <<
2648 <GIC_SPI <<
2649 interrupt-names = "co <<
2650 <<
2651 clocks = <&txmacro>; <<
2652 clock-names = "iface" <<
2653 label = "TX"; <<
2654 <<
2655 pinctrl-0 = <&tx_swr_ <<
2656 pinctrl-names = "defa <<
2657 <<
2658 qcom,din-ports = <4>; <<
2659 qcom,dout-ports = <0> <<
2660 qcom,ports-sinterval- <<
2661 qcom,ports-offset1 = <<
2662 qcom,ports-offset2 = <<
2663 qcom,ports-hstart = <<
2664 qcom,ports-hstop = <<
2665 qcom,ports-word-lengt <<
2666 qcom,ports-block-pack <<
2667 qcom,ports-block-grou <<
2668 qcom,ports-lane-contr <<
2669 <<
2670 #address-cells = <2>; <<
2671 #size-cells = <0>; <<
2672 #sound-dai-cells = <1 <<
2673 status = "disabled"; <<
2674 }; <<
2675 <<
2676 vamacro: codec@33f0000 { <<
2677 compatible = "qcom,sm <<
2678 reg = <0 0x033f0000 0 <<
2679 clocks = <&q6prmcc LP <<
2680 <&q6prmcc LP <<
2681 <&q6prmcc LP <<
2682 <&q6prmcc LP <<
2683 clock-names = "mclk", <<
2684 <<
2685 #clock-cells = <0>; <<
2686 clock-output-names = <<
2687 #sound-dai-cells = <1 <<
2688 status = "disabled"; <<
2689 }; <<
2690 <<
2691 remoteproc_adsp: remoteproc@3 2093 remoteproc_adsp: remoteproc@30000000 {
2692 compatible = "qcom,sm 2094 compatible = "qcom,sm8450-adsp-pas";
2693 reg = <0 0x30000000 0 !! 2095 reg = <0 0x030000000 0 0x100>;
2694 2096
2695 interrupts-extended = 2097 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
2696 2098 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
2697 2099 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
2698 2100 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
2699 2101 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
2700 interrupt-names = "wd 2102 interrupt-names = "wdog", "fatal", "ready",
2701 "ha 2103 "handover", "stop-ack";
2702 2104
2703 clocks = <&rpmhcc RPM 2105 clocks = <&rpmhcc RPMH_CXO_CLK>;
2704 clock-names = "xo"; 2106 clock-names = "xo";
2705 2107
2706 power-domains = <&rpm !! 2108 power-domains = <&rpmhpd SM8450_LCX>,
2707 <&rpm !! 2109 <&rpmhpd SM8450_LMX>;
2708 power-domain-names = 2110 power-domain-names = "lcx", "lmx";
2709 2111
2710 memory-region = <&ads 2112 memory-region = <&adsp_mem>;
2711 2113
2712 qcom,qmp = <&aoss_qmp 2114 qcom,qmp = <&aoss_qmp>;
2713 2115
2714 qcom,smem-states = <& 2116 qcom,smem-states = <&smp2p_adsp_out 0>;
2715 qcom,smem-state-names 2117 qcom,smem-state-names = "stop";
2716 2118
2717 status = "disabled"; 2119 status = "disabled";
2718 2120
2719 remoteproc_adsp_glink 2121 remoteproc_adsp_glink: glink-edge {
2720 interrupts-ex 2122 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
2721 2123 IPCC_MPROC_SIGNAL_GLINK_QMP
2722 2124 IRQ_TYPE_EDGE_RISING>;
2723 mboxes = <&ip 2125 mboxes = <&ipcc IPCC_CLIENT_LPASS
2724 2126 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2725 2127
2726 label = "lpas 2128 label = "lpass";
2727 qcom,remote-p 2129 qcom,remote-pid = <2>;
2728 2130
2729 gpr { <<
2730 compa <<
2731 qcom, <<
2732 qcom, <<
2733 qcom, <<
2734 #addr <<
2735 #size <<
2736 <<
2737 q6apm <<
2738 <<
2739 <<
2740 <<
2741 <<
2742 <<
2743 <<
2744 <<
2745 <<
2746 <<
2747 <<
2748 <<
2749 <<
2750 <<
2751 <<
2752 <<
2753 }; <<
2754 <<
2755 q6prm <<
2756 <<
2757 <<
2758 <<
2759 <<
2760 <<
2761 <<
2762 <<
2763 <<
2764 <<
2765 }; <<
2766 }; <<
2767 <<
2768 fastrpc { 2131 fastrpc {
2769 compa 2132 compatible = "qcom,fastrpc";
2770 qcom, 2133 qcom,glink-channels = "fastrpcglink-apps-dsp";
2771 label 2134 label = "adsp";
2772 qcom, <<
2773 #addr 2135 #address-cells = <1>;
2774 #size 2136 #size-cells = <0>;
2775 2137
2776 compu 2138 compute-cb@3 {
2777 2139 compatible = "qcom,fastrpc-compute-cb";
2778 2140 reg = <3>;
2779 2141 iommus = <&apps_smmu 0x1803 0x0>;
2780 }; 2142 };
2781 2143
2782 compu 2144 compute-cb@4 {
2783 2145 compatible = "qcom,fastrpc-compute-cb";
2784 2146 reg = <4>;
2785 2147 iommus = <&apps_smmu 0x1804 0x0>;
2786 }; 2148 };
2787 2149
2788 compu 2150 compute-cb@5 {
2789 2151 compatible = "qcom,fastrpc-compute-cb";
2790 2152 reg = <5>;
2791 2153 iommus = <&apps_smmu 0x1805 0x0>;
2792 }; 2154 };
2793 }; 2155 };
2794 }; 2156 };
2795 }; 2157 };
2796 2158
2797 remoteproc_cdsp: remoteproc@3 2159 remoteproc_cdsp: remoteproc@32300000 {
2798 compatible = "qcom,sm 2160 compatible = "qcom,sm8450-cdsp-pas";
2799 reg = <0 0x32300000 0 !! 2161 reg = <0 0x032300000 0 0x1400000>;
2800 2162
2801 interrupts-extended = 2163 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
2802 2164 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
2803 2165 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
2804 2166 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
2805 2167 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
2806 interrupt-names = "wd 2168 interrupt-names = "wdog", "fatal", "ready",
2807 "ha 2169 "handover", "stop-ack";
2808 2170
2809 clocks = <&rpmhcc RPM 2171 clocks = <&rpmhcc RPMH_CXO_CLK>;
2810 clock-names = "xo"; 2172 clock-names = "xo";
2811 2173
2812 power-domains = <&rpm !! 2174 power-domains = <&rpmhpd SM8450_CX>,
2813 <&rpm !! 2175 <&rpmhpd SM8450_MXC>;
2814 power-domain-names = 2176 power-domain-names = "cx", "mxc";
2815 2177
2816 memory-region = <&cds 2178 memory-region = <&cdsp_mem>;
2817 2179
2818 qcom,qmp = <&aoss_qmp 2180 qcom,qmp = <&aoss_qmp>;
2819 2181
2820 qcom,smem-states = <& 2182 qcom,smem-states = <&smp2p_cdsp_out 0>;
2821 qcom,smem-state-names 2183 qcom,smem-state-names = "stop";
2822 2184
2823 status = "disabled"; 2185 status = "disabled";
2824 2186
2825 glink-edge { 2187 glink-edge {
2826 interrupts-ex 2188 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
2827 2189 IPCC_MPROC_SIGNAL_GLINK_QMP
2828 2190 IRQ_TYPE_EDGE_RISING>;
2829 mboxes = <&ip 2191 mboxes = <&ipcc IPCC_CLIENT_CDSP
2830 2192 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2831 2193
2832 label = "cdsp 2194 label = "cdsp";
2833 qcom,remote-p 2195 qcom,remote-pid = <5>;
2834 2196
2835 fastrpc { 2197 fastrpc {
2836 compa 2198 compatible = "qcom,fastrpc";
2837 qcom, 2199 qcom,glink-channels = "fastrpcglink-apps-dsp";
2838 label 2200 label = "cdsp";
2839 qcom, <<
2840 #addr 2201 #address-cells = <1>;
2841 #size 2202 #size-cells = <0>;
2842 2203
2843 compu 2204 compute-cb@1 {
2844 2205 compatible = "qcom,fastrpc-compute-cb";
2845 2206 reg = <1>;
2846 2207 iommus = <&apps_smmu 0x2161 0x0400>,
2847 2208 <&apps_smmu 0x1021 0x1420>;
2848 }; 2209 };
2849 2210
2850 compu 2211 compute-cb@2 {
2851 2212 compatible = "qcom,fastrpc-compute-cb";
2852 2213 reg = <2>;
2853 2214 iommus = <&apps_smmu 0x2162 0x0400>,
2854 2215 <&apps_smmu 0x1022 0x1420>;
2855 }; 2216 };
2856 2217
2857 compu 2218 compute-cb@3 {
2858 2219 compatible = "qcom,fastrpc-compute-cb";
2859 2220 reg = <3>;
2860 2221 iommus = <&apps_smmu 0x2163 0x0400>,
2861 2222 <&apps_smmu 0x1023 0x1420>;
2862 }; 2223 };
2863 2224
2864 compu 2225 compute-cb@4 {
2865 2226 compatible = "qcom,fastrpc-compute-cb";
2866 2227 reg = <4>;
2867 2228 iommus = <&apps_smmu 0x2164 0x0400>,
2868 2229 <&apps_smmu 0x1024 0x1420>;
2869 }; 2230 };
2870 2231
2871 compu 2232 compute-cb@5 {
2872 2233 compatible = "qcom,fastrpc-compute-cb";
2873 2234 reg = <5>;
2874 2235 iommus = <&apps_smmu 0x2165 0x0400>,
2875 2236 <&apps_smmu 0x1025 0x1420>;
2876 }; 2237 };
2877 2238
2878 compu 2239 compute-cb@6 {
2879 2240 compatible = "qcom,fastrpc-compute-cb";
2880 2241 reg = <6>;
2881 2242 iommus = <&apps_smmu 0x2166 0x0400>,
2882 2243 <&apps_smmu 0x1026 0x1420>;
2883 }; 2244 };
2884 2245
2885 compu 2246 compute-cb@7 {
2886 2247 compatible = "qcom,fastrpc-compute-cb";
2887 2248 reg = <7>;
2888 2249 iommus = <&apps_smmu 0x2167 0x0400>,
2889 2250 <&apps_smmu 0x1027 0x1420>;
2890 }; 2251 };
2891 2252
2892 compu 2253 compute-cb@8 {
2893 2254 compatible = "qcom,fastrpc-compute-cb";
2894 2255 reg = <8>;
2895 2256 iommus = <&apps_smmu 0x2168 0x0400>,
2896 2257 <&apps_smmu 0x1028 0x1420>;
2897 }; 2258 };
2898 2259
2899 /* no 2260 /* note: secure cb9 in downstream */
2900 }; 2261 };
2901 }; 2262 };
2902 }; 2263 };
2903 2264
2904 remoteproc_mpss: remoteproc@4 2265 remoteproc_mpss: remoteproc@4080000 {
2905 compatible = "qcom,sm 2266 compatible = "qcom,sm8450-mpss-pas";
2906 reg = <0x0 0x04080000 2267 reg = <0x0 0x04080000 0x0 0x4040>;
2907 2268
2908 interrupts-extended = 2269 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
2909 2270 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
2910 2271 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
2911 2272 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
2912 2273 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>,
2913 2274 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>;
2914 interrupt-names = "wd 2275 interrupt-names = "wdog", "fatal", "ready", "handover",
2915 "st 2276 "stop-ack", "shutdown-ack";
2916 2277
2917 clocks = <&rpmhcc RPM 2278 clocks = <&rpmhcc RPMH_CXO_CLK>;
2918 clock-names = "xo"; 2279 clock-names = "xo";
2919 2280
2920 power-domains = <&rpm !! 2281 power-domains = <&rpmhpd 0>,
2921 <&rpm !! 2282 <&rpmhpd 12>;
2922 power-domain-names = 2283 power-domain-names = "cx", "mss";
2923 2284
2924 memory-region = <&mps 2285 memory-region = <&mpss_mem>;
2925 2286
2926 qcom,qmp = <&aoss_qmp 2287 qcom,qmp = <&aoss_qmp>;
2927 2288
2928 qcom,smem-states = <& 2289 qcom,smem-states = <&smp2p_modem_out 0>;
2929 qcom,smem-state-names 2290 qcom,smem-state-names = "stop";
2930 2291
2931 status = "disabled"; 2292 status = "disabled";
2932 2293
2933 glink-edge { 2294 glink-edge {
2934 interrupts-ex 2295 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
2935 2296 IPCC_MPROC_SIGNAL_GLINK_QMP
2936 2297 IRQ_TYPE_EDGE_RISING>;
2937 mboxes = <&ip 2298 mboxes = <&ipcc IPCC_CLIENT_MPSS
2938 2299 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2939 label = "mode 2300 label = "modem";
2940 qcom,remote-p 2301 qcom,remote-pid = <1>;
2941 }; 2302 };
2942 }; 2303 };
2943 2304
2944 videocc: clock-controller@aaf <<
2945 compatible = "qcom,sm <<
2946 reg = <0 0x0aaf0000 0 <<
2947 clocks = <&rpmhcc RPM <<
2948 <&gcc GCC_VI <<
2949 power-domains = <&rpm <<
2950 required-opps = <&rpm <<
2951 #clock-cells = <1>; <<
2952 #reset-cells = <1>; <<
2953 #power-domain-cells = <<
2954 }; <<
2955 <<
2956 cci0: cci@ac15000 { <<
2957 compatible = "qcom,sm <<
2958 reg = <0 0x0ac15000 0 <<
2959 interrupts = <GIC_SPI <<
2960 power-domains = <&cam <<
2961 <<
2962 clocks = <&camcc CAM_ <<
2963 <&camcc CAM_ <<
2964 <&camcc CAM_ <<
2965 <&camcc CAM_ <<
2966 <&camcc CAM_ <<
2967 clock-names = "camnoc <<
2968 "slow_a <<
2969 "cpas_a <<
2970 "cci", <<
2971 "cci_sr <<
2972 pinctrl-0 = <&cci0_de <<
2973 pinctrl-1 = <&cci0_sl <<
2974 pinctrl-names = "defa <<
2975 <<
2976 status = "disabled"; <<
2977 #address-cells = <1>; <<
2978 #size-cells = <0>; <<
2979 <<
2980 cci0_i2c0: i2c-bus@0 <<
2981 reg = <0>; <<
2982 clock-frequen <<
2983 #address-cell <<
2984 #size-cells = <<
2985 }; <<
2986 <<
2987 cci0_i2c1: i2c-bus@1 <<
2988 reg = <1>; <<
2989 clock-frequen <<
2990 #address-cell <<
2991 #size-cells = <<
2992 }; <<
2993 }; <<
2994 <<
2995 cci1: cci@ac16000 { <<
2996 compatible = "qcom,sm <<
2997 reg = <0 0x0ac16000 0 <<
2998 interrupts = <GIC_SPI <<
2999 power-domains = <&cam <<
3000 <<
3001 clocks = <&camcc CAM_ <<
3002 <&camcc CAM_ <<
3003 <&camcc CAM_ <<
3004 <&camcc CAM_ <<
3005 <&camcc CAM_ <<
3006 clock-names = "camnoc <<
3007 "slow_a <<
3008 "cpas_a <<
3009 "cci", <<
3010 "cci_sr <<
3011 pinctrl-0 = <&cci2_de <<
3012 pinctrl-1 = <&cci2_sl <<
3013 pinctrl-names = "defa <<
3014 <<
3015 status = "disabled"; <<
3016 #address-cells = <1>; <<
3017 #size-cells = <0>; <<
3018 <<
3019 cci1_i2c0: i2c-bus@0 <<
3020 reg = <0>; <<
3021 clock-frequen <<
3022 #address-cell <<
3023 #size-cells = <<
3024 }; <<
3025 <<
3026 cci1_i2c1: i2c-bus@1 <<
3027 reg = <1>; <<
3028 clock-frequen <<
3029 #address-cell <<
3030 #size-cells = <<
3031 }; <<
3032 }; <<
3033 <<
3034 camcc: clock-controller@ade00 2305 camcc: clock-controller@ade0000 {
3035 compatible = "qcom,sm 2306 compatible = "qcom,sm8450-camcc";
3036 reg = <0 0x0ade0000 0 2307 reg = <0 0x0ade0000 0 0x20000>;
3037 clocks = <&gcc GCC_CA 2308 clocks = <&gcc GCC_CAMERA_AHB_CLK>,
3038 <&rpmhcc RPM 2309 <&rpmhcc RPMH_CXO_CLK>,
3039 <&rpmhcc RPM 2310 <&rpmhcc RPMH_CXO_CLK_A>,
3040 <&sleep_clk> 2311 <&sleep_clk>;
3041 power-domains = <&rpm !! 2312 power-domains = <&rpmhpd SM8450_MMCX>;
3042 required-opps = <&rpm <<
3043 #clock-cells = <1>; <<
3044 #reset-cells = <1>; <<
3045 #power-domain-cells = <<
3046 status = "disabled"; <<
3047 }; <<
3048 <<
3049 mdss: display-subsystem@ae000 <<
3050 compatible = "qcom,sm <<
3051 reg = <0 0x0ae00000 0 <<
3052 reg-names = "mdss"; <<
3053 <<
3054 /* same path used twi <<
3055 interconnects = <&mms <<
3056 <&mms <<
3057 <&gem <<
3058 &con <<
3059 interconnect-names = <<
3060 <<
3061 <<
3062 <<
3063 resets = <&dispcc DIS <<
3064 <<
3065 power-domains = <&dis <<
3066 <<
3067 clocks = <&dispcc DIS <<
3068 <&gcc GCC_DI <<
3069 <&gcc GCC_DI <<
3070 <&dispcc DIS <<
3071 <<
3072 interrupts = <GIC_SPI <<
3073 interrupt-controller; <<
3074 #interrupt-cells = <1 <<
3075 <<
3076 iommus = <&apps_smmu <<
3077 <<
3078 #address-cells = <2>; <<
3079 #size-cells = <2>; <<
3080 ranges; <<
3081 <<
3082 status = "disabled"; <<
3083 <<
3084 mdss_mdp: display-con <<
3085 compatible = <<
3086 reg = <0 0x0a <<
3087 <0 0x0a <<
3088 reg-names = " <<
3089 <<
3090 clocks = <&gc <<
3091 <&gcc <<
3092 <&dis <<
3093 <&dis <<
3094 <&dis <<
3095 <&dis <<
3096 clock-names = <<
3097 <<
3098 <<
3099 <<
3100 <<
3101 <<
3102 <<
3103 assigned-cloc <<
3104 assigned-cloc <<
3105 <<
3106 operating-poi <<
3107 power-domains <<
3108 <<
3109 interrupt-par <<
3110 interrupts = <<
3111 <<
3112 ports { <<
3113 #addr <<
3114 #size <<
3115 <<
3116 port@ <<
3117 <<
3118 <<
3119 <<
3120 <<
3121 }; <<
3122 <<
3123 port@ <<
3124 <<
3125 <<
3126 <<
3127 <<
3128 }; <<
3129 <<
3130 port@ <<
3131 <<
3132 <<
3133 <<
3134 <<
3135 }; <<
3136 }; <<
3137 <<
3138 mdp_opp_table <<
3139 compa <<
3140 <<
3141 opp-1 <<
3142 <<
3143 <<
3144 }; <<
3145 <<
3146 opp-2 <<
3147 <<
3148 <<
3149 }; <<
3150 <<
3151 opp-3 <<
3152 <<
3153 <<
3154 }; <<
3155 <<
3156 opp-3 <<
3157 <<
3158 <<
3159 }; <<
3160 <<
3161 opp-5 <<
3162 <<
3163 <<
3164 }; <<
3165 }; <<
3166 }; <<
3167 <<
3168 mdss_dp0: displayport <<
3169 compatible = <<
3170 reg = <0 0xae <<
3171 <0 0xae <<
3172 <0 0xae <<
3173 <0 0xae <<
3174 <0 0xae <<
3175 interrupt-par <<
3176 interrupts = <<
3177 clocks = <&di <<
3178 <&di <<
3179 <&di <<
3180 <&di <<
3181 <&di <<
3182 clock-names = <<
3183 <<
3184 <<
3185 <<
3186 <<
3187 <<
3188 assigned-cloc <<
3189 <<
3190 assigned-cloc <<
3191 <<
3192 <<
3193 phys = <&usb_ <<
3194 phy-names = " <<
3195 <<
3196 #sound-dai-ce <<
3197 <<
3198 operating-poi <<
3199 power-domains <<
3200 <<
3201 status = "dis <<
3202 <<
3203 ports { <<
3204 #addr <<
3205 #size <<
3206 <<
3207 port@ <<
3208 <<
3209 <<
3210 <<
3211 <<
3212 }; <<
3213 <<
3214 port@ <<
3215 <<
3216 <<
3217 <<
3218 <<
3219 <<
3220 }; <<
3221 }; <<
3222 <<
3223 dp_opp_table: <<
3224 compa <<
3225 <<
3226 opp-1 <<
3227 <<
3228 <<
3229 }; <<
3230 <<
3231 opp-2 <<
3232 <<
3233 <<
3234 }; <<
3235 <<
3236 opp-5 <<
3237 <<
3238 <<
3239 }; <<
3240 <<
3241 opp-8 <<
3242 <<
3243 <<
3244 }; <<
3245 }; <<
3246 }; <<
3247 <<
3248 mdss_dsi0: dsi@ae9400 <<
3249 compatible = <<
3250 reg = <0 0x0a <<
3251 reg-names = " <<
3252 <<
3253 interrupt-par <<
3254 interrupts = <<
3255 <<
3256 clocks = <&di <<
3257 <&di <<
3258 <&di <<
3259 <&di <<
3260 <&di <<
3261 <&gcc <<
3262 clock-names = <<
3263 <<
3264 <<
3265 <<
3266 <<
3267 <<
3268 <<
3269 assigned-cloc <<
3270 assigned-cloc <<
3271 <<
3272 operating-poi <<
3273 power-domains <<
3274 <<
3275 phys = <&mdss <<
3276 phy-names = " <<
3277 <<
3278 #address-cell <<
3279 #size-cells = <<
3280 <<
3281 status = "dis <<
3282 <<
3283 ports { <<
3284 #addr <<
3285 #size <<
3286 <<
3287 port@ <<
3288 <<
3289 <<
3290 <<
3291 <<
3292 }; <<
3293 <<
3294 port@ <<
3295 <<
3296 <<
3297 <<
3298 }; <<
3299 }; <<
3300 <<
3301 mdss_dsi_opp_ <<
3302 compa <<
3303 <<
3304 opp-1 <<
3305 <<
3306 <<
3307 }; <<
3308 <<
3309 opp-3 <<
3310 <<
3311 <<
3312 }; <<
3313 <<
3314 opp-3 <<
3315 <<
3316 <<
3317 }; <<
3318 }; <<
3319 }; <<
3320 <<
3321 mdss_dsi0_phy: phy@ae <<
3322 compatible = <<
3323 reg = <0 0x0a <<
3324 <0 0x0a <<
3325 <0 0x0a <<
3326 reg-names = " <<
3327 " <<
3328 " <<
3329 <<
3330 #clock-cells <<
3331 #phy-cells = <<
3332 <<
3333 clocks = <&di <<
3334 <&rp <<
3335 clock-names = <<
3336 <<
3337 status = "dis <<
3338 }; <<
3339 <<
3340 mdss_dsi1: dsi@ae9600 <<
3341 compatible = <<
3342 reg = <0 0x0a <<
3343 reg-names = " <<
3344 <<
3345 interrupt-par <<
3346 interrupts = <<
3347 <<
3348 clocks = <&di <<
3349 <&di <<
3350 <&di <<
3351 <&di <<
3352 <&di <<
3353 <&gc <<
3354 clock-names = <<
3355 <<
3356 <<
3357 <<
3358 <<
3359 <<
3360 <<
3361 assigned-cloc <<
3362 assigned-cloc <<
3363 <<
3364 operating-poi <<
3365 power-domains <<
3366 <<
3367 phys = <&mdss <<
3368 phy-names = " <<
3369 <<
3370 #address-cell <<
3371 #size-cells = <<
3372 <<
3373 status = "dis <<
3374 <<
3375 ports { <<
3376 #addr <<
3377 #size <<
3378 <<
3379 port@ <<
3380 <<
3381 <<
3382 <<
3383 <<
3384 }; <<
3385 <<
3386 port@ <<
3387 <<
3388 <<
3389 <<
3390 }; <<
3391 }; <<
3392 }; <<
3393 <<
3394 mdss_dsi1_phy: phy@ae <<
3395 compatible = <<
3396 reg = <0 0x0a <<
3397 <0 0x0a <<
3398 <0 0x0a <<
3399 reg-names = " <<
3400 " <<
3401 " <<
3402 <<
3403 #clock-cells <<
3404 #phy-cells = <<
3405 <<
3406 clocks = <&di <<
3407 <&rp <<
3408 clock-names = <<
3409 <<
3410 status = "dis <<
3411 }; <<
3412 }; <<
3413 <<
3414 dispcc: clock-controller@af00 <<
3415 compatible = "qcom,sm <<
3416 reg = <0 0x0af00000 0 <<
3417 clocks = <&rpmhcc RPM <<
3418 <&rpmhcc RPM <<
3419 <&gcc GCC_DI <<
3420 <&sleep_clk> <<
3421 <&mdss_dsi0_ <<
3422 <&mdss_dsi0_ <<
3423 <&mdss_dsi1_ <<
3424 <&mdss_dsi1_ <<
3425 <&usb_1_qmpp <<
3426 <&usb_1_qmpp <<
3427 <0>, /* dp1 <<
3428 <0>, <<
3429 <0>, /* dp2 <<
3430 <0>, <<
3431 <0>, /* dp3 <<
3432 <0>; <<
3433 power-domains = <&rpm <<
3434 required-opps = <&rpm 2313 required-opps = <&rpmhpd_opp_low_svs>;
3435 #clock-cells = <1>; 2314 #clock-cells = <1>;
3436 #reset-cells = <1>; 2315 #reset-cells = <1>;
3437 #power-domain-cells = 2316 #power-domain-cells = <1>;
3438 status = "disabled"; 2317 status = "disabled";
3439 }; 2318 };
3440 2319
3441 pdc: interrupt-controller@b22 2320 pdc: interrupt-controller@b220000 {
3442 compatible = "qcom,sm 2321 compatible = "qcom,sm8450-pdc", "qcom,pdc";
3443 reg = <0 0x0b220000 0 2322 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
3444 qcom,pdc-ranges = <0 2323 qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>,
3445 <94 2324 <94 609 31>, <125 63 1>, <126 716 12>;
3446 #interrupt-cells = <2 2325 #interrupt-cells = <2>;
3447 interrupt-parent = <& 2326 interrupt-parent = <&intc>;
3448 interrupt-controller; 2327 interrupt-controller;
3449 }; 2328 };
3450 2329
3451 tsens0: thermal-sensor@c26300 2330 tsens0: thermal-sensor@c263000 {
3452 compatible = "qcom,sm 2331 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2";
3453 reg = <0 0x0c263000 0 2332 reg = <0 0x0c263000 0 0x1000>, /* TM */
3454 <0 0x0c222000 0 2333 <0 0x0c222000 0 0x1000>; /* SROT */
3455 #qcom,sensors = <16>; 2334 #qcom,sensors = <16>;
3456 interrupts = <GIC_SPI 2335 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
3457 <GIC_SPI 2336 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
3458 interrupt-names = "up 2337 interrupt-names = "uplow", "critical";
3459 #thermal-sensor-cells 2338 #thermal-sensor-cells = <1>;
3460 }; 2339 };
3461 2340
3462 tsens1: thermal-sensor@c26500 2341 tsens1: thermal-sensor@c265000 {
3463 compatible = "qcom,sm 2342 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2";
3464 reg = <0 0x0c265000 0 2343 reg = <0 0x0c265000 0 0x1000>, /* TM */
3465 <0 0x0c223000 0 2344 <0 0x0c223000 0 0x1000>; /* SROT */
3466 #qcom,sensors = <16>; 2345 #qcom,sensors = <16>;
3467 interrupts = <GIC_SPI 2346 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
3468 <GIC_SPI 2347 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
3469 interrupt-names = "up 2348 interrupt-names = "uplow", "critical";
3470 #thermal-sensor-cells 2349 #thermal-sensor-cells = <1>;
3471 }; 2350 };
3472 2351
3473 aoss_qmp: power-management@c3 !! 2352 aoss_qmp: power-controller@c300000 {
3474 compatible = "qcom,sm 2353 compatible = "qcom,sm8450-aoss-qmp", "qcom,aoss-qmp";
3475 reg = <0 0x0c300000 0 2354 reg = <0 0x0c300000 0 0x400>;
3476 interrupts-extended = 2355 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
3477 2356 IRQ_TYPE_EDGE_RISING>;
3478 mboxes = <&ipcc IPCC_ 2357 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
3479 2358
3480 #clock-cells = <0>; 2359 #clock-cells = <0>;
3481 }; 2360 };
3482 2361
3483 sram@c3f0000 { <<
3484 compatible = "qcom,rp <<
3485 reg = <0 0x0c3f0000 0 <<
3486 }; <<
3487 <<
3488 spmi_bus: spmi@c400000 { <<
3489 compatible = "qcom,sp <<
3490 reg = <0 0x0c400000 0 <<
3491 <0 0x0c500000 0 <<
3492 <0 0x0c440000 0 <<
3493 <0 0x0c4c0000 0 <<
3494 <0 0x0c42d000 0 <<
3495 reg-names = "core", <<
3496 "chnls", <<
3497 "obsrvr", <<
3498 "intr", <<
3499 "cnfg"; <<
3500 interrupt-names = "pe <<
3501 interrupts-extended = <<
3502 qcom,ee = <0>; <<
3503 qcom,channel = <0>; <<
3504 interrupt-controller; <<
3505 #interrupt-cells = <4 <<
3506 #address-cells = <2>; <<
3507 #size-cells = <0>; <<
3508 }; <<
3509 <<
3510 ipcc: mailbox@ed18000 { 2362 ipcc: mailbox@ed18000 {
3511 compatible = "qcom,sm 2363 compatible = "qcom,sm8450-ipcc", "qcom,ipcc";
3512 reg = <0 0x0ed18000 0 2364 reg = <0 0x0ed18000 0 0x1000>;
3513 interrupts = <GIC_SPI 2365 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
3514 interrupt-controller; 2366 interrupt-controller;
3515 #interrupt-cells = <3 2367 #interrupt-cells = <3>;
3516 #mbox-cells = <2>; 2368 #mbox-cells = <2>;
3517 }; 2369 };
3518 2370
3519 tlmm: pinctrl@f100000 { 2371 tlmm: pinctrl@f100000 {
3520 compatible = "qcom,sm 2372 compatible = "qcom,sm8450-tlmm";
3521 reg = <0 0x0f100000 0 2373 reg = <0 0x0f100000 0 0x300000>;
3522 interrupts = <GIC_SPI 2374 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
3523 gpio-controller; 2375 gpio-controller;
3524 #gpio-cells = <2>; 2376 #gpio-cells = <2>;
3525 interrupt-controller; 2377 interrupt-controller;
3526 #interrupt-cells = <2 2378 #interrupt-cells = <2>;
3527 gpio-ranges = <&tlmm 2379 gpio-ranges = <&tlmm 0 0 211>;
3528 wakeup-parent = <&pdc 2380 wakeup-parent = <&pdc>;
3529 2381
3530 sdc2_default_state: s <<
3531 clk-pins { <<
3532 pins <<
3533 drive <<
3534 bias- <<
3535 }; <<
3536 <<
3537 cmd-pins { <<
3538 pins <<
3539 drive <<
3540 bias- <<
3541 }; <<
3542 <<
3543 data-pins { <<
3544 pins <<
3545 drive <<
3546 bias- <<
3547 }; <<
3548 }; <<
3549 <<
3550 sdc2_sleep_state: sdc <<
3551 clk-pins { <<
3552 pins <<
3553 drive <<
3554 bias- <<
3555 }; <<
3556 <<
3557 cmd-pins { <<
3558 pins <<
3559 drive <<
3560 bias- <<
3561 }; <<
3562 <<
3563 data-pins { <<
3564 pins <<
3565 drive <<
3566 bias- <<
3567 }; <<
3568 }; <<
3569 <<
3570 cci0_default: cci0-de <<
3571 /* SDA, SCL * <<
3572 pins = "gpio1 <<
3573 function = "c <<
3574 drive-strengt <<
3575 bias-pull-up; <<
3576 }; <<
3577 <<
3578 cci0_sleep: cci0-slee <<
3579 /* SDA, SCL * <<
3580 pins = "gpio1 <<
3581 function = "c <<
3582 drive-strengt <<
3583 bias-pull-dow <<
3584 }; <<
3585 <<
3586 cci1_default: cci1-de <<
3587 /* SDA, SCL * <<
3588 pins = "gpio1 <<
3589 function = "c <<
3590 drive-strengt <<
3591 bias-pull-up; <<
3592 }; <<
3593 <<
3594 cci1_sleep: cci1-slee <<
3595 /* SDA, SCL * <<
3596 pins = "gpio1 <<
3597 function = "c <<
3598 drive-strengt <<
3599 bias-pull-dow <<
3600 }; <<
3601 <<
3602 cci2_default: cci2-de <<
3603 /* SDA, SCL * <<
3604 pins = "gpio1 <<
3605 function = "c <<
3606 drive-strengt <<
3607 bias-pull-up; <<
3608 }; <<
3609 <<
3610 cci2_sleep: cci2-slee <<
3611 /* SDA, SCL * <<
3612 pins = "gpio1 <<
3613 function = "c <<
3614 drive-strengt <<
3615 bias-pull-dow <<
3616 }; <<
3617 <<
3618 cci3_default: cci3-de <<
3619 /* SDA, SCL * <<
3620 pins = "gpio2 <<
3621 function = "c <<
3622 drive-strengt <<
3623 bias-pull-up; <<
3624 }; <<
3625 <<
3626 cci3_sleep: cci3-slee <<
3627 /* SDA, SCL * <<
3628 pins = "gpio2 <<
3629 function = "c <<
3630 drive-strengt <<
3631 bias-pull-dow <<
3632 }; <<
3633 <<
3634 pcie0_default_state: 2382 pcie0_default_state: pcie0-default-state {
3635 perst-pins { !! 2383 perst {
3636 pins 2384 pins = "gpio94";
3637 funct 2385 function = "gpio";
3638 drive 2386 drive-strength = <2>;
3639 bias- 2387 bias-pull-down;
3640 }; 2388 };
3641 2389
3642 clkreq-pins { !! 2390 clkreq {
3643 pins 2391 pins = "gpio95";
3644 funct 2392 function = "pcie0_clkreqn";
3645 drive 2393 drive-strength = <2>;
3646 bias- 2394 bias-pull-up;
3647 }; 2395 };
3648 2396
3649 wake-pins { !! 2397 wake {
3650 pins 2398 pins = "gpio96";
3651 funct 2399 function = "gpio";
3652 drive 2400 drive-strength = <2>;
3653 bias- 2401 bias-pull-up;
3654 }; 2402 };
3655 }; 2403 };
3656 2404
3657 pcie1_default_state: 2405 pcie1_default_state: pcie1-default-state {
3658 perst-pins { !! 2406 perst {
3659 pins 2407 pins = "gpio97";
3660 funct 2408 function = "gpio";
3661 drive 2409 drive-strength = <2>;
3662 bias- 2410 bias-pull-down;
3663 }; 2411 };
3664 2412
3665 clkreq-pins { !! 2413 clkreq {
3666 pins 2414 pins = "gpio98";
3667 funct 2415 function = "pcie1_clkreqn";
3668 drive 2416 drive-strength = <2>;
3669 bias- 2417 bias-pull-up;
3670 }; 2418 };
3671 2419
3672 wake-pins { !! 2420 wake {
3673 pins 2421 pins = "gpio99";
3674 funct 2422 function = "gpio";
3675 drive 2423 drive-strength = <2>;
3676 bias- 2424 bias-pull-up;
3677 }; 2425 };
3678 }; 2426 };
3679 2427
3680 qup_i2c0_data_clk: qu !! 2428 qup_i2c0_data_clk: qup-i2c0-data-clk {
3681 pins = "gpio0 2429 pins = "gpio0", "gpio1";
3682 function = "q 2430 function = "qup0";
3683 }; 2431 };
3684 2432
3685 qup_i2c1_data_clk: qu !! 2433 qup_i2c1_data_clk: qup-i2c1-data-clk {
3686 pins = "gpio4 2434 pins = "gpio4", "gpio5";
3687 function = "q 2435 function = "qup1";
3688 }; 2436 };
3689 2437
3690 qup_i2c2_data_clk: qu !! 2438 qup_i2c2_data_clk: qup-i2c2-data-clk {
3691 pins = "gpio8 2439 pins = "gpio8", "gpio9";
3692 function = "q 2440 function = "qup2";
3693 }; 2441 };
3694 2442
3695 qup_i2c3_data_clk: qu !! 2443 qup_i2c3_data_clk: qup-i2c3-data-clk {
3696 pins = "gpio1 2444 pins = "gpio12", "gpio13";
3697 function = "q 2445 function = "qup3";
3698 }; 2446 };
3699 2447
3700 qup_i2c4_data_clk: qu !! 2448 qup_i2c4_data_clk: qup-i2c4-data-clk {
3701 pins = "gpio1 2449 pins = "gpio16", "gpio17";
3702 function = "q 2450 function = "qup4";
3703 }; 2451 };
3704 2452
3705 qup_i2c5_data_clk: qu !! 2453 qup_i2c5_data_clk: qup-i2c5-data-clk {
3706 pins = "gpio2 2454 pins = "gpio206", "gpio207";
3707 function = "q 2455 function = "qup5";
3708 }; 2456 };
3709 2457
3710 qup_i2c6_data_clk: qu !! 2458 qup_i2c6_data_clk: qup-i2c6-data-clk {
3711 pins = "gpio2 2459 pins = "gpio20", "gpio21";
3712 function = "q 2460 function = "qup6";
3713 }; 2461 };
3714 2462
3715 qup_i2c8_data_clk: qu !! 2463 qup_i2c8_data_clk: qup-i2c8-data-clk {
3716 pins = "gpio2 2464 pins = "gpio28", "gpio29";
3717 function = "q 2465 function = "qup8";
3718 }; 2466 };
3719 2467
3720 qup_i2c9_data_clk: qu !! 2468 qup_i2c9_data_clk: qup-i2c9-data-clk {
3721 pins = "gpio3 2469 pins = "gpio32", "gpio33";
3722 function = "q 2470 function = "qup9";
3723 }; 2471 };
3724 2472
3725 qup_i2c10_data_clk: q !! 2473 qup_i2c10_data_clk: qup-i2c10-data-clk {
3726 pins = "gpio3 2474 pins = "gpio36", "gpio37";
3727 function = "q 2475 function = "qup10";
3728 }; 2476 };
3729 2477
3730 qup_i2c11_data_clk: q !! 2478 qup_i2c11_data_clk: qup-i2c11-data-clk {
3731 pins = "gpio4 2479 pins = "gpio40", "gpio41";
3732 function = "q 2480 function = "qup11";
3733 }; 2481 };
3734 2482
3735 qup_i2c12_data_clk: q !! 2483 qup_i2c12_data_clk: qup-i2c12-data-clk {
3736 pins = "gpio4 2484 pins = "gpio44", "gpio45";
3737 function = "q 2485 function = "qup12";
3738 }; 2486 };
3739 2487
3740 qup_i2c13_data_clk: q !! 2488 qup_i2c13_data_clk: qup-i2c13-data-clk {
3741 pins = "gpio4 2489 pins = "gpio48", "gpio49";
3742 function = "q 2490 function = "qup13";
3743 drive-strengt 2491 drive-strength = <2>;
3744 bias-pull-up; 2492 bias-pull-up;
3745 }; 2493 };
3746 2494
3747 qup_i2c14_data_clk: q !! 2495 qup_i2c14_data_clk: qup-i2c14-data-clk {
3748 pins = "gpio5 2496 pins = "gpio52", "gpio53";
3749 function = "q 2497 function = "qup14";
3750 drive-strengt 2498 drive-strength = <2>;
3751 bias-pull-up; 2499 bias-pull-up;
3752 }; 2500 };
3753 2501
3754 qup_i2c15_data_clk: q !! 2502 qup_i2c15_data_clk: qup-i2c15-data-clk {
3755 pins = "gpio5 2503 pins = "gpio56", "gpio57";
3756 function = "q 2504 function = "qup15";
3757 }; 2505 };
3758 2506
3759 qup_i2c16_data_clk: q !! 2507 qup_i2c16_data_clk: qup-i2c16-data-clk {
3760 pins = "gpio6 2508 pins = "gpio60", "gpio61";
3761 function = "q 2509 function = "qup16";
3762 }; 2510 };
3763 2511
3764 qup_i2c17_data_clk: q !! 2512 qup_i2c17_data_clk: qup-i2c17-data-clk {
3765 pins = "gpio6 2513 pins = "gpio64", "gpio65";
3766 function = "q 2514 function = "qup17";
3767 }; 2515 };
3768 2516
3769 qup_i2c18_data_clk: q !! 2517 qup_i2c18_data_clk: qup-i2c18-data-clk {
3770 pins = "gpio6 2518 pins = "gpio68", "gpio69";
3771 function = "q 2519 function = "qup18";
3772 }; 2520 };
3773 2521
3774 qup_i2c19_data_clk: q !! 2522 qup_i2c19_data_clk: qup-i2c19-data-clk {
3775 pins = "gpio7 2523 pins = "gpio72", "gpio73";
3776 function = "q 2524 function = "qup19";
3777 }; 2525 };
3778 2526
3779 qup_i2c20_data_clk: q !! 2527 qup_i2c20_data_clk: qup-i2c20-data-clk {
3780 pins = "gpio7 2528 pins = "gpio76", "gpio77";
3781 function = "q 2529 function = "qup20";
3782 }; 2530 };
3783 2531
3784 qup_i2c21_data_clk: q !! 2532 qup_i2c21_data_clk: qup-i2c21-data-clk {
3785 pins = "gpio8 2533 pins = "gpio80", "gpio81";
3786 function = "q 2534 function = "qup21";
3787 }; 2535 };
3788 2536
3789 qup_spi0_cs: qup-spi0 !! 2537 qup_spi0_cs: qup-spi0-cs {
3790 pins = "gpio3 2538 pins = "gpio3";
3791 function = "q 2539 function = "qup0";
3792 }; 2540 };
3793 2541
3794 qup_spi0_data_clk: qu !! 2542 qup_spi0_data_clk: qup-spi0-data-clk {
3795 pins = "gpio0 2543 pins = "gpio0", "gpio1", "gpio2";
3796 function = "q 2544 function = "qup0";
3797 }; 2545 };
3798 2546
3799 qup_spi1_cs: qup-spi1 !! 2547 qup_spi1_cs: qup-spi1-cs {
3800 pins = "gpio7 2548 pins = "gpio7";
3801 function = "q 2549 function = "qup1";
3802 }; 2550 };
3803 2551
3804 qup_spi1_data_clk: qu !! 2552 qup_spi1_data_clk: qup-spi1-data-clk {
3805 pins = "gpio4 2553 pins = "gpio4", "gpio5", "gpio6";
3806 function = "q 2554 function = "qup1";
3807 }; 2555 };
3808 2556
3809 qup_spi2_cs: qup-spi2 !! 2557 qup_spi2_cs: qup-spi2-cs {
3810 pins = "gpio1 2558 pins = "gpio11";
3811 function = "q 2559 function = "qup2";
3812 }; 2560 };
3813 2561
3814 qup_spi2_data_clk: qu !! 2562 qup_spi2_data_clk: qup-spi2-data-clk {
3815 pins = "gpio8 2563 pins = "gpio8", "gpio9", "gpio10";
3816 function = "q 2564 function = "qup2";
3817 }; 2565 };
3818 2566
3819 qup_spi3_cs: qup-spi3 !! 2567 qup_spi3_cs: qup-spi3-cs {
3820 pins = "gpio1 2568 pins = "gpio15";
3821 function = "q 2569 function = "qup3";
3822 }; 2570 };
3823 2571
3824 qup_spi3_data_clk: qu !! 2572 qup_spi3_data_clk: qup-spi3-data-clk {
3825 pins = "gpio1 2573 pins = "gpio12", "gpio13", "gpio14";
3826 function = "q 2574 function = "qup3";
3827 }; 2575 };
3828 2576
3829 qup_spi4_cs: qup-spi4 !! 2577 qup_spi4_cs: qup-spi4-cs {
3830 pins = "gpio1 2578 pins = "gpio19";
3831 function = "q 2579 function = "qup4";
3832 drive-strengt 2580 drive-strength = <6>;
3833 bias-disable; 2581 bias-disable;
3834 }; 2582 };
3835 2583
3836 qup_spi4_data_clk: qu !! 2584 qup_spi4_data_clk: qup-spi4-data-clk {
3837 pins = "gpio1 2585 pins = "gpio16", "gpio17", "gpio18";
3838 function = "q 2586 function = "qup4";
3839 }; 2587 };
3840 2588
3841 qup_spi5_cs: qup-spi5 !! 2589 qup_spi5_cs: qup-spi5-cs {
3842 pins = "gpio8 2590 pins = "gpio85";
3843 function = "q 2591 function = "qup5";
3844 }; 2592 };
3845 2593
3846 qup_spi5_data_clk: qu !! 2594 qup_spi5_data_clk: qup-spi5-data-clk {
3847 pins = "gpio2 2595 pins = "gpio206", "gpio207", "gpio84";
3848 function = "q 2596 function = "qup5";
3849 }; 2597 };
3850 2598
3851 qup_spi6_cs: qup-spi6 !! 2599 qup_spi6_cs: qup-spi6-cs {
3852 pins = "gpio2 2600 pins = "gpio23";
3853 function = "q 2601 function = "qup6";
3854 }; 2602 };
3855 2603
3856 qup_spi6_data_clk: qu !! 2604 qup_spi6_data_clk: qup-spi6-data-clk {
3857 pins = "gpio2 2605 pins = "gpio20", "gpio21", "gpio22";
3858 function = "q 2606 function = "qup6";
3859 }; 2607 };
3860 2608
3861 qup_spi8_cs: qup-spi8 !! 2609 qup_spi8_cs: qup-spi8-cs {
3862 pins = "gpio3 2610 pins = "gpio31";
3863 function = "q 2611 function = "qup8";
3864 }; 2612 };
3865 2613
3866 qup_spi8_data_clk: qu !! 2614 qup_spi8_data_clk: qup-spi8-data-clk {
3867 pins = "gpio2 2615 pins = "gpio28", "gpio29", "gpio30";
3868 function = "q 2616 function = "qup8";
3869 }; 2617 };
3870 2618
3871 qup_spi9_cs: qup-spi9 !! 2619 qup_spi9_cs: qup-spi9-cs {
3872 pins = "gpio3 2620 pins = "gpio35";
3873 function = "q 2621 function = "qup9";
3874 }; 2622 };
3875 2623
3876 qup_spi9_data_clk: qu !! 2624 qup_spi9_data_clk: qup-spi9-data-clk {
3877 pins = "gpio3 2625 pins = "gpio32", "gpio33", "gpio34";
3878 function = "q 2626 function = "qup9";
3879 }; 2627 };
3880 2628
3881 qup_spi10_cs: qup-spi !! 2629 qup_spi10_cs: qup-spi10-cs {
3882 pins = "gpio3 2630 pins = "gpio39";
3883 function = "q 2631 function = "qup10";
3884 }; 2632 };
3885 2633
3886 qup_spi10_data_clk: q !! 2634 qup_spi10_data_clk: qup-spi10-data-clk {
3887 pins = "gpio3 2635 pins = "gpio36", "gpio37", "gpio38";
3888 function = "q 2636 function = "qup10";
3889 }; 2637 };
3890 2638
3891 qup_spi11_cs: qup-spi !! 2639 qup_spi11_cs: qup-spi11-cs {
3892 pins = "gpio4 2640 pins = "gpio43";
3893 function = "q 2641 function = "qup11";
3894 }; 2642 };
3895 2643
3896 qup_spi11_data_clk: q !! 2644 qup_spi11_data_clk: qup-spi11-data-clk {
3897 pins = "gpio4 2645 pins = "gpio40", "gpio41", "gpio42";
3898 function = "q 2646 function = "qup11";
3899 }; 2647 };
3900 2648
3901 qup_spi12_cs: qup-spi !! 2649 qup_spi12_cs: qup-spi12-cs {
3902 pins = "gpio4 2650 pins = "gpio47";
3903 function = "q 2651 function = "qup12";
3904 }; 2652 };
3905 2653
3906 qup_spi12_data_clk: q !! 2654 qup_spi12_data_clk: qup-spi12-data-clk {
3907 pins = "gpio4 2655 pins = "gpio44", "gpio45", "gpio46";
3908 function = "q 2656 function = "qup12";
3909 }; 2657 };
3910 2658
3911 qup_spi13_cs: qup-spi !! 2659 qup_spi13_cs: qup-spi13-cs {
3912 pins = "gpio5 2660 pins = "gpio51";
3913 function = "q 2661 function = "qup13";
3914 }; 2662 };
3915 2663
3916 qup_spi13_data_clk: q !! 2664 qup_spi13_data_clk: qup-spi13-data-clk {
3917 pins = "gpio4 2665 pins = "gpio48", "gpio49", "gpio50";
3918 function = "q 2666 function = "qup13";
3919 }; 2667 };
3920 2668
3921 qup_spi14_cs: qup-spi !! 2669 qup_spi14_cs: qup-spi14-cs {
3922 pins = "gpio5 2670 pins = "gpio55";
3923 function = "q 2671 function = "qup14";
3924 }; 2672 };
3925 2673
3926 qup_spi14_data_clk: q !! 2674 qup_spi14_data_clk: qup-spi14-data-clk {
3927 pins = "gpio5 2675 pins = "gpio52", "gpio53", "gpio54";
3928 function = "q 2676 function = "qup14";
3929 }; 2677 };
3930 2678
3931 qup_spi15_cs: qup-spi !! 2679 qup_spi15_cs: qup-spi15-cs {
3932 pins = "gpio5 2680 pins = "gpio59";
3933 function = "q 2681 function = "qup15";
3934 }; 2682 };
3935 2683
3936 qup_spi15_data_clk: q !! 2684 qup_spi15_data_clk: qup-spi15-data-clk {
3937 pins = "gpio5 2685 pins = "gpio56", "gpio57", "gpio58";
3938 function = "q 2686 function = "qup15";
3939 }; 2687 };
3940 2688
3941 qup_spi16_cs: qup-spi !! 2689 qup_spi16_cs: qup-spi16-cs {
3942 pins = "gpio6 2690 pins = "gpio63";
3943 function = "q 2691 function = "qup16";
3944 }; 2692 };
3945 2693
3946 qup_spi16_data_clk: q !! 2694 qup_spi16_data_clk: qup-spi16-data-clk {
3947 pins = "gpio6 2695 pins = "gpio60", "gpio61", "gpio62";
3948 function = "q 2696 function = "qup16";
3949 }; 2697 };
3950 2698
3951 qup_spi17_cs: qup-spi !! 2699 qup_spi17_cs: qup-spi17-cs {
3952 pins = "gpio6 2700 pins = "gpio67";
3953 function = "q 2701 function = "qup17";
3954 }; 2702 };
3955 2703
3956 qup_spi17_data_clk: q !! 2704 qup_spi17_data_clk: qup-spi17-data-clk {
3957 pins = "gpio6 2705 pins = "gpio64", "gpio65", "gpio66";
3958 function = "q 2706 function = "qup17";
3959 }; 2707 };
3960 2708
3961 qup_spi18_cs: qup-spi !! 2709 qup_spi18_cs: qup-spi18-cs {
3962 pins = "gpio7 2710 pins = "gpio71";
3963 function = "q 2711 function = "qup18";
3964 drive-strengt 2712 drive-strength = <6>;
3965 bias-disable; 2713 bias-disable;
3966 }; 2714 };
3967 2715
3968 qup_spi18_data_clk: q !! 2716 qup_spi18_data_clk: qup-spi18-data-clk {
3969 pins = "gpio6 2717 pins = "gpio68", "gpio69", "gpio70";
3970 function = "q 2718 function = "qup18";
3971 drive-strengt 2719 drive-strength = <6>;
3972 bias-disable; 2720 bias-disable;
3973 }; 2721 };
3974 2722
3975 qup_spi19_cs: qup-spi !! 2723 qup_spi19_cs: qup-spi19-cs {
3976 pins = "gpio7 2724 pins = "gpio75";
3977 function = "q 2725 function = "qup19";
3978 drive-strengt 2726 drive-strength = <6>;
3979 bias-disable; 2727 bias-disable;
3980 }; 2728 };
3981 2729
3982 qup_spi19_data_clk: q !! 2730 qup_spi19_data_clk: qup-spi19-data-clk {
3983 pins = "gpio7 2731 pins = "gpio72", "gpio73", "gpio74";
3984 function = "q 2732 function = "qup19";
3985 drive-strengt 2733 drive-strength = <6>;
3986 bias-disable; 2734 bias-disable;
3987 }; 2735 };
3988 2736
3989 qup_spi20_cs: qup-spi !! 2737 qup_spi20_cs: qup-spi20-cs {
3990 pins = "gpio7 2738 pins = "gpio79";
3991 function = "q 2739 function = "qup20";
3992 }; 2740 };
3993 2741
3994 qup_spi20_data_clk: q !! 2742 qup_spi20_data_clk: qup-spi20-data-clk {
3995 pins = "gpio7 2743 pins = "gpio76", "gpio77", "gpio78";
3996 function = "q 2744 function = "qup20";
3997 }; 2745 };
3998 2746
3999 qup_spi21_cs: qup-spi !! 2747 qup_spi21_cs: qup-spi21-cs {
4000 pins = "gpio8 2748 pins = "gpio83";
4001 function = "q 2749 function = "qup21";
4002 }; 2750 };
4003 2751
4004 qup_spi21_data_clk: q !! 2752 qup_spi21_data_clk: qup-spi21-data-clk {
4005 pins = "gpio8 2753 pins = "gpio80", "gpio81", "gpio82";
4006 function = "q 2754 function = "qup21";
4007 }; 2755 };
4008 2756
4009 qup_uart7_rx: qup-uar !! 2757 qup_uart7_rx: qup-uart7-rx {
4010 pins = "gpio2 2758 pins = "gpio26";
4011 function = "q 2759 function = "qup7";
4012 drive-strengt 2760 drive-strength = <2>;
4013 bias-disable; 2761 bias-disable;
4014 }; 2762 };
4015 2763
4016 qup_uart7_tx: qup-uar !! 2764 qup_uart7_tx: qup-uart7-tx {
4017 pins = "gpio2 2765 pins = "gpio27";
4018 function = "q 2766 function = "qup7";
4019 drive-strengt 2767 drive-strength = <2>;
4020 bias-disable; 2768 bias-disable;
4021 }; 2769 };
4022 2770
4023 qup_uart20_default: q !! 2771 qup_uart20_default: qup-uart20-default {
4024 pins = "gpio7 2772 pins = "gpio76", "gpio77", "gpio78", "gpio79";
4025 function = "q 2773 function = "qup20";
4026 }; 2774 };
4027 }; <<
4028 <<
4029 lpass_tlmm: pinctrl@3440000 { <<
4030 compatible = "qcom,sm <<
4031 reg = <0 0x03440000 0 <<
4032 <0 0x034d0000 0 <<
4033 gpio-controller; <<
4034 #gpio-cells = <2>; <<
4035 gpio-ranges = <&lpass <<
4036 <<
4037 clocks = <&q6prmcc LP <<
4038 <&q6prmcc LP <<
4039 clock-names = "core", <<
4040 <<
4041 tx_swr_active: tx-swr <<
4042 clk-pins { <<
4043 pins <<
4044 funct <<
4045 drive <<
4046 slew- <<
4047 bias- <<
4048 }; <<
4049 <<
4050 data-pins { <<
4051 pins <<
4052 funct <<
4053 drive <<
4054 slew- <<
4055 bias- <<
4056 }; <<
4057 }; <<
4058 <<
4059 rx_swr_active: rx-swr <<
4060 clk-pins { <<
4061 pins <<
4062 funct <<
4063 drive <<
4064 slew- <<
4065 bias- <<
4066 }; <<
4067 <<
4068 data-pins { <<
4069 pins <<
4070 funct <<
4071 drive <<
4072 slew- <<
4073 bias- <<
4074 }; <<
4075 }; <<
4076 <<
4077 dmic01_default: dmic0 <<
4078 clk-pins { <<
4079 pins <<
4080 funct <<
4081 drive <<
4082 outpu <<
4083 }; <<
4084 <<
4085 data-pins { <<
4086 pins <<
4087 funct <<
4088 drive <<
4089 }; <<
4090 }; <<
4091 <<
4092 dmic23_default: dmic2 <<
4093 clk-pins { <<
4094 pins <<
4095 funct <<
4096 drive <<
4097 outpu <<
4098 }; <<
4099 <<
4100 data-pins { <<
4101 pins <<
4102 funct <<
4103 drive <<
4104 }; <<
4105 }; <<
4106 <<
4107 wsa_swr_active: wsa-s <<
4108 clk-pins { <<
4109 pins <<
4110 funct <<
4111 drive <<
4112 slew- <<
4113 bias- <<
4114 }; <<
4115 <<
4116 data-pins { <<
4117 pins <<
4118 funct <<
4119 drive <<
4120 slew- <<
4121 bias- <<
4122 }; <<
4123 }; <<
4124 <<
4125 wsa2_swr_active: wsa2 <<
4126 clk-pins { <<
4127 pins <<
4128 funct <<
4129 drive <<
4130 slew- <<
4131 bias- <<
4132 }; <<
4133 2775
4134 data-pins { <<
4135 pins <<
4136 funct <<
4137 drive <<
4138 slew- <<
4139 bias- <<
4140 }; <<
4141 }; <<
4142 }; <<
4143 <<
4144 sram@146aa000 { <<
4145 compatible = "qcom,sm <<
4146 reg = <0 0x146aa000 0 <<
4147 ranges = <0 0 0x146aa <<
4148 <<
4149 #address-cells = <1>; <<
4150 #size-cells = <1>; <<
4151 <<
4152 pil-reloc@94c { <<
4153 compatible = <<
4154 reg = <0x94c <<
4155 }; <<
4156 }; 2776 };
4157 2777
4158 apps_smmu: iommu@15000000 { 2778 apps_smmu: iommu@15000000 {
4159 compatible = "qcom,sm 2779 compatible = "qcom,sm8450-smmu-500", "arm,mmu-500";
4160 reg = <0 0x15000000 0 2780 reg = <0 0x15000000 0 0x100000>;
4161 #iommu-cells = <2>; 2781 #iommu-cells = <2>;
4162 #global-interrupts = 2782 #global-interrupts = <1>;
4163 interrupts = <GIC_SPI !! 2783 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
4164 <GIC_SPI !! 2784 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
4165 <GIC_SPI !! 2785 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
4166 <GIC_SPI !! 2786 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
4167 <GIC_SPI !! 2787 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
4168 <GIC_SPI !! 2788 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
4169 <GIC_SPI !! 2789 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
4170 <GIC_SPI !! 2790 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
4171 <GIC_SPI !! 2791 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
4172 <GIC_SPI !! 2792 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
4173 <GIC_SPI !! 2793 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
4174 <GIC_SPI !! 2794 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
4175 <GIC_SPI !! 2795 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
4176 <GIC_SPI !! 2796 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
4177 <GIC_SPI !! 2797 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
4178 <GIC_SPI !! 2798 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
4179 <GIC_SPI !! 2799 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
4180 <GIC_SPI !! 2800 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
4181 <GIC_SPI !! 2801 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
4182 <GIC_SPI !! 2802 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
4183 <GIC_SPI !! 2803 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
4184 <GIC_SPI !! 2804 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
4185 <GIC_SPI !! 2805 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
4186 <GIC_SPI !! 2806 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
4187 <GIC_SPI !! 2807 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
4188 <GIC_SPI !! 2808 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
4189 <GIC_SPI !! 2809 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
4190 <GIC_SPI !! 2810 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
4191 <GIC_SPI !! 2811 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
4192 <GIC_SPI !! 2812 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
4193 <GIC_SPI !! 2813 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
4194 <GIC_SPI !! 2814 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
4195 <GIC_SPI !! 2815 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
4196 <GIC_SPI !! 2816 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
4197 <GIC_SPI !! 2817 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
4198 <GIC_SPI !! 2818 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
4199 <GIC_SPI !! 2819 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
4200 <GIC_SPI !! 2820 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
4201 <GIC_SPI !! 2821 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
4202 <GIC_SPI !! 2822 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
4203 <GIC_SPI !! 2823 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
4204 <GIC_SPI !! 2824 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
4205 <GIC_SPI !! 2825 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
4206 <GIC_SPI !! 2826 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
4207 <GIC_SPI !! 2827 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
4208 <GIC_SPI !! 2828 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
4209 <GIC_SPI !! 2829 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
4210 <GIC_SPI !! 2830 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
4211 <GIC_SPI !! 2831 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
4212 <GIC_SPI !! 2832 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
4213 <GIC_SPI !! 2833 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
4214 <GIC_SPI !! 2834 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
4215 <GIC_SPI !! 2835 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
4216 <GIC_SPI !! 2836 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
4217 <GIC_SPI !! 2837 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
4218 <GIC_SPI !! 2838 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
4219 <GIC_SPI !! 2839 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
4220 <GIC_SPI !! 2840 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
4221 <GIC_SPI !! 2841 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
4222 <GIC_SPI !! 2842 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
4223 <GIC_SPI !! 2843 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
4224 <GIC_SPI !! 2844 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
4225 <GIC_SPI !! 2845 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
4226 <GIC_SPI !! 2846 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
4227 <GIC_SPI !! 2847 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
4228 <GIC_SPI !! 2848 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
4229 <GIC_SPI !! 2849 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
4230 <GIC_SPI !! 2850 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
4231 <GIC_SPI !! 2851 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
4232 <GIC_SPI !! 2852 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
4233 <GIC_SPI !! 2853 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
4234 <GIC_SPI !! 2854 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
4235 <GIC_SPI !! 2855 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
4236 <GIC_SPI !! 2856 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
4237 <GIC_SPI !! 2857 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
4238 <GIC_SPI !! 2858 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
4239 <GIC_SPI !! 2859 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
4240 <GIC_SPI !! 2860 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
4241 <GIC_SPI !! 2861 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
4242 <GIC_SPI !! 2862 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
4243 <GIC_SPI !! 2863 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
4244 <GIC_SPI !! 2864 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
4245 <GIC_SPI !! 2865 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
4246 <GIC_SPI !! 2866 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
4247 <GIC_SPI !! 2867 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
4248 <GIC_SPI !! 2868 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
4249 <GIC_SPI !! 2869 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
4250 <GIC_SPI !! 2870 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
4251 <GIC_SPI !! 2871 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
4252 <GIC_SPI !! 2872 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
4253 <GIC_SPI !! 2873 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
4254 <GIC_SPI !! 2874 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
4255 <GIC_SPI !! 2875 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
4256 <GIC_SPI !! 2876 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
4257 <GIC_SPI !! 2877 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
4258 <GIC_SPI !! 2878 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
4259 <GIC_SPI !! 2879 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>;
4260 }; 2880 };
4261 2881
4262 intc: interrupt-controller@17 2882 intc: interrupt-controller@17100000 {
4263 compatible = "arm,gic 2883 compatible = "arm,gic-v3";
4264 #interrupt-cells = <3 2884 #interrupt-cells = <3>;
4265 interrupt-controller; 2885 interrupt-controller;
4266 #redistributor-region 2886 #redistributor-regions = <1>;
4267 redistributor-stride 2887 redistributor-stride = <0x0 0x40000>;
4268 reg = <0x0 0x17100000 2888 reg = <0x0 0x17100000 0x0 0x10000>, /* GICD */
4269 <0x0 0x17180000 2889 <0x0 0x17180000 0x0 0x200000>; /* GICR * 8 */
4270 interrupts = <GIC_PPI 2890 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
4271 #address-cells = <2>; 2891 #address-cells = <2>;
4272 #size-cells = <2>; 2892 #size-cells = <2>;
4273 ranges; 2893 ranges;
4274 2894
4275 gic_its: msi-controll 2895 gic_its: msi-controller@17140000 {
4276 compatible = 2896 compatible = "arm,gic-v3-its";
4277 reg = <0x0 0x 2897 reg = <0x0 0x17140000 0x0 0x20000>;
4278 msi-controlle 2898 msi-controller;
4279 #msi-cells = 2899 #msi-cells = <1>;
4280 }; 2900 };
4281 }; 2901 };
4282 2902
4283 timer@17420000 { 2903 timer@17420000 {
4284 compatible = "arm,arm 2904 compatible = "arm,armv7-timer-mem";
4285 #address-cells = <1>; 2905 #address-cells = <1>;
4286 #size-cells = <1>; 2906 #size-cells = <1>;
4287 ranges = <0 0 0 0x200 2907 ranges = <0 0 0 0x20000000>;
4288 reg = <0x0 0x17420000 2908 reg = <0x0 0x17420000 0x0 0x1000>;
4289 clock-frequency = <19 2909 clock-frequency = <19200000>;
4290 2910
4291 frame@17421000 { 2911 frame@17421000 {
4292 frame-number 2912 frame-number = <0>;
4293 interrupts = 2913 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
4294 2914 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
4295 reg = <0x1742 2915 reg = <0x17421000 0x1000>,
4296 <0x1742 2916 <0x17422000 0x1000>;
4297 }; 2917 };
4298 2918
4299 frame@17423000 { 2919 frame@17423000 {
4300 frame-number 2920 frame-number = <1>;
4301 interrupts = 2921 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
4302 reg = <0x1742 2922 reg = <0x17423000 0x1000>;
4303 status = "dis 2923 status = "disabled";
4304 }; 2924 };
4305 2925
4306 frame@17425000 { 2926 frame@17425000 {
4307 frame-number 2927 frame-number = <2>;
4308 interrupts = 2928 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
4309 reg = <0x1742 2929 reg = <0x17425000 0x1000>;
4310 status = "dis 2930 status = "disabled";
4311 }; 2931 };
4312 2932
4313 frame@17427000 { 2933 frame@17427000 {
4314 frame-number 2934 frame-number = <3>;
4315 interrupts = 2935 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
4316 reg = <0x1742 2936 reg = <0x17427000 0x1000>;
4317 status = "dis 2937 status = "disabled";
4318 }; 2938 };
4319 2939
4320 frame@17429000 { 2940 frame@17429000 {
4321 frame-number 2941 frame-number = <4>;
4322 interrupts = 2942 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
4323 reg = <0x1742 2943 reg = <0x17429000 0x1000>;
4324 status = "dis 2944 status = "disabled";
4325 }; 2945 };
4326 2946
4327 frame@1742b000 { 2947 frame@1742b000 {
4328 frame-number 2948 frame-number = <5>;
4329 interrupts = 2949 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
4330 reg = <0x1742 2950 reg = <0x1742b000 0x1000>;
4331 status = "dis 2951 status = "disabled";
4332 }; 2952 };
4333 2953
4334 frame@1742d000 { 2954 frame@1742d000 {
4335 frame-number 2955 frame-number = <6>;
4336 interrupts = 2956 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
4337 reg = <0x1742 2957 reg = <0x1742d000 0x1000>;
4338 status = "dis 2958 status = "disabled";
4339 }; 2959 };
4340 }; 2960 };
4341 2961
4342 apps_rsc: rsc@17a00000 { 2962 apps_rsc: rsc@17a00000 {
4343 label = "apps_rsc"; 2963 label = "apps_rsc";
4344 compatible = "qcom,rp 2964 compatible = "qcom,rpmh-rsc";
4345 reg = <0x0 0x17a00000 2965 reg = <0x0 0x17a00000 0x0 0x10000>,
4346 <0x0 0x17a10000 2966 <0x0 0x17a10000 0x0 0x10000>,
4347 <0x0 0x17a20000 2967 <0x0 0x17a20000 0x0 0x10000>,
4348 <0x0 0x17a30000 2968 <0x0 0x17a30000 0x0 0x10000>;
4349 reg-names = "drv-0", 2969 reg-names = "drv-0", "drv-1", "drv-2", "drv-3";
4350 interrupts = <GIC_SPI 2970 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
4351 <GIC_SPI 2971 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
4352 <GIC_SPI 2972 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
4353 qcom,tcs-offset = <0x 2973 qcom,tcs-offset = <0xd00>;
4354 qcom,drv-id = <2>; 2974 qcom,drv-id = <2>;
4355 qcom,tcs-config = <AC 2975 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
4356 <WA 2976 <WAKE_TCS 2>, <CONTROL_TCS 0>;
4357 power-domains = <&CLU <<
4358 2977
4359 apps_bcm_voter: bcm-v 2978 apps_bcm_voter: bcm-voter {
4360 compatible = 2979 compatible = "qcom,bcm-voter";
4361 }; 2980 };
4362 2981
4363 rpmhcc: clock-control 2982 rpmhcc: clock-controller {
4364 compatible = 2983 compatible = "qcom,sm8450-rpmh-clk";
4365 #clock-cells 2984 #clock-cells = <1>;
4366 clock-names = 2985 clock-names = "xo";
4367 clocks = <&xo 2986 clocks = <&xo_board>;
4368 }; 2987 };
4369 2988
4370 rpmhpd: power-control 2989 rpmhpd: power-controller {
4371 compatible = 2990 compatible = "qcom,sm8450-rpmhpd";
4372 #power-domain 2991 #power-domain-cells = <1>;
4373 operating-poi 2992 operating-points-v2 = <&rpmhpd_opp_table>;
4374 2993
4375 rpmhpd_opp_ta 2994 rpmhpd_opp_table: opp-table {
4376 compa 2995 compatible = "operating-points-v2";
4377 2996
4378 rpmhp 2997 rpmhpd_opp_ret: opp1 {
4379 2998 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4380 }; 2999 };
4381 3000
4382 rpmhp 3001 rpmhpd_opp_min_svs: opp2 {
4383 3002 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4384 }; 3003 };
4385 3004
4386 rpmhp !! 3005 rpmhpd_opp_low_svs: opp3 {
4387 <<
4388 }; <<
4389 <<
4390 rpmhp <<
4391 3006 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4392 }; 3007 };
4393 3008
4394 rpmhp !! 3009 rpmhpd_opp_svs: opp4 {
4395 <<
4396 }; <<
4397 <<
4398 rpmhp <<
4399 3010 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4400 }; 3011 };
4401 3012
4402 rpmhp !! 3013 rpmhpd_opp_svs_l1: opp5 {
4403 <<
4404 }; <<
4405 <<
4406 rpmhp <<
4407 3014 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4408 }; 3015 };
4409 3016
4410 rpmhp !! 3017 rpmhpd_opp_nom: opp6 {
4411 <<
4412 }; <<
4413 <<
4414 rpmhp <<
4415 3018 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4416 }; 3019 };
4417 3020
4418 rpmhp !! 3021 rpmhpd_opp_nom_l1: opp7 {
4419 3022 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4420 }; 3023 };
4421 3024
4422 rpmhp !! 3025 rpmhpd_opp_nom_l2: opp8 {
4423 3026 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4424 }; 3027 };
4425 3028
4426 rpmhp !! 3029 rpmhpd_opp_turbo: opp9 {
4427 3030 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4428 }; 3031 };
4429 3032
4430 rpmhp !! 3033 rpmhpd_opp_turbo_l1: opp10 {
4431 3034 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4432 }; 3035 };
4433 }; 3036 };
4434 }; 3037 };
4435 }; 3038 };
4436 3039
4437 cpufreq_hw: cpufreq@17d91000 3040 cpufreq_hw: cpufreq@17d91000 {
4438 compatible = "qcom,sm 3041 compatible = "qcom,sm8450-cpufreq-epss", "qcom,cpufreq-epss";
4439 reg = <0 0x17d91000 0 3042 reg = <0 0x17d91000 0 0x1000>,
4440 <0 0x17d92000 0 3043 <0 0x17d92000 0 0x1000>,
4441 <0 0x17d93000 0 3044 <0 0x17d93000 0 0x1000>;
4442 reg-names = "freq-dom 3045 reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
4443 clocks = <&rpmhcc RPM 3046 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
4444 clock-names = "xo", " 3047 clock-names = "xo", "alternate";
4445 interrupts = <GIC_SPI 3048 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
4446 <GIC_SPI 3049 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
4447 <GIC_SPI 3050 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
4448 interrupt-names = "dc 3051 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
4449 #freq-domain-cells = 3052 #freq-domain-cells = <1>;
4450 #clock-cells = <1>; <<
4451 }; 3053 };
4452 3054
4453 gem_noc: interconnect@1910000 3055 gem_noc: interconnect@19100000 {
4454 compatible = "qcom,sm 3056 compatible = "qcom,sm8450-gem-noc";
4455 reg = <0 0x19100000 0 3057 reg = <0 0x19100000 0 0xbb800>;
4456 #interconnect-cells = 3058 #interconnect-cells = <2>;
4457 qcom,bcm-voters = <&a 3059 qcom,bcm-voters = <&apps_bcm_voter>;
4458 }; 3060 };
4459 3061
4460 system-cache-controller@19200 3062 system-cache-controller@19200000 {
4461 compatible = "qcom,sm 3063 compatible = "qcom,sm8450-llcc";
4462 reg = <0 0x19200000 0 !! 3064 reg = <0 0x19200000 0 0x580000>, <0 0x19a00000 0 0x80000>;
4463 <0 0x19300000 0 !! 3065 reg-names = "llcc_base", "llcc_broadcast_base";
4464 <0 0x19a00000 0 <<
4465 reg-names = "llcc0_ba <<
4466 "llcc3_ba <<
4467 "llcc_bro <<
4468 interrupts = <GIC_SPI 3066 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
4469 }; 3067 };
4470 3068
4471 ufs_mem_hc: ufshc@1d84000 { 3069 ufs_mem_hc: ufshc@1d84000 {
4472 compatible = "qcom,sm 3070 compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
4473 "jedec,u 3071 "jedec,ufs-2.0";
4474 reg = <0 0x01d84000 0 3072 reg = <0 0x01d84000 0 0x3000>;
4475 interrupts = <GIC_SPI 3073 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
4476 phys = <&ufs_mem_phy> !! 3074 phys = <&ufs_mem_phy_lanes>;
4477 phy-names = "ufsphy"; 3075 phy-names = "ufsphy";
4478 lanes-per-direction = 3076 lanes-per-direction = <2>;
4479 #reset-cells = <1>; 3077 #reset-cells = <1>;
4480 resets = <&gcc GCC_UF 3078 resets = <&gcc GCC_UFS_PHY_BCR>;
4481 reset-names = "rst"; 3079 reset-names = "rst";
4482 3080
4483 power-domains = <&gcc 3081 power-domains = <&gcc UFS_PHY_GDSC>;
4484 3082
4485 iommus = <&apps_smmu 3083 iommus = <&apps_smmu 0xe0 0x0>;
4486 dma-coherent; <<
4487 3084
4488 interconnects = <&agg 3085 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>,
4489 <&gem 3086 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
4490 interconnect-names = 3087 interconnect-names = "ufs-ddr", "cpu-ufs";
4491 clock-names = 3088 clock-names =
4492 "core_clk", 3089 "core_clk",
4493 "bus_aggr_clk 3090 "bus_aggr_clk",
4494 "iface_clk", 3091 "iface_clk",
4495 "core_clk_uni 3092 "core_clk_unipro",
4496 "ref_clk", 3093 "ref_clk",
4497 "tx_lane0_syn 3094 "tx_lane0_sync_clk",
4498 "rx_lane0_syn 3095 "rx_lane0_sync_clk",
4499 "rx_lane1_syn 3096 "rx_lane1_sync_clk";
4500 clocks = 3097 clocks =
4501 <&gcc GCC_UFS 3098 <&gcc GCC_UFS_PHY_AXI_CLK>,
4502 <&gcc GCC_AGG 3099 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
4503 <&gcc GCC_UFS 3100 <&gcc GCC_UFS_PHY_AHB_CLK>,
4504 <&gcc GCC_UFS 3101 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
4505 <&rpmhcc RPMH 3102 <&rpmhcc RPMH_CXO_CLK>,
4506 <&gcc GCC_UFS 3103 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
4507 <&gcc GCC_UFS 3104 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
4508 <&gcc GCC_UFS 3105 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
4509 freq-table-hz = 3106 freq-table-hz =
4510 <75000000 300 3107 <75000000 300000000>,
4511 <0 0>, 3108 <0 0>,
4512 <0 0>, 3109 <0 0>,
4513 <75000000 300 3110 <75000000 300000000>,
4514 <75000000 300 3111 <75000000 300000000>,
4515 <0 0>, 3112 <0 0>,
4516 <0 0>, 3113 <0 0>,
4517 <0 0>; 3114 <0 0>;
4518 qcom,ice = <&ice>; <<
4519 <<
4520 status = "disabled"; 3115 status = "disabled";
4521 }; 3116 };
4522 3117
4523 ufs_mem_phy: phy@1d87000 { 3118 ufs_mem_phy: phy@1d87000 {
4524 compatible = "qcom,sm 3119 compatible = "qcom,sm8450-qmp-ufs-phy";
4525 reg = <0 0x01d87000 0 !! 3120 reg = <0 0x01d87000 0 0x1c4>;
4526 !! 3121 #address-cells = <2>;
>> 3122 #size-cells = <2>;
>> 3123 ranges;
4527 clock-names = "ref", 3124 clock-names = "ref", "ref_aux", "qref";
4528 clocks = <&rpmhcc RPM 3125 clocks = <&rpmhcc RPMH_CXO_CLK>,
4529 <&gcc GCC_UF 3126 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
4530 <&gcc GCC_UF 3127 <&gcc GCC_UFS_0_CLKREF_EN>;
4531 3128
4532 power-domains = <&gcc <<
4533 <<
4534 resets = <&ufs_mem_hc 3129 resets = <&ufs_mem_hc 0>;
4535 reset-names = "ufsphy 3130 reset-names = "ufsphy";
4536 <<
4537 #clock-cells = <1>; <<
4538 #phy-cells = <0>; <<
4539 <<
4540 status = "disabled"; 3131 status = "disabled";
4541 }; <<
4542 <<
4543 ice: crypto@1d88000 { <<
4544 compatible = "qcom,sm <<
4545 "qcom,in <<
4546 reg = <0 0x01d88000 0 <<
4547 clocks = <&gcc GCC_UF <<
4548 }; <<
4549 <<
4550 cryptobam: dma-controller@1dc <<
4551 compatible = "qcom,ba <<
4552 reg = <0 0x01dc4000 0 <<
4553 interrupts = <GIC_SPI <<
4554 #dma-cells = <1>; <<
4555 qcom,ee = <0>; <<
4556 qcom,controlled-remot <<
4557 iommus = <&apps_smmu <<
4558 <&apps_smmu <<
4559 <&apps_smmu <<
4560 <&apps_smmu <<
4561 <&apps_smmu <<
4562 }; <<
4563 <<
4564 crypto: crypto@1dfa000 { <<
4565 compatible = "qcom,sm <<
4566 reg = <0 0x01dfa000 0 <<
4567 dmas = <&cryptobam 4> <<
4568 dma-names = "rx", "tx <<
4569 iommus = <&apps_smmu <<
4570 <&apps_smmu <<
4571 <&apps_smmu <<
4572 <&apps_smmu <<
4573 <&apps_smmu <<
4574 interconnects = <&agg <<
4575 interconnect-names = <<
4576 }; <<
4577 <<
4578 sdhc_2: mmc@8804000 { <<
4579 compatible = "qcom,sm <<
4580 reg = <0 0x08804000 0 <<
4581 <<
4582 interrupts = <GIC_SPI <<
4583 <GIC_SPI <<
4584 interrupt-names = "hc <<
4585 <<
4586 clocks = <&gcc GCC_SD <<
4587 <&gcc GCC_SD <<
4588 <&rpmhcc RPM <<
4589 clock-names = "iface" <<
4590 resets = <&gcc GCC_SD <<
4591 interconnects = <&agg <<
4592 <&gem <<
4593 interconnect-names = <<
4594 iommus = <&apps_smmu <<
4595 power-domains = <&rpm <<
4596 operating-points-v2 = <<
4597 bus-width = <4>; <<
4598 dma-coherent; <<
4599 3132
4600 /* Forbid SDR104/SDR5 !! 3133 ufs_mem_phy_lanes: phy@1d87400 {
4601 sdhci-caps-mask = <0x !! 3134 reg = <0 0x01d87400 0 0x188>,
4602 !! 3135 <0 0x01d87600 0 0x200>,
4603 status = "disabled"; !! 3136 <0 0x01d87c00 0 0x200>,
4604 !! 3137 <0 0x01d87800 0 0x188>,
4605 sdhc2_opp_table: opp- !! 3138 <0 0x01d87a00 0 0x200>;
4606 compatible = !! 3139 #phy-cells = <0>;
4607 <<
4608 opp-100000000 <<
4609 opp-h <<
4610 requi <<
4611 }; <<
4612 <<
4613 opp-202000000 <<
4614 opp-h <<
4615 requi <<
4616 }; <<
4617 }; 3140 };
4618 }; 3141 };
4619 3142
4620 usb_1: usb@a6f8800 { 3143 usb_1: usb@a6f8800 {
4621 compatible = "qcom,sm 3144 compatible = "qcom,sm8450-dwc3", "qcom,dwc3";
4622 reg = <0 0x0a6f8800 0 3145 reg = <0 0x0a6f8800 0 0x400>;
4623 status = "disabled"; 3146 status = "disabled";
4624 #address-cells = <2>; 3147 #address-cells = <2>;
4625 #size-cells = <2>; 3148 #size-cells = <2>;
4626 ranges; 3149 ranges;
4627 3150
4628 clocks = <&gcc GCC_CF 3151 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
4629 <&gcc GCC_US 3152 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
4630 <&gcc GCC_AG 3153 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
4631 <&gcc GCC_US 3154 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
4632 <&gcc GCC_US 3155 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4633 <&gcc GCC_US 3156 <&gcc GCC_USB3_0_CLKREF_EN>;
4634 clock-names = "cfg_no 3157 clock-names = "cfg_noc",
4635 "core", 3158 "core",
4636 "iface" 3159 "iface",
4637 "sleep" 3160 "sleep",
4638 "mock_u 3161 "mock_utmi",
4639 "xo"; 3162 "xo";
4640 3163
4641 assigned-clocks = <&g 3164 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4642 <&g 3165 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
4643 assigned-clock-rates 3166 assigned-clock-rates = <19200000>, <200000000>;
4644 3167
4645 interrupts-extended = 3168 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
4646 !! 3169 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
4647 <<
4648 3170 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
4649 !! 3171 <&pdc 14 IRQ_TYPE_EDGE_BOTH>;
4650 interrupt-names = "pw !! 3172 interrupt-names = "hs_phy_irq",
4651 "hs !! 3173 "ss_phy_irq",
4652 "dp <<
4653 "dm 3174 "dm_hs_phy_irq",
4654 "ss !! 3175 "dp_hs_phy_irq";
4655 3176
4656 power-domains = <&gcc 3177 power-domains = <&gcc USB30_PRIM_GDSC>;
4657 3178
4658 resets = <&gcc GCC_US 3179 resets = <&gcc GCC_USB30_PRIM_BCR>;
4659 3180
4660 interconnects = <&agg <<
4661 <&gem <<
4662 interconnect-names = <<
4663 <<
4664 usb_1_dwc3: usb@a6000 3181 usb_1_dwc3: usb@a600000 {
4665 compatible = 3182 compatible = "snps,dwc3";
4666 reg = <0 0x0a 3183 reg = <0 0x0a600000 0 0xcd00>;
4667 interrupts = 3184 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
4668 iommus = <&ap 3185 iommus = <&apps_smmu 0x0 0x0>;
4669 snps,dis_u2_s 3186 snps,dis_u2_susphy_quirk;
4670 snps,dis_enbl 3187 snps,dis_enblslpm_quirk;
4671 phys = <&usb_ !! 3188 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
4672 phy-names = " 3189 phy-names = "usb2-phy", "usb3-phy";
4673 <<
4674 ports { <<
4675 #addr <<
4676 #size <<
4677 <<
4678 port@ <<
4679 <<
4680 <<
4681 <<
4682 <<
4683 }; <<
4684 <<
4685 port@ <<
4686 <<
4687 <<
4688 <<
4689 <<
4690 <<
4691 }; <<
4692 }; <<
4693 }; 3190 };
4694 }; 3191 };
4695 3192
4696 nsp_noc: interconnect@320c000 3193 nsp_noc: interconnect@320c0000 {
4697 compatible = "qcom,sm 3194 compatible = "qcom,sm8450-nsp-noc";
4698 reg = <0 0x320c0000 0 3195 reg = <0 0x320c0000 0 0x10000>;
4699 #interconnect-cells = 3196 #interconnect-cells = <2>;
4700 qcom,bcm-voters = <&a 3197 qcom,bcm-voters = <&apps_bcm_voter>;
4701 }; 3198 };
4702 3199
4703 lpass_ag_noc: interconnect@3c 3200 lpass_ag_noc: interconnect@3c40000 {
4704 compatible = "qcom,sm 3201 compatible = "qcom,sm8450-lpass-ag-noc";
4705 reg = <0 0x03c40000 0 !! 3202 reg = <0 0x3c40000 0 0x17200>;
4706 #interconnect-cells = 3203 #interconnect-cells = <2>;
4707 qcom,bcm-voters = <&a 3204 qcom,bcm-voters = <&apps_bcm_voter>;
4708 }; 3205 };
4709 }; 3206 };
4710 3207
4711 sound: sound { <<
4712 }; <<
4713 <<
4714 thermal-zones { 3208 thermal-zones {
4715 aoss0-thermal { 3209 aoss0-thermal {
>> 3210 polling-delay-passive = <0>;
>> 3211 polling-delay = <0>;
4716 thermal-sensors = <&t 3212 thermal-sensors = <&tsens0 0>;
4717 3213
4718 trips { 3214 trips {
4719 thermal-engin 3215 thermal-engine-config {
4720 tempe 3216 temperature = <125000>;
4721 hyste 3217 hysteresis = <1000>;
4722 type 3218 type = "passive";
4723 }; 3219 };
4724 3220
4725 reset-mon-cfg 3221 reset-mon-cfg {
4726 tempe 3222 temperature = <115000>;
4727 hyste 3223 hysteresis = <5000>;
4728 type 3224 type = "passive";
4729 }; 3225 };
4730 }; 3226 };
4731 }; 3227 };
4732 3228
4733 cpuss0-thermal { 3229 cpuss0-thermal {
>> 3230 polling-delay-passive = <0>;
>> 3231 polling-delay = <0>;
4734 thermal-sensors = <&t 3232 thermal-sensors = <&tsens0 1>;
4735 3233
4736 trips { 3234 trips {
4737 thermal-engin 3235 thermal-engine-config {
4738 tempe 3236 temperature = <125000>;
4739 hyste 3237 hysteresis = <1000>;
4740 type 3238 type = "passive";
4741 }; 3239 };
4742 3240
4743 reset-mon-cfg 3241 reset-mon-cfg {
4744 tempe 3242 temperature = <115000>;
4745 hyste 3243 hysteresis = <5000>;
4746 type 3244 type = "passive";
4747 }; 3245 };
4748 }; 3246 };
4749 }; 3247 };
4750 3248
4751 cpuss1-thermal { 3249 cpuss1-thermal {
>> 3250 polling-delay-passive = <0>;
>> 3251 polling-delay = <0>;
4752 thermal-sensors = <&t 3252 thermal-sensors = <&tsens0 2>;
4753 3253
4754 trips { 3254 trips {
4755 thermal-engin 3255 thermal-engine-config {
4756 tempe 3256 temperature = <125000>;
4757 hyste 3257 hysteresis = <1000>;
4758 type 3258 type = "passive";
4759 }; 3259 };
4760 3260
4761 reset-mon-cfg 3261 reset-mon-cfg {
4762 tempe 3262 temperature = <115000>;
4763 hyste 3263 hysteresis = <5000>;
4764 type 3264 type = "passive";
4765 }; 3265 };
4766 }; 3266 };
4767 }; 3267 };
4768 3268
4769 cpuss3-thermal { 3269 cpuss3-thermal {
>> 3270 polling-delay-passive = <0>;
>> 3271 polling-delay = <0>;
4770 thermal-sensors = <&t 3272 thermal-sensors = <&tsens0 3>;
4771 3273
4772 trips { 3274 trips {
4773 thermal-engin 3275 thermal-engine-config {
4774 tempe 3276 temperature = <125000>;
4775 hyste 3277 hysteresis = <1000>;
4776 type 3278 type = "passive";
4777 }; 3279 };
4778 3280
4779 reset-mon-cfg 3281 reset-mon-cfg {
4780 tempe 3282 temperature = <115000>;
4781 hyste 3283 hysteresis = <5000>;
4782 type 3284 type = "passive";
4783 }; 3285 };
4784 }; 3286 };
4785 }; 3287 };
4786 3288
4787 cpuss4-thermal { 3289 cpuss4-thermal {
>> 3290 polling-delay-passive = <0>;
>> 3291 polling-delay = <0>;
4788 thermal-sensors = <&t 3292 thermal-sensors = <&tsens0 4>;
4789 3293
4790 trips { 3294 trips {
4791 thermal-engin 3295 thermal-engine-config {
4792 tempe 3296 temperature = <125000>;
4793 hyste 3297 hysteresis = <1000>;
4794 type 3298 type = "passive";
4795 }; 3299 };
4796 3300
4797 reset-mon-cfg 3301 reset-mon-cfg {
4798 tempe 3302 temperature = <115000>;
4799 hyste 3303 hysteresis = <5000>;
4800 type 3304 type = "passive";
4801 }; 3305 };
4802 }; 3306 };
4803 }; 3307 };
4804 3308
4805 cpu4-top-thermal { 3309 cpu4-top-thermal {
>> 3310 polling-delay-passive = <0>;
>> 3311 polling-delay = <0>;
4806 thermal-sensors = <&t 3312 thermal-sensors = <&tsens0 5>;
4807 3313
4808 trips { 3314 trips {
4809 cpu4_top_aler 3315 cpu4_top_alert0: trip-point0 {
4810 tempe 3316 temperature = <90000>;
4811 hyste 3317 hysteresis = <2000>;
4812 type 3318 type = "passive";
4813 }; 3319 };
4814 3320
4815 cpu4_top_aler 3321 cpu4_top_alert1: trip-point1 {
4816 tempe 3322 temperature = <95000>;
4817 hyste 3323 hysteresis = <2000>;
4818 type 3324 type = "passive";
4819 }; 3325 };
4820 3326
4821 cpu4_top_crit !! 3327 cpu4_top_crit: cpu_crit {
4822 tempe 3328 temperature = <110000>;
4823 hyste 3329 hysteresis = <1000>;
4824 type 3330 type = "critical";
4825 }; 3331 };
4826 }; 3332 };
4827 }; 3333 };
4828 3334
4829 cpu4-bottom-thermal { 3335 cpu4-bottom-thermal {
>> 3336 polling-delay-passive = <0>;
>> 3337 polling-delay = <0>;
4830 thermal-sensors = <&t 3338 thermal-sensors = <&tsens0 6>;
4831 3339
4832 trips { 3340 trips {
4833 cpu4_bottom_a 3341 cpu4_bottom_alert0: trip-point0 {
4834 tempe 3342 temperature = <90000>;
4835 hyste 3343 hysteresis = <2000>;
4836 type 3344 type = "passive";
4837 }; 3345 };
4838 3346
4839 cpu4_bottom_a 3347 cpu4_bottom_alert1: trip-point1 {
4840 tempe 3348 temperature = <95000>;
4841 hyste 3349 hysteresis = <2000>;
4842 type 3350 type = "passive";
4843 }; 3351 };
4844 3352
4845 cpu4_bottom_c !! 3353 cpu4_bottom_crit: cpu_crit {
4846 tempe 3354 temperature = <110000>;
4847 hyste 3355 hysteresis = <1000>;
4848 type 3356 type = "critical";
4849 }; 3357 };
4850 }; 3358 };
4851 }; 3359 };
4852 3360
4853 cpu5-top-thermal { 3361 cpu5-top-thermal {
>> 3362 polling-delay-passive = <0>;
>> 3363 polling-delay = <0>;
4854 thermal-sensors = <&t 3364 thermal-sensors = <&tsens0 7>;
4855 3365
4856 trips { 3366 trips {
4857 cpu5_top_aler 3367 cpu5_top_alert0: trip-point0 {
4858 tempe 3368 temperature = <90000>;
4859 hyste 3369 hysteresis = <2000>;
4860 type 3370 type = "passive";
4861 }; 3371 };
4862 3372
4863 cpu5_top_aler 3373 cpu5_top_alert1: trip-point1 {
4864 tempe 3374 temperature = <95000>;
4865 hyste 3375 hysteresis = <2000>;
4866 type 3376 type = "passive";
4867 }; 3377 };
4868 3378
4869 cpu5_top_crit !! 3379 cpu5_top_crit: cpu_crit {
4870 tempe 3380 temperature = <110000>;
4871 hyste 3381 hysteresis = <1000>;
4872 type 3382 type = "critical";
4873 }; 3383 };
4874 }; 3384 };
4875 }; 3385 };
4876 3386
4877 cpu5-bottom-thermal { 3387 cpu5-bottom-thermal {
>> 3388 polling-delay-passive = <0>;
>> 3389 polling-delay = <0>;
4878 thermal-sensors = <&t 3390 thermal-sensors = <&tsens0 8>;
4879 3391
4880 trips { 3392 trips {
4881 cpu5_bottom_a 3393 cpu5_bottom_alert0: trip-point0 {
4882 tempe 3394 temperature = <90000>;
4883 hyste 3395 hysteresis = <2000>;
4884 type 3396 type = "passive";
4885 }; 3397 };
4886 3398
4887 cpu5_bottom_a 3399 cpu5_bottom_alert1: trip-point1 {
4888 tempe 3400 temperature = <95000>;
4889 hyste 3401 hysteresis = <2000>;
4890 type 3402 type = "passive";
4891 }; 3403 };
4892 3404
4893 cpu5_bottom_c !! 3405 cpu5_bottom_crit: cpu_crit {
4894 tempe 3406 temperature = <110000>;
4895 hyste 3407 hysteresis = <1000>;
4896 type 3408 type = "critical";
4897 }; 3409 };
4898 }; 3410 };
4899 }; 3411 };
4900 3412
4901 cpu6-top-thermal { 3413 cpu6-top-thermal {
>> 3414 polling-delay-passive = <0>;
>> 3415 polling-delay = <0>;
4902 thermal-sensors = <&t 3416 thermal-sensors = <&tsens0 9>;
4903 3417
4904 trips { 3418 trips {
4905 cpu6_top_aler 3419 cpu6_top_alert0: trip-point0 {
4906 tempe 3420 temperature = <90000>;
4907 hyste 3421 hysteresis = <2000>;
4908 type 3422 type = "passive";
4909 }; 3423 };
4910 3424
4911 cpu6_top_aler 3425 cpu6_top_alert1: trip-point1 {
4912 tempe 3426 temperature = <95000>;
4913 hyste 3427 hysteresis = <2000>;
4914 type 3428 type = "passive";
4915 }; 3429 };
4916 3430
4917 cpu6_top_crit !! 3431 cpu6_top_crit: cpu_crit {
4918 tempe 3432 temperature = <110000>;
4919 hyste 3433 hysteresis = <1000>;
4920 type 3434 type = "critical";
4921 }; 3435 };
4922 }; 3436 };
4923 }; 3437 };
4924 3438
4925 cpu6-bottom-thermal { 3439 cpu6-bottom-thermal {
>> 3440 polling-delay-passive = <0>;
>> 3441 polling-delay = <0>;
4926 thermal-sensors = <&t 3442 thermal-sensors = <&tsens0 10>;
4927 3443
4928 trips { 3444 trips {
4929 cpu6_bottom_a 3445 cpu6_bottom_alert0: trip-point0 {
4930 tempe 3446 temperature = <90000>;
4931 hyste 3447 hysteresis = <2000>;
4932 type 3448 type = "passive";
4933 }; 3449 };
4934 3450
4935 cpu6_bottom_a 3451 cpu6_bottom_alert1: trip-point1 {
4936 tempe 3452 temperature = <95000>;
4937 hyste 3453 hysteresis = <2000>;
4938 type 3454 type = "passive";
4939 }; 3455 };
4940 3456
4941 cpu6_bottom_c !! 3457 cpu6_bottom_crit: cpu_crit {
4942 tempe 3458 temperature = <110000>;
4943 hyste 3459 hysteresis = <1000>;
4944 type 3460 type = "critical";
4945 }; 3461 };
4946 }; 3462 };
4947 }; 3463 };
4948 3464
4949 cpu7-top-thermal { 3465 cpu7-top-thermal {
>> 3466 polling-delay-passive = <0>;
>> 3467 polling-delay = <0>;
4950 thermal-sensors = <&t 3468 thermal-sensors = <&tsens0 11>;
4951 3469
4952 trips { 3470 trips {
4953 cpu7_top_aler 3471 cpu7_top_alert0: trip-point0 {
4954 tempe 3472 temperature = <90000>;
4955 hyste 3473 hysteresis = <2000>;
4956 type 3474 type = "passive";
4957 }; 3475 };
4958 3476
4959 cpu7_top_aler 3477 cpu7_top_alert1: trip-point1 {
4960 tempe 3478 temperature = <95000>;
4961 hyste 3479 hysteresis = <2000>;
4962 type 3480 type = "passive";
4963 }; 3481 };
4964 3482
4965 cpu7_top_crit !! 3483 cpu7_top_crit: cpu_crit {
4966 tempe 3484 temperature = <110000>;
4967 hyste 3485 hysteresis = <1000>;
4968 type 3486 type = "critical";
4969 }; 3487 };
4970 }; 3488 };
4971 }; 3489 };
4972 3490
4973 cpu7-middle-thermal { 3491 cpu7-middle-thermal {
>> 3492 polling-delay-passive = <0>;
>> 3493 polling-delay = <0>;
4974 thermal-sensors = <&t 3494 thermal-sensors = <&tsens0 12>;
4975 3495
4976 trips { 3496 trips {
4977 cpu7_middle_a 3497 cpu7_middle_alert0: trip-point0 {
4978 tempe 3498 temperature = <90000>;
4979 hyste 3499 hysteresis = <2000>;
4980 type 3500 type = "passive";
4981 }; 3501 };
4982 3502
4983 cpu7_middle_a 3503 cpu7_middle_alert1: trip-point1 {
4984 tempe 3504 temperature = <95000>;
4985 hyste 3505 hysteresis = <2000>;
4986 type 3506 type = "passive";
4987 }; 3507 };
4988 3508
4989 cpu7_middle_c !! 3509 cpu7_middle_crit: cpu_crit {
4990 tempe 3510 temperature = <110000>;
4991 hyste 3511 hysteresis = <1000>;
4992 type 3512 type = "critical";
4993 }; 3513 };
4994 }; 3514 };
4995 }; 3515 };
4996 3516
4997 cpu7-bottom-thermal { 3517 cpu7-bottom-thermal {
>> 3518 polling-delay-passive = <0>;
>> 3519 polling-delay = <0>;
4998 thermal-sensors = <&t 3520 thermal-sensors = <&tsens0 13>;
4999 3521
5000 trips { 3522 trips {
5001 cpu7_bottom_a 3523 cpu7_bottom_alert0: trip-point0 {
5002 tempe 3524 temperature = <90000>;
5003 hyste 3525 hysteresis = <2000>;
5004 type 3526 type = "passive";
5005 }; 3527 };
5006 3528
5007 cpu7_bottom_a 3529 cpu7_bottom_alert1: trip-point1 {
5008 tempe 3530 temperature = <95000>;
5009 hyste 3531 hysteresis = <2000>;
5010 type 3532 type = "passive";
5011 }; 3533 };
5012 3534
5013 cpu7_bottom_c !! 3535 cpu7_bottom_crit: cpu_crit {
5014 tempe 3536 temperature = <110000>;
5015 hyste 3537 hysteresis = <1000>;
5016 type 3538 type = "critical";
5017 }; 3539 };
5018 }; 3540 };
5019 }; 3541 };
5020 3542
5021 gpu-top-thermal { 3543 gpu-top-thermal {
5022 polling-delay-passive 3544 polling-delay-passive = <10>;
5023 !! 3545 polling-delay = <0>;
5024 thermal-sensors = <&t 3546 thermal-sensors = <&tsens0 14>;
5025 3547
5026 cooling-maps { <<
5027 map0 { <<
5028 trip <<
5029 cooli <<
5030 }; <<
5031 }; <<
5032 <<
5033 trips { 3548 trips {
5034 gpu_top_alert !! 3549 thermal-engine-config {
5035 tempe !! 3550 temperature = <125000>;
5036 hyste 3551 hysteresis = <1000>;
5037 type 3552 type = "passive";
5038 }; 3553 };
5039 3554
5040 trip-point1 { !! 3555 thermal-hal-config {
5041 tempe !! 3556 temperature = <125000>;
5042 hyste 3557 hysteresis = <1000>;
5043 type !! 3558 type = "passive";
5044 }; 3559 };
5045 3560
5046 trip-point2 { !! 3561 reset-mon-cfg {
5047 tempe !! 3562 temperature = <115000>;
5048 hyste !! 3563 hysteresis = <5000>;
5049 type !! 3564 type = "passive";
>> 3565 };
>> 3566
>> 3567 gpu0_tj_cfg: tj_cfg {
>> 3568 temperature = <95000>;
>> 3569 hysteresis = <5000>;
>> 3570 type = "passive";
5050 }; 3571 };
5051 }; 3572 };
5052 }; 3573 };
5053 3574
5054 gpu-bottom-thermal { 3575 gpu-bottom-thermal {
5055 polling-delay-passive 3576 polling-delay-passive = <10>;
5056 !! 3577 polling-delay = <0>;
5057 thermal-sensors = <&t 3578 thermal-sensors = <&tsens0 15>;
5058 3579
5059 cooling-maps { <<
5060 map0 { <<
5061 trip <<
5062 cooli <<
5063 }; <<
5064 }; <<
5065 <<
5066 trips { 3580 trips {
5067 gpu_bottom_al !! 3581 thermal-engine-config {
5068 tempe !! 3582 temperature = <125000>;
5069 hyste 3583 hysteresis = <1000>;
5070 type 3584 type = "passive";
5071 }; 3585 };
5072 3586
5073 trip-point1 { !! 3587 thermal-hal-config {
5074 tempe !! 3588 temperature = <125000>;
5075 hyste 3589 hysteresis = <1000>;
5076 type !! 3590 type = "passive";
5077 }; 3591 };
5078 3592
5079 trip-point2 { !! 3593 reset-mon-cfg {
5080 tempe !! 3594 temperature = <115000>;
5081 hyste !! 3595 hysteresis = <5000>;
5082 type !! 3596 type = "passive";
>> 3597 };
>> 3598
>> 3599 gpu1_tj_cfg: tj_cfg {
>> 3600 temperature = <95000>;
>> 3601 hysteresis = <5000>;
>> 3602 type = "passive";
5083 }; 3603 };
5084 }; 3604 };
5085 }; 3605 };
5086 3606
5087 aoss1-thermal { 3607 aoss1-thermal {
>> 3608 polling-delay-passive = <0>;
>> 3609 polling-delay = <0>;
5088 thermal-sensors = <&t 3610 thermal-sensors = <&tsens1 0>;
5089 3611
5090 trips { 3612 trips {
5091 thermal-engin 3613 thermal-engine-config {
5092 tempe 3614 temperature = <125000>;
5093 hyste 3615 hysteresis = <1000>;
5094 type 3616 type = "passive";
5095 }; 3617 };
5096 3618
5097 reset-mon-cfg 3619 reset-mon-cfg {
5098 tempe 3620 temperature = <115000>;
5099 hyste 3621 hysteresis = <5000>;
5100 type 3622 type = "passive";
5101 }; 3623 };
5102 }; 3624 };
5103 }; 3625 };
5104 3626
5105 cpu0-thermal { 3627 cpu0-thermal {
>> 3628 polling-delay-passive = <0>;
>> 3629 polling-delay = <0>;
5106 thermal-sensors = <&t 3630 thermal-sensors = <&tsens1 1>;
5107 3631
5108 trips { 3632 trips {
5109 cpu0_alert0: 3633 cpu0_alert0: trip-point0 {
5110 tempe 3634 temperature = <90000>;
5111 hyste 3635 hysteresis = <2000>;
5112 type 3636 type = "passive";
5113 }; 3637 };
5114 3638
5115 cpu0_alert1: 3639 cpu0_alert1: trip-point1 {
5116 tempe 3640 temperature = <95000>;
5117 hyste 3641 hysteresis = <2000>;
5118 type 3642 type = "passive";
5119 }; 3643 };
5120 3644
5121 cpu0_crit: cp !! 3645 cpu0_crit: cpu_crit {
5122 tempe 3646 temperature = <110000>;
5123 hyste 3647 hysteresis = <1000>;
5124 type 3648 type = "critical";
5125 }; 3649 };
5126 }; 3650 };
5127 }; 3651 };
5128 3652
5129 cpu1-thermal { 3653 cpu1-thermal {
>> 3654 polling-delay-passive = <0>;
>> 3655 polling-delay = <0>;
5130 thermal-sensors = <&t 3656 thermal-sensors = <&tsens1 2>;
5131 3657
5132 trips { 3658 trips {
5133 cpu1_alert0: 3659 cpu1_alert0: trip-point0 {
5134 tempe 3660 temperature = <90000>;
5135 hyste 3661 hysteresis = <2000>;
5136 type 3662 type = "passive";
5137 }; 3663 };
5138 3664
5139 cpu1_alert1: 3665 cpu1_alert1: trip-point1 {
5140 tempe 3666 temperature = <95000>;
5141 hyste 3667 hysteresis = <2000>;
5142 type 3668 type = "passive";
5143 }; 3669 };
5144 3670
5145 cpu1_crit: cp !! 3671 cpu1_crit: cpu_crit {
5146 tempe 3672 temperature = <110000>;
5147 hyste 3673 hysteresis = <1000>;
5148 type 3674 type = "critical";
5149 }; 3675 };
5150 }; 3676 };
5151 }; 3677 };
5152 3678
5153 cpu2-thermal { 3679 cpu2-thermal {
>> 3680 polling-delay-passive = <0>;
>> 3681 polling-delay = <0>;
5154 thermal-sensors = <&t 3682 thermal-sensors = <&tsens1 3>;
5155 3683
5156 trips { 3684 trips {
5157 cpu2_alert0: 3685 cpu2_alert0: trip-point0 {
5158 tempe 3686 temperature = <90000>;
5159 hyste 3687 hysteresis = <2000>;
5160 type 3688 type = "passive";
5161 }; 3689 };
5162 3690
5163 cpu2_alert1: 3691 cpu2_alert1: trip-point1 {
5164 tempe 3692 temperature = <95000>;
5165 hyste 3693 hysteresis = <2000>;
5166 type 3694 type = "passive";
5167 }; 3695 };
5168 3696
5169 cpu2_crit: cp !! 3697 cpu2_crit: cpu_crit {
5170 tempe 3698 temperature = <110000>;
5171 hyste 3699 hysteresis = <1000>;
5172 type 3700 type = "critical";
5173 }; 3701 };
5174 }; 3702 };
5175 }; 3703 };
5176 3704
5177 cpu3-thermal { 3705 cpu3-thermal {
>> 3706 polling-delay-passive = <0>;
>> 3707 polling-delay = <0>;
5178 thermal-sensors = <&t 3708 thermal-sensors = <&tsens1 4>;
5179 3709
5180 trips { 3710 trips {
5181 cpu3_alert0: 3711 cpu3_alert0: trip-point0 {
5182 tempe 3712 temperature = <90000>;
5183 hyste 3713 hysteresis = <2000>;
5184 type 3714 type = "passive";
5185 }; 3715 };
5186 3716
5187 cpu3_alert1: 3717 cpu3_alert1: trip-point1 {
5188 tempe 3718 temperature = <95000>;
5189 hyste 3719 hysteresis = <2000>;
5190 type 3720 type = "passive";
5191 }; 3721 };
5192 3722
5193 cpu3_crit: cp !! 3723 cpu3_crit: cpu_crit {
5194 tempe 3724 temperature = <110000>;
5195 hyste 3725 hysteresis = <1000>;
5196 type 3726 type = "critical";
5197 }; 3727 };
5198 }; 3728 };
5199 }; 3729 };
5200 3730
5201 cdsp0-thermal { 3731 cdsp0-thermal {
5202 polling-delay-passive 3732 polling-delay-passive = <10>;
5203 !! 3733 polling-delay = <0>;
5204 thermal-sensors = <&t 3734 thermal-sensors = <&tsens1 5>;
5205 3735
5206 trips { 3736 trips {
5207 thermal-engin 3737 thermal-engine-config {
5208 tempe 3738 temperature = <125000>;
5209 hyste 3739 hysteresis = <1000>;
5210 type 3740 type = "passive";
5211 }; 3741 };
5212 3742
5213 thermal-hal-c 3743 thermal-hal-config {
5214 tempe 3744 temperature = <125000>;
5215 hyste 3745 hysteresis = <1000>;
5216 type 3746 type = "passive";
5217 }; 3747 };
5218 3748
5219 reset-mon-cfg 3749 reset-mon-cfg {
5220 tempe 3750 temperature = <115000>;
5221 hyste 3751 hysteresis = <5000>;
5222 type 3752 type = "passive";
5223 }; 3753 };
5224 3754
5225 cdsp_0_config 3755 cdsp_0_config: junction-config {
5226 tempe 3756 temperature = <95000>;
5227 hyste 3757 hysteresis = <5000>;
5228 type 3758 type = "passive";
5229 }; 3759 };
5230 }; 3760 };
5231 }; 3761 };
5232 3762
5233 cdsp1-thermal { 3763 cdsp1-thermal {
5234 polling-delay-passive 3764 polling-delay-passive = <10>;
5235 !! 3765 polling-delay = <0>;
5236 thermal-sensors = <&t 3766 thermal-sensors = <&tsens1 6>;
5237 3767
5238 trips { 3768 trips {
5239 thermal-engin 3769 thermal-engine-config {
5240 tempe 3770 temperature = <125000>;
5241 hyste 3771 hysteresis = <1000>;
5242 type 3772 type = "passive";
5243 }; 3773 };
5244 3774
5245 thermal-hal-c 3775 thermal-hal-config {
5246 tempe 3776 temperature = <125000>;
5247 hyste 3777 hysteresis = <1000>;
5248 type 3778 type = "passive";
5249 }; 3779 };
5250 3780
5251 reset-mon-cfg 3781 reset-mon-cfg {
5252 tempe 3782 temperature = <115000>;
5253 hyste 3783 hysteresis = <5000>;
5254 type 3784 type = "passive";
5255 }; 3785 };
5256 3786
5257 cdsp_1_config 3787 cdsp_1_config: junction-config {
5258 tempe 3788 temperature = <95000>;
5259 hyste 3789 hysteresis = <5000>;
5260 type 3790 type = "passive";
5261 }; 3791 };
5262 }; 3792 };
5263 }; 3793 };
5264 3794
5265 cdsp2-thermal { 3795 cdsp2-thermal {
5266 polling-delay-passive 3796 polling-delay-passive = <10>;
5267 !! 3797 polling-delay = <0>;
5268 thermal-sensors = <&t 3798 thermal-sensors = <&tsens1 7>;
5269 3799
5270 trips { 3800 trips {
5271 thermal-engin 3801 thermal-engine-config {
5272 tempe 3802 temperature = <125000>;
5273 hyste 3803 hysteresis = <1000>;
5274 type 3804 type = "passive";
5275 }; 3805 };
5276 3806
5277 thermal-hal-c 3807 thermal-hal-config {
5278 tempe 3808 temperature = <125000>;
5279 hyste 3809 hysteresis = <1000>;
5280 type 3810 type = "passive";
5281 }; 3811 };
5282 3812
5283 reset-mon-cfg 3813 reset-mon-cfg {
5284 tempe 3814 temperature = <115000>;
5285 hyste 3815 hysteresis = <5000>;
5286 type 3816 type = "passive";
5287 }; 3817 };
5288 3818
5289 cdsp_2_config 3819 cdsp_2_config: junction-config {
5290 tempe 3820 temperature = <95000>;
5291 hyste 3821 hysteresis = <5000>;
5292 type 3822 type = "passive";
5293 }; 3823 };
5294 }; 3824 };
5295 }; 3825 };
5296 3826
5297 video-thermal { 3827 video-thermal {
>> 3828 polling-delay-passive = <0>;
>> 3829 polling-delay = <0>;
5298 thermal-sensors = <&t 3830 thermal-sensors = <&tsens1 8>;
5299 3831
5300 trips { 3832 trips {
5301 thermal-engin 3833 thermal-engine-config {
5302 tempe 3834 temperature = <125000>;
5303 hyste 3835 hysteresis = <1000>;
5304 type 3836 type = "passive";
5305 }; 3837 };
5306 3838
5307 reset-mon-cfg 3839 reset-mon-cfg {
5308 tempe 3840 temperature = <115000>;
5309 hyste 3841 hysteresis = <5000>;
5310 type 3842 type = "passive";
5311 }; 3843 };
5312 }; 3844 };
5313 }; 3845 };
5314 3846
5315 mem-thermal { 3847 mem-thermal {
5316 polling-delay-passive 3848 polling-delay-passive = <10>;
5317 !! 3849 polling-delay = <0>;
5318 thermal-sensors = <&t 3850 thermal-sensors = <&tsens1 9>;
5319 3851
5320 trips { 3852 trips {
5321 thermal-engin 3853 thermal-engine-config {
5322 tempe 3854 temperature = <125000>;
5323 hyste 3855 hysteresis = <1000>;
5324 type 3856 type = "passive";
5325 }; 3857 };
5326 3858
5327 ddr_config0: 3859 ddr_config0: ddr0-config {
5328 tempe 3860 temperature = <90000>;
5329 hyste 3861 hysteresis = <5000>;
5330 type 3862 type = "passive";
5331 }; 3863 };
5332 3864
5333 reset-mon-cfg 3865 reset-mon-cfg {
5334 tempe 3866 temperature = <115000>;
5335 hyste 3867 hysteresis = <5000>;
5336 type 3868 type = "passive";
5337 }; 3869 };
5338 }; 3870 };
5339 }; 3871 };
5340 3872
5341 modem0-thermal { 3873 modem0-thermal {
>> 3874 polling-delay-passive = <0>;
>> 3875 polling-delay = <0>;
5342 thermal-sensors = <&t 3876 thermal-sensors = <&tsens1 10>;
5343 3877
5344 trips { 3878 trips {
5345 thermal-engin 3879 thermal-engine-config {
5346 tempe 3880 temperature = <125000>;
5347 hyste 3881 hysteresis = <1000>;
5348 type 3882 type = "passive";
5349 }; 3883 };
5350 3884
5351 mdmss0_config 3885 mdmss0_config0: mdmss0-config0 {
5352 tempe 3886 temperature = <102000>;
5353 hyste 3887 hysteresis = <3000>;
5354 type 3888 type = "passive";
5355 }; 3889 };
5356 3890
5357 mdmss0_config 3891 mdmss0_config1: mdmss0-config1 {
5358 tempe 3892 temperature = <105000>;
5359 hyste 3893 hysteresis = <3000>;
5360 type 3894 type = "passive";
5361 }; 3895 };
5362 3896
5363 reset-mon-cfg 3897 reset-mon-cfg {
5364 tempe 3898 temperature = <115000>;
5365 hyste 3899 hysteresis = <5000>;
5366 type 3900 type = "passive";
5367 }; 3901 };
5368 }; 3902 };
5369 }; 3903 };
5370 3904
5371 modem1-thermal { 3905 modem1-thermal {
>> 3906 polling-delay-passive = <0>;
>> 3907 polling-delay = <0>;
5372 thermal-sensors = <&t 3908 thermal-sensors = <&tsens1 11>;
5373 3909
5374 trips { 3910 trips {
5375 thermal-engin 3911 thermal-engine-config {
5376 tempe 3912 temperature = <125000>;
5377 hyste 3913 hysteresis = <1000>;
5378 type 3914 type = "passive";
5379 }; 3915 };
5380 3916
5381 mdmss1_config 3917 mdmss1_config0: mdmss1-config0 {
5382 tempe 3918 temperature = <102000>;
5383 hyste 3919 hysteresis = <3000>;
5384 type 3920 type = "passive";
5385 }; 3921 };
5386 3922
5387 mdmss1_config 3923 mdmss1_config1: mdmss1-config1 {
5388 tempe 3924 temperature = <105000>;
5389 hyste 3925 hysteresis = <3000>;
5390 type 3926 type = "passive";
5391 }; 3927 };
5392 3928
5393 reset-mon-cfg 3929 reset-mon-cfg {
5394 tempe 3930 temperature = <115000>;
5395 hyste 3931 hysteresis = <5000>;
5396 type 3932 type = "passive";
5397 }; 3933 };
5398 }; 3934 };
5399 }; 3935 };
5400 3936
5401 modem2-thermal { 3937 modem2-thermal {
>> 3938 polling-delay-passive = <0>;
>> 3939 polling-delay = <0>;
5402 thermal-sensors = <&t 3940 thermal-sensors = <&tsens1 12>;
5403 3941
5404 trips { 3942 trips {
5405 thermal-engin 3943 thermal-engine-config {
5406 tempe 3944 temperature = <125000>;
5407 hyste 3945 hysteresis = <1000>;
5408 type 3946 type = "passive";
5409 }; 3947 };
5410 3948
5411 mdmss2_config 3949 mdmss2_config0: mdmss2-config0 {
5412 tempe 3950 temperature = <102000>;
5413 hyste 3951 hysteresis = <3000>;
5414 type 3952 type = "passive";
5415 }; 3953 };
5416 3954
5417 mdmss2_config 3955 mdmss2_config1: mdmss2-config1 {
5418 tempe 3956 temperature = <105000>;
5419 hyste 3957 hysteresis = <3000>;
5420 type 3958 type = "passive";
5421 }; 3959 };
5422 3960
5423 reset-mon-cfg 3961 reset-mon-cfg {
5424 tempe 3962 temperature = <115000>;
5425 hyste 3963 hysteresis = <5000>;
5426 type 3964 type = "passive";
5427 }; 3965 };
5428 }; 3966 };
5429 }; 3967 };
5430 3968
5431 modem3-thermal { 3969 modem3-thermal {
>> 3970 polling-delay-passive = <0>;
>> 3971 polling-delay = <0>;
5432 thermal-sensors = <&t 3972 thermal-sensors = <&tsens1 13>;
5433 3973
5434 trips { 3974 trips {
5435 thermal-engin 3975 thermal-engine-config {
5436 tempe 3976 temperature = <125000>;
5437 hyste 3977 hysteresis = <1000>;
5438 type 3978 type = "passive";
5439 }; 3979 };
5440 3980
5441 mdmss3_config 3981 mdmss3_config0: mdmss3-config0 {
5442 tempe 3982 temperature = <102000>;
5443 hyste 3983 hysteresis = <3000>;
5444 type 3984 type = "passive";
5445 }; 3985 };
5446 3986
5447 mdmss3_config 3987 mdmss3_config1: mdmss3-config1 {
5448 tempe 3988 temperature = <105000>;
5449 hyste 3989 hysteresis = <3000>;
5450 type 3990 type = "passive";
5451 }; 3991 };
5452 3992
5453 reset-mon-cfg 3993 reset-mon-cfg {
5454 tempe 3994 temperature = <115000>;
5455 hyste 3995 hysteresis = <5000>;
5456 type 3996 type = "passive";
5457 }; 3997 };
5458 }; 3998 };
5459 }; 3999 };
5460 4000
5461 camera0-thermal { 4001 camera0-thermal {
>> 4002 polling-delay-passive = <0>;
>> 4003 polling-delay = <0>;
5462 thermal-sensors = <&t 4004 thermal-sensors = <&tsens1 14>;
5463 4005
5464 trips { 4006 trips {
5465 thermal-engin 4007 thermal-engine-config {
5466 tempe 4008 temperature = <125000>;
5467 hyste 4009 hysteresis = <1000>;
5468 type 4010 type = "passive";
5469 }; 4011 };
5470 4012
5471 reset-mon-cfg 4013 reset-mon-cfg {
5472 tempe 4014 temperature = <115000>;
5473 hyste 4015 hysteresis = <5000>;
5474 type 4016 type = "passive";
5475 }; 4017 };
5476 }; 4018 };
5477 }; 4019 };
5478 4020
5479 camera1-thermal { 4021 camera1-thermal {
>> 4022 polling-delay-passive = <0>;
>> 4023 polling-delay = <0>;
5480 thermal-sensors = <&t 4024 thermal-sensors = <&tsens1 15>;
5481 4025
5482 trips { 4026 trips {
5483 thermal-engin 4027 thermal-engine-config {
5484 tempe 4028 temperature = <125000>;
5485 hyste 4029 hysteresis = <1000>;
5486 type 4030 type = "passive";
5487 }; 4031 };
5488 4032
5489 reset-mon-cfg 4033 reset-mon-cfg {
5490 tempe 4034 temperature = <115000>;
5491 hyste 4035 hysteresis = <5000>;
5492 type 4036 type = "passive";
5493 }; 4037 };
5494 }; 4038 };
5495 }; 4039 };
5496 }; 4040 };
5497 4041
5498 timer { 4042 timer {
5499 compatible = "arm,armv8-timer 4043 compatible = "arm,armv8-timer";
5500 interrupts = <GIC_PPI 13 (GIC 4044 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5501 <GIC_PPI 14 (GIC 4045 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5502 <GIC_PPI 11 (GIC 4046 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5503 <GIC_PPI 10 (GIC 4047 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
5504 clock-frequency = <19200000>; 4048 clock-frequency = <19200000>;
5505 }; 4049 };
5506 }; 4050 };
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