1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * Copyright (c) 2021, Linaro Limited 3 * Copyright (c) 2021, Linaro Limited
4 */ 4 */
5 5
6 #include <dt-bindings/interrupt-controller/arm 6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-sm8450.h> 7 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
8 #include <dt-bindings/clock/qcom,rpmh.h> 8 #include <dt-bindings/clock/qcom,rpmh.h>
9 #include <dt-bindings/clock/qcom,sm8450-camcc. 9 #include <dt-bindings/clock/qcom,sm8450-camcc.h>
10 #include <dt-bindings/clock/qcom,sm8450-dispcc <<
11 #include <dt-bindings/clock/qcom,sm8450-gpucc. <<
12 #include <dt-bindings/clock/qcom,sm8450-videoc <<
13 #include <dt-bindings/dma/qcom-gpi.h> 10 #include <dt-bindings/dma/qcom-gpi.h>
14 #include <dt-bindings/firmware/qcom,scm.h> <<
15 #include <dt-bindings/gpio/gpio.h> 11 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/mailbox/qcom-ipcc.h> 12 #include <dt-bindings/mailbox/qcom-ipcc.h>
17 #include <dt-bindings/phy/phy-qcom-qmp.h> <<
18 #include <dt-bindings/power/qcom,rpmhpd.h> <<
19 #include <dt-bindings/power/qcom-rpmpd.h> 13 #include <dt-bindings/power/qcom-rpmpd.h>
20 #include <dt-bindings/interconnect/qcom,icc.h> <<
21 #include <dt-bindings/interconnect/qcom,sm8450 14 #include <dt-bindings/interconnect/qcom,sm8450.h>
22 #include <dt-bindings/reset/qcom,sm8450-gpucc. <<
23 #include <dt-bindings/soc/qcom,gpr.h> <<
24 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 15 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
25 #include <dt-bindings/sound/qcom,q6dsp-lpass-p <<
26 #include <dt-bindings/thermal/thermal.h> 16 #include <dt-bindings/thermal/thermal.h>
27 17
28 / { 18 / {
29 interrupt-parent = <&intc>; 19 interrupt-parent = <&intc>;
30 20
31 #address-cells = <2>; 21 #address-cells = <2>;
32 #size-cells = <2>; 22 #size-cells = <2>;
33 23
34 chosen { }; 24 chosen { };
35 25
36 clocks { 26 clocks {
37 xo_board: xo-board { 27 xo_board: xo-board {
38 compatible = "fixed-cl 28 compatible = "fixed-clock";
39 #clock-cells = <0>; 29 #clock-cells = <0>;
40 clock-frequency = <768 30 clock-frequency = <76800000>;
41 }; 31 };
42 32
43 sleep_clk: sleep-clk { 33 sleep_clk: sleep-clk {
44 compatible = "fixed-cl 34 compatible = "fixed-clock";
45 #clock-cells = <0>; 35 #clock-cells = <0>;
46 clock-frequency = <320 36 clock-frequency = <32000>;
47 }; 37 };
48 }; 38 };
49 39
50 cpus { 40 cpus {
51 #address-cells = <2>; 41 #address-cells = <2>;
52 #size-cells = <0>; 42 #size-cells = <0>;
53 43
54 CPU0: cpu@0 { 44 CPU0: cpu@0 {
55 device_type = "cpu"; 45 device_type = "cpu";
56 compatible = "qcom,kry 46 compatible = "qcom,kryo780";
57 reg = <0x0 0x0>; 47 reg = <0x0 0x0>;
58 enable-method = "psci" 48 enable-method = "psci";
59 next-level-cache = <&L 49 next-level-cache = <&L2_0>;
60 power-domains = <&CPU_ 50 power-domains = <&CPU_PD0>;
61 power-domain-names = " 51 power-domain-names = "psci";
62 qcom,freq-domain = <&c 52 qcom,freq-domain = <&cpufreq_hw 0>;
63 #cooling-cells = <2>; 53 #cooling-cells = <2>;
64 clocks = <&cpufreq_hw <<
65 L2_0: l2-cache { 54 L2_0: l2-cache {
66 compatible = " !! 55 compatible = "cache";
67 cache-level = !! 56 next-level-cache = <&L3_0>;
68 cache-unified; <<
69 next-level-cac <<
70 L3_0: l3-cache 57 L3_0: l3-cache {
71 compat !! 58 compatible = "cache";
72 cache- <<
73 cache- <<
74 }; 59 };
75 }; 60 };
76 }; 61 };
77 62
78 CPU1: cpu@100 { 63 CPU1: cpu@100 {
79 device_type = "cpu"; 64 device_type = "cpu";
80 compatible = "qcom,kry 65 compatible = "qcom,kryo780";
81 reg = <0x0 0x100>; 66 reg = <0x0 0x100>;
82 enable-method = "psci" 67 enable-method = "psci";
83 next-level-cache = <&L 68 next-level-cache = <&L2_100>;
84 power-domains = <&CPU_ 69 power-domains = <&CPU_PD1>;
85 power-domain-names = " 70 power-domain-names = "psci";
86 qcom,freq-domain = <&c 71 qcom,freq-domain = <&cpufreq_hw 0>;
87 #cooling-cells = <2>; 72 #cooling-cells = <2>;
88 clocks = <&cpufreq_hw <<
89 L2_100: l2-cache { 73 L2_100: l2-cache {
90 compatible = " !! 74 compatible = "cache";
91 cache-level = !! 75 next-level-cache = <&L3_0>;
92 cache-unified; <<
93 next-level-cac <<
94 }; 76 };
95 }; 77 };
96 78
97 CPU2: cpu@200 { 79 CPU2: cpu@200 {
98 device_type = "cpu"; 80 device_type = "cpu";
99 compatible = "qcom,kry 81 compatible = "qcom,kryo780";
100 reg = <0x0 0x200>; 82 reg = <0x0 0x200>;
101 enable-method = "psci" 83 enable-method = "psci";
102 next-level-cache = <&L 84 next-level-cache = <&L2_200>;
103 power-domains = <&CPU_ 85 power-domains = <&CPU_PD2>;
104 power-domain-names = " 86 power-domain-names = "psci";
105 qcom,freq-domain = <&c 87 qcom,freq-domain = <&cpufreq_hw 0>;
106 #cooling-cells = <2>; 88 #cooling-cells = <2>;
107 clocks = <&cpufreq_hw <<
108 L2_200: l2-cache { 89 L2_200: l2-cache {
109 compatible = " !! 90 compatible = "cache";
110 cache-level = !! 91 next-level-cache = <&L3_0>;
111 cache-unified; <<
112 next-level-cac <<
113 }; 92 };
114 }; 93 };
115 94
116 CPU3: cpu@300 { 95 CPU3: cpu@300 {
117 device_type = "cpu"; 96 device_type = "cpu";
118 compatible = "qcom,kry 97 compatible = "qcom,kryo780";
119 reg = <0x0 0x300>; 98 reg = <0x0 0x300>;
120 enable-method = "psci" 99 enable-method = "psci";
121 next-level-cache = <&L 100 next-level-cache = <&L2_300>;
122 power-domains = <&CPU_ 101 power-domains = <&CPU_PD3>;
123 power-domain-names = " 102 power-domain-names = "psci";
124 qcom,freq-domain = <&c 103 qcom,freq-domain = <&cpufreq_hw 0>;
125 #cooling-cells = <2>; 104 #cooling-cells = <2>;
126 clocks = <&cpufreq_hw <<
127 L2_300: l2-cache { 105 L2_300: l2-cache {
128 compatible = " !! 106 compatible = "cache";
129 cache-level = !! 107 next-level-cache = <&L3_0>;
130 cache-unified; <<
131 next-level-cac <<
132 }; 108 };
133 }; 109 };
134 110
135 CPU4: cpu@400 { 111 CPU4: cpu@400 {
136 device_type = "cpu"; 112 device_type = "cpu";
137 compatible = "qcom,kry 113 compatible = "qcom,kryo780";
138 reg = <0x0 0x400>; 114 reg = <0x0 0x400>;
139 enable-method = "psci" 115 enable-method = "psci";
140 next-level-cache = <&L 116 next-level-cache = <&L2_400>;
141 power-domains = <&CPU_ 117 power-domains = <&CPU_PD4>;
142 power-domain-names = " 118 power-domain-names = "psci";
143 qcom,freq-domain = <&c 119 qcom,freq-domain = <&cpufreq_hw 1>;
144 #cooling-cells = <2>; 120 #cooling-cells = <2>;
145 clocks = <&cpufreq_hw <<
146 L2_400: l2-cache { 121 L2_400: l2-cache {
147 compatible = " !! 122 compatible = "cache";
148 cache-level = !! 123 next-level-cache = <&L3_0>;
149 cache-unified; <<
150 next-level-cac <<
151 }; 124 };
152 }; 125 };
153 126
154 CPU5: cpu@500 { 127 CPU5: cpu@500 {
155 device_type = "cpu"; 128 device_type = "cpu";
156 compatible = "qcom,kry 129 compatible = "qcom,kryo780";
157 reg = <0x0 0x500>; 130 reg = <0x0 0x500>;
158 enable-method = "psci" 131 enable-method = "psci";
159 next-level-cache = <&L 132 next-level-cache = <&L2_500>;
160 power-domains = <&CPU_ 133 power-domains = <&CPU_PD5>;
161 power-domain-names = " 134 power-domain-names = "psci";
162 qcom,freq-domain = <&c 135 qcom,freq-domain = <&cpufreq_hw 1>;
163 #cooling-cells = <2>; 136 #cooling-cells = <2>;
164 clocks = <&cpufreq_hw <<
165 L2_500: l2-cache { 137 L2_500: l2-cache {
166 compatible = " !! 138 compatible = "cache";
167 cache-level = !! 139 next-level-cache = <&L3_0>;
168 cache-unified; <<
169 next-level-cac <<
170 }; 140 };
>> 141
171 }; 142 };
172 143
173 CPU6: cpu@600 { 144 CPU6: cpu@600 {
174 device_type = "cpu"; 145 device_type = "cpu";
175 compatible = "qcom,kry 146 compatible = "qcom,kryo780";
176 reg = <0x0 0x600>; 147 reg = <0x0 0x600>;
177 enable-method = "psci" 148 enable-method = "psci";
178 next-level-cache = <&L 149 next-level-cache = <&L2_600>;
179 power-domains = <&CPU_ 150 power-domains = <&CPU_PD6>;
180 power-domain-names = " 151 power-domain-names = "psci";
181 qcom,freq-domain = <&c 152 qcom,freq-domain = <&cpufreq_hw 1>;
182 #cooling-cells = <2>; 153 #cooling-cells = <2>;
183 clocks = <&cpufreq_hw <<
184 L2_600: l2-cache { 154 L2_600: l2-cache {
185 compatible = " !! 155 compatible = "cache";
186 cache-level = !! 156 next-level-cache = <&L3_0>;
187 cache-unified; <<
188 next-level-cac <<
189 }; 157 };
190 }; 158 };
191 159
192 CPU7: cpu@700 { 160 CPU7: cpu@700 {
193 device_type = "cpu"; 161 device_type = "cpu";
194 compatible = "qcom,kry 162 compatible = "qcom,kryo780";
195 reg = <0x0 0x700>; 163 reg = <0x0 0x700>;
196 enable-method = "psci" 164 enable-method = "psci";
197 next-level-cache = <&L 165 next-level-cache = <&L2_700>;
198 power-domains = <&CPU_ 166 power-domains = <&CPU_PD7>;
199 power-domain-names = " 167 power-domain-names = "psci";
200 qcom,freq-domain = <&c 168 qcom,freq-domain = <&cpufreq_hw 2>;
201 #cooling-cells = <2>; 169 #cooling-cells = <2>;
202 clocks = <&cpufreq_hw <<
203 L2_700: l2-cache { 170 L2_700: l2-cache {
204 compatible = " !! 171 compatible = "cache";
205 cache-level = !! 172 next-level-cache = <&L3_0>;
206 cache-unified; <<
207 next-level-cac <<
208 }; 173 };
209 }; 174 };
210 175
211 cpu-map { 176 cpu-map {
212 cluster0 { 177 cluster0 {
213 core0 { 178 core0 {
214 cpu = 179 cpu = <&CPU0>;
215 }; 180 };
216 181
217 core1 { 182 core1 {
218 cpu = 183 cpu = <&CPU1>;
219 }; 184 };
220 185
221 core2 { 186 core2 {
222 cpu = 187 cpu = <&CPU2>;
223 }; 188 };
224 189
225 core3 { 190 core3 {
226 cpu = 191 cpu = <&CPU3>;
227 }; 192 };
228 193
229 core4 { 194 core4 {
230 cpu = 195 cpu = <&CPU4>;
231 }; 196 };
232 197
233 core5 { 198 core5 {
234 cpu = 199 cpu = <&CPU5>;
235 }; 200 };
236 201
237 core6 { 202 core6 {
238 cpu = 203 cpu = <&CPU6>;
239 }; 204 };
240 205
241 core7 { 206 core7 {
242 cpu = 207 cpu = <&CPU7>;
243 }; 208 };
244 }; 209 };
245 }; 210 };
246 211
247 idle-states { 212 idle-states {
248 entry-method = "psci"; 213 entry-method = "psci";
249 214
250 LITTLE_CPU_SLEEP_0: cp 215 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
251 compatible = " 216 compatible = "arm,idle-state";
252 idle-state-nam 217 idle-state-name = "silver-rail-power-collapse";
253 arm,psci-suspe 218 arm,psci-suspend-param = <0x40000004>;
254 entry-latency- 219 entry-latency-us = <800>;
255 exit-latency-u 220 exit-latency-us = <750>;
256 min-residency- 221 min-residency-us = <4090>;
257 local-timer-st 222 local-timer-stop;
258 }; 223 };
259 224
260 BIG_CPU_SLEEP_0: cpu-s 225 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
261 compatible = " 226 compatible = "arm,idle-state";
262 idle-state-nam 227 idle-state-name = "gold-rail-power-collapse";
263 arm,psci-suspe 228 arm,psci-suspend-param = <0x40000004>;
264 entry-latency- 229 entry-latency-us = <600>;
265 exit-latency-u 230 exit-latency-us = <1550>;
266 min-residency- 231 min-residency-us = <4791>;
267 local-timer-st 232 local-timer-stop;
268 }; 233 };
269 }; 234 };
270 235
271 domain-idle-states { 236 domain-idle-states {
272 CLUSTER_SLEEP_0: clust 237 CLUSTER_SLEEP_0: cluster-sleep-0 {
273 compatible = " 238 compatible = "domain-idle-state";
>> 239 idle-state-name = "cluster-l3-off";
274 arm,psci-suspe 240 arm,psci-suspend-param = <0x41000044>;
275 entry-latency- 241 entry-latency-us = <1050>;
276 exit-latency-u 242 exit-latency-us = <2500>;
277 min-residency- 243 min-residency-us = <5309>;
>> 244 local-timer-stop;
278 }; 245 };
279 246
280 CLUSTER_SLEEP_1: clust 247 CLUSTER_SLEEP_1: cluster-sleep-1 {
281 compatible = " 248 compatible = "domain-idle-state";
>> 249 idle-state-name = "cluster-power-collapse";
282 arm,psci-suspe 250 arm,psci-suspend-param = <0x4100c344>;
283 entry-latency- 251 entry-latency-us = <2700>;
284 exit-latency-u 252 exit-latency-us = <3500>;
285 min-residency- 253 min-residency-us = <13959>;
>> 254 local-timer-stop;
286 }; 255 };
287 }; 256 };
288 }; 257 };
289 258
290 firmware { 259 firmware {
291 scm: scm { 260 scm: scm {
292 compatible = "qcom,scm 261 compatible = "qcom,scm-sm8450", "qcom,scm";
293 qcom,dload-mode = <&tc <<
294 interconnects = <&aggr 262 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
295 #reset-cells = <1>; 263 #reset-cells = <1>;
296 }; 264 };
297 }; 265 };
298 266
299 clk_virt: interconnect-0 { 267 clk_virt: interconnect-0 {
300 compatible = "qcom,sm8450-clk- 268 compatible = "qcom,sm8450-clk-virt";
301 #interconnect-cells = <2>; 269 #interconnect-cells = <2>;
302 qcom,bcm-voters = <&apps_bcm_v 270 qcom,bcm-voters = <&apps_bcm_voter>;
303 }; 271 };
304 272
305 mc_virt: interconnect-1 { 273 mc_virt: interconnect-1 {
306 compatible = "qcom,sm8450-mc-v 274 compatible = "qcom,sm8450-mc-virt";
307 #interconnect-cells = <2>; 275 #interconnect-cells = <2>;
308 qcom,bcm-voters = <&apps_bcm_v 276 qcom,bcm-voters = <&apps_bcm_voter>;
309 }; 277 };
310 278
311 memory@a0000000 { 279 memory@a0000000 {
312 device_type = "memory"; 280 device_type = "memory";
313 /* We expect the bootloader to 281 /* We expect the bootloader to fill in the size */
314 reg = <0x0 0xa0000000 0x0 0x0> 282 reg = <0x0 0xa0000000 0x0 0x0>;
315 }; 283 };
316 284
317 pmu { 285 pmu {
318 compatible = "arm,armv8-pmuv3" 286 compatible = "arm,armv8-pmuv3";
319 interrupts = <GIC_PPI 7 IRQ_TY 287 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
320 }; 288 };
321 289
322 psci { 290 psci {
323 compatible = "arm,psci-1.0"; 291 compatible = "arm,psci-1.0";
324 method = "smc"; 292 method = "smc";
325 293
326 CPU_PD0: power-domain-cpu0 { !! 294 CPU_PD0: cpu0 {
327 #power-domain-cells = 295 #power-domain-cells = <0>;
328 power-domains = <&CLUS 296 power-domains = <&CLUSTER_PD>;
329 domain-idle-states = < 297 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
330 }; 298 };
331 299
332 CPU_PD1: power-domain-cpu1 { !! 300 CPU_PD1: cpu1 {
333 #power-domain-cells = 301 #power-domain-cells = <0>;
334 power-domains = <&CLUS 302 power-domains = <&CLUSTER_PD>;
335 domain-idle-states = < 303 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
336 }; 304 };
337 305
338 CPU_PD2: power-domain-cpu2 { !! 306 CPU_PD2: cpu2 {
339 #power-domain-cells = 307 #power-domain-cells = <0>;
340 power-domains = <&CLUS 308 power-domains = <&CLUSTER_PD>;
341 domain-idle-states = < 309 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
342 }; 310 };
343 311
344 CPU_PD3: power-domain-cpu3 { !! 312 CPU_PD3: cpu3 {
345 #power-domain-cells = 313 #power-domain-cells = <0>;
346 power-domains = <&CLUS 314 power-domains = <&CLUSTER_PD>;
347 domain-idle-states = < 315 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
348 }; 316 };
349 317
350 CPU_PD4: power-domain-cpu4 { !! 318 CPU_PD4: cpu4 {
351 #power-domain-cells = 319 #power-domain-cells = <0>;
352 power-domains = <&CLUS 320 power-domains = <&CLUSTER_PD>;
353 domain-idle-states = < 321 domain-idle-states = <&BIG_CPU_SLEEP_0>;
354 }; 322 };
355 323
356 CPU_PD5: power-domain-cpu5 { !! 324 CPU_PD5: cpu5 {
357 #power-domain-cells = 325 #power-domain-cells = <0>;
358 power-domains = <&CLUS 326 power-domains = <&CLUSTER_PD>;
359 domain-idle-states = < 327 domain-idle-states = <&BIG_CPU_SLEEP_0>;
360 }; 328 };
361 329
362 CPU_PD6: power-domain-cpu6 { !! 330 CPU_PD6: cpu6 {
363 #power-domain-cells = 331 #power-domain-cells = <0>;
364 power-domains = <&CLUS 332 power-domains = <&CLUSTER_PD>;
365 domain-idle-states = < 333 domain-idle-states = <&BIG_CPU_SLEEP_0>;
366 }; 334 };
367 335
368 CPU_PD7: power-domain-cpu7 { !! 336 CPU_PD7: cpu7 {
369 #power-domain-cells = 337 #power-domain-cells = <0>;
370 power-domains = <&CLUS 338 power-domains = <&CLUSTER_PD>;
371 domain-idle-states = < 339 domain-idle-states = <&BIG_CPU_SLEEP_0>;
372 }; 340 };
373 341
374 CLUSTER_PD: power-domain-cpu-c !! 342 CLUSTER_PD: cpu-cluster0 {
375 #power-domain-cells = 343 #power-domain-cells = <0>;
376 domain-idle-states = < 344 domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>;
377 }; 345 };
378 }; 346 };
379 347
380 qup_opp_table_100mhz: opp-table-qup { 348 qup_opp_table_100mhz: opp-table-qup {
381 compatible = "operating-points 349 compatible = "operating-points-v2";
382 350
383 opp-50000000 { 351 opp-50000000 {
384 opp-hz = /bits/ 64 <50 352 opp-hz = /bits/ 64 <50000000>;
385 required-opps = <&rpmh 353 required-opps = <&rpmhpd_opp_min_svs>;
386 }; 354 };
387 355
388 opp-75000000 { 356 opp-75000000 {
389 opp-hz = /bits/ 64 <75 357 opp-hz = /bits/ 64 <75000000>;
390 required-opps = <&rpmh 358 required-opps = <&rpmhpd_opp_low_svs>;
391 }; 359 };
392 360
393 opp-100000000 { 361 opp-100000000 {
394 opp-hz = /bits/ 64 <10 362 opp-hz = /bits/ 64 <100000000>;
395 required-opps = <&rpmh 363 required-opps = <&rpmhpd_opp_svs>;
396 }; 364 };
397 }; 365 };
398 366
399 reserved_memory: reserved-memory { 367 reserved_memory: reserved-memory {
400 #address-cells = <2>; 368 #address-cells = <2>;
401 #size-cells = <2>; 369 #size-cells = <2>;
402 ranges; 370 ranges;
403 371
404 hyp_mem: memory@80000000 { 372 hyp_mem: memory@80000000 {
405 reg = <0x0 0x80000000 373 reg = <0x0 0x80000000 0x0 0x600000>;
406 no-map; 374 no-map;
407 }; 375 };
408 376
409 xbl_dt_log_mem: memory@8060000 377 xbl_dt_log_mem: memory@80600000 {
410 reg = <0x0 0x80600000 378 reg = <0x0 0x80600000 0x0 0x40000>;
411 no-map; 379 no-map;
412 }; 380 };
413 381
414 xbl_ramdump_mem: memory@806400 382 xbl_ramdump_mem: memory@80640000 {
415 reg = <0x0 0x80640000 383 reg = <0x0 0x80640000 0x0 0x180000>;
416 no-map; 384 no-map;
417 }; 385 };
418 386
419 xbl_sc_mem: memory@807c0000 { 387 xbl_sc_mem: memory@807c0000 {
420 reg = <0x0 0x807c0000 388 reg = <0x0 0x807c0000 0x0 0x40000>;
421 no-map; 389 no-map;
422 }; 390 };
423 391
424 aop_image_mem: memory@80800000 392 aop_image_mem: memory@80800000 {
425 reg = <0x0 0x80800000 393 reg = <0x0 0x80800000 0x0 0x60000>;
426 no-map; 394 no-map;
427 }; 395 };
428 396
429 aop_cmd_db_mem: memory@8086000 397 aop_cmd_db_mem: memory@80860000 {
430 compatible = "qcom,cmd 398 compatible = "qcom,cmd-db";
431 reg = <0x0 0x80860000 399 reg = <0x0 0x80860000 0x0 0x20000>;
432 no-map; 400 no-map;
433 }; 401 };
434 402
435 aop_config_mem: memory@8088000 403 aop_config_mem: memory@80880000 {
436 reg = <0x0 0x80880000 404 reg = <0x0 0x80880000 0x0 0x20000>;
437 no-map; 405 no-map;
438 }; 406 };
439 407
440 tme_crash_dump_mem: memory@808 408 tme_crash_dump_mem: memory@808a0000 {
441 reg = <0x0 0x808a0000 409 reg = <0x0 0x808a0000 0x0 0x40000>;
442 no-map; 410 no-map;
443 }; 411 };
444 412
445 tme_log_mem: memory@808e0000 { 413 tme_log_mem: memory@808e0000 {
446 reg = <0x0 0x808e0000 414 reg = <0x0 0x808e0000 0x0 0x4000>;
447 no-map; 415 no-map;
448 }; 416 };
449 417
450 uefi_log_mem: memory@808e4000 418 uefi_log_mem: memory@808e4000 {
451 reg = <0x0 0x808e4000 419 reg = <0x0 0x808e4000 0x0 0x10000>;
452 no-map; 420 no-map;
453 }; 421 };
454 422
455 /* secdata region can be reuse 423 /* secdata region can be reused by apps */
456 smem: memory@80900000 { 424 smem: memory@80900000 {
457 compatible = "qcom,sme 425 compatible = "qcom,smem";
458 reg = <0x0 0x80900000 426 reg = <0x0 0x80900000 0x0 0x200000>;
459 hwlocks = <&tcsr_mutex 427 hwlocks = <&tcsr_mutex 3>;
460 no-map; 428 no-map;
461 }; 429 };
462 430
463 cpucp_fw_mem: memory@80b00000 431 cpucp_fw_mem: memory@80b00000 {
464 reg = <0x0 0x80b00000 432 reg = <0x0 0x80b00000 0x0 0x100000>;
465 no-map; 433 no-map;
466 }; 434 };
467 435
468 cdsp_secure_heap: memory@80c00 436 cdsp_secure_heap: memory@80c00000 {
469 reg = <0x0 0x80c00000 437 reg = <0x0 0x80c00000 0x0 0x4600000>;
470 no-map; 438 no-map;
471 }; 439 };
472 440
473 video_mem: memory@85700000 { 441 video_mem: memory@85700000 {
474 reg = <0x0 0x85700000 442 reg = <0x0 0x85700000 0x0 0x700000>;
475 no-map; 443 no-map;
476 }; 444 };
477 445
478 adsp_mem: memory@85e00000 { 446 adsp_mem: memory@85e00000 {
479 reg = <0x0 0x85e00000 447 reg = <0x0 0x85e00000 0x0 0x2100000>;
480 no-map; 448 no-map;
481 }; 449 };
482 450
483 slpi_mem: memory@88000000 { 451 slpi_mem: memory@88000000 {
484 reg = <0x0 0x88000000 452 reg = <0x0 0x88000000 0x0 0x1900000>;
485 no-map; 453 no-map;
486 }; 454 };
487 455
488 cdsp_mem: memory@89900000 { 456 cdsp_mem: memory@89900000 {
489 reg = <0x0 0x89900000 457 reg = <0x0 0x89900000 0x0 0x2000000>;
490 no-map; 458 no-map;
491 }; 459 };
492 460
493 ipa_fw_mem: memory@8b900000 { 461 ipa_fw_mem: memory@8b900000 {
494 reg = <0x0 0x8b900000 462 reg = <0x0 0x8b900000 0x0 0x10000>;
495 no-map; 463 no-map;
496 }; 464 };
497 465
498 ipa_gsi_mem: memory@8b910000 { 466 ipa_gsi_mem: memory@8b910000 {
499 reg = <0x0 0x8b910000 467 reg = <0x0 0x8b910000 0x0 0xa000>;
500 no-map; 468 no-map;
501 }; 469 };
502 470
503 gpu_micro_code_mem: memory@8b9 471 gpu_micro_code_mem: memory@8b91a000 {
504 reg = <0x0 0x8b91a000 472 reg = <0x0 0x8b91a000 0x0 0x2000>;
505 no-map; 473 no-map;
506 }; 474 };
507 475
508 spss_region_mem: memory@8ba000 476 spss_region_mem: memory@8ba00000 {
509 reg = <0x0 0x8ba00000 477 reg = <0x0 0x8ba00000 0x0 0x180000>;
510 no-map; 478 no-map;
511 }; 479 };
512 480
513 /* First part of the "SPU secu 481 /* First part of the "SPU secure shared memory" region */
514 spu_tz_shared_mem: memory@8bb8 482 spu_tz_shared_mem: memory@8bb80000 {
515 reg = <0x0 0x8bb80000 483 reg = <0x0 0x8bb80000 0x0 0x60000>;
516 no-map; 484 no-map;
517 }; 485 };
518 486
519 /* Second part of the "SPU sec 487 /* Second part of the "SPU secure shared memory" region */
520 spu_modem_shared_mem: memory@8 488 spu_modem_shared_mem: memory@8bbe0000 {
521 reg = <0x0 0x8bbe0000 489 reg = <0x0 0x8bbe0000 0x0 0x20000>;
522 no-map; 490 no-map;
523 }; 491 };
524 492
525 mpss_mem: memory@8bc00000 { 493 mpss_mem: memory@8bc00000 {
526 reg = <0x0 0x8bc00000 494 reg = <0x0 0x8bc00000 0x0 0x13200000>;
527 no-map; 495 no-map;
528 }; 496 };
529 497
530 cvp_mem: memory@9ee00000 { 498 cvp_mem: memory@9ee00000 {
531 reg = <0x0 0x9ee00000 499 reg = <0x0 0x9ee00000 0x0 0x700000>;
532 no-map; 500 no-map;
533 }; 501 };
534 502
535 camera_mem: memory@9f500000 { 503 camera_mem: memory@9f500000 {
536 reg = <0x0 0x9f500000 504 reg = <0x0 0x9f500000 0x0 0x800000>;
537 no-map; 505 no-map;
538 }; 506 };
539 507
540 rmtfs_mem: memory@9fd00000 { 508 rmtfs_mem: memory@9fd00000 {
541 compatible = "qcom,rmt 509 compatible = "qcom,rmtfs-mem";
542 reg = <0x0 0x9fd00000 510 reg = <0x0 0x9fd00000 0x0 0x280000>;
543 no-map; 511 no-map;
544 512
545 qcom,client-id = <1>; 513 qcom,client-id = <1>;
546 qcom,vmid = <QCOM_SCM_ !! 514 qcom,vmid = <15>;
547 }; 515 };
548 516
549 xbl_sc_mem2: memory@a6e00000 { 517 xbl_sc_mem2: memory@a6e00000 {
550 reg = <0x0 0xa6e00000 518 reg = <0x0 0xa6e00000 0x0 0x40000>;
551 no-map; 519 no-map;
552 }; 520 };
553 521
554 global_sync_mem: memory@a6f000 522 global_sync_mem: memory@a6f00000 {
555 reg = <0x0 0xa6f00000 523 reg = <0x0 0xa6f00000 0x0 0x100000>;
556 no-map; 524 no-map;
557 }; 525 };
558 526
559 /* uefi region can be reused b 527 /* uefi region can be reused by APPS */
560 528
561 /* Linux kernel image is loade 529 /* Linux kernel image is loaded at 0xa0000000 */
562 530
563 oem_vm_mem: memory@bb000000 { 531 oem_vm_mem: memory@bb000000 {
564 reg = <0x0 0xbb000000 532 reg = <0x0 0xbb000000 0x0 0x5000000>;
565 no-map; 533 no-map;
566 }; 534 };
567 535
568 mte_mem: memory@c0000000 { 536 mte_mem: memory@c0000000 {
569 reg = <0x0 0xc0000000 537 reg = <0x0 0xc0000000 0x0 0x20000000>;
570 no-map; 538 no-map;
571 }; 539 };
572 540
573 qheebsp_reserved_mem: memory@e 541 qheebsp_reserved_mem: memory@e0000000 {
574 reg = <0x0 0xe0000000 542 reg = <0x0 0xe0000000 0x0 0x600000>;
575 no-map; 543 no-map;
576 }; 544 };
577 545
578 cpusys_vm_mem: memory@e0600000 546 cpusys_vm_mem: memory@e0600000 {
579 reg = <0x0 0xe0600000 547 reg = <0x0 0xe0600000 0x0 0x400000>;
580 no-map; 548 no-map;
581 }; 549 };
582 550
583 hyp_reserved_mem: memory@e0a00 551 hyp_reserved_mem: memory@e0a00000 {
584 reg = <0x0 0xe0a00000 552 reg = <0x0 0xe0a00000 0x0 0x100000>;
585 no-map; 553 no-map;
586 }; 554 };
587 555
588 trust_ui_vm_mem: memory@e0b000 556 trust_ui_vm_mem: memory@e0b00000 {
589 reg = <0x0 0xe0b00000 557 reg = <0x0 0xe0b00000 0x0 0x4af3000>;
590 no-map; 558 no-map;
591 }; 559 };
592 560
593 trust_ui_vm_qrtr: memory@e55f3 561 trust_ui_vm_qrtr: memory@e55f3000 {
594 reg = <0x0 0xe55f3000 562 reg = <0x0 0xe55f3000 0x0 0x9000>;
595 no-map; 563 no-map;
596 }; 564 };
597 565
598 trust_ui_vm_vblk0_ring: memory 566 trust_ui_vm_vblk0_ring: memory@e55fc000 {
599 reg = <0x0 0xe55fc000 567 reg = <0x0 0xe55fc000 0x0 0x4000>;
600 no-map; 568 no-map;
601 }; 569 };
602 570
603 trust_ui_vm_swiotlb: memory@e5 571 trust_ui_vm_swiotlb: memory@e5600000 {
604 reg = <0x0 0xe5600000 572 reg = <0x0 0xe5600000 0x0 0x100000>;
605 no-map; 573 no-map;
606 }; 574 };
607 575
608 tz_stat_mem: memory@e8800000 { 576 tz_stat_mem: memory@e8800000 {
609 reg = <0x0 0xe8800000 577 reg = <0x0 0xe8800000 0x0 0x100000>;
610 no-map; 578 no-map;
611 }; 579 };
612 580
613 tags_mem: memory@e8900000 { 581 tags_mem: memory@e8900000 {
614 reg = <0x0 0xe8900000 582 reg = <0x0 0xe8900000 0x0 0x1200000>;
615 no-map; 583 no-map;
616 }; 584 };
617 585
618 qtee_mem: memory@e9b00000 { 586 qtee_mem: memory@e9b00000 {
619 reg = <0x0 0xe9b00000 587 reg = <0x0 0xe9b00000 0x0 0x500000>;
620 no-map; 588 no-map;
621 }; 589 };
622 590
623 trusted_apps_mem: memory@ea000 591 trusted_apps_mem: memory@ea000000 {
624 reg = <0x0 0xea000000 592 reg = <0x0 0xea000000 0x0 0x3900000>;
625 no-map; 593 no-map;
626 }; 594 };
627 595
628 trusted_apps_ext_mem: memory@e 596 trusted_apps_ext_mem: memory@ed900000 {
629 reg = <0x0 0xed900000 597 reg = <0x0 0xed900000 0x0 0x3b00000>;
630 no-map; 598 no-map;
631 }; 599 };
632 }; 600 };
633 601
634 smp2p-adsp { 602 smp2p-adsp {
635 compatible = "qcom,smp2p"; 603 compatible = "qcom,smp2p";
636 qcom,smem = <443>, <429>; 604 qcom,smem = <443>, <429>;
637 interrupts-extended = <&ipcc I 605 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
638 I 606 IPCC_MPROC_SIGNAL_SMP2P
639 I 607 IRQ_TYPE_EDGE_RISING>;
640 mboxes = <&ipcc IPCC_CLIENT_LP 608 mboxes = <&ipcc IPCC_CLIENT_LPASS
641 IPCC_MPROC_SIG 609 IPCC_MPROC_SIGNAL_SMP2P>;
642 610
643 qcom,local-pid = <0>; 611 qcom,local-pid = <0>;
644 qcom,remote-pid = <2>; 612 qcom,remote-pid = <2>;
645 613
646 smp2p_adsp_out: master-kernel 614 smp2p_adsp_out: master-kernel {
647 qcom,entry-name = "mas 615 qcom,entry-name = "master-kernel";
648 #qcom,smem-state-cells 616 #qcom,smem-state-cells = <1>;
649 }; 617 };
650 618
651 smp2p_adsp_in: slave-kernel { 619 smp2p_adsp_in: slave-kernel {
652 qcom,entry-name = "sla 620 qcom,entry-name = "slave-kernel";
653 interrupt-controller; 621 interrupt-controller;
654 #interrupt-cells = <2> 622 #interrupt-cells = <2>;
655 }; 623 };
656 }; 624 };
657 625
658 smp2p-cdsp { 626 smp2p-cdsp {
659 compatible = "qcom,smp2p"; 627 compatible = "qcom,smp2p";
660 qcom,smem = <94>, <432>; 628 qcom,smem = <94>, <432>;
661 interrupts-extended = <&ipcc I 629 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
662 I 630 IPCC_MPROC_SIGNAL_SMP2P
663 I 631 IRQ_TYPE_EDGE_RISING>;
664 mboxes = <&ipcc IPCC_CLIENT_CD 632 mboxes = <&ipcc IPCC_CLIENT_CDSP
665 IPCC_MPROC_SIG 633 IPCC_MPROC_SIGNAL_SMP2P>;
666 634
667 qcom,local-pid = <0>; 635 qcom,local-pid = <0>;
668 qcom,remote-pid = <5>; 636 qcom,remote-pid = <5>;
669 637
670 smp2p_cdsp_out: master-kernel 638 smp2p_cdsp_out: master-kernel {
671 qcom,entry-name = "mas 639 qcom,entry-name = "master-kernel";
672 #qcom,smem-state-cells 640 #qcom,smem-state-cells = <1>;
673 }; 641 };
674 642
675 smp2p_cdsp_in: slave-kernel { 643 smp2p_cdsp_in: slave-kernel {
676 qcom,entry-name = "sla 644 qcom,entry-name = "slave-kernel";
677 interrupt-controller; 645 interrupt-controller;
678 #interrupt-cells = <2> 646 #interrupt-cells = <2>;
679 }; 647 };
680 }; 648 };
681 649
682 smp2p-modem { 650 smp2p-modem {
683 compatible = "qcom,smp2p"; 651 compatible = "qcom,smp2p";
684 qcom,smem = <435>, <428>; 652 qcom,smem = <435>, <428>;
685 interrupts-extended = <&ipcc I 653 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
686 I 654 IPCC_MPROC_SIGNAL_SMP2P
687 I 655 IRQ_TYPE_EDGE_RISING>;
688 mboxes = <&ipcc IPCC_CLIENT_MP 656 mboxes = <&ipcc IPCC_CLIENT_MPSS
689 IPCC_MPROC_SIG 657 IPCC_MPROC_SIGNAL_SMP2P>;
690 658
691 qcom,local-pid = <0>; 659 qcom,local-pid = <0>;
692 qcom,remote-pid = <1>; 660 qcom,remote-pid = <1>;
693 661
694 smp2p_modem_out: master-kernel 662 smp2p_modem_out: master-kernel {
695 qcom,entry-name = "mas 663 qcom,entry-name = "master-kernel";
696 #qcom,smem-state-cells 664 #qcom,smem-state-cells = <1>;
697 }; 665 };
698 666
699 smp2p_modem_in: slave-kernel { 667 smp2p_modem_in: slave-kernel {
700 qcom,entry-name = "sla 668 qcom,entry-name = "slave-kernel";
701 interrupt-controller; 669 interrupt-controller;
702 #interrupt-cells = <2> 670 #interrupt-cells = <2>;
703 }; 671 };
704 672
705 ipa_smp2p_out: ipa-ap-to-modem 673 ipa_smp2p_out: ipa-ap-to-modem {
706 qcom,entry-name = "ipa 674 qcom,entry-name = "ipa";
707 #qcom,smem-state-cells 675 #qcom,smem-state-cells = <1>;
708 }; 676 };
709 677
710 ipa_smp2p_in: ipa-modem-to-ap 678 ipa_smp2p_in: ipa-modem-to-ap {
711 qcom,entry-name = "ipa 679 qcom,entry-name = "ipa";
712 interrupt-controller; 680 interrupt-controller;
713 #interrupt-cells = <2> 681 #interrupt-cells = <2>;
714 }; 682 };
715 }; 683 };
716 684
717 smp2p-slpi { 685 smp2p-slpi {
718 compatible = "qcom,smp2p"; 686 compatible = "qcom,smp2p";
719 qcom,smem = <481>, <430>; 687 qcom,smem = <481>, <430>;
720 interrupts-extended = <&ipcc I 688 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
721 I 689 IPCC_MPROC_SIGNAL_SMP2P
722 I 690 IRQ_TYPE_EDGE_RISING>;
723 mboxes = <&ipcc IPCC_CLIENT_SL 691 mboxes = <&ipcc IPCC_CLIENT_SLPI
724 IPCC_MPROC_SIG 692 IPCC_MPROC_SIGNAL_SMP2P>;
725 693
726 qcom,local-pid = <0>; 694 qcom,local-pid = <0>;
727 qcom,remote-pid = <3>; 695 qcom,remote-pid = <3>;
728 696
729 smp2p_slpi_out: master-kernel 697 smp2p_slpi_out: master-kernel {
730 qcom,entry-name = "mas 698 qcom,entry-name = "master-kernel";
731 #qcom,smem-state-cells 699 #qcom,smem-state-cells = <1>;
732 }; 700 };
733 701
734 smp2p_slpi_in: slave-kernel { 702 smp2p_slpi_in: slave-kernel {
735 qcom,entry-name = "sla 703 qcom,entry-name = "slave-kernel";
736 interrupt-controller; 704 interrupt-controller;
737 #interrupt-cells = <2> 705 #interrupt-cells = <2>;
738 }; 706 };
739 }; 707 };
740 708
741 soc: soc@0 { 709 soc: soc@0 {
742 #address-cells = <2>; 710 #address-cells = <2>;
743 #size-cells = <2>; 711 #size-cells = <2>;
744 ranges = <0 0 0 0 0x10 0>; 712 ranges = <0 0 0 0 0x10 0>;
745 dma-ranges = <0 0 0 0 0x10 0>; 713 dma-ranges = <0 0 0 0 0x10 0>;
746 compatible = "simple-bus"; 714 compatible = "simple-bus";
747 715
748 gcc: clock-controller@100000 { 716 gcc: clock-controller@100000 {
749 compatible = "qcom,gcc 717 compatible = "qcom,gcc-sm8450";
750 reg = <0x0 0x00100000 718 reg = <0x0 0x00100000 0x0 0x1f4200>;
751 #clock-cells = <1>; 719 #clock-cells = <1>;
752 #reset-cells = <1>; 720 #reset-cells = <1>;
753 #power-domain-cells = 721 #power-domain-cells = <1>;
754 clocks = <&rpmhcc RPMH 722 clocks = <&rpmhcc RPMH_CXO_CLK>,
755 <&sleep_clk>, !! 723 <&pcie0_lane>,
756 <&pcie0_phy>, !! 724 <&pcie1_lane>,
757 <&pcie1_phy Q !! 725 <&sleep_clk>;
758 <&pcie1_phy Q <<
759 <&ufs_mem_phy <<
760 <&ufs_mem_phy <<
761 <&ufs_mem_phy <<
762 <&usb_1_qmpph <<
763 clock-names = "bi_tcxo 726 clock-names = "bi_tcxo",
764 "sleep_c <<
765 "pcie_0_ 727 "pcie_0_pipe_clk",
766 "pcie_1_ 728 "pcie_1_pipe_clk",
767 "pcie_1_ !! 729 "sleep_clk";
768 "ufs_phy <<
769 "ufs_phy <<
770 "ufs_phy <<
771 "usb3_ph <<
772 }; 730 };
773 731
774 gpi_dma2: dma-controller@80000 732 gpi_dma2: dma-controller@800000 {
775 compatible = "qcom,sm8 !! 733 compatible = "qcom,sm8450-gpi-dma";
776 #dma-cells = <3>; 734 #dma-cells = <3>;
777 reg = <0 0x00800000 0 !! 735 reg = <0 0x800000 0 0x60000>;
778 interrupts = <GIC_SPI 736 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
779 <GIC_SPI 737 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
780 <GIC_SPI 738 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
781 <GIC_SPI 739 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
782 <GIC_SPI 740 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
783 <GIC_SPI 741 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
784 <GIC_SPI 742 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
785 <GIC_SPI 743 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
786 <GIC_SPI 744 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
787 <GIC_SPI 745 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
788 <GIC_SPI 746 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
789 <GIC_SPI 747 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
790 dma-channels = <12>; 748 dma-channels = <12>;
791 dma-channel-mask = <0x 749 dma-channel-mask = <0x7e>;
792 iommus = <&apps_smmu 0 750 iommus = <&apps_smmu 0x496 0x0>;
793 status = "disabled"; 751 status = "disabled";
794 }; 752 };
795 753
796 qupv3_id_2: geniqup@8c0000 { 754 qupv3_id_2: geniqup@8c0000 {
797 compatible = "qcom,gen 755 compatible = "qcom,geni-se-qup";
798 reg = <0x0 0x008c0000 756 reg = <0x0 0x008c0000 0x0 0x2000>;
799 clock-names = "m-ahb", 757 clock-names = "m-ahb", "s-ahb";
800 clocks = <&gcc GCC_QUP 758 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
801 <&gcc GCC_QUP 759 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
802 iommus = <&apps_smmu 0 760 iommus = <&apps_smmu 0x483 0x0>;
803 #address-cells = <2>; 761 #address-cells = <2>;
804 #size-cells = <2>; 762 #size-cells = <2>;
805 ranges; 763 ranges;
806 status = "disabled"; 764 status = "disabled";
807 765
808 i2c15: i2c@880000 { 766 i2c15: i2c@880000 {
809 compatible = " 767 compatible = "qcom,geni-i2c";
810 reg = <0x0 0x0 768 reg = <0x0 0x00880000 0x0 0x4000>;
811 clock-names = 769 clock-names = "se";
812 clocks = <&gcc 770 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
813 pinctrl-names 771 pinctrl-names = "default";
814 pinctrl-0 = <& 772 pinctrl-0 = <&qup_i2c15_data_clk>;
815 interrupts = < 773 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
816 #address-cells 774 #address-cells = <1>;
817 #size-cells = 775 #size-cells = <0>;
818 interconnects 776 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
819 777 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
820 778 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
821 interconnect-n 779 interconnect-names = "qup-core", "qup-config", "qup-memory";
822 dmas = <&gpi_d 780 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
823 <&gpi_d 781 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
824 dma-names = "t 782 dma-names = "tx", "rx";
825 status = "disa 783 status = "disabled";
826 }; 784 };
827 785
828 spi15: spi@880000 { 786 spi15: spi@880000 {
829 compatible = " 787 compatible = "qcom,geni-spi";
830 reg = <0x0 0x0 788 reg = <0x0 0x00880000 0x0 0x4000>;
831 clock-names = 789 clock-names = "se";
832 clocks = <&gcc 790 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
833 interrupts = < 791 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
834 pinctrl-names 792 pinctrl-names = "default";
835 pinctrl-0 = <& 793 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
>> 794 spi-max-frequency = <50000000>;
836 interconnects 795 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
837 796 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
838 interconnect-n 797 interconnect-names = "qup-core", "qup-config";
839 dmas = <&gpi_d 798 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
840 <&gpi_d 799 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
841 dma-names = "t 800 dma-names = "tx", "rx";
842 #address-cells 801 #address-cells = <1>;
843 #size-cells = 802 #size-cells = <0>;
844 status = "disa 803 status = "disabled";
845 }; 804 };
846 805
847 i2c16: i2c@884000 { 806 i2c16: i2c@884000 {
848 compatible = " 807 compatible = "qcom,geni-i2c";
849 reg = <0x0 0x0 808 reg = <0x0 0x00884000 0x0 0x4000>;
850 clock-names = 809 clock-names = "se";
851 clocks = <&gcc 810 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
852 pinctrl-names 811 pinctrl-names = "default";
853 pinctrl-0 = <& 812 pinctrl-0 = <&qup_i2c16_data_clk>;
854 interrupts = < 813 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
855 #address-cells 814 #address-cells = <1>;
856 #size-cells = 815 #size-cells = <0>;
857 interconnects 816 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
858 817 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
859 818 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
860 interconnect-n 819 interconnect-names = "qup-core", "qup-config", "qup-memory";
861 dmas = <&gpi_d 820 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
862 <&gpi_d 821 <&gpi_dma2 1 1 QCOM_GPI_I2C>;
863 dma-names = "t 822 dma-names = "tx", "rx";
864 status = "disa 823 status = "disabled";
865 }; 824 };
866 825
867 spi16: spi@884000 { 826 spi16: spi@884000 {
868 compatible = " 827 compatible = "qcom,geni-spi";
869 reg = <0x0 0x0 828 reg = <0x0 0x00884000 0x0 0x4000>;
870 clock-names = 829 clock-names = "se";
871 clocks = <&gcc 830 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
872 interrupts = < 831 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
873 pinctrl-names 832 pinctrl-names = "default";
874 pinctrl-0 = <& 833 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>;
>> 834 spi-max-frequency = <50000000>;
875 interconnects 835 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
876 836 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
877 interconnect-n 837 interconnect-names = "qup-core", "qup-config";
878 dmas = <&gpi_d 838 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
879 <&gpi_d 839 <&gpi_dma2 1 1 QCOM_GPI_SPI>;
880 dma-names = "t 840 dma-names = "tx", "rx";
881 #address-cells 841 #address-cells = <1>;
882 #size-cells = 842 #size-cells = <0>;
883 status = "disa 843 status = "disabled";
884 }; 844 };
885 845
886 i2c17: i2c@888000 { 846 i2c17: i2c@888000 {
887 compatible = " 847 compatible = "qcom,geni-i2c";
888 reg = <0x0 0x0 848 reg = <0x0 0x00888000 0x0 0x4000>;
889 clock-names = 849 clock-names = "se";
890 clocks = <&gcc 850 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
891 pinctrl-names 851 pinctrl-names = "default";
892 pinctrl-0 = <& 852 pinctrl-0 = <&qup_i2c17_data_clk>;
893 interrupts = < 853 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
894 #address-cells 854 #address-cells = <1>;
895 #size-cells = 855 #size-cells = <0>;
896 interconnects 856 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
897 857 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
898 858 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
899 interconnect-n 859 interconnect-names = "qup-core", "qup-config", "qup-memory";
900 dmas = <&gpi_d 860 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
901 <&gpi_d 861 <&gpi_dma2 1 2 QCOM_GPI_I2C>;
902 dma-names = "t 862 dma-names = "tx", "rx";
903 status = "disa 863 status = "disabled";
904 }; 864 };
905 865
906 spi17: spi@888000 { 866 spi17: spi@888000 {
907 compatible = " 867 compatible = "qcom,geni-spi";
908 reg = <0x0 0x0 868 reg = <0x0 0x00888000 0x0 0x4000>;
909 clock-names = 869 clock-names = "se";
910 clocks = <&gcc 870 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
911 interrupts = < 871 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
912 pinctrl-names 872 pinctrl-names = "default";
913 pinctrl-0 = <& 873 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>;
>> 874 spi-max-frequency = <50000000>;
914 interconnects 875 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
915 876 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
916 interconnect-n 877 interconnect-names = "qup-core", "qup-config";
917 dmas = <&gpi_d 878 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
918 <&gpi_d 879 <&gpi_dma2 1 2 QCOM_GPI_SPI>;
919 dma-names = "t 880 dma-names = "tx", "rx";
920 #address-cells 881 #address-cells = <1>;
921 #size-cells = 882 #size-cells = <0>;
922 status = "disa 883 status = "disabled";
923 }; 884 };
924 885
925 i2c18: i2c@88c000 { 886 i2c18: i2c@88c000 {
926 compatible = " 887 compatible = "qcom,geni-i2c";
927 reg = <0x0 0x0 888 reg = <0x0 0x0088c000 0x0 0x4000>;
928 clock-names = 889 clock-names = "se";
929 clocks = <&gcc 890 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
930 pinctrl-names 891 pinctrl-names = "default";
931 pinctrl-0 = <& 892 pinctrl-0 = <&qup_i2c18_data_clk>;
932 interrupts = < 893 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
933 #address-cells 894 #address-cells = <1>;
934 #size-cells = 895 #size-cells = <0>;
935 interconnects 896 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
936 897 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
937 898 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
938 interconnect-n 899 interconnect-names = "qup-core", "qup-config", "qup-memory";
939 dmas = <&gpi_d 900 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
940 <&gpi_d 901 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
941 dma-names = "t 902 dma-names = "tx", "rx";
942 status = "disa 903 status = "disabled";
943 }; 904 };
944 905
945 spi18: spi@88c000 { 906 spi18: spi@88c000 {
946 compatible = " 907 compatible = "qcom,geni-spi";
947 reg = <0 0x008 908 reg = <0 0x0088c000 0 0x4000>;
948 clock-names = 909 clock-names = "se";
949 clocks = <&gcc 910 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
950 interrupts = < 911 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
951 pinctrl-names 912 pinctrl-names = "default";
952 pinctrl-0 = <& 913 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>;
>> 914 spi-max-frequency = <50000000>;
953 interconnects 915 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
954 916 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
955 interconnect-n 917 interconnect-names = "qup-core", "qup-config";
956 dmas = <&gpi_d 918 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
957 <&gpi_d 919 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
958 dma-names = "t 920 dma-names = "tx", "rx";
959 #address-cells 921 #address-cells = <1>;
960 #size-cells = 922 #size-cells = <0>;
961 status = "disa 923 status = "disabled";
962 }; 924 };
963 925
964 i2c19: i2c@890000 { 926 i2c19: i2c@890000 {
965 compatible = " 927 compatible = "qcom,geni-i2c";
966 reg = <0x0 0x0 928 reg = <0x0 0x00890000 0x0 0x4000>;
967 clock-names = 929 clock-names = "se";
968 clocks = <&gcc 930 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
969 pinctrl-names 931 pinctrl-names = "default";
970 pinctrl-0 = <& 932 pinctrl-0 = <&qup_i2c19_data_clk>;
971 interrupts = < 933 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
972 #address-cells 934 #address-cells = <1>;
973 #size-cells = 935 #size-cells = <0>;
974 interconnects 936 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
975 937 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
976 938 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
977 interconnect-n 939 interconnect-names = "qup-core", "qup-config", "qup-memory";
978 dmas = <&gpi_d 940 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
979 <&gpi_d 941 <&gpi_dma2 1 4 QCOM_GPI_I2C>;
980 dma-names = "t 942 dma-names = "tx", "rx";
981 status = "disa 943 status = "disabled";
982 }; 944 };
983 945
984 spi19: spi@890000 { 946 spi19: spi@890000 {
985 compatible = " 947 compatible = "qcom,geni-spi";
986 reg = <0 0x008 948 reg = <0 0x00890000 0 0x4000>;
987 clock-names = 949 clock-names = "se";
988 clocks = <&gcc 950 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
989 interrupts = < 951 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
990 pinctrl-names 952 pinctrl-names = "default";
991 pinctrl-0 = <& 953 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>;
>> 954 spi-max-frequency = <50000000>;
992 interconnects 955 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
993 956 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
994 interconnect-n 957 interconnect-names = "qup-core", "qup-config";
995 dmas = <&gpi_d 958 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
996 <&gpi_d 959 <&gpi_dma2 1 4 QCOM_GPI_I2C>;
997 dma-names = "t 960 dma-names = "tx", "rx";
998 #address-cells 961 #address-cells = <1>;
999 #size-cells = 962 #size-cells = <0>;
1000 status = "dis 963 status = "disabled";
1001 }; 964 };
1002 965
1003 i2c20: i2c@894000 { 966 i2c20: i2c@894000 {
1004 compatible = 967 compatible = "qcom,geni-i2c";
1005 reg = <0x0 0x 968 reg = <0x0 0x00894000 0x0 0x4000>;
1006 clock-names = 969 clock-names = "se";
1007 clocks = <&gc 970 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1008 pinctrl-names 971 pinctrl-names = "default";
1009 pinctrl-0 = < 972 pinctrl-0 = <&qup_i2c20_data_clk>;
1010 interrupts = 973 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1011 #address-cell 974 #address-cells = <1>;
1012 #size-cells = 975 #size-cells = <0>;
1013 interconnects 976 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1014 977 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1015 978 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1016 interconnect- 979 interconnect-names = "qup-core", "qup-config", "qup-memory";
1017 dmas = <&gpi_ 980 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1018 <&gpi_ 981 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1019 dma-names = " 982 dma-names = "tx", "rx";
1020 status = "dis 983 status = "disabled";
1021 }; 984 };
1022 985
1023 uart20: serial@894000 986 uart20: serial@894000 {
1024 compatible = 987 compatible = "qcom,geni-uart";
1025 reg = <0 0x00 988 reg = <0 0x00894000 0 0x4000>;
1026 clock-names = 989 clock-names = "se";
1027 clocks = <&gc 990 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1028 pinctrl-names 991 pinctrl-names = "default";
1029 pinctrl-0 = < 992 pinctrl-0 = <&qup_uart20_default>;
1030 interrupts = 993 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1031 interconnects <<
1032 <<
1033 <<
1034 <<
1035 interconnect- <<
1036 <<
1037 status = "dis 994 status = "disabled";
1038 }; 995 };
1039 996
1040 spi20: spi@894000 { 997 spi20: spi@894000 {
1041 compatible = 998 compatible = "qcom,geni-spi";
1042 reg = <0 0x00 999 reg = <0 0x00894000 0 0x4000>;
1043 clock-names = 1000 clock-names = "se";
1044 clocks = <&gc 1001 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1045 interrupts = 1002 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1046 pinctrl-names 1003 pinctrl-names = "default";
1047 pinctrl-0 = < 1004 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>;
>> 1005 spi-max-frequency = <50000000>;
1048 interconnects 1006 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1049 1007 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
1050 interconnect- 1008 interconnect-names = "qup-core", "qup-config";
1051 dmas = <&gpi_ 1009 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1052 <&gpi_ 1010 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1053 dma-names = " 1011 dma-names = "tx", "rx";
1054 #address-cell 1012 #address-cells = <1>;
1055 #size-cells = 1013 #size-cells = <0>;
1056 status = "dis 1014 status = "disabled";
1057 }; 1015 };
1058 1016
1059 i2c21: i2c@898000 { 1017 i2c21: i2c@898000 {
1060 compatible = 1018 compatible = "qcom,geni-i2c";
1061 reg = <0x0 0x 1019 reg = <0x0 0x00898000 0x0 0x4000>;
1062 clock-names = 1020 clock-names = "se";
1063 clocks = <&gc 1021 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1064 pinctrl-names 1022 pinctrl-names = "default";
1065 pinctrl-0 = < 1023 pinctrl-0 = <&qup_i2c21_data_clk>;
1066 interrupts = 1024 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
1067 #address-cell 1025 #address-cells = <1>;
1068 #size-cells = 1026 #size-cells = <0>;
1069 interconnects 1027 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1070 1028 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1071 1029 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1072 interconnect- 1030 interconnect-names = "qup-core", "qup-config", "qup-memory";
1073 dmas = <&gpi_ 1031 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>,
1074 <&gpi_ 1032 <&gpi_dma2 1 6 QCOM_GPI_I2C>;
1075 dma-names = " 1033 dma-names = "tx", "rx";
1076 status = "dis 1034 status = "disabled";
1077 }; 1035 };
1078 1036
1079 spi21: spi@898000 { 1037 spi21: spi@898000 {
1080 compatible = 1038 compatible = "qcom,geni-spi";
1081 reg = <0 0x00 1039 reg = <0 0x00898000 0 0x4000>;
1082 clock-names = 1040 clock-names = "se";
1083 clocks = <&gc 1041 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1084 interrupts = 1042 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
1085 pinctrl-names 1043 pinctrl-names = "default";
1086 pinctrl-0 = < 1044 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>;
>> 1045 spi-max-frequency = <50000000>;
1087 interconnects 1046 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1088 1047 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
1089 interconnect- 1048 interconnect-names = "qup-core", "qup-config";
1090 dmas = <&gpi_ 1049 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>,
1091 <&gpi_ 1050 <&gpi_dma2 1 6 QCOM_GPI_SPI>;
1092 dma-names = " 1051 dma-names = "tx", "rx";
1093 #address-cell 1052 #address-cells = <1>;
1094 #size-cells = 1053 #size-cells = <0>;
1095 status = "dis 1054 status = "disabled";
1096 }; 1055 };
1097 }; 1056 };
1098 1057
1099 gpi_dma0: dma-controller@9000 1058 gpi_dma0: dma-controller@900000 {
1100 compatible = "qcom,sm !! 1059 compatible = "qcom,sm8450-gpi-dma";
1101 #dma-cells = <3>; 1060 #dma-cells = <3>;
1102 reg = <0 0x00900000 0 !! 1061 reg = <0 0x900000 0 0x60000>;
1103 interrupts = <GIC_SPI 1062 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
1104 <GIC_SPI 1063 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
1105 <GIC_SPI 1064 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
1106 <GIC_SPI 1065 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
1107 <GIC_SPI 1066 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
1108 <GIC_SPI 1067 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
1109 <GIC_SPI 1068 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
1110 <GIC_SPI 1069 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
1111 <GIC_SPI 1070 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
1112 <GIC_SPI 1071 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
1113 <GIC_SPI 1072 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
1114 <GIC_SPI 1073 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
1115 dma-channels = <12>; 1074 dma-channels = <12>;
1116 dma-channel-mask = <0 1075 dma-channel-mask = <0x7e>;
1117 iommus = <&apps_smmu 1076 iommus = <&apps_smmu 0x5b6 0x0>;
1118 status = "disabled"; 1077 status = "disabled";
1119 }; 1078 };
1120 1079
1121 qupv3_id_0: geniqup@9c0000 { 1080 qupv3_id_0: geniqup@9c0000 {
1122 compatible = "qcom,ge 1081 compatible = "qcom,geni-se-qup";
1123 reg = <0x0 0x009c0000 1082 reg = <0x0 0x009c0000 0x0 0x2000>;
1124 clock-names = "m-ahb" 1083 clock-names = "m-ahb", "s-ahb";
1125 clocks = <&gcc GCC_QU 1084 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1126 <&gcc GCC_QU 1085 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1127 iommus = <&apps_smmu 1086 iommus = <&apps_smmu 0x5a3 0x0>;
1128 interconnects = <&clk 1087 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>;
1129 interconnect-names = 1088 interconnect-names = "qup-core";
1130 #address-cells = <2>; 1089 #address-cells = <2>;
1131 #size-cells = <2>; 1090 #size-cells = <2>;
1132 ranges; 1091 ranges;
1133 status = "disabled"; 1092 status = "disabled";
1134 1093
1135 i2c0: i2c@980000 { 1094 i2c0: i2c@980000 {
1136 compatible = 1095 compatible = "qcom,geni-i2c";
1137 reg = <0x0 0x 1096 reg = <0x0 0x00980000 0x0 0x4000>;
1138 clock-names = 1097 clock-names = "se";
1139 clocks = <&gc 1098 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1140 pinctrl-names 1099 pinctrl-names = "default";
1141 pinctrl-0 = < 1100 pinctrl-0 = <&qup_i2c0_data_clk>;
1142 interrupts = 1101 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1143 #address-cell 1102 #address-cells = <1>;
1144 #size-cells = 1103 #size-cells = <0>;
1145 interconnects 1104 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1146 1105 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1147 1106 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1148 interconnect- 1107 interconnect-names = "qup-core", "qup-config", "qup-memory";
1149 dmas = <&gpi_ 1108 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1150 <&gpi_ 1109 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1151 dma-names = " 1110 dma-names = "tx", "rx";
1152 status = "dis 1111 status = "disabled";
1153 }; 1112 };
1154 1113
1155 spi0: spi@980000 { 1114 spi0: spi@980000 {
1156 compatible = 1115 compatible = "qcom,geni-spi";
1157 reg = <0x0 0x 1116 reg = <0x0 0x00980000 0x0 0x4000>;
1158 clock-names = 1117 clock-names = "se";
1159 clocks = <&gc 1118 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1160 interrupts = 1119 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1161 pinctrl-names 1120 pinctrl-names = "default";
1162 pinctrl-0 = < 1121 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1163 power-domains !! 1122 power-domains = <&rpmhpd SM8450_CX>;
1164 operating-poi 1123 operating-points-v2 = <&qup_opp_table_100mhz>;
1165 interconnects 1124 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1166 1125 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1167 1126 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1168 interconnect- 1127 interconnect-names = "qup-core", "qup-config", "qup-memory";
1169 dmas = <&gpi_ 1128 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1170 <&gpi_ 1129 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1171 dma-names = " 1130 dma-names = "tx", "rx";
1172 #address-cell 1131 #address-cells = <1>;
1173 #size-cells = 1132 #size-cells = <0>;
1174 status = "dis 1133 status = "disabled";
1175 }; 1134 };
1176 1135
1177 i2c1: i2c@984000 { 1136 i2c1: i2c@984000 {
1178 compatible = 1137 compatible = "qcom,geni-i2c";
1179 reg = <0x0 0x 1138 reg = <0x0 0x00984000 0x0 0x4000>;
1180 clock-names = 1139 clock-names = "se";
1181 clocks = <&gc 1140 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1182 pinctrl-names 1141 pinctrl-names = "default";
1183 pinctrl-0 = < 1142 pinctrl-0 = <&qup_i2c1_data_clk>;
1184 interrupts = 1143 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1185 #address-cell 1144 #address-cells = <1>;
1186 #size-cells = 1145 #size-cells = <0>;
1187 interconnects 1146 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1188 1147 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1189 1148 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1190 interconnect- 1149 interconnect-names = "qup-core", "qup-config", "qup-memory";
1191 dmas = <&gpi_ 1150 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1192 <&gpi_ 1151 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1193 dma-names = " 1152 dma-names = "tx", "rx";
1194 status = "dis 1153 status = "disabled";
1195 }; 1154 };
1196 1155
1197 spi1: spi@984000 { 1156 spi1: spi@984000 {
1198 compatible = 1157 compatible = "qcom,geni-spi";
1199 reg = <0x0 0x 1158 reg = <0x0 0x00984000 0x0 0x4000>;
1200 clock-names = 1159 clock-names = "se";
1201 clocks = <&gc 1160 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1202 interrupts = 1161 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1203 pinctrl-names 1162 pinctrl-names = "default";
1204 pinctrl-0 = < 1163 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1205 interconnects 1164 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1206 1165 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1207 1166 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1208 interconnect- 1167 interconnect-names = "qup-core", "qup-config", "qup-memory";
1209 dmas = <&gpi_ 1168 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1210 <&gpi_ 1169 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1211 dma-names = " 1170 dma-names = "tx", "rx";
1212 #address-cell 1171 #address-cells = <1>;
1213 #size-cells = 1172 #size-cells = <0>;
1214 status = "dis 1173 status = "disabled";
1215 }; 1174 };
1216 1175
1217 i2c2: i2c@988000 { 1176 i2c2: i2c@988000 {
1218 compatible = 1177 compatible = "qcom,geni-i2c";
1219 reg = <0x0 0x 1178 reg = <0x0 0x00988000 0x0 0x4000>;
1220 clock-names = 1179 clock-names = "se";
1221 clocks = <&gc 1180 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1222 pinctrl-names 1181 pinctrl-names = "default";
1223 pinctrl-0 = < 1182 pinctrl-0 = <&qup_i2c2_data_clk>;
1224 interrupts = 1183 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1225 #address-cell 1184 #address-cells = <1>;
1226 #size-cells = 1185 #size-cells = <0>;
1227 interconnects 1186 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1228 1187 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1229 1188 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1230 interconnect- 1189 interconnect-names = "qup-core", "qup-config", "qup-memory";
1231 dmas = <&gpi_ 1190 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1232 <&gpi_ 1191 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1233 dma-names = " 1192 dma-names = "tx", "rx";
1234 status = "dis 1193 status = "disabled";
1235 }; 1194 };
1236 1195
1237 spi2: spi@988000 { 1196 spi2: spi@988000 {
1238 compatible = 1197 compatible = "qcom,geni-spi";
1239 reg = <0x0 0x 1198 reg = <0x0 0x00988000 0x0 0x4000>;
1240 clock-names = 1199 clock-names = "se";
1241 clocks = <&gc 1200 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1242 interrupts = 1201 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1243 pinctrl-names 1202 pinctrl-names = "default";
1244 pinctrl-0 = < 1203 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1245 interconnects 1204 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1246 1205 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1247 1206 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1248 interconnect- 1207 interconnect-names = "qup-core", "qup-config", "qup-memory";
1249 dmas = <&gpi_ 1208 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1250 <&gpi_ 1209 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1251 dma-names = " 1210 dma-names = "tx", "rx";
1252 #address-cell 1211 #address-cells = <1>;
1253 #size-cells = 1212 #size-cells = <0>;
1254 status = "dis 1213 status = "disabled";
1255 }; 1214 };
1256 1215
1257 1216
1258 i2c3: i2c@98c000 { 1217 i2c3: i2c@98c000 {
1259 compatible = 1218 compatible = "qcom,geni-i2c";
1260 reg = <0x0 0x 1219 reg = <0x0 0x0098c000 0x0 0x4000>;
1261 clock-names = 1220 clock-names = "se";
1262 clocks = <&gc 1221 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1263 pinctrl-names 1222 pinctrl-names = "default";
1264 pinctrl-0 = < 1223 pinctrl-0 = <&qup_i2c3_data_clk>;
1265 interrupts = 1224 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1266 #address-cell 1225 #address-cells = <1>;
1267 #size-cells = 1226 #size-cells = <0>;
1268 interconnects 1227 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1269 1228 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1270 1229 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1271 interconnect- 1230 interconnect-names = "qup-core", "qup-config", "qup-memory";
1272 dmas = <&gpi_ 1231 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1273 <&gpi_ 1232 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1274 dma-names = " 1233 dma-names = "tx", "rx";
1275 status = "dis 1234 status = "disabled";
1276 }; 1235 };
1277 1236
1278 spi3: spi@98c000 { 1237 spi3: spi@98c000 {
1279 compatible = 1238 compatible = "qcom,geni-spi";
1280 reg = <0x0 0x 1239 reg = <0x0 0x0098c000 0x0 0x4000>;
1281 clock-names = 1240 clock-names = "se";
1282 clocks = <&gc 1241 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1283 interrupts = 1242 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1284 pinctrl-names 1243 pinctrl-names = "default";
1285 pinctrl-0 = < 1244 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1286 interconnects 1245 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1287 1246 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1288 1247 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1289 interconnect- 1248 interconnect-names = "qup-core", "qup-config", "qup-memory";
1290 dmas = <&gpi_ 1249 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1291 <&gpi_ 1250 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1292 dma-names = " 1251 dma-names = "tx", "rx";
1293 #address-cell 1252 #address-cells = <1>;
1294 #size-cells = 1253 #size-cells = <0>;
1295 status = "dis 1254 status = "disabled";
1296 }; 1255 };
1297 1256
1298 i2c4: i2c@990000 { 1257 i2c4: i2c@990000 {
1299 compatible = 1258 compatible = "qcom,geni-i2c";
1300 reg = <0x0 0x 1259 reg = <0x0 0x00990000 0x0 0x4000>;
1301 clock-names = 1260 clock-names = "se";
1302 clocks = <&gc 1261 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1303 pinctrl-names 1262 pinctrl-names = "default";
1304 pinctrl-0 = < 1263 pinctrl-0 = <&qup_i2c4_data_clk>;
1305 interrupts = 1264 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1306 #address-cell 1265 #address-cells = <1>;
1307 #size-cells = 1266 #size-cells = <0>;
1308 interconnects 1267 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1309 1268 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1310 1269 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1311 interconnect- 1270 interconnect-names = "qup-core", "qup-config", "qup-memory";
1312 dmas = <&gpi_ 1271 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1313 <&gpi_ 1272 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1314 dma-names = " 1273 dma-names = "tx", "rx";
1315 status = "dis 1274 status = "disabled";
1316 }; 1275 };
1317 1276
1318 spi4: spi@990000 { 1277 spi4: spi@990000 {
1319 compatible = 1278 compatible = "qcom,geni-spi";
1320 reg = <0x0 0x 1279 reg = <0x0 0x00990000 0x0 0x4000>;
1321 clock-names = 1280 clock-names = "se";
1322 clocks = <&gc 1281 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1323 interrupts = 1282 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1324 pinctrl-names 1283 pinctrl-names = "default";
1325 pinctrl-0 = < 1284 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1326 power-domains !! 1285 power-domains = <&rpmhpd SM8450_CX>;
1327 operating-poi 1286 operating-points-v2 = <&qup_opp_table_100mhz>;
1328 interconnects 1287 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1329 1288 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1330 1289 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1331 interconnect- 1290 interconnect-names = "qup-core", "qup-config", "qup-memory";
1332 dmas = <&gpi_ 1291 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1333 <&gpi_ 1292 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1334 dma-names = " 1293 dma-names = "tx", "rx";
1335 #address-cell 1294 #address-cells = <1>;
1336 #size-cells = 1295 #size-cells = <0>;
1337 status = "dis 1296 status = "disabled";
1338 }; 1297 };
1339 1298
1340 i2c5: i2c@994000 { 1299 i2c5: i2c@994000 {
1341 compatible = 1300 compatible = "qcom,geni-i2c";
1342 reg = <0x0 0x 1301 reg = <0x0 0x00994000 0x0 0x4000>;
1343 clock-names = 1302 clock-names = "se";
1344 clocks = <&gc 1303 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1345 pinctrl-names 1304 pinctrl-names = "default";
1346 pinctrl-0 = < 1305 pinctrl-0 = <&qup_i2c5_data_clk>;
1347 interrupts = 1306 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1348 #address-cell 1307 #address-cells = <1>;
1349 #size-cells = 1308 #size-cells = <0>;
1350 interconnects 1309 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1351 1310 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1352 1311 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1353 interconnect- 1312 interconnect-names = "qup-core", "qup-config", "qup-memory";
1354 dmas = <&gpi_ 1313 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1355 <&gpi_ 1314 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1356 dma-names = " 1315 dma-names = "tx", "rx";
1357 status = "dis 1316 status = "disabled";
1358 }; 1317 };
1359 1318
1360 spi5: spi@994000 { 1319 spi5: spi@994000 {
1361 compatible = 1320 compatible = "qcom,geni-spi";
1362 reg = <0x0 0x 1321 reg = <0x0 0x00994000 0x0 0x4000>;
1363 clock-names = 1322 clock-names = "se";
1364 clocks = <&gc 1323 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1365 interrupts = 1324 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1366 pinctrl-names 1325 pinctrl-names = "default";
1367 pinctrl-0 = < 1326 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1368 interconnects 1327 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1369 1328 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1370 1329 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1371 interconnect- 1330 interconnect-names = "qup-core", "qup-config", "qup-memory";
1372 dmas = <&gpi_ 1331 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1373 <&gpi_ 1332 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1374 dma-names = " 1333 dma-names = "tx", "rx";
1375 #address-cell 1334 #address-cells = <1>;
1376 #size-cells = 1335 #size-cells = <0>;
1377 status = "dis 1336 status = "disabled";
1378 }; 1337 };
1379 1338
1380 1339
1381 i2c6: i2c@998000 { 1340 i2c6: i2c@998000 {
1382 compatible = 1341 compatible = "qcom,geni-i2c";
1383 reg = <0x0 0x !! 1342 reg = <0x0 0x998000 0x0 0x4000>;
1384 clock-names = 1343 clock-names = "se";
1385 clocks = <&gc 1344 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1386 pinctrl-names 1345 pinctrl-names = "default";
1387 pinctrl-0 = < 1346 pinctrl-0 = <&qup_i2c6_data_clk>;
1388 interrupts = 1347 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1389 #address-cell 1348 #address-cells = <1>;
1390 #size-cells = 1349 #size-cells = <0>;
1391 interconnects 1350 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1392 1351 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1393 1352 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1394 interconnect- 1353 interconnect-names = "qup-core", "qup-config", "qup-memory";
1395 dmas = <&gpi_ 1354 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1396 <&gpi_ 1355 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1397 dma-names = " 1356 dma-names = "tx", "rx";
1398 status = "dis 1357 status = "disabled";
1399 }; 1358 };
1400 1359
1401 spi6: spi@998000 { 1360 spi6: spi@998000 {
1402 compatible = 1361 compatible = "qcom,geni-spi";
1403 reg = <0x0 0x !! 1362 reg = <0x0 0x998000 0x0 0x4000>;
1404 clock-names = 1363 clock-names = "se";
1405 clocks = <&gc 1364 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1406 interrupts = 1365 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1407 pinctrl-names 1366 pinctrl-names = "default";
1408 pinctrl-0 = < 1367 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1409 interconnects 1368 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1410 1369 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1411 1370 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1412 interconnect- 1371 interconnect-names = "qup-core", "qup-config", "qup-memory";
1413 dmas = <&gpi_ 1372 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1414 <&gpi_ 1373 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1415 dma-names = " 1374 dma-names = "tx", "rx";
1416 #address-cell 1375 #address-cells = <1>;
1417 #size-cells = 1376 #size-cells = <0>;
1418 status = "dis 1377 status = "disabled";
1419 }; 1378 };
1420 1379
1421 uart7: serial@99c000 1380 uart7: serial@99c000 {
1422 compatible = 1381 compatible = "qcom,geni-debug-uart";
1423 reg = <0 0x00 1382 reg = <0 0x0099c000 0 0x4000>;
1424 clock-names = 1383 clock-names = "se";
1425 clocks = <&gc 1384 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1426 pinctrl-names 1385 pinctrl-names = "default";
1427 pinctrl-0 = < 1386 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>;
1428 interrupts = 1387 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1429 interconnects <<
1430 <<
1431 <<
1432 <<
1433 interconnect- <<
1434 <<
1435 status = "dis 1388 status = "disabled";
1436 }; 1389 };
1437 }; 1390 };
1438 1391
1439 gpi_dma1: dma-controller@a000 1392 gpi_dma1: dma-controller@a00000 {
1440 compatible = "qcom,sm !! 1393 compatible = "qcom,sm8450-gpi-dma";
1441 #dma-cells = <3>; 1394 #dma-cells = <3>;
1442 reg = <0 0x00a00000 0 !! 1395 reg = <0 0xa00000 0 0x60000>;
1443 interrupts = <GIC_SPI 1396 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1444 <GIC_SPI 1397 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1445 <GIC_SPI 1398 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1446 <GIC_SPI 1399 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1447 <GIC_SPI 1400 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1448 <GIC_SPI 1401 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1449 <GIC_SPI 1402 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1450 <GIC_SPI 1403 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1451 <GIC_SPI 1404 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1452 <GIC_SPI 1405 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1453 <GIC_SPI 1406 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1454 <GIC_SPI 1407 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
1455 dma-channels = <12>; 1408 dma-channels = <12>;
1456 dma-channel-mask = <0 1409 dma-channel-mask = <0x7e>;
1457 iommus = <&apps_smmu 1410 iommus = <&apps_smmu 0x56 0x0>;
1458 status = "disabled"; 1411 status = "disabled";
1459 }; 1412 };
1460 1413
1461 qupv3_id_1: geniqup@ac0000 { 1414 qupv3_id_1: geniqup@ac0000 {
1462 compatible = "qcom,ge 1415 compatible = "qcom,geni-se-qup";
1463 reg = <0x0 0x00ac0000 1416 reg = <0x0 0x00ac0000 0x0 0x6000>;
1464 clock-names = "m-ahb" 1417 clock-names = "m-ahb", "s-ahb";
1465 clocks = <&gcc GCC_QU 1418 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1466 <&gcc GCC_QU 1419 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1467 iommus = <&apps_smmu 1420 iommus = <&apps_smmu 0x43 0x0>;
1468 interconnects = <&clk 1421 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>;
1469 interconnect-names = 1422 interconnect-names = "qup-core";
1470 #address-cells = <2>; 1423 #address-cells = <2>;
1471 #size-cells = <2>; 1424 #size-cells = <2>;
1472 ranges; 1425 ranges;
1473 status = "disabled"; 1426 status = "disabled";
1474 1427
1475 i2c8: i2c@a80000 { 1428 i2c8: i2c@a80000 {
1476 compatible = 1429 compatible = "qcom,geni-i2c";
1477 reg = <0x0 0x 1430 reg = <0x0 0x00a80000 0x0 0x4000>;
1478 clock-names = 1431 clock-names = "se";
1479 clocks = <&gc 1432 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1480 pinctrl-names 1433 pinctrl-names = "default";
1481 pinctrl-0 = < 1434 pinctrl-0 = <&qup_i2c8_data_clk>;
1482 interrupts = 1435 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1483 #address-cell 1436 #address-cells = <1>;
1484 #size-cells = 1437 #size-cells = <0>;
1485 interconnects 1438 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1486 1439 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1487 1440 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1488 interconnect- 1441 interconnect-names = "qup-core", "qup-config", "qup-memory";
1489 dmas = <&gpi_ 1442 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1490 <&gpi_ 1443 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1491 dma-names = " 1444 dma-names = "tx", "rx";
1492 status = "dis 1445 status = "disabled";
1493 }; 1446 };
1494 1447
1495 spi8: spi@a80000 { 1448 spi8: spi@a80000 {
1496 compatible = 1449 compatible = "qcom,geni-spi";
1497 reg = <0x0 0x 1450 reg = <0x0 0x00a80000 0x0 0x4000>;
1498 clock-names = 1451 clock-names = "se";
1499 clocks = <&gc 1452 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1500 interrupts = 1453 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1501 pinctrl-names 1454 pinctrl-names = "default";
1502 pinctrl-0 = < 1455 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1503 interconnects 1456 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1504 1457 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1505 1458 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1506 interconnect- 1459 interconnect-names = "qup-core", "qup-config", "qup-memory";
1507 dmas = <&gpi_ 1460 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1508 <&gpi_ 1461 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1509 dma-names = " 1462 dma-names = "tx", "rx";
1510 #address-cell 1463 #address-cells = <1>;
1511 #size-cells = 1464 #size-cells = <0>;
1512 status = "dis 1465 status = "disabled";
1513 }; 1466 };
1514 1467
1515 i2c9: i2c@a84000 { 1468 i2c9: i2c@a84000 {
1516 compatible = 1469 compatible = "qcom,geni-i2c";
1517 reg = <0x0 0x 1470 reg = <0x0 0x00a84000 0x0 0x4000>;
1518 clock-names = 1471 clock-names = "se";
1519 clocks = <&gc 1472 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1520 pinctrl-names 1473 pinctrl-names = "default";
1521 pinctrl-0 = < 1474 pinctrl-0 = <&qup_i2c9_data_clk>;
1522 interrupts = 1475 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1523 #address-cell 1476 #address-cells = <1>;
1524 #size-cells = 1477 #size-cells = <0>;
1525 interconnects 1478 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1526 1479 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1527 1480 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1528 interconnect- 1481 interconnect-names = "qup-core", "qup-config", "qup-memory";
1529 dmas = <&gpi_ 1482 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1530 <&gpi_ 1483 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1531 dma-names = " 1484 dma-names = "tx", "rx";
1532 status = "dis 1485 status = "disabled";
1533 }; 1486 };
1534 1487
1535 spi9: spi@a84000 { 1488 spi9: spi@a84000 {
1536 compatible = 1489 compatible = "qcom,geni-spi";
1537 reg = <0x0 0x 1490 reg = <0x0 0x00a84000 0x0 0x4000>;
1538 clock-names = 1491 clock-names = "se";
1539 clocks = <&gc 1492 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1540 interrupts = 1493 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1541 pinctrl-names 1494 pinctrl-names = "default";
1542 pinctrl-0 = < 1495 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1543 interconnects 1496 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1544 1497 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1545 1498 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1546 interconnect- 1499 interconnect-names = "qup-core", "qup-config", "qup-memory";
1547 dmas = <&gpi_ 1500 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1548 <&gpi_ 1501 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1549 dma-names = " 1502 dma-names = "tx", "rx";
1550 #address-cell 1503 #address-cells = <1>;
1551 #size-cells = 1504 #size-cells = <0>;
1552 status = "dis 1505 status = "disabled";
1553 }; 1506 };
1554 1507
1555 i2c10: i2c@a88000 { 1508 i2c10: i2c@a88000 {
1556 compatible = 1509 compatible = "qcom,geni-i2c";
1557 reg = <0x0 0x 1510 reg = <0x0 0x00a88000 0x0 0x4000>;
1558 clock-names = 1511 clock-names = "se";
1559 clocks = <&gc 1512 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1560 pinctrl-names 1513 pinctrl-names = "default";
1561 pinctrl-0 = < 1514 pinctrl-0 = <&qup_i2c10_data_clk>;
1562 interrupts = 1515 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1563 #address-cell 1516 #address-cells = <1>;
1564 #size-cells = 1517 #size-cells = <0>;
1565 interconnects 1518 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1566 1519 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1567 1520 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1568 interconnect- 1521 interconnect-names = "qup-core", "qup-config", "qup-memory";
1569 dmas = <&gpi_ 1522 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1570 <&gpi_ 1523 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1571 dma-names = " 1524 dma-names = "tx", "rx";
1572 status = "dis 1525 status = "disabled";
1573 }; 1526 };
1574 1527
1575 spi10: spi@a88000 { 1528 spi10: spi@a88000 {
1576 compatible = 1529 compatible = "qcom,geni-spi";
1577 reg = <0x0 0x 1530 reg = <0x0 0x00a88000 0x0 0x4000>;
1578 clock-names = 1531 clock-names = "se";
1579 clocks = <&gc 1532 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1580 interrupts = 1533 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1581 pinctrl-names 1534 pinctrl-names = "default";
1582 pinctrl-0 = < 1535 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1583 interconnects 1536 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1584 1537 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1585 1538 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1586 interconnect- 1539 interconnect-names = "qup-core", "qup-config", "qup-memory";
1587 dmas = <&gpi_ 1540 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1588 <&gpi_ 1541 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1589 dma-names = " 1542 dma-names = "tx", "rx";
1590 #address-cell 1543 #address-cells = <1>;
1591 #size-cells = 1544 #size-cells = <0>;
1592 status = "dis 1545 status = "disabled";
1593 }; 1546 };
1594 1547
1595 i2c11: i2c@a8c000 { 1548 i2c11: i2c@a8c000 {
1596 compatible = 1549 compatible = "qcom,geni-i2c";
1597 reg = <0x0 0x 1550 reg = <0x0 0x00a8c000 0x0 0x4000>;
1598 clock-names = 1551 clock-names = "se";
1599 clocks = <&gc 1552 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1600 pinctrl-names 1553 pinctrl-names = "default";
1601 pinctrl-0 = < 1554 pinctrl-0 = <&qup_i2c11_data_clk>;
1602 interrupts = 1555 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1603 #address-cell 1556 #address-cells = <1>;
1604 #size-cells = 1557 #size-cells = <0>;
1605 interconnects 1558 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1606 1559 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1607 1560 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1608 interconnect- 1561 interconnect-names = "qup-core", "qup-config", "qup-memory";
1609 dmas = <&gpi_ 1562 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1610 <&gpi_ 1563 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1611 dma-names = " 1564 dma-names = "tx", "rx";
1612 status = "dis 1565 status = "disabled";
1613 }; 1566 };
1614 1567
1615 spi11: spi@a8c000 { 1568 spi11: spi@a8c000 {
1616 compatible = 1569 compatible = "qcom,geni-spi";
1617 reg = <0x0 0x 1570 reg = <0x0 0x00a8c000 0x0 0x4000>;
1618 clock-names = 1571 clock-names = "se";
1619 clocks = <&gc 1572 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1620 interrupts = 1573 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1621 pinctrl-names 1574 pinctrl-names = "default";
1622 pinctrl-0 = < 1575 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1623 interconnects 1576 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1624 1577 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1625 1578 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1626 interconnect- 1579 interconnect-names = "qup-core", "qup-config", "qup-memory";
1627 dmas = <&gpi_ 1580 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1628 <&gpi_ 1581 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1629 dma-names = " 1582 dma-names = "tx", "rx";
1630 #address-cell 1583 #address-cells = <1>;
1631 #size-cells = 1584 #size-cells = <0>;
1632 status = "dis 1585 status = "disabled";
1633 }; 1586 };
1634 1587
1635 i2c12: i2c@a90000 { 1588 i2c12: i2c@a90000 {
1636 compatible = 1589 compatible = "qcom,geni-i2c";
1637 reg = <0x0 0x 1590 reg = <0x0 0x00a90000 0x0 0x4000>;
1638 clock-names = 1591 clock-names = "se";
1639 clocks = <&gc 1592 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1640 pinctrl-names 1593 pinctrl-names = "default";
1641 pinctrl-0 = < 1594 pinctrl-0 = <&qup_i2c12_data_clk>;
1642 interrupts = 1595 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1643 #address-cell 1596 #address-cells = <1>;
1644 #size-cells = 1597 #size-cells = <0>;
1645 interconnects 1598 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1646 1599 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1647 1600 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1648 interconnect- 1601 interconnect-names = "qup-core", "qup-config", "qup-memory";
1649 dmas = <&gpi_ 1602 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1650 <&gpi_ 1603 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1651 dma-names = " 1604 dma-names = "tx", "rx";
1652 status = "dis 1605 status = "disabled";
1653 }; 1606 };
1654 1607
1655 spi12: spi@a90000 { 1608 spi12: spi@a90000 {
1656 compatible = 1609 compatible = "qcom,geni-spi";
1657 reg = <0x0 0x 1610 reg = <0x0 0x00a90000 0x0 0x4000>;
1658 clock-names = 1611 clock-names = "se";
1659 clocks = <&gc 1612 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1660 interrupts = 1613 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1661 pinctrl-names 1614 pinctrl-names = "default";
1662 pinctrl-0 = < 1615 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1663 interconnects 1616 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1664 1617 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1665 1618 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1666 interconnect- 1619 interconnect-names = "qup-core", "qup-config", "qup-memory";
1667 dmas = <&gpi_ 1620 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1668 <&gpi_ 1621 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1669 dma-names = " 1622 dma-names = "tx", "rx";
1670 #address-cell 1623 #address-cells = <1>;
1671 #size-cells = 1624 #size-cells = <0>;
1672 status = "dis 1625 status = "disabled";
1673 }; 1626 };
1674 1627
1675 i2c13: i2c@a94000 { 1628 i2c13: i2c@a94000 {
1676 compatible = 1629 compatible = "qcom,geni-i2c";
1677 reg = <0 0x00 1630 reg = <0 0x00a94000 0 0x4000>;
1678 clock-names = 1631 clock-names = "se";
1679 clocks = <&gc 1632 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1680 pinctrl-names 1633 pinctrl-names = "default";
1681 pinctrl-0 = < 1634 pinctrl-0 = <&qup_i2c13_data_clk>;
1682 interrupts = 1635 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1683 interconnects 1636 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1684 1637 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1685 1638 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1686 interconnect- 1639 interconnect-names = "qup-core", "qup-config", "qup-memory";
1687 dmas = <&gpi_ 1640 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1688 <&gpi_ 1641 <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1689 dma-names = " 1642 dma-names = "tx", "rx";
1690 #address-cell 1643 #address-cells = <1>;
1691 #size-cells = 1644 #size-cells = <0>;
1692 status = "dis 1645 status = "disabled";
1693 }; 1646 };
1694 1647
1695 spi13: spi@a94000 { 1648 spi13: spi@a94000 {
1696 compatible = 1649 compatible = "qcom,geni-spi";
1697 reg = <0x0 0x 1650 reg = <0x0 0x00a94000 0x0 0x4000>;
1698 clock-names = 1651 clock-names = "se";
1699 clocks = <&gc 1652 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1700 interrupts = 1653 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1701 pinctrl-names 1654 pinctrl-names = "default";
1702 pinctrl-0 = < 1655 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1703 interconnects 1656 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1704 1657 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1705 1658 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1706 interconnect- 1659 interconnect-names = "qup-core", "qup-config", "qup-memory";
1707 dmas = <&gpi_ 1660 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1708 <&gpi_ 1661 <&gpi_dma1 1 5 QCOM_GPI_SPI>;
1709 dma-names = " 1662 dma-names = "tx", "rx";
1710 #address-cell 1663 #address-cells = <1>;
1711 #size-cells = 1664 #size-cells = <0>;
1712 status = "dis 1665 status = "disabled";
1713 }; 1666 };
1714 1667
1715 i2c14: i2c@a98000 { 1668 i2c14: i2c@a98000 {
1716 compatible = 1669 compatible = "qcom,geni-i2c";
1717 reg = <0 0x00 1670 reg = <0 0x00a98000 0 0x4000>;
1718 clock-names = 1671 clock-names = "se";
1719 clocks = <&gc 1672 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1720 pinctrl-names 1673 pinctrl-names = "default";
1721 pinctrl-0 = < 1674 pinctrl-0 = <&qup_i2c14_data_clk>;
1722 interrupts = 1675 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
1723 interconnects 1676 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1724 1677 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1725 1678 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1726 interconnect- 1679 interconnect-names = "qup-core", "qup-config", "qup-memory";
1727 dmas = <&gpi_ 1680 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
1728 <&gpi_ 1681 <&gpi_dma1 1 6 QCOM_GPI_I2C>;
1729 dma-names = " 1682 dma-names = "tx", "rx";
1730 #address-cell 1683 #address-cells = <1>;
1731 #size-cells = 1684 #size-cells = <0>;
1732 status = "dis 1685 status = "disabled";
1733 }; 1686 };
1734 1687
1735 spi14: spi@a98000 { 1688 spi14: spi@a98000 {
1736 compatible = 1689 compatible = "qcom,geni-spi";
1737 reg = <0x0 0x 1690 reg = <0x0 0x00a98000 0x0 0x4000>;
1738 clock-names = 1691 clock-names = "se";
1739 clocks = <&gc 1692 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1740 interrupts = 1693 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
1741 pinctrl-names 1694 pinctrl-names = "default";
1742 pinctrl-0 = < 1695 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
1743 interconnects 1696 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1744 1697 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1745 1698 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1746 interconnect- 1699 interconnect-names = "qup-core", "qup-config", "qup-memory";
1747 dmas = <&gpi_ 1700 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
1748 <&gpi_ 1701 <&gpi_dma1 1 6 QCOM_GPI_SPI>;
1749 dma-names = " 1702 dma-names = "tx", "rx";
1750 #address-cell 1703 #address-cells = <1>;
1751 #size-cells = 1704 #size-cells = <0>;
1752 status = "dis 1705 status = "disabled";
1753 }; 1706 };
1754 }; 1707 };
1755 1708
1756 rng: rng@10c3000 { !! 1709 pcie0: pci@1c00000 {
1757 compatible = "qcom,sm <<
1758 reg = <0 0x010c3000 0 <<
1759 }; <<
1760 <<
1761 pcie0: pcie@1c00000 { <<
1762 compatible = "qcom,pc 1710 compatible = "qcom,pcie-sm8450-pcie0";
1763 reg = <0 0x01c00000 0 1711 reg = <0 0x01c00000 0 0x3000>,
1764 <0 0x60000000 0 1712 <0 0x60000000 0 0xf1d>,
1765 <0 0x60000f20 0 1713 <0 0x60000f20 0 0xa8>,
1766 <0 0x60001000 0 1714 <0 0x60001000 0 0x1000>,
1767 <0 0x60100000 0 1715 <0 0x60100000 0 0x100000>;
1768 reg-names = "parf", " 1716 reg-names = "parf", "dbi", "elbi", "atu", "config";
1769 device_type = "pci"; 1717 device_type = "pci";
1770 linux,pci-domain = <0 1718 linux,pci-domain = <0>;
1771 bus-range = <0x00 0xf 1719 bus-range = <0x00 0xff>;
1772 num-lanes = <1>; 1720 num-lanes = <1>;
1773 1721
1774 #address-cells = <3>; 1722 #address-cells = <3>;
1775 #size-cells = <2>; 1723 #size-cells = <2>;
1776 1724
1777 ranges = <0x01000000 1725 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
1778 <0x02000000 1726 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1779 1727
1780 msi-map = <0x0 &gic_i !! 1728 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
1781 <0x100 &gic !! 1729 interrupt-names = "msi";
1782 msi-map-mask = <0xff0 <<
1783 interrupts = <GIC_SPI <<
1784 <GIC_SPI <<
1785 <GIC_SPI <<
1786 <GIC_SPI <<
1787 <GIC_SPI <<
1788 <GIC_SPI <<
1789 <GIC_SPI <<
1790 <GIC_SPI <<
1791 interrupt-names = "ms <<
1792 "ms <<
1793 "ms <<
1794 "ms <<
1795 "ms <<
1796 "ms <<
1797 "ms <<
1798 "ms <<
1799 #interrupt-cells = <1 1730 #interrupt-cells = <1>;
1800 interrupt-map-mask = 1731 interrupt-map-mask = <0 0 0 0x7>;
1801 interrupt-map = <0 0 1732 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1802 <0 0 1733 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1803 <0 0 1734 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1804 <0 0 1735 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1805 1736
1806 interconnects = <&pci <<
1807 &mc_ <<
1808 <&gem <<
1809 &con <<
1810 interconnect-names = <<
1811 <<
1812 clocks = <&gcc GCC_PC 1737 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1813 <&gcc GCC_PC 1738 <&gcc GCC_PCIE_0_PIPE_CLK_SRC>,
1814 <&pcie0_phy> !! 1739 <&pcie0_lane>,
1815 <&rpmhcc RPM 1740 <&rpmhcc RPMH_CXO_CLK>,
1816 <&gcc GCC_PC 1741 <&gcc GCC_PCIE_0_AUX_CLK>,
1817 <&gcc GCC_PC 1742 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1818 <&gcc GCC_PC 1743 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1819 <&gcc GCC_PC 1744 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1820 <&gcc GCC_PC 1745 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
1821 <&gcc GCC_DD 1746 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1822 <&gcc GCC_AG 1747 <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
1823 <&gcc GCC_AG 1748 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
1824 clock-names = "pipe", 1749 clock-names = "pipe",
1825 "pipe_m 1750 "pipe_mux",
1826 "phy_pi 1751 "phy_pipe",
1827 "ref", 1752 "ref",
1828 "aux", 1753 "aux",
1829 "cfg", 1754 "cfg",
1830 "bus_ma 1755 "bus_master",
1831 "bus_sl 1756 "bus_slave",
1832 "slave_ 1757 "slave_q2a",
1833 "ddrss_ 1758 "ddrss_sf_tbu",
1834 "aggre0 1759 "aggre0",
1835 "aggre1 1760 "aggre1";
1836 1761
>> 1762 iommus = <&apps_smmu 0x1c00 0x7f>;
1837 iommu-map = <0x0 &a 1763 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
1838 <0x100 &a 1764 <0x100 &apps_smmu 0x1c01 0x1>;
1839 1765
1840 resets = <&gcc GCC_PC 1766 resets = <&gcc GCC_PCIE_0_BCR>;
1841 reset-names = "pci"; 1767 reset-names = "pci";
1842 1768
1843 power-domains = <&gcc 1769 power-domains = <&gcc PCIE_0_GDSC>;
>> 1770 power-domain-names = "gdsc";
1844 1771
1845 phys = <&pcie0_phy>; !! 1772 phys = <&pcie0_lane>;
1846 phy-names = "pciephy" 1773 phy-names = "pciephy";
1847 1774
1848 perst-gpios = <&tlmm 1775 perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
1849 wake-gpios = <&tlmm 9 1776 wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
1850 1777
1851 pinctrl-names = "defa 1778 pinctrl-names = "default";
1852 pinctrl-0 = <&pcie0_d 1779 pinctrl-0 = <&pcie0_default_state>;
1853 1780
1854 operating-points-v2 = <<
1855 <<
1856 status = "disabled"; 1781 status = "disabled";
1857 <<
1858 pcie0_opp_table: opp- <<
1859 compatible = <<
1860 <<
1861 /* GEN 1 x1 * <<
1862 opp-2500000 { <<
1863 opp-h <<
1864 requi <<
1865 opp-p <<
1866 }; <<
1867 <<
1868 /* GEN 2 x1 * <<
1869 opp-5000000 { <<
1870 opp-h <<
1871 requi <<
1872 opp-p <<
1873 }; <<
1874 <<
1875 /* GEN 3 x1 * <<
1876 opp-8000000 { <<
1877 opp-h <<
1878 requi <<
1879 opp-p <<
1880 }; <<
1881 }; <<
1882 <<
1883 pcie@0 { <<
1884 device_type = <<
1885 reg = <0x0 0x <<
1886 bus-range = < <<
1887 <<
1888 #address-cell <<
1889 #size-cells = <<
1890 ranges; <<
1891 }; <<
1892 }; 1782 };
1893 1783
1894 pcie0_phy: phy@1c06000 { 1784 pcie0_phy: phy@1c06000 {
1895 compatible = "qcom,sm 1785 compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy";
1896 reg = <0 0x01c06000 0 !! 1786 reg = <0 0x01c06000 0 0x200>;
1897 !! 1787 #address-cells = <2>;
>> 1788 #size-cells = <2>;
>> 1789 ranges;
1898 clocks = <&gcc GCC_PC 1790 clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
1899 <&gcc GCC_PC 1791 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1900 <&gcc GCC_PC 1792 <&gcc GCC_PCIE_0_CLKREF_EN>,
1901 <&gcc GCC_PC !! 1793 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
1902 <&gcc GCC_PC !! 1794 clock-names = "aux", "cfg_ahb", "ref", "refgen";
1903 clock-names = "aux", <<
1904 "cfg_ah <<
1905 "ref", <<
1906 "rchng" <<
1907 "pipe"; <<
1908 <<
1909 clock-output-names = <<
1910 #clock-cells = <0>; <<
1911 <<
1912 #phy-cells = <0>; <<
1913 1795
1914 resets = <&gcc GCC_PC 1796 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1915 reset-names = "phy"; 1797 reset-names = "phy";
1916 1798
1917 assigned-clocks = <&g 1799 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
1918 assigned-clock-rates 1800 assigned-clock-rates = <100000000>;
1919 1801
1920 status = "disabled"; 1802 status = "disabled";
>> 1803
>> 1804 pcie0_lane: phy@1c06200 {
>> 1805 reg = <0 0x1c06e00 0 0x200>, /* tx */
>> 1806 <0 0x1c07000 0 0x200>, /* rx */
>> 1807 <0 0x1c06200 0 0x200>, /* pcs */
>> 1808 <0 0x1c06600 0 0x200>; /* pcs_pcie */
>> 1809 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
>> 1810 clock-names = "pipe0";
>> 1811
>> 1812 #clock-cells = <0>;
>> 1813 #phy-cells = <0>;
>> 1814 clock-output-names = "pcie_0_pipe_clk";
>> 1815 };
1921 }; 1816 };
1922 1817
1923 pcie1: pcie@1c08000 { !! 1818 pcie1: pci@1c08000 {
1924 compatible = "qcom,pc 1819 compatible = "qcom,pcie-sm8450-pcie1";
1925 reg = <0 0x01c08000 0 1820 reg = <0 0x01c08000 0 0x3000>,
1926 <0 0x40000000 0 1821 <0 0x40000000 0 0xf1d>,
1927 <0 0x40000f20 0 1822 <0 0x40000f20 0 0xa8>,
1928 <0 0x40001000 0 1823 <0 0x40001000 0 0x1000>,
1929 <0 0x40100000 0 1824 <0 0x40100000 0 0x100000>;
1930 reg-names = "parf", " 1825 reg-names = "parf", "dbi", "elbi", "atu", "config";
1931 device_type = "pci"; 1826 device_type = "pci";
1932 linux,pci-domain = <1 1827 linux,pci-domain = <1>;
1933 bus-range = <0x00 0xf 1828 bus-range = <0x00 0xff>;
1934 num-lanes = <2>; 1829 num-lanes = <2>;
1935 1830
1936 #address-cells = <3>; 1831 #address-cells = <3>;
1937 #size-cells = <2>; 1832 #size-cells = <2>;
1938 1833
1939 ranges = <0x01000000 1834 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
1940 <0x02000000 1835 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1941 1836
1942 msi-map = <0x0 &gic_i !! 1837 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
1943 <0x100 &gic !! 1838 interrupt-names = "msi";
1944 msi-map-mask = <0xff0 <<
1945 interrupts = <GIC_SPI <<
1946 <GIC_SPI <<
1947 <GIC_SPI <<
1948 <GIC_SPI <<
1949 <GIC_SPI <<
1950 <GIC_SPI <<
1951 <GIC_SPI <<
1952 <GIC_SPI <<
1953 interrupt-names = "ms <<
1954 "ms <<
1955 "ms <<
1956 "ms <<
1957 "ms <<
1958 "ms <<
1959 "ms <<
1960 "ms <<
1961 #interrupt-cells = <1 1839 #interrupt-cells = <1>;
1962 interrupt-map-mask = 1840 interrupt-map-mask = <0 0 0 0x7>;
1963 interrupt-map = <0 0 1841 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1964 <0 0 1842 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1965 <0 0 1843 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1966 <0 0 1844 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1967 1845
1968 interconnects = <&pci <<
1969 &mc_ <<
1970 <&gem <<
1971 &con <<
1972 interconnect-names = <<
1973 <<
1974 clocks = <&gcc GCC_PC 1846 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1975 <&gcc GCC_PC 1847 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>,
1976 <&pcie1_phy !! 1848 <&pcie1_lane>,
1977 <&rpmhcc RPM 1849 <&rpmhcc RPMH_CXO_CLK>,
1978 <&gcc GCC_PC 1850 <&gcc GCC_PCIE_1_AUX_CLK>,
1979 <&gcc GCC_PC 1851 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1980 <&gcc GCC_PC 1852 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1981 <&gcc GCC_PC 1853 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
1982 <&gcc GCC_PC 1854 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
1983 <&gcc GCC_DD 1855 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1984 <&gcc GCC_AG 1856 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
1985 clock-names = "pipe", 1857 clock-names = "pipe",
1986 "pipe_m 1858 "pipe_mux",
1987 "phy_pi 1859 "phy_pipe",
1988 "ref", 1860 "ref",
1989 "aux", 1861 "aux",
1990 "cfg", 1862 "cfg",
1991 "bus_ma 1863 "bus_master",
1992 "bus_sl 1864 "bus_slave",
1993 "slave_ 1865 "slave_q2a",
1994 "ddrss_ 1866 "ddrss_sf_tbu",
1995 "aggre1 1867 "aggre1";
1996 1868
>> 1869 iommus = <&apps_smmu 0x1c80 0x7f>;
1997 iommu-map = <0x0 &a 1870 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
1998 <0x100 &a 1871 <0x100 &apps_smmu 0x1c81 0x1>;
1999 1872
2000 resets = <&gcc GCC_PC 1873 resets = <&gcc GCC_PCIE_1_BCR>;
2001 reset-names = "pci"; 1874 reset-names = "pci";
2002 1875
2003 power-domains = <&gcc 1876 power-domains = <&gcc PCIE_1_GDSC>;
>> 1877 power-domain-names = "gdsc";
2004 1878
2005 phys = <&pcie1_phy>; !! 1879 phys = <&pcie1_lane>;
2006 phy-names = "pciephy" 1880 phy-names = "pciephy";
2007 1881
2008 perst-gpios = <&tlmm 1882 perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
2009 wake-gpios = <&tlmm 9 1883 wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
2010 1884
2011 pinctrl-names = "defa 1885 pinctrl-names = "default";
2012 pinctrl-0 = <&pcie1_d 1886 pinctrl-0 = <&pcie1_default_state>;
2013 1887
2014 operating-points-v2 = <<
2015 <<
2016 status = "disabled"; 1888 status = "disabled";
2017 <<
2018 pcie1_opp_table: opp- <<
2019 compatible = <<
2020 <<
2021 /* GEN 1 x1 * <<
2022 opp-2500000 { <<
2023 opp-h <<
2024 requi <<
2025 opp-p <<
2026 }; <<
2027 <<
2028 /* GEN 1 x2 a <<
2029 opp-5000000 { <<
2030 opp-h <<
2031 requi <<
2032 opp-p <<
2033 }; <<
2034 <<
2035 /* GEN 2 x2 * <<
2036 opp-10000000 <<
2037 opp-h <<
2038 requi <<
2039 opp-p <<
2040 }; <<
2041 <<
2042 /* GEN 3 x1 * <<
2043 opp-8000000 { <<
2044 opp-h <<
2045 requi <<
2046 opp-p <<
2047 }; <<
2048 <<
2049 /* GEN 3 x2 a <<
2050 opp-16000000 <<
2051 opp-h <<
2052 requi <<
2053 opp-p <<
2054 }; <<
2055 <<
2056 /* GEN 4 x2 * <<
2057 opp-32000000 <<
2058 opp-h <<
2059 requi <<
2060 opp-p <<
2061 }; <<
2062 }; <<
2063 <<
2064 pcie@0 { <<
2065 device_type = <<
2066 reg = <0x0 0x <<
2067 bus-range = < <<
2068 <<
2069 #address-cell <<
2070 #size-cells = <<
2071 ranges; <<
2072 }; <<
2073 }; 1889 };
2074 1890
2075 pcie1_phy: phy@1c0e000 { !! 1891 pcie1_phy: phy@1c0f000 {
2076 compatible = "qcom,sm 1892 compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy";
2077 reg = <0 0x01c0e000 0 !! 1893 reg = <0 0x01c0f000 0 0x200>;
2078 !! 1894 #address-cells = <2>;
>> 1895 #size-cells = <2>;
>> 1896 ranges;
2079 clocks = <&gcc GCC_PC 1897 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>,
2080 <&gcc GCC_PC 1898 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2081 <&gcc GCC_PC 1899 <&gcc GCC_PCIE_1_CLKREF_EN>,
2082 <&gcc GCC_PC !! 1900 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
2083 <&gcc GCC_PC !! 1901 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2084 clock-names = "aux", <<
2085 "cfg_ah <<
2086 "ref", <<
2087 "rchng" <<
2088 "pipe"; <<
2089 <<
2090 clock-output-names = <<
2091 #clock-cells = <1>; <<
2092 <<
2093 #phy-cells = <0>; <<
2094 1902
2095 resets = <&gcc GCC_PC 1903 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2096 reset-names = "phy"; 1904 reset-names = "phy";
2097 1905
2098 assigned-clocks = <&g 1906 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
2099 assigned-clock-rates 1907 assigned-clock-rates = <100000000>;
2100 1908
2101 status = "disabled"; 1909 status = "disabled";
>> 1910
>> 1911 pcie1_lane: phy@1c0e000 {
>> 1912 reg = <0 0x1c0e000 0 0x200>, /* tx */
>> 1913 <0 0x1c0e200 0 0x300>, /* rx */
>> 1914 <0 0x1c0f200 0 0x200>, /* pcs */
>> 1915 <0 0x1c0e800 0 0x200>, /* tx */
>> 1916 <0 0x1c0ea00 0 0x300>, /* rx */
>> 1917 <0 0x1c0f400 0 0xc00>; /* pcs_pcie */
>> 1918 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
>> 1919 clock-names = "pipe0";
>> 1920
>> 1921 #clock-cells = <0>;
>> 1922 #phy-cells = <0>;
>> 1923 clock-output-names = "pcie_1_pipe_clk";
>> 1924 };
2102 }; 1925 };
2103 1926
2104 config_noc: interconnect@1500 1927 config_noc: interconnect@1500000 {
2105 compatible = "qcom,sm 1928 compatible = "qcom,sm8450-config-noc";
2106 reg = <0 0x01500000 0 1929 reg = <0 0x01500000 0 0x1c000>;
2107 #interconnect-cells = 1930 #interconnect-cells = <2>;
2108 qcom,bcm-voters = <&a 1931 qcom,bcm-voters = <&apps_bcm_voter>;
2109 }; 1932 };
2110 1933
2111 system_noc: interconnect@1680 1934 system_noc: interconnect@1680000 {
2112 compatible = "qcom,sm 1935 compatible = "qcom,sm8450-system-noc";
2113 reg = <0 0x01680000 0 1936 reg = <0 0x01680000 0 0x1e200>;
2114 #interconnect-cells = 1937 #interconnect-cells = <2>;
2115 qcom,bcm-voters = <&a 1938 qcom,bcm-voters = <&apps_bcm_voter>;
2116 }; 1939 };
2117 1940
2118 pcie_noc: interconnect@16c000 1941 pcie_noc: interconnect@16c0000 {
2119 compatible = "qcom,sm 1942 compatible = "qcom,sm8450-pcie-anoc";
2120 reg = <0 0x016c0000 0 1943 reg = <0 0x016c0000 0 0xe280>;
2121 #interconnect-cells = 1944 #interconnect-cells = <2>;
2122 qcom,bcm-voters = <&a 1945 qcom,bcm-voters = <&apps_bcm_voter>;
2123 }; 1946 };
2124 1947
2125 aggre1_noc: interconnect@16e0 1948 aggre1_noc: interconnect@16e0000 {
2126 compatible = "qcom,sm 1949 compatible = "qcom,sm8450-aggre1-noc";
2127 reg = <0 0x016e0000 0 1950 reg = <0 0x016e0000 0 0x1c080>;
2128 #interconnect-cells = 1951 #interconnect-cells = <2>;
2129 clocks = <&gcc GCC_AG 1952 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2130 <&gcc GCC_AG 1953 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
2131 qcom,bcm-voters = <&a 1954 qcom,bcm-voters = <&apps_bcm_voter>;
2132 }; 1955 };
2133 1956
2134 aggre2_noc: interconnect@1700 1957 aggre2_noc: interconnect@1700000 {
2135 compatible = "qcom,sm 1958 compatible = "qcom,sm8450-aggre2-noc";
2136 reg = <0 0x01700000 0 1959 reg = <0 0x01700000 0 0x31080>;
2137 #interconnect-cells = 1960 #interconnect-cells = <2>;
2138 qcom,bcm-voters = <&a 1961 qcom,bcm-voters = <&apps_bcm_voter>;
2139 clocks = <&gcc GCC_AG 1962 clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
2140 <&gcc GCC_AG 1963 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
2141 <&gcc GCC_AG 1964 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2142 <&rpmhcc RPM 1965 <&rpmhcc RPMH_IPA_CLK>;
2143 }; 1966 };
2144 1967
2145 mmss_noc: interconnect@174000 1968 mmss_noc: interconnect@1740000 {
2146 compatible = "qcom,sm 1969 compatible = "qcom,sm8450-mmss-noc";
2147 reg = <0 0x01740000 0 1970 reg = <0 0x01740000 0 0x1f080>;
2148 #interconnect-cells = 1971 #interconnect-cells = <2>;
2149 qcom,bcm-voters = <&a 1972 qcom,bcm-voters = <&apps_bcm_voter>;
2150 }; 1973 };
2151 1974
2152 tcsr_mutex: hwlock@1f40000 { 1975 tcsr_mutex: hwlock@1f40000 {
2153 compatible = "qcom,tc 1976 compatible = "qcom,tcsr-mutex";
2154 reg = <0x0 0x01f40000 1977 reg = <0x0 0x01f40000 0x0 0x40000>;
2155 #hwlock-cells = <1>; 1978 #hwlock-cells = <1>;
2156 }; 1979 };
2157 1980
2158 tcsr: syscon@1fc0000 { <<
2159 compatible = "qcom,sm <<
2160 reg = <0x0 0x1fc0000 <<
2161 }; <<
2162 <<
2163 gpu: gpu@3d00000 { <<
2164 compatible = "qcom,ad <<
2165 reg = <0x0 0x03d00000 <<
2166 <0x0 0x03d9e000 <<
2167 <0x0 0x03d61000 <<
2168 reg-names = "kgsl_3d0 <<
2169 "cx_mem", <<
2170 "cx_dbgc" <<
2171 <<
2172 interrupts = <GIC_SPI <<
2173 <<
2174 iommus = <&adreno_smm <<
2175 <&adreno_smm <<
2176 <<
2177 operating-points-v2 = <<
2178 <<
2179 qcom,gmu = <&gmu>; <<
2180 #cooling-cells = <2>; <<
2181 <<
2182 status = "disabled"; <<
2183 <<
2184 zap-shader { <<
2185 memory-region <<
2186 }; <<
2187 <<
2188 gpu_opp_table: opp-ta <<
2189 compatible = <<
2190 <<
2191 opp-818000000 <<
2192 opp-h <<
2193 opp-l <<
2194 }; <<
2195 <<
2196 opp-791000000 <<
2197 opp-h <<
2198 opp-l <<
2199 }; <<
2200 <<
2201 opp-734000000 <<
2202 opp-h <<
2203 opp-l <<
2204 }; <<
2205 <<
2206 opp-640000000 <<
2207 opp-h <<
2208 opp-l <<
2209 }; <<
2210 <<
2211 opp-599000000 <<
2212 opp-h <<
2213 opp-l <<
2214 }; <<
2215 <<
2216 opp-545000000 <<
2217 opp-h <<
2218 opp-l <<
2219 }; <<
2220 <<
2221 opp-492000000 <<
2222 opp-h <<
2223 opp-l <<
2224 }; <<
2225 <<
2226 opp-421000000 <<
2227 opp-h <<
2228 opp-l <<
2229 }; <<
2230 <<
2231 opp-350000000 <<
2232 opp-h <<
2233 opp-l <<
2234 }; <<
2235 <<
2236 opp-317000000 <<
2237 opp-h <<
2238 opp-l <<
2239 }; <<
2240 <<
2241 opp-285000000 <<
2242 opp-h <<
2243 opp-l <<
2244 }; <<
2245 <<
2246 opp-220000000 <<
2247 opp-h <<
2248 opp-l <<
2249 }; <<
2250 }; <<
2251 }; <<
2252 <<
2253 gmu: gmu@3d6a000 { <<
2254 compatible = "qcom,ad <<
2255 reg = <0x0 0x03d6a000 <<
2256 <0x0 0x03d50000 <<
2257 <0x0 0x0b290000 <<
2258 reg-names = "gmu", "r <<
2259 <<
2260 interrupts = <GIC_SPI <<
2261 <GIC_SPI <<
2262 interrupt-names = "hf <<
2263 <<
2264 clocks = <&gpucc GPU_ <<
2265 <&gpucc GPU_ <<
2266 <&gpucc GPU_ <<
2267 <&gcc GCC_DD <<
2268 <&gcc GCC_GP <<
2269 <&gpucc GPU_ <<
2270 <&gpucc GPU_ <<
2271 clock-names = "ahb", <<
2272 "gmu", <<
2273 "cxo", <<
2274 "axi", <<
2275 "memnoc <<
2276 "hub", <<
2277 "demet" <<
2278 <<
2279 power-domains = <&gpu <<
2280 <&gpu <<
2281 power-domain-names = <<
2282 <<
2283 <<
2284 iommus = <&adreno_smm <<
2285 <<
2286 qcom,qmp = <&aoss_qmp <<
2287 <<
2288 operating-points-v2 = <<
2289 <<
2290 gmu_opp_table: opp-ta <<
2291 compatible = <<
2292 <<
2293 opp-500000000 <<
2294 opp-h <<
2295 opp-l <<
2296 }; <<
2297 <<
2298 opp-200000000 <<
2299 opp-h <<
2300 opp-l <<
2301 }; <<
2302 }; <<
2303 }; <<
2304 <<
2305 gpucc: clock-controller@3d900 <<
2306 compatible = "qcom,sm <<
2307 reg = <0x0 0x03d90000 <<
2308 clocks = <&rpmhcc RPM <<
2309 <&gcc GCC_GP <<
2310 <&gcc GCC_GP <<
2311 #clock-cells = <1>; <<
2312 #reset-cells = <1>; <<
2313 #power-domain-cells = <<
2314 }; <<
2315 <<
2316 adreno_smmu: iommu@3da0000 { <<
2317 compatible = "qcom,sm <<
2318 "qcom,sm <<
2319 reg = <0x0 0x03da0000 <<
2320 #iommu-cells = <2>; <<
2321 #global-interrupts = <<
2322 interrupts = <GIC_SPI <<
2323 <GIC_SPI <<
2324 <GIC_SPI <<
2325 <GIC_SPI <<
2326 <GIC_SPI <<
2327 <GIC_SPI <<
2328 <GIC_SPI <<
2329 <GIC_SPI <<
2330 <GIC_SPI <<
2331 <GIC_SPI <<
2332 <GIC_SPI <<
2333 <GIC_SPI <<
2334 <GIC_SPI <<
2335 <GIC_SPI <<
2336 <GIC_SPI <<
2337 <GIC_SPI <<
2338 <GIC_SPI <<
2339 <GIC_SPI <<
2340 <GIC_SPI <<
2341 <GIC_SPI <<
2342 <GIC_SPI <<
2343 <GIC_SPI <<
2344 <GIC_SPI <<
2345 <GIC_SPI <<
2346 <GIC_SPI <<
2347 <GIC_SPI <<
2348 clocks = <&gpucc GPU_ <<
2349 <&gpucc GPU_ <<
2350 <&gpucc GPU_ <<
2351 <&gcc GCC_GP <<
2352 <&gcc GCC_GP <<
2353 <&gpucc GPU_ <<
2354 clock-names = "gmu", <<
2355 "hub", <<
2356 "hlos", <<
2357 "bus", <<
2358 "iface" <<
2359 "ahb"; <<
2360 power-domains = <&gpu <<
2361 dma-coherent; <<
2362 }; <<
2363 <<
2364 usb_1_hsphy: phy@88e3000 { 1981 usb_1_hsphy: phy@88e3000 {
2365 compatible = "qcom,sm 1982 compatible = "qcom,sm8450-usb-hs-phy",
2366 "qcom,us 1983 "qcom,usb-snps-hs-7nm-phy";
2367 reg = <0 0x088e3000 0 1984 reg = <0 0x088e3000 0 0x400>;
2368 status = "disabled"; 1985 status = "disabled";
2369 #phy-cells = <0>; 1986 #phy-cells = <0>;
2370 1987
2371 clocks = <&rpmhcc RPM 1988 clocks = <&rpmhcc RPMH_CXO_CLK>;
2372 clock-names = "ref"; 1989 clock-names = "ref";
2373 1990
2374 resets = <&gcc GCC_QU 1991 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2375 }; 1992 };
2376 1993
2377 usb_1_qmpphy: phy@88e8000 { !! 1994 usb_1_qmpphy: phy-wrapper@88e9000 {
2378 compatible = "qcom,sm !! 1995 compatible = "qcom,sm8450-qmp-usb3-phy";
2379 reg = <0 0x088e8000 0 !! 1996 reg = <0 0x088e9000 0 0x200>,
>> 1997 <0 0x088e8000 0 0x20>;
>> 1998 status = "disabled";
>> 1999 #address-cells = <2>;
>> 2000 #size-cells = <2>;
>> 2001 ranges;
2380 2002
2381 clocks = <&gcc GCC_US 2003 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2382 <&rpmhcc RPM 2004 <&rpmhcc RPMH_CXO_CLK>,
2383 <&gcc GCC_US !! 2005 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
2384 <&gcc GCC_US !! 2006 clock-names = "aux", "ref_clk_src", "com_aux";
2385 clock-names = "aux", <<
2386 2007
2387 resets = <&gcc GCC_US 2008 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
2388 <&gcc GCC_US 2009 <&gcc GCC_USB3_PHY_PRIM_BCR>;
2389 reset-names = "phy", 2010 reset-names = "phy", "common";
2390 2011
2391 #clock-cells = <1>; !! 2012 usb_1_ssphy: phy@88e9200 {
2392 #phy-cells = <1>; !! 2013 reg = <0 0x088e9200 0 0x200>,
2393 !! 2014 <0 0x088e9400 0 0x200>,
2394 orientation-switch; !! 2015 <0 0x088e9c00 0 0x400>,
2395 !! 2016 <0 0x088e9600 0 0x200>,
2396 status = "disabled"; !! 2017 <0 0x088e9800 0 0x200>,
2397 !! 2018 <0 0x088e9a00 0 0x100>;
2398 ports { !! 2019 #phy-cells = <0>;
2399 #address-cell !! 2020 #clock-cells = <0>;
2400 #size-cells = !! 2021 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2401 !! 2022 clock-names = "pipe0";
2402 port@0 { !! 2023 clock-output-names = "usb3_phy_pipe_clk_src";
2403 reg = <<
2404 <<
2405 usb_1 <<
2406 }; <<
2407 }; <<
2408 <<
2409 port@1 { <<
2410 reg = <<
2411 <<
2412 usb_1 <<
2413 <<
2414 }; <<
2415 }; <<
2416 <<
2417 port@2 { <<
2418 reg = <<
2419 <<
2420 usb_1 <<
2421 <<
2422 }; <<
2423 }; <<
2424 }; 2024 };
2425 }; 2025 };
2426 2026
2427 remoteproc_slpi: remoteproc@2 2027 remoteproc_slpi: remoteproc@2400000 {
2428 compatible = "qcom,sm 2028 compatible = "qcom,sm8450-slpi-pas";
2429 reg = <0 0x02400000 0 2029 reg = <0 0x02400000 0 0x4000>;
2430 2030
2431 interrupts-extended = 2031 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>,
2432 2032 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
2433 2033 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
2434 2034 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
2435 2035 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
2436 interrupt-names = "wd 2036 interrupt-names = "wdog", "fatal", "ready",
2437 "ha 2037 "handover", "stop-ack";
2438 2038
2439 clocks = <&rpmhcc RPM 2039 clocks = <&rpmhcc RPMH_CXO_CLK>;
2440 clock-names = "xo"; 2040 clock-names = "xo";
2441 2041
2442 power-domains = <&rpm !! 2042 power-domains = <&rpmhpd SM8450_LCX>,
2443 <&rpm !! 2043 <&rpmhpd SM8450_LMX>;
2444 power-domain-names = 2044 power-domain-names = "lcx", "lmx";
2445 2045
2446 memory-region = <&slp 2046 memory-region = <&slpi_mem>;
2447 2047
2448 qcom,qmp = <&aoss_qmp 2048 qcom,qmp = <&aoss_qmp>;
2449 2049
2450 qcom,smem-states = <& 2050 qcom,smem-states = <&smp2p_slpi_out 0>;
2451 qcom,smem-state-names 2051 qcom,smem-state-names = "stop";
2452 2052
2453 status = "disabled"; 2053 status = "disabled";
2454 2054
2455 glink-edge { 2055 glink-edge {
2456 interrupts-ex 2056 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
2457 2057 IPCC_MPROC_SIGNAL_GLINK_QMP
2458 2058 IRQ_TYPE_EDGE_RISING>;
2459 mboxes = <&ip 2059 mboxes = <&ipcc IPCC_CLIENT_SLPI
2460 2060 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2461 2061
2462 label = "slpi 2062 label = "slpi";
2463 qcom,remote-p 2063 qcom,remote-pid = <3>;
2464 2064
2465 fastrpc { 2065 fastrpc {
2466 compa 2066 compatible = "qcom,fastrpc";
2467 qcom, 2067 qcom,glink-channels = "fastrpcglink-apps-dsp";
2468 label 2068 label = "sdsp";
2469 qcom, <<
2470 #addr 2069 #address-cells = <1>;
2471 #size 2070 #size-cells = <0>;
2472 2071
2473 compu 2072 compute-cb@1 {
2474 2073 compatible = "qcom,fastrpc-compute-cb";
2475 2074 reg = <1>;
2476 2075 iommus = <&apps_smmu 0x0541 0x0>;
2477 }; 2076 };
2478 2077
2479 compu 2078 compute-cb@2 {
2480 2079 compatible = "qcom,fastrpc-compute-cb";
2481 2080 reg = <2>;
2482 2081 iommus = <&apps_smmu 0x0542 0x0>;
2483 }; 2082 };
2484 2083
2485 compu 2084 compute-cb@3 {
2486 2085 compatible = "qcom,fastrpc-compute-cb";
2487 2086 reg = <3>;
2488 2087 iommus = <&apps_smmu 0x0543 0x0>;
2489 2088 /* note: shared-cb = <4> in downstream */
2490 }; 2089 };
2491 }; 2090 };
2492 }; 2091 };
2493 }; 2092 };
2494 2093
2495 wsa2macro: codec@31e0000 { <<
2496 compatible = "qcom,sm <<
2497 reg = <0 0x031e0000 0 <<
2498 clocks = <&q6prmcc LP <<
2499 <&q6prmcc LP <<
2500 <&q6prmcc LP <<
2501 <&q6prmcc LP <<
2502 <&vamacro>; <<
2503 clock-names = "mclk", <<
2504 <<
2505 #clock-cells = <0>; <<
2506 clock-output-names = <<
2507 #sound-dai-cells = <1 <<
2508 }; <<
2509 <<
2510 swr4: soundwire@31f0000 { <<
2511 compatible = "qcom,so <<
2512 reg = <0 0x031f0000 0 <<
2513 interrupts = <GIC_SPI <<
2514 clocks = <&wsa2macro> <<
2515 clock-names = "iface" <<
2516 label = "WSA2"; <<
2517 <<
2518 pinctrl-0 = <&wsa2_sw <<
2519 pinctrl-names = "defa <<
2520 <<
2521 qcom,din-ports = <2>; <<
2522 qcom,dout-ports = <6> <<
2523 <<
2524 qcom,ports-sinterval- <<
2525 qcom,ports-offset1 = <<
2526 qcom,ports-offset2 = <<
2527 qcom,ports-hstart = <<
2528 qcom,ports-hstop = <<
2529 qcom,ports-word-lengt <<
2530 qcom,ports-block-pack <<
2531 qcom,ports-block-grou <<
2532 qcom,ports-lane-contr <<
2533 <<
2534 #address-cells = <2>; <<
2535 #size-cells = <0>; <<
2536 #sound-dai-cells = <1 <<
2537 status = "disabled"; <<
2538 }; <<
2539 <<
2540 rxmacro: codec@3200000 { <<
2541 compatible = "qcom,sm <<
2542 reg = <0 0x03200000 0 <<
2543 clocks = <&q6prmcc LP <<
2544 <&q6prmcc LP <<
2545 <&q6prmcc LP <<
2546 <&q6prmcc LP <<
2547 <&vamacro>; <<
2548 clock-names = "mclk", <<
2549 <<
2550 #clock-cells = <0>; <<
2551 clock-output-names = <<
2552 #sound-dai-cells = <1 <<
2553 }; <<
2554 <<
2555 swr1: soundwire@3210000 { <<
2556 compatible = "qcom,so <<
2557 reg = <0 0x03210000 0 <<
2558 interrupts = <GIC_SPI <<
2559 clocks = <&rxmacro>; <<
2560 clock-names = "iface" <<
2561 label = "RX"; <<
2562 qcom,din-ports = <0>; <<
2563 qcom,dout-ports = <5> <<
2564 <<
2565 pinctrl-0 = <&rx_swr_ <<
2566 pinctrl-names = "defa <<
2567 <<
2568 qcom,ports-sinterval- <<
2569 qcom,ports-offset1 = <<
2570 qcom,ports-offset2 = <<
2571 qcom,ports-hstart = <<
2572 qcom,ports-hstop = <<
2573 qcom,ports-word-lengt <<
2574 qcom,ports-block-pack <<
2575 qcom,ports-block-grou <<
2576 qcom,ports-lane-contr <<
2577 <<
2578 #address-cells = <2>; <<
2579 #size-cells = <0>; <<
2580 #sound-dai-cells = <1 <<
2581 status = "disabled"; <<
2582 }; <<
2583 <<
2584 txmacro: codec@3220000 { <<
2585 compatible = "qcom,sm <<
2586 reg = <0 0x03220000 0 <<
2587 clocks = <&q6prmcc LP <<
2588 <&q6prmcc LP <<
2589 <&q6prmcc LP <<
2590 <&q6prmcc LP <<
2591 <&vamacro>; <<
2592 clock-names = "mclk", <<
2593 <<
2594 #clock-cells = <0>; <<
2595 clock-output-names = <<
2596 #sound-dai-cells = <1 <<
2597 }; <<
2598 <<
2599 wsamacro: codec@3240000 { <<
2600 compatible = "qcom,sm <<
2601 reg = <0 0x03240000 0 <<
2602 clocks = <&q6prmcc LP <<
2603 <&q6prmcc LP <<
2604 <&q6prmcc LP <<
2605 <&q6prmcc LP <<
2606 <&vamacro>; <<
2607 clock-names = "mclk", <<
2608 <<
2609 #clock-cells = <0>; <<
2610 clock-output-names = <<
2611 #sound-dai-cells = <1 <<
2612 }; <<
2613 <<
2614 swr0: soundwire@3250000 { <<
2615 compatible = "qcom,so <<
2616 reg = <0 0x03250000 0 <<
2617 interrupts = <GIC_SPI <<
2618 clocks = <&wsamacro>; <<
2619 clock-names = "iface" <<
2620 label = "WSA"; <<
2621 <<
2622 pinctrl-0 = <&wsa_swr <<
2623 pinctrl-names = "defa <<
2624 <<
2625 qcom,din-ports = <2>; <<
2626 qcom,dout-ports = <6> <<
2627 <<
2628 qcom,ports-sinterval- <<
2629 qcom,ports-offset1 = <<
2630 qcom,ports-offset2 = <<
2631 qcom,ports-hstart = <<
2632 qcom,ports-hstop = <<
2633 qcom,ports-word-lengt <<
2634 qcom,ports-block-pack <<
2635 qcom,ports-block-grou <<
2636 qcom,ports-lane-contr <<
2637 <<
2638 #address-cells = <2>; <<
2639 #size-cells = <0>; <<
2640 #sound-dai-cells = <1 <<
2641 status = "disabled"; <<
2642 }; <<
2643 <<
2644 swr2: soundwire@33b0000 { <<
2645 compatible = "qcom,so <<
2646 reg = <0 0x033b0000 0 <<
2647 interrupts = <GIC_SPI <<
2648 <GIC_SPI <<
2649 interrupt-names = "co <<
2650 <<
2651 clocks = <&txmacro>; <<
2652 clock-names = "iface" <<
2653 label = "TX"; <<
2654 <<
2655 pinctrl-0 = <&tx_swr_ <<
2656 pinctrl-names = "defa <<
2657 <<
2658 qcom,din-ports = <4>; <<
2659 qcom,dout-ports = <0> <<
2660 qcom,ports-sinterval- <<
2661 qcom,ports-offset1 = <<
2662 qcom,ports-offset2 = <<
2663 qcom,ports-hstart = <<
2664 qcom,ports-hstop = <<
2665 qcom,ports-word-lengt <<
2666 qcom,ports-block-pack <<
2667 qcom,ports-block-grou <<
2668 qcom,ports-lane-contr <<
2669 <<
2670 #address-cells = <2>; <<
2671 #size-cells = <0>; <<
2672 #sound-dai-cells = <1 <<
2673 status = "disabled"; <<
2674 }; <<
2675 <<
2676 vamacro: codec@33f0000 { <<
2677 compatible = "qcom,sm <<
2678 reg = <0 0x033f0000 0 <<
2679 clocks = <&q6prmcc LP <<
2680 <&q6prmcc LP <<
2681 <&q6prmcc LP <<
2682 <&q6prmcc LP <<
2683 clock-names = "mclk", <<
2684 <<
2685 #clock-cells = <0>; <<
2686 clock-output-names = <<
2687 #sound-dai-cells = <1 <<
2688 status = "disabled"; <<
2689 }; <<
2690 <<
2691 remoteproc_adsp: remoteproc@3 2094 remoteproc_adsp: remoteproc@30000000 {
2692 compatible = "qcom,sm 2095 compatible = "qcom,sm8450-adsp-pas";
2693 reg = <0 0x30000000 0 !! 2096 reg = <0 0x030000000 0 0x100>;
2694 2097
2695 interrupts-extended = 2098 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
2696 2099 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
2697 2100 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
2698 2101 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
2699 2102 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
2700 interrupt-names = "wd 2103 interrupt-names = "wdog", "fatal", "ready",
2701 "ha 2104 "handover", "stop-ack";
2702 2105
2703 clocks = <&rpmhcc RPM 2106 clocks = <&rpmhcc RPMH_CXO_CLK>;
2704 clock-names = "xo"; 2107 clock-names = "xo";
2705 2108
2706 power-domains = <&rpm !! 2109 power-domains = <&rpmhpd SM8450_LCX>,
2707 <&rpm !! 2110 <&rpmhpd SM8450_LMX>;
2708 power-domain-names = 2111 power-domain-names = "lcx", "lmx";
2709 2112
2710 memory-region = <&ads 2113 memory-region = <&adsp_mem>;
2711 2114
2712 qcom,qmp = <&aoss_qmp 2115 qcom,qmp = <&aoss_qmp>;
2713 2116
2714 qcom,smem-states = <& 2117 qcom,smem-states = <&smp2p_adsp_out 0>;
2715 qcom,smem-state-names 2118 qcom,smem-state-names = "stop";
2716 2119
2717 status = "disabled"; 2120 status = "disabled";
2718 2121
2719 remoteproc_adsp_glink 2122 remoteproc_adsp_glink: glink-edge {
2720 interrupts-ex 2123 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
2721 2124 IPCC_MPROC_SIGNAL_GLINK_QMP
2722 2125 IRQ_TYPE_EDGE_RISING>;
2723 mboxes = <&ip 2126 mboxes = <&ipcc IPCC_CLIENT_LPASS
2724 2127 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2725 2128
2726 label = "lpas 2129 label = "lpass";
2727 qcom,remote-p 2130 qcom,remote-pid = <2>;
2728 2131
2729 gpr { <<
2730 compa <<
2731 qcom, <<
2732 qcom, <<
2733 qcom, <<
2734 #addr <<
2735 #size <<
2736 <<
2737 q6apm <<
2738 <<
2739 <<
2740 <<
2741 <<
2742 <<
2743 <<
2744 <<
2745 <<
2746 <<
2747 <<
2748 <<
2749 <<
2750 <<
2751 <<
2752 <<
2753 }; <<
2754 <<
2755 q6prm <<
2756 <<
2757 <<
2758 <<
2759 <<
2760 <<
2761 <<
2762 <<
2763 <<
2764 <<
2765 }; <<
2766 }; <<
2767 <<
2768 fastrpc { 2132 fastrpc {
2769 compa 2133 compatible = "qcom,fastrpc";
2770 qcom, 2134 qcom,glink-channels = "fastrpcglink-apps-dsp";
2771 label 2135 label = "adsp";
2772 qcom, <<
2773 #addr 2136 #address-cells = <1>;
2774 #size 2137 #size-cells = <0>;
2775 2138
2776 compu 2139 compute-cb@3 {
2777 2140 compatible = "qcom,fastrpc-compute-cb";
2778 2141 reg = <3>;
2779 2142 iommus = <&apps_smmu 0x1803 0x0>;
2780 }; 2143 };
2781 2144
2782 compu 2145 compute-cb@4 {
2783 2146 compatible = "qcom,fastrpc-compute-cb";
2784 2147 reg = <4>;
2785 2148 iommus = <&apps_smmu 0x1804 0x0>;
2786 }; 2149 };
2787 2150
2788 compu 2151 compute-cb@5 {
2789 2152 compatible = "qcom,fastrpc-compute-cb";
2790 2153 reg = <5>;
2791 2154 iommus = <&apps_smmu 0x1805 0x0>;
2792 }; 2155 };
2793 }; 2156 };
2794 }; 2157 };
2795 }; 2158 };
2796 2159
2797 remoteproc_cdsp: remoteproc@3 2160 remoteproc_cdsp: remoteproc@32300000 {
2798 compatible = "qcom,sm 2161 compatible = "qcom,sm8450-cdsp-pas";
2799 reg = <0 0x32300000 0 !! 2162 reg = <0 0x032300000 0 0x1400000>;
2800 2163
2801 interrupts-extended = 2164 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
2802 2165 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
2803 2166 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
2804 2167 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
2805 2168 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
2806 interrupt-names = "wd 2169 interrupt-names = "wdog", "fatal", "ready",
2807 "ha 2170 "handover", "stop-ack";
2808 2171
2809 clocks = <&rpmhcc RPM 2172 clocks = <&rpmhcc RPMH_CXO_CLK>;
2810 clock-names = "xo"; 2173 clock-names = "xo";
2811 2174
2812 power-domains = <&rpm !! 2175 power-domains = <&rpmhpd SM8450_CX>,
2813 <&rpm !! 2176 <&rpmhpd SM8450_MXC>;
2814 power-domain-names = 2177 power-domain-names = "cx", "mxc";
2815 2178
2816 memory-region = <&cds 2179 memory-region = <&cdsp_mem>;
2817 2180
2818 qcom,qmp = <&aoss_qmp 2181 qcom,qmp = <&aoss_qmp>;
2819 2182
2820 qcom,smem-states = <& 2183 qcom,smem-states = <&smp2p_cdsp_out 0>;
2821 qcom,smem-state-names 2184 qcom,smem-state-names = "stop";
2822 2185
2823 status = "disabled"; 2186 status = "disabled";
2824 2187
2825 glink-edge { 2188 glink-edge {
2826 interrupts-ex 2189 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
2827 2190 IPCC_MPROC_SIGNAL_GLINK_QMP
2828 2191 IRQ_TYPE_EDGE_RISING>;
2829 mboxes = <&ip 2192 mboxes = <&ipcc IPCC_CLIENT_CDSP
2830 2193 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2831 2194
2832 label = "cdsp 2195 label = "cdsp";
2833 qcom,remote-p 2196 qcom,remote-pid = <5>;
2834 2197
2835 fastrpc { 2198 fastrpc {
2836 compa 2199 compatible = "qcom,fastrpc";
2837 qcom, 2200 qcom,glink-channels = "fastrpcglink-apps-dsp";
2838 label 2201 label = "cdsp";
2839 qcom, <<
2840 #addr 2202 #address-cells = <1>;
2841 #size 2203 #size-cells = <0>;
2842 2204
2843 compu 2205 compute-cb@1 {
2844 2206 compatible = "qcom,fastrpc-compute-cb";
2845 2207 reg = <1>;
2846 2208 iommus = <&apps_smmu 0x2161 0x0400>,
2847 2209 <&apps_smmu 0x1021 0x1420>;
2848 }; 2210 };
2849 2211
2850 compu 2212 compute-cb@2 {
2851 2213 compatible = "qcom,fastrpc-compute-cb";
2852 2214 reg = <2>;
2853 2215 iommus = <&apps_smmu 0x2162 0x0400>,
2854 2216 <&apps_smmu 0x1022 0x1420>;
2855 }; 2217 };
2856 2218
2857 compu 2219 compute-cb@3 {
2858 2220 compatible = "qcom,fastrpc-compute-cb";
2859 2221 reg = <3>;
2860 2222 iommus = <&apps_smmu 0x2163 0x0400>,
2861 2223 <&apps_smmu 0x1023 0x1420>;
2862 }; 2224 };
2863 2225
2864 compu 2226 compute-cb@4 {
2865 2227 compatible = "qcom,fastrpc-compute-cb";
2866 2228 reg = <4>;
2867 2229 iommus = <&apps_smmu 0x2164 0x0400>,
2868 2230 <&apps_smmu 0x1024 0x1420>;
2869 }; 2231 };
2870 2232
2871 compu 2233 compute-cb@5 {
2872 2234 compatible = "qcom,fastrpc-compute-cb";
2873 2235 reg = <5>;
2874 2236 iommus = <&apps_smmu 0x2165 0x0400>,
2875 2237 <&apps_smmu 0x1025 0x1420>;
2876 }; 2238 };
2877 2239
2878 compu 2240 compute-cb@6 {
2879 2241 compatible = "qcom,fastrpc-compute-cb";
2880 2242 reg = <6>;
2881 2243 iommus = <&apps_smmu 0x2166 0x0400>,
2882 2244 <&apps_smmu 0x1026 0x1420>;
2883 }; 2245 };
2884 2246
2885 compu 2247 compute-cb@7 {
2886 2248 compatible = "qcom,fastrpc-compute-cb";
2887 2249 reg = <7>;
2888 2250 iommus = <&apps_smmu 0x2167 0x0400>,
2889 2251 <&apps_smmu 0x1027 0x1420>;
2890 }; 2252 };
2891 2253
2892 compu 2254 compute-cb@8 {
2893 2255 compatible = "qcom,fastrpc-compute-cb";
2894 2256 reg = <8>;
2895 2257 iommus = <&apps_smmu 0x2168 0x0400>,
2896 2258 <&apps_smmu 0x1028 0x1420>;
2897 }; 2259 };
2898 2260
2899 /* no 2261 /* note: secure cb9 in downstream */
2900 }; 2262 };
2901 }; 2263 };
2902 }; 2264 };
2903 2265
2904 remoteproc_mpss: remoteproc@4 2266 remoteproc_mpss: remoteproc@4080000 {
2905 compatible = "qcom,sm 2267 compatible = "qcom,sm8450-mpss-pas";
2906 reg = <0x0 0x04080000 2268 reg = <0x0 0x04080000 0x0 0x4040>;
2907 2269
2908 interrupts-extended = 2270 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
2909 2271 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
2910 2272 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
2911 2273 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
2912 2274 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>,
2913 2275 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>;
2914 interrupt-names = "wd 2276 interrupt-names = "wdog", "fatal", "ready", "handover",
2915 "st 2277 "stop-ack", "shutdown-ack";
2916 2278
2917 clocks = <&rpmhcc RPM 2279 clocks = <&rpmhcc RPMH_CXO_CLK>;
2918 clock-names = "xo"; 2280 clock-names = "xo";
2919 2281
2920 power-domains = <&rpm !! 2282 power-domains = <&rpmhpd 0>,
2921 <&rpm !! 2283 <&rpmhpd 12>;
2922 power-domain-names = 2284 power-domain-names = "cx", "mss";
2923 2285
2924 memory-region = <&mps 2286 memory-region = <&mpss_mem>;
2925 2287
2926 qcom,qmp = <&aoss_qmp 2288 qcom,qmp = <&aoss_qmp>;
2927 2289
2928 qcom,smem-states = <& 2290 qcom,smem-states = <&smp2p_modem_out 0>;
2929 qcom,smem-state-names 2291 qcom,smem-state-names = "stop";
2930 2292
2931 status = "disabled"; 2293 status = "disabled";
2932 2294
2933 glink-edge { 2295 glink-edge {
2934 interrupts-ex 2296 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
2935 2297 IPCC_MPROC_SIGNAL_GLINK_QMP
2936 2298 IRQ_TYPE_EDGE_RISING>;
2937 mboxes = <&ip 2299 mboxes = <&ipcc IPCC_CLIENT_MPSS
2938 2300 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2939 label = "mode 2301 label = "modem";
2940 qcom,remote-p 2302 qcom,remote-pid = <1>;
2941 }; 2303 };
2942 }; 2304 };
2943 2305
2944 videocc: clock-controller@aaf <<
2945 compatible = "qcom,sm <<
2946 reg = <0 0x0aaf0000 0 <<
2947 clocks = <&rpmhcc RPM <<
2948 <&gcc GCC_VI <<
2949 power-domains = <&rpm <<
2950 required-opps = <&rpm <<
2951 #clock-cells = <1>; <<
2952 #reset-cells = <1>; <<
2953 #power-domain-cells = <<
2954 }; <<
2955 <<
2956 cci0: cci@ac15000 { <<
2957 compatible = "qcom,sm <<
2958 reg = <0 0x0ac15000 0 <<
2959 interrupts = <GIC_SPI <<
2960 power-domains = <&cam <<
2961 <<
2962 clocks = <&camcc CAM_ <<
2963 <&camcc CAM_ <<
2964 <&camcc CAM_ <<
2965 <&camcc CAM_ <<
2966 <&camcc CAM_ <<
2967 clock-names = "camnoc <<
2968 "slow_a <<
2969 "cpas_a <<
2970 "cci", <<
2971 "cci_sr <<
2972 pinctrl-0 = <&cci0_de <<
2973 pinctrl-1 = <&cci0_sl <<
2974 pinctrl-names = "defa <<
2975 <<
2976 status = "disabled"; <<
2977 #address-cells = <1>; <<
2978 #size-cells = <0>; <<
2979 <<
2980 cci0_i2c0: i2c-bus@0 <<
2981 reg = <0>; <<
2982 clock-frequen <<
2983 #address-cell <<
2984 #size-cells = <<
2985 }; <<
2986 <<
2987 cci0_i2c1: i2c-bus@1 <<
2988 reg = <1>; <<
2989 clock-frequen <<
2990 #address-cell <<
2991 #size-cells = <<
2992 }; <<
2993 }; <<
2994 <<
2995 cci1: cci@ac16000 { <<
2996 compatible = "qcom,sm <<
2997 reg = <0 0x0ac16000 0 <<
2998 interrupts = <GIC_SPI <<
2999 power-domains = <&cam <<
3000 <<
3001 clocks = <&camcc CAM_ <<
3002 <&camcc CAM_ <<
3003 <&camcc CAM_ <<
3004 <&camcc CAM_ <<
3005 <&camcc CAM_ <<
3006 clock-names = "camnoc <<
3007 "slow_a <<
3008 "cpas_a <<
3009 "cci", <<
3010 "cci_sr <<
3011 pinctrl-0 = <&cci2_de <<
3012 pinctrl-1 = <&cci2_sl <<
3013 pinctrl-names = "defa <<
3014 <<
3015 status = "disabled"; <<
3016 #address-cells = <1>; <<
3017 #size-cells = <0>; <<
3018 <<
3019 cci1_i2c0: i2c-bus@0 <<
3020 reg = <0>; <<
3021 clock-frequen <<
3022 #address-cell <<
3023 #size-cells = <<
3024 }; <<
3025 <<
3026 cci1_i2c1: i2c-bus@1 <<
3027 reg = <1>; <<
3028 clock-frequen <<
3029 #address-cell <<
3030 #size-cells = <<
3031 }; <<
3032 }; <<
3033 <<
3034 camcc: clock-controller@ade00 2306 camcc: clock-controller@ade0000 {
3035 compatible = "qcom,sm 2307 compatible = "qcom,sm8450-camcc";
3036 reg = <0 0x0ade0000 0 2308 reg = <0 0x0ade0000 0 0x20000>;
3037 clocks = <&gcc GCC_CA 2309 clocks = <&gcc GCC_CAMERA_AHB_CLK>,
3038 <&rpmhcc RPM 2310 <&rpmhcc RPMH_CXO_CLK>,
3039 <&rpmhcc RPM 2311 <&rpmhcc RPMH_CXO_CLK_A>,
3040 <&sleep_clk> 2312 <&sleep_clk>;
3041 power-domains = <&rpm !! 2313 power-domains = <&rpmhpd SM8450_MMCX>;
3042 required-opps = <&rpm <<
3043 #clock-cells = <1>; <<
3044 #reset-cells = <1>; <<
3045 #power-domain-cells = <<
3046 status = "disabled"; <<
3047 }; <<
3048 <<
3049 mdss: display-subsystem@ae000 <<
3050 compatible = "qcom,sm <<
3051 reg = <0 0x0ae00000 0 <<
3052 reg-names = "mdss"; <<
3053 <<
3054 /* same path used twi <<
3055 interconnects = <&mms <<
3056 <&mms <<
3057 <&gem <<
3058 &con <<
3059 interconnect-names = <<
3060 <<
3061 <<
3062 <<
3063 resets = <&dispcc DIS <<
3064 <<
3065 power-domains = <&dis <<
3066 <<
3067 clocks = <&dispcc DIS <<
3068 <&gcc GCC_DI <<
3069 <&gcc GCC_DI <<
3070 <&dispcc DIS <<
3071 <<
3072 interrupts = <GIC_SPI <<
3073 interrupt-controller; <<
3074 #interrupt-cells = <1 <<
3075 <<
3076 iommus = <&apps_smmu <<
3077 <<
3078 #address-cells = <2>; <<
3079 #size-cells = <2>; <<
3080 ranges; <<
3081 <<
3082 status = "disabled"; <<
3083 <<
3084 mdss_mdp: display-con <<
3085 compatible = <<
3086 reg = <0 0x0a <<
3087 <0 0x0a <<
3088 reg-names = " <<
3089 <<
3090 clocks = <&gc <<
3091 <&gcc <<
3092 <&dis <<
3093 <&dis <<
3094 <&dis <<
3095 <&dis <<
3096 clock-names = <<
3097 <<
3098 <<
3099 <<
3100 <<
3101 <<
3102 <<
3103 assigned-cloc <<
3104 assigned-cloc <<
3105 <<
3106 operating-poi <<
3107 power-domains <<
3108 <<
3109 interrupt-par <<
3110 interrupts = <<
3111 <<
3112 ports { <<
3113 #addr <<
3114 #size <<
3115 <<
3116 port@ <<
3117 <<
3118 <<
3119 <<
3120 <<
3121 }; <<
3122 <<
3123 port@ <<
3124 <<
3125 <<
3126 <<
3127 <<
3128 }; <<
3129 <<
3130 port@ <<
3131 <<
3132 <<
3133 <<
3134 <<
3135 }; <<
3136 }; <<
3137 <<
3138 mdp_opp_table <<
3139 compa <<
3140 <<
3141 opp-1 <<
3142 <<
3143 <<
3144 }; <<
3145 <<
3146 opp-2 <<
3147 <<
3148 <<
3149 }; <<
3150 <<
3151 opp-3 <<
3152 <<
3153 <<
3154 }; <<
3155 <<
3156 opp-3 <<
3157 <<
3158 <<
3159 }; <<
3160 <<
3161 opp-5 <<
3162 <<
3163 <<
3164 }; <<
3165 }; <<
3166 }; <<
3167 <<
3168 mdss_dp0: displayport <<
3169 compatible = <<
3170 reg = <0 0xae <<
3171 <0 0xae <<
3172 <0 0xae <<
3173 <0 0xae <<
3174 <0 0xae <<
3175 interrupt-par <<
3176 interrupts = <<
3177 clocks = <&di <<
3178 <&di <<
3179 <&di <<
3180 <&di <<
3181 <&di <<
3182 clock-names = <<
3183 <<
3184 <<
3185 <<
3186 <<
3187 <<
3188 assigned-cloc <<
3189 <<
3190 assigned-cloc <<
3191 <<
3192 <<
3193 phys = <&usb_ <<
3194 phy-names = " <<
3195 <<
3196 #sound-dai-ce <<
3197 <<
3198 operating-poi <<
3199 power-domains <<
3200 <<
3201 status = "dis <<
3202 <<
3203 ports { <<
3204 #addr <<
3205 #size <<
3206 <<
3207 port@ <<
3208 <<
3209 <<
3210 <<
3211 <<
3212 }; <<
3213 <<
3214 port@ <<
3215 <<
3216 <<
3217 <<
3218 <<
3219 <<
3220 }; <<
3221 }; <<
3222 <<
3223 dp_opp_table: <<
3224 compa <<
3225 <<
3226 opp-1 <<
3227 <<
3228 <<
3229 }; <<
3230 <<
3231 opp-2 <<
3232 <<
3233 <<
3234 }; <<
3235 <<
3236 opp-5 <<
3237 <<
3238 <<
3239 }; <<
3240 <<
3241 opp-8 <<
3242 <<
3243 <<
3244 }; <<
3245 }; <<
3246 }; <<
3247 <<
3248 mdss_dsi0: dsi@ae9400 <<
3249 compatible = <<
3250 reg = <0 0x0a <<
3251 reg-names = " <<
3252 <<
3253 interrupt-par <<
3254 interrupts = <<
3255 <<
3256 clocks = <&di <<
3257 <&di <<
3258 <&di <<
3259 <&di <<
3260 <&di <<
3261 <&gcc <<
3262 clock-names = <<
3263 <<
3264 <<
3265 <<
3266 <<
3267 <<
3268 <<
3269 assigned-cloc <<
3270 assigned-cloc <<
3271 <<
3272 operating-poi <<
3273 power-domains <<
3274 <<
3275 phys = <&mdss <<
3276 phy-names = " <<
3277 <<
3278 #address-cell <<
3279 #size-cells = <<
3280 <<
3281 status = "dis <<
3282 <<
3283 ports { <<
3284 #addr <<
3285 #size <<
3286 <<
3287 port@ <<
3288 <<
3289 <<
3290 <<
3291 <<
3292 }; <<
3293 <<
3294 port@ <<
3295 <<
3296 <<
3297 <<
3298 }; <<
3299 }; <<
3300 <<
3301 mdss_dsi_opp_ <<
3302 compa <<
3303 <<
3304 opp-1 <<
3305 <<
3306 <<
3307 }; <<
3308 <<
3309 opp-3 <<
3310 <<
3311 <<
3312 }; <<
3313 <<
3314 opp-3 <<
3315 <<
3316 <<
3317 }; <<
3318 }; <<
3319 }; <<
3320 <<
3321 mdss_dsi0_phy: phy@ae <<
3322 compatible = <<
3323 reg = <0 0x0a <<
3324 <0 0x0a <<
3325 <0 0x0a <<
3326 reg-names = " <<
3327 " <<
3328 " <<
3329 <<
3330 #clock-cells <<
3331 #phy-cells = <<
3332 <<
3333 clocks = <&di <<
3334 <&rp <<
3335 clock-names = <<
3336 <<
3337 status = "dis <<
3338 }; <<
3339 <<
3340 mdss_dsi1: dsi@ae9600 <<
3341 compatible = <<
3342 reg = <0 0x0a <<
3343 reg-names = " <<
3344 <<
3345 interrupt-par <<
3346 interrupts = <<
3347 <<
3348 clocks = <&di <<
3349 <&di <<
3350 <&di <<
3351 <&di <<
3352 <&di <<
3353 <&gc <<
3354 clock-names = <<
3355 <<
3356 <<
3357 <<
3358 <<
3359 <<
3360 <<
3361 assigned-cloc <<
3362 assigned-cloc <<
3363 <<
3364 operating-poi <<
3365 power-domains <<
3366 <<
3367 phys = <&mdss <<
3368 phy-names = " <<
3369 <<
3370 #address-cell <<
3371 #size-cells = <<
3372 <<
3373 status = "dis <<
3374 <<
3375 ports { <<
3376 #addr <<
3377 #size <<
3378 <<
3379 port@ <<
3380 <<
3381 <<
3382 <<
3383 <<
3384 }; <<
3385 <<
3386 port@ <<
3387 <<
3388 <<
3389 <<
3390 }; <<
3391 }; <<
3392 }; <<
3393 <<
3394 mdss_dsi1_phy: phy@ae <<
3395 compatible = <<
3396 reg = <0 0x0a <<
3397 <0 0x0a <<
3398 <0 0x0a <<
3399 reg-names = " <<
3400 " <<
3401 " <<
3402 <<
3403 #clock-cells <<
3404 #phy-cells = <<
3405 <<
3406 clocks = <&di <<
3407 <&rp <<
3408 clock-names = <<
3409 <<
3410 status = "dis <<
3411 }; <<
3412 }; <<
3413 <<
3414 dispcc: clock-controller@af00 <<
3415 compatible = "qcom,sm <<
3416 reg = <0 0x0af00000 0 <<
3417 clocks = <&rpmhcc RPM <<
3418 <&rpmhcc RPM <<
3419 <&gcc GCC_DI <<
3420 <&sleep_clk> <<
3421 <&mdss_dsi0_ <<
3422 <&mdss_dsi0_ <<
3423 <&mdss_dsi1_ <<
3424 <&mdss_dsi1_ <<
3425 <&usb_1_qmpp <<
3426 <&usb_1_qmpp <<
3427 <0>, /* dp1 <<
3428 <0>, <<
3429 <0>, /* dp2 <<
3430 <0>, <<
3431 <0>, /* dp3 <<
3432 <0>; <<
3433 power-domains = <&rpm <<
3434 required-opps = <&rpm 2314 required-opps = <&rpmhpd_opp_low_svs>;
3435 #clock-cells = <1>; 2315 #clock-cells = <1>;
3436 #reset-cells = <1>; 2316 #reset-cells = <1>;
3437 #power-domain-cells = 2317 #power-domain-cells = <1>;
3438 status = "disabled"; 2318 status = "disabled";
3439 }; 2319 };
3440 2320
3441 pdc: interrupt-controller@b22 2321 pdc: interrupt-controller@b220000 {
3442 compatible = "qcom,sm 2322 compatible = "qcom,sm8450-pdc", "qcom,pdc";
3443 reg = <0 0x0b220000 0 2323 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
3444 qcom,pdc-ranges = <0 2324 qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>,
3445 <94 2325 <94 609 31>, <125 63 1>, <126 716 12>;
3446 #interrupt-cells = <2 2326 #interrupt-cells = <2>;
3447 interrupt-parent = <& 2327 interrupt-parent = <&intc>;
3448 interrupt-controller; 2328 interrupt-controller;
3449 }; 2329 };
3450 2330
3451 tsens0: thermal-sensor@c26300 2331 tsens0: thermal-sensor@c263000 {
3452 compatible = "qcom,sm 2332 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2";
3453 reg = <0 0x0c263000 0 2333 reg = <0 0x0c263000 0 0x1000>, /* TM */
3454 <0 0x0c222000 0 2334 <0 0x0c222000 0 0x1000>; /* SROT */
3455 #qcom,sensors = <16>; 2335 #qcom,sensors = <16>;
3456 interrupts = <GIC_SPI 2336 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
3457 <GIC_SPI 2337 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
3458 interrupt-names = "up 2338 interrupt-names = "uplow", "critical";
3459 #thermal-sensor-cells 2339 #thermal-sensor-cells = <1>;
3460 }; 2340 };
3461 2341
3462 tsens1: thermal-sensor@c26500 2342 tsens1: thermal-sensor@c265000 {
3463 compatible = "qcom,sm 2343 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2";
3464 reg = <0 0x0c265000 0 2344 reg = <0 0x0c265000 0 0x1000>, /* TM */
3465 <0 0x0c223000 0 2345 <0 0x0c223000 0 0x1000>; /* SROT */
3466 #qcom,sensors = <16>; 2346 #qcom,sensors = <16>;
3467 interrupts = <GIC_SPI 2347 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
3468 <GIC_SPI 2348 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
3469 interrupt-names = "up 2349 interrupt-names = "uplow", "critical";
3470 #thermal-sensor-cells 2350 #thermal-sensor-cells = <1>;
3471 }; 2351 };
3472 2352
3473 aoss_qmp: power-management@c3 !! 2353 aoss_qmp: power-controller@c300000 {
3474 compatible = "qcom,sm 2354 compatible = "qcom,sm8450-aoss-qmp", "qcom,aoss-qmp";
3475 reg = <0 0x0c300000 0 2355 reg = <0 0x0c300000 0 0x400>;
3476 interrupts-extended = 2356 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
3477 2357 IRQ_TYPE_EDGE_RISING>;
3478 mboxes = <&ipcc IPCC_ 2358 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
3479 2359
3480 #clock-cells = <0>; 2360 #clock-cells = <0>;
3481 }; 2361 };
3482 2362
3483 sram@c3f0000 { <<
3484 compatible = "qcom,rp <<
3485 reg = <0 0x0c3f0000 0 <<
3486 }; <<
3487 <<
3488 spmi_bus: spmi@c400000 { <<
3489 compatible = "qcom,sp <<
3490 reg = <0 0x0c400000 0 <<
3491 <0 0x0c500000 0 <<
3492 <0 0x0c440000 0 <<
3493 <0 0x0c4c0000 0 <<
3494 <0 0x0c42d000 0 <<
3495 reg-names = "core", <<
3496 "chnls", <<
3497 "obsrvr", <<
3498 "intr", <<
3499 "cnfg"; <<
3500 interrupt-names = "pe <<
3501 interrupts-extended = <<
3502 qcom,ee = <0>; <<
3503 qcom,channel = <0>; <<
3504 interrupt-controller; <<
3505 #interrupt-cells = <4 <<
3506 #address-cells = <2>; <<
3507 #size-cells = <0>; <<
3508 }; <<
3509 <<
3510 ipcc: mailbox@ed18000 { 2363 ipcc: mailbox@ed18000 {
3511 compatible = "qcom,sm 2364 compatible = "qcom,sm8450-ipcc", "qcom,ipcc";
3512 reg = <0 0x0ed18000 0 2365 reg = <0 0x0ed18000 0 0x1000>;
3513 interrupts = <GIC_SPI 2366 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
3514 interrupt-controller; 2367 interrupt-controller;
3515 #interrupt-cells = <3 2368 #interrupt-cells = <3>;
3516 #mbox-cells = <2>; 2369 #mbox-cells = <2>;
3517 }; 2370 };
3518 2371
3519 tlmm: pinctrl@f100000 { 2372 tlmm: pinctrl@f100000 {
3520 compatible = "qcom,sm 2373 compatible = "qcom,sm8450-tlmm";
3521 reg = <0 0x0f100000 0 2374 reg = <0 0x0f100000 0 0x300000>;
3522 interrupts = <GIC_SPI 2375 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
3523 gpio-controller; 2376 gpio-controller;
3524 #gpio-cells = <2>; 2377 #gpio-cells = <2>;
3525 interrupt-controller; 2378 interrupt-controller;
3526 #interrupt-cells = <2 2379 #interrupt-cells = <2>;
3527 gpio-ranges = <&tlmm 2380 gpio-ranges = <&tlmm 0 0 211>;
3528 wakeup-parent = <&pdc 2381 wakeup-parent = <&pdc>;
3529 2382
3530 sdc2_default_state: s <<
3531 clk-pins { <<
3532 pins <<
3533 drive <<
3534 bias- <<
3535 }; <<
3536 <<
3537 cmd-pins { <<
3538 pins <<
3539 drive <<
3540 bias- <<
3541 }; <<
3542 <<
3543 data-pins { <<
3544 pins <<
3545 drive <<
3546 bias- <<
3547 }; <<
3548 }; <<
3549 <<
3550 sdc2_sleep_state: sdc 2383 sdc2_sleep_state: sdc2-sleep-state {
3551 clk-pins { 2384 clk-pins {
3552 pins 2385 pins = "sdc2_clk";
3553 drive 2386 drive-strength = <2>;
3554 bias- 2387 bias-disable;
3555 }; 2388 };
3556 2389
3557 cmd-pins { 2390 cmd-pins {
3558 pins 2391 pins = "sdc2_cmd";
3559 drive 2392 drive-strength = <2>;
3560 bias- 2393 bias-pull-up;
3561 }; 2394 };
3562 2395
3563 data-pins { 2396 data-pins {
3564 pins 2397 pins = "sdc2_data";
3565 drive 2398 drive-strength = <2>;
3566 bias- 2399 bias-pull-up;
3567 }; 2400 };
3568 }; 2401 };
3569 2402
3570 cci0_default: cci0-de <<
3571 /* SDA, SCL * <<
3572 pins = "gpio1 <<
3573 function = "c <<
3574 drive-strengt <<
3575 bias-pull-up; <<
3576 }; <<
3577 <<
3578 cci0_sleep: cci0-slee <<
3579 /* SDA, SCL * <<
3580 pins = "gpio1 <<
3581 function = "c <<
3582 drive-strengt <<
3583 bias-pull-dow <<
3584 }; <<
3585 <<
3586 cci1_default: cci1-de <<
3587 /* SDA, SCL * <<
3588 pins = "gpio1 <<
3589 function = "c <<
3590 drive-strengt <<
3591 bias-pull-up; <<
3592 }; <<
3593 <<
3594 cci1_sleep: cci1-slee <<
3595 /* SDA, SCL * <<
3596 pins = "gpio1 <<
3597 function = "c <<
3598 drive-strengt <<
3599 bias-pull-dow <<
3600 }; <<
3601 <<
3602 cci2_default: cci2-de <<
3603 /* SDA, SCL * <<
3604 pins = "gpio1 <<
3605 function = "c <<
3606 drive-strengt <<
3607 bias-pull-up; <<
3608 }; <<
3609 <<
3610 cci2_sleep: cci2-slee <<
3611 /* SDA, SCL * <<
3612 pins = "gpio1 <<
3613 function = "c <<
3614 drive-strengt <<
3615 bias-pull-dow <<
3616 }; <<
3617 <<
3618 cci3_default: cci3-de <<
3619 /* SDA, SCL * <<
3620 pins = "gpio2 <<
3621 function = "c <<
3622 drive-strengt <<
3623 bias-pull-up; <<
3624 }; <<
3625 <<
3626 cci3_sleep: cci3-slee <<
3627 /* SDA, SCL * <<
3628 pins = "gpio2 <<
3629 function = "c <<
3630 drive-strengt <<
3631 bias-pull-dow <<
3632 }; <<
3633 <<
3634 pcie0_default_state: 2403 pcie0_default_state: pcie0-default-state {
3635 perst-pins { 2404 perst-pins {
3636 pins 2405 pins = "gpio94";
3637 funct 2406 function = "gpio";
3638 drive 2407 drive-strength = <2>;
3639 bias- 2408 bias-pull-down;
3640 }; 2409 };
3641 2410
3642 clkreq-pins { 2411 clkreq-pins {
3643 pins 2412 pins = "gpio95";
3644 funct 2413 function = "pcie0_clkreqn";
3645 drive 2414 drive-strength = <2>;
3646 bias- 2415 bias-pull-up;
3647 }; 2416 };
3648 2417
3649 wake-pins { 2418 wake-pins {
3650 pins 2419 pins = "gpio96";
3651 funct 2420 function = "gpio";
3652 drive 2421 drive-strength = <2>;
3653 bias- 2422 bias-pull-up;
3654 }; 2423 };
3655 }; 2424 };
3656 2425
3657 pcie1_default_state: 2426 pcie1_default_state: pcie1-default-state {
3658 perst-pins { 2427 perst-pins {
3659 pins 2428 pins = "gpio97";
3660 funct 2429 function = "gpio";
3661 drive 2430 drive-strength = <2>;
3662 bias- 2431 bias-pull-down;
3663 }; 2432 };
3664 2433
3665 clkreq-pins { 2434 clkreq-pins {
3666 pins 2435 pins = "gpio98";
3667 funct 2436 function = "pcie1_clkreqn";
3668 drive 2437 drive-strength = <2>;
3669 bias- 2438 bias-pull-up;
3670 }; 2439 };
3671 2440
3672 wake-pins { 2441 wake-pins {
3673 pins 2442 pins = "gpio99";
3674 funct 2443 function = "gpio";
3675 drive 2444 drive-strength = <2>;
3676 bias- 2445 bias-pull-up;
3677 }; 2446 };
3678 }; 2447 };
3679 2448
3680 qup_i2c0_data_clk: qu 2449 qup_i2c0_data_clk: qup-i2c0-data-clk-state {
3681 pins = "gpio0 2450 pins = "gpio0", "gpio1";
3682 function = "q 2451 function = "qup0";
3683 }; 2452 };
3684 2453
3685 qup_i2c1_data_clk: qu 2454 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
3686 pins = "gpio4 2455 pins = "gpio4", "gpio5";
3687 function = "q 2456 function = "qup1";
3688 }; 2457 };
3689 2458
3690 qup_i2c2_data_clk: qu 2459 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
3691 pins = "gpio8 2460 pins = "gpio8", "gpio9";
3692 function = "q 2461 function = "qup2";
3693 }; 2462 };
3694 2463
3695 qup_i2c3_data_clk: qu 2464 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
3696 pins = "gpio1 2465 pins = "gpio12", "gpio13";
3697 function = "q 2466 function = "qup3";
3698 }; 2467 };
3699 2468
3700 qup_i2c4_data_clk: qu 2469 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
3701 pins = "gpio1 2470 pins = "gpio16", "gpio17";
3702 function = "q 2471 function = "qup4";
3703 }; 2472 };
3704 2473
3705 qup_i2c5_data_clk: qu 2474 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
3706 pins = "gpio2 2475 pins = "gpio206", "gpio207";
3707 function = "q 2476 function = "qup5";
3708 }; 2477 };
3709 2478
3710 qup_i2c6_data_clk: qu 2479 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
3711 pins = "gpio2 2480 pins = "gpio20", "gpio21";
3712 function = "q 2481 function = "qup6";
3713 }; 2482 };
3714 2483
3715 qup_i2c8_data_clk: qu 2484 qup_i2c8_data_clk: qup-i2c8-data-clk-state {
3716 pins = "gpio2 2485 pins = "gpio28", "gpio29";
3717 function = "q 2486 function = "qup8";
3718 }; 2487 };
3719 2488
3720 qup_i2c9_data_clk: qu 2489 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
3721 pins = "gpio3 2490 pins = "gpio32", "gpio33";
3722 function = "q 2491 function = "qup9";
3723 }; 2492 };
3724 2493
3725 qup_i2c10_data_clk: q 2494 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
3726 pins = "gpio3 2495 pins = "gpio36", "gpio37";
3727 function = "q 2496 function = "qup10";
3728 }; 2497 };
3729 2498
3730 qup_i2c11_data_clk: q 2499 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
3731 pins = "gpio4 2500 pins = "gpio40", "gpio41";
3732 function = "q 2501 function = "qup11";
3733 }; 2502 };
3734 2503
3735 qup_i2c12_data_clk: q 2504 qup_i2c12_data_clk: qup-i2c12-data-clk-state {
3736 pins = "gpio4 2505 pins = "gpio44", "gpio45";
3737 function = "q 2506 function = "qup12";
3738 }; 2507 };
3739 2508
3740 qup_i2c13_data_clk: q 2509 qup_i2c13_data_clk: qup-i2c13-data-clk-state {
3741 pins = "gpio4 2510 pins = "gpio48", "gpio49";
3742 function = "q 2511 function = "qup13";
3743 drive-strengt 2512 drive-strength = <2>;
3744 bias-pull-up; 2513 bias-pull-up;
3745 }; 2514 };
3746 2515
3747 qup_i2c14_data_clk: q 2516 qup_i2c14_data_clk: qup-i2c14-data-clk-state {
3748 pins = "gpio5 2517 pins = "gpio52", "gpio53";
3749 function = "q 2518 function = "qup14";
3750 drive-strengt 2519 drive-strength = <2>;
3751 bias-pull-up; 2520 bias-pull-up;
3752 }; 2521 };
3753 2522
3754 qup_i2c15_data_clk: q 2523 qup_i2c15_data_clk: qup-i2c15-data-clk-state {
3755 pins = "gpio5 2524 pins = "gpio56", "gpio57";
3756 function = "q 2525 function = "qup15";
3757 }; 2526 };
3758 2527
3759 qup_i2c16_data_clk: q 2528 qup_i2c16_data_clk: qup-i2c16-data-clk-state {
3760 pins = "gpio6 2529 pins = "gpio60", "gpio61";
3761 function = "q 2530 function = "qup16";
3762 }; 2531 };
3763 2532
3764 qup_i2c17_data_clk: q 2533 qup_i2c17_data_clk: qup-i2c17-data-clk-state {
3765 pins = "gpio6 2534 pins = "gpio64", "gpio65";
3766 function = "q 2535 function = "qup17";
3767 }; 2536 };
3768 2537
3769 qup_i2c18_data_clk: q 2538 qup_i2c18_data_clk: qup-i2c18-data-clk-state {
3770 pins = "gpio6 2539 pins = "gpio68", "gpio69";
3771 function = "q 2540 function = "qup18";
3772 }; 2541 };
3773 2542
3774 qup_i2c19_data_clk: q 2543 qup_i2c19_data_clk: qup-i2c19-data-clk-state {
3775 pins = "gpio7 2544 pins = "gpio72", "gpio73";
3776 function = "q 2545 function = "qup19";
3777 }; 2546 };
3778 2547
3779 qup_i2c20_data_clk: q 2548 qup_i2c20_data_clk: qup-i2c20-data-clk-state {
3780 pins = "gpio7 2549 pins = "gpio76", "gpio77";
3781 function = "q 2550 function = "qup20";
3782 }; 2551 };
3783 2552
3784 qup_i2c21_data_clk: q 2553 qup_i2c21_data_clk: qup-i2c21-data-clk-state {
3785 pins = "gpio8 2554 pins = "gpio80", "gpio81";
3786 function = "q 2555 function = "qup21";
3787 }; 2556 };
3788 2557
3789 qup_spi0_cs: qup-spi0 2558 qup_spi0_cs: qup-spi0-cs-state {
3790 pins = "gpio3 2559 pins = "gpio3";
3791 function = "q 2560 function = "qup0";
3792 }; 2561 };
3793 2562
3794 qup_spi0_data_clk: qu 2563 qup_spi0_data_clk: qup-spi0-data-clk-state {
3795 pins = "gpio0 2564 pins = "gpio0", "gpio1", "gpio2";
3796 function = "q 2565 function = "qup0";
3797 }; 2566 };
3798 2567
3799 qup_spi1_cs: qup-spi1 2568 qup_spi1_cs: qup-spi1-cs-state {
3800 pins = "gpio7 2569 pins = "gpio7";
3801 function = "q 2570 function = "qup1";
3802 }; 2571 };
3803 2572
3804 qup_spi1_data_clk: qu 2573 qup_spi1_data_clk: qup-spi1-data-clk-state {
3805 pins = "gpio4 2574 pins = "gpio4", "gpio5", "gpio6";
3806 function = "q 2575 function = "qup1";
3807 }; 2576 };
3808 2577
3809 qup_spi2_cs: qup-spi2 2578 qup_spi2_cs: qup-spi2-cs-state {
3810 pins = "gpio1 2579 pins = "gpio11";
3811 function = "q 2580 function = "qup2";
3812 }; 2581 };
3813 2582
3814 qup_spi2_data_clk: qu 2583 qup_spi2_data_clk: qup-spi2-data-clk-state {
3815 pins = "gpio8 2584 pins = "gpio8", "gpio9", "gpio10";
3816 function = "q 2585 function = "qup2";
3817 }; 2586 };
3818 2587
3819 qup_spi3_cs: qup-spi3 2588 qup_spi3_cs: qup-spi3-cs-state {
3820 pins = "gpio1 2589 pins = "gpio15";
3821 function = "q 2590 function = "qup3";
3822 }; 2591 };
3823 2592
3824 qup_spi3_data_clk: qu 2593 qup_spi3_data_clk: qup-spi3-data-clk-state {
3825 pins = "gpio1 2594 pins = "gpio12", "gpio13", "gpio14";
3826 function = "q 2595 function = "qup3";
3827 }; 2596 };
3828 2597
3829 qup_spi4_cs: qup-spi4 2598 qup_spi4_cs: qup-spi4-cs-state {
3830 pins = "gpio1 2599 pins = "gpio19";
3831 function = "q 2600 function = "qup4";
3832 drive-strengt 2601 drive-strength = <6>;
3833 bias-disable; 2602 bias-disable;
3834 }; 2603 };
3835 2604
3836 qup_spi4_data_clk: qu 2605 qup_spi4_data_clk: qup-spi4-data-clk-state {
3837 pins = "gpio1 2606 pins = "gpio16", "gpio17", "gpio18";
3838 function = "q 2607 function = "qup4";
3839 }; 2608 };
3840 2609
3841 qup_spi5_cs: qup-spi5 2610 qup_spi5_cs: qup-spi5-cs-state {
3842 pins = "gpio8 2611 pins = "gpio85";
3843 function = "q 2612 function = "qup5";
3844 }; 2613 };
3845 2614
3846 qup_spi5_data_clk: qu 2615 qup_spi5_data_clk: qup-spi5-data-clk-state {
3847 pins = "gpio2 2616 pins = "gpio206", "gpio207", "gpio84";
3848 function = "q 2617 function = "qup5";
3849 }; 2618 };
3850 2619
3851 qup_spi6_cs: qup-spi6 2620 qup_spi6_cs: qup-spi6-cs-state {
3852 pins = "gpio2 2621 pins = "gpio23";
3853 function = "q 2622 function = "qup6";
3854 }; 2623 };
3855 2624
3856 qup_spi6_data_clk: qu 2625 qup_spi6_data_clk: qup-spi6-data-clk-state {
3857 pins = "gpio2 2626 pins = "gpio20", "gpio21", "gpio22";
3858 function = "q 2627 function = "qup6";
3859 }; 2628 };
3860 2629
3861 qup_spi8_cs: qup-spi8 2630 qup_spi8_cs: qup-spi8-cs-state {
3862 pins = "gpio3 2631 pins = "gpio31";
3863 function = "q 2632 function = "qup8";
3864 }; 2633 };
3865 2634
3866 qup_spi8_data_clk: qu 2635 qup_spi8_data_clk: qup-spi8-data-clk-state {
3867 pins = "gpio2 2636 pins = "gpio28", "gpio29", "gpio30";
3868 function = "q 2637 function = "qup8";
3869 }; 2638 };
3870 2639
3871 qup_spi9_cs: qup-spi9 2640 qup_spi9_cs: qup-spi9-cs-state {
3872 pins = "gpio3 2641 pins = "gpio35";
3873 function = "q 2642 function = "qup9";
3874 }; 2643 };
3875 2644
3876 qup_spi9_data_clk: qu 2645 qup_spi9_data_clk: qup-spi9-data-clk-state {
3877 pins = "gpio3 2646 pins = "gpio32", "gpio33", "gpio34";
3878 function = "q 2647 function = "qup9";
3879 }; 2648 };
3880 2649
3881 qup_spi10_cs: qup-spi 2650 qup_spi10_cs: qup-spi10-cs-state {
3882 pins = "gpio3 2651 pins = "gpio39";
3883 function = "q 2652 function = "qup10";
3884 }; 2653 };
3885 2654
3886 qup_spi10_data_clk: q 2655 qup_spi10_data_clk: qup-spi10-data-clk-state {
3887 pins = "gpio3 2656 pins = "gpio36", "gpio37", "gpio38";
3888 function = "q 2657 function = "qup10";
3889 }; 2658 };
3890 2659
3891 qup_spi11_cs: qup-spi 2660 qup_spi11_cs: qup-spi11-cs-state {
3892 pins = "gpio4 2661 pins = "gpio43";
3893 function = "q 2662 function = "qup11";
3894 }; 2663 };
3895 2664
3896 qup_spi11_data_clk: q 2665 qup_spi11_data_clk: qup-spi11-data-clk-state {
3897 pins = "gpio4 2666 pins = "gpio40", "gpio41", "gpio42";
3898 function = "q 2667 function = "qup11";
3899 }; 2668 };
3900 2669
3901 qup_spi12_cs: qup-spi 2670 qup_spi12_cs: qup-spi12-cs-state {
3902 pins = "gpio4 2671 pins = "gpio47";
3903 function = "q 2672 function = "qup12";
3904 }; 2673 };
3905 2674
3906 qup_spi12_data_clk: q 2675 qup_spi12_data_clk: qup-spi12-data-clk-state {
3907 pins = "gpio4 2676 pins = "gpio44", "gpio45", "gpio46";
3908 function = "q 2677 function = "qup12";
3909 }; 2678 };
3910 2679
3911 qup_spi13_cs: qup-spi 2680 qup_spi13_cs: qup-spi13-cs-state {
3912 pins = "gpio5 2681 pins = "gpio51";
3913 function = "q 2682 function = "qup13";
3914 }; 2683 };
3915 2684
3916 qup_spi13_data_clk: q 2685 qup_spi13_data_clk: qup-spi13-data-clk-state {
3917 pins = "gpio4 2686 pins = "gpio48", "gpio49", "gpio50";
3918 function = "q 2687 function = "qup13";
3919 }; 2688 };
3920 2689
3921 qup_spi14_cs: qup-spi 2690 qup_spi14_cs: qup-spi14-cs-state {
3922 pins = "gpio5 2691 pins = "gpio55";
3923 function = "q 2692 function = "qup14";
3924 }; 2693 };
3925 2694
3926 qup_spi14_data_clk: q 2695 qup_spi14_data_clk: qup-spi14-data-clk-state {
3927 pins = "gpio5 2696 pins = "gpio52", "gpio53", "gpio54";
3928 function = "q 2697 function = "qup14";
3929 }; 2698 };
3930 2699
3931 qup_spi15_cs: qup-spi 2700 qup_spi15_cs: qup-spi15-cs-state {
3932 pins = "gpio5 2701 pins = "gpio59";
3933 function = "q 2702 function = "qup15";
3934 }; 2703 };
3935 2704
3936 qup_spi15_data_clk: q 2705 qup_spi15_data_clk: qup-spi15-data-clk-state {
3937 pins = "gpio5 2706 pins = "gpio56", "gpio57", "gpio58";
3938 function = "q 2707 function = "qup15";
3939 }; 2708 };
3940 2709
3941 qup_spi16_cs: qup-spi 2710 qup_spi16_cs: qup-spi16-cs-state {
3942 pins = "gpio6 2711 pins = "gpio63";
3943 function = "q 2712 function = "qup16";
3944 }; 2713 };
3945 2714
3946 qup_spi16_data_clk: q 2715 qup_spi16_data_clk: qup-spi16-data-clk-state {
3947 pins = "gpio6 2716 pins = "gpio60", "gpio61", "gpio62";
3948 function = "q 2717 function = "qup16";
3949 }; 2718 };
3950 2719
3951 qup_spi17_cs: qup-spi 2720 qup_spi17_cs: qup-spi17-cs-state {
3952 pins = "gpio6 2721 pins = "gpio67";
3953 function = "q 2722 function = "qup17";
3954 }; 2723 };
3955 2724
3956 qup_spi17_data_clk: q 2725 qup_spi17_data_clk: qup-spi17-data-clk-state {
3957 pins = "gpio6 2726 pins = "gpio64", "gpio65", "gpio66";
3958 function = "q 2727 function = "qup17";
3959 }; 2728 };
3960 2729
3961 qup_spi18_cs: qup-spi 2730 qup_spi18_cs: qup-spi18-cs-state {
3962 pins = "gpio7 2731 pins = "gpio71";
3963 function = "q 2732 function = "qup18";
3964 drive-strengt 2733 drive-strength = <6>;
3965 bias-disable; 2734 bias-disable;
3966 }; 2735 };
3967 2736
3968 qup_spi18_data_clk: q 2737 qup_spi18_data_clk: qup-spi18-data-clk-state {
3969 pins = "gpio6 2738 pins = "gpio68", "gpio69", "gpio70";
3970 function = "q 2739 function = "qup18";
3971 drive-strengt 2740 drive-strength = <6>;
3972 bias-disable; 2741 bias-disable;
3973 }; 2742 };
3974 2743
3975 qup_spi19_cs: qup-spi 2744 qup_spi19_cs: qup-spi19-cs-state {
3976 pins = "gpio7 2745 pins = "gpio75";
3977 function = "q 2746 function = "qup19";
3978 drive-strengt 2747 drive-strength = <6>;
3979 bias-disable; 2748 bias-disable;
3980 }; 2749 };
3981 2750
3982 qup_spi19_data_clk: q 2751 qup_spi19_data_clk: qup-spi19-data-clk-state {
3983 pins = "gpio7 2752 pins = "gpio72", "gpio73", "gpio74";
3984 function = "q 2753 function = "qup19";
3985 drive-strengt 2754 drive-strength = <6>;
3986 bias-disable; 2755 bias-disable;
3987 }; 2756 };
3988 2757
3989 qup_spi20_cs: qup-spi 2758 qup_spi20_cs: qup-spi20-cs-state {
3990 pins = "gpio7 2759 pins = "gpio79";
3991 function = "q 2760 function = "qup20";
3992 }; 2761 };
3993 2762
3994 qup_spi20_data_clk: q 2763 qup_spi20_data_clk: qup-spi20-data-clk-state {
3995 pins = "gpio7 2764 pins = "gpio76", "gpio77", "gpio78";
3996 function = "q 2765 function = "qup20";
3997 }; 2766 };
3998 2767
3999 qup_spi21_cs: qup-spi 2768 qup_spi21_cs: qup-spi21-cs-state {
4000 pins = "gpio8 2769 pins = "gpio83";
4001 function = "q 2770 function = "qup21";
4002 }; 2771 };
4003 2772
4004 qup_spi21_data_clk: q 2773 qup_spi21_data_clk: qup-spi21-data-clk-state {
4005 pins = "gpio8 2774 pins = "gpio80", "gpio81", "gpio82";
4006 function = "q 2775 function = "qup21";
4007 }; 2776 };
4008 2777
4009 qup_uart7_rx: qup-uar 2778 qup_uart7_rx: qup-uart7-rx-state {
4010 pins = "gpio2 2779 pins = "gpio26";
4011 function = "q 2780 function = "qup7";
4012 drive-strengt 2781 drive-strength = <2>;
4013 bias-disable; 2782 bias-disable;
4014 }; 2783 };
4015 2784
4016 qup_uart7_tx: qup-uar 2785 qup_uart7_tx: qup-uart7-tx-state {
4017 pins = "gpio2 2786 pins = "gpio27";
4018 function = "q 2787 function = "qup7";
4019 drive-strengt 2788 drive-strength = <2>;
4020 bias-disable; 2789 bias-disable;
4021 }; 2790 };
4022 2791
4023 qup_uart20_default: q 2792 qup_uart20_default: qup-uart20-default-state {
4024 pins = "gpio7 2793 pins = "gpio76", "gpio77", "gpio78", "gpio79";
4025 function = "q 2794 function = "qup20";
4026 }; 2795 };
4027 }; <<
4028 2796
4029 lpass_tlmm: pinctrl@3440000 { <<
4030 compatible = "qcom,sm <<
4031 reg = <0 0x03440000 0 <<
4032 <0 0x034d0000 0 <<
4033 gpio-controller; <<
4034 #gpio-cells = <2>; <<
4035 gpio-ranges = <&lpass <<
4036 <<
4037 clocks = <&q6prmcc LP <<
4038 <&q6prmcc LP <<
4039 clock-names = "core", <<
4040 <<
4041 tx_swr_active: tx-swr <<
4042 clk-pins { <<
4043 pins <<
4044 funct <<
4045 drive <<
4046 slew- <<
4047 bias- <<
4048 }; <<
4049 <<
4050 data-pins { <<
4051 pins <<
4052 funct <<
4053 drive <<
4054 slew- <<
4055 bias- <<
4056 }; <<
4057 }; <<
4058 <<
4059 rx_swr_active: rx-swr <<
4060 clk-pins { <<
4061 pins <<
4062 funct <<
4063 drive <<
4064 slew- <<
4065 bias- <<
4066 }; <<
4067 <<
4068 data-pins { <<
4069 pins <<
4070 funct <<
4071 drive <<
4072 slew- <<
4073 bias- <<
4074 }; <<
4075 }; <<
4076 <<
4077 dmic01_default: dmic0 <<
4078 clk-pins { <<
4079 pins <<
4080 funct <<
4081 drive <<
4082 outpu <<
4083 }; <<
4084 <<
4085 data-pins { <<
4086 pins <<
4087 funct <<
4088 drive <<
4089 }; <<
4090 }; <<
4091 <<
4092 dmic23_default: dmic2 <<
4093 clk-pins { <<
4094 pins <<
4095 funct <<
4096 drive <<
4097 outpu <<
4098 }; <<
4099 <<
4100 data-pins { <<
4101 pins <<
4102 funct <<
4103 drive <<
4104 }; <<
4105 }; <<
4106 <<
4107 wsa_swr_active: wsa-s <<
4108 clk-pins { <<
4109 pins <<
4110 funct <<
4111 drive <<
4112 slew- <<
4113 bias- <<
4114 }; <<
4115 <<
4116 data-pins { <<
4117 pins <<
4118 funct <<
4119 drive <<
4120 slew- <<
4121 bias- <<
4122 }; <<
4123 }; <<
4124 <<
4125 wsa2_swr_active: wsa2 <<
4126 clk-pins { <<
4127 pins <<
4128 funct <<
4129 drive <<
4130 slew- <<
4131 bias- <<
4132 }; <<
4133 <<
4134 data-pins { <<
4135 pins <<
4136 funct <<
4137 drive <<
4138 slew- <<
4139 bias- <<
4140 }; <<
4141 }; <<
4142 }; <<
4143 <<
4144 sram@146aa000 { <<
4145 compatible = "qcom,sm <<
4146 reg = <0 0x146aa000 0 <<
4147 ranges = <0 0 0x146aa <<
4148 <<
4149 #address-cells = <1>; <<
4150 #size-cells = <1>; <<
4151 <<
4152 pil-reloc@94c { <<
4153 compatible = <<
4154 reg = <0x94c <<
4155 }; <<
4156 }; 2797 };
4157 2798
4158 apps_smmu: iommu@15000000 { 2799 apps_smmu: iommu@15000000 {
4159 compatible = "qcom,sm 2800 compatible = "qcom,sm8450-smmu-500", "arm,mmu-500";
4160 reg = <0 0x15000000 0 2801 reg = <0 0x15000000 0 0x100000>;
4161 #iommu-cells = <2>; 2802 #iommu-cells = <2>;
4162 #global-interrupts = 2803 #global-interrupts = <1>;
4163 interrupts = <GIC_SPI !! 2804 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
4164 <GIC_SPI !! 2805 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
4165 <GIC_SPI !! 2806 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
4166 <GIC_SPI !! 2807 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
4167 <GIC_SPI !! 2808 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
4168 <GIC_SPI !! 2809 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
4169 <GIC_SPI !! 2810 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
4170 <GIC_SPI !! 2811 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
4171 <GIC_SPI !! 2812 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
4172 <GIC_SPI !! 2813 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
4173 <GIC_SPI !! 2814 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
4174 <GIC_SPI !! 2815 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
4175 <GIC_SPI !! 2816 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
4176 <GIC_SPI !! 2817 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
4177 <GIC_SPI !! 2818 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
4178 <GIC_SPI !! 2819 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
4179 <GIC_SPI !! 2820 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
4180 <GIC_SPI !! 2821 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
4181 <GIC_SPI !! 2822 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
4182 <GIC_SPI !! 2823 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
4183 <GIC_SPI !! 2824 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
4184 <GIC_SPI !! 2825 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
4185 <GIC_SPI !! 2826 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
4186 <GIC_SPI !! 2827 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
4187 <GIC_SPI !! 2828 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
4188 <GIC_SPI !! 2829 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
4189 <GIC_SPI !! 2830 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
4190 <GIC_SPI !! 2831 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
4191 <GIC_SPI !! 2832 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
4192 <GIC_SPI !! 2833 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
4193 <GIC_SPI !! 2834 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
4194 <GIC_SPI !! 2835 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
4195 <GIC_SPI !! 2836 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
4196 <GIC_SPI !! 2837 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
4197 <GIC_SPI !! 2838 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
4198 <GIC_SPI !! 2839 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
4199 <GIC_SPI !! 2840 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
4200 <GIC_SPI !! 2841 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
4201 <GIC_SPI !! 2842 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
4202 <GIC_SPI !! 2843 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
4203 <GIC_SPI !! 2844 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
4204 <GIC_SPI !! 2845 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
4205 <GIC_SPI !! 2846 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
4206 <GIC_SPI !! 2847 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
4207 <GIC_SPI !! 2848 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
4208 <GIC_SPI !! 2849 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
4209 <GIC_SPI !! 2850 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
4210 <GIC_SPI !! 2851 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
4211 <GIC_SPI !! 2852 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
4212 <GIC_SPI !! 2853 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
4213 <GIC_SPI !! 2854 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
4214 <GIC_SPI !! 2855 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
4215 <GIC_SPI !! 2856 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
4216 <GIC_SPI !! 2857 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
4217 <GIC_SPI !! 2858 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
4218 <GIC_SPI !! 2859 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
4219 <GIC_SPI !! 2860 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
4220 <GIC_SPI !! 2861 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
4221 <GIC_SPI !! 2862 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
4222 <GIC_SPI !! 2863 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
4223 <GIC_SPI !! 2864 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
4224 <GIC_SPI !! 2865 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
4225 <GIC_SPI !! 2866 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
4226 <GIC_SPI !! 2867 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
4227 <GIC_SPI !! 2868 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
4228 <GIC_SPI !! 2869 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
4229 <GIC_SPI !! 2870 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
4230 <GIC_SPI !! 2871 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
4231 <GIC_SPI !! 2872 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
4232 <GIC_SPI !! 2873 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
4233 <GIC_SPI !! 2874 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
4234 <GIC_SPI !! 2875 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
4235 <GIC_SPI !! 2876 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
4236 <GIC_SPI !! 2877 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
4237 <GIC_SPI !! 2878 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
4238 <GIC_SPI !! 2879 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
4239 <GIC_SPI !! 2880 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
4240 <GIC_SPI !! 2881 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
4241 <GIC_SPI !! 2882 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
4242 <GIC_SPI !! 2883 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
4243 <GIC_SPI !! 2884 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
4244 <GIC_SPI !! 2885 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
4245 <GIC_SPI !! 2886 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
4246 <GIC_SPI !! 2887 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
4247 <GIC_SPI !! 2888 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
4248 <GIC_SPI !! 2889 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
4249 <GIC_SPI !! 2890 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
4250 <GIC_SPI !! 2891 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
4251 <GIC_SPI !! 2892 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
4252 <GIC_SPI !! 2893 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
4253 <GIC_SPI !! 2894 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
4254 <GIC_SPI !! 2895 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
4255 <GIC_SPI !! 2896 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
4256 <GIC_SPI !! 2897 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
4257 <GIC_SPI !! 2898 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
4258 <GIC_SPI !! 2899 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
4259 <GIC_SPI !! 2900 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>;
4260 }; 2901 };
4261 2902
4262 intc: interrupt-controller@17 2903 intc: interrupt-controller@17100000 {
4263 compatible = "arm,gic 2904 compatible = "arm,gic-v3";
4264 #interrupt-cells = <3 2905 #interrupt-cells = <3>;
4265 interrupt-controller; 2906 interrupt-controller;
4266 #redistributor-region 2907 #redistributor-regions = <1>;
4267 redistributor-stride 2908 redistributor-stride = <0x0 0x40000>;
4268 reg = <0x0 0x17100000 2909 reg = <0x0 0x17100000 0x0 0x10000>, /* GICD */
4269 <0x0 0x17180000 2910 <0x0 0x17180000 0x0 0x200000>; /* GICR * 8 */
4270 interrupts = <GIC_PPI 2911 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
4271 #address-cells = <2>; 2912 #address-cells = <2>;
4272 #size-cells = <2>; 2913 #size-cells = <2>;
4273 ranges; 2914 ranges;
4274 2915
4275 gic_its: msi-controll 2916 gic_its: msi-controller@17140000 {
4276 compatible = 2917 compatible = "arm,gic-v3-its";
4277 reg = <0x0 0x 2918 reg = <0x0 0x17140000 0x0 0x20000>;
4278 msi-controlle 2919 msi-controller;
4279 #msi-cells = 2920 #msi-cells = <1>;
4280 }; 2921 };
4281 }; 2922 };
4282 2923
4283 timer@17420000 { 2924 timer@17420000 {
4284 compatible = "arm,arm 2925 compatible = "arm,armv7-timer-mem";
4285 #address-cells = <1>; 2926 #address-cells = <1>;
4286 #size-cells = <1>; 2927 #size-cells = <1>;
4287 ranges = <0 0 0 0x200 2928 ranges = <0 0 0 0x20000000>;
4288 reg = <0x0 0x17420000 2929 reg = <0x0 0x17420000 0x0 0x1000>;
4289 clock-frequency = <19 2930 clock-frequency = <19200000>;
4290 2931
4291 frame@17421000 { 2932 frame@17421000 {
4292 frame-number 2933 frame-number = <0>;
4293 interrupts = 2934 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
4294 2935 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
4295 reg = <0x1742 2936 reg = <0x17421000 0x1000>,
4296 <0x1742 2937 <0x17422000 0x1000>;
4297 }; 2938 };
4298 2939
4299 frame@17423000 { 2940 frame@17423000 {
4300 frame-number 2941 frame-number = <1>;
4301 interrupts = 2942 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
4302 reg = <0x1742 2943 reg = <0x17423000 0x1000>;
4303 status = "dis 2944 status = "disabled";
4304 }; 2945 };
4305 2946
4306 frame@17425000 { 2947 frame@17425000 {
4307 frame-number 2948 frame-number = <2>;
4308 interrupts = 2949 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
4309 reg = <0x1742 2950 reg = <0x17425000 0x1000>;
4310 status = "dis 2951 status = "disabled";
4311 }; 2952 };
4312 2953
4313 frame@17427000 { 2954 frame@17427000 {
4314 frame-number 2955 frame-number = <3>;
4315 interrupts = 2956 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
4316 reg = <0x1742 2957 reg = <0x17427000 0x1000>;
4317 status = "dis 2958 status = "disabled";
4318 }; 2959 };
4319 2960
4320 frame@17429000 { 2961 frame@17429000 {
4321 frame-number 2962 frame-number = <4>;
4322 interrupts = 2963 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
4323 reg = <0x1742 2964 reg = <0x17429000 0x1000>;
4324 status = "dis 2965 status = "disabled";
4325 }; 2966 };
4326 2967
4327 frame@1742b000 { 2968 frame@1742b000 {
4328 frame-number 2969 frame-number = <5>;
4329 interrupts = 2970 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
4330 reg = <0x1742 2971 reg = <0x1742b000 0x1000>;
4331 status = "dis 2972 status = "disabled";
4332 }; 2973 };
4333 2974
4334 frame@1742d000 { 2975 frame@1742d000 {
4335 frame-number 2976 frame-number = <6>;
4336 interrupts = 2977 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
4337 reg = <0x1742 2978 reg = <0x1742d000 0x1000>;
4338 status = "dis 2979 status = "disabled";
4339 }; 2980 };
4340 }; 2981 };
4341 2982
4342 apps_rsc: rsc@17a00000 { 2983 apps_rsc: rsc@17a00000 {
4343 label = "apps_rsc"; 2984 label = "apps_rsc";
4344 compatible = "qcom,rp 2985 compatible = "qcom,rpmh-rsc";
4345 reg = <0x0 0x17a00000 2986 reg = <0x0 0x17a00000 0x0 0x10000>,
4346 <0x0 0x17a10000 2987 <0x0 0x17a10000 0x0 0x10000>,
4347 <0x0 0x17a20000 2988 <0x0 0x17a20000 0x0 0x10000>,
4348 <0x0 0x17a30000 2989 <0x0 0x17a30000 0x0 0x10000>;
4349 reg-names = "drv-0", 2990 reg-names = "drv-0", "drv-1", "drv-2", "drv-3";
4350 interrupts = <GIC_SPI 2991 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
4351 <GIC_SPI 2992 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
4352 <GIC_SPI 2993 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
4353 qcom,tcs-offset = <0x 2994 qcom,tcs-offset = <0xd00>;
4354 qcom,drv-id = <2>; 2995 qcom,drv-id = <2>;
4355 qcom,tcs-config = <AC 2996 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
4356 <WA 2997 <WAKE_TCS 2>, <CONTROL_TCS 0>;
4357 power-domains = <&CLU <<
4358 2998
4359 apps_bcm_voter: bcm-v 2999 apps_bcm_voter: bcm-voter {
4360 compatible = 3000 compatible = "qcom,bcm-voter";
4361 }; 3001 };
4362 3002
4363 rpmhcc: clock-control 3003 rpmhcc: clock-controller {
4364 compatible = 3004 compatible = "qcom,sm8450-rpmh-clk";
4365 #clock-cells 3005 #clock-cells = <1>;
4366 clock-names = 3006 clock-names = "xo";
4367 clocks = <&xo 3007 clocks = <&xo_board>;
4368 }; 3008 };
4369 3009
4370 rpmhpd: power-control 3010 rpmhpd: power-controller {
4371 compatible = 3011 compatible = "qcom,sm8450-rpmhpd";
4372 #power-domain 3012 #power-domain-cells = <1>;
4373 operating-poi 3013 operating-points-v2 = <&rpmhpd_opp_table>;
4374 3014
4375 rpmhpd_opp_ta 3015 rpmhpd_opp_table: opp-table {
4376 compa 3016 compatible = "operating-points-v2";
4377 3017
4378 rpmhp 3018 rpmhpd_opp_ret: opp1 {
4379 3019 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4380 }; 3020 };
4381 3021
4382 rpmhp 3022 rpmhpd_opp_min_svs: opp2 {
4383 3023 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4384 }; 3024 };
4385 3025
4386 rpmhp !! 3026 rpmhpd_opp_low_svs: opp3 {
4387 <<
4388 }; <<
4389 <<
4390 rpmhp <<
4391 3027 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4392 }; 3028 };
4393 3029
4394 rpmhp !! 3030 rpmhpd_opp_svs: opp4 {
4395 <<
4396 }; <<
4397 <<
4398 rpmhp <<
4399 3031 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4400 }; 3032 };
4401 3033
4402 rpmhp !! 3034 rpmhpd_opp_svs_l1: opp5 {
4403 <<
4404 }; <<
4405 <<
4406 rpmhp <<
4407 3035 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4408 }; 3036 };
4409 3037
4410 rpmhp !! 3038 rpmhpd_opp_nom: opp6 {
4411 <<
4412 }; <<
4413 <<
4414 rpmhp <<
4415 3039 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4416 }; 3040 };
4417 3041
4418 rpmhp !! 3042 rpmhpd_opp_nom_l1: opp7 {
4419 3043 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4420 }; 3044 };
4421 3045
4422 rpmhp !! 3046 rpmhpd_opp_nom_l2: opp8 {
4423 3047 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4424 }; 3048 };
4425 3049
4426 rpmhp !! 3050 rpmhpd_opp_turbo: opp9 {
4427 3051 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4428 }; 3052 };
4429 3053
4430 rpmhp !! 3054 rpmhpd_opp_turbo_l1: opp10 {
4431 3055 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4432 }; 3056 };
4433 }; 3057 };
4434 }; 3058 };
4435 }; 3059 };
4436 3060
4437 cpufreq_hw: cpufreq@17d91000 3061 cpufreq_hw: cpufreq@17d91000 {
4438 compatible = "qcom,sm 3062 compatible = "qcom,sm8450-cpufreq-epss", "qcom,cpufreq-epss";
4439 reg = <0 0x17d91000 0 3063 reg = <0 0x17d91000 0 0x1000>,
4440 <0 0x17d92000 0 3064 <0 0x17d92000 0 0x1000>,
4441 <0 0x17d93000 0 3065 <0 0x17d93000 0 0x1000>;
4442 reg-names = "freq-dom 3066 reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
4443 clocks = <&rpmhcc RPM 3067 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
4444 clock-names = "xo", " 3068 clock-names = "xo", "alternate";
4445 interrupts = <GIC_SPI 3069 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
4446 <GIC_SPI 3070 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
4447 <GIC_SPI 3071 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
4448 interrupt-names = "dc 3072 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
4449 #freq-domain-cells = 3073 #freq-domain-cells = <1>;
4450 #clock-cells = <1>; <<
4451 }; 3074 };
4452 3075
4453 gem_noc: interconnect@1910000 3076 gem_noc: interconnect@19100000 {
4454 compatible = "qcom,sm 3077 compatible = "qcom,sm8450-gem-noc";
4455 reg = <0 0x19100000 0 3078 reg = <0 0x19100000 0 0xbb800>;
4456 #interconnect-cells = 3079 #interconnect-cells = <2>;
4457 qcom,bcm-voters = <&a 3080 qcom,bcm-voters = <&apps_bcm_voter>;
4458 }; 3081 };
4459 3082
4460 system-cache-controller@19200 3083 system-cache-controller@19200000 {
4461 compatible = "qcom,sm 3084 compatible = "qcom,sm8450-llcc";
4462 reg = <0 0x19200000 0 !! 3085 reg = <0 0x19200000 0 0x580000>, <0 0x19a00000 0 0x80000>;
4463 <0 0x19300000 0 !! 3086 reg-names = "llcc_base", "llcc_broadcast_base";
4464 <0 0x19a00000 0 <<
4465 reg-names = "llcc0_ba <<
4466 "llcc3_ba <<
4467 "llcc_bro <<
4468 interrupts = <GIC_SPI 3087 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
4469 }; 3088 };
4470 3089
4471 ufs_mem_hc: ufshc@1d84000 { 3090 ufs_mem_hc: ufshc@1d84000 {
4472 compatible = "qcom,sm 3091 compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
4473 "jedec,u 3092 "jedec,ufs-2.0";
4474 reg = <0 0x01d84000 0 !! 3093 reg = <0 0x01d84000 0 0x3000>,
>> 3094 <0 0x01d88000 0 0x8000>;
>> 3095 reg-names = "std", "ice";
4475 interrupts = <GIC_SPI 3096 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
4476 phys = <&ufs_mem_phy> !! 3097 phys = <&ufs_mem_phy_lanes>;
4477 phy-names = "ufsphy"; 3098 phy-names = "ufsphy";
4478 lanes-per-direction = 3099 lanes-per-direction = <2>;
4479 #reset-cells = <1>; 3100 #reset-cells = <1>;
4480 resets = <&gcc GCC_UF 3101 resets = <&gcc GCC_UFS_PHY_BCR>;
4481 reset-names = "rst"; 3102 reset-names = "rst";
4482 3103
4483 power-domains = <&gcc 3104 power-domains = <&gcc UFS_PHY_GDSC>;
4484 3105
4485 iommus = <&apps_smmu 3106 iommus = <&apps_smmu 0xe0 0x0>;
4486 dma-coherent; 3107 dma-coherent;
4487 3108
4488 interconnects = <&agg 3109 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>,
4489 <&gem 3110 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
4490 interconnect-names = 3111 interconnect-names = "ufs-ddr", "cpu-ufs";
4491 clock-names = 3112 clock-names =
4492 "core_clk", 3113 "core_clk",
4493 "bus_aggr_clk 3114 "bus_aggr_clk",
4494 "iface_clk", 3115 "iface_clk",
4495 "core_clk_uni 3116 "core_clk_unipro",
4496 "ref_clk", 3117 "ref_clk",
4497 "tx_lane0_syn 3118 "tx_lane0_sync_clk",
4498 "rx_lane0_syn 3119 "rx_lane0_sync_clk",
4499 "rx_lane1_syn !! 3120 "rx_lane1_sync_clk",
>> 3121 "ice_core_clk";
4500 clocks = 3122 clocks =
4501 <&gcc GCC_UFS 3123 <&gcc GCC_UFS_PHY_AXI_CLK>,
4502 <&gcc GCC_AGG 3124 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
4503 <&gcc GCC_UFS 3125 <&gcc GCC_UFS_PHY_AHB_CLK>,
4504 <&gcc GCC_UFS 3126 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
4505 <&rpmhcc RPMH 3127 <&rpmhcc RPMH_CXO_CLK>,
4506 <&gcc GCC_UFS 3128 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
4507 <&gcc GCC_UFS 3129 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
4508 <&gcc GCC_UFS !! 3130 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
>> 3131 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
4509 freq-table-hz = 3132 freq-table-hz =
4510 <75000000 300 3133 <75000000 300000000>,
4511 <0 0>, 3134 <0 0>,
4512 <0 0>, 3135 <0 0>,
4513 <75000000 300 3136 <75000000 300000000>,
4514 <75000000 300 3137 <75000000 300000000>,
4515 <0 0>, 3138 <0 0>,
4516 <0 0>, 3139 <0 0>,
4517 <0 0>; !! 3140 <0 0>,
4518 qcom,ice = <&ice>; !! 3141 <75000000 300000000>;
4519 <<
4520 status = "disabled"; 3142 status = "disabled";
4521 }; 3143 };
4522 3144
4523 ufs_mem_phy: phy@1d87000 { 3145 ufs_mem_phy: phy@1d87000 {
4524 compatible = "qcom,sm 3146 compatible = "qcom,sm8450-qmp-ufs-phy";
4525 reg = <0 0x01d87000 0 !! 3147 reg = <0 0x01d87000 0 0x1c4>;
4526 !! 3148 #address-cells = <2>;
>> 3149 #size-cells = <2>;
>> 3150 ranges;
4527 clock-names = "ref", 3151 clock-names = "ref", "ref_aux", "qref";
4528 clocks = <&rpmhcc RPM 3152 clocks = <&rpmhcc RPMH_CXO_CLK>,
4529 <&gcc GCC_UF 3153 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
4530 <&gcc GCC_UF 3154 <&gcc GCC_UFS_0_CLKREF_EN>;
4531 3155
4532 power-domains = <&gcc 3156 power-domains = <&gcc UFS_PHY_GDSC>;
4533 3157
4534 resets = <&ufs_mem_hc 3158 resets = <&ufs_mem_hc 0>;
4535 reset-names = "ufsphy 3159 reset-names = "ufsphy";
4536 <<
4537 #clock-cells = <1>; <<
4538 #phy-cells = <0>; <<
4539 <<
4540 status = "disabled"; 3160 status = "disabled";
4541 }; <<
4542 3161
4543 ice: crypto@1d88000 { !! 3162 ufs_mem_phy_lanes: phy@1d87400 {
4544 compatible = "qcom,sm !! 3163 reg = <0 0x01d87400 0 0x188>,
4545 "qcom,in !! 3164 <0 0x01d87600 0 0x200>,
4546 reg = <0 0x01d88000 0 !! 3165 <0 0x01d87c00 0 0x200>,
4547 clocks = <&gcc GCC_UF !! 3166 <0 0x01d87800 0 0x188>,
4548 }; !! 3167 <0 0x01d87a00 0 0x200>;
4549 !! 3168 #phy-cells = <0>;
4550 cryptobam: dma-controller@1dc !! 3169 };
4551 compatible = "qcom,ba <<
4552 reg = <0 0x01dc4000 0 <<
4553 interrupts = <GIC_SPI <<
4554 #dma-cells = <1>; <<
4555 qcom,ee = <0>; <<
4556 qcom,controlled-remot <<
4557 iommus = <&apps_smmu <<
4558 <&apps_smmu <<
4559 <&apps_smmu <<
4560 <&apps_smmu <<
4561 <&apps_smmu <<
4562 }; <<
4563 <<
4564 crypto: crypto@1dfa000 { <<
4565 compatible = "qcom,sm <<
4566 reg = <0 0x01dfa000 0 <<
4567 dmas = <&cryptobam 4> <<
4568 dma-names = "rx", "tx <<
4569 iommus = <&apps_smmu <<
4570 <&apps_smmu <<
4571 <&apps_smmu <<
4572 <&apps_smmu <<
4573 <&apps_smmu <<
4574 interconnects = <&agg <<
4575 interconnect-names = <<
4576 }; 3170 };
4577 3171
4578 sdhc_2: mmc@8804000 { !! 3172 sdhc_2: sdhci@8804000 {
4579 compatible = "qcom,sm 3173 compatible = "qcom,sm8450-sdhci", "qcom,sdhci-msm-v5";
4580 reg = <0 0x08804000 0 3174 reg = <0 0x08804000 0 0x1000>;
4581 3175
4582 interrupts = <GIC_SPI 3176 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
4583 <GIC_SPI 3177 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
4584 interrupt-names = "hc 3178 interrupt-names = "hc_irq", "pwr_irq";
4585 3179
4586 clocks = <&gcc GCC_SD 3180 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
4587 <&gcc GCC_SD 3181 <&gcc GCC_SDCC2_APPS_CLK>,
4588 <&rpmhcc RPM 3182 <&rpmhcc RPMH_CXO_CLK>;
4589 clock-names = "iface" 3183 clock-names = "iface", "core", "xo";
4590 resets = <&gcc GCC_SD 3184 resets = <&gcc GCC_SDCC2_BCR>;
4591 interconnects = <&agg 3185 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
4592 <&gem 3186 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
4593 interconnect-names = 3187 interconnect-names = "sdhc-ddr","cpu-sdhc";
4594 iommus = <&apps_smmu 3188 iommus = <&apps_smmu 0x4a0 0x0>;
4595 power-domains = <&rpm !! 3189 power-domains = <&rpmhpd SM8450_CX>;
4596 operating-points-v2 = 3190 operating-points-v2 = <&sdhc2_opp_table>;
4597 bus-width = <4>; 3191 bus-width = <4>;
4598 dma-coherent; 3192 dma-coherent;
4599 3193
4600 /* Forbid SDR104/SDR5 3194 /* Forbid SDR104/SDR50 - broken hw! */
4601 sdhci-caps-mask = <0x 3195 sdhci-caps-mask = <0x3 0x0>;
4602 3196
4603 status = "disabled"; 3197 status = "disabled";
4604 3198
4605 sdhc2_opp_table: opp- 3199 sdhc2_opp_table: opp-table {
4606 compatible = 3200 compatible = "operating-points-v2";
4607 3201
4608 opp-100000000 3202 opp-100000000 {
4609 opp-h 3203 opp-hz = /bits/ 64 <100000000>;
4610 requi 3204 required-opps = <&rpmhpd_opp_low_svs>;
4611 }; 3205 };
4612 3206
4613 opp-202000000 3207 opp-202000000 {
4614 opp-h 3208 opp-hz = /bits/ 64 <202000000>;
4615 requi 3209 required-opps = <&rpmhpd_opp_svs_l1>;
4616 }; 3210 };
4617 }; 3211 };
4618 }; 3212 };
4619 3213
4620 usb_1: usb@a6f8800 { 3214 usb_1: usb@a6f8800 {
4621 compatible = "qcom,sm 3215 compatible = "qcom,sm8450-dwc3", "qcom,dwc3";
4622 reg = <0 0x0a6f8800 0 3216 reg = <0 0x0a6f8800 0 0x400>;
4623 status = "disabled"; 3217 status = "disabled";
4624 #address-cells = <2>; 3218 #address-cells = <2>;
4625 #size-cells = <2>; 3219 #size-cells = <2>;
4626 ranges; 3220 ranges;
4627 3221
4628 clocks = <&gcc GCC_CF 3222 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
4629 <&gcc GCC_US 3223 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
4630 <&gcc GCC_AG 3224 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
4631 <&gcc GCC_US 3225 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
4632 <&gcc GCC_US 3226 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4633 <&gcc GCC_US 3227 <&gcc GCC_USB3_0_CLKREF_EN>;
4634 clock-names = "cfg_no 3228 clock-names = "cfg_noc",
4635 "core", 3229 "core",
4636 "iface" 3230 "iface",
4637 "sleep" 3231 "sleep",
4638 "mock_u 3232 "mock_utmi",
4639 "xo"; 3233 "xo";
4640 3234
4641 assigned-clocks = <&g 3235 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4642 <&g 3236 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
4643 assigned-clock-rates 3237 assigned-clock-rates = <19200000>, <200000000>;
4644 3238
4645 interrupts-extended = 3239 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
4646 !! 3240 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
4647 <<
4648 3241 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
4649 !! 3242 <&pdc 14 IRQ_TYPE_EDGE_BOTH>;
4650 interrupt-names = "pw !! 3243 interrupt-names = "hs_phy_irq",
4651 "hs !! 3244 "ss_phy_irq",
4652 "dp <<
4653 "dm 3245 "dm_hs_phy_irq",
4654 "ss !! 3246 "dp_hs_phy_irq";
4655 3247
4656 power-domains = <&gcc 3248 power-domains = <&gcc USB30_PRIM_GDSC>;
4657 3249
4658 resets = <&gcc GCC_US 3250 resets = <&gcc GCC_USB30_PRIM_BCR>;
4659 3251
4660 interconnects = <&agg <<
4661 <&gem <<
4662 interconnect-names = <<
4663 <<
4664 usb_1_dwc3: usb@a6000 3252 usb_1_dwc3: usb@a600000 {
4665 compatible = 3253 compatible = "snps,dwc3";
4666 reg = <0 0x0a 3254 reg = <0 0x0a600000 0 0xcd00>;
4667 interrupts = 3255 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
4668 iommus = <&ap 3256 iommus = <&apps_smmu 0x0 0x0>;
4669 snps,dis_u2_s 3257 snps,dis_u2_susphy_quirk;
4670 snps,dis_enbl 3258 snps,dis_enblslpm_quirk;
4671 phys = <&usb_ !! 3259 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
4672 phy-names = " 3260 phy-names = "usb2-phy", "usb3-phy";
4673 <<
4674 ports { <<
4675 #addr <<
4676 #size <<
4677 <<
4678 port@ <<
4679 <<
4680 <<
4681 <<
4682 <<
4683 }; <<
4684 <<
4685 port@ <<
4686 <<
4687 <<
4688 <<
4689 <<
4690 <<
4691 }; <<
4692 }; <<
4693 }; 3261 };
4694 }; 3262 };
4695 3263
4696 nsp_noc: interconnect@320c000 3264 nsp_noc: interconnect@320c0000 {
4697 compatible = "qcom,sm 3265 compatible = "qcom,sm8450-nsp-noc";
4698 reg = <0 0x320c0000 0 3266 reg = <0 0x320c0000 0 0x10000>;
4699 #interconnect-cells = 3267 #interconnect-cells = <2>;
4700 qcom,bcm-voters = <&a 3268 qcom,bcm-voters = <&apps_bcm_voter>;
4701 }; 3269 };
4702 3270
4703 lpass_ag_noc: interconnect@3c 3271 lpass_ag_noc: interconnect@3c40000 {
4704 compatible = "qcom,sm 3272 compatible = "qcom,sm8450-lpass-ag-noc";
4705 reg = <0 0x03c40000 0 !! 3273 reg = <0 0x3c40000 0 0x17200>;
4706 #interconnect-cells = 3274 #interconnect-cells = <2>;
4707 qcom,bcm-voters = <&a 3275 qcom,bcm-voters = <&apps_bcm_voter>;
4708 }; 3276 };
4709 }; 3277 };
4710 3278
4711 sound: sound { <<
4712 }; <<
4713 <<
4714 thermal-zones { 3279 thermal-zones {
4715 aoss0-thermal { 3280 aoss0-thermal {
>> 3281 polling-delay-passive = <0>;
>> 3282 polling-delay = <0>;
4716 thermal-sensors = <&t 3283 thermal-sensors = <&tsens0 0>;
4717 3284
4718 trips { 3285 trips {
4719 thermal-engin 3286 thermal-engine-config {
4720 tempe 3287 temperature = <125000>;
4721 hyste 3288 hysteresis = <1000>;
4722 type 3289 type = "passive";
4723 }; 3290 };
4724 3291
4725 reset-mon-cfg 3292 reset-mon-cfg {
4726 tempe 3293 temperature = <115000>;
4727 hyste 3294 hysteresis = <5000>;
4728 type 3295 type = "passive";
4729 }; 3296 };
4730 }; 3297 };
4731 }; 3298 };
4732 3299
4733 cpuss0-thermal { 3300 cpuss0-thermal {
>> 3301 polling-delay-passive = <0>;
>> 3302 polling-delay = <0>;
4734 thermal-sensors = <&t 3303 thermal-sensors = <&tsens0 1>;
4735 3304
4736 trips { 3305 trips {
4737 thermal-engin 3306 thermal-engine-config {
4738 tempe 3307 temperature = <125000>;
4739 hyste 3308 hysteresis = <1000>;
4740 type 3309 type = "passive";
4741 }; 3310 };
4742 3311
4743 reset-mon-cfg 3312 reset-mon-cfg {
4744 tempe 3313 temperature = <115000>;
4745 hyste 3314 hysteresis = <5000>;
4746 type 3315 type = "passive";
4747 }; 3316 };
4748 }; 3317 };
4749 }; 3318 };
4750 3319
4751 cpuss1-thermal { 3320 cpuss1-thermal {
>> 3321 polling-delay-passive = <0>;
>> 3322 polling-delay = <0>;
4752 thermal-sensors = <&t 3323 thermal-sensors = <&tsens0 2>;
4753 3324
4754 trips { 3325 trips {
4755 thermal-engin 3326 thermal-engine-config {
4756 tempe 3327 temperature = <125000>;
4757 hyste 3328 hysteresis = <1000>;
4758 type 3329 type = "passive";
4759 }; 3330 };
4760 3331
4761 reset-mon-cfg 3332 reset-mon-cfg {
4762 tempe 3333 temperature = <115000>;
4763 hyste 3334 hysteresis = <5000>;
4764 type 3335 type = "passive";
4765 }; 3336 };
4766 }; 3337 };
4767 }; 3338 };
4768 3339
4769 cpuss3-thermal { 3340 cpuss3-thermal {
>> 3341 polling-delay-passive = <0>;
>> 3342 polling-delay = <0>;
4770 thermal-sensors = <&t 3343 thermal-sensors = <&tsens0 3>;
4771 3344
4772 trips { 3345 trips {
4773 thermal-engin 3346 thermal-engine-config {
4774 tempe 3347 temperature = <125000>;
4775 hyste 3348 hysteresis = <1000>;
4776 type 3349 type = "passive";
4777 }; 3350 };
4778 3351
4779 reset-mon-cfg 3352 reset-mon-cfg {
4780 tempe 3353 temperature = <115000>;
4781 hyste 3354 hysteresis = <5000>;
4782 type 3355 type = "passive";
4783 }; 3356 };
4784 }; 3357 };
4785 }; 3358 };
4786 3359
4787 cpuss4-thermal { 3360 cpuss4-thermal {
>> 3361 polling-delay-passive = <0>;
>> 3362 polling-delay = <0>;
4788 thermal-sensors = <&t 3363 thermal-sensors = <&tsens0 4>;
4789 3364
4790 trips { 3365 trips {
4791 thermal-engin 3366 thermal-engine-config {
4792 tempe 3367 temperature = <125000>;
4793 hyste 3368 hysteresis = <1000>;
4794 type 3369 type = "passive";
4795 }; 3370 };
4796 3371
4797 reset-mon-cfg 3372 reset-mon-cfg {
4798 tempe 3373 temperature = <115000>;
4799 hyste 3374 hysteresis = <5000>;
4800 type 3375 type = "passive";
4801 }; 3376 };
4802 }; 3377 };
4803 }; 3378 };
4804 3379
4805 cpu4-top-thermal { 3380 cpu4-top-thermal {
>> 3381 polling-delay-passive = <0>;
>> 3382 polling-delay = <0>;
4806 thermal-sensors = <&t 3383 thermal-sensors = <&tsens0 5>;
4807 3384
4808 trips { 3385 trips {
4809 cpu4_top_aler 3386 cpu4_top_alert0: trip-point0 {
4810 tempe 3387 temperature = <90000>;
4811 hyste 3388 hysteresis = <2000>;
4812 type 3389 type = "passive";
4813 }; 3390 };
4814 3391
4815 cpu4_top_aler 3392 cpu4_top_alert1: trip-point1 {
4816 tempe 3393 temperature = <95000>;
4817 hyste 3394 hysteresis = <2000>;
4818 type 3395 type = "passive";
4819 }; 3396 };
4820 3397
4821 cpu4_top_crit !! 3398 cpu4_top_crit: cpu_crit {
4822 tempe 3399 temperature = <110000>;
4823 hyste 3400 hysteresis = <1000>;
4824 type 3401 type = "critical";
4825 }; 3402 };
4826 }; 3403 };
4827 }; 3404 };
4828 3405
4829 cpu4-bottom-thermal { 3406 cpu4-bottom-thermal {
>> 3407 polling-delay-passive = <0>;
>> 3408 polling-delay = <0>;
4830 thermal-sensors = <&t 3409 thermal-sensors = <&tsens0 6>;
4831 3410
4832 trips { 3411 trips {
4833 cpu4_bottom_a 3412 cpu4_bottom_alert0: trip-point0 {
4834 tempe 3413 temperature = <90000>;
4835 hyste 3414 hysteresis = <2000>;
4836 type 3415 type = "passive";
4837 }; 3416 };
4838 3417
4839 cpu4_bottom_a 3418 cpu4_bottom_alert1: trip-point1 {
4840 tempe 3419 temperature = <95000>;
4841 hyste 3420 hysteresis = <2000>;
4842 type 3421 type = "passive";
4843 }; 3422 };
4844 3423
4845 cpu4_bottom_c !! 3424 cpu4_bottom_crit: cpu_crit {
4846 tempe 3425 temperature = <110000>;
4847 hyste 3426 hysteresis = <1000>;
4848 type 3427 type = "critical";
4849 }; 3428 };
4850 }; 3429 };
4851 }; 3430 };
4852 3431
4853 cpu5-top-thermal { 3432 cpu5-top-thermal {
>> 3433 polling-delay-passive = <0>;
>> 3434 polling-delay = <0>;
4854 thermal-sensors = <&t 3435 thermal-sensors = <&tsens0 7>;
4855 3436
4856 trips { 3437 trips {
4857 cpu5_top_aler 3438 cpu5_top_alert0: trip-point0 {
4858 tempe 3439 temperature = <90000>;
4859 hyste 3440 hysteresis = <2000>;
4860 type 3441 type = "passive";
4861 }; 3442 };
4862 3443
4863 cpu5_top_aler 3444 cpu5_top_alert1: trip-point1 {
4864 tempe 3445 temperature = <95000>;
4865 hyste 3446 hysteresis = <2000>;
4866 type 3447 type = "passive";
4867 }; 3448 };
4868 3449
4869 cpu5_top_crit !! 3450 cpu5_top_crit: cpu_crit {
4870 tempe 3451 temperature = <110000>;
4871 hyste 3452 hysteresis = <1000>;
4872 type 3453 type = "critical";
4873 }; 3454 };
4874 }; 3455 };
4875 }; 3456 };
4876 3457
4877 cpu5-bottom-thermal { 3458 cpu5-bottom-thermal {
>> 3459 polling-delay-passive = <0>;
>> 3460 polling-delay = <0>;
4878 thermal-sensors = <&t 3461 thermal-sensors = <&tsens0 8>;
4879 3462
4880 trips { 3463 trips {
4881 cpu5_bottom_a 3464 cpu5_bottom_alert0: trip-point0 {
4882 tempe 3465 temperature = <90000>;
4883 hyste 3466 hysteresis = <2000>;
4884 type 3467 type = "passive";
4885 }; 3468 };
4886 3469
4887 cpu5_bottom_a 3470 cpu5_bottom_alert1: trip-point1 {
4888 tempe 3471 temperature = <95000>;
4889 hyste 3472 hysteresis = <2000>;
4890 type 3473 type = "passive";
4891 }; 3474 };
4892 3475
4893 cpu5_bottom_c !! 3476 cpu5_bottom_crit: cpu_crit {
4894 tempe 3477 temperature = <110000>;
4895 hyste 3478 hysteresis = <1000>;
4896 type 3479 type = "critical";
4897 }; 3480 };
4898 }; 3481 };
4899 }; 3482 };
4900 3483
4901 cpu6-top-thermal { 3484 cpu6-top-thermal {
>> 3485 polling-delay-passive = <0>;
>> 3486 polling-delay = <0>;
4902 thermal-sensors = <&t 3487 thermal-sensors = <&tsens0 9>;
4903 3488
4904 trips { 3489 trips {
4905 cpu6_top_aler 3490 cpu6_top_alert0: trip-point0 {
4906 tempe 3491 temperature = <90000>;
4907 hyste 3492 hysteresis = <2000>;
4908 type 3493 type = "passive";
4909 }; 3494 };
4910 3495
4911 cpu6_top_aler 3496 cpu6_top_alert1: trip-point1 {
4912 tempe 3497 temperature = <95000>;
4913 hyste 3498 hysteresis = <2000>;
4914 type 3499 type = "passive";
4915 }; 3500 };
4916 3501
4917 cpu6_top_crit !! 3502 cpu6_top_crit: cpu_crit {
4918 tempe 3503 temperature = <110000>;
4919 hyste 3504 hysteresis = <1000>;
4920 type 3505 type = "critical";
4921 }; 3506 };
4922 }; 3507 };
4923 }; 3508 };
4924 3509
4925 cpu6-bottom-thermal { 3510 cpu6-bottom-thermal {
>> 3511 polling-delay-passive = <0>;
>> 3512 polling-delay = <0>;
4926 thermal-sensors = <&t 3513 thermal-sensors = <&tsens0 10>;
4927 3514
4928 trips { 3515 trips {
4929 cpu6_bottom_a 3516 cpu6_bottom_alert0: trip-point0 {
4930 tempe 3517 temperature = <90000>;
4931 hyste 3518 hysteresis = <2000>;
4932 type 3519 type = "passive";
4933 }; 3520 };
4934 3521
4935 cpu6_bottom_a 3522 cpu6_bottom_alert1: trip-point1 {
4936 tempe 3523 temperature = <95000>;
4937 hyste 3524 hysteresis = <2000>;
4938 type 3525 type = "passive";
4939 }; 3526 };
4940 3527
4941 cpu6_bottom_c !! 3528 cpu6_bottom_crit: cpu_crit {
4942 tempe 3529 temperature = <110000>;
4943 hyste 3530 hysteresis = <1000>;
4944 type 3531 type = "critical";
4945 }; 3532 };
4946 }; 3533 };
4947 }; 3534 };
4948 3535
4949 cpu7-top-thermal { 3536 cpu7-top-thermal {
>> 3537 polling-delay-passive = <0>;
>> 3538 polling-delay = <0>;
4950 thermal-sensors = <&t 3539 thermal-sensors = <&tsens0 11>;
4951 3540
4952 trips { 3541 trips {
4953 cpu7_top_aler 3542 cpu7_top_alert0: trip-point0 {
4954 tempe 3543 temperature = <90000>;
4955 hyste 3544 hysteresis = <2000>;
4956 type 3545 type = "passive";
4957 }; 3546 };
4958 3547
4959 cpu7_top_aler 3548 cpu7_top_alert1: trip-point1 {
4960 tempe 3549 temperature = <95000>;
4961 hyste 3550 hysteresis = <2000>;
4962 type 3551 type = "passive";
4963 }; 3552 };
4964 3553
4965 cpu7_top_crit !! 3554 cpu7_top_crit: cpu_crit {
4966 tempe 3555 temperature = <110000>;
4967 hyste 3556 hysteresis = <1000>;
4968 type 3557 type = "critical";
4969 }; 3558 };
4970 }; 3559 };
4971 }; 3560 };
4972 3561
4973 cpu7-middle-thermal { 3562 cpu7-middle-thermal {
>> 3563 polling-delay-passive = <0>;
>> 3564 polling-delay = <0>;
4974 thermal-sensors = <&t 3565 thermal-sensors = <&tsens0 12>;
4975 3566
4976 trips { 3567 trips {
4977 cpu7_middle_a 3568 cpu7_middle_alert0: trip-point0 {
4978 tempe 3569 temperature = <90000>;
4979 hyste 3570 hysteresis = <2000>;
4980 type 3571 type = "passive";
4981 }; 3572 };
4982 3573
4983 cpu7_middle_a 3574 cpu7_middle_alert1: trip-point1 {
4984 tempe 3575 temperature = <95000>;
4985 hyste 3576 hysteresis = <2000>;
4986 type 3577 type = "passive";
4987 }; 3578 };
4988 3579
4989 cpu7_middle_c !! 3580 cpu7_middle_crit: cpu_crit {
4990 tempe 3581 temperature = <110000>;
4991 hyste 3582 hysteresis = <1000>;
4992 type 3583 type = "critical";
4993 }; 3584 };
4994 }; 3585 };
4995 }; 3586 };
4996 3587
4997 cpu7-bottom-thermal { 3588 cpu7-bottom-thermal {
>> 3589 polling-delay-passive = <0>;
>> 3590 polling-delay = <0>;
4998 thermal-sensors = <&t 3591 thermal-sensors = <&tsens0 13>;
4999 3592
5000 trips { 3593 trips {
5001 cpu7_bottom_a 3594 cpu7_bottom_alert0: trip-point0 {
5002 tempe 3595 temperature = <90000>;
5003 hyste 3596 hysteresis = <2000>;
5004 type 3597 type = "passive";
5005 }; 3598 };
5006 3599
5007 cpu7_bottom_a 3600 cpu7_bottom_alert1: trip-point1 {
5008 tempe 3601 temperature = <95000>;
5009 hyste 3602 hysteresis = <2000>;
5010 type 3603 type = "passive";
5011 }; 3604 };
5012 3605
5013 cpu7_bottom_c !! 3606 cpu7_bottom_crit: cpu_crit {
5014 tempe 3607 temperature = <110000>;
5015 hyste 3608 hysteresis = <1000>;
5016 type 3609 type = "critical";
5017 }; 3610 };
5018 }; 3611 };
5019 }; 3612 };
5020 3613
5021 gpu-top-thermal { 3614 gpu-top-thermal {
5022 polling-delay-passive 3615 polling-delay-passive = <10>;
5023 !! 3616 polling-delay = <0>;
5024 thermal-sensors = <&t 3617 thermal-sensors = <&tsens0 14>;
5025 3618
5026 cooling-maps { <<
5027 map0 { <<
5028 trip <<
5029 cooli <<
5030 }; <<
5031 }; <<
5032 <<
5033 trips { 3619 trips {
5034 gpu_top_alert !! 3620 thermal-engine-config {
5035 tempe !! 3621 temperature = <125000>;
5036 hyste 3622 hysteresis = <1000>;
5037 type 3623 type = "passive";
5038 }; 3624 };
5039 3625
5040 trip-point1 { !! 3626 thermal-hal-config {
5041 tempe !! 3627 temperature = <125000>;
5042 hyste 3628 hysteresis = <1000>;
5043 type !! 3629 type = "passive";
5044 }; 3630 };
5045 3631
5046 trip-point2 { !! 3632 reset-mon-cfg {
5047 tempe !! 3633 temperature = <115000>;
5048 hyste !! 3634 hysteresis = <5000>;
5049 type !! 3635 type = "passive";
>> 3636 };
>> 3637
>> 3638 gpu0_tj_cfg: tj_cfg {
>> 3639 temperature = <95000>;
>> 3640 hysteresis = <5000>;
>> 3641 type = "passive";
5050 }; 3642 };
5051 }; 3643 };
5052 }; 3644 };
5053 3645
5054 gpu-bottom-thermal { 3646 gpu-bottom-thermal {
5055 polling-delay-passive 3647 polling-delay-passive = <10>;
5056 !! 3648 polling-delay = <0>;
5057 thermal-sensors = <&t 3649 thermal-sensors = <&tsens0 15>;
5058 3650
5059 cooling-maps { <<
5060 map0 { <<
5061 trip <<
5062 cooli <<
5063 }; <<
5064 }; <<
5065 <<
5066 trips { 3651 trips {
5067 gpu_bottom_al !! 3652 thermal-engine-config {
5068 tempe !! 3653 temperature = <125000>;
5069 hyste 3654 hysteresis = <1000>;
5070 type 3655 type = "passive";
5071 }; 3656 };
5072 3657
5073 trip-point1 { !! 3658 thermal-hal-config {
5074 tempe !! 3659 temperature = <125000>;
5075 hyste 3660 hysteresis = <1000>;
5076 type !! 3661 type = "passive";
5077 }; 3662 };
5078 3663
5079 trip-point2 { !! 3664 reset-mon-cfg {
5080 tempe !! 3665 temperature = <115000>;
5081 hyste !! 3666 hysteresis = <5000>;
5082 type !! 3667 type = "passive";
>> 3668 };
>> 3669
>> 3670 gpu1_tj_cfg: tj_cfg {
>> 3671 temperature = <95000>;
>> 3672 hysteresis = <5000>;
>> 3673 type = "passive";
5083 }; 3674 };
5084 }; 3675 };
5085 }; 3676 };
5086 3677
5087 aoss1-thermal { 3678 aoss1-thermal {
>> 3679 polling-delay-passive = <0>;
>> 3680 polling-delay = <0>;
5088 thermal-sensors = <&t 3681 thermal-sensors = <&tsens1 0>;
5089 3682
5090 trips { 3683 trips {
5091 thermal-engin 3684 thermal-engine-config {
5092 tempe 3685 temperature = <125000>;
5093 hyste 3686 hysteresis = <1000>;
5094 type 3687 type = "passive";
5095 }; 3688 };
5096 3689
5097 reset-mon-cfg 3690 reset-mon-cfg {
5098 tempe 3691 temperature = <115000>;
5099 hyste 3692 hysteresis = <5000>;
5100 type 3693 type = "passive";
5101 }; 3694 };
5102 }; 3695 };
5103 }; 3696 };
5104 3697
5105 cpu0-thermal { 3698 cpu0-thermal {
>> 3699 polling-delay-passive = <0>;
>> 3700 polling-delay = <0>;
5106 thermal-sensors = <&t 3701 thermal-sensors = <&tsens1 1>;
5107 3702
5108 trips { 3703 trips {
5109 cpu0_alert0: 3704 cpu0_alert0: trip-point0 {
5110 tempe 3705 temperature = <90000>;
5111 hyste 3706 hysteresis = <2000>;
5112 type 3707 type = "passive";
5113 }; 3708 };
5114 3709
5115 cpu0_alert1: 3710 cpu0_alert1: trip-point1 {
5116 tempe 3711 temperature = <95000>;
5117 hyste 3712 hysteresis = <2000>;
5118 type 3713 type = "passive";
5119 }; 3714 };
5120 3715
5121 cpu0_crit: cp !! 3716 cpu0_crit: cpu_crit {
5122 tempe 3717 temperature = <110000>;
5123 hyste 3718 hysteresis = <1000>;
5124 type 3719 type = "critical";
5125 }; 3720 };
5126 }; 3721 };
5127 }; 3722 };
5128 3723
5129 cpu1-thermal { 3724 cpu1-thermal {
>> 3725 polling-delay-passive = <0>;
>> 3726 polling-delay = <0>;
5130 thermal-sensors = <&t 3727 thermal-sensors = <&tsens1 2>;
5131 3728
5132 trips { 3729 trips {
5133 cpu1_alert0: 3730 cpu1_alert0: trip-point0 {
5134 tempe 3731 temperature = <90000>;
5135 hyste 3732 hysteresis = <2000>;
5136 type 3733 type = "passive";
5137 }; 3734 };
5138 3735
5139 cpu1_alert1: 3736 cpu1_alert1: trip-point1 {
5140 tempe 3737 temperature = <95000>;
5141 hyste 3738 hysteresis = <2000>;
5142 type 3739 type = "passive";
5143 }; 3740 };
5144 3741
5145 cpu1_crit: cp !! 3742 cpu1_crit: cpu_crit {
5146 tempe 3743 temperature = <110000>;
5147 hyste 3744 hysteresis = <1000>;
5148 type 3745 type = "critical";
5149 }; 3746 };
5150 }; 3747 };
5151 }; 3748 };
5152 3749
5153 cpu2-thermal { 3750 cpu2-thermal {
>> 3751 polling-delay-passive = <0>;
>> 3752 polling-delay = <0>;
5154 thermal-sensors = <&t 3753 thermal-sensors = <&tsens1 3>;
5155 3754
5156 trips { 3755 trips {
5157 cpu2_alert0: 3756 cpu2_alert0: trip-point0 {
5158 tempe 3757 temperature = <90000>;
5159 hyste 3758 hysteresis = <2000>;
5160 type 3759 type = "passive";
5161 }; 3760 };
5162 3761
5163 cpu2_alert1: 3762 cpu2_alert1: trip-point1 {
5164 tempe 3763 temperature = <95000>;
5165 hyste 3764 hysteresis = <2000>;
5166 type 3765 type = "passive";
5167 }; 3766 };
5168 3767
5169 cpu2_crit: cp !! 3768 cpu2_crit: cpu_crit {
5170 tempe 3769 temperature = <110000>;
5171 hyste 3770 hysteresis = <1000>;
5172 type 3771 type = "critical";
5173 }; 3772 };
5174 }; 3773 };
5175 }; 3774 };
5176 3775
5177 cpu3-thermal { 3776 cpu3-thermal {
>> 3777 polling-delay-passive = <0>;
>> 3778 polling-delay = <0>;
5178 thermal-sensors = <&t 3779 thermal-sensors = <&tsens1 4>;
5179 3780
5180 trips { 3781 trips {
5181 cpu3_alert0: 3782 cpu3_alert0: trip-point0 {
5182 tempe 3783 temperature = <90000>;
5183 hyste 3784 hysteresis = <2000>;
5184 type 3785 type = "passive";
5185 }; 3786 };
5186 3787
5187 cpu3_alert1: 3788 cpu3_alert1: trip-point1 {
5188 tempe 3789 temperature = <95000>;
5189 hyste 3790 hysteresis = <2000>;
5190 type 3791 type = "passive";
5191 }; 3792 };
5192 3793
5193 cpu3_crit: cp !! 3794 cpu3_crit: cpu_crit {
5194 tempe 3795 temperature = <110000>;
5195 hyste 3796 hysteresis = <1000>;
5196 type 3797 type = "critical";
5197 }; 3798 };
5198 }; 3799 };
5199 }; 3800 };
5200 3801
5201 cdsp0-thermal { 3802 cdsp0-thermal {
5202 polling-delay-passive 3803 polling-delay-passive = <10>;
5203 !! 3804 polling-delay = <0>;
5204 thermal-sensors = <&t 3805 thermal-sensors = <&tsens1 5>;
5205 3806
5206 trips { 3807 trips {
5207 thermal-engin 3808 thermal-engine-config {
5208 tempe 3809 temperature = <125000>;
5209 hyste 3810 hysteresis = <1000>;
5210 type 3811 type = "passive";
5211 }; 3812 };
5212 3813
5213 thermal-hal-c 3814 thermal-hal-config {
5214 tempe 3815 temperature = <125000>;
5215 hyste 3816 hysteresis = <1000>;
5216 type 3817 type = "passive";
5217 }; 3818 };
5218 3819
5219 reset-mon-cfg 3820 reset-mon-cfg {
5220 tempe 3821 temperature = <115000>;
5221 hyste 3822 hysteresis = <5000>;
5222 type 3823 type = "passive";
5223 }; 3824 };
5224 3825
5225 cdsp_0_config 3826 cdsp_0_config: junction-config {
5226 tempe 3827 temperature = <95000>;
5227 hyste 3828 hysteresis = <5000>;
5228 type 3829 type = "passive";
5229 }; 3830 };
5230 }; 3831 };
5231 }; 3832 };
5232 3833
5233 cdsp1-thermal { 3834 cdsp1-thermal {
5234 polling-delay-passive 3835 polling-delay-passive = <10>;
5235 !! 3836 polling-delay = <0>;
5236 thermal-sensors = <&t 3837 thermal-sensors = <&tsens1 6>;
5237 3838
5238 trips { 3839 trips {
5239 thermal-engin 3840 thermal-engine-config {
5240 tempe 3841 temperature = <125000>;
5241 hyste 3842 hysteresis = <1000>;
5242 type 3843 type = "passive";
5243 }; 3844 };
5244 3845
5245 thermal-hal-c 3846 thermal-hal-config {
5246 tempe 3847 temperature = <125000>;
5247 hyste 3848 hysteresis = <1000>;
5248 type 3849 type = "passive";
5249 }; 3850 };
5250 3851
5251 reset-mon-cfg 3852 reset-mon-cfg {
5252 tempe 3853 temperature = <115000>;
5253 hyste 3854 hysteresis = <5000>;
5254 type 3855 type = "passive";
5255 }; 3856 };
5256 3857
5257 cdsp_1_config 3858 cdsp_1_config: junction-config {
5258 tempe 3859 temperature = <95000>;
5259 hyste 3860 hysteresis = <5000>;
5260 type 3861 type = "passive";
5261 }; 3862 };
5262 }; 3863 };
5263 }; 3864 };
5264 3865
5265 cdsp2-thermal { 3866 cdsp2-thermal {
5266 polling-delay-passive 3867 polling-delay-passive = <10>;
5267 !! 3868 polling-delay = <0>;
5268 thermal-sensors = <&t 3869 thermal-sensors = <&tsens1 7>;
5269 3870
5270 trips { 3871 trips {
5271 thermal-engin 3872 thermal-engine-config {
5272 tempe 3873 temperature = <125000>;
5273 hyste 3874 hysteresis = <1000>;
5274 type 3875 type = "passive";
5275 }; 3876 };
5276 3877
5277 thermal-hal-c 3878 thermal-hal-config {
5278 tempe 3879 temperature = <125000>;
5279 hyste 3880 hysteresis = <1000>;
5280 type 3881 type = "passive";
5281 }; 3882 };
5282 3883
5283 reset-mon-cfg 3884 reset-mon-cfg {
5284 tempe 3885 temperature = <115000>;
5285 hyste 3886 hysteresis = <5000>;
5286 type 3887 type = "passive";
5287 }; 3888 };
5288 3889
5289 cdsp_2_config 3890 cdsp_2_config: junction-config {
5290 tempe 3891 temperature = <95000>;
5291 hyste 3892 hysteresis = <5000>;
5292 type 3893 type = "passive";
5293 }; 3894 };
5294 }; 3895 };
5295 }; 3896 };
5296 3897
5297 video-thermal { 3898 video-thermal {
>> 3899 polling-delay-passive = <0>;
>> 3900 polling-delay = <0>;
5298 thermal-sensors = <&t 3901 thermal-sensors = <&tsens1 8>;
5299 3902
5300 trips { 3903 trips {
5301 thermal-engin 3904 thermal-engine-config {
5302 tempe 3905 temperature = <125000>;
5303 hyste 3906 hysteresis = <1000>;
5304 type 3907 type = "passive";
5305 }; 3908 };
5306 3909
5307 reset-mon-cfg 3910 reset-mon-cfg {
5308 tempe 3911 temperature = <115000>;
5309 hyste 3912 hysteresis = <5000>;
5310 type 3913 type = "passive";
5311 }; 3914 };
5312 }; 3915 };
5313 }; 3916 };
5314 3917
5315 mem-thermal { 3918 mem-thermal {
5316 polling-delay-passive 3919 polling-delay-passive = <10>;
5317 !! 3920 polling-delay = <0>;
5318 thermal-sensors = <&t 3921 thermal-sensors = <&tsens1 9>;
5319 3922
5320 trips { 3923 trips {
5321 thermal-engin 3924 thermal-engine-config {
5322 tempe 3925 temperature = <125000>;
5323 hyste 3926 hysteresis = <1000>;
5324 type 3927 type = "passive";
5325 }; 3928 };
5326 3929
5327 ddr_config0: 3930 ddr_config0: ddr0-config {
5328 tempe 3931 temperature = <90000>;
5329 hyste 3932 hysteresis = <5000>;
5330 type 3933 type = "passive";
5331 }; 3934 };
5332 3935
5333 reset-mon-cfg 3936 reset-mon-cfg {
5334 tempe 3937 temperature = <115000>;
5335 hyste 3938 hysteresis = <5000>;
5336 type 3939 type = "passive";
5337 }; 3940 };
5338 }; 3941 };
5339 }; 3942 };
5340 3943
5341 modem0-thermal { 3944 modem0-thermal {
>> 3945 polling-delay-passive = <0>;
>> 3946 polling-delay = <0>;
5342 thermal-sensors = <&t 3947 thermal-sensors = <&tsens1 10>;
5343 3948
5344 trips { 3949 trips {
5345 thermal-engin 3950 thermal-engine-config {
5346 tempe 3951 temperature = <125000>;
5347 hyste 3952 hysteresis = <1000>;
5348 type 3953 type = "passive";
5349 }; 3954 };
5350 3955
5351 mdmss0_config 3956 mdmss0_config0: mdmss0-config0 {
5352 tempe 3957 temperature = <102000>;
5353 hyste 3958 hysteresis = <3000>;
5354 type 3959 type = "passive";
5355 }; 3960 };
5356 3961
5357 mdmss0_config 3962 mdmss0_config1: mdmss0-config1 {
5358 tempe 3963 temperature = <105000>;
5359 hyste 3964 hysteresis = <3000>;
5360 type 3965 type = "passive";
5361 }; 3966 };
5362 3967
5363 reset-mon-cfg 3968 reset-mon-cfg {
5364 tempe 3969 temperature = <115000>;
5365 hyste 3970 hysteresis = <5000>;
5366 type 3971 type = "passive";
5367 }; 3972 };
5368 }; 3973 };
5369 }; 3974 };
5370 3975
5371 modem1-thermal { 3976 modem1-thermal {
>> 3977 polling-delay-passive = <0>;
>> 3978 polling-delay = <0>;
5372 thermal-sensors = <&t 3979 thermal-sensors = <&tsens1 11>;
5373 3980
5374 trips { 3981 trips {
5375 thermal-engin 3982 thermal-engine-config {
5376 tempe 3983 temperature = <125000>;
5377 hyste 3984 hysteresis = <1000>;
5378 type 3985 type = "passive";
5379 }; 3986 };
5380 3987
5381 mdmss1_config 3988 mdmss1_config0: mdmss1-config0 {
5382 tempe 3989 temperature = <102000>;
5383 hyste 3990 hysteresis = <3000>;
5384 type 3991 type = "passive";
5385 }; 3992 };
5386 3993
5387 mdmss1_config 3994 mdmss1_config1: mdmss1-config1 {
5388 tempe 3995 temperature = <105000>;
5389 hyste 3996 hysteresis = <3000>;
5390 type 3997 type = "passive";
5391 }; 3998 };
5392 3999
5393 reset-mon-cfg 4000 reset-mon-cfg {
5394 tempe 4001 temperature = <115000>;
5395 hyste 4002 hysteresis = <5000>;
5396 type 4003 type = "passive";
5397 }; 4004 };
5398 }; 4005 };
5399 }; 4006 };
5400 4007
5401 modem2-thermal { 4008 modem2-thermal {
>> 4009 polling-delay-passive = <0>;
>> 4010 polling-delay = <0>;
5402 thermal-sensors = <&t 4011 thermal-sensors = <&tsens1 12>;
5403 4012
5404 trips { 4013 trips {
5405 thermal-engin 4014 thermal-engine-config {
5406 tempe 4015 temperature = <125000>;
5407 hyste 4016 hysteresis = <1000>;
5408 type 4017 type = "passive";
5409 }; 4018 };
5410 4019
5411 mdmss2_config 4020 mdmss2_config0: mdmss2-config0 {
5412 tempe 4021 temperature = <102000>;
5413 hyste 4022 hysteresis = <3000>;
5414 type 4023 type = "passive";
5415 }; 4024 };
5416 4025
5417 mdmss2_config 4026 mdmss2_config1: mdmss2-config1 {
5418 tempe 4027 temperature = <105000>;
5419 hyste 4028 hysteresis = <3000>;
5420 type 4029 type = "passive";
5421 }; 4030 };
5422 4031
5423 reset-mon-cfg 4032 reset-mon-cfg {
5424 tempe 4033 temperature = <115000>;
5425 hyste 4034 hysteresis = <5000>;
5426 type 4035 type = "passive";
5427 }; 4036 };
5428 }; 4037 };
5429 }; 4038 };
5430 4039
5431 modem3-thermal { 4040 modem3-thermal {
>> 4041 polling-delay-passive = <0>;
>> 4042 polling-delay = <0>;
5432 thermal-sensors = <&t 4043 thermal-sensors = <&tsens1 13>;
5433 4044
5434 trips { 4045 trips {
5435 thermal-engin 4046 thermal-engine-config {
5436 tempe 4047 temperature = <125000>;
5437 hyste 4048 hysteresis = <1000>;
5438 type 4049 type = "passive";
5439 }; 4050 };
5440 4051
5441 mdmss3_config 4052 mdmss3_config0: mdmss3-config0 {
5442 tempe 4053 temperature = <102000>;
5443 hyste 4054 hysteresis = <3000>;
5444 type 4055 type = "passive";
5445 }; 4056 };
5446 4057
5447 mdmss3_config 4058 mdmss3_config1: mdmss3-config1 {
5448 tempe 4059 temperature = <105000>;
5449 hyste 4060 hysteresis = <3000>;
5450 type 4061 type = "passive";
5451 }; 4062 };
5452 4063
5453 reset-mon-cfg 4064 reset-mon-cfg {
5454 tempe 4065 temperature = <115000>;
5455 hyste 4066 hysteresis = <5000>;
5456 type 4067 type = "passive";
5457 }; 4068 };
5458 }; 4069 };
5459 }; 4070 };
5460 4071
5461 camera0-thermal { 4072 camera0-thermal {
>> 4073 polling-delay-passive = <0>;
>> 4074 polling-delay = <0>;
5462 thermal-sensors = <&t 4075 thermal-sensors = <&tsens1 14>;
5463 4076
5464 trips { 4077 trips {
5465 thermal-engin 4078 thermal-engine-config {
5466 tempe 4079 temperature = <125000>;
5467 hyste 4080 hysteresis = <1000>;
5468 type 4081 type = "passive";
5469 }; 4082 };
5470 4083
5471 reset-mon-cfg 4084 reset-mon-cfg {
5472 tempe 4085 temperature = <115000>;
5473 hyste 4086 hysteresis = <5000>;
5474 type 4087 type = "passive";
5475 }; 4088 };
5476 }; 4089 };
5477 }; 4090 };
5478 4091
5479 camera1-thermal { 4092 camera1-thermal {
>> 4093 polling-delay-passive = <0>;
>> 4094 polling-delay = <0>;
5480 thermal-sensors = <&t 4095 thermal-sensors = <&tsens1 15>;
5481 4096
5482 trips { 4097 trips {
5483 thermal-engin 4098 thermal-engine-config {
5484 tempe 4099 temperature = <125000>;
5485 hyste 4100 hysteresis = <1000>;
5486 type 4101 type = "passive";
5487 }; 4102 };
5488 4103
5489 reset-mon-cfg 4104 reset-mon-cfg {
5490 tempe 4105 temperature = <115000>;
5491 hyste 4106 hysteresis = <5000>;
5492 type 4107 type = "passive";
5493 }; 4108 };
5494 }; 4109 };
5495 }; 4110 };
5496 }; 4111 };
5497 4112
5498 timer { 4113 timer {
5499 compatible = "arm,armv8-timer 4114 compatible = "arm,armv8-timer";
5500 interrupts = <GIC_PPI 13 (GIC 4115 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5501 <GIC_PPI 14 (GIC 4116 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5502 <GIC_PPI 11 (GIC 4117 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5503 <GIC_PPI 10 (GIC 4118 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
5504 clock-frequency = <19200000>; 4119 clock-frequency = <19200000>;
5505 }; 4120 };
5506 }; 4121 };
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