1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * Copyright (c) 2021, Linaro Limited 3 * Copyright (c) 2021, Linaro Limited
4 */ 4 */
5 5
6 #include <dt-bindings/interrupt-controller/arm 6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-sm8450.h> 7 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
8 #include <dt-bindings/clock/qcom,rpmh.h> 8 #include <dt-bindings/clock/qcom,rpmh.h>
9 #include <dt-bindings/clock/qcom,sm8450-camcc. 9 #include <dt-bindings/clock/qcom,sm8450-camcc.h>
10 #include <dt-bindings/clock/qcom,sm8450-dispcc 10 #include <dt-bindings/clock/qcom,sm8450-dispcc.h>
11 #include <dt-bindings/clock/qcom,sm8450-gpucc. 11 #include <dt-bindings/clock/qcom,sm8450-gpucc.h>
12 #include <dt-bindings/clock/qcom,sm8450-videoc 12 #include <dt-bindings/clock/qcom,sm8450-videocc.h>
13 #include <dt-bindings/dma/qcom-gpi.h> 13 #include <dt-bindings/dma/qcom-gpi.h>
14 #include <dt-bindings/firmware/qcom,scm.h> 14 #include <dt-bindings/firmware/qcom,scm.h>
15 #include <dt-bindings/gpio/gpio.h> 15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/mailbox/qcom-ipcc.h> 16 #include <dt-bindings/mailbox/qcom-ipcc.h>
17 #include <dt-bindings/phy/phy-qcom-qmp.h> 17 #include <dt-bindings/phy/phy-qcom-qmp.h>
18 #include <dt-bindings/power/qcom,rpmhpd.h> 18 #include <dt-bindings/power/qcom,rpmhpd.h>
19 #include <dt-bindings/power/qcom-rpmpd.h> 19 #include <dt-bindings/power/qcom-rpmpd.h>
20 #include <dt-bindings/interconnect/qcom,icc.h> 20 #include <dt-bindings/interconnect/qcom,icc.h>
21 #include <dt-bindings/interconnect/qcom,sm8450 21 #include <dt-bindings/interconnect/qcom,sm8450.h>
22 #include <dt-bindings/reset/qcom,sm8450-gpucc. 22 #include <dt-bindings/reset/qcom,sm8450-gpucc.h>
23 #include <dt-bindings/soc/qcom,gpr.h> 23 #include <dt-bindings/soc/qcom,gpr.h>
24 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 24 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
25 #include <dt-bindings/sound/qcom,q6dsp-lpass-p 25 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
26 #include <dt-bindings/thermal/thermal.h> 26 #include <dt-bindings/thermal/thermal.h>
27 27
28 / { 28 / {
29 interrupt-parent = <&intc>; 29 interrupt-parent = <&intc>;
30 30
31 #address-cells = <2>; 31 #address-cells = <2>;
32 #size-cells = <2>; 32 #size-cells = <2>;
33 33
34 chosen { }; 34 chosen { };
35 35
36 clocks { 36 clocks {
37 xo_board: xo-board { 37 xo_board: xo-board {
38 compatible = "fixed-cl 38 compatible = "fixed-clock";
39 #clock-cells = <0>; 39 #clock-cells = <0>;
40 clock-frequency = <768 40 clock-frequency = <76800000>;
41 }; 41 };
42 42
43 sleep_clk: sleep-clk { 43 sleep_clk: sleep-clk {
44 compatible = "fixed-cl 44 compatible = "fixed-clock";
45 #clock-cells = <0>; 45 #clock-cells = <0>;
46 clock-frequency = <320 46 clock-frequency = <32000>;
47 }; 47 };
48 }; 48 };
49 49
50 cpus { 50 cpus {
51 #address-cells = <2>; 51 #address-cells = <2>;
52 #size-cells = <0>; 52 #size-cells = <0>;
53 53
54 CPU0: cpu@0 { 54 CPU0: cpu@0 {
55 device_type = "cpu"; 55 device_type = "cpu";
56 compatible = "qcom,kry 56 compatible = "qcom,kryo780";
57 reg = <0x0 0x0>; 57 reg = <0x0 0x0>;
58 enable-method = "psci" 58 enable-method = "psci";
59 next-level-cache = <&L 59 next-level-cache = <&L2_0>;
60 power-domains = <&CPU_ 60 power-domains = <&CPU_PD0>;
61 power-domain-names = " 61 power-domain-names = "psci";
62 qcom,freq-domain = <&c 62 qcom,freq-domain = <&cpufreq_hw 0>;
63 #cooling-cells = <2>; 63 #cooling-cells = <2>;
64 clocks = <&cpufreq_hw 64 clocks = <&cpufreq_hw 0>;
65 L2_0: l2-cache { 65 L2_0: l2-cache {
66 compatible = " 66 compatible = "cache";
67 cache-level = 67 cache-level = <2>;
68 cache-unified; 68 cache-unified;
69 next-level-cac 69 next-level-cache = <&L3_0>;
70 L3_0: l3-cache 70 L3_0: l3-cache {
71 compat 71 compatible = "cache";
72 cache- 72 cache-level = <3>;
73 cache- 73 cache-unified;
74 }; 74 };
75 }; 75 };
76 }; 76 };
77 77
78 CPU1: cpu@100 { 78 CPU1: cpu@100 {
79 device_type = "cpu"; 79 device_type = "cpu";
80 compatible = "qcom,kry 80 compatible = "qcom,kryo780";
81 reg = <0x0 0x100>; 81 reg = <0x0 0x100>;
82 enable-method = "psci" 82 enable-method = "psci";
83 next-level-cache = <&L 83 next-level-cache = <&L2_100>;
84 power-domains = <&CPU_ 84 power-domains = <&CPU_PD1>;
85 power-domain-names = " 85 power-domain-names = "psci";
86 qcom,freq-domain = <&c 86 qcom,freq-domain = <&cpufreq_hw 0>;
87 #cooling-cells = <2>; 87 #cooling-cells = <2>;
88 clocks = <&cpufreq_hw 88 clocks = <&cpufreq_hw 0>;
89 L2_100: l2-cache { 89 L2_100: l2-cache {
90 compatible = " 90 compatible = "cache";
91 cache-level = 91 cache-level = <2>;
92 cache-unified; 92 cache-unified;
93 next-level-cac 93 next-level-cache = <&L3_0>;
94 }; 94 };
95 }; 95 };
96 96
97 CPU2: cpu@200 { 97 CPU2: cpu@200 {
98 device_type = "cpu"; 98 device_type = "cpu";
99 compatible = "qcom,kry 99 compatible = "qcom,kryo780";
100 reg = <0x0 0x200>; 100 reg = <0x0 0x200>;
101 enable-method = "psci" 101 enable-method = "psci";
102 next-level-cache = <&L 102 next-level-cache = <&L2_200>;
103 power-domains = <&CPU_ 103 power-domains = <&CPU_PD2>;
104 power-domain-names = " 104 power-domain-names = "psci";
105 qcom,freq-domain = <&c 105 qcom,freq-domain = <&cpufreq_hw 0>;
106 #cooling-cells = <2>; 106 #cooling-cells = <2>;
107 clocks = <&cpufreq_hw 107 clocks = <&cpufreq_hw 0>;
108 L2_200: l2-cache { 108 L2_200: l2-cache {
109 compatible = " 109 compatible = "cache";
110 cache-level = 110 cache-level = <2>;
111 cache-unified; 111 cache-unified;
112 next-level-cac 112 next-level-cache = <&L3_0>;
113 }; 113 };
114 }; 114 };
115 115
116 CPU3: cpu@300 { 116 CPU3: cpu@300 {
117 device_type = "cpu"; 117 device_type = "cpu";
118 compatible = "qcom,kry 118 compatible = "qcom,kryo780";
119 reg = <0x0 0x300>; 119 reg = <0x0 0x300>;
120 enable-method = "psci" 120 enable-method = "psci";
121 next-level-cache = <&L 121 next-level-cache = <&L2_300>;
122 power-domains = <&CPU_ 122 power-domains = <&CPU_PD3>;
123 power-domain-names = " 123 power-domain-names = "psci";
124 qcom,freq-domain = <&c 124 qcom,freq-domain = <&cpufreq_hw 0>;
125 #cooling-cells = <2>; 125 #cooling-cells = <2>;
126 clocks = <&cpufreq_hw 126 clocks = <&cpufreq_hw 0>;
127 L2_300: l2-cache { 127 L2_300: l2-cache {
128 compatible = " 128 compatible = "cache";
129 cache-level = 129 cache-level = <2>;
130 cache-unified; 130 cache-unified;
131 next-level-cac 131 next-level-cache = <&L3_0>;
132 }; 132 };
133 }; 133 };
134 134
135 CPU4: cpu@400 { 135 CPU4: cpu@400 {
136 device_type = "cpu"; 136 device_type = "cpu";
137 compatible = "qcom,kry 137 compatible = "qcom,kryo780";
138 reg = <0x0 0x400>; 138 reg = <0x0 0x400>;
139 enable-method = "psci" 139 enable-method = "psci";
140 next-level-cache = <&L 140 next-level-cache = <&L2_400>;
141 power-domains = <&CPU_ 141 power-domains = <&CPU_PD4>;
142 power-domain-names = " 142 power-domain-names = "psci";
143 qcom,freq-domain = <&c 143 qcom,freq-domain = <&cpufreq_hw 1>;
144 #cooling-cells = <2>; 144 #cooling-cells = <2>;
145 clocks = <&cpufreq_hw 145 clocks = <&cpufreq_hw 1>;
146 L2_400: l2-cache { 146 L2_400: l2-cache {
147 compatible = " 147 compatible = "cache";
148 cache-level = 148 cache-level = <2>;
149 cache-unified; 149 cache-unified;
150 next-level-cac 150 next-level-cache = <&L3_0>;
151 }; 151 };
152 }; 152 };
153 153
154 CPU5: cpu@500 { 154 CPU5: cpu@500 {
155 device_type = "cpu"; 155 device_type = "cpu";
156 compatible = "qcom,kry 156 compatible = "qcom,kryo780";
157 reg = <0x0 0x500>; 157 reg = <0x0 0x500>;
158 enable-method = "psci" 158 enable-method = "psci";
159 next-level-cache = <&L 159 next-level-cache = <&L2_500>;
160 power-domains = <&CPU_ 160 power-domains = <&CPU_PD5>;
161 power-domain-names = " 161 power-domain-names = "psci";
162 qcom,freq-domain = <&c 162 qcom,freq-domain = <&cpufreq_hw 1>;
163 #cooling-cells = <2>; 163 #cooling-cells = <2>;
164 clocks = <&cpufreq_hw 164 clocks = <&cpufreq_hw 1>;
165 L2_500: l2-cache { 165 L2_500: l2-cache {
166 compatible = " 166 compatible = "cache";
167 cache-level = 167 cache-level = <2>;
168 cache-unified; 168 cache-unified;
169 next-level-cac 169 next-level-cache = <&L3_0>;
170 }; 170 };
171 }; 171 };
172 172
173 CPU6: cpu@600 { 173 CPU6: cpu@600 {
174 device_type = "cpu"; 174 device_type = "cpu";
175 compatible = "qcom,kry 175 compatible = "qcom,kryo780";
176 reg = <0x0 0x600>; 176 reg = <0x0 0x600>;
177 enable-method = "psci" 177 enable-method = "psci";
178 next-level-cache = <&L 178 next-level-cache = <&L2_600>;
179 power-domains = <&CPU_ 179 power-domains = <&CPU_PD6>;
180 power-domain-names = " 180 power-domain-names = "psci";
181 qcom,freq-domain = <&c 181 qcom,freq-domain = <&cpufreq_hw 1>;
182 #cooling-cells = <2>; 182 #cooling-cells = <2>;
183 clocks = <&cpufreq_hw 183 clocks = <&cpufreq_hw 1>;
184 L2_600: l2-cache { 184 L2_600: l2-cache {
185 compatible = " 185 compatible = "cache";
186 cache-level = 186 cache-level = <2>;
187 cache-unified; 187 cache-unified;
188 next-level-cac 188 next-level-cache = <&L3_0>;
189 }; 189 };
190 }; 190 };
191 191
192 CPU7: cpu@700 { 192 CPU7: cpu@700 {
193 device_type = "cpu"; 193 device_type = "cpu";
194 compatible = "qcom,kry 194 compatible = "qcom,kryo780";
195 reg = <0x0 0x700>; 195 reg = <0x0 0x700>;
196 enable-method = "psci" 196 enable-method = "psci";
197 next-level-cache = <&L 197 next-level-cache = <&L2_700>;
198 power-domains = <&CPU_ 198 power-domains = <&CPU_PD7>;
199 power-domain-names = " 199 power-domain-names = "psci";
200 qcom,freq-domain = <&c 200 qcom,freq-domain = <&cpufreq_hw 2>;
201 #cooling-cells = <2>; 201 #cooling-cells = <2>;
202 clocks = <&cpufreq_hw 202 clocks = <&cpufreq_hw 2>;
203 L2_700: l2-cache { 203 L2_700: l2-cache {
204 compatible = " 204 compatible = "cache";
205 cache-level = 205 cache-level = <2>;
206 cache-unified; 206 cache-unified;
207 next-level-cac 207 next-level-cache = <&L3_0>;
208 }; 208 };
209 }; 209 };
210 210
211 cpu-map { 211 cpu-map {
212 cluster0 { 212 cluster0 {
213 core0 { 213 core0 {
214 cpu = 214 cpu = <&CPU0>;
215 }; 215 };
216 216
217 core1 { 217 core1 {
218 cpu = 218 cpu = <&CPU1>;
219 }; 219 };
220 220
221 core2 { 221 core2 {
222 cpu = 222 cpu = <&CPU2>;
223 }; 223 };
224 224
225 core3 { 225 core3 {
226 cpu = 226 cpu = <&CPU3>;
227 }; 227 };
228 228
229 core4 { 229 core4 {
230 cpu = 230 cpu = <&CPU4>;
231 }; 231 };
232 232
233 core5 { 233 core5 {
234 cpu = 234 cpu = <&CPU5>;
235 }; 235 };
236 236
237 core6 { 237 core6 {
238 cpu = 238 cpu = <&CPU6>;
239 }; 239 };
240 240
241 core7 { 241 core7 {
242 cpu = 242 cpu = <&CPU7>;
243 }; 243 };
244 }; 244 };
245 }; 245 };
246 246
247 idle-states { 247 idle-states {
248 entry-method = "psci"; 248 entry-method = "psci";
249 249
250 LITTLE_CPU_SLEEP_0: cp 250 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
251 compatible = " 251 compatible = "arm,idle-state";
252 idle-state-nam 252 idle-state-name = "silver-rail-power-collapse";
253 arm,psci-suspe 253 arm,psci-suspend-param = <0x40000004>;
254 entry-latency- 254 entry-latency-us = <800>;
255 exit-latency-u 255 exit-latency-us = <750>;
256 min-residency- 256 min-residency-us = <4090>;
257 local-timer-st 257 local-timer-stop;
258 }; 258 };
259 259
260 BIG_CPU_SLEEP_0: cpu-s 260 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
261 compatible = " 261 compatible = "arm,idle-state";
262 idle-state-nam 262 idle-state-name = "gold-rail-power-collapse";
263 arm,psci-suspe 263 arm,psci-suspend-param = <0x40000004>;
264 entry-latency- 264 entry-latency-us = <600>;
265 exit-latency-u 265 exit-latency-us = <1550>;
266 min-residency- 266 min-residency-us = <4791>;
267 local-timer-st 267 local-timer-stop;
268 }; 268 };
269 }; 269 };
270 270
271 domain-idle-states { 271 domain-idle-states {
272 CLUSTER_SLEEP_0: clust 272 CLUSTER_SLEEP_0: cluster-sleep-0 {
273 compatible = " 273 compatible = "domain-idle-state";
274 arm,psci-suspe 274 arm,psci-suspend-param = <0x41000044>;
275 entry-latency- 275 entry-latency-us = <1050>;
276 exit-latency-u 276 exit-latency-us = <2500>;
277 min-residency- 277 min-residency-us = <5309>;
278 }; 278 };
279 279
280 CLUSTER_SLEEP_1: clust 280 CLUSTER_SLEEP_1: cluster-sleep-1 {
281 compatible = " 281 compatible = "domain-idle-state";
282 arm,psci-suspe 282 arm,psci-suspend-param = <0x4100c344>;
283 entry-latency- 283 entry-latency-us = <2700>;
284 exit-latency-u 284 exit-latency-us = <3500>;
285 min-residency- 285 min-residency-us = <13959>;
286 }; 286 };
287 }; 287 };
288 }; 288 };
289 289
290 firmware { 290 firmware {
291 scm: scm { 291 scm: scm {
292 compatible = "qcom,scm 292 compatible = "qcom,scm-sm8450", "qcom,scm";
293 qcom,dload-mode = <&tc 293 qcom,dload-mode = <&tcsr 0x13000>;
294 interconnects = <&aggr 294 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
295 #reset-cells = <1>; 295 #reset-cells = <1>;
296 }; 296 };
297 }; 297 };
298 298
299 clk_virt: interconnect-0 { 299 clk_virt: interconnect-0 {
300 compatible = "qcom,sm8450-clk- 300 compatible = "qcom,sm8450-clk-virt";
301 #interconnect-cells = <2>; 301 #interconnect-cells = <2>;
302 qcom,bcm-voters = <&apps_bcm_v 302 qcom,bcm-voters = <&apps_bcm_voter>;
303 }; 303 };
304 304
305 mc_virt: interconnect-1 { 305 mc_virt: interconnect-1 {
306 compatible = "qcom,sm8450-mc-v 306 compatible = "qcom,sm8450-mc-virt";
307 #interconnect-cells = <2>; 307 #interconnect-cells = <2>;
308 qcom,bcm-voters = <&apps_bcm_v 308 qcom,bcm-voters = <&apps_bcm_voter>;
309 }; 309 };
310 310
311 memory@a0000000 { 311 memory@a0000000 {
312 device_type = "memory"; 312 device_type = "memory";
313 /* We expect the bootloader to 313 /* We expect the bootloader to fill in the size */
314 reg = <0x0 0xa0000000 0x0 0x0> 314 reg = <0x0 0xa0000000 0x0 0x0>;
315 }; 315 };
316 316
317 pmu { 317 pmu {
318 compatible = "arm,armv8-pmuv3" 318 compatible = "arm,armv8-pmuv3";
319 interrupts = <GIC_PPI 7 IRQ_TY 319 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
320 }; 320 };
321 321
322 psci { 322 psci {
323 compatible = "arm,psci-1.0"; 323 compatible = "arm,psci-1.0";
324 method = "smc"; 324 method = "smc";
325 325
326 CPU_PD0: power-domain-cpu0 { 326 CPU_PD0: power-domain-cpu0 {
327 #power-domain-cells = 327 #power-domain-cells = <0>;
328 power-domains = <&CLUS 328 power-domains = <&CLUSTER_PD>;
329 domain-idle-states = < 329 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
330 }; 330 };
331 331
332 CPU_PD1: power-domain-cpu1 { 332 CPU_PD1: power-domain-cpu1 {
333 #power-domain-cells = 333 #power-domain-cells = <0>;
334 power-domains = <&CLUS 334 power-domains = <&CLUSTER_PD>;
335 domain-idle-states = < 335 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
336 }; 336 };
337 337
338 CPU_PD2: power-domain-cpu2 { 338 CPU_PD2: power-domain-cpu2 {
339 #power-domain-cells = 339 #power-domain-cells = <0>;
340 power-domains = <&CLUS 340 power-domains = <&CLUSTER_PD>;
341 domain-idle-states = < 341 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
342 }; 342 };
343 343
344 CPU_PD3: power-domain-cpu3 { 344 CPU_PD3: power-domain-cpu3 {
345 #power-domain-cells = 345 #power-domain-cells = <0>;
346 power-domains = <&CLUS 346 power-domains = <&CLUSTER_PD>;
347 domain-idle-states = < 347 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
348 }; 348 };
349 349
350 CPU_PD4: power-domain-cpu4 { 350 CPU_PD4: power-domain-cpu4 {
351 #power-domain-cells = 351 #power-domain-cells = <0>;
352 power-domains = <&CLUS 352 power-domains = <&CLUSTER_PD>;
353 domain-idle-states = < 353 domain-idle-states = <&BIG_CPU_SLEEP_0>;
354 }; 354 };
355 355
356 CPU_PD5: power-domain-cpu5 { 356 CPU_PD5: power-domain-cpu5 {
357 #power-domain-cells = 357 #power-domain-cells = <0>;
358 power-domains = <&CLUS 358 power-domains = <&CLUSTER_PD>;
359 domain-idle-states = < 359 domain-idle-states = <&BIG_CPU_SLEEP_0>;
360 }; 360 };
361 361
362 CPU_PD6: power-domain-cpu6 { 362 CPU_PD6: power-domain-cpu6 {
363 #power-domain-cells = 363 #power-domain-cells = <0>;
364 power-domains = <&CLUS 364 power-domains = <&CLUSTER_PD>;
365 domain-idle-states = < 365 domain-idle-states = <&BIG_CPU_SLEEP_0>;
366 }; 366 };
367 367
368 CPU_PD7: power-domain-cpu7 { 368 CPU_PD7: power-domain-cpu7 {
369 #power-domain-cells = 369 #power-domain-cells = <0>;
370 power-domains = <&CLUS 370 power-domains = <&CLUSTER_PD>;
371 domain-idle-states = < 371 domain-idle-states = <&BIG_CPU_SLEEP_0>;
372 }; 372 };
373 373
374 CLUSTER_PD: power-domain-cpu-c 374 CLUSTER_PD: power-domain-cpu-cluster0 {
375 #power-domain-cells = 375 #power-domain-cells = <0>;
376 domain-idle-states = < 376 domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>;
377 }; 377 };
378 }; 378 };
379 379
380 qup_opp_table_100mhz: opp-table-qup { 380 qup_opp_table_100mhz: opp-table-qup {
381 compatible = "operating-points 381 compatible = "operating-points-v2";
382 382
383 opp-50000000 { 383 opp-50000000 {
384 opp-hz = /bits/ 64 <50 384 opp-hz = /bits/ 64 <50000000>;
385 required-opps = <&rpmh 385 required-opps = <&rpmhpd_opp_min_svs>;
386 }; 386 };
387 387
388 opp-75000000 { 388 opp-75000000 {
389 opp-hz = /bits/ 64 <75 389 opp-hz = /bits/ 64 <75000000>;
390 required-opps = <&rpmh 390 required-opps = <&rpmhpd_opp_low_svs>;
391 }; 391 };
392 392
393 opp-100000000 { 393 opp-100000000 {
394 opp-hz = /bits/ 64 <10 394 opp-hz = /bits/ 64 <100000000>;
395 required-opps = <&rpmh 395 required-opps = <&rpmhpd_opp_svs>;
396 }; 396 };
397 }; 397 };
398 398
399 reserved_memory: reserved-memory { 399 reserved_memory: reserved-memory {
400 #address-cells = <2>; 400 #address-cells = <2>;
401 #size-cells = <2>; 401 #size-cells = <2>;
402 ranges; 402 ranges;
403 403
404 hyp_mem: memory@80000000 { 404 hyp_mem: memory@80000000 {
405 reg = <0x0 0x80000000 405 reg = <0x0 0x80000000 0x0 0x600000>;
406 no-map; 406 no-map;
407 }; 407 };
408 408
409 xbl_dt_log_mem: memory@8060000 409 xbl_dt_log_mem: memory@80600000 {
410 reg = <0x0 0x80600000 410 reg = <0x0 0x80600000 0x0 0x40000>;
411 no-map; 411 no-map;
412 }; 412 };
413 413
414 xbl_ramdump_mem: memory@806400 414 xbl_ramdump_mem: memory@80640000 {
415 reg = <0x0 0x80640000 415 reg = <0x0 0x80640000 0x0 0x180000>;
416 no-map; 416 no-map;
417 }; 417 };
418 418
419 xbl_sc_mem: memory@807c0000 { 419 xbl_sc_mem: memory@807c0000 {
420 reg = <0x0 0x807c0000 420 reg = <0x0 0x807c0000 0x0 0x40000>;
421 no-map; 421 no-map;
422 }; 422 };
423 423
424 aop_image_mem: memory@80800000 424 aop_image_mem: memory@80800000 {
425 reg = <0x0 0x80800000 425 reg = <0x0 0x80800000 0x0 0x60000>;
426 no-map; 426 no-map;
427 }; 427 };
428 428
429 aop_cmd_db_mem: memory@8086000 429 aop_cmd_db_mem: memory@80860000 {
430 compatible = "qcom,cmd 430 compatible = "qcom,cmd-db";
431 reg = <0x0 0x80860000 431 reg = <0x0 0x80860000 0x0 0x20000>;
432 no-map; 432 no-map;
433 }; 433 };
434 434
435 aop_config_mem: memory@8088000 435 aop_config_mem: memory@80880000 {
436 reg = <0x0 0x80880000 436 reg = <0x0 0x80880000 0x0 0x20000>;
437 no-map; 437 no-map;
438 }; 438 };
439 439
440 tme_crash_dump_mem: memory@808 440 tme_crash_dump_mem: memory@808a0000 {
441 reg = <0x0 0x808a0000 441 reg = <0x0 0x808a0000 0x0 0x40000>;
442 no-map; 442 no-map;
443 }; 443 };
444 444
445 tme_log_mem: memory@808e0000 { 445 tme_log_mem: memory@808e0000 {
446 reg = <0x0 0x808e0000 446 reg = <0x0 0x808e0000 0x0 0x4000>;
447 no-map; 447 no-map;
448 }; 448 };
449 449
450 uefi_log_mem: memory@808e4000 450 uefi_log_mem: memory@808e4000 {
451 reg = <0x0 0x808e4000 451 reg = <0x0 0x808e4000 0x0 0x10000>;
452 no-map; 452 no-map;
453 }; 453 };
454 454
455 /* secdata region can be reuse 455 /* secdata region can be reused by apps */
456 smem: memory@80900000 { 456 smem: memory@80900000 {
457 compatible = "qcom,sme 457 compatible = "qcom,smem";
458 reg = <0x0 0x80900000 458 reg = <0x0 0x80900000 0x0 0x200000>;
459 hwlocks = <&tcsr_mutex 459 hwlocks = <&tcsr_mutex 3>;
460 no-map; 460 no-map;
461 }; 461 };
462 462
463 cpucp_fw_mem: memory@80b00000 463 cpucp_fw_mem: memory@80b00000 {
464 reg = <0x0 0x80b00000 464 reg = <0x0 0x80b00000 0x0 0x100000>;
465 no-map; 465 no-map;
466 }; 466 };
467 467
468 cdsp_secure_heap: memory@80c00 468 cdsp_secure_heap: memory@80c00000 {
469 reg = <0x0 0x80c00000 469 reg = <0x0 0x80c00000 0x0 0x4600000>;
470 no-map; 470 no-map;
471 }; 471 };
472 472
473 video_mem: memory@85700000 { 473 video_mem: memory@85700000 {
474 reg = <0x0 0x85700000 474 reg = <0x0 0x85700000 0x0 0x700000>;
475 no-map; 475 no-map;
476 }; 476 };
477 477
478 adsp_mem: memory@85e00000 { 478 adsp_mem: memory@85e00000 {
479 reg = <0x0 0x85e00000 479 reg = <0x0 0x85e00000 0x0 0x2100000>;
480 no-map; 480 no-map;
481 }; 481 };
482 482
483 slpi_mem: memory@88000000 { 483 slpi_mem: memory@88000000 {
484 reg = <0x0 0x88000000 484 reg = <0x0 0x88000000 0x0 0x1900000>;
485 no-map; 485 no-map;
486 }; 486 };
487 487
488 cdsp_mem: memory@89900000 { 488 cdsp_mem: memory@89900000 {
489 reg = <0x0 0x89900000 489 reg = <0x0 0x89900000 0x0 0x2000000>;
490 no-map; 490 no-map;
491 }; 491 };
492 492
493 ipa_fw_mem: memory@8b900000 { 493 ipa_fw_mem: memory@8b900000 {
494 reg = <0x0 0x8b900000 494 reg = <0x0 0x8b900000 0x0 0x10000>;
495 no-map; 495 no-map;
496 }; 496 };
497 497
498 ipa_gsi_mem: memory@8b910000 { 498 ipa_gsi_mem: memory@8b910000 {
499 reg = <0x0 0x8b910000 499 reg = <0x0 0x8b910000 0x0 0xa000>;
500 no-map; 500 no-map;
501 }; 501 };
502 502
503 gpu_micro_code_mem: memory@8b9 503 gpu_micro_code_mem: memory@8b91a000 {
504 reg = <0x0 0x8b91a000 504 reg = <0x0 0x8b91a000 0x0 0x2000>;
505 no-map; 505 no-map;
506 }; 506 };
507 507
508 spss_region_mem: memory@8ba000 508 spss_region_mem: memory@8ba00000 {
509 reg = <0x0 0x8ba00000 509 reg = <0x0 0x8ba00000 0x0 0x180000>;
510 no-map; 510 no-map;
511 }; 511 };
512 512
513 /* First part of the "SPU secu 513 /* First part of the "SPU secure shared memory" region */
514 spu_tz_shared_mem: memory@8bb8 514 spu_tz_shared_mem: memory@8bb80000 {
515 reg = <0x0 0x8bb80000 515 reg = <0x0 0x8bb80000 0x0 0x60000>;
516 no-map; 516 no-map;
517 }; 517 };
518 518
519 /* Second part of the "SPU sec 519 /* Second part of the "SPU secure shared memory" region */
520 spu_modem_shared_mem: memory@8 520 spu_modem_shared_mem: memory@8bbe0000 {
521 reg = <0x0 0x8bbe0000 521 reg = <0x0 0x8bbe0000 0x0 0x20000>;
522 no-map; 522 no-map;
523 }; 523 };
524 524
525 mpss_mem: memory@8bc00000 { 525 mpss_mem: memory@8bc00000 {
526 reg = <0x0 0x8bc00000 526 reg = <0x0 0x8bc00000 0x0 0x13200000>;
527 no-map; 527 no-map;
528 }; 528 };
529 529
530 cvp_mem: memory@9ee00000 { 530 cvp_mem: memory@9ee00000 {
531 reg = <0x0 0x9ee00000 531 reg = <0x0 0x9ee00000 0x0 0x700000>;
532 no-map; 532 no-map;
533 }; 533 };
534 534
535 camera_mem: memory@9f500000 { 535 camera_mem: memory@9f500000 {
536 reg = <0x0 0x9f500000 536 reg = <0x0 0x9f500000 0x0 0x800000>;
537 no-map; 537 no-map;
538 }; 538 };
539 539
540 rmtfs_mem: memory@9fd00000 { 540 rmtfs_mem: memory@9fd00000 {
541 compatible = "qcom,rmt 541 compatible = "qcom,rmtfs-mem";
542 reg = <0x0 0x9fd00000 542 reg = <0x0 0x9fd00000 0x0 0x280000>;
543 no-map; 543 no-map;
544 544
545 qcom,client-id = <1>; 545 qcom,client-id = <1>;
546 qcom,vmid = <QCOM_SCM_ 546 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
547 }; 547 };
548 548
549 xbl_sc_mem2: memory@a6e00000 { 549 xbl_sc_mem2: memory@a6e00000 {
550 reg = <0x0 0xa6e00000 550 reg = <0x0 0xa6e00000 0x0 0x40000>;
551 no-map; 551 no-map;
552 }; 552 };
553 553
554 global_sync_mem: memory@a6f000 554 global_sync_mem: memory@a6f00000 {
555 reg = <0x0 0xa6f00000 555 reg = <0x0 0xa6f00000 0x0 0x100000>;
556 no-map; 556 no-map;
557 }; 557 };
558 558
559 /* uefi region can be reused b 559 /* uefi region can be reused by APPS */
560 560
561 /* Linux kernel image is loade 561 /* Linux kernel image is loaded at 0xa0000000 */
562 562
563 oem_vm_mem: memory@bb000000 { 563 oem_vm_mem: memory@bb000000 {
564 reg = <0x0 0xbb000000 564 reg = <0x0 0xbb000000 0x0 0x5000000>;
565 no-map; 565 no-map;
566 }; 566 };
567 567
568 mte_mem: memory@c0000000 { 568 mte_mem: memory@c0000000 {
569 reg = <0x0 0xc0000000 569 reg = <0x0 0xc0000000 0x0 0x20000000>;
570 no-map; 570 no-map;
571 }; 571 };
572 572
573 qheebsp_reserved_mem: memory@e 573 qheebsp_reserved_mem: memory@e0000000 {
574 reg = <0x0 0xe0000000 574 reg = <0x0 0xe0000000 0x0 0x600000>;
575 no-map; 575 no-map;
576 }; 576 };
577 577
578 cpusys_vm_mem: memory@e0600000 578 cpusys_vm_mem: memory@e0600000 {
579 reg = <0x0 0xe0600000 579 reg = <0x0 0xe0600000 0x0 0x400000>;
580 no-map; 580 no-map;
581 }; 581 };
582 582
583 hyp_reserved_mem: memory@e0a00 583 hyp_reserved_mem: memory@e0a00000 {
584 reg = <0x0 0xe0a00000 584 reg = <0x0 0xe0a00000 0x0 0x100000>;
585 no-map; 585 no-map;
586 }; 586 };
587 587
588 trust_ui_vm_mem: memory@e0b000 588 trust_ui_vm_mem: memory@e0b00000 {
589 reg = <0x0 0xe0b00000 589 reg = <0x0 0xe0b00000 0x0 0x4af3000>;
590 no-map; 590 no-map;
591 }; 591 };
592 592
593 trust_ui_vm_qrtr: memory@e55f3 593 trust_ui_vm_qrtr: memory@e55f3000 {
594 reg = <0x0 0xe55f3000 594 reg = <0x0 0xe55f3000 0x0 0x9000>;
595 no-map; 595 no-map;
596 }; 596 };
597 597
598 trust_ui_vm_vblk0_ring: memory 598 trust_ui_vm_vblk0_ring: memory@e55fc000 {
599 reg = <0x0 0xe55fc000 599 reg = <0x0 0xe55fc000 0x0 0x4000>;
600 no-map; 600 no-map;
601 }; 601 };
602 602
603 trust_ui_vm_swiotlb: memory@e5 603 trust_ui_vm_swiotlb: memory@e5600000 {
604 reg = <0x0 0xe5600000 604 reg = <0x0 0xe5600000 0x0 0x100000>;
605 no-map; 605 no-map;
606 }; 606 };
607 607
608 tz_stat_mem: memory@e8800000 { 608 tz_stat_mem: memory@e8800000 {
609 reg = <0x0 0xe8800000 609 reg = <0x0 0xe8800000 0x0 0x100000>;
610 no-map; 610 no-map;
611 }; 611 };
612 612
613 tags_mem: memory@e8900000 { 613 tags_mem: memory@e8900000 {
614 reg = <0x0 0xe8900000 614 reg = <0x0 0xe8900000 0x0 0x1200000>;
615 no-map; 615 no-map;
616 }; 616 };
617 617
618 qtee_mem: memory@e9b00000 { 618 qtee_mem: memory@e9b00000 {
619 reg = <0x0 0xe9b00000 619 reg = <0x0 0xe9b00000 0x0 0x500000>;
620 no-map; 620 no-map;
621 }; 621 };
622 622
623 trusted_apps_mem: memory@ea000 623 trusted_apps_mem: memory@ea000000 {
624 reg = <0x0 0xea000000 624 reg = <0x0 0xea000000 0x0 0x3900000>;
625 no-map; 625 no-map;
626 }; 626 };
627 627
628 trusted_apps_ext_mem: memory@e 628 trusted_apps_ext_mem: memory@ed900000 {
629 reg = <0x0 0xed900000 629 reg = <0x0 0xed900000 0x0 0x3b00000>;
630 no-map; 630 no-map;
631 }; 631 };
632 }; 632 };
633 633
634 smp2p-adsp { 634 smp2p-adsp {
635 compatible = "qcom,smp2p"; 635 compatible = "qcom,smp2p";
636 qcom,smem = <443>, <429>; 636 qcom,smem = <443>, <429>;
637 interrupts-extended = <&ipcc I 637 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
638 I 638 IPCC_MPROC_SIGNAL_SMP2P
639 I 639 IRQ_TYPE_EDGE_RISING>;
640 mboxes = <&ipcc IPCC_CLIENT_LP 640 mboxes = <&ipcc IPCC_CLIENT_LPASS
641 IPCC_MPROC_SIG 641 IPCC_MPROC_SIGNAL_SMP2P>;
642 642
643 qcom,local-pid = <0>; 643 qcom,local-pid = <0>;
644 qcom,remote-pid = <2>; 644 qcom,remote-pid = <2>;
645 645
646 smp2p_adsp_out: master-kernel 646 smp2p_adsp_out: master-kernel {
647 qcom,entry-name = "mas 647 qcom,entry-name = "master-kernel";
648 #qcom,smem-state-cells 648 #qcom,smem-state-cells = <1>;
649 }; 649 };
650 650
651 smp2p_adsp_in: slave-kernel { 651 smp2p_adsp_in: slave-kernel {
652 qcom,entry-name = "sla 652 qcom,entry-name = "slave-kernel";
653 interrupt-controller; 653 interrupt-controller;
654 #interrupt-cells = <2> 654 #interrupt-cells = <2>;
655 }; 655 };
656 }; 656 };
657 657
658 smp2p-cdsp { 658 smp2p-cdsp {
659 compatible = "qcom,smp2p"; 659 compatible = "qcom,smp2p";
660 qcom,smem = <94>, <432>; 660 qcom,smem = <94>, <432>;
661 interrupts-extended = <&ipcc I 661 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
662 I 662 IPCC_MPROC_SIGNAL_SMP2P
663 I 663 IRQ_TYPE_EDGE_RISING>;
664 mboxes = <&ipcc IPCC_CLIENT_CD 664 mboxes = <&ipcc IPCC_CLIENT_CDSP
665 IPCC_MPROC_SIG 665 IPCC_MPROC_SIGNAL_SMP2P>;
666 666
667 qcom,local-pid = <0>; 667 qcom,local-pid = <0>;
668 qcom,remote-pid = <5>; 668 qcom,remote-pid = <5>;
669 669
670 smp2p_cdsp_out: master-kernel 670 smp2p_cdsp_out: master-kernel {
671 qcom,entry-name = "mas 671 qcom,entry-name = "master-kernel";
672 #qcom,smem-state-cells 672 #qcom,smem-state-cells = <1>;
673 }; 673 };
674 674
675 smp2p_cdsp_in: slave-kernel { 675 smp2p_cdsp_in: slave-kernel {
676 qcom,entry-name = "sla 676 qcom,entry-name = "slave-kernel";
677 interrupt-controller; 677 interrupt-controller;
678 #interrupt-cells = <2> 678 #interrupt-cells = <2>;
679 }; 679 };
680 }; 680 };
681 681
682 smp2p-modem { 682 smp2p-modem {
683 compatible = "qcom,smp2p"; 683 compatible = "qcom,smp2p";
684 qcom,smem = <435>, <428>; 684 qcom,smem = <435>, <428>;
685 interrupts-extended = <&ipcc I 685 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
686 I 686 IPCC_MPROC_SIGNAL_SMP2P
687 I 687 IRQ_TYPE_EDGE_RISING>;
688 mboxes = <&ipcc IPCC_CLIENT_MP 688 mboxes = <&ipcc IPCC_CLIENT_MPSS
689 IPCC_MPROC_SIG 689 IPCC_MPROC_SIGNAL_SMP2P>;
690 690
691 qcom,local-pid = <0>; 691 qcom,local-pid = <0>;
692 qcom,remote-pid = <1>; 692 qcom,remote-pid = <1>;
693 693
694 smp2p_modem_out: master-kernel 694 smp2p_modem_out: master-kernel {
695 qcom,entry-name = "mas 695 qcom,entry-name = "master-kernel";
696 #qcom,smem-state-cells 696 #qcom,smem-state-cells = <1>;
697 }; 697 };
698 698
699 smp2p_modem_in: slave-kernel { 699 smp2p_modem_in: slave-kernel {
700 qcom,entry-name = "sla 700 qcom,entry-name = "slave-kernel";
701 interrupt-controller; 701 interrupt-controller;
702 #interrupt-cells = <2> 702 #interrupt-cells = <2>;
703 }; 703 };
704 704
705 ipa_smp2p_out: ipa-ap-to-modem 705 ipa_smp2p_out: ipa-ap-to-modem {
706 qcom,entry-name = "ipa 706 qcom,entry-name = "ipa";
707 #qcom,smem-state-cells 707 #qcom,smem-state-cells = <1>;
708 }; 708 };
709 709
710 ipa_smp2p_in: ipa-modem-to-ap 710 ipa_smp2p_in: ipa-modem-to-ap {
711 qcom,entry-name = "ipa 711 qcom,entry-name = "ipa";
712 interrupt-controller; 712 interrupt-controller;
713 #interrupt-cells = <2> 713 #interrupt-cells = <2>;
714 }; 714 };
715 }; 715 };
716 716
717 smp2p-slpi { 717 smp2p-slpi {
718 compatible = "qcom,smp2p"; 718 compatible = "qcom,smp2p";
719 qcom,smem = <481>, <430>; 719 qcom,smem = <481>, <430>;
720 interrupts-extended = <&ipcc I 720 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
721 I 721 IPCC_MPROC_SIGNAL_SMP2P
722 I 722 IRQ_TYPE_EDGE_RISING>;
723 mboxes = <&ipcc IPCC_CLIENT_SL 723 mboxes = <&ipcc IPCC_CLIENT_SLPI
724 IPCC_MPROC_SIG 724 IPCC_MPROC_SIGNAL_SMP2P>;
725 725
726 qcom,local-pid = <0>; 726 qcom,local-pid = <0>;
727 qcom,remote-pid = <3>; 727 qcom,remote-pid = <3>;
728 728
729 smp2p_slpi_out: master-kernel 729 smp2p_slpi_out: master-kernel {
730 qcom,entry-name = "mas 730 qcom,entry-name = "master-kernel";
731 #qcom,smem-state-cells 731 #qcom,smem-state-cells = <1>;
732 }; 732 };
733 733
734 smp2p_slpi_in: slave-kernel { 734 smp2p_slpi_in: slave-kernel {
735 qcom,entry-name = "sla 735 qcom,entry-name = "slave-kernel";
736 interrupt-controller; 736 interrupt-controller;
737 #interrupt-cells = <2> 737 #interrupt-cells = <2>;
738 }; 738 };
739 }; 739 };
740 740
741 soc: soc@0 { 741 soc: soc@0 {
742 #address-cells = <2>; 742 #address-cells = <2>;
743 #size-cells = <2>; 743 #size-cells = <2>;
744 ranges = <0 0 0 0 0x10 0>; 744 ranges = <0 0 0 0 0x10 0>;
745 dma-ranges = <0 0 0 0 0x10 0>; 745 dma-ranges = <0 0 0 0 0x10 0>;
746 compatible = "simple-bus"; 746 compatible = "simple-bus";
747 747
748 gcc: clock-controller@100000 { 748 gcc: clock-controller@100000 {
749 compatible = "qcom,gcc 749 compatible = "qcom,gcc-sm8450";
750 reg = <0x0 0x00100000 750 reg = <0x0 0x00100000 0x0 0x1f4200>;
751 #clock-cells = <1>; 751 #clock-cells = <1>;
752 #reset-cells = <1>; 752 #reset-cells = <1>;
753 #power-domain-cells = 753 #power-domain-cells = <1>;
754 clocks = <&rpmhcc RPMH 754 clocks = <&rpmhcc RPMH_CXO_CLK>,
755 <&sleep_clk>, 755 <&sleep_clk>,
756 <&pcie0_phy>, 756 <&pcie0_phy>,
757 <&pcie1_phy Q !! 757 <&pcie1_phy>,
758 <&pcie1_phy Q !! 758 <0>,
759 <&ufs_mem_phy 759 <&ufs_mem_phy 0>,
760 <&ufs_mem_phy 760 <&ufs_mem_phy 1>,
761 <&ufs_mem_phy 761 <&ufs_mem_phy 2>,
762 <&usb_1_qmpph 762 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
763 clock-names = "bi_tcxo 763 clock-names = "bi_tcxo",
764 "sleep_c 764 "sleep_clk",
765 "pcie_0_ 765 "pcie_0_pipe_clk",
766 "pcie_1_ 766 "pcie_1_pipe_clk",
767 "pcie_1_ 767 "pcie_1_phy_aux_clk",
768 "ufs_phy 768 "ufs_phy_rx_symbol_0_clk",
769 "ufs_phy 769 "ufs_phy_rx_symbol_1_clk",
770 "ufs_phy 770 "ufs_phy_tx_symbol_0_clk",
771 "usb3_ph 771 "usb3_phy_wrapper_gcc_usb30_pipe_clk";
772 }; 772 };
773 773
774 gpi_dma2: dma-controller@80000 774 gpi_dma2: dma-controller@800000 {
775 compatible = "qcom,sm8 775 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
776 #dma-cells = <3>; 776 #dma-cells = <3>;
777 reg = <0 0x00800000 0 777 reg = <0 0x00800000 0 0x60000>;
778 interrupts = <GIC_SPI 778 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
779 <GIC_SPI 779 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
780 <GIC_SPI 780 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
781 <GIC_SPI 781 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
782 <GIC_SPI 782 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
783 <GIC_SPI 783 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
784 <GIC_SPI 784 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
785 <GIC_SPI 785 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
786 <GIC_SPI 786 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
787 <GIC_SPI 787 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
788 <GIC_SPI 788 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
789 <GIC_SPI 789 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
790 dma-channels = <12>; 790 dma-channels = <12>;
791 dma-channel-mask = <0x 791 dma-channel-mask = <0x7e>;
792 iommus = <&apps_smmu 0 792 iommus = <&apps_smmu 0x496 0x0>;
793 status = "disabled"; 793 status = "disabled";
794 }; 794 };
795 795
796 qupv3_id_2: geniqup@8c0000 { 796 qupv3_id_2: geniqup@8c0000 {
797 compatible = "qcom,gen 797 compatible = "qcom,geni-se-qup";
798 reg = <0x0 0x008c0000 798 reg = <0x0 0x008c0000 0x0 0x2000>;
799 clock-names = "m-ahb", 799 clock-names = "m-ahb", "s-ahb";
800 clocks = <&gcc GCC_QUP 800 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
801 <&gcc GCC_QUP 801 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
802 iommus = <&apps_smmu 0 802 iommus = <&apps_smmu 0x483 0x0>;
803 #address-cells = <2>; 803 #address-cells = <2>;
804 #size-cells = <2>; 804 #size-cells = <2>;
805 ranges; 805 ranges;
806 status = "disabled"; 806 status = "disabled";
807 807
808 i2c15: i2c@880000 { 808 i2c15: i2c@880000 {
809 compatible = " 809 compatible = "qcom,geni-i2c";
810 reg = <0x0 0x0 810 reg = <0x0 0x00880000 0x0 0x4000>;
811 clock-names = 811 clock-names = "se";
812 clocks = <&gcc 812 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
813 pinctrl-names 813 pinctrl-names = "default";
814 pinctrl-0 = <& 814 pinctrl-0 = <&qup_i2c15_data_clk>;
815 interrupts = < 815 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
816 #address-cells 816 #address-cells = <1>;
817 #size-cells = 817 #size-cells = <0>;
818 interconnects 818 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
819 819 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
820 820 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
821 interconnect-n 821 interconnect-names = "qup-core", "qup-config", "qup-memory";
822 dmas = <&gpi_d 822 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
823 <&gpi_d 823 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
824 dma-names = "t 824 dma-names = "tx", "rx";
825 status = "disa 825 status = "disabled";
826 }; 826 };
827 827
828 spi15: spi@880000 { 828 spi15: spi@880000 {
829 compatible = " 829 compatible = "qcom,geni-spi";
830 reg = <0x0 0x0 830 reg = <0x0 0x00880000 0x0 0x4000>;
831 clock-names = 831 clock-names = "se";
832 clocks = <&gcc 832 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
833 interrupts = < 833 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
834 pinctrl-names 834 pinctrl-names = "default";
835 pinctrl-0 = <& 835 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
836 interconnects 836 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
837 837 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
838 interconnect-n 838 interconnect-names = "qup-core", "qup-config";
839 dmas = <&gpi_d 839 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
840 <&gpi_d 840 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
841 dma-names = "t 841 dma-names = "tx", "rx";
842 #address-cells 842 #address-cells = <1>;
843 #size-cells = 843 #size-cells = <0>;
844 status = "disa 844 status = "disabled";
845 }; 845 };
846 846
847 i2c16: i2c@884000 { 847 i2c16: i2c@884000 {
848 compatible = " 848 compatible = "qcom,geni-i2c";
849 reg = <0x0 0x0 849 reg = <0x0 0x00884000 0x0 0x4000>;
850 clock-names = 850 clock-names = "se";
851 clocks = <&gcc 851 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
852 pinctrl-names 852 pinctrl-names = "default";
853 pinctrl-0 = <& 853 pinctrl-0 = <&qup_i2c16_data_clk>;
854 interrupts = < 854 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
855 #address-cells 855 #address-cells = <1>;
856 #size-cells = 856 #size-cells = <0>;
857 interconnects 857 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
858 858 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
859 859 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
860 interconnect-n 860 interconnect-names = "qup-core", "qup-config", "qup-memory";
861 dmas = <&gpi_d 861 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
862 <&gpi_d 862 <&gpi_dma2 1 1 QCOM_GPI_I2C>;
863 dma-names = "t 863 dma-names = "tx", "rx";
864 status = "disa 864 status = "disabled";
865 }; 865 };
866 866
867 spi16: spi@884000 { 867 spi16: spi@884000 {
868 compatible = " 868 compatible = "qcom,geni-spi";
869 reg = <0x0 0x0 869 reg = <0x0 0x00884000 0x0 0x4000>;
870 clock-names = 870 clock-names = "se";
871 clocks = <&gcc 871 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
872 interrupts = < 872 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
873 pinctrl-names 873 pinctrl-names = "default";
874 pinctrl-0 = <& 874 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>;
875 interconnects 875 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
876 876 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
877 interconnect-n 877 interconnect-names = "qup-core", "qup-config";
878 dmas = <&gpi_d 878 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
879 <&gpi_d 879 <&gpi_dma2 1 1 QCOM_GPI_SPI>;
880 dma-names = "t 880 dma-names = "tx", "rx";
881 #address-cells 881 #address-cells = <1>;
882 #size-cells = 882 #size-cells = <0>;
883 status = "disa 883 status = "disabled";
884 }; 884 };
885 885
886 i2c17: i2c@888000 { 886 i2c17: i2c@888000 {
887 compatible = " 887 compatible = "qcom,geni-i2c";
888 reg = <0x0 0x0 888 reg = <0x0 0x00888000 0x0 0x4000>;
889 clock-names = 889 clock-names = "se";
890 clocks = <&gcc 890 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
891 pinctrl-names 891 pinctrl-names = "default";
892 pinctrl-0 = <& 892 pinctrl-0 = <&qup_i2c17_data_clk>;
893 interrupts = < 893 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
894 #address-cells 894 #address-cells = <1>;
895 #size-cells = 895 #size-cells = <0>;
896 interconnects 896 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
897 897 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
898 898 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
899 interconnect-n 899 interconnect-names = "qup-core", "qup-config", "qup-memory";
900 dmas = <&gpi_d 900 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
901 <&gpi_d 901 <&gpi_dma2 1 2 QCOM_GPI_I2C>;
902 dma-names = "t 902 dma-names = "tx", "rx";
903 status = "disa 903 status = "disabled";
904 }; 904 };
905 905
906 spi17: spi@888000 { 906 spi17: spi@888000 {
907 compatible = " 907 compatible = "qcom,geni-spi";
908 reg = <0x0 0x0 908 reg = <0x0 0x00888000 0x0 0x4000>;
909 clock-names = 909 clock-names = "se";
910 clocks = <&gcc 910 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
911 interrupts = < 911 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
912 pinctrl-names 912 pinctrl-names = "default";
913 pinctrl-0 = <& 913 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>;
914 interconnects 914 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
915 915 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
916 interconnect-n 916 interconnect-names = "qup-core", "qup-config";
917 dmas = <&gpi_d 917 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
918 <&gpi_d 918 <&gpi_dma2 1 2 QCOM_GPI_SPI>;
919 dma-names = "t 919 dma-names = "tx", "rx";
920 #address-cells 920 #address-cells = <1>;
921 #size-cells = 921 #size-cells = <0>;
922 status = "disa 922 status = "disabled";
923 }; 923 };
924 924
925 i2c18: i2c@88c000 { 925 i2c18: i2c@88c000 {
926 compatible = " 926 compatible = "qcom,geni-i2c";
927 reg = <0x0 0x0 927 reg = <0x0 0x0088c000 0x0 0x4000>;
928 clock-names = 928 clock-names = "se";
929 clocks = <&gcc 929 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
930 pinctrl-names 930 pinctrl-names = "default";
931 pinctrl-0 = <& 931 pinctrl-0 = <&qup_i2c18_data_clk>;
932 interrupts = < 932 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
933 #address-cells 933 #address-cells = <1>;
934 #size-cells = 934 #size-cells = <0>;
935 interconnects 935 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
936 936 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
937 937 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
938 interconnect-n 938 interconnect-names = "qup-core", "qup-config", "qup-memory";
939 dmas = <&gpi_d 939 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
940 <&gpi_d 940 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
941 dma-names = "t 941 dma-names = "tx", "rx";
942 status = "disa 942 status = "disabled";
943 }; 943 };
944 944
945 spi18: spi@88c000 { 945 spi18: spi@88c000 {
946 compatible = " 946 compatible = "qcom,geni-spi";
947 reg = <0 0x008 947 reg = <0 0x0088c000 0 0x4000>;
948 clock-names = 948 clock-names = "se";
949 clocks = <&gcc 949 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
950 interrupts = < 950 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
951 pinctrl-names 951 pinctrl-names = "default";
952 pinctrl-0 = <& 952 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>;
953 interconnects 953 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
954 954 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
955 interconnect-n 955 interconnect-names = "qup-core", "qup-config";
956 dmas = <&gpi_d 956 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
957 <&gpi_d 957 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
958 dma-names = "t 958 dma-names = "tx", "rx";
959 #address-cells 959 #address-cells = <1>;
960 #size-cells = 960 #size-cells = <0>;
961 status = "disa 961 status = "disabled";
962 }; 962 };
963 963
964 i2c19: i2c@890000 { 964 i2c19: i2c@890000 {
965 compatible = " 965 compatible = "qcom,geni-i2c";
966 reg = <0x0 0x0 966 reg = <0x0 0x00890000 0x0 0x4000>;
967 clock-names = 967 clock-names = "se";
968 clocks = <&gcc 968 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
969 pinctrl-names 969 pinctrl-names = "default";
970 pinctrl-0 = <& 970 pinctrl-0 = <&qup_i2c19_data_clk>;
971 interrupts = < 971 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
972 #address-cells 972 #address-cells = <1>;
973 #size-cells = 973 #size-cells = <0>;
974 interconnects 974 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
975 975 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
976 976 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
977 interconnect-n 977 interconnect-names = "qup-core", "qup-config", "qup-memory";
978 dmas = <&gpi_d 978 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
979 <&gpi_d 979 <&gpi_dma2 1 4 QCOM_GPI_I2C>;
980 dma-names = "t 980 dma-names = "tx", "rx";
981 status = "disa 981 status = "disabled";
982 }; 982 };
983 983
984 spi19: spi@890000 { 984 spi19: spi@890000 {
985 compatible = " 985 compatible = "qcom,geni-spi";
986 reg = <0 0x008 986 reg = <0 0x00890000 0 0x4000>;
987 clock-names = 987 clock-names = "se";
988 clocks = <&gcc 988 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
989 interrupts = < 989 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
990 pinctrl-names 990 pinctrl-names = "default";
991 pinctrl-0 = <& 991 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>;
992 interconnects 992 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
993 993 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
994 interconnect-n 994 interconnect-names = "qup-core", "qup-config";
995 dmas = <&gpi_d 995 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
996 <&gpi_d 996 <&gpi_dma2 1 4 QCOM_GPI_I2C>;
997 dma-names = "t 997 dma-names = "tx", "rx";
998 #address-cells 998 #address-cells = <1>;
999 #size-cells = 999 #size-cells = <0>;
1000 status = "dis 1000 status = "disabled";
1001 }; 1001 };
1002 1002
1003 i2c20: i2c@894000 { 1003 i2c20: i2c@894000 {
1004 compatible = 1004 compatible = "qcom,geni-i2c";
1005 reg = <0x0 0x 1005 reg = <0x0 0x00894000 0x0 0x4000>;
1006 clock-names = 1006 clock-names = "se";
1007 clocks = <&gc 1007 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1008 pinctrl-names 1008 pinctrl-names = "default";
1009 pinctrl-0 = < 1009 pinctrl-0 = <&qup_i2c20_data_clk>;
1010 interrupts = 1010 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1011 #address-cell 1011 #address-cells = <1>;
1012 #size-cells = 1012 #size-cells = <0>;
1013 interconnects 1013 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1014 1014 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1015 1015 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1016 interconnect- 1016 interconnect-names = "qup-core", "qup-config", "qup-memory";
1017 dmas = <&gpi_ 1017 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1018 <&gpi_ 1018 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1019 dma-names = " 1019 dma-names = "tx", "rx";
1020 status = "dis 1020 status = "disabled";
1021 }; 1021 };
1022 1022
1023 uart20: serial@894000 1023 uart20: serial@894000 {
1024 compatible = 1024 compatible = "qcom,geni-uart";
1025 reg = <0 0x00 1025 reg = <0 0x00894000 0 0x4000>;
1026 clock-names = 1026 clock-names = "se";
1027 clocks = <&gc 1027 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1028 pinctrl-names 1028 pinctrl-names = "default";
1029 pinctrl-0 = < 1029 pinctrl-0 = <&qup_uart20_default>;
1030 interrupts = 1030 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1031 interconnects 1031 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1032 1032 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1033 1033 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1034 1034 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
1035 interconnect- 1035 interconnect-names = "qup-core",
1036 1036 "qup-config";
1037 status = "dis 1037 status = "disabled";
1038 }; 1038 };
1039 1039
1040 spi20: spi@894000 { 1040 spi20: spi@894000 {
1041 compatible = 1041 compatible = "qcom,geni-spi";
1042 reg = <0 0x00 1042 reg = <0 0x00894000 0 0x4000>;
1043 clock-names = 1043 clock-names = "se";
1044 clocks = <&gc 1044 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1045 interrupts = 1045 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1046 pinctrl-names 1046 pinctrl-names = "default";
1047 pinctrl-0 = < 1047 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>;
1048 interconnects 1048 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1049 1049 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
1050 interconnect- 1050 interconnect-names = "qup-core", "qup-config";
1051 dmas = <&gpi_ 1051 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1052 <&gpi_ 1052 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1053 dma-names = " 1053 dma-names = "tx", "rx";
1054 #address-cell 1054 #address-cells = <1>;
1055 #size-cells = 1055 #size-cells = <0>;
1056 status = "dis 1056 status = "disabled";
1057 }; 1057 };
1058 1058
1059 i2c21: i2c@898000 { 1059 i2c21: i2c@898000 {
1060 compatible = 1060 compatible = "qcom,geni-i2c";
1061 reg = <0x0 0x 1061 reg = <0x0 0x00898000 0x0 0x4000>;
1062 clock-names = 1062 clock-names = "se";
1063 clocks = <&gc 1063 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1064 pinctrl-names 1064 pinctrl-names = "default";
1065 pinctrl-0 = < 1065 pinctrl-0 = <&qup_i2c21_data_clk>;
1066 interrupts = 1066 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
1067 #address-cell 1067 #address-cells = <1>;
1068 #size-cells = 1068 #size-cells = <0>;
1069 interconnects 1069 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1070 1070 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1071 1071 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1072 interconnect- 1072 interconnect-names = "qup-core", "qup-config", "qup-memory";
1073 dmas = <&gpi_ 1073 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>,
1074 <&gpi_ 1074 <&gpi_dma2 1 6 QCOM_GPI_I2C>;
1075 dma-names = " 1075 dma-names = "tx", "rx";
1076 status = "dis 1076 status = "disabled";
1077 }; 1077 };
1078 1078
1079 spi21: spi@898000 { 1079 spi21: spi@898000 {
1080 compatible = 1080 compatible = "qcom,geni-spi";
1081 reg = <0 0x00 1081 reg = <0 0x00898000 0 0x4000>;
1082 clock-names = 1082 clock-names = "se";
1083 clocks = <&gc 1083 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1084 interrupts = 1084 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
1085 pinctrl-names 1085 pinctrl-names = "default";
1086 pinctrl-0 = < 1086 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>;
1087 interconnects 1087 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1088 1088 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
1089 interconnect- 1089 interconnect-names = "qup-core", "qup-config";
1090 dmas = <&gpi_ 1090 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>,
1091 <&gpi_ 1091 <&gpi_dma2 1 6 QCOM_GPI_SPI>;
1092 dma-names = " 1092 dma-names = "tx", "rx";
1093 #address-cell 1093 #address-cells = <1>;
1094 #size-cells = 1094 #size-cells = <0>;
1095 status = "dis 1095 status = "disabled";
1096 }; 1096 };
1097 }; 1097 };
1098 1098
1099 gpi_dma0: dma-controller@9000 1099 gpi_dma0: dma-controller@900000 {
1100 compatible = "qcom,sm 1100 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
1101 #dma-cells = <3>; 1101 #dma-cells = <3>;
1102 reg = <0 0x00900000 0 1102 reg = <0 0x00900000 0 0x60000>;
1103 interrupts = <GIC_SPI 1103 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
1104 <GIC_SPI 1104 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
1105 <GIC_SPI 1105 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
1106 <GIC_SPI 1106 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
1107 <GIC_SPI 1107 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
1108 <GIC_SPI 1108 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
1109 <GIC_SPI 1109 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
1110 <GIC_SPI 1110 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
1111 <GIC_SPI 1111 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
1112 <GIC_SPI 1112 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
1113 <GIC_SPI 1113 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
1114 <GIC_SPI 1114 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
1115 dma-channels = <12>; 1115 dma-channels = <12>;
1116 dma-channel-mask = <0 1116 dma-channel-mask = <0x7e>;
1117 iommus = <&apps_smmu 1117 iommus = <&apps_smmu 0x5b6 0x0>;
1118 status = "disabled"; 1118 status = "disabled";
1119 }; 1119 };
1120 1120
1121 qupv3_id_0: geniqup@9c0000 { 1121 qupv3_id_0: geniqup@9c0000 {
1122 compatible = "qcom,ge 1122 compatible = "qcom,geni-se-qup";
1123 reg = <0x0 0x009c0000 1123 reg = <0x0 0x009c0000 0x0 0x2000>;
1124 clock-names = "m-ahb" 1124 clock-names = "m-ahb", "s-ahb";
1125 clocks = <&gcc GCC_QU 1125 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1126 <&gcc GCC_QU 1126 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1127 iommus = <&apps_smmu 1127 iommus = <&apps_smmu 0x5a3 0x0>;
1128 interconnects = <&clk 1128 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>;
1129 interconnect-names = 1129 interconnect-names = "qup-core";
1130 #address-cells = <2>; 1130 #address-cells = <2>;
1131 #size-cells = <2>; 1131 #size-cells = <2>;
1132 ranges; 1132 ranges;
1133 status = "disabled"; 1133 status = "disabled";
1134 1134
1135 i2c0: i2c@980000 { 1135 i2c0: i2c@980000 {
1136 compatible = 1136 compatible = "qcom,geni-i2c";
1137 reg = <0x0 0x 1137 reg = <0x0 0x00980000 0x0 0x4000>;
1138 clock-names = 1138 clock-names = "se";
1139 clocks = <&gc 1139 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1140 pinctrl-names 1140 pinctrl-names = "default";
1141 pinctrl-0 = < 1141 pinctrl-0 = <&qup_i2c0_data_clk>;
1142 interrupts = 1142 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1143 #address-cell 1143 #address-cells = <1>;
1144 #size-cells = 1144 #size-cells = <0>;
1145 interconnects 1145 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1146 1146 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1147 1147 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1148 interconnect- 1148 interconnect-names = "qup-core", "qup-config", "qup-memory";
1149 dmas = <&gpi_ 1149 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1150 <&gpi_ 1150 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1151 dma-names = " 1151 dma-names = "tx", "rx";
1152 status = "dis 1152 status = "disabled";
1153 }; 1153 };
1154 1154
1155 spi0: spi@980000 { 1155 spi0: spi@980000 {
1156 compatible = 1156 compatible = "qcom,geni-spi";
1157 reg = <0x0 0x 1157 reg = <0x0 0x00980000 0x0 0x4000>;
1158 clock-names = 1158 clock-names = "se";
1159 clocks = <&gc 1159 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1160 interrupts = 1160 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1161 pinctrl-names 1161 pinctrl-names = "default";
1162 pinctrl-0 = < 1162 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1163 power-domains 1163 power-domains = <&rpmhpd RPMHPD_CX>;
1164 operating-poi 1164 operating-points-v2 = <&qup_opp_table_100mhz>;
1165 interconnects 1165 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1166 1166 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1167 1167 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1168 interconnect- 1168 interconnect-names = "qup-core", "qup-config", "qup-memory";
1169 dmas = <&gpi_ 1169 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1170 <&gpi_ 1170 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1171 dma-names = " 1171 dma-names = "tx", "rx";
1172 #address-cell 1172 #address-cells = <1>;
1173 #size-cells = 1173 #size-cells = <0>;
1174 status = "dis 1174 status = "disabled";
1175 }; 1175 };
1176 1176
1177 i2c1: i2c@984000 { 1177 i2c1: i2c@984000 {
1178 compatible = 1178 compatible = "qcom,geni-i2c";
1179 reg = <0x0 0x 1179 reg = <0x0 0x00984000 0x0 0x4000>;
1180 clock-names = 1180 clock-names = "se";
1181 clocks = <&gc 1181 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1182 pinctrl-names 1182 pinctrl-names = "default";
1183 pinctrl-0 = < 1183 pinctrl-0 = <&qup_i2c1_data_clk>;
1184 interrupts = 1184 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1185 #address-cell 1185 #address-cells = <1>;
1186 #size-cells = 1186 #size-cells = <0>;
1187 interconnects 1187 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1188 1188 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1189 1189 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1190 interconnect- 1190 interconnect-names = "qup-core", "qup-config", "qup-memory";
1191 dmas = <&gpi_ 1191 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1192 <&gpi_ 1192 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1193 dma-names = " 1193 dma-names = "tx", "rx";
1194 status = "dis 1194 status = "disabled";
1195 }; 1195 };
1196 1196
1197 spi1: spi@984000 { 1197 spi1: spi@984000 {
1198 compatible = 1198 compatible = "qcom,geni-spi";
1199 reg = <0x0 0x 1199 reg = <0x0 0x00984000 0x0 0x4000>;
1200 clock-names = 1200 clock-names = "se";
1201 clocks = <&gc 1201 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1202 interrupts = 1202 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1203 pinctrl-names 1203 pinctrl-names = "default";
1204 pinctrl-0 = < 1204 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1205 interconnects 1205 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1206 1206 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1207 1207 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1208 interconnect- 1208 interconnect-names = "qup-core", "qup-config", "qup-memory";
1209 dmas = <&gpi_ 1209 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1210 <&gpi_ 1210 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1211 dma-names = " 1211 dma-names = "tx", "rx";
1212 #address-cell 1212 #address-cells = <1>;
1213 #size-cells = 1213 #size-cells = <0>;
1214 status = "dis 1214 status = "disabled";
1215 }; 1215 };
1216 1216
1217 i2c2: i2c@988000 { 1217 i2c2: i2c@988000 {
1218 compatible = 1218 compatible = "qcom,geni-i2c";
1219 reg = <0x0 0x 1219 reg = <0x0 0x00988000 0x0 0x4000>;
1220 clock-names = 1220 clock-names = "se";
1221 clocks = <&gc 1221 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1222 pinctrl-names 1222 pinctrl-names = "default";
1223 pinctrl-0 = < 1223 pinctrl-0 = <&qup_i2c2_data_clk>;
1224 interrupts = 1224 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1225 #address-cell 1225 #address-cells = <1>;
1226 #size-cells = 1226 #size-cells = <0>;
1227 interconnects 1227 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1228 1228 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1229 1229 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1230 interconnect- 1230 interconnect-names = "qup-core", "qup-config", "qup-memory";
1231 dmas = <&gpi_ 1231 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1232 <&gpi_ 1232 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1233 dma-names = " 1233 dma-names = "tx", "rx";
1234 status = "dis 1234 status = "disabled";
1235 }; 1235 };
1236 1236
1237 spi2: spi@988000 { 1237 spi2: spi@988000 {
1238 compatible = 1238 compatible = "qcom,geni-spi";
1239 reg = <0x0 0x 1239 reg = <0x0 0x00988000 0x0 0x4000>;
1240 clock-names = 1240 clock-names = "se";
1241 clocks = <&gc 1241 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1242 interrupts = 1242 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1243 pinctrl-names 1243 pinctrl-names = "default";
1244 pinctrl-0 = < 1244 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1245 interconnects 1245 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1246 1246 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1247 1247 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1248 interconnect- 1248 interconnect-names = "qup-core", "qup-config", "qup-memory";
1249 dmas = <&gpi_ 1249 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1250 <&gpi_ 1250 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1251 dma-names = " 1251 dma-names = "tx", "rx";
1252 #address-cell 1252 #address-cells = <1>;
1253 #size-cells = 1253 #size-cells = <0>;
1254 status = "dis 1254 status = "disabled";
1255 }; 1255 };
1256 1256
1257 1257
1258 i2c3: i2c@98c000 { 1258 i2c3: i2c@98c000 {
1259 compatible = 1259 compatible = "qcom,geni-i2c";
1260 reg = <0x0 0x 1260 reg = <0x0 0x0098c000 0x0 0x4000>;
1261 clock-names = 1261 clock-names = "se";
1262 clocks = <&gc 1262 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1263 pinctrl-names 1263 pinctrl-names = "default";
1264 pinctrl-0 = < 1264 pinctrl-0 = <&qup_i2c3_data_clk>;
1265 interrupts = 1265 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1266 #address-cell 1266 #address-cells = <1>;
1267 #size-cells = 1267 #size-cells = <0>;
1268 interconnects 1268 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1269 1269 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1270 1270 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1271 interconnect- 1271 interconnect-names = "qup-core", "qup-config", "qup-memory";
1272 dmas = <&gpi_ 1272 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1273 <&gpi_ 1273 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1274 dma-names = " 1274 dma-names = "tx", "rx";
1275 status = "dis 1275 status = "disabled";
1276 }; 1276 };
1277 1277
1278 spi3: spi@98c000 { 1278 spi3: spi@98c000 {
1279 compatible = 1279 compatible = "qcom,geni-spi";
1280 reg = <0x0 0x 1280 reg = <0x0 0x0098c000 0x0 0x4000>;
1281 clock-names = 1281 clock-names = "se";
1282 clocks = <&gc 1282 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1283 interrupts = 1283 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1284 pinctrl-names 1284 pinctrl-names = "default";
1285 pinctrl-0 = < 1285 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1286 interconnects 1286 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1287 1287 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1288 1288 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1289 interconnect- 1289 interconnect-names = "qup-core", "qup-config", "qup-memory";
1290 dmas = <&gpi_ 1290 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1291 <&gpi_ 1291 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1292 dma-names = " 1292 dma-names = "tx", "rx";
1293 #address-cell 1293 #address-cells = <1>;
1294 #size-cells = 1294 #size-cells = <0>;
1295 status = "dis 1295 status = "disabled";
1296 }; 1296 };
1297 1297
1298 i2c4: i2c@990000 { 1298 i2c4: i2c@990000 {
1299 compatible = 1299 compatible = "qcom,geni-i2c";
1300 reg = <0x0 0x 1300 reg = <0x0 0x00990000 0x0 0x4000>;
1301 clock-names = 1301 clock-names = "se";
1302 clocks = <&gc 1302 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1303 pinctrl-names 1303 pinctrl-names = "default";
1304 pinctrl-0 = < 1304 pinctrl-0 = <&qup_i2c4_data_clk>;
1305 interrupts = 1305 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1306 #address-cell 1306 #address-cells = <1>;
1307 #size-cells = 1307 #size-cells = <0>;
1308 interconnects 1308 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1309 1309 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1310 1310 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1311 interconnect- 1311 interconnect-names = "qup-core", "qup-config", "qup-memory";
1312 dmas = <&gpi_ 1312 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1313 <&gpi_ 1313 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1314 dma-names = " 1314 dma-names = "tx", "rx";
1315 status = "dis 1315 status = "disabled";
1316 }; 1316 };
1317 1317
1318 spi4: spi@990000 { 1318 spi4: spi@990000 {
1319 compatible = 1319 compatible = "qcom,geni-spi";
1320 reg = <0x0 0x 1320 reg = <0x0 0x00990000 0x0 0x4000>;
1321 clock-names = 1321 clock-names = "se";
1322 clocks = <&gc 1322 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1323 interrupts = 1323 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1324 pinctrl-names 1324 pinctrl-names = "default";
1325 pinctrl-0 = < 1325 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1326 power-domains 1326 power-domains = <&rpmhpd RPMHPD_CX>;
1327 operating-poi 1327 operating-points-v2 = <&qup_opp_table_100mhz>;
1328 interconnects 1328 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1329 1329 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1330 1330 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1331 interconnect- 1331 interconnect-names = "qup-core", "qup-config", "qup-memory";
1332 dmas = <&gpi_ 1332 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1333 <&gpi_ 1333 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1334 dma-names = " 1334 dma-names = "tx", "rx";
1335 #address-cell 1335 #address-cells = <1>;
1336 #size-cells = 1336 #size-cells = <0>;
1337 status = "dis 1337 status = "disabled";
1338 }; 1338 };
1339 1339
1340 i2c5: i2c@994000 { 1340 i2c5: i2c@994000 {
1341 compatible = 1341 compatible = "qcom,geni-i2c";
1342 reg = <0x0 0x 1342 reg = <0x0 0x00994000 0x0 0x4000>;
1343 clock-names = 1343 clock-names = "se";
1344 clocks = <&gc 1344 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1345 pinctrl-names 1345 pinctrl-names = "default";
1346 pinctrl-0 = < 1346 pinctrl-0 = <&qup_i2c5_data_clk>;
1347 interrupts = 1347 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1348 #address-cell 1348 #address-cells = <1>;
1349 #size-cells = 1349 #size-cells = <0>;
1350 interconnects 1350 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1351 1351 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1352 1352 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1353 interconnect- 1353 interconnect-names = "qup-core", "qup-config", "qup-memory";
1354 dmas = <&gpi_ 1354 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1355 <&gpi_ 1355 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1356 dma-names = " 1356 dma-names = "tx", "rx";
1357 status = "dis 1357 status = "disabled";
1358 }; 1358 };
1359 1359
1360 spi5: spi@994000 { 1360 spi5: spi@994000 {
1361 compatible = 1361 compatible = "qcom,geni-spi";
1362 reg = <0x0 0x 1362 reg = <0x0 0x00994000 0x0 0x4000>;
1363 clock-names = 1363 clock-names = "se";
1364 clocks = <&gc 1364 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1365 interrupts = 1365 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1366 pinctrl-names 1366 pinctrl-names = "default";
1367 pinctrl-0 = < 1367 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1368 interconnects 1368 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1369 1369 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1370 1370 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1371 interconnect- 1371 interconnect-names = "qup-core", "qup-config", "qup-memory";
1372 dmas = <&gpi_ 1372 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1373 <&gpi_ 1373 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1374 dma-names = " 1374 dma-names = "tx", "rx";
1375 #address-cell 1375 #address-cells = <1>;
1376 #size-cells = 1376 #size-cells = <0>;
1377 status = "dis 1377 status = "disabled";
1378 }; 1378 };
1379 1379
1380 1380
1381 i2c6: i2c@998000 { 1381 i2c6: i2c@998000 {
1382 compatible = 1382 compatible = "qcom,geni-i2c";
1383 reg = <0x0 0x 1383 reg = <0x0 0x00998000 0x0 0x4000>;
1384 clock-names = 1384 clock-names = "se";
1385 clocks = <&gc 1385 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1386 pinctrl-names 1386 pinctrl-names = "default";
1387 pinctrl-0 = < 1387 pinctrl-0 = <&qup_i2c6_data_clk>;
1388 interrupts = 1388 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1389 #address-cell 1389 #address-cells = <1>;
1390 #size-cells = 1390 #size-cells = <0>;
1391 interconnects 1391 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1392 1392 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1393 1393 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1394 interconnect- 1394 interconnect-names = "qup-core", "qup-config", "qup-memory";
1395 dmas = <&gpi_ 1395 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1396 <&gpi_ 1396 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1397 dma-names = " 1397 dma-names = "tx", "rx";
1398 status = "dis 1398 status = "disabled";
1399 }; 1399 };
1400 1400
1401 spi6: spi@998000 { 1401 spi6: spi@998000 {
1402 compatible = 1402 compatible = "qcom,geni-spi";
1403 reg = <0x0 0x 1403 reg = <0x0 0x00998000 0x0 0x4000>;
1404 clock-names = 1404 clock-names = "se";
1405 clocks = <&gc 1405 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1406 interrupts = 1406 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1407 pinctrl-names 1407 pinctrl-names = "default";
1408 pinctrl-0 = < 1408 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1409 interconnects 1409 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1410 1410 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1411 1411 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1412 interconnect- 1412 interconnect-names = "qup-core", "qup-config", "qup-memory";
1413 dmas = <&gpi_ 1413 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1414 <&gpi_ 1414 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1415 dma-names = " 1415 dma-names = "tx", "rx";
1416 #address-cell 1416 #address-cells = <1>;
1417 #size-cells = 1417 #size-cells = <0>;
1418 status = "dis 1418 status = "disabled";
1419 }; 1419 };
1420 1420
1421 uart7: serial@99c000 1421 uart7: serial@99c000 {
1422 compatible = 1422 compatible = "qcom,geni-debug-uart";
1423 reg = <0 0x00 1423 reg = <0 0x0099c000 0 0x4000>;
1424 clock-names = 1424 clock-names = "se";
1425 clocks = <&gc 1425 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1426 pinctrl-names 1426 pinctrl-names = "default";
1427 pinctrl-0 = < 1427 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>;
1428 interrupts = 1428 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1429 interconnects 1429 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1430 1430 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1431 1431 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1432 1432 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
1433 interconnect- 1433 interconnect-names = "qup-core",
1434 1434 "qup-config";
1435 status = "dis 1435 status = "disabled";
1436 }; 1436 };
1437 }; 1437 };
1438 1438
1439 gpi_dma1: dma-controller@a000 1439 gpi_dma1: dma-controller@a00000 {
1440 compatible = "qcom,sm 1440 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
1441 #dma-cells = <3>; 1441 #dma-cells = <3>;
1442 reg = <0 0x00a00000 0 1442 reg = <0 0x00a00000 0 0x60000>;
1443 interrupts = <GIC_SPI 1443 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1444 <GIC_SPI 1444 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1445 <GIC_SPI 1445 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1446 <GIC_SPI 1446 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1447 <GIC_SPI 1447 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1448 <GIC_SPI 1448 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1449 <GIC_SPI 1449 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1450 <GIC_SPI 1450 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1451 <GIC_SPI 1451 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1452 <GIC_SPI 1452 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1453 <GIC_SPI 1453 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1454 <GIC_SPI 1454 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
1455 dma-channels = <12>; 1455 dma-channels = <12>;
1456 dma-channel-mask = <0 1456 dma-channel-mask = <0x7e>;
1457 iommus = <&apps_smmu 1457 iommus = <&apps_smmu 0x56 0x0>;
1458 status = "disabled"; 1458 status = "disabled";
1459 }; 1459 };
1460 1460
1461 qupv3_id_1: geniqup@ac0000 { 1461 qupv3_id_1: geniqup@ac0000 {
1462 compatible = "qcom,ge 1462 compatible = "qcom,geni-se-qup";
1463 reg = <0x0 0x00ac0000 1463 reg = <0x0 0x00ac0000 0x0 0x6000>;
1464 clock-names = "m-ahb" 1464 clock-names = "m-ahb", "s-ahb";
1465 clocks = <&gcc GCC_QU 1465 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1466 <&gcc GCC_QU 1466 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1467 iommus = <&apps_smmu 1467 iommus = <&apps_smmu 0x43 0x0>;
1468 interconnects = <&clk 1468 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>;
1469 interconnect-names = 1469 interconnect-names = "qup-core";
1470 #address-cells = <2>; 1470 #address-cells = <2>;
1471 #size-cells = <2>; 1471 #size-cells = <2>;
1472 ranges; 1472 ranges;
1473 status = "disabled"; 1473 status = "disabled";
1474 1474
1475 i2c8: i2c@a80000 { 1475 i2c8: i2c@a80000 {
1476 compatible = 1476 compatible = "qcom,geni-i2c";
1477 reg = <0x0 0x 1477 reg = <0x0 0x00a80000 0x0 0x4000>;
1478 clock-names = 1478 clock-names = "se";
1479 clocks = <&gc 1479 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1480 pinctrl-names 1480 pinctrl-names = "default";
1481 pinctrl-0 = < 1481 pinctrl-0 = <&qup_i2c8_data_clk>;
1482 interrupts = 1482 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1483 #address-cell 1483 #address-cells = <1>;
1484 #size-cells = 1484 #size-cells = <0>;
1485 interconnects 1485 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1486 1486 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1487 1487 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1488 interconnect- 1488 interconnect-names = "qup-core", "qup-config", "qup-memory";
1489 dmas = <&gpi_ 1489 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1490 <&gpi_ 1490 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1491 dma-names = " 1491 dma-names = "tx", "rx";
1492 status = "dis 1492 status = "disabled";
1493 }; 1493 };
1494 1494
1495 spi8: spi@a80000 { 1495 spi8: spi@a80000 {
1496 compatible = 1496 compatible = "qcom,geni-spi";
1497 reg = <0x0 0x 1497 reg = <0x0 0x00a80000 0x0 0x4000>;
1498 clock-names = 1498 clock-names = "se";
1499 clocks = <&gc 1499 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1500 interrupts = 1500 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1501 pinctrl-names 1501 pinctrl-names = "default";
1502 pinctrl-0 = < 1502 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1503 interconnects 1503 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1504 1504 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1505 1505 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1506 interconnect- 1506 interconnect-names = "qup-core", "qup-config", "qup-memory";
1507 dmas = <&gpi_ 1507 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1508 <&gpi_ 1508 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1509 dma-names = " 1509 dma-names = "tx", "rx";
1510 #address-cell 1510 #address-cells = <1>;
1511 #size-cells = 1511 #size-cells = <0>;
1512 status = "dis 1512 status = "disabled";
1513 }; 1513 };
1514 1514
1515 i2c9: i2c@a84000 { 1515 i2c9: i2c@a84000 {
1516 compatible = 1516 compatible = "qcom,geni-i2c";
1517 reg = <0x0 0x 1517 reg = <0x0 0x00a84000 0x0 0x4000>;
1518 clock-names = 1518 clock-names = "se";
1519 clocks = <&gc 1519 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1520 pinctrl-names 1520 pinctrl-names = "default";
1521 pinctrl-0 = < 1521 pinctrl-0 = <&qup_i2c9_data_clk>;
1522 interrupts = 1522 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1523 #address-cell 1523 #address-cells = <1>;
1524 #size-cells = 1524 #size-cells = <0>;
1525 interconnects 1525 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1526 1526 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1527 1527 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1528 interconnect- 1528 interconnect-names = "qup-core", "qup-config", "qup-memory";
1529 dmas = <&gpi_ 1529 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1530 <&gpi_ 1530 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1531 dma-names = " 1531 dma-names = "tx", "rx";
1532 status = "dis 1532 status = "disabled";
1533 }; 1533 };
1534 1534
1535 spi9: spi@a84000 { 1535 spi9: spi@a84000 {
1536 compatible = 1536 compatible = "qcom,geni-spi";
1537 reg = <0x0 0x 1537 reg = <0x0 0x00a84000 0x0 0x4000>;
1538 clock-names = 1538 clock-names = "se";
1539 clocks = <&gc 1539 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1540 interrupts = 1540 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1541 pinctrl-names 1541 pinctrl-names = "default";
1542 pinctrl-0 = < 1542 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1543 interconnects 1543 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1544 1544 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1545 1545 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1546 interconnect- 1546 interconnect-names = "qup-core", "qup-config", "qup-memory";
1547 dmas = <&gpi_ 1547 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1548 <&gpi_ 1548 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1549 dma-names = " 1549 dma-names = "tx", "rx";
1550 #address-cell 1550 #address-cells = <1>;
1551 #size-cells = 1551 #size-cells = <0>;
1552 status = "dis 1552 status = "disabled";
1553 }; 1553 };
1554 1554
1555 i2c10: i2c@a88000 { 1555 i2c10: i2c@a88000 {
1556 compatible = 1556 compatible = "qcom,geni-i2c";
1557 reg = <0x0 0x 1557 reg = <0x0 0x00a88000 0x0 0x4000>;
1558 clock-names = 1558 clock-names = "se";
1559 clocks = <&gc 1559 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1560 pinctrl-names 1560 pinctrl-names = "default";
1561 pinctrl-0 = < 1561 pinctrl-0 = <&qup_i2c10_data_clk>;
1562 interrupts = 1562 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1563 #address-cell 1563 #address-cells = <1>;
1564 #size-cells = 1564 #size-cells = <0>;
1565 interconnects 1565 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1566 1566 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1567 1567 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1568 interconnect- 1568 interconnect-names = "qup-core", "qup-config", "qup-memory";
1569 dmas = <&gpi_ 1569 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1570 <&gpi_ 1570 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1571 dma-names = " 1571 dma-names = "tx", "rx";
1572 status = "dis 1572 status = "disabled";
1573 }; 1573 };
1574 1574
1575 spi10: spi@a88000 { 1575 spi10: spi@a88000 {
1576 compatible = 1576 compatible = "qcom,geni-spi";
1577 reg = <0x0 0x 1577 reg = <0x0 0x00a88000 0x0 0x4000>;
1578 clock-names = 1578 clock-names = "se";
1579 clocks = <&gc 1579 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1580 interrupts = 1580 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1581 pinctrl-names 1581 pinctrl-names = "default";
1582 pinctrl-0 = < 1582 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1583 interconnects 1583 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1584 1584 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1585 1585 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1586 interconnect- 1586 interconnect-names = "qup-core", "qup-config", "qup-memory";
1587 dmas = <&gpi_ 1587 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1588 <&gpi_ 1588 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1589 dma-names = " 1589 dma-names = "tx", "rx";
1590 #address-cell 1590 #address-cells = <1>;
1591 #size-cells = 1591 #size-cells = <0>;
1592 status = "dis 1592 status = "disabled";
1593 }; 1593 };
1594 1594
1595 i2c11: i2c@a8c000 { 1595 i2c11: i2c@a8c000 {
1596 compatible = 1596 compatible = "qcom,geni-i2c";
1597 reg = <0x0 0x 1597 reg = <0x0 0x00a8c000 0x0 0x4000>;
1598 clock-names = 1598 clock-names = "se";
1599 clocks = <&gc 1599 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1600 pinctrl-names 1600 pinctrl-names = "default";
1601 pinctrl-0 = < 1601 pinctrl-0 = <&qup_i2c11_data_clk>;
1602 interrupts = 1602 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1603 #address-cell 1603 #address-cells = <1>;
1604 #size-cells = 1604 #size-cells = <0>;
1605 interconnects 1605 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1606 1606 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1607 1607 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1608 interconnect- 1608 interconnect-names = "qup-core", "qup-config", "qup-memory";
1609 dmas = <&gpi_ 1609 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1610 <&gpi_ 1610 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1611 dma-names = " 1611 dma-names = "tx", "rx";
1612 status = "dis 1612 status = "disabled";
1613 }; 1613 };
1614 1614
1615 spi11: spi@a8c000 { 1615 spi11: spi@a8c000 {
1616 compatible = 1616 compatible = "qcom,geni-spi";
1617 reg = <0x0 0x 1617 reg = <0x0 0x00a8c000 0x0 0x4000>;
1618 clock-names = 1618 clock-names = "se";
1619 clocks = <&gc 1619 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1620 interrupts = 1620 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1621 pinctrl-names 1621 pinctrl-names = "default";
1622 pinctrl-0 = < 1622 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1623 interconnects 1623 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1624 1624 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1625 1625 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1626 interconnect- 1626 interconnect-names = "qup-core", "qup-config", "qup-memory";
1627 dmas = <&gpi_ 1627 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1628 <&gpi_ 1628 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1629 dma-names = " 1629 dma-names = "tx", "rx";
1630 #address-cell 1630 #address-cells = <1>;
1631 #size-cells = 1631 #size-cells = <0>;
1632 status = "dis 1632 status = "disabled";
1633 }; 1633 };
1634 1634
1635 i2c12: i2c@a90000 { 1635 i2c12: i2c@a90000 {
1636 compatible = 1636 compatible = "qcom,geni-i2c";
1637 reg = <0x0 0x 1637 reg = <0x0 0x00a90000 0x0 0x4000>;
1638 clock-names = 1638 clock-names = "se";
1639 clocks = <&gc 1639 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1640 pinctrl-names 1640 pinctrl-names = "default";
1641 pinctrl-0 = < 1641 pinctrl-0 = <&qup_i2c12_data_clk>;
1642 interrupts = 1642 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1643 #address-cell 1643 #address-cells = <1>;
1644 #size-cells = 1644 #size-cells = <0>;
1645 interconnects 1645 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1646 1646 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1647 1647 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1648 interconnect- 1648 interconnect-names = "qup-core", "qup-config", "qup-memory";
1649 dmas = <&gpi_ 1649 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1650 <&gpi_ 1650 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1651 dma-names = " 1651 dma-names = "tx", "rx";
1652 status = "dis 1652 status = "disabled";
1653 }; 1653 };
1654 1654
1655 spi12: spi@a90000 { 1655 spi12: spi@a90000 {
1656 compatible = 1656 compatible = "qcom,geni-spi";
1657 reg = <0x0 0x 1657 reg = <0x0 0x00a90000 0x0 0x4000>;
1658 clock-names = 1658 clock-names = "se";
1659 clocks = <&gc 1659 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1660 interrupts = 1660 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1661 pinctrl-names 1661 pinctrl-names = "default";
1662 pinctrl-0 = < 1662 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1663 interconnects 1663 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1664 1664 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1665 1665 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1666 interconnect- 1666 interconnect-names = "qup-core", "qup-config", "qup-memory";
1667 dmas = <&gpi_ 1667 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1668 <&gpi_ 1668 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1669 dma-names = " 1669 dma-names = "tx", "rx";
1670 #address-cell 1670 #address-cells = <1>;
1671 #size-cells = 1671 #size-cells = <0>;
1672 status = "dis 1672 status = "disabled";
1673 }; 1673 };
1674 1674
1675 i2c13: i2c@a94000 { 1675 i2c13: i2c@a94000 {
1676 compatible = 1676 compatible = "qcom,geni-i2c";
1677 reg = <0 0x00 1677 reg = <0 0x00a94000 0 0x4000>;
1678 clock-names = 1678 clock-names = "se";
1679 clocks = <&gc 1679 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1680 pinctrl-names 1680 pinctrl-names = "default";
1681 pinctrl-0 = < 1681 pinctrl-0 = <&qup_i2c13_data_clk>;
1682 interrupts = 1682 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1683 interconnects 1683 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1684 1684 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1685 1685 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1686 interconnect- 1686 interconnect-names = "qup-core", "qup-config", "qup-memory";
1687 dmas = <&gpi_ 1687 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1688 <&gpi_ 1688 <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1689 dma-names = " 1689 dma-names = "tx", "rx";
1690 #address-cell 1690 #address-cells = <1>;
1691 #size-cells = 1691 #size-cells = <0>;
1692 status = "dis 1692 status = "disabled";
1693 }; 1693 };
1694 1694
1695 spi13: spi@a94000 { 1695 spi13: spi@a94000 {
1696 compatible = 1696 compatible = "qcom,geni-spi";
1697 reg = <0x0 0x 1697 reg = <0x0 0x00a94000 0x0 0x4000>;
1698 clock-names = 1698 clock-names = "se";
1699 clocks = <&gc 1699 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1700 interrupts = 1700 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1701 pinctrl-names 1701 pinctrl-names = "default";
1702 pinctrl-0 = < 1702 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1703 interconnects 1703 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1704 1704 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1705 1705 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1706 interconnect- 1706 interconnect-names = "qup-core", "qup-config", "qup-memory";
1707 dmas = <&gpi_ 1707 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1708 <&gpi_ 1708 <&gpi_dma1 1 5 QCOM_GPI_SPI>;
1709 dma-names = " 1709 dma-names = "tx", "rx";
1710 #address-cell 1710 #address-cells = <1>;
1711 #size-cells = 1711 #size-cells = <0>;
1712 status = "dis 1712 status = "disabled";
1713 }; 1713 };
1714 1714
1715 i2c14: i2c@a98000 { 1715 i2c14: i2c@a98000 {
1716 compatible = 1716 compatible = "qcom,geni-i2c";
1717 reg = <0 0x00 1717 reg = <0 0x00a98000 0 0x4000>;
1718 clock-names = 1718 clock-names = "se";
1719 clocks = <&gc 1719 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1720 pinctrl-names 1720 pinctrl-names = "default";
1721 pinctrl-0 = < 1721 pinctrl-0 = <&qup_i2c14_data_clk>;
1722 interrupts = 1722 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
1723 interconnects 1723 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1724 1724 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1725 1725 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1726 interconnect- 1726 interconnect-names = "qup-core", "qup-config", "qup-memory";
1727 dmas = <&gpi_ 1727 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
1728 <&gpi_ 1728 <&gpi_dma1 1 6 QCOM_GPI_I2C>;
1729 dma-names = " 1729 dma-names = "tx", "rx";
1730 #address-cell 1730 #address-cells = <1>;
1731 #size-cells = 1731 #size-cells = <0>;
1732 status = "dis 1732 status = "disabled";
1733 }; 1733 };
1734 1734
1735 spi14: spi@a98000 { 1735 spi14: spi@a98000 {
1736 compatible = 1736 compatible = "qcom,geni-spi";
1737 reg = <0x0 0x 1737 reg = <0x0 0x00a98000 0x0 0x4000>;
1738 clock-names = 1738 clock-names = "se";
1739 clocks = <&gc 1739 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1740 interrupts = 1740 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
1741 pinctrl-names 1741 pinctrl-names = "default";
1742 pinctrl-0 = < 1742 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
1743 interconnects 1743 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1744 1744 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1745 1745 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1746 interconnect- 1746 interconnect-names = "qup-core", "qup-config", "qup-memory";
1747 dmas = <&gpi_ 1747 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
1748 <&gpi_ 1748 <&gpi_dma1 1 6 QCOM_GPI_SPI>;
1749 dma-names = " 1749 dma-names = "tx", "rx";
1750 #address-cell 1750 #address-cells = <1>;
1751 #size-cells = 1751 #size-cells = <0>;
1752 status = "dis 1752 status = "disabled";
1753 }; 1753 };
1754 }; 1754 };
1755 1755
1756 rng: rng@10c3000 { 1756 rng: rng@10c3000 {
1757 compatible = "qcom,sm 1757 compatible = "qcom,sm8450-trng", "qcom,trng";
1758 reg = <0 0x010c3000 0 1758 reg = <0 0x010c3000 0 0x1000>;
1759 }; 1759 };
1760 1760
1761 pcie0: pcie@1c00000 { 1761 pcie0: pcie@1c00000 {
1762 compatible = "qcom,pc 1762 compatible = "qcom,pcie-sm8450-pcie0";
1763 reg = <0 0x01c00000 0 1763 reg = <0 0x01c00000 0 0x3000>,
1764 <0 0x60000000 0 1764 <0 0x60000000 0 0xf1d>,
1765 <0 0x60000f20 0 1765 <0 0x60000f20 0 0xa8>,
1766 <0 0x60001000 0 1766 <0 0x60001000 0 0x1000>,
1767 <0 0x60100000 0 1767 <0 0x60100000 0 0x100000>;
1768 reg-names = "parf", " 1768 reg-names = "parf", "dbi", "elbi", "atu", "config";
1769 device_type = "pci"; 1769 device_type = "pci";
1770 linux,pci-domain = <0 1770 linux,pci-domain = <0>;
1771 bus-range = <0x00 0xf 1771 bus-range = <0x00 0xff>;
1772 num-lanes = <1>; 1772 num-lanes = <1>;
1773 1773
1774 #address-cells = <3>; 1774 #address-cells = <3>;
1775 #size-cells = <2>; 1775 #size-cells = <2>;
1776 1776
1777 ranges = <0x01000000 1777 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
1778 <0x02000000 1778 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1779 1779
1780 msi-map = <0x0 &gic_i 1780 msi-map = <0x0 &gic_its 0x5980 0x1>,
1781 <0x100 &gic 1781 <0x100 &gic_its 0x5981 0x1>;
1782 msi-map-mask = <0xff0 1782 msi-map-mask = <0xff00>;
1783 interrupts = <GIC_SPI 1783 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
1784 <GIC_SPI 1784 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
1785 <GIC_SPI 1785 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
1786 <GIC_SPI 1786 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
1787 <GIC_SPI 1787 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1788 <GIC_SPI 1788 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1789 <GIC_SPI 1789 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
1790 <GIC_SPI 1790 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1791 interrupt-names = "ms 1791 interrupt-names = "msi0",
1792 "ms 1792 "msi1",
1793 "ms 1793 "msi2",
1794 "ms 1794 "msi3",
1795 "ms 1795 "msi4",
1796 "ms 1796 "msi5",
1797 "ms 1797 "msi6",
1798 "ms 1798 "msi7";
1799 #interrupt-cells = <1 1799 #interrupt-cells = <1>;
1800 interrupt-map-mask = 1800 interrupt-map-mask = <0 0 0 0x7>;
1801 interrupt-map = <0 0 1801 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1802 <0 0 1802 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1803 <0 0 1803 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1804 <0 0 1804 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1805 1805
1806 interconnects = <&pci <<
1807 &mc_ <<
1808 <&gem <<
1809 &con <<
1810 interconnect-names = <<
1811 <<
1812 clocks = <&gcc GCC_PC 1806 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1813 <&gcc GCC_PC 1807 <&gcc GCC_PCIE_0_PIPE_CLK_SRC>,
1814 <&pcie0_phy> 1808 <&pcie0_phy>,
1815 <&rpmhcc RPM 1809 <&rpmhcc RPMH_CXO_CLK>,
1816 <&gcc GCC_PC 1810 <&gcc GCC_PCIE_0_AUX_CLK>,
1817 <&gcc GCC_PC 1811 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1818 <&gcc GCC_PC 1812 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1819 <&gcc GCC_PC 1813 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1820 <&gcc GCC_PC 1814 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
1821 <&gcc GCC_DD 1815 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1822 <&gcc GCC_AG 1816 <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
1823 <&gcc GCC_AG 1817 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
1824 clock-names = "pipe", 1818 clock-names = "pipe",
1825 "pipe_m 1819 "pipe_mux",
1826 "phy_pi 1820 "phy_pipe",
1827 "ref", 1821 "ref",
1828 "aux", 1822 "aux",
1829 "cfg", 1823 "cfg",
1830 "bus_ma 1824 "bus_master",
1831 "bus_sl 1825 "bus_slave",
1832 "slave_ 1826 "slave_q2a",
1833 "ddrss_ 1827 "ddrss_sf_tbu",
1834 "aggre0 1828 "aggre0",
1835 "aggre1 1829 "aggre1";
1836 1830
1837 iommu-map = <0x0 &a 1831 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
1838 <0x100 &a 1832 <0x100 &apps_smmu 0x1c01 0x1>;
1839 1833
1840 resets = <&gcc GCC_PC 1834 resets = <&gcc GCC_PCIE_0_BCR>;
1841 reset-names = "pci"; 1835 reset-names = "pci";
1842 1836
1843 power-domains = <&gcc 1837 power-domains = <&gcc PCIE_0_GDSC>;
1844 1838
1845 phys = <&pcie0_phy>; 1839 phys = <&pcie0_phy>;
1846 phy-names = "pciephy" 1840 phy-names = "pciephy";
1847 1841
1848 perst-gpios = <&tlmm 1842 perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
1849 wake-gpios = <&tlmm 9 1843 wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
1850 1844
1851 pinctrl-names = "defa 1845 pinctrl-names = "default";
1852 pinctrl-0 = <&pcie0_d 1846 pinctrl-0 = <&pcie0_default_state>;
1853 1847
1854 operating-points-v2 = <<
1855 <<
1856 status = "disabled"; 1848 status = "disabled";
1857 1849
1858 pcie0_opp_table: opp- <<
1859 compatible = <<
1860 <<
1861 /* GEN 1 x1 * <<
1862 opp-2500000 { <<
1863 opp-h <<
1864 requi <<
1865 opp-p <<
1866 }; <<
1867 <<
1868 /* GEN 2 x1 * <<
1869 opp-5000000 { <<
1870 opp-h <<
1871 requi <<
1872 opp-p <<
1873 }; <<
1874 <<
1875 /* GEN 3 x1 * <<
1876 opp-8000000 { <<
1877 opp-h <<
1878 requi <<
1879 opp-p <<
1880 }; <<
1881 }; <<
1882 <<
1883 pcie@0 { 1850 pcie@0 {
1884 device_type = 1851 device_type = "pci";
1885 reg = <0x0 0x 1852 reg = <0x0 0x0 0x0 0x0 0x0>;
1886 bus-range = < 1853 bus-range = <0x01 0xff>;
1887 1854
1888 #address-cell 1855 #address-cells = <3>;
1889 #size-cells = 1856 #size-cells = <2>;
1890 ranges; 1857 ranges;
1891 }; 1858 };
1892 }; 1859 };
1893 1860
1894 pcie0_phy: phy@1c06000 { 1861 pcie0_phy: phy@1c06000 {
1895 compatible = "qcom,sm 1862 compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy";
1896 reg = <0 0x01c06000 0 1863 reg = <0 0x01c06000 0 0x2000>;
1897 1864
1898 clocks = <&gcc GCC_PC 1865 clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
1899 <&gcc GCC_PC 1866 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1900 <&gcc GCC_PC 1867 <&gcc GCC_PCIE_0_CLKREF_EN>,
1901 <&gcc GCC_PC 1868 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
1902 <&gcc GCC_PC 1869 <&gcc GCC_PCIE_0_PIPE_CLK>;
1903 clock-names = "aux", 1870 clock-names = "aux",
1904 "cfg_ah 1871 "cfg_ahb",
1905 "ref", 1872 "ref",
1906 "rchng" 1873 "rchng",
1907 "pipe"; 1874 "pipe";
1908 1875
1909 clock-output-names = 1876 clock-output-names = "pcie_0_pipe_clk";
1910 #clock-cells = <0>; 1877 #clock-cells = <0>;
1911 1878
1912 #phy-cells = <0>; 1879 #phy-cells = <0>;
1913 1880
1914 resets = <&gcc GCC_PC 1881 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1915 reset-names = "phy"; 1882 reset-names = "phy";
1916 1883
1917 assigned-clocks = <&g 1884 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
1918 assigned-clock-rates 1885 assigned-clock-rates = <100000000>;
1919 1886
1920 status = "disabled"; 1887 status = "disabled";
1921 }; 1888 };
1922 1889
1923 pcie1: pcie@1c08000 { 1890 pcie1: pcie@1c08000 {
1924 compatible = "qcom,pc 1891 compatible = "qcom,pcie-sm8450-pcie1";
1925 reg = <0 0x01c08000 0 1892 reg = <0 0x01c08000 0 0x3000>,
1926 <0 0x40000000 0 1893 <0 0x40000000 0 0xf1d>,
1927 <0 0x40000f20 0 1894 <0 0x40000f20 0 0xa8>,
1928 <0 0x40001000 0 1895 <0 0x40001000 0 0x1000>,
1929 <0 0x40100000 0 1896 <0 0x40100000 0 0x100000>;
1930 reg-names = "parf", " 1897 reg-names = "parf", "dbi", "elbi", "atu", "config";
1931 device_type = "pci"; 1898 device_type = "pci";
1932 linux,pci-domain = <1 1899 linux,pci-domain = <1>;
1933 bus-range = <0x00 0xf 1900 bus-range = <0x00 0xff>;
1934 num-lanes = <2>; 1901 num-lanes = <2>;
1935 1902
1936 #address-cells = <3>; 1903 #address-cells = <3>;
1937 #size-cells = <2>; 1904 #size-cells = <2>;
1938 1905
1939 ranges = <0x01000000 1906 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
1940 <0x02000000 1907 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1941 1908
1942 msi-map = <0x0 &gic_i 1909 msi-map = <0x0 &gic_its 0x5a00 0x1>,
1943 <0x100 &gic 1910 <0x100 &gic_its 0x5a01 0x1>;
1944 msi-map-mask = <0xff0 1911 msi-map-mask = <0xff00>;
1945 interrupts = <GIC_SPI 1912 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
1946 <GIC_SPI 1913 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
1947 <GIC_SPI 1914 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
1948 <GIC_SPI 1915 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
1949 <GIC_SPI 1916 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
1950 <GIC_SPI 1917 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
1951 <GIC_SPI 1918 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
1952 <GIC_SPI 1919 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1953 interrupt-names = "ms 1920 interrupt-names = "msi0",
1954 "ms 1921 "msi1",
1955 "ms 1922 "msi2",
1956 "ms 1923 "msi3",
1957 "ms 1924 "msi4",
1958 "ms 1925 "msi5",
1959 "ms 1926 "msi6",
1960 "ms 1927 "msi7";
1961 #interrupt-cells = <1 1928 #interrupt-cells = <1>;
1962 interrupt-map-mask = 1929 interrupt-map-mask = <0 0 0 0x7>;
1963 interrupt-map = <0 0 1930 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1964 <0 0 1931 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1965 <0 0 1932 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1966 <0 0 1933 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1967 1934
1968 interconnects = <&pci <<
1969 &mc_ <<
1970 <&gem <<
1971 &con <<
1972 interconnect-names = <<
1973 <<
1974 clocks = <&gcc GCC_PC 1935 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1975 <&gcc GCC_PC 1936 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>,
1976 <&pcie1_phy !! 1937 <&pcie1_phy>,
1977 <&rpmhcc RPM 1938 <&rpmhcc RPMH_CXO_CLK>,
1978 <&gcc GCC_PC 1939 <&gcc GCC_PCIE_1_AUX_CLK>,
1979 <&gcc GCC_PC 1940 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1980 <&gcc GCC_PC 1941 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1981 <&gcc GCC_PC 1942 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
1982 <&gcc GCC_PC 1943 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
1983 <&gcc GCC_DD 1944 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1984 <&gcc GCC_AG 1945 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
1985 clock-names = "pipe", 1946 clock-names = "pipe",
1986 "pipe_m 1947 "pipe_mux",
1987 "phy_pi 1948 "phy_pipe",
1988 "ref", 1949 "ref",
1989 "aux", 1950 "aux",
1990 "cfg", 1951 "cfg",
1991 "bus_ma 1952 "bus_master",
1992 "bus_sl 1953 "bus_slave",
1993 "slave_ 1954 "slave_q2a",
1994 "ddrss_ 1955 "ddrss_sf_tbu",
1995 "aggre1 1956 "aggre1";
1996 1957
1997 iommu-map = <0x0 &a 1958 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
1998 <0x100 &a 1959 <0x100 &apps_smmu 0x1c81 0x1>;
1999 1960
2000 resets = <&gcc GCC_PC 1961 resets = <&gcc GCC_PCIE_1_BCR>;
2001 reset-names = "pci"; 1962 reset-names = "pci";
2002 1963
2003 power-domains = <&gcc 1964 power-domains = <&gcc PCIE_1_GDSC>;
2004 1965
2005 phys = <&pcie1_phy>; 1966 phys = <&pcie1_phy>;
2006 phy-names = "pciephy" 1967 phy-names = "pciephy";
2007 1968
2008 perst-gpios = <&tlmm 1969 perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
2009 wake-gpios = <&tlmm 9 1970 wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
2010 1971
2011 pinctrl-names = "defa 1972 pinctrl-names = "default";
2012 pinctrl-0 = <&pcie1_d 1973 pinctrl-0 = <&pcie1_default_state>;
2013 1974
2014 operating-points-v2 = <<
2015 <<
2016 status = "disabled"; 1975 status = "disabled";
2017 1976
2018 pcie1_opp_table: opp- <<
2019 compatible = <<
2020 <<
2021 /* GEN 1 x1 * <<
2022 opp-2500000 { <<
2023 opp-h <<
2024 requi <<
2025 opp-p <<
2026 }; <<
2027 <<
2028 /* GEN 1 x2 a <<
2029 opp-5000000 { <<
2030 opp-h <<
2031 requi <<
2032 opp-p <<
2033 }; <<
2034 <<
2035 /* GEN 2 x2 * <<
2036 opp-10000000 <<
2037 opp-h <<
2038 requi <<
2039 opp-p <<
2040 }; <<
2041 <<
2042 /* GEN 3 x1 * <<
2043 opp-8000000 { <<
2044 opp-h <<
2045 requi <<
2046 opp-p <<
2047 }; <<
2048 <<
2049 /* GEN 3 x2 a <<
2050 opp-16000000 <<
2051 opp-h <<
2052 requi <<
2053 opp-p <<
2054 }; <<
2055 <<
2056 /* GEN 4 x2 * <<
2057 opp-32000000 <<
2058 opp-h <<
2059 requi <<
2060 opp-p <<
2061 }; <<
2062 }; <<
2063 <<
2064 pcie@0 { 1977 pcie@0 {
2065 device_type = 1978 device_type = "pci";
2066 reg = <0x0 0x 1979 reg = <0x0 0x0 0x0 0x0 0x0>;
2067 bus-range = < 1980 bus-range = <0x01 0xff>;
2068 1981
2069 #address-cell 1982 #address-cells = <3>;
2070 #size-cells = 1983 #size-cells = <2>;
2071 ranges; 1984 ranges;
2072 }; 1985 };
2073 }; 1986 };
2074 1987
2075 pcie1_phy: phy@1c0e000 { 1988 pcie1_phy: phy@1c0e000 {
2076 compatible = "qcom,sm 1989 compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy";
2077 reg = <0 0x01c0e000 0 1990 reg = <0 0x01c0e000 0 0x2000>;
2078 1991
2079 clocks = <&gcc GCC_PC 1992 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>,
2080 <&gcc GCC_PC 1993 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2081 <&gcc GCC_PC 1994 <&gcc GCC_PCIE_1_CLKREF_EN>,
2082 <&gcc GCC_PC 1995 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
2083 <&gcc GCC_PC 1996 <&gcc GCC_PCIE_1_PIPE_CLK>;
2084 clock-names = "aux", 1997 clock-names = "aux",
2085 "cfg_ah 1998 "cfg_ahb",
2086 "ref", 1999 "ref",
2087 "rchng" 2000 "rchng",
2088 "pipe"; 2001 "pipe";
2089 2002
2090 clock-output-names = 2003 clock-output-names = "pcie_1_pipe_clk";
2091 #clock-cells = <1>; !! 2004 #clock-cells = <0>;
2092 2005
2093 #phy-cells = <0>; 2006 #phy-cells = <0>;
2094 2007
2095 resets = <&gcc GCC_PC 2008 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2096 reset-names = "phy"; 2009 reset-names = "phy";
2097 2010
2098 assigned-clocks = <&g 2011 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
2099 assigned-clock-rates 2012 assigned-clock-rates = <100000000>;
2100 2013
2101 status = "disabled"; 2014 status = "disabled";
2102 }; 2015 };
2103 2016
2104 config_noc: interconnect@1500 2017 config_noc: interconnect@1500000 {
2105 compatible = "qcom,sm 2018 compatible = "qcom,sm8450-config-noc";
2106 reg = <0 0x01500000 0 2019 reg = <0 0x01500000 0 0x1c000>;
2107 #interconnect-cells = 2020 #interconnect-cells = <2>;
2108 qcom,bcm-voters = <&a 2021 qcom,bcm-voters = <&apps_bcm_voter>;
2109 }; 2022 };
2110 2023
2111 system_noc: interconnect@1680 2024 system_noc: interconnect@1680000 {
2112 compatible = "qcom,sm 2025 compatible = "qcom,sm8450-system-noc";
2113 reg = <0 0x01680000 0 2026 reg = <0 0x01680000 0 0x1e200>;
2114 #interconnect-cells = 2027 #interconnect-cells = <2>;
2115 qcom,bcm-voters = <&a 2028 qcom,bcm-voters = <&apps_bcm_voter>;
2116 }; 2029 };
2117 2030
2118 pcie_noc: interconnect@16c000 2031 pcie_noc: interconnect@16c0000 {
2119 compatible = "qcom,sm 2032 compatible = "qcom,sm8450-pcie-anoc";
2120 reg = <0 0x016c0000 0 2033 reg = <0 0x016c0000 0 0xe280>;
2121 #interconnect-cells = 2034 #interconnect-cells = <2>;
2122 qcom,bcm-voters = <&a 2035 qcom,bcm-voters = <&apps_bcm_voter>;
2123 }; 2036 };
2124 2037
2125 aggre1_noc: interconnect@16e0 2038 aggre1_noc: interconnect@16e0000 {
2126 compatible = "qcom,sm 2039 compatible = "qcom,sm8450-aggre1-noc";
2127 reg = <0 0x016e0000 0 2040 reg = <0 0x016e0000 0 0x1c080>;
2128 #interconnect-cells = 2041 #interconnect-cells = <2>;
2129 clocks = <&gcc GCC_AG 2042 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2130 <&gcc GCC_AG 2043 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
2131 qcom,bcm-voters = <&a 2044 qcom,bcm-voters = <&apps_bcm_voter>;
2132 }; 2045 };
2133 2046
2134 aggre2_noc: interconnect@1700 2047 aggre2_noc: interconnect@1700000 {
2135 compatible = "qcom,sm 2048 compatible = "qcom,sm8450-aggre2-noc";
2136 reg = <0 0x01700000 0 2049 reg = <0 0x01700000 0 0x31080>;
2137 #interconnect-cells = 2050 #interconnect-cells = <2>;
2138 qcom,bcm-voters = <&a 2051 qcom,bcm-voters = <&apps_bcm_voter>;
2139 clocks = <&gcc GCC_AG 2052 clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
2140 <&gcc GCC_AG 2053 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
2141 <&gcc GCC_AG 2054 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2142 <&rpmhcc RPM 2055 <&rpmhcc RPMH_IPA_CLK>;
2143 }; 2056 };
2144 2057
2145 mmss_noc: interconnect@174000 2058 mmss_noc: interconnect@1740000 {
2146 compatible = "qcom,sm 2059 compatible = "qcom,sm8450-mmss-noc";
2147 reg = <0 0x01740000 0 2060 reg = <0 0x01740000 0 0x1f080>;
2148 #interconnect-cells = 2061 #interconnect-cells = <2>;
2149 qcom,bcm-voters = <&a 2062 qcom,bcm-voters = <&apps_bcm_voter>;
2150 }; 2063 };
2151 2064
2152 tcsr_mutex: hwlock@1f40000 { 2065 tcsr_mutex: hwlock@1f40000 {
2153 compatible = "qcom,tc 2066 compatible = "qcom,tcsr-mutex";
2154 reg = <0x0 0x01f40000 2067 reg = <0x0 0x01f40000 0x0 0x40000>;
2155 #hwlock-cells = <1>; 2068 #hwlock-cells = <1>;
2156 }; 2069 };
2157 2070
2158 tcsr: syscon@1fc0000 { 2071 tcsr: syscon@1fc0000 {
2159 compatible = "qcom,sm 2072 compatible = "qcom,sm8450-tcsr", "syscon";
2160 reg = <0x0 0x1fc0000 2073 reg = <0x0 0x1fc0000 0x0 0x30000>;
2161 }; 2074 };
2162 2075
2163 gpu: gpu@3d00000 { 2076 gpu: gpu@3d00000 {
2164 compatible = "qcom,ad 2077 compatible = "qcom,adreno-730.1", "qcom,adreno";
2165 reg = <0x0 0x03d00000 2078 reg = <0x0 0x03d00000 0x0 0x40000>,
2166 <0x0 0x03d9e000 2079 <0x0 0x03d9e000 0x0 0x1000>,
2167 <0x0 0x03d61000 2080 <0x0 0x03d61000 0x0 0x800>;
2168 reg-names = "kgsl_3d0 2081 reg-names = "kgsl_3d0_reg_memory",
2169 "cx_mem", 2082 "cx_mem",
2170 "cx_dbgc" 2083 "cx_dbgc";
2171 2084
2172 interrupts = <GIC_SPI 2085 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2173 2086
2174 iommus = <&adreno_smm 2087 iommus = <&adreno_smmu 0 0x400>,
2175 <&adreno_smm 2088 <&adreno_smmu 1 0x400>;
2176 2089
2177 operating-points-v2 = 2090 operating-points-v2 = <&gpu_opp_table>;
2178 2091
2179 qcom,gmu = <&gmu>; 2092 qcom,gmu = <&gmu>;
2180 #cooling-cells = <2>; 2093 #cooling-cells = <2>;
2181 2094
2182 status = "disabled"; 2095 status = "disabled";
2183 2096
2184 zap-shader { 2097 zap-shader {
2185 memory-region 2098 memory-region = <&gpu_micro_code_mem>;
2186 }; 2099 };
2187 2100
2188 gpu_opp_table: opp-ta 2101 gpu_opp_table: opp-table {
2189 compatible = 2102 compatible = "operating-points-v2";
2190 2103
2191 opp-818000000 2104 opp-818000000 {
2192 opp-h 2105 opp-hz = /bits/ 64 <818000000>;
2193 opp-l 2106 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2194 }; 2107 };
2195 2108
2196 opp-791000000 2109 opp-791000000 {
2197 opp-h 2110 opp-hz = /bits/ 64 <791000000>;
2198 opp-l 2111 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2199 }; 2112 };
2200 2113
2201 opp-734000000 2114 opp-734000000 {
2202 opp-h 2115 opp-hz = /bits/ 64 <734000000>;
2203 opp-l 2116 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2204 }; 2117 };
2205 2118
2206 opp-640000000 2119 opp-640000000 {
2207 opp-h 2120 opp-hz = /bits/ 64 <640000000>;
2208 opp-l 2121 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2209 }; 2122 };
2210 2123
2211 opp-599000000 2124 opp-599000000 {
2212 opp-h 2125 opp-hz = /bits/ 64 <599000000>;
2213 opp-l 2126 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2214 }; 2127 };
2215 2128
2216 opp-545000000 2129 opp-545000000 {
2217 opp-h 2130 opp-hz = /bits/ 64 <545000000>;
2218 opp-l 2131 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
2219 }; 2132 };
2220 2133
2221 opp-492000000 2134 opp-492000000 {
2222 opp-h 2135 opp-hz = /bits/ 64 <492000000>;
2223 opp-l 2136 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2224 }; 2137 };
2225 2138
2226 opp-421000000 2139 opp-421000000 {
2227 opp-h 2140 opp-hz = /bits/ 64 <421000000>;
2228 opp-l 2141 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
2229 }; 2142 };
2230 2143
2231 opp-350000000 2144 opp-350000000 {
2232 opp-h 2145 opp-hz = /bits/ 64 <350000000>;
2233 opp-l 2146 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2234 }; 2147 };
2235 2148
2236 opp-317000000 2149 opp-317000000 {
2237 opp-h 2150 opp-hz = /bits/ 64 <317000000>;
2238 opp-l 2151 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2239 }; 2152 };
2240 2153
2241 opp-285000000 2154 opp-285000000 {
2242 opp-h 2155 opp-hz = /bits/ 64 <285000000>;
2243 opp-l 2156 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
2244 }; 2157 };
2245 2158
2246 opp-220000000 2159 opp-220000000 {
2247 opp-h 2160 opp-hz = /bits/ 64 <220000000>;
2248 opp-l 2161 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
2249 }; 2162 };
2250 }; 2163 };
2251 }; 2164 };
2252 2165
2253 gmu: gmu@3d6a000 { 2166 gmu: gmu@3d6a000 {
2254 compatible = "qcom,ad 2167 compatible = "qcom,adreno-gmu-730.1", "qcom,adreno-gmu";
2255 reg = <0x0 0x03d6a000 2168 reg = <0x0 0x03d6a000 0x0 0x35000>,
2256 <0x0 0x03d50000 2169 <0x0 0x03d50000 0x0 0x10000>,
2257 <0x0 0x0b290000 2170 <0x0 0x0b290000 0x0 0x10000>;
2258 reg-names = "gmu", "r 2171 reg-names = "gmu", "rscc", "gmu_pdc";
2259 2172
2260 interrupts = <GIC_SPI 2173 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2261 <GIC_SPI 2174 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2262 interrupt-names = "hf 2175 interrupt-names = "hfi", "gmu";
2263 2176
2264 clocks = <&gpucc GPU_ 2177 clocks = <&gpucc GPU_CC_AHB_CLK>,
2265 <&gpucc GPU_ 2178 <&gpucc GPU_CC_CX_GMU_CLK>,
2266 <&gpucc GPU_ 2179 <&gpucc GPU_CC_CXO_CLK>,
2267 <&gcc GCC_DD 2180 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2268 <&gcc GCC_GP 2181 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2269 <&gpucc GPU_ 2182 <&gpucc GPU_CC_HUB_CX_INT_CLK>,
2270 <&gpucc GPU_ 2183 <&gpucc GPU_CC_DEMET_CLK>;
2271 clock-names = "ahb", 2184 clock-names = "ahb",
2272 "gmu", 2185 "gmu",
2273 "cxo", 2186 "cxo",
2274 "axi", 2187 "axi",
2275 "memnoc 2188 "memnoc",
2276 "hub", 2189 "hub",
2277 "demet" 2190 "demet";
2278 2191
2279 power-domains = <&gpu 2192 power-domains = <&gpucc GPU_CX_GDSC>,
2280 <&gpu 2193 <&gpucc GPU_GX_GDSC>;
2281 power-domain-names = 2194 power-domain-names = "cx",
2282 2195 "gx";
2283 2196
2284 iommus = <&adreno_smm 2197 iommus = <&adreno_smmu 5 0x400>;
2285 2198
2286 qcom,qmp = <&aoss_qmp 2199 qcom,qmp = <&aoss_qmp>;
2287 2200
2288 operating-points-v2 = 2201 operating-points-v2 = <&gmu_opp_table>;
2289 2202
2290 gmu_opp_table: opp-ta 2203 gmu_opp_table: opp-table {
2291 compatible = 2204 compatible = "operating-points-v2";
2292 2205
2293 opp-500000000 2206 opp-500000000 {
2294 opp-h 2207 opp-hz = /bits/ 64 <500000000>;
2295 opp-l 2208 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2296 }; 2209 };
2297 2210
2298 opp-200000000 2211 opp-200000000 {
2299 opp-h 2212 opp-hz = /bits/ 64 <200000000>;
2300 opp-l 2213 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2301 }; 2214 };
2302 }; 2215 };
2303 }; 2216 };
2304 2217
2305 gpucc: clock-controller@3d900 2218 gpucc: clock-controller@3d90000 {
2306 compatible = "qcom,sm 2219 compatible = "qcom,sm8450-gpucc";
2307 reg = <0x0 0x03d90000 2220 reg = <0x0 0x03d90000 0x0 0xa000>;
2308 clocks = <&rpmhcc RPM 2221 clocks = <&rpmhcc RPMH_CXO_CLK>,
2309 <&gcc GCC_GP 2222 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2310 <&gcc GCC_GP 2223 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2311 #clock-cells = <1>; 2224 #clock-cells = <1>;
2312 #reset-cells = <1>; 2225 #reset-cells = <1>;
2313 #power-domain-cells = 2226 #power-domain-cells = <1>;
2314 }; 2227 };
2315 2228
2316 adreno_smmu: iommu@3da0000 { 2229 adreno_smmu: iommu@3da0000 {
2317 compatible = "qcom,sm 2230 compatible = "qcom,sm8450-smmu-500", "qcom,adreno-smmu",
2318 "qcom,sm 2231 "qcom,smmu-500", "arm,mmu-500";
2319 reg = <0x0 0x03da0000 2232 reg = <0x0 0x03da0000 0x0 0x40000>;
2320 #iommu-cells = <2>; 2233 #iommu-cells = <2>;
2321 #global-interrupts = 2234 #global-interrupts = <1>;
2322 interrupts = <GIC_SPI 2235 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
2323 <GIC_SPI 2236 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
2324 <GIC_SPI 2237 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
2325 <GIC_SPI 2238 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
2326 <GIC_SPI 2239 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
2327 <GIC_SPI 2240 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
2328 <GIC_SPI 2241 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
2329 <GIC_SPI 2242 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
2330 <GIC_SPI 2243 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
2331 <GIC_SPI 2244 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
2332 <GIC_SPI 2245 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
2333 <GIC_SPI 2246 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
2334 <GIC_SPI 2247 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
2335 <GIC_SPI 2248 <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>,
2336 <GIC_SPI 2249 <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>,
2337 <GIC_SPI 2250 <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
2338 <GIC_SPI 2251 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>,
2339 <GIC_SPI 2252 <GIC_SPI 659 IRQ_TYPE_LEVEL_HIGH>,
2340 <GIC_SPI 2253 <GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH>,
2341 <GIC_SPI 2254 <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH>,
2342 <GIC_SPI 2255 <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>,
2343 <GIC_SPI 2256 <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>,
2344 <GIC_SPI 2257 <GIC_SPI 668 IRQ_TYPE_LEVEL_HIGH>,
2345 <GIC_SPI 2258 <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>,
2346 <GIC_SPI 2259 <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>,
2347 <GIC_SPI 2260 <GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH>;
2348 clocks = <&gpucc GPU_ 2261 clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
2349 <&gpucc GPU_ 2262 <&gpucc GPU_CC_HUB_CX_INT_CLK>,
2350 <&gpucc GPU_ 2263 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
2351 <&gcc GCC_GP 2264 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2352 <&gcc GCC_GP 2265 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
2353 <&gpucc GPU_ 2266 <&gpucc GPU_CC_AHB_CLK>;
2354 clock-names = "gmu", 2267 clock-names = "gmu",
2355 "hub", 2268 "hub",
2356 "hlos", 2269 "hlos",
2357 "bus", 2270 "bus",
2358 "iface" 2271 "iface",
2359 "ahb"; 2272 "ahb";
2360 power-domains = <&gpu 2273 power-domains = <&gpucc GPU_CX_GDSC>;
2361 dma-coherent; 2274 dma-coherent;
2362 }; 2275 };
2363 2276
2364 usb_1_hsphy: phy@88e3000 { 2277 usb_1_hsphy: phy@88e3000 {
2365 compatible = "qcom,sm 2278 compatible = "qcom,sm8450-usb-hs-phy",
2366 "qcom,us 2279 "qcom,usb-snps-hs-7nm-phy";
2367 reg = <0 0x088e3000 0 2280 reg = <0 0x088e3000 0 0x400>;
2368 status = "disabled"; 2281 status = "disabled";
2369 #phy-cells = <0>; 2282 #phy-cells = <0>;
2370 2283
2371 clocks = <&rpmhcc RPM 2284 clocks = <&rpmhcc RPMH_CXO_CLK>;
2372 clock-names = "ref"; 2285 clock-names = "ref";
2373 2286
2374 resets = <&gcc GCC_QU 2287 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2375 }; 2288 };
2376 2289
2377 usb_1_qmpphy: phy@88e8000 { 2290 usb_1_qmpphy: phy@88e8000 {
2378 compatible = "qcom,sm 2291 compatible = "qcom,sm8450-qmp-usb3-dp-phy";
2379 reg = <0 0x088e8000 0 2292 reg = <0 0x088e8000 0 0x3000>;
2380 2293
2381 clocks = <&gcc GCC_US 2294 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2382 <&rpmhcc RPM 2295 <&rpmhcc RPMH_CXO_CLK>,
2383 <&gcc GCC_US 2296 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
2384 <&gcc GCC_US 2297 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2385 clock-names = "aux", 2298 clock-names = "aux", "ref", "com_aux", "usb3_pipe";
2386 2299
2387 resets = <&gcc GCC_US 2300 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
2388 <&gcc GCC_US 2301 <&gcc GCC_USB3_PHY_PRIM_BCR>;
2389 reset-names = "phy", 2302 reset-names = "phy", "common";
2390 2303
2391 #clock-cells = <1>; 2304 #clock-cells = <1>;
2392 #phy-cells = <1>; 2305 #phy-cells = <1>;
2393 2306
2394 orientation-switch; <<
2395 <<
2396 status = "disabled"; 2307 status = "disabled";
2397 2308
2398 ports { 2309 ports {
2399 #address-cell 2310 #address-cells = <1>;
2400 #size-cells = 2311 #size-cells = <0>;
2401 2312
2402 port@0 { 2313 port@0 {
2403 reg = 2314 reg = <0>;
2404 2315
2405 usb_1 2316 usb_1_qmpphy_out: endpoint {
2406 }; 2317 };
2407 }; 2318 };
2408 2319
2409 port@1 { 2320 port@1 {
2410 reg = 2321 reg = <1>;
2411 2322
2412 usb_1 2323 usb_1_qmpphy_usb_ss_in: endpoint {
2413 <<
2414 }; 2324 };
2415 }; 2325 };
2416 2326
2417 port@2 { 2327 port@2 {
2418 reg = 2328 reg = <2>;
2419 2329
2420 usb_1 2330 usb_1_qmpphy_dp_in: endpoint {
2421 <<
2422 }; 2331 };
2423 }; 2332 };
2424 }; 2333 };
2425 }; 2334 };
2426 2335
2427 remoteproc_slpi: remoteproc@2 2336 remoteproc_slpi: remoteproc@2400000 {
2428 compatible = "qcom,sm 2337 compatible = "qcom,sm8450-slpi-pas";
2429 reg = <0 0x02400000 0 2338 reg = <0 0x02400000 0 0x4000>;
2430 2339
2431 interrupts-extended = 2340 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>,
2432 2341 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
2433 2342 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
2434 2343 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
2435 2344 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
2436 interrupt-names = "wd 2345 interrupt-names = "wdog", "fatal", "ready",
2437 "ha 2346 "handover", "stop-ack";
2438 2347
2439 clocks = <&rpmhcc RPM 2348 clocks = <&rpmhcc RPMH_CXO_CLK>;
2440 clock-names = "xo"; 2349 clock-names = "xo";
2441 2350
2442 power-domains = <&rpm 2351 power-domains = <&rpmhpd RPMHPD_LCX>,
2443 <&rpm 2352 <&rpmhpd RPMHPD_LMX>;
2444 power-domain-names = 2353 power-domain-names = "lcx", "lmx";
2445 2354
2446 memory-region = <&slp 2355 memory-region = <&slpi_mem>;
2447 2356
2448 qcom,qmp = <&aoss_qmp 2357 qcom,qmp = <&aoss_qmp>;
2449 2358
2450 qcom,smem-states = <& 2359 qcom,smem-states = <&smp2p_slpi_out 0>;
2451 qcom,smem-state-names 2360 qcom,smem-state-names = "stop";
2452 2361
2453 status = "disabled"; 2362 status = "disabled";
2454 2363
2455 glink-edge { 2364 glink-edge {
2456 interrupts-ex 2365 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
2457 2366 IPCC_MPROC_SIGNAL_GLINK_QMP
2458 2367 IRQ_TYPE_EDGE_RISING>;
2459 mboxes = <&ip 2368 mboxes = <&ipcc IPCC_CLIENT_SLPI
2460 2369 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2461 2370
2462 label = "slpi 2371 label = "slpi";
2463 qcom,remote-p 2372 qcom,remote-pid = <3>;
2464 2373
2465 fastrpc { 2374 fastrpc {
2466 compa 2375 compatible = "qcom,fastrpc";
2467 qcom, 2376 qcom,glink-channels = "fastrpcglink-apps-dsp";
2468 label 2377 label = "sdsp";
2469 qcom, 2378 qcom,non-secure-domain;
2470 #addr 2379 #address-cells = <1>;
2471 #size 2380 #size-cells = <0>;
2472 2381
2473 compu 2382 compute-cb@1 {
2474 2383 compatible = "qcom,fastrpc-compute-cb";
2475 2384 reg = <1>;
2476 2385 iommus = <&apps_smmu 0x0541 0x0>;
2477 }; 2386 };
2478 2387
2479 compu 2388 compute-cb@2 {
2480 2389 compatible = "qcom,fastrpc-compute-cb";
2481 2390 reg = <2>;
2482 2391 iommus = <&apps_smmu 0x0542 0x0>;
2483 }; 2392 };
2484 2393
2485 compu 2394 compute-cb@3 {
2486 2395 compatible = "qcom,fastrpc-compute-cb";
2487 2396 reg = <3>;
2488 2397 iommus = <&apps_smmu 0x0543 0x0>;
2489 2398 /* note: shared-cb = <4> in downstream */
2490 }; 2399 };
2491 }; 2400 };
2492 }; 2401 };
2493 }; 2402 };
2494 2403
2495 wsa2macro: codec@31e0000 { 2404 wsa2macro: codec@31e0000 {
2496 compatible = "qcom,sm 2405 compatible = "qcom,sm8450-lpass-wsa-macro";
2497 reg = <0 0x031e0000 0 2406 reg = <0 0x031e0000 0 0x1000>;
2498 clocks = <&q6prmcc LP 2407 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2499 <&q6prmcc LP 2408 <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2500 <&q6prmcc LP 2409 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2501 <&q6prmcc LP 2410 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2502 <&vamacro>; 2411 <&vamacro>;
2503 clock-names = "mclk", 2412 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2504 2413
2505 #clock-cells = <0>; 2414 #clock-cells = <0>;
2506 clock-output-names = 2415 clock-output-names = "wsa2-mclk";
2507 #sound-dai-cells = <1 2416 #sound-dai-cells = <1>;
2508 }; 2417 };
2509 2418
2510 swr4: soundwire@31f0000 { 2419 swr4: soundwire@31f0000 {
2511 compatible = "qcom,so 2420 compatible = "qcom,soundwire-v1.7.0";
2512 reg = <0 0x031f0000 0 2421 reg = <0 0x031f0000 0 0x2000>;
2513 interrupts = <GIC_SPI 2422 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
2514 clocks = <&wsa2macro> 2423 clocks = <&wsa2macro>;
2515 clock-names = "iface" 2424 clock-names = "iface";
2516 label = "WSA2"; 2425 label = "WSA2";
2517 2426
2518 pinctrl-0 = <&wsa2_sw 2427 pinctrl-0 = <&wsa2_swr_active>;
2519 pinctrl-names = "defa 2428 pinctrl-names = "default";
2520 2429
2521 qcom,din-ports = <2>; 2430 qcom,din-ports = <2>;
2522 qcom,dout-ports = <6> 2431 qcom,dout-ports = <6>;
2523 2432
2524 qcom,ports-sinterval- 2433 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2525 qcom,ports-offset1 = 2434 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2526 qcom,ports-offset2 = 2435 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2527 qcom,ports-hstart = 2436 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2528 qcom,ports-hstop = 2437 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2529 qcom,ports-word-lengt 2438 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2530 qcom,ports-block-pack 2439 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
2531 qcom,ports-block-grou 2440 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2532 qcom,ports-lane-contr 2441 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2533 2442
2534 #address-cells = <2>; 2443 #address-cells = <2>;
2535 #size-cells = <0>; 2444 #size-cells = <0>;
2536 #sound-dai-cells = <1 2445 #sound-dai-cells = <1>;
2537 status = "disabled"; 2446 status = "disabled";
2538 }; 2447 };
2539 2448
2540 rxmacro: codec@3200000 { 2449 rxmacro: codec@3200000 {
2541 compatible = "qcom,sm 2450 compatible = "qcom,sm8450-lpass-rx-macro";
2542 reg = <0 0x03200000 0 2451 reg = <0 0x03200000 0 0x1000>;
2543 clocks = <&q6prmcc LP 2452 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2544 <&q6prmcc LP 2453 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2545 <&q6prmcc LP 2454 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2546 <&q6prmcc LP 2455 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2547 <&vamacro>; 2456 <&vamacro>;
2548 clock-names = "mclk", 2457 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2549 2458
2550 #clock-cells = <0>; 2459 #clock-cells = <0>;
2551 clock-output-names = 2460 clock-output-names = "mclk";
2552 #sound-dai-cells = <1 2461 #sound-dai-cells = <1>;
2553 }; 2462 };
2554 2463
2555 swr1: soundwire@3210000 { 2464 swr1: soundwire@3210000 {
2556 compatible = "qcom,so 2465 compatible = "qcom,soundwire-v1.7.0";
2557 reg = <0 0x03210000 0 2466 reg = <0 0x03210000 0 0x2000>;
2558 interrupts = <GIC_SPI 2467 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
2559 clocks = <&rxmacro>; 2468 clocks = <&rxmacro>;
2560 clock-names = "iface" 2469 clock-names = "iface";
2561 label = "RX"; 2470 label = "RX";
2562 qcom,din-ports = <0>; 2471 qcom,din-ports = <0>;
2563 qcom,dout-ports = <5> 2472 qcom,dout-ports = <5>;
2564 2473
2565 pinctrl-0 = <&rx_swr_ 2474 pinctrl-0 = <&rx_swr_active>;
2566 pinctrl-names = "defa 2475 pinctrl-names = "default";
2567 2476
2568 qcom,ports-sinterval- 2477 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
2569 qcom,ports-offset1 = 2478 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>;
2570 qcom,ports-offset2 = 2479 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
2571 qcom,ports-hstart = 2480 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
2572 qcom,ports-hstop = 2481 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
2573 qcom,ports-word-lengt 2482 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2574 qcom,ports-block-pack 2483 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
2575 qcom,ports-block-grou 2484 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
2576 qcom,ports-lane-contr 2485 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2577 2486
2578 #address-cells = <2>; 2487 #address-cells = <2>;
2579 #size-cells = <0>; 2488 #size-cells = <0>;
2580 #sound-dai-cells = <1 2489 #sound-dai-cells = <1>;
2581 status = "disabled"; 2490 status = "disabled";
2582 }; 2491 };
2583 2492
2584 txmacro: codec@3220000 { 2493 txmacro: codec@3220000 {
2585 compatible = "qcom,sm 2494 compatible = "qcom,sm8450-lpass-tx-macro";
2586 reg = <0 0x03220000 0 2495 reg = <0 0x03220000 0 0x1000>;
2587 clocks = <&q6prmcc LP 2496 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2588 <&q6prmcc LP 2497 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2589 <&q6prmcc LP 2498 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2590 <&q6prmcc LP 2499 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2591 <&vamacro>; 2500 <&vamacro>;
2592 clock-names = "mclk", 2501 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2593 2502
2594 #clock-cells = <0>; 2503 #clock-cells = <0>;
2595 clock-output-names = 2504 clock-output-names = "mclk";
2596 #sound-dai-cells = <1 2505 #sound-dai-cells = <1>;
2597 }; 2506 };
2598 2507
2599 wsamacro: codec@3240000 { 2508 wsamacro: codec@3240000 {
2600 compatible = "qcom,sm 2509 compatible = "qcom,sm8450-lpass-wsa-macro";
2601 reg = <0 0x03240000 0 2510 reg = <0 0x03240000 0 0x1000>;
2602 clocks = <&q6prmcc LP 2511 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2603 <&q6prmcc LP 2512 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2604 <&q6prmcc LP 2513 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2605 <&q6prmcc LP 2514 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2606 <&vamacro>; 2515 <&vamacro>;
2607 clock-names = "mclk", 2516 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2608 2517
2609 #clock-cells = <0>; 2518 #clock-cells = <0>;
2610 clock-output-names = 2519 clock-output-names = "mclk";
2611 #sound-dai-cells = <1 2520 #sound-dai-cells = <1>;
2612 }; 2521 };
2613 2522
2614 swr0: soundwire@3250000 { 2523 swr0: soundwire@3250000 {
2615 compatible = "qcom,so 2524 compatible = "qcom,soundwire-v1.7.0";
2616 reg = <0 0x03250000 0 2525 reg = <0 0x03250000 0 0x2000>;
2617 interrupts = <GIC_SPI 2526 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
2618 clocks = <&wsamacro>; 2527 clocks = <&wsamacro>;
2619 clock-names = "iface" 2528 clock-names = "iface";
2620 label = "WSA"; 2529 label = "WSA";
2621 2530
2622 pinctrl-0 = <&wsa_swr 2531 pinctrl-0 = <&wsa_swr_active>;
2623 pinctrl-names = "defa 2532 pinctrl-names = "default";
2624 2533
2625 qcom,din-ports = <2>; 2534 qcom,din-ports = <2>;
2626 qcom,dout-ports = <6> 2535 qcom,dout-ports = <6>;
2627 2536
2628 qcom,ports-sinterval- 2537 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2629 qcom,ports-offset1 = 2538 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2630 qcom,ports-offset2 = 2539 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2631 qcom,ports-hstart = 2540 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2632 qcom,ports-hstop = 2541 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2633 qcom,ports-word-lengt 2542 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2634 qcom,ports-block-pack 2543 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
2635 qcom,ports-block-grou 2544 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2636 qcom,ports-lane-contr 2545 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2637 2546
2638 #address-cells = <2>; 2547 #address-cells = <2>;
2639 #size-cells = <0>; 2548 #size-cells = <0>;
2640 #sound-dai-cells = <1 2549 #sound-dai-cells = <1>;
2641 status = "disabled"; 2550 status = "disabled";
2642 }; 2551 };
2643 2552
2644 swr2: soundwire@33b0000 { 2553 swr2: soundwire@33b0000 {
2645 compatible = "qcom,so 2554 compatible = "qcom,soundwire-v1.7.0";
2646 reg = <0 0x033b0000 0 2555 reg = <0 0x033b0000 0 0x2000>;
2647 interrupts = <GIC_SPI 2556 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
2648 <GIC_SPI 2557 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>;
2649 interrupt-names = "co 2558 interrupt-names = "core", "wakeup";
2650 2559
2651 clocks = <&txmacro>; 2560 clocks = <&txmacro>;
2652 clock-names = "iface" 2561 clock-names = "iface";
2653 label = "TX"; 2562 label = "TX";
2654 2563
2655 pinctrl-0 = <&tx_swr_ 2564 pinctrl-0 = <&tx_swr_active>;
2656 pinctrl-names = "defa 2565 pinctrl-names = "default";
2657 2566
2658 qcom,din-ports = <4>; 2567 qcom,din-ports = <4>;
2659 qcom,dout-ports = <0> 2568 qcom,dout-ports = <0>;
2660 qcom,ports-sinterval- 2569 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
2661 qcom,ports-offset1 = 2570 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>;
2662 qcom,ports-offset2 = 2571 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
2663 qcom,ports-hstart = 2572 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
2664 qcom,ports-hstop = 2573 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
2665 qcom,ports-word-lengt 2574 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
2666 qcom,ports-block-pack 2575 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
2667 qcom,ports-block-grou 2576 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
2668 qcom,ports-lane-contr 2577 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>;
2669 2578
2670 #address-cells = <2>; 2579 #address-cells = <2>;
2671 #size-cells = <0>; 2580 #size-cells = <0>;
2672 #sound-dai-cells = <1 2581 #sound-dai-cells = <1>;
2673 status = "disabled"; 2582 status = "disabled";
2674 }; 2583 };
2675 2584
2676 vamacro: codec@33f0000 { 2585 vamacro: codec@33f0000 {
2677 compatible = "qcom,sm 2586 compatible = "qcom,sm8450-lpass-va-macro";
2678 reg = <0 0x033f0000 0 2587 reg = <0 0x033f0000 0 0x1000>;
2679 clocks = <&q6prmcc LP 2588 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2680 <&q6prmcc LP 2589 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2681 <&q6prmcc LP 2590 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2682 <&q6prmcc LP 2591 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2683 clock-names = "mclk", 2592 clock-names = "mclk", "macro", "dcodec", "npl";
2684 2593
2685 #clock-cells = <0>; 2594 #clock-cells = <0>;
2686 clock-output-names = 2595 clock-output-names = "fsgen";
2687 #sound-dai-cells = <1 2596 #sound-dai-cells = <1>;
2688 status = "disabled"; 2597 status = "disabled";
2689 }; 2598 };
2690 2599
2691 remoteproc_adsp: remoteproc@3 2600 remoteproc_adsp: remoteproc@30000000 {
2692 compatible = "qcom,sm 2601 compatible = "qcom,sm8450-adsp-pas";
2693 reg = <0 0x30000000 0 2602 reg = <0 0x30000000 0 0x100>;
2694 2603
2695 interrupts-extended = 2604 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
2696 2605 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
2697 2606 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
2698 2607 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
2699 2608 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
2700 interrupt-names = "wd 2609 interrupt-names = "wdog", "fatal", "ready",
2701 "ha 2610 "handover", "stop-ack";
2702 2611
2703 clocks = <&rpmhcc RPM 2612 clocks = <&rpmhcc RPMH_CXO_CLK>;
2704 clock-names = "xo"; 2613 clock-names = "xo";
2705 2614
2706 power-domains = <&rpm 2615 power-domains = <&rpmhpd RPMHPD_LCX>,
2707 <&rpm 2616 <&rpmhpd RPMHPD_LMX>;
2708 power-domain-names = 2617 power-domain-names = "lcx", "lmx";
2709 2618
2710 memory-region = <&ads 2619 memory-region = <&adsp_mem>;
2711 2620
2712 qcom,qmp = <&aoss_qmp 2621 qcom,qmp = <&aoss_qmp>;
2713 2622
2714 qcom,smem-states = <& 2623 qcom,smem-states = <&smp2p_adsp_out 0>;
2715 qcom,smem-state-names 2624 qcom,smem-state-names = "stop";
2716 2625
2717 status = "disabled"; 2626 status = "disabled";
2718 2627
2719 remoteproc_adsp_glink 2628 remoteproc_adsp_glink: glink-edge {
2720 interrupts-ex 2629 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
2721 2630 IPCC_MPROC_SIGNAL_GLINK_QMP
2722 2631 IRQ_TYPE_EDGE_RISING>;
2723 mboxes = <&ip 2632 mboxes = <&ipcc IPCC_CLIENT_LPASS
2724 2633 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2725 2634
2726 label = "lpas 2635 label = "lpass";
2727 qcom,remote-p 2636 qcom,remote-pid = <2>;
2728 2637
2729 gpr { 2638 gpr {
2730 compa 2639 compatible = "qcom,gpr";
2731 qcom, 2640 qcom,glink-channels = "adsp_apps";
2732 qcom, 2641 qcom,domain = <GPR_DOMAIN_ID_ADSP>;
2733 qcom, 2642 qcom,intents = <512 20>;
2734 #addr 2643 #address-cells = <1>;
2735 #size 2644 #size-cells = <0>;
2736 2645
2737 q6apm 2646 q6apm: service@1 {
2738 2647 compatible = "qcom,q6apm";
2739 2648 reg = <GPR_APM_MODULE_IID>;
2740 2649 #sound-dai-cells = <0>;
2741 2650 qcom,protection-domain = "avs/audio",
2742 2651 "msm/adsp/audio_pd";
2743 2652
2744 2653 q6apmdai: dais {
2745 2654 compatible = "qcom,q6apm-dais";
2746 2655 iommus = <&apps_smmu 0x1801 0x0>;
2747 2656 };
2748 2657
2749 2658 q6apmbedai: bedais {
2750 2659 compatible = "qcom,q6apm-lpass-dais";
2751 2660 #sound-dai-cells = <1>;
2752 2661 };
2753 }; 2662 };
2754 2663
2755 q6prm 2664 q6prm: service@2 {
2756 2665 compatible = "qcom,q6prm";
2757 2666 reg = <GPR_PRM_MODULE_IID>;
2758 2667 qcom,protection-domain = "avs/audio",
2759 2668 "msm/adsp/audio_pd";
2760 2669
2761 2670 q6prmcc: clock-controller {
2762 2671 compatible = "qcom,q6prm-lpass-clocks";
2763 2672 #clock-cells = <2>;
2764 2673 };
2765 }; 2674 };
2766 }; 2675 };
2767 2676
2768 fastrpc { 2677 fastrpc {
2769 compa 2678 compatible = "qcom,fastrpc";
2770 qcom, 2679 qcom,glink-channels = "fastrpcglink-apps-dsp";
2771 label 2680 label = "adsp";
2772 qcom, 2681 qcom,non-secure-domain;
2773 #addr 2682 #address-cells = <1>;
2774 #size 2683 #size-cells = <0>;
2775 2684
2776 compu 2685 compute-cb@3 {
2777 2686 compatible = "qcom,fastrpc-compute-cb";
2778 2687 reg = <3>;
2779 2688 iommus = <&apps_smmu 0x1803 0x0>;
2780 }; 2689 };
2781 2690
2782 compu 2691 compute-cb@4 {
2783 2692 compatible = "qcom,fastrpc-compute-cb";
2784 2693 reg = <4>;
2785 2694 iommus = <&apps_smmu 0x1804 0x0>;
2786 }; 2695 };
2787 2696
2788 compu 2697 compute-cb@5 {
2789 2698 compatible = "qcom,fastrpc-compute-cb";
2790 2699 reg = <5>;
2791 2700 iommus = <&apps_smmu 0x1805 0x0>;
2792 }; 2701 };
2793 }; 2702 };
2794 }; 2703 };
2795 }; 2704 };
2796 2705
2797 remoteproc_cdsp: remoteproc@3 2706 remoteproc_cdsp: remoteproc@32300000 {
2798 compatible = "qcom,sm 2707 compatible = "qcom,sm8450-cdsp-pas";
2799 reg = <0 0x32300000 0 2708 reg = <0 0x32300000 0 0x1400000>;
2800 2709
2801 interrupts-extended = 2710 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
2802 2711 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
2803 2712 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
2804 2713 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
2805 2714 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
2806 interrupt-names = "wd 2715 interrupt-names = "wdog", "fatal", "ready",
2807 "ha 2716 "handover", "stop-ack";
2808 2717
2809 clocks = <&rpmhcc RPM 2718 clocks = <&rpmhcc RPMH_CXO_CLK>;
2810 clock-names = "xo"; 2719 clock-names = "xo";
2811 2720
2812 power-domains = <&rpm 2721 power-domains = <&rpmhpd RPMHPD_CX>,
2813 <&rpm 2722 <&rpmhpd RPMHPD_MXC>;
2814 power-domain-names = 2723 power-domain-names = "cx", "mxc";
2815 2724
2816 memory-region = <&cds 2725 memory-region = <&cdsp_mem>;
2817 2726
2818 qcom,qmp = <&aoss_qmp 2727 qcom,qmp = <&aoss_qmp>;
2819 2728
2820 qcom,smem-states = <& 2729 qcom,smem-states = <&smp2p_cdsp_out 0>;
2821 qcom,smem-state-names 2730 qcom,smem-state-names = "stop";
2822 2731
2823 status = "disabled"; 2732 status = "disabled";
2824 2733
2825 glink-edge { 2734 glink-edge {
2826 interrupts-ex 2735 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
2827 2736 IPCC_MPROC_SIGNAL_GLINK_QMP
2828 2737 IRQ_TYPE_EDGE_RISING>;
2829 mboxes = <&ip 2738 mboxes = <&ipcc IPCC_CLIENT_CDSP
2830 2739 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2831 2740
2832 label = "cdsp 2741 label = "cdsp";
2833 qcom,remote-p 2742 qcom,remote-pid = <5>;
2834 2743
2835 fastrpc { 2744 fastrpc {
2836 compa 2745 compatible = "qcom,fastrpc";
2837 qcom, 2746 qcom,glink-channels = "fastrpcglink-apps-dsp";
2838 label 2747 label = "cdsp";
2839 qcom, 2748 qcom,non-secure-domain;
2840 #addr 2749 #address-cells = <1>;
2841 #size 2750 #size-cells = <0>;
2842 2751
2843 compu 2752 compute-cb@1 {
2844 2753 compatible = "qcom,fastrpc-compute-cb";
2845 2754 reg = <1>;
2846 2755 iommus = <&apps_smmu 0x2161 0x0400>,
2847 2756 <&apps_smmu 0x1021 0x1420>;
2848 }; 2757 };
2849 2758
2850 compu 2759 compute-cb@2 {
2851 2760 compatible = "qcom,fastrpc-compute-cb";
2852 2761 reg = <2>;
2853 2762 iommus = <&apps_smmu 0x2162 0x0400>,
2854 2763 <&apps_smmu 0x1022 0x1420>;
2855 }; 2764 };
2856 2765
2857 compu 2766 compute-cb@3 {
2858 2767 compatible = "qcom,fastrpc-compute-cb";
2859 2768 reg = <3>;
2860 2769 iommus = <&apps_smmu 0x2163 0x0400>,
2861 2770 <&apps_smmu 0x1023 0x1420>;
2862 }; 2771 };
2863 2772
2864 compu 2773 compute-cb@4 {
2865 2774 compatible = "qcom,fastrpc-compute-cb";
2866 2775 reg = <4>;
2867 2776 iommus = <&apps_smmu 0x2164 0x0400>,
2868 2777 <&apps_smmu 0x1024 0x1420>;
2869 }; 2778 };
2870 2779
2871 compu 2780 compute-cb@5 {
2872 2781 compatible = "qcom,fastrpc-compute-cb";
2873 2782 reg = <5>;
2874 2783 iommus = <&apps_smmu 0x2165 0x0400>,
2875 2784 <&apps_smmu 0x1025 0x1420>;
2876 }; 2785 };
2877 2786
2878 compu 2787 compute-cb@6 {
2879 2788 compatible = "qcom,fastrpc-compute-cb";
2880 2789 reg = <6>;
2881 2790 iommus = <&apps_smmu 0x2166 0x0400>,
2882 2791 <&apps_smmu 0x1026 0x1420>;
2883 }; 2792 };
2884 2793
2885 compu 2794 compute-cb@7 {
2886 2795 compatible = "qcom,fastrpc-compute-cb";
2887 2796 reg = <7>;
2888 2797 iommus = <&apps_smmu 0x2167 0x0400>,
2889 2798 <&apps_smmu 0x1027 0x1420>;
2890 }; 2799 };
2891 2800
2892 compu 2801 compute-cb@8 {
2893 2802 compatible = "qcom,fastrpc-compute-cb";
2894 2803 reg = <8>;
2895 2804 iommus = <&apps_smmu 0x2168 0x0400>,
2896 2805 <&apps_smmu 0x1028 0x1420>;
2897 }; 2806 };
2898 2807
2899 /* no 2808 /* note: secure cb9 in downstream */
2900 }; 2809 };
2901 }; 2810 };
2902 }; 2811 };
2903 2812
2904 remoteproc_mpss: remoteproc@4 2813 remoteproc_mpss: remoteproc@4080000 {
2905 compatible = "qcom,sm 2814 compatible = "qcom,sm8450-mpss-pas";
2906 reg = <0x0 0x04080000 2815 reg = <0x0 0x04080000 0x0 0x4040>;
2907 2816
2908 interrupts-extended = 2817 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
2909 2818 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
2910 2819 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
2911 2820 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
2912 2821 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>,
2913 2822 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>;
2914 interrupt-names = "wd 2823 interrupt-names = "wdog", "fatal", "ready", "handover",
2915 "st 2824 "stop-ack", "shutdown-ack";
2916 2825
2917 clocks = <&rpmhcc RPM 2826 clocks = <&rpmhcc RPMH_CXO_CLK>;
2918 clock-names = "xo"; 2827 clock-names = "xo";
2919 2828
2920 power-domains = <&rpm 2829 power-domains = <&rpmhpd RPMHPD_CX>,
2921 <&rpm 2830 <&rpmhpd RPMHPD_MSS>;
2922 power-domain-names = 2831 power-domain-names = "cx", "mss";
2923 2832
2924 memory-region = <&mps 2833 memory-region = <&mpss_mem>;
2925 2834
2926 qcom,qmp = <&aoss_qmp 2835 qcom,qmp = <&aoss_qmp>;
2927 2836
2928 qcom,smem-states = <& 2837 qcom,smem-states = <&smp2p_modem_out 0>;
2929 qcom,smem-state-names 2838 qcom,smem-state-names = "stop";
2930 2839
2931 status = "disabled"; 2840 status = "disabled";
2932 2841
2933 glink-edge { 2842 glink-edge {
2934 interrupts-ex 2843 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
2935 2844 IPCC_MPROC_SIGNAL_GLINK_QMP
2936 2845 IRQ_TYPE_EDGE_RISING>;
2937 mboxes = <&ip 2846 mboxes = <&ipcc IPCC_CLIENT_MPSS
2938 2847 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2939 label = "mode 2848 label = "modem";
2940 qcom,remote-p 2849 qcom,remote-pid = <1>;
2941 }; 2850 };
2942 }; 2851 };
2943 2852
2944 videocc: clock-controller@aaf 2853 videocc: clock-controller@aaf0000 {
2945 compatible = "qcom,sm 2854 compatible = "qcom,sm8450-videocc";
2946 reg = <0 0x0aaf0000 0 2855 reg = <0 0x0aaf0000 0 0x10000>;
2947 clocks = <&rpmhcc RPM 2856 clocks = <&rpmhcc RPMH_CXO_CLK>,
2948 <&gcc GCC_VI 2857 <&gcc GCC_VIDEO_AHB_CLK>;
2949 power-domains = <&rpm 2858 power-domains = <&rpmhpd RPMHPD_MMCX>;
2950 required-opps = <&rpm 2859 required-opps = <&rpmhpd_opp_low_svs>;
2951 #clock-cells = <1>; 2860 #clock-cells = <1>;
2952 #reset-cells = <1>; 2861 #reset-cells = <1>;
2953 #power-domain-cells = 2862 #power-domain-cells = <1>;
2954 }; 2863 };
2955 2864
2956 cci0: cci@ac15000 { 2865 cci0: cci@ac15000 {
2957 compatible = "qcom,sm 2866 compatible = "qcom,sm8450-cci", "qcom,msm8996-cci";
2958 reg = <0 0x0ac15000 0 2867 reg = <0 0x0ac15000 0 0x1000>;
2959 interrupts = <GIC_SPI 2868 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
2960 power-domains = <&cam 2869 power-domains = <&camcc TITAN_TOP_GDSC>;
2961 2870
2962 clocks = <&camcc CAM_ 2871 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
2963 <&camcc CAM_ 2872 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
2964 <&camcc CAM_ 2873 <&camcc CAM_CC_CPAS_AHB_CLK>,
2965 <&camcc CAM_ 2874 <&camcc CAM_CC_CCI_0_CLK>,
2966 <&camcc CAM_ 2875 <&camcc CAM_CC_CCI_0_CLK_SRC>;
2967 clock-names = "camnoc 2876 clock-names = "camnoc_axi",
2968 "slow_a 2877 "slow_ahb_src",
2969 "cpas_a 2878 "cpas_ahb",
2970 "cci", 2879 "cci",
2971 "cci_sr 2880 "cci_src";
2972 pinctrl-0 = <&cci0_de 2881 pinctrl-0 = <&cci0_default &cci1_default>;
2973 pinctrl-1 = <&cci0_sl 2882 pinctrl-1 = <&cci0_sleep &cci1_sleep>;
2974 pinctrl-names = "defa 2883 pinctrl-names = "default", "sleep";
2975 2884
2976 status = "disabled"; 2885 status = "disabled";
2977 #address-cells = <1>; 2886 #address-cells = <1>;
2978 #size-cells = <0>; 2887 #size-cells = <0>;
2979 2888
2980 cci0_i2c0: i2c-bus@0 2889 cci0_i2c0: i2c-bus@0 {
2981 reg = <0>; 2890 reg = <0>;
2982 clock-frequen 2891 clock-frequency = <1000000>;
2983 #address-cell 2892 #address-cells = <1>;
2984 #size-cells = 2893 #size-cells = <0>;
2985 }; 2894 };
2986 2895
2987 cci0_i2c1: i2c-bus@1 2896 cci0_i2c1: i2c-bus@1 {
2988 reg = <1>; 2897 reg = <1>;
2989 clock-frequen 2898 clock-frequency = <1000000>;
2990 #address-cell 2899 #address-cells = <1>;
2991 #size-cells = 2900 #size-cells = <0>;
2992 }; 2901 };
2993 }; 2902 };
2994 2903
2995 cci1: cci@ac16000 { 2904 cci1: cci@ac16000 {
2996 compatible = "qcom,sm 2905 compatible = "qcom,sm8450-cci", "qcom,msm8996-cci";
2997 reg = <0 0x0ac16000 0 2906 reg = <0 0x0ac16000 0 0x1000>;
2998 interrupts = <GIC_SPI 2907 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>;
2999 power-domains = <&cam 2908 power-domains = <&camcc TITAN_TOP_GDSC>;
3000 2909
3001 clocks = <&camcc CAM_ 2910 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
3002 <&camcc CAM_ 2911 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
3003 <&camcc CAM_ 2912 <&camcc CAM_CC_CPAS_AHB_CLK>,
3004 <&camcc CAM_ 2913 <&camcc CAM_CC_CCI_1_CLK>,
3005 <&camcc CAM_ 2914 <&camcc CAM_CC_CCI_1_CLK_SRC>;
3006 clock-names = "camnoc 2915 clock-names = "camnoc_axi",
3007 "slow_a 2916 "slow_ahb_src",
3008 "cpas_a 2917 "cpas_ahb",
3009 "cci", 2918 "cci",
3010 "cci_sr 2919 "cci_src";
3011 pinctrl-0 = <&cci2_de 2920 pinctrl-0 = <&cci2_default &cci3_default>;
3012 pinctrl-1 = <&cci2_sl 2921 pinctrl-1 = <&cci2_sleep &cci3_sleep>;
3013 pinctrl-names = "defa 2922 pinctrl-names = "default", "sleep";
3014 2923
3015 status = "disabled"; 2924 status = "disabled";
3016 #address-cells = <1>; 2925 #address-cells = <1>;
3017 #size-cells = <0>; 2926 #size-cells = <0>;
3018 2927
3019 cci1_i2c0: i2c-bus@0 2928 cci1_i2c0: i2c-bus@0 {
3020 reg = <0>; 2929 reg = <0>;
3021 clock-frequen 2930 clock-frequency = <1000000>;
3022 #address-cell 2931 #address-cells = <1>;
3023 #size-cells = 2932 #size-cells = <0>;
3024 }; 2933 };
3025 2934
3026 cci1_i2c1: i2c-bus@1 2935 cci1_i2c1: i2c-bus@1 {
3027 reg = <1>; 2936 reg = <1>;
3028 clock-frequen 2937 clock-frequency = <1000000>;
3029 #address-cell 2938 #address-cells = <1>;
3030 #size-cells = 2939 #size-cells = <0>;
3031 }; 2940 };
3032 }; 2941 };
3033 2942
3034 camcc: clock-controller@ade00 2943 camcc: clock-controller@ade0000 {
3035 compatible = "qcom,sm 2944 compatible = "qcom,sm8450-camcc";
3036 reg = <0 0x0ade0000 0 2945 reg = <0 0x0ade0000 0 0x20000>;
3037 clocks = <&gcc GCC_CA 2946 clocks = <&gcc GCC_CAMERA_AHB_CLK>,
3038 <&rpmhcc RPM 2947 <&rpmhcc RPMH_CXO_CLK>,
3039 <&rpmhcc RPM 2948 <&rpmhcc RPMH_CXO_CLK_A>,
3040 <&sleep_clk> 2949 <&sleep_clk>;
3041 power-domains = <&rpm 2950 power-domains = <&rpmhpd RPMHPD_MMCX>;
3042 required-opps = <&rpm 2951 required-opps = <&rpmhpd_opp_low_svs>;
3043 #clock-cells = <1>; 2952 #clock-cells = <1>;
3044 #reset-cells = <1>; 2953 #reset-cells = <1>;
3045 #power-domain-cells = 2954 #power-domain-cells = <1>;
3046 status = "disabled"; 2955 status = "disabled";
3047 }; 2956 };
3048 2957
3049 mdss: display-subsystem@ae000 2958 mdss: display-subsystem@ae00000 {
3050 compatible = "qcom,sm 2959 compatible = "qcom,sm8450-mdss";
3051 reg = <0 0x0ae00000 0 2960 reg = <0 0x0ae00000 0 0x1000>;
3052 reg-names = "mdss"; 2961 reg-names = "mdss";
3053 2962
3054 /* same path used twi 2963 /* same path used twice */
3055 interconnects = <&mms 2964 interconnects = <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>,
3056 <&mms 2965 <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>,
3057 <&gem 2966 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
3058 &con 2967 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
3059 interconnect-names = 2968 interconnect-names = "mdp0-mem",
3060 2969 "mdp1-mem",
3061 2970 "cpu-cfg";
3062 2971
3063 resets = <&dispcc DIS 2972 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
3064 2973
3065 power-domains = <&dis 2974 power-domains = <&dispcc MDSS_GDSC>;
3066 2975
3067 clocks = <&dispcc DIS 2976 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3068 <&gcc GCC_DI 2977 <&gcc GCC_DISP_HF_AXI_CLK>,
3069 <&gcc GCC_DI 2978 <&gcc GCC_DISP_SF_AXI_CLK>,
3070 <&dispcc DIS 2979 <&dispcc DISP_CC_MDSS_MDP_CLK>;
3071 2980
3072 interrupts = <GIC_SPI 2981 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
3073 interrupt-controller; 2982 interrupt-controller;
3074 #interrupt-cells = <1 2983 #interrupt-cells = <1>;
3075 2984
3076 iommus = <&apps_smmu 2985 iommus = <&apps_smmu 0x2800 0x402>;
3077 2986
3078 #address-cells = <2>; 2987 #address-cells = <2>;
3079 #size-cells = <2>; 2988 #size-cells = <2>;
3080 ranges; 2989 ranges;
3081 2990
3082 status = "disabled"; 2991 status = "disabled";
3083 2992
3084 mdss_mdp: display-con 2993 mdss_mdp: display-controller@ae01000 {
3085 compatible = 2994 compatible = "qcom,sm8450-dpu";
3086 reg = <0 0x0a 2995 reg = <0 0x0ae01000 0 0x8f000>,
3087 <0 0x0a 2996 <0 0x0aeb0000 0 0x2008>;
3088 reg-names = " 2997 reg-names = "mdp", "vbif";
3089 2998
3090 clocks = <&gc 2999 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
3091 <&gcc 3000 <&gcc GCC_DISP_SF_AXI_CLK>,
3092 <&dis 3001 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3093 <&dis 3002 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
3094 <&dis 3003 <&dispcc DISP_CC_MDSS_MDP_CLK>,
3095 <&dis 3004 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3096 clock-names = 3005 clock-names = "bus",
3097 3006 "nrt_bus",
3098 3007 "iface",
3099 3008 "lut",
3100 3009 "core",
3101 3010 "vsync";
3102 3011
3103 assigned-cloc 3012 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3104 assigned-cloc 3013 assigned-clock-rates = <19200000>;
3105 3014
3106 operating-poi 3015 operating-points-v2 = <&mdp_opp_table>;
3107 power-domains 3016 power-domains = <&rpmhpd RPMHPD_MMCX>;
3108 3017
3109 interrupt-par 3018 interrupt-parent = <&mdss>;
3110 interrupts = 3019 interrupts = <0>;
3111 3020
3112 ports { 3021 ports {
3113 #addr 3022 #address-cells = <1>;
3114 #size 3023 #size-cells = <0>;
3115 3024
3116 port@ 3025 port@0 {
3117 3026 reg = <0>;
3118 3027 dpu_intf1_out: endpoint {
3119 3028 remote-endpoint = <&mdss_dsi0_in>;
3120 3029 };
3121 }; 3030 };
3122 3031
3123 port@ 3032 port@1 {
3124 3033 reg = <1>;
3125 3034 dpu_intf2_out: endpoint {
3126 3035 remote-endpoint = <&mdss_dsi1_in>;
3127 3036 };
3128 }; 3037 };
3129 3038
3130 port@ 3039 port@2 {
3131 3040 reg = <2>;
3132 3041 dpu_intf0_out: endpoint {
3133 3042 remote-endpoint = <&mdss_dp0_in>;
3134 3043 };
3135 }; 3044 };
3136 }; 3045 };
3137 3046
3138 mdp_opp_table 3047 mdp_opp_table: opp-table {
3139 compa 3048 compatible = "operating-points-v2";
3140 3049
3141 opp-1 3050 opp-172000000 {
3142 3051 opp-hz = /bits/ 64 <172000000>;
3143 3052 required-opps = <&rpmhpd_opp_low_svs_d1>;
3144 }; 3053 };
3145 3054
3146 opp-2 3055 opp-200000000 {
3147 3056 opp-hz = /bits/ 64 <200000000>;
3148 3057 required-opps = <&rpmhpd_opp_low_svs>;
3149 }; 3058 };
3150 3059
3151 opp-3 3060 opp-325000000 {
3152 3061 opp-hz = /bits/ 64 <325000000>;
3153 3062 required-opps = <&rpmhpd_opp_svs>;
3154 }; 3063 };
3155 3064
3156 opp-3 3065 opp-375000000 {
3157 3066 opp-hz = /bits/ 64 <375000000>;
3158 3067 required-opps = <&rpmhpd_opp_svs_l1>;
3159 }; 3068 };
3160 3069
3161 opp-5 3070 opp-500000000 {
3162 3071 opp-hz = /bits/ 64 <500000000>;
3163 3072 required-opps = <&rpmhpd_opp_nom>;
3164 }; 3073 };
3165 }; 3074 };
3166 }; 3075 };
3167 3076
3168 mdss_dp0: displayport 3077 mdss_dp0: displayport-controller@ae90000 {
3169 compatible = 3078 compatible = "qcom,sm8450-dp", "qcom,sm8350-dp";
3170 reg = <0 0xae 3079 reg = <0 0xae90000 0 0x200>,
3171 <0 0xae 3080 <0 0xae90200 0 0x200>,
3172 <0 0xae 3081 <0 0xae90400 0 0xc00>,
3173 <0 0xae 3082 <0 0xae91000 0 0x400>,
3174 <0 0xae 3083 <0 0xae91400 0 0x400>;
3175 interrupt-par 3084 interrupt-parent = <&mdss>;
3176 interrupts = 3085 interrupts = <12>;
3177 clocks = <&di 3086 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3178 <&di 3087 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
3179 <&di 3088 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
3180 <&di 3089 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
3181 <&di 3090 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
3182 clock-names = 3091 clock-names = "core_iface",
3183 3092 "core_aux",
3184 3093 "ctrl_link",
3185 3094 "ctrl_link_iface",
3186 3095 "stream_pixel";
3187 3096
3188 assigned-cloc 3097 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
3189 3098 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
3190 assigned-cloc 3099 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3191 3100 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
3192 3101
3193 phys = <&usb_ 3102 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
3194 phy-names = " 3103 phy-names = "dp";
3195 3104
3196 #sound-dai-ce 3105 #sound-dai-cells = <0>;
3197 3106
3198 operating-poi 3107 operating-points-v2 = <&dp_opp_table>;
3199 power-domains 3108 power-domains = <&rpmhpd RPMHPD_MMCX>;
3200 3109
3201 status = "dis 3110 status = "disabled";
3202 3111
3203 ports { 3112 ports {
3204 #addr 3113 #address-cells = <1>;
3205 #size 3114 #size-cells = <0>;
3206 3115
3207 port@ 3116 port@0 {
3208 3117 reg = <0>;
3209 3118 mdss_dp0_in: endpoint {
3210 3119 remote-endpoint = <&dpu_intf0_out>;
3211 3120 };
3212 }; 3121 };
3213 <<
3214 port@ <<
3215 <<
3216 <<
3217 <<
3218 <<
3219 <<
3220 }; <<
3221 }; 3122 };
3222 3123
3223 dp_opp_table: 3124 dp_opp_table: opp-table {
3224 compa 3125 compatible = "operating-points-v2";
3225 3126
3226 opp-1 3127 opp-160000000 {
3227 3128 opp-hz = /bits/ 64 <160000000>;
3228 3129 required-opps = <&rpmhpd_opp_low_svs>;
3229 }; 3130 };
3230 3131
3231 opp-2 3132 opp-270000000 {
3232 3133 opp-hz = /bits/ 64 <270000000>;
3233 3134 required-opps = <&rpmhpd_opp_svs>;
3234 }; 3135 };
3235 3136
3236 opp-5 3137 opp-540000000 {
3237 3138 opp-hz = /bits/ 64 <540000000>;
3238 3139 required-opps = <&rpmhpd_opp_svs_l1>;
3239 }; 3140 };
3240 3141
3241 opp-8 3142 opp-810000000 {
3242 3143 opp-hz = /bits/ 64 <810000000>;
3243 3144 required-opps = <&rpmhpd_opp_nom>;
3244 }; 3145 };
3245 }; 3146 };
3246 }; 3147 };
3247 3148
3248 mdss_dsi0: dsi@ae9400 3149 mdss_dsi0: dsi@ae94000 {
3249 compatible = 3150 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3250 reg = <0 0x0a 3151 reg = <0 0x0ae94000 0 0x400>;
3251 reg-names = " 3152 reg-names = "dsi_ctrl";
3252 3153
3253 interrupt-par 3154 interrupt-parent = <&mdss>;
3254 interrupts = 3155 interrupts = <4>;
3255 3156
3256 clocks = <&di 3157 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
3257 <&di 3158 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
3258 <&di 3159 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
3259 <&di 3160 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
3260 <&di 3161 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3261 <&gcc 3162 <&gcc GCC_DISP_HF_AXI_CLK>;
3262 clock-names = 3163 clock-names = "byte",
3263 3164 "byte_intf",
3264 3165 "pixel",
3265 3166 "core",
3266 3167 "iface",
3267 3168 "bus";
3268 3169
3269 assigned-cloc 3170 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
3270 assigned-cloc 3171 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
3271 3172
3272 operating-poi 3173 operating-points-v2 = <&mdss_dsi_opp_table>;
3273 power-domains 3174 power-domains = <&rpmhpd RPMHPD_MMCX>;
3274 3175
3275 phys = <&mdss 3176 phys = <&mdss_dsi0_phy>;
3276 phy-names = " 3177 phy-names = "dsi";
3277 3178
3278 #address-cell 3179 #address-cells = <1>;
3279 #size-cells = 3180 #size-cells = <0>;
3280 3181
3281 status = "dis 3182 status = "disabled";
3282 3183
3283 ports { 3184 ports {
3284 #addr 3185 #address-cells = <1>;
3285 #size 3186 #size-cells = <0>;
3286 3187
3287 port@ 3188 port@0 {
3288 3189 reg = <0>;
3289 3190 mdss_dsi0_in: endpoint {
3290 3191 remote-endpoint = <&dpu_intf1_out>;
3291 3192 };
3292 }; 3193 };
3293 3194
3294 port@ 3195 port@1 {
3295 3196 reg = <1>;
3296 3197 mdss_dsi0_out: endpoint {
3297 3198 };
3298 }; 3199 };
3299 }; 3200 };
3300 3201
3301 mdss_dsi_opp_ 3202 mdss_dsi_opp_table: opp-table {
3302 compa 3203 compatible = "operating-points-v2";
3303 3204
3304 opp-1 3205 opp-187500000 {
3305 3206 opp-hz = /bits/ 64 <187500000>;
3306 3207 required-opps = <&rpmhpd_opp_low_svs>;
3307 }; 3208 };
3308 3209
3309 opp-3 3210 opp-300000000 {
3310 3211 opp-hz = /bits/ 64 <300000000>;
3311 3212 required-opps = <&rpmhpd_opp_svs>;
3312 }; 3213 };
3313 3214
3314 opp-3 3215 opp-358000000 {
3315 3216 opp-hz = /bits/ 64 <358000000>;
3316 3217 required-opps = <&rpmhpd_opp_svs_l1>;
3317 }; 3218 };
3318 }; 3219 };
3319 }; 3220 };
3320 3221
3321 mdss_dsi0_phy: phy@ae 3222 mdss_dsi0_phy: phy@ae94400 {
3322 compatible = 3223 compatible = "qcom,sm8450-dsi-phy-5nm";
3323 reg = <0 0x0a 3224 reg = <0 0x0ae94400 0 0x200>,
3324 <0 0x0a 3225 <0 0x0ae94600 0 0x280>,
3325 <0 0x0a 3226 <0 0x0ae94900 0 0x260>;
3326 reg-names = " 3227 reg-names = "dsi_phy",
3327 " 3228 "dsi_phy_lane",
3328 " 3229 "dsi_pll";
3329 3230
3330 #clock-cells 3231 #clock-cells = <1>;
3331 #phy-cells = 3232 #phy-cells = <0>;
3332 3233
3333 clocks = <&di 3234 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3334 <&rp 3235 <&rpmhcc RPMH_CXO_CLK>;
3335 clock-names = 3236 clock-names = "iface", "ref";
3336 3237
3337 status = "dis 3238 status = "disabled";
3338 }; 3239 };
3339 3240
3340 mdss_dsi1: dsi@ae9600 3241 mdss_dsi1: dsi@ae96000 {
3341 compatible = 3242 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3342 reg = <0 0x0a 3243 reg = <0 0x0ae96000 0 0x400>;
3343 reg-names = " 3244 reg-names = "dsi_ctrl";
3344 3245
3345 interrupt-par 3246 interrupt-parent = <&mdss>;
3346 interrupts = 3247 interrupts = <5>;
3347 3248
3348 clocks = <&di 3249 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
3349 <&di 3250 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
3350 <&di 3251 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
3351 <&di 3252 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
3352 <&di 3253 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3353 <&gc 3254 <&gcc GCC_DISP_HF_AXI_CLK>;
3354 clock-names = 3255 clock-names = "byte",
3355 3256 "byte_intf",
3356 3257 "pixel",
3357 3258 "core",
3358 3259 "iface",
3359 3260 "bus";
3360 3261
3361 assigned-cloc 3262 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
3362 assigned-cloc 3263 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
3363 3264
3364 operating-poi 3265 operating-points-v2 = <&mdss_dsi_opp_table>;
3365 power-domains 3266 power-domains = <&rpmhpd RPMHPD_MMCX>;
3366 3267
3367 phys = <&mdss 3268 phys = <&mdss_dsi1_phy>;
3368 phy-names = " 3269 phy-names = "dsi";
3369 3270
3370 #address-cell 3271 #address-cells = <1>;
3371 #size-cells = 3272 #size-cells = <0>;
3372 3273
3373 status = "dis 3274 status = "disabled";
3374 3275
3375 ports { 3276 ports {
3376 #addr 3277 #address-cells = <1>;
3377 #size 3278 #size-cells = <0>;
3378 3279
3379 port@ 3280 port@0 {
3380 3281 reg = <0>;
3381 3282 mdss_dsi1_in: endpoint {
3382 3283 remote-endpoint = <&dpu_intf2_out>;
3383 3284 };
3384 }; 3285 };
3385 3286
3386 port@ 3287 port@1 {
3387 3288 reg = <1>;
3388 3289 mdss_dsi1_out: endpoint {
3389 3290 };
3390 }; 3291 };
3391 }; 3292 };
3392 }; 3293 };
3393 3294
3394 mdss_dsi1_phy: phy@ae 3295 mdss_dsi1_phy: phy@ae96400 {
3395 compatible = 3296 compatible = "qcom,sm8450-dsi-phy-5nm";
3396 reg = <0 0x0a 3297 reg = <0 0x0ae96400 0 0x200>,
3397 <0 0x0a 3298 <0 0x0ae96600 0 0x280>,
3398 <0 0x0a 3299 <0 0x0ae96900 0 0x260>;
3399 reg-names = " 3300 reg-names = "dsi_phy",
3400 " 3301 "dsi_phy_lane",
3401 " 3302 "dsi_pll";
3402 3303
3403 #clock-cells 3304 #clock-cells = <1>;
3404 #phy-cells = 3305 #phy-cells = <0>;
3405 3306
3406 clocks = <&di 3307 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3407 <&rp 3308 <&rpmhcc RPMH_CXO_CLK>;
3408 clock-names = 3309 clock-names = "iface", "ref";
3409 3310
3410 status = "dis 3311 status = "disabled";
3411 }; 3312 };
3412 }; 3313 };
3413 3314
3414 dispcc: clock-controller@af00 3315 dispcc: clock-controller@af00000 {
3415 compatible = "qcom,sm 3316 compatible = "qcom,sm8450-dispcc";
3416 reg = <0 0x0af00000 0 3317 reg = <0 0x0af00000 0 0x20000>;
3417 clocks = <&rpmhcc RPM 3318 clocks = <&rpmhcc RPMH_CXO_CLK>,
3418 <&rpmhcc RPM 3319 <&rpmhcc RPMH_CXO_CLK_A>,
3419 <&gcc GCC_DI 3320 <&gcc GCC_DISP_AHB_CLK>,
3420 <&sleep_clk> 3321 <&sleep_clk>,
3421 <&mdss_dsi0_ 3322 <&mdss_dsi0_phy 0>,
3422 <&mdss_dsi0_ 3323 <&mdss_dsi0_phy 1>,
3423 <&mdss_dsi1_ 3324 <&mdss_dsi1_phy 0>,
3424 <&mdss_dsi1_ 3325 <&mdss_dsi1_phy 1>,
3425 <&usb_1_qmpp 3326 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3426 <&usb_1_qmpp 3327 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
3427 <0>, /* dp1 3328 <0>, /* dp1 */
3428 <0>, 3329 <0>,
3429 <0>, /* dp2 3330 <0>, /* dp2 */
3430 <0>, 3331 <0>,
3431 <0>, /* dp3 3332 <0>, /* dp3 */
3432 <0>; 3333 <0>;
3433 power-domains = <&rpm 3334 power-domains = <&rpmhpd RPMHPD_MMCX>;
3434 required-opps = <&rpm 3335 required-opps = <&rpmhpd_opp_low_svs>;
3435 #clock-cells = <1>; 3336 #clock-cells = <1>;
3436 #reset-cells = <1>; 3337 #reset-cells = <1>;
3437 #power-domain-cells = 3338 #power-domain-cells = <1>;
3438 status = "disabled"; 3339 status = "disabled";
3439 }; 3340 };
3440 3341
3441 pdc: interrupt-controller@b22 3342 pdc: interrupt-controller@b220000 {
3442 compatible = "qcom,sm 3343 compatible = "qcom,sm8450-pdc", "qcom,pdc";
3443 reg = <0 0x0b220000 0 3344 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
3444 qcom,pdc-ranges = <0 3345 qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>,
3445 <94 3346 <94 609 31>, <125 63 1>, <126 716 12>;
3446 #interrupt-cells = <2 3347 #interrupt-cells = <2>;
3447 interrupt-parent = <& 3348 interrupt-parent = <&intc>;
3448 interrupt-controller; 3349 interrupt-controller;
3449 }; 3350 };
3450 3351
3451 tsens0: thermal-sensor@c26300 3352 tsens0: thermal-sensor@c263000 {
3452 compatible = "qcom,sm 3353 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2";
3453 reg = <0 0x0c263000 0 3354 reg = <0 0x0c263000 0 0x1000>, /* TM */
3454 <0 0x0c222000 0 3355 <0 0x0c222000 0 0x1000>; /* SROT */
3455 #qcom,sensors = <16>; 3356 #qcom,sensors = <16>;
3456 interrupts = <GIC_SPI 3357 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
3457 <GIC_SPI 3358 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
3458 interrupt-names = "up 3359 interrupt-names = "uplow", "critical";
3459 #thermal-sensor-cells 3360 #thermal-sensor-cells = <1>;
3460 }; 3361 };
3461 3362
3462 tsens1: thermal-sensor@c26500 3363 tsens1: thermal-sensor@c265000 {
3463 compatible = "qcom,sm 3364 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2";
3464 reg = <0 0x0c265000 0 3365 reg = <0 0x0c265000 0 0x1000>, /* TM */
3465 <0 0x0c223000 0 3366 <0 0x0c223000 0 0x1000>; /* SROT */
3466 #qcom,sensors = <16>; 3367 #qcom,sensors = <16>;
3467 interrupts = <GIC_SPI 3368 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
3468 <GIC_SPI 3369 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
3469 interrupt-names = "up 3370 interrupt-names = "uplow", "critical";
3470 #thermal-sensor-cells 3371 #thermal-sensor-cells = <1>;
3471 }; 3372 };
3472 3373
3473 aoss_qmp: power-management@c3 3374 aoss_qmp: power-management@c300000 {
3474 compatible = "qcom,sm 3375 compatible = "qcom,sm8450-aoss-qmp", "qcom,aoss-qmp";
3475 reg = <0 0x0c300000 0 3376 reg = <0 0x0c300000 0 0x400>;
3476 interrupts-extended = 3377 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
3477 3378 IRQ_TYPE_EDGE_RISING>;
3478 mboxes = <&ipcc IPCC_ 3379 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
3479 3380
3480 #clock-cells = <0>; 3381 #clock-cells = <0>;
3481 }; 3382 };
3482 3383
3483 sram@c3f0000 { 3384 sram@c3f0000 {
3484 compatible = "qcom,rp 3385 compatible = "qcom,rpmh-stats";
3485 reg = <0 0x0c3f0000 0 3386 reg = <0 0x0c3f0000 0 0x400>;
3486 }; 3387 };
3487 3388
3488 spmi_bus: spmi@c400000 { 3389 spmi_bus: spmi@c400000 {
3489 compatible = "qcom,sp 3390 compatible = "qcom,spmi-pmic-arb";
3490 reg = <0 0x0c400000 0 3391 reg = <0 0x0c400000 0 0x00003000>,
3491 <0 0x0c500000 0 3392 <0 0x0c500000 0 0x00400000>,
3492 <0 0x0c440000 0 3393 <0 0x0c440000 0 0x00080000>,
3493 <0 0x0c4c0000 0 3394 <0 0x0c4c0000 0 0x00010000>,
3494 <0 0x0c42d000 0 3395 <0 0x0c42d000 0 0x00010000>;
3495 reg-names = "core", 3396 reg-names = "core",
3496 "chnls", 3397 "chnls",
3497 "obsrvr", 3398 "obsrvr",
3498 "intr", 3399 "intr",
3499 "cnfg"; 3400 "cnfg";
3500 interrupt-names = "pe 3401 interrupt-names = "periph_irq";
3501 interrupts-extended = 3402 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3502 qcom,ee = <0>; 3403 qcom,ee = <0>;
3503 qcom,channel = <0>; 3404 qcom,channel = <0>;
3504 interrupt-controller; 3405 interrupt-controller;
3505 #interrupt-cells = <4 3406 #interrupt-cells = <4>;
3506 #address-cells = <2>; 3407 #address-cells = <2>;
3507 #size-cells = <0>; 3408 #size-cells = <0>;
3508 }; 3409 };
3509 3410
3510 ipcc: mailbox@ed18000 { 3411 ipcc: mailbox@ed18000 {
3511 compatible = "qcom,sm 3412 compatible = "qcom,sm8450-ipcc", "qcom,ipcc";
3512 reg = <0 0x0ed18000 0 3413 reg = <0 0x0ed18000 0 0x1000>;
3513 interrupts = <GIC_SPI 3414 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
3514 interrupt-controller; 3415 interrupt-controller;
3515 #interrupt-cells = <3 3416 #interrupt-cells = <3>;
3516 #mbox-cells = <2>; 3417 #mbox-cells = <2>;
3517 }; 3418 };
3518 3419
3519 tlmm: pinctrl@f100000 { 3420 tlmm: pinctrl@f100000 {
3520 compatible = "qcom,sm 3421 compatible = "qcom,sm8450-tlmm";
3521 reg = <0 0x0f100000 0 3422 reg = <0 0x0f100000 0 0x300000>;
3522 interrupts = <GIC_SPI 3423 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
3523 gpio-controller; 3424 gpio-controller;
3524 #gpio-cells = <2>; 3425 #gpio-cells = <2>;
3525 interrupt-controller; 3426 interrupt-controller;
3526 #interrupt-cells = <2 3427 #interrupt-cells = <2>;
3527 gpio-ranges = <&tlmm 3428 gpio-ranges = <&tlmm 0 0 211>;
3528 wakeup-parent = <&pdc 3429 wakeup-parent = <&pdc>;
3529 3430
3530 sdc2_default_state: s 3431 sdc2_default_state: sdc2-default-state {
3531 clk-pins { 3432 clk-pins {
3532 pins 3433 pins = "sdc2_clk";
3533 drive 3434 drive-strength = <16>;
3534 bias- 3435 bias-disable;
3535 }; 3436 };
3536 3437
3537 cmd-pins { 3438 cmd-pins {
3538 pins 3439 pins = "sdc2_cmd";
3539 drive 3440 drive-strength = <16>;
3540 bias- 3441 bias-pull-up;
3541 }; 3442 };
3542 3443
3543 data-pins { 3444 data-pins {
3544 pins 3445 pins = "sdc2_data";
3545 drive 3446 drive-strength = <16>;
3546 bias- 3447 bias-pull-up;
3547 }; 3448 };
3548 }; 3449 };
3549 3450
3550 sdc2_sleep_state: sdc 3451 sdc2_sleep_state: sdc2-sleep-state {
3551 clk-pins { 3452 clk-pins {
3552 pins 3453 pins = "sdc2_clk";
3553 drive 3454 drive-strength = <2>;
3554 bias- 3455 bias-disable;
3555 }; 3456 };
3556 3457
3557 cmd-pins { 3458 cmd-pins {
3558 pins 3459 pins = "sdc2_cmd";
3559 drive 3460 drive-strength = <2>;
3560 bias- 3461 bias-pull-up;
3561 }; 3462 };
3562 3463
3563 data-pins { 3464 data-pins {
3564 pins 3465 pins = "sdc2_data";
3565 drive 3466 drive-strength = <2>;
3566 bias- 3467 bias-pull-up;
3567 }; 3468 };
3568 }; 3469 };
3569 3470
3570 cci0_default: cci0-de 3471 cci0_default: cci0-default-state {
3571 /* SDA, SCL * 3472 /* SDA, SCL */
3572 pins = "gpio1 3473 pins = "gpio110", "gpio111";
3573 function = "c 3474 function = "cci_i2c";
3574 drive-strengt 3475 drive-strength = <2>;
3575 bias-pull-up; 3476 bias-pull-up;
3576 }; 3477 };
3577 3478
3578 cci0_sleep: cci0-slee 3479 cci0_sleep: cci0-sleep-state {
3579 /* SDA, SCL * 3480 /* SDA, SCL */
3580 pins = "gpio1 3481 pins = "gpio110", "gpio111";
3581 function = "c 3482 function = "cci_i2c";
3582 drive-strengt 3483 drive-strength = <2>;
3583 bias-pull-dow 3484 bias-pull-down;
3584 }; 3485 };
3585 3486
3586 cci1_default: cci1-de 3487 cci1_default: cci1-default-state {
3587 /* SDA, SCL * 3488 /* SDA, SCL */
3588 pins = "gpio1 3489 pins = "gpio112", "gpio113";
3589 function = "c 3490 function = "cci_i2c";
3590 drive-strengt 3491 drive-strength = <2>;
3591 bias-pull-up; 3492 bias-pull-up;
3592 }; 3493 };
3593 3494
3594 cci1_sleep: cci1-slee 3495 cci1_sleep: cci1-sleep-state {
3595 /* SDA, SCL * 3496 /* SDA, SCL */
3596 pins = "gpio1 3497 pins = "gpio112", "gpio113";
3597 function = "c 3498 function = "cci_i2c";
3598 drive-strengt 3499 drive-strength = <2>;
3599 bias-pull-dow 3500 bias-pull-down;
3600 }; 3501 };
3601 3502
3602 cci2_default: cci2-de 3503 cci2_default: cci2-default-state {
3603 /* SDA, SCL * 3504 /* SDA, SCL */
3604 pins = "gpio1 3505 pins = "gpio114", "gpio115";
3605 function = "c 3506 function = "cci_i2c";
3606 drive-strengt 3507 drive-strength = <2>;
3607 bias-pull-up; 3508 bias-pull-up;
3608 }; 3509 };
3609 3510
3610 cci2_sleep: cci2-slee 3511 cci2_sleep: cci2-sleep-state {
3611 /* SDA, SCL * 3512 /* SDA, SCL */
3612 pins = "gpio1 3513 pins = "gpio114", "gpio115";
3613 function = "c 3514 function = "cci_i2c";
3614 drive-strengt 3515 drive-strength = <2>;
3615 bias-pull-dow 3516 bias-pull-down;
3616 }; 3517 };
3617 3518
3618 cci3_default: cci3-de 3519 cci3_default: cci3-default-state {
3619 /* SDA, SCL * 3520 /* SDA, SCL */
3620 pins = "gpio2 3521 pins = "gpio208", "gpio209";
3621 function = "c 3522 function = "cci_i2c";
3622 drive-strengt 3523 drive-strength = <2>;
3623 bias-pull-up; 3524 bias-pull-up;
3624 }; 3525 };
3625 3526
3626 cci3_sleep: cci3-slee 3527 cci3_sleep: cci3-sleep-state {
3627 /* SDA, SCL * 3528 /* SDA, SCL */
3628 pins = "gpio2 3529 pins = "gpio208", "gpio209";
3629 function = "c 3530 function = "cci_i2c";
3630 drive-strengt 3531 drive-strength = <2>;
3631 bias-pull-dow 3532 bias-pull-down;
3632 }; 3533 };
3633 3534
3634 pcie0_default_state: 3535 pcie0_default_state: pcie0-default-state {
3635 perst-pins { 3536 perst-pins {
3636 pins 3537 pins = "gpio94";
3637 funct 3538 function = "gpio";
3638 drive 3539 drive-strength = <2>;
3639 bias- 3540 bias-pull-down;
3640 }; 3541 };
3641 3542
3642 clkreq-pins { 3543 clkreq-pins {
3643 pins 3544 pins = "gpio95";
3644 funct 3545 function = "pcie0_clkreqn";
3645 drive 3546 drive-strength = <2>;
3646 bias- 3547 bias-pull-up;
3647 }; 3548 };
3648 3549
3649 wake-pins { 3550 wake-pins {
3650 pins 3551 pins = "gpio96";
3651 funct 3552 function = "gpio";
3652 drive 3553 drive-strength = <2>;
3653 bias- 3554 bias-pull-up;
3654 }; 3555 };
3655 }; 3556 };
3656 3557
3657 pcie1_default_state: 3558 pcie1_default_state: pcie1-default-state {
3658 perst-pins { 3559 perst-pins {
3659 pins 3560 pins = "gpio97";
3660 funct 3561 function = "gpio";
3661 drive 3562 drive-strength = <2>;
3662 bias- 3563 bias-pull-down;
3663 }; 3564 };
3664 3565
3665 clkreq-pins { 3566 clkreq-pins {
3666 pins 3567 pins = "gpio98";
3667 funct 3568 function = "pcie1_clkreqn";
3668 drive 3569 drive-strength = <2>;
3669 bias- 3570 bias-pull-up;
3670 }; 3571 };
3671 3572
3672 wake-pins { 3573 wake-pins {
3673 pins 3574 pins = "gpio99";
3674 funct 3575 function = "gpio";
3675 drive 3576 drive-strength = <2>;
3676 bias- 3577 bias-pull-up;
3677 }; 3578 };
3678 }; 3579 };
3679 3580
3680 qup_i2c0_data_clk: qu 3581 qup_i2c0_data_clk: qup-i2c0-data-clk-state {
3681 pins = "gpio0 3582 pins = "gpio0", "gpio1";
3682 function = "q 3583 function = "qup0";
3683 }; 3584 };
3684 3585
3685 qup_i2c1_data_clk: qu 3586 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
3686 pins = "gpio4 3587 pins = "gpio4", "gpio5";
3687 function = "q 3588 function = "qup1";
3688 }; 3589 };
3689 3590
3690 qup_i2c2_data_clk: qu 3591 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
3691 pins = "gpio8 3592 pins = "gpio8", "gpio9";
3692 function = "q 3593 function = "qup2";
3693 }; 3594 };
3694 3595
3695 qup_i2c3_data_clk: qu 3596 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
3696 pins = "gpio1 3597 pins = "gpio12", "gpio13";
3697 function = "q 3598 function = "qup3";
3698 }; 3599 };
3699 3600
3700 qup_i2c4_data_clk: qu 3601 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
3701 pins = "gpio1 3602 pins = "gpio16", "gpio17";
3702 function = "q 3603 function = "qup4";
3703 }; 3604 };
3704 3605
3705 qup_i2c5_data_clk: qu 3606 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
3706 pins = "gpio2 3607 pins = "gpio206", "gpio207";
3707 function = "q 3608 function = "qup5";
3708 }; 3609 };
3709 3610
3710 qup_i2c6_data_clk: qu 3611 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
3711 pins = "gpio2 3612 pins = "gpio20", "gpio21";
3712 function = "q 3613 function = "qup6";
3713 }; 3614 };
3714 3615
3715 qup_i2c8_data_clk: qu 3616 qup_i2c8_data_clk: qup-i2c8-data-clk-state {
3716 pins = "gpio2 3617 pins = "gpio28", "gpio29";
3717 function = "q 3618 function = "qup8";
3718 }; 3619 };
3719 3620
3720 qup_i2c9_data_clk: qu 3621 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
3721 pins = "gpio3 3622 pins = "gpio32", "gpio33";
3722 function = "q 3623 function = "qup9";
3723 }; 3624 };
3724 3625
3725 qup_i2c10_data_clk: q 3626 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
3726 pins = "gpio3 3627 pins = "gpio36", "gpio37";
3727 function = "q 3628 function = "qup10";
3728 }; 3629 };
3729 3630
3730 qup_i2c11_data_clk: q 3631 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
3731 pins = "gpio4 3632 pins = "gpio40", "gpio41";
3732 function = "q 3633 function = "qup11";
3733 }; 3634 };
3734 3635
3735 qup_i2c12_data_clk: q 3636 qup_i2c12_data_clk: qup-i2c12-data-clk-state {
3736 pins = "gpio4 3637 pins = "gpio44", "gpio45";
3737 function = "q 3638 function = "qup12";
3738 }; 3639 };
3739 3640
3740 qup_i2c13_data_clk: q 3641 qup_i2c13_data_clk: qup-i2c13-data-clk-state {
3741 pins = "gpio4 3642 pins = "gpio48", "gpio49";
3742 function = "q 3643 function = "qup13";
3743 drive-strengt 3644 drive-strength = <2>;
3744 bias-pull-up; 3645 bias-pull-up;
3745 }; 3646 };
3746 3647
3747 qup_i2c14_data_clk: q 3648 qup_i2c14_data_clk: qup-i2c14-data-clk-state {
3748 pins = "gpio5 3649 pins = "gpio52", "gpio53";
3749 function = "q 3650 function = "qup14";
3750 drive-strengt 3651 drive-strength = <2>;
3751 bias-pull-up; 3652 bias-pull-up;
3752 }; 3653 };
3753 3654
3754 qup_i2c15_data_clk: q 3655 qup_i2c15_data_clk: qup-i2c15-data-clk-state {
3755 pins = "gpio5 3656 pins = "gpio56", "gpio57";
3756 function = "q 3657 function = "qup15";
3757 }; 3658 };
3758 3659
3759 qup_i2c16_data_clk: q 3660 qup_i2c16_data_clk: qup-i2c16-data-clk-state {
3760 pins = "gpio6 3661 pins = "gpio60", "gpio61";
3761 function = "q 3662 function = "qup16";
3762 }; 3663 };
3763 3664
3764 qup_i2c17_data_clk: q 3665 qup_i2c17_data_clk: qup-i2c17-data-clk-state {
3765 pins = "gpio6 3666 pins = "gpio64", "gpio65";
3766 function = "q 3667 function = "qup17";
3767 }; 3668 };
3768 3669
3769 qup_i2c18_data_clk: q 3670 qup_i2c18_data_clk: qup-i2c18-data-clk-state {
3770 pins = "gpio6 3671 pins = "gpio68", "gpio69";
3771 function = "q 3672 function = "qup18";
3772 }; 3673 };
3773 3674
3774 qup_i2c19_data_clk: q 3675 qup_i2c19_data_clk: qup-i2c19-data-clk-state {
3775 pins = "gpio7 3676 pins = "gpio72", "gpio73";
3776 function = "q 3677 function = "qup19";
3777 }; 3678 };
3778 3679
3779 qup_i2c20_data_clk: q 3680 qup_i2c20_data_clk: qup-i2c20-data-clk-state {
3780 pins = "gpio7 3681 pins = "gpio76", "gpio77";
3781 function = "q 3682 function = "qup20";
3782 }; 3683 };
3783 3684
3784 qup_i2c21_data_clk: q 3685 qup_i2c21_data_clk: qup-i2c21-data-clk-state {
3785 pins = "gpio8 3686 pins = "gpio80", "gpio81";
3786 function = "q 3687 function = "qup21";
3787 }; 3688 };
3788 3689
3789 qup_spi0_cs: qup-spi0 3690 qup_spi0_cs: qup-spi0-cs-state {
3790 pins = "gpio3 3691 pins = "gpio3";
3791 function = "q 3692 function = "qup0";
3792 }; 3693 };
3793 3694
3794 qup_spi0_data_clk: qu 3695 qup_spi0_data_clk: qup-spi0-data-clk-state {
3795 pins = "gpio0 3696 pins = "gpio0", "gpio1", "gpio2";
3796 function = "q 3697 function = "qup0";
3797 }; 3698 };
3798 3699
3799 qup_spi1_cs: qup-spi1 3700 qup_spi1_cs: qup-spi1-cs-state {
3800 pins = "gpio7 3701 pins = "gpio7";
3801 function = "q 3702 function = "qup1";
3802 }; 3703 };
3803 3704
3804 qup_spi1_data_clk: qu 3705 qup_spi1_data_clk: qup-spi1-data-clk-state {
3805 pins = "gpio4 3706 pins = "gpio4", "gpio5", "gpio6";
3806 function = "q 3707 function = "qup1";
3807 }; 3708 };
3808 3709
3809 qup_spi2_cs: qup-spi2 3710 qup_spi2_cs: qup-spi2-cs-state {
3810 pins = "gpio1 3711 pins = "gpio11";
3811 function = "q 3712 function = "qup2";
3812 }; 3713 };
3813 3714
3814 qup_spi2_data_clk: qu 3715 qup_spi2_data_clk: qup-spi2-data-clk-state {
3815 pins = "gpio8 3716 pins = "gpio8", "gpio9", "gpio10";
3816 function = "q 3717 function = "qup2";
3817 }; 3718 };
3818 3719
3819 qup_spi3_cs: qup-spi3 3720 qup_spi3_cs: qup-spi3-cs-state {
3820 pins = "gpio1 3721 pins = "gpio15";
3821 function = "q 3722 function = "qup3";
3822 }; 3723 };
3823 3724
3824 qup_spi3_data_clk: qu 3725 qup_spi3_data_clk: qup-spi3-data-clk-state {
3825 pins = "gpio1 3726 pins = "gpio12", "gpio13", "gpio14";
3826 function = "q 3727 function = "qup3";
3827 }; 3728 };
3828 3729
3829 qup_spi4_cs: qup-spi4 3730 qup_spi4_cs: qup-spi4-cs-state {
3830 pins = "gpio1 3731 pins = "gpio19";
3831 function = "q 3732 function = "qup4";
3832 drive-strengt 3733 drive-strength = <6>;
3833 bias-disable; 3734 bias-disable;
3834 }; 3735 };
3835 3736
3836 qup_spi4_data_clk: qu 3737 qup_spi4_data_clk: qup-spi4-data-clk-state {
3837 pins = "gpio1 3738 pins = "gpio16", "gpio17", "gpio18";
3838 function = "q 3739 function = "qup4";
3839 }; 3740 };
3840 3741
3841 qup_spi5_cs: qup-spi5 3742 qup_spi5_cs: qup-spi5-cs-state {
3842 pins = "gpio8 3743 pins = "gpio85";
3843 function = "q 3744 function = "qup5";
3844 }; 3745 };
3845 3746
3846 qup_spi5_data_clk: qu 3747 qup_spi5_data_clk: qup-spi5-data-clk-state {
3847 pins = "gpio2 3748 pins = "gpio206", "gpio207", "gpio84";
3848 function = "q 3749 function = "qup5";
3849 }; 3750 };
3850 3751
3851 qup_spi6_cs: qup-spi6 3752 qup_spi6_cs: qup-spi6-cs-state {
3852 pins = "gpio2 3753 pins = "gpio23";
3853 function = "q 3754 function = "qup6";
3854 }; 3755 };
3855 3756
3856 qup_spi6_data_clk: qu 3757 qup_spi6_data_clk: qup-spi6-data-clk-state {
3857 pins = "gpio2 3758 pins = "gpio20", "gpio21", "gpio22";
3858 function = "q 3759 function = "qup6";
3859 }; 3760 };
3860 3761
3861 qup_spi8_cs: qup-spi8 3762 qup_spi8_cs: qup-spi8-cs-state {
3862 pins = "gpio3 3763 pins = "gpio31";
3863 function = "q 3764 function = "qup8";
3864 }; 3765 };
3865 3766
3866 qup_spi8_data_clk: qu 3767 qup_spi8_data_clk: qup-spi8-data-clk-state {
3867 pins = "gpio2 3768 pins = "gpio28", "gpio29", "gpio30";
3868 function = "q 3769 function = "qup8";
3869 }; 3770 };
3870 3771
3871 qup_spi9_cs: qup-spi9 3772 qup_spi9_cs: qup-spi9-cs-state {
3872 pins = "gpio3 3773 pins = "gpio35";
3873 function = "q 3774 function = "qup9";
3874 }; 3775 };
3875 3776
3876 qup_spi9_data_clk: qu 3777 qup_spi9_data_clk: qup-spi9-data-clk-state {
3877 pins = "gpio3 3778 pins = "gpio32", "gpio33", "gpio34";
3878 function = "q 3779 function = "qup9";
3879 }; 3780 };
3880 3781
3881 qup_spi10_cs: qup-spi 3782 qup_spi10_cs: qup-spi10-cs-state {
3882 pins = "gpio3 3783 pins = "gpio39";
3883 function = "q 3784 function = "qup10";
3884 }; 3785 };
3885 3786
3886 qup_spi10_data_clk: q 3787 qup_spi10_data_clk: qup-spi10-data-clk-state {
3887 pins = "gpio3 3788 pins = "gpio36", "gpio37", "gpio38";
3888 function = "q 3789 function = "qup10";
3889 }; 3790 };
3890 3791
3891 qup_spi11_cs: qup-spi 3792 qup_spi11_cs: qup-spi11-cs-state {
3892 pins = "gpio4 3793 pins = "gpio43";
3893 function = "q 3794 function = "qup11";
3894 }; 3795 };
3895 3796
3896 qup_spi11_data_clk: q 3797 qup_spi11_data_clk: qup-spi11-data-clk-state {
3897 pins = "gpio4 3798 pins = "gpio40", "gpio41", "gpio42";
3898 function = "q 3799 function = "qup11";
3899 }; 3800 };
3900 3801
3901 qup_spi12_cs: qup-spi 3802 qup_spi12_cs: qup-spi12-cs-state {
3902 pins = "gpio4 3803 pins = "gpio47";
3903 function = "q 3804 function = "qup12";
3904 }; 3805 };
3905 3806
3906 qup_spi12_data_clk: q 3807 qup_spi12_data_clk: qup-spi12-data-clk-state {
3907 pins = "gpio4 3808 pins = "gpio44", "gpio45", "gpio46";
3908 function = "q 3809 function = "qup12";
3909 }; 3810 };
3910 3811
3911 qup_spi13_cs: qup-spi 3812 qup_spi13_cs: qup-spi13-cs-state {
3912 pins = "gpio5 3813 pins = "gpio51";
3913 function = "q 3814 function = "qup13";
3914 }; 3815 };
3915 3816
3916 qup_spi13_data_clk: q 3817 qup_spi13_data_clk: qup-spi13-data-clk-state {
3917 pins = "gpio4 3818 pins = "gpio48", "gpio49", "gpio50";
3918 function = "q 3819 function = "qup13";
3919 }; 3820 };
3920 3821
3921 qup_spi14_cs: qup-spi 3822 qup_spi14_cs: qup-spi14-cs-state {
3922 pins = "gpio5 3823 pins = "gpio55";
3923 function = "q 3824 function = "qup14";
3924 }; 3825 };
3925 3826
3926 qup_spi14_data_clk: q 3827 qup_spi14_data_clk: qup-spi14-data-clk-state {
3927 pins = "gpio5 3828 pins = "gpio52", "gpio53", "gpio54";
3928 function = "q 3829 function = "qup14";
3929 }; 3830 };
3930 3831
3931 qup_spi15_cs: qup-spi 3832 qup_spi15_cs: qup-spi15-cs-state {
3932 pins = "gpio5 3833 pins = "gpio59";
3933 function = "q 3834 function = "qup15";
3934 }; 3835 };
3935 3836
3936 qup_spi15_data_clk: q 3837 qup_spi15_data_clk: qup-spi15-data-clk-state {
3937 pins = "gpio5 3838 pins = "gpio56", "gpio57", "gpio58";
3938 function = "q 3839 function = "qup15";
3939 }; 3840 };
3940 3841
3941 qup_spi16_cs: qup-spi 3842 qup_spi16_cs: qup-spi16-cs-state {
3942 pins = "gpio6 3843 pins = "gpio63";
3943 function = "q 3844 function = "qup16";
3944 }; 3845 };
3945 3846
3946 qup_spi16_data_clk: q 3847 qup_spi16_data_clk: qup-spi16-data-clk-state {
3947 pins = "gpio6 3848 pins = "gpio60", "gpio61", "gpio62";
3948 function = "q 3849 function = "qup16";
3949 }; 3850 };
3950 3851
3951 qup_spi17_cs: qup-spi 3852 qup_spi17_cs: qup-spi17-cs-state {
3952 pins = "gpio6 3853 pins = "gpio67";
3953 function = "q 3854 function = "qup17";
3954 }; 3855 };
3955 3856
3956 qup_spi17_data_clk: q 3857 qup_spi17_data_clk: qup-spi17-data-clk-state {
3957 pins = "gpio6 3858 pins = "gpio64", "gpio65", "gpio66";
3958 function = "q 3859 function = "qup17";
3959 }; 3860 };
3960 3861
3961 qup_spi18_cs: qup-spi 3862 qup_spi18_cs: qup-spi18-cs-state {
3962 pins = "gpio7 3863 pins = "gpio71";
3963 function = "q 3864 function = "qup18";
3964 drive-strengt 3865 drive-strength = <6>;
3965 bias-disable; 3866 bias-disable;
3966 }; 3867 };
3967 3868
3968 qup_spi18_data_clk: q 3869 qup_spi18_data_clk: qup-spi18-data-clk-state {
3969 pins = "gpio6 3870 pins = "gpio68", "gpio69", "gpio70";
3970 function = "q 3871 function = "qup18";
3971 drive-strengt 3872 drive-strength = <6>;
3972 bias-disable; 3873 bias-disable;
3973 }; 3874 };
3974 3875
3975 qup_spi19_cs: qup-spi 3876 qup_spi19_cs: qup-spi19-cs-state {
3976 pins = "gpio7 3877 pins = "gpio75";
3977 function = "q 3878 function = "qup19";
3978 drive-strengt 3879 drive-strength = <6>;
3979 bias-disable; 3880 bias-disable;
3980 }; 3881 };
3981 3882
3982 qup_spi19_data_clk: q 3883 qup_spi19_data_clk: qup-spi19-data-clk-state {
3983 pins = "gpio7 3884 pins = "gpio72", "gpio73", "gpio74";
3984 function = "q 3885 function = "qup19";
3985 drive-strengt 3886 drive-strength = <6>;
3986 bias-disable; 3887 bias-disable;
3987 }; 3888 };
3988 3889
3989 qup_spi20_cs: qup-spi 3890 qup_spi20_cs: qup-spi20-cs-state {
3990 pins = "gpio7 3891 pins = "gpio79";
3991 function = "q 3892 function = "qup20";
3992 }; 3893 };
3993 3894
3994 qup_spi20_data_clk: q 3895 qup_spi20_data_clk: qup-spi20-data-clk-state {
3995 pins = "gpio7 3896 pins = "gpio76", "gpio77", "gpio78";
3996 function = "q 3897 function = "qup20";
3997 }; 3898 };
3998 3899
3999 qup_spi21_cs: qup-spi 3900 qup_spi21_cs: qup-spi21-cs-state {
4000 pins = "gpio8 3901 pins = "gpio83";
4001 function = "q 3902 function = "qup21";
4002 }; 3903 };
4003 3904
4004 qup_spi21_data_clk: q 3905 qup_spi21_data_clk: qup-spi21-data-clk-state {
4005 pins = "gpio8 3906 pins = "gpio80", "gpio81", "gpio82";
4006 function = "q 3907 function = "qup21";
4007 }; 3908 };
4008 3909
4009 qup_uart7_rx: qup-uar 3910 qup_uart7_rx: qup-uart7-rx-state {
4010 pins = "gpio2 3911 pins = "gpio26";
4011 function = "q 3912 function = "qup7";
4012 drive-strengt 3913 drive-strength = <2>;
4013 bias-disable; 3914 bias-disable;
4014 }; 3915 };
4015 3916
4016 qup_uart7_tx: qup-uar 3917 qup_uart7_tx: qup-uart7-tx-state {
4017 pins = "gpio2 3918 pins = "gpio27";
4018 function = "q 3919 function = "qup7";
4019 drive-strengt 3920 drive-strength = <2>;
4020 bias-disable; 3921 bias-disable;
4021 }; 3922 };
4022 3923
4023 qup_uart20_default: q 3924 qup_uart20_default: qup-uart20-default-state {
4024 pins = "gpio7 3925 pins = "gpio76", "gpio77", "gpio78", "gpio79";
4025 function = "q 3926 function = "qup20";
4026 }; 3927 };
4027 }; 3928 };
4028 3929
4029 lpass_tlmm: pinctrl@3440000 { 3930 lpass_tlmm: pinctrl@3440000 {
4030 compatible = "qcom,sm 3931 compatible = "qcom,sm8450-lpass-lpi-pinctrl";
4031 reg = <0 0x03440000 0 3932 reg = <0 0x03440000 0x0 0x20000>,
4032 <0 0x034d0000 0 3933 <0 0x034d0000 0x0 0x10000>;
4033 gpio-controller; 3934 gpio-controller;
4034 #gpio-cells = <2>; 3935 #gpio-cells = <2>;
4035 gpio-ranges = <&lpass 3936 gpio-ranges = <&lpass_tlmm 0 0 23>;
4036 3937
4037 clocks = <&q6prmcc LP 3938 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
4038 <&q6prmcc LP 3939 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
4039 clock-names = "core", 3940 clock-names = "core", "audio";
4040 3941
4041 tx_swr_active: tx-swr 3942 tx_swr_active: tx-swr-active-state {
4042 clk-pins { 3943 clk-pins {
4043 pins 3944 pins = "gpio0";
4044 funct 3945 function = "swr_tx_clk";
4045 drive 3946 drive-strength = <2>;
4046 slew- 3947 slew-rate = <1>;
4047 bias- 3948 bias-disable;
4048 }; 3949 };
4049 3950
4050 data-pins { 3951 data-pins {
4051 pins 3952 pins = "gpio1", "gpio2", "gpio14";
4052 funct 3953 function = "swr_tx_data";
4053 drive 3954 drive-strength = <2>;
4054 slew- 3955 slew-rate = <1>;
4055 bias- 3956 bias-bus-hold;
4056 }; 3957 };
4057 }; 3958 };
4058 3959
4059 rx_swr_active: rx-swr 3960 rx_swr_active: rx-swr-active-state {
4060 clk-pins { 3961 clk-pins {
4061 pins 3962 pins = "gpio3";
4062 funct 3963 function = "swr_rx_clk";
4063 drive 3964 drive-strength = <2>;
4064 slew- 3965 slew-rate = <1>;
4065 bias- 3966 bias-disable;
4066 }; 3967 };
4067 3968
4068 data-pins { 3969 data-pins {
4069 pins 3970 pins = "gpio4", "gpio5";
4070 funct 3971 function = "swr_rx_data";
4071 drive 3972 drive-strength = <2>;
4072 slew- 3973 slew-rate = <1>;
4073 bias- 3974 bias-bus-hold;
4074 }; 3975 };
4075 }; 3976 };
4076 3977
4077 dmic01_default: dmic0 3978 dmic01_default: dmic01-default-state {
4078 clk-pins { 3979 clk-pins {
4079 pins 3980 pins = "gpio6";
4080 funct 3981 function = "dmic1_clk";
4081 drive 3982 drive-strength = <8>;
4082 outpu 3983 output-high;
4083 }; 3984 };
4084 3985
4085 data-pins { 3986 data-pins {
4086 pins 3987 pins = "gpio7";
4087 funct 3988 function = "dmic1_data";
4088 drive 3989 drive-strength = <8>;
4089 }; 3990 };
4090 }; 3991 };
4091 3992
4092 dmic23_default: dmic2 3993 dmic23_default: dmic23-default-state {
4093 clk-pins { 3994 clk-pins {
4094 pins 3995 pins = "gpio8";
4095 funct 3996 function = "dmic2_clk";
4096 drive 3997 drive-strength = <8>;
4097 outpu 3998 output-high;
4098 }; 3999 };
4099 4000
4100 data-pins { 4001 data-pins {
4101 pins 4002 pins = "gpio9";
4102 funct 4003 function = "dmic2_data";
4103 drive 4004 drive-strength = <8>;
4104 }; 4005 };
4105 }; 4006 };
4106 4007
4107 wsa_swr_active: wsa-s 4008 wsa_swr_active: wsa-swr-active-state {
4108 clk-pins { 4009 clk-pins {
4109 pins 4010 pins = "gpio10";
4110 funct 4011 function = "wsa_swr_clk";
4111 drive 4012 drive-strength = <2>;
4112 slew- 4013 slew-rate = <1>;
4113 bias- 4014 bias-disable;
4114 }; 4015 };
4115 4016
4116 data-pins { 4017 data-pins {
4117 pins 4018 pins = "gpio11";
4118 funct 4019 function = "wsa_swr_data";
4119 drive 4020 drive-strength = <2>;
4120 slew- 4021 slew-rate = <1>;
4121 bias- 4022 bias-bus-hold;
4122 }; 4023 };
4123 }; 4024 };
4124 4025
4125 wsa2_swr_active: wsa2 4026 wsa2_swr_active: wsa2-swr-active-state {
4126 clk-pins { 4027 clk-pins {
4127 pins 4028 pins = "gpio15";
4128 funct 4029 function = "wsa2_swr_clk";
4129 drive 4030 drive-strength = <2>;
4130 slew- 4031 slew-rate = <1>;
4131 bias- 4032 bias-disable;
4132 }; 4033 };
4133 4034
4134 data-pins { 4035 data-pins {
4135 pins 4036 pins = "gpio16";
4136 funct 4037 function = "wsa2_swr_data";
4137 drive 4038 drive-strength = <2>;
4138 slew- 4039 slew-rate = <1>;
4139 bias- 4040 bias-bus-hold;
4140 }; 4041 };
4141 }; 4042 };
4142 }; 4043 };
4143 4044
4144 sram@146aa000 { 4045 sram@146aa000 {
4145 compatible = "qcom,sm 4046 compatible = "qcom,sm8450-imem", "syscon", "simple-mfd";
4146 reg = <0 0x146aa000 0 4047 reg = <0 0x146aa000 0 0x1000>;
4147 ranges = <0 0 0x146aa 4048 ranges = <0 0 0x146aa000 0x1000>;
4148 4049
4149 #address-cells = <1>; 4050 #address-cells = <1>;
4150 #size-cells = <1>; 4051 #size-cells = <1>;
4151 4052
4152 pil-reloc@94c { 4053 pil-reloc@94c {
4153 compatible = 4054 compatible = "qcom,pil-reloc-info";
4154 reg = <0x94c 4055 reg = <0x94c 0xc8>;
4155 }; 4056 };
4156 }; 4057 };
4157 4058
4158 apps_smmu: iommu@15000000 { 4059 apps_smmu: iommu@15000000 {
4159 compatible = "qcom,sm 4060 compatible = "qcom,sm8450-smmu-500", "arm,mmu-500";
4160 reg = <0 0x15000000 0 4061 reg = <0 0x15000000 0 0x100000>;
4161 #iommu-cells = <2>; 4062 #iommu-cells = <2>;
4162 #global-interrupts = 4063 #global-interrupts = <1>;
4163 interrupts = <GIC_SPI 4064 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
4164 <GIC_SPI 4065 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
4165 <GIC_SPI 4066 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
4166 <GIC_SPI 4067 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
4167 <GIC_SPI 4068 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
4168 <GIC_SPI 4069 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
4169 <GIC_SPI 4070 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
4170 <GIC_SPI 4071 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
4171 <GIC_SPI 4072 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
4172 <GIC_SPI 4073 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
4173 <GIC_SPI 4074 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
4174 <GIC_SPI 4075 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
4175 <GIC_SPI 4076 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
4176 <GIC_SPI 4077 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
4177 <GIC_SPI 4078 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
4178 <GIC_SPI 4079 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
4179 <GIC_SPI 4080 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
4180 <GIC_SPI 4081 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
4181 <GIC_SPI 4082 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
4182 <GIC_SPI 4083 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
4183 <GIC_SPI 4084 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
4184 <GIC_SPI 4085 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
4185 <GIC_SPI 4086 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
4186 <GIC_SPI 4087 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
4187 <GIC_SPI 4088 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
4188 <GIC_SPI 4089 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
4189 <GIC_SPI 4090 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
4190 <GIC_SPI 4091 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
4191 <GIC_SPI 4092 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
4192 <GIC_SPI 4093 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
4193 <GIC_SPI 4094 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
4194 <GIC_SPI 4095 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
4195 <GIC_SPI 4096 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
4196 <GIC_SPI 4097 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
4197 <GIC_SPI 4098 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
4198 <GIC_SPI 4099 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
4199 <GIC_SPI 4100 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
4200 <GIC_SPI 4101 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
4201 <GIC_SPI 4102 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
4202 <GIC_SPI 4103 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
4203 <GIC_SPI 4104 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
4204 <GIC_SPI 4105 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
4205 <GIC_SPI 4106 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
4206 <GIC_SPI 4107 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
4207 <GIC_SPI 4108 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
4208 <GIC_SPI 4109 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
4209 <GIC_SPI 4110 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
4210 <GIC_SPI 4111 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
4211 <GIC_SPI 4112 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
4212 <GIC_SPI 4113 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
4213 <GIC_SPI 4114 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
4214 <GIC_SPI 4115 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
4215 <GIC_SPI 4116 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
4216 <GIC_SPI 4117 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
4217 <GIC_SPI 4118 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
4218 <GIC_SPI 4119 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
4219 <GIC_SPI 4120 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
4220 <GIC_SPI 4121 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
4221 <GIC_SPI 4122 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
4222 <GIC_SPI 4123 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
4223 <GIC_SPI 4124 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
4224 <GIC_SPI 4125 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
4225 <GIC_SPI 4126 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
4226 <GIC_SPI 4127 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
4227 <GIC_SPI 4128 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
4228 <GIC_SPI 4129 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
4229 <GIC_SPI 4130 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
4230 <GIC_SPI 4131 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
4231 <GIC_SPI 4132 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
4232 <GIC_SPI 4133 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
4233 <GIC_SPI 4134 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
4234 <GIC_SPI 4135 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
4235 <GIC_SPI 4136 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
4236 <GIC_SPI 4137 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
4237 <GIC_SPI 4138 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
4238 <GIC_SPI 4139 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
4239 <GIC_SPI 4140 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
4240 <GIC_SPI 4141 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
4241 <GIC_SPI 4142 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
4242 <GIC_SPI 4143 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
4243 <GIC_SPI 4144 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
4244 <GIC_SPI 4145 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
4245 <GIC_SPI 4146 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
4246 <GIC_SPI 4147 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
4247 <GIC_SPI 4148 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
4248 <GIC_SPI 4149 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
4249 <GIC_SPI 4150 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
4250 <GIC_SPI 4151 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
4251 <GIC_SPI 4152 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
4252 <GIC_SPI 4153 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
4253 <GIC_SPI 4154 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
4254 <GIC_SPI 4155 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
4255 <GIC_SPI 4156 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
4256 <GIC_SPI 4157 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
4257 <GIC_SPI 4158 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
4258 <GIC_SPI 4159 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
4259 <GIC_SPI 4160 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>;
4260 }; 4161 };
4261 4162
4262 intc: interrupt-controller@17 4163 intc: interrupt-controller@17100000 {
4263 compatible = "arm,gic 4164 compatible = "arm,gic-v3";
4264 #interrupt-cells = <3 4165 #interrupt-cells = <3>;
4265 interrupt-controller; 4166 interrupt-controller;
4266 #redistributor-region 4167 #redistributor-regions = <1>;
4267 redistributor-stride 4168 redistributor-stride = <0x0 0x40000>;
4268 reg = <0x0 0x17100000 4169 reg = <0x0 0x17100000 0x0 0x10000>, /* GICD */
4269 <0x0 0x17180000 4170 <0x0 0x17180000 0x0 0x200000>; /* GICR * 8 */
4270 interrupts = <GIC_PPI 4171 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
4271 #address-cells = <2>; 4172 #address-cells = <2>;
4272 #size-cells = <2>; 4173 #size-cells = <2>;
4273 ranges; 4174 ranges;
4274 4175
4275 gic_its: msi-controll 4176 gic_its: msi-controller@17140000 {
4276 compatible = 4177 compatible = "arm,gic-v3-its";
4277 reg = <0x0 0x 4178 reg = <0x0 0x17140000 0x0 0x20000>;
4278 msi-controlle 4179 msi-controller;
4279 #msi-cells = 4180 #msi-cells = <1>;
4280 }; 4181 };
4281 }; 4182 };
4282 4183
4283 timer@17420000 { 4184 timer@17420000 {
4284 compatible = "arm,arm 4185 compatible = "arm,armv7-timer-mem";
4285 #address-cells = <1>; 4186 #address-cells = <1>;
4286 #size-cells = <1>; 4187 #size-cells = <1>;
4287 ranges = <0 0 0 0x200 4188 ranges = <0 0 0 0x20000000>;
4288 reg = <0x0 0x17420000 4189 reg = <0x0 0x17420000 0x0 0x1000>;
4289 clock-frequency = <19 4190 clock-frequency = <19200000>;
4290 4191
4291 frame@17421000 { 4192 frame@17421000 {
4292 frame-number 4193 frame-number = <0>;
4293 interrupts = 4194 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
4294 4195 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
4295 reg = <0x1742 4196 reg = <0x17421000 0x1000>,
4296 <0x1742 4197 <0x17422000 0x1000>;
4297 }; 4198 };
4298 4199
4299 frame@17423000 { 4200 frame@17423000 {
4300 frame-number 4201 frame-number = <1>;
4301 interrupts = 4202 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
4302 reg = <0x1742 4203 reg = <0x17423000 0x1000>;
4303 status = "dis 4204 status = "disabled";
4304 }; 4205 };
4305 4206
4306 frame@17425000 { 4207 frame@17425000 {
4307 frame-number 4208 frame-number = <2>;
4308 interrupts = 4209 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
4309 reg = <0x1742 4210 reg = <0x17425000 0x1000>;
4310 status = "dis 4211 status = "disabled";
4311 }; 4212 };
4312 4213
4313 frame@17427000 { 4214 frame@17427000 {
4314 frame-number 4215 frame-number = <3>;
4315 interrupts = 4216 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
4316 reg = <0x1742 4217 reg = <0x17427000 0x1000>;
4317 status = "dis 4218 status = "disabled";
4318 }; 4219 };
4319 4220
4320 frame@17429000 { 4221 frame@17429000 {
4321 frame-number 4222 frame-number = <4>;
4322 interrupts = 4223 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
4323 reg = <0x1742 4224 reg = <0x17429000 0x1000>;
4324 status = "dis 4225 status = "disabled";
4325 }; 4226 };
4326 4227
4327 frame@1742b000 { 4228 frame@1742b000 {
4328 frame-number 4229 frame-number = <5>;
4329 interrupts = 4230 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
4330 reg = <0x1742 4231 reg = <0x1742b000 0x1000>;
4331 status = "dis 4232 status = "disabled";
4332 }; 4233 };
4333 4234
4334 frame@1742d000 { 4235 frame@1742d000 {
4335 frame-number 4236 frame-number = <6>;
4336 interrupts = 4237 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
4337 reg = <0x1742 4238 reg = <0x1742d000 0x1000>;
4338 status = "dis 4239 status = "disabled";
4339 }; 4240 };
4340 }; 4241 };
4341 4242
4342 apps_rsc: rsc@17a00000 { 4243 apps_rsc: rsc@17a00000 {
4343 label = "apps_rsc"; 4244 label = "apps_rsc";
4344 compatible = "qcom,rp 4245 compatible = "qcom,rpmh-rsc";
4345 reg = <0x0 0x17a00000 4246 reg = <0x0 0x17a00000 0x0 0x10000>,
4346 <0x0 0x17a10000 4247 <0x0 0x17a10000 0x0 0x10000>,
4347 <0x0 0x17a20000 4248 <0x0 0x17a20000 0x0 0x10000>,
4348 <0x0 0x17a30000 4249 <0x0 0x17a30000 0x0 0x10000>;
4349 reg-names = "drv-0", 4250 reg-names = "drv-0", "drv-1", "drv-2", "drv-3";
4350 interrupts = <GIC_SPI 4251 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
4351 <GIC_SPI 4252 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
4352 <GIC_SPI 4253 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
4353 qcom,tcs-offset = <0x 4254 qcom,tcs-offset = <0xd00>;
4354 qcom,drv-id = <2>; 4255 qcom,drv-id = <2>;
4355 qcom,tcs-config = <AC 4256 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
4356 <WA 4257 <WAKE_TCS 2>, <CONTROL_TCS 0>;
4357 power-domains = <&CLU 4258 power-domains = <&CLUSTER_PD>;
4358 4259
4359 apps_bcm_voter: bcm-v 4260 apps_bcm_voter: bcm-voter {
4360 compatible = 4261 compatible = "qcom,bcm-voter";
4361 }; 4262 };
4362 4263
4363 rpmhcc: clock-control 4264 rpmhcc: clock-controller {
4364 compatible = 4265 compatible = "qcom,sm8450-rpmh-clk";
4365 #clock-cells 4266 #clock-cells = <1>;
4366 clock-names = 4267 clock-names = "xo";
4367 clocks = <&xo 4268 clocks = <&xo_board>;
4368 }; 4269 };
4369 4270
4370 rpmhpd: power-control 4271 rpmhpd: power-controller {
4371 compatible = 4272 compatible = "qcom,sm8450-rpmhpd";
4372 #power-domain 4273 #power-domain-cells = <1>;
4373 operating-poi 4274 operating-points-v2 = <&rpmhpd_opp_table>;
4374 4275
4375 rpmhpd_opp_ta 4276 rpmhpd_opp_table: opp-table {
4376 compa 4277 compatible = "operating-points-v2";
4377 4278
4378 rpmhp 4279 rpmhpd_opp_ret: opp1 {
4379 4280 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4380 }; 4281 };
4381 4282
4382 rpmhp 4283 rpmhpd_opp_min_svs: opp2 {
4383 4284 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4384 }; 4285 };
4385 4286
4386 rpmhp 4287 rpmhpd_opp_low_svs_d1: opp3 {
4387 4288 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
4388 }; 4289 };
4389 4290
4390 rpmhp 4291 rpmhpd_opp_low_svs: opp4 {
4391 4292 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4392 }; 4293 };
4393 4294
4394 rpmhp 4295 rpmhpd_opp_low_svs_l1: opp5 {
4395 4296 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
4396 }; 4297 };
4397 4298
4398 rpmhp 4299 rpmhpd_opp_svs: opp6 {
4399 4300 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4400 }; 4301 };
4401 4302
4402 rpmhp 4303 rpmhpd_opp_svs_l0: opp7 {
4403 4304 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
4404 }; 4305 };
4405 4306
4406 rpmhp 4307 rpmhpd_opp_svs_l1: opp8 {
4407 4308 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4408 }; 4309 };
4409 4310
4410 rpmhp 4311 rpmhpd_opp_svs_l2: opp9 {
4411 4312 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
4412 }; 4313 };
4413 4314
4414 rpmhp 4315 rpmhpd_opp_nom: opp10 {
4415 4316 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4416 }; 4317 };
4417 4318
4418 rpmhp 4319 rpmhpd_opp_nom_l1: opp11 {
4419 4320 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4420 }; 4321 };
4421 4322
4422 rpmhp 4323 rpmhpd_opp_nom_l2: opp12 {
4423 4324 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4424 }; 4325 };
4425 4326
4426 rpmhp 4327 rpmhpd_opp_turbo: opp13 {
4427 4328 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4428 }; 4329 };
4429 4330
4430 rpmhp 4331 rpmhpd_opp_turbo_l1: opp14 {
4431 4332 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4432 }; 4333 };
4433 }; 4334 };
4434 }; 4335 };
4435 }; 4336 };
4436 4337
4437 cpufreq_hw: cpufreq@17d91000 4338 cpufreq_hw: cpufreq@17d91000 {
4438 compatible = "qcom,sm 4339 compatible = "qcom,sm8450-cpufreq-epss", "qcom,cpufreq-epss";
4439 reg = <0 0x17d91000 0 4340 reg = <0 0x17d91000 0 0x1000>,
4440 <0 0x17d92000 0 4341 <0 0x17d92000 0 0x1000>,
4441 <0 0x17d93000 0 4342 <0 0x17d93000 0 0x1000>;
4442 reg-names = "freq-dom 4343 reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
4443 clocks = <&rpmhcc RPM 4344 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
4444 clock-names = "xo", " 4345 clock-names = "xo", "alternate";
4445 interrupts = <GIC_SPI 4346 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
4446 <GIC_SPI 4347 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
4447 <GIC_SPI 4348 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
4448 interrupt-names = "dc 4349 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
4449 #freq-domain-cells = 4350 #freq-domain-cells = <1>;
4450 #clock-cells = <1>; 4351 #clock-cells = <1>;
4451 }; 4352 };
4452 4353
4453 gem_noc: interconnect@1910000 4354 gem_noc: interconnect@19100000 {
4454 compatible = "qcom,sm 4355 compatible = "qcom,sm8450-gem-noc";
4455 reg = <0 0x19100000 0 4356 reg = <0 0x19100000 0 0xbb800>;
4456 #interconnect-cells = 4357 #interconnect-cells = <2>;
4457 qcom,bcm-voters = <&a 4358 qcom,bcm-voters = <&apps_bcm_voter>;
4458 }; 4359 };
4459 4360
4460 system-cache-controller@19200 4361 system-cache-controller@19200000 {
4461 compatible = "qcom,sm 4362 compatible = "qcom,sm8450-llcc";
4462 reg = <0 0x19200000 0 4363 reg = <0 0x19200000 0 0x80000>, <0 0x19600000 0 0x80000>,
4463 <0 0x19300000 0 4364 <0 0x19300000 0 0x80000>, <0 0x19700000 0 0x80000>,
4464 <0 0x19a00000 0 !! 4365 <0 0x19a00000 0 0x80000>;
4465 reg-names = "llcc0_ba 4366 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
4466 "llcc3_ba !! 4367 "llcc3_base", "llcc_broadcast_base";
4467 "llcc_bro <<
4468 interrupts = <GIC_SPI 4368 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
4469 }; 4369 };
4470 4370
4471 ufs_mem_hc: ufshc@1d84000 { 4371 ufs_mem_hc: ufshc@1d84000 {
4472 compatible = "qcom,sm 4372 compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
4473 "jedec,u 4373 "jedec,ufs-2.0";
4474 reg = <0 0x01d84000 0 4374 reg = <0 0x01d84000 0 0x3000>;
4475 interrupts = <GIC_SPI 4375 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
4476 phys = <&ufs_mem_phy> 4376 phys = <&ufs_mem_phy>;
4477 phy-names = "ufsphy"; 4377 phy-names = "ufsphy";
4478 lanes-per-direction = 4378 lanes-per-direction = <2>;
4479 #reset-cells = <1>; 4379 #reset-cells = <1>;
4480 resets = <&gcc GCC_UF 4380 resets = <&gcc GCC_UFS_PHY_BCR>;
4481 reset-names = "rst"; 4381 reset-names = "rst";
4482 4382
4483 power-domains = <&gcc 4383 power-domains = <&gcc UFS_PHY_GDSC>;
4484 4384
4485 iommus = <&apps_smmu 4385 iommus = <&apps_smmu 0xe0 0x0>;
4486 dma-coherent; 4386 dma-coherent;
4487 4387
4488 interconnects = <&agg 4388 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>,
4489 <&gem 4389 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
4490 interconnect-names = 4390 interconnect-names = "ufs-ddr", "cpu-ufs";
4491 clock-names = 4391 clock-names =
4492 "core_clk", 4392 "core_clk",
4493 "bus_aggr_clk 4393 "bus_aggr_clk",
4494 "iface_clk", 4394 "iface_clk",
4495 "core_clk_uni 4395 "core_clk_unipro",
4496 "ref_clk", 4396 "ref_clk",
4497 "tx_lane0_syn 4397 "tx_lane0_sync_clk",
4498 "rx_lane0_syn 4398 "rx_lane0_sync_clk",
4499 "rx_lane1_syn 4399 "rx_lane1_sync_clk";
4500 clocks = 4400 clocks =
4501 <&gcc GCC_UFS 4401 <&gcc GCC_UFS_PHY_AXI_CLK>,
4502 <&gcc GCC_AGG 4402 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
4503 <&gcc GCC_UFS 4403 <&gcc GCC_UFS_PHY_AHB_CLK>,
4504 <&gcc GCC_UFS 4404 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
4505 <&rpmhcc RPMH 4405 <&rpmhcc RPMH_CXO_CLK>,
4506 <&gcc GCC_UFS 4406 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
4507 <&gcc GCC_UFS 4407 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
4508 <&gcc GCC_UFS 4408 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
4509 freq-table-hz = 4409 freq-table-hz =
4510 <75000000 300 4410 <75000000 300000000>,
4511 <0 0>, 4411 <0 0>,
4512 <0 0>, 4412 <0 0>,
4513 <75000000 300 4413 <75000000 300000000>,
4514 <75000000 300 4414 <75000000 300000000>,
4515 <0 0>, 4415 <0 0>,
4516 <0 0>, 4416 <0 0>,
4517 <0 0>; 4417 <0 0>;
4518 qcom,ice = <&ice>; 4418 qcom,ice = <&ice>;
4519 4419
4520 status = "disabled"; 4420 status = "disabled";
4521 }; 4421 };
4522 4422
4523 ufs_mem_phy: phy@1d87000 { 4423 ufs_mem_phy: phy@1d87000 {
4524 compatible = "qcom,sm 4424 compatible = "qcom,sm8450-qmp-ufs-phy";
4525 reg = <0 0x01d87000 0 4425 reg = <0 0x01d87000 0 0x1000>;
4526 4426
4527 clock-names = "ref", 4427 clock-names = "ref", "ref_aux", "qref";
4528 clocks = <&rpmhcc RPM 4428 clocks = <&rpmhcc RPMH_CXO_CLK>,
4529 <&gcc GCC_UF 4429 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
4530 <&gcc GCC_UF 4430 <&gcc GCC_UFS_0_CLKREF_EN>;
4531 4431
4532 power-domains = <&gcc 4432 power-domains = <&gcc UFS_PHY_GDSC>;
4533 4433
4534 resets = <&ufs_mem_hc 4434 resets = <&ufs_mem_hc 0>;
4535 reset-names = "ufsphy 4435 reset-names = "ufsphy";
4536 4436
4537 #clock-cells = <1>; 4437 #clock-cells = <1>;
4538 #phy-cells = <0>; 4438 #phy-cells = <0>;
4539 4439
4540 status = "disabled"; 4440 status = "disabled";
4541 }; 4441 };
4542 4442
4543 ice: crypto@1d88000 { 4443 ice: crypto@1d88000 {
4544 compatible = "qcom,sm 4444 compatible = "qcom,sm8450-inline-crypto-engine",
4545 "qcom,in 4445 "qcom,inline-crypto-engine";
4546 reg = <0 0x01d88000 0 4446 reg = <0 0x01d88000 0 0x8000>;
4547 clocks = <&gcc GCC_UF 4447 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
4548 }; 4448 };
4549 4449
4550 cryptobam: dma-controller@1dc 4450 cryptobam: dma-controller@1dc4000 {
4551 compatible = "qcom,ba 4451 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
4552 reg = <0 0x01dc4000 0 4452 reg = <0 0x01dc4000 0 0x28000>;
4553 interrupts = <GIC_SPI 4453 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
4554 #dma-cells = <1>; 4454 #dma-cells = <1>;
4555 qcom,ee = <0>; 4455 qcom,ee = <0>;
4556 qcom,controlled-remot 4456 qcom,controlled-remotely;
4557 iommus = <&apps_smmu 4457 iommus = <&apps_smmu 0x584 0x11>,
4558 <&apps_smmu 4458 <&apps_smmu 0x588 0x0>,
4559 <&apps_smmu 4459 <&apps_smmu 0x598 0x5>,
4560 <&apps_smmu 4460 <&apps_smmu 0x59a 0x0>,
4561 <&apps_smmu 4461 <&apps_smmu 0x59f 0x0>;
4562 }; 4462 };
4563 4463
4564 crypto: crypto@1dfa000 { 4464 crypto: crypto@1dfa000 {
4565 compatible = "qcom,sm 4465 compatible = "qcom,sm8450-qce", "qcom,sm8150-qce", "qcom,qce";
4566 reg = <0 0x01dfa000 0 4466 reg = <0 0x01dfa000 0 0x6000>;
4567 dmas = <&cryptobam 4> 4467 dmas = <&cryptobam 4>, <&cryptobam 5>;
4568 dma-names = "rx", "tx 4468 dma-names = "rx", "tx";
4569 iommus = <&apps_smmu 4469 iommus = <&apps_smmu 0x584 0x11>,
4570 <&apps_smmu 4470 <&apps_smmu 0x588 0x0>,
4571 <&apps_smmu 4471 <&apps_smmu 0x598 0x5>,
4572 <&apps_smmu 4472 <&apps_smmu 0x59a 0x0>,
4573 <&apps_smmu 4473 <&apps_smmu 0x59f 0x0>;
4574 interconnects = <&agg 4474 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
4575 interconnect-names = 4475 interconnect-names = "memory";
4576 }; 4476 };
4577 4477
4578 sdhc_2: mmc@8804000 { 4478 sdhc_2: mmc@8804000 {
4579 compatible = "qcom,sm 4479 compatible = "qcom,sm8450-sdhci", "qcom,sdhci-msm-v5";
4580 reg = <0 0x08804000 0 4480 reg = <0 0x08804000 0 0x1000>;
4581 4481
4582 interrupts = <GIC_SPI 4482 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
4583 <GIC_SPI 4483 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
4584 interrupt-names = "hc 4484 interrupt-names = "hc_irq", "pwr_irq";
4585 4485
4586 clocks = <&gcc GCC_SD 4486 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
4587 <&gcc GCC_SD 4487 <&gcc GCC_SDCC2_APPS_CLK>,
4588 <&rpmhcc RPM 4488 <&rpmhcc RPMH_CXO_CLK>;
4589 clock-names = "iface" 4489 clock-names = "iface", "core", "xo";
4590 resets = <&gcc GCC_SD 4490 resets = <&gcc GCC_SDCC2_BCR>;
4591 interconnects = <&agg 4491 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
4592 <&gem 4492 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
4593 interconnect-names = 4493 interconnect-names = "sdhc-ddr","cpu-sdhc";
4594 iommus = <&apps_smmu 4494 iommus = <&apps_smmu 0x4a0 0x0>;
4595 power-domains = <&rpm 4495 power-domains = <&rpmhpd RPMHPD_CX>;
4596 operating-points-v2 = 4496 operating-points-v2 = <&sdhc2_opp_table>;
4597 bus-width = <4>; 4497 bus-width = <4>;
4598 dma-coherent; 4498 dma-coherent;
4599 4499
4600 /* Forbid SDR104/SDR5 4500 /* Forbid SDR104/SDR50 - broken hw! */
4601 sdhci-caps-mask = <0x 4501 sdhci-caps-mask = <0x3 0x0>;
4602 4502
4603 status = "disabled"; 4503 status = "disabled";
4604 4504
4605 sdhc2_opp_table: opp- 4505 sdhc2_opp_table: opp-table {
4606 compatible = 4506 compatible = "operating-points-v2";
4607 4507
4608 opp-100000000 4508 opp-100000000 {
4609 opp-h 4509 opp-hz = /bits/ 64 <100000000>;
4610 requi 4510 required-opps = <&rpmhpd_opp_low_svs>;
4611 }; 4511 };
4612 4512
4613 opp-202000000 4513 opp-202000000 {
4614 opp-h 4514 opp-hz = /bits/ 64 <202000000>;
4615 requi 4515 required-opps = <&rpmhpd_opp_svs_l1>;
4616 }; 4516 };
4617 }; 4517 };
4618 }; 4518 };
4619 4519
4620 usb_1: usb@a6f8800 { 4520 usb_1: usb@a6f8800 {
4621 compatible = "qcom,sm 4521 compatible = "qcom,sm8450-dwc3", "qcom,dwc3";
4622 reg = <0 0x0a6f8800 0 4522 reg = <0 0x0a6f8800 0 0x400>;
4623 status = "disabled"; 4523 status = "disabled";
4624 #address-cells = <2>; 4524 #address-cells = <2>;
4625 #size-cells = <2>; 4525 #size-cells = <2>;
4626 ranges; 4526 ranges;
4627 4527
4628 clocks = <&gcc GCC_CF 4528 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
4629 <&gcc GCC_US 4529 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
4630 <&gcc GCC_AG 4530 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
4631 <&gcc GCC_US 4531 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
4632 <&gcc GCC_US 4532 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4633 <&gcc GCC_US 4533 <&gcc GCC_USB3_0_CLKREF_EN>;
4634 clock-names = "cfg_no 4534 clock-names = "cfg_noc",
4635 "core", 4535 "core",
4636 "iface" 4536 "iface",
4637 "sleep" 4537 "sleep",
4638 "mock_u 4538 "mock_utmi",
4639 "xo"; 4539 "xo";
4640 4540
4641 assigned-clocks = <&g 4541 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4642 <&g 4542 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
4643 assigned-clock-rates 4543 assigned-clock-rates = <19200000>, <200000000>;
4644 4544
4645 interrupts-extended = 4545 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
4646 4546 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
4647 4547 <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
4648 4548 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
4649 4549 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
4650 interrupt-names = "pw 4550 interrupt-names = "pwr_event",
4651 "hs 4551 "hs_phy_irq",
4652 "dp 4552 "dp_hs_phy_irq",
4653 "dm 4553 "dm_hs_phy_irq",
4654 "ss 4554 "ss_phy_irq";
4655 4555
4656 power-domains = <&gcc 4556 power-domains = <&gcc USB30_PRIM_GDSC>;
4657 4557
4658 resets = <&gcc GCC_US 4558 resets = <&gcc GCC_USB30_PRIM_BCR>;
4659 4559
4660 interconnects = <&agg 4560 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
4661 <&gem 4561 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
4662 interconnect-names = 4562 interconnect-names = "usb-ddr", "apps-usb";
4663 4563
4664 usb_1_dwc3: usb@a6000 4564 usb_1_dwc3: usb@a600000 {
4665 compatible = 4565 compatible = "snps,dwc3";
4666 reg = <0 0x0a 4566 reg = <0 0x0a600000 0 0xcd00>;
4667 interrupts = 4567 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
4668 iommus = <&ap 4568 iommus = <&apps_smmu 0x0 0x0>;
4669 snps,dis_u2_s 4569 snps,dis_u2_susphy_quirk;
4670 snps,dis_enbl 4570 snps,dis_enblslpm_quirk;
4671 phys = <&usb_ 4571 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
4672 phy-names = " 4572 phy-names = "usb2-phy", "usb3-phy";
4673 4573
4674 ports { 4574 ports {
4675 #addr 4575 #address-cells = <1>;
4676 #size 4576 #size-cells = <0>;
4677 4577
4678 port@ 4578 port@0 {
4679 4579 reg = <0>;
4680 4580
4681 4581 usb_1_dwc3_hs: endpoint {
4682 4582 };
4683 }; 4583 };
4684 4584
4685 port@ 4585 port@1 {
4686 4586 reg = <1>;
4687 4587
4688 4588 usb_1_dwc3_ss: endpoint {
4689 <<
4690 4589 };
4691 }; 4590 };
4692 }; 4591 };
4693 }; 4592 };
4694 }; 4593 };
4695 4594
4696 nsp_noc: interconnect@320c000 4595 nsp_noc: interconnect@320c0000 {
4697 compatible = "qcom,sm 4596 compatible = "qcom,sm8450-nsp-noc";
4698 reg = <0 0x320c0000 0 4597 reg = <0 0x320c0000 0 0x10000>;
4699 #interconnect-cells = 4598 #interconnect-cells = <2>;
4700 qcom,bcm-voters = <&a 4599 qcom,bcm-voters = <&apps_bcm_voter>;
4701 }; 4600 };
4702 4601
4703 lpass_ag_noc: interconnect@3c 4602 lpass_ag_noc: interconnect@3c40000 {
4704 compatible = "qcom,sm 4603 compatible = "qcom,sm8450-lpass-ag-noc";
4705 reg = <0 0x03c40000 0 4604 reg = <0 0x03c40000 0 0x17200>;
4706 #interconnect-cells = 4605 #interconnect-cells = <2>;
4707 qcom,bcm-voters = <&a 4606 qcom,bcm-voters = <&apps_bcm_voter>;
4708 }; 4607 };
4709 }; 4608 };
4710 4609
4711 sound: sound { 4610 sound: sound {
4712 }; 4611 };
4713 4612
4714 thermal-zones { 4613 thermal-zones {
4715 aoss0-thermal { 4614 aoss0-thermal {
>> 4615 polling-delay-passive = <0>;
>> 4616 polling-delay = <0>;
4716 thermal-sensors = <&t 4617 thermal-sensors = <&tsens0 0>;
4717 4618
4718 trips { 4619 trips {
4719 thermal-engin 4620 thermal-engine-config {
4720 tempe 4621 temperature = <125000>;
4721 hyste 4622 hysteresis = <1000>;
4722 type 4623 type = "passive";
4723 }; 4624 };
4724 4625
4725 reset-mon-cfg 4626 reset-mon-cfg {
4726 tempe 4627 temperature = <115000>;
4727 hyste 4628 hysteresis = <5000>;
4728 type 4629 type = "passive";
4729 }; 4630 };
4730 }; 4631 };
4731 }; 4632 };
4732 4633
4733 cpuss0-thermal { 4634 cpuss0-thermal {
>> 4635 polling-delay-passive = <0>;
>> 4636 polling-delay = <0>;
4734 thermal-sensors = <&t 4637 thermal-sensors = <&tsens0 1>;
4735 4638
4736 trips { 4639 trips {
4737 thermal-engin 4640 thermal-engine-config {
4738 tempe 4641 temperature = <125000>;
4739 hyste 4642 hysteresis = <1000>;
4740 type 4643 type = "passive";
4741 }; 4644 };
4742 4645
4743 reset-mon-cfg 4646 reset-mon-cfg {
4744 tempe 4647 temperature = <115000>;
4745 hyste 4648 hysteresis = <5000>;
4746 type 4649 type = "passive";
4747 }; 4650 };
4748 }; 4651 };
4749 }; 4652 };
4750 4653
4751 cpuss1-thermal { 4654 cpuss1-thermal {
>> 4655 polling-delay-passive = <0>;
>> 4656 polling-delay = <0>;
4752 thermal-sensors = <&t 4657 thermal-sensors = <&tsens0 2>;
4753 4658
4754 trips { 4659 trips {
4755 thermal-engin 4660 thermal-engine-config {
4756 tempe 4661 temperature = <125000>;
4757 hyste 4662 hysteresis = <1000>;
4758 type 4663 type = "passive";
4759 }; 4664 };
4760 4665
4761 reset-mon-cfg 4666 reset-mon-cfg {
4762 tempe 4667 temperature = <115000>;
4763 hyste 4668 hysteresis = <5000>;
4764 type 4669 type = "passive";
4765 }; 4670 };
4766 }; 4671 };
4767 }; 4672 };
4768 4673
4769 cpuss3-thermal { 4674 cpuss3-thermal {
>> 4675 polling-delay-passive = <0>;
>> 4676 polling-delay = <0>;
4770 thermal-sensors = <&t 4677 thermal-sensors = <&tsens0 3>;
4771 4678
4772 trips { 4679 trips {
4773 thermal-engin 4680 thermal-engine-config {
4774 tempe 4681 temperature = <125000>;
4775 hyste 4682 hysteresis = <1000>;
4776 type 4683 type = "passive";
4777 }; 4684 };
4778 4685
4779 reset-mon-cfg 4686 reset-mon-cfg {
4780 tempe 4687 temperature = <115000>;
4781 hyste 4688 hysteresis = <5000>;
4782 type 4689 type = "passive";
4783 }; 4690 };
4784 }; 4691 };
4785 }; 4692 };
4786 4693
4787 cpuss4-thermal { 4694 cpuss4-thermal {
>> 4695 polling-delay-passive = <0>;
>> 4696 polling-delay = <0>;
4788 thermal-sensors = <&t 4697 thermal-sensors = <&tsens0 4>;
4789 4698
4790 trips { 4699 trips {
4791 thermal-engin 4700 thermal-engine-config {
4792 tempe 4701 temperature = <125000>;
4793 hyste 4702 hysteresis = <1000>;
4794 type 4703 type = "passive";
4795 }; 4704 };
4796 4705
4797 reset-mon-cfg 4706 reset-mon-cfg {
4798 tempe 4707 temperature = <115000>;
4799 hyste 4708 hysteresis = <5000>;
4800 type 4709 type = "passive";
4801 }; 4710 };
4802 }; 4711 };
4803 }; 4712 };
4804 4713
4805 cpu4-top-thermal { 4714 cpu4-top-thermal {
>> 4715 polling-delay-passive = <0>;
>> 4716 polling-delay = <0>;
4806 thermal-sensors = <&t 4717 thermal-sensors = <&tsens0 5>;
4807 4718
4808 trips { 4719 trips {
4809 cpu4_top_aler 4720 cpu4_top_alert0: trip-point0 {
4810 tempe 4721 temperature = <90000>;
4811 hyste 4722 hysteresis = <2000>;
4812 type 4723 type = "passive";
4813 }; 4724 };
4814 4725
4815 cpu4_top_aler 4726 cpu4_top_alert1: trip-point1 {
4816 tempe 4727 temperature = <95000>;
4817 hyste 4728 hysteresis = <2000>;
4818 type 4729 type = "passive";
4819 }; 4730 };
4820 4731
4821 cpu4_top_crit 4732 cpu4_top_crit: cpu-crit {
4822 tempe 4733 temperature = <110000>;
4823 hyste 4734 hysteresis = <1000>;
4824 type 4735 type = "critical";
4825 }; 4736 };
4826 }; 4737 };
4827 }; 4738 };
4828 4739
4829 cpu4-bottom-thermal { 4740 cpu4-bottom-thermal {
>> 4741 polling-delay-passive = <0>;
>> 4742 polling-delay = <0>;
4830 thermal-sensors = <&t 4743 thermal-sensors = <&tsens0 6>;
4831 4744
4832 trips { 4745 trips {
4833 cpu4_bottom_a 4746 cpu4_bottom_alert0: trip-point0 {
4834 tempe 4747 temperature = <90000>;
4835 hyste 4748 hysteresis = <2000>;
4836 type 4749 type = "passive";
4837 }; 4750 };
4838 4751
4839 cpu4_bottom_a 4752 cpu4_bottom_alert1: trip-point1 {
4840 tempe 4753 temperature = <95000>;
4841 hyste 4754 hysteresis = <2000>;
4842 type 4755 type = "passive";
4843 }; 4756 };
4844 4757
4845 cpu4_bottom_c 4758 cpu4_bottom_crit: cpu-crit {
4846 tempe 4759 temperature = <110000>;
4847 hyste 4760 hysteresis = <1000>;
4848 type 4761 type = "critical";
4849 }; 4762 };
4850 }; 4763 };
4851 }; 4764 };
4852 4765
4853 cpu5-top-thermal { 4766 cpu5-top-thermal {
>> 4767 polling-delay-passive = <0>;
>> 4768 polling-delay = <0>;
4854 thermal-sensors = <&t 4769 thermal-sensors = <&tsens0 7>;
4855 4770
4856 trips { 4771 trips {
4857 cpu5_top_aler 4772 cpu5_top_alert0: trip-point0 {
4858 tempe 4773 temperature = <90000>;
4859 hyste 4774 hysteresis = <2000>;
4860 type 4775 type = "passive";
4861 }; 4776 };
4862 4777
4863 cpu5_top_aler 4778 cpu5_top_alert1: trip-point1 {
4864 tempe 4779 temperature = <95000>;
4865 hyste 4780 hysteresis = <2000>;
4866 type 4781 type = "passive";
4867 }; 4782 };
4868 4783
4869 cpu5_top_crit 4784 cpu5_top_crit: cpu-crit {
4870 tempe 4785 temperature = <110000>;
4871 hyste 4786 hysteresis = <1000>;
4872 type 4787 type = "critical";
4873 }; 4788 };
4874 }; 4789 };
4875 }; 4790 };
4876 4791
4877 cpu5-bottom-thermal { 4792 cpu5-bottom-thermal {
>> 4793 polling-delay-passive = <0>;
>> 4794 polling-delay = <0>;
4878 thermal-sensors = <&t 4795 thermal-sensors = <&tsens0 8>;
4879 4796
4880 trips { 4797 trips {
4881 cpu5_bottom_a 4798 cpu5_bottom_alert0: trip-point0 {
4882 tempe 4799 temperature = <90000>;
4883 hyste 4800 hysteresis = <2000>;
4884 type 4801 type = "passive";
4885 }; 4802 };
4886 4803
4887 cpu5_bottom_a 4804 cpu5_bottom_alert1: trip-point1 {
4888 tempe 4805 temperature = <95000>;
4889 hyste 4806 hysteresis = <2000>;
4890 type 4807 type = "passive";
4891 }; 4808 };
4892 4809
4893 cpu5_bottom_c 4810 cpu5_bottom_crit: cpu-crit {
4894 tempe 4811 temperature = <110000>;
4895 hyste 4812 hysteresis = <1000>;
4896 type 4813 type = "critical";
4897 }; 4814 };
4898 }; 4815 };
4899 }; 4816 };
4900 4817
4901 cpu6-top-thermal { 4818 cpu6-top-thermal {
>> 4819 polling-delay-passive = <0>;
>> 4820 polling-delay = <0>;
4902 thermal-sensors = <&t 4821 thermal-sensors = <&tsens0 9>;
4903 4822
4904 trips { 4823 trips {
4905 cpu6_top_aler 4824 cpu6_top_alert0: trip-point0 {
4906 tempe 4825 temperature = <90000>;
4907 hyste 4826 hysteresis = <2000>;
4908 type 4827 type = "passive";
4909 }; 4828 };
4910 4829
4911 cpu6_top_aler 4830 cpu6_top_alert1: trip-point1 {
4912 tempe 4831 temperature = <95000>;
4913 hyste 4832 hysteresis = <2000>;
4914 type 4833 type = "passive";
4915 }; 4834 };
4916 4835
4917 cpu6_top_crit 4836 cpu6_top_crit: cpu-crit {
4918 tempe 4837 temperature = <110000>;
4919 hyste 4838 hysteresis = <1000>;
4920 type 4839 type = "critical";
4921 }; 4840 };
4922 }; 4841 };
4923 }; 4842 };
4924 4843
4925 cpu6-bottom-thermal { 4844 cpu6-bottom-thermal {
>> 4845 polling-delay-passive = <0>;
>> 4846 polling-delay = <0>;
4926 thermal-sensors = <&t 4847 thermal-sensors = <&tsens0 10>;
4927 4848
4928 trips { 4849 trips {
4929 cpu6_bottom_a 4850 cpu6_bottom_alert0: trip-point0 {
4930 tempe 4851 temperature = <90000>;
4931 hyste 4852 hysteresis = <2000>;
4932 type 4853 type = "passive";
4933 }; 4854 };
4934 4855
4935 cpu6_bottom_a 4856 cpu6_bottom_alert1: trip-point1 {
4936 tempe 4857 temperature = <95000>;
4937 hyste 4858 hysteresis = <2000>;
4938 type 4859 type = "passive";
4939 }; 4860 };
4940 4861
4941 cpu6_bottom_c 4862 cpu6_bottom_crit: cpu-crit {
4942 tempe 4863 temperature = <110000>;
4943 hyste 4864 hysteresis = <1000>;
4944 type 4865 type = "critical";
4945 }; 4866 };
4946 }; 4867 };
4947 }; 4868 };
4948 4869
4949 cpu7-top-thermal { 4870 cpu7-top-thermal {
>> 4871 polling-delay-passive = <0>;
>> 4872 polling-delay = <0>;
4950 thermal-sensors = <&t 4873 thermal-sensors = <&tsens0 11>;
4951 4874
4952 trips { 4875 trips {
4953 cpu7_top_aler 4876 cpu7_top_alert0: trip-point0 {
4954 tempe 4877 temperature = <90000>;
4955 hyste 4878 hysteresis = <2000>;
4956 type 4879 type = "passive";
4957 }; 4880 };
4958 4881
4959 cpu7_top_aler 4882 cpu7_top_alert1: trip-point1 {
4960 tempe 4883 temperature = <95000>;
4961 hyste 4884 hysteresis = <2000>;
4962 type 4885 type = "passive";
4963 }; 4886 };
4964 4887
4965 cpu7_top_crit 4888 cpu7_top_crit: cpu-crit {
4966 tempe 4889 temperature = <110000>;
4967 hyste 4890 hysteresis = <1000>;
4968 type 4891 type = "critical";
4969 }; 4892 };
4970 }; 4893 };
4971 }; 4894 };
4972 4895
4973 cpu7-middle-thermal { 4896 cpu7-middle-thermal {
>> 4897 polling-delay-passive = <0>;
>> 4898 polling-delay = <0>;
4974 thermal-sensors = <&t 4899 thermal-sensors = <&tsens0 12>;
4975 4900
4976 trips { 4901 trips {
4977 cpu7_middle_a 4902 cpu7_middle_alert0: trip-point0 {
4978 tempe 4903 temperature = <90000>;
4979 hyste 4904 hysteresis = <2000>;
4980 type 4905 type = "passive";
4981 }; 4906 };
4982 4907
4983 cpu7_middle_a 4908 cpu7_middle_alert1: trip-point1 {
4984 tempe 4909 temperature = <95000>;
4985 hyste 4910 hysteresis = <2000>;
4986 type 4911 type = "passive";
4987 }; 4912 };
4988 4913
4989 cpu7_middle_c 4914 cpu7_middle_crit: cpu-crit {
4990 tempe 4915 temperature = <110000>;
4991 hyste 4916 hysteresis = <1000>;
4992 type 4917 type = "critical";
4993 }; 4918 };
4994 }; 4919 };
4995 }; 4920 };
4996 4921
4997 cpu7-bottom-thermal { 4922 cpu7-bottom-thermal {
>> 4923 polling-delay-passive = <0>;
>> 4924 polling-delay = <0>;
4998 thermal-sensors = <&t 4925 thermal-sensors = <&tsens0 13>;
4999 4926
5000 trips { 4927 trips {
5001 cpu7_bottom_a 4928 cpu7_bottom_alert0: trip-point0 {
5002 tempe 4929 temperature = <90000>;
5003 hyste 4930 hysteresis = <2000>;
5004 type 4931 type = "passive";
5005 }; 4932 };
5006 4933
5007 cpu7_bottom_a 4934 cpu7_bottom_alert1: trip-point1 {
5008 tempe 4935 temperature = <95000>;
5009 hyste 4936 hysteresis = <2000>;
5010 type 4937 type = "passive";
5011 }; 4938 };
5012 4939
5013 cpu7_bottom_c 4940 cpu7_bottom_crit: cpu-crit {
5014 tempe 4941 temperature = <110000>;
5015 hyste 4942 hysteresis = <1000>;
5016 type 4943 type = "critical";
5017 }; 4944 };
5018 }; 4945 };
5019 }; 4946 };
5020 4947
5021 gpu-top-thermal { 4948 gpu-top-thermal {
5022 polling-delay-passive 4949 polling-delay-passive = <10>;
5023 !! 4950 polling-delay = <0>;
5024 thermal-sensors = <&t 4951 thermal-sensors = <&tsens0 14>;
5025 4952
5026 cooling-maps { 4953 cooling-maps {
5027 map0 { 4954 map0 {
5028 trip 4955 trip = <&gpu_top_alert0>;
5029 cooli 4956 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5030 }; 4957 };
5031 }; 4958 };
5032 4959
5033 trips { 4960 trips {
5034 gpu_top_alert !! 4961 thermal-engine-config {
5035 tempe !! 4962 temperature = <125000>;
5036 hyste 4963 hysteresis = <1000>;
5037 type 4964 type = "passive";
5038 }; 4965 };
5039 4966
5040 trip-point1 { !! 4967 thermal-hal-config {
5041 tempe !! 4968 temperature = <125000>;
5042 hyste 4969 hysteresis = <1000>;
5043 type !! 4970 type = "passive";
5044 }; 4971 };
5045 4972
5046 trip-point2 { !! 4973 reset-mon-cfg {
5047 tempe !! 4974 temperature = <115000>;
5048 hyste !! 4975 hysteresis = <5000>;
5049 type !! 4976 type = "passive";
>> 4977 };
>> 4978
>> 4979 gpu_top_alert0: trip-point0 {
>> 4980 temperature = <95000>;
>> 4981 hysteresis = <5000>;
>> 4982 type = "passive";
5050 }; 4983 };
5051 }; 4984 };
5052 }; 4985 };
5053 4986
5054 gpu-bottom-thermal { 4987 gpu-bottom-thermal {
5055 polling-delay-passive 4988 polling-delay-passive = <10>;
5056 !! 4989 polling-delay = <0>;
5057 thermal-sensors = <&t 4990 thermal-sensors = <&tsens0 15>;
5058 4991
5059 cooling-maps { 4992 cooling-maps {
5060 map0 { 4993 map0 {
5061 trip 4994 trip = <&gpu_bottom_alert0>;
5062 cooli 4995 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5063 }; 4996 };
5064 }; 4997 };
5065 4998
5066 trips { 4999 trips {
5067 gpu_bottom_al !! 5000 thermal-engine-config {
5068 tempe !! 5001 temperature = <125000>;
5069 hyste 5002 hysteresis = <1000>;
5070 type 5003 type = "passive";
5071 }; 5004 };
5072 5005
5073 trip-point1 { !! 5006 thermal-hal-config {
5074 tempe !! 5007 temperature = <125000>;
5075 hyste 5008 hysteresis = <1000>;
5076 type !! 5009 type = "passive";
5077 }; 5010 };
5078 5011
5079 trip-point2 { !! 5012 reset-mon-cfg {
5080 tempe !! 5013 temperature = <115000>;
5081 hyste !! 5014 hysteresis = <5000>;
5082 type !! 5015 type = "passive";
>> 5016 };
>> 5017
>> 5018 gpu_bottom_alert0: trip-point0 {
>> 5019 temperature = <95000>;
>> 5020 hysteresis = <5000>;
>> 5021 type = "passive";
5083 }; 5022 };
5084 }; 5023 };
5085 }; 5024 };
5086 5025
5087 aoss1-thermal { 5026 aoss1-thermal {
>> 5027 polling-delay-passive = <0>;
>> 5028 polling-delay = <0>;
5088 thermal-sensors = <&t 5029 thermal-sensors = <&tsens1 0>;
5089 5030
5090 trips { 5031 trips {
5091 thermal-engin 5032 thermal-engine-config {
5092 tempe 5033 temperature = <125000>;
5093 hyste 5034 hysteresis = <1000>;
5094 type 5035 type = "passive";
5095 }; 5036 };
5096 5037
5097 reset-mon-cfg 5038 reset-mon-cfg {
5098 tempe 5039 temperature = <115000>;
5099 hyste 5040 hysteresis = <5000>;
5100 type 5041 type = "passive";
5101 }; 5042 };
5102 }; 5043 };
5103 }; 5044 };
5104 5045
5105 cpu0-thermal { 5046 cpu0-thermal {
>> 5047 polling-delay-passive = <0>;
>> 5048 polling-delay = <0>;
5106 thermal-sensors = <&t 5049 thermal-sensors = <&tsens1 1>;
5107 5050
5108 trips { 5051 trips {
5109 cpu0_alert0: 5052 cpu0_alert0: trip-point0 {
5110 tempe 5053 temperature = <90000>;
5111 hyste 5054 hysteresis = <2000>;
5112 type 5055 type = "passive";
5113 }; 5056 };
5114 5057
5115 cpu0_alert1: 5058 cpu0_alert1: trip-point1 {
5116 tempe 5059 temperature = <95000>;
5117 hyste 5060 hysteresis = <2000>;
5118 type 5061 type = "passive";
5119 }; 5062 };
5120 5063
5121 cpu0_crit: cp 5064 cpu0_crit: cpu-crit {
5122 tempe 5065 temperature = <110000>;
5123 hyste 5066 hysteresis = <1000>;
5124 type 5067 type = "critical";
5125 }; 5068 };
5126 }; 5069 };
5127 }; 5070 };
5128 5071
5129 cpu1-thermal { 5072 cpu1-thermal {
>> 5073 polling-delay-passive = <0>;
>> 5074 polling-delay = <0>;
5130 thermal-sensors = <&t 5075 thermal-sensors = <&tsens1 2>;
5131 5076
5132 trips { 5077 trips {
5133 cpu1_alert0: 5078 cpu1_alert0: trip-point0 {
5134 tempe 5079 temperature = <90000>;
5135 hyste 5080 hysteresis = <2000>;
5136 type 5081 type = "passive";
5137 }; 5082 };
5138 5083
5139 cpu1_alert1: 5084 cpu1_alert1: trip-point1 {
5140 tempe 5085 temperature = <95000>;
5141 hyste 5086 hysteresis = <2000>;
5142 type 5087 type = "passive";
5143 }; 5088 };
5144 5089
5145 cpu1_crit: cp 5090 cpu1_crit: cpu-crit {
5146 tempe 5091 temperature = <110000>;
5147 hyste 5092 hysteresis = <1000>;
5148 type 5093 type = "critical";
5149 }; 5094 };
5150 }; 5095 };
5151 }; 5096 };
5152 5097
5153 cpu2-thermal { 5098 cpu2-thermal {
>> 5099 polling-delay-passive = <0>;
>> 5100 polling-delay = <0>;
5154 thermal-sensors = <&t 5101 thermal-sensors = <&tsens1 3>;
5155 5102
5156 trips { 5103 trips {
5157 cpu2_alert0: 5104 cpu2_alert0: trip-point0 {
5158 tempe 5105 temperature = <90000>;
5159 hyste 5106 hysteresis = <2000>;
5160 type 5107 type = "passive";
5161 }; 5108 };
5162 5109
5163 cpu2_alert1: 5110 cpu2_alert1: trip-point1 {
5164 tempe 5111 temperature = <95000>;
5165 hyste 5112 hysteresis = <2000>;
5166 type 5113 type = "passive";
5167 }; 5114 };
5168 5115
5169 cpu2_crit: cp 5116 cpu2_crit: cpu-crit {
5170 tempe 5117 temperature = <110000>;
5171 hyste 5118 hysteresis = <1000>;
5172 type 5119 type = "critical";
5173 }; 5120 };
5174 }; 5121 };
5175 }; 5122 };
5176 5123
5177 cpu3-thermal { 5124 cpu3-thermal {
>> 5125 polling-delay-passive = <0>;
>> 5126 polling-delay = <0>;
5178 thermal-sensors = <&t 5127 thermal-sensors = <&tsens1 4>;
5179 5128
5180 trips { 5129 trips {
5181 cpu3_alert0: 5130 cpu3_alert0: trip-point0 {
5182 tempe 5131 temperature = <90000>;
5183 hyste 5132 hysteresis = <2000>;
5184 type 5133 type = "passive";
5185 }; 5134 };
5186 5135
5187 cpu3_alert1: 5136 cpu3_alert1: trip-point1 {
5188 tempe 5137 temperature = <95000>;
5189 hyste 5138 hysteresis = <2000>;
5190 type 5139 type = "passive";
5191 }; 5140 };
5192 5141
5193 cpu3_crit: cp 5142 cpu3_crit: cpu-crit {
5194 tempe 5143 temperature = <110000>;
5195 hyste 5144 hysteresis = <1000>;
5196 type 5145 type = "critical";
5197 }; 5146 };
5198 }; 5147 };
5199 }; 5148 };
5200 5149
5201 cdsp0-thermal { 5150 cdsp0-thermal {
5202 polling-delay-passive 5151 polling-delay-passive = <10>;
5203 !! 5152 polling-delay = <0>;
5204 thermal-sensors = <&t 5153 thermal-sensors = <&tsens1 5>;
5205 5154
5206 trips { 5155 trips {
5207 thermal-engin 5156 thermal-engine-config {
5208 tempe 5157 temperature = <125000>;
5209 hyste 5158 hysteresis = <1000>;
5210 type 5159 type = "passive";
5211 }; 5160 };
5212 5161
5213 thermal-hal-c 5162 thermal-hal-config {
5214 tempe 5163 temperature = <125000>;
5215 hyste 5164 hysteresis = <1000>;
5216 type 5165 type = "passive";
5217 }; 5166 };
5218 5167
5219 reset-mon-cfg 5168 reset-mon-cfg {
5220 tempe 5169 temperature = <115000>;
5221 hyste 5170 hysteresis = <5000>;
5222 type 5171 type = "passive";
5223 }; 5172 };
5224 5173
5225 cdsp_0_config 5174 cdsp_0_config: junction-config {
5226 tempe 5175 temperature = <95000>;
5227 hyste 5176 hysteresis = <5000>;
5228 type 5177 type = "passive";
5229 }; 5178 };
5230 }; 5179 };
5231 }; 5180 };
5232 5181
5233 cdsp1-thermal { 5182 cdsp1-thermal {
5234 polling-delay-passive 5183 polling-delay-passive = <10>;
5235 !! 5184 polling-delay = <0>;
5236 thermal-sensors = <&t 5185 thermal-sensors = <&tsens1 6>;
5237 5186
5238 trips { 5187 trips {
5239 thermal-engin 5188 thermal-engine-config {
5240 tempe 5189 temperature = <125000>;
5241 hyste 5190 hysteresis = <1000>;
5242 type 5191 type = "passive";
5243 }; 5192 };
5244 5193
5245 thermal-hal-c 5194 thermal-hal-config {
5246 tempe 5195 temperature = <125000>;
5247 hyste 5196 hysteresis = <1000>;
5248 type 5197 type = "passive";
5249 }; 5198 };
5250 5199
5251 reset-mon-cfg 5200 reset-mon-cfg {
5252 tempe 5201 temperature = <115000>;
5253 hyste 5202 hysteresis = <5000>;
5254 type 5203 type = "passive";
5255 }; 5204 };
5256 5205
5257 cdsp_1_config 5206 cdsp_1_config: junction-config {
5258 tempe 5207 temperature = <95000>;
5259 hyste 5208 hysteresis = <5000>;
5260 type 5209 type = "passive";
5261 }; 5210 };
5262 }; 5211 };
5263 }; 5212 };
5264 5213
5265 cdsp2-thermal { 5214 cdsp2-thermal {
5266 polling-delay-passive 5215 polling-delay-passive = <10>;
5267 !! 5216 polling-delay = <0>;
5268 thermal-sensors = <&t 5217 thermal-sensors = <&tsens1 7>;
5269 5218
5270 trips { 5219 trips {
5271 thermal-engin 5220 thermal-engine-config {
5272 tempe 5221 temperature = <125000>;
5273 hyste 5222 hysteresis = <1000>;
5274 type 5223 type = "passive";
5275 }; 5224 };
5276 5225
5277 thermal-hal-c 5226 thermal-hal-config {
5278 tempe 5227 temperature = <125000>;
5279 hyste 5228 hysteresis = <1000>;
5280 type 5229 type = "passive";
5281 }; 5230 };
5282 5231
5283 reset-mon-cfg 5232 reset-mon-cfg {
5284 tempe 5233 temperature = <115000>;
5285 hyste 5234 hysteresis = <5000>;
5286 type 5235 type = "passive";
5287 }; 5236 };
5288 5237
5289 cdsp_2_config 5238 cdsp_2_config: junction-config {
5290 tempe 5239 temperature = <95000>;
5291 hyste 5240 hysteresis = <5000>;
5292 type 5241 type = "passive";
5293 }; 5242 };
5294 }; 5243 };
5295 }; 5244 };
5296 5245
5297 video-thermal { 5246 video-thermal {
>> 5247 polling-delay-passive = <0>;
>> 5248 polling-delay = <0>;
5298 thermal-sensors = <&t 5249 thermal-sensors = <&tsens1 8>;
5299 5250
5300 trips { 5251 trips {
5301 thermal-engin 5252 thermal-engine-config {
5302 tempe 5253 temperature = <125000>;
5303 hyste 5254 hysteresis = <1000>;
5304 type 5255 type = "passive";
5305 }; 5256 };
5306 5257
5307 reset-mon-cfg 5258 reset-mon-cfg {
5308 tempe 5259 temperature = <115000>;
5309 hyste 5260 hysteresis = <5000>;
5310 type 5261 type = "passive";
5311 }; 5262 };
5312 }; 5263 };
5313 }; 5264 };
5314 5265
5315 mem-thermal { 5266 mem-thermal {
5316 polling-delay-passive 5267 polling-delay-passive = <10>;
5317 !! 5268 polling-delay = <0>;
5318 thermal-sensors = <&t 5269 thermal-sensors = <&tsens1 9>;
5319 5270
5320 trips { 5271 trips {
5321 thermal-engin 5272 thermal-engine-config {
5322 tempe 5273 temperature = <125000>;
5323 hyste 5274 hysteresis = <1000>;
5324 type 5275 type = "passive";
5325 }; 5276 };
5326 5277
5327 ddr_config0: 5278 ddr_config0: ddr0-config {
5328 tempe 5279 temperature = <90000>;
5329 hyste 5280 hysteresis = <5000>;
5330 type 5281 type = "passive";
5331 }; 5282 };
5332 5283
5333 reset-mon-cfg 5284 reset-mon-cfg {
5334 tempe 5285 temperature = <115000>;
5335 hyste 5286 hysteresis = <5000>;
5336 type 5287 type = "passive";
5337 }; 5288 };
5338 }; 5289 };
5339 }; 5290 };
5340 5291
5341 modem0-thermal { 5292 modem0-thermal {
>> 5293 polling-delay-passive = <0>;
>> 5294 polling-delay = <0>;
5342 thermal-sensors = <&t 5295 thermal-sensors = <&tsens1 10>;
5343 5296
5344 trips { 5297 trips {
5345 thermal-engin 5298 thermal-engine-config {
5346 tempe 5299 temperature = <125000>;
5347 hyste 5300 hysteresis = <1000>;
5348 type 5301 type = "passive";
5349 }; 5302 };
5350 5303
5351 mdmss0_config 5304 mdmss0_config0: mdmss0-config0 {
5352 tempe 5305 temperature = <102000>;
5353 hyste 5306 hysteresis = <3000>;
5354 type 5307 type = "passive";
5355 }; 5308 };
5356 5309
5357 mdmss0_config 5310 mdmss0_config1: mdmss0-config1 {
5358 tempe 5311 temperature = <105000>;
5359 hyste 5312 hysteresis = <3000>;
5360 type 5313 type = "passive";
5361 }; 5314 };
5362 5315
5363 reset-mon-cfg 5316 reset-mon-cfg {
5364 tempe 5317 temperature = <115000>;
5365 hyste 5318 hysteresis = <5000>;
5366 type 5319 type = "passive";
5367 }; 5320 };
5368 }; 5321 };
5369 }; 5322 };
5370 5323
5371 modem1-thermal { 5324 modem1-thermal {
>> 5325 polling-delay-passive = <0>;
>> 5326 polling-delay = <0>;
5372 thermal-sensors = <&t 5327 thermal-sensors = <&tsens1 11>;
5373 5328
5374 trips { 5329 trips {
5375 thermal-engin 5330 thermal-engine-config {
5376 tempe 5331 temperature = <125000>;
5377 hyste 5332 hysteresis = <1000>;
5378 type 5333 type = "passive";
5379 }; 5334 };
5380 5335
5381 mdmss1_config 5336 mdmss1_config0: mdmss1-config0 {
5382 tempe 5337 temperature = <102000>;
5383 hyste 5338 hysteresis = <3000>;
5384 type 5339 type = "passive";
5385 }; 5340 };
5386 5341
5387 mdmss1_config 5342 mdmss1_config1: mdmss1-config1 {
5388 tempe 5343 temperature = <105000>;
5389 hyste 5344 hysteresis = <3000>;
5390 type 5345 type = "passive";
5391 }; 5346 };
5392 5347
5393 reset-mon-cfg 5348 reset-mon-cfg {
5394 tempe 5349 temperature = <115000>;
5395 hyste 5350 hysteresis = <5000>;
5396 type 5351 type = "passive";
5397 }; 5352 };
5398 }; 5353 };
5399 }; 5354 };
5400 5355
5401 modem2-thermal { 5356 modem2-thermal {
>> 5357 polling-delay-passive = <0>;
>> 5358 polling-delay = <0>;
5402 thermal-sensors = <&t 5359 thermal-sensors = <&tsens1 12>;
5403 5360
5404 trips { 5361 trips {
5405 thermal-engin 5362 thermal-engine-config {
5406 tempe 5363 temperature = <125000>;
5407 hyste 5364 hysteresis = <1000>;
5408 type 5365 type = "passive";
5409 }; 5366 };
5410 5367
5411 mdmss2_config 5368 mdmss2_config0: mdmss2-config0 {
5412 tempe 5369 temperature = <102000>;
5413 hyste 5370 hysteresis = <3000>;
5414 type 5371 type = "passive";
5415 }; 5372 };
5416 5373
5417 mdmss2_config 5374 mdmss2_config1: mdmss2-config1 {
5418 tempe 5375 temperature = <105000>;
5419 hyste 5376 hysteresis = <3000>;
5420 type 5377 type = "passive";
5421 }; 5378 };
5422 5379
5423 reset-mon-cfg 5380 reset-mon-cfg {
5424 tempe 5381 temperature = <115000>;
5425 hyste 5382 hysteresis = <5000>;
5426 type 5383 type = "passive";
5427 }; 5384 };
5428 }; 5385 };
5429 }; 5386 };
5430 5387
5431 modem3-thermal { 5388 modem3-thermal {
>> 5389 polling-delay-passive = <0>;
>> 5390 polling-delay = <0>;
5432 thermal-sensors = <&t 5391 thermal-sensors = <&tsens1 13>;
5433 5392
5434 trips { 5393 trips {
5435 thermal-engin 5394 thermal-engine-config {
5436 tempe 5395 temperature = <125000>;
5437 hyste 5396 hysteresis = <1000>;
5438 type 5397 type = "passive";
5439 }; 5398 };
5440 5399
5441 mdmss3_config 5400 mdmss3_config0: mdmss3-config0 {
5442 tempe 5401 temperature = <102000>;
5443 hyste 5402 hysteresis = <3000>;
5444 type 5403 type = "passive";
5445 }; 5404 };
5446 5405
5447 mdmss3_config 5406 mdmss3_config1: mdmss3-config1 {
5448 tempe 5407 temperature = <105000>;
5449 hyste 5408 hysteresis = <3000>;
5450 type 5409 type = "passive";
5451 }; 5410 };
5452 5411
5453 reset-mon-cfg 5412 reset-mon-cfg {
5454 tempe 5413 temperature = <115000>;
5455 hyste 5414 hysteresis = <5000>;
5456 type 5415 type = "passive";
5457 }; 5416 };
5458 }; 5417 };
5459 }; 5418 };
5460 5419
5461 camera0-thermal { 5420 camera0-thermal {
>> 5421 polling-delay-passive = <0>;
>> 5422 polling-delay = <0>;
5462 thermal-sensors = <&t 5423 thermal-sensors = <&tsens1 14>;
5463 5424
5464 trips { 5425 trips {
5465 thermal-engin 5426 thermal-engine-config {
5466 tempe 5427 temperature = <125000>;
5467 hyste 5428 hysteresis = <1000>;
5468 type 5429 type = "passive";
5469 }; 5430 };
5470 5431
5471 reset-mon-cfg 5432 reset-mon-cfg {
5472 tempe 5433 temperature = <115000>;
5473 hyste 5434 hysteresis = <5000>;
5474 type 5435 type = "passive";
5475 }; 5436 };
5476 }; 5437 };
5477 }; 5438 };
5478 5439
5479 camera1-thermal { 5440 camera1-thermal {
>> 5441 polling-delay-passive = <0>;
>> 5442 polling-delay = <0>;
5480 thermal-sensors = <&t 5443 thermal-sensors = <&tsens1 15>;
5481 5444
5482 trips { 5445 trips {
5483 thermal-engin 5446 thermal-engine-config {
5484 tempe 5447 temperature = <125000>;
5485 hyste 5448 hysteresis = <1000>;
5486 type 5449 type = "passive";
5487 }; 5450 };
5488 5451
5489 reset-mon-cfg 5452 reset-mon-cfg {
5490 tempe 5453 temperature = <115000>;
5491 hyste 5454 hysteresis = <5000>;
5492 type 5455 type = "passive";
5493 }; 5456 };
5494 }; 5457 };
5495 }; 5458 };
5496 }; 5459 };
5497 5460
5498 timer { 5461 timer {
5499 compatible = "arm,armv8-timer 5462 compatible = "arm,armv8-timer";
5500 interrupts = <GIC_PPI 13 (GIC 5463 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5501 <GIC_PPI 14 (GIC 5464 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5502 <GIC_PPI 11 (GIC 5465 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5503 <GIC_PPI 10 (GIC 5466 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
5504 clock-frequency = <19200000>; 5467 clock-frequency = <19200000>;
5505 }; 5468 };
5506 }; 5469 };
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