1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * Copyright (c) 2021, Linaro Limited 3 * Copyright (c) 2021, Linaro Limited
4 */ 4 */
5 5
6 #include <dt-bindings/interrupt-controller/arm 6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-sm8450.h> 7 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
8 #include <dt-bindings/clock/qcom,rpmh.h> 8 #include <dt-bindings/clock/qcom,rpmh.h>
9 #include <dt-bindings/clock/qcom,sm8450-camcc. 9 #include <dt-bindings/clock/qcom,sm8450-camcc.h>
10 #include <dt-bindings/clock/qcom,sm8450-dispcc 10 #include <dt-bindings/clock/qcom,sm8450-dispcc.h>
11 #include <dt-bindings/clock/qcom,sm8450-gpucc. 11 #include <dt-bindings/clock/qcom,sm8450-gpucc.h>
12 #include <dt-bindings/clock/qcom,sm8450-videoc 12 #include <dt-bindings/clock/qcom,sm8450-videocc.h>
13 #include <dt-bindings/dma/qcom-gpi.h> 13 #include <dt-bindings/dma/qcom-gpi.h>
14 #include <dt-bindings/firmware/qcom,scm.h> 14 #include <dt-bindings/firmware/qcom,scm.h>
15 #include <dt-bindings/gpio/gpio.h> 15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/mailbox/qcom-ipcc.h> 16 #include <dt-bindings/mailbox/qcom-ipcc.h>
17 #include <dt-bindings/phy/phy-qcom-qmp.h> 17 #include <dt-bindings/phy/phy-qcom-qmp.h>
18 #include <dt-bindings/power/qcom,rpmhpd.h> 18 #include <dt-bindings/power/qcom,rpmhpd.h>
19 #include <dt-bindings/power/qcom-rpmpd.h> 19 #include <dt-bindings/power/qcom-rpmpd.h>
20 #include <dt-bindings/interconnect/qcom,icc.h> 20 #include <dt-bindings/interconnect/qcom,icc.h>
21 #include <dt-bindings/interconnect/qcom,sm8450 21 #include <dt-bindings/interconnect/qcom,sm8450.h>
22 #include <dt-bindings/reset/qcom,sm8450-gpucc. 22 #include <dt-bindings/reset/qcom,sm8450-gpucc.h>
23 #include <dt-bindings/soc/qcom,gpr.h> 23 #include <dt-bindings/soc/qcom,gpr.h>
24 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 24 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
25 #include <dt-bindings/sound/qcom,q6dsp-lpass-p 25 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
26 #include <dt-bindings/thermal/thermal.h> 26 #include <dt-bindings/thermal/thermal.h>
27 27
28 / { 28 / {
29 interrupt-parent = <&intc>; 29 interrupt-parent = <&intc>;
30 30
31 #address-cells = <2>; 31 #address-cells = <2>;
32 #size-cells = <2>; 32 #size-cells = <2>;
33 33
34 chosen { }; 34 chosen { };
35 35
36 clocks { 36 clocks {
37 xo_board: xo-board { 37 xo_board: xo-board {
38 compatible = "fixed-cl 38 compatible = "fixed-clock";
39 #clock-cells = <0>; 39 #clock-cells = <0>;
40 clock-frequency = <768 40 clock-frequency = <76800000>;
41 }; 41 };
42 42
43 sleep_clk: sleep-clk { 43 sleep_clk: sleep-clk {
44 compatible = "fixed-cl 44 compatible = "fixed-clock";
45 #clock-cells = <0>; 45 #clock-cells = <0>;
46 clock-frequency = <320 46 clock-frequency = <32000>;
47 }; 47 };
48 }; 48 };
49 49
50 cpus { 50 cpus {
51 #address-cells = <2>; 51 #address-cells = <2>;
52 #size-cells = <0>; 52 #size-cells = <0>;
53 53
54 CPU0: cpu@0 { 54 CPU0: cpu@0 {
55 device_type = "cpu"; 55 device_type = "cpu";
56 compatible = "qcom,kry 56 compatible = "qcom,kryo780";
57 reg = <0x0 0x0>; 57 reg = <0x0 0x0>;
58 enable-method = "psci" 58 enable-method = "psci";
59 next-level-cache = <&L 59 next-level-cache = <&L2_0>;
60 power-domains = <&CPU_ 60 power-domains = <&CPU_PD0>;
61 power-domain-names = " 61 power-domain-names = "psci";
62 qcom,freq-domain = <&c 62 qcom,freq-domain = <&cpufreq_hw 0>;
63 #cooling-cells = <2>; 63 #cooling-cells = <2>;
64 clocks = <&cpufreq_hw 64 clocks = <&cpufreq_hw 0>;
65 L2_0: l2-cache { 65 L2_0: l2-cache {
66 compatible = " 66 compatible = "cache";
67 cache-level = 67 cache-level = <2>;
68 cache-unified; 68 cache-unified;
69 next-level-cac 69 next-level-cache = <&L3_0>;
70 L3_0: l3-cache 70 L3_0: l3-cache {
71 compat 71 compatible = "cache";
72 cache- 72 cache-level = <3>;
73 cache- 73 cache-unified;
74 }; 74 };
75 }; 75 };
76 }; 76 };
77 77
78 CPU1: cpu@100 { 78 CPU1: cpu@100 {
79 device_type = "cpu"; 79 device_type = "cpu";
80 compatible = "qcom,kry 80 compatible = "qcom,kryo780";
81 reg = <0x0 0x100>; 81 reg = <0x0 0x100>;
82 enable-method = "psci" 82 enable-method = "psci";
83 next-level-cache = <&L 83 next-level-cache = <&L2_100>;
84 power-domains = <&CPU_ 84 power-domains = <&CPU_PD1>;
85 power-domain-names = " 85 power-domain-names = "psci";
86 qcom,freq-domain = <&c 86 qcom,freq-domain = <&cpufreq_hw 0>;
87 #cooling-cells = <2>; 87 #cooling-cells = <2>;
88 clocks = <&cpufreq_hw 88 clocks = <&cpufreq_hw 0>;
89 L2_100: l2-cache { 89 L2_100: l2-cache {
90 compatible = " 90 compatible = "cache";
91 cache-level = 91 cache-level = <2>;
92 cache-unified; 92 cache-unified;
93 next-level-cac 93 next-level-cache = <&L3_0>;
94 }; 94 };
95 }; 95 };
96 96
97 CPU2: cpu@200 { 97 CPU2: cpu@200 {
98 device_type = "cpu"; 98 device_type = "cpu";
99 compatible = "qcom,kry 99 compatible = "qcom,kryo780";
100 reg = <0x0 0x200>; 100 reg = <0x0 0x200>;
101 enable-method = "psci" 101 enable-method = "psci";
102 next-level-cache = <&L 102 next-level-cache = <&L2_200>;
103 power-domains = <&CPU_ 103 power-domains = <&CPU_PD2>;
104 power-domain-names = " 104 power-domain-names = "psci";
105 qcom,freq-domain = <&c 105 qcom,freq-domain = <&cpufreq_hw 0>;
106 #cooling-cells = <2>; 106 #cooling-cells = <2>;
107 clocks = <&cpufreq_hw 107 clocks = <&cpufreq_hw 0>;
108 L2_200: l2-cache { 108 L2_200: l2-cache {
109 compatible = " 109 compatible = "cache";
110 cache-level = 110 cache-level = <2>;
111 cache-unified; 111 cache-unified;
112 next-level-cac 112 next-level-cache = <&L3_0>;
113 }; 113 };
114 }; 114 };
115 115
116 CPU3: cpu@300 { 116 CPU3: cpu@300 {
117 device_type = "cpu"; 117 device_type = "cpu";
118 compatible = "qcom,kry 118 compatible = "qcom,kryo780";
119 reg = <0x0 0x300>; 119 reg = <0x0 0x300>;
120 enable-method = "psci" 120 enable-method = "psci";
121 next-level-cache = <&L 121 next-level-cache = <&L2_300>;
122 power-domains = <&CPU_ 122 power-domains = <&CPU_PD3>;
123 power-domain-names = " 123 power-domain-names = "psci";
124 qcom,freq-domain = <&c 124 qcom,freq-domain = <&cpufreq_hw 0>;
125 #cooling-cells = <2>; 125 #cooling-cells = <2>;
126 clocks = <&cpufreq_hw 126 clocks = <&cpufreq_hw 0>;
127 L2_300: l2-cache { 127 L2_300: l2-cache {
128 compatible = " 128 compatible = "cache";
129 cache-level = 129 cache-level = <2>;
130 cache-unified; 130 cache-unified;
131 next-level-cac 131 next-level-cache = <&L3_0>;
132 }; 132 };
133 }; 133 };
134 134
135 CPU4: cpu@400 { 135 CPU4: cpu@400 {
136 device_type = "cpu"; 136 device_type = "cpu";
137 compatible = "qcom,kry 137 compatible = "qcom,kryo780";
138 reg = <0x0 0x400>; 138 reg = <0x0 0x400>;
139 enable-method = "psci" 139 enable-method = "psci";
140 next-level-cache = <&L 140 next-level-cache = <&L2_400>;
141 power-domains = <&CPU_ 141 power-domains = <&CPU_PD4>;
142 power-domain-names = " 142 power-domain-names = "psci";
143 qcom,freq-domain = <&c 143 qcom,freq-domain = <&cpufreq_hw 1>;
144 #cooling-cells = <2>; 144 #cooling-cells = <2>;
145 clocks = <&cpufreq_hw 145 clocks = <&cpufreq_hw 1>;
146 L2_400: l2-cache { 146 L2_400: l2-cache {
147 compatible = " 147 compatible = "cache";
148 cache-level = 148 cache-level = <2>;
149 cache-unified; 149 cache-unified;
150 next-level-cac 150 next-level-cache = <&L3_0>;
151 }; 151 };
152 }; 152 };
153 153
154 CPU5: cpu@500 { 154 CPU5: cpu@500 {
155 device_type = "cpu"; 155 device_type = "cpu";
156 compatible = "qcom,kry 156 compatible = "qcom,kryo780";
157 reg = <0x0 0x500>; 157 reg = <0x0 0x500>;
158 enable-method = "psci" 158 enable-method = "psci";
159 next-level-cache = <&L 159 next-level-cache = <&L2_500>;
160 power-domains = <&CPU_ 160 power-domains = <&CPU_PD5>;
161 power-domain-names = " 161 power-domain-names = "psci";
162 qcom,freq-domain = <&c 162 qcom,freq-domain = <&cpufreq_hw 1>;
163 #cooling-cells = <2>; 163 #cooling-cells = <2>;
164 clocks = <&cpufreq_hw 164 clocks = <&cpufreq_hw 1>;
165 L2_500: l2-cache { 165 L2_500: l2-cache {
166 compatible = " 166 compatible = "cache";
167 cache-level = 167 cache-level = <2>;
168 cache-unified; 168 cache-unified;
169 next-level-cac 169 next-level-cache = <&L3_0>;
170 }; 170 };
171 }; 171 };
172 172
173 CPU6: cpu@600 { 173 CPU6: cpu@600 {
174 device_type = "cpu"; 174 device_type = "cpu";
175 compatible = "qcom,kry 175 compatible = "qcom,kryo780";
176 reg = <0x0 0x600>; 176 reg = <0x0 0x600>;
177 enable-method = "psci" 177 enable-method = "psci";
178 next-level-cache = <&L 178 next-level-cache = <&L2_600>;
179 power-domains = <&CPU_ 179 power-domains = <&CPU_PD6>;
180 power-domain-names = " 180 power-domain-names = "psci";
181 qcom,freq-domain = <&c 181 qcom,freq-domain = <&cpufreq_hw 1>;
182 #cooling-cells = <2>; 182 #cooling-cells = <2>;
183 clocks = <&cpufreq_hw 183 clocks = <&cpufreq_hw 1>;
184 L2_600: l2-cache { 184 L2_600: l2-cache {
185 compatible = " 185 compatible = "cache";
186 cache-level = 186 cache-level = <2>;
187 cache-unified; 187 cache-unified;
188 next-level-cac 188 next-level-cache = <&L3_0>;
189 }; 189 };
190 }; 190 };
191 191
192 CPU7: cpu@700 { 192 CPU7: cpu@700 {
193 device_type = "cpu"; 193 device_type = "cpu";
194 compatible = "qcom,kry 194 compatible = "qcom,kryo780";
195 reg = <0x0 0x700>; 195 reg = <0x0 0x700>;
196 enable-method = "psci" 196 enable-method = "psci";
197 next-level-cache = <&L 197 next-level-cache = <&L2_700>;
198 power-domains = <&CPU_ 198 power-domains = <&CPU_PD7>;
199 power-domain-names = " 199 power-domain-names = "psci";
200 qcom,freq-domain = <&c 200 qcom,freq-domain = <&cpufreq_hw 2>;
201 #cooling-cells = <2>; 201 #cooling-cells = <2>;
202 clocks = <&cpufreq_hw 202 clocks = <&cpufreq_hw 2>;
203 L2_700: l2-cache { 203 L2_700: l2-cache {
204 compatible = " 204 compatible = "cache";
205 cache-level = 205 cache-level = <2>;
206 cache-unified; 206 cache-unified;
207 next-level-cac 207 next-level-cache = <&L3_0>;
208 }; 208 };
209 }; 209 };
210 210
211 cpu-map { 211 cpu-map {
212 cluster0 { 212 cluster0 {
213 core0 { 213 core0 {
214 cpu = 214 cpu = <&CPU0>;
215 }; 215 };
216 216
217 core1 { 217 core1 {
218 cpu = 218 cpu = <&CPU1>;
219 }; 219 };
220 220
221 core2 { 221 core2 {
222 cpu = 222 cpu = <&CPU2>;
223 }; 223 };
224 224
225 core3 { 225 core3 {
226 cpu = 226 cpu = <&CPU3>;
227 }; 227 };
228 228
229 core4 { 229 core4 {
230 cpu = 230 cpu = <&CPU4>;
231 }; 231 };
232 232
233 core5 { 233 core5 {
234 cpu = 234 cpu = <&CPU5>;
235 }; 235 };
236 236
237 core6 { 237 core6 {
238 cpu = 238 cpu = <&CPU6>;
239 }; 239 };
240 240
241 core7 { 241 core7 {
242 cpu = 242 cpu = <&CPU7>;
243 }; 243 };
244 }; 244 };
245 }; 245 };
246 246
247 idle-states { 247 idle-states {
248 entry-method = "psci"; 248 entry-method = "psci";
249 249
250 LITTLE_CPU_SLEEP_0: cp 250 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
251 compatible = " 251 compatible = "arm,idle-state";
252 idle-state-nam 252 idle-state-name = "silver-rail-power-collapse";
253 arm,psci-suspe 253 arm,psci-suspend-param = <0x40000004>;
254 entry-latency- 254 entry-latency-us = <800>;
255 exit-latency-u 255 exit-latency-us = <750>;
256 min-residency- 256 min-residency-us = <4090>;
257 local-timer-st 257 local-timer-stop;
258 }; 258 };
259 259
260 BIG_CPU_SLEEP_0: cpu-s 260 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
261 compatible = " 261 compatible = "arm,idle-state";
262 idle-state-nam 262 idle-state-name = "gold-rail-power-collapse";
263 arm,psci-suspe 263 arm,psci-suspend-param = <0x40000004>;
264 entry-latency- 264 entry-latency-us = <600>;
265 exit-latency-u 265 exit-latency-us = <1550>;
266 min-residency- 266 min-residency-us = <4791>;
267 local-timer-st 267 local-timer-stop;
268 }; 268 };
269 }; 269 };
270 270
271 domain-idle-states { 271 domain-idle-states {
272 CLUSTER_SLEEP_0: clust 272 CLUSTER_SLEEP_0: cluster-sleep-0 {
273 compatible = " 273 compatible = "domain-idle-state";
274 arm,psci-suspe 274 arm,psci-suspend-param = <0x41000044>;
275 entry-latency- 275 entry-latency-us = <1050>;
276 exit-latency-u 276 exit-latency-us = <2500>;
277 min-residency- 277 min-residency-us = <5309>;
278 }; 278 };
279 279
280 CLUSTER_SLEEP_1: clust 280 CLUSTER_SLEEP_1: cluster-sleep-1 {
281 compatible = " 281 compatible = "domain-idle-state";
282 arm,psci-suspe 282 arm,psci-suspend-param = <0x4100c344>;
283 entry-latency- 283 entry-latency-us = <2700>;
284 exit-latency-u 284 exit-latency-us = <3500>;
285 min-residency- 285 min-residency-us = <13959>;
286 }; 286 };
287 }; 287 };
288 }; 288 };
289 289
290 firmware { 290 firmware {
291 scm: scm { 291 scm: scm {
292 compatible = "qcom,scm 292 compatible = "qcom,scm-sm8450", "qcom,scm";
293 qcom,dload-mode = <&tc 293 qcom,dload-mode = <&tcsr 0x13000>;
294 interconnects = <&aggr 294 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
295 #reset-cells = <1>; 295 #reset-cells = <1>;
296 }; 296 };
297 }; 297 };
298 298
299 clk_virt: interconnect-0 { 299 clk_virt: interconnect-0 {
300 compatible = "qcom,sm8450-clk- 300 compatible = "qcom,sm8450-clk-virt";
301 #interconnect-cells = <2>; 301 #interconnect-cells = <2>;
302 qcom,bcm-voters = <&apps_bcm_v 302 qcom,bcm-voters = <&apps_bcm_voter>;
303 }; 303 };
304 304
305 mc_virt: interconnect-1 { 305 mc_virt: interconnect-1 {
306 compatible = "qcom,sm8450-mc-v 306 compatible = "qcom,sm8450-mc-virt";
307 #interconnect-cells = <2>; 307 #interconnect-cells = <2>;
308 qcom,bcm-voters = <&apps_bcm_v 308 qcom,bcm-voters = <&apps_bcm_voter>;
309 }; 309 };
310 310
311 memory@a0000000 { 311 memory@a0000000 {
312 device_type = "memory"; 312 device_type = "memory";
313 /* We expect the bootloader to 313 /* We expect the bootloader to fill in the size */
314 reg = <0x0 0xa0000000 0x0 0x0> 314 reg = <0x0 0xa0000000 0x0 0x0>;
315 }; 315 };
316 316
317 pmu { 317 pmu {
318 compatible = "arm,armv8-pmuv3" 318 compatible = "arm,armv8-pmuv3";
319 interrupts = <GIC_PPI 7 IRQ_TY 319 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
320 }; 320 };
321 321
322 psci { 322 psci {
323 compatible = "arm,psci-1.0"; 323 compatible = "arm,psci-1.0";
324 method = "smc"; 324 method = "smc";
325 325
326 CPU_PD0: power-domain-cpu0 { 326 CPU_PD0: power-domain-cpu0 {
327 #power-domain-cells = 327 #power-domain-cells = <0>;
328 power-domains = <&CLUS 328 power-domains = <&CLUSTER_PD>;
329 domain-idle-states = < 329 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
330 }; 330 };
331 331
332 CPU_PD1: power-domain-cpu1 { 332 CPU_PD1: power-domain-cpu1 {
333 #power-domain-cells = 333 #power-domain-cells = <0>;
334 power-domains = <&CLUS 334 power-domains = <&CLUSTER_PD>;
335 domain-idle-states = < 335 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
336 }; 336 };
337 337
338 CPU_PD2: power-domain-cpu2 { 338 CPU_PD2: power-domain-cpu2 {
339 #power-domain-cells = 339 #power-domain-cells = <0>;
340 power-domains = <&CLUS 340 power-domains = <&CLUSTER_PD>;
341 domain-idle-states = < 341 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
342 }; 342 };
343 343
344 CPU_PD3: power-domain-cpu3 { 344 CPU_PD3: power-domain-cpu3 {
345 #power-domain-cells = 345 #power-domain-cells = <0>;
346 power-domains = <&CLUS 346 power-domains = <&CLUSTER_PD>;
347 domain-idle-states = < 347 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
348 }; 348 };
349 349
350 CPU_PD4: power-domain-cpu4 { 350 CPU_PD4: power-domain-cpu4 {
351 #power-domain-cells = 351 #power-domain-cells = <0>;
352 power-domains = <&CLUS 352 power-domains = <&CLUSTER_PD>;
353 domain-idle-states = < 353 domain-idle-states = <&BIG_CPU_SLEEP_0>;
354 }; 354 };
355 355
356 CPU_PD5: power-domain-cpu5 { 356 CPU_PD5: power-domain-cpu5 {
357 #power-domain-cells = 357 #power-domain-cells = <0>;
358 power-domains = <&CLUS 358 power-domains = <&CLUSTER_PD>;
359 domain-idle-states = < 359 domain-idle-states = <&BIG_CPU_SLEEP_0>;
360 }; 360 };
361 361
362 CPU_PD6: power-domain-cpu6 { 362 CPU_PD6: power-domain-cpu6 {
363 #power-domain-cells = 363 #power-domain-cells = <0>;
364 power-domains = <&CLUS 364 power-domains = <&CLUSTER_PD>;
365 domain-idle-states = < 365 domain-idle-states = <&BIG_CPU_SLEEP_0>;
366 }; 366 };
367 367
368 CPU_PD7: power-domain-cpu7 { 368 CPU_PD7: power-domain-cpu7 {
369 #power-domain-cells = 369 #power-domain-cells = <0>;
370 power-domains = <&CLUS 370 power-domains = <&CLUSTER_PD>;
371 domain-idle-states = < 371 domain-idle-states = <&BIG_CPU_SLEEP_0>;
372 }; 372 };
373 373
374 CLUSTER_PD: power-domain-cpu-c 374 CLUSTER_PD: power-domain-cpu-cluster0 {
375 #power-domain-cells = 375 #power-domain-cells = <0>;
376 domain-idle-states = < 376 domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>;
377 }; 377 };
378 }; 378 };
379 379
380 qup_opp_table_100mhz: opp-table-qup { 380 qup_opp_table_100mhz: opp-table-qup {
381 compatible = "operating-points 381 compatible = "operating-points-v2";
382 382
383 opp-50000000 { 383 opp-50000000 {
384 opp-hz = /bits/ 64 <50 384 opp-hz = /bits/ 64 <50000000>;
385 required-opps = <&rpmh 385 required-opps = <&rpmhpd_opp_min_svs>;
386 }; 386 };
387 387
388 opp-75000000 { 388 opp-75000000 {
389 opp-hz = /bits/ 64 <75 389 opp-hz = /bits/ 64 <75000000>;
390 required-opps = <&rpmh 390 required-opps = <&rpmhpd_opp_low_svs>;
391 }; 391 };
392 392
393 opp-100000000 { 393 opp-100000000 {
394 opp-hz = /bits/ 64 <10 394 opp-hz = /bits/ 64 <100000000>;
395 required-opps = <&rpmh 395 required-opps = <&rpmhpd_opp_svs>;
396 }; 396 };
397 }; 397 };
398 398
399 reserved_memory: reserved-memory { 399 reserved_memory: reserved-memory {
400 #address-cells = <2>; 400 #address-cells = <2>;
401 #size-cells = <2>; 401 #size-cells = <2>;
402 ranges; 402 ranges;
403 403
404 hyp_mem: memory@80000000 { 404 hyp_mem: memory@80000000 {
405 reg = <0x0 0x80000000 405 reg = <0x0 0x80000000 0x0 0x600000>;
406 no-map; 406 no-map;
407 }; 407 };
408 408
409 xbl_dt_log_mem: memory@8060000 409 xbl_dt_log_mem: memory@80600000 {
410 reg = <0x0 0x80600000 410 reg = <0x0 0x80600000 0x0 0x40000>;
411 no-map; 411 no-map;
412 }; 412 };
413 413
414 xbl_ramdump_mem: memory@806400 414 xbl_ramdump_mem: memory@80640000 {
415 reg = <0x0 0x80640000 415 reg = <0x0 0x80640000 0x0 0x180000>;
416 no-map; 416 no-map;
417 }; 417 };
418 418
419 xbl_sc_mem: memory@807c0000 { 419 xbl_sc_mem: memory@807c0000 {
420 reg = <0x0 0x807c0000 420 reg = <0x0 0x807c0000 0x0 0x40000>;
421 no-map; 421 no-map;
422 }; 422 };
423 423
424 aop_image_mem: memory@80800000 424 aop_image_mem: memory@80800000 {
425 reg = <0x0 0x80800000 425 reg = <0x0 0x80800000 0x0 0x60000>;
426 no-map; 426 no-map;
427 }; 427 };
428 428
429 aop_cmd_db_mem: memory@8086000 429 aop_cmd_db_mem: memory@80860000 {
430 compatible = "qcom,cmd 430 compatible = "qcom,cmd-db";
431 reg = <0x0 0x80860000 431 reg = <0x0 0x80860000 0x0 0x20000>;
432 no-map; 432 no-map;
433 }; 433 };
434 434
435 aop_config_mem: memory@8088000 435 aop_config_mem: memory@80880000 {
436 reg = <0x0 0x80880000 436 reg = <0x0 0x80880000 0x0 0x20000>;
437 no-map; 437 no-map;
438 }; 438 };
439 439
440 tme_crash_dump_mem: memory@808 440 tme_crash_dump_mem: memory@808a0000 {
441 reg = <0x0 0x808a0000 441 reg = <0x0 0x808a0000 0x0 0x40000>;
442 no-map; 442 no-map;
443 }; 443 };
444 444
445 tme_log_mem: memory@808e0000 { 445 tme_log_mem: memory@808e0000 {
446 reg = <0x0 0x808e0000 446 reg = <0x0 0x808e0000 0x0 0x4000>;
447 no-map; 447 no-map;
448 }; 448 };
449 449
450 uefi_log_mem: memory@808e4000 450 uefi_log_mem: memory@808e4000 {
451 reg = <0x0 0x808e4000 451 reg = <0x0 0x808e4000 0x0 0x10000>;
452 no-map; 452 no-map;
453 }; 453 };
454 454
455 /* secdata region can be reuse 455 /* secdata region can be reused by apps */
456 smem: memory@80900000 { 456 smem: memory@80900000 {
457 compatible = "qcom,sme 457 compatible = "qcom,smem";
458 reg = <0x0 0x80900000 458 reg = <0x0 0x80900000 0x0 0x200000>;
459 hwlocks = <&tcsr_mutex 459 hwlocks = <&tcsr_mutex 3>;
460 no-map; 460 no-map;
461 }; 461 };
462 462
463 cpucp_fw_mem: memory@80b00000 463 cpucp_fw_mem: memory@80b00000 {
464 reg = <0x0 0x80b00000 464 reg = <0x0 0x80b00000 0x0 0x100000>;
465 no-map; 465 no-map;
466 }; 466 };
467 467
468 cdsp_secure_heap: memory@80c00 468 cdsp_secure_heap: memory@80c00000 {
469 reg = <0x0 0x80c00000 469 reg = <0x0 0x80c00000 0x0 0x4600000>;
470 no-map; 470 no-map;
471 }; 471 };
472 472
473 video_mem: memory@85700000 { 473 video_mem: memory@85700000 {
474 reg = <0x0 0x85700000 474 reg = <0x0 0x85700000 0x0 0x700000>;
475 no-map; 475 no-map;
476 }; 476 };
477 477
478 adsp_mem: memory@85e00000 { 478 adsp_mem: memory@85e00000 {
479 reg = <0x0 0x85e00000 479 reg = <0x0 0x85e00000 0x0 0x2100000>;
480 no-map; 480 no-map;
481 }; 481 };
482 482
483 slpi_mem: memory@88000000 { 483 slpi_mem: memory@88000000 {
484 reg = <0x0 0x88000000 484 reg = <0x0 0x88000000 0x0 0x1900000>;
485 no-map; 485 no-map;
486 }; 486 };
487 487
488 cdsp_mem: memory@89900000 { 488 cdsp_mem: memory@89900000 {
489 reg = <0x0 0x89900000 489 reg = <0x0 0x89900000 0x0 0x2000000>;
490 no-map; 490 no-map;
491 }; 491 };
492 492
493 ipa_fw_mem: memory@8b900000 { 493 ipa_fw_mem: memory@8b900000 {
494 reg = <0x0 0x8b900000 494 reg = <0x0 0x8b900000 0x0 0x10000>;
495 no-map; 495 no-map;
496 }; 496 };
497 497
498 ipa_gsi_mem: memory@8b910000 { 498 ipa_gsi_mem: memory@8b910000 {
499 reg = <0x0 0x8b910000 499 reg = <0x0 0x8b910000 0x0 0xa000>;
500 no-map; 500 no-map;
501 }; 501 };
502 502
503 gpu_micro_code_mem: memory@8b9 503 gpu_micro_code_mem: memory@8b91a000 {
504 reg = <0x0 0x8b91a000 504 reg = <0x0 0x8b91a000 0x0 0x2000>;
505 no-map; 505 no-map;
506 }; 506 };
507 507
508 spss_region_mem: memory@8ba000 508 spss_region_mem: memory@8ba00000 {
509 reg = <0x0 0x8ba00000 509 reg = <0x0 0x8ba00000 0x0 0x180000>;
510 no-map; 510 no-map;
511 }; 511 };
512 512
513 /* First part of the "SPU secu 513 /* First part of the "SPU secure shared memory" region */
514 spu_tz_shared_mem: memory@8bb8 514 spu_tz_shared_mem: memory@8bb80000 {
515 reg = <0x0 0x8bb80000 515 reg = <0x0 0x8bb80000 0x0 0x60000>;
516 no-map; 516 no-map;
517 }; 517 };
518 518
519 /* Second part of the "SPU sec 519 /* Second part of the "SPU secure shared memory" region */
520 spu_modem_shared_mem: memory@8 520 spu_modem_shared_mem: memory@8bbe0000 {
521 reg = <0x0 0x8bbe0000 521 reg = <0x0 0x8bbe0000 0x0 0x20000>;
522 no-map; 522 no-map;
523 }; 523 };
524 524
525 mpss_mem: memory@8bc00000 { 525 mpss_mem: memory@8bc00000 {
526 reg = <0x0 0x8bc00000 526 reg = <0x0 0x8bc00000 0x0 0x13200000>;
527 no-map; 527 no-map;
528 }; 528 };
529 529
530 cvp_mem: memory@9ee00000 { 530 cvp_mem: memory@9ee00000 {
531 reg = <0x0 0x9ee00000 531 reg = <0x0 0x9ee00000 0x0 0x700000>;
532 no-map; 532 no-map;
533 }; 533 };
534 534
535 camera_mem: memory@9f500000 { 535 camera_mem: memory@9f500000 {
536 reg = <0x0 0x9f500000 536 reg = <0x0 0x9f500000 0x0 0x800000>;
537 no-map; 537 no-map;
538 }; 538 };
539 539
540 rmtfs_mem: memory@9fd00000 { 540 rmtfs_mem: memory@9fd00000 {
541 compatible = "qcom,rmt 541 compatible = "qcom,rmtfs-mem";
542 reg = <0x0 0x9fd00000 542 reg = <0x0 0x9fd00000 0x0 0x280000>;
543 no-map; 543 no-map;
544 544
545 qcom,client-id = <1>; 545 qcom,client-id = <1>;
546 qcom,vmid = <QCOM_SCM_ 546 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
547 }; 547 };
548 548
549 xbl_sc_mem2: memory@a6e00000 { 549 xbl_sc_mem2: memory@a6e00000 {
550 reg = <0x0 0xa6e00000 550 reg = <0x0 0xa6e00000 0x0 0x40000>;
551 no-map; 551 no-map;
552 }; 552 };
553 553
554 global_sync_mem: memory@a6f000 554 global_sync_mem: memory@a6f00000 {
555 reg = <0x0 0xa6f00000 555 reg = <0x0 0xa6f00000 0x0 0x100000>;
556 no-map; 556 no-map;
557 }; 557 };
558 558
559 /* uefi region can be reused b 559 /* uefi region can be reused by APPS */
560 560
561 /* Linux kernel image is loade 561 /* Linux kernel image is loaded at 0xa0000000 */
562 562
563 oem_vm_mem: memory@bb000000 { 563 oem_vm_mem: memory@bb000000 {
564 reg = <0x0 0xbb000000 564 reg = <0x0 0xbb000000 0x0 0x5000000>;
565 no-map; 565 no-map;
566 }; 566 };
567 567
568 mte_mem: memory@c0000000 { 568 mte_mem: memory@c0000000 {
569 reg = <0x0 0xc0000000 569 reg = <0x0 0xc0000000 0x0 0x20000000>;
570 no-map; 570 no-map;
571 }; 571 };
572 572
573 qheebsp_reserved_mem: memory@e 573 qheebsp_reserved_mem: memory@e0000000 {
574 reg = <0x0 0xe0000000 574 reg = <0x0 0xe0000000 0x0 0x600000>;
575 no-map; 575 no-map;
576 }; 576 };
577 577
578 cpusys_vm_mem: memory@e0600000 578 cpusys_vm_mem: memory@e0600000 {
579 reg = <0x0 0xe0600000 579 reg = <0x0 0xe0600000 0x0 0x400000>;
580 no-map; 580 no-map;
581 }; 581 };
582 582
583 hyp_reserved_mem: memory@e0a00 583 hyp_reserved_mem: memory@e0a00000 {
584 reg = <0x0 0xe0a00000 584 reg = <0x0 0xe0a00000 0x0 0x100000>;
585 no-map; 585 no-map;
586 }; 586 };
587 587
588 trust_ui_vm_mem: memory@e0b000 588 trust_ui_vm_mem: memory@e0b00000 {
589 reg = <0x0 0xe0b00000 589 reg = <0x0 0xe0b00000 0x0 0x4af3000>;
590 no-map; 590 no-map;
591 }; 591 };
592 592
593 trust_ui_vm_qrtr: memory@e55f3 593 trust_ui_vm_qrtr: memory@e55f3000 {
594 reg = <0x0 0xe55f3000 594 reg = <0x0 0xe55f3000 0x0 0x9000>;
595 no-map; 595 no-map;
596 }; 596 };
597 597
598 trust_ui_vm_vblk0_ring: memory 598 trust_ui_vm_vblk0_ring: memory@e55fc000 {
599 reg = <0x0 0xe55fc000 599 reg = <0x0 0xe55fc000 0x0 0x4000>;
600 no-map; 600 no-map;
601 }; 601 };
602 602
603 trust_ui_vm_swiotlb: memory@e5 603 trust_ui_vm_swiotlb: memory@e5600000 {
604 reg = <0x0 0xe5600000 604 reg = <0x0 0xe5600000 0x0 0x100000>;
605 no-map; 605 no-map;
606 }; 606 };
607 607
608 tz_stat_mem: memory@e8800000 { 608 tz_stat_mem: memory@e8800000 {
609 reg = <0x0 0xe8800000 609 reg = <0x0 0xe8800000 0x0 0x100000>;
610 no-map; 610 no-map;
611 }; 611 };
612 612
613 tags_mem: memory@e8900000 { 613 tags_mem: memory@e8900000 {
614 reg = <0x0 0xe8900000 614 reg = <0x0 0xe8900000 0x0 0x1200000>;
615 no-map; 615 no-map;
616 }; 616 };
617 617
618 qtee_mem: memory@e9b00000 { 618 qtee_mem: memory@e9b00000 {
619 reg = <0x0 0xe9b00000 619 reg = <0x0 0xe9b00000 0x0 0x500000>;
620 no-map; 620 no-map;
621 }; 621 };
622 622
623 trusted_apps_mem: memory@ea000 623 trusted_apps_mem: memory@ea000000 {
624 reg = <0x0 0xea000000 624 reg = <0x0 0xea000000 0x0 0x3900000>;
625 no-map; 625 no-map;
626 }; 626 };
627 627
628 trusted_apps_ext_mem: memory@e 628 trusted_apps_ext_mem: memory@ed900000 {
629 reg = <0x0 0xed900000 629 reg = <0x0 0xed900000 0x0 0x3b00000>;
630 no-map; 630 no-map;
631 }; 631 };
632 }; 632 };
633 633
634 smp2p-adsp { 634 smp2p-adsp {
635 compatible = "qcom,smp2p"; 635 compatible = "qcom,smp2p";
636 qcom,smem = <443>, <429>; 636 qcom,smem = <443>, <429>;
637 interrupts-extended = <&ipcc I 637 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
638 I 638 IPCC_MPROC_SIGNAL_SMP2P
639 I 639 IRQ_TYPE_EDGE_RISING>;
640 mboxes = <&ipcc IPCC_CLIENT_LP 640 mboxes = <&ipcc IPCC_CLIENT_LPASS
641 IPCC_MPROC_SIG 641 IPCC_MPROC_SIGNAL_SMP2P>;
642 642
643 qcom,local-pid = <0>; 643 qcom,local-pid = <0>;
644 qcom,remote-pid = <2>; 644 qcom,remote-pid = <2>;
645 645
646 smp2p_adsp_out: master-kernel 646 smp2p_adsp_out: master-kernel {
647 qcom,entry-name = "mas 647 qcom,entry-name = "master-kernel";
648 #qcom,smem-state-cells 648 #qcom,smem-state-cells = <1>;
649 }; 649 };
650 650
651 smp2p_adsp_in: slave-kernel { 651 smp2p_adsp_in: slave-kernel {
652 qcom,entry-name = "sla 652 qcom,entry-name = "slave-kernel";
653 interrupt-controller; 653 interrupt-controller;
654 #interrupt-cells = <2> 654 #interrupt-cells = <2>;
655 }; 655 };
656 }; 656 };
657 657
658 smp2p-cdsp { 658 smp2p-cdsp {
659 compatible = "qcom,smp2p"; 659 compatible = "qcom,smp2p";
660 qcom,smem = <94>, <432>; 660 qcom,smem = <94>, <432>;
661 interrupts-extended = <&ipcc I 661 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
662 I 662 IPCC_MPROC_SIGNAL_SMP2P
663 I 663 IRQ_TYPE_EDGE_RISING>;
664 mboxes = <&ipcc IPCC_CLIENT_CD 664 mboxes = <&ipcc IPCC_CLIENT_CDSP
665 IPCC_MPROC_SIG 665 IPCC_MPROC_SIGNAL_SMP2P>;
666 666
667 qcom,local-pid = <0>; 667 qcom,local-pid = <0>;
668 qcom,remote-pid = <5>; 668 qcom,remote-pid = <5>;
669 669
670 smp2p_cdsp_out: master-kernel 670 smp2p_cdsp_out: master-kernel {
671 qcom,entry-name = "mas 671 qcom,entry-name = "master-kernel";
672 #qcom,smem-state-cells 672 #qcom,smem-state-cells = <1>;
673 }; 673 };
674 674
675 smp2p_cdsp_in: slave-kernel { 675 smp2p_cdsp_in: slave-kernel {
676 qcom,entry-name = "sla 676 qcom,entry-name = "slave-kernel";
677 interrupt-controller; 677 interrupt-controller;
678 #interrupt-cells = <2> 678 #interrupt-cells = <2>;
679 }; 679 };
680 }; 680 };
681 681
682 smp2p-modem { 682 smp2p-modem {
683 compatible = "qcom,smp2p"; 683 compatible = "qcom,smp2p";
684 qcom,smem = <435>, <428>; 684 qcom,smem = <435>, <428>;
685 interrupts-extended = <&ipcc I 685 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
686 I 686 IPCC_MPROC_SIGNAL_SMP2P
687 I 687 IRQ_TYPE_EDGE_RISING>;
688 mboxes = <&ipcc IPCC_CLIENT_MP 688 mboxes = <&ipcc IPCC_CLIENT_MPSS
689 IPCC_MPROC_SIG 689 IPCC_MPROC_SIGNAL_SMP2P>;
690 690
691 qcom,local-pid = <0>; 691 qcom,local-pid = <0>;
692 qcom,remote-pid = <1>; 692 qcom,remote-pid = <1>;
693 693
694 smp2p_modem_out: master-kernel 694 smp2p_modem_out: master-kernel {
695 qcom,entry-name = "mas 695 qcom,entry-name = "master-kernel";
696 #qcom,smem-state-cells 696 #qcom,smem-state-cells = <1>;
697 }; 697 };
698 698
699 smp2p_modem_in: slave-kernel { 699 smp2p_modem_in: slave-kernel {
700 qcom,entry-name = "sla 700 qcom,entry-name = "slave-kernel";
701 interrupt-controller; 701 interrupt-controller;
702 #interrupt-cells = <2> 702 #interrupt-cells = <2>;
703 }; 703 };
704 704
705 ipa_smp2p_out: ipa-ap-to-modem 705 ipa_smp2p_out: ipa-ap-to-modem {
706 qcom,entry-name = "ipa 706 qcom,entry-name = "ipa";
707 #qcom,smem-state-cells 707 #qcom,smem-state-cells = <1>;
708 }; 708 };
709 709
710 ipa_smp2p_in: ipa-modem-to-ap 710 ipa_smp2p_in: ipa-modem-to-ap {
711 qcom,entry-name = "ipa 711 qcom,entry-name = "ipa";
712 interrupt-controller; 712 interrupt-controller;
713 #interrupt-cells = <2> 713 #interrupt-cells = <2>;
714 }; 714 };
715 }; 715 };
716 716
717 smp2p-slpi { 717 smp2p-slpi {
718 compatible = "qcom,smp2p"; 718 compatible = "qcom,smp2p";
719 qcom,smem = <481>, <430>; 719 qcom,smem = <481>, <430>;
720 interrupts-extended = <&ipcc I 720 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
721 I 721 IPCC_MPROC_SIGNAL_SMP2P
722 I 722 IRQ_TYPE_EDGE_RISING>;
723 mboxes = <&ipcc IPCC_CLIENT_SL 723 mboxes = <&ipcc IPCC_CLIENT_SLPI
724 IPCC_MPROC_SIG 724 IPCC_MPROC_SIGNAL_SMP2P>;
725 725
726 qcom,local-pid = <0>; 726 qcom,local-pid = <0>;
727 qcom,remote-pid = <3>; 727 qcom,remote-pid = <3>;
728 728
729 smp2p_slpi_out: master-kernel 729 smp2p_slpi_out: master-kernel {
730 qcom,entry-name = "mas 730 qcom,entry-name = "master-kernel";
731 #qcom,smem-state-cells 731 #qcom,smem-state-cells = <1>;
732 }; 732 };
733 733
734 smp2p_slpi_in: slave-kernel { 734 smp2p_slpi_in: slave-kernel {
735 qcom,entry-name = "sla 735 qcom,entry-name = "slave-kernel";
736 interrupt-controller; 736 interrupt-controller;
737 #interrupt-cells = <2> 737 #interrupt-cells = <2>;
738 }; 738 };
739 }; 739 };
740 740
741 soc: soc@0 { 741 soc: soc@0 {
742 #address-cells = <2>; 742 #address-cells = <2>;
743 #size-cells = <2>; 743 #size-cells = <2>;
744 ranges = <0 0 0 0 0x10 0>; 744 ranges = <0 0 0 0 0x10 0>;
745 dma-ranges = <0 0 0 0 0x10 0>; 745 dma-ranges = <0 0 0 0 0x10 0>;
746 compatible = "simple-bus"; 746 compatible = "simple-bus";
747 747
748 gcc: clock-controller@100000 { 748 gcc: clock-controller@100000 {
749 compatible = "qcom,gcc 749 compatible = "qcom,gcc-sm8450";
750 reg = <0x0 0x00100000 750 reg = <0x0 0x00100000 0x0 0x1f4200>;
751 #clock-cells = <1>; 751 #clock-cells = <1>;
752 #reset-cells = <1>; 752 #reset-cells = <1>;
753 #power-domain-cells = 753 #power-domain-cells = <1>;
754 clocks = <&rpmhcc RPMH 754 clocks = <&rpmhcc RPMH_CXO_CLK>,
755 <&sleep_clk>, 755 <&sleep_clk>,
756 <&pcie0_phy>, 756 <&pcie0_phy>,
757 <&pcie1_phy Q 757 <&pcie1_phy QMP_PCIE_PIPE_CLK>,
758 <&pcie1_phy Q 758 <&pcie1_phy QMP_PCIE_PHY_AUX_CLK>,
759 <&ufs_mem_phy 759 <&ufs_mem_phy 0>,
760 <&ufs_mem_phy 760 <&ufs_mem_phy 1>,
761 <&ufs_mem_phy 761 <&ufs_mem_phy 2>,
762 <&usb_1_qmpph 762 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
763 clock-names = "bi_tcxo 763 clock-names = "bi_tcxo",
764 "sleep_c 764 "sleep_clk",
765 "pcie_0_ 765 "pcie_0_pipe_clk",
766 "pcie_1_ 766 "pcie_1_pipe_clk",
767 "pcie_1_ 767 "pcie_1_phy_aux_clk",
768 "ufs_phy 768 "ufs_phy_rx_symbol_0_clk",
769 "ufs_phy 769 "ufs_phy_rx_symbol_1_clk",
770 "ufs_phy 770 "ufs_phy_tx_symbol_0_clk",
771 "usb3_ph 771 "usb3_phy_wrapper_gcc_usb30_pipe_clk";
772 }; 772 };
773 773
774 gpi_dma2: dma-controller@80000 774 gpi_dma2: dma-controller@800000 {
775 compatible = "qcom,sm8 775 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
776 #dma-cells = <3>; 776 #dma-cells = <3>;
777 reg = <0 0x00800000 0 777 reg = <0 0x00800000 0 0x60000>;
778 interrupts = <GIC_SPI 778 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
779 <GIC_SPI 779 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
780 <GIC_SPI 780 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
781 <GIC_SPI 781 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
782 <GIC_SPI 782 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
783 <GIC_SPI 783 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
784 <GIC_SPI 784 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
785 <GIC_SPI 785 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
786 <GIC_SPI 786 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
787 <GIC_SPI 787 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
788 <GIC_SPI 788 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
789 <GIC_SPI 789 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
790 dma-channels = <12>; 790 dma-channels = <12>;
791 dma-channel-mask = <0x 791 dma-channel-mask = <0x7e>;
792 iommus = <&apps_smmu 0 792 iommus = <&apps_smmu 0x496 0x0>;
793 status = "disabled"; 793 status = "disabled";
794 }; 794 };
795 795
796 qupv3_id_2: geniqup@8c0000 { 796 qupv3_id_2: geniqup@8c0000 {
797 compatible = "qcom,gen 797 compatible = "qcom,geni-se-qup";
798 reg = <0x0 0x008c0000 798 reg = <0x0 0x008c0000 0x0 0x2000>;
799 clock-names = "m-ahb", 799 clock-names = "m-ahb", "s-ahb";
800 clocks = <&gcc GCC_QUP 800 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
801 <&gcc GCC_QUP 801 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
802 iommus = <&apps_smmu 0 802 iommus = <&apps_smmu 0x483 0x0>;
803 #address-cells = <2>; 803 #address-cells = <2>;
804 #size-cells = <2>; 804 #size-cells = <2>;
805 ranges; 805 ranges;
806 status = "disabled"; 806 status = "disabled";
807 807
808 i2c15: i2c@880000 { 808 i2c15: i2c@880000 {
809 compatible = " 809 compatible = "qcom,geni-i2c";
810 reg = <0x0 0x0 810 reg = <0x0 0x00880000 0x0 0x4000>;
811 clock-names = 811 clock-names = "se";
812 clocks = <&gcc 812 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
813 pinctrl-names 813 pinctrl-names = "default";
814 pinctrl-0 = <& 814 pinctrl-0 = <&qup_i2c15_data_clk>;
815 interrupts = < 815 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
816 #address-cells 816 #address-cells = <1>;
817 #size-cells = 817 #size-cells = <0>;
818 interconnects 818 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
819 819 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
820 820 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
821 interconnect-n 821 interconnect-names = "qup-core", "qup-config", "qup-memory";
822 dmas = <&gpi_d 822 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
823 <&gpi_d 823 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
824 dma-names = "t 824 dma-names = "tx", "rx";
825 status = "disa 825 status = "disabled";
826 }; 826 };
827 827
828 spi15: spi@880000 { 828 spi15: spi@880000 {
829 compatible = " 829 compatible = "qcom,geni-spi";
830 reg = <0x0 0x0 830 reg = <0x0 0x00880000 0x0 0x4000>;
831 clock-names = 831 clock-names = "se";
832 clocks = <&gcc 832 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
833 interrupts = < 833 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
834 pinctrl-names 834 pinctrl-names = "default";
835 pinctrl-0 = <& 835 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
836 interconnects 836 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
837 837 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
838 interconnect-n 838 interconnect-names = "qup-core", "qup-config";
839 dmas = <&gpi_d 839 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
840 <&gpi_d 840 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
841 dma-names = "t 841 dma-names = "tx", "rx";
842 #address-cells 842 #address-cells = <1>;
843 #size-cells = 843 #size-cells = <0>;
844 status = "disa 844 status = "disabled";
845 }; 845 };
846 846
847 i2c16: i2c@884000 { 847 i2c16: i2c@884000 {
848 compatible = " 848 compatible = "qcom,geni-i2c";
849 reg = <0x0 0x0 849 reg = <0x0 0x00884000 0x0 0x4000>;
850 clock-names = 850 clock-names = "se";
851 clocks = <&gcc 851 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
852 pinctrl-names 852 pinctrl-names = "default";
853 pinctrl-0 = <& 853 pinctrl-0 = <&qup_i2c16_data_clk>;
854 interrupts = < 854 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
855 #address-cells 855 #address-cells = <1>;
856 #size-cells = 856 #size-cells = <0>;
857 interconnects 857 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
858 858 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
859 859 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
860 interconnect-n 860 interconnect-names = "qup-core", "qup-config", "qup-memory";
861 dmas = <&gpi_d 861 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
862 <&gpi_d 862 <&gpi_dma2 1 1 QCOM_GPI_I2C>;
863 dma-names = "t 863 dma-names = "tx", "rx";
864 status = "disa 864 status = "disabled";
865 }; 865 };
866 866
867 spi16: spi@884000 { 867 spi16: spi@884000 {
868 compatible = " 868 compatible = "qcom,geni-spi";
869 reg = <0x0 0x0 869 reg = <0x0 0x00884000 0x0 0x4000>;
870 clock-names = 870 clock-names = "se";
871 clocks = <&gcc 871 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
872 interrupts = < 872 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
873 pinctrl-names 873 pinctrl-names = "default";
874 pinctrl-0 = <& 874 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>;
875 interconnects 875 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
876 876 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
877 interconnect-n 877 interconnect-names = "qup-core", "qup-config";
878 dmas = <&gpi_d 878 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
879 <&gpi_d 879 <&gpi_dma2 1 1 QCOM_GPI_SPI>;
880 dma-names = "t 880 dma-names = "tx", "rx";
881 #address-cells 881 #address-cells = <1>;
882 #size-cells = 882 #size-cells = <0>;
883 status = "disa 883 status = "disabled";
884 }; 884 };
885 885
886 i2c17: i2c@888000 { 886 i2c17: i2c@888000 {
887 compatible = " 887 compatible = "qcom,geni-i2c";
888 reg = <0x0 0x0 888 reg = <0x0 0x00888000 0x0 0x4000>;
889 clock-names = 889 clock-names = "se";
890 clocks = <&gcc 890 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
891 pinctrl-names 891 pinctrl-names = "default";
892 pinctrl-0 = <& 892 pinctrl-0 = <&qup_i2c17_data_clk>;
893 interrupts = < 893 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
894 #address-cells 894 #address-cells = <1>;
895 #size-cells = 895 #size-cells = <0>;
896 interconnects 896 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
897 897 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
898 898 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
899 interconnect-n 899 interconnect-names = "qup-core", "qup-config", "qup-memory";
900 dmas = <&gpi_d 900 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
901 <&gpi_d 901 <&gpi_dma2 1 2 QCOM_GPI_I2C>;
902 dma-names = "t 902 dma-names = "tx", "rx";
903 status = "disa 903 status = "disabled";
904 }; 904 };
905 905
906 spi17: spi@888000 { 906 spi17: spi@888000 {
907 compatible = " 907 compatible = "qcom,geni-spi";
908 reg = <0x0 0x0 908 reg = <0x0 0x00888000 0x0 0x4000>;
909 clock-names = 909 clock-names = "se";
910 clocks = <&gcc 910 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
911 interrupts = < 911 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
912 pinctrl-names 912 pinctrl-names = "default";
913 pinctrl-0 = <& 913 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>;
914 interconnects 914 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
915 915 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
916 interconnect-n 916 interconnect-names = "qup-core", "qup-config";
917 dmas = <&gpi_d 917 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
918 <&gpi_d 918 <&gpi_dma2 1 2 QCOM_GPI_SPI>;
919 dma-names = "t 919 dma-names = "tx", "rx";
920 #address-cells 920 #address-cells = <1>;
921 #size-cells = 921 #size-cells = <0>;
922 status = "disa 922 status = "disabled";
923 }; 923 };
924 924
925 i2c18: i2c@88c000 { 925 i2c18: i2c@88c000 {
926 compatible = " 926 compatible = "qcom,geni-i2c";
927 reg = <0x0 0x0 927 reg = <0x0 0x0088c000 0x0 0x4000>;
928 clock-names = 928 clock-names = "se";
929 clocks = <&gcc 929 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
930 pinctrl-names 930 pinctrl-names = "default";
931 pinctrl-0 = <& 931 pinctrl-0 = <&qup_i2c18_data_clk>;
932 interrupts = < 932 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
933 #address-cells 933 #address-cells = <1>;
934 #size-cells = 934 #size-cells = <0>;
935 interconnects 935 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
936 936 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
937 937 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
938 interconnect-n 938 interconnect-names = "qup-core", "qup-config", "qup-memory";
939 dmas = <&gpi_d 939 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
940 <&gpi_d 940 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
941 dma-names = "t 941 dma-names = "tx", "rx";
942 status = "disa 942 status = "disabled";
943 }; 943 };
944 944
945 spi18: spi@88c000 { 945 spi18: spi@88c000 {
946 compatible = " 946 compatible = "qcom,geni-spi";
947 reg = <0 0x008 947 reg = <0 0x0088c000 0 0x4000>;
948 clock-names = 948 clock-names = "se";
949 clocks = <&gcc 949 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
950 interrupts = < 950 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
951 pinctrl-names 951 pinctrl-names = "default";
952 pinctrl-0 = <& 952 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>;
953 interconnects 953 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
954 954 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
955 interconnect-n 955 interconnect-names = "qup-core", "qup-config";
956 dmas = <&gpi_d 956 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
957 <&gpi_d 957 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
958 dma-names = "t 958 dma-names = "tx", "rx";
959 #address-cells 959 #address-cells = <1>;
960 #size-cells = 960 #size-cells = <0>;
961 status = "disa 961 status = "disabled";
962 }; 962 };
963 963
964 i2c19: i2c@890000 { 964 i2c19: i2c@890000 {
965 compatible = " 965 compatible = "qcom,geni-i2c";
966 reg = <0x0 0x0 966 reg = <0x0 0x00890000 0x0 0x4000>;
967 clock-names = 967 clock-names = "se";
968 clocks = <&gcc 968 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
969 pinctrl-names 969 pinctrl-names = "default";
970 pinctrl-0 = <& 970 pinctrl-0 = <&qup_i2c19_data_clk>;
971 interrupts = < 971 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
972 #address-cells 972 #address-cells = <1>;
973 #size-cells = 973 #size-cells = <0>;
974 interconnects 974 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
975 975 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
976 976 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
977 interconnect-n 977 interconnect-names = "qup-core", "qup-config", "qup-memory";
978 dmas = <&gpi_d 978 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
979 <&gpi_d 979 <&gpi_dma2 1 4 QCOM_GPI_I2C>;
980 dma-names = "t 980 dma-names = "tx", "rx";
981 status = "disa 981 status = "disabled";
982 }; 982 };
983 983
984 spi19: spi@890000 { 984 spi19: spi@890000 {
985 compatible = " 985 compatible = "qcom,geni-spi";
986 reg = <0 0x008 986 reg = <0 0x00890000 0 0x4000>;
987 clock-names = 987 clock-names = "se";
988 clocks = <&gcc 988 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
989 interrupts = < 989 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
990 pinctrl-names 990 pinctrl-names = "default";
991 pinctrl-0 = <& 991 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>;
992 interconnects 992 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
993 993 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
994 interconnect-n 994 interconnect-names = "qup-core", "qup-config";
995 dmas = <&gpi_d 995 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
996 <&gpi_d 996 <&gpi_dma2 1 4 QCOM_GPI_I2C>;
997 dma-names = "t 997 dma-names = "tx", "rx";
998 #address-cells 998 #address-cells = <1>;
999 #size-cells = 999 #size-cells = <0>;
1000 status = "dis 1000 status = "disabled";
1001 }; 1001 };
1002 1002
1003 i2c20: i2c@894000 { 1003 i2c20: i2c@894000 {
1004 compatible = 1004 compatible = "qcom,geni-i2c";
1005 reg = <0x0 0x 1005 reg = <0x0 0x00894000 0x0 0x4000>;
1006 clock-names = 1006 clock-names = "se";
1007 clocks = <&gc 1007 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1008 pinctrl-names 1008 pinctrl-names = "default";
1009 pinctrl-0 = < 1009 pinctrl-0 = <&qup_i2c20_data_clk>;
1010 interrupts = 1010 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1011 #address-cell 1011 #address-cells = <1>;
1012 #size-cells = 1012 #size-cells = <0>;
1013 interconnects 1013 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1014 1014 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1015 1015 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1016 interconnect- 1016 interconnect-names = "qup-core", "qup-config", "qup-memory";
1017 dmas = <&gpi_ 1017 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1018 <&gpi_ 1018 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1019 dma-names = " 1019 dma-names = "tx", "rx";
1020 status = "dis 1020 status = "disabled";
1021 }; 1021 };
1022 1022
1023 uart20: serial@894000 1023 uart20: serial@894000 {
1024 compatible = 1024 compatible = "qcom,geni-uart";
1025 reg = <0 0x00 1025 reg = <0 0x00894000 0 0x4000>;
1026 clock-names = 1026 clock-names = "se";
1027 clocks = <&gc 1027 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1028 pinctrl-names 1028 pinctrl-names = "default";
1029 pinctrl-0 = < 1029 pinctrl-0 = <&qup_uart20_default>;
1030 interrupts = 1030 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1031 interconnects 1031 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1032 1032 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1033 1033 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1034 1034 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
1035 interconnect- 1035 interconnect-names = "qup-core",
1036 1036 "qup-config";
1037 status = "dis 1037 status = "disabled";
1038 }; 1038 };
1039 1039
1040 spi20: spi@894000 { 1040 spi20: spi@894000 {
1041 compatible = 1041 compatible = "qcom,geni-spi";
1042 reg = <0 0x00 1042 reg = <0 0x00894000 0 0x4000>;
1043 clock-names = 1043 clock-names = "se";
1044 clocks = <&gc 1044 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1045 interrupts = 1045 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1046 pinctrl-names 1046 pinctrl-names = "default";
1047 pinctrl-0 = < 1047 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>;
1048 interconnects 1048 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1049 1049 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
1050 interconnect- 1050 interconnect-names = "qup-core", "qup-config";
1051 dmas = <&gpi_ 1051 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1052 <&gpi_ 1052 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1053 dma-names = " 1053 dma-names = "tx", "rx";
1054 #address-cell 1054 #address-cells = <1>;
1055 #size-cells = 1055 #size-cells = <0>;
1056 status = "dis 1056 status = "disabled";
1057 }; 1057 };
1058 1058
1059 i2c21: i2c@898000 { 1059 i2c21: i2c@898000 {
1060 compatible = 1060 compatible = "qcom,geni-i2c";
1061 reg = <0x0 0x 1061 reg = <0x0 0x00898000 0x0 0x4000>;
1062 clock-names = 1062 clock-names = "se";
1063 clocks = <&gc 1063 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1064 pinctrl-names 1064 pinctrl-names = "default";
1065 pinctrl-0 = < 1065 pinctrl-0 = <&qup_i2c21_data_clk>;
1066 interrupts = 1066 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
1067 #address-cell 1067 #address-cells = <1>;
1068 #size-cells = 1068 #size-cells = <0>;
1069 interconnects 1069 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1070 1070 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1071 1071 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1072 interconnect- 1072 interconnect-names = "qup-core", "qup-config", "qup-memory";
1073 dmas = <&gpi_ 1073 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>,
1074 <&gpi_ 1074 <&gpi_dma2 1 6 QCOM_GPI_I2C>;
1075 dma-names = " 1075 dma-names = "tx", "rx";
1076 status = "dis 1076 status = "disabled";
1077 }; 1077 };
1078 1078
1079 spi21: spi@898000 { 1079 spi21: spi@898000 {
1080 compatible = 1080 compatible = "qcom,geni-spi";
1081 reg = <0 0x00 1081 reg = <0 0x00898000 0 0x4000>;
1082 clock-names = 1082 clock-names = "se";
1083 clocks = <&gc 1083 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1084 interrupts = 1084 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
1085 pinctrl-names 1085 pinctrl-names = "default";
1086 pinctrl-0 = < 1086 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>;
1087 interconnects 1087 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1088 1088 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
1089 interconnect- 1089 interconnect-names = "qup-core", "qup-config";
1090 dmas = <&gpi_ 1090 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>,
1091 <&gpi_ 1091 <&gpi_dma2 1 6 QCOM_GPI_SPI>;
1092 dma-names = " 1092 dma-names = "tx", "rx";
1093 #address-cell 1093 #address-cells = <1>;
1094 #size-cells = 1094 #size-cells = <0>;
1095 status = "dis 1095 status = "disabled";
1096 }; 1096 };
1097 }; 1097 };
1098 1098
1099 gpi_dma0: dma-controller@9000 1099 gpi_dma0: dma-controller@900000 {
1100 compatible = "qcom,sm 1100 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
1101 #dma-cells = <3>; 1101 #dma-cells = <3>;
1102 reg = <0 0x00900000 0 1102 reg = <0 0x00900000 0 0x60000>;
1103 interrupts = <GIC_SPI 1103 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
1104 <GIC_SPI 1104 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
1105 <GIC_SPI 1105 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
1106 <GIC_SPI 1106 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
1107 <GIC_SPI 1107 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
1108 <GIC_SPI 1108 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
1109 <GIC_SPI 1109 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
1110 <GIC_SPI 1110 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
1111 <GIC_SPI 1111 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
1112 <GIC_SPI 1112 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
1113 <GIC_SPI 1113 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
1114 <GIC_SPI 1114 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
1115 dma-channels = <12>; 1115 dma-channels = <12>;
1116 dma-channel-mask = <0 1116 dma-channel-mask = <0x7e>;
1117 iommus = <&apps_smmu 1117 iommus = <&apps_smmu 0x5b6 0x0>;
1118 status = "disabled"; 1118 status = "disabled";
1119 }; 1119 };
1120 1120
1121 qupv3_id_0: geniqup@9c0000 { 1121 qupv3_id_0: geniqup@9c0000 {
1122 compatible = "qcom,ge 1122 compatible = "qcom,geni-se-qup";
1123 reg = <0x0 0x009c0000 1123 reg = <0x0 0x009c0000 0x0 0x2000>;
1124 clock-names = "m-ahb" 1124 clock-names = "m-ahb", "s-ahb";
1125 clocks = <&gcc GCC_QU 1125 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1126 <&gcc GCC_QU 1126 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1127 iommus = <&apps_smmu 1127 iommus = <&apps_smmu 0x5a3 0x0>;
1128 interconnects = <&clk 1128 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>;
1129 interconnect-names = 1129 interconnect-names = "qup-core";
1130 #address-cells = <2>; 1130 #address-cells = <2>;
1131 #size-cells = <2>; 1131 #size-cells = <2>;
1132 ranges; 1132 ranges;
1133 status = "disabled"; 1133 status = "disabled";
1134 1134
1135 i2c0: i2c@980000 { 1135 i2c0: i2c@980000 {
1136 compatible = 1136 compatible = "qcom,geni-i2c";
1137 reg = <0x0 0x 1137 reg = <0x0 0x00980000 0x0 0x4000>;
1138 clock-names = 1138 clock-names = "se";
1139 clocks = <&gc 1139 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1140 pinctrl-names 1140 pinctrl-names = "default";
1141 pinctrl-0 = < 1141 pinctrl-0 = <&qup_i2c0_data_clk>;
1142 interrupts = 1142 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1143 #address-cell 1143 #address-cells = <1>;
1144 #size-cells = 1144 #size-cells = <0>;
1145 interconnects 1145 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1146 1146 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1147 1147 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1148 interconnect- 1148 interconnect-names = "qup-core", "qup-config", "qup-memory";
1149 dmas = <&gpi_ 1149 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1150 <&gpi_ 1150 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1151 dma-names = " 1151 dma-names = "tx", "rx";
1152 status = "dis 1152 status = "disabled";
1153 }; 1153 };
1154 1154
1155 spi0: spi@980000 { 1155 spi0: spi@980000 {
1156 compatible = 1156 compatible = "qcom,geni-spi";
1157 reg = <0x0 0x 1157 reg = <0x0 0x00980000 0x0 0x4000>;
1158 clock-names = 1158 clock-names = "se";
1159 clocks = <&gc 1159 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1160 interrupts = 1160 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1161 pinctrl-names 1161 pinctrl-names = "default";
1162 pinctrl-0 = < 1162 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1163 power-domains 1163 power-domains = <&rpmhpd RPMHPD_CX>;
1164 operating-poi 1164 operating-points-v2 = <&qup_opp_table_100mhz>;
1165 interconnects 1165 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1166 1166 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1167 1167 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1168 interconnect- 1168 interconnect-names = "qup-core", "qup-config", "qup-memory";
1169 dmas = <&gpi_ 1169 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1170 <&gpi_ 1170 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1171 dma-names = " 1171 dma-names = "tx", "rx";
1172 #address-cell 1172 #address-cells = <1>;
1173 #size-cells = 1173 #size-cells = <0>;
1174 status = "dis 1174 status = "disabled";
1175 }; 1175 };
1176 1176
1177 i2c1: i2c@984000 { 1177 i2c1: i2c@984000 {
1178 compatible = 1178 compatible = "qcom,geni-i2c";
1179 reg = <0x0 0x 1179 reg = <0x0 0x00984000 0x0 0x4000>;
1180 clock-names = 1180 clock-names = "se";
1181 clocks = <&gc 1181 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1182 pinctrl-names 1182 pinctrl-names = "default";
1183 pinctrl-0 = < 1183 pinctrl-0 = <&qup_i2c1_data_clk>;
1184 interrupts = 1184 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1185 #address-cell 1185 #address-cells = <1>;
1186 #size-cells = 1186 #size-cells = <0>;
1187 interconnects 1187 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1188 1188 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1189 1189 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1190 interconnect- 1190 interconnect-names = "qup-core", "qup-config", "qup-memory";
1191 dmas = <&gpi_ 1191 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1192 <&gpi_ 1192 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1193 dma-names = " 1193 dma-names = "tx", "rx";
1194 status = "dis 1194 status = "disabled";
1195 }; 1195 };
1196 1196
1197 spi1: spi@984000 { 1197 spi1: spi@984000 {
1198 compatible = 1198 compatible = "qcom,geni-spi";
1199 reg = <0x0 0x 1199 reg = <0x0 0x00984000 0x0 0x4000>;
1200 clock-names = 1200 clock-names = "se";
1201 clocks = <&gc 1201 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1202 interrupts = 1202 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1203 pinctrl-names 1203 pinctrl-names = "default";
1204 pinctrl-0 = < 1204 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1205 interconnects 1205 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1206 1206 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1207 1207 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1208 interconnect- 1208 interconnect-names = "qup-core", "qup-config", "qup-memory";
1209 dmas = <&gpi_ 1209 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1210 <&gpi_ 1210 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1211 dma-names = " 1211 dma-names = "tx", "rx";
1212 #address-cell 1212 #address-cells = <1>;
1213 #size-cells = 1213 #size-cells = <0>;
1214 status = "dis 1214 status = "disabled";
1215 }; 1215 };
1216 1216
1217 i2c2: i2c@988000 { 1217 i2c2: i2c@988000 {
1218 compatible = 1218 compatible = "qcom,geni-i2c";
1219 reg = <0x0 0x 1219 reg = <0x0 0x00988000 0x0 0x4000>;
1220 clock-names = 1220 clock-names = "se";
1221 clocks = <&gc 1221 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1222 pinctrl-names 1222 pinctrl-names = "default";
1223 pinctrl-0 = < 1223 pinctrl-0 = <&qup_i2c2_data_clk>;
1224 interrupts = 1224 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1225 #address-cell 1225 #address-cells = <1>;
1226 #size-cells = 1226 #size-cells = <0>;
1227 interconnects 1227 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1228 1228 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1229 1229 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1230 interconnect- 1230 interconnect-names = "qup-core", "qup-config", "qup-memory";
1231 dmas = <&gpi_ 1231 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1232 <&gpi_ 1232 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1233 dma-names = " 1233 dma-names = "tx", "rx";
1234 status = "dis 1234 status = "disabled";
1235 }; 1235 };
1236 1236
1237 spi2: spi@988000 { 1237 spi2: spi@988000 {
1238 compatible = 1238 compatible = "qcom,geni-spi";
1239 reg = <0x0 0x 1239 reg = <0x0 0x00988000 0x0 0x4000>;
1240 clock-names = 1240 clock-names = "se";
1241 clocks = <&gc 1241 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1242 interrupts = 1242 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1243 pinctrl-names 1243 pinctrl-names = "default";
1244 pinctrl-0 = < 1244 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1245 interconnects 1245 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1246 1246 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1247 1247 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1248 interconnect- 1248 interconnect-names = "qup-core", "qup-config", "qup-memory";
1249 dmas = <&gpi_ 1249 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1250 <&gpi_ 1250 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1251 dma-names = " 1251 dma-names = "tx", "rx";
1252 #address-cell 1252 #address-cells = <1>;
1253 #size-cells = 1253 #size-cells = <0>;
1254 status = "dis 1254 status = "disabled";
1255 }; 1255 };
1256 1256
1257 1257
1258 i2c3: i2c@98c000 { 1258 i2c3: i2c@98c000 {
1259 compatible = 1259 compatible = "qcom,geni-i2c";
1260 reg = <0x0 0x 1260 reg = <0x0 0x0098c000 0x0 0x4000>;
1261 clock-names = 1261 clock-names = "se";
1262 clocks = <&gc 1262 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1263 pinctrl-names 1263 pinctrl-names = "default";
1264 pinctrl-0 = < 1264 pinctrl-0 = <&qup_i2c3_data_clk>;
1265 interrupts = 1265 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1266 #address-cell 1266 #address-cells = <1>;
1267 #size-cells = 1267 #size-cells = <0>;
1268 interconnects 1268 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1269 1269 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1270 1270 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1271 interconnect- 1271 interconnect-names = "qup-core", "qup-config", "qup-memory";
1272 dmas = <&gpi_ 1272 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1273 <&gpi_ 1273 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1274 dma-names = " 1274 dma-names = "tx", "rx";
1275 status = "dis 1275 status = "disabled";
1276 }; 1276 };
1277 1277
1278 spi3: spi@98c000 { 1278 spi3: spi@98c000 {
1279 compatible = 1279 compatible = "qcom,geni-spi";
1280 reg = <0x0 0x 1280 reg = <0x0 0x0098c000 0x0 0x4000>;
1281 clock-names = 1281 clock-names = "se";
1282 clocks = <&gc 1282 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1283 interrupts = 1283 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1284 pinctrl-names 1284 pinctrl-names = "default";
1285 pinctrl-0 = < 1285 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1286 interconnects 1286 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1287 1287 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1288 1288 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1289 interconnect- 1289 interconnect-names = "qup-core", "qup-config", "qup-memory";
1290 dmas = <&gpi_ 1290 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1291 <&gpi_ 1291 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1292 dma-names = " 1292 dma-names = "tx", "rx";
1293 #address-cell 1293 #address-cells = <1>;
1294 #size-cells = 1294 #size-cells = <0>;
1295 status = "dis 1295 status = "disabled";
1296 }; 1296 };
1297 1297
1298 i2c4: i2c@990000 { 1298 i2c4: i2c@990000 {
1299 compatible = 1299 compatible = "qcom,geni-i2c";
1300 reg = <0x0 0x 1300 reg = <0x0 0x00990000 0x0 0x4000>;
1301 clock-names = 1301 clock-names = "se";
1302 clocks = <&gc 1302 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1303 pinctrl-names 1303 pinctrl-names = "default";
1304 pinctrl-0 = < 1304 pinctrl-0 = <&qup_i2c4_data_clk>;
1305 interrupts = 1305 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1306 #address-cell 1306 #address-cells = <1>;
1307 #size-cells = 1307 #size-cells = <0>;
1308 interconnects 1308 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1309 1309 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1310 1310 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1311 interconnect- 1311 interconnect-names = "qup-core", "qup-config", "qup-memory";
1312 dmas = <&gpi_ 1312 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1313 <&gpi_ 1313 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1314 dma-names = " 1314 dma-names = "tx", "rx";
1315 status = "dis 1315 status = "disabled";
1316 }; 1316 };
1317 1317
1318 spi4: spi@990000 { 1318 spi4: spi@990000 {
1319 compatible = 1319 compatible = "qcom,geni-spi";
1320 reg = <0x0 0x 1320 reg = <0x0 0x00990000 0x0 0x4000>;
1321 clock-names = 1321 clock-names = "se";
1322 clocks = <&gc 1322 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1323 interrupts = 1323 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1324 pinctrl-names 1324 pinctrl-names = "default";
1325 pinctrl-0 = < 1325 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1326 power-domains 1326 power-domains = <&rpmhpd RPMHPD_CX>;
1327 operating-poi 1327 operating-points-v2 = <&qup_opp_table_100mhz>;
1328 interconnects 1328 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1329 1329 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1330 1330 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1331 interconnect- 1331 interconnect-names = "qup-core", "qup-config", "qup-memory";
1332 dmas = <&gpi_ 1332 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1333 <&gpi_ 1333 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1334 dma-names = " 1334 dma-names = "tx", "rx";
1335 #address-cell 1335 #address-cells = <1>;
1336 #size-cells = 1336 #size-cells = <0>;
1337 status = "dis 1337 status = "disabled";
1338 }; 1338 };
1339 1339
1340 i2c5: i2c@994000 { 1340 i2c5: i2c@994000 {
1341 compatible = 1341 compatible = "qcom,geni-i2c";
1342 reg = <0x0 0x 1342 reg = <0x0 0x00994000 0x0 0x4000>;
1343 clock-names = 1343 clock-names = "se";
1344 clocks = <&gc 1344 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1345 pinctrl-names 1345 pinctrl-names = "default";
1346 pinctrl-0 = < 1346 pinctrl-0 = <&qup_i2c5_data_clk>;
1347 interrupts = 1347 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1348 #address-cell 1348 #address-cells = <1>;
1349 #size-cells = 1349 #size-cells = <0>;
1350 interconnects 1350 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1351 1351 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1352 1352 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1353 interconnect- 1353 interconnect-names = "qup-core", "qup-config", "qup-memory";
1354 dmas = <&gpi_ 1354 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1355 <&gpi_ 1355 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1356 dma-names = " 1356 dma-names = "tx", "rx";
1357 status = "dis 1357 status = "disabled";
1358 }; 1358 };
1359 1359
1360 spi5: spi@994000 { 1360 spi5: spi@994000 {
1361 compatible = 1361 compatible = "qcom,geni-spi";
1362 reg = <0x0 0x 1362 reg = <0x0 0x00994000 0x0 0x4000>;
1363 clock-names = 1363 clock-names = "se";
1364 clocks = <&gc 1364 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1365 interrupts = 1365 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1366 pinctrl-names 1366 pinctrl-names = "default";
1367 pinctrl-0 = < 1367 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1368 interconnects 1368 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1369 1369 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1370 1370 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1371 interconnect- 1371 interconnect-names = "qup-core", "qup-config", "qup-memory";
1372 dmas = <&gpi_ 1372 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1373 <&gpi_ 1373 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1374 dma-names = " 1374 dma-names = "tx", "rx";
1375 #address-cell 1375 #address-cells = <1>;
1376 #size-cells = 1376 #size-cells = <0>;
1377 status = "dis 1377 status = "disabled";
1378 }; 1378 };
1379 1379
1380 1380
1381 i2c6: i2c@998000 { 1381 i2c6: i2c@998000 {
1382 compatible = 1382 compatible = "qcom,geni-i2c";
1383 reg = <0x0 0x 1383 reg = <0x0 0x00998000 0x0 0x4000>;
1384 clock-names = 1384 clock-names = "se";
1385 clocks = <&gc 1385 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1386 pinctrl-names 1386 pinctrl-names = "default";
1387 pinctrl-0 = < 1387 pinctrl-0 = <&qup_i2c6_data_clk>;
1388 interrupts = 1388 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1389 #address-cell 1389 #address-cells = <1>;
1390 #size-cells = 1390 #size-cells = <0>;
1391 interconnects 1391 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1392 1392 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1393 1393 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1394 interconnect- 1394 interconnect-names = "qup-core", "qup-config", "qup-memory";
1395 dmas = <&gpi_ 1395 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1396 <&gpi_ 1396 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1397 dma-names = " 1397 dma-names = "tx", "rx";
1398 status = "dis 1398 status = "disabled";
1399 }; 1399 };
1400 1400
1401 spi6: spi@998000 { 1401 spi6: spi@998000 {
1402 compatible = 1402 compatible = "qcom,geni-spi";
1403 reg = <0x0 0x 1403 reg = <0x0 0x00998000 0x0 0x4000>;
1404 clock-names = 1404 clock-names = "se";
1405 clocks = <&gc 1405 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1406 interrupts = 1406 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1407 pinctrl-names 1407 pinctrl-names = "default";
1408 pinctrl-0 = < 1408 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1409 interconnects 1409 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1410 1410 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1411 1411 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1412 interconnect- 1412 interconnect-names = "qup-core", "qup-config", "qup-memory";
1413 dmas = <&gpi_ 1413 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1414 <&gpi_ 1414 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1415 dma-names = " 1415 dma-names = "tx", "rx";
1416 #address-cell 1416 #address-cells = <1>;
1417 #size-cells = 1417 #size-cells = <0>;
1418 status = "dis 1418 status = "disabled";
1419 }; 1419 };
1420 1420
1421 uart7: serial@99c000 1421 uart7: serial@99c000 {
1422 compatible = 1422 compatible = "qcom,geni-debug-uart";
1423 reg = <0 0x00 1423 reg = <0 0x0099c000 0 0x4000>;
1424 clock-names = 1424 clock-names = "se";
1425 clocks = <&gc 1425 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1426 pinctrl-names 1426 pinctrl-names = "default";
1427 pinctrl-0 = < 1427 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>;
1428 interrupts = 1428 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1429 interconnects 1429 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1430 1430 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1431 1431 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1432 1432 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
1433 interconnect- 1433 interconnect-names = "qup-core",
1434 1434 "qup-config";
1435 status = "dis 1435 status = "disabled";
1436 }; 1436 };
1437 }; 1437 };
1438 1438
1439 gpi_dma1: dma-controller@a000 1439 gpi_dma1: dma-controller@a00000 {
1440 compatible = "qcom,sm 1440 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
1441 #dma-cells = <3>; 1441 #dma-cells = <3>;
1442 reg = <0 0x00a00000 0 1442 reg = <0 0x00a00000 0 0x60000>;
1443 interrupts = <GIC_SPI 1443 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1444 <GIC_SPI 1444 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1445 <GIC_SPI 1445 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1446 <GIC_SPI 1446 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1447 <GIC_SPI 1447 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1448 <GIC_SPI 1448 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1449 <GIC_SPI 1449 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1450 <GIC_SPI 1450 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1451 <GIC_SPI 1451 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1452 <GIC_SPI 1452 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1453 <GIC_SPI 1453 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1454 <GIC_SPI 1454 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
1455 dma-channels = <12>; 1455 dma-channels = <12>;
1456 dma-channel-mask = <0 1456 dma-channel-mask = <0x7e>;
1457 iommus = <&apps_smmu 1457 iommus = <&apps_smmu 0x56 0x0>;
1458 status = "disabled"; 1458 status = "disabled";
1459 }; 1459 };
1460 1460
1461 qupv3_id_1: geniqup@ac0000 { 1461 qupv3_id_1: geniqup@ac0000 {
1462 compatible = "qcom,ge 1462 compatible = "qcom,geni-se-qup";
1463 reg = <0x0 0x00ac0000 1463 reg = <0x0 0x00ac0000 0x0 0x6000>;
1464 clock-names = "m-ahb" 1464 clock-names = "m-ahb", "s-ahb";
1465 clocks = <&gcc GCC_QU 1465 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1466 <&gcc GCC_QU 1466 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1467 iommus = <&apps_smmu 1467 iommus = <&apps_smmu 0x43 0x0>;
1468 interconnects = <&clk 1468 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>;
1469 interconnect-names = 1469 interconnect-names = "qup-core";
1470 #address-cells = <2>; 1470 #address-cells = <2>;
1471 #size-cells = <2>; 1471 #size-cells = <2>;
1472 ranges; 1472 ranges;
1473 status = "disabled"; 1473 status = "disabled";
1474 1474
1475 i2c8: i2c@a80000 { 1475 i2c8: i2c@a80000 {
1476 compatible = 1476 compatible = "qcom,geni-i2c";
1477 reg = <0x0 0x 1477 reg = <0x0 0x00a80000 0x0 0x4000>;
1478 clock-names = 1478 clock-names = "se";
1479 clocks = <&gc 1479 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1480 pinctrl-names 1480 pinctrl-names = "default";
1481 pinctrl-0 = < 1481 pinctrl-0 = <&qup_i2c8_data_clk>;
1482 interrupts = 1482 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1483 #address-cell 1483 #address-cells = <1>;
1484 #size-cells = 1484 #size-cells = <0>;
1485 interconnects 1485 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1486 1486 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1487 1487 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1488 interconnect- 1488 interconnect-names = "qup-core", "qup-config", "qup-memory";
1489 dmas = <&gpi_ 1489 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1490 <&gpi_ 1490 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1491 dma-names = " 1491 dma-names = "tx", "rx";
1492 status = "dis 1492 status = "disabled";
1493 }; 1493 };
1494 1494
1495 spi8: spi@a80000 { 1495 spi8: spi@a80000 {
1496 compatible = 1496 compatible = "qcom,geni-spi";
1497 reg = <0x0 0x 1497 reg = <0x0 0x00a80000 0x0 0x4000>;
1498 clock-names = 1498 clock-names = "se";
1499 clocks = <&gc 1499 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1500 interrupts = 1500 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1501 pinctrl-names 1501 pinctrl-names = "default";
1502 pinctrl-0 = < 1502 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1503 interconnects 1503 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1504 1504 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1505 1505 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1506 interconnect- 1506 interconnect-names = "qup-core", "qup-config", "qup-memory";
1507 dmas = <&gpi_ 1507 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1508 <&gpi_ 1508 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1509 dma-names = " 1509 dma-names = "tx", "rx";
1510 #address-cell 1510 #address-cells = <1>;
1511 #size-cells = 1511 #size-cells = <0>;
1512 status = "dis 1512 status = "disabled";
1513 }; 1513 };
1514 1514
1515 i2c9: i2c@a84000 { 1515 i2c9: i2c@a84000 {
1516 compatible = 1516 compatible = "qcom,geni-i2c";
1517 reg = <0x0 0x 1517 reg = <0x0 0x00a84000 0x0 0x4000>;
1518 clock-names = 1518 clock-names = "se";
1519 clocks = <&gc 1519 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1520 pinctrl-names 1520 pinctrl-names = "default";
1521 pinctrl-0 = < 1521 pinctrl-0 = <&qup_i2c9_data_clk>;
1522 interrupts = 1522 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1523 #address-cell 1523 #address-cells = <1>;
1524 #size-cells = 1524 #size-cells = <0>;
1525 interconnects 1525 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1526 1526 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1527 1527 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1528 interconnect- 1528 interconnect-names = "qup-core", "qup-config", "qup-memory";
1529 dmas = <&gpi_ 1529 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1530 <&gpi_ 1530 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1531 dma-names = " 1531 dma-names = "tx", "rx";
1532 status = "dis 1532 status = "disabled";
1533 }; 1533 };
1534 1534
1535 spi9: spi@a84000 { 1535 spi9: spi@a84000 {
1536 compatible = 1536 compatible = "qcom,geni-spi";
1537 reg = <0x0 0x 1537 reg = <0x0 0x00a84000 0x0 0x4000>;
1538 clock-names = 1538 clock-names = "se";
1539 clocks = <&gc 1539 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1540 interrupts = 1540 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1541 pinctrl-names 1541 pinctrl-names = "default";
1542 pinctrl-0 = < 1542 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1543 interconnects 1543 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1544 1544 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1545 1545 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1546 interconnect- 1546 interconnect-names = "qup-core", "qup-config", "qup-memory";
1547 dmas = <&gpi_ 1547 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1548 <&gpi_ 1548 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1549 dma-names = " 1549 dma-names = "tx", "rx";
1550 #address-cell 1550 #address-cells = <1>;
1551 #size-cells = 1551 #size-cells = <0>;
1552 status = "dis 1552 status = "disabled";
1553 }; 1553 };
1554 1554
1555 i2c10: i2c@a88000 { 1555 i2c10: i2c@a88000 {
1556 compatible = 1556 compatible = "qcom,geni-i2c";
1557 reg = <0x0 0x 1557 reg = <0x0 0x00a88000 0x0 0x4000>;
1558 clock-names = 1558 clock-names = "se";
1559 clocks = <&gc 1559 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1560 pinctrl-names 1560 pinctrl-names = "default";
1561 pinctrl-0 = < 1561 pinctrl-0 = <&qup_i2c10_data_clk>;
1562 interrupts = 1562 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1563 #address-cell 1563 #address-cells = <1>;
1564 #size-cells = 1564 #size-cells = <0>;
1565 interconnects 1565 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1566 1566 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1567 1567 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1568 interconnect- 1568 interconnect-names = "qup-core", "qup-config", "qup-memory";
1569 dmas = <&gpi_ 1569 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1570 <&gpi_ 1570 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1571 dma-names = " 1571 dma-names = "tx", "rx";
1572 status = "dis 1572 status = "disabled";
1573 }; 1573 };
1574 1574
1575 spi10: spi@a88000 { 1575 spi10: spi@a88000 {
1576 compatible = 1576 compatible = "qcom,geni-spi";
1577 reg = <0x0 0x 1577 reg = <0x0 0x00a88000 0x0 0x4000>;
1578 clock-names = 1578 clock-names = "se";
1579 clocks = <&gc 1579 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1580 interrupts = 1580 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1581 pinctrl-names 1581 pinctrl-names = "default";
1582 pinctrl-0 = < 1582 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1583 interconnects 1583 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1584 1584 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1585 1585 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1586 interconnect- 1586 interconnect-names = "qup-core", "qup-config", "qup-memory";
1587 dmas = <&gpi_ 1587 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1588 <&gpi_ 1588 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1589 dma-names = " 1589 dma-names = "tx", "rx";
1590 #address-cell 1590 #address-cells = <1>;
1591 #size-cells = 1591 #size-cells = <0>;
1592 status = "dis 1592 status = "disabled";
1593 }; 1593 };
1594 1594
1595 i2c11: i2c@a8c000 { 1595 i2c11: i2c@a8c000 {
1596 compatible = 1596 compatible = "qcom,geni-i2c";
1597 reg = <0x0 0x 1597 reg = <0x0 0x00a8c000 0x0 0x4000>;
1598 clock-names = 1598 clock-names = "se";
1599 clocks = <&gc 1599 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1600 pinctrl-names 1600 pinctrl-names = "default";
1601 pinctrl-0 = < 1601 pinctrl-0 = <&qup_i2c11_data_clk>;
1602 interrupts = 1602 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1603 #address-cell 1603 #address-cells = <1>;
1604 #size-cells = 1604 #size-cells = <0>;
1605 interconnects 1605 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1606 1606 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1607 1607 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1608 interconnect- 1608 interconnect-names = "qup-core", "qup-config", "qup-memory";
1609 dmas = <&gpi_ 1609 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1610 <&gpi_ 1610 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1611 dma-names = " 1611 dma-names = "tx", "rx";
1612 status = "dis 1612 status = "disabled";
1613 }; 1613 };
1614 1614
1615 spi11: spi@a8c000 { 1615 spi11: spi@a8c000 {
1616 compatible = 1616 compatible = "qcom,geni-spi";
1617 reg = <0x0 0x 1617 reg = <0x0 0x00a8c000 0x0 0x4000>;
1618 clock-names = 1618 clock-names = "se";
1619 clocks = <&gc 1619 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1620 interrupts = 1620 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1621 pinctrl-names 1621 pinctrl-names = "default";
1622 pinctrl-0 = < 1622 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1623 interconnects 1623 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1624 1624 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1625 1625 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1626 interconnect- 1626 interconnect-names = "qup-core", "qup-config", "qup-memory";
1627 dmas = <&gpi_ 1627 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1628 <&gpi_ 1628 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1629 dma-names = " 1629 dma-names = "tx", "rx";
1630 #address-cell 1630 #address-cells = <1>;
1631 #size-cells = 1631 #size-cells = <0>;
1632 status = "dis 1632 status = "disabled";
1633 }; 1633 };
1634 1634
1635 i2c12: i2c@a90000 { 1635 i2c12: i2c@a90000 {
1636 compatible = 1636 compatible = "qcom,geni-i2c";
1637 reg = <0x0 0x 1637 reg = <0x0 0x00a90000 0x0 0x4000>;
1638 clock-names = 1638 clock-names = "se";
1639 clocks = <&gc 1639 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1640 pinctrl-names 1640 pinctrl-names = "default";
1641 pinctrl-0 = < 1641 pinctrl-0 = <&qup_i2c12_data_clk>;
1642 interrupts = 1642 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1643 #address-cell 1643 #address-cells = <1>;
1644 #size-cells = 1644 #size-cells = <0>;
1645 interconnects 1645 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1646 1646 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1647 1647 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1648 interconnect- 1648 interconnect-names = "qup-core", "qup-config", "qup-memory";
1649 dmas = <&gpi_ 1649 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1650 <&gpi_ 1650 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1651 dma-names = " 1651 dma-names = "tx", "rx";
1652 status = "dis 1652 status = "disabled";
1653 }; 1653 };
1654 1654
1655 spi12: spi@a90000 { 1655 spi12: spi@a90000 {
1656 compatible = 1656 compatible = "qcom,geni-spi";
1657 reg = <0x0 0x 1657 reg = <0x0 0x00a90000 0x0 0x4000>;
1658 clock-names = 1658 clock-names = "se";
1659 clocks = <&gc 1659 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1660 interrupts = 1660 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1661 pinctrl-names 1661 pinctrl-names = "default";
1662 pinctrl-0 = < 1662 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1663 interconnects 1663 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1664 1664 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1665 1665 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1666 interconnect- 1666 interconnect-names = "qup-core", "qup-config", "qup-memory";
1667 dmas = <&gpi_ 1667 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1668 <&gpi_ 1668 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1669 dma-names = " 1669 dma-names = "tx", "rx";
1670 #address-cell 1670 #address-cells = <1>;
1671 #size-cells = 1671 #size-cells = <0>;
1672 status = "dis 1672 status = "disabled";
1673 }; 1673 };
1674 1674
1675 i2c13: i2c@a94000 { 1675 i2c13: i2c@a94000 {
1676 compatible = 1676 compatible = "qcom,geni-i2c";
1677 reg = <0 0x00 1677 reg = <0 0x00a94000 0 0x4000>;
1678 clock-names = 1678 clock-names = "se";
1679 clocks = <&gc 1679 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1680 pinctrl-names 1680 pinctrl-names = "default";
1681 pinctrl-0 = < 1681 pinctrl-0 = <&qup_i2c13_data_clk>;
1682 interrupts = 1682 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1683 interconnects 1683 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1684 1684 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1685 1685 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1686 interconnect- 1686 interconnect-names = "qup-core", "qup-config", "qup-memory";
1687 dmas = <&gpi_ 1687 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1688 <&gpi_ 1688 <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1689 dma-names = " 1689 dma-names = "tx", "rx";
1690 #address-cell 1690 #address-cells = <1>;
1691 #size-cells = 1691 #size-cells = <0>;
1692 status = "dis 1692 status = "disabled";
1693 }; 1693 };
1694 1694
1695 spi13: spi@a94000 { 1695 spi13: spi@a94000 {
1696 compatible = 1696 compatible = "qcom,geni-spi";
1697 reg = <0x0 0x 1697 reg = <0x0 0x00a94000 0x0 0x4000>;
1698 clock-names = 1698 clock-names = "se";
1699 clocks = <&gc 1699 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1700 interrupts = 1700 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1701 pinctrl-names 1701 pinctrl-names = "default";
1702 pinctrl-0 = < 1702 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1703 interconnects 1703 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1704 1704 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1705 1705 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1706 interconnect- 1706 interconnect-names = "qup-core", "qup-config", "qup-memory";
1707 dmas = <&gpi_ 1707 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1708 <&gpi_ 1708 <&gpi_dma1 1 5 QCOM_GPI_SPI>;
1709 dma-names = " 1709 dma-names = "tx", "rx";
1710 #address-cell 1710 #address-cells = <1>;
1711 #size-cells = 1711 #size-cells = <0>;
1712 status = "dis 1712 status = "disabled";
1713 }; 1713 };
1714 1714
1715 i2c14: i2c@a98000 { 1715 i2c14: i2c@a98000 {
1716 compatible = 1716 compatible = "qcom,geni-i2c";
1717 reg = <0 0x00 1717 reg = <0 0x00a98000 0 0x4000>;
1718 clock-names = 1718 clock-names = "se";
1719 clocks = <&gc 1719 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1720 pinctrl-names 1720 pinctrl-names = "default";
1721 pinctrl-0 = < 1721 pinctrl-0 = <&qup_i2c14_data_clk>;
1722 interrupts = 1722 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
1723 interconnects 1723 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1724 1724 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1725 1725 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1726 interconnect- 1726 interconnect-names = "qup-core", "qup-config", "qup-memory";
1727 dmas = <&gpi_ 1727 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
1728 <&gpi_ 1728 <&gpi_dma1 1 6 QCOM_GPI_I2C>;
1729 dma-names = " 1729 dma-names = "tx", "rx";
1730 #address-cell 1730 #address-cells = <1>;
1731 #size-cells = 1731 #size-cells = <0>;
1732 status = "dis 1732 status = "disabled";
1733 }; 1733 };
1734 1734
1735 spi14: spi@a98000 { 1735 spi14: spi@a98000 {
1736 compatible = 1736 compatible = "qcom,geni-spi";
1737 reg = <0x0 0x 1737 reg = <0x0 0x00a98000 0x0 0x4000>;
1738 clock-names = 1738 clock-names = "se";
1739 clocks = <&gc 1739 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1740 interrupts = 1740 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
1741 pinctrl-names 1741 pinctrl-names = "default";
1742 pinctrl-0 = < 1742 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
1743 interconnects 1743 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1744 1744 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1745 1745 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1746 interconnect- 1746 interconnect-names = "qup-core", "qup-config", "qup-memory";
1747 dmas = <&gpi_ 1747 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
1748 <&gpi_ 1748 <&gpi_dma1 1 6 QCOM_GPI_SPI>;
1749 dma-names = " 1749 dma-names = "tx", "rx";
1750 #address-cell 1750 #address-cells = <1>;
1751 #size-cells = 1751 #size-cells = <0>;
1752 status = "dis 1752 status = "disabled";
1753 }; 1753 };
1754 }; 1754 };
1755 1755
1756 rng: rng@10c3000 { 1756 rng: rng@10c3000 {
1757 compatible = "qcom,sm 1757 compatible = "qcom,sm8450-trng", "qcom,trng";
1758 reg = <0 0x010c3000 0 1758 reg = <0 0x010c3000 0 0x1000>;
1759 }; 1759 };
1760 1760
1761 pcie0: pcie@1c00000 { 1761 pcie0: pcie@1c00000 {
1762 compatible = "qcom,pc 1762 compatible = "qcom,pcie-sm8450-pcie0";
1763 reg = <0 0x01c00000 0 1763 reg = <0 0x01c00000 0 0x3000>,
1764 <0 0x60000000 0 1764 <0 0x60000000 0 0xf1d>,
1765 <0 0x60000f20 0 1765 <0 0x60000f20 0 0xa8>,
1766 <0 0x60001000 0 1766 <0 0x60001000 0 0x1000>,
1767 <0 0x60100000 0 1767 <0 0x60100000 0 0x100000>;
1768 reg-names = "parf", " 1768 reg-names = "parf", "dbi", "elbi", "atu", "config";
1769 device_type = "pci"; 1769 device_type = "pci";
1770 linux,pci-domain = <0 1770 linux,pci-domain = <0>;
1771 bus-range = <0x00 0xf 1771 bus-range = <0x00 0xff>;
1772 num-lanes = <1>; 1772 num-lanes = <1>;
1773 1773
1774 #address-cells = <3>; 1774 #address-cells = <3>;
1775 #size-cells = <2>; 1775 #size-cells = <2>;
1776 1776
1777 ranges = <0x01000000 1777 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
1778 <0x02000000 1778 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1779 1779
1780 msi-map = <0x0 &gic_i 1780 msi-map = <0x0 &gic_its 0x5980 0x1>,
1781 <0x100 &gic 1781 <0x100 &gic_its 0x5981 0x1>;
1782 msi-map-mask = <0xff0 1782 msi-map-mask = <0xff00>;
1783 interrupts = <GIC_SPI 1783 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
1784 <GIC_SPI 1784 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
1785 <GIC_SPI 1785 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
1786 <GIC_SPI 1786 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
1787 <GIC_SPI 1787 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1788 <GIC_SPI 1788 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1789 <GIC_SPI 1789 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
1790 <GIC_SPI 1790 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1791 interrupt-names = "ms 1791 interrupt-names = "msi0",
1792 "ms 1792 "msi1",
1793 "ms 1793 "msi2",
1794 "ms 1794 "msi3",
1795 "ms 1795 "msi4",
1796 "ms 1796 "msi5",
1797 "ms 1797 "msi6",
1798 "ms 1798 "msi7";
1799 #interrupt-cells = <1 1799 #interrupt-cells = <1>;
1800 interrupt-map-mask = 1800 interrupt-map-mask = <0 0 0 0x7>;
1801 interrupt-map = <0 0 1801 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1802 <0 0 1802 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1803 <0 0 1803 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1804 <0 0 1804 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1805 1805
1806 interconnects = <&pci 1806 interconnects = <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS
1807 &mc_ 1807 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
1808 <&gem 1808 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1809 &con 1809 &config_noc SLAVE_PCIE_0 QCOM_ICC_TAG_ALWAYS>;
1810 interconnect-names = 1810 interconnect-names = "pcie-mem", "cpu-pcie";
1811 1811
1812 clocks = <&gcc GCC_PC 1812 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1813 <&gcc GCC_PC 1813 <&gcc GCC_PCIE_0_PIPE_CLK_SRC>,
1814 <&pcie0_phy> 1814 <&pcie0_phy>,
1815 <&rpmhcc RPM 1815 <&rpmhcc RPMH_CXO_CLK>,
1816 <&gcc GCC_PC 1816 <&gcc GCC_PCIE_0_AUX_CLK>,
1817 <&gcc GCC_PC 1817 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1818 <&gcc GCC_PC 1818 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1819 <&gcc GCC_PC 1819 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1820 <&gcc GCC_PC 1820 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
1821 <&gcc GCC_DD 1821 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1822 <&gcc GCC_AG 1822 <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
1823 <&gcc GCC_AG 1823 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
1824 clock-names = "pipe", 1824 clock-names = "pipe",
1825 "pipe_m 1825 "pipe_mux",
1826 "phy_pi 1826 "phy_pipe",
1827 "ref", 1827 "ref",
1828 "aux", 1828 "aux",
1829 "cfg", 1829 "cfg",
1830 "bus_ma 1830 "bus_master",
1831 "bus_sl 1831 "bus_slave",
1832 "slave_ 1832 "slave_q2a",
1833 "ddrss_ 1833 "ddrss_sf_tbu",
1834 "aggre0 1834 "aggre0",
1835 "aggre1 1835 "aggre1";
1836 1836
1837 iommu-map = <0x0 &a 1837 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
1838 <0x100 &a 1838 <0x100 &apps_smmu 0x1c01 0x1>;
1839 1839
1840 resets = <&gcc GCC_PC 1840 resets = <&gcc GCC_PCIE_0_BCR>;
1841 reset-names = "pci"; 1841 reset-names = "pci";
1842 1842
1843 power-domains = <&gcc 1843 power-domains = <&gcc PCIE_0_GDSC>;
1844 1844
1845 phys = <&pcie0_phy>; 1845 phys = <&pcie0_phy>;
1846 phy-names = "pciephy" 1846 phy-names = "pciephy";
1847 1847
1848 perst-gpios = <&tlmm 1848 perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
1849 wake-gpios = <&tlmm 9 1849 wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
1850 1850
1851 pinctrl-names = "defa 1851 pinctrl-names = "default";
1852 pinctrl-0 = <&pcie0_d 1852 pinctrl-0 = <&pcie0_default_state>;
1853 1853
1854 operating-points-v2 = 1854 operating-points-v2 = <&pcie0_opp_table>;
1855 1855
1856 status = "disabled"; 1856 status = "disabled";
1857 1857
1858 pcie0_opp_table: opp- 1858 pcie0_opp_table: opp-table {
1859 compatible = 1859 compatible = "operating-points-v2";
1860 1860
1861 /* GEN 1 x1 * 1861 /* GEN 1 x1 */
1862 opp-2500000 { 1862 opp-2500000 {
1863 opp-h 1863 opp-hz = /bits/ 64 <2500000>;
1864 requi 1864 required-opps = <&rpmhpd_opp_low_svs>;
1865 opp-p 1865 opp-peak-kBps = <250000 1>;
1866 }; 1866 };
1867 1867
1868 /* GEN 2 x1 * 1868 /* GEN 2 x1 */
1869 opp-5000000 { 1869 opp-5000000 {
1870 opp-h 1870 opp-hz = /bits/ 64 <5000000>;
1871 requi 1871 required-opps = <&rpmhpd_opp_low_svs>;
1872 opp-p 1872 opp-peak-kBps = <500000 1>;
1873 }; 1873 };
1874 1874
1875 /* GEN 3 x1 * 1875 /* GEN 3 x1 */
1876 opp-8000000 { 1876 opp-8000000 {
1877 opp-h 1877 opp-hz = /bits/ 64 <8000000>;
1878 requi 1878 required-opps = <&rpmhpd_opp_nom>;
1879 opp-p 1879 opp-peak-kBps = <984500 1>;
1880 }; 1880 };
1881 }; 1881 };
1882 1882
1883 pcie@0 { 1883 pcie@0 {
1884 device_type = 1884 device_type = "pci";
1885 reg = <0x0 0x 1885 reg = <0x0 0x0 0x0 0x0 0x0>;
1886 bus-range = < 1886 bus-range = <0x01 0xff>;
1887 1887
1888 #address-cell 1888 #address-cells = <3>;
1889 #size-cells = 1889 #size-cells = <2>;
1890 ranges; 1890 ranges;
1891 }; 1891 };
1892 }; 1892 };
1893 1893
1894 pcie0_phy: phy@1c06000 { 1894 pcie0_phy: phy@1c06000 {
1895 compatible = "qcom,sm 1895 compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy";
1896 reg = <0 0x01c06000 0 1896 reg = <0 0x01c06000 0 0x2000>;
1897 1897
1898 clocks = <&gcc GCC_PC 1898 clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
1899 <&gcc GCC_PC 1899 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1900 <&gcc GCC_PC 1900 <&gcc GCC_PCIE_0_CLKREF_EN>,
1901 <&gcc GCC_PC 1901 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
1902 <&gcc GCC_PC 1902 <&gcc GCC_PCIE_0_PIPE_CLK>;
1903 clock-names = "aux", 1903 clock-names = "aux",
1904 "cfg_ah 1904 "cfg_ahb",
1905 "ref", 1905 "ref",
1906 "rchng" 1906 "rchng",
1907 "pipe"; 1907 "pipe";
1908 1908
1909 clock-output-names = 1909 clock-output-names = "pcie_0_pipe_clk";
1910 #clock-cells = <0>; 1910 #clock-cells = <0>;
1911 1911
1912 #phy-cells = <0>; 1912 #phy-cells = <0>;
1913 1913
1914 resets = <&gcc GCC_PC 1914 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1915 reset-names = "phy"; 1915 reset-names = "phy";
1916 1916
1917 assigned-clocks = <&g 1917 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
1918 assigned-clock-rates 1918 assigned-clock-rates = <100000000>;
1919 1919
1920 status = "disabled"; 1920 status = "disabled";
1921 }; 1921 };
1922 1922
1923 pcie1: pcie@1c08000 { 1923 pcie1: pcie@1c08000 {
1924 compatible = "qcom,pc 1924 compatible = "qcom,pcie-sm8450-pcie1";
1925 reg = <0 0x01c08000 0 1925 reg = <0 0x01c08000 0 0x3000>,
1926 <0 0x40000000 0 1926 <0 0x40000000 0 0xf1d>,
1927 <0 0x40000f20 0 1927 <0 0x40000f20 0 0xa8>,
1928 <0 0x40001000 0 1928 <0 0x40001000 0 0x1000>,
1929 <0 0x40100000 0 1929 <0 0x40100000 0 0x100000>;
1930 reg-names = "parf", " 1930 reg-names = "parf", "dbi", "elbi", "atu", "config";
1931 device_type = "pci"; 1931 device_type = "pci";
1932 linux,pci-domain = <1 1932 linux,pci-domain = <1>;
1933 bus-range = <0x00 0xf 1933 bus-range = <0x00 0xff>;
1934 num-lanes = <2>; 1934 num-lanes = <2>;
1935 1935
1936 #address-cells = <3>; 1936 #address-cells = <3>;
1937 #size-cells = <2>; 1937 #size-cells = <2>;
1938 1938
1939 ranges = <0x01000000 1939 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
1940 <0x02000000 1940 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1941 1941
1942 msi-map = <0x0 &gic_i 1942 msi-map = <0x0 &gic_its 0x5a00 0x1>,
1943 <0x100 &gic 1943 <0x100 &gic_its 0x5a01 0x1>;
1944 msi-map-mask = <0xff0 1944 msi-map-mask = <0xff00>;
1945 interrupts = <GIC_SPI 1945 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
1946 <GIC_SPI 1946 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
1947 <GIC_SPI 1947 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
1948 <GIC_SPI 1948 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
1949 <GIC_SPI 1949 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
1950 <GIC_SPI 1950 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
1951 <GIC_SPI 1951 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
1952 <GIC_SPI 1952 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1953 interrupt-names = "ms 1953 interrupt-names = "msi0",
1954 "ms 1954 "msi1",
1955 "ms 1955 "msi2",
1956 "ms 1956 "msi3",
1957 "ms 1957 "msi4",
1958 "ms 1958 "msi5",
1959 "ms 1959 "msi6",
1960 "ms 1960 "msi7";
1961 #interrupt-cells = <1 1961 #interrupt-cells = <1>;
1962 interrupt-map-mask = 1962 interrupt-map-mask = <0 0 0 0x7>;
1963 interrupt-map = <0 0 1963 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1964 <0 0 1964 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1965 <0 0 1965 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1966 <0 0 1966 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1967 1967
1968 interconnects = <&pci 1968 interconnects = <&pcie_noc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS
1969 &mc_ 1969 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
1970 <&gem 1970 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1971 &con 1971 &config_noc SLAVE_PCIE_1 QCOM_ICC_TAG_ALWAYS>;
1972 interconnect-names = 1972 interconnect-names = "pcie-mem", "cpu-pcie";
1973 1973
1974 clocks = <&gcc GCC_PC 1974 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1975 <&gcc GCC_PC 1975 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>,
1976 <&pcie1_phy !! 1976 <&pcie1_phy>,
1977 <&rpmhcc RPM 1977 <&rpmhcc RPMH_CXO_CLK>,
1978 <&gcc GCC_PC 1978 <&gcc GCC_PCIE_1_AUX_CLK>,
1979 <&gcc GCC_PC 1979 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1980 <&gcc GCC_PC 1980 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1981 <&gcc GCC_PC 1981 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
1982 <&gcc GCC_PC 1982 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
1983 <&gcc GCC_DD 1983 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1984 <&gcc GCC_AG 1984 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
1985 clock-names = "pipe", 1985 clock-names = "pipe",
1986 "pipe_m 1986 "pipe_mux",
1987 "phy_pi 1987 "phy_pipe",
1988 "ref", 1988 "ref",
1989 "aux", 1989 "aux",
1990 "cfg", 1990 "cfg",
1991 "bus_ma 1991 "bus_master",
1992 "bus_sl 1992 "bus_slave",
1993 "slave_ 1993 "slave_q2a",
1994 "ddrss_ 1994 "ddrss_sf_tbu",
1995 "aggre1 1995 "aggre1";
1996 1996
1997 iommu-map = <0x0 &a 1997 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
1998 <0x100 &a 1998 <0x100 &apps_smmu 0x1c81 0x1>;
1999 1999
2000 resets = <&gcc GCC_PC 2000 resets = <&gcc GCC_PCIE_1_BCR>;
2001 reset-names = "pci"; 2001 reset-names = "pci";
2002 2002
2003 power-domains = <&gcc 2003 power-domains = <&gcc PCIE_1_GDSC>;
2004 2004
2005 phys = <&pcie1_phy>; 2005 phys = <&pcie1_phy>;
2006 phy-names = "pciephy" 2006 phy-names = "pciephy";
2007 2007
2008 perst-gpios = <&tlmm 2008 perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
2009 wake-gpios = <&tlmm 9 2009 wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
2010 2010
2011 pinctrl-names = "defa 2011 pinctrl-names = "default";
2012 pinctrl-0 = <&pcie1_d 2012 pinctrl-0 = <&pcie1_default_state>;
2013 2013
2014 operating-points-v2 = 2014 operating-points-v2 = <&pcie1_opp_table>;
2015 2015
2016 status = "disabled"; 2016 status = "disabled";
2017 2017
2018 pcie1_opp_table: opp- 2018 pcie1_opp_table: opp-table {
2019 compatible = 2019 compatible = "operating-points-v2";
2020 2020
2021 /* GEN 1 x1 * 2021 /* GEN 1 x1 */
2022 opp-2500000 { 2022 opp-2500000 {
2023 opp-h 2023 opp-hz = /bits/ 64 <2500000>;
2024 requi 2024 required-opps = <&rpmhpd_opp_low_svs>;
2025 opp-p 2025 opp-peak-kBps = <250000 1>;
2026 }; 2026 };
2027 2027
2028 /* GEN 1 x2 a 2028 /* GEN 1 x2 and GEN 2 x1 */
2029 opp-5000000 { 2029 opp-5000000 {
2030 opp-h 2030 opp-hz = /bits/ 64 <5000000>;
2031 requi 2031 required-opps = <&rpmhpd_opp_low_svs>;
2032 opp-p 2032 opp-peak-kBps = <500000 1>;
2033 }; 2033 };
2034 2034
2035 /* GEN 2 x2 * 2035 /* GEN 2 x2 */
2036 opp-10000000 2036 opp-10000000 {
2037 opp-h 2037 opp-hz = /bits/ 64 <10000000>;
2038 requi 2038 required-opps = <&rpmhpd_opp_low_svs>;
2039 opp-p 2039 opp-peak-kBps = <1000000 1>;
2040 }; 2040 };
2041 2041
2042 /* GEN 3 x1 * 2042 /* GEN 3 x1 */
2043 opp-8000000 { 2043 opp-8000000 {
2044 opp-h 2044 opp-hz = /bits/ 64 <8000000>;
2045 requi 2045 required-opps = <&rpmhpd_opp_nom>;
2046 opp-p 2046 opp-peak-kBps = <984500 1>;
2047 }; 2047 };
2048 2048
2049 /* GEN 3 x2 a 2049 /* GEN 3 x2 and GEN 4 x1 */
2050 opp-16000000 2050 opp-16000000 {
2051 opp-h 2051 opp-hz = /bits/ 64 <16000000>;
2052 requi 2052 required-opps = <&rpmhpd_opp_nom>;
2053 opp-p 2053 opp-peak-kBps = <1969000 1>;
2054 }; 2054 };
2055 2055
2056 /* GEN 4 x2 * 2056 /* GEN 4 x2 */
2057 opp-32000000 2057 opp-32000000 {
2058 opp-h 2058 opp-hz = /bits/ 64 <32000000>;
2059 requi 2059 required-opps = <&rpmhpd_opp_nom>;
2060 opp-p 2060 opp-peak-kBps = <3938000 1>;
2061 }; 2061 };
2062 }; 2062 };
2063 2063
2064 pcie@0 { 2064 pcie@0 {
2065 device_type = 2065 device_type = "pci";
2066 reg = <0x0 0x 2066 reg = <0x0 0x0 0x0 0x0 0x0>;
2067 bus-range = < 2067 bus-range = <0x01 0xff>;
2068 2068
2069 #address-cell 2069 #address-cells = <3>;
2070 #size-cells = 2070 #size-cells = <2>;
2071 ranges; 2071 ranges;
2072 }; 2072 };
2073 }; 2073 };
2074 2074
2075 pcie1_phy: phy@1c0e000 { 2075 pcie1_phy: phy@1c0e000 {
2076 compatible = "qcom,sm 2076 compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy";
2077 reg = <0 0x01c0e000 0 2077 reg = <0 0x01c0e000 0 0x2000>;
2078 2078
2079 clocks = <&gcc GCC_PC 2079 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>,
2080 <&gcc GCC_PC 2080 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2081 <&gcc GCC_PC 2081 <&gcc GCC_PCIE_1_CLKREF_EN>,
2082 <&gcc GCC_PC 2082 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
2083 <&gcc GCC_PC 2083 <&gcc GCC_PCIE_1_PIPE_CLK>;
2084 clock-names = "aux", 2084 clock-names = "aux",
2085 "cfg_ah 2085 "cfg_ahb",
2086 "ref", 2086 "ref",
2087 "rchng" 2087 "rchng",
2088 "pipe"; 2088 "pipe";
2089 2089
2090 clock-output-names = 2090 clock-output-names = "pcie_1_pipe_clk";
2091 #clock-cells = <1>; 2091 #clock-cells = <1>;
2092 2092
2093 #phy-cells = <0>; 2093 #phy-cells = <0>;
2094 2094
2095 resets = <&gcc GCC_PC 2095 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2096 reset-names = "phy"; 2096 reset-names = "phy";
2097 2097
2098 assigned-clocks = <&g 2098 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
2099 assigned-clock-rates 2099 assigned-clock-rates = <100000000>;
2100 2100
2101 status = "disabled"; 2101 status = "disabled";
2102 }; 2102 };
2103 2103
2104 config_noc: interconnect@1500 2104 config_noc: interconnect@1500000 {
2105 compatible = "qcom,sm 2105 compatible = "qcom,sm8450-config-noc";
2106 reg = <0 0x01500000 0 2106 reg = <0 0x01500000 0 0x1c000>;
2107 #interconnect-cells = 2107 #interconnect-cells = <2>;
2108 qcom,bcm-voters = <&a 2108 qcom,bcm-voters = <&apps_bcm_voter>;
2109 }; 2109 };
2110 2110
2111 system_noc: interconnect@1680 2111 system_noc: interconnect@1680000 {
2112 compatible = "qcom,sm 2112 compatible = "qcom,sm8450-system-noc";
2113 reg = <0 0x01680000 0 2113 reg = <0 0x01680000 0 0x1e200>;
2114 #interconnect-cells = 2114 #interconnect-cells = <2>;
2115 qcom,bcm-voters = <&a 2115 qcom,bcm-voters = <&apps_bcm_voter>;
2116 }; 2116 };
2117 2117
2118 pcie_noc: interconnect@16c000 2118 pcie_noc: interconnect@16c0000 {
2119 compatible = "qcom,sm 2119 compatible = "qcom,sm8450-pcie-anoc";
2120 reg = <0 0x016c0000 0 2120 reg = <0 0x016c0000 0 0xe280>;
2121 #interconnect-cells = 2121 #interconnect-cells = <2>;
2122 qcom,bcm-voters = <&a 2122 qcom,bcm-voters = <&apps_bcm_voter>;
2123 }; 2123 };
2124 2124
2125 aggre1_noc: interconnect@16e0 2125 aggre1_noc: interconnect@16e0000 {
2126 compatible = "qcom,sm 2126 compatible = "qcom,sm8450-aggre1-noc";
2127 reg = <0 0x016e0000 0 2127 reg = <0 0x016e0000 0 0x1c080>;
2128 #interconnect-cells = 2128 #interconnect-cells = <2>;
2129 clocks = <&gcc GCC_AG 2129 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2130 <&gcc GCC_AG 2130 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
2131 qcom,bcm-voters = <&a 2131 qcom,bcm-voters = <&apps_bcm_voter>;
2132 }; 2132 };
2133 2133
2134 aggre2_noc: interconnect@1700 2134 aggre2_noc: interconnect@1700000 {
2135 compatible = "qcom,sm 2135 compatible = "qcom,sm8450-aggre2-noc";
2136 reg = <0 0x01700000 0 2136 reg = <0 0x01700000 0 0x31080>;
2137 #interconnect-cells = 2137 #interconnect-cells = <2>;
2138 qcom,bcm-voters = <&a 2138 qcom,bcm-voters = <&apps_bcm_voter>;
2139 clocks = <&gcc GCC_AG 2139 clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
2140 <&gcc GCC_AG 2140 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
2141 <&gcc GCC_AG 2141 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2142 <&rpmhcc RPM 2142 <&rpmhcc RPMH_IPA_CLK>;
2143 }; 2143 };
2144 2144
2145 mmss_noc: interconnect@174000 2145 mmss_noc: interconnect@1740000 {
2146 compatible = "qcom,sm 2146 compatible = "qcom,sm8450-mmss-noc";
2147 reg = <0 0x01740000 0 2147 reg = <0 0x01740000 0 0x1f080>;
2148 #interconnect-cells = 2148 #interconnect-cells = <2>;
2149 qcom,bcm-voters = <&a 2149 qcom,bcm-voters = <&apps_bcm_voter>;
2150 }; 2150 };
2151 2151
2152 tcsr_mutex: hwlock@1f40000 { 2152 tcsr_mutex: hwlock@1f40000 {
2153 compatible = "qcom,tc 2153 compatible = "qcom,tcsr-mutex";
2154 reg = <0x0 0x01f40000 2154 reg = <0x0 0x01f40000 0x0 0x40000>;
2155 #hwlock-cells = <1>; 2155 #hwlock-cells = <1>;
2156 }; 2156 };
2157 2157
2158 tcsr: syscon@1fc0000 { 2158 tcsr: syscon@1fc0000 {
2159 compatible = "qcom,sm 2159 compatible = "qcom,sm8450-tcsr", "syscon";
2160 reg = <0x0 0x1fc0000 2160 reg = <0x0 0x1fc0000 0x0 0x30000>;
2161 }; 2161 };
2162 2162
2163 gpu: gpu@3d00000 { 2163 gpu: gpu@3d00000 {
2164 compatible = "qcom,ad 2164 compatible = "qcom,adreno-730.1", "qcom,adreno";
2165 reg = <0x0 0x03d00000 2165 reg = <0x0 0x03d00000 0x0 0x40000>,
2166 <0x0 0x03d9e000 2166 <0x0 0x03d9e000 0x0 0x1000>,
2167 <0x0 0x03d61000 2167 <0x0 0x03d61000 0x0 0x800>;
2168 reg-names = "kgsl_3d0 2168 reg-names = "kgsl_3d0_reg_memory",
2169 "cx_mem", 2169 "cx_mem",
2170 "cx_dbgc" 2170 "cx_dbgc";
2171 2171
2172 interrupts = <GIC_SPI 2172 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2173 2173
2174 iommus = <&adreno_smm 2174 iommus = <&adreno_smmu 0 0x400>,
2175 <&adreno_smm 2175 <&adreno_smmu 1 0x400>;
2176 2176
2177 operating-points-v2 = 2177 operating-points-v2 = <&gpu_opp_table>;
2178 2178
2179 qcom,gmu = <&gmu>; 2179 qcom,gmu = <&gmu>;
2180 #cooling-cells = <2>; 2180 #cooling-cells = <2>;
2181 2181
2182 status = "disabled"; 2182 status = "disabled";
2183 2183
2184 zap-shader { 2184 zap-shader {
2185 memory-region 2185 memory-region = <&gpu_micro_code_mem>;
2186 }; 2186 };
2187 2187
2188 gpu_opp_table: opp-ta 2188 gpu_opp_table: opp-table {
2189 compatible = 2189 compatible = "operating-points-v2";
2190 2190
2191 opp-818000000 2191 opp-818000000 {
2192 opp-h 2192 opp-hz = /bits/ 64 <818000000>;
2193 opp-l 2193 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2194 }; 2194 };
2195 2195
2196 opp-791000000 2196 opp-791000000 {
2197 opp-h 2197 opp-hz = /bits/ 64 <791000000>;
2198 opp-l 2198 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2199 }; 2199 };
2200 2200
2201 opp-734000000 2201 opp-734000000 {
2202 opp-h 2202 opp-hz = /bits/ 64 <734000000>;
2203 opp-l 2203 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2204 }; 2204 };
2205 2205
2206 opp-640000000 2206 opp-640000000 {
2207 opp-h 2207 opp-hz = /bits/ 64 <640000000>;
2208 opp-l 2208 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2209 }; 2209 };
2210 2210
2211 opp-599000000 2211 opp-599000000 {
2212 opp-h 2212 opp-hz = /bits/ 64 <599000000>;
2213 opp-l 2213 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2214 }; 2214 };
2215 2215
2216 opp-545000000 2216 opp-545000000 {
2217 opp-h 2217 opp-hz = /bits/ 64 <545000000>;
2218 opp-l 2218 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
2219 }; 2219 };
2220 2220
2221 opp-492000000 2221 opp-492000000 {
2222 opp-h 2222 opp-hz = /bits/ 64 <492000000>;
2223 opp-l 2223 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2224 }; 2224 };
2225 2225
2226 opp-421000000 2226 opp-421000000 {
2227 opp-h 2227 opp-hz = /bits/ 64 <421000000>;
2228 opp-l 2228 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
2229 }; 2229 };
2230 2230
2231 opp-350000000 2231 opp-350000000 {
2232 opp-h 2232 opp-hz = /bits/ 64 <350000000>;
2233 opp-l 2233 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2234 }; 2234 };
2235 2235
2236 opp-317000000 2236 opp-317000000 {
2237 opp-h 2237 opp-hz = /bits/ 64 <317000000>;
2238 opp-l 2238 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2239 }; 2239 };
2240 2240
2241 opp-285000000 2241 opp-285000000 {
2242 opp-h 2242 opp-hz = /bits/ 64 <285000000>;
2243 opp-l 2243 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
2244 }; 2244 };
2245 2245
2246 opp-220000000 2246 opp-220000000 {
2247 opp-h 2247 opp-hz = /bits/ 64 <220000000>;
2248 opp-l 2248 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
2249 }; 2249 };
2250 }; 2250 };
2251 }; 2251 };
2252 2252
2253 gmu: gmu@3d6a000 { 2253 gmu: gmu@3d6a000 {
2254 compatible = "qcom,ad 2254 compatible = "qcom,adreno-gmu-730.1", "qcom,adreno-gmu";
2255 reg = <0x0 0x03d6a000 2255 reg = <0x0 0x03d6a000 0x0 0x35000>,
2256 <0x0 0x03d50000 2256 <0x0 0x03d50000 0x0 0x10000>,
2257 <0x0 0x0b290000 2257 <0x0 0x0b290000 0x0 0x10000>;
2258 reg-names = "gmu", "r 2258 reg-names = "gmu", "rscc", "gmu_pdc";
2259 2259
2260 interrupts = <GIC_SPI 2260 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2261 <GIC_SPI 2261 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2262 interrupt-names = "hf 2262 interrupt-names = "hfi", "gmu";
2263 2263
2264 clocks = <&gpucc GPU_ 2264 clocks = <&gpucc GPU_CC_AHB_CLK>,
2265 <&gpucc GPU_ 2265 <&gpucc GPU_CC_CX_GMU_CLK>,
2266 <&gpucc GPU_ 2266 <&gpucc GPU_CC_CXO_CLK>,
2267 <&gcc GCC_DD 2267 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2268 <&gcc GCC_GP 2268 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2269 <&gpucc GPU_ 2269 <&gpucc GPU_CC_HUB_CX_INT_CLK>,
2270 <&gpucc GPU_ 2270 <&gpucc GPU_CC_DEMET_CLK>;
2271 clock-names = "ahb", 2271 clock-names = "ahb",
2272 "gmu", 2272 "gmu",
2273 "cxo", 2273 "cxo",
2274 "axi", 2274 "axi",
2275 "memnoc 2275 "memnoc",
2276 "hub", 2276 "hub",
2277 "demet" 2277 "demet";
2278 2278
2279 power-domains = <&gpu 2279 power-domains = <&gpucc GPU_CX_GDSC>,
2280 <&gpu 2280 <&gpucc GPU_GX_GDSC>;
2281 power-domain-names = 2281 power-domain-names = "cx",
2282 2282 "gx";
2283 2283
2284 iommus = <&adreno_smm 2284 iommus = <&adreno_smmu 5 0x400>;
2285 2285
2286 qcom,qmp = <&aoss_qmp 2286 qcom,qmp = <&aoss_qmp>;
2287 2287
2288 operating-points-v2 = 2288 operating-points-v2 = <&gmu_opp_table>;
2289 2289
2290 gmu_opp_table: opp-ta 2290 gmu_opp_table: opp-table {
2291 compatible = 2291 compatible = "operating-points-v2";
2292 2292
2293 opp-500000000 2293 opp-500000000 {
2294 opp-h 2294 opp-hz = /bits/ 64 <500000000>;
2295 opp-l 2295 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2296 }; 2296 };
2297 2297
2298 opp-200000000 2298 opp-200000000 {
2299 opp-h 2299 opp-hz = /bits/ 64 <200000000>;
2300 opp-l 2300 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2301 }; 2301 };
2302 }; 2302 };
2303 }; 2303 };
2304 2304
2305 gpucc: clock-controller@3d900 2305 gpucc: clock-controller@3d90000 {
2306 compatible = "qcom,sm 2306 compatible = "qcom,sm8450-gpucc";
2307 reg = <0x0 0x03d90000 2307 reg = <0x0 0x03d90000 0x0 0xa000>;
2308 clocks = <&rpmhcc RPM 2308 clocks = <&rpmhcc RPMH_CXO_CLK>,
2309 <&gcc GCC_GP 2309 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2310 <&gcc GCC_GP 2310 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2311 #clock-cells = <1>; 2311 #clock-cells = <1>;
2312 #reset-cells = <1>; 2312 #reset-cells = <1>;
2313 #power-domain-cells = 2313 #power-domain-cells = <1>;
2314 }; 2314 };
2315 2315
2316 adreno_smmu: iommu@3da0000 { 2316 adreno_smmu: iommu@3da0000 {
2317 compatible = "qcom,sm 2317 compatible = "qcom,sm8450-smmu-500", "qcom,adreno-smmu",
2318 "qcom,sm 2318 "qcom,smmu-500", "arm,mmu-500";
2319 reg = <0x0 0x03da0000 2319 reg = <0x0 0x03da0000 0x0 0x40000>;
2320 #iommu-cells = <2>; 2320 #iommu-cells = <2>;
2321 #global-interrupts = 2321 #global-interrupts = <1>;
2322 interrupts = <GIC_SPI 2322 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
2323 <GIC_SPI 2323 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
2324 <GIC_SPI 2324 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
2325 <GIC_SPI 2325 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
2326 <GIC_SPI 2326 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
2327 <GIC_SPI 2327 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
2328 <GIC_SPI 2328 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
2329 <GIC_SPI 2329 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
2330 <GIC_SPI 2330 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
2331 <GIC_SPI 2331 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
2332 <GIC_SPI 2332 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
2333 <GIC_SPI 2333 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
2334 <GIC_SPI 2334 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
2335 <GIC_SPI 2335 <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>,
2336 <GIC_SPI 2336 <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>,
2337 <GIC_SPI 2337 <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
2338 <GIC_SPI 2338 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>,
2339 <GIC_SPI 2339 <GIC_SPI 659 IRQ_TYPE_LEVEL_HIGH>,
2340 <GIC_SPI 2340 <GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH>,
2341 <GIC_SPI 2341 <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH>,
2342 <GIC_SPI 2342 <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>,
2343 <GIC_SPI 2343 <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>,
2344 <GIC_SPI 2344 <GIC_SPI 668 IRQ_TYPE_LEVEL_HIGH>,
2345 <GIC_SPI 2345 <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>,
2346 <GIC_SPI 2346 <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>,
2347 <GIC_SPI 2347 <GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH>;
2348 clocks = <&gpucc GPU_ 2348 clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
2349 <&gpucc GPU_ 2349 <&gpucc GPU_CC_HUB_CX_INT_CLK>,
2350 <&gpucc GPU_ 2350 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
2351 <&gcc GCC_GP 2351 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2352 <&gcc GCC_GP 2352 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
2353 <&gpucc GPU_ 2353 <&gpucc GPU_CC_AHB_CLK>;
2354 clock-names = "gmu", 2354 clock-names = "gmu",
2355 "hub", 2355 "hub",
2356 "hlos", 2356 "hlos",
2357 "bus", 2357 "bus",
2358 "iface" 2358 "iface",
2359 "ahb"; 2359 "ahb";
2360 power-domains = <&gpu 2360 power-domains = <&gpucc GPU_CX_GDSC>;
2361 dma-coherent; 2361 dma-coherent;
2362 }; 2362 };
2363 2363
2364 usb_1_hsphy: phy@88e3000 { 2364 usb_1_hsphy: phy@88e3000 {
2365 compatible = "qcom,sm 2365 compatible = "qcom,sm8450-usb-hs-phy",
2366 "qcom,us 2366 "qcom,usb-snps-hs-7nm-phy";
2367 reg = <0 0x088e3000 0 2367 reg = <0 0x088e3000 0 0x400>;
2368 status = "disabled"; 2368 status = "disabled";
2369 #phy-cells = <0>; 2369 #phy-cells = <0>;
2370 2370
2371 clocks = <&rpmhcc RPM 2371 clocks = <&rpmhcc RPMH_CXO_CLK>;
2372 clock-names = "ref"; 2372 clock-names = "ref";
2373 2373
2374 resets = <&gcc GCC_QU 2374 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2375 }; 2375 };
2376 2376
2377 usb_1_qmpphy: phy@88e8000 { 2377 usb_1_qmpphy: phy@88e8000 {
2378 compatible = "qcom,sm 2378 compatible = "qcom,sm8450-qmp-usb3-dp-phy";
2379 reg = <0 0x088e8000 0 2379 reg = <0 0x088e8000 0 0x3000>;
2380 2380
2381 clocks = <&gcc GCC_US 2381 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2382 <&rpmhcc RPM 2382 <&rpmhcc RPMH_CXO_CLK>,
2383 <&gcc GCC_US 2383 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
2384 <&gcc GCC_US 2384 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2385 clock-names = "aux", 2385 clock-names = "aux", "ref", "com_aux", "usb3_pipe";
2386 2386
2387 resets = <&gcc GCC_US 2387 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
2388 <&gcc GCC_US 2388 <&gcc GCC_USB3_PHY_PRIM_BCR>;
2389 reset-names = "phy", 2389 reset-names = "phy", "common";
2390 2390
2391 #clock-cells = <1>; 2391 #clock-cells = <1>;
2392 #phy-cells = <1>; 2392 #phy-cells = <1>;
2393 2393
2394 orientation-switch; 2394 orientation-switch;
2395 2395
2396 status = "disabled"; 2396 status = "disabled";
2397 2397
2398 ports { 2398 ports {
2399 #address-cell 2399 #address-cells = <1>;
2400 #size-cells = 2400 #size-cells = <0>;
2401 2401
2402 port@0 { 2402 port@0 {
2403 reg = 2403 reg = <0>;
2404 2404
2405 usb_1 2405 usb_1_qmpphy_out: endpoint {
2406 }; 2406 };
2407 }; 2407 };
2408 2408
2409 port@1 { 2409 port@1 {
2410 reg = 2410 reg = <1>;
2411 2411
2412 usb_1 2412 usb_1_qmpphy_usb_ss_in: endpoint {
2413 2413 remote-endpoint = <&usb_1_dwc3_ss>;
2414 }; 2414 };
2415 }; 2415 };
2416 2416
2417 port@2 { 2417 port@2 {
2418 reg = 2418 reg = <2>;
2419 2419
2420 usb_1 2420 usb_1_qmpphy_dp_in: endpoint {
2421 2421 remote-endpoint = <&mdss_dp0_out>;
2422 }; 2422 };
2423 }; 2423 };
2424 }; 2424 };
2425 }; 2425 };
2426 2426
2427 remoteproc_slpi: remoteproc@2 2427 remoteproc_slpi: remoteproc@2400000 {
2428 compatible = "qcom,sm 2428 compatible = "qcom,sm8450-slpi-pas";
2429 reg = <0 0x02400000 0 2429 reg = <0 0x02400000 0 0x4000>;
2430 2430
2431 interrupts-extended = 2431 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>,
2432 2432 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
2433 2433 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
2434 2434 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
2435 2435 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
2436 interrupt-names = "wd 2436 interrupt-names = "wdog", "fatal", "ready",
2437 "ha 2437 "handover", "stop-ack";
2438 2438
2439 clocks = <&rpmhcc RPM 2439 clocks = <&rpmhcc RPMH_CXO_CLK>;
2440 clock-names = "xo"; 2440 clock-names = "xo";
2441 2441
2442 power-domains = <&rpm 2442 power-domains = <&rpmhpd RPMHPD_LCX>,
2443 <&rpm 2443 <&rpmhpd RPMHPD_LMX>;
2444 power-domain-names = 2444 power-domain-names = "lcx", "lmx";
2445 2445
2446 memory-region = <&slp 2446 memory-region = <&slpi_mem>;
2447 2447
2448 qcom,qmp = <&aoss_qmp 2448 qcom,qmp = <&aoss_qmp>;
2449 2449
2450 qcom,smem-states = <& 2450 qcom,smem-states = <&smp2p_slpi_out 0>;
2451 qcom,smem-state-names 2451 qcom,smem-state-names = "stop";
2452 2452
2453 status = "disabled"; 2453 status = "disabled";
2454 2454
2455 glink-edge { 2455 glink-edge {
2456 interrupts-ex 2456 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
2457 2457 IPCC_MPROC_SIGNAL_GLINK_QMP
2458 2458 IRQ_TYPE_EDGE_RISING>;
2459 mboxes = <&ip 2459 mboxes = <&ipcc IPCC_CLIENT_SLPI
2460 2460 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2461 2461
2462 label = "slpi 2462 label = "slpi";
2463 qcom,remote-p 2463 qcom,remote-pid = <3>;
2464 2464
2465 fastrpc { 2465 fastrpc {
2466 compa 2466 compatible = "qcom,fastrpc";
2467 qcom, 2467 qcom,glink-channels = "fastrpcglink-apps-dsp";
2468 label 2468 label = "sdsp";
2469 qcom, 2469 qcom,non-secure-domain;
2470 #addr 2470 #address-cells = <1>;
2471 #size 2471 #size-cells = <0>;
2472 2472
2473 compu 2473 compute-cb@1 {
2474 2474 compatible = "qcom,fastrpc-compute-cb";
2475 2475 reg = <1>;
2476 2476 iommus = <&apps_smmu 0x0541 0x0>;
2477 }; 2477 };
2478 2478
2479 compu 2479 compute-cb@2 {
2480 2480 compatible = "qcom,fastrpc-compute-cb";
2481 2481 reg = <2>;
2482 2482 iommus = <&apps_smmu 0x0542 0x0>;
2483 }; 2483 };
2484 2484
2485 compu 2485 compute-cb@3 {
2486 2486 compatible = "qcom,fastrpc-compute-cb";
2487 2487 reg = <3>;
2488 2488 iommus = <&apps_smmu 0x0543 0x0>;
2489 2489 /* note: shared-cb = <4> in downstream */
2490 }; 2490 };
2491 }; 2491 };
2492 }; 2492 };
2493 }; 2493 };
2494 2494
2495 wsa2macro: codec@31e0000 { 2495 wsa2macro: codec@31e0000 {
2496 compatible = "qcom,sm 2496 compatible = "qcom,sm8450-lpass-wsa-macro";
2497 reg = <0 0x031e0000 0 2497 reg = <0 0x031e0000 0 0x1000>;
2498 clocks = <&q6prmcc LP 2498 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2499 <&q6prmcc LP 2499 <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2500 <&q6prmcc LP 2500 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2501 <&q6prmcc LP 2501 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2502 <&vamacro>; 2502 <&vamacro>;
2503 clock-names = "mclk", 2503 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2504 2504
2505 #clock-cells = <0>; 2505 #clock-cells = <0>;
2506 clock-output-names = 2506 clock-output-names = "wsa2-mclk";
2507 #sound-dai-cells = <1 2507 #sound-dai-cells = <1>;
2508 }; 2508 };
2509 2509
2510 swr4: soundwire@31f0000 { 2510 swr4: soundwire@31f0000 {
2511 compatible = "qcom,so 2511 compatible = "qcom,soundwire-v1.7.0";
2512 reg = <0 0x031f0000 0 2512 reg = <0 0x031f0000 0 0x2000>;
2513 interrupts = <GIC_SPI 2513 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
2514 clocks = <&wsa2macro> 2514 clocks = <&wsa2macro>;
2515 clock-names = "iface" 2515 clock-names = "iface";
2516 label = "WSA2"; 2516 label = "WSA2";
2517 2517
2518 pinctrl-0 = <&wsa2_sw 2518 pinctrl-0 = <&wsa2_swr_active>;
2519 pinctrl-names = "defa 2519 pinctrl-names = "default";
2520 2520
2521 qcom,din-ports = <2>; 2521 qcom,din-ports = <2>;
2522 qcom,dout-ports = <6> 2522 qcom,dout-ports = <6>;
2523 2523
2524 qcom,ports-sinterval- 2524 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2525 qcom,ports-offset1 = 2525 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2526 qcom,ports-offset2 = 2526 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2527 qcom,ports-hstart = 2527 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2528 qcom,ports-hstop = 2528 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2529 qcom,ports-word-lengt 2529 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2530 qcom,ports-block-pack 2530 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
2531 qcom,ports-block-grou 2531 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2532 qcom,ports-lane-contr 2532 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2533 2533
2534 #address-cells = <2>; 2534 #address-cells = <2>;
2535 #size-cells = <0>; 2535 #size-cells = <0>;
2536 #sound-dai-cells = <1 2536 #sound-dai-cells = <1>;
2537 status = "disabled"; 2537 status = "disabled";
2538 }; 2538 };
2539 2539
2540 rxmacro: codec@3200000 { 2540 rxmacro: codec@3200000 {
2541 compatible = "qcom,sm 2541 compatible = "qcom,sm8450-lpass-rx-macro";
2542 reg = <0 0x03200000 0 2542 reg = <0 0x03200000 0 0x1000>;
2543 clocks = <&q6prmcc LP 2543 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2544 <&q6prmcc LP 2544 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2545 <&q6prmcc LP 2545 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2546 <&q6prmcc LP 2546 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2547 <&vamacro>; 2547 <&vamacro>;
2548 clock-names = "mclk", 2548 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2549 2549
2550 #clock-cells = <0>; 2550 #clock-cells = <0>;
2551 clock-output-names = 2551 clock-output-names = "mclk";
2552 #sound-dai-cells = <1 2552 #sound-dai-cells = <1>;
2553 }; 2553 };
2554 2554
2555 swr1: soundwire@3210000 { 2555 swr1: soundwire@3210000 {
2556 compatible = "qcom,so 2556 compatible = "qcom,soundwire-v1.7.0";
2557 reg = <0 0x03210000 0 2557 reg = <0 0x03210000 0 0x2000>;
2558 interrupts = <GIC_SPI 2558 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
2559 clocks = <&rxmacro>; 2559 clocks = <&rxmacro>;
2560 clock-names = "iface" 2560 clock-names = "iface";
2561 label = "RX"; 2561 label = "RX";
2562 qcom,din-ports = <0>; 2562 qcom,din-ports = <0>;
2563 qcom,dout-ports = <5> 2563 qcom,dout-ports = <5>;
2564 2564
2565 pinctrl-0 = <&rx_swr_ 2565 pinctrl-0 = <&rx_swr_active>;
2566 pinctrl-names = "defa 2566 pinctrl-names = "default";
2567 2567
2568 qcom,ports-sinterval- 2568 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
2569 qcom,ports-offset1 = 2569 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>;
2570 qcom,ports-offset2 = 2570 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
2571 qcom,ports-hstart = 2571 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
2572 qcom,ports-hstop = 2572 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
2573 qcom,ports-word-lengt 2573 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2574 qcom,ports-block-pack 2574 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
2575 qcom,ports-block-grou 2575 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
2576 qcom,ports-lane-contr 2576 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2577 2577
2578 #address-cells = <2>; 2578 #address-cells = <2>;
2579 #size-cells = <0>; 2579 #size-cells = <0>;
2580 #sound-dai-cells = <1 2580 #sound-dai-cells = <1>;
2581 status = "disabled"; 2581 status = "disabled";
2582 }; 2582 };
2583 2583
2584 txmacro: codec@3220000 { 2584 txmacro: codec@3220000 {
2585 compatible = "qcom,sm 2585 compatible = "qcom,sm8450-lpass-tx-macro";
2586 reg = <0 0x03220000 0 2586 reg = <0 0x03220000 0 0x1000>;
2587 clocks = <&q6prmcc LP 2587 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2588 <&q6prmcc LP 2588 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2589 <&q6prmcc LP 2589 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2590 <&q6prmcc LP 2590 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2591 <&vamacro>; 2591 <&vamacro>;
2592 clock-names = "mclk", 2592 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2593 2593
2594 #clock-cells = <0>; 2594 #clock-cells = <0>;
2595 clock-output-names = 2595 clock-output-names = "mclk";
2596 #sound-dai-cells = <1 2596 #sound-dai-cells = <1>;
2597 }; 2597 };
2598 2598
2599 wsamacro: codec@3240000 { 2599 wsamacro: codec@3240000 {
2600 compatible = "qcom,sm 2600 compatible = "qcom,sm8450-lpass-wsa-macro";
2601 reg = <0 0x03240000 0 2601 reg = <0 0x03240000 0 0x1000>;
2602 clocks = <&q6prmcc LP 2602 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2603 <&q6prmcc LP 2603 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2604 <&q6prmcc LP 2604 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2605 <&q6prmcc LP 2605 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2606 <&vamacro>; 2606 <&vamacro>;
2607 clock-names = "mclk", 2607 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2608 2608
2609 #clock-cells = <0>; 2609 #clock-cells = <0>;
2610 clock-output-names = 2610 clock-output-names = "mclk";
2611 #sound-dai-cells = <1 2611 #sound-dai-cells = <1>;
2612 }; 2612 };
2613 2613
2614 swr0: soundwire@3250000 { 2614 swr0: soundwire@3250000 {
2615 compatible = "qcom,so 2615 compatible = "qcom,soundwire-v1.7.0";
2616 reg = <0 0x03250000 0 2616 reg = <0 0x03250000 0 0x2000>;
2617 interrupts = <GIC_SPI 2617 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
2618 clocks = <&wsamacro>; 2618 clocks = <&wsamacro>;
2619 clock-names = "iface" 2619 clock-names = "iface";
2620 label = "WSA"; 2620 label = "WSA";
2621 2621
2622 pinctrl-0 = <&wsa_swr 2622 pinctrl-0 = <&wsa_swr_active>;
2623 pinctrl-names = "defa 2623 pinctrl-names = "default";
2624 2624
2625 qcom,din-ports = <2>; 2625 qcom,din-ports = <2>;
2626 qcom,dout-ports = <6> 2626 qcom,dout-ports = <6>;
2627 2627
2628 qcom,ports-sinterval- 2628 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2629 qcom,ports-offset1 = 2629 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2630 qcom,ports-offset2 = 2630 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2631 qcom,ports-hstart = 2631 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2632 qcom,ports-hstop = 2632 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2633 qcom,ports-word-lengt 2633 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2634 qcom,ports-block-pack 2634 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
2635 qcom,ports-block-grou 2635 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2636 qcom,ports-lane-contr 2636 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2637 2637
2638 #address-cells = <2>; 2638 #address-cells = <2>;
2639 #size-cells = <0>; 2639 #size-cells = <0>;
2640 #sound-dai-cells = <1 2640 #sound-dai-cells = <1>;
2641 status = "disabled"; 2641 status = "disabled";
2642 }; 2642 };
2643 2643
2644 swr2: soundwire@33b0000 { 2644 swr2: soundwire@33b0000 {
2645 compatible = "qcom,so 2645 compatible = "qcom,soundwire-v1.7.0";
2646 reg = <0 0x033b0000 0 2646 reg = <0 0x033b0000 0 0x2000>;
2647 interrupts = <GIC_SPI 2647 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
2648 <GIC_SPI 2648 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>;
2649 interrupt-names = "co 2649 interrupt-names = "core", "wakeup";
2650 2650
2651 clocks = <&txmacro>; 2651 clocks = <&txmacro>;
2652 clock-names = "iface" 2652 clock-names = "iface";
2653 label = "TX"; 2653 label = "TX";
2654 2654
2655 pinctrl-0 = <&tx_swr_ 2655 pinctrl-0 = <&tx_swr_active>;
2656 pinctrl-names = "defa 2656 pinctrl-names = "default";
2657 2657
2658 qcom,din-ports = <4>; 2658 qcom,din-ports = <4>;
2659 qcom,dout-ports = <0> 2659 qcom,dout-ports = <0>;
2660 qcom,ports-sinterval- 2660 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
2661 qcom,ports-offset1 = 2661 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>;
2662 qcom,ports-offset2 = 2662 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
2663 qcom,ports-hstart = 2663 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
2664 qcom,ports-hstop = 2664 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
2665 qcom,ports-word-lengt 2665 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
2666 qcom,ports-block-pack 2666 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
2667 qcom,ports-block-grou 2667 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
2668 qcom,ports-lane-contr 2668 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>;
2669 2669
2670 #address-cells = <2>; 2670 #address-cells = <2>;
2671 #size-cells = <0>; 2671 #size-cells = <0>;
2672 #sound-dai-cells = <1 2672 #sound-dai-cells = <1>;
2673 status = "disabled"; 2673 status = "disabled";
2674 }; 2674 };
2675 2675
2676 vamacro: codec@33f0000 { 2676 vamacro: codec@33f0000 {
2677 compatible = "qcom,sm 2677 compatible = "qcom,sm8450-lpass-va-macro";
2678 reg = <0 0x033f0000 0 2678 reg = <0 0x033f0000 0 0x1000>;
2679 clocks = <&q6prmcc LP 2679 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2680 <&q6prmcc LP 2680 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2681 <&q6prmcc LP 2681 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2682 <&q6prmcc LP 2682 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2683 clock-names = "mclk", 2683 clock-names = "mclk", "macro", "dcodec", "npl";
2684 2684
2685 #clock-cells = <0>; 2685 #clock-cells = <0>;
2686 clock-output-names = 2686 clock-output-names = "fsgen";
2687 #sound-dai-cells = <1 2687 #sound-dai-cells = <1>;
2688 status = "disabled"; 2688 status = "disabled";
2689 }; 2689 };
2690 2690
2691 remoteproc_adsp: remoteproc@3 2691 remoteproc_adsp: remoteproc@30000000 {
2692 compatible = "qcom,sm 2692 compatible = "qcom,sm8450-adsp-pas";
2693 reg = <0 0x30000000 0 2693 reg = <0 0x30000000 0 0x100>;
2694 2694
2695 interrupts-extended = 2695 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
2696 2696 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
2697 2697 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
2698 2698 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
2699 2699 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
2700 interrupt-names = "wd 2700 interrupt-names = "wdog", "fatal", "ready",
2701 "ha 2701 "handover", "stop-ack";
2702 2702
2703 clocks = <&rpmhcc RPM 2703 clocks = <&rpmhcc RPMH_CXO_CLK>;
2704 clock-names = "xo"; 2704 clock-names = "xo";
2705 2705
2706 power-domains = <&rpm 2706 power-domains = <&rpmhpd RPMHPD_LCX>,
2707 <&rpm 2707 <&rpmhpd RPMHPD_LMX>;
2708 power-domain-names = 2708 power-domain-names = "lcx", "lmx";
2709 2709
2710 memory-region = <&ads 2710 memory-region = <&adsp_mem>;
2711 2711
2712 qcom,qmp = <&aoss_qmp 2712 qcom,qmp = <&aoss_qmp>;
2713 2713
2714 qcom,smem-states = <& 2714 qcom,smem-states = <&smp2p_adsp_out 0>;
2715 qcom,smem-state-names 2715 qcom,smem-state-names = "stop";
2716 2716
2717 status = "disabled"; 2717 status = "disabled";
2718 2718
2719 remoteproc_adsp_glink 2719 remoteproc_adsp_glink: glink-edge {
2720 interrupts-ex 2720 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
2721 2721 IPCC_MPROC_SIGNAL_GLINK_QMP
2722 2722 IRQ_TYPE_EDGE_RISING>;
2723 mboxes = <&ip 2723 mboxes = <&ipcc IPCC_CLIENT_LPASS
2724 2724 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2725 2725
2726 label = "lpas 2726 label = "lpass";
2727 qcom,remote-p 2727 qcom,remote-pid = <2>;
2728 2728
2729 gpr { 2729 gpr {
2730 compa 2730 compatible = "qcom,gpr";
2731 qcom, 2731 qcom,glink-channels = "adsp_apps";
2732 qcom, 2732 qcom,domain = <GPR_DOMAIN_ID_ADSP>;
2733 qcom, 2733 qcom,intents = <512 20>;
2734 #addr 2734 #address-cells = <1>;
2735 #size 2735 #size-cells = <0>;
2736 2736
2737 q6apm 2737 q6apm: service@1 {
2738 2738 compatible = "qcom,q6apm";
2739 2739 reg = <GPR_APM_MODULE_IID>;
2740 2740 #sound-dai-cells = <0>;
2741 2741 qcom,protection-domain = "avs/audio",
2742 2742 "msm/adsp/audio_pd";
2743 2743
2744 2744 q6apmdai: dais {
2745 2745 compatible = "qcom,q6apm-dais";
2746 2746 iommus = <&apps_smmu 0x1801 0x0>;
2747 2747 };
2748 2748
2749 2749 q6apmbedai: bedais {
2750 2750 compatible = "qcom,q6apm-lpass-dais";
2751 2751 #sound-dai-cells = <1>;
2752 2752 };
2753 }; 2753 };
2754 2754
2755 q6prm 2755 q6prm: service@2 {
2756 2756 compatible = "qcom,q6prm";
2757 2757 reg = <GPR_PRM_MODULE_IID>;
2758 2758 qcom,protection-domain = "avs/audio",
2759 2759 "msm/adsp/audio_pd";
2760 2760
2761 2761 q6prmcc: clock-controller {
2762 2762 compatible = "qcom,q6prm-lpass-clocks";
2763 2763 #clock-cells = <2>;
2764 2764 };
2765 }; 2765 };
2766 }; 2766 };
2767 2767
2768 fastrpc { 2768 fastrpc {
2769 compa 2769 compatible = "qcom,fastrpc";
2770 qcom, 2770 qcom,glink-channels = "fastrpcglink-apps-dsp";
2771 label 2771 label = "adsp";
2772 qcom, 2772 qcom,non-secure-domain;
2773 #addr 2773 #address-cells = <1>;
2774 #size 2774 #size-cells = <0>;
2775 2775
2776 compu 2776 compute-cb@3 {
2777 2777 compatible = "qcom,fastrpc-compute-cb";
2778 2778 reg = <3>;
2779 2779 iommus = <&apps_smmu 0x1803 0x0>;
2780 }; 2780 };
2781 2781
2782 compu 2782 compute-cb@4 {
2783 2783 compatible = "qcom,fastrpc-compute-cb";
2784 2784 reg = <4>;
2785 2785 iommus = <&apps_smmu 0x1804 0x0>;
2786 }; 2786 };
2787 2787
2788 compu 2788 compute-cb@5 {
2789 2789 compatible = "qcom,fastrpc-compute-cb";
2790 2790 reg = <5>;
2791 2791 iommus = <&apps_smmu 0x1805 0x0>;
2792 }; 2792 };
2793 }; 2793 };
2794 }; 2794 };
2795 }; 2795 };
2796 2796
2797 remoteproc_cdsp: remoteproc@3 2797 remoteproc_cdsp: remoteproc@32300000 {
2798 compatible = "qcom,sm 2798 compatible = "qcom,sm8450-cdsp-pas";
2799 reg = <0 0x32300000 0 2799 reg = <0 0x32300000 0 0x1400000>;
2800 2800
2801 interrupts-extended = 2801 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
2802 2802 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
2803 2803 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
2804 2804 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
2805 2805 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
2806 interrupt-names = "wd 2806 interrupt-names = "wdog", "fatal", "ready",
2807 "ha 2807 "handover", "stop-ack";
2808 2808
2809 clocks = <&rpmhcc RPM 2809 clocks = <&rpmhcc RPMH_CXO_CLK>;
2810 clock-names = "xo"; 2810 clock-names = "xo";
2811 2811
2812 power-domains = <&rpm 2812 power-domains = <&rpmhpd RPMHPD_CX>,
2813 <&rpm 2813 <&rpmhpd RPMHPD_MXC>;
2814 power-domain-names = 2814 power-domain-names = "cx", "mxc";
2815 2815
2816 memory-region = <&cds 2816 memory-region = <&cdsp_mem>;
2817 2817
2818 qcom,qmp = <&aoss_qmp 2818 qcom,qmp = <&aoss_qmp>;
2819 2819
2820 qcom,smem-states = <& 2820 qcom,smem-states = <&smp2p_cdsp_out 0>;
2821 qcom,smem-state-names 2821 qcom,smem-state-names = "stop";
2822 2822
2823 status = "disabled"; 2823 status = "disabled";
2824 2824
2825 glink-edge { 2825 glink-edge {
2826 interrupts-ex 2826 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
2827 2827 IPCC_MPROC_SIGNAL_GLINK_QMP
2828 2828 IRQ_TYPE_EDGE_RISING>;
2829 mboxes = <&ip 2829 mboxes = <&ipcc IPCC_CLIENT_CDSP
2830 2830 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2831 2831
2832 label = "cdsp 2832 label = "cdsp";
2833 qcom,remote-p 2833 qcom,remote-pid = <5>;
2834 2834
2835 fastrpc { 2835 fastrpc {
2836 compa 2836 compatible = "qcom,fastrpc";
2837 qcom, 2837 qcom,glink-channels = "fastrpcglink-apps-dsp";
2838 label 2838 label = "cdsp";
2839 qcom, 2839 qcom,non-secure-domain;
2840 #addr 2840 #address-cells = <1>;
2841 #size 2841 #size-cells = <0>;
2842 2842
2843 compu 2843 compute-cb@1 {
2844 2844 compatible = "qcom,fastrpc-compute-cb";
2845 2845 reg = <1>;
2846 2846 iommus = <&apps_smmu 0x2161 0x0400>,
2847 2847 <&apps_smmu 0x1021 0x1420>;
2848 }; 2848 };
2849 2849
2850 compu 2850 compute-cb@2 {
2851 2851 compatible = "qcom,fastrpc-compute-cb";
2852 2852 reg = <2>;
2853 2853 iommus = <&apps_smmu 0x2162 0x0400>,
2854 2854 <&apps_smmu 0x1022 0x1420>;
2855 }; 2855 };
2856 2856
2857 compu 2857 compute-cb@3 {
2858 2858 compatible = "qcom,fastrpc-compute-cb";
2859 2859 reg = <3>;
2860 2860 iommus = <&apps_smmu 0x2163 0x0400>,
2861 2861 <&apps_smmu 0x1023 0x1420>;
2862 }; 2862 };
2863 2863
2864 compu 2864 compute-cb@4 {
2865 2865 compatible = "qcom,fastrpc-compute-cb";
2866 2866 reg = <4>;
2867 2867 iommus = <&apps_smmu 0x2164 0x0400>,
2868 2868 <&apps_smmu 0x1024 0x1420>;
2869 }; 2869 };
2870 2870
2871 compu 2871 compute-cb@5 {
2872 2872 compatible = "qcom,fastrpc-compute-cb";
2873 2873 reg = <5>;
2874 2874 iommus = <&apps_smmu 0x2165 0x0400>,
2875 2875 <&apps_smmu 0x1025 0x1420>;
2876 }; 2876 };
2877 2877
2878 compu 2878 compute-cb@6 {
2879 2879 compatible = "qcom,fastrpc-compute-cb";
2880 2880 reg = <6>;
2881 2881 iommus = <&apps_smmu 0x2166 0x0400>,
2882 2882 <&apps_smmu 0x1026 0x1420>;
2883 }; 2883 };
2884 2884
2885 compu 2885 compute-cb@7 {
2886 2886 compatible = "qcom,fastrpc-compute-cb";
2887 2887 reg = <7>;
2888 2888 iommus = <&apps_smmu 0x2167 0x0400>,
2889 2889 <&apps_smmu 0x1027 0x1420>;
2890 }; 2890 };
2891 2891
2892 compu 2892 compute-cb@8 {
2893 2893 compatible = "qcom,fastrpc-compute-cb";
2894 2894 reg = <8>;
2895 2895 iommus = <&apps_smmu 0x2168 0x0400>,
2896 2896 <&apps_smmu 0x1028 0x1420>;
2897 }; 2897 };
2898 2898
2899 /* no 2899 /* note: secure cb9 in downstream */
2900 }; 2900 };
2901 }; 2901 };
2902 }; 2902 };
2903 2903
2904 remoteproc_mpss: remoteproc@4 2904 remoteproc_mpss: remoteproc@4080000 {
2905 compatible = "qcom,sm 2905 compatible = "qcom,sm8450-mpss-pas";
2906 reg = <0x0 0x04080000 2906 reg = <0x0 0x04080000 0x0 0x4040>;
2907 2907
2908 interrupts-extended = 2908 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
2909 2909 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
2910 2910 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
2911 2911 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
2912 2912 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>,
2913 2913 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>;
2914 interrupt-names = "wd 2914 interrupt-names = "wdog", "fatal", "ready", "handover",
2915 "st 2915 "stop-ack", "shutdown-ack";
2916 2916
2917 clocks = <&rpmhcc RPM 2917 clocks = <&rpmhcc RPMH_CXO_CLK>;
2918 clock-names = "xo"; 2918 clock-names = "xo";
2919 2919
2920 power-domains = <&rpm 2920 power-domains = <&rpmhpd RPMHPD_CX>,
2921 <&rpm 2921 <&rpmhpd RPMHPD_MSS>;
2922 power-domain-names = 2922 power-domain-names = "cx", "mss";
2923 2923
2924 memory-region = <&mps 2924 memory-region = <&mpss_mem>;
2925 2925
2926 qcom,qmp = <&aoss_qmp 2926 qcom,qmp = <&aoss_qmp>;
2927 2927
2928 qcom,smem-states = <& 2928 qcom,smem-states = <&smp2p_modem_out 0>;
2929 qcom,smem-state-names 2929 qcom,smem-state-names = "stop";
2930 2930
2931 status = "disabled"; 2931 status = "disabled";
2932 2932
2933 glink-edge { 2933 glink-edge {
2934 interrupts-ex 2934 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
2935 2935 IPCC_MPROC_SIGNAL_GLINK_QMP
2936 2936 IRQ_TYPE_EDGE_RISING>;
2937 mboxes = <&ip 2937 mboxes = <&ipcc IPCC_CLIENT_MPSS
2938 2938 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2939 label = "mode 2939 label = "modem";
2940 qcom,remote-p 2940 qcom,remote-pid = <1>;
2941 }; 2941 };
2942 }; 2942 };
2943 2943
2944 videocc: clock-controller@aaf 2944 videocc: clock-controller@aaf0000 {
2945 compatible = "qcom,sm 2945 compatible = "qcom,sm8450-videocc";
2946 reg = <0 0x0aaf0000 0 2946 reg = <0 0x0aaf0000 0 0x10000>;
2947 clocks = <&rpmhcc RPM 2947 clocks = <&rpmhcc RPMH_CXO_CLK>,
2948 <&gcc GCC_VI 2948 <&gcc GCC_VIDEO_AHB_CLK>;
2949 power-domains = <&rpm 2949 power-domains = <&rpmhpd RPMHPD_MMCX>;
2950 required-opps = <&rpm 2950 required-opps = <&rpmhpd_opp_low_svs>;
2951 #clock-cells = <1>; 2951 #clock-cells = <1>;
2952 #reset-cells = <1>; 2952 #reset-cells = <1>;
2953 #power-domain-cells = 2953 #power-domain-cells = <1>;
2954 }; 2954 };
2955 2955
2956 cci0: cci@ac15000 { 2956 cci0: cci@ac15000 {
2957 compatible = "qcom,sm 2957 compatible = "qcom,sm8450-cci", "qcom,msm8996-cci";
2958 reg = <0 0x0ac15000 0 2958 reg = <0 0x0ac15000 0 0x1000>;
2959 interrupts = <GIC_SPI 2959 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
2960 power-domains = <&cam 2960 power-domains = <&camcc TITAN_TOP_GDSC>;
2961 2961
2962 clocks = <&camcc CAM_ 2962 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
2963 <&camcc CAM_ 2963 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
2964 <&camcc CAM_ 2964 <&camcc CAM_CC_CPAS_AHB_CLK>,
2965 <&camcc CAM_ 2965 <&camcc CAM_CC_CCI_0_CLK>,
2966 <&camcc CAM_ 2966 <&camcc CAM_CC_CCI_0_CLK_SRC>;
2967 clock-names = "camnoc 2967 clock-names = "camnoc_axi",
2968 "slow_a 2968 "slow_ahb_src",
2969 "cpas_a 2969 "cpas_ahb",
2970 "cci", 2970 "cci",
2971 "cci_sr 2971 "cci_src";
2972 pinctrl-0 = <&cci0_de 2972 pinctrl-0 = <&cci0_default &cci1_default>;
2973 pinctrl-1 = <&cci0_sl 2973 pinctrl-1 = <&cci0_sleep &cci1_sleep>;
2974 pinctrl-names = "defa 2974 pinctrl-names = "default", "sleep";
2975 2975
2976 status = "disabled"; 2976 status = "disabled";
2977 #address-cells = <1>; 2977 #address-cells = <1>;
2978 #size-cells = <0>; 2978 #size-cells = <0>;
2979 2979
2980 cci0_i2c0: i2c-bus@0 2980 cci0_i2c0: i2c-bus@0 {
2981 reg = <0>; 2981 reg = <0>;
2982 clock-frequen 2982 clock-frequency = <1000000>;
2983 #address-cell 2983 #address-cells = <1>;
2984 #size-cells = 2984 #size-cells = <0>;
2985 }; 2985 };
2986 2986
2987 cci0_i2c1: i2c-bus@1 2987 cci0_i2c1: i2c-bus@1 {
2988 reg = <1>; 2988 reg = <1>;
2989 clock-frequen 2989 clock-frequency = <1000000>;
2990 #address-cell 2990 #address-cells = <1>;
2991 #size-cells = 2991 #size-cells = <0>;
2992 }; 2992 };
2993 }; 2993 };
2994 2994
2995 cci1: cci@ac16000 { 2995 cci1: cci@ac16000 {
2996 compatible = "qcom,sm 2996 compatible = "qcom,sm8450-cci", "qcom,msm8996-cci";
2997 reg = <0 0x0ac16000 0 2997 reg = <0 0x0ac16000 0 0x1000>;
2998 interrupts = <GIC_SPI 2998 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>;
2999 power-domains = <&cam 2999 power-domains = <&camcc TITAN_TOP_GDSC>;
3000 3000
3001 clocks = <&camcc CAM_ 3001 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
3002 <&camcc CAM_ 3002 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
3003 <&camcc CAM_ 3003 <&camcc CAM_CC_CPAS_AHB_CLK>,
3004 <&camcc CAM_ 3004 <&camcc CAM_CC_CCI_1_CLK>,
3005 <&camcc CAM_ 3005 <&camcc CAM_CC_CCI_1_CLK_SRC>;
3006 clock-names = "camnoc 3006 clock-names = "camnoc_axi",
3007 "slow_a 3007 "slow_ahb_src",
3008 "cpas_a 3008 "cpas_ahb",
3009 "cci", 3009 "cci",
3010 "cci_sr 3010 "cci_src";
3011 pinctrl-0 = <&cci2_de 3011 pinctrl-0 = <&cci2_default &cci3_default>;
3012 pinctrl-1 = <&cci2_sl 3012 pinctrl-1 = <&cci2_sleep &cci3_sleep>;
3013 pinctrl-names = "defa 3013 pinctrl-names = "default", "sleep";
3014 3014
3015 status = "disabled"; 3015 status = "disabled";
3016 #address-cells = <1>; 3016 #address-cells = <1>;
3017 #size-cells = <0>; 3017 #size-cells = <0>;
3018 3018
3019 cci1_i2c0: i2c-bus@0 3019 cci1_i2c0: i2c-bus@0 {
3020 reg = <0>; 3020 reg = <0>;
3021 clock-frequen 3021 clock-frequency = <1000000>;
3022 #address-cell 3022 #address-cells = <1>;
3023 #size-cells = 3023 #size-cells = <0>;
3024 }; 3024 };
3025 3025
3026 cci1_i2c1: i2c-bus@1 3026 cci1_i2c1: i2c-bus@1 {
3027 reg = <1>; 3027 reg = <1>;
3028 clock-frequen 3028 clock-frequency = <1000000>;
3029 #address-cell 3029 #address-cells = <1>;
3030 #size-cells = 3030 #size-cells = <0>;
3031 }; 3031 };
3032 }; 3032 };
3033 3033
3034 camcc: clock-controller@ade00 3034 camcc: clock-controller@ade0000 {
3035 compatible = "qcom,sm 3035 compatible = "qcom,sm8450-camcc";
3036 reg = <0 0x0ade0000 0 3036 reg = <0 0x0ade0000 0 0x20000>;
3037 clocks = <&gcc GCC_CA 3037 clocks = <&gcc GCC_CAMERA_AHB_CLK>,
3038 <&rpmhcc RPM 3038 <&rpmhcc RPMH_CXO_CLK>,
3039 <&rpmhcc RPM 3039 <&rpmhcc RPMH_CXO_CLK_A>,
3040 <&sleep_clk> 3040 <&sleep_clk>;
3041 power-domains = <&rpm 3041 power-domains = <&rpmhpd RPMHPD_MMCX>;
3042 required-opps = <&rpm 3042 required-opps = <&rpmhpd_opp_low_svs>;
3043 #clock-cells = <1>; 3043 #clock-cells = <1>;
3044 #reset-cells = <1>; 3044 #reset-cells = <1>;
3045 #power-domain-cells = 3045 #power-domain-cells = <1>;
3046 status = "disabled"; 3046 status = "disabled";
3047 }; 3047 };
3048 3048
3049 mdss: display-subsystem@ae000 3049 mdss: display-subsystem@ae00000 {
3050 compatible = "qcom,sm 3050 compatible = "qcom,sm8450-mdss";
3051 reg = <0 0x0ae00000 0 3051 reg = <0 0x0ae00000 0 0x1000>;
3052 reg-names = "mdss"; 3052 reg-names = "mdss";
3053 3053
3054 /* same path used twi 3054 /* same path used twice */
3055 interconnects = <&mms 3055 interconnects = <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>,
3056 <&mms 3056 <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>,
3057 <&gem 3057 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
3058 &con 3058 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
3059 interconnect-names = 3059 interconnect-names = "mdp0-mem",
3060 3060 "mdp1-mem",
3061 3061 "cpu-cfg";
3062 3062
3063 resets = <&dispcc DIS 3063 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
3064 3064
3065 power-domains = <&dis 3065 power-domains = <&dispcc MDSS_GDSC>;
3066 3066
3067 clocks = <&dispcc DIS 3067 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3068 <&gcc GCC_DI 3068 <&gcc GCC_DISP_HF_AXI_CLK>,
3069 <&gcc GCC_DI 3069 <&gcc GCC_DISP_SF_AXI_CLK>,
3070 <&dispcc DIS 3070 <&dispcc DISP_CC_MDSS_MDP_CLK>;
3071 3071
3072 interrupts = <GIC_SPI 3072 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
3073 interrupt-controller; 3073 interrupt-controller;
3074 #interrupt-cells = <1 3074 #interrupt-cells = <1>;
3075 3075
3076 iommus = <&apps_smmu 3076 iommus = <&apps_smmu 0x2800 0x402>;
3077 3077
3078 #address-cells = <2>; 3078 #address-cells = <2>;
3079 #size-cells = <2>; 3079 #size-cells = <2>;
3080 ranges; 3080 ranges;
3081 3081
3082 status = "disabled"; 3082 status = "disabled";
3083 3083
3084 mdss_mdp: display-con 3084 mdss_mdp: display-controller@ae01000 {
3085 compatible = 3085 compatible = "qcom,sm8450-dpu";
3086 reg = <0 0x0a 3086 reg = <0 0x0ae01000 0 0x8f000>,
3087 <0 0x0a 3087 <0 0x0aeb0000 0 0x2008>;
3088 reg-names = " 3088 reg-names = "mdp", "vbif";
3089 3089
3090 clocks = <&gc 3090 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
3091 <&gcc 3091 <&gcc GCC_DISP_SF_AXI_CLK>,
3092 <&dis 3092 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3093 <&dis 3093 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
3094 <&dis 3094 <&dispcc DISP_CC_MDSS_MDP_CLK>,
3095 <&dis 3095 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3096 clock-names = 3096 clock-names = "bus",
3097 3097 "nrt_bus",
3098 3098 "iface",
3099 3099 "lut",
3100 3100 "core",
3101 3101 "vsync";
3102 3102
3103 assigned-cloc 3103 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3104 assigned-cloc 3104 assigned-clock-rates = <19200000>;
3105 3105
3106 operating-poi 3106 operating-points-v2 = <&mdp_opp_table>;
3107 power-domains 3107 power-domains = <&rpmhpd RPMHPD_MMCX>;
3108 3108
3109 interrupt-par 3109 interrupt-parent = <&mdss>;
3110 interrupts = 3110 interrupts = <0>;
3111 3111
3112 ports { 3112 ports {
3113 #addr 3113 #address-cells = <1>;
3114 #size 3114 #size-cells = <0>;
3115 3115
3116 port@ 3116 port@0 {
3117 3117 reg = <0>;
3118 3118 dpu_intf1_out: endpoint {
3119 3119 remote-endpoint = <&mdss_dsi0_in>;
3120 3120 };
3121 }; 3121 };
3122 3122
3123 port@ 3123 port@1 {
3124 3124 reg = <1>;
3125 3125 dpu_intf2_out: endpoint {
3126 3126 remote-endpoint = <&mdss_dsi1_in>;
3127 3127 };
3128 }; 3128 };
3129 3129
3130 port@ 3130 port@2 {
3131 3131 reg = <2>;
3132 3132 dpu_intf0_out: endpoint {
3133 3133 remote-endpoint = <&mdss_dp0_in>;
3134 3134 };
3135 }; 3135 };
3136 }; 3136 };
3137 3137
3138 mdp_opp_table 3138 mdp_opp_table: opp-table {
3139 compa 3139 compatible = "operating-points-v2";
3140 3140
3141 opp-1 3141 opp-172000000 {
3142 3142 opp-hz = /bits/ 64 <172000000>;
3143 3143 required-opps = <&rpmhpd_opp_low_svs_d1>;
3144 }; 3144 };
3145 3145
3146 opp-2 3146 opp-200000000 {
3147 3147 opp-hz = /bits/ 64 <200000000>;
3148 3148 required-opps = <&rpmhpd_opp_low_svs>;
3149 }; 3149 };
3150 3150
3151 opp-3 3151 opp-325000000 {
3152 3152 opp-hz = /bits/ 64 <325000000>;
3153 3153 required-opps = <&rpmhpd_opp_svs>;
3154 }; 3154 };
3155 3155
3156 opp-3 3156 opp-375000000 {
3157 3157 opp-hz = /bits/ 64 <375000000>;
3158 3158 required-opps = <&rpmhpd_opp_svs_l1>;
3159 }; 3159 };
3160 3160
3161 opp-5 3161 opp-500000000 {
3162 3162 opp-hz = /bits/ 64 <500000000>;
3163 3163 required-opps = <&rpmhpd_opp_nom>;
3164 }; 3164 };
3165 }; 3165 };
3166 }; 3166 };
3167 3167
3168 mdss_dp0: displayport 3168 mdss_dp0: displayport-controller@ae90000 {
3169 compatible = 3169 compatible = "qcom,sm8450-dp", "qcom,sm8350-dp";
3170 reg = <0 0xae 3170 reg = <0 0xae90000 0 0x200>,
3171 <0 0xae 3171 <0 0xae90200 0 0x200>,
3172 <0 0xae 3172 <0 0xae90400 0 0xc00>,
3173 <0 0xae 3173 <0 0xae91000 0 0x400>,
3174 <0 0xae 3174 <0 0xae91400 0 0x400>;
3175 interrupt-par 3175 interrupt-parent = <&mdss>;
3176 interrupts = 3176 interrupts = <12>;
3177 clocks = <&di 3177 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3178 <&di 3178 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
3179 <&di 3179 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
3180 <&di 3180 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
3181 <&di 3181 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
3182 clock-names = 3182 clock-names = "core_iface",
3183 3183 "core_aux",
3184 3184 "ctrl_link",
3185 3185 "ctrl_link_iface",
3186 3186 "stream_pixel";
3187 3187
3188 assigned-cloc 3188 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
3189 3189 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
3190 assigned-cloc 3190 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3191 3191 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
3192 3192
3193 phys = <&usb_ 3193 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
3194 phy-names = " 3194 phy-names = "dp";
3195 3195
3196 #sound-dai-ce 3196 #sound-dai-cells = <0>;
3197 3197
3198 operating-poi 3198 operating-points-v2 = <&dp_opp_table>;
3199 power-domains 3199 power-domains = <&rpmhpd RPMHPD_MMCX>;
3200 3200
3201 status = "dis 3201 status = "disabled";
3202 3202
3203 ports { 3203 ports {
3204 #addr 3204 #address-cells = <1>;
3205 #size 3205 #size-cells = <0>;
3206 3206
3207 port@ 3207 port@0 {
3208 3208 reg = <0>;
3209 3209 mdss_dp0_in: endpoint {
3210 3210 remote-endpoint = <&dpu_intf0_out>;
3211 3211 };
3212 }; 3212 };
3213 3213
3214 port@ 3214 port@1 {
3215 3215 reg = <1>;
3216 3216
3217 3217 mdss_dp0_out: endpoint {
3218 3218 remote-endpoint = <&usb_1_qmpphy_dp_in>;
3219 3219 };
3220 }; 3220 };
3221 }; 3221 };
3222 3222
3223 dp_opp_table: 3223 dp_opp_table: opp-table {
3224 compa 3224 compatible = "operating-points-v2";
3225 3225
3226 opp-1 3226 opp-160000000 {
3227 3227 opp-hz = /bits/ 64 <160000000>;
3228 3228 required-opps = <&rpmhpd_opp_low_svs>;
3229 }; 3229 };
3230 3230
3231 opp-2 3231 opp-270000000 {
3232 3232 opp-hz = /bits/ 64 <270000000>;
3233 3233 required-opps = <&rpmhpd_opp_svs>;
3234 }; 3234 };
3235 3235
3236 opp-5 3236 opp-540000000 {
3237 3237 opp-hz = /bits/ 64 <540000000>;
3238 3238 required-opps = <&rpmhpd_opp_svs_l1>;
3239 }; 3239 };
3240 3240
3241 opp-8 3241 opp-810000000 {
3242 3242 opp-hz = /bits/ 64 <810000000>;
3243 3243 required-opps = <&rpmhpd_opp_nom>;
3244 }; 3244 };
3245 }; 3245 };
3246 }; 3246 };
3247 3247
3248 mdss_dsi0: dsi@ae9400 3248 mdss_dsi0: dsi@ae94000 {
3249 compatible = 3249 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3250 reg = <0 0x0a 3250 reg = <0 0x0ae94000 0 0x400>;
3251 reg-names = " 3251 reg-names = "dsi_ctrl";
3252 3252
3253 interrupt-par 3253 interrupt-parent = <&mdss>;
3254 interrupts = 3254 interrupts = <4>;
3255 3255
3256 clocks = <&di 3256 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
3257 <&di 3257 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
3258 <&di 3258 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
3259 <&di 3259 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
3260 <&di 3260 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3261 <&gcc 3261 <&gcc GCC_DISP_HF_AXI_CLK>;
3262 clock-names = 3262 clock-names = "byte",
3263 3263 "byte_intf",
3264 3264 "pixel",
3265 3265 "core",
3266 3266 "iface",
3267 3267 "bus";
3268 3268
3269 assigned-cloc 3269 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
3270 assigned-cloc 3270 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
3271 3271
3272 operating-poi 3272 operating-points-v2 = <&mdss_dsi_opp_table>;
3273 power-domains 3273 power-domains = <&rpmhpd RPMHPD_MMCX>;
3274 3274
3275 phys = <&mdss 3275 phys = <&mdss_dsi0_phy>;
3276 phy-names = " 3276 phy-names = "dsi";
3277 3277
3278 #address-cell 3278 #address-cells = <1>;
3279 #size-cells = 3279 #size-cells = <0>;
3280 3280
3281 status = "dis 3281 status = "disabled";
3282 3282
3283 ports { 3283 ports {
3284 #addr 3284 #address-cells = <1>;
3285 #size 3285 #size-cells = <0>;
3286 3286
3287 port@ 3287 port@0 {
3288 3288 reg = <0>;
3289 3289 mdss_dsi0_in: endpoint {
3290 3290 remote-endpoint = <&dpu_intf1_out>;
3291 3291 };
3292 }; 3292 };
3293 3293
3294 port@ 3294 port@1 {
3295 3295 reg = <1>;
3296 3296 mdss_dsi0_out: endpoint {
3297 3297 };
3298 }; 3298 };
3299 }; 3299 };
3300 3300
3301 mdss_dsi_opp_ 3301 mdss_dsi_opp_table: opp-table {
3302 compa 3302 compatible = "operating-points-v2";
3303 3303
3304 opp-1 3304 opp-187500000 {
3305 3305 opp-hz = /bits/ 64 <187500000>;
3306 3306 required-opps = <&rpmhpd_opp_low_svs>;
3307 }; 3307 };
3308 3308
3309 opp-3 3309 opp-300000000 {
3310 3310 opp-hz = /bits/ 64 <300000000>;
3311 3311 required-opps = <&rpmhpd_opp_svs>;
3312 }; 3312 };
3313 3313
3314 opp-3 3314 opp-358000000 {
3315 3315 opp-hz = /bits/ 64 <358000000>;
3316 3316 required-opps = <&rpmhpd_opp_svs_l1>;
3317 }; 3317 };
3318 }; 3318 };
3319 }; 3319 };
3320 3320
3321 mdss_dsi0_phy: phy@ae 3321 mdss_dsi0_phy: phy@ae94400 {
3322 compatible = 3322 compatible = "qcom,sm8450-dsi-phy-5nm";
3323 reg = <0 0x0a 3323 reg = <0 0x0ae94400 0 0x200>,
3324 <0 0x0a 3324 <0 0x0ae94600 0 0x280>,
3325 <0 0x0a 3325 <0 0x0ae94900 0 0x260>;
3326 reg-names = " 3326 reg-names = "dsi_phy",
3327 " 3327 "dsi_phy_lane",
3328 " 3328 "dsi_pll";
3329 3329
3330 #clock-cells 3330 #clock-cells = <1>;
3331 #phy-cells = 3331 #phy-cells = <0>;
3332 3332
3333 clocks = <&di 3333 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3334 <&rp 3334 <&rpmhcc RPMH_CXO_CLK>;
3335 clock-names = 3335 clock-names = "iface", "ref";
3336 3336
3337 status = "dis 3337 status = "disabled";
3338 }; 3338 };
3339 3339
3340 mdss_dsi1: dsi@ae9600 3340 mdss_dsi1: dsi@ae96000 {
3341 compatible = 3341 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3342 reg = <0 0x0a 3342 reg = <0 0x0ae96000 0 0x400>;
3343 reg-names = " 3343 reg-names = "dsi_ctrl";
3344 3344
3345 interrupt-par 3345 interrupt-parent = <&mdss>;
3346 interrupts = 3346 interrupts = <5>;
3347 3347
3348 clocks = <&di 3348 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
3349 <&di 3349 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
3350 <&di 3350 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
3351 <&di 3351 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
3352 <&di 3352 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3353 <&gc 3353 <&gcc GCC_DISP_HF_AXI_CLK>;
3354 clock-names = 3354 clock-names = "byte",
3355 3355 "byte_intf",
3356 3356 "pixel",
3357 3357 "core",
3358 3358 "iface",
3359 3359 "bus";
3360 3360
3361 assigned-cloc 3361 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
3362 assigned-cloc 3362 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
3363 3363
3364 operating-poi 3364 operating-points-v2 = <&mdss_dsi_opp_table>;
3365 power-domains 3365 power-domains = <&rpmhpd RPMHPD_MMCX>;
3366 3366
3367 phys = <&mdss 3367 phys = <&mdss_dsi1_phy>;
3368 phy-names = " 3368 phy-names = "dsi";
3369 3369
3370 #address-cell 3370 #address-cells = <1>;
3371 #size-cells = 3371 #size-cells = <0>;
3372 3372
3373 status = "dis 3373 status = "disabled";
3374 3374
3375 ports { 3375 ports {
3376 #addr 3376 #address-cells = <1>;
3377 #size 3377 #size-cells = <0>;
3378 3378
3379 port@ 3379 port@0 {
3380 3380 reg = <0>;
3381 3381 mdss_dsi1_in: endpoint {
3382 3382 remote-endpoint = <&dpu_intf2_out>;
3383 3383 };
3384 }; 3384 };
3385 3385
3386 port@ 3386 port@1 {
3387 3387 reg = <1>;
3388 3388 mdss_dsi1_out: endpoint {
3389 3389 };
3390 }; 3390 };
3391 }; 3391 };
3392 }; 3392 };
3393 3393
3394 mdss_dsi1_phy: phy@ae 3394 mdss_dsi1_phy: phy@ae96400 {
3395 compatible = 3395 compatible = "qcom,sm8450-dsi-phy-5nm";
3396 reg = <0 0x0a 3396 reg = <0 0x0ae96400 0 0x200>,
3397 <0 0x0a 3397 <0 0x0ae96600 0 0x280>,
3398 <0 0x0a 3398 <0 0x0ae96900 0 0x260>;
3399 reg-names = " 3399 reg-names = "dsi_phy",
3400 " 3400 "dsi_phy_lane",
3401 " 3401 "dsi_pll";
3402 3402
3403 #clock-cells 3403 #clock-cells = <1>;
3404 #phy-cells = 3404 #phy-cells = <0>;
3405 3405
3406 clocks = <&di 3406 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3407 <&rp 3407 <&rpmhcc RPMH_CXO_CLK>;
3408 clock-names = 3408 clock-names = "iface", "ref";
3409 3409
3410 status = "dis 3410 status = "disabled";
3411 }; 3411 };
3412 }; 3412 };
3413 3413
3414 dispcc: clock-controller@af00 3414 dispcc: clock-controller@af00000 {
3415 compatible = "qcom,sm 3415 compatible = "qcom,sm8450-dispcc";
3416 reg = <0 0x0af00000 0 3416 reg = <0 0x0af00000 0 0x20000>;
3417 clocks = <&rpmhcc RPM 3417 clocks = <&rpmhcc RPMH_CXO_CLK>,
3418 <&rpmhcc RPM 3418 <&rpmhcc RPMH_CXO_CLK_A>,
3419 <&gcc GCC_DI 3419 <&gcc GCC_DISP_AHB_CLK>,
3420 <&sleep_clk> 3420 <&sleep_clk>,
3421 <&mdss_dsi0_ 3421 <&mdss_dsi0_phy 0>,
3422 <&mdss_dsi0_ 3422 <&mdss_dsi0_phy 1>,
3423 <&mdss_dsi1_ 3423 <&mdss_dsi1_phy 0>,
3424 <&mdss_dsi1_ 3424 <&mdss_dsi1_phy 1>,
3425 <&usb_1_qmpp 3425 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3426 <&usb_1_qmpp 3426 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
3427 <0>, /* dp1 3427 <0>, /* dp1 */
3428 <0>, 3428 <0>,
3429 <0>, /* dp2 3429 <0>, /* dp2 */
3430 <0>, 3430 <0>,
3431 <0>, /* dp3 3431 <0>, /* dp3 */
3432 <0>; 3432 <0>;
3433 power-domains = <&rpm 3433 power-domains = <&rpmhpd RPMHPD_MMCX>;
3434 required-opps = <&rpm 3434 required-opps = <&rpmhpd_opp_low_svs>;
3435 #clock-cells = <1>; 3435 #clock-cells = <1>;
3436 #reset-cells = <1>; 3436 #reset-cells = <1>;
3437 #power-domain-cells = 3437 #power-domain-cells = <1>;
3438 status = "disabled"; 3438 status = "disabled";
3439 }; 3439 };
3440 3440
3441 pdc: interrupt-controller@b22 3441 pdc: interrupt-controller@b220000 {
3442 compatible = "qcom,sm 3442 compatible = "qcom,sm8450-pdc", "qcom,pdc";
3443 reg = <0 0x0b220000 0 3443 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
3444 qcom,pdc-ranges = <0 3444 qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>,
3445 <94 3445 <94 609 31>, <125 63 1>, <126 716 12>;
3446 #interrupt-cells = <2 3446 #interrupt-cells = <2>;
3447 interrupt-parent = <& 3447 interrupt-parent = <&intc>;
3448 interrupt-controller; 3448 interrupt-controller;
3449 }; 3449 };
3450 3450
3451 tsens0: thermal-sensor@c26300 3451 tsens0: thermal-sensor@c263000 {
3452 compatible = "qcom,sm 3452 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2";
3453 reg = <0 0x0c263000 0 3453 reg = <0 0x0c263000 0 0x1000>, /* TM */
3454 <0 0x0c222000 0 3454 <0 0x0c222000 0 0x1000>; /* SROT */
3455 #qcom,sensors = <16>; 3455 #qcom,sensors = <16>;
3456 interrupts = <GIC_SPI 3456 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
3457 <GIC_SPI 3457 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
3458 interrupt-names = "up 3458 interrupt-names = "uplow", "critical";
3459 #thermal-sensor-cells 3459 #thermal-sensor-cells = <1>;
3460 }; 3460 };
3461 3461
3462 tsens1: thermal-sensor@c26500 3462 tsens1: thermal-sensor@c265000 {
3463 compatible = "qcom,sm 3463 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2";
3464 reg = <0 0x0c265000 0 3464 reg = <0 0x0c265000 0 0x1000>, /* TM */
3465 <0 0x0c223000 0 3465 <0 0x0c223000 0 0x1000>; /* SROT */
3466 #qcom,sensors = <16>; 3466 #qcom,sensors = <16>;
3467 interrupts = <GIC_SPI 3467 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
3468 <GIC_SPI 3468 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
3469 interrupt-names = "up 3469 interrupt-names = "uplow", "critical";
3470 #thermal-sensor-cells 3470 #thermal-sensor-cells = <1>;
3471 }; 3471 };
3472 3472
3473 aoss_qmp: power-management@c3 3473 aoss_qmp: power-management@c300000 {
3474 compatible = "qcom,sm 3474 compatible = "qcom,sm8450-aoss-qmp", "qcom,aoss-qmp";
3475 reg = <0 0x0c300000 0 3475 reg = <0 0x0c300000 0 0x400>;
3476 interrupts-extended = 3476 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
3477 3477 IRQ_TYPE_EDGE_RISING>;
3478 mboxes = <&ipcc IPCC_ 3478 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
3479 3479
3480 #clock-cells = <0>; 3480 #clock-cells = <0>;
3481 }; 3481 };
3482 3482
3483 sram@c3f0000 { 3483 sram@c3f0000 {
3484 compatible = "qcom,rp 3484 compatible = "qcom,rpmh-stats";
3485 reg = <0 0x0c3f0000 0 3485 reg = <0 0x0c3f0000 0 0x400>;
3486 }; 3486 };
3487 3487
3488 spmi_bus: spmi@c400000 { 3488 spmi_bus: spmi@c400000 {
3489 compatible = "qcom,sp 3489 compatible = "qcom,spmi-pmic-arb";
3490 reg = <0 0x0c400000 0 3490 reg = <0 0x0c400000 0 0x00003000>,
3491 <0 0x0c500000 0 3491 <0 0x0c500000 0 0x00400000>,
3492 <0 0x0c440000 0 3492 <0 0x0c440000 0 0x00080000>,
3493 <0 0x0c4c0000 0 3493 <0 0x0c4c0000 0 0x00010000>,
3494 <0 0x0c42d000 0 3494 <0 0x0c42d000 0 0x00010000>;
3495 reg-names = "core", 3495 reg-names = "core",
3496 "chnls", 3496 "chnls",
3497 "obsrvr", 3497 "obsrvr",
3498 "intr", 3498 "intr",
3499 "cnfg"; 3499 "cnfg";
3500 interrupt-names = "pe 3500 interrupt-names = "periph_irq";
3501 interrupts-extended = 3501 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3502 qcom,ee = <0>; 3502 qcom,ee = <0>;
3503 qcom,channel = <0>; 3503 qcom,channel = <0>;
3504 interrupt-controller; 3504 interrupt-controller;
3505 #interrupt-cells = <4 3505 #interrupt-cells = <4>;
3506 #address-cells = <2>; 3506 #address-cells = <2>;
3507 #size-cells = <0>; 3507 #size-cells = <0>;
3508 }; 3508 };
3509 3509
3510 ipcc: mailbox@ed18000 { 3510 ipcc: mailbox@ed18000 {
3511 compatible = "qcom,sm 3511 compatible = "qcom,sm8450-ipcc", "qcom,ipcc";
3512 reg = <0 0x0ed18000 0 3512 reg = <0 0x0ed18000 0 0x1000>;
3513 interrupts = <GIC_SPI 3513 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
3514 interrupt-controller; 3514 interrupt-controller;
3515 #interrupt-cells = <3 3515 #interrupt-cells = <3>;
3516 #mbox-cells = <2>; 3516 #mbox-cells = <2>;
3517 }; 3517 };
3518 3518
3519 tlmm: pinctrl@f100000 { 3519 tlmm: pinctrl@f100000 {
3520 compatible = "qcom,sm 3520 compatible = "qcom,sm8450-tlmm";
3521 reg = <0 0x0f100000 0 3521 reg = <0 0x0f100000 0 0x300000>;
3522 interrupts = <GIC_SPI 3522 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
3523 gpio-controller; 3523 gpio-controller;
3524 #gpio-cells = <2>; 3524 #gpio-cells = <2>;
3525 interrupt-controller; 3525 interrupt-controller;
3526 #interrupt-cells = <2 3526 #interrupt-cells = <2>;
3527 gpio-ranges = <&tlmm 3527 gpio-ranges = <&tlmm 0 0 211>;
3528 wakeup-parent = <&pdc 3528 wakeup-parent = <&pdc>;
3529 3529
3530 sdc2_default_state: s 3530 sdc2_default_state: sdc2-default-state {
3531 clk-pins { 3531 clk-pins {
3532 pins 3532 pins = "sdc2_clk";
3533 drive 3533 drive-strength = <16>;
3534 bias- 3534 bias-disable;
3535 }; 3535 };
3536 3536
3537 cmd-pins { 3537 cmd-pins {
3538 pins 3538 pins = "sdc2_cmd";
3539 drive 3539 drive-strength = <16>;
3540 bias- 3540 bias-pull-up;
3541 }; 3541 };
3542 3542
3543 data-pins { 3543 data-pins {
3544 pins 3544 pins = "sdc2_data";
3545 drive 3545 drive-strength = <16>;
3546 bias- 3546 bias-pull-up;
3547 }; 3547 };
3548 }; 3548 };
3549 3549
3550 sdc2_sleep_state: sdc 3550 sdc2_sleep_state: sdc2-sleep-state {
3551 clk-pins { 3551 clk-pins {
3552 pins 3552 pins = "sdc2_clk";
3553 drive 3553 drive-strength = <2>;
3554 bias- 3554 bias-disable;
3555 }; 3555 };
3556 3556
3557 cmd-pins { 3557 cmd-pins {
3558 pins 3558 pins = "sdc2_cmd";
3559 drive 3559 drive-strength = <2>;
3560 bias- 3560 bias-pull-up;
3561 }; 3561 };
3562 3562
3563 data-pins { 3563 data-pins {
3564 pins 3564 pins = "sdc2_data";
3565 drive 3565 drive-strength = <2>;
3566 bias- 3566 bias-pull-up;
3567 }; 3567 };
3568 }; 3568 };
3569 3569
3570 cci0_default: cci0-de 3570 cci0_default: cci0-default-state {
3571 /* SDA, SCL * 3571 /* SDA, SCL */
3572 pins = "gpio1 3572 pins = "gpio110", "gpio111";
3573 function = "c 3573 function = "cci_i2c";
3574 drive-strengt 3574 drive-strength = <2>;
3575 bias-pull-up; 3575 bias-pull-up;
3576 }; 3576 };
3577 3577
3578 cci0_sleep: cci0-slee 3578 cci0_sleep: cci0-sleep-state {
3579 /* SDA, SCL * 3579 /* SDA, SCL */
3580 pins = "gpio1 3580 pins = "gpio110", "gpio111";
3581 function = "c 3581 function = "cci_i2c";
3582 drive-strengt 3582 drive-strength = <2>;
3583 bias-pull-dow 3583 bias-pull-down;
3584 }; 3584 };
3585 3585
3586 cci1_default: cci1-de 3586 cci1_default: cci1-default-state {
3587 /* SDA, SCL * 3587 /* SDA, SCL */
3588 pins = "gpio1 3588 pins = "gpio112", "gpio113";
3589 function = "c 3589 function = "cci_i2c";
3590 drive-strengt 3590 drive-strength = <2>;
3591 bias-pull-up; 3591 bias-pull-up;
3592 }; 3592 };
3593 3593
3594 cci1_sleep: cci1-slee 3594 cci1_sleep: cci1-sleep-state {
3595 /* SDA, SCL * 3595 /* SDA, SCL */
3596 pins = "gpio1 3596 pins = "gpio112", "gpio113";
3597 function = "c 3597 function = "cci_i2c";
3598 drive-strengt 3598 drive-strength = <2>;
3599 bias-pull-dow 3599 bias-pull-down;
3600 }; 3600 };
3601 3601
3602 cci2_default: cci2-de 3602 cci2_default: cci2-default-state {
3603 /* SDA, SCL * 3603 /* SDA, SCL */
3604 pins = "gpio1 3604 pins = "gpio114", "gpio115";
3605 function = "c 3605 function = "cci_i2c";
3606 drive-strengt 3606 drive-strength = <2>;
3607 bias-pull-up; 3607 bias-pull-up;
3608 }; 3608 };
3609 3609
3610 cci2_sleep: cci2-slee 3610 cci2_sleep: cci2-sleep-state {
3611 /* SDA, SCL * 3611 /* SDA, SCL */
3612 pins = "gpio1 3612 pins = "gpio114", "gpio115";
3613 function = "c 3613 function = "cci_i2c";
3614 drive-strengt 3614 drive-strength = <2>;
3615 bias-pull-dow 3615 bias-pull-down;
3616 }; 3616 };
3617 3617
3618 cci3_default: cci3-de 3618 cci3_default: cci3-default-state {
3619 /* SDA, SCL * 3619 /* SDA, SCL */
3620 pins = "gpio2 3620 pins = "gpio208", "gpio209";
3621 function = "c 3621 function = "cci_i2c";
3622 drive-strengt 3622 drive-strength = <2>;
3623 bias-pull-up; 3623 bias-pull-up;
3624 }; 3624 };
3625 3625
3626 cci3_sleep: cci3-slee 3626 cci3_sleep: cci3-sleep-state {
3627 /* SDA, SCL * 3627 /* SDA, SCL */
3628 pins = "gpio2 3628 pins = "gpio208", "gpio209";
3629 function = "c 3629 function = "cci_i2c";
3630 drive-strengt 3630 drive-strength = <2>;
3631 bias-pull-dow 3631 bias-pull-down;
3632 }; 3632 };
3633 3633
3634 pcie0_default_state: 3634 pcie0_default_state: pcie0-default-state {
3635 perst-pins { 3635 perst-pins {
3636 pins 3636 pins = "gpio94";
3637 funct 3637 function = "gpio";
3638 drive 3638 drive-strength = <2>;
3639 bias- 3639 bias-pull-down;
3640 }; 3640 };
3641 3641
3642 clkreq-pins { 3642 clkreq-pins {
3643 pins 3643 pins = "gpio95";
3644 funct 3644 function = "pcie0_clkreqn";
3645 drive 3645 drive-strength = <2>;
3646 bias- 3646 bias-pull-up;
3647 }; 3647 };
3648 3648
3649 wake-pins { 3649 wake-pins {
3650 pins 3650 pins = "gpio96";
3651 funct 3651 function = "gpio";
3652 drive 3652 drive-strength = <2>;
3653 bias- 3653 bias-pull-up;
3654 }; 3654 };
3655 }; 3655 };
3656 3656
3657 pcie1_default_state: 3657 pcie1_default_state: pcie1-default-state {
3658 perst-pins { 3658 perst-pins {
3659 pins 3659 pins = "gpio97";
3660 funct 3660 function = "gpio";
3661 drive 3661 drive-strength = <2>;
3662 bias- 3662 bias-pull-down;
3663 }; 3663 };
3664 3664
3665 clkreq-pins { 3665 clkreq-pins {
3666 pins 3666 pins = "gpio98";
3667 funct 3667 function = "pcie1_clkreqn";
3668 drive 3668 drive-strength = <2>;
3669 bias- 3669 bias-pull-up;
3670 }; 3670 };
3671 3671
3672 wake-pins { 3672 wake-pins {
3673 pins 3673 pins = "gpio99";
3674 funct 3674 function = "gpio";
3675 drive 3675 drive-strength = <2>;
3676 bias- 3676 bias-pull-up;
3677 }; 3677 };
3678 }; 3678 };
3679 3679
3680 qup_i2c0_data_clk: qu 3680 qup_i2c0_data_clk: qup-i2c0-data-clk-state {
3681 pins = "gpio0 3681 pins = "gpio0", "gpio1";
3682 function = "q 3682 function = "qup0";
3683 }; 3683 };
3684 3684
3685 qup_i2c1_data_clk: qu 3685 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
3686 pins = "gpio4 3686 pins = "gpio4", "gpio5";
3687 function = "q 3687 function = "qup1";
3688 }; 3688 };
3689 3689
3690 qup_i2c2_data_clk: qu 3690 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
3691 pins = "gpio8 3691 pins = "gpio8", "gpio9";
3692 function = "q 3692 function = "qup2";
3693 }; 3693 };
3694 3694
3695 qup_i2c3_data_clk: qu 3695 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
3696 pins = "gpio1 3696 pins = "gpio12", "gpio13";
3697 function = "q 3697 function = "qup3";
3698 }; 3698 };
3699 3699
3700 qup_i2c4_data_clk: qu 3700 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
3701 pins = "gpio1 3701 pins = "gpio16", "gpio17";
3702 function = "q 3702 function = "qup4";
3703 }; 3703 };
3704 3704
3705 qup_i2c5_data_clk: qu 3705 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
3706 pins = "gpio2 3706 pins = "gpio206", "gpio207";
3707 function = "q 3707 function = "qup5";
3708 }; 3708 };
3709 3709
3710 qup_i2c6_data_clk: qu 3710 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
3711 pins = "gpio2 3711 pins = "gpio20", "gpio21";
3712 function = "q 3712 function = "qup6";
3713 }; 3713 };
3714 3714
3715 qup_i2c8_data_clk: qu 3715 qup_i2c8_data_clk: qup-i2c8-data-clk-state {
3716 pins = "gpio2 3716 pins = "gpio28", "gpio29";
3717 function = "q 3717 function = "qup8";
3718 }; 3718 };
3719 3719
3720 qup_i2c9_data_clk: qu 3720 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
3721 pins = "gpio3 3721 pins = "gpio32", "gpio33";
3722 function = "q 3722 function = "qup9";
3723 }; 3723 };
3724 3724
3725 qup_i2c10_data_clk: q 3725 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
3726 pins = "gpio3 3726 pins = "gpio36", "gpio37";
3727 function = "q 3727 function = "qup10";
3728 }; 3728 };
3729 3729
3730 qup_i2c11_data_clk: q 3730 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
3731 pins = "gpio4 3731 pins = "gpio40", "gpio41";
3732 function = "q 3732 function = "qup11";
3733 }; 3733 };
3734 3734
3735 qup_i2c12_data_clk: q 3735 qup_i2c12_data_clk: qup-i2c12-data-clk-state {
3736 pins = "gpio4 3736 pins = "gpio44", "gpio45";
3737 function = "q 3737 function = "qup12";
3738 }; 3738 };
3739 3739
3740 qup_i2c13_data_clk: q 3740 qup_i2c13_data_clk: qup-i2c13-data-clk-state {
3741 pins = "gpio4 3741 pins = "gpio48", "gpio49";
3742 function = "q 3742 function = "qup13";
3743 drive-strengt 3743 drive-strength = <2>;
3744 bias-pull-up; 3744 bias-pull-up;
3745 }; 3745 };
3746 3746
3747 qup_i2c14_data_clk: q 3747 qup_i2c14_data_clk: qup-i2c14-data-clk-state {
3748 pins = "gpio5 3748 pins = "gpio52", "gpio53";
3749 function = "q 3749 function = "qup14";
3750 drive-strengt 3750 drive-strength = <2>;
3751 bias-pull-up; 3751 bias-pull-up;
3752 }; 3752 };
3753 3753
3754 qup_i2c15_data_clk: q 3754 qup_i2c15_data_clk: qup-i2c15-data-clk-state {
3755 pins = "gpio5 3755 pins = "gpio56", "gpio57";
3756 function = "q 3756 function = "qup15";
3757 }; 3757 };
3758 3758
3759 qup_i2c16_data_clk: q 3759 qup_i2c16_data_clk: qup-i2c16-data-clk-state {
3760 pins = "gpio6 3760 pins = "gpio60", "gpio61";
3761 function = "q 3761 function = "qup16";
3762 }; 3762 };
3763 3763
3764 qup_i2c17_data_clk: q 3764 qup_i2c17_data_clk: qup-i2c17-data-clk-state {
3765 pins = "gpio6 3765 pins = "gpio64", "gpio65";
3766 function = "q 3766 function = "qup17";
3767 }; 3767 };
3768 3768
3769 qup_i2c18_data_clk: q 3769 qup_i2c18_data_clk: qup-i2c18-data-clk-state {
3770 pins = "gpio6 3770 pins = "gpio68", "gpio69";
3771 function = "q 3771 function = "qup18";
3772 }; 3772 };
3773 3773
3774 qup_i2c19_data_clk: q 3774 qup_i2c19_data_clk: qup-i2c19-data-clk-state {
3775 pins = "gpio7 3775 pins = "gpio72", "gpio73";
3776 function = "q 3776 function = "qup19";
3777 }; 3777 };
3778 3778
3779 qup_i2c20_data_clk: q 3779 qup_i2c20_data_clk: qup-i2c20-data-clk-state {
3780 pins = "gpio7 3780 pins = "gpio76", "gpio77";
3781 function = "q 3781 function = "qup20";
3782 }; 3782 };
3783 3783
3784 qup_i2c21_data_clk: q 3784 qup_i2c21_data_clk: qup-i2c21-data-clk-state {
3785 pins = "gpio8 3785 pins = "gpio80", "gpio81";
3786 function = "q 3786 function = "qup21";
3787 }; 3787 };
3788 3788
3789 qup_spi0_cs: qup-spi0 3789 qup_spi0_cs: qup-spi0-cs-state {
3790 pins = "gpio3 3790 pins = "gpio3";
3791 function = "q 3791 function = "qup0";
3792 }; 3792 };
3793 3793
3794 qup_spi0_data_clk: qu 3794 qup_spi0_data_clk: qup-spi0-data-clk-state {
3795 pins = "gpio0 3795 pins = "gpio0", "gpio1", "gpio2";
3796 function = "q 3796 function = "qup0";
3797 }; 3797 };
3798 3798
3799 qup_spi1_cs: qup-spi1 3799 qup_spi1_cs: qup-spi1-cs-state {
3800 pins = "gpio7 3800 pins = "gpio7";
3801 function = "q 3801 function = "qup1";
3802 }; 3802 };
3803 3803
3804 qup_spi1_data_clk: qu 3804 qup_spi1_data_clk: qup-spi1-data-clk-state {
3805 pins = "gpio4 3805 pins = "gpio4", "gpio5", "gpio6";
3806 function = "q 3806 function = "qup1";
3807 }; 3807 };
3808 3808
3809 qup_spi2_cs: qup-spi2 3809 qup_spi2_cs: qup-spi2-cs-state {
3810 pins = "gpio1 3810 pins = "gpio11";
3811 function = "q 3811 function = "qup2";
3812 }; 3812 };
3813 3813
3814 qup_spi2_data_clk: qu 3814 qup_spi2_data_clk: qup-spi2-data-clk-state {
3815 pins = "gpio8 3815 pins = "gpio8", "gpio9", "gpio10";
3816 function = "q 3816 function = "qup2";
3817 }; 3817 };
3818 3818
3819 qup_spi3_cs: qup-spi3 3819 qup_spi3_cs: qup-spi3-cs-state {
3820 pins = "gpio1 3820 pins = "gpio15";
3821 function = "q 3821 function = "qup3";
3822 }; 3822 };
3823 3823
3824 qup_spi3_data_clk: qu 3824 qup_spi3_data_clk: qup-spi3-data-clk-state {
3825 pins = "gpio1 3825 pins = "gpio12", "gpio13", "gpio14";
3826 function = "q 3826 function = "qup3";
3827 }; 3827 };
3828 3828
3829 qup_spi4_cs: qup-spi4 3829 qup_spi4_cs: qup-spi4-cs-state {
3830 pins = "gpio1 3830 pins = "gpio19";
3831 function = "q 3831 function = "qup4";
3832 drive-strengt 3832 drive-strength = <6>;
3833 bias-disable; 3833 bias-disable;
3834 }; 3834 };
3835 3835
3836 qup_spi4_data_clk: qu 3836 qup_spi4_data_clk: qup-spi4-data-clk-state {
3837 pins = "gpio1 3837 pins = "gpio16", "gpio17", "gpio18";
3838 function = "q 3838 function = "qup4";
3839 }; 3839 };
3840 3840
3841 qup_spi5_cs: qup-spi5 3841 qup_spi5_cs: qup-spi5-cs-state {
3842 pins = "gpio8 3842 pins = "gpio85";
3843 function = "q 3843 function = "qup5";
3844 }; 3844 };
3845 3845
3846 qup_spi5_data_clk: qu 3846 qup_spi5_data_clk: qup-spi5-data-clk-state {
3847 pins = "gpio2 3847 pins = "gpio206", "gpio207", "gpio84";
3848 function = "q 3848 function = "qup5";
3849 }; 3849 };
3850 3850
3851 qup_spi6_cs: qup-spi6 3851 qup_spi6_cs: qup-spi6-cs-state {
3852 pins = "gpio2 3852 pins = "gpio23";
3853 function = "q 3853 function = "qup6";
3854 }; 3854 };
3855 3855
3856 qup_spi6_data_clk: qu 3856 qup_spi6_data_clk: qup-spi6-data-clk-state {
3857 pins = "gpio2 3857 pins = "gpio20", "gpio21", "gpio22";
3858 function = "q 3858 function = "qup6";
3859 }; 3859 };
3860 3860
3861 qup_spi8_cs: qup-spi8 3861 qup_spi8_cs: qup-spi8-cs-state {
3862 pins = "gpio3 3862 pins = "gpio31";
3863 function = "q 3863 function = "qup8";
3864 }; 3864 };
3865 3865
3866 qup_spi8_data_clk: qu 3866 qup_spi8_data_clk: qup-spi8-data-clk-state {
3867 pins = "gpio2 3867 pins = "gpio28", "gpio29", "gpio30";
3868 function = "q 3868 function = "qup8";
3869 }; 3869 };
3870 3870
3871 qup_spi9_cs: qup-spi9 3871 qup_spi9_cs: qup-spi9-cs-state {
3872 pins = "gpio3 3872 pins = "gpio35";
3873 function = "q 3873 function = "qup9";
3874 }; 3874 };
3875 3875
3876 qup_spi9_data_clk: qu 3876 qup_spi9_data_clk: qup-spi9-data-clk-state {
3877 pins = "gpio3 3877 pins = "gpio32", "gpio33", "gpio34";
3878 function = "q 3878 function = "qup9";
3879 }; 3879 };
3880 3880
3881 qup_spi10_cs: qup-spi 3881 qup_spi10_cs: qup-spi10-cs-state {
3882 pins = "gpio3 3882 pins = "gpio39";
3883 function = "q 3883 function = "qup10";
3884 }; 3884 };
3885 3885
3886 qup_spi10_data_clk: q 3886 qup_spi10_data_clk: qup-spi10-data-clk-state {
3887 pins = "gpio3 3887 pins = "gpio36", "gpio37", "gpio38";
3888 function = "q 3888 function = "qup10";
3889 }; 3889 };
3890 3890
3891 qup_spi11_cs: qup-spi 3891 qup_spi11_cs: qup-spi11-cs-state {
3892 pins = "gpio4 3892 pins = "gpio43";
3893 function = "q 3893 function = "qup11";
3894 }; 3894 };
3895 3895
3896 qup_spi11_data_clk: q 3896 qup_spi11_data_clk: qup-spi11-data-clk-state {
3897 pins = "gpio4 3897 pins = "gpio40", "gpio41", "gpio42";
3898 function = "q 3898 function = "qup11";
3899 }; 3899 };
3900 3900
3901 qup_spi12_cs: qup-spi 3901 qup_spi12_cs: qup-spi12-cs-state {
3902 pins = "gpio4 3902 pins = "gpio47";
3903 function = "q 3903 function = "qup12";
3904 }; 3904 };
3905 3905
3906 qup_spi12_data_clk: q 3906 qup_spi12_data_clk: qup-spi12-data-clk-state {
3907 pins = "gpio4 3907 pins = "gpio44", "gpio45", "gpio46";
3908 function = "q 3908 function = "qup12";
3909 }; 3909 };
3910 3910
3911 qup_spi13_cs: qup-spi 3911 qup_spi13_cs: qup-spi13-cs-state {
3912 pins = "gpio5 3912 pins = "gpio51";
3913 function = "q 3913 function = "qup13";
3914 }; 3914 };
3915 3915
3916 qup_spi13_data_clk: q 3916 qup_spi13_data_clk: qup-spi13-data-clk-state {
3917 pins = "gpio4 3917 pins = "gpio48", "gpio49", "gpio50";
3918 function = "q 3918 function = "qup13";
3919 }; 3919 };
3920 3920
3921 qup_spi14_cs: qup-spi 3921 qup_spi14_cs: qup-spi14-cs-state {
3922 pins = "gpio5 3922 pins = "gpio55";
3923 function = "q 3923 function = "qup14";
3924 }; 3924 };
3925 3925
3926 qup_spi14_data_clk: q 3926 qup_spi14_data_clk: qup-spi14-data-clk-state {
3927 pins = "gpio5 3927 pins = "gpio52", "gpio53", "gpio54";
3928 function = "q 3928 function = "qup14";
3929 }; 3929 };
3930 3930
3931 qup_spi15_cs: qup-spi 3931 qup_spi15_cs: qup-spi15-cs-state {
3932 pins = "gpio5 3932 pins = "gpio59";
3933 function = "q 3933 function = "qup15";
3934 }; 3934 };
3935 3935
3936 qup_spi15_data_clk: q 3936 qup_spi15_data_clk: qup-spi15-data-clk-state {
3937 pins = "gpio5 3937 pins = "gpio56", "gpio57", "gpio58";
3938 function = "q 3938 function = "qup15";
3939 }; 3939 };
3940 3940
3941 qup_spi16_cs: qup-spi 3941 qup_spi16_cs: qup-spi16-cs-state {
3942 pins = "gpio6 3942 pins = "gpio63";
3943 function = "q 3943 function = "qup16";
3944 }; 3944 };
3945 3945
3946 qup_spi16_data_clk: q 3946 qup_spi16_data_clk: qup-spi16-data-clk-state {
3947 pins = "gpio6 3947 pins = "gpio60", "gpio61", "gpio62";
3948 function = "q 3948 function = "qup16";
3949 }; 3949 };
3950 3950
3951 qup_spi17_cs: qup-spi 3951 qup_spi17_cs: qup-spi17-cs-state {
3952 pins = "gpio6 3952 pins = "gpio67";
3953 function = "q 3953 function = "qup17";
3954 }; 3954 };
3955 3955
3956 qup_spi17_data_clk: q 3956 qup_spi17_data_clk: qup-spi17-data-clk-state {
3957 pins = "gpio6 3957 pins = "gpio64", "gpio65", "gpio66";
3958 function = "q 3958 function = "qup17";
3959 }; 3959 };
3960 3960
3961 qup_spi18_cs: qup-spi 3961 qup_spi18_cs: qup-spi18-cs-state {
3962 pins = "gpio7 3962 pins = "gpio71";
3963 function = "q 3963 function = "qup18";
3964 drive-strengt 3964 drive-strength = <6>;
3965 bias-disable; 3965 bias-disable;
3966 }; 3966 };
3967 3967
3968 qup_spi18_data_clk: q 3968 qup_spi18_data_clk: qup-spi18-data-clk-state {
3969 pins = "gpio6 3969 pins = "gpio68", "gpio69", "gpio70";
3970 function = "q 3970 function = "qup18";
3971 drive-strengt 3971 drive-strength = <6>;
3972 bias-disable; 3972 bias-disable;
3973 }; 3973 };
3974 3974
3975 qup_spi19_cs: qup-spi 3975 qup_spi19_cs: qup-spi19-cs-state {
3976 pins = "gpio7 3976 pins = "gpio75";
3977 function = "q 3977 function = "qup19";
3978 drive-strengt 3978 drive-strength = <6>;
3979 bias-disable; 3979 bias-disable;
3980 }; 3980 };
3981 3981
3982 qup_spi19_data_clk: q 3982 qup_spi19_data_clk: qup-spi19-data-clk-state {
3983 pins = "gpio7 3983 pins = "gpio72", "gpio73", "gpio74";
3984 function = "q 3984 function = "qup19";
3985 drive-strengt 3985 drive-strength = <6>;
3986 bias-disable; 3986 bias-disable;
3987 }; 3987 };
3988 3988
3989 qup_spi20_cs: qup-spi 3989 qup_spi20_cs: qup-spi20-cs-state {
3990 pins = "gpio7 3990 pins = "gpio79";
3991 function = "q 3991 function = "qup20";
3992 }; 3992 };
3993 3993
3994 qup_spi20_data_clk: q 3994 qup_spi20_data_clk: qup-spi20-data-clk-state {
3995 pins = "gpio7 3995 pins = "gpio76", "gpio77", "gpio78";
3996 function = "q 3996 function = "qup20";
3997 }; 3997 };
3998 3998
3999 qup_spi21_cs: qup-spi 3999 qup_spi21_cs: qup-spi21-cs-state {
4000 pins = "gpio8 4000 pins = "gpio83";
4001 function = "q 4001 function = "qup21";
4002 }; 4002 };
4003 4003
4004 qup_spi21_data_clk: q 4004 qup_spi21_data_clk: qup-spi21-data-clk-state {
4005 pins = "gpio8 4005 pins = "gpio80", "gpio81", "gpio82";
4006 function = "q 4006 function = "qup21";
4007 }; 4007 };
4008 4008
4009 qup_uart7_rx: qup-uar 4009 qup_uart7_rx: qup-uart7-rx-state {
4010 pins = "gpio2 4010 pins = "gpio26";
4011 function = "q 4011 function = "qup7";
4012 drive-strengt 4012 drive-strength = <2>;
4013 bias-disable; 4013 bias-disable;
4014 }; 4014 };
4015 4015
4016 qup_uart7_tx: qup-uar 4016 qup_uart7_tx: qup-uart7-tx-state {
4017 pins = "gpio2 4017 pins = "gpio27";
4018 function = "q 4018 function = "qup7";
4019 drive-strengt 4019 drive-strength = <2>;
4020 bias-disable; 4020 bias-disable;
4021 }; 4021 };
4022 4022
4023 qup_uart20_default: q 4023 qup_uart20_default: qup-uart20-default-state {
4024 pins = "gpio7 4024 pins = "gpio76", "gpio77", "gpio78", "gpio79";
4025 function = "q 4025 function = "qup20";
4026 }; 4026 };
4027 }; 4027 };
4028 4028
4029 lpass_tlmm: pinctrl@3440000 { 4029 lpass_tlmm: pinctrl@3440000 {
4030 compatible = "qcom,sm 4030 compatible = "qcom,sm8450-lpass-lpi-pinctrl";
4031 reg = <0 0x03440000 0 4031 reg = <0 0x03440000 0x0 0x20000>,
4032 <0 0x034d0000 0 4032 <0 0x034d0000 0x0 0x10000>;
4033 gpio-controller; 4033 gpio-controller;
4034 #gpio-cells = <2>; 4034 #gpio-cells = <2>;
4035 gpio-ranges = <&lpass 4035 gpio-ranges = <&lpass_tlmm 0 0 23>;
4036 4036
4037 clocks = <&q6prmcc LP 4037 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
4038 <&q6prmcc LP 4038 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
4039 clock-names = "core", 4039 clock-names = "core", "audio";
4040 4040
4041 tx_swr_active: tx-swr 4041 tx_swr_active: tx-swr-active-state {
4042 clk-pins { 4042 clk-pins {
4043 pins 4043 pins = "gpio0";
4044 funct 4044 function = "swr_tx_clk";
4045 drive 4045 drive-strength = <2>;
4046 slew- 4046 slew-rate = <1>;
4047 bias- 4047 bias-disable;
4048 }; 4048 };
4049 4049
4050 data-pins { 4050 data-pins {
4051 pins 4051 pins = "gpio1", "gpio2", "gpio14";
4052 funct 4052 function = "swr_tx_data";
4053 drive 4053 drive-strength = <2>;
4054 slew- 4054 slew-rate = <1>;
4055 bias- 4055 bias-bus-hold;
4056 }; 4056 };
4057 }; 4057 };
4058 4058
4059 rx_swr_active: rx-swr 4059 rx_swr_active: rx-swr-active-state {
4060 clk-pins { 4060 clk-pins {
4061 pins 4061 pins = "gpio3";
4062 funct 4062 function = "swr_rx_clk";
4063 drive 4063 drive-strength = <2>;
4064 slew- 4064 slew-rate = <1>;
4065 bias- 4065 bias-disable;
4066 }; 4066 };
4067 4067
4068 data-pins { 4068 data-pins {
4069 pins 4069 pins = "gpio4", "gpio5";
4070 funct 4070 function = "swr_rx_data";
4071 drive 4071 drive-strength = <2>;
4072 slew- 4072 slew-rate = <1>;
4073 bias- 4073 bias-bus-hold;
4074 }; 4074 };
4075 }; 4075 };
4076 4076
4077 dmic01_default: dmic0 4077 dmic01_default: dmic01-default-state {
4078 clk-pins { 4078 clk-pins {
4079 pins 4079 pins = "gpio6";
4080 funct 4080 function = "dmic1_clk";
4081 drive 4081 drive-strength = <8>;
4082 outpu 4082 output-high;
4083 }; 4083 };
4084 4084
4085 data-pins { 4085 data-pins {
4086 pins 4086 pins = "gpio7";
4087 funct 4087 function = "dmic1_data";
4088 drive 4088 drive-strength = <8>;
4089 }; 4089 };
4090 }; 4090 };
4091 4091
4092 dmic23_default: dmic2 4092 dmic23_default: dmic23-default-state {
4093 clk-pins { 4093 clk-pins {
4094 pins 4094 pins = "gpio8";
4095 funct 4095 function = "dmic2_clk";
4096 drive 4096 drive-strength = <8>;
4097 outpu 4097 output-high;
4098 }; 4098 };
4099 4099
4100 data-pins { 4100 data-pins {
4101 pins 4101 pins = "gpio9";
4102 funct 4102 function = "dmic2_data";
4103 drive 4103 drive-strength = <8>;
4104 }; 4104 };
4105 }; 4105 };
4106 4106
4107 wsa_swr_active: wsa-s 4107 wsa_swr_active: wsa-swr-active-state {
4108 clk-pins { 4108 clk-pins {
4109 pins 4109 pins = "gpio10";
4110 funct 4110 function = "wsa_swr_clk";
4111 drive 4111 drive-strength = <2>;
4112 slew- 4112 slew-rate = <1>;
4113 bias- 4113 bias-disable;
4114 }; 4114 };
4115 4115
4116 data-pins { 4116 data-pins {
4117 pins 4117 pins = "gpio11";
4118 funct 4118 function = "wsa_swr_data";
4119 drive 4119 drive-strength = <2>;
4120 slew- 4120 slew-rate = <1>;
4121 bias- 4121 bias-bus-hold;
4122 }; 4122 };
4123 }; 4123 };
4124 4124
4125 wsa2_swr_active: wsa2 4125 wsa2_swr_active: wsa2-swr-active-state {
4126 clk-pins { 4126 clk-pins {
4127 pins 4127 pins = "gpio15";
4128 funct 4128 function = "wsa2_swr_clk";
4129 drive 4129 drive-strength = <2>;
4130 slew- 4130 slew-rate = <1>;
4131 bias- 4131 bias-disable;
4132 }; 4132 };
4133 4133
4134 data-pins { 4134 data-pins {
4135 pins 4135 pins = "gpio16";
4136 funct 4136 function = "wsa2_swr_data";
4137 drive 4137 drive-strength = <2>;
4138 slew- 4138 slew-rate = <1>;
4139 bias- 4139 bias-bus-hold;
4140 }; 4140 };
4141 }; 4141 };
4142 }; 4142 };
4143 4143
4144 sram@146aa000 { 4144 sram@146aa000 {
4145 compatible = "qcom,sm 4145 compatible = "qcom,sm8450-imem", "syscon", "simple-mfd";
4146 reg = <0 0x146aa000 0 4146 reg = <0 0x146aa000 0 0x1000>;
4147 ranges = <0 0 0x146aa 4147 ranges = <0 0 0x146aa000 0x1000>;
4148 4148
4149 #address-cells = <1>; 4149 #address-cells = <1>;
4150 #size-cells = <1>; 4150 #size-cells = <1>;
4151 4151
4152 pil-reloc@94c { 4152 pil-reloc@94c {
4153 compatible = 4153 compatible = "qcom,pil-reloc-info";
4154 reg = <0x94c 4154 reg = <0x94c 0xc8>;
4155 }; 4155 };
4156 }; 4156 };
4157 4157
4158 apps_smmu: iommu@15000000 { 4158 apps_smmu: iommu@15000000 {
4159 compatible = "qcom,sm 4159 compatible = "qcom,sm8450-smmu-500", "arm,mmu-500";
4160 reg = <0 0x15000000 0 4160 reg = <0 0x15000000 0 0x100000>;
4161 #iommu-cells = <2>; 4161 #iommu-cells = <2>;
4162 #global-interrupts = 4162 #global-interrupts = <1>;
4163 interrupts = <GIC_SPI 4163 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
4164 <GIC_SPI 4164 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
4165 <GIC_SPI 4165 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
4166 <GIC_SPI 4166 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
4167 <GIC_SPI 4167 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
4168 <GIC_SPI 4168 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
4169 <GIC_SPI 4169 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
4170 <GIC_SPI 4170 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
4171 <GIC_SPI 4171 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
4172 <GIC_SPI 4172 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
4173 <GIC_SPI 4173 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
4174 <GIC_SPI 4174 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
4175 <GIC_SPI 4175 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
4176 <GIC_SPI 4176 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
4177 <GIC_SPI 4177 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
4178 <GIC_SPI 4178 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
4179 <GIC_SPI 4179 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
4180 <GIC_SPI 4180 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
4181 <GIC_SPI 4181 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
4182 <GIC_SPI 4182 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
4183 <GIC_SPI 4183 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
4184 <GIC_SPI 4184 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
4185 <GIC_SPI 4185 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
4186 <GIC_SPI 4186 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
4187 <GIC_SPI 4187 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
4188 <GIC_SPI 4188 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
4189 <GIC_SPI 4189 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
4190 <GIC_SPI 4190 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
4191 <GIC_SPI 4191 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
4192 <GIC_SPI 4192 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
4193 <GIC_SPI 4193 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
4194 <GIC_SPI 4194 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
4195 <GIC_SPI 4195 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
4196 <GIC_SPI 4196 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
4197 <GIC_SPI 4197 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
4198 <GIC_SPI 4198 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
4199 <GIC_SPI 4199 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
4200 <GIC_SPI 4200 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
4201 <GIC_SPI 4201 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
4202 <GIC_SPI 4202 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
4203 <GIC_SPI 4203 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
4204 <GIC_SPI 4204 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
4205 <GIC_SPI 4205 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
4206 <GIC_SPI 4206 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
4207 <GIC_SPI 4207 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
4208 <GIC_SPI 4208 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
4209 <GIC_SPI 4209 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
4210 <GIC_SPI 4210 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
4211 <GIC_SPI 4211 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
4212 <GIC_SPI 4212 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
4213 <GIC_SPI 4213 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
4214 <GIC_SPI 4214 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
4215 <GIC_SPI 4215 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
4216 <GIC_SPI 4216 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
4217 <GIC_SPI 4217 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
4218 <GIC_SPI 4218 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
4219 <GIC_SPI 4219 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
4220 <GIC_SPI 4220 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
4221 <GIC_SPI 4221 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
4222 <GIC_SPI 4222 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
4223 <GIC_SPI 4223 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
4224 <GIC_SPI 4224 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
4225 <GIC_SPI 4225 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
4226 <GIC_SPI 4226 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
4227 <GIC_SPI 4227 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
4228 <GIC_SPI 4228 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
4229 <GIC_SPI 4229 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
4230 <GIC_SPI 4230 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
4231 <GIC_SPI 4231 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
4232 <GIC_SPI 4232 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
4233 <GIC_SPI 4233 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
4234 <GIC_SPI 4234 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
4235 <GIC_SPI 4235 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
4236 <GIC_SPI 4236 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
4237 <GIC_SPI 4237 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
4238 <GIC_SPI 4238 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
4239 <GIC_SPI 4239 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
4240 <GIC_SPI 4240 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
4241 <GIC_SPI 4241 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
4242 <GIC_SPI 4242 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
4243 <GIC_SPI 4243 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
4244 <GIC_SPI 4244 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
4245 <GIC_SPI 4245 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
4246 <GIC_SPI 4246 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
4247 <GIC_SPI 4247 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
4248 <GIC_SPI 4248 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
4249 <GIC_SPI 4249 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
4250 <GIC_SPI 4250 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
4251 <GIC_SPI 4251 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
4252 <GIC_SPI 4252 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
4253 <GIC_SPI 4253 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
4254 <GIC_SPI 4254 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
4255 <GIC_SPI 4255 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
4256 <GIC_SPI 4256 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
4257 <GIC_SPI 4257 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
4258 <GIC_SPI 4258 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
4259 <GIC_SPI 4259 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>;
4260 }; 4260 };
4261 4261
4262 intc: interrupt-controller@17 4262 intc: interrupt-controller@17100000 {
4263 compatible = "arm,gic 4263 compatible = "arm,gic-v3";
4264 #interrupt-cells = <3 4264 #interrupt-cells = <3>;
4265 interrupt-controller; 4265 interrupt-controller;
4266 #redistributor-region 4266 #redistributor-regions = <1>;
4267 redistributor-stride 4267 redistributor-stride = <0x0 0x40000>;
4268 reg = <0x0 0x17100000 4268 reg = <0x0 0x17100000 0x0 0x10000>, /* GICD */
4269 <0x0 0x17180000 4269 <0x0 0x17180000 0x0 0x200000>; /* GICR * 8 */
4270 interrupts = <GIC_PPI 4270 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
4271 #address-cells = <2>; 4271 #address-cells = <2>;
4272 #size-cells = <2>; 4272 #size-cells = <2>;
4273 ranges; 4273 ranges;
4274 4274
4275 gic_its: msi-controll 4275 gic_its: msi-controller@17140000 {
4276 compatible = 4276 compatible = "arm,gic-v3-its";
4277 reg = <0x0 0x 4277 reg = <0x0 0x17140000 0x0 0x20000>;
4278 msi-controlle 4278 msi-controller;
4279 #msi-cells = 4279 #msi-cells = <1>;
4280 }; 4280 };
4281 }; 4281 };
4282 4282
4283 timer@17420000 { 4283 timer@17420000 {
4284 compatible = "arm,arm 4284 compatible = "arm,armv7-timer-mem";
4285 #address-cells = <1>; 4285 #address-cells = <1>;
4286 #size-cells = <1>; 4286 #size-cells = <1>;
4287 ranges = <0 0 0 0x200 4287 ranges = <0 0 0 0x20000000>;
4288 reg = <0x0 0x17420000 4288 reg = <0x0 0x17420000 0x0 0x1000>;
4289 clock-frequency = <19 4289 clock-frequency = <19200000>;
4290 4290
4291 frame@17421000 { 4291 frame@17421000 {
4292 frame-number 4292 frame-number = <0>;
4293 interrupts = 4293 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
4294 4294 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
4295 reg = <0x1742 4295 reg = <0x17421000 0x1000>,
4296 <0x1742 4296 <0x17422000 0x1000>;
4297 }; 4297 };
4298 4298
4299 frame@17423000 { 4299 frame@17423000 {
4300 frame-number 4300 frame-number = <1>;
4301 interrupts = 4301 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
4302 reg = <0x1742 4302 reg = <0x17423000 0x1000>;
4303 status = "dis 4303 status = "disabled";
4304 }; 4304 };
4305 4305
4306 frame@17425000 { 4306 frame@17425000 {
4307 frame-number 4307 frame-number = <2>;
4308 interrupts = 4308 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
4309 reg = <0x1742 4309 reg = <0x17425000 0x1000>;
4310 status = "dis 4310 status = "disabled";
4311 }; 4311 };
4312 4312
4313 frame@17427000 { 4313 frame@17427000 {
4314 frame-number 4314 frame-number = <3>;
4315 interrupts = 4315 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
4316 reg = <0x1742 4316 reg = <0x17427000 0x1000>;
4317 status = "dis 4317 status = "disabled";
4318 }; 4318 };
4319 4319
4320 frame@17429000 { 4320 frame@17429000 {
4321 frame-number 4321 frame-number = <4>;
4322 interrupts = 4322 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
4323 reg = <0x1742 4323 reg = <0x17429000 0x1000>;
4324 status = "dis 4324 status = "disabled";
4325 }; 4325 };
4326 4326
4327 frame@1742b000 { 4327 frame@1742b000 {
4328 frame-number 4328 frame-number = <5>;
4329 interrupts = 4329 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
4330 reg = <0x1742 4330 reg = <0x1742b000 0x1000>;
4331 status = "dis 4331 status = "disabled";
4332 }; 4332 };
4333 4333
4334 frame@1742d000 { 4334 frame@1742d000 {
4335 frame-number 4335 frame-number = <6>;
4336 interrupts = 4336 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
4337 reg = <0x1742 4337 reg = <0x1742d000 0x1000>;
4338 status = "dis 4338 status = "disabled";
4339 }; 4339 };
4340 }; 4340 };
4341 4341
4342 apps_rsc: rsc@17a00000 { 4342 apps_rsc: rsc@17a00000 {
4343 label = "apps_rsc"; 4343 label = "apps_rsc";
4344 compatible = "qcom,rp 4344 compatible = "qcom,rpmh-rsc";
4345 reg = <0x0 0x17a00000 4345 reg = <0x0 0x17a00000 0x0 0x10000>,
4346 <0x0 0x17a10000 4346 <0x0 0x17a10000 0x0 0x10000>,
4347 <0x0 0x17a20000 4347 <0x0 0x17a20000 0x0 0x10000>,
4348 <0x0 0x17a30000 4348 <0x0 0x17a30000 0x0 0x10000>;
4349 reg-names = "drv-0", 4349 reg-names = "drv-0", "drv-1", "drv-2", "drv-3";
4350 interrupts = <GIC_SPI 4350 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
4351 <GIC_SPI 4351 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
4352 <GIC_SPI 4352 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
4353 qcom,tcs-offset = <0x 4353 qcom,tcs-offset = <0xd00>;
4354 qcom,drv-id = <2>; 4354 qcom,drv-id = <2>;
4355 qcom,tcs-config = <AC 4355 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
4356 <WA 4356 <WAKE_TCS 2>, <CONTROL_TCS 0>;
4357 power-domains = <&CLU 4357 power-domains = <&CLUSTER_PD>;
4358 4358
4359 apps_bcm_voter: bcm-v 4359 apps_bcm_voter: bcm-voter {
4360 compatible = 4360 compatible = "qcom,bcm-voter";
4361 }; 4361 };
4362 4362
4363 rpmhcc: clock-control 4363 rpmhcc: clock-controller {
4364 compatible = 4364 compatible = "qcom,sm8450-rpmh-clk";
4365 #clock-cells 4365 #clock-cells = <1>;
4366 clock-names = 4366 clock-names = "xo";
4367 clocks = <&xo 4367 clocks = <&xo_board>;
4368 }; 4368 };
4369 4369
4370 rpmhpd: power-control 4370 rpmhpd: power-controller {
4371 compatible = 4371 compatible = "qcom,sm8450-rpmhpd";
4372 #power-domain 4372 #power-domain-cells = <1>;
4373 operating-poi 4373 operating-points-v2 = <&rpmhpd_opp_table>;
4374 4374
4375 rpmhpd_opp_ta 4375 rpmhpd_opp_table: opp-table {
4376 compa 4376 compatible = "operating-points-v2";
4377 4377
4378 rpmhp 4378 rpmhpd_opp_ret: opp1 {
4379 4379 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4380 }; 4380 };
4381 4381
4382 rpmhp 4382 rpmhpd_opp_min_svs: opp2 {
4383 4383 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4384 }; 4384 };
4385 4385
4386 rpmhp 4386 rpmhpd_opp_low_svs_d1: opp3 {
4387 4387 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
4388 }; 4388 };
4389 4389
4390 rpmhp 4390 rpmhpd_opp_low_svs: opp4 {
4391 4391 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4392 }; 4392 };
4393 4393
4394 rpmhp 4394 rpmhpd_opp_low_svs_l1: opp5 {
4395 4395 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
4396 }; 4396 };
4397 4397
4398 rpmhp 4398 rpmhpd_opp_svs: opp6 {
4399 4399 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4400 }; 4400 };
4401 4401
4402 rpmhp 4402 rpmhpd_opp_svs_l0: opp7 {
4403 4403 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
4404 }; 4404 };
4405 4405
4406 rpmhp 4406 rpmhpd_opp_svs_l1: opp8 {
4407 4407 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4408 }; 4408 };
4409 4409
4410 rpmhp 4410 rpmhpd_opp_svs_l2: opp9 {
4411 4411 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
4412 }; 4412 };
4413 4413
4414 rpmhp 4414 rpmhpd_opp_nom: opp10 {
4415 4415 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4416 }; 4416 };
4417 4417
4418 rpmhp 4418 rpmhpd_opp_nom_l1: opp11 {
4419 4419 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4420 }; 4420 };
4421 4421
4422 rpmhp 4422 rpmhpd_opp_nom_l2: opp12 {
4423 4423 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4424 }; 4424 };
4425 4425
4426 rpmhp 4426 rpmhpd_opp_turbo: opp13 {
4427 4427 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4428 }; 4428 };
4429 4429
4430 rpmhp 4430 rpmhpd_opp_turbo_l1: opp14 {
4431 4431 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4432 }; 4432 };
4433 }; 4433 };
4434 }; 4434 };
4435 }; 4435 };
4436 4436
4437 cpufreq_hw: cpufreq@17d91000 4437 cpufreq_hw: cpufreq@17d91000 {
4438 compatible = "qcom,sm 4438 compatible = "qcom,sm8450-cpufreq-epss", "qcom,cpufreq-epss";
4439 reg = <0 0x17d91000 0 4439 reg = <0 0x17d91000 0 0x1000>,
4440 <0 0x17d92000 0 4440 <0 0x17d92000 0 0x1000>,
4441 <0 0x17d93000 0 4441 <0 0x17d93000 0 0x1000>;
4442 reg-names = "freq-dom 4442 reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
4443 clocks = <&rpmhcc RPM 4443 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
4444 clock-names = "xo", " 4444 clock-names = "xo", "alternate";
4445 interrupts = <GIC_SPI 4445 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
4446 <GIC_SPI 4446 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
4447 <GIC_SPI 4447 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
4448 interrupt-names = "dc 4448 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
4449 #freq-domain-cells = 4449 #freq-domain-cells = <1>;
4450 #clock-cells = <1>; 4450 #clock-cells = <1>;
4451 }; 4451 };
4452 4452
4453 gem_noc: interconnect@1910000 4453 gem_noc: interconnect@19100000 {
4454 compatible = "qcom,sm 4454 compatible = "qcom,sm8450-gem-noc";
4455 reg = <0 0x19100000 0 4455 reg = <0 0x19100000 0 0xbb800>;
4456 #interconnect-cells = 4456 #interconnect-cells = <2>;
4457 qcom,bcm-voters = <&a 4457 qcom,bcm-voters = <&apps_bcm_voter>;
4458 }; 4458 };
4459 4459
4460 system-cache-controller@19200 4460 system-cache-controller@19200000 {
4461 compatible = "qcom,sm 4461 compatible = "qcom,sm8450-llcc";
4462 reg = <0 0x19200000 0 4462 reg = <0 0x19200000 0 0x80000>, <0 0x19600000 0 0x80000>,
4463 <0 0x19300000 0 4463 <0 0x19300000 0 0x80000>, <0 0x19700000 0 0x80000>,
4464 <0 0x19a00000 0 4464 <0 0x19a00000 0 0x80000>, <0 0x19c00000 0 0x80000>;
4465 reg-names = "llcc0_ba 4465 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
4466 "llcc3_ba 4466 "llcc3_base", "llcc_broadcast_base",
4467 "llcc_bro 4467 "llcc_broadcast_and_base";
4468 interrupts = <GIC_SPI 4468 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
4469 }; 4469 };
4470 4470
4471 ufs_mem_hc: ufshc@1d84000 { 4471 ufs_mem_hc: ufshc@1d84000 {
4472 compatible = "qcom,sm 4472 compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
4473 "jedec,u 4473 "jedec,ufs-2.0";
4474 reg = <0 0x01d84000 0 4474 reg = <0 0x01d84000 0 0x3000>;
4475 interrupts = <GIC_SPI 4475 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
4476 phys = <&ufs_mem_phy> 4476 phys = <&ufs_mem_phy>;
4477 phy-names = "ufsphy"; 4477 phy-names = "ufsphy";
4478 lanes-per-direction = 4478 lanes-per-direction = <2>;
4479 #reset-cells = <1>; 4479 #reset-cells = <1>;
4480 resets = <&gcc GCC_UF 4480 resets = <&gcc GCC_UFS_PHY_BCR>;
4481 reset-names = "rst"; 4481 reset-names = "rst";
4482 4482
4483 power-domains = <&gcc 4483 power-domains = <&gcc UFS_PHY_GDSC>;
4484 4484
4485 iommus = <&apps_smmu 4485 iommus = <&apps_smmu 0xe0 0x0>;
4486 dma-coherent; 4486 dma-coherent;
4487 4487
4488 interconnects = <&agg 4488 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>,
4489 <&gem 4489 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
4490 interconnect-names = 4490 interconnect-names = "ufs-ddr", "cpu-ufs";
4491 clock-names = 4491 clock-names =
4492 "core_clk", 4492 "core_clk",
4493 "bus_aggr_clk 4493 "bus_aggr_clk",
4494 "iface_clk", 4494 "iface_clk",
4495 "core_clk_uni 4495 "core_clk_unipro",
4496 "ref_clk", 4496 "ref_clk",
4497 "tx_lane0_syn 4497 "tx_lane0_sync_clk",
4498 "rx_lane0_syn 4498 "rx_lane0_sync_clk",
4499 "rx_lane1_syn 4499 "rx_lane1_sync_clk";
4500 clocks = 4500 clocks =
4501 <&gcc GCC_UFS 4501 <&gcc GCC_UFS_PHY_AXI_CLK>,
4502 <&gcc GCC_AGG 4502 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
4503 <&gcc GCC_UFS 4503 <&gcc GCC_UFS_PHY_AHB_CLK>,
4504 <&gcc GCC_UFS 4504 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
4505 <&rpmhcc RPMH 4505 <&rpmhcc RPMH_CXO_CLK>,
4506 <&gcc GCC_UFS 4506 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
4507 <&gcc GCC_UFS 4507 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
4508 <&gcc GCC_UFS 4508 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
4509 freq-table-hz = 4509 freq-table-hz =
4510 <75000000 300 4510 <75000000 300000000>,
4511 <0 0>, 4511 <0 0>,
4512 <0 0>, 4512 <0 0>,
4513 <75000000 300 4513 <75000000 300000000>,
4514 <75000000 300 4514 <75000000 300000000>,
4515 <0 0>, 4515 <0 0>,
4516 <0 0>, 4516 <0 0>,
4517 <0 0>; 4517 <0 0>;
4518 qcom,ice = <&ice>; 4518 qcom,ice = <&ice>;
4519 4519
4520 status = "disabled"; 4520 status = "disabled";
4521 }; 4521 };
4522 4522
4523 ufs_mem_phy: phy@1d87000 { 4523 ufs_mem_phy: phy@1d87000 {
4524 compatible = "qcom,sm 4524 compatible = "qcom,sm8450-qmp-ufs-phy";
4525 reg = <0 0x01d87000 0 4525 reg = <0 0x01d87000 0 0x1000>;
4526 4526
4527 clock-names = "ref", 4527 clock-names = "ref", "ref_aux", "qref";
4528 clocks = <&rpmhcc RPM 4528 clocks = <&rpmhcc RPMH_CXO_CLK>,
4529 <&gcc GCC_UF 4529 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
4530 <&gcc GCC_UF 4530 <&gcc GCC_UFS_0_CLKREF_EN>;
4531 4531
4532 power-domains = <&gcc 4532 power-domains = <&gcc UFS_PHY_GDSC>;
4533 4533
4534 resets = <&ufs_mem_hc 4534 resets = <&ufs_mem_hc 0>;
4535 reset-names = "ufsphy 4535 reset-names = "ufsphy";
4536 4536
4537 #clock-cells = <1>; 4537 #clock-cells = <1>;
4538 #phy-cells = <0>; 4538 #phy-cells = <0>;
4539 4539
4540 status = "disabled"; 4540 status = "disabled";
4541 }; 4541 };
4542 4542
4543 ice: crypto@1d88000 { 4543 ice: crypto@1d88000 {
4544 compatible = "qcom,sm 4544 compatible = "qcom,sm8450-inline-crypto-engine",
4545 "qcom,in 4545 "qcom,inline-crypto-engine";
4546 reg = <0 0x01d88000 0 4546 reg = <0 0x01d88000 0 0x8000>;
4547 clocks = <&gcc GCC_UF 4547 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
4548 }; 4548 };
4549 4549
4550 cryptobam: dma-controller@1dc 4550 cryptobam: dma-controller@1dc4000 {
4551 compatible = "qcom,ba 4551 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
4552 reg = <0 0x01dc4000 0 4552 reg = <0 0x01dc4000 0 0x28000>;
4553 interrupts = <GIC_SPI 4553 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
4554 #dma-cells = <1>; 4554 #dma-cells = <1>;
4555 qcom,ee = <0>; 4555 qcom,ee = <0>;
4556 qcom,controlled-remot 4556 qcom,controlled-remotely;
4557 iommus = <&apps_smmu 4557 iommus = <&apps_smmu 0x584 0x11>,
4558 <&apps_smmu 4558 <&apps_smmu 0x588 0x0>,
4559 <&apps_smmu 4559 <&apps_smmu 0x598 0x5>,
4560 <&apps_smmu 4560 <&apps_smmu 0x59a 0x0>,
4561 <&apps_smmu 4561 <&apps_smmu 0x59f 0x0>;
4562 }; 4562 };
4563 4563
4564 crypto: crypto@1dfa000 { 4564 crypto: crypto@1dfa000 {
4565 compatible = "qcom,sm 4565 compatible = "qcom,sm8450-qce", "qcom,sm8150-qce", "qcom,qce";
4566 reg = <0 0x01dfa000 0 4566 reg = <0 0x01dfa000 0 0x6000>;
4567 dmas = <&cryptobam 4> 4567 dmas = <&cryptobam 4>, <&cryptobam 5>;
4568 dma-names = "rx", "tx 4568 dma-names = "rx", "tx";
4569 iommus = <&apps_smmu 4569 iommus = <&apps_smmu 0x584 0x11>,
4570 <&apps_smmu 4570 <&apps_smmu 0x588 0x0>,
4571 <&apps_smmu 4571 <&apps_smmu 0x598 0x5>,
4572 <&apps_smmu 4572 <&apps_smmu 0x59a 0x0>,
4573 <&apps_smmu 4573 <&apps_smmu 0x59f 0x0>;
4574 interconnects = <&agg 4574 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
4575 interconnect-names = 4575 interconnect-names = "memory";
4576 }; 4576 };
4577 4577
4578 sdhc_2: mmc@8804000 { 4578 sdhc_2: mmc@8804000 {
4579 compatible = "qcom,sm 4579 compatible = "qcom,sm8450-sdhci", "qcom,sdhci-msm-v5";
4580 reg = <0 0x08804000 0 4580 reg = <0 0x08804000 0 0x1000>;
4581 4581
4582 interrupts = <GIC_SPI 4582 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
4583 <GIC_SPI 4583 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
4584 interrupt-names = "hc 4584 interrupt-names = "hc_irq", "pwr_irq";
4585 4585
4586 clocks = <&gcc GCC_SD 4586 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
4587 <&gcc GCC_SD 4587 <&gcc GCC_SDCC2_APPS_CLK>,
4588 <&rpmhcc RPM 4588 <&rpmhcc RPMH_CXO_CLK>;
4589 clock-names = "iface" 4589 clock-names = "iface", "core", "xo";
4590 resets = <&gcc GCC_SD 4590 resets = <&gcc GCC_SDCC2_BCR>;
4591 interconnects = <&agg 4591 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
4592 <&gem 4592 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
4593 interconnect-names = 4593 interconnect-names = "sdhc-ddr","cpu-sdhc";
4594 iommus = <&apps_smmu 4594 iommus = <&apps_smmu 0x4a0 0x0>;
4595 power-domains = <&rpm 4595 power-domains = <&rpmhpd RPMHPD_CX>;
4596 operating-points-v2 = 4596 operating-points-v2 = <&sdhc2_opp_table>;
4597 bus-width = <4>; 4597 bus-width = <4>;
4598 dma-coherent; 4598 dma-coherent;
4599 4599
4600 /* Forbid SDR104/SDR5 4600 /* Forbid SDR104/SDR50 - broken hw! */
4601 sdhci-caps-mask = <0x 4601 sdhci-caps-mask = <0x3 0x0>;
4602 4602
4603 status = "disabled"; 4603 status = "disabled";
4604 4604
4605 sdhc2_opp_table: opp- 4605 sdhc2_opp_table: opp-table {
4606 compatible = 4606 compatible = "operating-points-v2";
4607 4607
4608 opp-100000000 4608 opp-100000000 {
4609 opp-h 4609 opp-hz = /bits/ 64 <100000000>;
4610 requi 4610 required-opps = <&rpmhpd_opp_low_svs>;
4611 }; 4611 };
4612 4612
4613 opp-202000000 4613 opp-202000000 {
4614 opp-h 4614 opp-hz = /bits/ 64 <202000000>;
4615 requi 4615 required-opps = <&rpmhpd_opp_svs_l1>;
4616 }; 4616 };
4617 }; 4617 };
4618 }; 4618 };
4619 4619
4620 usb_1: usb@a6f8800 { 4620 usb_1: usb@a6f8800 {
4621 compatible = "qcom,sm 4621 compatible = "qcom,sm8450-dwc3", "qcom,dwc3";
4622 reg = <0 0x0a6f8800 0 4622 reg = <0 0x0a6f8800 0 0x400>;
4623 status = "disabled"; 4623 status = "disabled";
4624 #address-cells = <2>; 4624 #address-cells = <2>;
4625 #size-cells = <2>; 4625 #size-cells = <2>;
4626 ranges; 4626 ranges;
4627 4627
4628 clocks = <&gcc GCC_CF 4628 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
4629 <&gcc GCC_US 4629 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
4630 <&gcc GCC_AG 4630 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
4631 <&gcc GCC_US 4631 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
4632 <&gcc GCC_US 4632 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4633 <&gcc GCC_US 4633 <&gcc GCC_USB3_0_CLKREF_EN>;
4634 clock-names = "cfg_no 4634 clock-names = "cfg_noc",
4635 "core", 4635 "core",
4636 "iface" 4636 "iface",
4637 "sleep" 4637 "sleep",
4638 "mock_u 4638 "mock_utmi",
4639 "xo"; 4639 "xo";
4640 4640
4641 assigned-clocks = <&g 4641 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4642 <&g 4642 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
4643 assigned-clock-rates 4643 assigned-clock-rates = <19200000>, <200000000>;
4644 4644
4645 interrupts-extended = 4645 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
4646 4646 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
4647 4647 <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
4648 4648 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
4649 4649 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
4650 interrupt-names = "pw 4650 interrupt-names = "pwr_event",
4651 "hs 4651 "hs_phy_irq",
4652 "dp 4652 "dp_hs_phy_irq",
4653 "dm 4653 "dm_hs_phy_irq",
4654 "ss 4654 "ss_phy_irq";
4655 4655
4656 power-domains = <&gcc 4656 power-domains = <&gcc USB30_PRIM_GDSC>;
4657 4657
4658 resets = <&gcc GCC_US 4658 resets = <&gcc GCC_USB30_PRIM_BCR>;
4659 4659
4660 interconnects = <&agg 4660 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
4661 <&gem 4661 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
4662 interconnect-names = 4662 interconnect-names = "usb-ddr", "apps-usb";
4663 4663
4664 usb_1_dwc3: usb@a6000 4664 usb_1_dwc3: usb@a600000 {
4665 compatible = 4665 compatible = "snps,dwc3";
4666 reg = <0 0x0a 4666 reg = <0 0x0a600000 0 0xcd00>;
4667 interrupts = 4667 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
4668 iommus = <&ap 4668 iommus = <&apps_smmu 0x0 0x0>;
4669 snps,dis_u2_s 4669 snps,dis_u2_susphy_quirk;
4670 snps,dis_enbl 4670 snps,dis_enblslpm_quirk;
4671 phys = <&usb_ 4671 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
4672 phy-names = " 4672 phy-names = "usb2-phy", "usb3-phy";
4673 4673
4674 ports { 4674 ports {
4675 #addr 4675 #address-cells = <1>;
4676 #size 4676 #size-cells = <0>;
4677 4677
4678 port@ 4678 port@0 {
4679 4679 reg = <0>;
4680 4680
4681 4681 usb_1_dwc3_hs: endpoint {
4682 4682 };
4683 }; 4683 };
4684 4684
4685 port@ 4685 port@1 {
4686 4686 reg = <1>;
4687 4687
4688 4688 usb_1_dwc3_ss: endpoint {
4689 4689 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>;
4690 4690 };
4691 }; 4691 };
4692 }; 4692 };
4693 }; 4693 };
4694 }; 4694 };
4695 4695
4696 nsp_noc: interconnect@320c000 4696 nsp_noc: interconnect@320c0000 {
4697 compatible = "qcom,sm 4697 compatible = "qcom,sm8450-nsp-noc";
4698 reg = <0 0x320c0000 0 4698 reg = <0 0x320c0000 0 0x10000>;
4699 #interconnect-cells = 4699 #interconnect-cells = <2>;
4700 qcom,bcm-voters = <&a 4700 qcom,bcm-voters = <&apps_bcm_voter>;
4701 }; 4701 };
4702 4702
4703 lpass_ag_noc: interconnect@3c 4703 lpass_ag_noc: interconnect@3c40000 {
4704 compatible = "qcom,sm 4704 compatible = "qcom,sm8450-lpass-ag-noc";
4705 reg = <0 0x03c40000 0 4705 reg = <0 0x03c40000 0 0x17200>;
4706 #interconnect-cells = 4706 #interconnect-cells = <2>;
4707 qcom,bcm-voters = <&a 4707 qcom,bcm-voters = <&apps_bcm_voter>;
4708 }; 4708 };
4709 }; 4709 };
4710 4710
4711 sound: sound { 4711 sound: sound {
4712 }; 4712 };
4713 4713
4714 thermal-zones { 4714 thermal-zones {
4715 aoss0-thermal { 4715 aoss0-thermal {
4716 thermal-sensors = <&t 4716 thermal-sensors = <&tsens0 0>;
4717 4717
4718 trips { 4718 trips {
4719 thermal-engin 4719 thermal-engine-config {
4720 tempe 4720 temperature = <125000>;
4721 hyste 4721 hysteresis = <1000>;
4722 type 4722 type = "passive";
4723 }; 4723 };
4724 4724
4725 reset-mon-cfg 4725 reset-mon-cfg {
4726 tempe 4726 temperature = <115000>;
4727 hyste 4727 hysteresis = <5000>;
4728 type 4728 type = "passive";
4729 }; 4729 };
4730 }; 4730 };
4731 }; 4731 };
4732 4732
4733 cpuss0-thermal { 4733 cpuss0-thermal {
4734 thermal-sensors = <&t 4734 thermal-sensors = <&tsens0 1>;
4735 4735
4736 trips { 4736 trips {
4737 thermal-engin 4737 thermal-engine-config {
4738 tempe 4738 temperature = <125000>;
4739 hyste 4739 hysteresis = <1000>;
4740 type 4740 type = "passive";
4741 }; 4741 };
4742 4742
4743 reset-mon-cfg 4743 reset-mon-cfg {
4744 tempe 4744 temperature = <115000>;
4745 hyste 4745 hysteresis = <5000>;
4746 type 4746 type = "passive";
4747 }; 4747 };
4748 }; 4748 };
4749 }; 4749 };
4750 4750
4751 cpuss1-thermal { 4751 cpuss1-thermal {
4752 thermal-sensors = <&t 4752 thermal-sensors = <&tsens0 2>;
4753 4753
4754 trips { 4754 trips {
4755 thermal-engin 4755 thermal-engine-config {
4756 tempe 4756 temperature = <125000>;
4757 hyste 4757 hysteresis = <1000>;
4758 type 4758 type = "passive";
4759 }; 4759 };
4760 4760
4761 reset-mon-cfg 4761 reset-mon-cfg {
4762 tempe 4762 temperature = <115000>;
4763 hyste 4763 hysteresis = <5000>;
4764 type 4764 type = "passive";
4765 }; 4765 };
4766 }; 4766 };
4767 }; 4767 };
4768 4768
4769 cpuss3-thermal { 4769 cpuss3-thermal {
4770 thermal-sensors = <&t 4770 thermal-sensors = <&tsens0 3>;
4771 4771
4772 trips { 4772 trips {
4773 thermal-engin 4773 thermal-engine-config {
4774 tempe 4774 temperature = <125000>;
4775 hyste 4775 hysteresis = <1000>;
4776 type 4776 type = "passive";
4777 }; 4777 };
4778 4778
4779 reset-mon-cfg 4779 reset-mon-cfg {
4780 tempe 4780 temperature = <115000>;
4781 hyste 4781 hysteresis = <5000>;
4782 type 4782 type = "passive";
4783 }; 4783 };
4784 }; 4784 };
4785 }; 4785 };
4786 4786
4787 cpuss4-thermal { 4787 cpuss4-thermal {
4788 thermal-sensors = <&t 4788 thermal-sensors = <&tsens0 4>;
4789 4789
4790 trips { 4790 trips {
4791 thermal-engin 4791 thermal-engine-config {
4792 tempe 4792 temperature = <125000>;
4793 hyste 4793 hysteresis = <1000>;
4794 type 4794 type = "passive";
4795 }; 4795 };
4796 4796
4797 reset-mon-cfg 4797 reset-mon-cfg {
4798 tempe 4798 temperature = <115000>;
4799 hyste 4799 hysteresis = <5000>;
4800 type 4800 type = "passive";
4801 }; 4801 };
4802 }; 4802 };
4803 }; 4803 };
4804 4804
4805 cpu4-top-thermal { 4805 cpu4-top-thermal {
4806 thermal-sensors = <&t 4806 thermal-sensors = <&tsens0 5>;
4807 4807
4808 trips { 4808 trips {
4809 cpu4_top_aler 4809 cpu4_top_alert0: trip-point0 {
4810 tempe 4810 temperature = <90000>;
4811 hyste 4811 hysteresis = <2000>;
4812 type 4812 type = "passive";
4813 }; 4813 };
4814 4814
4815 cpu4_top_aler 4815 cpu4_top_alert1: trip-point1 {
4816 tempe 4816 temperature = <95000>;
4817 hyste 4817 hysteresis = <2000>;
4818 type 4818 type = "passive";
4819 }; 4819 };
4820 4820
4821 cpu4_top_crit 4821 cpu4_top_crit: cpu-crit {
4822 tempe 4822 temperature = <110000>;
4823 hyste 4823 hysteresis = <1000>;
4824 type 4824 type = "critical";
4825 }; 4825 };
4826 }; 4826 };
4827 }; 4827 };
4828 4828
4829 cpu4-bottom-thermal { 4829 cpu4-bottom-thermal {
4830 thermal-sensors = <&t 4830 thermal-sensors = <&tsens0 6>;
4831 4831
4832 trips { 4832 trips {
4833 cpu4_bottom_a 4833 cpu4_bottom_alert0: trip-point0 {
4834 tempe 4834 temperature = <90000>;
4835 hyste 4835 hysteresis = <2000>;
4836 type 4836 type = "passive";
4837 }; 4837 };
4838 4838
4839 cpu4_bottom_a 4839 cpu4_bottom_alert1: trip-point1 {
4840 tempe 4840 temperature = <95000>;
4841 hyste 4841 hysteresis = <2000>;
4842 type 4842 type = "passive";
4843 }; 4843 };
4844 4844
4845 cpu4_bottom_c 4845 cpu4_bottom_crit: cpu-crit {
4846 tempe 4846 temperature = <110000>;
4847 hyste 4847 hysteresis = <1000>;
4848 type 4848 type = "critical";
4849 }; 4849 };
4850 }; 4850 };
4851 }; 4851 };
4852 4852
4853 cpu5-top-thermal { 4853 cpu5-top-thermal {
4854 thermal-sensors = <&t 4854 thermal-sensors = <&tsens0 7>;
4855 4855
4856 trips { 4856 trips {
4857 cpu5_top_aler 4857 cpu5_top_alert0: trip-point0 {
4858 tempe 4858 temperature = <90000>;
4859 hyste 4859 hysteresis = <2000>;
4860 type 4860 type = "passive";
4861 }; 4861 };
4862 4862
4863 cpu5_top_aler 4863 cpu5_top_alert1: trip-point1 {
4864 tempe 4864 temperature = <95000>;
4865 hyste 4865 hysteresis = <2000>;
4866 type 4866 type = "passive";
4867 }; 4867 };
4868 4868
4869 cpu5_top_crit 4869 cpu5_top_crit: cpu-crit {
4870 tempe 4870 temperature = <110000>;
4871 hyste 4871 hysteresis = <1000>;
4872 type 4872 type = "critical";
4873 }; 4873 };
4874 }; 4874 };
4875 }; 4875 };
4876 4876
4877 cpu5-bottom-thermal { 4877 cpu5-bottom-thermal {
4878 thermal-sensors = <&t 4878 thermal-sensors = <&tsens0 8>;
4879 4879
4880 trips { 4880 trips {
4881 cpu5_bottom_a 4881 cpu5_bottom_alert0: trip-point0 {
4882 tempe 4882 temperature = <90000>;
4883 hyste 4883 hysteresis = <2000>;
4884 type 4884 type = "passive";
4885 }; 4885 };
4886 4886
4887 cpu5_bottom_a 4887 cpu5_bottom_alert1: trip-point1 {
4888 tempe 4888 temperature = <95000>;
4889 hyste 4889 hysteresis = <2000>;
4890 type 4890 type = "passive";
4891 }; 4891 };
4892 4892
4893 cpu5_bottom_c 4893 cpu5_bottom_crit: cpu-crit {
4894 tempe 4894 temperature = <110000>;
4895 hyste 4895 hysteresis = <1000>;
4896 type 4896 type = "critical";
4897 }; 4897 };
4898 }; 4898 };
4899 }; 4899 };
4900 4900
4901 cpu6-top-thermal { 4901 cpu6-top-thermal {
4902 thermal-sensors = <&t 4902 thermal-sensors = <&tsens0 9>;
4903 4903
4904 trips { 4904 trips {
4905 cpu6_top_aler 4905 cpu6_top_alert0: trip-point0 {
4906 tempe 4906 temperature = <90000>;
4907 hyste 4907 hysteresis = <2000>;
4908 type 4908 type = "passive";
4909 }; 4909 };
4910 4910
4911 cpu6_top_aler 4911 cpu6_top_alert1: trip-point1 {
4912 tempe 4912 temperature = <95000>;
4913 hyste 4913 hysteresis = <2000>;
4914 type 4914 type = "passive";
4915 }; 4915 };
4916 4916
4917 cpu6_top_crit 4917 cpu6_top_crit: cpu-crit {
4918 tempe 4918 temperature = <110000>;
4919 hyste 4919 hysteresis = <1000>;
4920 type 4920 type = "critical";
4921 }; 4921 };
4922 }; 4922 };
4923 }; 4923 };
4924 4924
4925 cpu6-bottom-thermal { 4925 cpu6-bottom-thermal {
4926 thermal-sensors = <&t 4926 thermal-sensors = <&tsens0 10>;
4927 4927
4928 trips { 4928 trips {
4929 cpu6_bottom_a 4929 cpu6_bottom_alert0: trip-point0 {
4930 tempe 4930 temperature = <90000>;
4931 hyste 4931 hysteresis = <2000>;
4932 type 4932 type = "passive";
4933 }; 4933 };
4934 4934
4935 cpu6_bottom_a 4935 cpu6_bottom_alert1: trip-point1 {
4936 tempe 4936 temperature = <95000>;
4937 hyste 4937 hysteresis = <2000>;
4938 type 4938 type = "passive";
4939 }; 4939 };
4940 4940
4941 cpu6_bottom_c 4941 cpu6_bottom_crit: cpu-crit {
4942 tempe 4942 temperature = <110000>;
4943 hyste 4943 hysteresis = <1000>;
4944 type 4944 type = "critical";
4945 }; 4945 };
4946 }; 4946 };
4947 }; 4947 };
4948 4948
4949 cpu7-top-thermal { 4949 cpu7-top-thermal {
4950 thermal-sensors = <&t 4950 thermal-sensors = <&tsens0 11>;
4951 4951
4952 trips { 4952 trips {
4953 cpu7_top_aler 4953 cpu7_top_alert0: trip-point0 {
4954 tempe 4954 temperature = <90000>;
4955 hyste 4955 hysteresis = <2000>;
4956 type 4956 type = "passive";
4957 }; 4957 };
4958 4958
4959 cpu7_top_aler 4959 cpu7_top_alert1: trip-point1 {
4960 tempe 4960 temperature = <95000>;
4961 hyste 4961 hysteresis = <2000>;
4962 type 4962 type = "passive";
4963 }; 4963 };
4964 4964
4965 cpu7_top_crit 4965 cpu7_top_crit: cpu-crit {
4966 tempe 4966 temperature = <110000>;
4967 hyste 4967 hysteresis = <1000>;
4968 type 4968 type = "critical";
4969 }; 4969 };
4970 }; 4970 };
4971 }; 4971 };
4972 4972
4973 cpu7-middle-thermal { 4973 cpu7-middle-thermal {
4974 thermal-sensors = <&t 4974 thermal-sensors = <&tsens0 12>;
4975 4975
4976 trips { 4976 trips {
4977 cpu7_middle_a 4977 cpu7_middle_alert0: trip-point0 {
4978 tempe 4978 temperature = <90000>;
4979 hyste 4979 hysteresis = <2000>;
4980 type 4980 type = "passive";
4981 }; 4981 };
4982 4982
4983 cpu7_middle_a 4983 cpu7_middle_alert1: trip-point1 {
4984 tempe 4984 temperature = <95000>;
4985 hyste 4985 hysteresis = <2000>;
4986 type 4986 type = "passive";
4987 }; 4987 };
4988 4988
4989 cpu7_middle_c 4989 cpu7_middle_crit: cpu-crit {
4990 tempe 4990 temperature = <110000>;
4991 hyste 4991 hysteresis = <1000>;
4992 type 4992 type = "critical";
4993 }; 4993 };
4994 }; 4994 };
4995 }; 4995 };
4996 4996
4997 cpu7-bottom-thermal { 4997 cpu7-bottom-thermal {
4998 thermal-sensors = <&t 4998 thermal-sensors = <&tsens0 13>;
4999 4999
5000 trips { 5000 trips {
5001 cpu7_bottom_a 5001 cpu7_bottom_alert0: trip-point0 {
5002 tempe 5002 temperature = <90000>;
5003 hyste 5003 hysteresis = <2000>;
5004 type 5004 type = "passive";
5005 }; 5005 };
5006 5006
5007 cpu7_bottom_a 5007 cpu7_bottom_alert1: trip-point1 {
5008 tempe 5008 temperature = <95000>;
5009 hyste 5009 hysteresis = <2000>;
5010 type 5010 type = "passive";
5011 }; 5011 };
5012 5012
5013 cpu7_bottom_c 5013 cpu7_bottom_crit: cpu-crit {
5014 tempe 5014 temperature = <110000>;
5015 hyste 5015 hysteresis = <1000>;
5016 type 5016 type = "critical";
5017 }; 5017 };
5018 }; 5018 };
5019 }; 5019 };
5020 5020
5021 gpu-top-thermal { 5021 gpu-top-thermal {
5022 polling-delay-passive 5022 polling-delay-passive = <10>;
5023 5023
5024 thermal-sensors = <&t 5024 thermal-sensors = <&tsens0 14>;
5025 5025
5026 cooling-maps { 5026 cooling-maps {
5027 map0 { 5027 map0 {
5028 trip 5028 trip = <&gpu_top_alert0>;
5029 cooli 5029 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5030 }; 5030 };
5031 }; 5031 };
5032 5032
5033 trips { 5033 trips {
5034 gpu_top_alert 5034 gpu_top_alert0: trip-point0 {
5035 tempe 5035 temperature = <85000>;
5036 hyste 5036 hysteresis = <1000>;
5037 type 5037 type = "passive";
5038 }; 5038 };
5039 5039
5040 trip-point1 { 5040 trip-point1 {
5041 tempe 5041 temperature = <90000>;
5042 hyste 5042 hysteresis = <1000>;
5043 type 5043 type = "hot";
5044 }; 5044 };
5045 5045
5046 trip-point2 { 5046 trip-point2 {
5047 tempe 5047 temperature = <110000>;
5048 hyste 5048 hysteresis = <1000>;
5049 type 5049 type = "critical";
5050 }; 5050 };
5051 }; 5051 };
5052 }; 5052 };
5053 5053
5054 gpu-bottom-thermal { 5054 gpu-bottom-thermal {
5055 polling-delay-passive 5055 polling-delay-passive = <10>;
5056 5056
5057 thermal-sensors = <&t 5057 thermal-sensors = <&tsens0 15>;
5058 5058
5059 cooling-maps { 5059 cooling-maps {
5060 map0 { 5060 map0 {
5061 trip 5061 trip = <&gpu_bottom_alert0>;
5062 cooli 5062 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5063 }; 5063 };
5064 }; 5064 };
5065 5065
5066 trips { 5066 trips {
5067 gpu_bottom_al 5067 gpu_bottom_alert0: trip-point0 {
5068 tempe 5068 temperature = <85000>;
5069 hyste 5069 hysteresis = <1000>;
5070 type 5070 type = "passive";
5071 }; 5071 };
5072 5072
5073 trip-point1 { 5073 trip-point1 {
5074 tempe 5074 temperature = <90000>;
5075 hyste 5075 hysteresis = <1000>;
5076 type 5076 type = "hot";
5077 }; 5077 };
5078 5078
5079 trip-point2 { 5079 trip-point2 {
5080 tempe 5080 temperature = <110000>;
5081 hyste 5081 hysteresis = <1000>;
5082 type 5082 type = "critical";
5083 }; 5083 };
5084 }; 5084 };
5085 }; 5085 };
5086 5086
5087 aoss1-thermal { 5087 aoss1-thermal {
5088 thermal-sensors = <&t 5088 thermal-sensors = <&tsens1 0>;
5089 5089
5090 trips { 5090 trips {
5091 thermal-engin 5091 thermal-engine-config {
5092 tempe 5092 temperature = <125000>;
5093 hyste 5093 hysteresis = <1000>;
5094 type 5094 type = "passive";
5095 }; 5095 };
5096 5096
5097 reset-mon-cfg 5097 reset-mon-cfg {
5098 tempe 5098 temperature = <115000>;
5099 hyste 5099 hysteresis = <5000>;
5100 type 5100 type = "passive";
5101 }; 5101 };
5102 }; 5102 };
5103 }; 5103 };
5104 5104
5105 cpu0-thermal { 5105 cpu0-thermal {
5106 thermal-sensors = <&t 5106 thermal-sensors = <&tsens1 1>;
5107 5107
5108 trips { 5108 trips {
5109 cpu0_alert0: 5109 cpu0_alert0: trip-point0 {
5110 tempe 5110 temperature = <90000>;
5111 hyste 5111 hysteresis = <2000>;
5112 type 5112 type = "passive";
5113 }; 5113 };
5114 5114
5115 cpu0_alert1: 5115 cpu0_alert1: trip-point1 {
5116 tempe 5116 temperature = <95000>;
5117 hyste 5117 hysteresis = <2000>;
5118 type 5118 type = "passive";
5119 }; 5119 };
5120 5120
5121 cpu0_crit: cp 5121 cpu0_crit: cpu-crit {
5122 tempe 5122 temperature = <110000>;
5123 hyste 5123 hysteresis = <1000>;
5124 type 5124 type = "critical";
5125 }; 5125 };
5126 }; 5126 };
5127 }; 5127 };
5128 5128
5129 cpu1-thermal { 5129 cpu1-thermal {
5130 thermal-sensors = <&t 5130 thermal-sensors = <&tsens1 2>;
5131 5131
5132 trips { 5132 trips {
5133 cpu1_alert0: 5133 cpu1_alert0: trip-point0 {
5134 tempe 5134 temperature = <90000>;
5135 hyste 5135 hysteresis = <2000>;
5136 type 5136 type = "passive";
5137 }; 5137 };
5138 5138
5139 cpu1_alert1: 5139 cpu1_alert1: trip-point1 {
5140 tempe 5140 temperature = <95000>;
5141 hyste 5141 hysteresis = <2000>;
5142 type 5142 type = "passive";
5143 }; 5143 };
5144 5144
5145 cpu1_crit: cp 5145 cpu1_crit: cpu-crit {
5146 tempe 5146 temperature = <110000>;
5147 hyste 5147 hysteresis = <1000>;
5148 type 5148 type = "critical";
5149 }; 5149 };
5150 }; 5150 };
5151 }; 5151 };
5152 5152
5153 cpu2-thermal { 5153 cpu2-thermal {
5154 thermal-sensors = <&t 5154 thermal-sensors = <&tsens1 3>;
5155 5155
5156 trips { 5156 trips {
5157 cpu2_alert0: 5157 cpu2_alert0: trip-point0 {
5158 tempe 5158 temperature = <90000>;
5159 hyste 5159 hysteresis = <2000>;
5160 type 5160 type = "passive";
5161 }; 5161 };
5162 5162
5163 cpu2_alert1: 5163 cpu2_alert1: trip-point1 {
5164 tempe 5164 temperature = <95000>;
5165 hyste 5165 hysteresis = <2000>;
5166 type 5166 type = "passive";
5167 }; 5167 };
5168 5168
5169 cpu2_crit: cp 5169 cpu2_crit: cpu-crit {
5170 tempe 5170 temperature = <110000>;
5171 hyste 5171 hysteresis = <1000>;
5172 type 5172 type = "critical";
5173 }; 5173 };
5174 }; 5174 };
5175 }; 5175 };
5176 5176
5177 cpu3-thermal { 5177 cpu3-thermal {
5178 thermal-sensors = <&t 5178 thermal-sensors = <&tsens1 4>;
5179 5179
5180 trips { 5180 trips {
5181 cpu3_alert0: 5181 cpu3_alert0: trip-point0 {
5182 tempe 5182 temperature = <90000>;
5183 hyste 5183 hysteresis = <2000>;
5184 type 5184 type = "passive";
5185 }; 5185 };
5186 5186
5187 cpu3_alert1: 5187 cpu3_alert1: trip-point1 {
5188 tempe 5188 temperature = <95000>;
5189 hyste 5189 hysteresis = <2000>;
5190 type 5190 type = "passive";
5191 }; 5191 };
5192 5192
5193 cpu3_crit: cp 5193 cpu3_crit: cpu-crit {
5194 tempe 5194 temperature = <110000>;
5195 hyste 5195 hysteresis = <1000>;
5196 type 5196 type = "critical";
5197 }; 5197 };
5198 }; 5198 };
5199 }; 5199 };
5200 5200
5201 cdsp0-thermal { 5201 cdsp0-thermal {
5202 polling-delay-passive 5202 polling-delay-passive = <10>;
5203 5203
5204 thermal-sensors = <&t 5204 thermal-sensors = <&tsens1 5>;
5205 5205
5206 trips { 5206 trips {
5207 thermal-engin 5207 thermal-engine-config {
5208 tempe 5208 temperature = <125000>;
5209 hyste 5209 hysteresis = <1000>;
5210 type 5210 type = "passive";
5211 }; 5211 };
5212 5212
5213 thermal-hal-c 5213 thermal-hal-config {
5214 tempe 5214 temperature = <125000>;
5215 hyste 5215 hysteresis = <1000>;
5216 type 5216 type = "passive";
5217 }; 5217 };
5218 5218
5219 reset-mon-cfg 5219 reset-mon-cfg {
5220 tempe 5220 temperature = <115000>;
5221 hyste 5221 hysteresis = <5000>;
5222 type 5222 type = "passive";
5223 }; 5223 };
5224 5224
5225 cdsp_0_config 5225 cdsp_0_config: junction-config {
5226 tempe 5226 temperature = <95000>;
5227 hyste 5227 hysteresis = <5000>;
5228 type 5228 type = "passive";
5229 }; 5229 };
5230 }; 5230 };
5231 }; 5231 };
5232 5232
5233 cdsp1-thermal { 5233 cdsp1-thermal {
5234 polling-delay-passive 5234 polling-delay-passive = <10>;
5235 5235
5236 thermal-sensors = <&t 5236 thermal-sensors = <&tsens1 6>;
5237 5237
5238 trips { 5238 trips {
5239 thermal-engin 5239 thermal-engine-config {
5240 tempe 5240 temperature = <125000>;
5241 hyste 5241 hysteresis = <1000>;
5242 type 5242 type = "passive";
5243 }; 5243 };
5244 5244
5245 thermal-hal-c 5245 thermal-hal-config {
5246 tempe 5246 temperature = <125000>;
5247 hyste 5247 hysteresis = <1000>;
5248 type 5248 type = "passive";
5249 }; 5249 };
5250 5250
5251 reset-mon-cfg 5251 reset-mon-cfg {
5252 tempe 5252 temperature = <115000>;
5253 hyste 5253 hysteresis = <5000>;
5254 type 5254 type = "passive";
5255 }; 5255 };
5256 5256
5257 cdsp_1_config 5257 cdsp_1_config: junction-config {
5258 tempe 5258 temperature = <95000>;
5259 hyste 5259 hysteresis = <5000>;
5260 type 5260 type = "passive";
5261 }; 5261 };
5262 }; 5262 };
5263 }; 5263 };
5264 5264
5265 cdsp2-thermal { 5265 cdsp2-thermal {
5266 polling-delay-passive 5266 polling-delay-passive = <10>;
5267 5267
5268 thermal-sensors = <&t 5268 thermal-sensors = <&tsens1 7>;
5269 5269
5270 trips { 5270 trips {
5271 thermal-engin 5271 thermal-engine-config {
5272 tempe 5272 temperature = <125000>;
5273 hyste 5273 hysteresis = <1000>;
5274 type 5274 type = "passive";
5275 }; 5275 };
5276 5276
5277 thermal-hal-c 5277 thermal-hal-config {
5278 tempe 5278 temperature = <125000>;
5279 hyste 5279 hysteresis = <1000>;
5280 type 5280 type = "passive";
5281 }; 5281 };
5282 5282
5283 reset-mon-cfg 5283 reset-mon-cfg {
5284 tempe 5284 temperature = <115000>;
5285 hyste 5285 hysteresis = <5000>;
5286 type 5286 type = "passive";
5287 }; 5287 };
5288 5288
5289 cdsp_2_config 5289 cdsp_2_config: junction-config {
5290 tempe 5290 temperature = <95000>;
5291 hyste 5291 hysteresis = <5000>;
5292 type 5292 type = "passive";
5293 }; 5293 };
5294 }; 5294 };
5295 }; 5295 };
5296 5296
5297 video-thermal { 5297 video-thermal {
5298 thermal-sensors = <&t 5298 thermal-sensors = <&tsens1 8>;
5299 5299
5300 trips { 5300 trips {
5301 thermal-engin 5301 thermal-engine-config {
5302 tempe 5302 temperature = <125000>;
5303 hyste 5303 hysteresis = <1000>;
5304 type 5304 type = "passive";
5305 }; 5305 };
5306 5306
5307 reset-mon-cfg 5307 reset-mon-cfg {
5308 tempe 5308 temperature = <115000>;
5309 hyste 5309 hysteresis = <5000>;
5310 type 5310 type = "passive";
5311 }; 5311 };
5312 }; 5312 };
5313 }; 5313 };
5314 5314
5315 mem-thermal { 5315 mem-thermal {
5316 polling-delay-passive 5316 polling-delay-passive = <10>;
5317 5317
5318 thermal-sensors = <&t 5318 thermal-sensors = <&tsens1 9>;
5319 5319
5320 trips { 5320 trips {
5321 thermal-engin 5321 thermal-engine-config {
5322 tempe 5322 temperature = <125000>;
5323 hyste 5323 hysteresis = <1000>;
5324 type 5324 type = "passive";
5325 }; 5325 };
5326 5326
5327 ddr_config0: 5327 ddr_config0: ddr0-config {
5328 tempe 5328 temperature = <90000>;
5329 hyste 5329 hysteresis = <5000>;
5330 type 5330 type = "passive";
5331 }; 5331 };
5332 5332
5333 reset-mon-cfg 5333 reset-mon-cfg {
5334 tempe 5334 temperature = <115000>;
5335 hyste 5335 hysteresis = <5000>;
5336 type 5336 type = "passive";
5337 }; 5337 };
5338 }; 5338 };
5339 }; 5339 };
5340 5340
5341 modem0-thermal { 5341 modem0-thermal {
5342 thermal-sensors = <&t 5342 thermal-sensors = <&tsens1 10>;
5343 5343
5344 trips { 5344 trips {
5345 thermal-engin 5345 thermal-engine-config {
5346 tempe 5346 temperature = <125000>;
5347 hyste 5347 hysteresis = <1000>;
5348 type 5348 type = "passive";
5349 }; 5349 };
5350 5350
5351 mdmss0_config 5351 mdmss0_config0: mdmss0-config0 {
5352 tempe 5352 temperature = <102000>;
5353 hyste 5353 hysteresis = <3000>;
5354 type 5354 type = "passive";
5355 }; 5355 };
5356 5356
5357 mdmss0_config 5357 mdmss0_config1: mdmss0-config1 {
5358 tempe 5358 temperature = <105000>;
5359 hyste 5359 hysteresis = <3000>;
5360 type 5360 type = "passive";
5361 }; 5361 };
5362 5362
5363 reset-mon-cfg 5363 reset-mon-cfg {
5364 tempe 5364 temperature = <115000>;
5365 hyste 5365 hysteresis = <5000>;
5366 type 5366 type = "passive";
5367 }; 5367 };
5368 }; 5368 };
5369 }; 5369 };
5370 5370
5371 modem1-thermal { 5371 modem1-thermal {
5372 thermal-sensors = <&t 5372 thermal-sensors = <&tsens1 11>;
5373 5373
5374 trips { 5374 trips {
5375 thermal-engin 5375 thermal-engine-config {
5376 tempe 5376 temperature = <125000>;
5377 hyste 5377 hysteresis = <1000>;
5378 type 5378 type = "passive";
5379 }; 5379 };
5380 5380
5381 mdmss1_config 5381 mdmss1_config0: mdmss1-config0 {
5382 tempe 5382 temperature = <102000>;
5383 hyste 5383 hysteresis = <3000>;
5384 type 5384 type = "passive";
5385 }; 5385 };
5386 5386
5387 mdmss1_config 5387 mdmss1_config1: mdmss1-config1 {
5388 tempe 5388 temperature = <105000>;
5389 hyste 5389 hysteresis = <3000>;
5390 type 5390 type = "passive";
5391 }; 5391 };
5392 5392
5393 reset-mon-cfg 5393 reset-mon-cfg {
5394 tempe 5394 temperature = <115000>;
5395 hyste 5395 hysteresis = <5000>;
5396 type 5396 type = "passive";
5397 }; 5397 };
5398 }; 5398 };
5399 }; 5399 };
5400 5400
5401 modem2-thermal { 5401 modem2-thermal {
5402 thermal-sensors = <&t 5402 thermal-sensors = <&tsens1 12>;
5403 5403
5404 trips { 5404 trips {
5405 thermal-engin 5405 thermal-engine-config {
5406 tempe 5406 temperature = <125000>;
5407 hyste 5407 hysteresis = <1000>;
5408 type 5408 type = "passive";
5409 }; 5409 };
5410 5410
5411 mdmss2_config 5411 mdmss2_config0: mdmss2-config0 {
5412 tempe 5412 temperature = <102000>;
5413 hyste 5413 hysteresis = <3000>;
5414 type 5414 type = "passive";
5415 }; 5415 };
5416 5416
5417 mdmss2_config 5417 mdmss2_config1: mdmss2-config1 {
5418 tempe 5418 temperature = <105000>;
5419 hyste 5419 hysteresis = <3000>;
5420 type 5420 type = "passive";
5421 }; 5421 };
5422 5422
5423 reset-mon-cfg 5423 reset-mon-cfg {
5424 tempe 5424 temperature = <115000>;
5425 hyste 5425 hysteresis = <5000>;
5426 type 5426 type = "passive";
5427 }; 5427 };
5428 }; 5428 };
5429 }; 5429 };
5430 5430
5431 modem3-thermal { 5431 modem3-thermal {
5432 thermal-sensors = <&t 5432 thermal-sensors = <&tsens1 13>;
5433 5433
5434 trips { 5434 trips {
5435 thermal-engin 5435 thermal-engine-config {
5436 tempe 5436 temperature = <125000>;
5437 hyste 5437 hysteresis = <1000>;
5438 type 5438 type = "passive";
5439 }; 5439 };
5440 5440
5441 mdmss3_config 5441 mdmss3_config0: mdmss3-config0 {
5442 tempe 5442 temperature = <102000>;
5443 hyste 5443 hysteresis = <3000>;
5444 type 5444 type = "passive";
5445 }; 5445 };
5446 5446
5447 mdmss3_config 5447 mdmss3_config1: mdmss3-config1 {
5448 tempe 5448 temperature = <105000>;
5449 hyste 5449 hysteresis = <3000>;
5450 type 5450 type = "passive";
5451 }; 5451 };
5452 5452
5453 reset-mon-cfg 5453 reset-mon-cfg {
5454 tempe 5454 temperature = <115000>;
5455 hyste 5455 hysteresis = <5000>;
5456 type 5456 type = "passive";
5457 }; 5457 };
5458 }; 5458 };
5459 }; 5459 };
5460 5460
5461 camera0-thermal { 5461 camera0-thermal {
5462 thermal-sensors = <&t 5462 thermal-sensors = <&tsens1 14>;
5463 5463
5464 trips { 5464 trips {
5465 thermal-engin 5465 thermal-engine-config {
5466 tempe 5466 temperature = <125000>;
5467 hyste 5467 hysteresis = <1000>;
5468 type 5468 type = "passive";
5469 }; 5469 };
5470 5470
5471 reset-mon-cfg 5471 reset-mon-cfg {
5472 tempe 5472 temperature = <115000>;
5473 hyste 5473 hysteresis = <5000>;
5474 type 5474 type = "passive";
5475 }; 5475 };
5476 }; 5476 };
5477 }; 5477 };
5478 5478
5479 camera1-thermal { 5479 camera1-thermal {
5480 thermal-sensors = <&t 5480 thermal-sensors = <&tsens1 15>;
5481 5481
5482 trips { 5482 trips {
5483 thermal-engin 5483 thermal-engine-config {
5484 tempe 5484 temperature = <125000>;
5485 hyste 5485 hysteresis = <1000>;
5486 type 5486 type = "passive";
5487 }; 5487 };
5488 5488
5489 reset-mon-cfg 5489 reset-mon-cfg {
5490 tempe 5490 temperature = <115000>;
5491 hyste 5491 hysteresis = <5000>;
5492 type 5492 type = "passive";
5493 }; 5493 };
5494 }; 5494 };
5495 }; 5495 };
5496 }; 5496 };
5497 5497
5498 timer { 5498 timer {
5499 compatible = "arm,armv8-timer 5499 compatible = "arm,armv8-timer";
5500 interrupts = <GIC_PPI 13 (GIC 5500 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5501 <GIC_PPI 14 (GIC 5501 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5502 <GIC_PPI 11 (GIC 5502 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5503 <GIC_PPI 10 (GIC 5503 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
5504 clock-frequency = <19200000>; 5504 clock-frequency = <19200000>;
5505 }; 5505 };
5506 }; 5506 };
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