1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * Copyright (c) 2021, Linaro Limited 3 * Copyright (c) 2021, Linaro Limited
4 */ 4 */
5 5
6 #include <dt-bindings/interrupt-controller/arm 6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-sm8450.h> 7 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
8 #include <dt-bindings/clock/qcom,rpmh.h> 8 #include <dt-bindings/clock/qcom,rpmh.h>
9 #include <dt-bindings/clock/qcom,sm8450-camcc. 9 #include <dt-bindings/clock/qcom,sm8450-camcc.h>
10 #include <dt-bindings/clock/qcom,sm8450-dispcc 10 #include <dt-bindings/clock/qcom,sm8450-dispcc.h>
11 #include <dt-bindings/clock/qcom,sm8450-gpucc. <<
12 #include <dt-bindings/clock/qcom,sm8450-videoc <<
13 #include <dt-bindings/dma/qcom-gpi.h> 11 #include <dt-bindings/dma/qcom-gpi.h>
14 #include <dt-bindings/firmware/qcom,scm.h> <<
15 #include <dt-bindings/gpio/gpio.h> 12 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/mailbox/qcom-ipcc.h> 13 #include <dt-bindings/mailbox/qcom-ipcc.h>
17 #include <dt-bindings/phy/phy-qcom-qmp.h> <<
18 #include <dt-bindings/power/qcom,rpmhpd.h> <<
19 #include <dt-bindings/power/qcom-rpmpd.h> 14 #include <dt-bindings/power/qcom-rpmpd.h>
20 #include <dt-bindings/interconnect/qcom,icc.h> <<
21 #include <dt-bindings/interconnect/qcom,sm8450 15 #include <dt-bindings/interconnect/qcom,sm8450.h>
22 #include <dt-bindings/reset/qcom,sm8450-gpucc. <<
23 #include <dt-bindings/soc/qcom,gpr.h> 16 #include <dt-bindings/soc/qcom,gpr.h>
24 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 17 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
25 #include <dt-bindings/sound/qcom,q6dsp-lpass-p 18 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
26 #include <dt-bindings/thermal/thermal.h> 19 #include <dt-bindings/thermal/thermal.h>
27 20
28 / { 21 / {
29 interrupt-parent = <&intc>; 22 interrupt-parent = <&intc>;
30 23
31 #address-cells = <2>; 24 #address-cells = <2>;
32 #size-cells = <2>; 25 #size-cells = <2>;
33 26
34 chosen { }; 27 chosen { };
35 28
36 clocks { 29 clocks {
37 xo_board: xo-board { 30 xo_board: xo-board {
38 compatible = "fixed-cl 31 compatible = "fixed-clock";
39 #clock-cells = <0>; 32 #clock-cells = <0>;
40 clock-frequency = <768 33 clock-frequency = <76800000>;
41 }; 34 };
42 35
43 sleep_clk: sleep-clk { 36 sleep_clk: sleep-clk {
44 compatible = "fixed-cl 37 compatible = "fixed-clock";
45 #clock-cells = <0>; 38 #clock-cells = <0>;
46 clock-frequency = <320 39 clock-frequency = <32000>;
47 }; 40 };
48 }; 41 };
49 42
50 cpus { 43 cpus {
51 #address-cells = <2>; 44 #address-cells = <2>;
52 #size-cells = <0>; 45 #size-cells = <0>;
53 46
54 CPU0: cpu@0 { 47 CPU0: cpu@0 {
55 device_type = "cpu"; 48 device_type = "cpu";
56 compatible = "qcom,kry 49 compatible = "qcom,kryo780";
57 reg = <0x0 0x0>; 50 reg = <0x0 0x0>;
58 enable-method = "psci" 51 enable-method = "psci";
59 next-level-cache = <&L 52 next-level-cache = <&L2_0>;
60 power-domains = <&CPU_ 53 power-domains = <&CPU_PD0>;
61 power-domain-names = " 54 power-domain-names = "psci";
62 qcom,freq-domain = <&c 55 qcom,freq-domain = <&cpufreq_hw 0>;
63 #cooling-cells = <2>; 56 #cooling-cells = <2>;
64 clocks = <&cpufreq_hw 57 clocks = <&cpufreq_hw 0>;
65 L2_0: l2-cache { 58 L2_0: l2-cache {
66 compatible = " !! 59 compatible = "cache";
67 cache-level = !! 60 cache-level = <2>;
68 cache-unified; !! 61 next-level-cache = <&L3_0>;
69 next-level-cac <<
70 L3_0: l3-cache 62 L3_0: l3-cache {
71 compat !! 63 compatible = "cache";
72 cache- !! 64 cache-level = <3>;
73 cache- <<
74 }; 65 };
75 }; 66 };
76 }; 67 };
77 68
78 CPU1: cpu@100 { 69 CPU1: cpu@100 {
79 device_type = "cpu"; 70 device_type = "cpu";
80 compatible = "qcom,kry 71 compatible = "qcom,kryo780";
81 reg = <0x0 0x100>; 72 reg = <0x0 0x100>;
82 enable-method = "psci" 73 enable-method = "psci";
83 next-level-cache = <&L 74 next-level-cache = <&L2_100>;
84 power-domains = <&CPU_ 75 power-domains = <&CPU_PD1>;
85 power-domain-names = " 76 power-domain-names = "psci";
86 qcom,freq-domain = <&c 77 qcom,freq-domain = <&cpufreq_hw 0>;
87 #cooling-cells = <2>; 78 #cooling-cells = <2>;
88 clocks = <&cpufreq_hw 79 clocks = <&cpufreq_hw 0>;
89 L2_100: l2-cache { 80 L2_100: l2-cache {
90 compatible = " !! 81 compatible = "cache";
91 cache-level = !! 82 cache-level = <2>;
92 cache-unified; !! 83 next-level-cache = <&L3_0>;
93 next-level-cac <<
94 }; 84 };
95 }; 85 };
96 86
97 CPU2: cpu@200 { 87 CPU2: cpu@200 {
98 device_type = "cpu"; 88 device_type = "cpu";
99 compatible = "qcom,kry 89 compatible = "qcom,kryo780";
100 reg = <0x0 0x200>; 90 reg = <0x0 0x200>;
101 enable-method = "psci" 91 enable-method = "psci";
102 next-level-cache = <&L 92 next-level-cache = <&L2_200>;
103 power-domains = <&CPU_ 93 power-domains = <&CPU_PD2>;
104 power-domain-names = " 94 power-domain-names = "psci";
105 qcom,freq-domain = <&c 95 qcom,freq-domain = <&cpufreq_hw 0>;
106 #cooling-cells = <2>; 96 #cooling-cells = <2>;
107 clocks = <&cpufreq_hw 97 clocks = <&cpufreq_hw 0>;
108 L2_200: l2-cache { 98 L2_200: l2-cache {
109 compatible = " !! 99 compatible = "cache";
110 cache-level = !! 100 cache-level = <2>;
111 cache-unified; !! 101 next-level-cache = <&L3_0>;
112 next-level-cac <<
113 }; 102 };
114 }; 103 };
115 104
116 CPU3: cpu@300 { 105 CPU3: cpu@300 {
117 device_type = "cpu"; 106 device_type = "cpu";
118 compatible = "qcom,kry 107 compatible = "qcom,kryo780";
119 reg = <0x0 0x300>; 108 reg = <0x0 0x300>;
120 enable-method = "psci" 109 enable-method = "psci";
121 next-level-cache = <&L 110 next-level-cache = <&L2_300>;
122 power-domains = <&CPU_ 111 power-domains = <&CPU_PD3>;
123 power-domain-names = " 112 power-domain-names = "psci";
124 qcom,freq-domain = <&c 113 qcom,freq-domain = <&cpufreq_hw 0>;
125 #cooling-cells = <2>; 114 #cooling-cells = <2>;
126 clocks = <&cpufreq_hw 115 clocks = <&cpufreq_hw 0>;
127 L2_300: l2-cache { 116 L2_300: l2-cache {
128 compatible = " !! 117 compatible = "cache";
129 cache-level = !! 118 cache-level = <2>;
130 cache-unified; !! 119 next-level-cache = <&L3_0>;
131 next-level-cac <<
132 }; 120 };
133 }; 121 };
134 122
135 CPU4: cpu@400 { 123 CPU4: cpu@400 {
136 device_type = "cpu"; 124 device_type = "cpu";
137 compatible = "qcom,kry 125 compatible = "qcom,kryo780";
138 reg = <0x0 0x400>; 126 reg = <0x0 0x400>;
139 enable-method = "psci" 127 enable-method = "psci";
140 next-level-cache = <&L 128 next-level-cache = <&L2_400>;
141 power-domains = <&CPU_ 129 power-domains = <&CPU_PD4>;
142 power-domain-names = " 130 power-domain-names = "psci";
143 qcom,freq-domain = <&c 131 qcom,freq-domain = <&cpufreq_hw 1>;
144 #cooling-cells = <2>; 132 #cooling-cells = <2>;
145 clocks = <&cpufreq_hw 133 clocks = <&cpufreq_hw 1>;
146 L2_400: l2-cache { 134 L2_400: l2-cache {
147 compatible = " !! 135 compatible = "cache";
148 cache-level = !! 136 cache-level = <2>;
149 cache-unified; !! 137 next-level-cache = <&L3_0>;
150 next-level-cac <<
151 }; 138 };
152 }; 139 };
153 140
154 CPU5: cpu@500 { 141 CPU5: cpu@500 {
155 device_type = "cpu"; 142 device_type = "cpu";
156 compatible = "qcom,kry 143 compatible = "qcom,kryo780";
157 reg = <0x0 0x500>; 144 reg = <0x0 0x500>;
158 enable-method = "psci" 145 enable-method = "psci";
159 next-level-cache = <&L 146 next-level-cache = <&L2_500>;
160 power-domains = <&CPU_ 147 power-domains = <&CPU_PD5>;
161 power-domain-names = " 148 power-domain-names = "psci";
162 qcom,freq-domain = <&c 149 qcom,freq-domain = <&cpufreq_hw 1>;
163 #cooling-cells = <2>; 150 #cooling-cells = <2>;
164 clocks = <&cpufreq_hw 151 clocks = <&cpufreq_hw 1>;
165 L2_500: l2-cache { 152 L2_500: l2-cache {
166 compatible = " !! 153 compatible = "cache";
167 cache-level = !! 154 cache-level = <2>;
168 cache-unified; !! 155 next-level-cache = <&L3_0>;
169 next-level-cac <<
170 }; 156 };
>> 157
171 }; 158 };
172 159
173 CPU6: cpu@600 { 160 CPU6: cpu@600 {
174 device_type = "cpu"; 161 device_type = "cpu";
175 compatible = "qcom,kry 162 compatible = "qcom,kryo780";
176 reg = <0x0 0x600>; 163 reg = <0x0 0x600>;
177 enable-method = "psci" 164 enable-method = "psci";
178 next-level-cache = <&L 165 next-level-cache = <&L2_600>;
179 power-domains = <&CPU_ 166 power-domains = <&CPU_PD6>;
180 power-domain-names = " 167 power-domain-names = "psci";
181 qcom,freq-domain = <&c 168 qcom,freq-domain = <&cpufreq_hw 1>;
182 #cooling-cells = <2>; 169 #cooling-cells = <2>;
183 clocks = <&cpufreq_hw 170 clocks = <&cpufreq_hw 1>;
184 L2_600: l2-cache { 171 L2_600: l2-cache {
185 compatible = " !! 172 compatible = "cache";
186 cache-level = !! 173 cache-level = <2>;
187 cache-unified; !! 174 next-level-cache = <&L3_0>;
188 next-level-cac <<
189 }; 175 };
190 }; 176 };
191 177
192 CPU7: cpu@700 { 178 CPU7: cpu@700 {
193 device_type = "cpu"; 179 device_type = "cpu";
194 compatible = "qcom,kry 180 compatible = "qcom,kryo780";
195 reg = <0x0 0x700>; 181 reg = <0x0 0x700>;
196 enable-method = "psci" 182 enable-method = "psci";
197 next-level-cache = <&L 183 next-level-cache = <&L2_700>;
198 power-domains = <&CPU_ 184 power-domains = <&CPU_PD7>;
199 power-domain-names = " 185 power-domain-names = "psci";
200 qcom,freq-domain = <&c 186 qcom,freq-domain = <&cpufreq_hw 2>;
201 #cooling-cells = <2>; 187 #cooling-cells = <2>;
202 clocks = <&cpufreq_hw 188 clocks = <&cpufreq_hw 2>;
203 L2_700: l2-cache { 189 L2_700: l2-cache {
204 compatible = " !! 190 compatible = "cache";
205 cache-level = !! 191 cache-level = <2>;
206 cache-unified; !! 192 next-level-cache = <&L3_0>;
207 next-level-cac <<
208 }; 193 };
209 }; 194 };
210 195
211 cpu-map { 196 cpu-map {
212 cluster0 { 197 cluster0 {
213 core0 { 198 core0 {
214 cpu = 199 cpu = <&CPU0>;
215 }; 200 };
216 201
217 core1 { 202 core1 {
218 cpu = 203 cpu = <&CPU1>;
219 }; 204 };
220 205
221 core2 { 206 core2 {
222 cpu = 207 cpu = <&CPU2>;
223 }; 208 };
224 209
225 core3 { 210 core3 {
226 cpu = 211 cpu = <&CPU3>;
227 }; 212 };
228 213
229 core4 { 214 core4 {
230 cpu = 215 cpu = <&CPU4>;
231 }; 216 };
232 217
233 core5 { 218 core5 {
234 cpu = 219 cpu = <&CPU5>;
235 }; 220 };
236 221
237 core6 { 222 core6 {
238 cpu = 223 cpu = <&CPU6>;
239 }; 224 };
240 225
241 core7 { 226 core7 {
242 cpu = 227 cpu = <&CPU7>;
243 }; 228 };
244 }; 229 };
245 }; 230 };
246 231
247 idle-states { 232 idle-states {
248 entry-method = "psci"; 233 entry-method = "psci";
249 234
250 LITTLE_CPU_SLEEP_0: cp 235 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
251 compatible = " 236 compatible = "arm,idle-state";
252 idle-state-nam 237 idle-state-name = "silver-rail-power-collapse";
253 arm,psci-suspe 238 arm,psci-suspend-param = <0x40000004>;
254 entry-latency- 239 entry-latency-us = <800>;
255 exit-latency-u 240 exit-latency-us = <750>;
256 min-residency- 241 min-residency-us = <4090>;
257 local-timer-st 242 local-timer-stop;
258 }; 243 };
259 244
260 BIG_CPU_SLEEP_0: cpu-s 245 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
261 compatible = " 246 compatible = "arm,idle-state";
262 idle-state-nam 247 idle-state-name = "gold-rail-power-collapse";
263 arm,psci-suspe 248 arm,psci-suspend-param = <0x40000004>;
264 entry-latency- 249 entry-latency-us = <600>;
265 exit-latency-u 250 exit-latency-us = <1550>;
266 min-residency- 251 min-residency-us = <4791>;
267 local-timer-st 252 local-timer-stop;
268 }; 253 };
269 }; 254 };
270 255
271 domain-idle-states { 256 domain-idle-states {
272 CLUSTER_SLEEP_0: clust 257 CLUSTER_SLEEP_0: cluster-sleep-0 {
273 compatible = " 258 compatible = "domain-idle-state";
>> 259 idle-state-name = "cluster-l3-off";
274 arm,psci-suspe 260 arm,psci-suspend-param = <0x41000044>;
275 entry-latency- 261 entry-latency-us = <1050>;
276 exit-latency-u 262 exit-latency-us = <2500>;
277 min-residency- 263 min-residency-us = <5309>;
>> 264 local-timer-stop;
278 }; 265 };
279 266
280 CLUSTER_SLEEP_1: clust 267 CLUSTER_SLEEP_1: cluster-sleep-1 {
281 compatible = " 268 compatible = "domain-idle-state";
>> 269 idle-state-name = "cluster-power-collapse";
282 arm,psci-suspe 270 arm,psci-suspend-param = <0x4100c344>;
283 entry-latency- 271 entry-latency-us = <2700>;
284 exit-latency-u 272 exit-latency-us = <3500>;
285 min-residency- 273 min-residency-us = <13959>;
>> 274 local-timer-stop;
286 }; 275 };
287 }; 276 };
288 }; 277 };
289 278
290 firmware { 279 firmware {
291 scm: scm { 280 scm: scm {
292 compatible = "qcom,scm 281 compatible = "qcom,scm-sm8450", "qcom,scm";
293 qcom,dload-mode = <&tc 282 qcom,dload-mode = <&tcsr 0x13000>;
294 interconnects = <&aggr 283 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
295 #reset-cells = <1>; 284 #reset-cells = <1>;
296 }; 285 };
297 }; 286 };
298 287
299 clk_virt: interconnect-0 { 288 clk_virt: interconnect-0 {
300 compatible = "qcom,sm8450-clk- 289 compatible = "qcom,sm8450-clk-virt";
301 #interconnect-cells = <2>; 290 #interconnect-cells = <2>;
302 qcom,bcm-voters = <&apps_bcm_v 291 qcom,bcm-voters = <&apps_bcm_voter>;
303 }; 292 };
304 293
305 mc_virt: interconnect-1 { 294 mc_virt: interconnect-1 {
306 compatible = "qcom,sm8450-mc-v 295 compatible = "qcom,sm8450-mc-virt";
307 #interconnect-cells = <2>; 296 #interconnect-cells = <2>;
308 qcom,bcm-voters = <&apps_bcm_v 297 qcom,bcm-voters = <&apps_bcm_voter>;
309 }; 298 };
310 299
311 memory@a0000000 { 300 memory@a0000000 {
312 device_type = "memory"; 301 device_type = "memory";
313 /* We expect the bootloader to 302 /* We expect the bootloader to fill in the size */
314 reg = <0x0 0xa0000000 0x0 0x0> 303 reg = <0x0 0xa0000000 0x0 0x0>;
315 }; 304 };
316 305
317 pmu { 306 pmu {
318 compatible = "arm,armv8-pmuv3" 307 compatible = "arm,armv8-pmuv3";
319 interrupts = <GIC_PPI 7 IRQ_TY 308 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
320 }; 309 };
321 310
322 psci { 311 psci {
323 compatible = "arm,psci-1.0"; 312 compatible = "arm,psci-1.0";
324 method = "smc"; 313 method = "smc";
325 314
326 CPU_PD0: power-domain-cpu0 { 315 CPU_PD0: power-domain-cpu0 {
327 #power-domain-cells = 316 #power-domain-cells = <0>;
328 power-domains = <&CLUS 317 power-domains = <&CLUSTER_PD>;
329 domain-idle-states = < 318 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
330 }; 319 };
331 320
332 CPU_PD1: power-domain-cpu1 { 321 CPU_PD1: power-domain-cpu1 {
333 #power-domain-cells = 322 #power-domain-cells = <0>;
334 power-domains = <&CLUS 323 power-domains = <&CLUSTER_PD>;
335 domain-idle-states = < 324 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
336 }; 325 };
337 326
338 CPU_PD2: power-domain-cpu2 { 327 CPU_PD2: power-domain-cpu2 {
339 #power-domain-cells = 328 #power-domain-cells = <0>;
340 power-domains = <&CLUS 329 power-domains = <&CLUSTER_PD>;
341 domain-idle-states = < 330 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
342 }; 331 };
343 332
344 CPU_PD3: power-domain-cpu3 { 333 CPU_PD3: power-domain-cpu3 {
345 #power-domain-cells = 334 #power-domain-cells = <0>;
346 power-domains = <&CLUS 335 power-domains = <&CLUSTER_PD>;
347 domain-idle-states = < 336 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
348 }; 337 };
349 338
350 CPU_PD4: power-domain-cpu4 { 339 CPU_PD4: power-domain-cpu4 {
351 #power-domain-cells = 340 #power-domain-cells = <0>;
352 power-domains = <&CLUS 341 power-domains = <&CLUSTER_PD>;
353 domain-idle-states = < 342 domain-idle-states = <&BIG_CPU_SLEEP_0>;
354 }; 343 };
355 344
356 CPU_PD5: power-domain-cpu5 { 345 CPU_PD5: power-domain-cpu5 {
357 #power-domain-cells = 346 #power-domain-cells = <0>;
358 power-domains = <&CLUS 347 power-domains = <&CLUSTER_PD>;
359 domain-idle-states = < 348 domain-idle-states = <&BIG_CPU_SLEEP_0>;
360 }; 349 };
361 350
362 CPU_PD6: power-domain-cpu6 { 351 CPU_PD6: power-domain-cpu6 {
363 #power-domain-cells = 352 #power-domain-cells = <0>;
364 power-domains = <&CLUS 353 power-domains = <&CLUSTER_PD>;
365 domain-idle-states = < 354 domain-idle-states = <&BIG_CPU_SLEEP_0>;
366 }; 355 };
367 356
368 CPU_PD7: power-domain-cpu7 { 357 CPU_PD7: power-domain-cpu7 {
369 #power-domain-cells = 358 #power-domain-cells = <0>;
370 power-domains = <&CLUS 359 power-domains = <&CLUSTER_PD>;
371 domain-idle-states = < 360 domain-idle-states = <&BIG_CPU_SLEEP_0>;
372 }; 361 };
373 362
374 CLUSTER_PD: power-domain-cpu-c 363 CLUSTER_PD: power-domain-cpu-cluster0 {
375 #power-domain-cells = 364 #power-domain-cells = <0>;
376 domain-idle-states = < 365 domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>;
377 }; 366 };
378 }; 367 };
379 368
380 qup_opp_table_100mhz: opp-table-qup { 369 qup_opp_table_100mhz: opp-table-qup {
381 compatible = "operating-points 370 compatible = "operating-points-v2";
382 371
383 opp-50000000 { 372 opp-50000000 {
384 opp-hz = /bits/ 64 <50 373 opp-hz = /bits/ 64 <50000000>;
385 required-opps = <&rpmh 374 required-opps = <&rpmhpd_opp_min_svs>;
386 }; 375 };
387 376
388 opp-75000000 { 377 opp-75000000 {
389 opp-hz = /bits/ 64 <75 378 opp-hz = /bits/ 64 <75000000>;
390 required-opps = <&rpmh 379 required-opps = <&rpmhpd_opp_low_svs>;
391 }; 380 };
392 381
393 opp-100000000 { 382 opp-100000000 {
394 opp-hz = /bits/ 64 <10 383 opp-hz = /bits/ 64 <100000000>;
395 required-opps = <&rpmh 384 required-opps = <&rpmhpd_opp_svs>;
396 }; 385 };
397 }; 386 };
398 387
399 reserved_memory: reserved-memory { 388 reserved_memory: reserved-memory {
400 #address-cells = <2>; 389 #address-cells = <2>;
401 #size-cells = <2>; 390 #size-cells = <2>;
402 ranges; 391 ranges;
403 392
404 hyp_mem: memory@80000000 { 393 hyp_mem: memory@80000000 {
405 reg = <0x0 0x80000000 394 reg = <0x0 0x80000000 0x0 0x600000>;
406 no-map; 395 no-map;
407 }; 396 };
408 397
409 xbl_dt_log_mem: memory@8060000 398 xbl_dt_log_mem: memory@80600000 {
410 reg = <0x0 0x80600000 399 reg = <0x0 0x80600000 0x0 0x40000>;
411 no-map; 400 no-map;
412 }; 401 };
413 402
414 xbl_ramdump_mem: memory@806400 403 xbl_ramdump_mem: memory@80640000 {
415 reg = <0x0 0x80640000 404 reg = <0x0 0x80640000 0x0 0x180000>;
416 no-map; 405 no-map;
417 }; 406 };
418 407
419 xbl_sc_mem: memory@807c0000 { 408 xbl_sc_mem: memory@807c0000 {
420 reg = <0x0 0x807c0000 409 reg = <0x0 0x807c0000 0x0 0x40000>;
421 no-map; 410 no-map;
422 }; 411 };
423 412
424 aop_image_mem: memory@80800000 413 aop_image_mem: memory@80800000 {
425 reg = <0x0 0x80800000 414 reg = <0x0 0x80800000 0x0 0x60000>;
426 no-map; 415 no-map;
427 }; 416 };
428 417
429 aop_cmd_db_mem: memory@8086000 418 aop_cmd_db_mem: memory@80860000 {
430 compatible = "qcom,cmd 419 compatible = "qcom,cmd-db";
431 reg = <0x0 0x80860000 420 reg = <0x0 0x80860000 0x0 0x20000>;
432 no-map; 421 no-map;
433 }; 422 };
434 423
435 aop_config_mem: memory@8088000 424 aop_config_mem: memory@80880000 {
436 reg = <0x0 0x80880000 425 reg = <0x0 0x80880000 0x0 0x20000>;
437 no-map; 426 no-map;
438 }; 427 };
439 428
440 tme_crash_dump_mem: memory@808 429 tme_crash_dump_mem: memory@808a0000 {
441 reg = <0x0 0x808a0000 430 reg = <0x0 0x808a0000 0x0 0x40000>;
442 no-map; 431 no-map;
443 }; 432 };
444 433
445 tme_log_mem: memory@808e0000 { 434 tme_log_mem: memory@808e0000 {
446 reg = <0x0 0x808e0000 435 reg = <0x0 0x808e0000 0x0 0x4000>;
447 no-map; 436 no-map;
448 }; 437 };
449 438
450 uefi_log_mem: memory@808e4000 439 uefi_log_mem: memory@808e4000 {
451 reg = <0x0 0x808e4000 440 reg = <0x0 0x808e4000 0x0 0x10000>;
452 no-map; 441 no-map;
453 }; 442 };
454 443
455 /* secdata region can be reuse 444 /* secdata region can be reused by apps */
456 smem: memory@80900000 { 445 smem: memory@80900000 {
457 compatible = "qcom,sme 446 compatible = "qcom,smem";
458 reg = <0x0 0x80900000 447 reg = <0x0 0x80900000 0x0 0x200000>;
459 hwlocks = <&tcsr_mutex 448 hwlocks = <&tcsr_mutex 3>;
460 no-map; 449 no-map;
461 }; 450 };
462 451
463 cpucp_fw_mem: memory@80b00000 452 cpucp_fw_mem: memory@80b00000 {
464 reg = <0x0 0x80b00000 453 reg = <0x0 0x80b00000 0x0 0x100000>;
465 no-map; 454 no-map;
466 }; 455 };
467 456
468 cdsp_secure_heap: memory@80c00 457 cdsp_secure_heap: memory@80c00000 {
469 reg = <0x0 0x80c00000 458 reg = <0x0 0x80c00000 0x0 0x4600000>;
470 no-map; 459 no-map;
471 }; 460 };
472 461
473 video_mem: memory@85700000 { 462 video_mem: memory@85700000 {
474 reg = <0x0 0x85700000 463 reg = <0x0 0x85700000 0x0 0x700000>;
475 no-map; 464 no-map;
476 }; 465 };
477 466
478 adsp_mem: memory@85e00000 { 467 adsp_mem: memory@85e00000 {
479 reg = <0x0 0x85e00000 468 reg = <0x0 0x85e00000 0x0 0x2100000>;
480 no-map; 469 no-map;
481 }; 470 };
482 471
483 slpi_mem: memory@88000000 { 472 slpi_mem: memory@88000000 {
484 reg = <0x0 0x88000000 473 reg = <0x0 0x88000000 0x0 0x1900000>;
485 no-map; 474 no-map;
486 }; 475 };
487 476
488 cdsp_mem: memory@89900000 { 477 cdsp_mem: memory@89900000 {
489 reg = <0x0 0x89900000 478 reg = <0x0 0x89900000 0x0 0x2000000>;
490 no-map; 479 no-map;
491 }; 480 };
492 481
493 ipa_fw_mem: memory@8b900000 { 482 ipa_fw_mem: memory@8b900000 {
494 reg = <0x0 0x8b900000 483 reg = <0x0 0x8b900000 0x0 0x10000>;
495 no-map; 484 no-map;
496 }; 485 };
497 486
498 ipa_gsi_mem: memory@8b910000 { 487 ipa_gsi_mem: memory@8b910000 {
499 reg = <0x0 0x8b910000 488 reg = <0x0 0x8b910000 0x0 0xa000>;
500 no-map; 489 no-map;
501 }; 490 };
502 491
503 gpu_micro_code_mem: memory@8b9 492 gpu_micro_code_mem: memory@8b91a000 {
504 reg = <0x0 0x8b91a000 493 reg = <0x0 0x8b91a000 0x0 0x2000>;
505 no-map; 494 no-map;
506 }; 495 };
507 496
508 spss_region_mem: memory@8ba000 497 spss_region_mem: memory@8ba00000 {
509 reg = <0x0 0x8ba00000 498 reg = <0x0 0x8ba00000 0x0 0x180000>;
510 no-map; 499 no-map;
511 }; 500 };
512 501
513 /* First part of the "SPU secu 502 /* First part of the "SPU secure shared memory" region */
514 spu_tz_shared_mem: memory@8bb8 503 spu_tz_shared_mem: memory@8bb80000 {
515 reg = <0x0 0x8bb80000 504 reg = <0x0 0x8bb80000 0x0 0x60000>;
516 no-map; 505 no-map;
517 }; 506 };
518 507
519 /* Second part of the "SPU sec 508 /* Second part of the "SPU secure shared memory" region */
520 spu_modem_shared_mem: memory@8 509 spu_modem_shared_mem: memory@8bbe0000 {
521 reg = <0x0 0x8bbe0000 510 reg = <0x0 0x8bbe0000 0x0 0x20000>;
522 no-map; 511 no-map;
523 }; 512 };
524 513
525 mpss_mem: memory@8bc00000 { 514 mpss_mem: memory@8bc00000 {
526 reg = <0x0 0x8bc00000 515 reg = <0x0 0x8bc00000 0x0 0x13200000>;
527 no-map; 516 no-map;
528 }; 517 };
529 518
530 cvp_mem: memory@9ee00000 { 519 cvp_mem: memory@9ee00000 {
531 reg = <0x0 0x9ee00000 520 reg = <0x0 0x9ee00000 0x0 0x700000>;
532 no-map; 521 no-map;
533 }; 522 };
534 523
535 camera_mem: memory@9f500000 { 524 camera_mem: memory@9f500000 {
536 reg = <0x0 0x9f500000 525 reg = <0x0 0x9f500000 0x0 0x800000>;
537 no-map; 526 no-map;
538 }; 527 };
539 528
540 rmtfs_mem: memory@9fd00000 { 529 rmtfs_mem: memory@9fd00000 {
541 compatible = "qcom,rmt 530 compatible = "qcom,rmtfs-mem";
542 reg = <0x0 0x9fd00000 531 reg = <0x0 0x9fd00000 0x0 0x280000>;
543 no-map; 532 no-map;
544 533
545 qcom,client-id = <1>; 534 qcom,client-id = <1>;
546 qcom,vmid = <QCOM_SCM_ !! 535 qcom,vmid = <15>;
547 }; 536 };
548 537
549 xbl_sc_mem2: memory@a6e00000 { 538 xbl_sc_mem2: memory@a6e00000 {
550 reg = <0x0 0xa6e00000 539 reg = <0x0 0xa6e00000 0x0 0x40000>;
551 no-map; 540 no-map;
552 }; 541 };
553 542
554 global_sync_mem: memory@a6f000 543 global_sync_mem: memory@a6f00000 {
555 reg = <0x0 0xa6f00000 544 reg = <0x0 0xa6f00000 0x0 0x100000>;
556 no-map; 545 no-map;
557 }; 546 };
558 547
559 /* uefi region can be reused b 548 /* uefi region can be reused by APPS */
560 549
561 /* Linux kernel image is loade 550 /* Linux kernel image is loaded at 0xa0000000 */
562 551
563 oem_vm_mem: memory@bb000000 { 552 oem_vm_mem: memory@bb000000 {
564 reg = <0x0 0xbb000000 553 reg = <0x0 0xbb000000 0x0 0x5000000>;
565 no-map; 554 no-map;
566 }; 555 };
567 556
568 mte_mem: memory@c0000000 { 557 mte_mem: memory@c0000000 {
569 reg = <0x0 0xc0000000 558 reg = <0x0 0xc0000000 0x0 0x20000000>;
570 no-map; 559 no-map;
571 }; 560 };
572 561
573 qheebsp_reserved_mem: memory@e 562 qheebsp_reserved_mem: memory@e0000000 {
574 reg = <0x0 0xe0000000 563 reg = <0x0 0xe0000000 0x0 0x600000>;
575 no-map; 564 no-map;
576 }; 565 };
577 566
578 cpusys_vm_mem: memory@e0600000 567 cpusys_vm_mem: memory@e0600000 {
579 reg = <0x0 0xe0600000 568 reg = <0x0 0xe0600000 0x0 0x400000>;
580 no-map; 569 no-map;
581 }; 570 };
582 571
583 hyp_reserved_mem: memory@e0a00 572 hyp_reserved_mem: memory@e0a00000 {
584 reg = <0x0 0xe0a00000 573 reg = <0x0 0xe0a00000 0x0 0x100000>;
585 no-map; 574 no-map;
586 }; 575 };
587 576
588 trust_ui_vm_mem: memory@e0b000 577 trust_ui_vm_mem: memory@e0b00000 {
589 reg = <0x0 0xe0b00000 578 reg = <0x0 0xe0b00000 0x0 0x4af3000>;
590 no-map; 579 no-map;
591 }; 580 };
592 581
593 trust_ui_vm_qrtr: memory@e55f3 582 trust_ui_vm_qrtr: memory@e55f3000 {
594 reg = <0x0 0xe55f3000 583 reg = <0x0 0xe55f3000 0x0 0x9000>;
595 no-map; 584 no-map;
596 }; 585 };
597 586
598 trust_ui_vm_vblk0_ring: memory 587 trust_ui_vm_vblk0_ring: memory@e55fc000 {
599 reg = <0x0 0xe55fc000 588 reg = <0x0 0xe55fc000 0x0 0x4000>;
600 no-map; 589 no-map;
601 }; 590 };
602 591
603 trust_ui_vm_swiotlb: memory@e5 592 trust_ui_vm_swiotlb: memory@e5600000 {
604 reg = <0x0 0xe5600000 593 reg = <0x0 0xe5600000 0x0 0x100000>;
605 no-map; 594 no-map;
606 }; 595 };
607 596
608 tz_stat_mem: memory@e8800000 { 597 tz_stat_mem: memory@e8800000 {
609 reg = <0x0 0xe8800000 598 reg = <0x0 0xe8800000 0x0 0x100000>;
610 no-map; 599 no-map;
611 }; 600 };
612 601
613 tags_mem: memory@e8900000 { 602 tags_mem: memory@e8900000 {
614 reg = <0x0 0xe8900000 603 reg = <0x0 0xe8900000 0x0 0x1200000>;
615 no-map; 604 no-map;
616 }; 605 };
617 606
618 qtee_mem: memory@e9b00000 { 607 qtee_mem: memory@e9b00000 {
619 reg = <0x0 0xe9b00000 608 reg = <0x0 0xe9b00000 0x0 0x500000>;
620 no-map; 609 no-map;
621 }; 610 };
622 611
623 trusted_apps_mem: memory@ea000 612 trusted_apps_mem: memory@ea000000 {
624 reg = <0x0 0xea000000 613 reg = <0x0 0xea000000 0x0 0x3900000>;
625 no-map; 614 no-map;
626 }; 615 };
627 616
628 trusted_apps_ext_mem: memory@e 617 trusted_apps_ext_mem: memory@ed900000 {
629 reg = <0x0 0xed900000 618 reg = <0x0 0xed900000 0x0 0x3b00000>;
630 no-map; 619 no-map;
631 }; 620 };
632 }; 621 };
633 622
634 smp2p-adsp { 623 smp2p-adsp {
635 compatible = "qcom,smp2p"; 624 compatible = "qcom,smp2p";
636 qcom,smem = <443>, <429>; 625 qcom,smem = <443>, <429>;
637 interrupts-extended = <&ipcc I 626 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
638 I 627 IPCC_MPROC_SIGNAL_SMP2P
639 I 628 IRQ_TYPE_EDGE_RISING>;
640 mboxes = <&ipcc IPCC_CLIENT_LP 629 mboxes = <&ipcc IPCC_CLIENT_LPASS
641 IPCC_MPROC_SIG 630 IPCC_MPROC_SIGNAL_SMP2P>;
642 631
643 qcom,local-pid = <0>; 632 qcom,local-pid = <0>;
644 qcom,remote-pid = <2>; 633 qcom,remote-pid = <2>;
645 634
646 smp2p_adsp_out: master-kernel 635 smp2p_adsp_out: master-kernel {
647 qcom,entry-name = "mas 636 qcom,entry-name = "master-kernel";
648 #qcom,smem-state-cells 637 #qcom,smem-state-cells = <1>;
649 }; 638 };
650 639
651 smp2p_adsp_in: slave-kernel { 640 smp2p_adsp_in: slave-kernel {
652 qcom,entry-name = "sla 641 qcom,entry-name = "slave-kernel";
653 interrupt-controller; 642 interrupt-controller;
654 #interrupt-cells = <2> 643 #interrupt-cells = <2>;
655 }; 644 };
656 }; 645 };
657 646
658 smp2p-cdsp { 647 smp2p-cdsp {
659 compatible = "qcom,smp2p"; 648 compatible = "qcom,smp2p";
660 qcom,smem = <94>, <432>; 649 qcom,smem = <94>, <432>;
661 interrupts-extended = <&ipcc I 650 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
662 I 651 IPCC_MPROC_SIGNAL_SMP2P
663 I 652 IRQ_TYPE_EDGE_RISING>;
664 mboxes = <&ipcc IPCC_CLIENT_CD 653 mboxes = <&ipcc IPCC_CLIENT_CDSP
665 IPCC_MPROC_SIG 654 IPCC_MPROC_SIGNAL_SMP2P>;
666 655
667 qcom,local-pid = <0>; 656 qcom,local-pid = <0>;
668 qcom,remote-pid = <5>; 657 qcom,remote-pid = <5>;
669 658
670 smp2p_cdsp_out: master-kernel 659 smp2p_cdsp_out: master-kernel {
671 qcom,entry-name = "mas 660 qcom,entry-name = "master-kernel";
672 #qcom,smem-state-cells 661 #qcom,smem-state-cells = <1>;
673 }; 662 };
674 663
675 smp2p_cdsp_in: slave-kernel { 664 smp2p_cdsp_in: slave-kernel {
676 qcom,entry-name = "sla 665 qcom,entry-name = "slave-kernel";
677 interrupt-controller; 666 interrupt-controller;
678 #interrupt-cells = <2> 667 #interrupt-cells = <2>;
679 }; 668 };
680 }; 669 };
681 670
682 smp2p-modem { 671 smp2p-modem {
683 compatible = "qcom,smp2p"; 672 compatible = "qcom,smp2p";
684 qcom,smem = <435>, <428>; 673 qcom,smem = <435>, <428>;
685 interrupts-extended = <&ipcc I 674 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
686 I 675 IPCC_MPROC_SIGNAL_SMP2P
687 I 676 IRQ_TYPE_EDGE_RISING>;
688 mboxes = <&ipcc IPCC_CLIENT_MP 677 mboxes = <&ipcc IPCC_CLIENT_MPSS
689 IPCC_MPROC_SIG 678 IPCC_MPROC_SIGNAL_SMP2P>;
690 679
691 qcom,local-pid = <0>; 680 qcom,local-pid = <0>;
692 qcom,remote-pid = <1>; 681 qcom,remote-pid = <1>;
693 682
694 smp2p_modem_out: master-kernel 683 smp2p_modem_out: master-kernel {
695 qcom,entry-name = "mas 684 qcom,entry-name = "master-kernel";
696 #qcom,smem-state-cells 685 #qcom,smem-state-cells = <1>;
697 }; 686 };
698 687
699 smp2p_modem_in: slave-kernel { 688 smp2p_modem_in: slave-kernel {
700 qcom,entry-name = "sla 689 qcom,entry-name = "slave-kernel";
701 interrupt-controller; 690 interrupt-controller;
702 #interrupt-cells = <2> 691 #interrupt-cells = <2>;
703 }; 692 };
704 693
705 ipa_smp2p_out: ipa-ap-to-modem 694 ipa_smp2p_out: ipa-ap-to-modem {
706 qcom,entry-name = "ipa 695 qcom,entry-name = "ipa";
707 #qcom,smem-state-cells 696 #qcom,smem-state-cells = <1>;
708 }; 697 };
709 698
710 ipa_smp2p_in: ipa-modem-to-ap 699 ipa_smp2p_in: ipa-modem-to-ap {
711 qcom,entry-name = "ipa 700 qcom,entry-name = "ipa";
712 interrupt-controller; 701 interrupt-controller;
713 #interrupt-cells = <2> 702 #interrupt-cells = <2>;
714 }; 703 };
715 }; 704 };
716 705
717 smp2p-slpi { 706 smp2p-slpi {
718 compatible = "qcom,smp2p"; 707 compatible = "qcom,smp2p";
719 qcom,smem = <481>, <430>; 708 qcom,smem = <481>, <430>;
720 interrupts-extended = <&ipcc I 709 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
721 I 710 IPCC_MPROC_SIGNAL_SMP2P
722 I 711 IRQ_TYPE_EDGE_RISING>;
723 mboxes = <&ipcc IPCC_CLIENT_SL 712 mboxes = <&ipcc IPCC_CLIENT_SLPI
724 IPCC_MPROC_SIG 713 IPCC_MPROC_SIGNAL_SMP2P>;
725 714
726 qcom,local-pid = <0>; 715 qcom,local-pid = <0>;
727 qcom,remote-pid = <3>; 716 qcom,remote-pid = <3>;
728 717
729 smp2p_slpi_out: master-kernel 718 smp2p_slpi_out: master-kernel {
730 qcom,entry-name = "mas 719 qcom,entry-name = "master-kernel";
731 #qcom,smem-state-cells 720 #qcom,smem-state-cells = <1>;
732 }; 721 };
733 722
734 smp2p_slpi_in: slave-kernel { 723 smp2p_slpi_in: slave-kernel {
735 qcom,entry-name = "sla 724 qcom,entry-name = "slave-kernel";
736 interrupt-controller; 725 interrupt-controller;
737 #interrupt-cells = <2> 726 #interrupt-cells = <2>;
738 }; 727 };
739 }; 728 };
740 729
741 soc: soc@0 { 730 soc: soc@0 {
742 #address-cells = <2>; 731 #address-cells = <2>;
743 #size-cells = <2>; 732 #size-cells = <2>;
744 ranges = <0 0 0 0 0x10 0>; 733 ranges = <0 0 0 0 0x10 0>;
745 dma-ranges = <0 0 0 0 0x10 0>; 734 dma-ranges = <0 0 0 0 0x10 0>;
746 compatible = "simple-bus"; 735 compatible = "simple-bus";
747 736
748 gcc: clock-controller@100000 { 737 gcc: clock-controller@100000 {
749 compatible = "qcom,gcc 738 compatible = "qcom,gcc-sm8450";
750 reg = <0x0 0x00100000 739 reg = <0x0 0x00100000 0x0 0x1f4200>;
751 #clock-cells = <1>; 740 #clock-cells = <1>;
752 #reset-cells = <1>; 741 #reset-cells = <1>;
753 #power-domain-cells = 742 #power-domain-cells = <1>;
754 clocks = <&rpmhcc RPMH 743 clocks = <&rpmhcc RPMH_CXO_CLK>,
755 <&sleep_clk>, 744 <&sleep_clk>,
756 <&pcie0_phy>, !! 745 <&pcie0_lane>,
757 <&pcie1_phy Q !! 746 <&pcie1_lane>,
758 <&pcie1_phy Q !! 747 <0>,
759 <&ufs_mem_phy !! 748 <&ufs_mem_phy_lanes 0>,
760 <&ufs_mem_phy !! 749 <&ufs_mem_phy_lanes 1>,
761 <&ufs_mem_phy !! 750 <&ufs_mem_phy_lanes 2>,
762 <&usb_1_qmpph !! 751 <0>;
763 clock-names = "bi_tcxo 752 clock-names = "bi_tcxo",
764 "sleep_c 753 "sleep_clk",
765 "pcie_0_ 754 "pcie_0_pipe_clk",
766 "pcie_1_ 755 "pcie_1_pipe_clk",
767 "pcie_1_ 756 "pcie_1_phy_aux_clk",
768 "ufs_phy 757 "ufs_phy_rx_symbol_0_clk",
769 "ufs_phy 758 "ufs_phy_rx_symbol_1_clk",
770 "ufs_phy 759 "ufs_phy_tx_symbol_0_clk",
771 "usb3_ph 760 "usb3_phy_wrapper_gcc_usb30_pipe_clk";
772 }; 761 };
773 762
774 gpi_dma2: dma-controller@80000 763 gpi_dma2: dma-controller@800000 {
775 compatible = "qcom,sm8 764 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
776 #dma-cells = <3>; 765 #dma-cells = <3>;
777 reg = <0 0x00800000 0 766 reg = <0 0x00800000 0 0x60000>;
778 interrupts = <GIC_SPI 767 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
779 <GIC_SPI 768 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
780 <GIC_SPI 769 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
781 <GIC_SPI 770 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
782 <GIC_SPI 771 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
783 <GIC_SPI 772 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
784 <GIC_SPI 773 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
785 <GIC_SPI 774 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
786 <GIC_SPI 775 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
787 <GIC_SPI 776 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
788 <GIC_SPI 777 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
789 <GIC_SPI 778 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
790 dma-channels = <12>; 779 dma-channels = <12>;
791 dma-channel-mask = <0x 780 dma-channel-mask = <0x7e>;
792 iommus = <&apps_smmu 0 781 iommus = <&apps_smmu 0x496 0x0>;
793 status = "disabled"; 782 status = "disabled";
794 }; 783 };
795 784
796 qupv3_id_2: geniqup@8c0000 { 785 qupv3_id_2: geniqup@8c0000 {
797 compatible = "qcom,gen 786 compatible = "qcom,geni-se-qup";
798 reg = <0x0 0x008c0000 787 reg = <0x0 0x008c0000 0x0 0x2000>;
799 clock-names = "m-ahb", 788 clock-names = "m-ahb", "s-ahb";
800 clocks = <&gcc GCC_QUP 789 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
801 <&gcc GCC_QUP 790 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
802 iommus = <&apps_smmu 0 791 iommus = <&apps_smmu 0x483 0x0>;
803 #address-cells = <2>; 792 #address-cells = <2>;
804 #size-cells = <2>; 793 #size-cells = <2>;
805 ranges; 794 ranges;
806 status = "disabled"; 795 status = "disabled";
807 796
808 i2c15: i2c@880000 { 797 i2c15: i2c@880000 {
809 compatible = " 798 compatible = "qcom,geni-i2c";
810 reg = <0x0 0x0 799 reg = <0x0 0x00880000 0x0 0x4000>;
811 clock-names = 800 clock-names = "se";
812 clocks = <&gcc 801 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
813 pinctrl-names 802 pinctrl-names = "default";
814 pinctrl-0 = <& 803 pinctrl-0 = <&qup_i2c15_data_clk>;
815 interrupts = < 804 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
816 #address-cells 805 #address-cells = <1>;
817 #size-cells = 806 #size-cells = <0>;
818 interconnects 807 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
819 808 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
820 809 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
821 interconnect-n 810 interconnect-names = "qup-core", "qup-config", "qup-memory";
822 dmas = <&gpi_d 811 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
823 <&gpi_d 812 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
824 dma-names = "t 813 dma-names = "tx", "rx";
825 status = "disa 814 status = "disabled";
826 }; 815 };
827 816
828 spi15: spi@880000 { 817 spi15: spi@880000 {
829 compatible = " 818 compatible = "qcom,geni-spi";
830 reg = <0x0 0x0 819 reg = <0x0 0x00880000 0x0 0x4000>;
831 clock-names = 820 clock-names = "se";
832 clocks = <&gcc 821 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
833 interrupts = < 822 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
834 pinctrl-names 823 pinctrl-names = "default";
835 pinctrl-0 = <& 824 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
836 interconnects 825 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
837 826 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
838 interconnect-n 827 interconnect-names = "qup-core", "qup-config";
839 dmas = <&gpi_d 828 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
840 <&gpi_d 829 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
841 dma-names = "t 830 dma-names = "tx", "rx";
842 #address-cells 831 #address-cells = <1>;
843 #size-cells = 832 #size-cells = <0>;
844 status = "disa 833 status = "disabled";
845 }; 834 };
846 835
847 i2c16: i2c@884000 { 836 i2c16: i2c@884000 {
848 compatible = " 837 compatible = "qcom,geni-i2c";
849 reg = <0x0 0x0 838 reg = <0x0 0x00884000 0x0 0x4000>;
850 clock-names = 839 clock-names = "se";
851 clocks = <&gcc 840 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
852 pinctrl-names 841 pinctrl-names = "default";
853 pinctrl-0 = <& 842 pinctrl-0 = <&qup_i2c16_data_clk>;
854 interrupts = < 843 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
855 #address-cells 844 #address-cells = <1>;
856 #size-cells = 845 #size-cells = <0>;
857 interconnects 846 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
858 847 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
859 848 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
860 interconnect-n 849 interconnect-names = "qup-core", "qup-config", "qup-memory";
861 dmas = <&gpi_d 850 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
862 <&gpi_d 851 <&gpi_dma2 1 1 QCOM_GPI_I2C>;
863 dma-names = "t 852 dma-names = "tx", "rx";
864 status = "disa 853 status = "disabled";
865 }; 854 };
866 855
867 spi16: spi@884000 { 856 spi16: spi@884000 {
868 compatible = " 857 compatible = "qcom,geni-spi";
869 reg = <0x0 0x0 858 reg = <0x0 0x00884000 0x0 0x4000>;
870 clock-names = 859 clock-names = "se";
871 clocks = <&gcc 860 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
872 interrupts = < 861 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
873 pinctrl-names 862 pinctrl-names = "default";
874 pinctrl-0 = <& 863 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>;
875 interconnects 864 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
876 865 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
877 interconnect-n 866 interconnect-names = "qup-core", "qup-config";
878 dmas = <&gpi_d 867 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
879 <&gpi_d 868 <&gpi_dma2 1 1 QCOM_GPI_SPI>;
880 dma-names = "t 869 dma-names = "tx", "rx";
881 #address-cells 870 #address-cells = <1>;
882 #size-cells = 871 #size-cells = <0>;
883 status = "disa 872 status = "disabled";
884 }; 873 };
885 874
886 i2c17: i2c@888000 { 875 i2c17: i2c@888000 {
887 compatible = " 876 compatible = "qcom,geni-i2c";
888 reg = <0x0 0x0 877 reg = <0x0 0x00888000 0x0 0x4000>;
889 clock-names = 878 clock-names = "se";
890 clocks = <&gcc 879 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
891 pinctrl-names 880 pinctrl-names = "default";
892 pinctrl-0 = <& 881 pinctrl-0 = <&qup_i2c17_data_clk>;
893 interrupts = < 882 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
894 #address-cells 883 #address-cells = <1>;
895 #size-cells = 884 #size-cells = <0>;
896 interconnects 885 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
897 886 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
898 887 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
899 interconnect-n 888 interconnect-names = "qup-core", "qup-config", "qup-memory";
900 dmas = <&gpi_d 889 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
901 <&gpi_d 890 <&gpi_dma2 1 2 QCOM_GPI_I2C>;
902 dma-names = "t 891 dma-names = "tx", "rx";
903 status = "disa 892 status = "disabled";
904 }; 893 };
905 894
906 spi17: spi@888000 { 895 spi17: spi@888000 {
907 compatible = " 896 compatible = "qcom,geni-spi";
908 reg = <0x0 0x0 897 reg = <0x0 0x00888000 0x0 0x4000>;
909 clock-names = 898 clock-names = "se";
910 clocks = <&gcc 899 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
911 interrupts = < 900 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
912 pinctrl-names 901 pinctrl-names = "default";
913 pinctrl-0 = <& 902 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>;
914 interconnects 903 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
915 904 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
916 interconnect-n 905 interconnect-names = "qup-core", "qup-config";
917 dmas = <&gpi_d 906 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
918 <&gpi_d 907 <&gpi_dma2 1 2 QCOM_GPI_SPI>;
919 dma-names = "t 908 dma-names = "tx", "rx";
920 #address-cells 909 #address-cells = <1>;
921 #size-cells = 910 #size-cells = <0>;
922 status = "disa 911 status = "disabled";
923 }; 912 };
924 913
925 i2c18: i2c@88c000 { 914 i2c18: i2c@88c000 {
926 compatible = " 915 compatible = "qcom,geni-i2c";
927 reg = <0x0 0x0 916 reg = <0x0 0x0088c000 0x0 0x4000>;
928 clock-names = 917 clock-names = "se";
929 clocks = <&gcc 918 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
930 pinctrl-names 919 pinctrl-names = "default";
931 pinctrl-0 = <& 920 pinctrl-0 = <&qup_i2c18_data_clk>;
932 interrupts = < 921 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
933 #address-cells 922 #address-cells = <1>;
934 #size-cells = 923 #size-cells = <0>;
935 interconnects 924 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
936 925 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
937 926 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
938 interconnect-n 927 interconnect-names = "qup-core", "qup-config", "qup-memory";
939 dmas = <&gpi_d 928 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
940 <&gpi_d 929 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
941 dma-names = "t 930 dma-names = "tx", "rx";
942 status = "disa 931 status = "disabled";
943 }; 932 };
944 933
945 spi18: spi@88c000 { 934 spi18: spi@88c000 {
946 compatible = " 935 compatible = "qcom,geni-spi";
947 reg = <0 0x008 936 reg = <0 0x0088c000 0 0x4000>;
948 clock-names = 937 clock-names = "se";
949 clocks = <&gcc 938 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
950 interrupts = < 939 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
951 pinctrl-names 940 pinctrl-names = "default";
952 pinctrl-0 = <& 941 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>;
953 interconnects 942 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
954 943 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
955 interconnect-n 944 interconnect-names = "qup-core", "qup-config";
956 dmas = <&gpi_d 945 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
957 <&gpi_d 946 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
958 dma-names = "t 947 dma-names = "tx", "rx";
959 #address-cells 948 #address-cells = <1>;
960 #size-cells = 949 #size-cells = <0>;
961 status = "disa 950 status = "disabled";
962 }; 951 };
963 952
964 i2c19: i2c@890000 { 953 i2c19: i2c@890000 {
965 compatible = " 954 compatible = "qcom,geni-i2c";
966 reg = <0x0 0x0 955 reg = <0x0 0x00890000 0x0 0x4000>;
967 clock-names = 956 clock-names = "se";
968 clocks = <&gcc 957 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
969 pinctrl-names 958 pinctrl-names = "default";
970 pinctrl-0 = <& 959 pinctrl-0 = <&qup_i2c19_data_clk>;
971 interrupts = < 960 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
972 #address-cells 961 #address-cells = <1>;
973 #size-cells = 962 #size-cells = <0>;
974 interconnects 963 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
975 964 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
976 965 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
977 interconnect-n 966 interconnect-names = "qup-core", "qup-config", "qup-memory";
978 dmas = <&gpi_d 967 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
979 <&gpi_d 968 <&gpi_dma2 1 4 QCOM_GPI_I2C>;
980 dma-names = "t 969 dma-names = "tx", "rx";
981 status = "disa 970 status = "disabled";
982 }; 971 };
983 972
984 spi19: spi@890000 { 973 spi19: spi@890000 {
985 compatible = " 974 compatible = "qcom,geni-spi";
986 reg = <0 0x008 975 reg = <0 0x00890000 0 0x4000>;
987 clock-names = 976 clock-names = "se";
988 clocks = <&gcc 977 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
989 interrupts = < 978 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
990 pinctrl-names 979 pinctrl-names = "default";
991 pinctrl-0 = <& 980 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>;
992 interconnects 981 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
993 982 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
994 interconnect-n 983 interconnect-names = "qup-core", "qup-config";
995 dmas = <&gpi_d 984 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
996 <&gpi_d 985 <&gpi_dma2 1 4 QCOM_GPI_I2C>;
997 dma-names = "t 986 dma-names = "tx", "rx";
998 #address-cells 987 #address-cells = <1>;
999 #size-cells = 988 #size-cells = <0>;
1000 status = "dis 989 status = "disabled";
1001 }; 990 };
1002 991
1003 i2c20: i2c@894000 { 992 i2c20: i2c@894000 {
1004 compatible = 993 compatible = "qcom,geni-i2c";
1005 reg = <0x0 0x 994 reg = <0x0 0x00894000 0x0 0x4000>;
1006 clock-names = 995 clock-names = "se";
1007 clocks = <&gc 996 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1008 pinctrl-names 997 pinctrl-names = "default";
1009 pinctrl-0 = < 998 pinctrl-0 = <&qup_i2c20_data_clk>;
1010 interrupts = 999 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1011 #address-cell 1000 #address-cells = <1>;
1012 #size-cells = 1001 #size-cells = <0>;
1013 interconnects 1002 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1014 1003 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1015 1004 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1016 interconnect- 1005 interconnect-names = "qup-core", "qup-config", "qup-memory";
1017 dmas = <&gpi_ 1006 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1018 <&gpi_ 1007 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1019 dma-names = " 1008 dma-names = "tx", "rx";
1020 status = "dis 1009 status = "disabled";
1021 }; 1010 };
1022 1011
1023 uart20: serial@894000 1012 uart20: serial@894000 {
1024 compatible = 1013 compatible = "qcom,geni-uart";
1025 reg = <0 0x00 1014 reg = <0 0x00894000 0 0x4000>;
1026 clock-names = 1015 clock-names = "se";
1027 clocks = <&gc 1016 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1028 pinctrl-names 1017 pinctrl-names = "default";
1029 pinctrl-0 = < 1018 pinctrl-0 = <&qup_uart20_default>;
1030 interrupts = 1019 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1031 interconnects <<
1032 <<
1033 <<
1034 <<
1035 interconnect- <<
1036 <<
1037 status = "dis 1020 status = "disabled";
1038 }; 1021 };
1039 1022
1040 spi20: spi@894000 { 1023 spi20: spi@894000 {
1041 compatible = 1024 compatible = "qcom,geni-spi";
1042 reg = <0 0x00 1025 reg = <0 0x00894000 0 0x4000>;
1043 clock-names = 1026 clock-names = "se";
1044 clocks = <&gc 1027 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1045 interrupts = 1028 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1046 pinctrl-names 1029 pinctrl-names = "default";
1047 pinctrl-0 = < 1030 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>;
1048 interconnects 1031 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1049 1032 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
1050 interconnect- 1033 interconnect-names = "qup-core", "qup-config";
1051 dmas = <&gpi_ 1034 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1052 <&gpi_ 1035 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1053 dma-names = " 1036 dma-names = "tx", "rx";
1054 #address-cell 1037 #address-cells = <1>;
1055 #size-cells = 1038 #size-cells = <0>;
1056 status = "dis 1039 status = "disabled";
1057 }; 1040 };
1058 1041
1059 i2c21: i2c@898000 { 1042 i2c21: i2c@898000 {
1060 compatible = 1043 compatible = "qcom,geni-i2c";
1061 reg = <0x0 0x 1044 reg = <0x0 0x00898000 0x0 0x4000>;
1062 clock-names = 1045 clock-names = "se";
1063 clocks = <&gc 1046 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1064 pinctrl-names 1047 pinctrl-names = "default";
1065 pinctrl-0 = < 1048 pinctrl-0 = <&qup_i2c21_data_clk>;
1066 interrupts = 1049 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
1067 #address-cell 1050 #address-cells = <1>;
1068 #size-cells = 1051 #size-cells = <0>;
1069 interconnects 1052 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1070 1053 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1071 1054 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1072 interconnect- 1055 interconnect-names = "qup-core", "qup-config", "qup-memory";
1073 dmas = <&gpi_ 1056 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>,
1074 <&gpi_ 1057 <&gpi_dma2 1 6 QCOM_GPI_I2C>;
1075 dma-names = " 1058 dma-names = "tx", "rx";
1076 status = "dis 1059 status = "disabled";
1077 }; 1060 };
1078 1061
1079 spi21: spi@898000 { 1062 spi21: spi@898000 {
1080 compatible = 1063 compatible = "qcom,geni-spi";
1081 reg = <0 0x00 1064 reg = <0 0x00898000 0 0x4000>;
1082 clock-names = 1065 clock-names = "se";
1083 clocks = <&gc 1066 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1084 interrupts = 1067 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
1085 pinctrl-names 1068 pinctrl-names = "default";
1086 pinctrl-0 = < 1069 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>;
1087 interconnects 1070 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1088 1071 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
1089 interconnect- 1072 interconnect-names = "qup-core", "qup-config";
1090 dmas = <&gpi_ 1073 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>,
1091 <&gpi_ 1074 <&gpi_dma2 1 6 QCOM_GPI_SPI>;
1092 dma-names = " 1075 dma-names = "tx", "rx";
1093 #address-cell 1076 #address-cells = <1>;
1094 #size-cells = 1077 #size-cells = <0>;
1095 status = "dis 1078 status = "disabled";
1096 }; 1079 };
1097 }; 1080 };
1098 1081
1099 gpi_dma0: dma-controller@9000 1082 gpi_dma0: dma-controller@900000 {
1100 compatible = "qcom,sm 1083 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
1101 #dma-cells = <3>; 1084 #dma-cells = <3>;
1102 reg = <0 0x00900000 0 1085 reg = <0 0x00900000 0 0x60000>;
1103 interrupts = <GIC_SPI 1086 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
1104 <GIC_SPI 1087 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
1105 <GIC_SPI 1088 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
1106 <GIC_SPI 1089 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
1107 <GIC_SPI 1090 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
1108 <GIC_SPI 1091 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
1109 <GIC_SPI 1092 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
1110 <GIC_SPI 1093 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
1111 <GIC_SPI 1094 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
1112 <GIC_SPI 1095 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
1113 <GIC_SPI 1096 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
1114 <GIC_SPI 1097 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
1115 dma-channels = <12>; 1098 dma-channels = <12>;
1116 dma-channel-mask = <0 1099 dma-channel-mask = <0x7e>;
1117 iommus = <&apps_smmu 1100 iommus = <&apps_smmu 0x5b6 0x0>;
1118 status = "disabled"; 1101 status = "disabled";
1119 }; 1102 };
1120 1103
1121 qupv3_id_0: geniqup@9c0000 { 1104 qupv3_id_0: geniqup@9c0000 {
1122 compatible = "qcom,ge 1105 compatible = "qcom,geni-se-qup";
1123 reg = <0x0 0x009c0000 1106 reg = <0x0 0x009c0000 0x0 0x2000>;
1124 clock-names = "m-ahb" 1107 clock-names = "m-ahb", "s-ahb";
1125 clocks = <&gcc GCC_QU 1108 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1126 <&gcc GCC_QU 1109 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1127 iommus = <&apps_smmu 1110 iommus = <&apps_smmu 0x5a3 0x0>;
1128 interconnects = <&clk 1111 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>;
1129 interconnect-names = 1112 interconnect-names = "qup-core";
1130 #address-cells = <2>; 1113 #address-cells = <2>;
1131 #size-cells = <2>; 1114 #size-cells = <2>;
1132 ranges; 1115 ranges;
1133 status = "disabled"; 1116 status = "disabled";
1134 1117
1135 i2c0: i2c@980000 { 1118 i2c0: i2c@980000 {
1136 compatible = 1119 compatible = "qcom,geni-i2c";
1137 reg = <0x0 0x 1120 reg = <0x0 0x00980000 0x0 0x4000>;
1138 clock-names = 1121 clock-names = "se";
1139 clocks = <&gc 1122 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1140 pinctrl-names 1123 pinctrl-names = "default";
1141 pinctrl-0 = < 1124 pinctrl-0 = <&qup_i2c0_data_clk>;
1142 interrupts = 1125 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1143 #address-cell 1126 #address-cells = <1>;
1144 #size-cells = 1127 #size-cells = <0>;
1145 interconnects 1128 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1146 1129 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1147 1130 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1148 interconnect- 1131 interconnect-names = "qup-core", "qup-config", "qup-memory";
1149 dmas = <&gpi_ 1132 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1150 <&gpi_ 1133 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1151 dma-names = " 1134 dma-names = "tx", "rx";
1152 status = "dis 1135 status = "disabled";
1153 }; 1136 };
1154 1137
1155 spi0: spi@980000 { 1138 spi0: spi@980000 {
1156 compatible = 1139 compatible = "qcom,geni-spi";
1157 reg = <0x0 0x 1140 reg = <0x0 0x00980000 0x0 0x4000>;
1158 clock-names = 1141 clock-names = "se";
1159 clocks = <&gc 1142 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1160 interrupts = 1143 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1161 pinctrl-names 1144 pinctrl-names = "default";
1162 pinctrl-0 = < 1145 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1163 power-domains !! 1146 power-domains = <&rpmhpd SM8450_CX>;
1164 operating-poi 1147 operating-points-v2 = <&qup_opp_table_100mhz>;
1165 interconnects 1148 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1166 1149 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1167 1150 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1168 interconnect- 1151 interconnect-names = "qup-core", "qup-config", "qup-memory";
1169 dmas = <&gpi_ 1152 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1170 <&gpi_ 1153 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1171 dma-names = " 1154 dma-names = "tx", "rx";
1172 #address-cell 1155 #address-cells = <1>;
1173 #size-cells = 1156 #size-cells = <0>;
1174 status = "dis 1157 status = "disabled";
1175 }; 1158 };
1176 1159
1177 i2c1: i2c@984000 { 1160 i2c1: i2c@984000 {
1178 compatible = 1161 compatible = "qcom,geni-i2c";
1179 reg = <0x0 0x 1162 reg = <0x0 0x00984000 0x0 0x4000>;
1180 clock-names = 1163 clock-names = "se";
1181 clocks = <&gc 1164 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1182 pinctrl-names 1165 pinctrl-names = "default";
1183 pinctrl-0 = < 1166 pinctrl-0 = <&qup_i2c1_data_clk>;
1184 interrupts = 1167 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1185 #address-cell 1168 #address-cells = <1>;
1186 #size-cells = 1169 #size-cells = <0>;
1187 interconnects 1170 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1188 1171 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1189 1172 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1190 interconnect- 1173 interconnect-names = "qup-core", "qup-config", "qup-memory";
1191 dmas = <&gpi_ 1174 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1192 <&gpi_ 1175 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1193 dma-names = " 1176 dma-names = "tx", "rx";
1194 status = "dis 1177 status = "disabled";
1195 }; 1178 };
1196 1179
1197 spi1: spi@984000 { 1180 spi1: spi@984000 {
1198 compatible = 1181 compatible = "qcom,geni-spi";
1199 reg = <0x0 0x 1182 reg = <0x0 0x00984000 0x0 0x4000>;
1200 clock-names = 1183 clock-names = "se";
1201 clocks = <&gc 1184 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1202 interrupts = 1185 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1203 pinctrl-names 1186 pinctrl-names = "default";
1204 pinctrl-0 = < 1187 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1205 interconnects 1188 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1206 1189 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1207 1190 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1208 interconnect- 1191 interconnect-names = "qup-core", "qup-config", "qup-memory";
1209 dmas = <&gpi_ 1192 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1210 <&gpi_ 1193 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1211 dma-names = " 1194 dma-names = "tx", "rx";
1212 #address-cell 1195 #address-cells = <1>;
1213 #size-cells = 1196 #size-cells = <0>;
1214 status = "dis 1197 status = "disabled";
1215 }; 1198 };
1216 1199
1217 i2c2: i2c@988000 { 1200 i2c2: i2c@988000 {
1218 compatible = 1201 compatible = "qcom,geni-i2c";
1219 reg = <0x0 0x 1202 reg = <0x0 0x00988000 0x0 0x4000>;
1220 clock-names = 1203 clock-names = "se";
1221 clocks = <&gc 1204 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1222 pinctrl-names 1205 pinctrl-names = "default";
1223 pinctrl-0 = < 1206 pinctrl-0 = <&qup_i2c2_data_clk>;
1224 interrupts = 1207 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1225 #address-cell 1208 #address-cells = <1>;
1226 #size-cells = 1209 #size-cells = <0>;
1227 interconnects 1210 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1228 1211 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1229 1212 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1230 interconnect- 1213 interconnect-names = "qup-core", "qup-config", "qup-memory";
1231 dmas = <&gpi_ 1214 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1232 <&gpi_ 1215 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1233 dma-names = " 1216 dma-names = "tx", "rx";
1234 status = "dis 1217 status = "disabled";
1235 }; 1218 };
1236 1219
1237 spi2: spi@988000 { 1220 spi2: spi@988000 {
1238 compatible = 1221 compatible = "qcom,geni-spi";
1239 reg = <0x0 0x 1222 reg = <0x0 0x00988000 0x0 0x4000>;
1240 clock-names = 1223 clock-names = "se";
1241 clocks = <&gc 1224 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1242 interrupts = 1225 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1243 pinctrl-names 1226 pinctrl-names = "default";
1244 pinctrl-0 = < 1227 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1245 interconnects 1228 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1246 1229 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1247 1230 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1248 interconnect- 1231 interconnect-names = "qup-core", "qup-config", "qup-memory";
1249 dmas = <&gpi_ 1232 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1250 <&gpi_ 1233 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1251 dma-names = " 1234 dma-names = "tx", "rx";
1252 #address-cell 1235 #address-cells = <1>;
1253 #size-cells = 1236 #size-cells = <0>;
1254 status = "dis 1237 status = "disabled";
1255 }; 1238 };
1256 1239
1257 1240
1258 i2c3: i2c@98c000 { 1241 i2c3: i2c@98c000 {
1259 compatible = 1242 compatible = "qcom,geni-i2c";
1260 reg = <0x0 0x 1243 reg = <0x0 0x0098c000 0x0 0x4000>;
1261 clock-names = 1244 clock-names = "se";
1262 clocks = <&gc 1245 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1263 pinctrl-names 1246 pinctrl-names = "default";
1264 pinctrl-0 = < 1247 pinctrl-0 = <&qup_i2c3_data_clk>;
1265 interrupts = 1248 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1266 #address-cell 1249 #address-cells = <1>;
1267 #size-cells = 1250 #size-cells = <0>;
1268 interconnects 1251 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1269 1252 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1270 1253 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1271 interconnect- 1254 interconnect-names = "qup-core", "qup-config", "qup-memory";
1272 dmas = <&gpi_ 1255 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1273 <&gpi_ 1256 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1274 dma-names = " 1257 dma-names = "tx", "rx";
1275 status = "dis 1258 status = "disabled";
1276 }; 1259 };
1277 1260
1278 spi3: spi@98c000 { 1261 spi3: spi@98c000 {
1279 compatible = 1262 compatible = "qcom,geni-spi";
1280 reg = <0x0 0x 1263 reg = <0x0 0x0098c000 0x0 0x4000>;
1281 clock-names = 1264 clock-names = "se";
1282 clocks = <&gc 1265 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1283 interrupts = 1266 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1284 pinctrl-names 1267 pinctrl-names = "default";
1285 pinctrl-0 = < 1268 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1286 interconnects 1269 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1287 1270 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1288 1271 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1289 interconnect- 1272 interconnect-names = "qup-core", "qup-config", "qup-memory";
1290 dmas = <&gpi_ 1273 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1291 <&gpi_ 1274 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1292 dma-names = " 1275 dma-names = "tx", "rx";
1293 #address-cell 1276 #address-cells = <1>;
1294 #size-cells = 1277 #size-cells = <0>;
1295 status = "dis 1278 status = "disabled";
1296 }; 1279 };
1297 1280
1298 i2c4: i2c@990000 { 1281 i2c4: i2c@990000 {
1299 compatible = 1282 compatible = "qcom,geni-i2c";
1300 reg = <0x0 0x 1283 reg = <0x0 0x00990000 0x0 0x4000>;
1301 clock-names = 1284 clock-names = "se";
1302 clocks = <&gc 1285 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1303 pinctrl-names 1286 pinctrl-names = "default";
1304 pinctrl-0 = < 1287 pinctrl-0 = <&qup_i2c4_data_clk>;
1305 interrupts = 1288 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1306 #address-cell 1289 #address-cells = <1>;
1307 #size-cells = 1290 #size-cells = <0>;
1308 interconnects 1291 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1309 1292 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1310 1293 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1311 interconnect- 1294 interconnect-names = "qup-core", "qup-config", "qup-memory";
1312 dmas = <&gpi_ 1295 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1313 <&gpi_ 1296 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1314 dma-names = " 1297 dma-names = "tx", "rx";
1315 status = "dis 1298 status = "disabled";
1316 }; 1299 };
1317 1300
1318 spi4: spi@990000 { 1301 spi4: spi@990000 {
1319 compatible = 1302 compatible = "qcom,geni-spi";
1320 reg = <0x0 0x 1303 reg = <0x0 0x00990000 0x0 0x4000>;
1321 clock-names = 1304 clock-names = "se";
1322 clocks = <&gc 1305 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1323 interrupts = 1306 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1324 pinctrl-names 1307 pinctrl-names = "default";
1325 pinctrl-0 = < 1308 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1326 power-domains !! 1309 power-domains = <&rpmhpd SM8450_CX>;
1327 operating-poi 1310 operating-points-v2 = <&qup_opp_table_100mhz>;
1328 interconnects 1311 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1329 1312 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1330 1313 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1331 interconnect- 1314 interconnect-names = "qup-core", "qup-config", "qup-memory";
1332 dmas = <&gpi_ 1315 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1333 <&gpi_ 1316 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1334 dma-names = " 1317 dma-names = "tx", "rx";
1335 #address-cell 1318 #address-cells = <1>;
1336 #size-cells = 1319 #size-cells = <0>;
1337 status = "dis 1320 status = "disabled";
1338 }; 1321 };
1339 1322
1340 i2c5: i2c@994000 { 1323 i2c5: i2c@994000 {
1341 compatible = 1324 compatible = "qcom,geni-i2c";
1342 reg = <0x0 0x 1325 reg = <0x0 0x00994000 0x0 0x4000>;
1343 clock-names = 1326 clock-names = "se";
1344 clocks = <&gc 1327 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1345 pinctrl-names 1328 pinctrl-names = "default";
1346 pinctrl-0 = < 1329 pinctrl-0 = <&qup_i2c5_data_clk>;
1347 interrupts = 1330 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1348 #address-cell 1331 #address-cells = <1>;
1349 #size-cells = 1332 #size-cells = <0>;
1350 interconnects 1333 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1351 1334 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1352 1335 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1353 interconnect- 1336 interconnect-names = "qup-core", "qup-config", "qup-memory";
1354 dmas = <&gpi_ 1337 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1355 <&gpi_ 1338 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1356 dma-names = " 1339 dma-names = "tx", "rx";
1357 status = "dis 1340 status = "disabled";
1358 }; 1341 };
1359 1342
1360 spi5: spi@994000 { 1343 spi5: spi@994000 {
1361 compatible = 1344 compatible = "qcom,geni-spi";
1362 reg = <0x0 0x 1345 reg = <0x0 0x00994000 0x0 0x4000>;
1363 clock-names = 1346 clock-names = "se";
1364 clocks = <&gc 1347 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1365 interrupts = 1348 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1366 pinctrl-names 1349 pinctrl-names = "default";
1367 pinctrl-0 = < 1350 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1368 interconnects 1351 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1369 1352 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1370 1353 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1371 interconnect- 1354 interconnect-names = "qup-core", "qup-config", "qup-memory";
1372 dmas = <&gpi_ 1355 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1373 <&gpi_ 1356 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1374 dma-names = " 1357 dma-names = "tx", "rx";
1375 #address-cell 1358 #address-cells = <1>;
1376 #size-cells = 1359 #size-cells = <0>;
1377 status = "dis 1360 status = "disabled";
1378 }; 1361 };
1379 1362
1380 1363
1381 i2c6: i2c@998000 { 1364 i2c6: i2c@998000 {
1382 compatible = 1365 compatible = "qcom,geni-i2c";
1383 reg = <0x0 0x 1366 reg = <0x0 0x00998000 0x0 0x4000>;
1384 clock-names = 1367 clock-names = "se";
1385 clocks = <&gc 1368 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1386 pinctrl-names 1369 pinctrl-names = "default";
1387 pinctrl-0 = < 1370 pinctrl-0 = <&qup_i2c6_data_clk>;
1388 interrupts = 1371 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1389 #address-cell 1372 #address-cells = <1>;
1390 #size-cells = 1373 #size-cells = <0>;
1391 interconnects 1374 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1392 1375 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1393 1376 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1394 interconnect- 1377 interconnect-names = "qup-core", "qup-config", "qup-memory";
1395 dmas = <&gpi_ 1378 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1396 <&gpi_ 1379 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1397 dma-names = " 1380 dma-names = "tx", "rx";
1398 status = "dis 1381 status = "disabled";
1399 }; 1382 };
1400 1383
1401 spi6: spi@998000 { 1384 spi6: spi@998000 {
1402 compatible = 1385 compatible = "qcom,geni-spi";
1403 reg = <0x0 0x 1386 reg = <0x0 0x00998000 0x0 0x4000>;
1404 clock-names = 1387 clock-names = "se";
1405 clocks = <&gc 1388 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1406 interrupts = 1389 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1407 pinctrl-names 1390 pinctrl-names = "default";
1408 pinctrl-0 = < 1391 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1409 interconnects 1392 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1410 1393 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1411 1394 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1412 interconnect- 1395 interconnect-names = "qup-core", "qup-config", "qup-memory";
1413 dmas = <&gpi_ 1396 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1414 <&gpi_ 1397 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1415 dma-names = " 1398 dma-names = "tx", "rx";
1416 #address-cell 1399 #address-cells = <1>;
1417 #size-cells = 1400 #size-cells = <0>;
1418 status = "dis 1401 status = "disabled";
1419 }; 1402 };
1420 1403
1421 uart7: serial@99c000 1404 uart7: serial@99c000 {
1422 compatible = 1405 compatible = "qcom,geni-debug-uart";
1423 reg = <0 0x00 1406 reg = <0 0x0099c000 0 0x4000>;
1424 clock-names = 1407 clock-names = "se";
1425 clocks = <&gc 1408 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1426 pinctrl-names 1409 pinctrl-names = "default";
1427 pinctrl-0 = < 1410 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>;
1428 interrupts = 1411 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1429 interconnects <<
1430 <<
1431 <<
1432 <<
1433 interconnect- <<
1434 <<
1435 status = "dis 1412 status = "disabled";
1436 }; 1413 };
1437 }; 1414 };
1438 1415
1439 gpi_dma1: dma-controller@a000 1416 gpi_dma1: dma-controller@a00000 {
1440 compatible = "qcom,sm 1417 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
1441 #dma-cells = <3>; 1418 #dma-cells = <3>;
1442 reg = <0 0x00a00000 0 1419 reg = <0 0x00a00000 0 0x60000>;
1443 interrupts = <GIC_SPI 1420 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1444 <GIC_SPI 1421 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1445 <GIC_SPI 1422 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1446 <GIC_SPI 1423 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1447 <GIC_SPI 1424 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1448 <GIC_SPI 1425 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1449 <GIC_SPI 1426 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1450 <GIC_SPI 1427 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1451 <GIC_SPI 1428 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1452 <GIC_SPI 1429 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1453 <GIC_SPI 1430 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1454 <GIC_SPI 1431 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
1455 dma-channels = <12>; 1432 dma-channels = <12>;
1456 dma-channel-mask = <0 1433 dma-channel-mask = <0x7e>;
1457 iommus = <&apps_smmu 1434 iommus = <&apps_smmu 0x56 0x0>;
1458 status = "disabled"; 1435 status = "disabled";
1459 }; 1436 };
1460 1437
1461 qupv3_id_1: geniqup@ac0000 { 1438 qupv3_id_1: geniqup@ac0000 {
1462 compatible = "qcom,ge 1439 compatible = "qcom,geni-se-qup";
1463 reg = <0x0 0x00ac0000 1440 reg = <0x0 0x00ac0000 0x0 0x6000>;
1464 clock-names = "m-ahb" 1441 clock-names = "m-ahb", "s-ahb";
1465 clocks = <&gcc GCC_QU 1442 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1466 <&gcc GCC_QU 1443 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1467 iommus = <&apps_smmu 1444 iommus = <&apps_smmu 0x43 0x0>;
1468 interconnects = <&clk 1445 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>;
1469 interconnect-names = 1446 interconnect-names = "qup-core";
1470 #address-cells = <2>; 1447 #address-cells = <2>;
1471 #size-cells = <2>; 1448 #size-cells = <2>;
1472 ranges; 1449 ranges;
1473 status = "disabled"; 1450 status = "disabled";
1474 1451
1475 i2c8: i2c@a80000 { 1452 i2c8: i2c@a80000 {
1476 compatible = 1453 compatible = "qcom,geni-i2c";
1477 reg = <0x0 0x 1454 reg = <0x0 0x00a80000 0x0 0x4000>;
1478 clock-names = 1455 clock-names = "se";
1479 clocks = <&gc 1456 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1480 pinctrl-names 1457 pinctrl-names = "default";
1481 pinctrl-0 = < 1458 pinctrl-0 = <&qup_i2c8_data_clk>;
1482 interrupts = 1459 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1483 #address-cell 1460 #address-cells = <1>;
1484 #size-cells = 1461 #size-cells = <0>;
1485 interconnects 1462 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1486 1463 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1487 1464 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1488 interconnect- 1465 interconnect-names = "qup-core", "qup-config", "qup-memory";
1489 dmas = <&gpi_ 1466 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1490 <&gpi_ 1467 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1491 dma-names = " 1468 dma-names = "tx", "rx";
1492 status = "dis 1469 status = "disabled";
1493 }; 1470 };
1494 1471
1495 spi8: spi@a80000 { 1472 spi8: spi@a80000 {
1496 compatible = 1473 compatible = "qcom,geni-spi";
1497 reg = <0x0 0x 1474 reg = <0x0 0x00a80000 0x0 0x4000>;
1498 clock-names = 1475 clock-names = "se";
1499 clocks = <&gc 1476 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1500 interrupts = 1477 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1501 pinctrl-names 1478 pinctrl-names = "default";
1502 pinctrl-0 = < 1479 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1503 interconnects 1480 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1504 1481 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1505 1482 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1506 interconnect- 1483 interconnect-names = "qup-core", "qup-config", "qup-memory";
1507 dmas = <&gpi_ 1484 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1508 <&gpi_ 1485 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1509 dma-names = " 1486 dma-names = "tx", "rx";
1510 #address-cell 1487 #address-cells = <1>;
1511 #size-cells = 1488 #size-cells = <0>;
1512 status = "dis 1489 status = "disabled";
1513 }; 1490 };
1514 1491
1515 i2c9: i2c@a84000 { 1492 i2c9: i2c@a84000 {
1516 compatible = 1493 compatible = "qcom,geni-i2c";
1517 reg = <0x0 0x 1494 reg = <0x0 0x00a84000 0x0 0x4000>;
1518 clock-names = 1495 clock-names = "se";
1519 clocks = <&gc 1496 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1520 pinctrl-names 1497 pinctrl-names = "default";
1521 pinctrl-0 = < 1498 pinctrl-0 = <&qup_i2c9_data_clk>;
1522 interrupts = 1499 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1523 #address-cell 1500 #address-cells = <1>;
1524 #size-cells = 1501 #size-cells = <0>;
1525 interconnects 1502 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1526 1503 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1527 1504 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1528 interconnect- 1505 interconnect-names = "qup-core", "qup-config", "qup-memory";
1529 dmas = <&gpi_ 1506 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1530 <&gpi_ 1507 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1531 dma-names = " 1508 dma-names = "tx", "rx";
1532 status = "dis 1509 status = "disabled";
1533 }; 1510 };
1534 1511
1535 spi9: spi@a84000 { 1512 spi9: spi@a84000 {
1536 compatible = 1513 compatible = "qcom,geni-spi";
1537 reg = <0x0 0x 1514 reg = <0x0 0x00a84000 0x0 0x4000>;
1538 clock-names = 1515 clock-names = "se";
1539 clocks = <&gc 1516 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1540 interrupts = 1517 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1541 pinctrl-names 1518 pinctrl-names = "default";
1542 pinctrl-0 = < 1519 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1543 interconnects 1520 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1544 1521 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1545 1522 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1546 interconnect- 1523 interconnect-names = "qup-core", "qup-config", "qup-memory";
1547 dmas = <&gpi_ 1524 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1548 <&gpi_ 1525 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1549 dma-names = " 1526 dma-names = "tx", "rx";
1550 #address-cell 1527 #address-cells = <1>;
1551 #size-cells = 1528 #size-cells = <0>;
1552 status = "dis 1529 status = "disabled";
1553 }; 1530 };
1554 1531
1555 i2c10: i2c@a88000 { 1532 i2c10: i2c@a88000 {
1556 compatible = 1533 compatible = "qcom,geni-i2c";
1557 reg = <0x0 0x 1534 reg = <0x0 0x00a88000 0x0 0x4000>;
1558 clock-names = 1535 clock-names = "se";
1559 clocks = <&gc 1536 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1560 pinctrl-names 1537 pinctrl-names = "default";
1561 pinctrl-0 = < 1538 pinctrl-0 = <&qup_i2c10_data_clk>;
1562 interrupts = 1539 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1563 #address-cell 1540 #address-cells = <1>;
1564 #size-cells = 1541 #size-cells = <0>;
1565 interconnects 1542 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1566 1543 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1567 1544 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1568 interconnect- 1545 interconnect-names = "qup-core", "qup-config", "qup-memory";
1569 dmas = <&gpi_ 1546 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1570 <&gpi_ 1547 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1571 dma-names = " 1548 dma-names = "tx", "rx";
1572 status = "dis 1549 status = "disabled";
1573 }; 1550 };
1574 1551
1575 spi10: spi@a88000 { 1552 spi10: spi@a88000 {
1576 compatible = 1553 compatible = "qcom,geni-spi";
1577 reg = <0x0 0x 1554 reg = <0x0 0x00a88000 0x0 0x4000>;
1578 clock-names = 1555 clock-names = "se";
1579 clocks = <&gc 1556 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1580 interrupts = 1557 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1581 pinctrl-names 1558 pinctrl-names = "default";
1582 pinctrl-0 = < 1559 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1583 interconnects 1560 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1584 1561 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1585 1562 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1586 interconnect- 1563 interconnect-names = "qup-core", "qup-config", "qup-memory";
1587 dmas = <&gpi_ 1564 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1588 <&gpi_ 1565 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1589 dma-names = " 1566 dma-names = "tx", "rx";
1590 #address-cell 1567 #address-cells = <1>;
1591 #size-cells = 1568 #size-cells = <0>;
1592 status = "dis 1569 status = "disabled";
1593 }; 1570 };
1594 1571
1595 i2c11: i2c@a8c000 { 1572 i2c11: i2c@a8c000 {
1596 compatible = 1573 compatible = "qcom,geni-i2c";
1597 reg = <0x0 0x 1574 reg = <0x0 0x00a8c000 0x0 0x4000>;
1598 clock-names = 1575 clock-names = "se";
1599 clocks = <&gc 1576 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1600 pinctrl-names 1577 pinctrl-names = "default";
1601 pinctrl-0 = < 1578 pinctrl-0 = <&qup_i2c11_data_clk>;
1602 interrupts = 1579 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1603 #address-cell 1580 #address-cells = <1>;
1604 #size-cells = 1581 #size-cells = <0>;
1605 interconnects 1582 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1606 1583 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1607 1584 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1608 interconnect- 1585 interconnect-names = "qup-core", "qup-config", "qup-memory";
1609 dmas = <&gpi_ 1586 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1610 <&gpi_ 1587 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1611 dma-names = " 1588 dma-names = "tx", "rx";
1612 status = "dis 1589 status = "disabled";
1613 }; 1590 };
1614 1591
1615 spi11: spi@a8c000 { 1592 spi11: spi@a8c000 {
1616 compatible = 1593 compatible = "qcom,geni-spi";
1617 reg = <0x0 0x 1594 reg = <0x0 0x00a8c000 0x0 0x4000>;
1618 clock-names = 1595 clock-names = "se";
1619 clocks = <&gc 1596 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1620 interrupts = 1597 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1621 pinctrl-names 1598 pinctrl-names = "default";
1622 pinctrl-0 = < 1599 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1623 interconnects 1600 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1624 1601 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1625 1602 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1626 interconnect- 1603 interconnect-names = "qup-core", "qup-config", "qup-memory";
1627 dmas = <&gpi_ 1604 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1628 <&gpi_ 1605 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1629 dma-names = " 1606 dma-names = "tx", "rx";
1630 #address-cell 1607 #address-cells = <1>;
1631 #size-cells = 1608 #size-cells = <0>;
1632 status = "dis 1609 status = "disabled";
1633 }; 1610 };
1634 1611
1635 i2c12: i2c@a90000 { 1612 i2c12: i2c@a90000 {
1636 compatible = 1613 compatible = "qcom,geni-i2c";
1637 reg = <0x0 0x 1614 reg = <0x0 0x00a90000 0x0 0x4000>;
1638 clock-names = 1615 clock-names = "se";
1639 clocks = <&gc 1616 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1640 pinctrl-names 1617 pinctrl-names = "default";
1641 pinctrl-0 = < 1618 pinctrl-0 = <&qup_i2c12_data_clk>;
1642 interrupts = 1619 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1643 #address-cell 1620 #address-cells = <1>;
1644 #size-cells = 1621 #size-cells = <0>;
1645 interconnects 1622 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1646 1623 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1647 1624 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1648 interconnect- 1625 interconnect-names = "qup-core", "qup-config", "qup-memory";
1649 dmas = <&gpi_ 1626 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1650 <&gpi_ 1627 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1651 dma-names = " 1628 dma-names = "tx", "rx";
1652 status = "dis 1629 status = "disabled";
1653 }; 1630 };
1654 1631
1655 spi12: spi@a90000 { 1632 spi12: spi@a90000 {
1656 compatible = 1633 compatible = "qcom,geni-spi";
1657 reg = <0x0 0x 1634 reg = <0x0 0x00a90000 0x0 0x4000>;
1658 clock-names = 1635 clock-names = "se";
1659 clocks = <&gc 1636 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1660 interrupts = 1637 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1661 pinctrl-names 1638 pinctrl-names = "default";
1662 pinctrl-0 = < 1639 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1663 interconnects 1640 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1664 1641 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1665 1642 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1666 interconnect- 1643 interconnect-names = "qup-core", "qup-config", "qup-memory";
1667 dmas = <&gpi_ 1644 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1668 <&gpi_ 1645 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1669 dma-names = " 1646 dma-names = "tx", "rx";
1670 #address-cell 1647 #address-cells = <1>;
1671 #size-cells = 1648 #size-cells = <0>;
1672 status = "dis 1649 status = "disabled";
1673 }; 1650 };
1674 1651
1675 i2c13: i2c@a94000 { 1652 i2c13: i2c@a94000 {
1676 compatible = 1653 compatible = "qcom,geni-i2c";
1677 reg = <0 0x00 1654 reg = <0 0x00a94000 0 0x4000>;
1678 clock-names = 1655 clock-names = "se";
1679 clocks = <&gc 1656 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1680 pinctrl-names 1657 pinctrl-names = "default";
1681 pinctrl-0 = < 1658 pinctrl-0 = <&qup_i2c13_data_clk>;
1682 interrupts = 1659 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1683 interconnects 1660 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1684 1661 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1685 1662 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1686 interconnect- 1663 interconnect-names = "qup-core", "qup-config", "qup-memory";
1687 dmas = <&gpi_ 1664 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1688 <&gpi_ 1665 <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1689 dma-names = " 1666 dma-names = "tx", "rx";
1690 #address-cell 1667 #address-cells = <1>;
1691 #size-cells = 1668 #size-cells = <0>;
1692 status = "dis 1669 status = "disabled";
1693 }; 1670 };
1694 1671
1695 spi13: spi@a94000 { 1672 spi13: spi@a94000 {
1696 compatible = 1673 compatible = "qcom,geni-spi";
1697 reg = <0x0 0x 1674 reg = <0x0 0x00a94000 0x0 0x4000>;
1698 clock-names = 1675 clock-names = "se";
1699 clocks = <&gc 1676 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1700 interrupts = 1677 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1701 pinctrl-names 1678 pinctrl-names = "default";
1702 pinctrl-0 = < 1679 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1703 interconnects 1680 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1704 1681 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1705 1682 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1706 interconnect- 1683 interconnect-names = "qup-core", "qup-config", "qup-memory";
1707 dmas = <&gpi_ 1684 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1708 <&gpi_ 1685 <&gpi_dma1 1 5 QCOM_GPI_SPI>;
1709 dma-names = " 1686 dma-names = "tx", "rx";
1710 #address-cell 1687 #address-cells = <1>;
1711 #size-cells = 1688 #size-cells = <0>;
1712 status = "dis 1689 status = "disabled";
1713 }; 1690 };
1714 1691
1715 i2c14: i2c@a98000 { 1692 i2c14: i2c@a98000 {
1716 compatible = 1693 compatible = "qcom,geni-i2c";
1717 reg = <0 0x00 1694 reg = <0 0x00a98000 0 0x4000>;
1718 clock-names = 1695 clock-names = "se";
1719 clocks = <&gc 1696 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1720 pinctrl-names 1697 pinctrl-names = "default";
1721 pinctrl-0 = < 1698 pinctrl-0 = <&qup_i2c14_data_clk>;
1722 interrupts = 1699 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
1723 interconnects 1700 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1724 1701 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1725 1702 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1726 interconnect- 1703 interconnect-names = "qup-core", "qup-config", "qup-memory";
1727 dmas = <&gpi_ 1704 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
1728 <&gpi_ 1705 <&gpi_dma1 1 6 QCOM_GPI_I2C>;
1729 dma-names = " 1706 dma-names = "tx", "rx";
1730 #address-cell 1707 #address-cells = <1>;
1731 #size-cells = 1708 #size-cells = <0>;
1732 status = "dis 1709 status = "disabled";
1733 }; 1710 };
1734 1711
1735 spi14: spi@a98000 { 1712 spi14: spi@a98000 {
1736 compatible = 1713 compatible = "qcom,geni-spi";
1737 reg = <0x0 0x 1714 reg = <0x0 0x00a98000 0x0 0x4000>;
1738 clock-names = 1715 clock-names = "se";
1739 clocks = <&gc 1716 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1740 interrupts = 1717 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
1741 pinctrl-names 1718 pinctrl-names = "default";
1742 pinctrl-0 = < 1719 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
1743 interconnects 1720 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1744 1721 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1745 1722 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1746 interconnect- 1723 interconnect-names = "qup-core", "qup-config", "qup-memory";
1747 dmas = <&gpi_ 1724 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
1748 <&gpi_ 1725 <&gpi_dma1 1 6 QCOM_GPI_SPI>;
1749 dma-names = " 1726 dma-names = "tx", "rx";
1750 #address-cell 1727 #address-cells = <1>;
1751 #size-cells = 1728 #size-cells = <0>;
1752 status = "dis 1729 status = "disabled";
1753 }; 1730 };
1754 }; 1731 };
1755 1732
1756 rng: rng@10c3000 { !! 1733 pcie0: pci@1c00000 {
1757 compatible = "qcom,sm <<
1758 reg = <0 0x010c3000 0 <<
1759 }; <<
1760 <<
1761 pcie0: pcie@1c00000 { <<
1762 compatible = "qcom,pc 1734 compatible = "qcom,pcie-sm8450-pcie0";
1763 reg = <0 0x01c00000 0 1735 reg = <0 0x01c00000 0 0x3000>,
1764 <0 0x60000000 0 1736 <0 0x60000000 0 0xf1d>,
1765 <0 0x60000f20 0 1737 <0 0x60000f20 0 0xa8>,
1766 <0 0x60001000 0 1738 <0 0x60001000 0 0x1000>,
1767 <0 0x60100000 0 1739 <0 0x60100000 0 0x100000>;
1768 reg-names = "parf", " 1740 reg-names = "parf", "dbi", "elbi", "atu", "config";
1769 device_type = "pci"; 1741 device_type = "pci";
1770 linux,pci-domain = <0 1742 linux,pci-domain = <0>;
1771 bus-range = <0x00 0xf 1743 bus-range = <0x00 0xff>;
1772 num-lanes = <1>; 1744 num-lanes = <1>;
1773 1745
1774 #address-cells = <3>; 1746 #address-cells = <3>;
1775 #size-cells = <2>; 1747 #size-cells = <2>;
1776 1748
1777 ranges = <0x01000000 1749 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
1778 <0x02000000 1750 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1779 1751
1780 msi-map = <0x0 &gic_i !! 1752 /*
1781 <0x100 &gic !! 1753 * MSIs for BDF (1:0.0) only works with Device ID 0x5980.
>> 1754 * Hence, the IDs are swapped.
>> 1755 */
>> 1756 msi-map = <0x0 &gic_its 0x5981 0x1>,
>> 1757 <0x100 &gic_its 0x5980 0x1>;
1782 msi-map-mask = <0xff0 1758 msi-map-mask = <0xff00>;
1783 interrupts = <GIC_SPI !! 1759 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
1784 <GIC_SPI !! 1760 interrupt-names = "msi";
1785 <GIC_SPI <<
1786 <GIC_SPI <<
1787 <GIC_SPI <<
1788 <GIC_SPI <<
1789 <GIC_SPI <<
1790 <GIC_SPI <<
1791 interrupt-names = "ms <<
1792 "ms <<
1793 "ms <<
1794 "ms <<
1795 "ms <<
1796 "ms <<
1797 "ms <<
1798 "ms <<
1799 #interrupt-cells = <1 1761 #interrupt-cells = <1>;
1800 interrupt-map-mask = 1762 interrupt-map-mask = <0 0 0 0x7>;
1801 interrupt-map = <0 0 1763 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1802 <0 0 1764 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1803 <0 0 1765 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1804 <0 0 1766 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1805 1767
1806 interconnects = <&pci <<
1807 &mc_ <<
1808 <&gem <<
1809 &con <<
1810 interconnect-names = <<
1811 <<
1812 clocks = <&gcc GCC_PC 1768 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1813 <&gcc GCC_PC 1769 <&gcc GCC_PCIE_0_PIPE_CLK_SRC>,
1814 <&pcie0_phy> !! 1770 <&pcie0_lane>,
1815 <&rpmhcc RPM 1771 <&rpmhcc RPMH_CXO_CLK>,
1816 <&gcc GCC_PC 1772 <&gcc GCC_PCIE_0_AUX_CLK>,
1817 <&gcc GCC_PC 1773 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1818 <&gcc GCC_PC 1774 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1819 <&gcc GCC_PC 1775 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1820 <&gcc GCC_PC 1776 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
1821 <&gcc GCC_DD 1777 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1822 <&gcc GCC_AG 1778 <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
1823 <&gcc GCC_AG 1779 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
1824 clock-names = "pipe", 1780 clock-names = "pipe",
1825 "pipe_m 1781 "pipe_mux",
1826 "phy_pi 1782 "phy_pipe",
1827 "ref", 1783 "ref",
1828 "aux", 1784 "aux",
1829 "cfg", 1785 "cfg",
1830 "bus_ma 1786 "bus_master",
1831 "bus_sl 1787 "bus_slave",
1832 "slave_ 1788 "slave_q2a",
1833 "ddrss_ 1789 "ddrss_sf_tbu",
1834 "aggre0 1790 "aggre0",
1835 "aggre1 1791 "aggre1";
1836 1792
>> 1793 iommus = <&apps_smmu 0x1c00 0x7f>;
1837 iommu-map = <0x0 &a 1794 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
1838 <0x100 &a 1795 <0x100 &apps_smmu 0x1c01 0x1>;
1839 1796
1840 resets = <&gcc GCC_PC 1797 resets = <&gcc GCC_PCIE_0_BCR>;
1841 reset-names = "pci"; 1798 reset-names = "pci";
1842 1799
1843 power-domains = <&gcc 1800 power-domains = <&gcc PCIE_0_GDSC>;
>> 1801 power-domain-names = "gdsc";
1844 1802
1845 phys = <&pcie0_phy>; !! 1803 phys = <&pcie0_lane>;
1846 phy-names = "pciephy" 1804 phy-names = "pciephy";
1847 1805
1848 perst-gpios = <&tlmm 1806 perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
1849 wake-gpios = <&tlmm 9 1807 wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
1850 1808
1851 pinctrl-names = "defa 1809 pinctrl-names = "default";
1852 pinctrl-0 = <&pcie0_d 1810 pinctrl-0 = <&pcie0_default_state>;
1853 1811
1854 operating-points-v2 = <<
1855 <<
1856 status = "disabled"; 1812 status = "disabled";
1857 <<
1858 pcie0_opp_table: opp- <<
1859 compatible = <<
1860 <<
1861 /* GEN 1 x1 * <<
1862 opp-2500000 { <<
1863 opp-h <<
1864 requi <<
1865 opp-p <<
1866 }; <<
1867 <<
1868 /* GEN 2 x1 * <<
1869 opp-5000000 { <<
1870 opp-h <<
1871 requi <<
1872 opp-p <<
1873 }; <<
1874 <<
1875 /* GEN 3 x1 * <<
1876 opp-8000000 { <<
1877 opp-h <<
1878 requi <<
1879 opp-p <<
1880 }; <<
1881 }; <<
1882 <<
1883 pcie@0 { <<
1884 device_type = <<
1885 reg = <0x0 0x <<
1886 bus-range = < <<
1887 <<
1888 #address-cell <<
1889 #size-cells = <<
1890 ranges; <<
1891 }; <<
1892 }; 1813 };
1893 1814
1894 pcie0_phy: phy@1c06000 { 1815 pcie0_phy: phy@1c06000 {
1895 compatible = "qcom,sm 1816 compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy";
1896 reg = <0 0x01c06000 0 !! 1817 reg = <0 0x01c06000 0 0x200>;
1897 !! 1818 #address-cells = <2>;
>> 1819 #size-cells = <2>;
>> 1820 ranges;
1898 clocks = <&gcc GCC_PC 1821 clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
1899 <&gcc GCC_PC 1822 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1900 <&gcc GCC_PC 1823 <&gcc GCC_PCIE_0_CLKREF_EN>,
1901 <&gcc GCC_PC !! 1824 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
1902 <&gcc GCC_PC !! 1825 clock-names = "aux", "cfg_ahb", "ref", "refgen";
1903 clock-names = "aux", <<
1904 "cfg_ah <<
1905 "ref", <<
1906 "rchng" <<
1907 "pipe"; <<
1908 <<
1909 clock-output-names = <<
1910 #clock-cells = <0>; <<
1911 <<
1912 #phy-cells = <0>; <<
1913 1826
1914 resets = <&gcc GCC_PC 1827 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1915 reset-names = "phy"; 1828 reset-names = "phy";
1916 1829
1917 assigned-clocks = <&g 1830 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
1918 assigned-clock-rates 1831 assigned-clock-rates = <100000000>;
1919 1832
1920 status = "disabled"; 1833 status = "disabled";
>> 1834
>> 1835 pcie0_lane: phy@1c06200 {
>> 1836 reg = <0 0x01c06e00 0 0x200>, /* tx */
>> 1837 <0 0x01c07000 0 0x200>, /* rx */
>> 1838 <0 0x01c06200 0 0x200>, /* pcs */
>> 1839 <0 0x01c06600 0 0x200>; /* pcs_pcie */
>> 1840 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
>> 1841 clock-names = "pipe0";
>> 1842
>> 1843 #clock-cells = <0>;
>> 1844 #phy-cells = <0>;
>> 1845 clock-output-names = "pcie_0_pipe_clk";
>> 1846 };
1921 }; 1847 };
1922 1848
1923 pcie1: pcie@1c08000 { !! 1849 pcie1: pci@1c08000 {
1924 compatible = "qcom,pc 1850 compatible = "qcom,pcie-sm8450-pcie1";
1925 reg = <0 0x01c08000 0 1851 reg = <0 0x01c08000 0 0x3000>,
1926 <0 0x40000000 0 1852 <0 0x40000000 0 0xf1d>,
1927 <0 0x40000f20 0 1853 <0 0x40000f20 0 0xa8>,
1928 <0 0x40001000 0 1854 <0 0x40001000 0 0x1000>,
1929 <0 0x40100000 0 1855 <0 0x40100000 0 0x100000>;
1930 reg-names = "parf", " 1856 reg-names = "parf", "dbi", "elbi", "atu", "config";
1931 device_type = "pci"; 1857 device_type = "pci";
1932 linux,pci-domain = <1 1858 linux,pci-domain = <1>;
1933 bus-range = <0x00 0xf 1859 bus-range = <0x00 0xff>;
1934 num-lanes = <2>; 1860 num-lanes = <2>;
1935 1861
1936 #address-cells = <3>; 1862 #address-cells = <3>;
1937 #size-cells = <2>; 1863 #size-cells = <2>;
1938 1864
1939 ranges = <0x01000000 1865 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
1940 <0x02000000 1866 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1941 1867
1942 msi-map = <0x0 &gic_i !! 1868 /*
1943 <0x100 &gic !! 1869 * MSIs for BDF (1:0.0) only works with Device ID 0x5a00.
>> 1870 * Hence, the IDs are swapped.
>> 1871 */
>> 1872 msi-map = <0x0 &gic_its 0x5a01 0x1>,
>> 1873 <0x100 &gic_its 0x5a00 0x1>;
1944 msi-map-mask = <0xff0 1874 msi-map-mask = <0xff00>;
1945 interrupts = <GIC_SPI !! 1875 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
1946 <GIC_SPI !! 1876 interrupt-names = "msi";
1947 <GIC_SPI <<
1948 <GIC_SPI <<
1949 <GIC_SPI <<
1950 <GIC_SPI <<
1951 <GIC_SPI <<
1952 <GIC_SPI <<
1953 interrupt-names = "ms <<
1954 "ms <<
1955 "ms <<
1956 "ms <<
1957 "ms <<
1958 "ms <<
1959 "ms <<
1960 "ms <<
1961 #interrupt-cells = <1 1877 #interrupt-cells = <1>;
1962 interrupt-map-mask = 1878 interrupt-map-mask = <0 0 0 0x7>;
1963 interrupt-map = <0 0 1879 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1964 <0 0 1880 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1965 <0 0 1881 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1966 <0 0 1882 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1967 1883
1968 interconnects = <&pci <<
1969 &mc_ <<
1970 <&gem <<
1971 &con <<
1972 interconnect-names = <<
1973 <<
1974 clocks = <&gcc GCC_PC 1884 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1975 <&gcc GCC_PC 1885 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>,
1976 <&pcie1_phy !! 1886 <&pcie1_lane>,
1977 <&rpmhcc RPM 1887 <&rpmhcc RPMH_CXO_CLK>,
1978 <&gcc GCC_PC 1888 <&gcc GCC_PCIE_1_AUX_CLK>,
1979 <&gcc GCC_PC 1889 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1980 <&gcc GCC_PC 1890 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1981 <&gcc GCC_PC 1891 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
1982 <&gcc GCC_PC 1892 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
1983 <&gcc GCC_DD 1893 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1984 <&gcc GCC_AG 1894 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
1985 clock-names = "pipe", 1895 clock-names = "pipe",
1986 "pipe_m 1896 "pipe_mux",
1987 "phy_pi 1897 "phy_pipe",
1988 "ref", 1898 "ref",
1989 "aux", 1899 "aux",
1990 "cfg", 1900 "cfg",
1991 "bus_ma 1901 "bus_master",
1992 "bus_sl 1902 "bus_slave",
1993 "slave_ 1903 "slave_q2a",
1994 "ddrss_ 1904 "ddrss_sf_tbu",
1995 "aggre1 1905 "aggre1";
1996 1906
>> 1907 iommus = <&apps_smmu 0x1c80 0x7f>;
1997 iommu-map = <0x0 &a 1908 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
1998 <0x100 &a 1909 <0x100 &apps_smmu 0x1c81 0x1>;
1999 1910
2000 resets = <&gcc GCC_PC 1911 resets = <&gcc GCC_PCIE_1_BCR>;
2001 reset-names = "pci"; 1912 reset-names = "pci";
2002 1913
2003 power-domains = <&gcc 1914 power-domains = <&gcc PCIE_1_GDSC>;
>> 1915 power-domain-names = "gdsc";
2004 1916
2005 phys = <&pcie1_phy>; !! 1917 phys = <&pcie1_lane>;
2006 phy-names = "pciephy" 1918 phy-names = "pciephy";
2007 1919
2008 perst-gpios = <&tlmm 1920 perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
2009 wake-gpios = <&tlmm 9 1921 wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
2010 1922
2011 pinctrl-names = "defa 1923 pinctrl-names = "default";
2012 pinctrl-0 = <&pcie1_d 1924 pinctrl-0 = <&pcie1_default_state>;
2013 1925
2014 operating-points-v2 = <<
2015 <<
2016 status = "disabled"; 1926 status = "disabled";
2017 <<
2018 pcie1_opp_table: opp- <<
2019 compatible = <<
2020 <<
2021 /* GEN 1 x1 * <<
2022 opp-2500000 { <<
2023 opp-h <<
2024 requi <<
2025 opp-p <<
2026 }; <<
2027 <<
2028 /* GEN 1 x2 a <<
2029 opp-5000000 { <<
2030 opp-h <<
2031 requi <<
2032 opp-p <<
2033 }; <<
2034 <<
2035 /* GEN 2 x2 * <<
2036 opp-10000000 <<
2037 opp-h <<
2038 requi <<
2039 opp-p <<
2040 }; <<
2041 <<
2042 /* GEN 3 x1 * <<
2043 opp-8000000 { <<
2044 opp-h <<
2045 requi <<
2046 opp-p <<
2047 }; <<
2048 <<
2049 /* GEN 3 x2 a <<
2050 opp-16000000 <<
2051 opp-h <<
2052 requi <<
2053 opp-p <<
2054 }; <<
2055 <<
2056 /* GEN 4 x2 * <<
2057 opp-32000000 <<
2058 opp-h <<
2059 requi <<
2060 opp-p <<
2061 }; <<
2062 }; <<
2063 <<
2064 pcie@0 { <<
2065 device_type = <<
2066 reg = <0x0 0x <<
2067 bus-range = < <<
2068 <<
2069 #address-cell <<
2070 #size-cells = <<
2071 ranges; <<
2072 }; <<
2073 }; 1927 };
2074 1928
2075 pcie1_phy: phy@1c0e000 { !! 1929 pcie1_phy: phy@1c0f000 {
2076 compatible = "qcom,sm 1930 compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy";
2077 reg = <0 0x01c0e000 0 !! 1931 reg = <0 0x01c0f000 0 0x200>;
2078 !! 1932 #address-cells = <2>;
>> 1933 #size-cells = <2>;
>> 1934 ranges;
2079 clocks = <&gcc GCC_PC 1935 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>,
2080 <&gcc GCC_PC 1936 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2081 <&gcc GCC_PC 1937 <&gcc GCC_PCIE_1_CLKREF_EN>,
2082 <&gcc GCC_PC !! 1938 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
2083 <&gcc GCC_PC !! 1939 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2084 clock-names = "aux", <<
2085 "cfg_ah <<
2086 "ref", <<
2087 "rchng" <<
2088 "pipe"; <<
2089 <<
2090 clock-output-names = <<
2091 #clock-cells = <1>; <<
2092 <<
2093 #phy-cells = <0>; <<
2094 1940
2095 resets = <&gcc GCC_PC 1941 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2096 reset-names = "phy"; 1942 reset-names = "phy";
2097 1943
2098 assigned-clocks = <&g 1944 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
2099 assigned-clock-rates 1945 assigned-clock-rates = <100000000>;
2100 1946
2101 status = "disabled"; 1947 status = "disabled";
>> 1948
>> 1949 pcie1_lane: phy@1c0e000 {
>> 1950 reg = <0 0x01c0e000 0 0x200>, /* tx */
>> 1951 <0 0x01c0e200 0 0x300>, /* rx */
>> 1952 <0 0x01c0f200 0 0x200>, /* pcs */
>> 1953 <0 0x01c0e800 0 0x200>, /* tx */
>> 1954 <0 0x01c0ea00 0 0x300>, /* rx */
>> 1955 <0 0x01c0f400 0 0xc00>; /* pcs_pcie */
>> 1956 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
>> 1957 clock-names = "pipe0";
>> 1958
>> 1959 #clock-cells = <0>;
>> 1960 #phy-cells = <0>;
>> 1961 clock-output-names = "pcie_1_pipe_clk";
>> 1962 };
2102 }; 1963 };
2103 1964
2104 config_noc: interconnect@1500 1965 config_noc: interconnect@1500000 {
2105 compatible = "qcom,sm 1966 compatible = "qcom,sm8450-config-noc";
2106 reg = <0 0x01500000 0 1967 reg = <0 0x01500000 0 0x1c000>;
2107 #interconnect-cells = 1968 #interconnect-cells = <2>;
2108 qcom,bcm-voters = <&a 1969 qcom,bcm-voters = <&apps_bcm_voter>;
2109 }; 1970 };
2110 1971
2111 system_noc: interconnect@1680 1972 system_noc: interconnect@1680000 {
2112 compatible = "qcom,sm 1973 compatible = "qcom,sm8450-system-noc";
2113 reg = <0 0x01680000 0 1974 reg = <0 0x01680000 0 0x1e200>;
2114 #interconnect-cells = 1975 #interconnect-cells = <2>;
2115 qcom,bcm-voters = <&a 1976 qcom,bcm-voters = <&apps_bcm_voter>;
2116 }; 1977 };
2117 1978
2118 pcie_noc: interconnect@16c000 1979 pcie_noc: interconnect@16c0000 {
2119 compatible = "qcom,sm 1980 compatible = "qcom,sm8450-pcie-anoc";
2120 reg = <0 0x016c0000 0 1981 reg = <0 0x016c0000 0 0xe280>;
2121 #interconnect-cells = 1982 #interconnect-cells = <2>;
2122 qcom,bcm-voters = <&a 1983 qcom,bcm-voters = <&apps_bcm_voter>;
2123 }; 1984 };
2124 1985
2125 aggre1_noc: interconnect@16e0 1986 aggre1_noc: interconnect@16e0000 {
2126 compatible = "qcom,sm 1987 compatible = "qcom,sm8450-aggre1-noc";
2127 reg = <0 0x016e0000 0 1988 reg = <0 0x016e0000 0 0x1c080>;
2128 #interconnect-cells = 1989 #interconnect-cells = <2>;
2129 clocks = <&gcc GCC_AG 1990 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2130 <&gcc GCC_AG 1991 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
2131 qcom,bcm-voters = <&a 1992 qcom,bcm-voters = <&apps_bcm_voter>;
2132 }; 1993 };
2133 1994
2134 aggre2_noc: interconnect@1700 1995 aggre2_noc: interconnect@1700000 {
2135 compatible = "qcom,sm 1996 compatible = "qcom,sm8450-aggre2-noc";
2136 reg = <0 0x01700000 0 1997 reg = <0 0x01700000 0 0x31080>;
2137 #interconnect-cells = 1998 #interconnect-cells = <2>;
2138 qcom,bcm-voters = <&a 1999 qcom,bcm-voters = <&apps_bcm_voter>;
2139 clocks = <&gcc GCC_AG 2000 clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
2140 <&gcc GCC_AG 2001 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
2141 <&gcc GCC_AG 2002 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2142 <&rpmhcc RPM 2003 <&rpmhcc RPMH_IPA_CLK>;
2143 }; 2004 };
2144 2005
2145 mmss_noc: interconnect@174000 2006 mmss_noc: interconnect@1740000 {
2146 compatible = "qcom,sm 2007 compatible = "qcom,sm8450-mmss-noc";
2147 reg = <0 0x01740000 0 2008 reg = <0 0x01740000 0 0x1f080>;
2148 #interconnect-cells = 2009 #interconnect-cells = <2>;
2149 qcom,bcm-voters = <&a 2010 qcom,bcm-voters = <&apps_bcm_voter>;
2150 }; 2011 };
2151 2012
2152 tcsr_mutex: hwlock@1f40000 { 2013 tcsr_mutex: hwlock@1f40000 {
2153 compatible = "qcom,tc 2014 compatible = "qcom,tcsr-mutex";
2154 reg = <0x0 0x01f40000 2015 reg = <0x0 0x01f40000 0x0 0x40000>;
2155 #hwlock-cells = <1>; 2016 #hwlock-cells = <1>;
2156 }; 2017 };
2157 2018
2158 tcsr: syscon@1fc0000 { 2019 tcsr: syscon@1fc0000 {
2159 compatible = "qcom,sm 2020 compatible = "qcom,sm8450-tcsr", "syscon";
2160 reg = <0x0 0x1fc0000 2021 reg = <0x0 0x1fc0000 0x0 0x30000>;
2161 }; 2022 };
2162 2023
2163 gpu: gpu@3d00000 { <<
2164 compatible = "qcom,ad <<
2165 reg = <0x0 0x03d00000 <<
2166 <0x0 0x03d9e000 <<
2167 <0x0 0x03d61000 <<
2168 reg-names = "kgsl_3d0 <<
2169 "cx_mem", <<
2170 "cx_dbgc" <<
2171 <<
2172 interrupts = <GIC_SPI <<
2173 <<
2174 iommus = <&adreno_smm <<
2175 <&adreno_smm <<
2176 <<
2177 operating-points-v2 = <<
2178 <<
2179 qcom,gmu = <&gmu>; <<
2180 #cooling-cells = <2>; <<
2181 <<
2182 status = "disabled"; <<
2183 <<
2184 zap-shader { <<
2185 memory-region <<
2186 }; <<
2187 <<
2188 gpu_opp_table: opp-ta <<
2189 compatible = <<
2190 <<
2191 opp-818000000 <<
2192 opp-h <<
2193 opp-l <<
2194 }; <<
2195 <<
2196 opp-791000000 <<
2197 opp-h <<
2198 opp-l <<
2199 }; <<
2200 <<
2201 opp-734000000 <<
2202 opp-h <<
2203 opp-l <<
2204 }; <<
2205 <<
2206 opp-640000000 <<
2207 opp-h <<
2208 opp-l <<
2209 }; <<
2210 <<
2211 opp-599000000 <<
2212 opp-h <<
2213 opp-l <<
2214 }; <<
2215 <<
2216 opp-545000000 <<
2217 opp-h <<
2218 opp-l <<
2219 }; <<
2220 <<
2221 opp-492000000 <<
2222 opp-h <<
2223 opp-l <<
2224 }; <<
2225 <<
2226 opp-421000000 <<
2227 opp-h <<
2228 opp-l <<
2229 }; <<
2230 <<
2231 opp-350000000 <<
2232 opp-h <<
2233 opp-l <<
2234 }; <<
2235 <<
2236 opp-317000000 <<
2237 opp-h <<
2238 opp-l <<
2239 }; <<
2240 <<
2241 opp-285000000 <<
2242 opp-h <<
2243 opp-l <<
2244 }; <<
2245 <<
2246 opp-220000000 <<
2247 opp-h <<
2248 opp-l <<
2249 }; <<
2250 }; <<
2251 }; <<
2252 <<
2253 gmu: gmu@3d6a000 { <<
2254 compatible = "qcom,ad <<
2255 reg = <0x0 0x03d6a000 <<
2256 <0x0 0x03d50000 <<
2257 <0x0 0x0b290000 <<
2258 reg-names = "gmu", "r <<
2259 <<
2260 interrupts = <GIC_SPI <<
2261 <GIC_SPI <<
2262 interrupt-names = "hf <<
2263 <<
2264 clocks = <&gpucc GPU_ <<
2265 <&gpucc GPU_ <<
2266 <&gpucc GPU_ <<
2267 <&gcc GCC_DD <<
2268 <&gcc GCC_GP <<
2269 <&gpucc GPU_ <<
2270 <&gpucc GPU_ <<
2271 clock-names = "ahb", <<
2272 "gmu", <<
2273 "cxo", <<
2274 "axi", <<
2275 "memnoc <<
2276 "hub", <<
2277 "demet" <<
2278 <<
2279 power-domains = <&gpu <<
2280 <&gpu <<
2281 power-domain-names = <<
2282 <<
2283 <<
2284 iommus = <&adreno_smm <<
2285 <<
2286 qcom,qmp = <&aoss_qmp <<
2287 <<
2288 operating-points-v2 = <<
2289 <<
2290 gmu_opp_table: opp-ta <<
2291 compatible = <<
2292 <<
2293 opp-500000000 <<
2294 opp-h <<
2295 opp-l <<
2296 }; <<
2297 <<
2298 opp-200000000 <<
2299 opp-h <<
2300 opp-l <<
2301 }; <<
2302 }; <<
2303 }; <<
2304 <<
2305 gpucc: clock-controller@3d900 <<
2306 compatible = "qcom,sm <<
2307 reg = <0x0 0x03d90000 <<
2308 clocks = <&rpmhcc RPM <<
2309 <&gcc GCC_GP <<
2310 <&gcc GCC_GP <<
2311 #clock-cells = <1>; <<
2312 #reset-cells = <1>; <<
2313 #power-domain-cells = <<
2314 }; <<
2315 <<
2316 adreno_smmu: iommu@3da0000 { <<
2317 compatible = "qcom,sm <<
2318 "qcom,sm <<
2319 reg = <0x0 0x03da0000 <<
2320 #iommu-cells = <2>; <<
2321 #global-interrupts = <<
2322 interrupts = <GIC_SPI <<
2323 <GIC_SPI <<
2324 <GIC_SPI <<
2325 <GIC_SPI <<
2326 <GIC_SPI <<
2327 <GIC_SPI <<
2328 <GIC_SPI <<
2329 <GIC_SPI <<
2330 <GIC_SPI <<
2331 <GIC_SPI <<
2332 <GIC_SPI <<
2333 <GIC_SPI <<
2334 <GIC_SPI <<
2335 <GIC_SPI <<
2336 <GIC_SPI <<
2337 <GIC_SPI <<
2338 <GIC_SPI <<
2339 <GIC_SPI <<
2340 <GIC_SPI <<
2341 <GIC_SPI <<
2342 <GIC_SPI <<
2343 <GIC_SPI <<
2344 <GIC_SPI <<
2345 <GIC_SPI <<
2346 <GIC_SPI <<
2347 <GIC_SPI <<
2348 clocks = <&gpucc GPU_ <<
2349 <&gpucc GPU_ <<
2350 <&gpucc GPU_ <<
2351 <&gcc GCC_GP <<
2352 <&gcc GCC_GP <<
2353 <&gpucc GPU_ <<
2354 clock-names = "gmu", <<
2355 "hub", <<
2356 "hlos", <<
2357 "bus", <<
2358 "iface" <<
2359 "ahb"; <<
2360 power-domains = <&gpu <<
2361 dma-coherent; <<
2362 }; <<
2363 <<
2364 usb_1_hsphy: phy@88e3000 { 2024 usb_1_hsphy: phy@88e3000 {
2365 compatible = "qcom,sm 2025 compatible = "qcom,sm8450-usb-hs-phy",
2366 "qcom,us 2026 "qcom,usb-snps-hs-7nm-phy";
2367 reg = <0 0x088e3000 0 2027 reg = <0 0x088e3000 0 0x400>;
2368 status = "disabled"; 2028 status = "disabled";
2369 #phy-cells = <0>; 2029 #phy-cells = <0>;
2370 2030
2371 clocks = <&rpmhcc RPM 2031 clocks = <&rpmhcc RPMH_CXO_CLK>;
2372 clock-names = "ref"; 2032 clock-names = "ref";
2373 2033
2374 resets = <&gcc GCC_QU 2034 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2375 }; 2035 };
2376 2036
2377 usb_1_qmpphy: phy@88e8000 { !! 2037 usb_1_qmpphy: phy-wrapper@88e9000 {
2378 compatible = "qcom,sm !! 2038 compatible = "qcom,sm8450-qmp-usb3-phy";
2379 reg = <0 0x088e8000 0 !! 2039 reg = <0 0x088e9000 0 0x200>,
>> 2040 <0 0x088e8000 0 0x20>;
>> 2041 status = "disabled";
>> 2042 #address-cells = <2>;
>> 2043 #size-cells = <2>;
>> 2044 ranges;
2380 2045
2381 clocks = <&gcc GCC_US 2046 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2382 <&rpmhcc RPM 2047 <&rpmhcc RPMH_CXO_CLK>,
2383 <&gcc GCC_US !! 2048 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
2384 <&gcc GCC_US !! 2049 clock-names = "aux", "ref_clk_src", "com_aux";
2385 clock-names = "aux", <<
2386 2050
2387 resets = <&gcc GCC_US 2051 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
2388 <&gcc GCC_US 2052 <&gcc GCC_USB3_PHY_PRIM_BCR>;
2389 reset-names = "phy", 2053 reset-names = "phy", "common";
2390 2054
2391 #clock-cells = <1>; !! 2055 usb_1_ssphy: phy@88e9200 {
2392 #phy-cells = <1>; !! 2056 reg = <0 0x088e9200 0 0x200>,
2393 !! 2057 <0 0x088e9400 0 0x200>,
2394 orientation-switch; !! 2058 <0 0x088e9c00 0 0x400>,
2395 !! 2059 <0 0x088e9600 0 0x200>,
2396 status = "disabled"; !! 2060 <0 0x088e9800 0 0x200>,
2397 !! 2061 <0 0x088e9a00 0 0x100>;
2398 ports { !! 2062 #phy-cells = <0>;
2399 #address-cell !! 2063 #clock-cells = <0>;
2400 #size-cells = !! 2064 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2401 !! 2065 clock-names = "pipe0";
2402 port@0 { !! 2066 clock-output-names = "usb3_phy_pipe_clk_src";
2403 reg = <<
2404 <<
2405 usb_1 <<
2406 }; <<
2407 }; <<
2408 <<
2409 port@1 { <<
2410 reg = <<
2411 <<
2412 usb_1 <<
2413 <<
2414 }; <<
2415 }; <<
2416 <<
2417 port@2 { <<
2418 reg = <<
2419 <<
2420 usb_1 <<
2421 <<
2422 }; <<
2423 }; <<
2424 }; 2067 };
2425 }; 2068 };
2426 2069
2427 remoteproc_slpi: remoteproc@2 2070 remoteproc_slpi: remoteproc@2400000 {
2428 compatible = "qcom,sm 2071 compatible = "qcom,sm8450-slpi-pas";
2429 reg = <0 0x02400000 0 2072 reg = <0 0x02400000 0 0x4000>;
2430 2073
2431 interrupts-extended = 2074 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>,
2432 2075 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
2433 2076 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
2434 2077 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
2435 2078 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
2436 interrupt-names = "wd 2079 interrupt-names = "wdog", "fatal", "ready",
2437 "ha 2080 "handover", "stop-ack";
2438 2081
2439 clocks = <&rpmhcc RPM 2082 clocks = <&rpmhcc RPMH_CXO_CLK>;
2440 clock-names = "xo"; 2083 clock-names = "xo";
2441 2084
2442 power-domains = <&rpm !! 2085 power-domains = <&rpmhpd SM8450_LCX>,
2443 <&rpm !! 2086 <&rpmhpd SM8450_LMX>;
2444 power-domain-names = 2087 power-domain-names = "lcx", "lmx";
2445 2088
2446 memory-region = <&slp 2089 memory-region = <&slpi_mem>;
2447 2090
2448 qcom,qmp = <&aoss_qmp 2091 qcom,qmp = <&aoss_qmp>;
2449 2092
2450 qcom,smem-states = <& 2093 qcom,smem-states = <&smp2p_slpi_out 0>;
2451 qcom,smem-state-names 2094 qcom,smem-state-names = "stop";
2452 2095
2453 status = "disabled"; 2096 status = "disabled";
2454 2097
2455 glink-edge { 2098 glink-edge {
2456 interrupts-ex 2099 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
2457 2100 IPCC_MPROC_SIGNAL_GLINK_QMP
2458 2101 IRQ_TYPE_EDGE_RISING>;
2459 mboxes = <&ip 2102 mboxes = <&ipcc IPCC_CLIENT_SLPI
2460 2103 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2461 2104
2462 label = "slpi 2105 label = "slpi";
2463 qcom,remote-p 2106 qcom,remote-pid = <3>;
2464 2107
2465 fastrpc { 2108 fastrpc {
2466 compa 2109 compatible = "qcom,fastrpc";
2467 qcom, 2110 qcom,glink-channels = "fastrpcglink-apps-dsp";
2468 label 2111 label = "sdsp";
2469 qcom, <<
2470 #addr 2112 #address-cells = <1>;
2471 #size 2113 #size-cells = <0>;
2472 2114
2473 compu 2115 compute-cb@1 {
2474 2116 compatible = "qcom,fastrpc-compute-cb";
2475 2117 reg = <1>;
2476 2118 iommus = <&apps_smmu 0x0541 0x0>;
2477 }; 2119 };
2478 2120
2479 compu 2121 compute-cb@2 {
2480 2122 compatible = "qcom,fastrpc-compute-cb";
2481 2123 reg = <2>;
2482 2124 iommus = <&apps_smmu 0x0542 0x0>;
2483 }; 2125 };
2484 2126
2485 compu 2127 compute-cb@3 {
2486 2128 compatible = "qcom,fastrpc-compute-cb";
2487 2129 reg = <3>;
2488 2130 iommus = <&apps_smmu 0x0543 0x0>;
2489 2131 /* note: shared-cb = <4> in downstream */
2490 }; 2132 };
2491 }; 2133 };
2492 }; 2134 };
2493 }; 2135 };
2494 2136
2495 wsa2macro: codec@31e0000 { 2137 wsa2macro: codec@31e0000 {
2496 compatible = "qcom,sm 2138 compatible = "qcom,sm8450-lpass-wsa-macro";
2497 reg = <0 0x031e0000 0 2139 reg = <0 0x031e0000 0 0x1000>;
2498 clocks = <&q6prmcc LP 2140 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2499 <&q6prmcc LP 2141 <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2500 <&q6prmcc LP 2142 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2501 <&q6prmcc LP 2143 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2502 <&vamacro>; 2144 <&vamacro>;
2503 clock-names = "mclk", 2145 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
>> 2146 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 2147 <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
>> 2148 assigned-clock-rates = <19200000>, <19200000>;
2504 2149
2505 #clock-cells = <0>; 2150 #clock-cells = <0>;
2506 clock-output-names = 2151 clock-output-names = "wsa2-mclk";
>> 2152 pinctrl-names = "default";
>> 2153 pinctrl-0 = <&wsa2_swr_active>;
2507 #sound-dai-cells = <1 2154 #sound-dai-cells = <1>;
2508 }; 2155 };
2509 2156
2510 swr4: soundwire@31f0000 { !! 2157 /* WSA2 */
>> 2158 swr4: soundwire-controller@31f0000 {
2511 compatible = "qcom,so 2159 compatible = "qcom,soundwire-v1.7.0";
2512 reg = <0 0x031f0000 0 2160 reg = <0 0x031f0000 0 0x2000>;
2513 interrupts = <GIC_SPI 2161 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
2514 clocks = <&wsa2macro> 2162 clocks = <&wsa2macro>;
2515 clock-names = "iface" 2163 clock-names = "iface";
2516 label = "WSA2"; <<
2517 <<
2518 pinctrl-0 = <&wsa2_sw <<
2519 pinctrl-names = "defa <<
2520 2164
2521 qcom,din-ports = <2>; 2165 qcom,din-ports = <2>;
2522 qcom,dout-ports = <6> 2166 qcom,dout-ports = <6>;
2523 2167
2524 qcom,ports-sinterval- 2168 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2525 qcom,ports-offset1 = 2169 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2526 qcom,ports-offset2 = 2170 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2527 qcom,ports-hstart = 2171 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2528 qcom,ports-hstop = 2172 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2529 qcom,ports-word-lengt 2173 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2530 qcom,ports-block-pack 2174 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
2531 qcom,ports-block-grou 2175 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2532 qcom,ports-lane-contr 2176 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2533 2177
2534 #address-cells = <2>; 2178 #address-cells = <2>;
2535 #size-cells = <0>; 2179 #size-cells = <0>;
2536 #sound-dai-cells = <1 2180 #sound-dai-cells = <1>;
2537 status = "disabled"; 2181 status = "disabled";
2538 }; 2182 };
2539 2183
2540 rxmacro: codec@3200000 { 2184 rxmacro: codec@3200000 {
2541 compatible = "qcom,sm 2185 compatible = "qcom,sm8450-lpass-rx-macro";
2542 reg = <0 0x03200000 0 2186 reg = <0 0x03200000 0 0x1000>;
2543 clocks = <&q6prmcc LP 2187 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2544 <&q6prmcc LP 2188 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2545 <&q6prmcc LP 2189 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2546 <&q6prmcc LP 2190 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2547 <&vamacro>; 2191 <&vamacro>;
2548 clock-names = "mclk", 2192 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2549 2193
>> 2194 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 2195 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
>> 2196 assigned-clock-rates = <19200000>, <19200000>;
>> 2197
2550 #clock-cells = <0>; 2198 #clock-cells = <0>;
2551 clock-output-names = 2199 clock-output-names = "mclk";
>> 2200 pinctrl-names = "default";
>> 2201 pinctrl-0 = <&rx_swr_active>;
2552 #sound-dai-cells = <1 2202 #sound-dai-cells = <1>;
2553 }; 2203 };
2554 2204
2555 swr1: soundwire@3210000 { !! 2205 swr1: soundwire-controller@3210000 {
2556 compatible = "qcom,so 2206 compatible = "qcom,soundwire-v1.7.0";
2557 reg = <0 0x03210000 0 2207 reg = <0 0x03210000 0 0x2000>;
2558 interrupts = <GIC_SPI 2208 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
2559 clocks = <&rxmacro>; 2209 clocks = <&rxmacro>;
2560 clock-names = "iface" 2210 clock-names = "iface";
2561 label = "RX"; 2211 label = "RX";
2562 qcom,din-ports = <0>; 2212 qcom,din-ports = <0>;
2563 qcom,dout-ports = <5> 2213 qcom,dout-ports = <5>;
2564 2214
2565 pinctrl-0 = <&rx_swr_ <<
2566 pinctrl-names = "defa <<
2567 <<
2568 qcom,ports-sinterval- 2215 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
2569 qcom,ports-offset1 = 2216 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>;
2570 qcom,ports-offset2 = 2217 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
2571 qcom,ports-hstart = 2218 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
2572 qcom,ports-hstop = 2219 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
2573 qcom,ports-word-lengt 2220 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2574 qcom,ports-block-pack 2221 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
2575 qcom,ports-block-grou 2222 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
2576 qcom,ports-lane-contr 2223 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2577 2224
2578 #address-cells = <2>; 2225 #address-cells = <2>;
2579 #size-cells = <0>; 2226 #size-cells = <0>;
2580 #sound-dai-cells = <1 2227 #sound-dai-cells = <1>;
2581 status = "disabled"; 2228 status = "disabled";
2582 }; 2229 };
2583 2230
2584 txmacro: codec@3220000 { 2231 txmacro: codec@3220000 {
2585 compatible = "qcom,sm 2232 compatible = "qcom,sm8450-lpass-tx-macro";
2586 reg = <0 0x03220000 0 2233 reg = <0 0x03220000 0 0x1000>;
2587 clocks = <&q6prmcc LP 2234 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2588 <&q6prmcc LP 2235 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2589 <&q6prmcc LP 2236 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2590 <&q6prmcc LP 2237 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2591 <&vamacro>; 2238 <&vamacro>;
2592 clock-names = "mclk", 2239 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
>> 2240 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 2241 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
>> 2242 assigned-clock-rates = <19200000>, <19200000>;
2593 2243
2594 #clock-cells = <0>; 2244 #clock-cells = <0>;
2595 clock-output-names = 2245 clock-output-names = "mclk";
>> 2246 pinctrl-names = "default";
>> 2247 pinctrl-0 = <&tx_swr_active>;
2596 #sound-dai-cells = <1 2248 #sound-dai-cells = <1>;
2597 }; 2249 };
2598 2250
2599 wsamacro: codec@3240000 { 2251 wsamacro: codec@3240000 {
2600 compatible = "qcom,sm 2252 compatible = "qcom,sm8450-lpass-wsa-macro";
2601 reg = <0 0x03240000 0 2253 reg = <0 0x03240000 0 0x1000>;
2602 clocks = <&q6prmcc LP 2254 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2603 <&q6prmcc LP 2255 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2604 <&q6prmcc LP 2256 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2605 <&q6prmcc LP 2257 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2606 <&vamacro>; 2258 <&vamacro>;
2607 clock-names = "mclk", 2259 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2608 2260
>> 2261 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 2262 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
>> 2263 assigned-clock-rates = <19200000>, <19200000>;
>> 2264
2609 #clock-cells = <0>; 2265 #clock-cells = <0>;
2610 clock-output-names = 2266 clock-output-names = "mclk";
>> 2267 pinctrl-names = "default";
>> 2268 pinctrl-0 = <&wsa_swr_active>;
2611 #sound-dai-cells = <1 2269 #sound-dai-cells = <1>;
2612 }; 2270 };
2613 2271
2614 swr0: soundwire@3250000 { !! 2272 /* WSA */
>> 2273 swr0: soundwire-controller@3250000 {
2615 compatible = "qcom,so 2274 compatible = "qcom,soundwire-v1.7.0";
2616 reg = <0 0x03250000 0 2275 reg = <0 0x03250000 0 0x2000>;
2617 interrupts = <GIC_SPI 2276 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
2618 clocks = <&wsamacro>; 2277 clocks = <&wsamacro>;
2619 clock-names = "iface" 2278 clock-names = "iface";
2620 label = "WSA"; <<
2621 <<
2622 pinctrl-0 = <&wsa_swr <<
2623 pinctrl-names = "defa <<
2624 2279
2625 qcom,din-ports = <2>; 2280 qcom,din-ports = <2>;
2626 qcom,dout-ports = <6> 2281 qcom,dout-ports = <6>;
2627 2282
2628 qcom,ports-sinterval- 2283 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2629 qcom,ports-offset1 = 2284 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2630 qcom,ports-offset2 = 2285 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2631 qcom,ports-hstart = 2286 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2632 qcom,ports-hstop = 2287 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2633 qcom,ports-word-lengt 2288 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2634 qcom,ports-block-pack 2289 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
2635 qcom,ports-block-grou 2290 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2636 qcom,ports-lane-contr 2291 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2637 2292
2638 #address-cells = <2>; 2293 #address-cells = <2>;
2639 #size-cells = <0>; 2294 #size-cells = <0>;
2640 #sound-dai-cells = <1 2295 #sound-dai-cells = <1>;
2641 status = "disabled"; 2296 status = "disabled";
2642 }; 2297 };
2643 2298
2644 swr2: soundwire@33b0000 { !! 2299 swr2: soundwire-controller@33b0000 {
2645 compatible = "qcom,so 2300 compatible = "qcom,soundwire-v1.7.0";
2646 reg = <0 0x033b0000 0 2301 reg = <0 0x033b0000 0 0x2000>;
2647 interrupts = <GIC_SPI !! 2302 interrupts-extended = <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
2648 <GIC_SPI !! 2303 <&intc GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>;
2649 interrupt-names = "co 2304 interrupt-names = "core", "wakeup";
2650 2305
2651 clocks = <&txmacro>; !! 2306 clocks = <&vamacro>;
2652 clock-names = "iface" 2307 clock-names = "iface";
2653 label = "TX"; 2308 label = "TX";
2654 2309
2655 pinctrl-0 = <&tx_swr_ <<
2656 pinctrl-names = "defa <<
2657 <<
2658 qcom,din-ports = <4>; 2310 qcom,din-ports = <4>;
2659 qcom,dout-ports = <0> 2311 qcom,dout-ports = <0>;
2660 qcom,ports-sinterval- 2312 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
2661 qcom,ports-offset1 = 2313 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>;
2662 qcom,ports-offset2 = 2314 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
2663 qcom,ports-hstart = 2315 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
2664 qcom,ports-hstop = 2316 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
2665 qcom,ports-word-lengt 2317 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
2666 qcom,ports-block-pack 2318 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
2667 qcom,ports-block-grou 2319 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
2668 qcom,ports-lane-contr 2320 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>;
2669 2321
2670 #address-cells = <2>; 2322 #address-cells = <2>;
2671 #size-cells = <0>; 2323 #size-cells = <0>;
2672 #sound-dai-cells = <1 2324 #sound-dai-cells = <1>;
2673 status = "disabled"; 2325 status = "disabled";
2674 }; 2326 };
2675 2327
2676 vamacro: codec@33f0000 { 2328 vamacro: codec@33f0000 {
2677 compatible = "qcom,sm 2329 compatible = "qcom,sm8450-lpass-va-macro";
2678 reg = <0 0x033f0000 0 2330 reg = <0 0x033f0000 0 0x1000>;
2679 clocks = <&q6prmcc LP 2331 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2680 <&q6prmcc LP 2332 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2681 <&q6prmcc LP 2333 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2682 <&q6prmcc LP 2334 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2683 clock-names = "mclk", 2335 clock-names = "mclk", "macro", "dcodec", "npl";
>> 2336 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
>> 2337 assigned-clock-rates = <19200000>;
2684 2338
2685 #clock-cells = <0>; 2339 #clock-cells = <0>;
2686 clock-output-names = 2340 clock-output-names = "fsgen";
2687 #sound-dai-cells = <1 2341 #sound-dai-cells = <1>;
2688 status = "disabled"; 2342 status = "disabled";
2689 }; 2343 };
2690 2344
2691 remoteproc_adsp: remoteproc@3 2345 remoteproc_adsp: remoteproc@30000000 {
2692 compatible = "qcom,sm 2346 compatible = "qcom,sm8450-adsp-pas";
2693 reg = <0 0x30000000 0 2347 reg = <0 0x30000000 0 0x100>;
2694 2348
2695 interrupts-extended = 2349 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
2696 2350 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
2697 2351 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
2698 2352 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
2699 2353 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
2700 interrupt-names = "wd 2354 interrupt-names = "wdog", "fatal", "ready",
2701 "ha 2355 "handover", "stop-ack";
2702 2356
2703 clocks = <&rpmhcc RPM 2357 clocks = <&rpmhcc RPMH_CXO_CLK>;
2704 clock-names = "xo"; 2358 clock-names = "xo";
2705 2359
2706 power-domains = <&rpm !! 2360 power-domains = <&rpmhpd SM8450_LCX>,
2707 <&rpm !! 2361 <&rpmhpd SM8450_LMX>;
2708 power-domain-names = 2362 power-domain-names = "lcx", "lmx";
2709 2363
2710 memory-region = <&ads 2364 memory-region = <&adsp_mem>;
2711 2365
2712 qcom,qmp = <&aoss_qmp 2366 qcom,qmp = <&aoss_qmp>;
2713 2367
2714 qcom,smem-states = <& 2368 qcom,smem-states = <&smp2p_adsp_out 0>;
2715 qcom,smem-state-names 2369 qcom,smem-state-names = "stop";
2716 2370
2717 status = "disabled"; 2371 status = "disabled";
2718 2372
2719 remoteproc_adsp_glink 2373 remoteproc_adsp_glink: glink-edge {
2720 interrupts-ex 2374 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
2721 2375 IPCC_MPROC_SIGNAL_GLINK_QMP
2722 2376 IRQ_TYPE_EDGE_RISING>;
2723 mboxes = <&ip 2377 mboxes = <&ipcc IPCC_CLIENT_LPASS
2724 2378 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2725 2379
2726 label = "lpas 2380 label = "lpass";
2727 qcom,remote-p 2381 qcom,remote-pid = <2>;
2728 2382
2729 gpr { 2383 gpr {
2730 compa 2384 compatible = "qcom,gpr";
2731 qcom, 2385 qcom,glink-channels = "adsp_apps";
2732 qcom, 2386 qcom,domain = <GPR_DOMAIN_ID_ADSP>;
2733 qcom, 2387 qcom,intents = <512 20>;
2734 #addr 2388 #address-cells = <1>;
2735 #size 2389 #size-cells = <0>;
2736 2390
2737 q6apm 2391 q6apm: service@1 {
2738 2392 compatible = "qcom,q6apm";
2739 2393 reg = <GPR_APM_MODULE_IID>;
2740 2394 #sound-dai-cells = <0>;
2741 2395 qcom,protection-domain = "avs/audio",
2742 2396 "msm/adsp/audio_pd";
2743 2397
2744 2398 q6apmdai: dais {
2745 2399 compatible = "qcom,q6apm-dais";
2746 2400 iommus = <&apps_smmu 0x1801 0x0>;
2747 2401 };
2748 2402
2749 2403 q6apmbedai: bedais {
2750 2404 compatible = "qcom,q6apm-lpass-dais";
2751 2405 #sound-dai-cells = <1>;
2752 2406 };
2753 }; 2407 };
2754 2408
2755 q6prm 2409 q6prm: service@2 {
2756 2410 compatible = "qcom,q6prm";
2757 2411 reg = <GPR_PRM_MODULE_IID>;
2758 2412 qcom,protection-domain = "avs/audio",
2759 2413 "msm/adsp/audio_pd";
2760 2414
2761 2415 q6prmcc: clock-controller {
2762 2416 compatible = "qcom,q6prm-lpass-clocks";
2763 2417 #clock-cells = <2>;
2764 2418 };
2765 }; 2419 };
2766 }; 2420 };
2767 2421
2768 fastrpc { 2422 fastrpc {
2769 compa 2423 compatible = "qcom,fastrpc";
2770 qcom, 2424 qcom,glink-channels = "fastrpcglink-apps-dsp";
2771 label 2425 label = "adsp";
2772 qcom, <<
2773 #addr 2426 #address-cells = <1>;
2774 #size 2427 #size-cells = <0>;
2775 2428
2776 compu 2429 compute-cb@3 {
2777 2430 compatible = "qcom,fastrpc-compute-cb";
2778 2431 reg = <3>;
2779 2432 iommus = <&apps_smmu 0x1803 0x0>;
2780 }; 2433 };
2781 2434
2782 compu 2435 compute-cb@4 {
2783 2436 compatible = "qcom,fastrpc-compute-cb";
2784 2437 reg = <4>;
2785 2438 iommus = <&apps_smmu 0x1804 0x0>;
2786 }; 2439 };
2787 2440
2788 compu 2441 compute-cb@5 {
2789 2442 compatible = "qcom,fastrpc-compute-cb";
2790 2443 reg = <5>;
2791 2444 iommus = <&apps_smmu 0x1805 0x0>;
2792 }; 2445 };
2793 }; 2446 };
2794 }; 2447 };
2795 }; 2448 };
2796 2449
2797 remoteproc_cdsp: remoteproc@3 2450 remoteproc_cdsp: remoteproc@32300000 {
2798 compatible = "qcom,sm 2451 compatible = "qcom,sm8450-cdsp-pas";
2799 reg = <0 0x32300000 0 2452 reg = <0 0x32300000 0 0x1400000>;
2800 2453
2801 interrupts-extended = 2454 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
2802 2455 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
2803 2456 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
2804 2457 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
2805 2458 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
2806 interrupt-names = "wd 2459 interrupt-names = "wdog", "fatal", "ready",
2807 "ha 2460 "handover", "stop-ack";
2808 2461
2809 clocks = <&rpmhcc RPM 2462 clocks = <&rpmhcc RPMH_CXO_CLK>;
2810 clock-names = "xo"; 2463 clock-names = "xo";
2811 2464
2812 power-domains = <&rpm !! 2465 power-domains = <&rpmhpd SM8450_CX>,
2813 <&rpm !! 2466 <&rpmhpd SM8450_MXC>;
2814 power-domain-names = 2467 power-domain-names = "cx", "mxc";
2815 2468
2816 memory-region = <&cds 2469 memory-region = <&cdsp_mem>;
2817 2470
2818 qcom,qmp = <&aoss_qmp 2471 qcom,qmp = <&aoss_qmp>;
2819 2472
2820 qcom,smem-states = <& 2473 qcom,smem-states = <&smp2p_cdsp_out 0>;
2821 qcom,smem-state-names 2474 qcom,smem-state-names = "stop";
2822 2475
2823 status = "disabled"; 2476 status = "disabled";
2824 2477
2825 glink-edge { 2478 glink-edge {
2826 interrupts-ex 2479 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
2827 2480 IPCC_MPROC_SIGNAL_GLINK_QMP
2828 2481 IRQ_TYPE_EDGE_RISING>;
2829 mboxes = <&ip 2482 mboxes = <&ipcc IPCC_CLIENT_CDSP
2830 2483 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2831 2484
2832 label = "cdsp 2485 label = "cdsp";
2833 qcom,remote-p 2486 qcom,remote-pid = <5>;
2834 2487
2835 fastrpc { 2488 fastrpc {
2836 compa 2489 compatible = "qcom,fastrpc";
2837 qcom, 2490 qcom,glink-channels = "fastrpcglink-apps-dsp";
2838 label 2491 label = "cdsp";
2839 qcom, <<
2840 #addr 2492 #address-cells = <1>;
2841 #size 2493 #size-cells = <0>;
2842 2494
2843 compu 2495 compute-cb@1 {
2844 2496 compatible = "qcom,fastrpc-compute-cb";
2845 2497 reg = <1>;
2846 2498 iommus = <&apps_smmu 0x2161 0x0400>,
2847 2499 <&apps_smmu 0x1021 0x1420>;
2848 }; 2500 };
2849 2501
2850 compu 2502 compute-cb@2 {
2851 2503 compatible = "qcom,fastrpc-compute-cb";
2852 2504 reg = <2>;
2853 2505 iommus = <&apps_smmu 0x2162 0x0400>,
2854 2506 <&apps_smmu 0x1022 0x1420>;
2855 }; 2507 };
2856 2508
2857 compu 2509 compute-cb@3 {
2858 2510 compatible = "qcom,fastrpc-compute-cb";
2859 2511 reg = <3>;
2860 2512 iommus = <&apps_smmu 0x2163 0x0400>,
2861 2513 <&apps_smmu 0x1023 0x1420>;
2862 }; 2514 };
2863 2515
2864 compu 2516 compute-cb@4 {
2865 2517 compatible = "qcom,fastrpc-compute-cb";
2866 2518 reg = <4>;
2867 2519 iommus = <&apps_smmu 0x2164 0x0400>,
2868 2520 <&apps_smmu 0x1024 0x1420>;
2869 }; 2521 };
2870 2522
2871 compu 2523 compute-cb@5 {
2872 2524 compatible = "qcom,fastrpc-compute-cb";
2873 2525 reg = <5>;
2874 2526 iommus = <&apps_smmu 0x2165 0x0400>,
2875 2527 <&apps_smmu 0x1025 0x1420>;
2876 }; 2528 };
2877 2529
2878 compu 2530 compute-cb@6 {
2879 2531 compatible = "qcom,fastrpc-compute-cb";
2880 2532 reg = <6>;
2881 2533 iommus = <&apps_smmu 0x2166 0x0400>,
2882 2534 <&apps_smmu 0x1026 0x1420>;
2883 }; 2535 };
2884 2536
2885 compu 2537 compute-cb@7 {
2886 2538 compatible = "qcom,fastrpc-compute-cb";
2887 2539 reg = <7>;
2888 2540 iommus = <&apps_smmu 0x2167 0x0400>,
2889 2541 <&apps_smmu 0x1027 0x1420>;
2890 }; 2542 };
2891 2543
2892 compu 2544 compute-cb@8 {
2893 2545 compatible = "qcom,fastrpc-compute-cb";
2894 2546 reg = <8>;
2895 2547 iommus = <&apps_smmu 0x2168 0x0400>,
2896 2548 <&apps_smmu 0x1028 0x1420>;
2897 }; 2549 };
2898 2550
2899 /* no 2551 /* note: secure cb9 in downstream */
2900 }; 2552 };
2901 }; 2553 };
2902 }; 2554 };
2903 2555
2904 remoteproc_mpss: remoteproc@4 2556 remoteproc_mpss: remoteproc@4080000 {
2905 compatible = "qcom,sm 2557 compatible = "qcom,sm8450-mpss-pas";
2906 reg = <0x0 0x04080000 2558 reg = <0x0 0x04080000 0x0 0x4040>;
2907 2559
2908 interrupts-extended = 2560 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
2909 2561 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
2910 2562 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
2911 2563 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
2912 2564 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>,
2913 2565 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>;
2914 interrupt-names = "wd 2566 interrupt-names = "wdog", "fatal", "ready", "handover",
2915 "st 2567 "stop-ack", "shutdown-ack";
2916 2568
2917 clocks = <&rpmhcc RPM 2569 clocks = <&rpmhcc RPMH_CXO_CLK>;
2918 clock-names = "xo"; 2570 clock-names = "xo";
2919 2571
2920 power-domains = <&rpm !! 2572 power-domains = <&rpmhpd SM8450_CX>,
2921 <&rpm !! 2573 <&rpmhpd SM8450_MSS>;
2922 power-domain-names = 2574 power-domain-names = "cx", "mss";
2923 2575
2924 memory-region = <&mps 2576 memory-region = <&mpss_mem>;
2925 2577
2926 qcom,qmp = <&aoss_qmp 2578 qcom,qmp = <&aoss_qmp>;
2927 2579
2928 qcom,smem-states = <& 2580 qcom,smem-states = <&smp2p_modem_out 0>;
2929 qcom,smem-state-names 2581 qcom,smem-state-names = "stop";
2930 2582
2931 status = "disabled"; 2583 status = "disabled";
2932 2584
2933 glink-edge { 2585 glink-edge {
2934 interrupts-ex 2586 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
2935 2587 IPCC_MPROC_SIGNAL_GLINK_QMP
2936 2588 IRQ_TYPE_EDGE_RISING>;
2937 mboxes = <&ip 2589 mboxes = <&ipcc IPCC_CLIENT_MPSS
2938 2590 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2939 label = "mode 2591 label = "modem";
2940 qcom,remote-p 2592 qcom,remote-pid = <1>;
2941 }; 2593 };
2942 }; 2594 };
2943 2595
2944 videocc: clock-controller@aaf <<
2945 compatible = "qcom,sm <<
2946 reg = <0 0x0aaf0000 0 <<
2947 clocks = <&rpmhcc RPM <<
2948 <&gcc GCC_VI <<
2949 power-domains = <&rpm <<
2950 required-opps = <&rpm <<
2951 #clock-cells = <1>; <<
2952 #reset-cells = <1>; <<
2953 #power-domain-cells = <<
2954 }; <<
2955 <<
2956 cci0: cci@ac15000 { 2596 cci0: cci@ac15000 {
2957 compatible = "qcom,sm 2597 compatible = "qcom,sm8450-cci", "qcom,msm8996-cci";
2958 reg = <0 0x0ac15000 0 2598 reg = <0 0x0ac15000 0 0x1000>;
2959 interrupts = <GIC_SPI 2599 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
2960 power-domains = <&cam 2600 power-domains = <&camcc TITAN_TOP_GDSC>;
2961 2601
2962 clocks = <&camcc CAM_ 2602 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
2963 <&camcc CAM_ 2603 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
2964 <&camcc CAM_ 2604 <&camcc CAM_CC_CPAS_AHB_CLK>,
2965 <&camcc CAM_ 2605 <&camcc CAM_CC_CCI_0_CLK>,
2966 <&camcc CAM_ 2606 <&camcc CAM_CC_CCI_0_CLK_SRC>;
2967 clock-names = "camnoc 2607 clock-names = "camnoc_axi",
2968 "slow_a 2608 "slow_ahb_src",
2969 "cpas_a 2609 "cpas_ahb",
2970 "cci", 2610 "cci",
2971 "cci_sr 2611 "cci_src";
2972 pinctrl-0 = <&cci0_de 2612 pinctrl-0 = <&cci0_default &cci1_default>;
2973 pinctrl-1 = <&cci0_sl 2613 pinctrl-1 = <&cci0_sleep &cci1_sleep>;
2974 pinctrl-names = "defa 2614 pinctrl-names = "default", "sleep";
2975 2615
2976 status = "disabled"; 2616 status = "disabled";
2977 #address-cells = <1>; 2617 #address-cells = <1>;
2978 #size-cells = <0>; 2618 #size-cells = <0>;
2979 2619
2980 cci0_i2c0: i2c-bus@0 2620 cci0_i2c0: i2c-bus@0 {
2981 reg = <0>; 2621 reg = <0>;
2982 clock-frequen 2622 clock-frequency = <1000000>;
2983 #address-cell 2623 #address-cells = <1>;
2984 #size-cells = 2624 #size-cells = <0>;
2985 }; 2625 };
2986 2626
2987 cci0_i2c1: i2c-bus@1 2627 cci0_i2c1: i2c-bus@1 {
2988 reg = <1>; 2628 reg = <1>;
2989 clock-frequen 2629 clock-frequency = <1000000>;
2990 #address-cell 2630 #address-cells = <1>;
2991 #size-cells = 2631 #size-cells = <0>;
2992 }; 2632 };
2993 }; 2633 };
2994 2634
2995 cci1: cci@ac16000 { 2635 cci1: cci@ac16000 {
2996 compatible = "qcom,sm 2636 compatible = "qcom,sm8450-cci", "qcom,msm8996-cci";
2997 reg = <0 0x0ac16000 0 2637 reg = <0 0x0ac16000 0 0x1000>;
2998 interrupts = <GIC_SPI 2638 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>;
2999 power-domains = <&cam 2639 power-domains = <&camcc TITAN_TOP_GDSC>;
3000 2640
3001 clocks = <&camcc CAM_ 2641 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
3002 <&camcc CAM_ 2642 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
3003 <&camcc CAM_ 2643 <&camcc CAM_CC_CPAS_AHB_CLK>,
3004 <&camcc CAM_ 2644 <&camcc CAM_CC_CCI_1_CLK>,
3005 <&camcc CAM_ 2645 <&camcc CAM_CC_CCI_1_CLK_SRC>;
3006 clock-names = "camnoc 2646 clock-names = "camnoc_axi",
3007 "slow_a 2647 "slow_ahb_src",
3008 "cpas_a 2648 "cpas_ahb",
3009 "cci", 2649 "cci",
3010 "cci_sr 2650 "cci_src";
3011 pinctrl-0 = <&cci2_de 2651 pinctrl-0 = <&cci2_default &cci3_default>;
3012 pinctrl-1 = <&cci2_sl 2652 pinctrl-1 = <&cci2_sleep &cci3_sleep>;
3013 pinctrl-names = "defa 2653 pinctrl-names = "default", "sleep";
3014 2654
3015 status = "disabled"; 2655 status = "disabled";
3016 #address-cells = <1>; 2656 #address-cells = <1>;
3017 #size-cells = <0>; 2657 #size-cells = <0>;
3018 2658
3019 cci1_i2c0: i2c-bus@0 2659 cci1_i2c0: i2c-bus@0 {
3020 reg = <0>; 2660 reg = <0>;
3021 clock-frequen 2661 clock-frequency = <1000000>;
3022 #address-cell 2662 #address-cells = <1>;
3023 #size-cells = 2663 #size-cells = <0>;
3024 }; 2664 };
3025 2665
3026 cci1_i2c1: i2c-bus@1 2666 cci1_i2c1: i2c-bus@1 {
3027 reg = <1>; 2667 reg = <1>;
3028 clock-frequen 2668 clock-frequency = <1000000>;
3029 #address-cell 2669 #address-cells = <1>;
3030 #size-cells = 2670 #size-cells = <0>;
3031 }; 2671 };
3032 }; 2672 };
3033 2673
3034 camcc: clock-controller@ade00 2674 camcc: clock-controller@ade0000 {
3035 compatible = "qcom,sm 2675 compatible = "qcom,sm8450-camcc";
3036 reg = <0 0x0ade0000 0 2676 reg = <0 0x0ade0000 0 0x20000>;
3037 clocks = <&gcc GCC_CA 2677 clocks = <&gcc GCC_CAMERA_AHB_CLK>,
3038 <&rpmhcc RPM 2678 <&rpmhcc RPMH_CXO_CLK>,
3039 <&rpmhcc RPM 2679 <&rpmhcc RPMH_CXO_CLK_A>,
3040 <&sleep_clk> 2680 <&sleep_clk>;
3041 power-domains = <&rpm !! 2681 power-domains = <&rpmhpd SM8450_MMCX>;
3042 required-opps = <&rpm 2682 required-opps = <&rpmhpd_opp_low_svs>;
3043 #clock-cells = <1>; 2683 #clock-cells = <1>;
3044 #reset-cells = <1>; 2684 #reset-cells = <1>;
3045 #power-domain-cells = 2685 #power-domain-cells = <1>;
3046 status = "disabled"; 2686 status = "disabled";
3047 }; 2687 };
3048 2688
3049 mdss: display-subsystem@ae000 2689 mdss: display-subsystem@ae00000 {
3050 compatible = "qcom,sm 2690 compatible = "qcom,sm8450-mdss";
3051 reg = <0 0x0ae00000 0 2691 reg = <0 0x0ae00000 0 0x1000>;
3052 reg-names = "mdss"; 2692 reg-names = "mdss";
3053 2693
3054 /* same path used twi 2694 /* same path used twice */
3055 interconnects = <&mms 2695 interconnects = <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>,
3056 <&mms !! 2696 <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>;
3057 <&gem !! 2697 interconnect-names = "mdp0-mem", "mdp1-mem";
3058 &con <<
3059 interconnect-names = <<
3060 <<
3061 <<
3062 2698
3063 resets = <&dispcc DIS 2699 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
3064 2700
3065 power-domains = <&dis 2701 power-domains = <&dispcc MDSS_GDSC>;
3066 2702
3067 clocks = <&dispcc DIS 2703 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3068 <&gcc GCC_DI 2704 <&gcc GCC_DISP_HF_AXI_CLK>,
3069 <&gcc GCC_DI 2705 <&gcc GCC_DISP_SF_AXI_CLK>,
3070 <&dispcc DIS 2706 <&dispcc DISP_CC_MDSS_MDP_CLK>;
3071 2707
3072 interrupts = <GIC_SPI 2708 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
3073 interrupt-controller; 2709 interrupt-controller;
3074 #interrupt-cells = <1 2710 #interrupt-cells = <1>;
3075 2711
3076 iommus = <&apps_smmu 2712 iommus = <&apps_smmu 0x2800 0x402>;
3077 2713
3078 #address-cells = <2>; 2714 #address-cells = <2>;
3079 #size-cells = <2>; 2715 #size-cells = <2>;
3080 ranges; 2716 ranges;
3081 2717
3082 status = "disabled"; 2718 status = "disabled";
3083 2719
3084 mdss_mdp: display-con 2720 mdss_mdp: display-controller@ae01000 {
3085 compatible = 2721 compatible = "qcom,sm8450-dpu";
3086 reg = <0 0x0a 2722 reg = <0 0x0ae01000 0 0x8f000>,
3087 <0 0x0a 2723 <0 0x0aeb0000 0 0x2008>;
3088 reg-names = " 2724 reg-names = "mdp", "vbif";
3089 2725
3090 clocks = <&gc 2726 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
3091 <&gcc 2727 <&gcc GCC_DISP_SF_AXI_CLK>,
3092 <&dis 2728 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3093 <&dis 2729 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
3094 <&dis 2730 <&dispcc DISP_CC_MDSS_MDP_CLK>,
3095 <&dis 2731 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3096 clock-names = 2732 clock-names = "bus",
3097 2733 "nrt_bus",
3098 2734 "iface",
3099 2735 "lut",
3100 2736 "core",
3101 2737 "vsync";
3102 2738
3103 assigned-cloc 2739 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3104 assigned-cloc 2740 assigned-clock-rates = <19200000>;
3105 2741
3106 operating-poi 2742 operating-points-v2 = <&mdp_opp_table>;
3107 power-domains !! 2743 power-domains = <&rpmhpd SM8450_MMCX>;
3108 2744
3109 interrupt-par 2745 interrupt-parent = <&mdss>;
3110 interrupts = 2746 interrupts = <0>;
3111 2747
3112 ports { 2748 ports {
3113 #addr 2749 #address-cells = <1>;
3114 #size 2750 #size-cells = <0>;
3115 2751
3116 port@ 2752 port@0 {
3117 2753 reg = <0>;
3118 2754 dpu_intf1_out: endpoint {
3119 2755 remote-endpoint = <&mdss_dsi0_in>;
3120 2756 };
3121 }; 2757 };
3122 2758
3123 port@ 2759 port@1 {
3124 2760 reg = <1>;
3125 2761 dpu_intf2_out: endpoint {
3126 2762 remote-endpoint = <&mdss_dsi1_in>;
3127 2763 };
3128 }; 2764 };
3129 2765
3130 port@ <<
3131 <<
3132 <<
3133 <<
3134 <<
3135 }; <<
3136 }; 2766 };
3137 2767
3138 mdp_opp_table 2768 mdp_opp_table: opp-table {
3139 compa 2769 compatible = "operating-points-v2";
3140 2770
3141 opp-1 2771 opp-172000000 {
3142 2772 opp-hz = /bits/ 64 <172000000>;
3143 2773 required-opps = <&rpmhpd_opp_low_svs_d1>;
3144 }; 2774 };
3145 2775
3146 opp-2 2776 opp-200000000 {
3147 2777 opp-hz = /bits/ 64 <200000000>;
3148 2778 required-opps = <&rpmhpd_opp_low_svs>;
3149 }; 2779 };
3150 2780
3151 opp-3 2781 opp-325000000 {
3152 2782 opp-hz = /bits/ 64 <325000000>;
3153 2783 required-opps = <&rpmhpd_opp_svs>;
3154 }; 2784 };
3155 2785
3156 opp-3 2786 opp-375000000 {
3157 2787 opp-hz = /bits/ 64 <375000000>;
3158 2788 required-opps = <&rpmhpd_opp_svs_l1>;
3159 }; 2789 };
3160 2790
3161 opp-5 2791 opp-500000000 {
3162 2792 opp-hz = /bits/ 64 <500000000>;
3163 2793 required-opps = <&rpmhpd_opp_nom>;
3164 }; 2794 };
3165 }; 2795 };
3166 }; 2796 };
3167 2797
3168 mdss_dp0: displayport <<
3169 compatible = <<
3170 reg = <0 0xae <<
3171 <0 0xae <<
3172 <0 0xae <<
3173 <0 0xae <<
3174 <0 0xae <<
3175 interrupt-par <<
3176 interrupts = <<
3177 clocks = <&di <<
3178 <&di <<
3179 <&di <<
3180 <&di <<
3181 <&di <<
3182 clock-names = <<
3183 <<
3184 <<
3185 <<
3186 <<
3187 <<
3188 assigned-cloc <<
3189 <<
3190 assigned-cloc <<
3191 <<
3192 <<
3193 phys = <&usb_ <<
3194 phy-names = " <<
3195 <<
3196 #sound-dai-ce <<
3197 <<
3198 operating-poi <<
3199 power-domains <<
3200 <<
3201 status = "dis <<
3202 <<
3203 ports { <<
3204 #addr <<
3205 #size <<
3206 <<
3207 port@ <<
3208 <<
3209 <<
3210 <<
3211 <<
3212 }; <<
3213 <<
3214 port@ <<
3215 <<
3216 <<
3217 <<
3218 <<
3219 <<
3220 }; <<
3221 }; <<
3222 <<
3223 dp_opp_table: <<
3224 compa <<
3225 <<
3226 opp-1 <<
3227 <<
3228 <<
3229 }; <<
3230 <<
3231 opp-2 <<
3232 <<
3233 <<
3234 }; <<
3235 <<
3236 opp-5 <<
3237 <<
3238 <<
3239 }; <<
3240 <<
3241 opp-8 <<
3242 <<
3243 <<
3244 }; <<
3245 }; <<
3246 }; <<
3247 <<
3248 mdss_dsi0: dsi@ae9400 2798 mdss_dsi0: dsi@ae94000 {
3249 compatible = 2799 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3250 reg = <0 0x0a 2800 reg = <0 0x0ae94000 0 0x400>;
3251 reg-names = " 2801 reg-names = "dsi_ctrl";
3252 2802
3253 interrupt-par 2803 interrupt-parent = <&mdss>;
3254 interrupts = 2804 interrupts = <4>;
3255 2805
3256 clocks = <&di 2806 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
3257 <&di 2807 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
3258 <&di 2808 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
3259 <&di 2809 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
3260 <&di 2810 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3261 <&gcc 2811 <&gcc GCC_DISP_HF_AXI_CLK>;
3262 clock-names = 2812 clock-names = "byte",
3263 2813 "byte_intf",
3264 2814 "pixel",
3265 2815 "core",
3266 2816 "iface",
3267 2817 "bus";
3268 2818
3269 assigned-cloc 2819 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
3270 assigned-cloc 2820 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
3271 2821
3272 operating-poi 2822 operating-points-v2 = <&mdss_dsi_opp_table>;
3273 power-domains !! 2823 power-domains = <&rpmhpd SM8450_MMCX>;
3274 2824
3275 phys = <&mdss 2825 phys = <&mdss_dsi0_phy>;
3276 phy-names = " 2826 phy-names = "dsi";
3277 2827
3278 #address-cell 2828 #address-cells = <1>;
3279 #size-cells = 2829 #size-cells = <0>;
3280 2830
3281 status = "dis 2831 status = "disabled";
3282 2832
3283 ports { 2833 ports {
3284 #addr 2834 #address-cells = <1>;
3285 #size 2835 #size-cells = <0>;
3286 2836
3287 port@ 2837 port@0 {
3288 2838 reg = <0>;
3289 2839 mdss_dsi0_in: endpoint {
3290 2840 remote-endpoint = <&dpu_intf1_out>;
3291 2841 };
3292 }; 2842 };
3293 2843
3294 port@ 2844 port@1 {
3295 2845 reg = <1>;
3296 2846 mdss_dsi0_out: endpoint {
3297 2847 };
3298 }; 2848 };
3299 }; 2849 };
3300 2850
3301 mdss_dsi_opp_ 2851 mdss_dsi_opp_table: opp-table {
3302 compa 2852 compatible = "operating-points-v2";
3303 2853
3304 opp-1 2854 opp-187500000 {
3305 2855 opp-hz = /bits/ 64 <187500000>;
3306 2856 required-opps = <&rpmhpd_opp_low_svs>;
3307 }; 2857 };
3308 2858
3309 opp-3 2859 opp-300000000 {
3310 2860 opp-hz = /bits/ 64 <300000000>;
3311 2861 required-opps = <&rpmhpd_opp_svs>;
3312 }; 2862 };
3313 2863
3314 opp-3 2864 opp-358000000 {
3315 2865 opp-hz = /bits/ 64 <358000000>;
3316 2866 required-opps = <&rpmhpd_opp_svs_l1>;
3317 }; 2867 };
3318 }; 2868 };
3319 }; 2869 };
3320 2870
3321 mdss_dsi0_phy: phy@ae 2871 mdss_dsi0_phy: phy@ae94400 {
3322 compatible = 2872 compatible = "qcom,sm8450-dsi-phy-5nm";
3323 reg = <0 0x0a 2873 reg = <0 0x0ae94400 0 0x200>,
3324 <0 0x0a 2874 <0 0x0ae94600 0 0x280>,
3325 <0 0x0a 2875 <0 0x0ae94900 0 0x260>;
3326 reg-names = " 2876 reg-names = "dsi_phy",
3327 " 2877 "dsi_phy_lane",
3328 " 2878 "dsi_pll";
3329 2879
3330 #clock-cells 2880 #clock-cells = <1>;
3331 #phy-cells = 2881 #phy-cells = <0>;
3332 2882
3333 clocks = <&di 2883 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3334 <&rp 2884 <&rpmhcc RPMH_CXO_CLK>;
3335 clock-names = 2885 clock-names = "iface", "ref";
3336 2886
3337 status = "dis 2887 status = "disabled";
3338 }; 2888 };
3339 2889
3340 mdss_dsi1: dsi@ae9600 2890 mdss_dsi1: dsi@ae96000 {
3341 compatible = 2891 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3342 reg = <0 0x0a 2892 reg = <0 0x0ae96000 0 0x400>;
3343 reg-names = " 2893 reg-names = "dsi_ctrl";
3344 2894
3345 interrupt-par 2895 interrupt-parent = <&mdss>;
3346 interrupts = 2896 interrupts = <5>;
3347 2897
3348 clocks = <&di 2898 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
3349 <&di 2899 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
3350 <&di 2900 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
3351 <&di 2901 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
3352 <&di 2902 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3353 <&gc 2903 <&gcc GCC_DISP_HF_AXI_CLK>;
3354 clock-names = 2904 clock-names = "byte",
3355 2905 "byte_intf",
3356 2906 "pixel",
3357 2907 "core",
3358 2908 "iface",
3359 2909 "bus";
3360 2910
3361 assigned-cloc 2911 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
3362 assigned-cloc 2912 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
3363 2913
3364 operating-poi 2914 operating-points-v2 = <&mdss_dsi_opp_table>;
3365 power-domains !! 2915 power-domains = <&rpmhpd SM8450_MMCX>;
3366 2916
3367 phys = <&mdss 2917 phys = <&mdss_dsi1_phy>;
3368 phy-names = " 2918 phy-names = "dsi";
3369 2919
3370 #address-cell 2920 #address-cells = <1>;
3371 #size-cells = 2921 #size-cells = <0>;
3372 2922
3373 status = "dis 2923 status = "disabled";
3374 2924
3375 ports { 2925 ports {
3376 #addr 2926 #address-cells = <1>;
3377 #size 2927 #size-cells = <0>;
3378 2928
3379 port@ 2929 port@0 {
3380 2930 reg = <0>;
3381 2931 mdss_dsi1_in: endpoint {
3382 2932 remote-endpoint = <&dpu_intf2_out>;
3383 2933 };
3384 }; 2934 };
3385 2935
3386 port@ 2936 port@1 {
3387 2937 reg = <1>;
3388 2938 mdss_dsi1_out: endpoint {
3389 2939 };
3390 }; 2940 };
3391 }; 2941 };
3392 }; 2942 };
3393 2943
3394 mdss_dsi1_phy: phy@ae 2944 mdss_dsi1_phy: phy@ae96400 {
3395 compatible = 2945 compatible = "qcom,sm8450-dsi-phy-5nm";
3396 reg = <0 0x0a 2946 reg = <0 0x0ae96400 0 0x200>,
3397 <0 0x0a 2947 <0 0x0ae96600 0 0x280>,
3398 <0 0x0a 2948 <0 0x0ae96900 0 0x260>;
3399 reg-names = " 2949 reg-names = "dsi_phy",
3400 " 2950 "dsi_phy_lane",
3401 " 2951 "dsi_pll";
3402 2952
3403 #clock-cells 2953 #clock-cells = <1>;
3404 #phy-cells = 2954 #phy-cells = <0>;
3405 2955
3406 clocks = <&di 2956 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3407 <&rp 2957 <&rpmhcc RPMH_CXO_CLK>;
3408 clock-names = 2958 clock-names = "iface", "ref";
3409 2959
3410 status = "dis 2960 status = "disabled";
3411 }; 2961 };
3412 }; 2962 };
3413 2963
3414 dispcc: clock-controller@af00 2964 dispcc: clock-controller@af00000 {
3415 compatible = "qcom,sm 2965 compatible = "qcom,sm8450-dispcc";
3416 reg = <0 0x0af00000 0 2966 reg = <0 0x0af00000 0 0x20000>;
3417 clocks = <&rpmhcc RPM 2967 clocks = <&rpmhcc RPMH_CXO_CLK>,
3418 <&rpmhcc RPM 2968 <&rpmhcc RPMH_CXO_CLK_A>,
3419 <&gcc GCC_DI 2969 <&gcc GCC_DISP_AHB_CLK>,
3420 <&sleep_clk> 2970 <&sleep_clk>,
3421 <&mdss_dsi0_ 2971 <&mdss_dsi0_phy 0>,
3422 <&mdss_dsi0_ 2972 <&mdss_dsi0_phy 1>,
3423 <&mdss_dsi1_ 2973 <&mdss_dsi1_phy 0>,
3424 <&mdss_dsi1_ 2974 <&mdss_dsi1_phy 1>,
3425 <&usb_1_qmpp !! 2975 <0>, /* dp0 */
3426 <&usb_1_qmpp !! 2976 <0>,
3427 <0>, /* dp1 2977 <0>, /* dp1 */
3428 <0>, 2978 <0>,
3429 <0>, /* dp2 2979 <0>, /* dp2 */
3430 <0>, 2980 <0>,
3431 <0>, /* dp3 2981 <0>, /* dp3 */
3432 <0>; 2982 <0>;
3433 power-domains = <&rpm !! 2983 power-domains = <&rpmhpd SM8450_MMCX>;
3434 required-opps = <&rpm 2984 required-opps = <&rpmhpd_opp_low_svs>;
3435 #clock-cells = <1>; 2985 #clock-cells = <1>;
3436 #reset-cells = <1>; 2986 #reset-cells = <1>;
3437 #power-domain-cells = 2987 #power-domain-cells = <1>;
3438 status = "disabled"; 2988 status = "disabled";
3439 }; 2989 };
3440 2990
3441 pdc: interrupt-controller@b22 2991 pdc: interrupt-controller@b220000 {
3442 compatible = "qcom,sm 2992 compatible = "qcom,sm8450-pdc", "qcom,pdc";
3443 reg = <0 0x0b220000 0 2993 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
3444 qcom,pdc-ranges = <0 2994 qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>,
3445 <94 2995 <94 609 31>, <125 63 1>, <126 716 12>;
3446 #interrupt-cells = <2 2996 #interrupt-cells = <2>;
3447 interrupt-parent = <& 2997 interrupt-parent = <&intc>;
3448 interrupt-controller; 2998 interrupt-controller;
3449 }; 2999 };
3450 3000
3451 tsens0: thermal-sensor@c26300 3001 tsens0: thermal-sensor@c263000 {
3452 compatible = "qcom,sm 3002 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2";
3453 reg = <0 0x0c263000 0 3003 reg = <0 0x0c263000 0 0x1000>, /* TM */
3454 <0 0x0c222000 0 3004 <0 0x0c222000 0 0x1000>; /* SROT */
3455 #qcom,sensors = <16>; 3005 #qcom,sensors = <16>;
3456 interrupts = <GIC_SPI 3006 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
3457 <GIC_SPI 3007 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
3458 interrupt-names = "up 3008 interrupt-names = "uplow", "critical";
3459 #thermal-sensor-cells 3009 #thermal-sensor-cells = <1>;
3460 }; 3010 };
3461 3011
3462 tsens1: thermal-sensor@c26500 3012 tsens1: thermal-sensor@c265000 {
3463 compatible = "qcom,sm 3013 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2";
3464 reg = <0 0x0c265000 0 3014 reg = <0 0x0c265000 0 0x1000>, /* TM */
3465 <0 0x0c223000 0 3015 <0 0x0c223000 0 0x1000>; /* SROT */
3466 #qcom,sensors = <16>; 3016 #qcom,sensors = <16>;
3467 interrupts = <GIC_SPI 3017 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
3468 <GIC_SPI 3018 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
3469 interrupt-names = "up 3019 interrupt-names = "uplow", "critical";
3470 #thermal-sensor-cells 3020 #thermal-sensor-cells = <1>;
3471 }; 3021 };
3472 3022
3473 aoss_qmp: power-management@c3 3023 aoss_qmp: power-management@c300000 {
3474 compatible = "qcom,sm 3024 compatible = "qcom,sm8450-aoss-qmp", "qcom,aoss-qmp";
3475 reg = <0 0x0c300000 0 3025 reg = <0 0x0c300000 0 0x400>;
3476 interrupts-extended = 3026 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
3477 3027 IRQ_TYPE_EDGE_RISING>;
3478 mboxes = <&ipcc IPCC_ 3028 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
3479 3029
3480 #clock-cells = <0>; 3030 #clock-cells = <0>;
3481 }; 3031 };
3482 3032
3483 sram@c3f0000 { <<
3484 compatible = "qcom,rp <<
3485 reg = <0 0x0c3f0000 0 <<
3486 }; <<
3487 <<
3488 spmi_bus: spmi@c400000 { 3033 spmi_bus: spmi@c400000 {
3489 compatible = "qcom,sp 3034 compatible = "qcom,spmi-pmic-arb";
3490 reg = <0 0x0c400000 0 3035 reg = <0 0x0c400000 0 0x00003000>,
3491 <0 0x0c500000 0 3036 <0 0x0c500000 0 0x00400000>,
3492 <0 0x0c440000 0 3037 <0 0x0c440000 0 0x00080000>,
3493 <0 0x0c4c0000 0 3038 <0 0x0c4c0000 0 0x00010000>,
3494 <0 0x0c42d000 0 3039 <0 0x0c42d000 0 0x00010000>;
3495 reg-names = "core", 3040 reg-names = "core",
3496 "chnls", 3041 "chnls",
3497 "obsrvr", 3042 "obsrvr",
3498 "intr", 3043 "intr",
3499 "cnfg"; 3044 "cnfg";
3500 interrupt-names = "pe 3045 interrupt-names = "periph_irq";
3501 interrupts-extended = 3046 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3502 qcom,ee = <0>; 3047 qcom,ee = <0>;
3503 qcom,channel = <0>; 3048 qcom,channel = <0>;
3504 interrupt-controller; 3049 interrupt-controller;
3505 #interrupt-cells = <4 3050 #interrupt-cells = <4>;
3506 #address-cells = <2>; 3051 #address-cells = <2>;
3507 #size-cells = <0>; 3052 #size-cells = <0>;
3508 }; 3053 };
3509 3054
3510 ipcc: mailbox@ed18000 { 3055 ipcc: mailbox@ed18000 {
3511 compatible = "qcom,sm 3056 compatible = "qcom,sm8450-ipcc", "qcom,ipcc";
3512 reg = <0 0x0ed18000 0 3057 reg = <0 0x0ed18000 0 0x1000>;
3513 interrupts = <GIC_SPI 3058 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
3514 interrupt-controller; 3059 interrupt-controller;
3515 #interrupt-cells = <3 3060 #interrupt-cells = <3>;
3516 #mbox-cells = <2>; 3061 #mbox-cells = <2>;
3517 }; 3062 };
3518 3063
3519 tlmm: pinctrl@f100000 { 3064 tlmm: pinctrl@f100000 {
3520 compatible = "qcom,sm 3065 compatible = "qcom,sm8450-tlmm";
3521 reg = <0 0x0f100000 0 3066 reg = <0 0x0f100000 0 0x300000>;
3522 interrupts = <GIC_SPI 3067 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
3523 gpio-controller; 3068 gpio-controller;
3524 #gpio-cells = <2>; 3069 #gpio-cells = <2>;
3525 interrupt-controller; 3070 interrupt-controller;
3526 #interrupt-cells = <2 3071 #interrupt-cells = <2>;
3527 gpio-ranges = <&tlmm 3072 gpio-ranges = <&tlmm 0 0 211>;
3528 wakeup-parent = <&pdc 3073 wakeup-parent = <&pdc>;
3529 3074
3530 sdc2_default_state: s 3075 sdc2_default_state: sdc2-default-state {
3531 clk-pins { 3076 clk-pins {
3532 pins 3077 pins = "sdc2_clk";
3533 drive 3078 drive-strength = <16>;
3534 bias- 3079 bias-disable;
3535 }; 3080 };
3536 3081
3537 cmd-pins { 3082 cmd-pins {
3538 pins 3083 pins = "sdc2_cmd";
3539 drive 3084 drive-strength = <16>;
3540 bias- 3085 bias-pull-up;
3541 }; 3086 };
3542 3087
3543 data-pins { 3088 data-pins {
3544 pins 3089 pins = "sdc2_data";
3545 drive 3090 drive-strength = <16>;
3546 bias- 3091 bias-pull-up;
3547 }; 3092 };
3548 }; 3093 };
3549 3094
3550 sdc2_sleep_state: sdc 3095 sdc2_sleep_state: sdc2-sleep-state {
3551 clk-pins { 3096 clk-pins {
3552 pins 3097 pins = "sdc2_clk";
3553 drive 3098 drive-strength = <2>;
3554 bias- 3099 bias-disable;
3555 }; 3100 };
3556 3101
3557 cmd-pins { 3102 cmd-pins {
3558 pins 3103 pins = "sdc2_cmd";
3559 drive 3104 drive-strength = <2>;
3560 bias- 3105 bias-pull-up;
3561 }; 3106 };
3562 3107
3563 data-pins { 3108 data-pins {
3564 pins 3109 pins = "sdc2_data";
3565 drive 3110 drive-strength = <2>;
3566 bias- 3111 bias-pull-up;
3567 }; 3112 };
3568 }; 3113 };
3569 3114
3570 cci0_default: cci0-de 3115 cci0_default: cci0-default-state {
3571 /* SDA, SCL * 3116 /* SDA, SCL */
3572 pins = "gpio1 3117 pins = "gpio110", "gpio111";
3573 function = "c 3118 function = "cci_i2c";
3574 drive-strengt 3119 drive-strength = <2>;
3575 bias-pull-up; 3120 bias-pull-up;
3576 }; 3121 };
3577 3122
3578 cci0_sleep: cci0-slee 3123 cci0_sleep: cci0-sleep-state {
3579 /* SDA, SCL * 3124 /* SDA, SCL */
3580 pins = "gpio1 3125 pins = "gpio110", "gpio111";
3581 function = "c 3126 function = "cci_i2c";
3582 drive-strengt 3127 drive-strength = <2>;
3583 bias-pull-dow 3128 bias-pull-down;
3584 }; 3129 };
3585 3130
3586 cci1_default: cci1-de 3131 cci1_default: cci1-default-state {
3587 /* SDA, SCL * 3132 /* SDA, SCL */
3588 pins = "gpio1 3133 pins = "gpio112", "gpio113";
3589 function = "c 3134 function = "cci_i2c";
3590 drive-strengt 3135 drive-strength = <2>;
3591 bias-pull-up; 3136 bias-pull-up;
3592 }; 3137 };
3593 3138
3594 cci1_sleep: cci1-slee 3139 cci1_sleep: cci1-sleep-state {
3595 /* SDA, SCL * 3140 /* SDA, SCL */
3596 pins = "gpio1 3141 pins = "gpio112", "gpio113";
3597 function = "c 3142 function = "cci_i2c";
3598 drive-strengt 3143 drive-strength = <2>;
3599 bias-pull-dow 3144 bias-pull-down;
3600 }; 3145 };
3601 3146
3602 cci2_default: cci2-de 3147 cci2_default: cci2-default-state {
3603 /* SDA, SCL * 3148 /* SDA, SCL */
3604 pins = "gpio1 3149 pins = "gpio114", "gpio115";
3605 function = "c 3150 function = "cci_i2c";
3606 drive-strengt 3151 drive-strength = <2>;
3607 bias-pull-up; 3152 bias-pull-up;
3608 }; 3153 };
3609 3154
3610 cci2_sleep: cci2-slee 3155 cci2_sleep: cci2-sleep-state {
3611 /* SDA, SCL * 3156 /* SDA, SCL */
3612 pins = "gpio1 3157 pins = "gpio114", "gpio115";
3613 function = "c 3158 function = "cci_i2c";
3614 drive-strengt 3159 drive-strength = <2>;
3615 bias-pull-dow 3160 bias-pull-down;
3616 }; 3161 };
3617 3162
3618 cci3_default: cci3-de 3163 cci3_default: cci3-default-state {
3619 /* SDA, SCL * 3164 /* SDA, SCL */
3620 pins = "gpio2 3165 pins = "gpio208", "gpio209";
3621 function = "c 3166 function = "cci_i2c";
3622 drive-strengt 3167 drive-strength = <2>;
3623 bias-pull-up; 3168 bias-pull-up;
3624 }; 3169 };
3625 3170
3626 cci3_sleep: cci3-slee 3171 cci3_sleep: cci3-sleep-state {
3627 /* SDA, SCL * 3172 /* SDA, SCL */
3628 pins = "gpio2 3173 pins = "gpio208", "gpio209";
3629 function = "c 3174 function = "cci_i2c";
3630 drive-strengt 3175 drive-strength = <2>;
3631 bias-pull-dow 3176 bias-pull-down;
3632 }; 3177 };
3633 3178
3634 pcie0_default_state: 3179 pcie0_default_state: pcie0-default-state {
3635 perst-pins { 3180 perst-pins {
3636 pins 3181 pins = "gpio94";
3637 funct 3182 function = "gpio";
3638 drive 3183 drive-strength = <2>;
3639 bias- 3184 bias-pull-down;
3640 }; 3185 };
3641 3186
3642 clkreq-pins { 3187 clkreq-pins {
3643 pins 3188 pins = "gpio95";
3644 funct 3189 function = "pcie0_clkreqn";
3645 drive 3190 drive-strength = <2>;
3646 bias- 3191 bias-pull-up;
3647 }; 3192 };
3648 3193
3649 wake-pins { 3194 wake-pins {
3650 pins 3195 pins = "gpio96";
3651 funct 3196 function = "gpio";
3652 drive 3197 drive-strength = <2>;
3653 bias- 3198 bias-pull-up;
3654 }; 3199 };
3655 }; 3200 };
3656 3201
3657 pcie1_default_state: 3202 pcie1_default_state: pcie1-default-state {
3658 perst-pins { 3203 perst-pins {
3659 pins 3204 pins = "gpio97";
3660 funct 3205 function = "gpio";
3661 drive 3206 drive-strength = <2>;
3662 bias- 3207 bias-pull-down;
3663 }; 3208 };
3664 3209
3665 clkreq-pins { 3210 clkreq-pins {
3666 pins 3211 pins = "gpio98";
3667 funct 3212 function = "pcie1_clkreqn";
3668 drive 3213 drive-strength = <2>;
3669 bias- 3214 bias-pull-up;
3670 }; 3215 };
3671 3216
3672 wake-pins { 3217 wake-pins {
3673 pins 3218 pins = "gpio99";
3674 funct 3219 function = "gpio";
3675 drive 3220 drive-strength = <2>;
3676 bias- 3221 bias-pull-up;
3677 }; 3222 };
3678 }; 3223 };
3679 3224
3680 qup_i2c0_data_clk: qu 3225 qup_i2c0_data_clk: qup-i2c0-data-clk-state {
3681 pins = "gpio0 3226 pins = "gpio0", "gpio1";
3682 function = "q 3227 function = "qup0";
3683 }; 3228 };
3684 3229
3685 qup_i2c1_data_clk: qu 3230 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
3686 pins = "gpio4 3231 pins = "gpio4", "gpio5";
3687 function = "q 3232 function = "qup1";
3688 }; 3233 };
3689 3234
3690 qup_i2c2_data_clk: qu 3235 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
3691 pins = "gpio8 3236 pins = "gpio8", "gpio9";
3692 function = "q 3237 function = "qup2";
3693 }; 3238 };
3694 3239
3695 qup_i2c3_data_clk: qu 3240 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
3696 pins = "gpio1 3241 pins = "gpio12", "gpio13";
3697 function = "q 3242 function = "qup3";
3698 }; 3243 };
3699 3244
3700 qup_i2c4_data_clk: qu 3245 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
3701 pins = "gpio1 3246 pins = "gpio16", "gpio17";
3702 function = "q 3247 function = "qup4";
3703 }; 3248 };
3704 3249
3705 qup_i2c5_data_clk: qu 3250 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
3706 pins = "gpio2 3251 pins = "gpio206", "gpio207";
3707 function = "q 3252 function = "qup5";
3708 }; 3253 };
3709 3254
3710 qup_i2c6_data_clk: qu 3255 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
3711 pins = "gpio2 3256 pins = "gpio20", "gpio21";
3712 function = "q 3257 function = "qup6";
3713 }; 3258 };
3714 3259
3715 qup_i2c8_data_clk: qu 3260 qup_i2c8_data_clk: qup-i2c8-data-clk-state {
3716 pins = "gpio2 3261 pins = "gpio28", "gpio29";
3717 function = "q 3262 function = "qup8";
3718 }; 3263 };
3719 3264
3720 qup_i2c9_data_clk: qu 3265 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
3721 pins = "gpio3 3266 pins = "gpio32", "gpio33";
3722 function = "q 3267 function = "qup9";
3723 }; 3268 };
3724 3269
3725 qup_i2c10_data_clk: q 3270 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
3726 pins = "gpio3 3271 pins = "gpio36", "gpio37";
3727 function = "q 3272 function = "qup10";
3728 }; 3273 };
3729 3274
3730 qup_i2c11_data_clk: q 3275 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
3731 pins = "gpio4 3276 pins = "gpio40", "gpio41";
3732 function = "q 3277 function = "qup11";
3733 }; 3278 };
3734 3279
3735 qup_i2c12_data_clk: q 3280 qup_i2c12_data_clk: qup-i2c12-data-clk-state {
3736 pins = "gpio4 3281 pins = "gpio44", "gpio45";
3737 function = "q 3282 function = "qup12";
3738 }; 3283 };
3739 3284
3740 qup_i2c13_data_clk: q 3285 qup_i2c13_data_clk: qup-i2c13-data-clk-state {
3741 pins = "gpio4 3286 pins = "gpio48", "gpio49";
3742 function = "q 3287 function = "qup13";
3743 drive-strengt 3288 drive-strength = <2>;
3744 bias-pull-up; 3289 bias-pull-up;
3745 }; 3290 };
3746 3291
3747 qup_i2c14_data_clk: q 3292 qup_i2c14_data_clk: qup-i2c14-data-clk-state {
3748 pins = "gpio5 3293 pins = "gpio52", "gpio53";
3749 function = "q 3294 function = "qup14";
3750 drive-strengt 3295 drive-strength = <2>;
3751 bias-pull-up; 3296 bias-pull-up;
3752 }; 3297 };
3753 3298
3754 qup_i2c15_data_clk: q 3299 qup_i2c15_data_clk: qup-i2c15-data-clk-state {
3755 pins = "gpio5 3300 pins = "gpio56", "gpio57";
3756 function = "q 3301 function = "qup15";
3757 }; 3302 };
3758 3303
3759 qup_i2c16_data_clk: q 3304 qup_i2c16_data_clk: qup-i2c16-data-clk-state {
3760 pins = "gpio6 3305 pins = "gpio60", "gpio61";
3761 function = "q 3306 function = "qup16";
3762 }; 3307 };
3763 3308
3764 qup_i2c17_data_clk: q 3309 qup_i2c17_data_clk: qup-i2c17-data-clk-state {
3765 pins = "gpio6 3310 pins = "gpio64", "gpio65";
3766 function = "q 3311 function = "qup17";
3767 }; 3312 };
3768 3313
3769 qup_i2c18_data_clk: q 3314 qup_i2c18_data_clk: qup-i2c18-data-clk-state {
3770 pins = "gpio6 3315 pins = "gpio68", "gpio69";
3771 function = "q 3316 function = "qup18";
3772 }; 3317 };
3773 3318
3774 qup_i2c19_data_clk: q 3319 qup_i2c19_data_clk: qup-i2c19-data-clk-state {
3775 pins = "gpio7 3320 pins = "gpio72", "gpio73";
3776 function = "q 3321 function = "qup19";
3777 }; 3322 };
3778 3323
3779 qup_i2c20_data_clk: q 3324 qup_i2c20_data_clk: qup-i2c20-data-clk-state {
3780 pins = "gpio7 3325 pins = "gpio76", "gpio77";
3781 function = "q 3326 function = "qup20";
3782 }; 3327 };
3783 3328
3784 qup_i2c21_data_clk: q 3329 qup_i2c21_data_clk: qup-i2c21-data-clk-state {
3785 pins = "gpio8 3330 pins = "gpio80", "gpio81";
3786 function = "q 3331 function = "qup21";
3787 }; 3332 };
3788 3333
3789 qup_spi0_cs: qup-spi0 3334 qup_spi0_cs: qup-spi0-cs-state {
3790 pins = "gpio3 3335 pins = "gpio3";
3791 function = "q 3336 function = "qup0";
3792 }; 3337 };
3793 3338
3794 qup_spi0_data_clk: qu 3339 qup_spi0_data_clk: qup-spi0-data-clk-state {
3795 pins = "gpio0 3340 pins = "gpio0", "gpio1", "gpio2";
3796 function = "q 3341 function = "qup0";
3797 }; 3342 };
3798 3343
3799 qup_spi1_cs: qup-spi1 3344 qup_spi1_cs: qup-spi1-cs-state {
3800 pins = "gpio7 3345 pins = "gpio7";
3801 function = "q 3346 function = "qup1";
3802 }; 3347 };
3803 3348
3804 qup_spi1_data_clk: qu 3349 qup_spi1_data_clk: qup-spi1-data-clk-state {
3805 pins = "gpio4 3350 pins = "gpio4", "gpio5", "gpio6";
3806 function = "q 3351 function = "qup1";
3807 }; 3352 };
3808 3353
3809 qup_spi2_cs: qup-spi2 3354 qup_spi2_cs: qup-spi2-cs-state {
3810 pins = "gpio1 3355 pins = "gpio11";
3811 function = "q 3356 function = "qup2";
3812 }; 3357 };
3813 3358
3814 qup_spi2_data_clk: qu 3359 qup_spi2_data_clk: qup-spi2-data-clk-state {
3815 pins = "gpio8 3360 pins = "gpio8", "gpio9", "gpio10";
3816 function = "q 3361 function = "qup2";
3817 }; 3362 };
3818 3363
3819 qup_spi3_cs: qup-spi3 3364 qup_spi3_cs: qup-spi3-cs-state {
3820 pins = "gpio1 3365 pins = "gpio15";
3821 function = "q 3366 function = "qup3";
3822 }; 3367 };
3823 3368
3824 qup_spi3_data_clk: qu 3369 qup_spi3_data_clk: qup-spi3-data-clk-state {
3825 pins = "gpio1 3370 pins = "gpio12", "gpio13", "gpio14";
3826 function = "q 3371 function = "qup3";
3827 }; 3372 };
3828 3373
3829 qup_spi4_cs: qup-spi4 3374 qup_spi4_cs: qup-spi4-cs-state {
3830 pins = "gpio1 3375 pins = "gpio19";
3831 function = "q 3376 function = "qup4";
3832 drive-strengt 3377 drive-strength = <6>;
3833 bias-disable; 3378 bias-disable;
3834 }; 3379 };
3835 3380
3836 qup_spi4_data_clk: qu 3381 qup_spi4_data_clk: qup-spi4-data-clk-state {
3837 pins = "gpio1 3382 pins = "gpio16", "gpio17", "gpio18";
3838 function = "q 3383 function = "qup4";
3839 }; 3384 };
3840 3385
3841 qup_spi5_cs: qup-spi5 3386 qup_spi5_cs: qup-spi5-cs-state {
3842 pins = "gpio8 3387 pins = "gpio85";
3843 function = "q 3388 function = "qup5";
3844 }; 3389 };
3845 3390
3846 qup_spi5_data_clk: qu 3391 qup_spi5_data_clk: qup-spi5-data-clk-state {
3847 pins = "gpio2 3392 pins = "gpio206", "gpio207", "gpio84";
3848 function = "q 3393 function = "qup5";
3849 }; 3394 };
3850 3395
3851 qup_spi6_cs: qup-spi6 3396 qup_spi6_cs: qup-spi6-cs-state {
3852 pins = "gpio2 3397 pins = "gpio23";
3853 function = "q 3398 function = "qup6";
3854 }; 3399 };
3855 3400
3856 qup_spi6_data_clk: qu 3401 qup_spi6_data_clk: qup-spi6-data-clk-state {
3857 pins = "gpio2 3402 pins = "gpio20", "gpio21", "gpio22";
3858 function = "q 3403 function = "qup6";
3859 }; 3404 };
3860 3405
3861 qup_spi8_cs: qup-spi8 3406 qup_spi8_cs: qup-spi8-cs-state {
3862 pins = "gpio3 3407 pins = "gpio31";
3863 function = "q 3408 function = "qup8";
3864 }; 3409 };
3865 3410
3866 qup_spi8_data_clk: qu 3411 qup_spi8_data_clk: qup-spi8-data-clk-state {
3867 pins = "gpio2 3412 pins = "gpio28", "gpio29", "gpio30";
3868 function = "q 3413 function = "qup8";
3869 }; 3414 };
3870 3415
3871 qup_spi9_cs: qup-spi9 3416 qup_spi9_cs: qup-spi9-cs-state {
3872 pins = "gpio3 3417 pins = "gpio35";
3873 function = "q 3418 function = "qup9";
3874 }; 3419 };
3875 3420
3876 qup_spi9_data_clk: qu 3421 qup_spi9_data_clk: qup-spi9-data-clk-state {
3877 pins = "gpio3 3422 pins = "gpio32", "gpio33", "gpio34";
3878 function = "q 3423 function = "qup9";
3879 }; 3424 };
3880 3425
3881 qup_spi10_cs: qup-spi 3426 qup_spi10_cs: qup-spi10-cs-state {
3882 pins = "gpio3 3427 pins = "gpio39";
3883 function = "q 3428 function = "qup10";
3884 }; 3429 };
3885 3430
3886 qup_spi10_data_clk: q 3431 qup_spi10_data_clk: qup-spi10-data-clk-state {
3887 pins = "gpio3 3432 pins = "gpio36", "gpio37", "gpio38";
3888 function = "q 3433 function = "qup10";
3889 }; 3434 };
3890 3435
3891 qup_spi11_cs: qup-spi 3436 qup_spi11_cs: qup-spi11-cs-state {
3892 pins = "gpio4 3437 pins = "gpio43";
3893 function = "q 3438 function = "qup11";
3894 }; 3439 };
3895 3440
3896 qup_spi11_data_clk: q 3441 qup_spi11_data_clk: qup-spi11-data-clk-state {
3897 pins = "gpio4 3442 pins = "gpio40", "gpio41", "gpio42";
3898 function = "q 3443 function = "qup11";
3899 }; 3444 };
3900 3445
3901 qup_spi12_cs: qup-spi 3446 qup_spi12_cs: qup-spi12-cs-state {
3902 pins = "gpio4 3447 pins = "gpio47";
3903 function = "q 3448 function = "qup12";
3904 }; 3449 };
3905 3450
3906 qup_spi12_data_clk: q 3451 qup_spi12_data_clk: qup-spi12-data-clk-state {
3907 pins = "gpio4 3452 pins = "gpio44", "gpio45", "gpio46";
3908 function = "q 3453 function = "qup12";
3909 }; 3454 };
3910 3455
3911 qup_spi13_cs: qup-spi 3456 qup_spi13_cs: qup-spi13-cs-state {
3912 pins = "gpio5 3457 pins = "gpio51";
3913 function = "q 3458 function = "qup13";
3914 }; 3459 };
3915 3460
3916 qup_spi13_data_clk: q 3461 qup_spi13_data_clk: qup-spi13-data-clk-state {
3917 pins = "gpio4 3462 pins = "gpio48", "gpio49", "gpio50";
3918 function = "q 3463 function = "qup13";
3919 }; 3464 };
3920 3465
3921 qup_spi14_cs: qup-spi 3466 qup_spi14_cs: qup-spi14-cs-state {
3922 pins = "gpio5 3467 pins = "gpio55";
3923 function = "q 3468 function = "qup14";
3924 }; 3469 };
3925 3470
3926 qup_spi14_data_clk: q 3471 qup_spi14_data_clk: qup-spi14-data-clk-state {
3927 pins = "gpio5 3472 pins = "gpio52", "gpio53", "gpio54";
3928 function = "q 3473 function = "qup14";
3929 }; 3474 };
3930 3475
3931 qup_spi15_cs: qup-spi 3476 qup_spi15_cs: qup-spi15-cs-state {
3932 pins = "gpio5 3477 pins = "gpio59";
3933 function = "q 3478 function = "qup15";
3934 }; 3479 };
3935 3480
3936 qup_spi15_data_clk: q 3481 qup_spi15_data_clk: qup-spi15-data-clk-state {
3937 pins = "gpio5 3482 pins = "gpio56", "gpio57", "gpio58";
3938 function = "q 3483 function = "qup15";
3939 }; 3484 };
3940 3485
3941 qup_spi16_cs: qup-spi 3486 qup_spi16_cs: qup-spi16-cs-state {
3942 pins = "gpio6 3487 pins = "gpio63";
3943 function = "q 3488 function = "qup16";
3944 }; 3489 };
3945 3490
3946 qup_spi16_data_clk: q 3491 qup_spi16_data_clk: qup-spi16-data-clk-state {
3947 pins = "gpio6 3492 pins = "gpio60", "gpio61", "gpio62";
3948 function = "q 3493 function = "qup16";
3949 }; 3494 };
3950 3495
3951 qup_spi17_cs: qup-spi 3496 qup_spi17_cs: qup-spi17-cs-state {
3952 pins = "gpio6 3497 pins = "gpio67";
3953 function = "q 3498 function = "qup17";
3954 }; 3499 };
3955 3500
3956 qup_spi17_data_clk: q 3501 qup_spi17_data_clk: qup-spi17-data-clk-state {
3957 pins = "gpio6 3502 pins = "gpio64", "gpio65", "gpio66";
3958 function = "q 3503 function = "qup17";
3959 }; 3504 };
3960 3505
3961 qup_spi18_cs: qup-spi 3506 qup_spi18_cs: qup-spi18-cs-state {
3962 pins = "gpio7 3507 pins = "gpio71";
3963 function = "q 3508 function = "qup18";
3964 drive-strengt 3509 drive-strength = <6>;
3965 bias-disable; 3510 bias-disable;
3966 }; 3511 };
3967 3512
3968 qup_spi18_data_clk: q 3513 qup_spi18_data_clk: qup-spi18-data-clk-state {
3969 pins = "gpio6 3514 pins = "gpio68", "gpio69", "gpio70";
3970 function = "q 3515 function = "qup18";
3971 drive-strengt 3516 drive-strength = <6>;
3972 bias-disable; 3517 bias-disable;
3973 }; 3518 };
3974 3519
3975 qup_spi19_cs: qup-spi 3520 qup_spi19_cs: qup-spi19-cs-state {
3976 pins = "gpio7 3521 pins = "gpio75";
3977 function = "q 3522 function = "qup19";
3978 drive-strengt 3523 drive-strength = <6>;
3979 bias-disable; 3524 bias-disable;
3980 }; 3525 };
3981 3526
3982 qup_spi19_data_clk: q 3527 qup_spi19_data_clk: qup-spi19-data-clk-state {
3983 pins = "gpio7 3528 pins = "gpio72", "gpio73", "gpio74";
3984 function = "q 3529 function = "qup19";
3985 drive-strengt 3530 drive-strength = <6>;
3986 bias-disable; 3531 bias-disable;
3987 }; 3532 };
3988 3533
3989 qup_spi20_cs: qup-spi 3534 qup_spi20_cs: qup-spi20-cs-state {
3990 pins = "gpio7 3535 pins = "gpio79";
3991 function = "q 3536 function = "qup20";
3992 }; 3537 };
3993 3538
3994 qup_spi20_data_clk: q 3539 qup_spi20_data_clk: qup-spi20-data-clk-state {
3995 pins = "gpio7 3540 pins = "gpio76", "gpio77", "gpio78";
3996 function = "q 3541 function = "qup20";
3997 }; 3542 };
3998 3543
3999 qup_spi21_cs: qup-spi 3544 qup_spi21_cs: qup-spi21-cs-state {
4000 pins = "gpio8 3545 pins = "gpio83";
4001 function = "q 3546 function = "qup21";
4002 }; 3547 };
4003 3548
4004 qup_spi21_data_clk: q 3549 qup_spi21_data_clk: qup-spi21-data-clk-state {
4005 pins = "gpio8 3550 pins = "gpio80", "gpio81", "gpio82";
4006 function = "q 3551 function = "qup21";
4007 }; 3552 };
4008 3553
4009 qup_uart7_rx: qup-uar 3554 qup_uart7_rx: qup-uart7-rx-state {
4010 pins = "gpio2 3555 pins = "gpio26";
4011 function = "q 3556 function = "qup7";
4012 drive-strengt 3557 drive-strength = <2>;
4013 bias-disable; 3558 bias-disable;
4014 }; 3559 };
4015 3560
4016 qup_uart7_tx: qup-uar 3561 qup_uart7_tx: qup-uart7-tx-state {
4017 pins = "gpio2 3562 pins = "gpio27";
4018 function = "q 3563 function = "qup7";
4019 drive-strengt 3564 drive-strength = <2>;
4020 bias-disable; 3565 bias-disable;
4021 }; 3566 };
4022 3567
4023 qup_uart20_default: q 3568 qup_uart20_default: qup-uart20-default-state {
4024 pins = "gpio7 3569 pins = "gpio76", "gpio77", "gpio78", "gpio79";
4025 function = "q 3570 function = "qup20";
4026 }; 3571 };
>> 3572
4027 }; 3573 };
4028 3574
4029 lpass_tlmm: pinctrl@3440000 { 3575 lpass_tlmm: pinctrl@3440000 {
4030 compatible = "qcom,sm 3576 compatible = "qcom,sm8450-lpass-lpi-pinctrl";
4031 reg = <0 0x03440000 0 3577 reg = <0 0x03440000 0x0 0x20000>,
4032 <0 0x034d0000 0 3578 <0 0x034d0000 0x0 0x10000>;
4033 gpio-controller; 3579 gpio-controller;
4034 #gpio-cells = <2>; 3580 #gpio-cells = <2>;
4035 gpio-ranges = <&lpass 3581 gpio-ranges = <&lpass_tlmm 0 0 23>;
4036 3582
4037 clocks = <&q6prmcc LP 3583 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
4038 <&q6prmcc LP 3584 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
4039 clock-names = "core", 3585 clock-names = "core", "audio";
4040 3586
4041 tx_swr_active: tx-swr 3587 tx_swr_active: tx-swr-active-state {
4042 clk-pins { 3588 clk-pins {
4043 pins 3589 pins = "gpio0";
4044 funct 3590 function = "swr_tx_clk";
4045 drive 3591 drive-strength = <2>;
4046 slew- 3592 slew-rate = <1>;
4047 bias- 3593 bias-disable;
4048 }; 3594 };
4049 3595
4050 data-pins { 3596 data-pins {
4051 pins 3597 pins = "gpio1", "gpio2", "gpio14";
4052 funct 3598 function = "swr_tx_data";
4053 drive 3599 drive-strength = <2>;
4054 slew- 3600 slew-rate = <1>;
4055 bias- 3601 bias-bus-hold;
4056 }; 3602 };
4057 }; 3603 };
4058 3604
4059 rx_swr_active: rx-swr 3605 rx_swr_active: rx-swr-active-state {
4060 clk-pins { 3606 clk-pins {
4061 pins 3607 pins = "gpio3";
4062 funct 3608 function = "swr_rx_clk";
4063 drive 3609 drive-strength = <2>;
4064 slew- 3610 slew-rate = <1>;
4065 bias- 3611 bias-disable;
4066 }; 3612 };
4067 3613
4068 data-pins { 3614 data-pins {
4069 pins 3615 pins = "gpio4", "gpio5";
4070 funct 3616 function = "swr_rx_data";
4071 drive 3617 drive-strength = <2>;
4072 slew- 3618 slew-rate = <1>;
4073 bias- 3619 bias-bus-hold;
4074 }; 3620 };
4075 }; 3621 };
4076 3622
4077 dmic01_default: dmic0 3623 dmic01_default: dmic01-default-state {
4078 clk-pins { 3624 clk-pins {
4079 pins 3625 pins = "gpio6";
4080 funct 3626 function = "dmic1_clk";
4081 drive 3627 drive-strength = <8>;
4082 outpu 3628 output-high;
4083 }; 3629 };
4084 3630
4085 data-pins { 3631 data-pins {
4086 pins 3632 pins = "gpio7";
4087 funct 3633 function = "dmic1_data";
4088 drive 3634 drive-strength = <8>;
>> 3635 input-enable;
4089 }; 3636 };
4090 }; 3637 };
4091 3638
4092 dmic23_default: dmic2 !! 3639 dmic02_default: dmic02-default-state {
4093 clk-pins { 3640 clk-pins {
4094 pins 3641 pins = "gpio8";
4095 funct 3642 function = "dmic2_clk";
4096 drive 3643 drive-strength = <8>;
4097 outpu 3644 output-high;
4098 }; 3645 };
4099 3646
4100 data-pins { 3647 data-pins {
4101 pins 3648 pins = "gpio9";
4102 funct 3649 function = "dmic2_data";
4103 drive 3650 drive-strength = <8>;
>> 3651 input-enable;
4104 }; 3652 };
4105 }; 3653 };
4106 3654
4107 wsa_swr_active: wsa-s 3655 wsa_swr_active: wsa-swr-active-state {
4108 clk-pins { 3656 clk-pins {
4109 pins 3657 pins = "gpio10";
4110 funct 3658 function = "wsa_swr_clk";
4111 drive 3659 drive-strength = <2>;
4112 slew- 3660 slew-rate = <1>;
4113 bias- 3661 bias-disable;
4114 }; 3662 };
4115 3663
4116 data-pins { 3664 data-pins {
4117 pins 3665 pins = "gpio11";
4118 funct 3666 function = "wsa_swr_data";
4119 drive 3667 drive-strength = <2>;
4120 slew- 3668 slew-rate = <1>;
4121 bias- 3669 bias-bus-hold;
4122 }; 3670 };
4123 }; 3671 };
4124 3672
4125 wsa2_swr_active: wsa2 3673 wsa2_swr_active: wsa2-swr-active-state {
4126 clk-pins { 3674 clk-pins {
4127 pins 3675 pins = "gpio15";
4128 funct 3676 function = "wsa2_swr_clk";
4129 drive 3677 drive-strength = <2>;
4130 slew- 3678 slew-rate = <1>;
4131 bias- 3679 bias-disable;
4132 }; 3680 };
4133 3681
4134 data-pins { 3682 data-pins {
4135 pins 3683 pins = "gpio16";
4136 funct 3684 function = "wsa2_swr_data";
4137 drive 3685 drive-strength = <2>;
4138 slew- 3686 slew-rate = <1>;
4139 bias- 3687 bias-bus-hold;
4140 }; 3688 };
4141 }; 3689 };
4142 }; 3690 };
4143 3691
4144 sram@146aa000 { <<
4145 compatible = "qcom,sm <<
4146 reg = <0 0x146aa000 0 <<
4147 ranges = <0 0 0x146aa <<
4148 <<
4149 #address-cells = <1>; <<
4150 #size-cells = <1>; <<
4151 <<
4152 pil-reloc@94c { <<
4153 compatible = <<
4154 reg = <0x94c <<
4155 }; <<
4156 }; <<
4157 <<
4158 apps_smmu: iommu@15000000 { 3692 apps_smmu: iommu@15000000 {
4159 compatible = "qcom,sm 3693 compatible = "qcom,sm8450-smmu-500", "arm,mmu-500";
4160 reg = <0 0x15000000 0 3694 reg = <0 0x15000000 0 0x100000>;
4161 #iommu-cells = <2>; 3695 #iommu-cells = <2>;
4162 #global-interrupts = 3696 #global-interrupts = <1>;
4163 interrupts = <GIC_SPI !! 3697 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
4164 <GIC_SPI !! 3698 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
4165 <GIC_SPI !! 3699 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
4166 <GIC_SPI !! 3700 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
4167 <GIC_SPI !! 3701 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
4168 <GIC_SPI !! 3702 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
4169 <GIC_SPI !! 3703 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
4170 <GIC_SPI !! 3704 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
4171 <GIC_SPI !! 3705 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
4172 <GIC_SPI !! 3706 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
4173 <GIC_SPI !! 3707 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
4174 <GIC_SPI !! 3708 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
4175 <GIC_SPI !! 3709 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
4176 <GIC_SPI !! 3710 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
4177 <GIC_SPI !! 3711 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
4178 <GIC_SPI !! 3712 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
4179 <GIC_SPI !! 3713 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
4180 <GIC_SPI !! 3714 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
4181 <GIC_SPI !! 3715 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
4182 <GIC_SPI !! 3716 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
4183 <GIC_SPI !! 3717 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
4184 <GIC_SPI !! 3718 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
4185 <GIC_SPI !! 3719 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
4186 <GIC_SPI !! 3720 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
4187 <GIC_SPI !! 3721 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
4188 <GIC_SPI !! 3722 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
4189 <GIC_SPI !! 3723 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
4190 <GIC_SPI !! 3724 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
4191 <GIC_SPI !! 3725 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
4192 <GIC_SPI !! 3726 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
4193 <GIC_SPI !! 3727 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
4194 <GIC_SPI !! 3728 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
4195 <GIC_SPI !! 3729 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
4196 <GIC_SPI !! 3730 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
4197 <GIC_SPI !! 3731 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
4198 <GIC_SPI !! 3732 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
4199 <GIC_SPI !! 3733 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
4200 <GIC_SPI !! 3734 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
4201 <GIC_SPI !! 3735 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
4202 <GIC_SPI !! 3736 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
4203 <GIC_SPI !! 3737 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
4204 <GIC_SPI !! 3738 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
4205 <GIC_SPI !! 3739 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
4206 <GIC_SPI !! 3740 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
4207 <GIC_SPI !! 3741 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
4208 <GIC_SPI !! 3742 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
4209 <GIC_SPI !! 3743 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
4210 <GIC_SPI !! 3744 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
4211 <GIC_SPI !! 3745 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
4212 <GIC_SPI !! 3746 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
4213 <GIC_SPI !! 3747 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
4214 <GIC_SPI !! 3748 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
4215 <GIC_SPI !! 3749 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
4216 <GIC_SPI !! 3750 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
4217 <GIC_SPI !! 3751 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
4218 <GIC_SPI !! 3752 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
4219 <GIC_SPI !! 3753 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
4220 <GIC_SPI !! 3754 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
4221 <GIC_SPI !! 3755 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
4222 <GIC_SPI !! 3756 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
4223 <GIC_SPI !! 3757 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
4224 <GIC_SPI !! 3758 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
4225 <GIC_SPI !! 3759 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
4226 <GIC_SPI !! 3760 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
4227 <GIC_SPI !! 3761 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
4228 <GIC_SPI !! 3762 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
4229 <GIC_SPI !! 3763 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
4230 <GIC_SPI !! 3764 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
4231 <GIC_SPI !! 3765 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
4232 <GIC_SPI !! 3766 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
4233 <GIC_SPI !! 3767 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
4234 <GIC_SPI !! 3768 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
4235 <GIC_SPI !! 3769 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
4236 <GIC_SPI !! 3770 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
4237 <GIC_SPI !! 3771 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
4238 <GIC_SPI !! 3772 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
4239 <GIC_SPI !! 3773 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
4240 <GIC_SPI !! 3774 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
4241 <GIC_SPI !! 3775 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
4242 <GIC_SPI !! 3776 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
4243 <GIC_SPI !! 3777 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
4244 <GIC_SPI !! 3778 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
4245 <GIC_SPI !! 3779 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
4246 <GIC_SPI !! 3780 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
4247 <GIC_SPI !! 3781 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
4248 <GIC_SPI !! 3782 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
4249 <GIC_SPI !! 3783 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
4250 <GIC_SPI !! 3784 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
4251 <GIC_SPI !! 3785 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
4252 <GIC_SPI !! 3786 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
4253 <GIC_SPI !! 3787 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
4254 <GIC_SPI !! 3788 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
4255 <GIC_SPI !! 3789 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
4256 <GIC_SPI !! 3790 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
4257 <GIC_SPI !! 3791 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
4258 <GIC_SPI !! 3792 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
4259 <GIC_SPI !! 3793 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>;
4260 }; 3794 };
4261 3795
4262 intc: interrupt-controller@17 3796 intc: interrupt-controller@17100000 {
4263 compatible = "arm,gic 3797 compatible = "arm,gic-v3";
4264 #interrupt-cells = <3 3798 #interrupt-cells = <3>;
4265 interrupt-controller; 3799 interrupt-controller;
4266 #redistributor-region 3800 #redistributor-regions = <1>;
4267 redistributor-stride 3801 redistributor-stride = <0x0 0x40000>;
4268 reg = <0x0 0x17100000 3802 reg = <0x0 0x17100000 0x0 0x10000>, /* GICD */
4269 <0x0 0x17180000 3803 <0x0 0x17180000 0x0 0x200000>; /* GICR * 8 */
4270 interrupts = <GIC_PPI 3804 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
4271 #address-cells = <2>; 3805 #address-cells = <2>;
4272 #size-cells = <2>; 3806 #size-cells = <2>;
4273 ranges; 3807 ranges;
4274 3808
4275 gic_its: msi-controll 3809 gic_its: msi-controller@17140000 {
4276 compatible = 3810 compatible = "arm,gic-v3-its";
4277 reg = <0x0 0x 3811 reg = <0x0 0x17140000 0x0 0x20000>;
4278 msi-controlle 3812 msi-controller;
4279 #msi-cells = 3813 #msi-cells = <1>;
4280 }; 3814 };
4281 }; 3815 };
4282 3816
4283 timer@17420000 { 3817 timer@17420000 {
4284 compatible = "arm,arm 3818 compatible = "arm,armv7-timer-mem";
4285 #address-cells = <1>; 3819 #address-cells = <1>;
4286 #size-cells = <1>; 3820 #size-cells = <1>;
4287 ranges = <0 0 0 0x200 3821 ranges = <0 0 0 0x20000000>;
4288 reg = <0x0 0x17420000 3822 reg = <0x0 0x17420000 0x0 0x1000>;
4289 clock-frequency = <19 3823 clock-frequency = <19200000>;
4290 3824
4291 frame@17421000 { 3825 frame@17421000 {
4292 frame-number 3826 frame-number = <0>;
4293 interrupts = 3827 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
4294 3828 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
4295 reg = <0x1742 3829 reg = <0x17421000 0x1000>,
4296 <0x1742 3830 <0x17422000 0x1000>;
4297 }; 3831 };
4298 3832
4299 frame@17423000 { 3833 frame@17423000 {
4300 frame-number 3834 frame-number = <1>;
4301 interrupts = 3835 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
4302 reg = <0x1742 3836 reg = <0x17423000 0x1000>;
4303 status = "dis 3837 status = "disabled";
4304 }; 3838 };
4305 3839
4306 frame@17425000 { 3840 frame@17425000 {
4307 frame-number 3841 frame-number = <2>;
4308 interrupts = 3842 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
4309 reg = <0x1742 3843 reg = <0x17425000 0x1000>;
4310 status = "dis 3844 status = "disabled";
4311 }; 3845 };
4312 3846
4313 frame@17427000 { 3847 frame@17427000 {
4314 frame-number 3848 frame-number = <3>;
4315 interrupts = 3849 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
4316 reg = <0x1742 3850 reg = <0x17427000 0x1000>;
4317 status = "dis 3851 status = "disabled";
4318 }; 3852 };
4319 3853
4320 frame@17429000 { 3854 frame@17429000 {
4321 frame-number 3855 frame-number = <4>;
4322 interrupts = 3856 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
4323 reg = <0x1742 3857 reg = <0x17429000 0x1000>;
4324 status = "dis 3858 status = "disabled";
4325 }; 3859 };
4326 3860
4327 frame@1742b000 { 3861 frame@1742b000 {
4328 frame-number 3862 frame-number = <5>;
4329 interrupts = 3863 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
4330 reg = <0x1742 3864 reg = <0x1742b000 0x1000>;
4331 status = "dis 3865 status = "disabled";
4332 }; 3866 };
4333 3867
4334 frame@1742d000 { 3868 frame@1742d000 {
4335 frame-number 3869 frame-number = <6>;
4336 interrupts = 3870 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
4337 reg = <0x1742 3871 reg = <0x1742d000 0x1000>;
4338 status = "dis 3872 status = "disabled";
4339 }; 3873 };
4340 }; 3874 };
4341 3875
4342 apps_rsc: rsc@17a00000 { 3876 apps_rsc: rsc@17a00000 {
4343 label = "apps_rsc"; 3877 label = "apps_rsc";
4344 compatible = "qcom,rp 3878 compatible = "qcom,rpmh-rsc";
4345 reg = <0x0 0x17a00000 3879 reg = <0x0 0x17a00000 0x0 0x10000>,
4346 <0x0 0x17a10000 3880 <0x0 0x17a10000 0x0 0x10000>,
4347 <0x0 0x17a20000 3881 <0x0 0x17a20000 0x0 0x10000>,
4348 <0x0 0x17a30000 3882 <0x0 0x17a30000 0x0 0x10000>;
4349 reg-names = "drv-0", 3883 reg-names = "drv-0", "drv-1", "drv-2", "drv-3";
4350 interrupts = <GIC_SPI 3884 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
4351 <GIC_SPI 3885 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
4352 <GIC_SPI 3886 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
4353 qcom,tcs-offset = <0x 3887 qcom,tcs-offset = <0xd00>;
4354 qcom,drv-id = <2>; 3888 qcom,drv-id = <2>;
4355 qcom,tcs-config = <AC 3889 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
4356 <WA 3890 <WAKE_TCS 2>, <CONTROL_TCS 0>;
4357 power-domains = <&CLU 3891 power-domains = <&CLUSTER_PD>;
4358 3892
4359 apps_bcm_voter: bcm-v 3893 apps_bcm_voter: bcm-voter {
4360 compatible = 3894 compatible = "qcom,bcm-voter";
4361 }; 3895 };
4362 3896
4363 rpmhcc: clock-control 3897 rpmhcc: clock-controller {
4364 compatible = 3898 compatible = "qcom,sm8450-rpmh-clk";
4365 #clock-cells 3899 #clock-cells = <1>;
4366 clock-names = 3900 clock-names = "xo";
4367 clocks = <&xo 3901 clocks = <&xo_board>;
4368 }; 3902 };
4369 3903
4370 rpmhpd: power-control 3904 rpmhpd: power-controller {
4371 compatible = 3905 compatible = "qcom,sm8450-rpmhpd";
4372 #power-domain 3906 #power-domain-cells = <1>;
4373 operating-poi 3907 operating-points-v2 = <&rpmhpd_opp_table>;
4374 3908
4375 rpmhpd_opp_ta 3909 rpmhpd_opp_table: opp-table {
4376 compa 3910 compatible = "operating-points-v2";
4377 3911
4378 rpmhp 3912 rpmhpd_opp_ret: opp1 {
4379 3913 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4380 }; 3914 };
4381 3915
4382 rpmhp 3916 rpmhpd_opp_min_svs: opp2 {
4383 3917 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4384 }; 3918 };
4385 3919
4386 rpmhp 3920 rpmhpd_opp_low_svs_d1: opp3 {
4387 3921 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
4388 }; 3922 };
4389 3923
4390 rpmhp 3924 rpmhpd_opp_low_svs: opp4 {
4391 3925 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4392 }; 3926 };
4393 3927
4394 rpmhp !! 3928 rpmhpd_opp_svs: opp5 {
4395 <<
4396 }; <<
4397 <<
4398 rpmhp <<
4399 3929 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4400 }; 3930 };
4401 3931
4402 rpmhp !! 3932 rpmhpd_opp_svs_l1: opp6 {
4403 <<
4404 }; <<
4405 <<
4406 rpmhp <<
4407 3933 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4408 }; 3934 };
4409 3935
4410 rpmhp !! 3936 rpmhpd_opp_nom: opp7 {
4411 <<
4412 }; <<
4413 <<
4414 rpmhp <<
4415 3937 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4416 }; 3938 };
4417 3939
4418 rpmhp !! 3940 rpmhpd_opp_nom_l1: opp8 {
4419 3941 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4420 }; 3942 };
4421 3943
4422 rpmhp !! 3944 rpmhpd_opp_nom_l2: opp9 {
4423 3945 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4424 }; 3946 };
4425 3947
4426 rpmhp !! 3948 rpmhpd_opp_turbo: opp10 {
4427 3949 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4428 }; 3950 };
4429 3951
4430 rpmhp !! 3952 rpmhpd_opp_turbo_l1: opp11 {
4431 3953 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4432 }; 3954 };
4433 }; 3955 };
4434 }; 3956 };
4435 }; 3957 };
4436 3958
4437 cpufreq_hw: cpufreq@17d91000 3959 cpufreq_hw: cpufreq@17d91000 {
4438 compatible = "qcom,sm 3960 compatible = "qcom,sm8450-cpufreq-epss", "qcom,cpufreq-epss";
4439 reg = <0 0x17d91000 0 3961 reg = <0 0x17d91000 0 0x1000>,
4440 <0 0x17d92000 0 3962 <0 0x17d92000 0 0x1000>,
4441 <0 0x17d93000 0 3963 <0 0x17d93000 0 0x1000>;
4442 reg-names = "freq-dom 3964 reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
4443 clocks = <&rpmhcc RPM 3965 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
4444 clock-names = "xo", " 3966 clock-names = "xo", "alternate";
4445 interrupts = <GIC_SPI 3967 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
4446 <GIC_SPI 3968 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
4447 <GIC_SPI 3969 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
4448 interrupt-names = "dc 3970 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
4449 #freq-domain-cells = 3971 #freq-domain-cells = <1>;
4450 #clock-cells = <1>; 3972 #clock-cells = <1>;
4451 }; 3973 };
4452 3974
4453 gem_noc: interconnect@1910000 3975 gem_noc: interconnect@19100000 {
4454 compatible = "qcom,sm 3976 compatible = "qcom,sm8450-gem-noc";
4455 reg = <0 0x19100000 0 3977 reg = <0 0x19100000 0 0xbb800>;
4456 #interconnect-cells = 3978 #interconnect-cells = <2>;
4457 qcom,bcm-voters = <&a 3979 qcom,bcm-voters = <&apps_bcm_voter>;
4458 }; 3980 };
4459 3981
4460 system-cache-controller@19200 3982 system-cache-controller@19200000 {
4461 compatible = "qcom,sm 3983 compatible = "qcom,sm8450-llcc";
4462 reg = <0 0x19200000 0 !! 3984 reg = <0 0x19200000 0 0x580000>, <0 0x19a00000 0 0x80000>;
4463 <0 0x19300000 0 !! 3985 reg-names = "llcc_base", "llcc_broadcast_base";
4464 <0 0x19a00000 0 <<
4465 reg-names = "llcc0_ba <<
4466 "llcc3_ba <<
4467 "llcc_bro <<
4468 interrupts = <GIC_SPI 3986 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
4469 }; 3987 };
4470 3988
4471 ufs_mem_hc: ufshc@1d84000 { 3989 ufs_mem_hc: ufshc@1d84000 {
4472 compatible = "qcom,sm 3990 compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
4473 "jedec,u 3991 "jedec,ufs-2.0";
4474 reg = <0 0x01d84000 0 !! 3992 reg = <0 0x01d84000 0 0x3000>,
>> 3993 <0 0x01d88000 0 0x8000>;
>> 3994 reg-names = "std", "ice";
4475 interrupts = <GIC_SPI 3995 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
4476 phys = <&ufs_mem_phy> !! 3996 phys = <&ufs_mem_phy_lanes>;
4477 phy-names = "ufsphy"; 3997 phy-names = "ufsphy";
4478 lanes-per-direction = 3998 lanes-per-direction = <2>;
4479 #reset-cells = <1>; 3999 #reset-cells = <1>;
4480 resets = <&gcc GCC_UF 4000 resets = <&gcc GCC_UFS_PHY_BCR>;
4481 reset-names = "rst"; 4001 reset-names = "rst";
4482 4002
4483 power-domains = <&gcc 4003 power-domains = <&gcc UFS_PHY_GDSC>;
4484 4004
4485 iommus = <&apps_smmu 4005 iommus = <&apps_smmu 0xe0 0x0>;
4486 dma-coherent; 4006 dma-coherent;
4487 4007
4488 interconnects = <&agg 4008 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>,
4489 <&gem 4009 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
4490 interconnect-names = 4010 interconnect-names = "ufs-ddr", "cpu-ufs";
4491 clock-names = 4011 clock-names =
4492 "core_clk", 4012 "core_clk",
4493 "bus_aggr_clk 4013 "bus_aggr_clk",
4494 "iface_clk", 4014 "iface_clk",
4495 "core_clk_uni 4015 "core_clk_unipro",
4496 "ref_clk", 4016 "ref_clk",
4497 "tx_lane0_syn 4017 "tx_lane0_sync_clk",
4498 "rx_lane0_syn 4018 "rx_lane0_sync_clk",
4499 "rx_lane1_syn !! 4019 "rx_lane1_sync_clk",
>> 4020 "ice_core_clk";
4500 clocks = 4021 clocks =
4501 <&gcc GCC_UFS 4022 <&gcc GCC_UFS_PHY_AXI_CLK>,
4502 <&gcc GCC_AGG 4023 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
4503 <&gcc GCC_UFS 4024 <&gcc GCC_UFS_PHY_AHB_CLK>,
4504 <&gcc GCC_UFS 4025 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
4505 <&rpmhcc RPMH 4026 <&rpmhcc RPMH_CXO_CLK>,
4506 <&gcc GCC_UFS 4027 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
4507 <&gcc GCC_UFS 4028 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
4508 <&gcc GCC_UFS !! 4029 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
>> 4030 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
4509 freq-table-hz = 4031 freq-table-hz =
4510 <75000000 300 4032 <75000000 300000000>,
4511 <0 0>, 4033 <0 0>,
4512 <0 0>, 4034 <0 0>,
4513 <75000000 300 4035 <75000000 300000000>,
4514 <75000000 300 4036 <75000000 300000000>,
4515 <0 0>, 4037 <0 0>,
4516 <0 0>, 4038 <0 0>,
4517 <0 0>; !! 4039 <0 0>,
4518 qcom,ice = <&ice>; !! 4040 <75000000 300000000>;
4519 <<
4520 status = "disabled"; 4041 status = "disabled";
4521 }; 4042 };
4522 4043
4523 ufs_mem_phy: phy@1d87000 { 4044 ufs_mem_phy: phy@1d87000 {
4524 compatible = "qcom,sm 4045 compatible = "qcom,sm8450-qmp-ufs-phy";
4525 reg = <0 0x01d87000 0 !! 4046 reg = <0 0x01d87000 0 0x1c4>;
4526 !! 4047 #address-cells = <2>;
>> 4048 #size-cells = <2>;
>> 4049 ranges;
4527 clock-names = "ref", 4050 clock-names = "ref", "ref_aux", "qref";
4528 clocks = <&rpmhcc RPM 4051 clocks = <&rpmhcc RPMH_CXO_CLK>,
4529 <&gcc GCC_UF 4052 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
4530 <&gcc GCC_UF 4053 <&gcc GCC_UFS_0_CLKREF_EN>;
4531 4054
4532 power-domains = <&gcc <<
4533 <<
4534 resets = <&ufs_mem_hc 4055 resets = <&ufs_mem_hc 0>;
4535 reset-names = "ufsphy 4056 reset-names = "ufsphy";
4536 <<
4537 #clock-cells = <1>; <<
4538 #phy-cells = <0>; <<
4539 <<
4540 status = "disabled"; 4057 status = "disabled";
4541 }; <<
4542 4058
4543 ice: crypto@1d88000 { !! 4059 ufs_mem_phy_lanes: phy@1d87400 {
4544 compatible = "qcom,sm !! 4060 reg = <0 0x01d87400 0 0x188>,
4545 "qcom,in !! 4061 <0 0x01d87600 0 0x200>,
4546 reg = <0 0x01d88000 0 !! 4062 <0 0x01d87c00 0 0x200>,
4547 clocks = <&gcc GCC_UF !! 4063 <0 0x01d87800 0 0x188>,
4548 }; !! 4064 <0 0x01d87a00 0 0x200>;
4549 !! 4065 #clock-cells = <1>;
4550 cryptobam: dma-controller@1dc !! 4066 #phy-cells = <0>;
4551 compatible = "qcom,ba !! 4067 };
4552 reg = <0 0x01dc4000 0 <<
4553 interrupts = <GIC_SPI <<
4554 #dma-cells = <1>; <<
4555 qcom,ee = <0>; <<
4556 qcom,controlled-remot <<
4557 iommus = <&apps_smmu <<
4558 <&apps_smmu <<
4559 <&apps_smmu <<
4560 <&apps_smmu <<
4561 <&apps_smmu <<
4562 }; <<
4563 <<
4564 crypto: crypto@1dfa000 { <<
4565 compatible = "qcom,sm <<
4566 reg = <0 0x01dfa000 0 <<
4567 dmas = <&cryptobam 4> <<
4568 dma-names = "rx", "tx <<
4569 iommus = <&apps_smmu <<
4570 <&apps_smmu <<
4571 <&apps_smmu <<
4572 <&apps_smmu <<
4573 <&apps_smmu <<
4574 interconnects = <&agg <<
4575 interconnect-names = <<
4576 }; 4068 };
4577 4069
4578 sdhc_2: mmc@8804000 { 4070 sdhc_2: mmc@8804000 {
4579 compatible = "qcom,sm 4071 compatible = "qcom,sm8450-sdhci", "qcom,sdhci-msm-v5";
4580 reg = <0 0x08804000 0 4072 reg = <0 0x08804000 0 0x1000>;
4581 4073
4582 interrupts = <GIC_SPI 4074 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
4583 <GIC_SPI 4075 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
4584 interrupt-names = "hc 4076 interrupt-names = "hc_irq", "pwr_irq";
4585 4077
4586 clocks = <&gcc GCC_SD 4078 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
4587 <&gcc GCC_SD 4079 <&gcc GCC_SDCC2_APPS_CLK>,
4588 <&rpmhcc RPM 4080 <&rpmhcc RPMH_CXO_CLK>;
4589 clock-names = "iface" 4081 clock-names = "iface", "core", "xo";
4590 resets = <&gcc GCC_SD 4082 resets = <&gcc GCC_SDCC2_BCR>;
4591 interconnects = <&agg 4083 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
4592 <&gem 4084 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
4593 interconnect-names = 4085 interconnect-names = "sdhc-ddr","cpu-sdhc";
4594 iommus = <&apps_smmu 4086 iommus = <&apps_smmu 0x4a0 0x0>;
4595 power-domains = <&rpm !! 4087 power-domains = <&rpmhpd SM8450_CX>;
4596 operating-points-v2 = 4088 operating-points-v2 = <&sdhc2_opp_table>;
4597 bus-width = <4>; 4089 bus-width = <4>;
4598 dma-coherent; 4090 dma-coherent;
4599 4091
4600 /* Forbid SDR104/SDR5 4092 /* Forbid SDR104/SDR50 - broken hw! */
4601 sdhci-caps-mask = <0x 4093 sdhci-caps-mask = <0x3 0x0>;
4602 4094
4603 status = "disabled"; 4095 status = "disabled";
4604 4096
4605 sdhc2_opp_table: opp- 4097 sdhc2_opp_table: opp-table {
4606 compatible = 4098 compatible = "operating-points-v2";
4607 4099
4608 opp-100000000 4100 opp-100000000 {
4609 opp-h 4101 opp-hz = /bits/ 64 <100000000>;
4610 requi 4102 required-opps = <&rpmhpd_opp_low_svs>;
4611 }; 4103 };
4612 4104
4613 opp-202000000 4105 opp-202000000 {
4614 opp-h 4106 opp-hz = /bits/ 64 <202000000>;
4615 requi 4107 required-opps = <&rpmhpd_opp_svs_l1>;
4616 }; 4108 };
4617 }; 4109 };
4618 }; 4110 };
4619 4111
4620 usb_1: usb@a6f8800 { 4112 usb_1: usb@a6f8800 {
4621 compatible = "qcom,sm 4113 compatible = "qcom,sm8450-dwc3", "qcom,dwc3";
4622 reg = <0 0x0a6f8800 0 4114 reg = <0 0x0a6f8800 0 0x400>;
4623 status = "disabled"; 4115 status = "disabled";
4624 #address-cells = <2>; 4116 #address-cells = <2>;
4625 #size-cells = <2>; 4117 #size-cells = <2>;
4626 ranges; 4118 ranges;
4627 4119
4628 clocks = <&gcc GCC_CF 4120 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
4629 <&gcc GCC_US 4121 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
4630 <&gcc GCC_AG 4122 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
4631 <&gcc GCC_US 4123 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
4632 <&gcc GCC_US 4124 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4633 <&gcc GCC_US 4125 <&gcc GCC_USB3_0_CLKREF_EN>;
4634 clock-names = "cfg_no 4126 clock-names = "cfg_noc",
4635 "core", 4127 "core",
4636 "iface" 4128 "iface",
4637 "sleep" 4129 "sleep",
4638 "mock_u 4130 "mock_utmi",
4639 "xo"; 4131 "xo";
4640 4132
4641 assigned-clocks = <&g 4133 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4642 <&g 4134 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
4643 assigned-clock-rates 4135 assigned-clock-rates = <19200000>, <200000000>;
4644 4136
4645 interrupts-extended = 4137 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
4646 !! 4138 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
4647 <<
4648 4139 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
4649 !! 4140 <&pdc 14 IRQ_TYPE_EDGE_BOTH>;
4650 interrupt-names = "pw !! 4141 interrupt-names = "hs_phy_irq",
4651 "hs !! 4142 "ss_phy_irq",
4652 "dp <<
4653 "dm 4143 "dm_hs_phy_irq",
4654 "ss !! 4144 "dp_hs_phy_irq";
4655 4145
4656 power-domains = <&gcc 4146 power-domains = <&gcc USB30_PRIM_GDSC>;
4657 4147
4658 resets = <&gcc GCC_US 4148 resets = <&gcc GCC_USB30_PRIM_BCR>;
4659 4149
4660 interconnects = <&agg <<
4661 <&gem <<
4662 interconnect-names = <<
4663 <<
4664 usb_1_dwc3: usb@a6000 4150 usb_1_dwc3: usb@a600000 {
4665 compatible = 4151 compatible = "snps,dwc3";
4666 reg = <0 0x0a 4152 reg = <0 0x0a600000 0 0xcd00>;
4667 interrupts = 4153 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
4668 iommus = <&ap 4154 iommus = <&apps_smmu 0x0 0x0>;
4669 snps,dis_u2_s 4155 snps,dis_u2_susphy_quirk;
4670 snps,dis_enbl 4156 snps,dis_enblslpm_quirk;
4671 phys = <&usb_ !! 4157 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
4672 phy-names = " 4158 phy-names = "usb2-phy", "usb3-phy";
4673 <<
4674 ports { <<
4675 #addr <<
4676 #size <<
4677 <<
4678 port@ <<
4679 <<
4680 <<
4681 <<
4682 <<
4683 }; <<
4684 <<
4685 port@ <<
4686 <<
4687 <<
4688 <<
4689 <<
4690 <<
4691 }; <<
4692 }; <<
4693 }; 4159 };
4694 }; 4160 };
4695 4161
4696 nsp_noc: interconnect@320c000 4162 nsp_noc: interconnect@320c0000 {
4697 compatible = "qcom,sm 4163 compatible = "qcom,sm8450-nsp-noc";
4698 reg = <0 0x320c0000 0 4164 reg = <0 0x320c0000 0 0x10000>;
4699 #interconnect-cells = 4165 #interconnect-cells = <2>;
4700 qcom,bcm-voters = <&a 4166 qcom,bcm-voters = <&apps_bcm_voter>;
4701 }; 4167 };
4702 4168
4703 lpass_ag_noc: interconnect@3c 4169 lpass_ag_noc: interconnect@3c40000 {
4704 compatible = "qcom,sm 4170 compatible = "qcom,sm8450-lpass-ag-noc";
4705 reg = <0 0x03c40000 0 4171 reg = <0 0x03c40000 0 0x17200>;
4706 #interconnect-cells = 4172 #interconnect-cells = <2>;
4707 qcom,bcm-voters = <&a 4173 qcom,bcm-voters = <&apps_bcm_voter>;
4708 }; 4174 };
4709 }; 4175 };
4710 4176
4711 sound: sound { 4177 sound: sound {
4712 }; 4178 };
4713 4179
4714 thermal-zones { 4180 thermal-zones {
4715 aoss0-thermal { 4181 aoss0-thermal {
>> 4182 polling-delay-passive = <0>;
>> 4183 polling-delay = <0>;
4716 thermal-sensors = <&t 4184 thermal-sensors = <&tsens0 0>;
4717 4185
4718 trips { 4186 trips {
4719 thermal-engin 4187 thermal-engine-config {
4720 tempe 4188 temperature = <125000>;
4721 hyste 4189 hysteresis = <1000>;
4722 type 4190 type = "passive";
4723 }; 4191 };
4724 4192
4725 reset-mon-cfg 4193 reset-mon-cfg {
4726 tempe 4194 temperature = <115000>;
4727 hyste 4195 hysteresis = <5000>;
4728 type 4196 type = "passive";
4729 }; 4197 };
4730 }; 4198 };
4731 }; 4199 };
4732 4200
4733 cpuss0-thermal { 4201 cpuss0-thermal {
>> 4202 polling-delay-passive = <0>;
>> 4203 polling-delay = <0>;
4734 thermal-sensors = <&t 4204 thermal-sensors = <&tsens0 1>;
4735 4205
4736 trips { 4206 trips {
4737 thermal-engin 4207 thermal-engine-config {
4738 tempe 4208 temperature = <125000>;
4739 hyste 4209 hysteresis = <1000>;
4740 type 4210 type = "passive";
4741 }; 4211 };
4742 4212
4743 reset-mon-cfg 4213 reset-mon-cfg {
4744 tempe 4214 temperature = <115000>;
4745 hyste 4215 hysteresis = <5000>;
4746 type 4216 type = "passive";
4747 }; 4217 };
4748 }; 4218 };
4749 }; 4219 };
4750 4220
4751 cpuss1-thermal { 4221 cpuss1-thermal {
>> 4222 polling-delay-passive = <0>;
>> 4223 polling-delay = <0>;
4752 thermal-sensors = <&t 4224 thermal-sensors = <&tsens0 2>;
4753 4225
4754 trips { 4226 trips {
4755 thermal-engin 4227 thermal-engine-config {
4756 tempe 4228 temperature = <125000>;
4757 hyste 4229 hysteresis = <1000>;
4758 type 4230 type = "passive";
4759 }; 4231 };
4760 4232
4761 reset-mon-cfg 4233 reset-mon-cfg {
4762 tempe 4234 temperature = <115000>;
4763 hyste 4235 hysteresis = <5000>;
4764 type 4236 type = "passive";
4765 }; 4237 };
4766 }; 4238 };
4767 }; 4239 };
4768 4240
4769 cpuss3-thermal { 4241 cpuss3-thermal {
>> 4242 polling-delay-passive = <0>;
>> 4243 polling-delay = <0>;
4770 thermal-sensors = <&t 4244 thermal-sensors = <&tsens0 3>;
4771 4245
4772 trips { 4246 trips {
4773 thermal-engin 4247 thermal-engine-config {
4774 tempe 4248 temperature = <125000>;
4775 hyste 4249 hysteresis = <1000>;
4776 type 4250 type = "passive";
4777 }; 4251 };
4778 4252
4779 reset-mon-cfg 4253 reset-mon-cfg {
4780 tempe 4254 temperature = <115000>;
4781 hyste 4255 hysteresis = <5000>;
4782 type 4256 type = "passive";
4783 }; 4257 };
4784 }; 4258 };
4785 }; 4259 };
4786 4260
4787 cpuss4-thermal { 4261 cpuss4-thermal {
>> 4262 polling-delay-passive = <0>;
>> 4263 polling-delay = <0>;
4788 thermal-sensors = <&t 4264 thermal-sensors = <&tsens0 4>;
4789 4265
4790 trips { 4266 trips {
4791 thermal-engin 4267 thermal-engine-config {
4792 tempe 4268 temperature = <125000>;
4793 hyste 4269 hysteresis = <1000>;
4794 type 4270 type = "passive";
4795 }; 4271 };
4796 4272
4797 reset-mon-cfg 4273 reset-mon-cfg {
4798 tempe 4274 temperature = <115000>;
4799 hyste 4275 hysteresis = <5000>;
4800 type 4276 type = "passive";
4801 }; 4277 };
4802 }; 4278 };
4803 }; 4279 };
4804 4280
4805 cpu4-top-thermal { 4281 cpu4-top-thermal {
>> 4282 polling-delay-passive = <0>;
>> 4283 polling-delay = <0>;
4806 thermal-sensors = <&t 4284 thermal-sensors = <&tsens0 5>;
4807 4285
4808 trips { 4286 trips {
4809 cpu4_top_aler 4287 cpu4_top_alert0: trip-point0 {
4810 tempe 4288 temperature = <90000>;
4811 hyste 4289 hysteresis = <2000>;
4812 type 4290 type = "passive";
4813 }; 4291 };
4814 4292
4815 cpu4_top_aler 4293 cpu4_top_alert1: trip-point1 {
4816 tempe 4294 temperature = <95000>;
4817 hyste 4295 hysteresis = <2000>;
4818 type 4296 type = "passive";
4819 }; 4297 };
4820 4298
4821 cpu4_top_crit 4299 cpu4_top_crit: cpu-crit {
4822 tempe 4300 temperature = <110000>;
4823 hyste 4301 hysteresis = <1000>;
4824 type 4302 type = "critical";
4825 }; 4303 };
4826 }; 4304 };
4827 }; 4305 };
4828 4306
4829 cpu4-bottom-thermal { 4307 cpu4-bottom-thermal {
>> 4308 polling-delay-passive = <0>;
>> 4309 polling-delay = <0>;
4830 thermal-sensors = <&t 4310 thermal-sensors = <&tsens0 6>;
4831 4311
4832 trips { 4312 trips {
4833 cpu4_bottom_a 4313 cpu4_bottom_alert0: trip-point0 {
4834 tempe 4314 temperature = <90000>;
4835 hyste 4315 hysteresis = <2000>;
4836 type 4316 type = "passive";
4837 }; 4317 };
4838 4318
4839 cpu4_bottom_a 4319 cpu4_bottom_alert1: trip-point1 {
4840 tempe 4320 temperature = <95000>;
4841 hyste 4321 hysteresis = <2000>;
4842 type 4322 type = "passive";
4843 }; 4323 };
4844 4324
4845 cpu4_bottom_c 4325 cpu4_bottom_crit: cpu-crit {
4846 tempe 4326 temperature = <110000>;
4847 hyste 4327 hysteresis = <1000>;
4848 type 4328 type = "critical";
4849 }; 4329 };
4850 }; 4330 };
4851 }; 4331 };
4852 4332
4853 cpu5-top-thermal { 4333 cpu5-top-thermal {
>> 4334 polling-delay-passive = <0>;
>> 4335 polling-delay = <0>;
4854 thermal-sensors = <&t 4336 thermal-sensors = <&tsens0 7>;
4855 4337
4856 trips { 4338 trips {
4857 cpu5_top_aler 4339 cpu5_top_alert0: trip-point0 {
4858 tempe 4340 temperature = <90000>;
4859 hyste 4341 hysteresis = <2000>;
4860 type 4342 type = "passive";
4861 }; 4343 };
4862 4344
4863 cpu5_top_aler 4345 cpu5_top_alert1: trip-point1 {
4864 tempe 4346 temperature = <95000>;
4865 hyste 4347 hysteresis = <2000>;
4866 type 4348 type = "passive";
4867 }; 4349 };
4868 4350
4869 cpu5_top_crit 4351 cpu5_top_crit: cpu-crit {
4870 tempe 4352 temperature = <110000>;
4871 hyste 4353 hysteresis = <1000>;
4872 type 4354 type = "critical";
4873 }; 4355 };
4874 }; 4356 };
4875 }; 4357 };
4876 4358
4877 cpu5-bottom-thermal { 4359 cpu5-bottom-thermal {
>> 4360 polling-delay-passive = <0>;
>> 4361 polling-delay = <0>;
4878 thermal-sensors = <&t 4362 thermal-sensors = <&tsens0 8>;
4879 4363
4880 trips { 4364 trips {
4881 cpu5_bottom_a 4365 cpu5_bottom_alert0: trip-point0 {
4882 tempe 4366 temperature = <90000>;
4883 hyste 4367 hysteresis = <2000>;
4884 type 4368 type = "passive";
4885 }; 4369 };
4886 4370
4887 cpu5_bottom_a 4371 cpu5_bottom_alert1: trip-point1 {
4888 tempe 4372 temperature = <95000>;
4889 hyste 4373 hysteresis = <2000>;
4890 type 4374 type = "passive";
4891 }; 4375 };
4892 4376
4893 cpu5_bottom_c 4377 cpu5_bottom_crit: cpu-crit {
4894 tempe 4378 temperature = <110000>;
4895 hyste 4379 hysteresis = <1000>;
4896 type 4380 type = "critical";
4897 }; 4381 };
4898 }; 4382 };
4899 }; 4383 };
4900 4384
4901 cpu6-top-thermal { 4385 cpu6-top-thermal {
>> 4386 polling-delay-passive = <0>;
>> 4387 polling-delay = <0>;
4902 thermal-sensors = <&t 4388 thermal-sensors = <&tsens0 9>;
4903 4389
4904 trips { 4390 trips {
4905 cpu6_top_aler 4391 cpu6_top_alert0: trip-point0 {
4906 tempe 4392 temperature = <90000>;
4907 hyste 4393 hysteresis = <2000>;
4908 type 4394 type = "passive";
4909 }; 4395 };
4910 4396
4911 cpu6_top_aler 4397 cpu6_top_alert1: trip-point1 {
4912 tempe 4398 temperature = <95000>;
4913 hyste 4399 hysteresis = <2000>;
4914 type 4400 type = "passive";
4915 }; 4401 };
4916 4402
4917 cpu6_top_crit 4403 cpu6_top_crit: cpu-crit {
4918 tempe 4404 temperature = <110000>;
4919 hyste 4405 hysteresis = <1000>;
4920 type 4406 type = "critical";
4921 }; 4407 };
4922 }; 4408 };
4923 }; 4409 };
4924 4410
4925 cpu6-bottom-thermal { 4411 cpu6-bottom-thermal {
>> 4412 polling-delay-passive = <0>;
>> 4413 polling-delay = <0>;
4926 thermal-sensors = <&t 4414 thermal-sensors = <&tsens0 10>;
4927 4415
4928 trips { 4416 trips {
4929 cpu6_bottom_a 4417 cpu6_bottom_alert0: trip-point0 {
4930 tempe 4418 temperature = <90000>;
4931 hyste 4419 hysteresis = <2000>;
4932 type 4420 type = "passive";
4933 }; 4421 };
4934 4422
4935 cpu6_bottom_a 4423 cpu6_bottom_alert1: trip-point1 {
4936 tempe 4424 temperature = <95000>;
4937 hyste 4425 hysteresis = <2000>;
4938 type 4426 type = "passive";
4939 }; 4427 };
4940 4428
4941 cpu6_bottom_c 4429 cpu6_bottom_crit: cpu-crit {
4942 tempe 4430 temperature = <110000>;
4943 hyste 4431 hysteresis = <1000>;
4944 type 4432 type = "critical";
4945 }; 4433 };
4946 }; 4434 };
4947 }; 4435 };
4948 4436
4949 cpu7-top-thermal { 4437 cpu7-top-thermal {
>> 4438 polling-delay-passive = <0>;
>> 4439 polling-delay = <0>;
4950 thermal-sensors = <&t 4440 thermal-sensors = <&tsens0 11>;
4951 4441
4952 trips { 4442 trips {
4953 cpu7_top_aler 4443 cpu7_top_alert0: trip-point0 {
4954 tempe 4444 temperature = <90000>;
4955 hyste 4445 hysteresis = <2000>;
4956 type 4446 type = "passive";
4957 }; 4447 };
4958 4448
4959 cpu7_top_aler 4449 cpu7_top_alert1: trip-point1 {
4960 tempe 4450 temperature = <95000>;
4961 hyste 4451 hysteresis = <2000>;
4962 type 4452 type = "passive";
4963 }; 4453 };
4964 4454
4965 cpu7_top_crit 4455 cpu7_top_crit: cpu-crit {
4966 tempe 4456 temperature = <110000>;
4967 hyste 4457 hysteresis = <1000>;
4968 type 4458 type = "critical";
4969 }; 4459 };
4970 }; 4460 };
4971 }; 4461 };
4972 4462
4973 cpu7-middle-thermal { 4463 cpu7-middle-thermal {
>> 4464 polling-delay-passive = <0>;
>> 4465 polling-delay = <0>;
4974 thermal-sensors = <&t 4466 thermal-sensors = <&tsens0 12>;
4975 4467
4976 trips { 4468 trips {
4977 cpu7_middle_a 4469 cpu7_middle_alert0: trip-point0 {
4978 tempe 4470 temperature = <90000>;
4979 hyste 4471 hysteresis = <2000>;
4980 type 4472 type = "passive";
4981 }; 4473 };
4982 4474
4983 cpu7_middle_a 4475 cpu7_middle_alert1: trip-point1 {
4984 tempe 4476 temperature = <95000>;
4985 hyste 4477 hysteresis = <2000>;
4986 type 4478 type = "passive";
4987 }; 4479 };
4988 4480
4989 cpu7_middle_c 4481 cpu7_middle_crit: cpu-crit {
4990 tempe 4482 temperature = <110000>;
4991 hyste 4483 hysteresis = <1000>;
4992 type 4484 type = "critical";
4993 }; 4485 };
4994 }; 4486 };
4995 }; 4487 };
4996 4488
4997 cpu7-bottom-thermal { 4489 cpu7-bottom-thermal {
>> 4490 polling-delay-passive = <0>;
>> 4491 polling-delay = <0>;
4998 thermal-sensors = <&t 4492 thermal-sensors = <&tsens0 13>;
4999 4493
5000 trips { 4494 trips {
5001 cpu7_bottom_a 4495 cpu7_bottom_alert0: trip-point0 {
5002 tempe 4496 temperature = <90000>;
5003 hyste 4497 hysteresis = <2000>;
5004 type 4498 type = "passive";
5005 }; 4499 };
5006 4500
5007 cpu7_bottom_a 4501 cpu7_bottom_alert1: trip-point1 {
5008 tempe 4502 temperature = <95000>;
5009 hyste 4503 hysteresis = <2000>;
5010 type 4504 type = "passive";
5011 }; 4505 };
5012 4506
5013 cpu7_bottom_c 4507 cpu7_bottom_crit: cpu-crit {
5014 tempe 4508 temperature = <110000>;
5015 hyste 4509 hysteresis = <1000>;
5016 type 4510 type = "critical";
5017 }; 4511 };
5018 }; 4512 };
5019 }; 4513 };
5020 4514
5021 gpu-top-thermal { 4515 gpu-top-thermal {
5022 polling-delay-passive 4516 polling-delay-passive = <10>;
5023 !! 4517 polling-delay = <0>;
5024 thermal-sensors = <&t 4518 thermal-sensors = <&tsens0 14>;
5025 4519
5026 cooling-maps { <<
5027 map0 { <<
5028 trip <<
5029 cooli <<
5030 }; <<
5031 }; <<
5032 <<
5033 trips { 4520 trips {
5034 gpu_top_alert !! 4521 thermal-engine-config {
5035 tempe !! 4522 temperature = <125000>;
5036 hyste 4523 hysteresis = <1000>;
5037 type 4524 type = "passive";
5038 }; 4525 };
5039 4526
5040 trip-point1 { !! 4527 thermal-hal-config {
5041 tempe !! 4528 temperature = <125000>;
5042 hyste 4529 hysteresis = <1000>;
5043 type !! 4530 type = "passive";
5044 }; 4531 };
5045 4532
5046 trip-point2 { !! 4533 reset-mon-cfg {
5047 tempe !! 4534 temperature = <115000>;
5048 hyste !! 4535 hysteresis = <5000>;
5049 type !! 4536 type = "passive";
>> 4537 };
>> 4538
>> 4539 gpu0_tj_cfg: tj-cfg {
>> 4540 temperature = <95000>;
>> 4541 hysteresis = <5000>;
>> 4542 type = "passive";
5050 }; 4543 };
5051 }; 4544 };
5052 }; 4545 };
5053 4546
5054 gpu-bottom-thermal { 4547 gpu-bottom-thermal {
5055 polling-delay-passive 4548 polling-delay-passive = <10>;
5056 !! 4549 polling-delay = <0>;
5057 thermal-sensors = <&t 4550 thermal-sensors = <&tsens0 15>;
5058 4551
5059 cooling-maps { <<
5060 map0 { <<
5061 trip <<
5062 cooli <<
5063 }; <<
5064 }; <<
5065 <<
5066 trips { 4552 trips {
5067 gpu_bottom_al !! 4553 thermal-engine-config {
5068 tempe !! 4554 temperature = <125000>;
5069 hyste 4555 hysteresis = <1000>;
5070 type 4556 type = "passive";
5071 }; 4557 };
5072 4558
5073 trip-point1 { !! 4559 thermal-hal-config {
5074 tempe !! 4560 temperature = <125000>;
5075 hyste 4561 hysteresis = <1000>;
5076 type !! 4562 type = "passive";
5077 }; 4563 };
5078 4564
5079 trip-point2 { !! 4565 reset-mon-cfg {
5080 tempe !! 4566 temperature = <115000>;
5081 hyste !! 4567 hysteresis = <5000>;
5082 type !! 4568 type = "passive";
>> 4569 };
>> 4570
>> 4571 gpu1_tj_cfg: tj-cfg {
>> 4572 temperature = <95000>;
>> 4573 hysteresis = <5000>;
>> 4574 type = "passive";
5083 }; 4575 };
5084 }; 4576 };
5085 }; 4577 };
5086 4578
5087 aoss1-thermal { 4579 aoss1-thermal {
>> 4580 polling-delay-passive = <0>;
>> 4581 polling-delay = <0>;
5088 thermal-sensors = <&t 4582 thermal-sensors = <&tsens1 0>;
5089 4583
5090 trips { 4584 trips {
5091 thermal-engin 4585 thermal-engine-config {
5092 tempe 4586 temperature = <125000>;
5093 hyste 4587 hysteresis = <1000>;
5094 type 4588 type = "passive";
5095 }; 4589 };
5096 4590
5097 reset-mon-cfg 4591 reset-mon-cfg {
5098 tempe 4592 temperature = <115000>;
5099 hyste 4593 hysteresis = <5000>;
5100 type 4594 type = "passive";
5101 }; 4595 };
5102 }; 4596 };
5103 }; 4597 };
5104 4598
5105 cpu0-thermal { 4599 cpu0-thermal {
>> 4600 polling-delay-passive = <0>;
>> 4601 polling-delay = <0>;
5106 thermal-sensors = <&t 4602 thermal-sensors = <&tsens1 1>;
5107 4603
5108 trips { 4604 trips {
5109 cpu0_alert0: 4605 cpu0_alert0: trip-point0 {
5110 tempe 4606 temperature = <90000>;
5111 hyste 4607 hysteresis = <2000>;
5112 type 4608 type = "passive";
5113 }; 4609 };
5114 4610
5115 cpu0_alert1: 4611 cpu0_alert1: trip-point1 {
5116 tempe 4612 temperature = <95000>;
5117 hyste 4613 hysteresis = <2000>;
5118 type 4614 type = "passive";
5119 }; 4615 };
5120 4616
5121 cpu0_crit: cp 4617 cpu0_crit: cpu-crit {
5122 tempe 4618 temperature = <110000>;
5123 hyste 4619 hysteresis = <1000>;
5124 type 4620 type = "critical";
5125 }; 4621 };
5126 }; 4622 };
5127 }; 4623 };
5128 4624
5129 cpu1-thermal { 4625 cpu1-thermal {
>> 4626 polling-delay-passive = <0>;
>> 4627 polling-delay = <0>;
5130 thermal-sensors = <&t 4628 thermal-sensors = <&tsens1 2>;
5131 4629
5132 trips { 4630 trips {
5133 cpu1_alert0: 4631 cpu1_alert0: trip-point0 {
5134 tempe 4632 temperature = <90000>;
5135 hyste 4633 hysteresis = <2000>;
5136 type 4634 type = "passive";
5137 }; 4635 };
5138 4636
5139 cpu1_alert1: 4637 cpu1_alert1: trip-point1 {
5140 tempe 4638 temperature = <95000>;
5141 hyste 4639 hysteresis = <2000>;
5142 type 4640 type = "passive";
5143 }; 4641 };
5144 4642
5145 cpu1_crit: cp 4643 cpu1_crit: cpu-crit {
5146 tempe 4644 temperature = <110000>;
5147 hyste 4645 hysteresis = <1000>;
5148 type 4646 type = "critical";
5149 }; 4647 };
5150 }; 4648 };
5151 }; 4649 };
5152 4650
5153 cpu2-thermal { 4651 cpu2-thermal {
>> 4652 polling-delay-passive = <0>;
>> 4653 polling-delay = <0>;
5154 thermal-sensors = <&t 4654 thermal-sensors = <&tsens1 3>;
5155 4655
5156 trips { 4656 trips {
5157 cpu2_alert0: 4657 cpu2_alert0: trip-point0 {
5158 tempe 4658 temperature = <90000>;
5159 hyste 4659 hysteresis = <2000>;
5160 type 4660 type = "passive";
5161 }; 4661 };
5162 4662
5163 cpu2_alert1: 4663 cpu2_alert1: trip-point1 {
5164 tempe 4664 temperature = <95000>;
5165 hyste 4665 hysteresis = <2000>;
5166 type 4666 type = "passive";
5167 }; 4667 };
5168 4668
5169 cpu2_crit: cp 4669 cpu2_crit: cpu-crit {
5170 tempe 4670 temperature = <110000>;
5171 hyste 4671 hysteresis = <1000>;
5172 type 4672 type = "critical";
5173 }; 4673 };
5174 }; 4674 };
5175 }; 4675 };
5176 4676
5177 cpu3-thermal { 4677 cpu3-thermal {
>> 4678 polling-delay-passive = <0>;
>> 4679 polling-delay = <0>;
5178 thermal-sensors = <&t 4680 thermal-sensors = <&tsens1 4>;
5179 4681
5180 trips { 4682 trips {
5181 cpu3_alert0: 4683 cpu3_alert0: trip-point0 {
5182 tempe 4684 temperature = <90000>;
5183 hyste 4685 hysteresis = <2000>;
5184 type 4686 type = "passive";
5185 }; 4687 };
5186 4688
5187 cpu3_alert1: 4689 cpu3_alert1: trip-point1 {
5188 tempe 4690 temperature = <95000>;
5189 hyste 4691 hysteresis = <2000>;
5190 type 4692 type = "passive";
5191 }; 4693 };
5192 4694
5193 cpu3_crit: cp 4695 cpu3_crit: cpu-crit {
5194 tempe 4696 temperature = <110000>;
5195 hyste 4697 hysteresis = <1000>;
5196 type 4698 type = "critical";
5197 }; 4699 };
5198 }; 4700 };
5199 }; 4701 };
5200 4702
5201 cdsp0-thermal { 4703 cdsp0-thermal {
5202 polling-delay-passive 4704 polling-delay-passive = <10>;
5203 !! 4705 polling-delay = <0>;
5204 thermal-sensors = <&t 4706 thermal-sensors = <&tsens1 5>;
5205 4707
5206 trips { 4708 trips {
5207 thermal-engin 4709 thermal-engine-config {
5208 tempe 4710 temperature = <125000>;
5209 hyste 4711 hysteresis = <1000>;
5210 type 4712 type = "passive";
5211 }; 4713 };
5212 4714
5213 thermal-hal-c 4715 thermal-hal-config {
5214 tempe 4716 temperature = <125000>;
5215 hyste 4717 hysteresis = <1000>;
5216 type 4718 type = "passive";
5217 }; 4719 };
5218 4720
5219 reset-mon-cfg 4721 reset-mon-cfg {
5220 tempe 4722 temperature = <115000>;
5221 hyste 4723 hysteresis = <5000>;
5222 type 4724 type = "passive";
5223 }; 4725 };
5224 4726
5225 cdsp_0_config 4727 cdsp_0_config: junction-config {
5226 tempe 4728 temperature = <95000>;
5227 hyste 4729 hysteresis = <5000>;
5228 type 4730 type = "passive";
5229 }; 4731 };
5230 }; 4732 };
5231 }; 4733 };
5232 4734
5233 cdsp1-thermal { 4735 cdsp1-thermal {
5234 polling-delay-passive 4736 polling-delay-passive = <10>;
5235 !! 4737 polling-delay = <0>;
5236 thermal-sensors = <&t 4738 thermal-sensors = <&tsens1 6>;
5237 4739
5238 trips { 4740 trips {
5239 thermal-engin 4741 thermal-engine-config {
5240 tempe 4742 temperature = <125000>;
5241 hyste 4743 hysteresis = <1000>;
5242 type 4744 type = "passive";
5243 }; 4745 };
5244 4746
5245 thermal-hal-c 4747 thermal-hal-config {
5246 tempe 4748 temperature = <125000>;
5247 hyste 4749 hysteresis = <1000>;
5248 type 4750 type = "passive";
5249 }; 4751 };
5250 4752
5251 reset-mon-cfg 4753 reset-mon-cfg {
5252 tempe 4754 temperature = <115000>;
5253 hyste 4755 hysteresis = <5000>;
5254 type 4756 type = "passive";
5255 }; 4757 };
5256 4758
5257 cdsp_1_config 4759 cdsp_1_config: junction-config {
5258 tempe 4760 temperature = <95000>;
5259 hyste 4761 hysteresis = <5000>;
5260 type 4762 type = "passive";
5261 }; 4763 };
5262 }; 4764 };
5263 }; 4765 };
5264 4766
5265 cdsp2-thermal { 4767 cdsp2-thermal {
5266 polling-delay-passive 4768 polling-delay-passive = <10>;
5267 !! 4769 polling-delay = <0>;
5268 thermal-sensors = <&t 4770 thermal-sensors = <&tsens1 7>;
5269 4771
5270 trips { 4772 trips {
5271 thermal-engin 4773 thermal-engine-config {
5272 tempe 4774 temperature = <125000>;
5273 hyste 4775 hysteresis = <1000>;
5274 type 4776 type = "passive";
5275 }; 4777 };
5276 4778
5277 thermal-hal-c 4779 thermal-hal-config {
5278 tempe 4780 temperature = <125000>;
5279 hyste 4781 hysteresis = <1000>;
5280 type 4782 type = "passive";
5281 }; 4783 };
5282 4784
5283 reset-mon-cfg 4785 reset-mon-cfg {
5284 tempe 4786 temperature = <115000>;
5285 hyste 4787 hysteresis = <5000>;
5286 type 4788 type = "passive";
5287 }; 4789 };
5288 4790
5289 cdsp_2_config 4791 cdsp_2_config: junction-config {
5290 tempe 4792 temperature = <95000>;
5291 hyste 4793 hysteresis = <5000>;
5292 type 4794 type = "passive";
5293 }; 4795 };
5294 }; 4796 };
5295 }; 4797 };
5296 4798
5297 video-thermal { 4799 video-thermal {
>> 4800 polling-delay-passive = <0>;
>> 4801 polling-delay = <0>;
5298 thermal-sensors = <&t 4802 thermal-sensors = <&tsens1 8>;
5299 4803
5300 trips { 4804 trips {
5301 thermal-engin 4805 thermal-engine-config {
5302 tempe 4806 temperature = <125000>;
5303 hyste 4807 hysteresis = <1000>;
5304 type 4808 type = "passive";
5305 }; 4809 };
5306 4810
5307 reset-mon-cfg 4811 reset-mon-cfg {
5308 tempe 4812 temperature = <115000>;
5309 hyste 4813 hysteresis = <5000>;
5310 type 4814 type = "passive";
5311 }; 4815 };
5312 }; 4816 };
5313 }; 4817 };
5314 4818
5315 mem-thermal { 4819 mem-thermal {
5316 polling-delay-passive 4820 polling-delay-passive = <10>;
5317 !! 4821 polling-delay = <0>;
5318 thermal-sensors = <&t 4822 thermal-sensors = <&tsens1 9>;
5319 4823
5320 trips { 4824 trips {
5321 thermal-engin 4825 thermal-engine-config {
5322 tempe 4826 temperature = <125000>;
5323 hyste 4827 hysteresis = <1000>;
5324 type 4828 type = "passive";
5325 }; 4829 };
5326 4830
5327 ddr_config0: 4831 ddr_config0: ddr0-config {
5328 tempe 4832 temperature = <90000>;
5329 hyste 4833 hysteresis = <5000>;
5330 type 4834 type = "passive";
5331 }; 4835 };
5332 4836
5333 reset-mon-cfg 4837 reset-mon-cfg {
5334 tempe 4838 temperature = <115000>;
5335 hyste 4839 hysteresis = <5000>;
5336 type 4840 type = "passive";
5337 }; 4841 };
5338 }; 4842 };
5339 }; 4843 };
5340 4844
5341 modem0-thermal { 4845 modem0-thermal {
>> 4846 polling-delay-passive = <0>;
>> 4847 polling-delay = <0>;
5342 thermal-sensors = <&t 4848 thermal-sensors = <&tsens1 10>;
5343 4849
5344 trips { 4850 trips {
5345 thermal-engin 4851 thermal-engine-config {
5346 tempe 4852 temperature = <125000>;
5347 hyste 4853 hysteresis = <1000>;
5348 type 4854 type = "passive";
5349 }; 4855 };
5350 4856
5351 mdmss0_config 4857 mdmss0_config0: mdmss0-config0 {
5352 tempe 4858 temperature = <102000>;
5353 hyste 4859 hysteresis = <3000>;
5354 type 4860 type = "passive";
5355 }; 4861 };
5356 4862
5357 mdmss0_config 4863 mdmss0_config1: mdmss0-config1 {
5358 tempe 4864 temperature = <105000>;
5359 hyste 4865 hysteresis = <3000>;
5360 type 4866 type = "passive";
5361 }; 4867 };
5362 4868
5363 reset-mon-cfg 4869 reset-mon-cfg {
5364 tempe 4870 temperature = <115000>;
5365 hyste 4871 hysteresis = <5000>;
5366 type 4872 type = "passive";
5367 }; 4873 };
5368 }; 4874 };
5369 }; 4875 };
5370 4876
5371 modem1-thermal { 4877 modem1-thermal {
>> 4878 polling-delay-passive = <0>;
>> 4879 polling-delay = <0>;
5372 thermal-sensors = <&t 4880 thermal-sensors = <&tsens1 11>;
5373 4881
5374 trips { 4882 trips {
5375 thermal-engin 4883 thermal-engine-config {
5376 tempe 4884 temperature = <125000>;
5377 hyste 4885 hysteresis = <1000>;
5378 type 4886 type = "passive";
5379 }; 4887 };
5380 4888
5381 mdmss1_config 4889 mdmss1_config0: mdmss1-config0 {
5382 tempe 4890 temperature = <102000>;
5383 hyste 4891 hysteresis = <3000>;
5384 type 4892 type = "passive";
5385 }; 4893 };
5386 4894
5387 mdmss1_config 4895 mdmss1_config1: mdmss1-config1 {
5388 tempe 4896 temperature = <105000>;
5389 hyste 4897 hysteresis = <3000>;
5390 type 4898 type = "passive";
5391 }; 4899 };
5392 4900
5393 reset-mon-cfg 4901 reset-mon-cfg {
5394 tempe 4902 temperature = <115000>;
5395 hyste 4903 hysteresis = <5000>;
5396 type 4904 type = "passive";
5397 }; 4905 };
5398 }; 4906 };
5399 }; 4907 };
5400 4908
5401 modem2-thermal { 4909 modem2-thermal {
>> 4910 polling-delay-passive = <0>;
>> 4911 polling-delay = <0>;
5402 thermal-sensors = <&t 4912 thermal-sensors = <&tsens1 12>;
5403 4913
5404 trips { 4914 trips {
5405 thermal-engin 4915 thermal-engine-config {
5406 tempe 4916 temperature = <125000>;
5407 hyste 4917 hysteresis = <1000>;
5408 type 4918 type = "passive";
5409 }; 4919 };
5410 4920
5411 mdmss2_config 4921 mdmss2_config0: mdmss2-config0 {
5412 tempe 4922 temperature = <102000>;
5413 hyste 4923 hysteresis = <3000>;
5414 type 4924 type = "passive";
5415 }; 4925 };
5416 4926
5417 mdmss2_config 4927 mdmss2_config1: mdmss2-config1 {
5418 tempe 4928 temperature = <105000>;
5419 hyste 4929 hysteresis = <3000>;
5420 type 4930 type = "passive";
5421 }; 4931 };
5422 4932
5423 reset-mon-cfg 4933 reset-mon-cfg {
5424 tempe 4934 temperature = <115000>;
5425 hyste 4935 hysteresis = <5000>;
5426 type 4936 type = "passive";
5427 }; 4937 };
5428 }; 4938 };
5429 }; 4939 };
5430 4940
5431 modem3-thermal { 4941 modem3-thermal {
>> 4942 polling-delay-passive = <0>;
>> 4943 polling-delay = <0>;
5432 thermal-sensors = <&t 4944 thermal-sensors = <&tsens1 13>;
5433 4945
5434 trips { 4946 trips {
5435 thermal-engin 4947 thermal-engine-config {
5436 tempe 4948 temperature = <125000>;
5437 hyste 4949 hysteresis = <1000>;
5438 type 4950 type = "passive";
5439 }; 4951 };
5440 4952
5441 mdmss3_config 4953 mdmss3_config0: mdmss3-config0 {
5442 tempe 4954 temperature = <102000>;
5443 hyste 4955 hysteresis = <3000>;
5444 type 4956 type = "passive";
5445 }; 4957 };
5446 4958
5447 mdmss3_config 4959 mdmss3_config1: mdmss3-config1 {
5448 tempe 4960 temperature = <105000>;
5449 hyste 4961 hysteresis = <3000>;
5450 type 4962 type = "passive";
5451 }; 4963 };
5452 4964
5453 reset-mon-cfg 4965 reset-mon-cfg {
5454 tempe 4966 temperature = <115000>;
5455 hyste 4967 hysteresis = <5000>;
5456 type 4968 type = "passive";
5457 }; 4969 };
5458 }; 4970 };
5459 }; 4971 };
5460 4972
5461 camera0-thermal { 4973 camera0-thermal {
>> 4974 polling-delay-passive = <0>;
>> 4975 polling-delay = <0>;
5462 thermal-sensors = <&t 4976 thermal-sensors = <&tsens1 14>;
5463 4977
5464 trips { 4978 trips {
5465 thermal-engin 4979 thermal-engine-config {
5466 tempe 4980 temperature = <125000>;
5467 hyste 4981 hysteresis = <1000>;
5468 type 4982 type = "passive";
5469 }; 4983 };
5470 4984
5471 reset-mon-cfg 4985 reset-mon-cfg {
5472 tempe 4986 temperature = <115000>;
5473 hyste 4987 hysteresis = <5000>;
5474 type 4988 type = "passive";
5475 }; 4989 };
5476 }; 4990 };
5477 }; 4991 };
5478 4992
5479 camera1-thermal { 4993 camera1-thermal {
>> 4994 polling-delay-passive = <0>;
>> 4995 polling-delay = <0>;
5480 thermal-sensors = <&t 4996 thermal-sensors = <&tsens1 15>;
5481 4997
5482 trips { 4998 trips {
5483 thermal-engin 4999 thermal-engine-config {
5484 tempe 5000 temperature = <125000>;
5485 hyste 5001 hysteresis = <1000>;
5486 type 5002 type = "passive";
5487 }; 5003 };
5488 5004
5489 reset-mon-cfg 5005 reset-mon-cfg {
5490 tempe 5006 temperature = <115000>;
5491 hyste 5007 hysteresis = <5000>;
5492 type 5008 type = "passive";
5493 }; 5009 };
5494 }; 5010 };
5495 }; 5011 };
5496 }; 5012 };
5497 5013
5498 timer { 5014 timer {
5499 compatible = "arm,armv8-timer 5015 compatible = "arm,armv8-timer";
5500 interrupts = <GIC_PPI 13 (GIC 5016 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5501 <GIC_PPI 14 (GIC 5017 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5502 <GIC_PPI 11 (GIC 5018 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5503 <GIC_PPI 10 (GIC 5019 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
5504 clock-frequency = <19200000>; 5020 clock-frequency = <19200000>;
5505 }; 5021 };
5506 }; 5022 };
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