1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * Copyright (c) 2021, Linaro Limited 3 * Copyright (c) 2021, Linaro Limited
4 */ 4 */
5 5
6 #include <dt-bindings/interrupt-controller/arm 6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-sm8450.h> 7 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
8 #include <dt-bindings/clock/qcom,rpmh.h> 8 #include <dt-bindings/clock/qcom,rpmh.h>
9 #include <dt-bindings/clock/qcom,sm8450-camcc. 9 #include <dt-bindings/clock/qcom,sm8450-camcc.h>
10 #include <dt-bindings/clock/qcom,sm8450-dispcc 10 #include <dt-bindings/clock/qcom,sm8450-dispcc.h>
11 #include <dt-bindings/clock/qcom,sm8450-gpucc. <<
12 #include <dt-bindings/clock/qcom,sm8450-videoc <<
13 #include <dt-bindings/dma/qcom-gpi.h> 11 #include <dt-bindings/dma/qcom-gpi.h>
14 #include <dt-bindings/firmware/qcom,scm.h> <<
15 #include <dt-bindings/gpio/gpio.h> 12 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/mailbox/qcom-ipcc.h> 13 #include <dt-bindings/mailbox/qcom-ipcc.h>
17 #include <dt-bindings/phy/phy-qcom-qmp.h> 14 #include <dt-bindings/phy/phy-qcom-qmp.h>
18 #include <dt-bindings/power/qcom,rpmhpd.h> <<
19 #include <dt-bindings/power/qcom-rpmpd.h> 15 #include <dt-bindings/power/qcom-rpmpd.h>
20 #include <dt-bindings/interconnect/qcom,icc.h> <<
21 #include <dt-bindings/interconnect/qcom,sm8450 16 #include <dt-bindings/interconnect/qcom,sm8450.h>
22 #include <dt-bindings/reset/qcom,sm8450-gpucc. <<
23 #include <dt-bindings/soc/qcom,gpr.h> 17 #include <dt-bindings/soc/qcom,gpr.h>
24 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 18 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
25 #include <dt-bindings/sound/qcom,q6dsp-lpass-p 19 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
26 #include <dt-bindings/thermal/thermal.h> 20 #include <dt-bindings/thermal/thermal.h>
27 21
28 / { 22 / {
29 interrupt-parent = <&intc>; 23 interrupt-parent = <&intc>;
30 24
31 #address-cells = <2>; 25 #address-cells = <2>;
32 #size-cells = <2>; 26 #size-cells = <2>;
33 27
34 chosen { }; 28 chosen { };
35 29
36 clocks { 30 clocks {
37 xo_board: xo-board { 31 xo_board: xo-board {
38 compatible = "fixed-cl 32 compatible = "fixed-clock";
39 #clock-cells = <0>; 33 #clock-cells = <0>;
40 clock-frequency = <768 34 clock-frequency = <76800000>;
41 }; 35 };
42 36
43 sleep_clk: sleep-clk { 37 sleep_clk: sleep-clk {
44 compatible = "fixed-cl 38 compatible = "fixed-clock";
45 #clock-cells = <0>; 39 #clock-cells = <0>;
46 clock-frequency = <320 40 clock-frequency = <32000>;
47 }; 41 };
48 }; 42 };
49 43
50 cpus { 44 cpus {
51 #address-cells = <2>; 45 #address-cells = <2>;
52 #size-cells = <0>; 46 #size-cells = <0>;
53 47
54 CPU0: cpu@0 { 48 CPU0: cpu@0 {
55 device_type = "cpu"; 49 device_type = "cpu";
56 compatible = "qcom,kry 50 compatible = "qcom,kryo780";
57 reg = <0x0 0x0>; 51 reg = <0x0 0x0>;
58 enable-method = "psci" 52 enable-method = "psci";
59 next-level-cache = <&L 53 next-level-cache = <&L2_0>;
60 power-domains = <&CPU_ 54 power-domains = <&CPU_PD0>;
61 power-domain-names = " 55 power-domain-names = "psci";
62 qcom,freq-domain = <&c 56 qcom,freq-domain = <&cpufreq_hw 0>;
63 #cooling-cells = <2>; 57 #cooling-cells = <2>;
64 clocks = <&cpufreq_hw 58 clocks = <&cpufreq_hw 0>;
65 L2_0: l2-cache { 59 L2_0: l2-cache {
66 compatible = " 60 compatible = "cache";
67 cache-level = 61 cache-level = <2>;
68 cache-unified; 62 cache-unified;
69 next-level-cac 63 next-level-cache = <&L3_0>;
70 L3_0: l3-cache 64 L3_0: l3-cache {
71 compat 65 compatible = "cache";
72 cache- 66 cache-level = <3>;
73 cache- 67 cache-unified;
74 }; 68 };
75 }; 69 };
76 }; 70 };
77 71
78 CPU1: cpu@100 { 72 CPU1: cpu@100 {
79 device_type = "cpu"; 73 device_type = "cpu";
80 compatible = "qcom,kry 74 compatible = "qcom,kryo780";
81 reg = <0x0 0x100>; 75 reg = <0x0 0x100>;
82 enable-method = "psci" 76 enable-method = "psci";
83 next-level-cache = <&L 77 next-level-cache = <&L2_100>;
84 power-domains = <&CPU_ 78 power-domains = <&CPU_PD1>;
85 power-domain-names = " 79 power-domain-names = "psci";
86 qcom,freq-domain = <&c 80 qcom,freq-domain = <&cpufreq_hw 0>;
87 #cooling-cells = <2>; 81 #cooling-cells = <2>;
88 clocks = <&cpufreq_hw 82 clocks = <&cpufreq_hw 0>;
89 L2_100: l2-cache { 83 L2_100: l2-cache {
90 compatible = " 84 compatible = "cache";
91 cache-level = 85 cache-level = <2>;
92 cache-unified; 86 cache-unified;
93 next-level-cac 87 next-level-cache = <&L3_0>;
94 }; 88 };
95 }; 89 };
96 90
97 CPU2: cpu@200 { 91 CPU2: cpu@200 {
98 device_type = "cpu"; 92 device_type = "cpu";
99 compatible = "qcom,kry 93 compatible = "qcom,kryo780";
100 reg = <0x0 0x200>; 94 reg = <0x0 0x200>;
101 enable-method = "psci" 95 enable-method = "psci";
102 next-level-cache = <&L 96 next-level-cache = <&L2_200>;
103 power-domains = <&CPU_ 97 power-domains = <&CPU_PD2>;
104 power-domain-names = " 98 power-domain-names = "psci";
105 qcom,freq-domain = <&c 99 qcom,freq-domain = <&cpufreq_hw 0>;
106 #cooling-cells = <2>; 100 #cooling-cells = <2>;
107 clocks = <&cpufreq_hw 101 clocks = <&cpufreq_hw 0>;
108 L2_200: l2-cache { 102 L2_200: l2-cache {
109 compatible = " 103 compatible = "cache";
110 cache-level = 104 cache-level = <2>;
111 cache-unified; 105 cache-unified;
112 next-level-cac 106 next-level-cache = <&L3_0>;
113 }; 107 };
114 }; 108 };
115 109
116 CPU3: cpu@300 { 110 CPU3: cpu@300 {
117 device_type = "cpu"; 111 device_type = "cpu";
118 compatible = "qcom,kry 112 compatible = "qcom,kryo780";
119 reg = <0x0 0x300>; 113 reg = <0x0 0x300>;
120 enable-method = "psci" 114 enable-method = "psci";
121 next-level-cache = <&L 115 next-level-cache = <&L2_300>;
122 power-domains = <&CPU_ 116 power-domains = <&CPU_PD3>;
123 power-domain-names = " 117 power-domain-names = "psci";
124 qcom,freq-domain = <&c 118 qcom,freq-domain = <&cpufreq_hw 0>;
125 #cooling-cells = <2>; 119 #cooling-cells = <2>;
126 clocks = <&cpufreq_hw 120 clocks = <&cpufreq_hw 0>;
127 L2_300: l2-cache { 121 L2_300: l2-cache {
128 compatible = " 122 compatible = "cache";
129 cache-level = 123 cache-level = <2>;
130 cache-unified; 124 cache-unified;
131 next-level-cac 125 next-level-cache = <&L3_0>;
132 }; 126 };
133 }; 127 };
134 128
135 CPU4: cpu@400 { 129 CPU4: cpu@400 {
136 device_type = "cpu"; 130 device_type = "cpu";
137 compatible = "qcom,kry 131 compatible = "qcom,kryo780";
138 reg = <0x0 0x400>; 132 reg = <0x0 0x400>;
139 enable-method = "psci" 133 enable-method = "psci";
140 next-level-cache = <&L 134 next-level-cache = <&L2_400>;
141 power-domains = <&CPU_ 135 power-domains = <&CPU_PD4>;
142 power-domain-names = " 136 power-domain-names = "psci";
143 qcom,freq-domain = <&c 137 qcom,freq-domain = <&cpufreq_hw 1>;
144 #cooling-cells = <2>; 138 #cooling-cells = <2>;
145 clocks = <&cpufreq_hw 139 clocks = <&cpufreq_hw 1>;
146 L2_400: l2-cache { 140 L2_400: l2-cache {
147 compatible = " 141 compatible = "cache";
148 cache-level = 142 cache-level = <2>;
149 cache-unified; 143 cache-unified;
150 next-level-cac 144 next-level-cache = <&L3_0>;
151 }; 145 };
152 }; 146 };
153 147
154 CPU5: cpu@500 { 148 CPU5: cpu@500 {
155 device_type = "cpu"; 149 device_type = "cpu";
156 compatible = "qcom,kry 150 compatible = "qcom,kryo780";
157 reg = <0x0 0x500>; 151 reg = <0x0 0x500>;
158 enable-method = "psci" 152 enable-method = "psci";
159 next-level-cache = <&L 153 next-level-cache = <&L2_500>;
160 power-domains = <&CPU_ 154 power-domains = <&CPU_PD5>;
161 power-domain-names = " 155 power-domain-names = "psci";
162 qcom,freq-domain = <&c 156 qcom,freq-domain = <&cpufreq_hw 1>;
163 #cooling-cells = <2>; 157 #cooling-cells = <2>;
164 clocks = <&cpufreq_hw 158 clocks = <&cpufreq_hw 1>;
165 L2_500: l2-cache { 159 L2_500: l2-cache {
166 compatible = " 160 compatible = "cache";
167 cache-level = 161 cache-level = <2>;
168 cache-unified; 162 cache-unified;
169 next-level-cac 163 next-level-cache = <&L3_0>;
170 }; 164 };
171 }; 165 };
172 166
173 CPU6: cpu@600 { 167 CPU6: cpu@600 {
174 device_type = "cpu"; 168 device_type = "cpu";
175 compatible = "qcom,kry 169 compatible = "qcom,kryo780";
176 reg = <0x0 0x600>; 170 reg = <0x0 0x600>;
177 enable-method = "psci" 171 enable-method = "psci";
178 next-level-cache = <&L 172 next-level-cache = <&L2_600>;
179 power-domains = <&CPU_ 173 power-domains = <&CPU_PD6>;
180 power-domain-names = " 174 power-domain-names = "psci";
181 qcom,freq-domain = <&c 175 qcom,freq-domain = <&cpufreq_hw 1>;
182 #cooling-cells = <2>; 176 #cooling-cells = <2>;
183 clocks = <&cpufreq_hw 177 clocks = <&cpufreq_hw 1>;
184 L2_600: l2-cache { 178 L2_600: l2-cache {
185 compatible = " 179 compatible = "cache";
186 cache-level = 180 cache-level = <2>;
187 cache-unified; 181 cache-unified;
188 next-level-cac 182 next-level-cache = <&L3_0>;
189 }; 183 };
190 }; 184 };
191 185
192 CPU7: cpu@700 { 186 CPU7: cpu@700 {
193 device_type = "cpu"; 187 device_type = "cpu";
194 compatible = "qcom,kry 188 compatible = "qcom,kryo780";
195 reg = <0x0 0x700>; 189 reg = <0x0 0x700>;
196 enable-method = "psci" 190 enable-method = "psci";
197 next-level-cache = <&L 191 next-level-cache = <&L2_700>;
198 power-domains = <&CPU_ 192 power-domains = <&CPU_PD7>;
199 power-domain-names = " 193 power-domain-names = "psci";
200 qcom,freq-domain = <&c 194 qcom,freq-domain = <&cpufreq_hw 2>;
201 #cooling-cells = <2>; 195 #cooling-cells = <2>;
202 clocks = <&cpufreq_hw 196 clocks = <&cpufreq_hw 2>;
203 L2_700: l2-cache { 197 L2_700: l2-cache {
204 compatible = " 198 compatible = "cache";
205 cache-level = 199 cache-level = <2>;
206 cache-unified; 200 cache-unified;
207 next-level-cac 201 next-level-cache = <&L3_0>;
208 }; 202 };
209 }; 203 };
210 204
211 cpu-map { 205 cpu-map {
212 cluster0 { 206 cluster0 {
213 core0 { 207 core0 {
214 cpu = 208 cpu = <&CPU0>;
215 }; 209 };
216 210
217 core1 { 211 core1 {
218 cpu = 212 cpu = <&CPU1>;
219 }; 213 };
220 214
221 core2 { 215 core2 {
222 cpu = 216 cpu = <&CPU2>;
223 }; 217 };
224 218
225 core3 { 219 core3 {
226 cpu = 220 cpu = <&CPU3>;
227 }; 221 };
228 222
229 core4 { 223 core4 {
230 cpu = 224 cpu = <&CPU4>;
231 }; 225 };
232 226
233 core5 { 227 core5 {
234 cpu = 228 cpu = <&CPU5>;
235 }; 229 };
236 230
237 core6 { 231 core6 {
238 cpu = 232 cpu = <&CPU6>;
239 }; 233 };
240 234
241 core7 { 235 core7 {
242 cpu = 236 cpu = <&CPU7>;
243 }; 237 };
244 }; 238 };
245 }; 239 };
246 240
247 idle-states { 241 idle-states {
248 entry-method = "psci"; 242 entry-method = "psci";
249 243
250 LITTLE_CPU_SLEEP_0: cp 244 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
251 compatible = " 245 compatible = "arm,idle-state";
252 idle-state-nam 246 idle-state-name = "silver-rail-power-collapse";
253 arm,psci-suspe 247 arm,psci-suspend-param = <0x40000004>;
254 entry-latency- 248 entry-latency-us = <800>;
255 exit-latency-u 249 exit-latency-us = <750>;
256 min-residency- 250 min-residency-us = <4090>;
257 local-timer-st 251 local-timer-stop;
258 }; 252 };
259 253
260 BIG_CPU_SLEEP_0: cpu-s 254 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
261 compatible = " 255 compatible = "arm,idle-state";
262 idle-state-nam 256 idle-state-name = "gold-rail-power-collapse";
263 arm,psci-suspe 257 arm,psci-suspend-param = <0x40000004>;
264 entry-latency- 258 entry-latency-us = <600>;
265 exit-latency-u 259 exit-latency-us = <1550>;
266 min-residency- 260 min-residency-us = <4791>;
267 local-timer-st 261 local-timer-stop;
268 }; 262 };
269 }; 263 };
270 264
271 domain-idle-states { 265 domain-idle-states {
272 CLUSTER_SLEEP_0: clust 266 CLUSTER_SLEEP_0: cluster-sleep-0 {
273 compatible = " 267 compatible = "domain-idle-state";
274 arm,psci-suspe 268 arm,psci-suspend-param = <0x41000044>;
275 entry-latency- 269 entry-latency-us = <1050>;
276 exit-latency-u 270 exit-latency-us = <2500>;
277 min-residency- 271 min-residency-us = <5309>;
278 }; 272 };
279 273
280 CLUSTER_SLEEP_1: clust 274 CLUSTER_SLEEP_1: cluster-sleep-1 {
281 compatible = " 275 compatible = "domain-idle-state";
282 arm,psci-suspe 276 arm,psci-suspend-param = <0x4100c344>;
283 entry-latency- 277 entry-latency-us = <2700>;
284 exit-latency-u 278 exit-latency-us = <3500>;
285 min-residency- 279 min-residency-us = <13959>;
286 }; 280 };
287 }; 281 };
288 }; 282 };
289 283
290 firmware { 284 firmware {
291 scm: scm { 285 scm: scm {
292 compatible = "qcom,scm 286 compatible = "qcom,scm-sm8450", "qcom,scm";
293 qcom,dload-mode = <&tc 287 qcom,dload-mode = <&tcsr 0x13000>;
294 interconnects = <&aggr 288 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
295 #reset-cells = <1>; 289 #reset-cells = <1>;
296 }; 290 };
297 }; 291 };
298 292
299 clk_virt: interconnect-0 { 293 clk_virt: interconnect-0 {
300 compatible = "qcom,sm8450-clk- 294 compatible = "qcom,sm8450-clk-virt";
301 #interconnect-cells = <2>; 295 #interconnect-cells = <2>;
302 qcom,bcm-voters = <&apps_bcm_v 296 qcom,bcm-voters = <&apps_bcm_voter>;
303 }; 297 };
304 298
305 mc_virt: interconnect-1 { 299 mc_virt: interconnect-1 {
306 compatible = "qcom,sm8450-mc-v 300 compatible = "qcom,sm8450-mc-virt";
307 #interconnect-cells = <2>; 301 #interconnect-cells = <2>;
308 qcom,bcm-voters = <&apps_bcm_v 302 qcom,bcm-voters = <&apps_bcm_voter>;
309 }; 303 };
310 304
311 memory@a0000000 { 305 memory@a0000000 {
312 device_type = "memory"; 306 device_type = "memory";
313 /* We expect the bootloader to 307 /* We expect the bootloader to fill in the size */
314 reg = <0x0 0xa0000000 0x0 0x0> 308 reg = <0x0 0xa0000000 0x0 0x0>;
315 }; 309 };
316 310
317 pmu { 311 pmu {
318 compatible = "arm,armv8-pmuv3" 312 compatible = "arm,armv8-pmuv3";
319 interrupts = <GIC_PPI 7 IRQ_TY 313 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
320 }; 314 };
321 315
322 psci { 316 psci {
323 compatible = "arm,psci-1.0"; 317 compatible = "arm,psci-1.0";
324 method = "smc"; 318 method = "smc";
325 319
326 CPU_PD0: power-domain-cpu0 { 320 CPU_PD0: power-domain-cpu0 {
327 #power-domain-cells = 321 #power-domain-cells = <0>;
328 power-domains = <&CLUS 322 power-domains = <&CLUSTER_PD>;
329 domain-idle-states = < 323 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
330 }; 324 };
331 325
332 CPU_PD1: power-domain-cpu1 { 326 CPU_PD1: power-domain-cpu1 {
333 #power-domain-cells = 327 #power-domain-cells = <0>;
334 power-domains = <&CLUS 328 power-domains = <&CLUSTER_PD>;
335 domain-idle-states = < 329 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
336 }; 330 };
337 331
338 CPU_PD2: power-domain-cpu2 { 332 CPU_PD2: power-domain-cpu2 {
339 #power-domain-cells = 333 #power-domain-cells = <0>;
340 power-domains = <&CLUS 334 power-domains = <&CLUSTER_PD>;
341 domain-idle-states = < 335 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
342 }; 336 };
343 337
344 CPU_PD3: power-domain-cpu3 { 338 CPU_PD3: power-domain-cpu3 {
345 #power-domain-cells = 339 #power-domain-cells = <0>;
346 power-domains = <&CLUS 340 power-domains = <&CLUSTER_PD>;
347 domain-idle-states = < 341 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
348 }; 342 };
349 343
350 CPU_PD4: power-domain-cpu4 { 344 CPU_PD4: power-domain-cpu4 {
351 #power-domain-cells = 345 #power-domain-cells = <0>;
352 power-domains = <&CLUS 346 power-domains = <&CLUSTER_PD>;
353 domain-idle-states = < 347 domain-idle-states = <&BIG_CPU_SLEEP_0>;
354 }; 348 };
355 349
356 CPU_PD5: power-domain-cpu5 { 350 CPU_PD5: power-domain-cpu5 {
357 #power-domain-cells = 351 #power-domain-cells = <0>;
358 power-domains = <&CLUS 352 power-domains = <&CLUSTER_PD>;
359 domain-idle-states = < 353 domain-idle-states = <&BIG_CPU_SLEEP_0>;
360 }; 354 };
361 355
362 CPU_PD6: power-domain-cpu6 { 356 CPU_PD6: power-domain-cpu6 {
363 #power-domain-cells = 357 #power-domain-cells = <0>;
364 power-domains = <&CLUS 358 power-domains = <&CLUSTER_PD>;
365 domain-idle-states = < 359 domain-idle-states = <&BIG_CPU_SLEEP_0>;
366 }; 360 };
367 361
368 CPU_PD7: power-domain-cpu7 { 362 CPU_PD7: power-domain-cpu7 {
369 #power-domain-cells = 363 #power-domain-cells = <0>;
370 power-domains = <&CLUS 364 power-domains = <&CLUSTER_PD>;
371 domain-idle-states = < 365 domain-idle-states = <&BIG_CPU_SLEEP_0>;
372 }; 366 };
373 367
374 CLUSTER_PD: power-domain-cpu-c 368 CLUSTER_PD: power-domain-cpu-cluster0 {
375 #power-domain-cells = 369 #power-domain-cells = <0>;
376 domain-idle-states = < 370 domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>;
377 }; 371 };
378 }; 372 };
379 373
380 qup_opp_table_100mhz: opp-table-qup { 374 qup_opp_table_100mhz: opp-table-qup {
381 compatible = "operating-points 375 compatible = "operating-points-v2";
382 376
383 opp-50000000 { 377 opp-50000000 {
384 opp-hz = /bits/ 64 <50 378 opp-hz = /bits/ 64 <50000000>;
385 required-opps = <&rpmh 379 required-opps = <&rpmhpd_opp_min_svs>;
386 }; 380 };
387 381
388 opp-75000000 { 382 opp-75000000 {
389 opp-hz = /bits/ 64 <75 383 opp-hz = /bits/ 64 <75000000>;
390 required-opps = <&rpmh 384 required-opps = <&rpmhpd_opp_low_svs>;
391 }; 385 };
392 386
393 opp-100000000 { 387 opp-100000000 {
394 opp-hz = /bits/ 64 <10 388 opp-hz = /bits/ 64 <100000000>;
395 required-opps = <&rpmh 389 required-opps = <&rpmhpd_opp_svs>;
396 }; 390 };
397 }; 391 };
398 392
399 reserved_memory: reserved-memory { 393 reserved_memory: reserved-memory {
400 #address-cells = <2>; 394 #address-cells = <2>;
401 #size-cells = <2>; 395 #size-cells = <2>;
402 ranges; 396 ranges;
403 397
404 hyp_mem: memory@80000000 { 398 hyp_mem: memory@80000000 {
405 reg = <0x0 0x80000000 399 reg = <0x0 0x80000000 0x0 0x600000>;
406 no-map; 400 no-map;
407 }; 401 };
408 402
409 xbl_dt_log_mem: memory@8060000 403 xbl_dt_log_mem: memory@80600000 {
410 reg = <0x0 0x80600000 404 reg = <0x0 0x80600000 0x0 0x40000>;
411 no-map; 405 no-map;
412 }; 406 };
413 407
414 xbl_ramdump_mem: memory@806400 408 xbl_ramdump_mem: memory@80640000 {
415 reg = <0x0 0x80640000 409 reg = <0x0 0x80640000 0x0 0x180000>;
416 no-map; 410 no-map;
417 }; 411 };
418 412
419 xbl_sc_mem: memory@807c0000 { 413 xbl_sc_mem: memory@807c0000 {
420 reg = <0x0 0x807c0000 414 reg = <0x0 0x807c0000 0x0 0x40000>;
421 no-map; 415 no-map;
422 }; 416 };
423 417
424 aop_image_mem: memory@80800000 418 aop_image_mem: memory@80800000 {
425 reg = <0x0 0x80800000 419 reg = <0x0 0x80800000 0x0 0x60000>;
426 no-map; 420 no-map;
427 }; 421 };
428 422
429 aop_cmd_db_mem: memory@8086000 423 aop_cmd_db_mem: memory@80860000 {
430 compatible = "qcom,cmd 424 compatible = "qcom,cmd-db";
431 reg = <0x0 0x80860000 425 reg = <0x0 0x80860000 0x0 0x20000>;
432 no-map; 426 no-map;
433 }; 427 };
434 428
435 aop_config_mem: memory@8088000 429 aop_config_mem: memory@80880000 {
436 reg = <0x0 0x80880000 430 reg = <0x0 0x80880000 0x0 0x20000>;
437 no-map; 431 no-map;
438 }; 432 };
439 433
440 tme_crash_dump_mem: memory@808 434 tme_crash_dump_mem: memory@808a0000 {
441 reg = <0x0 0x808a0000 435 reg = <0x0 0x808a0000 0x0 0x40000>;
442 no-map; 436 no-map;
443 }; 437 };
444 438
445 tme_log_mem: memory@808e0000 { 439 tme_log_mem: memory@808e0000 {
446 reg = <0x0 0x808e0000 440 reg = <0x0 0x808e0000 0x0 0x4000>;
447 no-map; 441 no-map;
448 }; 442 };
449 443
450 uefi_log_mem: memory@808e4000 444 uefi_log_mem: memory@808e4000 {
451 reg = <0x0 0x808e4000 445 reg = <0x0 0x808e4000 0x0 0x10000>;
452 no-map; 446 no-map;
453 }; 447 };
454 448
455 /* secdata region can be reuse 449 /* secdata region can be reused by apps */
456 smem: memory@80900000 { 450 smem: memory@80900000 {
457 compatible = "qcom,sme 451 compatible = "qcom,smem";
458 reg = <0x0 0x80900000 452 reg = <0x0 0x80900000 0x0 0x200000>;
459 hwlocks = <&tcsr_mutex 453 hwlocks = <&tcsr_mutex 3>;
460 no-map; 454 no-map;
461 }; 455 };
462 456
463 cpucp_fw_mem: memory@80b00000 457 cpucp_fw_mem: memory@80b00000 {
464 reg = <0x0 0x80b00000 458 reg = <0x0 0x80b00000 0x0 0x100000>;
465 no-map; 459 no-map;
466 }; 460 };
467 461
468 cdsp_secure_heap: memory@80c00 462 cdsp_secure_heap: memory@80c00000 {
469 reg = <0x0 0x80c00000 463 reg = <0x0 0x80c00000 0x0 0x4600000>;
470 no-map; 464 no-map;
471 }; 465 };
472 466
473 video_mem: memory@85700000 { 467 video_mem: memory@85700000 {
474 reg = <0x0 0x85700000 468 reg = <0x0 0x85700000 0x0 0x700000>;
475 no-map; 469 no-map;
476 }; 470 };
477 471
478 adsp_mem: memory@85e00000 { 472 adsp_mem: memory@85e00000 {
479 reg = <0x0 0x85e00000 473 reg = <0x0 0x85e00000 0x0 0x2100000>;
480 no-map; 474 no-map;
481 }; 475 };
482 476
483 slpi_mem: memory@88000000 { 477 slpi_mem: memory@88000000 {
484 reg = <0x0 0x88000000 478 reg = <0x0 0x88000000 0x0 0x1900000>;
485 no-map; 479 no-map;
486 }; 480 };
487 481
488 cdsp_mem: memory@89900000 { 482 cdsp_mem: memory@89900000 {
489 reg = <0x0 0x89900000 483 reg = <0x0 0x89900000 0x0 0x2000000>;
490 no-map; 484 no-map;
491 }; 485 };
492 486
493 ipa_fw_mem: memory@8b900000 { 487 ipa_fw_mem: memory@8b900000 {
494 reg = <0x0 0x8b900000 488 reg = <0x0 0x8b900000 0x0 0x10000>;
495 no-map; 489 no-map;
496 }; 490 };
497 491
498 ipa_gsi_mem: memory@8b910000 { 492 ipa_gsi_mem: memory@8b910000 {
499 reg = <0x0 0x8b910000 493 reg = <0x0 0x8b910000 0x0 0xa000>;
500 no-map; 494 no-map;
501 }; 495 };
502 496
503 gpu_micro_code_mem: memory@8b9 497 gpu_micro_code_mem: memory@8b91a000 {
504 reg = <0x0 0x8b91a000 498 reg = <0x0 0x8b91a000 0x0 0x2000>;
505 no-map; 499 no-map;
506 }; 500 };
507 501
508 spss_region_mem: memory@8ba000 502 spss_region_mem: memory@8ba00000 {
509 reg = <0x0 0x8ba00000 503 reg = <0x0 0x8ba00000 0x0 0x180000>;
510 no-map; 504 no-map;
511 }; 505 };
512 506
513 /* First part of the "SPU secu 507 /* First part of the "SPU secure shared memory" region */
514 spu_tz_shared_mem: memory@8bb8 508 spu_tz_shared_mem: memory@8bb80000 {
515 reg = <0x0 0x8bb80000 509 reg = <0x0 0x8bb80000 0x0 0x60000>;
516 no-map; 510 no-map;
517 }; 511 };
518 512
519 /* Second part of the "SPU sec 513 /* Second part of the "SPU secure shared memory" region */
520 spu_modem_shared_mem: memory@8 514 spu_modem_shared_mem: memory@8bbe0000 {
521 reg = <0x0 0x8bbe0000 515 reg = <0x0 0x8bbe0000 0x0 0x20000>;
522 no-map; 516 no-map;
523 }; 517 };
524 518
525 mpss_mem: memory@8bc00000 { 519 mpss_mem: memory@8bc00000 {
526 reg = <0x0 0x8bc00000 520 reg = <0x0 0x8bc00000 0x0 0x13200000>;
527 no-map; 521 no-map;
528 }; 522 };
529 523
530 cvp_mem: memory@9ee00000 { 524 cvp_mem: memory@9ee00000 {
531 reg = <0x0 0x9ee00000 525 reg = <0x0 0x9ee00000 0x0 0x700000>;
532 no-map; 526 no-map;
533 }; 527 };
534 528
535 camera_mem: memory@9f500000 { 529 camera_mem: memory@9f500000 {
536 reg = <0x0 0x9f500000 530 reg = <0x0 0x9f500000 0x0 0x800000>;
537 no-map; 531 no-map;
538 }; 532 };
539 533
540 rmtfs_mem: memory@9fd00000 { 534 rmtfs_mem: memory@9fd00000 {
541 compatible = "qcom,rmt 535 compatible = "qcom,rmtfs-mem";
542 reg = <0x0 0x9fd00000 536 reg = <0x0 0x9fd00000 0x0 0x280000>;
543 no-map; 537 no-map;
544 538
545 qcom,client-id = <1>; 539 qcom,client-id = <1>;
546 qcom,vmid = <QCOM_SCM_ !! 540 qcom,vmid = <15>;
547 }; 541 };
548 542
549 xbl_sc_mem2: memory@a6e00000 { 543 xbl_sc_mem2: memory@a6e00000 {
550 reg = <0x0 0xa6e00000 544 reg = <0x0 0xa6e00000 0x0 0x40000>;
551 no-map; 545 no-map;
552 }; 546 };
553 547
554 global_sync_mem: memory@a6f000 548 global_sync_mem: memory@a6f00000 {
555 reg = <0x0 0xa6f00000 549 reg = <0x0 0xa6f00000 0x0 0x100000>;
556 no-map; 550 no-map;
557 }; 551 };
558 552
559 /* uefi region can be reused b 553 /* uefi region can be reused by APPS */
560 554
561 /* Linux kernel image is loade 555 /* Linux kernel image is loaded at 0xa0000000 */
562 556
563 oem_vm_mem: memory@bb000000 { 557 oem_vm_mem: memory@bb000000 {
564 reg = <0x0 0xbb000000 558 reg = <0x0 0xbb000000 0x0 0x5000000>;
565 no-map; 559 no-map;
566 }; 560 };
567 561
568 mte_mem: memory@c0000000 { 562 mte_mem: memory@c0000000 {
569 reg = <0x0 0xc0000000 563 reg = <0x0 0xc0000000 0x0 0x20000000>;
570 no-map; 564 no-map;
571 }; 565 };
572 566
573 qheebsp_reserved_mem: memory@e 567 qheebsp_reserved_mem: memory@e0000000 {
574 reg = <0x0 0xe0000000 568 reg = <0x0 0xe0000000 0x0 0x600000>;
575 no-map; 569 no-map;
576 }; 570 };
577 571
578 cpusys_vm_mem: memory@e0600000 572 cpusys_vm_mem: memory@e0600000 {
579 reg = <0x0 0xe0600000 573 reg = <0x0 0xe0600000 0x0 0x400000>;
580 no-map; 574 no-map;
581 }; 575 };
582 576
583 hyp_reserved_mem: memory@e0a00 577 hyp_reserved_mem: memory@e0a00000 {
584 reg = <0x0 0xe0a00000 578 reg = <0x0 0xe0a00000 0x0 0x100000>;
585 no-map; 579 no-map;
586 }; 580 };
587 581
588 trust_ui_vm_mem: memory@e0b000 582 trust_ui_vm_mem: memory@e0b00000 {
589 reg = <0x0 0xe0b00000 583 reg = <0x0 0xe0b00000 0x0 0x4af3000>;
590 no-map; 584 no-map;
591 }; 585 };
592 586
593 trust_ui_vm_qrtr: memory@e55f3 587 trust_ui_vm_qrtr: memory@e55f3000 {
594 reg = <0x0 0xe55f3000 588 reg = <0x0 0xe55f3000 0x0 0x9000>;
595 no-map; 589 no-map;
596 }; 590 };
597 591
598 trust_ui_vm_vblk0_ring: memory 592 trust_ui_vm_vblk0_ring: memory@e55fc000 {
599 reg = <0x0 0xe55fc000 593 reg = <0x0 0xe55fc000 0x0 0x4000>;
600 no-map; 594 no-map;
601 }; 595 };
602 596
603 trust_ui_vm_swiotlb: memory@e5 597 trust_ui_vm_swiotlb: memory@e5600000 {
604 reg = <0x0 0xe5600000 598 reg = <0x0 0xe5600000 0x0 0x100000>;
605 no-map; 599 no-map;
606 }; 600 };
607 601
608 tz_stat_mem: memory@e8800000 { 602 tz_stat_mem: memory@e8800000 {
609 reg = <0x0 0xe8800000 603 reg = <0x0 0xe8800000 0x0 0x100000>;
610 no-map; 604 no-map;
611 }; 605 };
612 606
613 tags_mem: memory@e8900000 { 607 tags_mem: memory@e8900000 {
614 reg = <0x0 0xe8900000 608 reg = <0x0 0xe8900000 0x0 0x1200000>;
615 no-map; 609 no-map;
616 }; 610 };
617 611
618 qtee_mem: memory@e9b00000 { 612 qtee_mem: memory@e9b00000 {
619 reg = <0x0 0xe9b00000 613 reg = <0x0 0xe9b00000 0x0 0x500000>;
620 no-map; 614 no-map;
621 }; 615 };
622 616
623 trusted_apps_mem: memory@ea000 617 trusted_apps_mem: memory@ea000000 {
624 reg = <0x0 0xea000000 618 reg = <0x0 0xea000000 0x0 0x3900000>;
625 no-map; 619 no-map;
626 }; 620 };
627 621
628 trusted_apps_ext_mem: memory@e 622 trusted_apps_ext_mem: memory@ed900000 {
629 reg = <0x0 0xed900000 623 reg = <0x0 0xed900000 0x0 0x3b00000>;
630 no-map; 624 no-map;
631 }; 625 };
632 }; 626 };
633 627
634 smp2p-adsp { 628 smp2p-adsp {
635 compatible = "qcom,smp2p"; 629 compatible = "qcom,smp2p";
636 qcom,smem = <443>, <429>; 630 qcom,smem = <443>, <429>;
637 interrupts-extended = <&ipcc I 631 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
638 I 632 IPCC_MPROC_SIGNAL_SMP2P
639 I 633 IRQ_TYPE_EDGE_RISING>;
640 mboxes = <&ipcc IPCC_CLIENT_LP 634 mboxes = <&ipcc IPCC_CLIENT_LPASS
641 IPCC_MPROC_SIG 635 IPCC_MPROC_SIGNAL_SMP2P>;
642 636
643 qcom,local-pid = <0>; 637 qcom,local-pid = <0>;
644 qcom,remote-pid = <2>; 638 qcom,remote-pid = <2>;
645 639
646 smp2p_adsp_out: master-kernel 640 smp2p_adsp_out: master-kernel {
647 qcom,entry-name = "mas 641 qcom,entry-name = "master-kernel";
648 #qcom,smem-state-cells 642 #qcom,smem-state-cells = <1>;
649 }; 643 };
650 644
651 smp2p_adsp_in: slave-kernel { 645 smp2p_adsp_in: slave-kernel {
652 qcom,entry-name = "sla 646 qcom,entry-name = "slave-kernel";
653 interrupt-controller; 647 interrupt-controller;
654 #interrupt-cells = <2> 648 #interrupt-cells = <2>;
655 }; 649 };
656 }; 650 };
657 651
658 smp2p-cdsp { 652 smp2p-cdsp {
659 compatible = "qcom,smp2p"; 653 compatible = "qcom,smp2p";
660 qcom,smem = <94>, <432>; 654 qcom,smem = <94>, <432>;
661 interrupts-extended = <&ipcc I 655 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
662 I 656 IPCC_MPROC_SIGNAL_SMP2P
663 I 657 IRQ_TYPE_EDGE_RISING>;
664 mboxes = <&ipcc IPCC_CLIENT_CD 658 mboxes = <&ipcc IPCC_CLIENT_CDSP
665 IPCC_MPROC_SIG 659 IPCC_MPROC_SIGNAL_SMP2P>;
666 660
667 qcom,local-pid = <0>; 661 qcom,local-pid = <0>;
668 qcom,remote-pid = <5>; 662 qcom,remote-pid = <5>;
669 663
670 smp2p_cdsp_out: master-kernel 664 smp2p_cdsp_out: master-kernel {
671 qcom,entry-name = "mas 665 qcom,entry-name = "master-kernel";
672 #qcom,smem-state-cells 666 #qcom,smem-state-cells = <1>;
673 }; 667 };
674 668
675 smp2p_cdsp_in: slave-kernel { 669 smp2p_cdsp_in: slave-kernel {
676 qcom,entry-name = "sla 670 qcom,entry-name = "slave-kernel";
677 interrupt-controller; 671 interrupt-controller;
678 #interrupt-cells = <2> 672 #interrupt-cells = <2>;
679 }; 673 };
680 }; 674 };
681 675
682 smp2p-modem { 676 smp2p-modem {
683 compatible = "qcom,smp2p"; 677 compatible = "qcom,smp2p";
684 qcom,smem = <435>, <428>; 678 qcom,smem = <435>, <428>;
685 interrupts-extended = <&ipcc I 679 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
686 I 680 IPCC_MPROC_SIGNAL_SMP2P
687 I 681 IRQ_TYPE_EDGE_RISING>;
688 mboxes = <&ipcc IPCC_CLIENT_MP 682 mboxes = <&ipcc IPCC_CLIENT_MPSS
689 IPCC_MPROC_SIG 683 IPCC_MPROC_SIGNAL_SMP2P>;
690 684
691 qcom,local-pid = <0>; 685 qcom,local-pid = <0>;
692 qcom,remote-pid = <1>; 686 qcom,remote-pid = <1>;
693 687
694 smp2p_modem_out: master-kernel 688 smp2p_modem_out: master-kernel {
695 qcom,entry-name = "mas 689 qcom,entry-name = "master-kernel";
696 #qcom,smem-state-cells 690 #qcom,smem-state-cells = <1>;
697 }; 691 };
698 692
699 smp2p_modem_in: slave-kernel { 693 smp2p_modem_in: slave-kernel {
700 qcom,entry-name = "sla 694 qcom,entry-name = "slave-kernel";
701 interrupt-controller; 695 interrupt-controller;
702 #interrupt-cells = <2> 696 #interrupt-cells = <2>;
703 }; 697 };
704 698
705 ipa_smp2p_out: ipa-ap-to-modem 699 ipa_smp2p_out: ipa-ap-to-modem {
706 qcom,entry-name = "ipa 700 qcom,entry-name = "ipa";
707 #qcom,smem-state-cells 701 #qcom,smem-state-cells = <1>;
708 }; 702 };
709 703
710 ipa_smp2p_in: ipa-modem-to-ap 704 ipa_smp2p_in: ipa-modem-to-ap {
711 qcom,entry-name = "ipa 705 qcom,entry-name = "ipa";
712 interrupt-controller; 706 interrupt-controller;
713 #interrupt-cells = <2> 707 #interrupt-cells = <2>;
714 }; 708 };
715 }; 709 };
716 710
717 smp2p-slpi { 711 smp2p-slpi {
718 compatible = "qcom,smp2p"; 712 compatible = "qcom,smp2p";
719 qcom,smem = <481>, <430>; 713 qcom,smem = <481>, <430>;
720 interrupts-extended = <&ipcc I 714 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
721 I 715 IPCC_MPROC_SIGNAL_SMP2P
722 I 716 IRQ_TYPE_EDGE_RISING>;
723 mboxes = <&ipcc IPCC_CLIENT_SL 717 mboxes = <&ipcc IPCC_CLIENT_SLPI
724 IPCC_MPROC_SIG 718 IPCC_MPROC_SIGNAL_SMP2P>;
725 719
726 qcom,local-pid = <0>; 720 qcom,local-pid = <0>;
727 qcom,remote-pid = <3>; 721 qcom,remote-pid = <3>;
728 722
729 smp2p_slpi_out: master-kernel 723 smp2p_slpi_out: master-kernel {
730 qcom,entry-name = "mas 724 qcom,entry-name = "master-kernel";
731 #qcom,smem-state-cells 725 #qcom,smem-state-cells = <1>;
732 }; 726 };
733 727
734 smp2p_slpi_in: slave-kernel { 728 smp2p_slpi_in: slave-kernel {
735 qcom,entry-name = "sla 729 qcom,entry-name = "slave-kernel";
736 interrupt-controller; 730 interrupt-controller;
737 #interrupt-cells = <2> 731 #interrupt-cells = <2>;
738 }; 732 };
739 }; 733 };
740 734
741 soc: soc@0 { 735 soc: soc@0 {
742 #address-cells = <2>; 736 #address-cells = <2>;
743 #size-cells = <2>; 737 #size-cells = <2>;
744 ranges = <0 0 0 0 0x10 0>; 738 ranges = <0 0 0 0 0x10 0>;
745 dma-ranges = <0 0 0 0 0x10 0>; 739 dma-ranges = <0 0 0 0 0x10 0>;
746 compatible = "simple-bus"; 740 compatible = "simple-bus";
747 741
748 gcc: clock-controller@100000 { 742 gcc: clock-controller@100000 {
749 compatible = "qcom,gcc 743 compatible = "qcom,gcc-sm8450";
750 reg = <0x0 0x00100000 744 reg = <0x0 0x00100000 0x0 0x1f4200>;
751 #clock-cells = <1>; 745 #clock-cells = <1>;
752 #reset-cells = <1>; 746 #reset-cells = <1>;
753 #power-domain-cells = 747 #power-domain-cells = <1>;
754 clocks = <&rpmhcc RPMH 748 clocks = <&rpmhcc RPMH_CXO_CLK>,
755 <&sleep_clk>, 749 <&sleep_clk>,
756 <&pcie0_phy>, !! 750 <&pcie0_lane>,
757 <&pcie1_phy Q !! 751 <&pcie1_lane>,
758 <&pcie1_phy Q !! 752 <0>,
759 <&ufs_mem_phy !! 753 <&ufs_mem_phy_lanes 0>,
760 <&ufs_mem_phy !! 754 <&ufs_mem_phy_lanes 1>,
761 <&ufs_mem_phy !! 755 <&ufs_mem_phy_lanes 2>,
762 <&usb_1_qmpph 756 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
763 clock-names = "bi_tcxo 757 clock-names = "bi_tcxo",
764 "sleep_c 758 "sleep_clk",
765 "pcie_0_ 759 "pcie_0_pipe_clk",
766 "pcie_1_ 760 "pcie_1_pipe_clk",
767 "pcie_1_ 761 "pcie_1_phy_aux_clk",
768 "ufs_phy 762 "ufs_phy_rx_symbol_0_clk",
769 "ufs_phy 763 "ufs_phy_rx_symbol_1_clk",
770 "ufs_phy 764 "ufs_phy_tx_symbol_0_clk",
771 "usb3_ph 765 "usb3_phy_wrapper_gcc_usb30_pipe_clk";
772 }; 766 };
773 767
774 gpi_dma2: dma-controller@80000 768 gpi_dma2: dma-controller@800000 {
775 compatible = "qcom,sm8 769 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
776 #dma-cells = <3>; 770 #dma-cells = <3>;
777 reg = <0 0x00800000 0 771 reg = <0 0x00800000 0 0x60000>;
778 interrupts = <GIC_SPI 772 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
779 <GIC_SPI 773 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
780 <GIC_SPI 774 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
781 <GIC_SPI 775 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
782 <GIC_SPI 776 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
783 <GIC_SPI 777 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
784 <GIC_SPI 778 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
785 <GIC_SPI 779 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
786 <GIC_SPI 780 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
787 <GIC_SPI 781 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
788 <GIC_SPI 782 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
789 <GIC_SPI 783 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
790 dma-channels = <12>; 784 dma-channels = <12>;
791 dma-channel-mask = <0x 785 dma-channel-mask = <0x7e>;
792 iommus = <&apps_smmu 0 786 iommus = <&apps_smmu 0x496 0x0>;
793 status = "disabled"; 787 status = "disabled";
794 }; 788 };
795 789
796 qupv3_id_2: geniqup@8c0000 { 790 qupv3_id_2: geniqup@8c0000 {
797 compatible = "qcom,gen 791 compatible = "qcom,geni-se-qup";
798 reg = <0x0 0x008c0000 792 reg = <0x0 0x008c0000 0x0 0x2000>;
799 clock-names = "m-ahb", 793 clock-names = "m-ahb", "s-ahb";
800 clocks = <&gcc GCC_QUP 794 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
801 <&gcc GCC_QUP 795 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
802 iommus = <&apps_smmu 0 796 iommus = <&apps_smmu 0x483 0x0>;
803 #address-cells = <2>; 797 #address-cells = <2>;
804 #size-cells = <2>; 798 #size-cells = <2>;
805 ranges; 799 ranges;
806 status = "disabled"; 800 status = "disabled";
807 801
808 i2c15: i2c@880000 { 802 i2c15: i2c@880000 {
809 compatible = " 803 compatible = "qcom,geni-i2c";
810 reg = <0x0 0x0 804 reg = <0x0 0x00880000 0x0 0x4000>;
811 clock-names = 805 clock-names = "se";
812 clocks = <&gcc 806 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
813 pinctrl-names 807 pinctrl-names = "default";
814 pinctrl-0 = <& 808 pinctrl-0 = <&qup_i2c15_data_clk>;
815 interrupts = < 809 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
816 #address-cells 810 #address-cells = <1>;
817 #size-cells = 811 #size-cells = <0>;
818 interconnects 812 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
819 813 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
820 814 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
821 interconnect-n 815 interconnect-names = "qup-core", "qup-config", "qup-memory";
822 dmas = <&gpi_d 816 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
823 <&gpi_d 817 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
824 dma-names = "t 818 dma-names = "tx", "rx";
825 status = "disa 819 status = "disabled";
826 }; 820 };
827 821
828 spi15: spi@880000 { 822 spi15: spi@880000 {
829 compatible = " 823 compatible = "qcom,geni-spi";
830 reg = <0x0 0x0 824 reg = <0x0 0x00880000 0x0 0x4000>;
831 clock-names = 825 clock-names = "se";
832 clocks = <&gcc 826 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
833 interrupts = < 827 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
834 pinctrl-names 828 pinctrl-names = "default";
835 pinctrl-0 = <& 829 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
836 interconnects 830 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
837 831 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
838 interconnect-n 832 interconnect-names = "qup-core", "qup-config";
839 dmas = <&gpi_d 833 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
840 <&gpi_d 834 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
841 dma-names = "t 835 dma-names = "tx", "rx";
842 #address-cells 836 #address-cells = <1>;
843 #size-cells = 837 #size-cells = <0>;
844 status = "disa 838 status = "disabled";
845 }; 839 };
846 840
847 i2c16: i2c@884000 { 841 i2c16: i2c@884000 {
848 compatible = " 842 compatible = "qcom,geni-i2c";
849 reg = <0x0 0x0 843 reg = <0x0 0x00884000 0x0 0x4000>;
850 clock-names = 844 clock-names = "se";
851 clocks = <&gcc 845 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
852 pinctrl-names 846 pinctrl-names = "default";
853 pinctrl-0 = <& 847 pinctrl-0 = <&qup_i2c16_data_clk>;
854 interrupts = < 848 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
855 #address-cells 849 #address-cells = <1>;
856 #size-cells = 850 #size-cells = <0>;
857 interconnects 851 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
858 852 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
859 853 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
860 interconnect-n 854 interconnect-names = "qup-core", "qup-config", "qup-memory";
861 dmas = <&gpi_d 855 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
862 <&gpi_d 856 <&gpi_dma2 1 1 QCOM_GPI_I2C>;
863 dma-names = "t 857 dma-names = "tx", "rx";
864 status = "disa 858 status = "disabled";
865 }; 859 };
866 860
867 spi16: spi@884000 { 861 spi16: spi@884000 {
868 compatible = " 862 compatible = "qcom,geni-spi";
869 reg = <0x0 0x0 863 reg = <0x0 0x00884000 0x0 0x4000>;
870 clock-names = 864 clock-names = "se";
871 clocks = <&gcc 865 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
872 interrupts = < 866 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
873 pinctrl-names 867 pinctrl-names = "default";
874 pinctrl-0 = <& 868 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>;
875 interconnects 869 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
876 870 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
877 interconnect-n 871 interconnect-names = "qup-core", "qup-config";
878 dmas = <&gpi_d 872 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
879 <&gpi_d 873 <&gpi_dma2 1 1 QCOM_GPI_SPI>;
880 dma-names = "t 874 dma-names = "tx", "rx";
881 #address-cells 875 #address-cells = <1>;
882 #size-cells = 876 #size-cells = <0>;
883 status = "disa 877 status = "disabled";
884 }; 878 };
885 879
886 i2c17: i2c@888000 { 880 i2c17: i2c@888000 {
887 compatible = " 881 compatible = "qcom,geni-i2c";
888 reg = <0x0 0x0 882 reg = <0x0 0x00888000 0x0 0x4000>;
889 clock-names = 883 clock-names = "se";
890 clocks = <&gcc 884 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
891 pinctrl-names 885 pinctrl-names = "default";
892 pinctrl-0 = <& 886 pinctrl-0 = <&qup_i2c17_data_clk>;
893 interrupts = < 887 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
894 #address-cells 888 #address-cells = <1>;
895 #size-cells = 889 #size-cells = <0>;
896 interconnects 890 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
897 891 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
898 892 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
899 interconnect-n 893 interconnect-names = "qup-core", "qup-config", "qup-memory";
900 dmas = <&gpi_d 894 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
901 <&gpi_d 895 <&gpi_dma2 1 2 QCOM_GPI_I2C>;
902 dma-names = "t 896 dma-names = "tx", "rx";
903 status = "disa 897 status = "disabled";
904 }; 898 };
905 899
906 spi17: spi@888000 { 900 spi17: spi@888000 {
907 compatible = " 901 compatible = "qcom,geni-spi";
908 reg = <0x0 0x0 902 reg = <0x0 0x00888000 0x0 0x4000>;
909 clock-names = 903 clock-names = "se";
910 clocks = <&gcc 904 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
911 interrupts = < 905 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
912 pinctrl-names 906 pinctrl-names = "default";
913 pinctrl-0 = <& 907 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>;
914 interconnects 908 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
915 909 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
916 interconnect-n 910 interconnect-names = "qup-core", "qup-config";
917 dmas = <&gpi_d 911 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
918 <&gpi_d 912 <&gpi_dma2 1 2 QCOM_GPI_SPI>;
919 dma-names = "t 913 dma-names = "tx", "rx";
920 #address-cells 914 #address-cells = <1>;
921 #size-cells = 915 #size-cells = <0>;
922 status = "disa 916 status = "disabled";
923 }; 917 };
924 918
925 i2c18: i2c@88c000 { 919 i2c18: i2c@88c000 {
926 compatible = " 920 compatible = "qcom,geni-i2c";
927 reg = <0x0 0x0 921 reg = <0x0 0x0088c000 0x0 0x4000>;
928 clock-names = 922 clock-names = "se";
929 clocks = <&gcc 923 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
930 pinctrl-names 924 pinctrl-names = "default";
931 pinctrl-0 = <& 925 pinctrl-0 = <&qup_i2c18_data_clk>;
932 interrupts = < 926 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
933 #address-cells 927 #address-cells = <1>;
934 #size-cells = 928 #size-cells = <0>;
935 interconnects 929 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
936 930 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
937 931 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
938 interconnect-n 932 interconnect-names = "qup-core", "qup-config", "qup-memory";
939 dmas = <&gpi_d 933 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
940 <&gpi_d 934 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
941 dma-names = "t 935 dma-names = "tx", "rx";
942 status = "disa 936 status = "disabled";
943 }; 937 };
944 938
945 spi18: spi@88c000 { 939 spi18: spi@88c000 {
946 compatible = " 940 compatible = "qcom,geni-spi";
947 reg = <0 0x008 941 reg = <0 0x0088c000 0 0x4000>;
948 clock-names = 942 clock-names = "se";
949 clocks = <&gcc 943 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
950 interrupts = < 944 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
951 pinctrl-names 945 pinctrl-names = "default";
952 pinctrl-0 = <& 946 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>;
953 interconnects 947 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
954 948 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
955 interconnect-n 949 interconnect-names = "qup-core", "qup-config";
956 dmas = <&gpi_d 950 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
957 <&gpi_d 951 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
958 dma-names = "t 952 dma-names = "tx", "rx";
959 #address-cells 953 #address-cells = <1>;
960 #size-cells = 954 #size-cells = <0>;
961 status = "disa 955 status = "disabled";
962 }; 956 };
963 957
964 i2c19: i2c@890000 { 958 i2c19: i2c@890000 {
965 compatible = " 959 compatible = "qcom,geni-i2c";
966 reg = <0x0 0x0 960 reg = <0x0 0x00890000 0x0 0x4000>;
967 clock-names = 961 clock-names = "se";
968 clocks = <&gcc 962 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
969 pinctrl-names 963 pinctrl-names = "default";
970 pinctrl-0 = <& 964 pinctrl-0 = <&qup_i2c19_data_clk>;
971 interrupts = < 965 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
972 #address-cells 966 #address-cells = <1>;
973 #size-cells = 967 #size-cells = <0>;
974 interconnects 968 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
975 969 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
976 970 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
977 interconnect-n 971 interconnect-names = "qup-core", "qup-config", "qup-memory";
978 dmas = <&gpi_d 972 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
979 <&gpi_d 973 <&gpi_dma2 1 4 QCOM_GPI_I2C>;
980 dma-names = "t 974 dma-names = "tx", "rx";
981 status = "disa 975 status = "disabled";
982 }; 976 };
983 977
984 spi19: spi@890000 { 978 spi19: spi@890000 {
985 compatible = " 979 compatible = "qcom,geni-spi";
986 reg = <0 0x008 980 reg = <0 0x00890000 0 0x4000>;
987 clock-names = 981 clock-names = "se";
988 clocks = <&gcc 982 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
989 interrupts = < 983 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
990 pinctrl-names 984 pinctrl-names = "default";
991 pinctrl-0 = <& 985 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>;
992 interconnects 986 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
993 987 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
994 interconnect-n 988 interconnect-names = "qup-core", "qup-config";
995 dmas = <&gpi_d 989 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
996 <&gpi_d 990 <&gpi_dma2 1 4 QCOM_GPI_I2C>;
997 dma-names = "t 991 dma-names = "tx", "rx";
998 #address-cells 992 #address-cells = <1>;
999 #size-cells = 993 #size-cells = <0>;
1000 status = "dis 994 status = "disabled";
1001 }; 995 };
1002 996
1003 i2c20: i2c@894000 { 997 i2c20: i2c@894000 {
1004 compatible = 998 compatible = "qcom,geni-i2c";
1005 reg = <0x0 0x 999 reg = <0x0 0x00894000 0x0 0x4000>;
1006 clock-names = 1000 clock-names = "se";
1007 clocks = <&gc 1001 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1008 pinctrl-names 1002 pinctrl-names = "default";
1009 pinctrl-0 = < 1003 pinctrl-0 = <&qup_i2c20_data_clk>;
1010 interrupts = 1004 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1011 #address-cell 1005 #address-cells = <1>;
1012 #size-cells = 1006 #size-cells = <0>;
1013 interconnects 1007 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1014 1008 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1015 1009 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1016 interconnect- 1010 interconnect-names = "qup-core", "qup-config", "qup-memory";
1017 dmas = <&gpi_ 1011 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1018 <&gpi_ 1012 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1019 dma-names = " 1013 dma-names = "tx", "rx";
1020 status = "dis 1014 status = "disabled";
1021 }; 1015 };
1022 1016
1023 uart20: serial@894000 1017 uart20: serial@894000 {
1024 compatible = 1018 compatible = "qcom,geni-uart";
1025 reg = <0 0x00 1019 reg = <0 0x00894000 0 0x4000>;
1026 clock-names = 1020 clock-names = "se";
1027 clocks = <&gc 1021 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1028 pinctrl-names 1022 pinctrl-names = "default";
1029 pinctrl-0 = < 1023 pinctrl-0 = <&qup_uart20_default>;
1030 interrupts = 1024 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1031 interconnects <<
1032 <<
1033 <<
1034 <<
1035 interconnect- <<
1036 <<
1037 status = "dis 1025 status = "disabled";
1038 }; 1026 };
1039 1027
1040 spi20: spi@894000 { 1028 spi20: spi@894000 {
1041 compatible = 1029 compatible = "qcom,geni-spi";
1042 reg = <0 0x00 1030 reg = <0 0x00894000 0 0x4000>;
1043 clock-names = 1031 clock-names = "se";
1044 clocks = <&gc 1032 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1045 interrupts = 1033 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1046 pinctrl-names 1034 pinctrl-names = "default";
1047 pinctrl-0 = < 1035 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>;
1048 interconnects 1036 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1049 1037 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
1050 interconnect- 1038 interconnect-names = "qup-core", "qup-config";
1051 dmas = <&gpi_ 1039 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1052 <&gpi_ 1040 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1053 dma-names = " 1041 dma-names = "tx", "rx";
1054 #address-cell 1042 #address-cells = <1>;
1055 #size-cells = 1043 #size-cells = <0>;
1056 status = "dis 1044 status = "disabled";
1057 }; 1045 };
1058 1046
1059 i2c21: i2c@898000 { 1047 i2c21: i2c@898000 {
1060 compatible = 1048 compatible = "qcom,geni-i2c";
1061 reg = <0x0 0x 1049 reg = <0x0 0x00898000 0x0 0x4000>;
1062 clock-names = 1050 clock-names = "se";
1063 clocks = <&gc 1051 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1064 pinctrl-names 1052 pinctrl-names = "default";
1065 pinctrl-0 = < 1053 pinctrl-0 = <&qup_i2c21_data_clk>;
1066 interrupts = 1054 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
1067 #address-cell 1055 #address-cells = <1>;
1068 #size-cells = 1056 #size-cells = <0>;
1069 interconnects 1057 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1070 1058 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1071 1059 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1072 interconnect- 1060 interconnect-names = "qup-core", "qup-config", "qup-memory";
1073 dmas = <&gpi_ 1061 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>,
1074 <&gpi_ 1062 <&gpi_dma2 1 6 QCOM_GPI_I2C>;
1075 dma-names = " 1063 dma-names = "tx", "rx";
1076 status = "dis 1064 status = "disabled";
1077 }; 1065 };
1078 1066
1079 spi21: spi@898000 { 1067 spi21: spi@898000 {
1080 compatible = 1068 compatible = "qcom,geni-spi";
1081 reg = <0 0x00 1069 reg = <0 0x00898000 0 0x4000>;
1082 clock-names = 1070 clock-names = "se";
1083 clocks = <&gc 1071 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1084 interrupts = 1072 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
1085 pinctrl-names 1073 pinctrl-names = "default";
1086 pinctrl-0 = < 1074 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>;
1087 interconnects 1075 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1088 1076 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
1089 interconnect- 1077 interconnect-names = "qup-core", "qup-config";
1090 dmas = <&gpi_ 1078 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>,
1091 <&gpi_ 1079 <&gpi_dma2 1 6 QCOM_GPI_SPI>;
1092 dma-names = " 1080 dma-names = "tx", "rx";
1093 #address-cell 1081 #address-cells = <1>;
1094 #size-cells = 1082 #size-cells = <0>;
1095 status = "dis 1083 status = "disabled";
1096 }; 1084 };
1097 }; 1085 };
1098 1086
1099 gpi_dma0: dma-controller@9000 1087 gpi_dma0: dma-controller@900000 {
1100 compatible = "qcom,sm 1088 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
1101 #dma-cells = <3>; 1089 #dma-cells = <3>;
1102 reg = <0 0x00900000 0 1090 reg = <0 0x00900000 0 0x60000>;
1103 interrupts = <GIC_SPI 1091 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
1104 <GIC_SPI 1092 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
1105 <GIC_SPI 1093 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
1106 <GIC_SPI 1094 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
1107 <GIC_SPI 1095 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
1108 <GIC_SPI 1096 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
1109 <GIC_SPI 1097 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
1110 <GIC_SPI 1098 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
1111 <GIC_SPI 1099 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
1112 <GIC_SPI 1100 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
1113 <GIC_SPI 1101 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
1114 <GIC_SPI 1102 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
1115 dma-channels = <12>; 1103 dma-channels = <12>;
1116 dma-channel-mask = <0 1104 dma-channel-mask = <0x7e>;
1117 iommus = <&apps_smmu 1105 iommus = <&apps_smmu 0x5b6 0x0>;
1118 status = "disabled"; 1106 status = "disabled";
1119 }; 1107 };
1120 1108
1121 qupv3_id_0: geniqup@9c0000 { 1109 qupv3_id_0: geniqup@9c0000 {
1122 compatible = "qcom,ge 1110 compatible = "qcom,geni-se-qup";
1123 reg = <0x0 0x009c0000 1111 reg = <0x0 0x009c0000 0x0 0x2000>;
1124 clock-names = "m-ahb" 1112 clock-names = "m-ahb", "s-ahb";
1125 clocks = <&gcc GCC_QU 1113 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1126 <&gcc GCC_QU 1114 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1127 iommus = <&apps_smmu 1115 iommus = <&apps_smmu 0x5a3 0x0>;
1128 interconnects = <&clk 1116 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>;
1129 interconnect-names = 1117 interconnect-names = "qup-core";
1130 #address-cells = <2>; 1118 #address-cells = <2>;
1131 #size-cells = <2>; 1119 #size-cells = <2>;
1132 ranges; 1120 ranges;
1133 status = "disabled"; 1121 status = "disabled";
1134 1122
1135 i2c0: i2c@980000 { 1123 i2c0: i2c@980000 {
1136 compatible = 1124 compatible = "qcom,geni-i2c";
1137 reg = <0x0 0x 1125 reg = <0x0 0x00980000 0x0 0x4000>;
1138 clock-names = 1126 clock-names = "se";
1139 clocks = <&gc 1127 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1140 pinctrl-names 1128 pinctrl-names = "default";
1141 pinctrl-0 = < 1129 pinctrl-0 = <&qup_i2c0_data_clk>;
1142 interrupts = 1130 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1143 #address-cell 1131 #address-cells = <1>;
1144 #size-cells = 1132 #size-cells = <0>;
1145 interconnects 1133 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1146 1134 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1147 1135 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1148 interconnect- 1136 interconnect-names = "qup-core", "qup-config", "qup-memory";
1149 dmas = <&gpi_ 1137 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1150 <&gpi_ 1138 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1151 dma-names = " 1139 dma-names = "tx", "rx";
1152 status = "dis 1140 status = "disabled";
1153 }; 1141 };
1154 1142
1155 spi0: spi@980000 { 1143 spi0: spi@980000 {
1156 compatible = 1144 compatible = "qcom,geni-spi";
1157 reg = <0x0 0x 1145 reg = <0x0 0x00980000 0x0 0x4000>;
1158 clock-names = 1146 clock-names = "se";
1159 clocks = <&gc 1147 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1160 interrupts = 1148 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1161 pinctrl-names 1149 pinctrl-names = "default";
1162 pinctrl-0 = < 1150 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1163 power-domains !! 1151 power-domains = <&rpmhpd SM8450_CX>;
1164 operating-poi 1152 operating-points-v2 = <&qup_opp_table_100mhz>;
1165 interconnects 1153 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1166 1154 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1167 1155 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1168 interconnect- 1156 interconnect-names = "qup-core", "qup-config", "qup-memory";
1169 dmas = <&gpi_ 1157 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1170 <&gpi_ 1158 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1171 dma-names = " 1159 dma-names = "tx", "rx";
1172 #address-cell 1160 #address-cells = <1>;
1173 #size-cells = 1161 #size-cells = <0>;
1174 status = "dis 1162 status = "disabled";
1175 }; 1163 };
1176 1164
1177 i2c1: i2c@984000 { 1165 i2c1: i2c@984000 {
1178 compatible = 1166 compatible = "qcom,geni-i2c";
1179 reg = <0x0 0x 1167 reg = <0x0 0x00984000 0x0 0x4000>;
1180 clock-names = 1168 clock-names = "se";
1181 clocks = <&gc 1169 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1182 pinctrl-names 1170 pinctrl-names = "default";
1183 pinctrl-0 = < 1171 pinctrl-0 = <&qup_i2c1_data_clk>;
1184 interrupts = 1172 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1185 #address-cell 1173 #address-cells = <1>;
1186 #size-cells = 1174 #size-cells = <0>;
1187 interconnects 1175 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1188 1176 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1189 1177 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1190 interconnect- 1178 interconnect-names = "qup-core", "qup-config", "qup-memory";
1191 dmas = <&gpi_ 1179 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1192 <&gpi_ 1180 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1193 dma-names = " 1181 dma-names = "tx", "rx";
1194 status = "dis 1182 status = "disabled";
1195 }; 1183 };
1196 1184
1197 spi1: spi@984000 { 1185 spi1: spi@984000 {
1198 compatible = 1186 compatible = "qcom,geni-spi";
1199 reg = <0x0 0x 1187 reg = <0x0 0x00984000 0x0 0x4000>;
1200 clock-names = 1188 clock-names = "se";
1201 clocks = <&gc 1189 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1202 interrupts = 1190 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1203 pinctrl-names 1191 pinctrl-names = "default";
1204 pinctrl-0 = < 1192 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1205 interconnects 1193 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1206 1194 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1207 1195 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1208 interconnect- 1196 interconnect-names = "qup-core", "qup-config", "qup-memory";
1209 dmas = <&gpi_ 1197 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1210 <&gpi_ 1198 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1211 dma-names = " 1199 dma-names = "tx", "rx";
1212 #address-cell 1200 #address-cells = <1>;
1213 #size-cells = 1201 #size-cells = <0>;
1214 status = "dis 1202 status = "disabled";
1215 }; 1203 };
1216 1204
1217 i2c2: i2c@988000 { 1205 i2c2: i2c@988000 {
1218 compatible = 1206 compatible = "qcom,geni-i2c";
1219 reg = <0x0 0x 1207 reg = <0x0 0x00988000 0x0 0x4000>;
1220 clock-names = 1208 clock-names = "se";
1221 clocks = <&gc 1209 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1222 pinctrl-names 1210 pinctrl-names = "default";
1223 pinctrl-0 = < 1211 pinctrl-0 = <&qup_i2c2_data_clk>;
1224 interrupts = 1212 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1225 #address-cell 1213 #address-cells = <1>;
1226 #size-cells = 1214 #size-cells = <0>;
1227 interconnects 1215 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1228 1216 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1229 1217 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1230 interconnect- 1218 interconnect-names = "qup-core", "qup-config", "qup-memory";
1231 dmas = <&gpi_ 1219 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1232 <&gpi_ 1220 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1233 dma-names = " 1221 dma-names = "tx", "rx";
1234 status = "dis 1222 status = "disabled";
1235 }; 1223 };
1236 1224
1237 spi2: spi@988000 { 1225 spi2: spi@988000 {
1238 compatible = 1226 compatible = "qcom,geni-spi";
1239 reg = <0x0 0x 1227 reg = <0x0 0x00988000 0x0 0x4000>;
1240 clock-names = 1228 clock-names = "se";
1241 clocks = <&gc 1229 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1242 interrupts = 1230 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1243 pinctrl-names 1231 pinctrl-names = "default";
1244 pinctrl-0 = < 1232 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1245 interconnects 1233 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1246 1234 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1247 1235 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1248 interconnect- 1236 interconnect-names = "qup-core", "qup-config", "qup-memory";
1249 dmas = <&gpi_ 1237 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1250 <&gpi_ 1238 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1251 dma-names = " 1239 dma-names = "tx", "rx";
1252 #address-cell 1240 #address-cells = <1>;
1253 #size-cells = 1241 #size-cells = <0>;
1254 status = "dis 1242 status = "disabled";
1255 }; 1243 };
1256 1244
1257 1245
1258 i2c3: i2c@98c000 { 1246 i2c3: i2c@98c000 {
1259 compatible = 1247 compatible = "qcom,geni-i2c";
1260 reg = <0x0 0x 1248 reg = <0x0 0x0098c000 0x0 0x4000>;
1261 clock-names = 1249 clock-names = "se";
1262 clocks = <&gc 1250 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1263 pinctrl-names 1251 pinctrl-names = "default";
1264 pinctrl-0 = < 1252 pinctrl-0 = <&qup_i2c3_data_clk>;
1265 interrupts = 1253 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1266 #address-cell 1254 #address-cells = <1>;
1267 #size-cells = 1255 #size-cells = <0>;
1268 interconnects 1256 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1269 1257 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1270 1258 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1271 interconnect- 1259 interconnect-names = "qup-core", "qup-config", "qup-memory";
1272 dmas = <&gpi_ 1260 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1273 <&gpi_ 1261 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1274 dma-names = " 1262 dma-names = "tx", "rx";
1275 status = "dis 1263 status = "disabled";
1276 }; 1264 };
1277 1265
1278 spi3: spi@98c000 { 1266 spi3: spi@98c000 {
1279 compatible = 1267 compatible = "qcom,geni-spi";
1280 reg = <0x0 0x 1268 reg = <0x0 0x0098c000 0x0 0x4000>;
1281 clock-names = 1269 clock-names = "se";
1282 clocks = <&gc 1270 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1283 interrupts = 1271 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1284 pinctrl-names 1272 pinctrl-names = "default";
1285 pinctrl-0 = < 1273 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1286 interconnects 1274 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1287 1275 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1288 1276 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1289 interconnect- 1277 interconnect-names = "qup-core", "qup-config", "qup-memory";
1290 dmas = <&gpi_ 1278 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1291 <&gpi_ 1279 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1292 dma-names = " 1280 dma-names = "tx", "rx";
1293 #address-cell 1281 #address-cells = <1>;
1294 #size-cells = 1282 #size-cells = <0>;
1295 status = "dis 1283 status = "disabled";
1296 }; 1284 };
1297 1285
1298 i2c4: i2c@990000 { 1286 i2c4: i2c@990000 {
1299 compatible = 1287 compatible = "qcom,geni-i2c";
1300 reg = <0x0 0x 1288 reg = <0x0 0x00990000 0x0 0x4000>;
1301 clock-names = 1289 clock-names = "se";
1302 clocks = <&gc 1290 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1303 pinctrl-names 1291 pinctrl-names = "default";
1304 pinctrl-0 = < 1292 pinctrl-0 = <&qup_i2c4_data_clk>;
1305 interrupts = 1293 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1306 #address-cell 1294 #address-cells = <1>;
1307 #size-cells = 1295 #size-cells = <0>;
1308 interconnects 1296 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1309 1297 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1310 1298 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1311 interconnect- 1299 interconnect-names = "qup-core", "qup-config", "qup-memory";
1312 dmas = <&gpi_ 1300 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1313 <&gpi_ 1301 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1314 dma-names = " 1302 dma-names = "tx", "rx";
1315 status = "dis 1303 status = "disabled";
1316 }; 1304 };
1317 1305
1318 spi4: spi@990000 { 1306 spi4: spi@990000 {
1319 compatible = 1307 compatible = "qcom,geni-spi";
1320 reg = <0x0 0x 1308 reg = <0x0 0x00990000 0x0 0x4000>;
1321 clock-names = 1309 clock-names = "se";
1322 clocks = <&gc 1310 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1323 interrupts = 1311 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1324 pinctrl-names 1312 pinctrl-names = "default";
1325 pinctrl-0 = < 1313 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1326 power-domains !! 1314 power-domains = <&rpmhpd SM8450_CX>;
1327 operating-poi 1315 operating-points-v2 = <&qup_opp_table_100mhz>;
1328 interconnects 1316 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1329 1317 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1330 1318 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1331 interconnect- 1319 interconnect-names = "qup-core", "qup-config", "qup-memory";
1332 dmas = <&gpi_ 1320 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1333 <&gpi_ 1321 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1334 dma-names = " 1322 dma-names = "tx", "rx";
1335 #address-cell 1323 #address-cells = <1>;
1336 #size-cells = 1324 #size-cells = <0>;
1337 status = "dis 1325 status = "disabled";
1338 }; 1326 };
1339 1327
1340 i2c5: i2c@994000 { 1328 i2c5: i2c@994000 {
1341 compatible = 1329 compatible = "qcom,geni-i2c";
1342 reg = <0x0 0x 1330 reg = <0x0 0x00994000 0x0 0x4000>;
1343 clock-names = 1331 clock-names = "se";
1344 clocks = <&gc 1332 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1345 pinctrl-names 1333 pinctrl-names = "default";
1346 pinctrl-0 = < 1334 pinctrl-0 = <&qup_i2c5_data_clk>;
1347 interrupts = 1335 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1348 #address-cell 1336 #address-cells = <1>;
1349 #size-cells = 1337 #size-cells = <0>;
1350 interconnects 1338 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1351 1339 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1352 1340 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1353 interconnect- 1341 interconnect-names = "qup-core", "qup-config", "qup-memory";
1354 dmas = <&gpi_ 1342 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1355 <&gpi_ 1343 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1356 dma-names = " 1344 dma-names = "tx", "rx";
1357 status = "dis 1345 status = "disabled";
1358 }; 1346 };
1359 1347
1360 spi5: spi@994000 { 1348 spi5: spi@994000 {
1361 compatible = 1349 compatible = "qcom,geni-spi";
1362 reg = <0x0 0x 1350 reg = <0x0 0x00994000 0x0 0x4000>;
1363 clock-names = 1351 clock-names = "se";
1364 clocks = <&gc 1352 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1365 interrupts = 1353 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1366 pinctrl-names 1354 pinctrl-names = "default";
1367 pinctrl-0 = < 1355 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1368 interconnects 1356 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1369 1357 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1370 1358 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1371 interconnect- 1359 interconnect-names = "qup-core", "qup-config", "qup-memory";
1372 dmas = <&gpi_ 1360 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1373 <&gpi_ 1361 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1374 dma-names = " 1362 dma-names = "tx", "rx";
1375 #address-cell 1363 #address-cells = <1>;
1376 #size-cells = 1364 #size-cells = <0>;
1377 status = "dis 1365 status = "disabled";
1378 }; 1366 };
1379 1367
1380 1368
1381 i2c6: i2c@998000 { 1369 i2c6: i2c@998000 {
1382 compatible = 1370 compatible = "qcom,geni-i2c";
1383 reg = <0x0 0x 1371 reg = <0x0 0x00998000 0x0 0x4000>;
1384 clock-names = 1372 clock-names = "se";
1385 clocks = <&gc 1373 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1386 pinctrl-names 1374 pinctrl-names = "default";
1387 pinctrl-0 = < 1375 pinctrl-0 = <&qup_i2c6_data_clk>;
1388 interrupts = 1376 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1389 #address-cell 1377 #address-cells = <1>;
1390 #size-cells = 1378 #size-cells = <0>;
1391 interconnects 1379 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1392 1380 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1393 1381 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1394 interconnect- 1382 interconnect-names = "qup-core", "qup-config", "qup-memory";
1395 dmas = <&gpi_ 1383 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1396 <&gpi_ 1384 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1397 dma-names = " 1385 dma-names = "tx", "rx";
1398 status = "dis 1386 status = "disabled";
1399 }; 1387 };
1400 1388
1401 spi6: spi@998000 { 1389 spi6: spi@998000 {
1402 compatible = 1390 compatible = "qcom,geni-spi";
1403 reg = <0x0 0x 1391 reg = <0x0 0x00998000 0x0 0x4000>;
1404 clock-names = 1392 clock-names = "se";
1405 clocks = <&gc 1393 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1406 interrupts = 1394 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1407 pinctrl-names 1395 pinctrl-names = "default";
1408 pinctrl-0 = < 1396 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1409 interconnects 1397 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1410 1398 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1411 1399 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1412 interconnect- 1400 interconnect-names = "qup-core", "qup-config", "qup-memory";
1413 dmas = <&gpi_ 1401 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1414 <&gpi_ 1402 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1415 dma-names = " 1403 dma-names = "tx", "rx";
1416 #address-cell 1404 #address-cells = <1>;
1417 #size-cells = 1405 #size-cells = <0>;
1418 status = "dis 1406 status = "disabled";
1419 }; 1407 };
1420 1408
1421 uart7: serial@99c000 1409 uart7: serial@99c000 {
1422 compatible = 1410 compatible = "qcom,geni-debug-uart";
1423 reg = <0 0x00 1411 reg = <0 0x0099c000 0 0x4000>;
1424 clock-names = 1412 clock-names = "se";
1425 clocks = <&gc 1413 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1426 pinctrl-names 1414 pinctrl-names = "default";
1427 pinctrl-0 = < 1415 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>;
1428 interrupts = 1416 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1429 interconnects <<
1430 <<
1431 <<
1432 <<
1433 interconnect- <<
1434 <<
1435 status = "dis 1417 status = "disabled";
1436 }; 1418 };
1437 }; 1419 };
1438 1420
1439 gpi_dma1: dma-controller@a000 1421 gpi_dma1: dma-controller@a00000 {
1440 compatible = "qcom,sm 1422 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
1441 #dma-cells = <3>; 1423 #dma-cells = <3>;
1442 reg = <0 0x00a00000 0 1424 reg = <0 0x00a00000 0 0x60000>;
1443 interrupts = <GIC_SPI 1425 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1444 <GIC_SPI 1426 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1445 <GIC_SPI 1427 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1446 <GIC_SPI 1428 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1447 <GIC_SPI 1429 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1448 <GIC_SPI 1430 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1449 <GIC_SPI 1431 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1450 <GIC_SPI 1432 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1451 <GIC_SPI 1433 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1452 <GIC_SPI 1434 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1453 <GIC_SPI 1435 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1454 <GIC_SPI 1436 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
1455 dma-channels = <12>; 1437 dma-channels = <12>;
1456 dma-channel-mask = <0 1438 dma-channel-mask = <0x7e>;
1457 iommus = <&apps_smmu 1439 iommus = <&apps_smmu 0x56 0x0>;
1458 status = "disabled"; 1440 status = "disabled";
1459 }; 1441 };
1460 1442
1461 qupv3_id_1: geniqup@ac0000 { 1443 qupv3_id_1: geniqup@ac0000 {
1462 compatible = "qcom,ge 1444 compatible = "qcom,geni-se-qup";
1463 reg = <0x0 0x00ac0000 1445 reg = <0x0 0x00ac0000 0x0 0x6000>;
1464 clock-names = "m-ahb" 1446 clock-names = "m-ahb", "s-ahb";
1465 clocks = <&gcc GCC_QU 1447 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1466 <&gcc GCC_QU 1448 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1467 iommus = <&apps_smmu 1449 iommus = <&apps_smmu 0x43 0x0>;
1468 interconnects = <&clk 1450 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>;
1469 interconnect-names = 1451 interconnect-names = "qup-core";
1470 #address-cells = <2>; 1452 #address-cells = <2>;
1471 #size-cells = <2>; 1453 #size-cells = <2>;
1472 ranges; 1454 ranges;
1473 status = "disabled"; 1455 status = "disabled";
1474 1456
1475 i2c8: i2c@a80000 { 1457 i2c8: i2c@a80000 {
1476 compatible = 1458 compatible = "qcom,geni-i2c";
1477 reg = <0x0 0x 1459 reg = <0x0 0x00a80000 0x0 0x4000>;
1478 clock-names = 1460 clock-names = "se";
1479 clocks = <&gc 1461 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1480 pinctrl-names 1462 pinctrl-names = "default";
1481 pinctrl-0 = < 1463 pinctrl-0 = <&qup_i2c8_data_clk>;
1482 interrupts = 1464 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1483 #address-cell 1465 #address-cells = <1>;
1484 #size-cells = 1466 #size-cells = <0>;
1485 interconnects 1467 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1486 1468 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1487 1469 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1488 interconnect- 1470 interconnect-names = "qup-core", "qup-config", "qup-memory";
1489 dmas = <&gpi_ 1471 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1490 <&gpi_ 1472 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1491 dma-names = " 1473 dma-names = "tx", "rx";
1492 status = "dis 1474 status = "disabled";
1493 }; 1475 };
1494 1476
1495 spi8: spi@a80000 { 1477 spi8: spi@a80000 {
1496 compatible = 1478 compatible = "qcom,geni-spi";
1497 reg = <0x0 0x 1479 reg = <0x0 0x00a80000 0x0 0x4000>;
1498 clock-names = 1480 clock-names = "se";
1499 clocks = <&gc 1481 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1500 interrupts = 1482 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1501 pinctrl-names 1483 pinctrl-names = "default";
1502 pinctrl-0 = < 1484 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1503 interconnects 1485 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1504 1486 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1505 1487 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1506 interconnect- 1488 interconnect-names = "qup-core", "qup-config", "qup-memory";
1507 dmas = <&gpi_ 1489 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1508 <&gpi_ 1490 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1509 dma-names = " 1491 dma-names = "tx", "rx";
1510 #address-cell 1492 #address-cells = <1>;
1511 #size-cells = 1493 #size-cells = <0>;
1512 status = "dis 1494 status = "disabled";
1513 }; 1495 };
1514 1496
1515 i2c9: i2c@a84000 { 1497 i2c9: i2c@a84000 {
1516 compatible = 1498 compatible = "qcom,geni-i2c";
1517 reg = <0x0 0x 1499 reg = <0x0 0x00a84000 0x0 0x4000>;
1518 clock-names = 1500 clock-names = "se";
1519 clocks = <&gc 1501 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1520 pinctrl-names 1502 pinctrl-names = "default";
1521 pinctrl-0 = < 1503 pinctrl-0 = <&qup_i2c9_data_clk>;
1522 interrupts = 1504 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1523 #address-cell 1505 #address-cells = <1>;
1524 #size-cells = 1506 #size-cells = <0>;
1525 interconnects 1507 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1526 1508 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1527 1509 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1528 interconnect- 1510 interconnect-names = "qup-core", "qup-config", "qup-memory";
1529 dmas = <&gpi_ 1511 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1530 <&gpi_ 1512 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1531 dma-names = " 1513 dma-names = "tx", "rx";
1532 status = "dis 1514 status = "disabled";
1533 }; 1515 };
1534 1516
1535 spi9: spi@a84000 { 1517 spi9: spi@a84000 {
1536 compatible = 1518 compatible = "qcom,geni-spi";
1537 reg = <0x0 0x 1519 reg = <0x0 0x00a84000 0x0 0x4000>;
1538 clock-names = 1520 clock-names = "se";
1539 clocks = <&gc 1521 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1540 interrupts = 1522 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1541 pinctrl-names 1523 pinctrl-names = "default";
1542 pinctrl-0 = < 1524 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1543 interconnects 1525 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1544 1526 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1545 1527 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1546 interconnect- 1528 interconnect-names = "qup-core", "qup-config", "qup-memory";
1547 dmas = <&gpi_ 1529 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1548 <&gpi_ 1530 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1549 dma-names = " 1531 dma-names = "tx", "rx";
1550 #address-cell 1532 #address-cells = <1>;
1551 #size-cells = 1533 #size-cells = <0>;
1552 status = "dis 1534 status = "disabled";
1553 }; 1535 };
1554 1536
1555 i2c10: i2c@a88000 { 1537 i2c10: i2c@a88000 {
1556 compatible = 1538 compatible = "qcom,geni-i2c";
1557 reg = <0x0 0x 1539 reg = <0x0 0x00a88000 0x0 0x4000>;
1558 clock-names = 1540 clock-names = "se";
1559 clocks = <&gc 1541 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1560 pinctrl-names 1542 pinctrl-names = "default";
1561 pinctrl-0 = < 1543 pinctrl-0 = <&qup_i2c10_data_clk>;
1562 interrupts = 1544 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1563 #address-cell 1545 #address-cells = <1>;
1564 #size-cells = 1546 #size-cells = <0>;
1565 interconnects 1547 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1566 1548 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1567 1549 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1568 interconnect- 1550 interconnect-names = "qup-core", "qup-config", "qup-memory";
1569 dmas = <&gpi_ 1551 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1570 <&gpi_ 1552 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1571 dma-names = " 1553 dma-names = "tx", "rx";
1572 status = "dis 1554 status = "disabled";
1573 }; 1555 };
1574 1556
1575 spi10: spi@a88000 { 1557 spi10: spi@a88000 {
1576 compatible = 1558 compatible = "qcom,geni-spi";
1577 reg = <0x0 0x 1559 reg = <0x0 0x00a88000 0x0 0x4000>;
1578 clock-names = 1560 clock-names = "se";
1579 clocks = <&gc 1561 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1580 interrupts = 1562 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1581 pinctrl-names 1563 pinctrl-names = "default";
1582 pinctrl-0 = < 1564 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1583 interconnects 1565 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1584 1566 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1585 1567 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1586 interconnect- 1568 interconnect-names = "qup-core", "qup-config", "qup-memory";
1587 dmas = <&gpi_ 1569 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1588 <&gpi_ 1570 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1589 dma-names = " 1571 dma-names = "tx", "rx";
1590 #address-cell 1572 #address-cells = <1>;
1591 #size-cells = 1573 #size-cells = <0>;
1592 status = "dis 1574 status = "disabled";
1593 }; 1575 };
1594 1576
1595 i2c11: i2c@a8c000 { 1577 i2c11: i2c@a8c000 {
1596 compatible = 1578 compatible = "qcom,geni-i2c";
1597 reg = <0x0 0x 1579 reg = <0x0 0x00a8c000 0x0 0x4000>;
1598 clock-names = 1580 clock-names = "se";
1599 clocks = <&gc 1581 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1600 pinctrl-names 1582 pinctrl-names = "default";
1601 pinctrl-0 = < 1583 pinctrl-0 = <&qup_i2c11_data_clk>;
1602 interrupts = 1584 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1603 #address-cell 1585 #address-cells = <1>;
1604 #size-cells = 1586 #size-cells = <0>;
1605 interconnects 1587 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1606 1588 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1607 1589 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1608 interconnect- 1590 interconnect-names = "qup-core", "qup-config", "qup-memory";
1609 dmas = <&gpi_ 1591 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1610 <&gpi_ 1592 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1611 dma-names = " 1593 dma-names = "tx", "rx";
1612 status = "dis 1594 status = "disabled";
1613 }; 1595 };
1614 1596
1615 spi11: spi@a8c000 { 1597 spi11: spi@a8c000 {
1616 compatible = 1598 compatible = "qcom,geni-spi";
1617 reg = <0x0 0x 1599 reg = <0x0 0x00a8c000 0x0 0x4000>;
1618 clock-names = 1600 clock-names = "se";
1619 clocks = <&gc 1601 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1620 interrupts = 1602 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1621 pinctrl-names 1603 pinctrl-names = "default";
1622 pinctrl-0 = < 1604 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1623 interconnects 1605 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1624 1606 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1625 1607 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1626 interconnect- 1608 interconnect-names = "qup-core", "qup-config", "qup-memory";
1627 dmas = <&gpi_ 1609 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1628 <&gpi_ 1610 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1629 dma-names = " 1611 dma-names = "tx", "rx";
1630 #address-cell 1612 #address-cells = <1>;
1631 #size-cells = 1613 #size-cells = <0>;
1632 status = "dis 1614 status = "disabled";
1633 }; 1615 };
1634 1616
1635 i2c12: i2c@a90000 { 1617 i2c12: i2c@a90000 {
1636 compatible = 1618 compatible = "qcom,geni-i2c";
1637 reg = <0x0 0x 1619 reg = <0x0 0x00a90000 0x0 0x4000>;
1638 clock-names = 1620 clock-names = "se";
1639 clocks = <&gc 1621 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1640 pinctrl-names 1622 pinctrl-names = "default";
1641 pinctrl-0 = < 1623 pinctrl-0 = <&qup_i2c12_data_clk>;
1642 interrupts = 1624 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1643 #address-cell 1625 #address-cells = <1>;
1644 #size-cells = 1626 #size-cells = <0>;
1645 interconnects 1627 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1646 1628 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1647 1629 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1648 interconnect- 1630 interconnect-names = "qup-core", "qup-config", "qup-memory";
1649 dmas = <&gpi_ 1631 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1650 <&gpi_ 1632 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1651 dma-names = " 1633 dma-names = "tx", "rx";
1652 status = "dis 1634 status = "disabled";
1653 }; 1635 };
1654 1636
1655 spi12: spi@a90000 { 1637 spi12: spi@a90000 {
1656 compatible = 1638 compatible = "qcom,geni-spi";
1657 reg = <0x0 0x 1639 reg = <0x0 0x00a90000 0x0 0x4000>;
1658 clock-names = 1640 clock-names = "se";
1659 clocks = <&gc 1641 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1660 interrupts = 1642 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1661 pinctrl-names 1643 pinctrl-names = "default";
1662 pinctrl-0 = < 1644 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1663 interconnects 1645 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1664 1646 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1665 1647 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1666 interconnect- 1648 interconnect-names = "qup-core", "qup-config", "qup-memory";
1667 dmas = <&gpi_ 1649 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1668 <&gpi_ 1650 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1669 dma-names = " 1651 dma-names = "tx", "rx";
1670 #address-cell 1652 #address-cells = <1>;
1671 #size-cells = 1653 #size-cells = <0>;
1672 status = "dis 1654 status = "disabled";
1673 }; 1655 };
1674 1656
1675 i2c13: i2c@a94000 { 1657 i2c13: i2c@a94000 {
1676 compatible = 1658 compatible = "qcom,geni-i2c";
1677 reg = <0 0x00 1659 reg = <0 0x00a94000 0 0x4000>;
1678 clock-names = 1660 clock-names = "se";
1679 clocks = <&gc 1661 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1680 pinctrl-names 1662 pinctrl-names = "default";
1681 pinctrl-0 = < 1663 pinctrl-0 = <&qup_i2c13_data_clk>;
1682 interrupts = 1664 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1683 interconnects 1665 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1684 1666 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1685 1667 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1686 interconnect- 1668 interconnect-names = "qup-core", "qup-config", "qup-memory";
1687 dmas = <&gpi_ 1669 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1688 <&gpi_ 1670 <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1689 dma-names = " 1671 dma-names = "tx", "rx";
1690 #address-cell 1672 #address-cells = <1>;
1691 #size-cells = 1673 #size-cells = <0>;
1692 status = "dis 1674 status = "disabled";
1693 }; 1675 };
1694 1676
1695 spi13: spi@a94000 { 1677 spi13: spi@a94000 {
1696 compatible = 1678 compatible = "qcom,geni-spi";
1697 reg = <0x0 0x 1679 reg = <0x0 0x00a94000 0x0 0x4000>;
1698 clock-names = 1680 clock-names = "se";
1699 clocks = <&gc 1681 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1700 interrupts = 1682 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1701 pinctrl-names 1683 pinctrl-names = "default";
1702 pinctrl-0 = < 1684 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1703 interconnects 1685 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1704 1686 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1705 1687 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1706 interconnect- 1688 interconnect-names = "qup-core", "qup-config", "qup-memory";
1707 dmas = <&gpi_ 1689 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1708 <&gpi_ 1690 <&gpi_dma1 1 5 QCOM_GPI_SPI>;
1709 dma-names = " 1691 dma-names = "tx", "rx";
1710 #address-cell 1692 #address-cells = <1>;
1711 #size-cells = 1693 #size-cells = <0>;
1712 status = "dis 1694 status = "disabled";
1713 }; 1695 };
1714 1696
1715 i2c14: i2c@a98000 { 1697 i2c14: i2c@a98000 {
1716 compatible = 1698 compatible = "qcom,geni-i2c";
1717 reg = <0 0x00 1699 reg = <0 0x00a98000 0 0x4000>;
1718 clock-names = 1700 clock-names = "se";
1719 clocks = <&gc 1701 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1720 pinctrl-names 1702 pinctrl-names = "default";
1721 pinctrl-0 = < 1703 pinctrl-0 = <&qup_i2c14_data_clk>;
1722 interrupts = 1704 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
1723 interconnects 1705 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1724 1706 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1725 1707 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1726 interconnect- 1708 interconnect-names = "qup-core", "qup-config", "qup-memory";
1727 dmas = <&gpi_ 1709 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
1728 <&gpi_ 1710 <&gpi_dma1 1 6 QCOM_GPI_I2C>;
1729 dma-names = " 1711 dma-names = "tx", "rx";
1730 #address-cell 1712 #address-cells = <1>;
1731 #size-cells = 1713 #size-cells = <0>;
1732 status = "dis 1714 status = "disabled";
1733 }; 1715 };
1734 1716
1735 spi14: spi@a98000 { 1717 spi14: spi@a98000 {
1736 compatible = 1718 compatible = "qcom,geni-spi";
1737 reg = <0x0 0x 1719 reg = <0x0 0x00a98000 0x0 0x4000>;
1738 clock-names = 1720 clock-names = "se";
1739 clocks = <&gc 1721 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1740 interrupts = 1722 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
1741 pinctrl-names 1723 pinctrl-names = "default";
1742 pinctrl-0 = < 1724 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
1743 interconnects 1725 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1744 1726 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1745 1727 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1746 interconnect- 1728 interconnect-names = "qup-core", "qup-config", "qup-memory";
1747 dmas = <&gpi_ 1729 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
1748 <&gpi_ 1730 <&gpi_dma1 1 6 QCOM_GPI_SPI>;
1749 dma-names = " 1731 dma-names = "tx", "rx";
1750 #address-cell 1732 #address-cells = <1>;
1751 #size-cells = 1733 #size-cells = <0>;
1752 status = "dis 1734 status = "disabled";
1753 }; 1735 };
1754 }; 1736 };
1755 1737
1756 rng: rng@10c3000 { !! 1738 pcie0: pci@1c00000 {
1757 compatible = "qcom,sm <<
1758 reg = <0 0x010c3000 0 <<
1759 }; <<
1760 <<
1761 pcie0: pcie@1c00000 { <<
1762 compatible = "qcom,pc 1739 compatible = "qcom,pcie-sm8450-pcie0";
1763 reg = <0 0x01c00000 0 1740 reg = <0 0x01c00000 0 0x3000>,
1764 <0 0x60000000 0 1741 <0 0x60000000 0 0xf1d>,
1765 <0 0x60000f20 0 1742 <0 0x60000f20 0 0xa8>,
1766 <0 0x60001000 0 1743 <0 0x60001000 0 0x1000>,
1767 <0 0x60100000 0 1744 <0 0x60100000 0 0x100000>;
1768 reg-names = "parf", " 1745 reg-names = "parf", "dbi", "elbi", "atu", "config";
1769 device_type = "pci"; 1746 device_type = "pci";
1770 linux,pci-domain = <0 1747 linux,pci-domain = <0>;
1771 bus-range = <0x00 0xf 1748 bus-range = <0x00 0xff>;
1772 num-lanes = <1>; 1749 num-lanes = <1>;
1773 1750
1774 #address-cells = <3>; 1751 #address-cells = <3>;
1775 #size-cells = <2>; 1752 #size-cells = <2>;
1776 1753
1777 ranges = <0x01000000 1754 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
1778 <0x02000000 1755 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1779 1756
1780 msi-map = <0x0 &gic_i !! 1757 /*
1781 <0x100 &gic !! 1758 * MSIs for BDF (1:0.0) only works with Device ID 0x5980.
>> 1759 * Hence, the IDs are swapped.
>> 1760 */
>> 1761 msi-map = <0x0 &gic_its 0x5981 0x1>,
>> 1762 <0x100 &gic_its 0x5980 0x1>;
1782 msi-map-mask = <0xff0 1763 msi-map-mask = <0xff00>;
1783 interrupts = <GIC_SPI !! 1764 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
1784 <GIC_SPI !! 1765 interrupt-names = "msi";
1785 <GIC_SPI <<
1786 <GIC_SPI <<
1787 <GIC_SPI <<
1788 <GIC_SPI <<
1789 <GIC_SPI <<
1790 <GIC_SPI <<
1791 interrupt-names = "ms <<
1792 "ms <<
1793 "ms <<
1794 "ms <<
1795 "ms <<
1796 "ms <<
1797 "ms <<
1798 "ms <<
1799 #interrupt-cells = <1 1766 #interrupt-cells = <1>;
1800 interrupt-map-mask = 1767 interrupt-map-mask = <0 0 0 0x7>;
1801 interrupt-map = <0 0 1768 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1802 <0 0 1769 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1803 <0 0 1770 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1804 <0 0 1771 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1805 1772
1806 interconnects = <&pci <<
1807 &mc_ <<
1808 <&gem <<
1809 &con <<
1810 interconnect-names = <<
1811 <<
1812 clocks = <&gcc GCC_PC 1773 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1813 <&gcc GCC_PC 1774 <&gcc GCC_PCIE_0_PIPE_CLK_SRC>,
1814 <&pcie0_phy> !! 1775 <&pcie0_lane>,
1815 <&rpmhcc RPM 1776 <&rpmhcc RPMH_CXO_CLK>,
1816 <&gcc GCC_PC 1777 <&gcc GCC_PCIE_0_AUX_CLK>,
1817 <&gcc GCC_PC 1778 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1818 <&gcc GCC_PC 1779 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1819 <&gcc GCC_PC 1780 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1820 <&gcc GCC_PC 1781 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
1821 <&gcc GCC_DD 1782 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1822 <&gcc GCC_AG 1783 <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
1823 <&gcc GCC_AG 1784 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
1824 clock-names = "pipe", 1785 clock-names = "pipe",
1825 "pipe_m 1786 "pipe_mux",
1826 "phy_pi 1787 "phy_pipe",
1827 "ref", 1788 "ref",
1828 "aux", 1789 "aux",
1829 "cfg", 1790 "cfg",
1830 "bus_ma 1791 "bus_master",
1831 "bus_sl 1792 "bus_slave",
1832 "slave_ 1793 "slave_q2a",
1833 "ddrss_ 1794 "ddrss_sf_tbu",
1834 "aggre0 1795 "aggre0",
1835 "aggre1 1796 "aggre1";
1836 1797
1837 iommu-map = <0x0 &a 1798 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
1838 <0x100 &a 1799 <0x100 &apps_smmu 0x1c01 0x1>;
1839 1800
1840 resets = <&gcc GCC_PC 1801 resets = <&gcc GCC_PCIE_0_BCR>;
1841 reset-names = "pci"; 1802 reset-names = "pci";
1842 1803
1843 power-domains = <&gcc 1804 power-domains = <&gcc PCIE_0_GDSC>;
1844 1805
1845 phys = <&pcie0_phy>; !! 1806 phys = <&pcie0_lane>;
1846 phy-names = "pciephy" 1807 phy-names = "pciephy";
1847 1808
1848 perst-gpios = <&tlmm 1809 perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
1849 wake-gpios = <&tlmm 9 1810 wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
1850 1811
1851 pinctrl-names = "defa 1812 pinctrl-names = "default";
1852 pinctrl-0 = <&pcie0_d 1813 pinctrl-0 = <&pcie0_default_state>;
1853 1814
1854 operating-points-v2 = <<
1855 <<
1856 status = "disabled"; 1815 status = "disabled";
1857 <<
1858 pcie0_opp_table: opp- <<
1859 compatible = <<
1860 <<
1861 /* GEN 1 x1 * <<
1862 opp-2500000 { <<
1863 opp-h <<
1864 requi <<
1865 opp-p <<
1866 }; <<
1867 <<
1868 /* GEN 2 x1 * <<
1869 opp-5000000 { <<
1870 opp-h <<
1871 requi <<
1872 opp-p <<
1873 }; <<
1874 <<
1875 /* GEN 3 x1 * <<
1876 opp-8000000 { <<
1877 opp-h <<
1878 requi <<
1879 opp-p <<
1880 }; <<
1881 }; <<
1882 <<
1883 pcie@0 { <<
1884 device_type = <<
1885 reg = <0x0 0x <<
1886 bus-range = < <<
1887 <<
1888 #address-cell <<
1889 #size-cells = <<
1890 ranges; <<
1891 }; <<
1892 }; 1816 };
1893 1817
1894 pcie0_phy: phy@1c06000 { 1818 pcie0_phy: phy@1c06000 {
1895 compatible = "qcom,sm 1819 compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy";
1896 reg = <0 0x01c06000 0 !! 1820 reg = <0 0x01c06000 0 0x200>;
1897 !! 1821 #address-cells = <2>;
>> 1822 #size-cells = <2>;
>> 1823 ranges;
1898 clocks = <&gcc GCC_PC 1824 clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
1899 <&gcc GCC_PC 1825 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1900 <&gcc GCC_PC 1826 <&gcc GCC_PCIE_0_CLKREF_EN>,
1901 <&gcc GCC_PC !! 1827 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
1902 <&gcc GCC_PC !! 1828 clock-names = "aux", "cfg_ahb", "ref", "refgen";
1903 clock-names = "aux", <<
1904 "cfg_ah <<
1905 "ref", <<
1906 "rchng" <<
1907 "pipe"; <<
1908 <<
1909 clock-output-names = <<
1910 #clock-cells = <0>; <<
1911 <<
1912 #phy-cells = <0>; <<
1913 1829
1914 resets = <&gcc GCC_PC 1830 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1915 reset-names = "phy"; 1831 reset-names = "phy";
1916 1832
1917 assigned-clocks = <&g 1833 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
1918 assigned-clock-rates 1834 assigned-clock-rates = <100000000>;
1919 1835
1920 status = "disabled"; 1836 status = "disabled";
>> 1837
>> 1838 pcie0_lane: phy@1c06200 {
>> 1839 reg = <0 0x01c06e00 0 0x200>, /* tx */
>> 1840 <0 0x01c07000 0 0x200>, /* rx */
>> 1841 <0 0x01c06200 0 0x200>, /* pcs */
>> 1842 <0 0x01c06600 0 0x200>; /* pcs_pcie */
>> 1843 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
>> 1844 clock-names = "pipe0";
>> 1845
>> 1846 #clock-cells = <0>;
>> 1847 #phy-cells = <0>;
>> 1848 clock-output-names = "pcie_0_pipe_clk";
>> 1849 };
1921 }; 1850 };
1922 1851
1923 pcie1: pcie@1c08000 { !! 1852 pcie1: pci@1c08000 {
1924 compatible = "qcom,pc 1853 compatible = "qcom,pcie-sm8450-pcie1";
1925 reg = <0 0x01c08000 0 1854 reg = <0 0x01c08000 0 0x3000>,
1926 <0 0x40000000 0 1855 <0 0x40000000 0 0xf1d>,
1927 <0 0x40000f20 0 1856 <0 0x40000f20 0 0xa8>,
1928 <0 0x40001000 0 1857 <0 0x40001000 0 0x1000>,
1929 <0 0x40100000 0 1858 <0 0x40100000 0 0x100000>;
1930 reg-names = "parf", " 1859 reg-names = "parf", "dbi", "elbi", "atu", "config";
1931 device_type = "pci"; 1860 device_type = "pci";
1932 linux,pci-domain = <1 1861 linux,pci-domain = <1>;
1933 bus-range = <0x00 0xf 1862 bus-range = <0x00 0xff>;
1934 num-lanes = <2>; 1863 num-lanes = <2>;
1935 1864
1936 #address-cells = <3>; 1865 #address-cells = <3>;
1937 #size-cells = <2>; 1866 #size-cells = <2>;
1938 1867
1939 ranges = <0x01000000 1868 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
1940 <0x02000000 1869 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1941 1870
1942 msi-map = <0x0 &gic_i !! 1871 /*
1943 <0x100 &gic !! 1872 * MSIs for BDF (1:0.0) only works with Device ID 0x5a00.
>> 1873 * Hence, the IDs are swapped.
>> 1874 */
>> 1875 msi-map = <0x0 &gic_its 0x5a01 0x1>,
>> 1876 <0x100 &gic_its 0x5a00 0x1>;
1944 msi-map-mask = <0xff0 1877 msi-map-mask = <0xff00>;
1945 interrupts = <GIC_SPI !! 1878 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
1946 <GIC_SPI !! 1879 interrupt-names = "msi";
1947 <GIC_SPI <<
1948 <GIC_SPI <<
1949 <GIC_SPI <<
1950 <GIC_SPI <<
1951 <GIC_SPI <<
1952 <GIC_SPI <<
1953 interrupt-names = "ms <<
1954 "ms <<
1955 "ms <<
1956 "ms <<
1957 "ms <<
1958 "ms <<
1959 "ms <<
1960 "ms <<
1961 #interrupt-cells = <1 1880 #interrupt-cells = <1>;
1962 interrupt-map-mask = 1881 interrupt-map-mask = <0 0 0 0x7>;
1963 interrupt-map = <0 0 1882 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1964 <0 0 1883 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1965 <0 0 1884 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1966 <0 0 1885 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1967 1886
1968 interconnects = <&pci <<
1969 &mc_ <<
1970 <&gem <<
1971 &con <<
1972 interconnect-names = <<
1973 <<
1974 clocks = <&gcc GCC_PC 1887 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1975 <&gcc GCC_PC 1888 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>,
1976 <&pcie1_phy !! 1889 <&pcie1_lane>,
1977 <&rpmhcc RPM 1890 <&rpmhcc RPMH_CXO_CLK>,
1978 <&gcc GCC_PC 1891 <&gcc GCC_PCIE_1_AUX_CLK>,
1979 <&gcc GCC_PC 1892 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1980 <&gcc GCC_PC 1893 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1981 <&gcc GCC_PC 1894 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
1982 <&gcc GCC_PC 1895 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
1983 <&gcc GCC_DD 1896 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1984 <&gcc GCC_AG 1897 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
1985 clock-names = "pipe", 1898 clock-names = "pipe",
1986 "pipe_m 1899 "pipe_mux",
1987 "phy_pi 1900 "phy_pipe",
1988 "ref", 1901 "ref",
1989 "aux", 1902 "aux",
1990 "cfg", 1903 "cfg",
1991 "bus_ma 1904 "bus_master",
1992 "bus_sl 1905 "bus_slave",
1993 "slave_ 1906 "slave_q2a",
1994 "ddrss_ 1907 "ddrss_sf_tbu",
1995 "aggre1 1908 "aggre1";
1996 1909
1997 iommu-map = <0x0 &a 1910 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
1998 <0x100 &a 1911 <0x100 &apps_smmu 0x1c81 0x1>;
1999 1912
2000 resets = <&gcc GCC_PC 1913 resets = <&gcc GCC_PCIE_1_BCR>;
2001 reset-names = "pci"; 1914 reset-names = "pci";
2002 1915
2003 power-domains = <&gcc 1916 power-domains = <&gcc PCIE_1_GDSC>;
2004 1917
2005 phys = <&pcie1_phy>; !! 1918 phys = <&pcie1_lane>;
2006 phy-names = "pciephy" 1919 phy-names = "pciephy";
2007 1920
2008 perst-gpios = <&tlmm 1921 perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
2009 wake-gpios = <&tlmm 9 1922 wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
2010 1923
2011 pinctrl-names = "defa 1924 pinctrl-names = "default";
2012 pinctrl-0 = <&pcie1_d 1925 pinctrl-0 = <&pcie1_default_state>;
2013 1926
2014 operating-points-v2 = <<
2015 <<
2016 status = "disabled"; 1927 status = "disabled";
2017 <<
2018 pcie1_opp_table: opp- <<
2019 compatible = <<
2020 <<
2021 /* GEN 1 x1 * <<
2022 opp-2500000 { <<
2023 opp-h <<
2024 requi <<
2025 opp-p <<
2026 }; <<
2027 <<
2028 /* GEN 1 x2 a <<
2029 opp-5000000 { <<
2030 opp-h <<
2031 requi <<
2032 opp-p <<
2033 }; <<
2034 <<
2035 /* GEN 2 x2 * <<
2036 opp-10000000 <<
2037 opp-h <<
2038 requi <<
2039 opp-p <<
2040 }; <<
2041 <<
2042 /* GEN 3 x1 * <<
2043 opp-8000000 { <<
2044 opp-h <<
2045 requi <<
2046 opp-p <<
2047 }; <<
2048 <<
2049 /* GEN 3 x2 a <<
2050 opp-16000000 <<
2051 opp-h <<
2052 requi <<
2053 opp-p <<
2054 }; <<
2055 <<
2056 /* GEN 4 x2 * <<
2057 opp-32000000 <<
2058 opp-h <<
2059 requi <<
2060 opp-p <<
2061 }; <<
2062 }; <<
2063 <<
2064 pcie@0 { <<
2065 device_type = <<
2066 reg = <0x0 0x <<
2067 bus-range = < <<
2068 <<
2069 #address-cell <<
2070 #size-cells = <<
2071 ranges; <<
2072 }; <<
2073 }; 1928 };
2074 1929
2075 pcie1_phy: phy@1c0e000 { !! 1930 pcie1_phy: phy@1c0f000 {
2076 compatible = "qcom,sm 1931 compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy";
2077 reg = <0 0x01c0e000 0 !! 1932 reg = <0 0x01c0f000 0 0x200>;
2078 !! 1933 #address-cells = <2>;
>> 1934 #size-cells = <2>;
>> 1935 ranges;
2079 clocks = <&gcc GCC_PC 1936 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>,
2080 <&gcc GCC_PC 1937 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2081 <&gcc GCC_PC 1938 <&gcc GCC_PCIE_1_CLKREF_EN>,
2082 <&gcc GCC_PC !! 1939 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
2083 <&gcc GCC_PC !! 1940 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2084 clock-names = "aux", <<
2085 "cfg_ah <<
2086 "ref", <<
2087 "rchng" <<
2088 "pipe"; <<
2089 <<
2090 clock-output-names = <<
2091 #clock-cells = <1>; <<
2092 <<
2093 #phy-cells = <0>; <<
2094 1941
2095 resets = <&gcc GCC_PC 1942 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2096 reset-names = "phy"; 1943 reset-names = "phy";
2097 1944
2098 assigned-clocks = <&g 1945 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
2099 assigned-clock-rates 1946 assigned-clock-rates = <100000000>;
2100 1947
2101 status = "disabled"; 1948 status = "disabled";
>> 1949
>> 1950 pcie1_lane: phy@1c0e000 {
>> 1951 reg = <0 0x01c0e000 0 0x200>, /* tx */
>> 1952 <0 0x01c0e200 0 0x300>, /* rx */
>> 1953 <0 0x01c0f200 0 0x200>, /* pcs */
>> 1954 <0 0x01c0e800 0 0x200>, /* tx */
>> 1955 <0 0x01c0ea00 0 0x300>, /* rx */
>> 1956 <0 0x01c0f400 0 0xc00>; /* pcs_pcie */
>> 1957 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
>> 1958 clock-names = "pipe0";
>> 1959
>> 1960 #clock-cells = <0>;
>> 1961 #phy-cells = <0>;
>> 1962 clock-output-names = "pcie_1_pipe_clk";
>> 1963 };
2102 }; 1964 };
2103 1965
2104 config_noc: interconnect@1500 1966 config_noc: interconnect@1500000 {
2105 compatible = "qcom,sm 1967 compatible = "qcom,sm8450-config-noc";
2106 reg = <0 0x01500000 0 1968 reg = <0 0x01500000 0 0x1c000>;
2107 #interconnect-cells = 1969 #interconnect-cells = <2>;
2108 qcom,bcm-voters = <&a 1970 qcom,bcm-voters = <&apps_bcm_voter>;
2109 }; 1971 };
2110 1972
2111 system_noc: interconnect@1680 1973 system_noc: interconnect@1680000 {
2112 compatible = "qcom,sm 1974 compatible = "qcom,sm8450-system-noc";
2113 reg = <0 0x01680000 0 1975 reg = <0 0x01680000 0 0x1e200>;
2114 #interconnect-cells = 1976 #interconnect-cells = <2>;
2115 qcom,bcm-voters = <&a 1977 qcom,bcm-voters = <&apps_bcm_voter>;
2116 }; 1978 };
2117 1979
2118 pcie_noc: interconnect@16c000 1980 pcie_noc: interconnect@16c0000 {
2119 compatible = "qcom,sm 1981 compatible = "qcom,sm8450-pcie-anoc";
2120 reg = <0 0x016c0000 0 1982 reg = <0 0x016c0000 0 0xe280>;
2121 #interconnect-cells = 1983 #interconnect-cells = <2>;
2122 qcom,bcm-voters = <&a 1984 qcom,bcm-voters = <&apps_bcm_voter>;
2123 }; 1985 };
2124 1986
2125 aggre1_noc: interconnect@16e0 1987 aggre1_noc: interconnect@16e0000 {
2126 compatible = "qcom,sm 1988 compatible = "qcom,sm8450-aggre1-noc";
2127 reg = <0 0x016e0000 0 1989 reg = <0 0x016e0000 0 0x1c080>;
2128 #interconnect-cells = 1990 #interconnect-cells = <2>;
2129 clocks = <&gcc GCC_AG 1991 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2130 <&gcc GCC_AG 1992 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
2131 qcom,bcm-voters = <&a 1993 qcom,bcm-voters = <&apps_bcm_voter>;
2132 }; 1994 };
2133 1995
2134 aggre2_noc: interconnect@1700 1996 aggre2_noc: interconnect@1700000 {
2135 compatible = "qcom,sm 1997 compatible = "qcom,sm8450-aggre2-noc";
2136 reg = <0 0x01700000 0 1998 reg = <0 0x01700000 0 0x31080>;
2137 #interconnect-cells = 1999 #interconnect-cells = <2>;
2138 qcom,bcm-voters = <&a 2000 qcom,bcm-voters = <&apps_bcm_voter>;
2139 clocks = <&gcc GCC_AG 2001 clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
2140 <&gcc GCC_AG 2002 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
2141 <&gcc GCC_AG 2003 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2142 <&rpmhcc RPM 2004 <&rpmhcc RPMH_IPA_CLK>;
2143 }; 2005 };
2144 2006
2145 mmss_noc: interconnect@174000 2007 mmss_noc: interconnect@1740000 {
2146 compatible = "qcom,sm 2008 compatible = "qcom,sm8450-mmss-noc";
2147 reg = <0 0x01740000 0 2009 reg = <0 0x01740000 0 0x1f080>;
2148 #interconnect-cells = 2010 #interconnect-cells = <2>;
2149 qcom,bcm-voters = <&a 2011 qcom,bcm-voters = <&apps_bcm_voter>;
2150 }; 2012 };
2151 2013
2152 tcsr_mutex: hwlock@1f40000 { 2014 tcsr_mutex: hwlock@1f40000 {
2153 compatible = "qcom,tc 2015 compatible = "qcom,tcsr-mutex";
2154 reg = <0x0 0x01f40000 2016 reg = <0x0 0x01f40000 0x0 0x40000>;
2155 #hwlock-cells = <1>; 2017 #hwlock-cells = <1>;
2156 }; 2018 };
2157 2019
2158 tcsr: syscon@1fc0000 { 2020 tcsr: syscon@1fc0000 {
2159 compatible = "qcom,sm 2021 compatible = "qcom,sm8450-tcsr", "syscon";
2160 reg = <0x0 0x1fc0000 2022 reg = <0x0 0x1fc0000 0x0 0x30000>;
2161 }; 2023 };
2162 2024
2163 gpu: gpu@3d00000 { <<
2164 compatible = "qcom,ad <<
2165 reg = <0x0 0x03d00000 <<
2166 <0x0 0x03d9e000 <<
2167 <0x0 0x03d61000 <<
2168 reg-names = "kgsl_3d0 <<
2169 "cx_mem", <<
2170 "cx_dbgc" <<
2171 <<
2172 interrupts = <GIC_SPI <<
2173 <<
2174 iommus = <&adreno_smm <<
2175 <&adreno_smm <<
2176 <<
2177 operating-points-v2 = <<
2178 <<
2179 qcom,gmu = <&gmu>; <<
2180 #cooling-cells = <2>; <<
2181 <<
2182 status = "disabled"; <<
2183 <<
2184 zap-shader { <<
2185 memory-region <<
2186 }; <<
2187 <<
2188 gpu_opp_table: opp-ta <<
2189 compatible = <<
2190 <<
2191 opp-818000000 <<
2192 opp-h <<
2193 opp-l <<
2194 }; <<
2195 <<
2196 opp-791000000 <<
2197 opp-h <<
2198 opp-l <<
2199 }; <<
2200 <<
2201 opp-734000000 <<
2202 opp-h <<
2203 opp-l <<
2204 }; <<
2205 <<
2206 opp-640000000 <<
2207 opp-h <<
2208 opp-l <<
2209 }; <<
2210 <<
2211 opp-599000000 <<
2212 opp-h <<
2213 opp-l <<
2214 }; <<
2215 <<
2216 opp-545000000 <<
2217 opp-h <<
2218 opp-l <<
2219 }; <<
2220 <<
2221 opp-492000000 <<
2222 opp-h <<
2223 opp-l <<
2224 }; <<
2225 <<
2226 opp-421000000 <<
2227 opp-h <<
2228 opp-l <<
2229 }; <<
2230 <<
2231 opp-350000000 <<
2232 opp-h <<
2233 opp-l <<
2234 }; <<
2235 <<
2236 opp-317000000 <<
2237 opp-h <<
2238 opp-l <<
2239 }; <<
2240 <<
2241 opp-285000000 <<
2242 opp-h <<
2243 opp-l <<
2244 }; <<
2245 <<
2246 opp-220000000 <<
2247 opp-h <<
2248 opp-l <<
2249 }; <<
2250 }; <<
2251 }; <<
2252 <<
2253 gmu: gmu@3d6a000 { <<
2254 compatible = "qcom,ad <<
2255 reg = <0x0 0x03d6a000 <<
2256 <0x0 0x03d50000 <<
2257 <0x0 0x0b290000 <<
2258 reg-names = "gmu", "r <<
2259 <<
2260 interrupts = <GIC_SPI <<
2261 <GIC_SPI <<
2262 interrupt-names = "hf <<
2263 <<
2264 clocks = <&gpucc GPU_ <<
2265 <&gpucc GPU_ <<
2266 <&gpucc GPU_ <<
2267 <&gcc GCC_DD <<
2268 <&gcc GCC_GP <<
2269 <&gpucc GPU_ <<
2270 <&gpucc GPU_ <<
2271 clock-names = "ahb", <<
2272 "gmu", <<
2273 "cxo", <<
2274 "axi", <<
2275 "memnoc <<
2276 "hub", <<
2277 "demet" <<
2278 <<
2279 power-domains = <&gpu <<
2280 <&gpu <<
2281 power-domain-names = <<
2282 <<
2283 <<
2284 iommus = <&adreno_smm <<
2285 <<
2286 qcom,qmp = <&aoss_qmp <<
2287 <<
2288 operating-points-v2 = <<
2289 <<
2290 gmu_opp_table: opp-ta <<
2291 compatible = <<
2292 <<
2293 opp-500000000 <<
2294 opp-h <<
2295 opp-l <<
2296 }; <<
2297 <<
2298 opp-200000000 <<
2299 opp-h <<
2300 opp-l <<
2301 }; <<
2302 }; <<
2303 }; <<
2304 <<
2305 gpucc: clock-controller@3d900 <<
2306 compatible = "qcom,sm <<
2307 reg = <0x0 0x03d90000 <<
2308 clocks = <&rpmhcc RPM <<
2309 <&gcc GCC_GP <<
2310 <&gcc GCC_GP <<
2311 #clock-cells = <1>; <<
2312 #reset-cells = <1>; <<
2313 #power-domain-cells = <<
2314 }; <<
2315 <<
2316 adreno_smmu: iommu@3da0000 { <<
2317 compatible = "qcom,sm <<
2318 "qcom,sm <<
2319 reg = <0x0 0x03da0000 <<
2320 #iommu-cells = <2>; <<
2321 #global-interrupts = <<
2322 interrupts = <GIC_SPI <<
2323 <GIC_SPI <<
2324 <GIC_SPI <<
2325 <GIC_SPI <<
2326 <GIC_SPI <<
2327 <GIC_SPI <<
2328 <GIC_SPI <<
2329 <GIC_SPI <<
2330 <GIC_SPI <<
2331 <GIC_SPI <<
2332 <GIC_SPI <<
2333 <GIC_SPI <<
2334 <GIC_SPI <<
2335 <GIC_SPI <<
2336 <GIC_SPI <<
2337 <GIC_SPI <<
2338 <GIC_SPI <<
2339 <GIC_SPI <<
2340 <GIC_SPI <<
2341 <GIC_SPI <<
2342 <GIC_SPI <<
2343 <GIC_SPI <<
2344 <GIC_SPI <<
2345 <GIC_SPI <<
2346 <GIC_SPI <<
2347 <GIC_SPI <<
2348 clocks = <&gpucc GPU_ <<
2349 <&gpucc GPU_ <<
2350 <&gpucc GPU_ <<
2351 <&gcc GCC_GP <<
2352 <&gcc GCC_GP <<
2353 <&gpucc GPU_ <<
2354 clock-names = "gmu", <<
2355 "hub", <<
2356 "hlos", <<
2357 "bus", <<
2358 "iface" <<
2359 "ahb"; <<
2360 power-domains = <&gpu <<
2361 dma-coherent; <<
2362 }; <<
2363 <<
2364 usb_1_hsphy: phy@88e3000 { 2025 usb_1_hsphy: phy@88e3000 {
2365 compatible = "qcom,sm 2026 compatible = "qcom,sm8450-usb-hs-phy",
2366 "qcom,us 2027 "qcom,usb-snps-hs-7nm-phy";
2367 reg = <0 0x088e3000 0 2028 reg = <0 0x088e3000 0 0x400>;
2368 status = "disabled"; 2029 status = "disabled";
2369 #phy-cells = <0>; 2030 #phy-cells = <0>;
2370 2031
2371 clocks = <&rpmhcc RPM 2032 clocks = <&rpmhcc RPMH_CXO_CLK>;
2372 clock-names = "ref"; 2033 clock-names = "ref";
2373 2034
2374 resets = <&gcc GCC_QU 2035 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2375 }; 2036 };
2376 2037
2377 usb_1_qmpphy: phy@88e8000 { 2038 usb_1_qmpphy: phy@88e8000 {
2378 compatible = "qcom,sm 2039 compatible = "qcom,sm8450-qmp-usb3-dp-phy";
2379 reg = <0 0x088e8000 0 2040 reg = <0 0x088e8000 0 0x3000>;
2380 2041
2381 clocks = <&gcc GCC_US 2042 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2382 <&rpmhcc RPM 2043 <&rpmhcc RPMH_CXO_CLK>,
2383 <&gcc GCC_US 2044 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
2384 <&gcc GCC_US 2045 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2385 clock-names = "aux", 2046 clock-names = "aux", "ref", "com_aux", "usb3_pipe";
2386 2047
2387 resets = <&gcc GCC_US 2048 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
2388 <&gcc GCC_US 2049 <&gcc GCC_USB3_PHY_PRIM_BCR>;
2389 reset-names = "phy", 2050 reset-names = "phy", "common";
2390 2051
2391 #clock-cells = <1>; 2052 #clock-cells = <1>;
2392 #phy-cells = <1>; 2053 #phy-cells = <1>;
2393 2054
2394 orientation-switch; <<
2395 <<
2396 status = "disabled"; 2055 status = "disabled";
2397 <<
2398 ports { <<
2399 #address-cell <<
2400 #size-cells = <<
2401 <<
2402 port@0 { <<
2403 reg = <<
2404 <<
2405 usb_1 <<
2406 }; <<
2407 }; <<
2408 <<
2409 port@1 { <<
2410 reg = <<
2411 <<
2412 usb_1 <<
2413 <<
2414 }; <<
2415 }; <<
2416 <<
2417 port@2 { <<
2418 reg = <<
2419 <<
2420 usb_1 <<
2421 <<
2422 }; <<
2423 }; <<
2424 }; <<
2425 }; 2056 };
2426 2057
2427 remoteproc_slpi: remoteproc@2 2058 remoteproc_slpi: remoteproc@2400000 {
2428 compatible = "qcom,sm 2059 compatible = "qcom,sm8450-slpi-pas";
2429 reg = <0 0x02400000 0 2060 reg = <0 0x02400000 0 0x4000>;
2430 2061
2431 interrupts-extended = 2062 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>,
2432 2063 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
2433 2064 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
2434 2065 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
2435 2066 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
2436 interrupt-names = "wd 2067 interrupt-names = "wdog", "fatal", "ready",
2437 "ha 2068 "handover", "stop-ack";
2438 2069
2439 clocks = <&rpmhcc RPM 2070 clocks = <&rpmhcc RPMH_CXO_CLK>;
2440 clock-names = "xo"; 2071 clock-names = "xo";
2441 2072
2442 power-domains = <&rpm !! 2073 power-domains = <&rpmhpd SM8450_LCX>,
2443 <&rpm !! 2074 <&rpmhpd SM8450_LMX>;
2444 power-domain-names = 2075 power-domain-names = "lcx", "lmx";
2445 2076
2446 memory-region = <&slp 2077 memory-region = <&slpi_mem>;
2447 2078
2448 qcom,qmp = <&aoss_qmp 2079 qcom,qmp = <&aoss_qmp>;
2449 2080
2450 qcom,smem-states = <& 2081 qcom,smem-states = <&smp2p_slpi_out 0>;
2451 qcom,smem-state-names 2082 qcom,smem-state-names = "stop";
2452 2083
2453 status = "disabled"; 2084 status = "disabled";
2454 2085
2455 glink-edge { 2086 glink-edge {
2456 interrupts-ex 2087 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
2457 2088 IPCC_MPROC_SIGNAL_GLINK_QMP
2458 2089 IRQ_TYPE_EDGE_RISING>;
2459 mboxes = <&ip 2090 mboxes = <&ipcc IPCC_CLIENT_SLPI
2460 2091 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2461 2092
2462 label = "slpi 2093 label = "slpi";
2463 qcom,remote-p 2094 qcom,remote-pid = <3>;
2464 2095
2465 fastrpc { 2096 fastrpc {
2466 compa 2097 compatible = "qcom,fastrpc";
2467 qcom, 2098 qcom,glink-channels = "fastrpcglink-apps-dsp";
2468 label 2099 label = "sdsp";
2469 qcom, <<
2470 #addr 2100 #address-cells = <1>;
2471 #size 2101 #size-cells = <0>;
2472 2102
2473 compu 2103 compute-cb@1 {
2474 2104 compatible = "qcom,fastrpc-compute-cb";
2475 2105 reg = <1>;
2476 2106 iommus = <&apps_smmu 0x0541 0x0>;
2477 }; 2107 };
2478 2108
2479 compu 2109 compute-cb@2 {
2480 2110 compatible = "qcom,fastrpc-compute-cb";
2481 2111 reg = <2>;
2482 2112 iommus = <&apps_smmu 0x0542 0x0>;
2483 }; 2113 };
2484 2114
2485 compu 2115 compute-cb@3 {
2486 2116 compatible = "qcom,fastrpc-compute-cb";
2487 2117 reg = <3>;
2488 2118 iommus = <&apps_smmu 0x0543 0x0>;
2489 2119 /* note: shared-cb = <4> in downstream */
2490 }; 2120 };
2491 }; 2121 };
2492 }; 2122 };
2493 }; 2123 };
2494 2124
2495 wsa2macro: codec@31e0000 { 2125 wsa2macro: codec@31e0000 {
2496 compatible = "qcom,sm 2126 compatible = "qcom,sm8450-lpass-wsa-macro";
2497 reg = <0 0x031e0000 0 2127 reg = <0 0x031e0000 0 0x1000>;
2498 clocks = <&q6prmcc LP 2128 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2499 <&q6prmcc LP 2129 <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2500 <&q6prmcc LP 2130 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2501 <&q6prmcc LP 2131 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2502 <&vamacro>; 2132 <&vamacro>;
2503 clock-names = "mclk", 2133 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
>> 2134 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 2135 <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
>> 2136 assigned-clock-rates = <19200000>, <19200000>;
2504 2137
2505 #clock-cells = <0>; 2138 #clock-cells = <0>;
2506 clock-output-names = 2139 clock-output-names = "wsa2-mclk";
>> 2140 pinctrl-names = "default";
>> 2141 pinctrl-0 = <&wsa2_swr_active>;
2507 #sound-dai-cells = <1 2142 #sound-dai-cells = <1>;
2508 }; 2143 };
2509 2144
2510 swr4: soundwire@31f0000 { !! 2145 swr4: soundwire-controller@31f0000 {
2511 compatible = "qcom,so 2146 compatible = "qcom,soundwire-v1.7.0";
2512 reg = <0 0x031f0000 0 2147 reg = <0 0x031f0000 0 0x2000>;
2513 interrupts = <GIC_SPI 2148 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
2514 clocks = <&wsa2macro> 2149 clocks = <&wsa2macro>;
2515 clock-names = "iface" 2150 clock-names = "iface";
2516 label = "WSA2"; 2151 label = "WSA2";
2517 2152
2518 pinctrl-0 = <&wsa2_sw <<
2519 pinctrl-names = "defa <<
2520 <<
2521 qcom,din-ports = <2>; 2153 qcom,din-ports = <2>;
2522 qcom,dout-ports = <6> 2154 qcom,dout-ports = <6>;
2523 2155
2524 qcom,ports-sinterval- 2156 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2525 qcom,ports-offset1 = 2157 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2526 qcom,ports-offset2 = 2158 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2527 qcom,ports-hstart = 2159 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2528 qcom,ports-hstop = 2160 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2529 qcom,ports-word-lengt 2161 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2530 qcom,ports-block-pack 2162 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
2531 qcom,ports-block-grou 2163 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2532 qcom,ports-lane-contr 2164 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2533 2165
2534 #address-cells = <2>; 2166 #address-cells = <2>;
2535 #size-cells = <0>; 2167 #size-cells = <0>;
2536 #sound-dai-cells = <1 2168 #sound-dai-cells = <1>;
2537 status = "disabled"; 2169 status = "disabled";
2538 }; 2170 };
2539 2171
2540 rxmacro: codec@3200000 { 2172 rxmacro: codec@3200000 {
2541 compatible = "qcom,sm 2173 compatible = "qcom,sm8450-lpass-rx-macro";
2542 reg = <0 0x03200000 0 2174 reg = <0 0x03200000 0 0x1000>;
2543 clocks = <&q6prmcc LP 2175 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2544 <&q6prmcc LP 2176 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2545 <&q6prmcc LP 2177 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2546 <&q6prmcc LP 2178 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2547 <&vamacro>; 2179 <&vamacro>;
2548 clock-names = "mclk", 2180 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2549 2181
>> 2182 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 2183 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
>> 2184 assigned-clock-rates = <19200000>, <19200000>;
>> 2185
2550 #clock-cells = <0>; 2186 #clock-cells = <0>;
2551 clock-output-names = 2187 clock-output-names = "mclk";
>> 2188 pinctrl-names = "default";
>> 2189 pinctrl-0 = <&rx_swr_active>;
2552 #sound-dai-cells = <1 2190 #sound-dai-cells = <1>;
2553 }; 2191 };
2554 2192
2555 swr1: soundwire@3210000 { !! 2193 swr1: soundwire-controller@3210000 {
2556 compatible = "qcom,so 2194 compatible = "qcom,soundwire-v1.7.0";
2557 reg = <0 0x03210000 0 2195 reg = <0 0x03210000 0 0x2000>;
2558 interrupts = <GIC_SPI 2196 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
2559 clocks = <&rxmacro>; 2197 clocks = <&rxmacro>;
2560 clock-names = "iface" 2198 clock-names = "iface";
2561 label = "RX"; 2199 label = "RX";
2562 qcom,din-ports = <0>; 2200 qcom,din-ports = <0>;
2563 qcom,dout-ports = <5> 2201 qcom,dout-ports = <5>;
2564 2202
2565 pinctrl-0 = <&rx_swr_ <<
2566 pinctrl-names = "defa <<
2567 <<
2568 qcom,ports-sinterval- 2203 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
2569 qcom,ports-offset1 = 2204 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>;
2570 qcom,ports-offset2 = 2205 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
2571 qcom,ports-hstart = 2206 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
2572 qcom,ports-hstop = 2207 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
2573 qcom,ports-word-lengt 2208 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2574 qcom,ports-block-pack 2209 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
2575 qcom,ports-block-grou 2210 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
2576 qcom,ports-lane-contr 2211 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2577 2212
2578 #address-cells = <2>; 2213 #address-cells = <2>;
2579 #size-cells = <0>; 2214 #size-cells = <0>;
2580 #sound-dai-cells = <1 2215 #sound-dai-cells = <1>;
2581 status = "disabled"; 2216 status = "disabled";
2582 }; 2217 };
2583 2218
2584 txmacro: codec@3220000 { 2219 txmacro: codec@3220000 {
2585 compatible = "qcom,sm 2220 compatible = "qcom,sm8450-lpass-tx-macro";
2586 reg = <0 0x03220000 0 2221 reg = <0 0x03220000 0 0x1000>;
2587 clocks = <&q6prmcc LP 2222 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2588 <&q6prmcc LP 2223 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2589 <&q6prmcc LP 2224 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2590 <&q6prmcc LP 2225 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2591 <&vamacro>; 2226 <&vamacro>;
2592 clock-names = "mclk", 2227 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
>> 2228 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 2229 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
>> 2230 assigned-clock-rates = <19200000>, <19200000>;
2593 2231
2594 #clock-cells = <0>; 2232 #clock-cells = <0>;
2595 clock-output-names = 2233 clock-output-names = "mclk";
>> 2234 pinctrl-names = "default";
>> 2235 pinctrl-0 = <&tx_swr_active>;
2596 #sound-dai-cells = <1 2236 #sound-dai-cells = <1>;
2597 }; 2237 };
2598 2238
2599 wsamacro: codec@3240000 { 2239 wsamacro: codec@3240000 {
2600 compatible = "qcom,sm 2240 compatible = "qcom,sm8450-lpass-wsa-macro";
2601 reg = <0 0x03240000 0 2241 reg = <0 0x03240000 0 0x1000>;
2602 clocks = <&q6prmcc LP 2242 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2603 <&q6prmcc LP 2243 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2604 <&q6prmcc LP 2244 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2605 <&q6prmcc LP 2245 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2606 <&vamacro>; 2246 <&vamacro>;
2607 clock-names = "mclk", 2247 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2608 2248
>> 2249 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 2250 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
>> 2251 assigned-clock-rates = <19200000>, <19200000>;
>> 2252
2609 #clock-cells = <0>; 2253 #clock-cells = <0>;
2610 clock-output-names = 2254 clock-output-names = "mclk";
>> 2255 pinctrl-names = "default";
>> 2256 pinctrl-0 = <&wsa_swr_active>;
2611 #sound-dai-cells = <1 2257 #sound-dai-cells = <1>;
2612 }; 2258 };
2613 2259
2614 swr0: soundwire@3250000 { !! 2260 swr0: soundwire-controller@3250000 {
2615 compatible = "qcom,so 2261 compatible = "qcom,soundwire-v1.7.0";
2616 reg = <0 0x03250000 0 2262 reg = <0 0x03250000 0 0x2000>;
2617 interrupts = <GIC_SPI 2263 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
2618 clocks = <&wsamacro>; 2264 clocks = <&wsamacro>;
2619 clock-names = "iface" 2265 clock-names = "iface";
2620 label = "WSA"; 2266 label = "WSA";
2621 2267
2622 pinctrl-0 = <&wsa_swr <<
2623 pinctrl-names = "defa <<
2624 <<
2625 qcom,din-ports = <2>; 2268 qcom,din-ports = <2>;
2626 qcom,dout-ports = <6> 2269 qcom,dout-ports = <6>;
2627 2270
2628 qcom,ports-sinterval- 2271 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2629 qcom,ports-offset1 = 2272 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2630 qcom,ports-offset2 = 2273 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2631 qcom,ports-hstart = 2274 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2632 qcom,ports-hstop = 2275 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2633 qcom,ports-word-lengt 2276 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2634 qcom,ports-block-pack 2277 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
2635 qcom,ports-block-grou 2278 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2636 qcom,ports-lane-contr 2279 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2637 2280
2638 #address-cells = <2>; 2281 #address-cells = <2>;
2639 #size-cells = <0>; 2282 #size-cells = <0>;
2640 #sound-dai-cells = <1 2283 #sound-dai-cells = <1>;
2641 status = "disabled"; 2284 status = "disabled";
2642 }; 2285 };
2643 2286
2644 swr2: soundwire@33b0000 { !! 2287 swr2: soundwire-controller@33b0000 {
2645 compatible = "qcom,so 2288 compatible = "qcom,soundwire-v1.7.0";
2646 reg = <0 0x033b0000 0 2289 reg = <0 0x033b0000 0 0x2000>;
2647 interrupts = <GIC_SPI 2290 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
2648 <GIC_SPI 2291 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>;
2649 interrupt-names = "co 2292 interrupt-names = "core", "wakeup";
2650 2293
2651 clocks = <&txmacro>; !! 2294 clocks = <&vamacro>;
2652 clock-names = "iface" 2295 clock-names = "iface";
2653 label = "TX"; 2296 label = "TX";
2654 2297
2655 pinctrl-0 = <&tx_swr_ <<
2656 pinctrl-names = "defa <<
2657 <<
2658 qcom,din-ports = <4>; 2298 qcom,din-ports = <4>;
2659 qcom,dout-ports = <0> 2299 qcom,dout-ports = <0>;
2660 qcom,ports-sinterval- 2300 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
2661 qcom,ports-offset1 = 2301 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>;
2662 qcom,ports-offset2 = 2302 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
2663 qcom,ports-hstart = 2303 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
2664 qcom,ports-hstop = 2304 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
2665 qcom,ports-word-lengt 2305 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
2666 qcom,ports-block-pack 2306 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
2667 qcom,ports-block-grou 2307 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
2668 qcom,ports-lane-contr 2308 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>;
2669 2309
2670 #address-cells = <2>; 2310 #address-cells = <2>;
2671 #size-cells = <0>; 2311 #size-cells = <0>;
2672 #sound-dai-cells = <1 2312 #sound-dai-cells = <1>;
2673 status = "disabled"; 2313 status = "disabled";
2674 }; 2314 };
2675 2315
2676 vamacro: codec@33f0000 { 2316 vamacro: codec@33f0000 {
2677 compatible = "qcom,sm 2317 compatible = "qcom,sm8450-lpass-va-macro";
2678 reg = <0 0x033f0000 0 2318 reg = <0 0x033f0000 0 0x1000>;
2679 clocks = <&q6prmcc LP 2319 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2680 <&q6prmcc LP 2320 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2681 <&q6prmcc LP 2321 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2682 <&q6prmcc LP 2322 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2683 clock-names = "mclk", 2323 clock-names = "mclk", "macro", "dcodec", "npl";
>> 2324 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
>> 2325 assigned-clock-rates = <19200000>;
2684 2326
2685 #clock-cells = <0>; 2327 #clock-cells = <0>;
2686 clock-output-names = 2328 clock-output-names = "fsgen";
2687 #sound-dai-cells = <1 2329 #sound-dai-cells = <1>;
2688 status = "disabled"; 2330 status = "disabled";
2689 }; 2331 };
2690 2332
2691 remoteproc_adsp: remoteproc@3 2333 remoteproc_adsp: remoteproc@30000000 {
2692 compatible = "qcom,sm 2334 compatible = "qcom,sm8450-adsp-pas";
2693 reg = <0 0x30000000 0 2335 reg = <0 0x30000000 0 0x100>;
2694 2336
2695 interrupts-extended = 2337 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
2696 2338 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
2697 2339 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
2698 2340 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
2699 2341 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
2700 interrupt-names = "wd 2342 interrupt-names = "wdog", "fatal", "ready",
2701 "ha 2343 "handover", "stop-ack";
2702 2344
2703 clocks = <&rpmhcc RPM 2345 clocks = <&rpmhcc RPMH_CXO_CLK>;
2704 clock-names = "xo"; 2346 clock-names = "xo";
2705 2347
2706 power-domains = <&rpm !! 2348 power-domains = <&rpmhpd SM8450_LCX>,
2707 <&rpm !! 2349 <&rpmhpd SM8450_LMX>;
2708 power-domain-names = 2350 power-domain-names = "lcx", "lmx";
2709 2351
2710 memory-region = <&ads 2352 memory-region = <&adsp_mem>;
2711 2353
2712 qcom,qmp = <&aoss_qmp 2354 qcom,qmp = <&aoss_qmp>;
2713 2355
2714 qcom,smem-states = <& 2356 qcom,smem-states = <&smp2p_adsp_out 0>;
2715 qcom,smem-state-names 2357 qcom,smem-state-names = "stop";
2716 2358
2717 status = "disabled"; 2359 status = "disabled";
2718 2360
2719 remoteproc_adsp_glink 2361 remoteproc_adsp_glink: glink-edge {
2720 interrupts-ex 2362 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
2721 2363 IPCC_MPROC_SIGNAL_GLINK_QMP
2722 2364 IRQ_TYPE_EDGE_RISING>;
2723 mboxes = <&ip 2365 mboxes = <&ipcc IPCC_CLIENT_LPASS
2724 2366 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2725 2367
2726 label = "lpas 2368 label = "lpass";
2727 qcom,remote-p 2369 qcom,remote-pid = <2>;
2728 2370
2729 gpr { 2371 gpr {
2730 compa 2372 compatible = "qcom,gpr";
2731 qcom, 2373 qcom,glink-channels = "adsp_apps";
2732 qcom, 2374 qcom,domain = <GPR_DOMAIN_ID_ADSP>;
2733 qcom, 2375 qcom,intents = <512 20>;
2734 #addr 2376 #address-cells = <1>;
2735 #size 2377 #size-cells = <0>;
2736 2378
2737 q6apm 2379 q6apm: service@1 {
2738 2380 compatible = "qcom,q6apm";
2739 2381 reg = <GPR_APM_MODULE_IID>;
2740 2382 #sound-dai-cells = <0>;
2741 2383 qcom,protection-domain = "avs/audio",
2742 2384 "msm/adsp/audio_pd";
2743 2385
2744 2386 q6apmdai: dais {
2745 2387 compatible = "qcom,q6apm-dais";
2746 2388 iommus = <&apps_smmu 0x1801 0x0>;
2747 2389 };
2748 2390
2749 2391 q6apmbedai: bedais {
2750 2392 compatible = "qcom,q6apm-lpass-dais";
2751 2393 #sound-dai-cells = <1>;
2752 2394 };
2753 }; 2395 };
2754 2396
2755 q6prm 2397 q6prm: service@2 {
2756 2398 compatible = "qcom,q6prm";
2757 2399 reg = <GPR_PRM_MODULE_IID>;
2758 2400 qcom,protection-domain = "avs/audio",
2759 2401 "msm/adsp/audio_pd";
2760 2402
2761 2403 q6prmcc: clock-controller {
2762 2404 compatible = "qcom,q6prm-lpass-clocks";
2763 2405 #clock-cells = <2>;
2764 2406 };
2765 }; 2407 };
2766 }; 2408 };
2767 2409
2768 fastrpc { 2410 fastrpc {
2769 compa 2411 compatible = "qcom,fastrpc";
2770 qcom, 2412 qcom,glink-channels = "fastrpcglink-apps-dsp";
2771 label 2413 label = "adsp";
2772 qcom, <<
2773 #addr 2414 #address-cells = <1>;
2774 #size 2415 #size-cells = <0>;
2775 2416
2776 compu 2417 compute-cb@3 {
2777 2418 compatible = "qcom,fastrpc-compute-cb";
2778 2419 reg = <3>;
2779 2420 iommus = <&apps_smmu 0x1803 0x0>;
2780 }; 2421 };
2781 2422
2782 compu 2423 compute-cb@4 {
2783 2424 compatible = "qcom,fastrpc-compute-cb";
2784 2425 reg = <4>;
2785 2426 iommus = <&apps_smmu 0x1804 0x0>;
2786 }; 2427 };
2787 2428
2788 compu 2429 compute-cb@5 {
2789 2430 compatible = "qcom,fastrpc-compute-cb";
2790 2431 reg = <5>;
2791 2432 iommus = <&apps_smmu 0x1805 0x0>;
2792 }; 2433 };
2793 }; 2434 };
2794 }; 2435 };
2795 }; 2436 };
2796 2437
2797 remoteproc_cdsp: remoteproc@3 2438 remoteproc_cdsp: remoteproc@32300000 {
2798 compatible = "qcom,sm 2439 compatible = "qcom,sm8450-cdsp-pas";
2799 reg = <0 0x32300000 0 2440 reg = <0 0x32300000 0 0x1400000>;
2800 2441
2801 interrupts-extended = 2442 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
2802 2443 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
2803 2444 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
2804 2445 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
2805 2446 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
2806 interrupt-names = "wd 2447 interrupt-names = "wdog", "fatal", "ready",
2807 "ha 2448 "handover", "stop-ack";
2808 2449
2809 clocks = <&rpmhcc RPM 2450 clocks = <&rpmhcc RPMH_CXO_CLK>;
2810 clock-names = "xo"; 2451 clock-names = "xo";
2811 2452
2812 power-domains = <&rpm !! 2453 power-domains = <&rpmhpd SM8450_CX>,
2813 <&rpm !! 2454 <&rpmhpd SM8450_MXC>;
2814 power-domain-names = 2455 power-domain-names = "cx", "mxc";
2815 2456
2816 memory-region = <&cds 2457 memory-region = <&cdsp_mem>;
2817 2458
2818 qcom,qmp = <&aoss_qmp 2459 qcom,qmp = <&aoss_qmp>;
2819 2460
2820 qcom,smem-states = <& 2461 qcom,smem-states = <&smp2p_cdsp_out 0>;
2821 qcom,smem-state-names 2462 qcom,smem-state-names = "stop";
2822 2463
2823 status = "disabled"; 2464 status = "disabled";
2824 2465
2825 glink-edge { 2466 glink-edge {
2826 interrupts-ex 2467 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
2827 2468 IPCC_MPROC_SIGNAL_GLINK_QMP
2828 2469 IRQ_TYPE_EDGE_RISING>;
2829 mboxes = <&ip 2470 mboxes = <&ipcc IPCC_CLIENT_CDSP
2830 2471 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2831 2472
2832 label = "cdsp 2473 label = "cdsp";
2833 qcom,remote-p 2474 qcom,remote-pid = <5>;
2834 2475
2835 fastrpc { 2476 fastrpc {
2836 compa 2477 compatible = "qcom,fastrpc";
2837 qcom, 2478 qcom,glink-channels = "fastrpcglink-apps-dsp";
2838 label 2479 label = "cdsp";
2839 qcom, <<
2840 #addr 2480 #address-cells = <1>;
2841 #size 2481 #size-cells = <0>;
2842 2482
2843 compu 2483 compute-cb@1 {
2844 2484 compatible = "qcom,fastrpc-compute-cb";
2845 2485 reg = <1>;
2846 2486 iommus = <&apps_smmu 0x2161 0x0400>,
2847 2487 <&apps_smmu 0x1021 0x1420>;
2848 }; 2488 };
2849 2489
2850 compu 2490 compute-cb@2 {
2851 2491 compatible = "qcom,fastrpc-compute-cb";
2852 2492 reg = <2>;
2853 2493 iommus = <&apps_smmu 0x2162 0x0400>,
2854 2494 <&apps_smmu 0x1022 0x1420>;
2855 }; 2495 };
2856 2496
2857 compu 2497 compute-cb@3 {
2858 2498 compatible = "qcom,fastrpc-compute-cb";
2859 2499 reg = <3>;
2860 2500 iommus = <&apps_smmu 0x2163 0x0400>,
2861 2501 <&apps_smmu 0x1023 0x1420>;
2862 }; 2502 };
2863 2503
2864 compu 2504 compute-cb@4 {
2865 2505 compatible = "qcom,fastrpc-compute-cb";
2866 2506 reg = <4>;
2867 2507 iommus = <&apps_smmu 0x2164 0x0400>,
2868 2508 <&apps_smmu 0x1024 0x1420>;
2869 }; 2509 };
2870 2510
2871 compu 2511 compute-cb@5 {
2872 2512 compatible = "qcom,fastrpc-compute-cb";
2873 2513 reg = <5>;
2874 2514 iommus = <&apps_smmu 0x2165 0x0400>,
2875 2515 <&apps_smmu 0x1025 0x1420>;
2876 }; 2516 };
2877 2517
2878 compu 2518 compute-cb@6 {
2879 2519 compatible = "qcom,fastrpc-compute-cb";
2880 2520 reg = <6>;
2881 2521 iommus = <&apps_smmu 0x2166 0x0400>,
2882 2522 <&apps_smmu 0x1026 0x1420>;
2883 }; 2523 };
2884 2524
2885 compu 2525 compute-cb@7 {
2886 2526 compatible = "qcom,fastrpc-compute-cb";
2887 2527 reg = <7>;
2888 2528 iommus = <&apps_smmu 0x2167 0x0400>,
2889 2529 <&apps_smmu 0x1027 0x1420>;
2890 }; 2530 };
2891 2531
2892 compu 2532 compute-cb@8 {
2893 2533 compatible = "qcom,fastrpc-compute-cb";
2894 2534 reg = <8>;
2895 2535 iommus = <&apps_smmu 0x2168 0x0400>,
2896 2536 <&apps_smmu 0x1028 0x1420>;
2897 }; 2537 };
2898 2538
2899 /* no 2539 /* note: secure cb9 in downstream */
2900 }; 2540 };
2901 }; 2541 };
2902 }; 2542 };
2903 2543
2904 remoteproc_mpss: remoteproc@4 2544 remoteproc_mpss: remoteproc@4080000 {
2905 compatible = "qcom,sm 2545 compatible = "qcom,sm8450-mpss-pas";
2906 reg = <0x0 0x04080000 2546 reg = <0x0 0x04080000 0x0 0x4040>;
2907 2547
2908 interrupts-extended = 2548 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
2909 2549 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
2910 2550 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
2911 2551 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
2912 2552 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>,
2913 2553 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>;
2914 interrupt-names = "wd 2554 interrupt-names = "wdog", "fatal", "ready", "handover",
2915 "st 2555 "stop-ack", "shutdown-ack";
2916 2556
2917 clocks = <&rpmhcc RPM 2557 clocks = <&rpmhcc RPMH_CXO_CLK>;
2918 clock-names = "xo"; 2558 clock-names = "xo";
2919 2559
2920 power-domains = <&rpm !! 2560 power-domains = <&rpmhpd SM8450_CX>,
2921 <&rpm !! 2561 <&rpmhpd SM8450_MSS>;
2922 power-domain-names = 2562 power-domain-names = "cx", "mss";
2923 2563
2924 memory-region = <&mps 2564 memory-region = <&mpss_mem>;
2925 2565
2926 qcom,qmp = <&aoss_qmp 2566 qcom,qmp = <&aoss_qmp>;
2927 2567
2928 qcom,smem-states = <& 2568 qcom,smem-states = <&smp2p_modem_out 0>;
2929 qcom,smem-state-names 2569 qcom,smem-state-names = "stop";
2930 2570
2931 status = "disabled"; 2571 status = "disabled";
2932 2572
2933 glink-edge { 2573 glink-edge {
2934 interrupts-ex 2574 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
2935 2575 IPCC_MPROC_SIGNAL_GLINK_QMP
2936 2576 IRQ_TYPE_EDGE_RISING>;
2937 mboxes = <&ip 2577 mboxes = <&ipcc IPCC_CLIENT_MPSS
2938 2578 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2939 label = "mode 2579 label = "modem";
2940 qcom,remote-p 2580 qcom,remote-pid = <1>;
2941 }; 2581 };
2942 }; 2582 };
2943 2583
2944 videocc: clock-controller@aaf <<
2945 compatible = "qcom,sm <<
2946 reg = <0 0x0aaf0000 0 <<
2947 clocks = <&rpmhcc RPM <<
2948 <&gcc GCC_VI <<
2949 power-domains = <&rpm <<
2950 required-opps = <&rpm <<
2951 #clock-cells = <1>; <<
2952 #reset-cells = <1>; <<
2953 #power-domain-cells = <<
2954 }; <<
2955 <<
2956 cci0: cci@ac15000 { 2584 cci0: cci@ac15000 {
2957 compatible = "qcom,sm 2585 compatible = "qcom,sm8450-cci", "qcom,msm8996-cci";
2958 reg = <0 0x0ac15000 0 2586 reg = <0 0x0ac15000 0 0x1000>;
2959 interrupts = <GIC_SPI 2587 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
2960 power-domains = <&cam 2588 power-domains = <&camcc TITAN_TOP_GDSC>;
2961 2589
2962 clocks = <&camcc CAM_ 2590 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
2963 <&camcc CAM_ 2591 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
2964 <&camcc CAM_ 2592 <&camcc CAM_CC_CPAS_AHB_CLK>,
2965 <&camcc CAM_ 2593 <&camcc CAM_CC_CCI_0_CLK>,
2966 <&camcc CAM_ 2594 <&camcc CAM_CC_CCI_0_CLK_SRC>;
2967 clock-names = "camnoc 2595 clock-names = "camnoc_axi",
2968 "slow_a 2596 "slow_ahb_src",
2969 "cpas_a 2597 "cpas_ahb",
2970 "cci", 2598 "cci",
2971 "cci_sr 2599 "cci_src";
2972 pinctrl-0 = <&cci0_de 2600 pinctrl-0 = <&cci0_default &cci1_default>;
2973 pinctrl-1 = <&cci0_sl 2601 pinctrl-1 = <&cci0_sleep &cci1_sleep>;
2974 pinctrl-names = "defa 2602 pinctrl-names = "default", "sleep";
2975 2603
2976 status = "disabled"; 2604 status = "disabled";
2977 #address-cells = <1>; 2605 #address-cells = <1>;
2978 #size-cells = <0>; 2606 #size-cells = <0>;
2979 2607
2980 cci0_i2c0: i2c-bus@0 2608 cci0_i2c0: i2c-bus@0 {
2981 reg = <0>; 2609 reg = <0>;
2982 clock-frequen 2610 clock-frequency = <1000000>;
2983 #address-cell 2611 #address-cells = <1>;
2984 #size-cells = 2612 #size-cells = <0>;
2985 }; 2613 };
2986 2614
2987 cci0_i2c1: i2c-bus@1 2615 cci0_i2c1: i2c-bus@1 {
2988 reg = <1>; 2616 reg = <1>;
2989 clock-frequen 2617 clock-frequency = <1000000>;
2990 #address-cell 2618 #address-cells = <1>;
2991 #size-cells = 2619 #size-cells = <0>;
2992 }; 2620 };
2993 }; 2621 };
2994 2622
2995 cci1: cci@ac16000 { 2623 cci1: cci@ac16000 {
2996 compatible = "qcom,sm 2624 compatible = "qcom,sm8450-cci", "qcom,msm8996-cci";
2997 reg = <0 0x0ac16000 0 2625 reg = <0 0x0ac16000 0 0x1000>;
2998 interrupts = <GIC_SPI 2626 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>;
2999 power-domains = <&cam 2627 power-domains = <&camcc TITAN_TOP_GDSC>;
3000 2628
3001 clocks = <&camcc CAM_ 2629 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
3002 <&camcc CAM_ 2630 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
3003 <&camcc CAM_ 2631 <&camcc CAM_CC_CPAS_AHB_CLK>,
3004 <&camcc CAM_ 2632 <&camcc CAM_CC_CCI_1_CLK>,
3005 <&camcc CAM_ 2633 <&camcc CAM_CC_CCI_1_CLK_SRC>;
3006 clock-names = "camnoc 2634 clock-names = "camnoc_axi",
3007 "slow_a 2635 "slow_ahb_src",
3008 "cpas_a 2636 "cpas_ahb",
3009 "cci", 2637 "cci",
3010 "cci_sr 2638 "cci_src";
3011 pinctrl-0 = <&cci2_de 2639 pinctrl-0 = <&cci2_default &cci3_default>;
3012 pinctrl-1 = <&cci2_sl 2640 pinctrl-1 = <&cci2_sleep &cci3_sleep>;
3013 pinctrl-names = "defa 2641 pinctrl-names = "default", "sleep";
3014 2642
3015 status = "disabled"; 2643 status = "disabled";
3016 #address-cells = <1>; 2644 #address-cells = <1>;
3017 #size-cells = <0>; 2645 #size-cells = <0>;
3018 2646
3019 cci1_i2c0: i2c-bus@0 2647 cci1_i2c0: i2c-bus@0 {
3020 reg = <0>; 2648 reg = <0>;
3021 clock-frequen 2649 clock-frequency = <1000000>;
3022 #address-cell 2650 #address-cells = <1>;
3023 #size-cells = 2651 #size-cells = <0>;
3024 }; 2652 };
3025 2653
3026 cci1_i2c1: i2c-bus@1 2654 cci1_i2c1: i2c-bus@1 {
3027 reg = <1>; 2655 reg = <1>;
3028 clock-frequen 2656 clock-frequency = <1000000>;
3029 #address-cell 2657 #address-cells = <1>;
3030 #size-cells = 2658 #size-cells = <0>;
3031 }; 2659 };
3032 }; 2660 };
3033 2661
3034 camcc: clock-controller@ade00 2662 camcc: clock-controller@ade0000 {
3035 compatible = "qcom,sm 2663 compatible = "qcom,sm8450-camcc";
3036 reg = <0 0x0ade0000 0 2664 reg = <0 0x0ade0000 0 0x20000>;
3037 clocks = <&gcc GCC_CA 2665 clocks = <&gcc GCC_CAMERA_AHB_CLK>,
3038 <&rpmhcc RPM 2666 <&rpmhcc RPMH_CXO_CLK>,
3039 <&rpmhcc RPM 2667 <&rpmhcc RPMH_CXO_CLK_A>,
3040 <&sleep_clk> 2668 <&sleep_clk>;
3041 power-domains = <&rpm !! 2669 power-domains = <&rpmhpd SM8450_MMCX>;
3042 required-opps = <&rpm 2670 required-opps = <&rpmhpd_opp_low_svs>;
3043 #clock-cells = <1>; 2671 #clock-cells = <1>;
3044 #reset-cells = <1>; 2672 #reset-cells = <1>;
3045 #power-domain-cells = 2673 #power-domain-cells = <1>;
3046 status = "disabled"; 2674 status = "disabled";
3047 }; 2675 };
3048 2676
3049 mdss: display-subsystem@ae000 2677 mdss: display-subsystem@ae00000 {
3050 compatible = "qcom,sm 2678 compatible = "qcom,sm8450-mdss";
3051 reg = <0 0x0ae00000 0 2679 reg = <0 0x0ae00000 0 0x1000>;
3052 reg-names = "mdss"; 2680 reg-names = "mdss";
3053 2681
3054 /* same path used twi 2682 /* same path used twice */
3055 interconnects = <&mms 2683 interconnects = <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>,
3056 <&mms !! 2684 <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>;
3057 <&gem !! 2685 interconnect-names = "mdp0-mem", "mdp1-mem";
3058 &con <<
3059 interconnect-names = <<
3060 <<
3061 <<
3062 2686
3063 resets = <&dispcc DIS 2687 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
3064 2688
3065 power-domains = <&dis 2689 power-domains = <&dispcc MDSS_GDSC>;
3066 2690
3067 clocks = <&dispcc DIS 2691 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3068 <&gcc GCC_DI 2692 <&gcc GCC_DISP_HF_AXI_CLK>,
3069 <&gcc GCC_DI 2693 <&gcc GCC_DISP_SF_AXI_CLK>,
3070 <&dispcc DIS 2694 <&dispcc DISP_CC_MDSS_MDP_CLK>;
3071 2695
3072 interrupts = <GIC_SPI 2696 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
3073 interrupt-controller; 2697 interrupt-controller;
3074 #interrupt-cells = <1 2698 #interrupt-cells = <1>;
3075 2699
3076 iommus = <&apps_smmu 2700 iommus = <&apps_smmu 0x2800 0x402>;
3077 2701
3078 #address-cells = <2>; 2702 #address-cells = <2>;
3079 #size-cells = <2>; 2703 #size-cells = <2>;
3080 ranges; 2704 ranges;
3081 2705
3082 status = "disabled"; 2706 status = "disabled";
3083 2707
3084 mdss_mdp: display-con 2708 mdss_mdp: display-controller@ae01000 {
3085 compatible = 2709 compatible = "qcom,sm8450-dpu";
3086 reg = <0 0x0a 2710 reg = <0 0x0ae01000 0 0x8f000>,
3087 <0 0x0a 2711 <0 0x0aeb0000 0 0x2008>;
3088 reg-names = " 2712 reg-names = "mdp", "vbif";
3089 2713
3090 clocks = <&gc 2714 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
3091 <&gcc 2715 <&gcc GCC_DISP_SF_AXI_CLK>,
3092 <&dis 2716 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3093 <&dis 2717 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
3094 <&dis 2718 <&dispcc DISP_CC_MDSS_MDP_CLK>,
3095 <&dis 2719 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3096 clock-names = 2720 clock-names = "bus",
3097 2721 "nrt_bus",
3098 2722 "iface",
3099 2723 "lut",
3100 2724 "core",
3101 2725 "vsync";
3102 2726
3103 assigned-cloc 2727 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3104 assigned-cloc 2728 assigned-clock-rates = <19200000>;
3105 2729
3106 operating-poi 2730 operating-points-v2 = <&mdp_opp_table>;
3107 power-domains !! 2731 power-domains = <&rpmhpd SM8450_MMCX>;
3108 2732
3109 interrupt-par 2733 interrupt-parent = <&mdss>;
3110 interrupts = 2734 interrupts = <0>;
3111 2735
3112 ports { 2736 ports {
3113 #addr 2737 #address-cells = <1>;
3114 #size 2738 #size-cells = <0>;
3115 2739
3116 port@ 2740 port@0 {
3117 2741 reg = <0>;
3118 2742 dpu_intf1_out: endpoint {
3119 2743 remote-endpoint = <&mdss_dsi0_in>;
3120 2744 };
3121 }; 2745 };
3122 2746
3123 port@ 2747 port@1 {
3124 2748 reg = <1>;
3125 2749 dpu_intf2_out: endpoint {
3126 2750 remote-endpoint = <&mdss_dsi1_in>;
3127 2751 };
3128 }; 2752 };
3129 2753
3130 port@ 2754 port@2 {
3131 2755 reg = <2>;
3132 2756 dpu_intf0_out: endpoint {
3133 2757 remote-endpoint = <&mdss_dp0_in>;
3134 2758 };
3135 }; 2759 };
3136 }; 2760 };
3137 2761
3138 mdp_opp_table 2762 mdp_opp_table: opp-table {
3139 compa 2763 compatible = "operating-points-v2";
3140 2764
3141 opp-1 2765 opp-172000000 {
3142 2766 opp-hz = /bits/ 64 <172000000>;
3143 2767 required-opps = <&rpmhpd_opp_low_svs_d1>;
3144 }; 2768 };
3145 2769
3146 opp-2 2770 opp-200000000 {
3147 2771 opp-hz = /bits/ 64 <200000000>;
3148 2772 required-opps = <&rpmhpd_opp_low_svs>;
3149 }; 2773 };
3150 2774
3151 opp-3 2775 opp-325000000 {
3152 2776 opp-hz = /bits/ 64 <325000000>;
3153 2777 required-opps = <&rpmhpd_opp_svs>;
3154 }; 2778 };
3155 2779
3156 opp-3 2780 opp-375000000 {
3157 2781 opp-hz = /bits/ 64 <375000000>;
3158 2782 required-opps = <&rpmhpd_opp_svs_l1>;
3159 }; 2783 };
3160 2784
3161 opp-5 2785 opp-500000000 {
3162 2786 opp-hz = /bits/ 64 <500000000>;
3163 2787 required-opps = <&rpmhpd_opp_nom>;
3164 }; 2788 };
3165 }; 2789 };
3166 }; 2790 };
3167 2791
3168 mdss_dp0: displayport 2792 mdss_dp0: displayport-controller@ae90000 {
3169 compatible = 2793 compatible = "qcom,sm8450-dp", "qcom,sm8350-dp";
3170 reg = <0 0xae 2794 reg = <0 0xae90000 0 0x200>,
3171 <0 0xae 2795 <0 0xae90200 0 0x200>,
3172 <0 0xae 2796 <0 0xae90400 0 0xc00>,
3173 <0 0xae 2797 <0 0xae91000 0 0x400>,
3174 <0 0xae 2798 <0 0xae91400 0 0x400>;
3175 interrupt-par 2799 interrupt-parent = <&mdss>;
3176 interrupts = 2800 interrupts = <12>;
3177 clocks = <&di 2801 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3178 <&di 2802 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
3179 <&di 2803 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
3180 <&di 2804 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
3181 <&di 2805 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
3182 clock-names = 2806 clock-names = "core_iface",
3183 2807 "core_aux",
3184 2808 "ctrl_link",
3185 2809 "ctrl_link_iface",
3186 2810 "stream_pixel";
3187 2811
3188 assigned-cloc 2812 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
3189 2813 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
3190 assigned-cloc 2814 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3191 2815 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
3192 2816
3193 phys = <&usb_ 2817 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
3194 phy-names = " 2818 phy-names = "dp";
3195 2819
3196 #sound-dai-ce 2820 #sound-dai-cells = <0>;
3197 2821
3198 operating-poi 2822 operating-points-v2 = <&dp_opp_table>;
3199 power-domains !! 2823 power-domains = <&rpmhpd SM8450_MMCX>;
3200 2824
3201 status = "dis 2825 status = "disabled";
3202 2826
3203 ports { 2827 ports {
3204 #addr 2828 #address-cells = <1>;
3205 #size 2829 #size-cells = <0>;
3206 2830
3207 port@ 2831 port@0 {
3208 2832 reg = <0>;
3209 2833 mdss_dp0_in: endpoint {
3210 2834 remote-endpoint = <&dpu_intf0_out>;
3211 2835 };
3212 }; 2836 };
3213 <<
3214 port@ <<
3215 <<
3216 <<
3217 <<
3218 <<
3219 <<
3220 }; <<
3221 }; 2837 };
3222 2838
3223 dp_opp_table: 2839 dp_opp_table: opp-table {
3224 compa 2840 compatible = "operating-points-v2";
3225 2841
3226 opp-1 2842 opp-160000000 {
3227 2843 opp-hz = /bits/ 64 <160000000>;
3228 2844 required-opps = <&rpmhpd_opp_low_svs>;
3229 }; 2845 };
3230 2846
3231 opp-2 2847 opp-270000000 {
3232 2848 opp-hz = /bits/ 64 <270000000>;
3233 2849 required-opps = <&rpmhpd_opp_svs>;
3234 }; 2850 };
3235 2851
3236 opp-5 2852 opp-540000000 {
3237 2853 opp-hz = /bits/ 64 <540000000>;
3238 2854 required-opps = <&rpmhpd_opp_svs_l1>;
3239 }; 2855 };
3240 2856
3241 opp-8 2857 opp-810000000 {
3242 2858 opp-hz = /bits/ 64 <810000000>;
3243 2859 required-opps = <&rpmhpd_opp_nom>;
3244 }; 2860 };
3245 }; 2861 };
3246 }; 2862 };
3247 2863
3248 mdss_dsi0: dsi@ae9400 2864 mdss_dsi0: dsi@ae94000 {
3249 compatible = 2865 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3250 reg = <0 0x0a 2866 reg = <0 0x0ae94000 0 0x400>;
3251 reg-names = " 2867 reg-names = "dsi_ctrl";
3252 2868
3253 interrupt-par 2869 interrupt-parent = <&mdss>;
3254 interrupts = 2870 interrupts = <4>;
3255 2871
3256 clocks = <&di 2872 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
3257 <&di 2873 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
3258 <&di 2874 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
3259 <&di 2875 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
3260 <&di 2876 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3261 <&gcc 2877 <&gcc GCC_DISP_HF_AXI_CLK>;
3262 clock-names = 2878 clock-names = "byte",
3263 2879 "byte_intf",
3264 2880 "pixel",
3265 2881 "core",
3266 2882 "iface",
3267 2883 "bus";
3268 2884
3269 assigned-cloc 2885 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
3270 assigned-cloc 2886 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
3271 2887
3272 operating-poi 2888 operating-points-v2 = <&mdss_dsi_opp_table>;
3273 power-domains !! 2889 power-domains = <&rpmhpd SM8450_MMCX>;
3274 2890
3275 phys = <&mdss 2891 phys = <&mdss_dsi0_phy>;
3276 phy-names = " 2892 phy-names = "dsi";
3277 2893
3278 #address-cell 2894 #address-cells = <1>;
3279 #size-cells = 2895 #size-cells = <0>;
3280 2896
3281 status = "dis 2897 status = "disabled";
3282 2898
3283 ports { 2899 ports {
3284 #addr 2900 #address-cells = <1>;
3285 #size 2901 #size-cells = <0>;
3286 2902
3287 port@ 2903 port@0 {
3288 2904 reg = <0>;
3289 2905 mdss_dsi0_in: endpoint {
3290 2906 remote-endpoint = <&dpu_intf1_out>;
3291 2907 };
3292 }; 2908 };
3293 2909
3294 port@ 2910 port@1 {
3295 2911 reg = <1>;
3296 2912 mdss_dsi0_out: endpoint {
3297 2913 };
3298 }; 2914 };
3299 }; 2915 };
3300 2916
3301 mdss_dsi_opp_ 2917 mdss_dsi_opp_table: opp-table {
3302 compa 2918 compatible = "operating-points-v2";
3303 2919
3304 opp-1 2920 opp-187500000 {
3305 2921 opp-hz = /bits/ 64 <187500000>;
3306 2922 required-opps = <&rpmhpd_opp_low_svs>;
3307 }; 2923 };
3308 2924
3309 opp-3 2925 opp-300000000 {
3310 2926 opp-hz = /bits/ 64 <300000000>;
3311 2927 required-opps = <&rpmhpd_opp_svs>;
3312 }; 2928 };
3313 2929
3314 opp-3 2930 opp-358000000 {
3315 2931 opp-hz = /bits/ 64 <358000000>;
3316 2932 required-opps = <&rpmhpd_opp_svs_l1>;
3317 }; 2933 };
3318 }; 2934 };
3319 }; 2935 };
3320 2936
3321 mdss_dsi0_phy: phy@ae 2937 mdss_dsi0_phy: phy@ae94400 {
3322 compatible = 2938 compatible = "qcom,sm8450-dsi-phy-5nm";
3323 reg = <0 0x0a 2939 reg = <0 0x0ae94400 0 0x200>,
3324 <0 0x0a 2940 <0 0x0ae94600 0 0x280>,
3325 <0 0x0a 2941 <0 0x0ae94900 0 0x260>;
3326 reg-names = " 2942 reg-names = "dsi_phy",
3327 " 2943 "dsi_phy_lane",
3328 " 2944 "dsi_pll";
3329 2945
3330 #clock-cells 2946 #clock-cells = <1>;
3331 #phy-cells = 2947 #phy-cells = <0>;
3332 2948
3333 clocks = <&di 2949 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3334 <&rp 2950 <&rpmhcc RPMH_CXO_CLK>;
3335 clock-names = 2951 clock-names = "iface", "ref";
3336 2952
3337 status = "dis 2953 status = "disabled";
3338 }; 2954 };
3339 2955
3340 mdss_dsi1: dsi@ae9600 2956 mdss_dsi1: dsi@ae96000 {
3341 compatible = 2957 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3342 reg = <0 0x0a 2958 reg = <0 0x0ae96000 0 0x400>;
3343 reg-names = " 2959 reg-names = "dsi_ctrl";
3344 2960
3345 interrupt-par 2961 interrupt-parent = <&mdss>;
3346 interrupts = 2962 interrupts = <5>;
3347 2963
3348 clocks = <&di 2964 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
3349 <&di 2965 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
3350 <&di 2966 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
3351 <&di 2967 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
3352 <&di 2968 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3353 <&gc 2969 <&gcc GCC_DISP_HF_AXI_CLK>;
3354 clock-names = 2970 clock-names = "byte",
3355 2971 "byte_intf",
3356 2972 "pixel",
3357 2973 "core",
3358 2974 "iface",
3359 2975 "bus";
3360 2976
3361 assigned-cloc 2977 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
3362 assigned-cloc 2978 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
3363 2979
3364 operating-poi 2980 operating-points-v2 = <&mdss_dsi_opp_table>;
3365 power-domains !! 2981 power-domains = <&rpmhpd SM8450_MMCX>;
3366 2982
3367 phys = <&mdss 2983 phys = <&mdss_dsi1_phy>;
3368 phy-names = " 2984 phy-names = "dsi";
3369 2985
3370 #address-cell 2986 #address-cells = <1>;
3371 #size-cells = 2987 #size-cells = <0>;
3372 2988
3373 status = "dis 2989 status = "disabled";
3374 2990
3375 ports { 2991 ports {
3376 #addr 2992 #address-cells = <1>;
3377 #size 2993 #size-cells = <0>;
3378 2994
3379 port@ 2995 port@0 {
3380 2996 reg = <0>;
3381 2997 mdss_dsi1_in: endpoint {
3382 2998 remote-endpoint = <&dpu_intf2_out>;
3383 2999 };
3384 }; 3000 };
3385 3001
3386 port@ 3002 port@1 {
3387 3003 reg = <1>;
3388 3004 mdss_dsi1_out: endpoint {
3389 3005 };
3390 }; 3006 };
3391 }; 3007 };
3392 }; 3008 };
3393 3009
3394 mdss_dsi1_phy: phy@ae 3010 mdss_dsi1_phy: phy@ae96400 {
3395 compatible = 3011 compatible = "qcom,sm8450-dsi-phy-5nm";
3396 reg = <0 0x0a 3012 reg = <0 0x0ae96400 0 0x200>,
3397 <0 0x0a 3013 <0 0x0ae96600 0 0x280>,
3398 <0 0x0a 3014 <0 0x0ae96900 0 0x260>;
3399 reg-names = " 3015 reg-names = "dsi_phy",
3400 " 3016 "dsi_phy_lane",
3401 " 3017 "dsi_pll";
3402 3018
3403 #clock-cells 3019 #clock-cells = <1>;
3404 #phy-cells = 3020 #phy-cells = <0>;
3405 3021
3406 clocks = <&di 3022 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3407 <&rp 3023 <&rpmhcc RPMH_CXO_CLK>;
3408 clock-names = 3024 clock-names = "iface", "ref";
3409 3025
3410 status = "dis 3026 status = "disabled";
3411 }; 3027 };
3412 }; 3028 };
3413 3029
3414 dispcc: clock-controller@af00 3030 dispcc: clock-controller@af00000 {
3415 compatible = "qcom,sm 3031 compatible = "qcom,sm8450-dispcc";
3416 reg = <0 0x0af00000 0 3032 reg = <0 0x0af00000 0 0x20000>;
3417 clocks = <&rpmhcc RPM 3033 clocks = <&rpmhcc RPMH_CXO_CLK>,
3418 <&rpmhcc RPM 3034 <&rpmhcc RPMH_CXO_CLK_A>,
3419 <&gcc GCC_DI 3035 <&gcc GCC_DISP_AHB_CLK>,
3420 <&sleep_clk> 3036 <&sleep_clk>,
3421 <&mdss_dsi0_ 3037 <&mdss_dsi0_phy 0>,
3422 <&mdss_dsi0_ 3038 <&mdss_dsi0_phy 1>,
3423 <&mdss_dsi1_ 3039 <&mdss_dsi1_phy 0>,
3424 <&mdss_dsi1_ 3040 <&mdss_dsi1_phy 1>,
3425 <&usb_1_qmpp 3041 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3426 <&usb_1_qmpp 3042 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
3427 <0>, /* dp1 3043 <0>, /* dp1 */
3428 <0>, 3044 <0>,
3429 <0>, /* dp2 3045 <0>, /* dp2 */
3430 <0>, 3046 <0>,
3431 <0>, /* dp3 3047 <0>, /* dp3 */
3432 <0>; 3048 <0>;
3433 power-domains = <&rpm !! 3049 power-domains = <&rpmhpd SM8450_MMCX>;
3434 required-opps = <&rpm 3050 required-opps = <&rpmhpd_opp_low_svs>;
3435 #clock-cells = <1>; 3051 #clock-cells = <1>;
3436 #reset-cells = <1>; 3052 #reset-cells = <1>;
3437 #power-domain-cells = 3053 #power-domain-cells = <1>;
3438 status = "disabled"; 3054 status = "disabled";
3439 }; 3055 };
3440 3056
3441 pdc: interrupt-controller@b22 3057 pdc: interrupt-controller@b220000 {
3442 compatible = "qcom,sm 3058 compatible = "qcom,sm8450-pdc", "qcom,pdc";
3443 reg = <0 0x0b220000 0 3059 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
3444 qcom,pdc-ranges = <0 3060 qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>,
3445 <94 3061 <94 609 31>, <125 63 1>, <126 716 12>;
3446 #interrupt-cells = <2 3062 #interrupt-cells = <2>;
3447 interrupt-parent = <& 3063 interrupt-parent = <&intc>;
3448 interrupt-controller; 3064 interrupt-controller;
3449 }; 3065 };
3450 3066
3451 tsens0: thermal-sensor@c26300 3067 tsens0: thermal-sensor@c263000 {
3452 compatible = "qcom,sm 3068 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2";
3453 reg = <0 0x0c263000 0 3069 reg = <0 0x0c263000 0 0x1000>, /* TM */
3454 <0 0x0c222000 0 3070 <0 0x0c222000 0 0x1000>; /* SROT */
3455 #qcom,sensors = <16>; 3071 #qcom,sensors = <16>;
3456 interrupts = <GIC_SPI 3072 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
3457 <GIC_SPI 3073 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
3458 interrupt-names = "up 3074 interrupt-names = "uplow", "critical";
3459 #thermal-sensor-cells 3075 #thermal-sensor-cells = <1>;
3460 }; 3076 };
3461 3077
3462 tsens1: thermal-sensor@c26500 3078 tsens1: thermal-sensor@c265000 {
3463 compatible = "qcom,sm 3079 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2";
3464 reg = <0 0x0c265000 0 3080 reg = <0 0x0c265000 0 0x1000>, /* TM */
3465 <0 0x0c223000 0 3081 <0 0x0c223000 0 0x1000>; /* SROT */
3466 #qcom,sensors = <16>; 3082 #qcom,sensors = <16>;
3467 interrupts = <GIC_SPI 3083 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
3468 <GIC_SPI 3084 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
3469 interrupt-names = "up 3085 interrupt-names = "uplow", "critical";
3470 #thermal-sensor-cells 3086 #thermal-sensor-cells = <1>;
3471 }; 3087 };
3472 3088
3473 aoss_qmp: power-management@c3 3089 aoss_qmp: power-management@c300000 {
3474 compatible = "qcom,sm 3090 compatible = "qcom,sm8450-aoss-qmp", "qcom,aoss-qmp";
3475 reg = <0 0x0c300000 0 3091 reg = <0 0x0c300000 0 0x400>;
3476 interrupts-extended = 3092 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
3477 3093 IRQ_TYPE_EDGE_RISING>;
3478 mboxes = <&ipcc IPCC_ 3094 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
3479 3095
3480 #clock-cells = <0>; 3096 #clock-cells = <0>;
3481 }; 3097 };
3482 3098
3483 sram@c3f0000 { <<
3484 compatible = "qcom,rp <<
3485 reg = <0 0x0c3f0000 0 <<
3486 }; <<
3487 <<
3488 spmi_bus: spmi@c400000 { 3099 spmi_bus: spmi@c400000 {
3489 compatible = "qcom,sp 3100 compatible = "qcom,spmi-pmic-arb";
3490 reg = <0 0x0c400000 0 3101 reg = <0 0x0c400000 0 0x00003000>,
3491 <0 0x0c500000 0 3102 <0 0x0c500000 0 0x00400000>,
3492 <0 0x0c440000 0 3103 <0 0x0c440000 0 0x00080000>,
3493 <0 0x0c4c0000 0 3104 <0 0x0c4c0000 0 0x00010000>,
3494 <0 0x0c42d000 0 3105 <0 0x0c42d000 0 0x00010000>;
3495 reg-names = "core", 3106 reg-names = "core",
3496 "chnls", 3107 "chnls",
3497 "obsrvr", 3108 "obsrvr",
3498 "intr", 3109 "intr",
3499 "cnfg"; 3110 "cnfg";
3500 interrupt-names = "pe 3111 interrupt-names = "periph_irq";
3501 interrupts-extended = 3112 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3502 qcom,ee = <0>; 3113 qcom,ee = <0>;
3503 qcom,channel = <0>; 3114 qcom,channel = <0>;
3504 interrupt-controller; 3115 interrupt-controller;
3505 #interrupt-cells = <4 3116 #interrupt-cells = <4>;
3506 #address-cells = <2>; 3117 #address-cells = <2>;
3507 #size-cells = <0>; 3118 #size-cells = <0>;
3508 }; 3119 };
3509 3120
3510 ipcc: mailbox@ed18000 { 3121 ipcc: mailbox@ed18000 {
3511 compatible = "qcom,sm 3122 compatible = "qcom,sm8450-ipcc", "qcom,ipcc";
3512 reg = <0 0x0ed18000 0 3123 reg = <0 0x0ed18000 0 0x1000>;
3513 interrupts = <GIC_SPI 3124 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
3514 interrupt-controller; 3125 interrupt-controller;
3515 #interrupt-cells = <3 3126 #interrupt-cells = <3>;
3516 #mbox-cells = <2>; 3127 #mbox-cells = <2>;
3517 }; 3128 };
3518 3129
3519 tlmm: pinctrl@f100000 { 3130 tlmm: pinctrl@f100000 {
3520 compatible = "qcom,sm 3131 compatible = "qcom,sm8450-tlmm";
3521 reg = <0 0x0f100000 0 3132 reg = <0 0x0f100000 0 0x300000>;
3522 interrupts = <GIC_SPI 3133 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
3523 gpio-controller; 3134 gpio-controller;
3524 #gpio-cells = <2>; 3135 #gpio-cells = <2>;
3525 interrupt-controller; 3136 interrupt-controller;
3526 #interrupt-cells = <2 3137 #interrupt-cells = <2>;
3527 gpio-ranges = <&tlmm 3138 gpio-ranges = <&tlmm 0 0 211>;
3528 wakeup-parent = <&pdc 3139 wakeup-parent = <&pdc>;
3529 3140
3530 sdc2_default_state: s 3141 sdc2_default_state: sdc2-default-state {
3531 clk-pins { 3142 clk-pins {
3532 pins 3143 pins = "sdc2_clk";
3533 drive 3144 drive-strength = <16>;
3534 bias- 3145 bias-disable;
3535 }; 3146 };
3536 3147
3537 cmd-pins { 3148 cmd-pins {
3538 pins 3149 pins = "sdc2_cmd";
3539 drive 3150 drive-strength = <16>;
3540 bias- 3151 bias-pull-up;
3541 }; 3152 };
3542 3153
3543 data-pins { 3154 data-pins {
3544 pins 3155 pins = "sdc2_data";
3545 drive 3156 drive-strength = <16>;
3546 bias- 3157 bias-pull-up;
3547 }; 3158 };
3548 }; 3159 };
3549 3160
3550 sdc2_sleep_state: sdc 3161 sdc2_sleep_state: sdc2-sleep-state {
3551 clk-pins { 3162 clk-pins {
3552 pins 3163 pins = "sdc2_clk";
3553 drive 3164 drive-strength = <2>;
3554 bias- 3165 bias-disable;
3555 }; 3166 };
3556 3167
3557 cmd-pins { 3168 cmd-pins {
3558 pins 3169 pins = "sdc2_cmd";
3559 drive 3170 drive-strength = <2>;
3560 bias- 3171 bias-pull-up;
3561 }; 3172 };
3562 3173
3563 data-pins { 3174 data-pins {
3564 pins 3175 pins = "sdc2_data";
3565 drive 3176 drive-strength = <2>;
3566 bias- 3177 bias-pull-up;
3567 }; 3178 };
3568 }; 3179 };
3569 3180
3570 cci0_default: cci0-de 3181 cci0_default: cci0-default-state {
3571 /* SDA, SCL * 3182 /* SDA, SCL */
3572 pins = "gpio1 3183 pins = "gpio110", "gpio111";
3573 function = "c 3184 function = "cci_i2c";
3574 drive-strengt 3185 drive-strength = <2>;
3575 bias-pull-up; 3186 bias-pull-up;
3576 }; 3187 };
3577 3188
3578 cci0_sleep: cci0-slee 3189 cci0_sleep: cci0-sleep-state {
3579 /* SDA, SCL * 3190 /* SDA, SCL */
3580 pins = "gpio1 3191 pins = "gpio110", "gpio111";
3581 function = "c 3192 function = "cci_i2c";
3582 drive-strengt 3193 drive-strength = <2>;
3583 bias-pull-dow 3194 bias-pull-down;
3584 }; 3195 };
3585 3196
3586 cci1_default: cci1-de 3197 cci1_default: cci1-default-state {
3587 /* SDA, SCL * 3198 /* SDA, SCL */
3588 pins = "gpio1 3199 pins = "gpio112", "gpio113";
3589 function = "c 3200 function = "cci_i2c";
3590 drive-strengt 3201 drive-strength = <2>;
3591 bias-pull-up; 3202 bias-pull-up;
3592 }; 3203 };
3593 3204
3594 cci1_sleep: cci1-slee 3205 cci1_sleep: cci1-sleep-state {
3595 /* SDA, SCL * 3206 /* SDA, SCL */
3596 pins = "gpio1 3207 pins = "gpio112", "gpio113";
3597 function = "c 3208 function = "cci_i2c";
3598 drive-strengt 3209 drive-strength = <2>;
3599 bias-pull-dow 3210 bias-pull-down;
3600 }; 3211 };
3601 3212
3602 cci2_default: cci2-de 3213 cci2_default: cci2-default-state {
3603 /* SDA, SCL * 3214 /* SDA, SCL */
3604 pins = "gpio1 3215 pins = "gpio114", "gpio115";
3605 function = "c 3216 function = "cci_i2c";
3606 drive-strengt 3217 drive-strength = <2>;
3607 bias-pull-up; 3218 bias-pull-up;
3608 }; 3219 };
3609 3220
3610 cci2_sleep: cci2-slee 3221 cci2_sleep: cci2-sleep-state {
3611 /* SDA, SCL * 3222 /* SDA, SCL */
3612 pins = "gpio1 3223 pins = "gpio114", "gpio115";
3613 function = "c 3224 function = "cci_i2c";
3614 drive-strengt 3225 drive-strength = <2>;
3615 bias-pull-dow 3226 bias-pull-down;
3616 }; 3227 };
3617 3228
3618 cci3_default: cci3-de 3229 cci3_default: cci3-default-state {
3619 /* SDA, SCL * 3230 /* SDA, SCL */
3620 pins = "gpio2 3231 pins = "gpio208", "gpio209";
3621 function = "c 3232 function = "cci_i2c";
3622 drive-strengt 3233 drive-strength = <2>;
3623 bias-pull-up; 3234 bias-pull-up;
3624 }; 3235 };
3625 3236
3626 cci3_sleep: cci3-slee 3237 cci3_sleep: cci3-sleep-state {
3627 /* SDA, SCL * 3238 /* SDA, SCL */
3628 pins = "gpio2 3239 pins = "gpio208", "gpio209";
3629 function = "c 3240 function = "cci_i2c";
3630 drive-strengt 3241 drive-strength = <2>;
3631 bias-pull-dow 3242 bias-pull-down;
3632 }; 3243 };
3633 3244
3634 pcie0_default_state: 3245 pcie0_default_state: pcie0-default-state {
3635 perst-pins { 3246 perst-pins {
3636 pins 3247 pins = "gpio94";
3637 funct 3248 function = "gpio";
3638 drive 3249 drive-strength = <2>;
3639 bias- 3250 bias-pull-down;
3640 }; 3251 };
3641 3252
3642 clkreq-pins { 3253 clkreq-pins {
3643 pins 3254 pins = "gpio95";
3644 funct 3255 function = "pcie0_clkreqn";
3645 drive 3256 drive-strength = <2>;
3646 bias- 3257 bias-pull-up;
3647 }; 3258 };
3648 3259
3649 wake-pins { 3260 wake-pins {
3650 pins 3261 pins = "gpio96";
3651 funct 3262 function = "gpio";
3652 drive 3263 drive-strength = <2>;
3653 bias- 3264 bias-pull-up;
3654 }; 3265 };
3655 }; 3266 };
3656 3267
3657 pcie1_default_state: 3268 pcie1_default_state: pcie1-default-state {
3658 perst-pins { 3269 perst-pins {
3659 pins 3270 pins = "gpio97";
3660 funct 3271 function = "gpio";
3661 drive 3272 drive-strength = <2>;
3662 bias- 3273 bias-pull-down;
3663 }; 3274 };
3664 3275
3665 clkreq-pins { 3276 clkreq-pins {
3666 pins 3277 pins = "gpio98";
3667 funct 3278 function = "pcie1_clkreqn";
3668 drive 3279 drive-strength = <2>;
3669 bias- 3280 bias-pull-up;
3670 }; 3281 };
3671 3282
3672 wake-pins { 3283 wake-pins {
3673 pins 3284 pins = "gpio99";
3674 funct 3285 function = "gpio";
3675 drive 3286 drive-strength = <2>;
3676 bias- 3287 bias-pull-up;
3677 }; 3288 };
3678 }; 3289 };
3679 3290
3680 qup_i2c0_data_clk: qu 3291 qup_i2c0_data_clk: qup-i2c0-data-clk-state {
3681 pins = "gpio0 3292 pins = "gpio0", "gpio1";
3682 function = "q 3293 function = "qup0";
3683 }; 3294 };
3684 3295
3685 qup_i2c1_data_clk: qu 3296 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
3686 pins = "gpio4 3297 pins = "gpio4", "gpio5";
3687 function = "q 3298 function = "qup1";
3688 }; 3299 };
3689 3300
3690 qup_i2c2_data_clk: qu 3301 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
3691 pins = "gpio8 3302 pins = "gpio8", "gpio9";
3692 function = "q 3303 function = "qup2";
3693 }; 3304 };
3694 3305
3695 qup_i2c3_data_clk: qu 3306 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
3696 pins = "gpio1 3307 pins = "gpio12", "gpio13";
3697 function = "q 3308 function = "qup3";
3698 }; 3309 };
3699 3310
3700 qup_i2c4_data_clk: qu 3311 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
3701 pins = "gpio1 3312 pins = "gpio16", "gpio17";
3702 function = "q 3313 function = "qup4";
3703 }; 3314 };
3704 3315
3705 qup_i2c5_data_clk: qu 3316 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
3706 pins = "gpio2 3317 pins = "gpio206", "gpio207";
3707 function = "q 3318 function = "qup5";
3708 }; 3319 };
3709 3320
3710 qup_i2c6_data_clk: qu 3321 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
3711 pins = "gpio2 3322 pins = "gpio20", "gpio21";
3712 function = "q 3323 function = "qup6";
3713 }; 3324 };
3714 3325
3715 qup_i2c8_data_clk: qu 3326 qup_i2c8_data_clk: qup-i2c8-data-clk-state {
3716 pins = "gpio2 3327 pins = "gpio28", "gpio29";
3717 function = "q 3328 function = "qup8";
3718 }; 3329 };
3719 3330
3720 qup_i2c9_data_clk: qu 3331 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
3721 pins = "gpio3 3332 pins = "gpio32", "gpio33";
3722 function = "q 3333 function = "qup9";
3723 }; 3334 };
3724 3335
3725 qup_i2c10_data_clk: q 3336 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
3726 pins = "gpio3 3337 pins = "gpio36", "gpio37";
3727 function = "q 3338 function = "qup10";
3728 }; 3339 };
3729 3340
3730 qup_i2c11_data_clk: q 3341 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
3731 pins = "gpio4 3342 pins = "gpio40", "gpio41";
3732 function = "q 3343 function = "qup11";
3733 }; 3344 };
3734 3345
3735 qup_i2c12_data_clk: q 3346 qup_i2c12_data_clk: qup-i2c12-data-clk-state {
3736 pins = "gpio4 3347 pins = "gpio44", "gpio45";
3737 function = "q 3348 function = "qup12";
3738 }; 3349 };
3739 3350
3740 qup_i2c13_data_clk: q 3351 qup_i2c13_data_clk: qup-i2c13-data-clk-state {
3741 pins = "gpio4 3352 pins = "gpio48", "gpio49";
3742 function = "q 3353 function = "qup13";
3743 drive-strengt 3354 drive-strength = <2>;
3744 bias-pull-up; 3355 bias-pull-up;
3745 }; 3356 };
3746 3357
3747 qup_i2c14_data_clk: q 3358 qup_i2c14_data_clk: qup-i2c14-data-clk-state {
3748 pins = "gpio5 3359 pins = "gpio52", "gpio53";
3749 function = "q 3360 function = "qup14";
3750 drive-strengt 3361 drive-strength = <2>;
3751 bias-pull-up; 3362 bias-pull-up;
3752 }; 3363 };
3753 3364
3754 qup_i2c15_data_clk: q 3365 qup_i2c15_data_clk: qup-i2c15-data-clk-state {
3755 pins = "gpio5 3366 pins = "gpio56", "gpio57";
3756 function = "q 3367 function = "qup15";
3757 }; 3368 };
3758 3369
3759 qup_i2c16_data_clk: q 3370 qup_i2c16_data_clk: qup-i2c16-data-clk-state {
3760 pins = "gpio6 3371 pins = "gpio60", "gpio61";
3761 function = "q 3372 function = "qup16";
3762 }; 3373 };
3763 3374
3764 qup_i2c17_data_clk: q 3375 qup_i2c17_data_clk: qup-i2c17-data-clk-state {
3765 pins = "gpio6 3376 pins = "gpio64", "gpio65";
3766 function = "q 3377 function = "qup17";
3767 }; 3378 };
3768 3379
3769 qup_i2c18_data_clk: q 3380 qup_i2c18_data_clk: qup-i2c18-data-clk-state {
3770 pins = "gpio6 3381 pins = "gpio68", "gpio69";
3771 function = "q 3382 function = "qup18";
3772 }; 3383 };
3773 3384
3774 qup_i2c19_data_clk: q 3385 qup_i2c19_data_clk: qup-i2c19-data-clk-state {
3775 pins = "gpio7 3386 pins = "gpio72", "gpio73";
3776 function = "q 3387 function = "qup19";
3777 }; 3388 };
3778 3389
3779 qup_i2c20_data_clk: q 3390 qup_i2c20_data_clk: qup-i2c20-data-clk-state {
3780 pins = "gpio7 3391 pins = "gpio76", "gpio77";
3781 function = "q 3392 function = "qup20";
3782 }; 3393 };
3783 3394
3784 qup_i2c21_data_clk: q 3395 qup_i2c21_data_clk: qup-i2c21-data-clk-state {
3785 pins = "gpio8 3396 pins = "gpio80", "gpio81";
3786 function = "q 3397 function = "qup21";
3787 }; 3398 };
3788 3399
3789 qup_spi0_cs: qup-spi0 3400 qup_spi0_cs: qup-spi0-cs-state {
3790 pins = "gpio3 3401 pins = "gpio3";
3791 function = "q 3402 function = "qup0";
3792 }; 3403 };
3793 3404
3794 qup_spi0_data_clk: qu 3405 qup_spi0_data_clk: qup-spi0-data-clk-state {
3795 pins = "gpio0 3406 pins = "gpio0", "gpio1", "gpio2";
3796 function = "q 3407 function = "qup0";
3797 }; 3408 };
3798 3409
3799 qup_spi1_cs: qup-spi1 3410 qup_spi1_cs: qup-spi1-cs-state {
3800 pins = "gpio7 3411 pins = "gpio7";
3801 function = "q 3412 function = "qup1";
3802 }; 3413 };
3803 3414
3804 qup_spi1_data_clk: qu 3415 qup_spi1_data_clk: qup-spi1-data-clk-state {
3805 pins = "gpio4 3416 pins = "gpio4", "gpio5", "gpio6";
3806 function = "q 3417 function = "qup1";
3807 }; 3418 };
3808 3419
3809 qup_spi2_cs: qup-spi2 3420 qup_spi2_cs: qup-spi2-cs-state {
3810 pins = "gpio1 3421 pins = "gpio11";
3811 function = "q 3422 function = "qup2";
3812 }; 3423 };
3813 3424
3814 qup_spi2_data_clk: qu 3425 qup_spi2_data_clk: qup-spi2-data-clk-state {
3815 pins = "gpio8 3426 pins = "gpio8", "gpio9", "gpio10";
3816 function = "q 3427 function = "qup2";
3817 }; 3428 };
3818 3429
3819 qup_spi3_cs: qup-spi3 3430 qup_spi3_cs: qup-spi3-cs-state {
3820 pins = "gpio1 3431 pins = "gpio15";
3821 function = "q 3432 function = "qup3";
3822 }; 3433 };
3823 3434
3824 qup_spi3_data_clk: qu 3435 qup_spi3_data_clk: qup-spi3-data-clk-state {
3825 pins = "gpio1 3436 pins = "gpio12", "gpio13", "gpio14";
3826 function = "q 3437 function = "qup3";
3827 }; 3438 };
3828 3439
3829 qup_spi4_cs: qup-spi4 3440 qup_spi4_cs: qup-spi4-cs-state {
3830 pins = "gpio1 3441 pins = "gpio19";
3831 function = "q 3442 function = "qup4";
3832 drive-strengt 3443 drive-strength = <6>;
3833 bias-disable; 3444 bias-disable;
3834 }; 3445 };
3835 3446
3836 qup_spi4_data_clk: qu 3447 qup_spi4_data_clk: qup-spi4-data-clk-state {
3837 pins = "gpio1 3448 pins = "gpio16", "gpio17", "gpio18";
3838 function = "q 3449 function = "qup4";
3839 }; 3450 };
3840 3451
3841 qup_spi5_cs: qup-spi5 3452 qup_spi5_cs: qup-spi5-cs-state {
3842 pins = "gpio8 3453 pins = "gpio85";
3843 function = "q 3454 function = "qup5";
3844 }; 3455 };
3845 3456
3846 qup_spi5_data_clk: qu 3457 qup_spi5_data_clk: qup-spi5-data-clk-state {
3847 pins = "gpio2 3458 pins = "gpio206", "gpio207", "gpio84";
3848 function = "q 3459 function = "qup5";
3849 }; 3460 };
3850 3461
3851 qup_spi6_cs: qup-spi6 3462 qup_spi6_cs: qup-spi6-cs-state {
3852 pins = "gpio2 3463 pins = "gpio23";
3853 function = "q 3464 function = "qup6";
3854 }; 3465 };
3855 3466
3856 qup_spi6_data_clk: qu 3467 qup_spi6_data_clk: qup-spi6-data-clk-state {
3857 pins = "gpio2 3468 pins = "gpio20", "gpio21", "gpio22";
3858 function = "q 3469 function = "qup6";
3859 }; 3470 };
3860 3471
3861 qup_spi8_cs: qup-spi8 3472 qup_spi8_cs: qup-spi8-cs-state {
3862 pins = "gpio3 3473 pins = "gpio31";
3863 function = "q 3474 function = "qup8";
3864 }; 3475 };
3865 3476
3866 qup_spi8_data_clk: qu 3477 qup_spi8_data_clk: qup-spi8-data-clk-state {
3867 pins = "gpio2 3478 pins = "gpio28", "gpio29", "gpio30";
3868 function = "q 3479 function = "qup8";
3869 }; 3480 };
3870 3481
3871 qup_spi9_cs: qup-spi9 3482 qup_spi9_cs: qup-spi9-cs-state {
3872 pins = "gpio3 3483 pins = "gpio35";
3873 function = "q 3484 function = "qup9";
3874 }; 3485 };
3875 3486
3876 qup_spi9_data_clk: qu 3487 qup_spi9_data_clk: qup-spi9-data-clk-state {
3877 pins = "gpio3 3488 pins = "gpio32", "gpio33", "gpio34";
3878 function = "q 3489 function = "qup9";
3879 }; 3490 };
3880 3491
3881 qup_spi10_cs: qup-spi 3492 qup_spi10_cs: qup-spi10-cs-state {
3882 pins = "gpio3 3493 pins = "gpio39";
3883 function = "q 3494 function = "qup10";
3884 }; 3495 };
3885 3496
3886 qup_spi10_data_clk: q 3497 qup_spi10_data_clk: qup-spi10-data-clk-state {
3887 pins = "gpio3 3498 pins = "gpio36", "gpio37", "gpio38";
3888 function = "q 3499 function = "qup10";
3889 }; 3500 };
3890 3501
3891 qup_spi11_cs: qup-spi 3502 qup_spi11_cs: qup-spi11-cs-state {
3892 pins = "gpio4 3503 pins = "gpio43";
3893 function = "q 3504 function = "qup11";
3894 }; 3505 };
3895 3506
3896 qup_spi11_data_clk: q 3507 qup_spi11_data_clk: qup-spi11-data-clk-state {
3897 pins = "gpio4 3508 pins = "gpio40", "gpio41", "gpio42";
3898 function = "q 3509 function = "qup11";
3899 }; 3510 };
3900 3511
3901 qup_spi12_cs: qup-spi 3512 qup_spi12_cs: qup-spi12-cs-state {
3902 pins = "gpio4 3513 pins = "gpio47";
3903 function = "q 3514 function = "qup12";
3904 }; 3515 };
3905 3516
3906 qup_spi12_data_clk: q 3517 qup_spi12_data_clk: qup-spi12-data-clk-state {
3907 pins = "gpio4 3518 pins = "gpio44", "gpio45", "gpio46";
3908 function = "q 3519 function = "qup12";
3909 }; 3520 };
3910 3521
3911 qup_spi13_cs: qup-spi 3522 qup_spi13_cs: qup-spi13-cs-state {
3912 pins = "gpio5 3523 pins = "gpio51";
3913 function = "q 3524 function = "qup13";
3914 }; 3525 };
3915 3526
3916 qup_spi13_data_clk: q 3527 qup_spi13_data_clk: qup-spi13-data-clk-state {
3917 pins = "gpio4 3528 pins = "gpio48", "gpio49", "gpio50";
3918 function = "q 3529 function = "qup13";
3919 }; 3530 };
3920 3531
3921 qup_spi14_cs: qup-spi 3532 qup_spi14_cs: qup-spi14-cs-state {
3922 pins = "gpio5 3533 pins = "gpio55";
3923 function = "q 3534 function = "qup14";
3924 }; 3535 };
3925 3536
3926 qup_spi14_data_clk: q 3537 qup_spi14_data_clk: qup-spi14-data-clk-state {
3927 pins = "gpio5 3538 pins = "gpio52", "gpio53", "gpio54";
3928 function = "q 3539 function = "qup14";
3929 }; 3540 };
3930 3541
3931 qup_spi15_cs: qup-spi 3542 qup_spi15_cs: qup-spi15-cs-state {
3932 pins = "gpio5 3543 pins = "gpio59";
3933 function = "q 3544 function = "qup15";
3934 }; 3545 };
3935 3546
3936 qup_spi15_data_clk: q 3547 qup_spi15_data_clk: qup-spi15-data-clk-state {
3937 pins = "gpio5 3548 pins = "gpio56", "gpio57", "gpio58";
3938 function = "q 3549 function = "qup15";
3939 }; 3550 };
3940 3551
3941 qup_spi16_cs: qup-spi 3552 qup_spi16_cs: qup-spi16-cs-state {
3942 pins = "gpio6 3553 pins = "gpio63";
3943 function = "q 3554 function = "qup16";
3944 }; 3555 };
3945 3556
3946 qup_spi16_data_clk: q 3557 qup_spi16_data_clk: qup-spi16-data-clk-state {
3947 pins = "gpio6 3558 pins = "gpio60", "gpio61", "gpio62";
3948 function = "q 3559 function = "qup16";
3949 }; 3560 };
3950 3561
3951 qup_spi17_cs: qup-spi 3562 qup_spi17_cs: qup-spi17-cs-state {
3952 pins = "gpio6 3563 pins = "gpio67";
3953 function = "q 3564 function = "qup17";
3954 }; 3565 };
3955 3566
3956 qup_spi17_data_clk: q 3567 qup_spi17_data_clk: qup-spi17-data-clk-state {
3957 pins = "gpio6 3568 pins = "gpio64", "gpio65", "gpio66";
3958 function = "q 3569 function = "qup17";
3959 }; 3570 };
3960 3571
3961 qup_spi18_cs: qup-spi 3572 qup_spi18_cs: qup-spi18-cs-state {
3962 pins = "gpio7 3573 pins = "gpio71";
3963 function = "q 3574 function = "qup18";
3964 drive-strengt 3575 drive-strength = <6>;
3965 bias-disable; 3576 bias-disable;
3966 }; 3577 };
3967 3578
3968 qup_spi18_data_clk: q 3579 qup_spi18_data_clk: qup-spi18-data-clk-state {
3969 pins = "gpio6 3580 pins = "gpio68", "gpio69", "gpio70";
3970 function = "q 3581 function = "qup18";
3971 drive-strengt 3582 drive-strength = <6>;
3972 bias-disable; 3583 bias-disable;
3973 }; 3584 };
3974 3585
3975 qup_spi19_cs: qup-spi 3586 qup_spi19_cs: qup-spi19-cs-state {
3976 pins = "gpio7 3587 pins = "gpio75";
3977 function = "q 3588 function = "qup19";
3978 drive-strengt 3589 drive-strength = <6>;
3979 bias-disable; 3590 bias-disable;
3980 }; 3591 };
3981 3592
3982 qup_spi19_data_clk: q 3593 qup_spi19_data_clk: qup-spi19-data-clk-state {
3983 pins = "gpio7 3594 pins = "gpio72", "gpio73", "gpio74";
3984 function = "q 3595 function = "qup19";
3985 drive-strengt 3596 drive-strength = <6>;
3986 bias-disable; 3597 bias-disable;
3987 }; 3598 };
3988 3599
3989 qup_spi20_cs: qup-spi 3600 qup_spi20_cs: qup-spi20-cs-state {
3990 pins = "gpio7 3601 pins = "gpio79";
3991 function = "q 3602 function = "qup20";
3992 }; 3603 };
3993 3604
3994 qup_spi20_data_clk: q 3605 qup_spi20_data_clk: qup-spi20-data-clk-state {
3995 pins = "gpio7 3606 pins = "gpio76", "gpio77", "gpio78";
3996 function = "q 3607 function = "qup20";
3997 }; 3608 };
3998 3609
3999 qup_spi21_cs: qup-spi 3610 qup_spi21_cs: qup-spi21-cs-state {
4000 pins = "gpio8 3611 pins = "gpio83";
4001 function = "q 3612 function = "qup21";
4002 }; 3613 };
4003 3614
4004 qup_spi21_data_clk: q 3615 qup_spi21_data_clk: qup-spi21-data-clk-state {
4005 pins = "gpio8 3616 pins = "gpio80", "gpio81", "gpio82";
4006 function = "q 3617 function = "qup21";
4007 }; 3618 };
4008 3619
4009 qup_uart7_rx: qup-uar 3620 qup_uart7_rx: qup-uart7-rx-state {
4010 pins = "gpio2 3621 pins = "gpio26";
4011 function = "q 3622 function = "qup7";
4012 drive-strengt 3623 drive-strength = <2>;
4013 bias-disable; 3624 bias-disable;
4014 }; 3625 };
4015 3626
4016 qup_uart7_tx: qup-uar 3627 qup_uart7_tx: qup-uart7-tx-state {
4017 pins = "gpio2 3628 pins = "gpio27";
4018 function = "q 3629 function = "qup7";
4019 drive-strengt 3630 drive-strength = <2>;
4020 bias-disable; 3631 bias-disable;
4021 }; 3632 };
4022 3633
4023 qup_uart20_default: q 3634 qup_uart20_default: qup-uart20-default-state {
4024 pins = "gpio7 3635 pins = "gpio76", "gpio77", "gpio78", "gpio79";
4025 function = "q 3636 function = "qup20";
4026 }; 3637 };
4027 }; 3638 };
4028 3639
4029 lpass_tlmm: pinctrl@3440000 { 3640 lpass_tlmm: pinctrl@3440000 {
4030 compatible = "qcom,sm 3641 compatible = "qcom,sm8450-lpass-lpi-pinctrl";
4031 reg = <0 0x03440000 0 3642 reg = <0 0x03440000 0x0 0x20000>,
4032 <0 0x034d0000 0 3643 <0 0x034d0000 0x0 0x10000>;
4033 gpio-controller; 3644 gpio-controller;
4034 #gpio-cells = <2>; 3645 #gpio-cells = <2>;
4035 gpio-ranges = <&lpass 3646 gpio-ranges = <&lpass_tlmm 0 0 23>;
4036 3647
4037 clocks = <&q6prmcc LP 3648 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
4038 <&q6prmcc LP 3649 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
4039 clock-names = "core", 3650 clock-names = "core", "audio";
4040 3651
4041 tx_swr_active: tx-swr 3652 tx_swr_active: tx-swr-active-state {
4042 clk-pins { 3653 clk-pins {
4043 pins 3654 pins = "gpio0";
4044 funct 3655 function = "swr_tx_clk";
4045 drive 3656 drive-strength = <2>;
4046 slew- 3657 slew-rate = <1>;
4047 bias- 3658 bias-disable;
4048 }; 3659 };
4049 3660
4050 data-pins { 3661 data-pins {
4051 pins 3662 pins = "gpio1", "gpio2", "gpio14";
4052 funct 3663 function = "swr_tx_data";
4053 drive 3664 drive-strength = <2>;
4054 slew- 3665 slew-rate = <1>;
4055 bias- 3666 bias-bus-hold;
4056 }; 3667 };
4057 }; 3668 };
4058 3669
4059 rx_swr_active: rx-swr 3670 rx_swr_active: rx-swr-active-state {
4060 clk-pins { 3671 clk-pins {
4061 pins 3672 pins = "gpio3";
4062 funct 3673 function = "swr_rx_clk";
4063 drive 3674 drive-strength = <2>;
4064 slew- 3675 slew-rate = <1>;
4065 bias- 3676 bias-disable;
4066 }; 3677 };
4067 3678
4068 data-pins { 3679 data-pins {
4069 pins 3680 pins = "gpio4", "gpio5";
4070 funct 3681 function = "swr_rx_data";
4071 drive 3682 drive-strength = <2>;
4072 slew- 3683 slew-rate = <1>;
4073 bias- 3684 bias-bus-hold;
4074 }; 3685 };
4075 }; 3686 };
4076 3687
4077 dmic01_default: dmic0 3688 dmic01_default: dmic01-default-state {
4078 clk-pins { 3689 clk-pins {
4079 pins 3690 pins = "gpio6";
4080 funct 3691 function = "dmic1_clk";
4081 drive 3692 drive-strength = <8>;
4082 outpu 3693 output-high;
4083 }; 3694 };
4084 3695
4085 data-pins { 3696 data-pins {
4086 pins 3697 pins = "gpio7";
4087 funct 3698 function = "dmic1_data";
4088 drive 3699 drive-strength = <8>;
4089 }; 3700 };
4090 }; 3701 };
4091 3702
4092 dmic23_default: dmic2 !! 3703 dmic02_default: dmic02-default-state {
4093 clk-pins { 3704 clk-pins {
4094 pins 3705 pins = "gpio8";
4095 funct 3706 function = "dmic2_clk";
4096 drive 3707 drive-strength = <8>;
4097 outpu 3708 output-high;
4098 }; 3709 };
4099 3710
4100 data-pins { 3711 data-pins {
4101 pins 3712 pins = "gpio9";
4102 funct 3713 function = "dmic2_data";
4103 drive 3714 drive-strength = <8>;
4104 }; 3715 };
4105 }; 3716 };
4106 3717
4107 wsa_swr_active: wsa-s 3718 wsa_swr_active: wsa-swr-active-state {
4108 clk-pins { 3719 clk-pins {
4109 pins 3720 pins = "gpio10";
4110 funct 3721 function = "wsa_swr_clk";
4111 drive 3722 drive-strength = <2>;
4112 slew- 3723 slew-rate = <1>;
4113 bias- 3724 bias-disable;
4114 }; 3725 };
4115 3726
4116 data-pins { 3727 data-pins {
4117 pins 3728 pins = "gpio11";
4118 funct 3729 function = "wsa_swr_data";
4119 drive 3730 drive-strength = <2>;
4120 slew- 3731 slew-rate = <1>;
4121 bias- 3732 bias-bus-hold;
4122 }; 3733 };
4123 }; 3734 };
4124 3735
4125 wsa2_swr_active: wsa2 3736 wsa2_swr_active: wsa2-swr-active-state {
4126 clk-pins { 3737 clk-pins {
4127 pins 3738 pins = "gpio15";
4128 funct 3739 function = "wsa2_swr_clk";
4129 drive 3740 drive-strength = <2>;
4130 slew- 3741 slew-rate = <1>;
4131 bias- 3742 bias-disable;
4132 }; 3743 };
4133 3744
4134 data-pins { 3745 data-pins {
4135 pins 3746 pins = "gpio16";
4136 funct 3747 function = "wsa2_swr_data";
4137 drive 3748 drive-strength = <2>;
4138 slew- 3749 slew-rate = <1>;
4139 bias- 3750 bias-bus-hold;
4140 }; 3751 };
4141 }; 3752 };
4142 }; 3753 };
4143 3754
4144 sram@146aa000 { 3755 sram@146aa000 {
4145 compatible = "qcom,sm 3756 compatible = "qcom,sm8450-imem", "syscon", "simple-mfd";
4146 reg = <0 0x146aa000 0 3757 reg = <0 0x146aa000 0 0x1000>;
4147 ranges = <0 0 0x146aa 3758 ranges = <0 0 0x146aa000 0x1000>;
4148 3759
4149 #address-cells = <1>; 3760 #address-cells = <1>;
4150 #size-cells = <1>; 3761 #size-cells = <1>;
4151 3762
4152 pil-reloc@94c { 3763 pil-reloc@94c {
4153 compatible = 3764 compatible = "qcom,pil-reloc-info";
4154 reg = <0x94c 3765 reg = <0x94c 0xc8>;
4155 }; 3766 };
4156 }; 3767 };
4157 3768
4158 apps_smmu: iommu@15000000 { 3769 apps_smmu: iommu@15000000 {
4159 compatible = "qcom,sm 3770 compatible = "qcom,sm8450-smmu-500", "arm,mmu-500";
4160 reg = <0 0x15000000 0 3771 reg = <0 0x15000000 0 0x100000>;
4161 #iommu-cells = <2>; 3772 #iommu-cells = <2>;
4162 #global-interrupts = 3773 #global-interrupts = <1>;
4163 interrupts = <GIC_SPI !! 3774 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
4164 <GIC_SPI !! 3775 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
4165 <GIC_SPI !! 3776 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
4166 <GIC_SPI !! 3777 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
4167 <GIC_SPI !! 3778 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
4168 <GIC_SPI !! 3779 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
4169 <GIC_SPI !! 3780 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
4170 <GIC_SPI !! 3781 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
4171 <GIC_SPI !! 3782 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
4172 <GIC_SPI !! 3783 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
4173 <GIC_SPI !! 3784 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
4174 <GIC_SPI !! 3785 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
4175 <GIC_SPI !! 3786 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
4176 <GIC_SPI !! 3787 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
4177 <GIC_SPI !! 3788 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
4178 <GIC_SPI !! 3789 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
4179 <GIC_SPI !! 3790 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
4180 <GIC_SPI !! 3791 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
4181 <GIC_SPI !! 3792 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
4182 <GIC_SPI !! 3793 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
4183 <GIC_SPI !! 3794 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
4184 <GIC_SPI !! 3795 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
4185 <GIC_SPI !! 3796 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
4186 <GIC_SPI !! 3797 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
4187 <GIC_SPI !! 3798 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
4188 <GIC_SPI !! 3799 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
4189 <GIC_SPI !! 3800 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
4190 <GIC_SPI !! 3801 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
4191 <GIC_SPI !! 3802 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
4192 <GIC_SPI !! 3803 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
4193 <GIC_SPI !! 3804 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
4194 <GIC_SPI !! 3805 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
4195 <GIC_SPI !! 3806 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
4196 <GIC_SPI !! 3807 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
4197 <GIC_SPI !! 3808 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
4198 <GIC_SPI !! 3809 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
4199 <GIC_SPI !! 3810 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
4200 <GIC_SPI !! 3811 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
4201 <GIC_SPI !! 3812 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
4202 <GIC_SPI !! 3813 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
4203 <GIC_SPI !! 3814 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
4204 <GIC_SPI !! 3815 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
4205 <GIC_SPI !! 3816 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
4206 <GIC_SPI !! 3817 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
4207 <GIC_SPI !! 3818 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
4208 <GIC_SPI !! 3819 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
4209 <GIC_SPI !! 3820 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
4210 <GIC_SPI !! 3821 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
4211 <GIC_SPI !! 3822 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
4212 <GIC_SPI !! 3823 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
4213 <GIC_SPI !! 3824 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
4214 <GIC_SPI !! 3825 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
4215 <GIC_SPI !! 3826 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
4216 <GIC_SPI !! 3827 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
4217 <GIC_SPI !! 3828 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
4218 <GIC_SPI !! 3829 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
4219 <GIC_SPI !! 3830 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
4220 <GIC_SPI !! 3831 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
4221 <GIC_SPI !! 3832 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
4222 <GIC_SPI !! 3833 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
4223 <GIC_SPI !! 3834 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
4224 <GIC_SPI !! 3835 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
4225 <GIC_SPI !! 3836 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
4226 <GIC_SPI !! 3837 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
4227 <GIC_SPI !! 3838 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
4228 <GIC_SPI !! 3839 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
4229 <GIC_SPI !! 3840 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
4230 <GIC_SPI !! 3841 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
4231 <GIC_SPI !! 3842 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
4232 <GIC_SPI !! 3843 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
4233 <GIC_SPI !! 3844 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
4234 <GIC_SPI !! 3845 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
4235 <GIC_SPI !! 3846 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
4236 <GIC_SPI !! 3847 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
4237 <GIC_SPI !! 3848 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
4238 <GIC_SPI !! 3849 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
4239 <GIC_SPI !! 3850 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
4240 <GIC_SPI !! 3851 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
4241 <GIC_SPI !! 3852 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
4242 <GIC_SPI !! 3853 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
4243 <GIC_SPI !! 3854 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
4244 <GIC_SPI !! 3855 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
4245 <GIC_SPI !! 3856 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
4246 <GIC_SPI !! 3857 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
4247 <GIC_SPI !! 3858 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
4248 <GIC_SPI !! 3859 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
4249 <GIC_SPI !! 3860 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
4250 <GIC_SPI !! 3861 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
4251 <GIC_SPI !! 3862 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
4252 <GIC_SPI !! 3863 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
4253 <GIC_SPI !! 3864 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
4254 <GIC_SPI !! 3865 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
4255 <GIC_SPI !! 3866 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
4256 <GIC_SPI !! 3867 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
4257 <GIC_SPI !! 3868 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
4258 <GIC_SPI !! 3869 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
4259 <GIC_SPI !! 3870 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>;
4260 }; 3871 };
4261 3872
4262 intc: interrupt-controller@17 3873 intc: interrupt-controller@17100000 {
4263 compatible = "arm,gic 3874 compatible = "arm,gic-v3";
4264 #interrupt-cells = <3 3875 #interrupt-cells = <3>;
4265 interrupt-controller; 3876 interrupt-controller;
4266 #redistributor-region 3877 #redistributor-regions = <1>;
4267 redistributor-stride 3878 redistributor-stride = <0x0 0x40000>;
4268 reg = <0x0 0x17100000 3879 reg = <0x0 0x17100000 0x0 0x10000>, /* GICD */
4269 <0x0 0x17180000 3880 <0x0 0x17180000 0x0 0x200000>; /* GICR * 8 */
4270 interrupts = <GIC_PPI 3881 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
4271 #address-cells = <2>; 3882 #address-cells = <2>;
4272 #size-cells = <2>; 3883 #size-cells = <2>;
4273 ranges; 3884 ranges;
4274 3885
4275 gic_its: msi-controll 3886 gic_its: msi-controller@17140000 {
4276 compatible = 3887 compatible = "arm,gic-v3-its";
4277 reg = <0x0 0x 3888 reg = <0x0 0x17140000 0x0 0x20000>;
4278 msi-controlle 3889 msi-controller;
4279 #msi-cells = 3890 #msi-cells = <1>;
4280 }; 3891 };
4281 }; 3892 };
4282 3893
4283 timer@17420000 { 3894 timer@17420000 {
4284 compatible = "arm,arm 3895 compatible = "arm,armv7-timer-mem";
4285 #address-cells = <1>; 3896 #address-cells = <1>;
4286 #size-cells = <1>; 3897 #size-cells = <1>;
4287 ranges = <0 0 0 0x200 3898 ranges = <0 0 0 0x20000000>;
4288 reg = <0x0 0x17420000 3899 reg = <0x0 0x17420000 0x0 0x1000>;
4289 clock-frequency = <19 3900 clock-frequency = <19200000>;
4290 3901
4291 frame@17421000 { 3902 frame@17421000 {
4292 frame-number 3903 frame-number = <0>;
4293 interrupts = 3904 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
4294 3905 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
4295 reg = <0x1742 3906 reg = <0x17421000 0x1000>,
4296 <0x1742 3907 <0x17422000 0x1000>;
4297 }; 3908 };
4298 3909
4299 frame@17423000 { 3910 frame@17423000 {
4300 frame-number 3911 frame-number = <1>;
4301 interrupts = 3912 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
4302 reg = <0x1742 3913 reg = <0x17423000 0x1000>;
4303 status = "dis 3914 status = "disabled";
4304 }; 3915 };
4305 3916
4306 frame@17425000 { 3917 frame@17425000 {
4307 frame-number 3918 frame-number = <2>;
4308 interrupts = 3919 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
4309 reg = <0x1742 3920 reg = <0x17425000 0x1000>;
4310 status = "dis 3921 status = "disabled";
4311 }; 3922 };
4312 3923
4313 frame@17427000 { 3924 frame@17427000 {
4314 frame-number 3925 frame-number = <3>;
4315 interrupts = 3926 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
4316 reg = <0x1742 3927 reg = <0x17427000 0x1000>;
4317 status = "dis 3928 status = "disabled";
4318 }; 3929 };
4319 3930
4320 frame@17429000 { 3931 frame@17429000 {
4321 frame-number 3932 frame-number = <4>;
4322 interrupts = 3933 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
4323 reg = <0x1742 3934 reg = <0x17429000 0x1000>;
4324 status = "dis 3935 status = "disabled";
4325 }; 3936 };
4326 3937
4327 frame@1742b000 { 3938 frame@1742b000 {
4328 frame-number 3939 frame-number = <5>;
4329 interrupts = 3940 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
4330 reg = <0x1742 3941 reg = <0x1742b000 0x1000>;
4331 status = "dis 3942 status = "disabled";
4332 }; 3943 };
4333 3944
4334 frame@1742d000 { 3945 frame@1742d000 {
4335 frame-number 3946 frame-number = <6>;
4336 interrupts = 3947 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
4337 reg = <0x1742 3948 reg = <0x1742d000 0x1000>;
4338 status = "dis 3949 status = "disabled";
4339 }; 3950 };
4340 }; 3951 };
4341 3952
4342 apps_rsc: rsc@17a00000 { 3953 apps_rsc: rsc@17a00000 {
4343 label = "apps_rsc"; 3954 label = "apps_rsc";
4344 compatible = "qcom,rp 3955 compatible = "qcom,rpmh-rsc";
4345 reg = <0x0 0x17a00000 3956 reg = <0x0 0x17a00000 0x0 0x10000>,
4346 <0x0 0x17a10000 3957 <0x0 0x17a10000 0x0 0x10000>,
4347 <0x0 0x17a20000 3958 <0x0 0x17a20000 0x0 0x10000>,
4348 <0x0 0x17a30000 3959 <0x0 0x17a30000 0x0 0x10000>;
4349 reg-names = "drv-0", 3960 reg-names = "drv-0", "drv-1", "drv-2", "drv-3";
4350 interrupts = <GIC_SPI 3961 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
4351 <GIC_SPI 3962 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
4352 <GIC_SPI 3963 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
4353 qcom,tcs-offset = <0x 3964 qcom,tcs-offset = <0xd00>;
4354 qcom,drv-id = <2>; 3965 qcom,drv-id = <2>;
4355 qcom,tcs-config = <AC 3966 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
4356 <WA 3967 <WAKE_TCS 2>, <CONTROL_TCS 0>;
4357 power-domains = <&CLU 3968 power-domains = <&CLUSTER_PD>;
4358 3969
4359 apps_bcm_voter: bcm-v 3970 apps_bcm_voter: bcm-voter {
4360 compatible = 3971 compatible = "qcom,bcm-voter";
4361 }; 3972 };
4362 3973
4363 rpmhcc: clock-control 3974 rpmhcc: clock-controller {
4364 compatible = 3975 compatible = "qcom,sm8450-rpmh-clk";
4365 #clock-cells 3976 #clock-cells = <1>;
4366 clock-names = 3977 clock-names = "xo";
4367 clocks = <&xo 3978 clocks = <&xo_board>;
4368 }; 3979 };
4369 3980
4370 rpmhpd: power-control 3981 rpmhpd: power-controller {
4371 compatible = 3982 compatible = "qcom,sm8450-rpmhpd";
4372 #power-domain 3983 #power-domain-cells = <1>;
4373 operating-poi 3984 operating-points-v2 = <&rpmhpd_opp_table>;
4374 3985
4375 rpmhpd_opp_ta 3986 rpmhpd_opp_table: opp-table {
4376 compa 3987 compatible = "operating-points-v2";
4377 3988
4378 rpmhp 3989 rpmhpd_opp_ret: opp1 {
4379 3990 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4380 }; 3991 };
4381 3992
4382 rpmhp 3993 rpmhpd_opp_min_svs: opp2 {
4383 3994 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4384 }; 3995 };
4385 3996
4386 rpmhp 3997 rpmhpd_opp_low_svs_d1: opp3 {
4387 3998 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
4388 }; 3999 };
4389 4000
4390 rpmhp 4001 rpmhpd_opp_low_svs: opp4 {
4391 4002 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4392 }; 4003 };
4393 4004
4394 rpmhp !! 4005 rpmhpd_opp_svs: opp5 {
4395 <<
4396 }; <<
4397 <<
4398 rpmhp <<
4399 4006 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4400 }; 4007 };
4401 4008
4402 rpmhp !! 4009 rpmhpd_opp_svs_l1: opp6 {
4403 <<
4404 }; <<
4405 <<
4406 rpmhp <<
4407 4010 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4408 }; 4011 };
4409 4012
4410 rpmhp !! 4013 rpmhpd_opp_nom: opp7 {
4411 <<
4412 }; <<
4413 <<
4414 rpmhp <<
4415 4014 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4416 }; 4015 };
4417 4016
4418 rpmhp !! 4017 rpmhpd_opp_nom_l1: opp8 {
4419 4018 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4420 }; 4019 };
4421 4020
4422 rpmhp !! 4021 rpmhpd_opp_nom_l2: opp9 {
4423 4022 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4424 }; 4023 };
4425 4024
4426 rpmhp !! 4025 rpmhpd_opp_turbo: opp10 {
4427 4026 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4428 }; 4027 };
4429 4028
4430 rpmhp !! 4029 rpmhpd_opp_turbo_l1: opp11 {
4431 4030 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4432 }; 4031 };
4433 }; 4032 };
4434 }; 4033 };
4435 }; 4034 };
4436 4035
4437 cpufreq_hw: cpufreq@17d91000 4036 cpufreq_hw: cpufreq@17d91000 {
4438 compatible = "qcom,sm 4037 compatible = "qcom,sm8450-cpufreq-epss", "qcom,cpufreq-epss";
4439 reg = <0 0x17d91000 0 4038 reg = <0 0x17d91000 0 0x1000>,
4440 <0 0x17d92000 0 4039 <0 0x17d92000 0 0x1000>,
4441 <0 0x17d93000 0 4040 <0 0x17d93000 0 0x1000>;
4442 reg-names = "freq-dom 4041 reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
4443 clocks = <&rpmhcc RPM 4042 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
4444 clock-names = "xo", " 4043 clock-names = "xo", "alternate";
4445 interrupts = <GIC_SPI 4044 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
4446 <GIC_SPI 4045 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
4447 <GIC_SPI 4046 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
4448 interrupt-names = "dc 4047 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
4449 #freq-domain-cells = 4048 #freq-domain-cells = <1>;
4450 #clock-cells = <1>; 4049 #clock-cells = <1>;
4451 }; 4050 };
4452 4051
4453 gem_noc: interconnect@1910000 4052 gem_noc: interconnect@19100000 {
4454 compatible = "qcom,sm 4053 compatible = "qcom,sm8450-gem-noc";
4455 reg = <0 0x19100000 0 4054 reg = <0 0x19100000 0 0xbb800>;
4456 #interconnect-cells = 4055 #interconnect-cells = <2>;
4457 qcom,bcm-voters = <&a 4056 qcom,bcm-voters = <&apps_bcm_voter>;
4458 }; 4057 };
4459 4058
4460 system-cache-controller@19200 4059 system-cache-controller@19200000 {
4461 compatible = "qcom,sm 4060 compatible = "qcom,sm8450-llcc";
4462 reg = <0 0x19200000 0 4061 reg = <0 0x19200000 0 0x80000>, <0 0x19600000 0 0x80000>,
4463 <0 0x19300000 0 4062 <0 0x19300000 0 0x80000>, <0 0x19700000 0 0x80000>,
4464 <0 0x19a00000 0 !! 4063 <0 0x19a00000 0 0x80000>;
4465 reg-names = "llcc0_ba 4064 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
4466 "llcc3_ba !! 4065 "llcc3_base", "llcc_broadcast_base";
4467 "llcc_bro <<
4468 interrupts = <GIC_SPI 4066 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
4469 }; 4067 };
4470 4068
4471 ufs_mem_hc: ufshc@1d84000 { 4069 ufs_mem_hc: ufshc@1d84000 {
4472 compatible = "qcom,sm 4070 compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
4473 "jedec,u 4071 "jedec,ufs-2.0";
4474 reg = <0 0x01d84000 0 !! 4072 reg = <0 0x01d84000 0 0x3000>,
>> 4073 <0 0x01d88000 0 0x8000>;
>> 4074 reg-names = "std", "ice";
4475 interrupts = <GIC_SPI 4075 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
4476 phys = <&ufs_mem_phy> !! 4076 phys = <&ufs_mem_phy_lanes>;
4477 phy-names = "ufsphy"; 4077 phy-names = "ufsphy";
4478 lanes-per-direction = 4078 lanes-per-direction = <2>;
4479 #reset-cells = <1>; 4079 #reset-cells = <1>;
4480 resets = <&gcc GCC_UF 4080 resets = <&gcc GCC_UFS_PHY_BCR>;
4481 reset-names = "rst"; 4081 reset-names = "rst";
4482 4082
4483 power-domains = <&gcc 4083 power-domains = <&gcc UFS_PHY_GDSC>;
4484 4084
4485 iommus = <&apps_smmu 4085 iommus = <&apps_smmu 0xe0 0x0>;
4486 dma-coherent; 4086 dma-coherent;
4487 4087
4488 interconnects = <&agg 4088 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>,
4489 <&gem 4089 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
4490 interconnect-names = 4090 interconnect-names = "ufs-ddr", "cpu-ufs";
4491 clock-names = 4091 clock-names =
4492 "core_clk", 4092 "core_clk",
4493 "bus_aggr_clk 4093 "bus_aggr_clk",
4494 "iface_clk", 4094 "iface_clk",
4495 "core_clk_uni 4095 "core_clk_unipro",
4496 "ref_clk", 4096 "ref_clk",
4497 "tx_lane0_syn 4097 "tx_lane0_sync_clk",
4498 "rx_lane0_syn 4098 "rx_lane0_sync_clk",
4499 "rx_lane1_syn !! 4099 "rx_lane1_sync_clk",
>> 4100 "ice_core_clk";
4500 clocks = 4101 clocks =
4501 <&gcc GCC_UFS 4102 <&gcc GCC_UFS_PHY_AXI_CLK>,
4502 <&gcc GCC_AGG 4103 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
4503 <&gcc GCC_UFS 4104 <&gcc GCC_UFS_PHY_AHB_CLK>,
4504 <&gcc GCC_UFS 4105 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
4505 <&rpmhcc RPMH 4106 <&rpmhcc RPMH_CXO_CLK>,
4506 <&gcc GCC_UFS 4107 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
4507 <&gcc GCC_UFS 4108 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
4508 <&gcc GCC_UFS !! 4109 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
>> 4110 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
4509 freq-table-hz = 4111 freq-table-hz =
4510 <75000000 300 4112 <75000000 300000000>,
4511 <0 0>, 4113 <0 0>,
4512 <0 0>, 4114 <0 0>,
4513 <75000000 300 4115 <75000000 300000000>,
4514 <75000000 300 4116 <75000000 300000000>,
4515 <0 0>, 4117 <0 0>,
4516 <0 0>, 4118 <0 0>,
4517 <0 0>; !! 4119 <0 0>,
4518 qcom,ice = <&ice>; !! 4120 <75000000 300000000>;
4519 <<
4520 status = "disabled"; 4121 status = "disabled";
4521 }; 4122 };
4522 4123
4523 ufs_mem_phy: phy@1d87000 { 4124 ufs_mem_phy: phy@1d87000 {
4524 compatible = "qcom,sm 4125 compatible = "qcom,sm8450-qmp-ufs-phy";
4525 reg = <0 0x01d87000 0 !! 4126 reg = <0 0x01d87000 0 0x1c4>;
4526 !! 4127 #address-cells = <2>;
>> 4128 #size-cells = <2>;
>> 4129 ranges;
4527 clock-names = "ref", 4130 clock-names = "ref", "ref_aux", "qref";
4528 clocks = <&rpmhcc RPM 4131 clocks = <&rpmhcc RPMH_CXO_CLK>,
4529 <&gcc GCC_UF 4132 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
4530 <&gcc GCC_UF 4133 <&gcc GCC_UFS_0_CLKREF_EN>;
4531 4134
4532 power-domains = <&gcc <<
4533 <<
4534 resets = <&ufs_mem_hc 4135 resets = <&ufs_mem_hc 0>;
4535 reset-names = "ufsphy 4136 reset-names = "ufsphy";
4536 <<
4537 #clock-cells = <1>; <<
4538 #phy-cells = <0>; <<
4539 <<
4540 status = "disabled"; 4137 status = "disabled";
4541 }; <<
4542 4138
4543 ice: crypto@1d88000 { !! 4139 ufs_mem_phy_lanes: phy@1d87400 {
4544 compatible = "qcom,sm !! 4140 reg = <0 0x01d87400 0 0x188>,
4545 "qcom,in !! 4141 <0 0x01d87600 0 0x200>,
4546 reg = <0 0x01d88000 0 !! 4142 <0 0x01d87c00 0 0x200>,
4547 clocks = <&gcc GCC_UF !! 4143 <0 0x01d87800 0 0x188>,
4548 }; !! 4144 <0 0x01d87a00 0 0x200>;
4549 !! 4145 #clock-cells = <1>;
4550 cryptobam: dma-controller@1dc !! 4146 #phy-cells = <0>;
4551 compatible = "qcom,ba !! 4147 };
4552 reg = <0 0x01dc4000 0 <<
4553 interrupts = <GIC_SPI <<
4554 #dma-cells = <1>; <<
4555 qcom,ee = <0>; <<
4556 qcom,controlled-remot <<
4557 iommus = <&apps_smmu <<
4558 <&apps_smmu <<
4559 <&apps_smmu <<
4560 <&apps_smmu <<
4561 <&apps_smmu <<
4562 }; <<
4563 <<
4564 crypto: crypto@1dfa000 { <<
4565 compatible = "qcom,sm <<
4566 reg = <0 0x01dfa000 0 <<
4567 dmas = <&cryptobam 4> <<
4568 dma-names = "rx", "tx <<
4569 iommus = <&apps_smmu <<
4570 <&apps_smmu <<
4571 <&apps_smmu <<
4572 <&apps_smmu <<
4573 <&apps_smmu <<
4574 interconnects = <&agg <<
4575 interconnect-names = <<
4576 }; 4148 };
4577 4149
4578 sdhc_2: mmc@8804000 { 4150 sdhc_2: mmc@8804000 {
4579 compatible = "qcom,sm 4151 compatible = "qcom,sm8450-sdhci", "qcom,sdhci-msm-v5";
4580 reg = <0 0x08804000 0 4152 reg = <0 0x08804000 0 0x1000>;
4581 4153
4582 interrupts = <GIC_SPI 4154 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
4583 <GIC_SPI 4155 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
4584 interrupt-names = "hc 4156 interrupt-names = "hc_irq", "pwr_irq";
4585 4157
4586 clocks = <&gcc GCC_SD 4158 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
4587 <&gcc GCC_SD 4159 <&gcc GCC_SDCC2_APPS_CLK>,
4588 <&rpmhcc RPM 4160 <&rpmhcc RPMH_CXO_CLK>;
4589 clock-names = "iface" 4161 clock-names = "iface", "core", "xo";
4590 resets = <&gcc GCC_SD 4162 resets = <&gcc GCC_SDCC2_BCR>;
4591 interconnects = <&agg 4163 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
4592 <&gem 4164 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
4593 interconnect-names = 4165 interconnect-names = "sdhc-ddr","cpu-sdhc";
4594 iommus = <&apps_smmu 4166 iommus = <&apps_smmu 0x4a0 0x0>;
4595 power-domains = <&rpm !! 4167 power-domains = <&rpmhpd SM8450_CX>;
4596 operating-points-v2 = 4168 operating-points-v2 = <&sdhc2_opp_table>;
4597 bus-width = <4>; 4169 bus-width = <4>;
4598 dma-coherent; 4170 dma-coherent;
4599 4171
4600 /* Forbid SDR104/SDR5 4172 /* Forbid SDR104/SDR50 - broken hw! */
4601 sdhci-caps-mask = <0x 4173 sdhci-caps-mask = <0x3 0x0>;
4602 4174
4603 status = "disabled"; 4175 status = "disabled";
4604 4176
4605 sdhc2_opp_table: opp- 4177 sdhc2_opp_table: opp-table {
4606 compatible = 4178 compatible = "operating-points-v2";
4607 4179
4608 opp-100000000 4180 opp-100000000 {
4609 opp-h 4181 opp-hz = /bits/ 64 <100000000>;
4610 requi 4182 required-opps = <&rpmhpd_opp_low_svs>;
4611 }; 4183 };
4612 4184
4613 opp-202000000 4185 opp-202000000 {
4614 opp-h 4186 opp-hz = /bits/ 64 <202000000>;
4615 requi 4187 required-opps = <&rpmhpd_opp_svs_l1>;
4616 }; 4188 };
4617 }; 4189 };
4618 }; 4190 };
4619 4191
4620 usb_1: usb@a6f8800 { 4192 usb_1: usb@a6f8800 {
4621 compatible = "qcom,sm 4193 compatible = "qcom,sm8450-dwc3", "qcom,dwc3";
4622 reg = <0 0x0a6f8800 0 4194 reg = <0 0x0a6f8800 0 0x400>;
4623 status = "disabled"; 4195 status = "disabled";
4624 #address-cells = <2>; 4196 #address-cells = <2>;
4625 #size-cells = <2>; 4197 #size-cells = <2>;
4626 ranges; 4198 ranges;
4627 4199
4628 clocks = <&gcc GCC_CF 4200 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
4629 <&gcc GCC_US 4201 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
4630 <&gcc GCC_AG 4202 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
4631 <&gcc GCC_US 4203 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
4632 <&gcc GCC_US 4204 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4633 <&gcc GCC_US 4205 <&gcc GCC_USB3_0_CLKREF_EN>;
4634 clock-names = "cfg_no 4206 clock-names = "cfg_noc",
4635 "core", 4207 "core",
4636 "iface" 4208 "iface",
4637 "sleep" 4209 "sleep",
4638 "mock_u 4210 "mock_utmi",
4639 "xo"; 4211 "xo";
4640 4212
4641 assigned-clocks = <&g 4213 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4642 <&g 4214 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
4643 assigned-clock-rates 4215 assigned-clock-rates = <19200000>, <200000000>;
4644 4216
4645 interrupts-extended = 4217 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
4646 !! 4218 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
4647 <<
4648 4219 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
4649 !! 4220 <&pdc 14 IRQ_TYPE_EDGE_BOTH>;
4650 interrupt-names = "pw !! 4221 interrupt-names = "hs_phy_irq",
4651 "hs !! 4222 "ss_phy_irq",
4652 "dp <<
4653 "dm 4223 "dm_hs_phy_irq",
4654 "ss !! 4224 "dp_hs_phy_irq";
4655 4225
4656 power-domains = <&gcc 4226 power-domains = <&gcc USB30_PRIM_GDSC>;
4657 4227
4658 resets = <&gcc GCC_US 4228 resets = <&gcc GCC_USB30_PRIM_BCR>;
4659 4229
4660 interconnects = <&agg <<
4661 <&gem <<
4662 interconnect-names = <<
4663 <<
4664 usb_1_dwc3: usb@a6000 4230 usb_1_dwc3: usb@a600000 {
4665 compatible = 4231 compatible = "snps,dwc3";
4666 reg = <0 0x0a 4232 reg = <0 0x0a600000 0 0xcd00>;
4667 interrupts = 4233 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
4668 iommus = <&ap 4234 iommus = <&apps_smmu 0x0 0x0>;
4669 snps,dis_u2_s 4235 snps,dis_u2_susphy_quirk;
4670 snps,dis_enbl 4236 snps,dis_enblslpm_quirk;
4671 phys = <&usb_ 4237 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
4672 phy-names = " 4238 phy-names = "usb2-phy", "usb3-phy";
4673 4239
4674 ports { 4240 ports {
4675 #addr 4241 #address-cells = <1>;
4676 #size 4242 #size-cells = <0>;
4677 4243
4678 port@ 4244 port@0 {
4679 4245 reg = <0>;
4680 4246
4681 4247 usb_1_dwc3_hs: endpoint {
4682 4248 };
4683 }; 4249 };
4684 4250
4685 port@ 4251 port@1 {
4686 4252 reg = <1>;
4687 4253
4688 4254 usb_1_dwc3_ss: endpoint {
4689 <<
4690 4255 };
4691 }; 4256 };
4692 }; 4257 };
4693 }; 4258 };
4694 }; 4259 };
4695 4260
4696 nsp_noc: interconnect@320c000 4261 nsp_noc: interconnect@320c0000 {
4697 compatible = "qcom,sm 4262 compatible = "qcom,sm8450-nsp-noc";
4698 reg = <0 0x320c0000 0 4263 reg = <0 0x320c0000 0 0x10000>;
4699 #interconnect-cells = 4264 #interconnect-cells = <2>;
4700 qcom,bcm-voters = <&a 4265 qcom,bcm-voters = <&apps_bcm_voter>;
4701 }; 4266 };
4702 4267
4703 lpass_ag_noc: interconnect@3c 4268 lpass_ag_noc: interconnect@3c40000 {
4704 compatible = "qcom,sm 4269 compatible = "qcom,sm8450-lpass-ag-noc";
4705 reg = <0 0x03c40000 0 4270 reg = <0 0x03c40000 0 0x17200>;
4706 #interconnect-cells = 4271 #interconnect-cells = <2>;
4707 qcom,bcm-voters = <&a 4272 qcom,bcm-voters = <&apps_bcm_voter>;
4708 }; 4273 };
4709 }; 4274 };
4710 4275
4711 sound: sound { 4276 sound: sound {
4712 }; 4277 };
4713 4278
4714 thermal-zones { 4279 thermal-zones {
4715 aoss0-thermal { 4280 aoss0-thermal {
>> 4281 polling-delay-passive = <0>;
>> 4282 polling-delay = <0>;
4716 thermal-sensors = <&t 4283 thermal-sensors = <&tsens0 0>;
4717 4284
4718 trips { 4285 trips {
4719 thermal-engin 4286 thermal-engine-config {
4720 tempe 4287 temperature = <125000>;
4721 hyste 4288 hysteresis = <1000>;
4722 type 4289 type = "passive";
4723 }; 4290 };
4724 4291
4725 reset-mon-cfg 4292 reset-mon-cfg {
4726 tempe 4293 temperature = <115000>;
4727 hyste 4294 hysteresis = <5000>;
4728 type 4295 type = "passive";
4729 }; 4296 };
4730 }; 4297 };
4731 }; 4298 };
4732 4299
4733 cpuss0-thermal { 4300 cpuss0-thermal {
>> 4301 polling-delay-passive = <0>;
>> 4302 polling-delay = <0>;
4734 thermal-sensors = <&t 4303 thermal-sensors = <&tsens0 1>;
4735 4304
4736 trips { 4305 trips {
4737 thermal-engin 4306 thermal-engine-config {
4738 tempe 4307 temperature = <125000>;
4739 hyste 4308 hysteresis = <1000>;
4740 type 4309 type = "passive";
4741 }; 4310 };
4742 4311
4743 reset-mon-cfg 4312 reset-mon-cfg {
4744 tempe 4313 temperature = <115000>;
4745 hyste 4314 hysteresis = <5000>;
4746 type 4315 type = "passive";
4747 }; 4316 };
4748 }; 4317 };
4749 }; 4318 };
4750 4319
4751 cpuss1-thermal { 4320 cpuss1-thermal {
>> 4321 polling-delay-passive = <0>;
>> 4322 polling-delay = <0>;
4752 thermal-sensors = <&t 4323 thermal-sensors = <&tsens0 2>;
4753 4324
4754 trips { 4325 trips {
4755 thermal-engin 4326 thermal-engine-config {
4756 tempe 4327 temperature = <125000>;
4757 hyste 4328 hysteresis = <1000>;
4758 type 4329 type = "passive";
4759 }; 4330 };
4760 4331
4761 reset-mon-cfg 4332 reset-mon-cfg {
4762 tempe 4333 temperature = <115000>;
4763 hyste 4334 hysteresis = <5000>;
4764 type 4335 type = "passive";
4765 }; 4336 };
4766 }; 4337 };
4767 }; 4338 };
4768 4339
4769 cpuss3-thermal { 4340 cpuss3-thermal {
>> 4341 polling-delay-passive = <0>;
>> 4342 polling-delay = <0>;
4770 thermal-sensors = <&t 4343 thermal-sensors = <&tsens0 3>;
4771 4344
4772 trips { 4345 trips {
4773 thermal-engin 4346 thermal-engine-config {
4774 tempe 4347 temperature = <125000>;
4775 hyste 4348 hysteresis = <1000>;
4776 type 4349 type = "passive";
4777 }; 4350 };
4778 4351
4779 reset-mon-cfg 4352 reset-mon-cfg {
4780 tempe 4353 temperature = <115000>;
4781 hyste 4354 hysteresis = <5000>;
4782 type 4355 type = "passive";
4783 }; 4356 };
4784 }; 4357 };
4785 }; 4358 };
4786 4359
4787 cpuss4-thermal { 4360 cpuss4-thermal {
>> 4361 polling-delay-passive = <0>;
>> 4362 polling-delay = <0>;
4788 thermal-sensors = <&t 4363 thermal-sensors = <&tsens0 4>;
4789 4364
4790 trips { 4365 trips {
4791 thermal-engin 4366 thermal-engine-config {
4792 tempe 4367 temperature = <125000>;
4793 hyste 4368 hysteresis = <1000>;
4794 type 4369 type = "passive";
4795 }; 4370 };
4796 4371
4797 reset-mon-cfg 4372 reset-mon-cfg {
4798 tempe 4373 temperature = <115000>;
4799 hyste 4374 hysteresis = <5000>;
4800 type 4375 type = "passive";
4801 }; 4376 };
4802 }; 4377 };
4803 }; 4378 };
4804 4379
4805 cpu4-top-thermal { 4380 cpu4-top-thermal {
>> 4381 polling-delay-passive = <0>;
>> 4382 polling-delay = <0>;
4806 thermal-sensors = <&t 4383 thermal-sensors = <&tsens0 5>;
4807 4384
4808 trips { 4385 trips {
4809 cpu4_top_aler 4386 cpu4_top_alert0: trip-point0 {
4810 tempe 4387 temperature = <90000>;
4811 hyste 4388 hysteresis = <2000>;
4812 type 4389 type = "passive";
4813 }; 4390 };
4814 4391
4815 cpu4_top_aler 4392 cpu4_top_alert1: trip-point1 {
4816 tempe 4393 temperature = <95000>;
4817 hyste 4394 hysteresis = <2000>;
4818 type 4395 type = "passive";
4819 }; 4396 };
4820 4397
4821 cpu4_top_crit 4398 cpu4_top_crit: cpu-crit {
4822 tempe 4399 temperature = <110000>;
4823 hyste 4400 hysteresis = <1000>;
4824 type 4401 type = "critical";
4825 }; 4402 };
4826 }; 4403 };
4827 }; 4404 };
4828 4405
4829 cpu4-bottom-thermal { 4406 cpu4-bottom-thermal {
>> 4407 polling-delay-passive = <0>;
>> 4408 polling-delay = <0>;
4830 thermal-sensors = <&t 4409 thermal-sensors = <&tsens0 6>;
4831 4410
4832 trips { 4411 trips {
4833 cpu4_bottom_a 4412 cpu4_bottom_alert0: trip-point0 {
4834 tempe 4413 temperature = <90000>;
4835 hyste 4414 hysteresis = <2000>;
4836 type 4415 type = "passive";
4837 }; 4416 };
4838 4417
4839 cpu4_bottom_a 4418 cpu4_bottom_alert1: trip-point1 {
4840 tempe 4419 temperature = <95000>;
4841 hyste 4420 hysteresis = <2000>;
4842 type 4421 type = "passive";
4843 }; 4422 };
4844 4423
4845 cpu4_bottom_c 4424 cpu4_bottom_crit: cpu-crit {
4846 tempe 4425 temperature = <110000>;
4847 hyste 4426 hysteresis = <1000>;
4848 type 4427 type = "critical";
4849 }; 4428 };
4850 }; 4429 };
4851 }; 4430 };
4852 4431
4853 cpu5-top-thermal { 4432 cpu5-top-thermal {
>> 4433 polling-delay-passive = <0>;
>> 4434 polling-delay = <0>;
4854 thermal-sensors = <&t 4435 thermal-sensors = <&tsens0 7>;
4855 4436
4856 trips { 4437 trips {
4857 cpu5_top_aler 4438 cpu5_top_alert0: trip-point0 {
4858 tempe 4439 temperature = <90000>;
4859 hyste 4440 hysteresis = <2000>;
4860 type 4441 type = "passive";
4861 }; 4442 };
4862 4443
4863 cpu5_top_aler 4444 cpu5_top_alert1: trip-point1 {
4864 tempe 4445 temperature = <95000>;
4865 hyste 4446 hysteresis = <2000>;
4866 type 4447 type = "passive";
4867 }; 4448 };
4868 4449
4869 cpu5_top_crit 4450 cpu5_top_crit: cpu-crit {
4870 tempe 4451 temperature = <110000>;
4871 hyste 4452 hysteresis = <1000>;
4872 type 4453 type = "critical";
4873 }; 4454 };
4874 }; 4455 };
4875 }; 4456 };
4876 4457
4877 cpu5-bottom-thermal { 4458 cpu5-bottom-thermal {
>> 4459 polling-delay-passive = <0>;
>> 4460 polling-delay = <0>;
4878 thermal-sensors = <&t 4461 thermal-sensors = <&tsens0 8>;
4879 4462
4880 trips { 4463 trips {
4881 cpu5_bottom_a 4464 cpu5_bottom_alert0: trip-point0 {
4882 tempe 4465 temperature = <90000>;
4883 hyste 4466 hysteresis = <2000>;
4884 type 4467 type = "passive";
4885 }; 4468 };
4886 4469
4887 cpu5_bottom_a 4470 cpu5_bottom_alert1: trip-point1 {
4888 tempe 4471 temperature = <95000>;
4889 hyste 4472 hysteresis = <2000>;
4890 type 4473 type = "passive";
4891 }; 4474 };
4892 4475
4893 cpu5_bottom_c 4476 cpu5_bottom_crit: cpu-crit {
4894 tempe 4477 temperature = <110000>;
4895 hyste 4478 hysteresis = <1000>;
4896 type 4479 type = "critical";
4897 }; 4480 };
4898 }; 4481 };
4899 }; 4482 };
4900 4483
4901 cpu6-top-thermal { 4484 cpu6-top-thermal {
>> 4485 polling-delay-passive = <0>;
>> 4486 polling-delay = <0>;
4902 thermal-sensors = <&t 4487 thermal-sensors = <&tsens0 9>;
4903 4488
4904 trips { 4489 trips {
4905 cpu6_top_aler 4490 cpu6_top_alert0: trip-point0 {
4906 tempe 4491 temperature = <90000>;
4907 hyste 4492 hysteresis = <2000>;
4908 type 4493 type = "passive";
4909 }; 4494 };
4910 4495
4911 cpu6_top_aler 4496 cpu6_top_alert1: trip-point1 {
4912 tempe 4497 temperature = <95000>;
4913 hyste 4498 hysteresis = <2000>;
4914 type 4499 type = "passive";
4915 }; 4500 };
4916 4501
4917 cpu6_top_crit 4502 cpu6_top_crit: cpu-crit {
4918 tempe 4503 temperature = <110000>;
4919 hyste 4504 hysteresis = <1000>;
4920 type 4505 type = "critical";
4921 }; 4506 };
4922 }; 4507 };
4923 }; 4508 };
4924 4509
4925 cpu6-bottom-thermal { 4510 cpu6-bottom-thermal {
>> 4511 polling-delay-passive = <0>;
>> 4512 polling-delay = <0>;
4926 thermal-sensors = <&t 4513 thermal-sensors = <&tsens0 10>;
4927 4514
4928 trips { 4515 trips {
4929 cpu6_bottom_a 4516 cpu6_bottom_alert0: trip-point0 {
4930 tempe 4517 temperature = <90000>;
4931 hyste 4518 hysteresis = <2000>;
4932 type 4519 type = "passive";
4933 }; 4520 };
4934 4521
4935 cpu6_bottom_a 4522 cpu6_bottom_alert1: trip-point1 {
4936 tempe 4523 temperature = <95000>;
4937 hyste 4524 hysteresis = <2000>;
4938 type 4525 type = "passive";
4939 }; 4526 };
4940 4527
4941 cpu6_bottom_c 4528 cpu6_bottom_crit: cpu-crit {
4942 tempe 4529 temperature = <110000>;
4943 hyste 4530 hysteresis = <1000>;
4944 type 4531 type = "critical";
4945 }; 4532 };
4946 }; 4533 };
4947 }; 4534 };
4948 4535
4949 cpu7-top-thermal { 4536 cpu7-top-thermal {
>> 4537 polling-delay-passive = <0>;
>> 4538 polling-delay = <0>;
4950 thermal-sensors = <&t 4539 thermal-sensors = <&tsens0 11>;
4951 4540
4952 trips { 4541 trips {
4953 cpu7_top_aler 4542 cpu7_top_alert0: trip-point0 {
4954 tempe 4543 temperature = <90000>;
4955 hyste 4544 hysteresis = <2000>;
4956 type 4545 type = "passive";
4957 }; 4546 };
4958 4547
4959 cpu7_top_aler 4548 cpu7_top_alert1: trip-point1 {
4960 tempe 4549 temperature = <95000>;
4961 hyste 4550 hysteresis = <2000>;
4962 type 4551 type = "passive";
4963 }; 4552 };
4964 4553
4965 cpu7_top_crit 4554 cpu7_top_crit: cpu-crit {
4966 tempe 4555 temperature = <110000>;
4967 hyste 4556 hysteresis = <1000>;
4968 type 4557 type = "critical";
4969 }; 4558 };
4970 }; 4559 };
4971 }; 4560 };
4972 4561
4973 cpu7-middle-thermal { 4562 cpu7-middle-thermal {
>> 4563 polling-delay-passive = <0>;
>> 4564 polling-delay = <0>;
4974 thermal-sensors = <&t 4565 thermal-sensors = <&tsens0 12>;
4975 4566
4976 trips { 4567 trips {
4977 cpu7_middle_a 4568 cpu7_middle_alert0: trip-point0 {
4978 tempe 4569 temperature = <90000>;
4979 hyste 4570 hysteresis = <2000>;
4980 type 4571 type = "passive";
4981 }; 4572 };
4982 4573
4983 cpu7_middle_a 4574 cpu7_middle_alert1: trip-point1 {
4984 tempe 4575 temperature = <95000>;
4985 hyste 4576 hysteresis = <2000>;
4986 type 4577 type = "passive";
4987 }; 4578 };
4988 4579
4989 cpu7_middle_c 4580 cpu7_middle_crit: cpu-crit {
4990 tempe 4581 temperature = <110000>;
4991 hyste 4582 hysteresis = <1000>;
4992 type 4583 type = "critical";
4993 }; 4584 };
4994 }; 4585 };
4995 }; 4586 };
4996 4587
4997 cpu7-bottom-thermal { 4588 cpu7-bottom-thermal {
>> 4589 polling-delay-passive = <0>;
>> 4590 polling-delay = <0>;
4998 thermal-sensors = <&t 4591 thermal-sensors = <&tsens0 13>;
4999 4592
5000 trips { 4593 trips {
5001 cpu7_bottom_a 4594 cpu7_bottom_alert0: trip-point0 {
5002 tempe 4595 temperature = <90000>;
5003 hyste 4596 hysteresis = <2000>;
5004 type 4597 type = "passive";
5005 }; 4598 };
5006 4599
5007 cpu7_bottom_a 4600 cpu7_bottom_alert1: trip-point1 {
5008 tempe 4601 temperature = <95000>;
5009 hyste 4602 hysteresis = <2000>;
5010 type 4603 type = "passive";
5011 }; 4604 };
5012 4605
5013 cpu7_bottom_c 4606 cpu7_bottom_crit: cpu-crit {
5014 tempe 4607 temperature = <110000>;
5015 hyste 4608 hysteresis = <1000>;
5016 type 4609 type = "critical";
5017 }; 4610 };
5018 }; 4611 };
5019 }; 4612 };
5020 4613
5021 gpu-top-thermal { 4614 gpu-top-thermal {
5022 polling-delay-passive 4615 polling-delay-passive = <10>;
5023 !! 4616 polling-delay = <0>;
5024 thermal-sensors = <&t 4617 thermal-sensors = <&tsens0 14>;
5025 4618
5026 cooling-maps { <<
5027 map0 { <<
5028 trip <<
5029 cooli <<
5030 }; <<
5031 }; <<
5032 <<
5033 trips { 4619 trips {
5034 gpu_top_alert !! 4620 thermal-engine-config {
5035 tempe !! 4621 temperature = <125000>;
5036 hyste 4622 hysteresis = <1000>;
5037 type 4623 type = "passive";
5038 }; 4624 };
5039 4625
5040 trip-point1 { !! 4626 thermal-hal-config {
5041 tempe !! 4627 temperature = <125000>;
5042 hyste 4628 hysteresis = <1000>;
5043 type !! 4629 type = "passive";
5044 }; 4630 };
5045 4631
5046 trip-point2 { !! 4632 reset-mon-cfg {
5047 tempe !! 4633 temperature = <115000>;
5048 hyste !! 4634 hysteresis = <5000>;
5049 type !! 4635 type = "passive";
>> 4636 };
>> 4637
>> 4638 gpu0_tj_cfg: tj-cfg {
>> 4639 temperature = <95000>;
>> 4640 hysteresis = <5000>;
>> 4641 type = "passive";
5050 }; 4642 };
5051 }; 4643 };
5052 }; 4644 };
5053 4645
5054 gpu-bottom-thermal { 4646 gpu-bottom-thermal {
5055 polling-delay-passive 4647 polling-delay-passive = <10>;
5056 !! 4648 polling-delay = <0>;
5057 thermal-sensors = <&t 4649 thermal-sensors = <&tsens0 15>;
5058 4650
5059 cooling-maps { <<
5060 map0 { <<
5061 trip <<
5062 cooli <<
5063 }; <<
5064 }; <<
5065 <<
5066 trips { 4651 trips {
5067 gpu_bottom_al !! 4652 thermal-engine-config {
5068 tempe !! 4653 temperature = <125000>;
5069 hyste 4654 hysteresis = <1000>;
5070 type 4655 type = "passive";
5071 }; 4656 };
5072 4657
5073 trip-point1 { !! 4658 thermal-hal-config {
5074 tempe !! 4659 temperature = <125000>;
5075 hyste 4660 hysteresis = <1000>;
5076 type !! 4661 type = "passive";
5077 }; 4662 };
5078 4663
5079 trip-point2 { !! 4664 reset-mon-cfg {
5080 tempe !! 4665 temperature = <115000>;
5081 hyste !! 4666 hysteresis = <5000>;
5082 type !! 4667 type = "passive";
>> 4668 };
>> 4669
>> 4670 gpu1_tj_cfg: tj-cfg {
>> 4671 temperature = <95000>;
>> 4672 hysteresis = <5000>;
>> 4673 type = "passive";
5083 }; 4674 };
5084 }; 4675 };
5085 }; 4676 };
5086 4677
5087 aoss1-thermal { 4678 aoss1-thermal {
>> 4679 polling-delay-passive = <0>;
>> 4680 polling-delay = <0>;
5088 thermal-sensors = <&t 4681 thermal-sensors = <&tsens1 0>;
5089 4682
5090 trips { 4683 trips {
5091 thermal-engin 4684 thermal-engine-config {
5092 tempe 4685 temperature = <125000>;
5093 hyste 4686 hysteresis = <1000>;
5094 type 4687 type = "passive";
5095 }; 4688 };
5096 4689
5097 reset-mon-cfg 4690 reset-mon-cfg {
5098 tempe 4691 temperature = <115000>;
5099 hyste 4692 hysteresis = <5000>;
5100 type 4693 type = "passive";
5101 }; 4694 };
5102 }; 4695 };
5103 }; 4696 };
5104 4697
5105 cpu0-thermal { 4698 cpu0-thermal {
>> 4699 polling-delay-passive = <0>;
>> 4700 polling-delay = <0>;
5106 thermal-sensors = <&t 4701 thermal-sensors = <&tsens1 1>;
5107 4702
5108 trips { 4703 trips {
5109 cpu0_alert0: 4704 cpu0_alert0: trip-point0 {
5110 tempe 4705 temperature = <90000>;
5111 hyste 4706 hysteresis = <2000>;
5112 type 4707 type = "passive";
5113 }; 4708 };
5114 4709
5115 cpu0_alert1: 4710 cpu0_alert1: trip-point1 {
5116 tempe 4711 temperature = <95000>;
5117 hyste 4712 hysteresis = <2000>;
5118 type 4713 type = "passive";
5119 }; 4714 };
5120 4715
5121 cpu0_crit: cp 4716 cpu0_crit: cpu-crit {
5122 tempe 4717 temperature = <110000>;
5123 hyste 4718 hysteresis = <1000>;
5124 type 4719 type = "critical";
5125 }; 4720 };
5126 }; 4721 };
5127 }; 4722 };
5128 4723
5129 cpu1-thermal { 4724 cpu1-thermal {
>> 4725 polling-delay-passive = <0>;
>> 4726 polling-delay = <0>;
5130 thermal-sensors = <&t 4727 thermal-sensors = <&tsens1 2>;
5131 4728
5132 trips { 4729 trips {
5133 cpu1_alert0: 4730 cpu1_alert0: trip-point0 {
5134 tempe 4731 temperature = <90000>;
5135 hyste 4732 hysteresis = <2000>;
5136 type 4733 type = "passive";
5137 }; 4734 };
5138 4735
5139 cpu1_alert1: 4736 cpu1_alert1: trip-point1 {
5140 tempe 4737 temperature = <95000>;
5141 hyste 4738 hysteresis = <2000>;
5142 type 4739 type = "passive";
5143 }; 4740 };
5144 4741
5145 cpu1_crit: cp 4742 cpu1_crit: cpu-crit {
5146 tempe 4743 temperature = <110000>;
5147 hyste 4744 hysteresis = <1000>;
5148 type 4745 type = "critical";
5149 }; 4746 };
5150 }; 4747 };
5151 }; 4748 };
5152 4749
5153 cpu2-thermal { 4750 cpu2-thermal {
>> 4751 polling-delay-passive = <0>;
>> 4752 polling-delay = <0>;
5154 thermal-sensors = <&t 4753 thermal-sensors = <&tsens1 3>;
5155 4754
5156 trips { 4755 trips {
5157 cpu2_alert0: 4756 cpu2_alert0: trip-point0 {
5158 tempe 4757 temperature = <90000>;
5159 hyste 4758 hysteresis = <2000>;
5160 type 4759 type = "passive";
5161 }; 4760 };
5162 4761
5163 cpu2_alert1: 4762 cpu2_alert1: trip-point1 {
5164 tempe 4763 temperature = <95000>;
5165 hyste 4764 hysteresis = <2000>;
5166 type 4765 type = "passive";
5167 }; 4766 };
5168 4767
5169 cpu2_crit: cp 4768 cpu2_crit: cpu-crit {
5170 tempe 4769 temperature = <110000>;
5171 hyste 4770 hysteresis = <1000>;
5172 type 4771 type = "critical";
5173 }; 4772 };
5174 }; 4773 };
5175 }; 4774 };
5176 4775
5177 cpu3-thermal { 4776 cpu3-thermal {
>> 4777 polling-delay-passive = <0>;
>> 4778 polling-delay = <0>;
5178 thermal-sensors = <&t 4779 thermal-sensors = <&tsens1 4>;
5179 4780
5180 trips { 4781 trips {
5181 cpu3_alert0: 4782 cpu3_alert0: trip-point0 {
5182 tempe 4783 temperature = <90000>;
5183 hyste 4784 hysteresis = <2000>;
5184 type 4785 type = "passive";
5185 }; 4786 };
5186 4787
5187 cpu3_alert1: 4788 cpu3_alert1: trip-point1 {
5188 tempe 4789 temperature = <95000>;
5189 hyste 4790 hysteresis = <2000>;
5190 type 4791 type = "passive";
5191 }; 4792 };
5192 4793
5193 cpu3_crit: cp 4794 cpu3_crit: cpu-crit {
5194 tempe 4795 temperature = <110000>;
5195 hyste 4796 hysteresis = <1000>;
5196 type 4797 type = "critical";
5197 }; 4798 };
5198 }; 4799 };
5199 }; 4800 };
5200 4801
5201 cdsp0-thermal { 4802 cdsp0-thermal {
5202 polling-delay-passive 4803 polling-delay-passive = <10>;
5203 !! 4804 polling-delay = <0>;
5204 thermal-sensors = <&t 4805 thermal-sensors = <&tsens1 5>;
5205 4806
5206 trips { 4807 trips {
5207 thermal-engin 4808 thermal-engine-config {
5208 tempe 4809 temperature = <125000>;
5209 hyste 4810 hysteresis = <1000>;
5210 type 4811 type = "passive";
5211 }; 4812 };
5212 4813
5213 thermal-hal-c 4814 thermal-hal-config {
5214 tempe 4815 temperature = <125000>;
5215 hyste 4816 hysteresis = <1000>;
5216 type 4817 type = "passive";
5217 }; 4818 };
5218 4819
5219 reset-mon-cfg 4820 reset-mon-cfg {
5220 tempe 4821 temperature = <115000>;
5221 hyste 4822 hysteresis = <5000>;
5222 type 4823 type = "passive";
5223 }; 4824 };
5224 4825
5225 cdsp_0_config 4826 cdsp_0_config: junction-config {
5226 tempe 4827 temperature = <95000>;
5227 hyste 4828 hysteresis = <5000>;
5228 type 4829 type = "passive";
5229 }; 4830 };
5230 }; 4831 };
5231 }; 4832 };
5232 4833
5233 cdsp1-thermal { 4834 cdsp1-thermal {
5234 polling-delay-passive 4835 polling-delay-passive = <10>;
5235 !! 4836 polling-delay = <0>;
5236 thermal-sensors = <&t 4837 thermal-sensors = <&tsens1 6>;
5237 4838
5238 trips { 4839 trips {
5239 thermal-engin 4840 thermal-engine-config {
5240 tempe 4841 temperature = <125000>;
5241 hyste 4842 hysteresis = <1000>;
5242 type 4843 type = "passive";
5243 }; 4844 };
5244 4845
5245 thermal-hal-c 4846 thermal-hal-config {
5246 tempe 4847 temperature = <125000>;
5247 hyste 4848 hysteresis = <1000>;
5248 type 4849 type = "passive";
5249 }; 4850 };
5250 4851
5251 reset-mon-cfg 4852 reset-mon-cfg {
5252 tempe 4853 temperature = <115000>;
5253 hyste 4854 hysteresis = <5000>;
5254 type 4855 type = "passive";
5255 }; 4856 };
5256 4857
5257 cdsp_1_config 4858 cdsp_1_config: junction-config {
5258 tempe 4859 temperature = <95000>;
5259 hyste 4860 hysteresis = <5000>;
5260 type 4861 type = "passive";
5261 }; 4862 };
5262 }; 4863 };
5263 }; 4864 };
5264 4865
5265 cdsp2-thermal { 4866 cdsp2-thermal {
5266 polling-delay-passive 4867 polling-delay-passive = <10>;
5267 !! 4868 polling-delay = <0>;
5268 thermal-sensors = <&t 4869 thermal-sensors = <&tsens1 7>;
5269 4870
5270 trips { 4871 trips {
5271 thermal-engin 4872 thermal-engine-config {
5272 tempe 4873 temperature = <125000>;
5273 hyste 4874 hysteresis = <1000>;
5274 type 4875 type = "passive";
5275 }; 4876 };
5276 4877
5277 thermal-hal-c 4878 thermal-hal-config {
5278 tempe 4879 temperature = <125000>;
5279 hyste 4880 hysteresis = <1000>;
5280 type 4881 type = "passive";
5281 }; 4882 };
5282 4883
5283 reset-mon-cfg 4884 reset-mon-cfg {
5284 tempe 4885 temperature = <115000>;
5285 hyste 4886 hysteresis = <5000>;
5286 type 4887 type = "passive";
5287 }; 4888 };
5288 4889
5289 cdsp_2_config 4890 cdsp_2_config: junction-config {
5290 tempe 4891 temperature = <95000>;
5291 hyste 4892 hysteresis = <5000>;
5292 type 4893 type = "passive";
5293 }; 4894 };
5294 }; 4895 };
5295 }; 4896 };
5296 4897
5297 video-thermal { 4898 video-thermal {
>> 4899 polling-delay-passive = <0>;
>> 4900 polling-delay = <0>;
5298 thermal-sensors = <&t 4901 thermal-sensors = <&tsens1 8>;
5299 4902
5300 trips { 4903 trips {
5301 thermal-engin 4904 thermal-engine-config {
5302 tempe 4905 temperature = <125000>;
5303 hyste 4906 hysteresis = <1000>;
5304 type 4907 type = "passive";
5305 }; 4908 };
5306 4909
5307 reset-mon-cfg 4910 reset-mon-cfg {
5308 tempe 4911 temperature = <115000>;
5309 hyste 4912 hysteresis = <5000>;
5310 type 4913 type = "passive";
5311 }; 4914 };
5312 }; 4915 };
5313 }; 4916 };
5314 4917
5315 mem-thermal { 4918 mem-thermal {
5316 polling-delay-passive 4919 polling-delay-passive = <10>;
5317 !! 4920 polling-delay = <0>;
5318 thermal-sensors = <&t 4921 thermal-sensors = <&tsens1 9>;
5319 4922
5320 trips { 4923 trips {
5321 thermal-engin 4924 thermal-engine-config {
5322 tempe 4925 temperature = <125000>;
5323 hyste 4926 hysteresis = <1000>;
5324 type 4927 type = "passive";
5325 }; 4928 };
5326 4929
5327 ddr_config0: 4930 ddr_config0: ddr0-config {
5328 tempe 4931 temperature = <90000>;
5329 hyste 4932 hysteresis = <5000>;
5330 type 4933 type = "passive";
5331 }; 4934 };
5332 4935
5333 reset-mon-cfg 4936 reset-mon-cfg {
5334 tempe 4937 temperature = <115000>;
5335 hyste 4938 hysteresis = <5000>;
5336 type 4939 type = "passive";
5337 }; 4940 };
5338 }; 4941 };
5339 }; 4942 };
5340 4943
5341 modem0-thermal { 4944 modem0-thermal {
>> 4945 polling-delay-passive = <0>;
>> 4946 polling-delay = <0>;
5342 thermal-sensors = <&t 4947 thermal-sensors = <&tsens1 10>;
5343 4948
5344 trips { 4949 trips {
5345 thermal-engin 4950 thermal-engine-config {
5346 tempe 4951 temperature = <125000>;
5347 hyste 4952 hysteresis = <1000>;
5348 type 4953 type = "passive";
5349 }; 4954 };
5350 4955
5351 mdmss0_config 4956 mdmss0_config0: mdmss0-config0 {
5352 tempe 4957 temperature = <102000>;
5353 hyste 4958 hysteresis = <3000>;
5354 type 4959 type = "passive";
5355 }; 4960 };
5356 4961
5357 mdmss0_config 4962 mdmss0_config1: mdmss0-config1 {
5358 tempe 4963 temperature = <105000>;
5359 hyste 4964 hysteresis = <3000>;
5360 type 4965 type = "passive";
5361 }; 4966 };
5362 4967
5363 reset-mon-cfg 4968 reset-mon-cfg {
5364 tempe 4969 temperature = <115000>;
5365 hyste 4970 hysteresis = <5000>;
5366 type 4971 type = "passive";
5367 }; 4972 };
5368 }; 4973 };
5369 }; 4974 };
5370 4975
5371 modem1-thermal { 4976 modem1-thermal {
>> 4977 polling-delay-passive = <0>;
>> 4978 polling-delay = <0>;
5372 thermal-sensors = <&t 4979 thermal-sensors = <&tsens1 11>;
5373 4980
5374 trips { 4981 trips {
5375 thermal-engin 4982 thermal-engine-config {
5376 tempe 4983 temperature = <125000>;
5377 hyste 4984 hysteresis = <1000>;
5378 type 4985 type = "passive";
5379 }; 4986 };
5380 4987
5381 mdmss1_config 4988 mdmss1_config0: mdmss1-config0 {
5382 tempe 4989 temperature = <102000>;
5383 hyste 4990 hysteresis = <3000>;
5384 type 4991 type = "passive";
5385 }; 4992 };
5386 4993
5387 mdmss1_config 4994 mdmss1_config1: mdmss1-config1 {
5388 tempe 4995 temperature = <105000>;
5389 hyste 4996 hysteresis = <3000>;
5390 type 4997 type = "passive";
5391 }; 4998 };
5392 4999
5393 reset-mon-cfg 5000 reset-mon-cfg {
5394 tempe 5001 temperature = <115000>;
5395 hyste 5002 hysteresis = <5000>;
5396 type 5003 type = "passive";
5397 }; 5004 };
5398 }; 5005 };
5399 }; 5006 };
5400 5007
5401 modem2-thermal { 5008 modem2-thermal {
>> 5009 polling-delay-passive = <0>;
>> 5010 polling-delay = <0>;
5402 thermal-sensors = <&t 5011 thermal-sensors = <&tsens1 12>;
5403 5012
5404 trips { 5013 trips {
5405 thermal-engin 5014 thermal-engine-config {
5406 tempe 5015 temperature = <125000>;
5407 hyste 5016 hysteresis = <1000>;
5408 type 5017 type = "passive";
5409 }; 5018 };
5410 5019
5411 mdmss2_config 5020 mdmss2_config0: mdmss2-config0 {
5412 tempe 5021 temperature = <102000>;
5413 hyste 5022 hysteresis = <3000>;
5414 type 5023 type = "passive";
5415 }; 5024 };
5416 5025
5417 mdmss2_config 5026 mdmss2_config1: mdmss2-config1 {
5418 tempe 5027 temperature = <105000>;
5419 hyste 5028 hysteresis = <3000>;
5420 type 5029 type = "passive";
5421 }; 5030 };
5422 5031
5423 reset-mon-cfg 5032 reset-mon-cfg {
5424 tempe 5033 temperature = <115000>;
5425 hyste 5034 hysteresis = <5000>;
5426 type 5035 type = "passive";
5427 }; 5036 };
5428 }; 5037 };
5429 }; 5038 };
5430 5039
5431 modem3-thermal { 5040 modem3-thermal {
>> 5041 polling-delay-passive = <0>;
>> 5042 polling-delay = <0>;
5432 thermal-sensors = <&t 5043 thermal-sensors = <&tsens1 13>;
5433 5044
5434 trips { 5045 trips {
5435 thermal-engin 5046 thermal-engine-config {
5436 tempe 5047 temperature = <125000>;
5437 hyste 5048 hysteresis = <1000>;
5438 type 5049 type = "passive";
5439 }; 5050 };
5440 5051
5441 mdmss3_config 5052 mdmss3_config0: mdmss3-config0 {
5442 tempe 5053 temperature = <102000>;
5443 hyste 5054 hysteresis = <3000>;
5444 type 5055 type = "passive";
5445 }; 5056 };
5446 5057
5447 mdmss3_config 5058 mdmss3_config1: mdmss3-config1 {
5448 tempe 5059 temperature = <105000>;
5449 hyste 5060 hysteresis = <3000>;
5450 type 5061 type = "passive";
5451 }; 5062 };
5452 5063
5453 reset-mon-cfg 5064 reset-mon-cfg {
5454 tempe 5065 temperature = <115000>;
5455 hyste 5066 hysteresis = <5000>;
5456 type 5067 type = "passive";
5457 }; 5068 };
5458 }; 5069 };
5459 }; 5070 };
5460 5071
5461 camera0-thermal { 5072 camera0-thermal {
>> 5073 polling-delay-passive = <0>;
>> 5074 polling-delay = <0>;
5462 thermal-sensors = <&t 5075 thermal-sensors = <&tsens1 14>;
5463 5076
5464 trips { 5077 trips {
5465 thermal-engin 5078 thermal-engine-config {
5466 tempe 5079 temperature = <125000>;
5467 hyste 5080 hysteresis = <1000>;
5468 type 5081 type = "passive";
5469 }; 5082 };
5470 5083
5471 reset-mon-cfg 5084 reset-mon-cfg {
5472 tempe 5085 temperature = <115000>;
5473 hyste 5086 hysteresis = <5000>;
5474 type 5087 type = "passive";
5475 }; 5088 };
5476 }; 5089 };
5477 }; 5090 };
5478 5091
5479 camera1-thermal { 5092 camera1-thermal {
>> 5093 polling-delay-passive = <0>;
>> 5094 polling-delay = <0>;
5480 thermal-sensors = <&t 5095 thermal-sensors = <&tsens1 15>;
5481 5096
5482 trips { 5097 trips {
5483 thermal-engin 5098 thermal-engine-config {
5484 tempe 5099 temperature = <125000>;
5485 hyste 5100 hysteresis = <1000>;
5486 type 5101 type = "passive";
5487 }; 5102 };
5488 5103
5489 reset-mon-cfg 5104 reset-mon-cfg {
5490 tempe 5105 temperature = <115000>;
5491 hyste 5106 hysteresis = <5000>;
5492 type 5107 type = "passive";
5493 }; 5108 };
5494 }; 5109 };
5495 }; 5110 };
5496 }; 5111 };
5497 5112
5498 timer { 5113 timer {
5499 compatible = "arm,armv8-timer 5114 compatible = "arm,armv8-timer";
5500 interrupts = <GIC_PPI 13 (GIC 5115 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5501 <GIC_PPI 14 (GIC 5116 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5502 <GIC_PPI 11 (GIC 5117 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5503 <GIC_PPI 10 (GIC 5118 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
5504 clock-frequency = <19200000>; 5119 clock-frequency = <19200000>;
5505 }; 5120 };
5506 }; 5121 };
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