1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * Copyright (c) 2021, Linaro Limited 3 * Copyright (c) 2021, Linaro Limited
4 */ 4 */
5 5
6 #include <dt-bindings/interrupt-controller/arm 6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-sm8450.h> 7 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
8 #include <dt-bindings/clock/qcom,rpmh.h> 8 #include <dt-bindings/clock/qcom,rpmh.h>
9 #include <dt-bindings/clock/qcom,sm8450-camcc. 9 #include <dt-bindings/clock/qcom,sm8450-camcc.h>
10 #include <dt-bindings/clock/qcom,sm8450-dispcc 10 #include <dt-bindings/clock/qcom,sm8450-dispcc.h>
11 #include <dt-bindings/clock/qcom,sm8450-gpucc. <<
12 #include <dt-bindings/clock/qcom,sm8450-videoc 11 #include <dt-bindings/clock/qcom,sm8450-videocc.h>
13 #include <dt-bindings/dma/qcom-gpi.h> 12 #include <dt-bindings/dma/qcom-gpi.h>
14 #include <dt-bindings/firmware/qcom,scm.h> <<
15 #include <dt-bindings/gpio/gpio.h> 13 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/mailbox/qcom-ipcc.h> 14 #include <dt-bindings/mailbox/qcom-ipcc.h>
17 #include <dt-bindings/phy/phy-qcom-qmp.h> 15 #include <dt-bindings/phy/phy-qcom-qmp.h>
18 #include <dt-bindings/power/qcom,rpmhpd.h> <<
19 #include <dt-bindings/power/qcom-rpmpd.h> 16 #include <dt-bindings/power/qcom-rpmpd.h>
20 #include <dt-bindings/interconnect/qcom,icc.h> <<
21 #include <dt-bindings/interconnect/qcom,sm8450 17 #include <dt-bindings/interconnect/qcom,sm8450.h>
22 #include <dt-bindings/reset/qcom,sm8450-gpucc. <<
23 #include <dt-bindings/soc/qcom,gpr.h> 18 #include <dt-bindings/soc/qcom,gpr.h>
24 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 19 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
25 #include <dt-bindings/sound/qcom,q6dsp-lpass-p 20 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
26 #include <dt-bindings/thermal/thermal.h> 21 #include <dt-bindings/thermal/thermal.h>
27 22
28 / { 23 / {
29 interrupt-parent = <&intc>; 24 interrupt-parent = <&intc>;
30 25
31 #address-cells = <2>; 26 #address-cells = <2>;
32 #size-cells = <2>; 27 #size-cells = <2>;
33 28
34 chosen { }; 29 chosen { };
35 30
36 clocks { 31 clocks {
37 xo_board: xo-board { 32 xo_board: xo-board {
38 compatible = "fixed-cl 33 compatible = "fixed-clock";
39 #clock-cells = <0>; 34 #clock-cells = <0>;
40 clock-frequency = <768 35 clock-frequency = <76800000>;
41 }; 36 };
42 37
43 sleep_clk: sleep-clk { 38 sleep_clk: sleep-clk {
44 compatible = "fixed-cl 39 compatible = "fixed-clock";
45 #clock-cells = <0>; 40 #clock-cells = <0>;
46 clock-frequency = <320 41 clock-frequency = <32000>;
47 }; 42 };
48 }; 43 };
49 44
50 cpus { 45 cpus {
51 #address-cells = <2>; 46 #address-cells = <2>;
52 #size-cells = <0>; 47 #size-cells = <0>;
53 48
54 CPU0: cpu@0 { 49 CPU0: cpu@0 {
55 device_type = "cpu"; 50 device_type = "cpu";
56 compatible = "qcom,kry 51 compatible = "qcom,kryo780";
57 reg = <0x0 0x0>; 52 reg = <0x0 0x0>;
58 enable-method = "psci" 53 enable-method = "psci";
59 next-level-cache = <&L 54 next-level-cache = <&L2_0>;
60 power-domains = <&CPU_ 55 power-domains = <&CPU_PD0>;
61 power-domain-names = " 56 power-domain-names = "psci";
62 qcom,freq-domain = <&c 57 qcom,freq-domain = <&cpufreq_hw 0>;
63 #cooling-cells = <2>; 58 #cooling-cells = <2>;
64 clocks = <&cpufreq_hw 59 clocks = <&cpufreq_hw 0>;
65 L2_0: l2-cache { 60 L2_0: l2-cache {
66 compatible = " 61 compatible = "cache";
67 cache-level = 62 cache-level = <2>;
68 cache-unified; 63 cache-unified;
69 next-level-cac 64 next-level-cache = <&L3_0>;
70 L3_0: l3-cache 65 L3_0: l3-cache {
71 compat 66 compatible = "cache";
72 cache- 67 cache-level = <3>;
73 cache- 68 cache-unified;
74 }; 69 };
75 }; 70 };
76 }; 71 };
77 72
78 CPU1: cpu@100 { 73 CPU1: cpu@100 {
79 device_type = "cpu"; 74 device_type = "cpu";
80 compatible = "qcom,kry 75 compatible = "qcom,kryo780";
81 reg = <0x0 0x100>; 76 reg = <0x0 0x100>;
82 enable-method = "psci" 77 enable-method = "psci";
83 next-level-cache = <&L 78 next-level-cache = <&L2_100>;
84 power-domains = <&CPU_ 79 power-domains = <&CPU_PD1>;
85 power-domain-names = " 80 power-domain-names = "psci";
86 qcom,freq-domain = <&c 81 qcom,freq-domain = <&cpufreq_hw 0>;
87 #cooling-cells = <2>; 82 #cooling-cells = <2>;
88 clocks = <&cpufreq_hw 83 clocks = <&cpufreq_hw 0>;
89 L2_100: l2-cache { 84 L2_100: l2-cache {
90 compatible = " 85 compatible = "cache";
91 cache-level = 86 cache-level = <2>;
92 cache-unified; 87 cache-unified;
93 next-level-cac 88 next-level-cache = <&L3_0>;
94 }; 89 };
95 }; 90 };
96 91
97 CPU2: cpu@200 { 92 CPU2: cpu@200 {
98 device_type = "cpu"; 93 device_type = "cpu";
99 compatible = "qcom,kry 94 compatible = "qcom,kryo780";
100 reg = <0x0 0x200>; 95 reg = <0x0 0x200>;
101 enable-method = "psci" 96 enable-method = "psci";
102 next-level-cache = <&L 97 next-level-cache = <&L2_200>;
103 power-domains = <&CPU_ 98 power-domains = <&CPU_PD2>;
104 power-domain-names = " 99 power-domain-names = "psci";
105 qcom,freq-domain = <&c 100 qcom,freq-domain = <&cpufreq_hw 0>;
106 #cooling-cells = <2>; 101 #cooling-cells = <2>;
107 clocks = <&cpufreq_hw 102 clocks = <&cpufreq_hw 0>;
108 L2_200: l2-cache { 103 L2_200: l2-cache {
109 compatible = " 104 compatible = "cache";
110 cache-level = 105 cache-level = <2>;
111 cache-unified; 106 cache-unified;
112 next-level-cac 107 next-level-cache = <&L3_0>;
113 }; 108 };
114 }; 109 };
115 110
116 CPU3: cpu@300 { 111 CPU3: cpu@300 {
117 device_type = "cpu"; 112 device_type = "cpu";
118 compatible = "qcom,kry 113 compatible = "qcom,kryo780";
119 reg = <0x0 0x300>; 114 reg = <0x0 0x300>;
120 enable-method = "psci" 115 enable-method = "psci";
121 next-level-cache = <&L 116 next-level-cache = <&L2_300>;
122 power-domains = <&CPU_ 117 power-domains = <&CPU_PD3>;
123 power-domain-names = " 118 power-domain-names = "psci";
124 qcom,freq-domain = <&c 119 qcom,freq-domain = <&cpufreq_hw 0>;
125 #cooling-cells = <2>; 120 #cooling-cells = <2>;
126 clocks = <&cpufreq_hw 121 clocks = <&cpufreq_hw 0>;
127 L2_300: l2-cache { 122 L2_300: l2-cache {
128 compatible = " 123 compatible = "cache";
129 cache-level = 124 cache-level = <2>;
130 cache-unified; 125 cache-unified;
131 next-level-cac 126 next-level-cache = <&L3_0>;
132 }; 127 };
133 }; 128 };
134 129
135 CPU4: cpu@400 { 130 CPU4: cpu@400 {
136 device_type = "cpu"; 131 device_type = "cpu";
137 compatible = "qcom,kry 132 compatible = "qcom,kryo780";
138 reg = <0x0 0x400>; 133 reg = <0x0 0x400>;
139 enable-method = "psci" 134 enable-method = "psci";
140 next-level-cache = <&L 135 next-level-cache = <&L2_400>;
141 power-domains = <&CPU_ 136 power-domains = <&CPU_PD4>;
142 power-domain-names = " 137 power-domain-names = "psci";
143 qcom,freq-domain = <&c 138 qcom,freq-domain = <&cpufreq_hw 1>;
144 #cooling-cells = <2>; 139 #cooling-cells = <2>;
145 clocks = <&cpufreq_hw 140 clocks = <&cpufreq_hw 1>;
146 L2_400: l2-cache { 141 L2_400: l2-cache {
147 compatible = " 142 compatible = "cache";
148 cache-level = 143 cache-level = <2>;
149 cache-unified; 144 cache-unified;
150 next-level-cac 145 next-level-cache = <&L3_0>;
151 }; 146 };
152 }; 147 };
153 148
154 CPU5: cpu@500 { 149 CPU5: cpu@500 {
155 device_type = "cpu"; 150 device_type = "cpu";
156 compatible = "qcom,kry 151 compatible = "qcom,kryo780";
157 reg = <0x0 0x500>; 152 reg = <0x0 0x500>;
158 enable-method = "psci" 153 enable-method = "psci";
159 next-level-cache = <&L 154 next-level-cache = <&L2_500>;
160 power-domains = <&CPU_ 155 power-domains = <&CPU_PD5>;
161 power-domain-names = " 156 power-domain-names = "psci";
162 qcom,freq-domain = <&c 157 qcom,freq-domain = <&cpufreq_hw 1>;
163 #cooling-cells = <2>; 158 #cooling-cells = <2>;
164 clocks = <&cpufreq_hw 159 clocks = <&cpufreq_hw 1>;
165 L2_500: l2-cache { 160 L2_500: l2-cache {
166 compatible = " 161 compatible = "cache";
167 cache-level = 162 cache-level = <2>;
168 cache-unified; 163 cache-unified;
169 next-level-cac 164 next-level-cache = <&L3_0>;
170 }; 165 };
171 }; 166 };
172 167
173 CPU6: cpu@600 { 168 CPU6: cpu@600 {
174 device_type = "cpu"; 169 device_type = "cpu";
175 compatible = "qcom,kry 170 compatible = "qcom,kryo780";
176 reg = <0x0 0x600>; 171 reg = <0x0 0x600>;
177 enable-method = "psci" 172 enable-method = "psci";
178 next-level-cache = <&L 173 next-level-cache = <&L2_600>;
179 power-domains = <&CPU_ 174 power-domains = <&CPU_PD6>;
180 power-domain-names = " 175 power-domain-names = "psci";
181 qcom,freq-domain = <&c 176 qcom,freq-domain = <&cpufreq_hw 1>;
182 #cooling-cells = <2>; 177 #cooling-cells = <2>;
183 clocks = <&cpufreq_hw 178 clocks = <&cpufreq_hw 1>;
184 L2_600: l2-cache { 179 L2_600: l2-cache {
185 compatible = " 180 compatible = "cache";
186 cache-level = 181 cache-level = <2>;
187 cache-unified; 182 cache-unified;
188 next-level-cac 183 next-level-cache = <&L3_0>;
189 }; 184 };
190 }; 185 };
191 186
192 CPU7: cpu@700 { 187 CPU7: cpu@700 {
193 device_type = "cpu"; 188 device_type = "cpu";
194 compatible = "qcom,kry 189 compatible = "qcom,kryo780";
195 reg = <0x0 0x700>; 190 reg = <0x0 0x700>;
196 enable-method = "psci" 191 enable-method = "psci";
197 next-level-cache = <&L 192 next-level-cache = <&L2_700>;
198 power-domains = <&CPU_ 193 power-domains = <&CPU_PD7>;
199 power-domain-names = " 194 power-domain-names = "psci";
200 qcom,freq-domain = <&c 195 qcom,freq-domain = <&cpufreq_hw 2>;
201 #cooling-cells = <2>; 196 #cooling-cells = <2>;
202 clocks = <&cpufreq_hw 197 clocks = <&cpufreq_hw 2>;
203 L2_700: l2-cache { 198 L2_700: l2-cache {
204 compatible = " 199 compatible = "cache";
205 cache-level = 200 cache-level = <2>;
206 cache-unified; 201 cache-unified;
207 next-level-cac 202 next-level-cache = <&L3_0>;
208 }; 203 };
209 }; 204 };
210 205
211 cpu-map { 206 cpu-map {
212 cluster0 { 207 cluster0 {
213 core0 { 208 core0 {
214 cpu = 209 cpu = <&CPU0>;
215 }; 210 };
216 211
217 core1 { 212 core1 {
218 cpu = 213 cpu = <&CPU1>;
219 }; 214 };
220 215
221 core2 { 216 core2 {
222 cpu = 217 cpu = <&CPU2>;
223 }; 218 };
224 219
225 core3 { 220 core3 {
226 cpu = 221 cpu = <&CPU3>;
227 }; 222 };
228 223
229 core4 { 224 core4 {
230 cpu = 225 cpu = <&CPU4>;
231 }; 226 };
232 227
233 core5 { 228 core5 {
234 cpu = 229 cpu = <&CPU5>;
235 }; 230 };
236 231
237 core6 { 232 core6 {
238 cpu = 233 cpu = <&CPU6>;
239 }; 234 };
240 235
241 core7 { 236 core7 {
242 cpu = 237 cpu = <&CPU7>;
243 }; 238 };
244 }; 239 };
245 }; 240 };
246 241
247 idle-states { 242 idle-states {
248 entry-method = "psci"; 243 entry-method = "psci";
249 244
250 LITTLE_CPU_SLEEP_0: cp 245 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
251 compatible = " 246 compatible = "arm,idle-state";
252 idle-state-nam 247 idle-state-name = "silver-rail-power-collapse";
253 arm,psci-suspe 248 arm,psci-suspend-param = <0x40000004>;
254 entry-latency- 249 entry-latency-us = <800>;
255 exit-latency-u 250 exit-latency-us = <750>;
256 min-residency- 251 min-residency-us = <4090>;
257 local-timer-st 252 local-timer-stop;
258 }; 253 };
259 254
260 BIG_CPU_SLEEP_0: cpu-s 255 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
261 compatible = " 256 compatible = "arm,idle-state";
262 idle-state-nam 257 idle-state-name = "gold-rail-power-collapse";
263 arm,psci-suspe 258 arm,psci-suspend-param = <0x40000004>;
264 entry-latency- 259 entry-latency-us = <600>;
265 exit-latency-u 260 exit-latency-us = <1550>;
266 min-residency- 261 min-residency-us = <4791>;
267 local-timer-st 262 local-timer-stop;
268 }; 263 };
269 }; 264 };
270 265
271 domain-idle-states { 266 domain-idle-states {
272 CLUSTER_SLEEP_0: clust 267 CLUSTER_SLEEP_0: cluster-sleep-0 {
273 compatible = " 268 compatible = "domain-idle-state";
274 arm,psci-suspe 269 arm,psci-suspend-param = <0x41000044>;
275 entry-latency- 270 entry-latency-us = <1050>;
276 exit-latency-u 271 exit-latency-us = <2500>;
277 min-residency- 272 min-residency-us = <5309>;
278 }; 273 };
279 274
280 CLUSTER_SLEEP_1: clust 275 CLUSTER_SLEEP_1: cluster-sleep-1 {
281 compatible = " 276 compatible = "domain-idle-state";
282 arm,psci-suspe 277 arm,psci-suspend-param = <0x4100c344>;
283 entry-latency- 278 entry-latency-us = <2700>;
284 exit-latency-u 279 exit-latency-us = <3500>;
285 min-residency- 280 min-residency-us = <13959>;
286 }; 281 };
287 }; 282 };
288 }; 283 };
289 284
290 firmware { 285 firmware {
291 scm: scm { 286 scm: scm {
292 compatible = "qcom,scm 287 compatible = "qcom,scm-sm8450", "qcom,scm";
293 qcom,dload-mode = <&tc 288 qcom,dload-mode = <&tcsr 0x13000>;
294 interconnects = <&aggr 289 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
295 #reset-cells = <1>; 290 #reset-cells = <1>;
296 }; 291 };
297 }; 292 };
298 293
299 clk_virt: interconnect-0 { 294 clk_virt: interconnect-0 {
300 compatible = "qcom,sm8450-clk- 295 compatible = "qcom,sm8450-clk-virt";
301 #interconnect-cells = <2>; 296 #interconnect-cells = <2>;
302 qcom,bcm-voters = <&apps_bcm_v 297 qcom,bcm-voters = <&apps_bcm_voter>;
303 }; 298 };
304 299
305 mc_virt: interconnect-1 { 300 mc_virt: interconnect-1 {
306 compatible = "qcom,sm8450-mc-v 301 compatible = "qcom,sm8450-mc-virt";
307 #interconnect-cells = <2>; 302 #interconnect-cells = <2>;
308 qcom,bcm-voters = <&apps_bcm_v 303 qcom,bcm-voters = <&apps_bcm_voter>;
309 }; 304 };
310 305
311 memory@a0000000 { 306 memory@a0000000 {
312 device_type = "memory"; 307 device_type = "memory";
313 /* We expect the bootloader to 308 /* We expect the bootloader to fill in the size */
314 reg = <0x0 0xa0000000 0x0 0x0> 309 reg = <0x0 0xa0000000 0x0 0x0>;
315 }; 310 };
316 311
317 pmu { 312 pmu {
318 compatible = "arm,armv8-pmuv3" 313 compatible = "arm,armv8-pmuv3";
319 interrupts = <GIC_PPI 7 IRQ_TY 314 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
320 }; 315 };
321 316
322 psci { 317 psci {
323 compatible = "arm,psci-1.0"; 318 compatible = "arm,psci-1.0";
324 method = "smc"; 319 method = "smc";
325 320
326 CPU_PD0: power-domain-cpu0 { 321 CPU_PD0: power-domain-cpu0 {
327 #power-domain-cells = 322 #power-domain-cells = <0>;
328 power-domains = <&CLUS 323 power-domains = <&CLUSTER_PD>;
329 domain-idle-states = < 324 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
330 }; 325 };
331 326
332 CPU_PD1: power-domain-cpu1 { 327 CPU_PD1: power-domain-cpu1 {
333 #power-domain-cells = 328 #power-domain-cells = <0>;
334 power-domains = <&CLUS 329 power-domains = <&CLUSTER_PD>;
335 domain-idle-states = < 330 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
336 }; 331 };
337 332
338 CPU_PD2: power-domain-cpu2 { 333 CPU_PD2: power-domain-cpu2 {
339 #power-domain-cells = 334 #power-domain-cells = <0>;
340 power-domains = <&CLUS 335 power-domains = <&CLUSTER_PD>;
341 domain-idle-states = < 336 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
342 }; 337 };
343 338
344 CPU_PD3: power-domain-cpu3 { 339 CPU_PD3: power-domain-cpu3 {
345 #power-domain-cells = 340 #power-domain-cells = <0>;
346 power-domains = <&CLUS 341 power-domains = <&CLUSTER_PD>;
347 domain-idle-states = < 342 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
348 }; 343 };
349 344
350 CPU_PD4: power-domain-cpu4 { 345 CPU_PD4: power-domain-cpu4 {
351 #power-domain-cells = 346 #power-domain-cells = <0>;
352 power-domains = <&CLUS 347 power-domains = <&CLUSTER_PD>;
353 domain-idle-states = < 348 domain-idle-states = <&BIG_CPU_SLEEP_0>;
354 }; 349 };
355 350
356 CPU_PD5: power-domain-cpu5 { 351 CPU_PD5: power-domain-cpu5 {
357 #power-domain-cells = 352 #power-domain-cells = <0>;
358 power-domains = <&CLUS 353 power-domains = <&CLUSTER_PD>;
359 domain-idle-states = < 354 domain-idle-states = <&BIG_CPU_SLEEP_0>;
360 }; 355 };
361 356
362 CPU_PD6: power-domain-cpu6 { 357 CPU_PD6: power-domain-cpu6 {
363 #power-domain-cells = 358 #power-domain-cells = <0>;
364 power-domains = <&CLUS 359 power-domains = <&CLUSTER_PD>;
365 domain-idle-states = < 360 domain-idle-states = <&BIG_CPU_SLEEP_0>;
366 }; 361 };
367 362
368 CPU_PD7: power-domain-cpu7 { 363 CPU_PD7: power-domain-cpu7 {
369 #power-domain-cells = 364 #power-domain-cells = <0>;
370 power-domains = <&CLUS 365 power-domains = <&CLUSTER_PD>;
371 domain-idle-states = < 366 domain-idle-states = <&BIG_CPU_SLEEP_0>;
372 }; 367 };
373 368
374 CLUSTER_PD: power-domain-cpu-c 369 CLUSTER_PD: power-domain-cpu-cluster0 {
375 #power-domain-cells = 370 #power-domain-cells = <0>;
376 domain-idle-states = < 371 domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>;
377 }; 372 };
378 }; 373 };
379 374
380 qup_opp_table_100mhz: opp-table-qup { 375 qup_opp_table_100mhz: opp-table-qup {
381 compatible = "operating-points 376 compatible = "operating-points-v2";
382 377
383 opp-50000000 { 378 opp-50000000 {
384 opp-hz = /bits/ 64 <50 379 opp-hz = /bits/ 64 <50000000>;
385 required-opps = <&rpmh 380 required-opps = <&rpmhpd_opp_min_svs>;
386 }; 381 };
387 382
388 opp-75000000 { 383 opp-75000000 {
389 opp-hz = /bits/ 64 <75 384 opp-hz = /bits/ 64 <75000000>;
390 required-opps = <&rpmh 385 required-opps = <&rpmhpd_opp_low_svs>;
391 }; 386 };
392 387
393 opp-100000000 { 388 opp-100000000 {
394 opp-hz = /bits/ 64 <10 389 opp-hz = /bits/ 64 <100000000>;
395 required-opps = <&rpmh 390 required-opps = <&rpmhpd_opp_svs>;
396 }; 391 };
397 }; 392 };
398 393
399 reserved_memory: reserved-memory { 394 reserved_memory: reserved-memory {
400 #address-cells = <2>; 395 #address-cells = <2>;
401 #size-cells = <2>; 396 #size-cells = <2>;
402 ranges; 397 ranges;
403 398
404 hyp_mem: memory@80000000 { 399 hyp_mem: memory@80000000 {
405 reg = <0x0 0x80000000 400 reg = <0x0 0x80000000 0x0 0x600000>;
406 no-map; 401 no-map;
407 }; 402 };
408 403
409 xbl_dt_log_mem: memory@8060000 404 xbl_dt_log_mem: memory@80600000 {
410 reg = <0x0 0x80600000 405 reg = <0x0 0x80600000 0x0 0x40000>;
411 no-map; 406 no-map;
412 }; 407 };
413 408
414 xbl_ramdump_mem: memory@806400 409 xbl_ramdump_mem: memory@80640000 {
415 reg = <0x0 0x80640000 410 reg = <0x0 0x80640000 0x0 0x180000>;
416 no-map; 411 no-map;
417 }; 412 };
418 413
419 xbl_sc_mem: memory@807c0000 { 414 xbl_sc_mem: memory@807c0000 {
420 reg = <0x0 0x807c0000 415 reg = <0x0 0x807c0000 0x0 0x40000>;
421 no-map; 416 no-map;
422 }; 417 };
423 418
424 aop_image_mem: memory@80800000 419 aop_image_mem: memory@80800000 {
425 reg = <0x0 0x80800000 420 reg = <0x0 0x80800000 0x0 0x60000>;
426 no-map; 421 no-map;
427 }; 422 };
428 423
429 aop_cmd_db_mem: memory@8086000 424 aop_cmd_db_mem: memory@80860000 {
430 compatible = "qcom,cmd 425 compatible = "qcom,cmd-db";
431 reg = <0x0 0x80860000 426 reg = <0x0 0x80860000 0x0 0x20000>;
432 no-map; 427 no-map;
433 }; 428 };
434 429
435 aop_config_mem: memory@8088000 430 aop_config_mem: memory@80880000 {
436 reg = <0x0 0x80880000 431 reg = <0x0 0x80880000 0x0 0x20000>;
437 no-map; 432 no-map;
438 }; 433 };
439 434
440 tme_crash_dump_mem: memory@808 435 tme_crash_dump_mem: memory@808a0000 {
441 reg = <0x0 0x808a0000 436 reg = <0x0 0x808a0000 0x0 0x40000>;
442 no-map; 437 no-map;
443 }; 438 };
444 439
445 tme_log_mem: memory@808e0000 { 440 tme_log_mem: memory@808e0000 {
446 reg = <0x0 0x808e0000 441 reg = <0x0 0x808e0000 0x0 0x4000>;
447 no-map; 442 no-map;
448 }; 443 };
449 444
450 uefi_log_mem: memory@808e4000 445 uefi_log_mem: memory@808e4000 {
451 reg = <0x0 0x808e4000 446 reg = <0x0 0x808e4000 0x0 0x10000>;
452 no-map; 447 no-map;
453 }; 448 };
454 449
455 /* secdata region can be reuse 450 /* secdata region can be reused by apps */
456 smem: memory@80900000 { 451 smem: memory@80900000 {
457 compatible = "qcom,sme 452 compatible = "qcom,smem";
458 reg = <0x0 0x80900000 453 reg = <0x0 0x80900000 0x0 0x200000>;
459 hwlocks = <&tcsr_mutex 454 hwlocks = <&tcsr_mutex 3>;
460 no-map; 455 no-map;
461 }; 456 };
462 457
463 cpucp_fw_mem: memory@80b00000 458 cpucp_fw_mem: memory@80b00000 {
464 reg = <0x0 0x80b00000 459 reg = <0x0 0x80b00000 0x0 0x100000>;
465 no-map; 460 no-map;
466 }; 461 };
467 462
468 cdsp_secure_heap: memory@80c00 463 cdsp_secure_heap: memory@80c00000 {
469 reg = <0x0 0x80c00000 464 reg = <0x0 0x80c00000 0x0 0x4600000>;
470 no-map; 465 no-map;
471 }; 466 };
472 467
473 video_mem: memory@85700000 { 468 video_mem: memory@85700000 {
474 reg = <0x0 0x85700000 469 reg = <0x0 0x85700000 0x0 0x700000>;
475 no-map; 470 no-map;
476 }; 471 };
477 472
478 adsp_mem: memory@85e00000 { 473 adsp_mem: memory@85e00000 {
479 reg = <0x0 0x85e00000 474 reg = <0x0 0x85e00000 0x0 0x2100000>;
480 no-map; 475 no-map;
481 }; 476 };
482 477
483 slpi_mem: memory@88000000 { 478 slpi_mem: memory@88000000 {
484 reg = <0x0 0x88000000 479 reg = <0x0 0x88000000 0x0 0x1900000>;
485 no-map; 480 no-map;
486 }; 481 };
487 482
488 cdsp_mem: memory@89900000 { 483 cdsp_mem: memory@89900000 {
489 reg = <0x0 0x89900000 484 reg = <0x0 0x89900000 0x0 0x2000000>;
490 no-map; 485 no-map;
491 }; 486 };
492 487
493 ipa_fw_mem: memory@8b900000 { 488 ipa_fw_mem: memory@8b900000 {
494 reg = <0x0 0x8b900000 489 reg = <0x0 0x8b900000 0x0 0x10000>;
495 no-map; 490 no-map;
496 }; 491 };
497 492
498 ipa_gsi_mem: memory@8b910000 { 493 ipa_gsi_mem: memory@8b910000 {
499 reg = <0x0 0x8b910000 494 reg = <0x0 0x8b910000 0x0 0xa000>;
500 no-map; 495 no-map;
501 }; 496 };
502 497
503 gpu_micro_code_mem: memory@8b9 498 gpu_micro_code_mem: memory@8b91a000 {
504 reg = <0x0 0x8b91a000 499 reg = <0x0 0x8b91a000 0x0 0x2000>;
505 no-map; 500 no-map;
506 }; 501 };
507 502
508 spss_region_mem: memory@8ba000 503 spss_region_mem: memory@8ba00000 {
509 reg = <0x0 0x8ba00000 504 reg = <0x0 0x8ba00000 0x0 0x180000>;
510 no-map; 505 no-map;
511 }; 506 };
512 507
513 /* First part of the "SPU secu 508 /* First part of the "SPU secure shared memory" region */
514 spu_tz_shared_mem: memory@8bb8 509 spu_tz_shared_mem: memory@8bb80000 {
515 reg = <0x0 0x8bb80000 510 reg = <0x0 0x8bb80000 0x0 0x60000>;
516 no-map; 511 no-map;
517 }; 512 };
518 513
519 /* Second part of the "SPU sec 514 /* Second part of the "SPU secure shared memory" region */
520 spu_modem_shared_mem: memory@8 515 spu_modem_shared_mem: memory@8bbe0000 {
521 reg = <0x0 0x8bbe0000 516 reg = <0x0 0x8bbe0000 0x0 0x20000>;
522 no-map; 517 no-map;
523 }; 518 };
524 519
525 mpss_mem: memory@8bc00000 { 520 mpss_mem: memory@8bc00000 {
526 reg = <0x0 0x8bc00000 521 reg = <0x0 0x8bc00000 0x0 0x13200000>;
527 no-map; 522 no-map;
528 }; 523 };
529 524
530 cvp_mem: memory@9ee00000 { 525 cvp_mem: memory@9ee00000 {
531 reg = <0x0 0x9ee00000 526 reg = <0x0 0x9ee00000 0x0 0x700000>;
532 no-map; 527 no-map;
533 }; 528 };
534 529
535 camera_mem: memory@9f500000 { 530 camera_mem: memory@9f500000 {
536 reg = <0x0 0x9f500000 531 reg = <0x0 0x9f500000 0x0 0x800000>;
537 no-map; 532 no-map;
538 }; 533 };
539 534
540 rmtfs_mem: memory@9fd00000 { 535 rmtfs_mem: memory@9fd00000 {
541 compatible = "qcom,rmt 536 compatible = "qcom,rmtfs-mem";
542 reg = <0x0 0x9fd00000 537 reg = <0x0 0x9fd00000 0x0 0x280000>;
543 no-map; 538 no-map;
544 539
545 qcom,client-id = <1>; 540 qcom,client-id = <1>;
546 qcom,vmid = <QCOM_SCM_ !! 541 qcom,vmid = <15>;
547 }; 542 };
548 543
549 xbl_sc_mem2: memory@a6e00000 { 544 xbl_sc_mem2: memory@a6e00000 {
550 reg = <0x0 0xa6e00000 545 reg = <0x0 0xa6e00000 0x0 0x40000>;
551 no-map; 546 no-map;
552 }; 547 };
553 548
554 global_sync_mem: memory@a6f000 549 global_sync_mem: memory@a6f00000 {
555 reg = <0x0 0xa6f00000 550 reg = <0x0 0xa6f00000 0x0 0x100000>;
556 no-map; 551 no-map;
557 }; 552 };
558 553
559 /* uefi region can be reused b 554 /* uefi region can be reused by APPS */
560 555
561 /* Linux kernel image is loade 556 /* Linux kernel image is loaded at 0xa0000000 */
562 557
563 oem_vm_mem: memory@bb000000 { 558 oem_vm_mem: memory@bb000000 {
564 reg = <0x0 0xbb000000 559 reg = <0x0 0xbb000000 0x0 0x5000000>;
565 no-map; 560 no-map;
566 }; 561 };
567 562
568 mte_mem: memory@c0000000 { 563 mte_mem: memory@c0000000 {
569 reg = <0x0 0xc0000000 564 reg = <0x0 0xc0000000 0x0 0x20000000>;
570 no-map; 565 no-map;
571 }; 566 };
572 567
573 qheebsp_reserved_mem: memory@e 568 qheebsp_reserved_mem: memory@e0000000 {
574 reg = <0x0 0xe0000000 569 reg = <0x0 0xe0000000 0x0 0x600000>;
575 no-map; 570 no-map;
576 }; 571 };
577 572
578 cpusys_vm_mem: memory@e0600000 573 cpusys_vm_mem: memory@e0600000 {
579 reg = <0x0 0xe0600000 574 reg = <0x0 0xe0600000 0x0 0x400000>;
580 no-map; 575 no-map;
581 }; 576 };
582 577
583 hyp_reserved_mem: memory@e0a00 578 hyp_reserved_mem: memory@e0a00000 {
584 reg = <0x0 0xe0a00000 579 reg = <0x0 0xe0a00000 0x0 0x100000>;
585 no-map; 580 no-map;
586 }; 581 };
587 582
588 trust_ui_vm_mem: memory@e0b000 583 trust_ui_vm_mem: memory@e0b00000 {
589 reg = <0x0 0xe0b00000 584 reg = <0x0 0xe0b00000 0x0 0x4af3000>;
590 no-map; 585 no-map;
591 }; 586 };
592 587
593 trust_ui_vm_qrtr: memory@e55f3 588 trust_ui_vm_qrtr: memory@e55f3000 {
594 reg = <0x0 0xe55f3000 589 reg = <0x0 0xe55f3000 0x0 0x9000>;
595 no-map; 590 no-map;
596 }; 591 };
597 592
598 trust_ui_vm_vblk0_ring: memory 593 trust_ui_vm_vblk0_ring: memory@e55fc000 {
599 reg = <0x0 0xe55fc000 594 reg = <0x0 0xe55fc000 0x0 0x4000>;
600 no-map; 595 no-map;
601 }; 596 };
602 597
603 trust_ui_vm_swiotlb: memory@e5 598 trust_ui_vm_swiotlb: memory@e5600000 {
604 reg = <0x0 0xe5600000 599 reg = <0x0 0xe5600000 0x0 0x100000>;
605 no-map; 600 no-map;
606 }; 601 };
607 602
608 tz_stat_mem: memory@e8800000 { 603 tz_stat_mem: memory@e8800000 {
609 reg = <0x0 0xe8800000 604 reg = <0x0 0xe8800000 0x0 0x100000>;
610 no-map; 605 no-map;
611 }; 606 };
612 607
613 tags_mem: memory@e8900000 { 608 tags_mem: memory@e8900000 {
614 reg = <0x0 0xe8900000 609 reg = <0x0 0xe8900000 0x0 0x1200000>;
615 no-map; 610 no-map;
616 }; 611 };
617 612
618 qtee_mem: memory@e9b00000 { 613 qtee_mem: memory@e9b00000 {
619 reg = <0x0 0xe9b00000 614 reg = <0x0 0xe9b00000 0x0 0x500000>;
620 no-map; 615 no-map;
621 }; 616 };
622 617
623 trusted_apps_mem: memory@ea000 618 trusted_apps_mem: memory@ea000000 {
624 reg = <0x0 0xea000000 619 reg = <0x0 0xea000000 0x0 0x3900000>;
625 no-map; 620 no-map;
626 }; 621 };
627 622
628 trusted_apps_ext_mem: memory@e 623 trusted_apps_ext_mem: memory@ed900000 {
629 reg = <0x0 0xed900000 624 reg = <0x0 0xed900000 0x0 0x3b00000>;
630 no-map; 625 no-map;
631 }; 626 };
632 }; 627 };
633 628
634 smp2p-adsp { 629 smp2p-adsp {
635 compatible = "qcom,smp2p"; 630 compatible = "qcom,smp2p";
636 qcom,smem = <443>, <429>; 631 qcom,smem = <443>, <429>;
637 interrupts-extended = <&ipcc I 632 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
638 I 633 IPCC_MPROC_SIGNAL_SMP2P
639 I 634 IRQ_TYPE_EDGE_RISING>;
640 mboxes = <&ipcc IPCC_CLIENT_LP 635 mboxes = <&ipcc IPCC_CLIENT_LPASS
641 IPCC_MPROC_SIG 636 IPCC_MPROC_SIGNAL_SMP2P>;
642 637
643 qcom,local-pid = <0>; 638 qcom,local-pid = <0>;
644 qcom,remote-pid = <2>; 639 qcom,remote-pid = <2>;
645 640
646 smp2p_adsp_out: master-kernel 641 smp2p_adsp_out: master-kernel {
647 qcom,entry-name = "mas 642 qcom,entry-name = "master-kernel";
648 #qcom,smem-state-cells 643 #qcom,smem-state-cells = <1>;
649 }; 644 };
650 645
651 smp2p_adsp_in: slave-kernel { 646 smp2p_adsp_in: slave-kernel {
652 qcom,entry-name = "sla 647 qcom,entry-name = "slave-kernel";
653 interrupt-controller; 648 interrupt-controller;
654 #interrupt-cells = <2> 649 #interrupt-cells = <2>;
655 }; 650 };
656 }; 651 };
657 652
658 smp2p-cdsp { 653 smp2p-cdsp {
659 compatible = "qcom,smp2p"; 654 compatible = "qcom,smp2p";
660 qcom,smem = <94>, <432>; 655 qcom,smem = <94>, <432>;
661 interrupts-extended = <&ipcc I 656 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
662 I 657 IPCC_MPROC_SIGNAL_SMP2P
663 I 658 IRQ_TYPE_EDGE_RISING>;
664 mboxes = <&ipcc IPCC_CLIENT_CD 659 mboxes = <&ipcc IPCC_CLIENT_CDSP
665 IPCC_MPROC_SIG 660 IPCC_MPROC_SIGNAL_SMP2P>;
666 661
667 qcom,local-pid = <0>; 662 qcom,local-pid = <0>;
668 qcom,remote-pid = <5>; 663 qcom,remote-pid = <5>;
669 664
670 smp2p_cdsp_out: master-kernel 665 smp2p_cdsp_out: master-kernel {
671 qcom,entry-name = "mas 666 qcom,entry-name = "master-kernel";
672 #qcom,smem-state-cells 667 #qcom,smem-state-cells = <1>;
673 }; 668 };
674 669
675 smp2p_cdsp_in: slave-kernel { 670 smp2p_cdsp_in: slave-kernel {
676 qcom,entry-name = "sla 671 qcom,entry-name = "slave-kernel";
677 interrupt-controller; 672 interrupt-controller;
678 #interrupt-cells = <2> 673 #interrupt-cells = <2>;
679 }; 674 };
680 }; 675 };
681 676
682 smp2p-modem { 677 smp2p-modem {
683 compatible = "qcom,smp2p"; 678 compatible = "qcom,smp2p";
684 qcom,smem = <435>, <428>; 679 qcom,smem = <435>, <428>;
685 interrupts-extended = <&ipcc I 680 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
686 I 681 IPCC_MPROC_SIGNAL_SMP2P
687 I 682 IRQ_TYPE_EDGE_RISING>;
688 mboxes = <&ipcc IPCC_CLIENT_MP 683 mboxes = <&ipcc IPCC_CLIENT_MPSS
689 IPCC_MPROC_SIG 684 IPCC_MPROC_SIGNAL_SMP2P>;
690 685
691 qcom,local-pid = <0>; 686 qcom,local-pid = <0>;
692 qcom,remote-pid = <1>; 687 qcom,remote-pid = <1>;
693 688
694 smp2p_modem_out: master-kernel 689 smp2p_modem_out: master-kernel {
695 qcom,entry-name = "mas 690 qcom,entry-name = "master-kernel";
696 #qcom,smem-state-cells 691 #qcom,smem-state-cells = <1>;
697 }; 692 };
698 693
699 smp2p_modem_in: slave-kernel { 694 smp2p_modem_in: slave-kernel {
700 qcom,entry-name = "sla 695 qcom,entry-name = "slave-kernel";
701 interrupt-controller; 696 interrupt-controller;
702 #interrupt-cells = <2> 697 #interrupt-cells = <2>;
703 }; 698 };
704 699
705 ipa_smp2p_out: ipa-ap-to-modem 700 ipa_smp2p_out: ipa-ap-to-modem {
706 qcom,entry-name = "ipa 701 qcom,entry-name = "ipa";
707 #qcom,smem-state-cells 702 #qcom,smem-state-cells = <1>;
708 }; 703 };
709 704
710 ipa_smp2p_in: ipa-modem-to-ap 705 ipa_smp2p_in: ipa-modem-to-ap {
711 qcom,entry-name = "ipa 706 qcom,entry-name = "ipa";
712 interrupt-controller; 707 interrupt-controller;
713 #interrupt-cells = <2> 708 #interrupt-cells = <2>;
714 }; 709 };
715 }; 710 };
716 711
717 smp2p-slpi { 712 smp2p-slpi {
718 compatible = "qcom,smp2p"; 713 compatible = "qcom,smp2p";
719 qcom,smem = <481>, <430>; 714 qcom,smem = <481>, <430>;
720 interrupts-extended = <&ipcc I 715 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
721 I 716 IPCC_MPROC_SIGNAL_SMP2P
722 I 717 IRQ_TYPE_EDGE_RISING>;
723 mboxes = <&ipcc IPCC_CLIENT_SL 718 mboxes = <&ipcc IPCC_CLIENT_SLPI
724 IPCC_MPROC_SIG 719 IPCC_MPROC_SIGNAL_SMP2P>;
725 720
726 qcom,local-pid = <0>; 721 qcom,local-pid = <0>;
727 qcom,remote-pid = <3>; 722 qcom,remote-pid = <3>;
728 723
729 smp2p_slpi_out: master-kernel 724 smp2p_slpi_out: master-kernel {
730 qcom,entry-name = "mas 725 qcom,entry-name = "master-kernel";
731 #qcom,smem-state-cells 726 #qcom,smem-state-cells = <1>;
732 }; 727 };
733 728
734 smp2p_slpi_in: slave-kernel { 729 smp2p_slpi_in: slave-kernel {
735 qcom,entry-name = "sla 730 qcom,entry-name = "slave-kernel";
736 interrupt-controller; 731 interrupt-controller;
737 #interrupt-cells = <2> 732 #interrupt-cells = <2>;
738 }; 733 };
739 }; 734 };
740 735
741 soc: soc@0 { 736 soc: soc@0 {
742 #address-cells = <2>; 737 #address-cells = <2>;
743 #size-cells = <2>; 738 #size-cells = <2>;
744 ranges = <0 0 0 0 0x10 0>; 739 ranges = <0 0 0 0 0x10 0>;
745 dma-ranges = <0 0 0 0 0x10 0>; 740 dma-ranges = <0 0 0 0 0x10 0>;
746 compatible = "simple-bus"; 741 compatible = "simple-bus";
747 742
748 gcc: clock-controller@100000 { 743 gcc: clock-controller@100000 {
749 compatible = "qcom,gcc 744 compatible = "qcom,gcc-sm8450";
750 reg = <0x0 0x00100000 745 reg = <0x0 0x00100000 0x0 0x1f4200>;
751 #clock-cells = <1>; 746 #clock-cells = <1>;
752 #reset-cells = <1>; 747 #reset-cells = <1>;
753 #power-domain-cells = 748 #power-domain-cells = <1>;
754 clocks = <&rpmhcc RPMH 749 clocks = <&rpmhcc RPMH_CXO_CLK>,
755 <&sleep_clk>, 750 <&sleep_clk>,
756 <&pcie0_phy>, !! 751 <&pcie0_lane>,
757 <&pcie1_phy Q !! 752 <&pcie1_lane>,
758 <&pcie1_phy Q !! 753 <0>,
759 <&ufs_mem_phy !! 754 <&ufs_mem_phy_lanes 0>,
760 <&ufs_mem_phy !! 755 <&ufs_mem_phy_lanes 1>,
761 <&ufs_mem_phy !! 756 <&ufs_mem_phy_lanes 2>,
762 <&usb_1_qmpph 757 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
763 clock-names = "bi_tcxo 758 clock-names = "bi_tcxo",
764 "sleep_c 759 "sleep_clk",
765 "pcie_0_ 760 "pcie_0_pipe_clk",
766 "pcie_1_ 761 "pcie_1_pipe_clk",
767 "pcie_1_ 762 "pcie_1_phy_aux_clk",
768 "ufs_phy 763 "ufs_phy_rx_symbol_0_clk",
769 "ufs_phy 764 "ufs_phy_rx_symbol_1_clk",
770 "ufs_phy 765 "ufs_phy_tx_symbol_0_clk",
771 "usb3_ph 766 "usb3_phy_wrapper_gcc_usb30_pipe_clk";
772 }; 767 };
773 768
774 gpi_dma2: dma-controller@80000 769 gpi_dma2: dma-controller@800000 {
775 compatible = "qcom,sm8 770 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
776 #dma-cells = <3>; 771 #dma-cells = <3>;
777 reg = <0 0x00800000 0 772 reg = <0 0x00800000 0 0x60000>;
778 interrupts = <GIC_SPI 773 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
779 <GIC_SPI 774 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
780 <GIC_SPI 775 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
781 <GIC_SPI 776 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
782 <GIC_SPI 777 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
783 <GIC_SPI 778 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
784 <GIC_SPI 779 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
785 <GIC_SPI 780 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
786 <GIC_SPI 781 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
787 <GIC_SPI 782 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
788 <GIC_SPI 783 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
789 <GIC_SPI 784 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
790 dma-channels = <12>; 785 dma-channels = <12>;
791 dma-channel-mask = <0x 786 dma-channel-mask = <0x7e>;
792 iommus = <&apps_smmu 0 787 iommus = <&apps_smmu 0x496 0x0>;
793 status = "disabled"; 788 status = "disabled";
794 }; 789 };
795 790
796 qupv3_id_2: geniqup@8c0000 { 791 qupv3_id_2: geniqup@8c0000 {
797 compatible = "qcom,gen 792 compatible = "qcom,geni-se-qup";
798 reg = <0x0 0x008c0000 793 reg = <0x0 0x008c0000 0x0 0x2000>;
799 clock-names = "m-ahb", 794 clock-names = "m-ahb", "s-ahb";
800 clocks = <&gcc GCC_QUP 795 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
801 <&gcc GCC_QUP 796 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
802 iommus = <&apps_smmu 0 797 iommus = <&apps_smmu 0x483 0x0>;
803 #address-cells = <2>; 798 #address-cells = <2>;
804 #size-cells = <2>; 799 #size-cells = <2>;
805 ranges; 800 ranges;
806 status = "disabled"; 801 status = "disabled";
807 802
808 i2c15: i2c@880000 { 803 i2c15: i2c@880000 {
809 compatible = " 804 compatible = "qcom,geni-i2c";
810 reg = <0x0 0x0 805 reg = <0x0 0x00880000 0x0 0x4000>;
811 clock-names = 806 clock-names = "se";
812 clocks = <&gcc 807 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
813 pinctrl-names 808 pinctrl-names = "default";
814 pinctrl-0 = <& 809 pinctrl-0 = <&qup_i2c15_data_clk>;
815 interrupts = < 810 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
816 #address-cells 811 #address-cells = <1>;
817 #size-cells = 812 #size-cells = <0>;
818 interconnects 813 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
819 814 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
820 815 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
821 interconnect-n 816 interconnect-names = "qup-core", "qup-config", "qup-memory";
822 dmas = <&gpi_d 817 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
823 <&gpi_d 818 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
824 dma-names = "t 819 dma-names = "tx", "rx";
825 status = "disa 820 status = "disabled";
826 }; 821 };
827 822
828 spi15: spi@880000 { 823 spi15: spi@880000 {
829 compatible = " 824 compatible = "qcom,geni-spi";
830 reg = <0x0 0x0 825 reg = <0x0 0x00880000 0x0 0x4000>;
831 clock-names = 826 clock-names = "se";
832 clocks = <&gcc 827 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
833 interrupts = < 828 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
834 pinctrl-names 829 pinctrl-names = "default";
835 pinctrl-0 = <& 830 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
836 interconnects 831 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
837 832 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
838 interconnect-n 833 interconnect-names = "qup-core", "qup-config";
839 dmas = <&gpi_d 834 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
840 <&gpi_d 835 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
841 dma-names = "t 836 dma-names = "tx", "rx";
842 #address-cells 837 #address-cells = <1>;
843 #size-cells = 838 #size-cells = <0>;
844 status = "disa 839 status = "disabled";
845 }; 840 };
846 841
847 i2c16: i2c@884000 { 842 i2c16: i2c@884000 {
848 compatible = " 843 compatible = "qcom,geni-i2c";
849 reg = <0x0 0x0 844 reg = <0x0 0x00884000 0x0 0x4000>;
850 clock-names = 845 clock-names = "se";
851 clocks = <&gcc 846 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
852 pinctrl-names 847 pinctrl-names = "default";
853 pinctrl-0 = <& 848 pinctrl-0 = <&qup_i2c16_data_clk>;
854 interrupts = < 849 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
855 #address-cells 850 #address-cells = <1>;
856 #size-cells = 851 #size-cells = <0>;
857 interconnects 852 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
858 853 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
859 854 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
860 interconnect-n 855 interconnect-names = "qup-core", "qup-config", "qup-memory";
861 dmas = <&gpi_d 856 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
862 <&gpi_d 857 <&gpi_dma2 1 1 QCOM_GPI_I2C>;
863 dma-names = "t 858 dma-names = "tx", "rx";
864 status = "disa 859 status = "disabled";
865 }; 860 };
866 861
867 spi16: spi@884000 { 862 spi16: spi@884000 {
868 compatible = " 863 compatible = "qcom,geni-spi";
869 reg = <0x0 0x0 864 reg = <0x0 0x00884000 0x0 0x4000>;
870 clock-names = 865 clock-names = "se";
871 clocks = <&gcc 866 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
872 interrupts = < 867 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
873 pinctrl-names 868 pinctrl-names = "default";
874 pinctrl-0 = <& 869 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>;
875 interconnects 870 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
876 871 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
877 interconnect-n 872 interconnect-names = "qup-core", "qup-config";
878 dmas = <&gpi_d 873 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
879 <&gpi_d 874 <&gpi_dma2 1 1 QCOM_GPI_SPI>;
880 dma-names = "t 875 dma-names = "tx", "rx";
881 #address-cells 876 #address-cells = <1>;
882 #size-cells = 877 #size-cells = <0>;
883 status = "disa 878 status = "disabled";
884 }; 879 };
885 880
886 i2c17: i2c@888000 { 881 i2c17: i2c@888000 {
887 compatible = " 882 compatible = "qcom,geni-i2c";
888 reg = <0x0 0x0 883 reg = <0x0 0x00888000 0x0 0x4000>;
889 clock-names = 884 clock-names = "se";
890 clocks = <&gcc 885 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
891 pinctrl-names 886 pinctrl-names = "default";
892 pinctrl-0 = <& 887 pinctrl-0 = <&qup_i2c17_data_clk>;
893 interrupts = < 888 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
894 #address-cells 889 #address-cells = <1>;
895 #size-cells = 890 #size-cells = <0>;
896 interconnects 891 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
897 892 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
898 893 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
899 interconnect-n 894 interconnect-names = "qup-core", "qup-config", "qup-memory";
900 dmas = <&gpi_d 895 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
901 <&gpi_d 896 <&gpi_dma2 1 2 QCOM_GPI_I2C>;
902 dma-names = "t 897 dma-names = "tx", "rx";
903 status = "disa 898 status = "disabled";
904 }; 899 };
905 900
906 spi17: spi@888000 { 901 spi17: spi@888000 {
907 compatible = " 902 compatible = "qcom,geni-spi";
908 reg = <0x0 0x0 903 reg = <0x0 0x00888000 0x0 0x4000>;
909 clock-names = 904 clock-names = "se";
910 clocks = <&gcc 905 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
911 interrupts = < 906 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
912 pinctrl-names 907 pinctrl-names = "default";
913 pinctrl-0 = <& 908 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>;
914 interconnects 909 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
915 910 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
916 interconnect-n 911 interconnect-names = "qup-core", "qup-config";
917 dmas = <&gpi_d 912 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
918 <&gpi_d 913 <&gpi_dma2 1 2 QCOM_GPI_SPI>;
919 dma-names = "t 914 dma-names = "tx", "rx";
920 #address-cells 915 #address-cells = <1>;
921 #size-cells = 916 #size-cells = <0>;
922 status = "disa 917 status = "disabled";
923 }; 918 };
924 919
925 i2c18: i2c@88c000 { 920 i2c18: i2c@88c000 {
926 compatible = " 921 compatible = "qcom,geni-i2c";
927 reg = <0x0 0x0 922 reg = <0x0 0x0088c000 0x0 0x4000>;
928 clock-names = 923 clock-names = "se";
929 clocks = <&gcc 924 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
930 pinctrl-names 925 pinctrl-names = "default";
931 pinctrl-0 = <& 926 pinctrl-0 = <&qup_i2c18_data_clk>;
932 interrupts = < 927 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
933 #address-cells 928 #address-cells = <1>;
934 #size-cells = 929 #size-cells = <0>;
935 interconnects 930 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
936 931 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
937 932 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
938 interconnect-n 933 interconnect-names = "qup-core", "qup-config", "qup-memory";
939 dmas = <&gpi_d 934 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
940 <&gpi_d 935 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
941 dma-names = "t 936 dma-names = "tx", "rx";
942 status = "disa 937 status = "disabled";
943 }; 938 };
944 939
945 spi18: spi@88c000 { 940 spi18: spi@88c000 {
946 compatible = " 941 compatible = "qcom,geni-spi";
947 reg = <0 0x008 942 reg = <0 0x0088c000 0 0x4000>;
948 clock-names = 943 clock-names = "se";
949 clocks = <&gcc 944 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
950 interrupts = < 945 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
951 pinctrl-names 946 pinctrl-names = "default";
952 pinctrl-0 = <& 947 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>;
953 interconnects 948 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
954 949 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
955 interconnect-n 950 interconnect-names = "qup-core", "qup-config";
956 dmas = <&gpi_d 951 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
957 <&gpi_d 952 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
958 dma-names = "t 953 dma-names = "tx", "rx";
959 #address-cells 954 #address-cells = <1>;
960 #size-cells = 955 #size-cells = <0>;
961 status = "disa 956 status = "disabled";
962 }; 957 };
963 958
964 i2c19: i2c@890000 { 959 i2c19: i2c@890000 {
965 compatible = " 960 compatible = "qcom,geni-i2c";
966 reg = <0x0 0x0 961 reg = <0x0 0x00890000 0x0 0x4000>;
967 clock-names = 962 clock-names = "se";
968 clocks = <&gcc 963 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
969 pinctrl-names 964 pinctrl-names = "default";
970 pinctrl-0 = <& 965 pinctrl-0 = <&qup_i2c19_data_clk>;
971 interrupts = < 966 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
972 #address-cells 967 #address-cells = <1>;
973 #size-cells = 968 #size-cells = <0>;
974 interconnects 969 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
975 970 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
976 971 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
977 interconnect-n 972 interconnect-names = "qup-core", "qup-config", "qup-memory";
978 dmas = <&gpi_d 973 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
979 <&gpi_d 974 <&gpi_dma2 1 4 QCOM_GPI_I2C>;
980 dma-names = "t 975 dma-names = "tx", "rx";
981 status = "disa 976 status = "disabled";
982 }; 977 };
983 978
984 spi19: spi@890000 { 979 spi19: spi@890000 {
985 compatible = " 980 compatible = "qcom,geni-spi";
986 reg = <0 0x008 981 reg = <0 0x00890000 0 0x4000>;
987 clock-names = 982 clock-names = "se";
988 clocks = <&gcc 983 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
989 interrupts = < 984 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
990 pinctrl-names 985 pinctrl-names = "default";
991 pinctrl-0 = <& 986 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>;
992 interconnects 987 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
993 988 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
994 interconnect-n 989 interconnect-names = "qup-core", "qup-config";
995 dmas = <&gpi_d 990 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
996 <&gpi_d 991 <&gpi_dma2 1 4 QCOM_GPI_I2C>;
997 dma-names = "t 992 dma-names = "tx", "rx";
998 #address-cells 993 #address-cells = <1>;
999 #size-cells = 994 #size-cells = <0>;
1000 status = "dis 995 status = "disabled";
1001 }; 996 };
1002 997
1003 i2c20: i2c@894000 { 998 i2c20: i2c@894000 {
1004 compatible = 999 compatible = "qcom,geni-i2c";
1005 reg = <0x0 0x 1000 reg = <0x0 0x00894000 0x0 0x4000>;
1006 clock-names = 1001 clock-names = "se";
1007 clocks = <&gc 1002 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1008 pinctrl-names 1003 pinctrl-names = "default";
1009 pinctrl-0 = < 1004 pinctrl-0 = <&qup_i2c20_data_clk>;
1010 interrupts = 1005 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1011 #address-cell 1006 #address-cells = <1>;
1012 #size-cells = 1007 #size-cells = <0>;
1013 interconnects 1008 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1014 1009 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1015 1010 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1016 interconnect- 1011 interconnect-names = "qup-core", "qup-config", "qup-memory";
1017 dmas = <&gpi_ 1012 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1018 <&gpi_ 1013 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1019 dma-names = " 1014 dma-names = "tx", "rx";
1020 status = "dis 1015 status = "disabled";
1021 }; 1016 };
1022 1017
1023 uart20: serial@894000 1018 uart20: serial@894000 {
1024 compatible = 1019 compatible = "qcom,geni-uart";
1025 reg = <0 0x00 1020 reg = <0 0x00894000 0 0x4000>;
1026 clock-names = 1021 clock-names = "se";
1027 clocks = <&gc 1022 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1028 pinctrl-names 1023 pinctrl-names = "default";
1029 pinctrl-0 = < 1024 pinctrl-0 = <&qup_uart20_default>;
1030 interrupts = 1025 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1031 interconnects <<
1032 <<
1033 <<
1034 <<
1035 interconnect- <<
1036 <<
1037 status = "dis 1026 status = "disabled";
1038 }; 1027 };
1039 1028
1040 spi20: spi@894000 { 1029 spi20: spi@894000 {
1041 compatible = 1030 compatible = "qcom,geni-spi";
1042 reg = <0 0x00 1031 reg = <0 0x00894000 0 0x4000>;
1043 clock-names = 1032 clock-names = "se";
1044 clocks = <&gc 1033 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1045 interrupts = 1034 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1046 pinctrl-names 1035 pinctrl-names = "default";
1047 pinctrl-0 = < 1036 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>;
1048 interconnects 1037 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1049 1038 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
1050 interconnect- 1039 interconnect-names = "qup-core", "qup-config";
1051 dmas = <&gpi_ 1040 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1052 <&gpi_ 1041 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1053 dma-names = " 1042 dma-names = "tx", "rx";
1054 #address-cell 1043 #address-cells = <1>;
1055 #size-cells = 1044 #size-cells = <0>;
1056 status = "dis 1045 status = "disabled";
1057 }; 1046 };
1058 1047
1059 i2c21: i2c@898000 { 1048 i2c21: i2c@898000 {
1060 compatible = 1049 compatible = "qcom,geni-i2c";
1061 reg = <0x0 0x 1050 reg = <0x0 0x00898000 0x0 0x4000>;
1062 clock-names = 1051 clock-names = "se";
1063 clocks = <&gc 1052 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1064 pinctrl-names 1053 pinctrl-names = "default";
1065 pinctrl-0 = < 1054 pinctrl-0 = <&qup_i2c21_data_clk>;
1066 interrupts = 1055 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
1067 #address-cell 1056 #address-cells = <1>;
1068 #size-cells = 1057 #size-cells = <0>;
1069 interconnects 1058 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1070 1059 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1071 1060 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1072 interconnect- 1061 interconnect-names = "qup-core", "qup-config", "qup-memory";
1073 dmas = <&gpi_ 1062 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>,
1074 <&gpi_ 1063 <&gpi_dma2 1 6 QCOM_GPI_I2C>;
1075 dma-names = " 1064 dma-names = "tx", "rx";
1076 status = "dis 1065 status = "disabled";
1077 }; 1066 };
1078 1067
1079 spi21: spi@898000 { 1068 spi21: spi@898000 {
1080 compatible = 1069 compatible = "qcom,geni-spi";
1081 reg = <0 0x00 1070 reg = <0 0x00898000 0 0x4000>;
1082 clock-names = 1071 clock-names = "se";
1083 clocks = <&gc 1072 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1084 interrupts = 1073 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
1085 pinctrl-names 1074 pinctrl-names = "default";
1086 pinctrl-0 = < 1075 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>;
1087 interconnects 1076 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1088 1077 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
1089 interconnect- 1078 interconnect-names = "qup-core", "qup-config";
1090 dmas = <&gpi_ 1079 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>,
1091 <&gpi_ 1080 <&gpi_dma2 1 6 QCOM_GPI_SPI>;
1092 dma-names = " 1081 dma-names = "tx", "rx";
1093 #address-cell 1082 #address-cells = <1>;
1094 #size-cells = 1083 #size-cells = <0>;
1095 status = "dis 1084 status = "disabled";
1096 }; 1085 };
1097 }; 1086 };
1098 1087
1099 gpi_dma0: dma-controller@9000 1088 gpi_dma0: dma-controller@900000 {
1100 compatible = "qcom,sm 1089 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
1101 #dma-cells = <3>; 1090 #dma-cells = <3>;
1102 reg = <0 0x00900000 0 1091 reg = <0 0x00900000 0 0x60000>;
1103 interrupts = <GIC_SPI 1092 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
1104 <GIC_SPI 1093 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
1105 <GIC_SPI 1094 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
1106 <GIC_SPI 1095 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
1107 <GIC_SPI 1096 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
1108 <GIC_SPI 1097 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
1109 <GIC_SPI 1098 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
1110 <GIC_SPI 1099 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
1111 <GIC_SPI 1100 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
1112 <GIC_SPI 1101 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
1113 <GIC_SPI 1102 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
1114 <GIC_SPI 1103 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
1115 dma-channels = <12>; 1104 dma-channels = <12>;
1116 dma-channel-mask = <0 1105 dma-channel-mask = <0x7e>;
1117 iommus = <&apps_smmu 1106 iommus = <&apps_smmu 0x5b6 0x0>;
1118 status = "disabled"; 1107 status = "disabled";
1119 }; 1108 };
1120 1109
1121 qupv3_id_0: geniqup@9c0000 { 1110 qupv3_id_0: geniqup@9c0000 {
1122 compatible = "qcom,ge 1111 compatible = "qcom,geni-se-qup";
1123 reg = <0x0 0x009c0000 1112 reg = <0x0 0x009c0000 0x0 0x2000>;
1124 clock-names = "m-ahb" 1113 clock-names = "m-ahb", "s-ahb";
1125 clocks = <&gcc GCC_QU 1114 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1126 <&gcc GCC_QU 1115 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1127 iommus = <&apps_smmu 1116 iommus = <&apps_smmu 0x5a3 0x0>;
1128 interconnects = <&clk 1117 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>;
1129 interconnect-names = 1118 interconnect-names = "qup-core";
1130 #address-cells = <2>; 1119 #address-cells = <2>;
1131 #size-cells = <2>; 1120 #size-cells = <2>;
1132 ranges; 1121 ranges;
1133 status = "disabled"; 1122 status = "disabled";
1134 1123
1135 i2c0: i2c@980000 { 1124 i2c0: i2c@980000 {
1136 compatible = 1125 compatible = "qcom,geni-i2c";
1137 reg = <0x0 0x 1126 reg = <0x0 0x00980000 0x0 0x4000>;
1138 clock-names = 1127 clock-names = "se";
1139 clocks = <&gc 1128 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1140 pinctrl-names 1129 pinctrl-names = "default";
1141 pinctrl-0 = < 1130 pinctrl-0 = <&qup_i2c0_data_clk>;
1142 interrupts = 1131 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1143 #address-cell 1132 #address-cells = <1>;
1144 #size-cells = 1133 #size-cells = <0>;
1145 interconnects 1134 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1146 1135 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1147 1136 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1148 interconnect- 1137 interconnect-names = "qup-core", "qup-config", "qup-memory";
1149 dmas = <&gpi_ 1138 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1150 <&gpi_ 1139 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1151 dma-names = " 1140 dma-names = "tx", "rx";
1152 status = "dis 1141 status = "disabled";
1153 }; 1142 };
1154 1143
1155 spi0: spi@980000 { 1144 spi0: spi@980000 {
1156 compatible = 1145 compatible = "qcom,geni-spi";
1157 reg = <0x0 0x 1146 reg = <0x0 0x00980000 0x0 0x4000>;
1158 clock-names = 1147 clock-names = "se";
1159 clocks = <&gc 1148 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1160 interrupts = 1149 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1161 pinctrl-names 1150 pinctrl-names = "default";
1162 pinctrl-0 = < 1151 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1163 power-domains !! 1152 power-domains = <&rpmhpd SM8450_CX>;
1164 operating-poi 1153 operating-points-v2 = <&qup_opp_table_100mhz>;
1165 interconnects 1154 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1166 1155 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1167 1156 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1168 interconnect- 1157 interconnect-names = "qup-core", "qup-config", "qup-memory";
1169 dmas = <&gpi_ 1158 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1170 <&gpi_ 1159 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1171 dma-names = " 1160 dma-names = "tx", "rx";
1172 #address-cell 1161 #address-cells = <1>;
1173 #size-cells = 1162 #size-cells = <0>;
1174 status = "dis 1163 status = "disabled";
1175 }; 1164 };
1176 1165
1177 i2c1: i2c@984000 { 1166 i2c1: i2c@984000 {
1178 compatible = 1167 compatible = "qcom,geni-i2c";
1179 reg = <0x0 0x 1168 reg = <0x0 0x00984000 0x0 0x4000>;
1180 clock-names = 1169 clock-names = "se";
1181 clocks = <&gc 1170 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1182 pinctrl-names 1171 pinctrl-names = "default";
1183 pinctrl-0 = < 1172 pinctrl-0 = <&qup_i2c1_data_clk>;
1184 interrupts = 1173 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1185 #address-cell 1174 #address-cells = <1>;
1186 #size-cells = 1175 #size-cells = <0>;
1187 interconnects 1176 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1188 1177 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1189 1178 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1190 interconnect- 1179 interconnect-names = "qup-core", "qup-config", "qup-memory";
1191 dmas = <&gpi_ 1180 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1192 <&gpi_ 1181 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1193 dma-names = " 1182 dma-names = "tx", "rx";
1194 status = "dis 1183 status = "disabled";
1195 }; 1184 };
1196 1185
1197 spi1: spi@984000 { 1186 spi1: spi@984000 {
1198 compatible = 1187 compatible = "qcom,geni-spi";
1199 reg = <0x0 0x 1188 reg = <0x0 0x00984000 0x0 0x4000>;
1200 clock-names = 1189 clock-names = "se";
1201 clocks = <&gc 1190 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1202 interrupts = 1191 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1203 pinctrl-names 1192 pinctrl-names = "default";
1204 pinctrl-0 = < 1193 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1205 interconnects 1194 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1206 1195 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1207 1196 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1208 interconnect- 1197 interconnect-names = "qup-core", "qup-config", "qup-memory";
1209 dmas = <&gpi_ 1198 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1210 <&gpi_ 1199 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1211 dma-names = " 1200 dma-names = "tx", "rx";
1212 #address-cell 1201 #address-cells = <1>;
1213 #size-cells = 1202 #size-cells = <0>;
1214 status = "dis 1203 status = "disabled";
1215 }; 1204 };
1216 1205
1217 i2c2: i2c@988000 { 1206 i2c2: i2c@988000 {
1218 compatible = 1207 compatible = "qcom,geni-i2c";
1219 reg = <0x0 0x 1208 reg = <0x0 0x00988000 0x0 0x4000>;
1220 clock-names = 1209 clock-names = "se";
1221 clocks = <&gc 1210 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1222 pinctrl-names 1211 pinctrl-names = "default";
1223 pinctrl-0 = < 1212 pinctrl-0 = <&qup_i2c2_data_clk>;
1224 interrupts = 1213 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1225 #address-cell 1214 #address-cells = <1>;
1226 #size-cells = 1215 #size-cells = <0>;
1227 interconnects 1216 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1228 1217 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1229 1218 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1230 interconnect- 1219 interconnect-names = "qup-core", "qup-config", "qup-memory";
1231 dmas = <&gpi_ 1220 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1232 <&gpi_ 1221 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1233 dma-names = " 1222 dma-names = "tx", "rx";
1234 status = "dis 1223 status = "disabled";
1235 }; 1224 };
1236 1225
1237 spi2: spi@988000 { 1226 spi2: spi@988000 {
1238 compatible = 1227 compatible = "qcom,geni-spi";
1239 reg = <0x0 0x 1228 reg = <0x0 0x00988000 0x0 0x4000>;
1240 clock-names = 1229 clock-names = "se";
1241 clocks = <&gc 1230 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1242 interrupts = 1231 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1243 pinctrl-names 1232 pinctrl-names = "default";
1244 pinctrl-0 = < 1233 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1245 interconnects 1234 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1246 1235 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1247 1236 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1248 interconnect- 1237 interconnect-names = "qup-core", "qup-config", "qup-memory";
1249 dmas = <&gpi_ 1238 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1250 <&gpi_ 1239 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1251 dma-names = " 1240 dma-names = "tx", "rx";
1252 #address-cell 1241 #address-cells = <1>;
1253 #size-cells = 1242 #size-cells = <0>;
1254 status = "dis 1243 status = "disabled";
1255 }; 1244 };
1256 1245
1257 1246
1258 i2c3: i2c@98c000 { 1247 i2c3: i2c@98c000 {
1259 compatible = 1248 compatible = "qcom,geni-i2c";
1260 reg = <0x0 0x 1249 reg = <0x0 0x0098c000 0x0 0x4000>;
1261 clock-names = 1250 clock-names = "se";
1262 clocks = <&gc 1251 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1263 pinctrl-names 1252 pinctrl-names = "default";
1264 pinctrl-0 = < 1253 pinctrl-0 = <&qup_i2c3_data_clk>;
1265 interrupts = 1254 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1266 #address-cell 1255 #address-cells = <1>;
1267 #size-cells = 1256 #size-cells = <0>;
1268 interconnects 1257 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1269 1258 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1270 1259 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1271 interconnect- 1260 interconnect-names = "qup-core", "qup-config", "qup-memory";
1272 dmas = <&gpi_ 1261 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1273 <&gpi_ 1262 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1274 dma-names = " 1263 dma-names = "tx", "rx";
1275 status = "dis 1264 status = "disabled";
1276 }; 1265 };
1277 1266
1278 spi3: spi@98c000 { 1267 spi3: spi@98c000 {
1279 compatible = 1268 compatible = "qcom,geni-spi";
1280 reg = <0x0 0x 1269 reg = <0x0 0x0098c000 0x0 0x4000>;
1281 clock-names = 1270 clock-names = "se";
1282 clocks = <&gc 1271 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1283 interrupts = 1272 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1284 pinctrl-names 1273 pinctrl-names = "default";
1285 pinctrl-0 = < 1274 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1286 interconnects 1275 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1287 1276 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1288 1277 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1289 interconnect- 1278 interconnect-names = "qup-core", "qup-config", "qup-memory";
1290 dmas = <&gpi_ 1279 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1291 <&gpi_ 1280 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1292 dma-names = " 1281 dma-names = "tx", "rx";
1293 #address-cell 1282 #address-cells = <1>;
1294 #size-cells = 1283 #size-cells = <0>;
1295 status = "dis 1284 status = "disabled";
1296 }; 1285 };
1297 1286
1298 i2c4: i2c@990000 { 1287 i2c4: i2c@990000 {
1299 compatible = 1288 compatible = "qcom,geni-i2c";
1300 reg = <0x0 0x 1289 reg = <0x0 0x00990000 0x0 0x4000>;
1301 clock-names = 1290 clock-names = "se";
1302 clocks = <&gc 1291 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1303 pinctrl-names 1292 pinctrl-names = "default";
1304 pinctrl-0 = < 1293 pinctrl-0 = <&qup_i2c4_data_clk>;
1305 interrupts = 1294 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1306 #address-cell 1295 #address-cells = <1>;
1307 #size-cells = 1296 #size-cells = <0>;
1308 interconnects 1297 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1309 1298 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1310 1299 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1311 interconnect- 1300 interconnect-names = "qup-core", "qup-config", "qup-memory";
1312 dmas = <&gpi_ 1301 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1313 <&gpi_ 1302 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1314 dma-names = " 1303 dma-names = "tx", "rx";
1315 status = "dis 1304 status = "disabled";
1316 }; 1305 };
1317 1306
1318 spi4: spi@990000 { 1307 spi4: spi@990000 {
1319 compatible = 1308 compatible = "qcom,geni-spi";
1320 reg = <0x0 0x 1309 reg = <0x0 0x00990000 0x0 0x4000>;
1321 clock-names = 1310 clock-names = "se";
1322 clocks = <&gc 1311 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1323 interrupts = 1312 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1324 pinctrl-names 1313 pinctrl-names = "default";
1325 pinctrl-0 = < 1314 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1326 power-domains !! 1315 power-domains = <&rpmhpd SM8450_CX>;
1327 operating-poi 1316 operating-points-v2 = <&qup_opp_table_100mhz>;
1328 interconnects 1317 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1329 1318 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1330 1319 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1331 interconnect- 1320 interconnect-names = "qup-core", "qup-config", "qup-memory";
1332 dmas = <&gpi_ 1321 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1333 <&gpi_ 1322 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1334 dma-names = " 1323 dma-names = "tx", "rx";
1335 #address-cell 1324 #address-cells = <1>;
1336 #size-cells = 1325 #size-cells = <0>;
1337 status = "dis 1326 status = "disabled";
1338 }; 1327 };
1339 1328
1340 i2c5: i2c@994000 { 1329 i2c5: i2c@994000 {
1341 compatible = 1330 compatible = "qcom,geni-i2c";
1342 reg = <0x0 0x 1331 reg = <0x0 0x00994000 0x0 0x4000>;
1343 clock-names = 1332 clock-names = "se";
1344 clocks = <&gc 1333 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1345 pinctrl-names 1334 pinctrl-names = "default";
1346 pinctrl-0 = < 1335 pinctrl-0 = <&qup_i2c5_data_clk>;
1347 interrupts = 1336 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1348 #address-cell 1337 #address-cells = <1>;
1349 #size-cells = 1338 #size-cells = <0>;
1350 interconnects 1339 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1351 1340 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1352 1341 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1353 interconnect- 1342 interconnect-names = "qup-core", "qup-config", "qup-memory";
1354 dmas = <&gpi_ 1343 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1355 <&gpi_ 1344 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1356 dma-names = " 1345 dma-names = "tx", "rx";
1357 status = "dis 1346 status = "disabled";
1358 }; 1347 };
1359 1348
1360 spi5: spi@994000 { 1349 spi5: spi@994000 {
1361 compatible = 1350 compatible = "qcom,geni-spi";
1362 reg = <0x0 0x 1351 reg = <0x0 0x00994000 0x0 0x4000>;
1363 clock-names = 1352 clock-names = "se";
1364 clocks = <&gc 1353 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1365 interrupts = 1354 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1366 pinctrl-names 1355 pinctrl-names = "default";
1367 pinctrl-0 = < 1356 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1368 interconnects 1357 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1369 1358 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1370 1359 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1371 interconnect- 1360 interconnect-names = "qup-core", "qup-config", "qup-memory";
1372 dmas = <&gpi_ 1361 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1373 <&gpi_ 1362 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1374 dma-names = " 1363 dma-names = "tx", "rx";
1375 #address-cell 1364 #address-cells = <1>;
1376 #size-cells = 1365 #size-cells = <0>;
1377 status = "dis 1366 status = "disabled";
1378 }; 1367 };
1379 1368
1380 1369
1381 i2c6: i2c@998000 { 1370 i2c6: i2c@998000 {
1382 compatible = 1371 compatible = "qcom,geni-i2c";
1383 reg = <0x0 0x 1372 reg = <0x0 0x00998000 0x0 0x4000>;
1384 clock-names = 1373 clock-names = "se";
1385 clocks = <&gc 1374 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1386 pinctrl-names 1375 pinctrl-names = "default";
1387 pinctrl-0 = < 1376 pinctrl-0 = <&qup_i2c6_data_clk>;
1388 interrupts = 1377 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1389 #address-cell 1378 #address-cells = <1>;
1390 #size-cells = 1379 #size-cells = <0>;
1391 interconnects 1380 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1392 1381 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1393 1382 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1394 interconnect- 1383 interconnect-names = "qup-core", "qup-config", "qup-memory";
1395 dmas = <&gpi_ 1384 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1396 <&gpi_ 1385 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1397 dma-names = " 1386 dma-names = "tx", "rx";
1398 status = "dis 1387 status = "disabled";
1399 }; 1388 };
1400 1389
1401 spi6: spi@998000 { 1390 spi6: spi@998000 {
1402 compatible = 1391 compatible = "qcom,geni-spi";
1403 reg = <0x0 0x 1392 reg = <0x0 0x00998000 0x0 0x4000>;
1404 clock-names = 1393 clock-names = "se";
1405 clocks = <&gc 1394 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1406 interrupts = 1395 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1407 pinctrl-names 1396 pinctrl-names = "default";
1408 pinctrl-0 = < 1397 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1409 interconnects 1398 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1410 1399 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1411 1400 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1412 interconnect- 1401 interconnect-names = "qup-core", "qup-config", "qup-memory";
1413 dmas = <&gpi_ 1402 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1414 <&gpi_ 1403 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1415 dma-names = " 1404 dma-names = "tx", "rx";
1416 #address-cell 1405 #address-cells = <1>;
1417 #size-cells = 1406 #size-cells = <0>;
1418 status = "dis 1407 status = "disabled";
1419 }; 1408 };
1420 1409
1421 uart7: serial@99c000 1410 uart7: serial@99c000 {
1422 compatible = 1411 compatible = "qcom,geni-debug-uart";
1423 reg = <0 0x00 1412 reg = <0 0x0099c000 0 0x4000>;
1424 clock-names = 1413 clock-names = "se";
1425 clocks = <&gc 1414 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1426 pinctrl-names 1415 pinctrl-names = "default";
1427 pinctrl-0 = < 1416 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>;
1428 interrupts = 1417 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1429 interconnects <<
1430 <<
1431 <<
1432 <<
1433 interconnect- <<
1434 <<
1435 status = "dis 1418 status = "disabled";
1436 }; 1419 };
1437 }; 1420 };
1438 1421
1439 gpi_dma1: dma-controller@a000 1422 gpi_dma1: dma-controller@a00000 {
1440 compatible = "qcom,sm 1423 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
1441 #dma-cells = <3>; 1424 #dma-cells = <3>;
1442 reg = <0 0x00a00000 0 1425 reg = <0 0x00a00000 0 0x60000>;
1443 interrupts = <GIC_SPI 1426 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1444 <GIC_SPI 1427 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1445 <GIC_SPI 1428 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1446 <GIC_SPI 1429 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1447 <GIC_SPI 1430 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1448 <GIC_SPI 1431 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1449 <GIC_SPI 1432 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1450 <GIC_SPI 1433 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1451 <GIC_SPI 1434 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1452 <GIC_SPI 1435 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1453 <GIC_SPI 1436 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1454 <GIC_SPI 1437 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
1455 dma-channels = <12>; 1438 dma-channels = <12>;
1456 dma-channel-mask = <0 1439 dma-channel-mask = <0x7e>;
1457 iommus = <&apps_smmu 1440 iommus = <&apps_smmu 0x56 0x0>;
1458 status = "disabled"; 1441 status = "disabled";
1459 }; 1442 };
1460 1443
1461 qupv3_id_1: geniqup@ac0000 { 1444 qupv3_id_1: geniqup@ac0000 {
1462 compatible = "qcom,ge 1445 compatible = "qcom,geni-se-qup";
1463 reg = <0x0 0x00ac0000 1446 reg = <0x0 0x00ac0000 0x0 0x6000>;
1464 clock-names = "m-ahb" 1447 clock-names = "m-ahb", "s-ahb";
1465 clocks = <&gcc GCC_QU 1448 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1466 <&gcc GCC_QU 1449 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1467 iommus = <&apps_smmu 1450 iommus = <&apps_smmu 0x43 0x0>;
1468 interconnects = <&clk 1451 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>;
1469 interconnect-names = 1452 interconnect-names = "qup-core";
1470 #address-cells = <2>; 1453 #address-cells = <2>;
1471 #size-cells = <2>; 1454 #size-cells = <2>;
1472 ranges; 1455 ranges;
1473 status = "disabled"; 1456 status = "disabled";
1474 1457
1475 i2c8: i2c@a80000 { 1458 i2c8: i2c@a80000 {
1476 compatible = 1459 compatible = "qcom,geni-i2c";
1477 reg = <0x0 0x 1460 reg = <0x0 0x00a80000 0x0 0x4000>;
1478 clock-names = 1461 clock-names = "se";
1479 clocks = <&gc 1462 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1480 pinctrl-names 1463 pinctrl-names = "default";
1481 pinctrl-0 = < 1464 pinctrl-0 = <&qup_i2c8_data_clk>;
1482 interrupts = 1465 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1483 #address-cell 1466 #address-cells = <1>;
1484 #size-cells = 1467 #size-cells = <0>;
1485 interconnects 1468 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1486 1469 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1487 1470 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1488 interconnect- 1471 interconnect-names = "qup-core", "qup-config", "qup-memory";
1489 dmas = <&gpi_ 1472 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1490 <&gpi_ 1473 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1491 dma-names = " 1474 dma-names = "tx", "rx";
1492 status = "dis 1475 status = "disabled";
1493 }; 1476 };
1494 1477
1495 spi8: spi@a80000 { 1478 spi8: spi@a80000 {
1496 compatible = 1479 compatible = "qcom,geni-spi";
1497 reg = <0x0 0x 1480 reg = <0x0 0x00a80000 0x0 0x4000>;
1498 clock-names = 1481 clock-names = "se";
1499 clocks = <&gc 1482 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1500 interrupts = 1483 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1501 pinctrl-names 1484 pinctrl-names = "default";
1502 pinctrl-0 = < 1485 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1503 interconnects 1486 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1504 1487 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1505 1488 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1506 interconnect- 1489 interconnect-names = "qup-core", "qup-config", "qup-memory";
1507 dmas = <&gpi_ 1490 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1508 <&gpi_ 1491 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1509 dma-names = " 1492 dma-names = "tx", "rx";
1510 #address-cell 1493 #address-cells = <1>;
1511 #size-cells = 1494 #size-cells = <0>;
1512 status = "dis 1495 status = "disabled";
1513 }; 1496 };
1514 1497
1515 i2c9: i2c@a84000 { 1498 i2c9: i2c@a84000 {
1516 compatible = 1499 compatible = "qcom,geni-i2c";
1517 reg = <0x0 0x 1500 reg = <0x0 0x00a84000 0x0 0x4000>;
1518 clock-names = 1501 clock-names = "se";
1519 clocks = <&gc 1502 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1520 pinctrl-names 1503 pinctrl-names = "default";
1521 pinctrl-0 = < 1504 pinctrl-0 = <&qup_i2c9_data_clk>;
1522 interrupts = 1505 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1523 #address-cell 1506 #address-cells = <1>;
1524 #size-cells = 1507 #size-cells = <0>;
1525 interconnects 1508 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1526 1509 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1527 1510 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1528 interconnect- 1511 interconnect-names = "qup-core", "qup-config", "qup-memory";
1529 dmas = <&gpi_ 1512 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1530 <&gpi_ 1513 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1531 dma-names = " 1514 dma-names = "tx", "rx";
1532 status = "dis 1515 status = "disabled";
1533 }; 1516 };
1534 1517
1535 spi9: spi@a84000 { 1518 spi9: spi@a84000 {
1536 compatible = 1519 compatible = "qcom,geni-spi";
1537 reg = <0x0 0x 1520 reg = <0x0 0x00a84000 0x0 0x4000>;
1538 clock-names = 1521 clock-names = "se";
1539 clocks = <&gc 1522 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1540 interrupts = 1523 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1541 pinctrl-names 1524 pinctrl-names = "default";
1542 pinctrl-0 = < 1525 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1543 interconnects 1526 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1544 1527 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1545 1528 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1546 interconnect- 1529 interconnect-names = "qup-core", "qup-config", "qup-memory";
1547 dmas = <&gpi_ 1530 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1548 <&gpi_ 1531 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1549 dma-names = " 1532 dma-names = "tx", "rx";
1550 #address-cell 1533 #address-cells = <1>;
1551 #size-cells = 1534 #size-cells = <0>;
1552 status = "dis 1535 status = "disabled";
1553 }; 1536 };
1554 1537
1555 i2c10: i2c@a88000 { 1538 i2c10: i2c@a88000 {
1556 compatible = 1539 compatible = "qcom,geni-i2c";
1557 reg = <0x0 0x 1540 reg = <0x0 0x00a88000 0x0 0x4000>;
1558 clock-names = 1541 clock-names = "se";
1559 clocks = <&gc 1542 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1560 pinctrl-names 1543 pinctrl-names = "default";
1561 pinctrl-0 = < 1544 pinctrl-0 = <&qup_i2c10_data_clk>;
1562 interrupts = 1545 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1563 #address-cell 1546 #address-cells = <1>;
1564 #size-cells = 1547 #size-cells = <0>;
1565 interconnects 1548 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1566 1549 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1567 1550 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1568 interconnect- 1551 interconnect-names = "qup-core", "qup-config", "qup-memory";
1569 dmas = <&gpi_ 1552 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1570 <&gpi_ 1553 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1571 dma-names = " 1554 dma-names = "tx", "rx";
1572 status = "dis 1555 status = "disabled";
1573 }; 1556 };
1574 1557
1575 spi10: spi@a88000 { 1558 spi10: spi@a88000 {
1576 compatible = 1559 compatible = "qcom,geni-spi";
1577 reg = <0x0 0x 1560 reg = <0x0 0x00a88000 0x0 0x4000>;
1578 clock-names = 1561 clock-names = "se";
1579 clocks = <&gc 1562 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1580 interrupts = 1563 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1581 pinctrl-names 1564 pinctrl-names = "default";
1582 pinctrl-0 = < 1565 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1583 interconnects 1566 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1584 1567 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1585 1568 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1586 interconnect- 1569 interconnect-names = "qup-core", "qup-config", "qup-memory";
1587 dmas = <&gpi_ 1570 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1588 <&gpi_ 1571 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1589 dma-names = " 1572 dma-names = "tx", "rx";
1590 #address-cell 1573 #address-cells = <1>;
1591 #size-cells = 1574 #size-cells = <0>;
1592 status = "dis 1575 status = "disabled";
1593 }; 1576 };
1594 1577
1595 i2c11: i2c@a8c000 { 1578 i2c11: i2c@a8c000 {
1596 compatible = 1579 compatible = "qcom,geni-i2c";
1597 reg = <0x0 0x 1580 reg = <0x0 0x00a8c000 0x0 0x4000>;
1598 clock-names = 1581 clock-names = "se";
1599 clocks = <&gc 1582 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1600 pinctrl-names 1583 pinctrl-names = "default";
1601 pinctrl-0 = < 1584 pinctrl-0 = <&qup_i2c11_data_clk>;
1602 interrupts = 1585 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1603 #address-cell 1586 #address-cells = <1>;
1604 #size-cells = 1587 #size-cells = <0>;
1605 interconnects 1588 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1606 1589 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1607 1590 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1608 interconnect- 1591 interconnect-names = "qup-core", "qup-config", "qup-memory";
1609 dmas = <&gpi_ 1592 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1610 <&gpi_ 1593 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1611 dma-names = " 1594 dma-names = "tx", "rx";
1612 status = "dis 1595 status = "disabled";
1613 }; 1596 };
1614 1597
1615 spi11: spi@a8c000 { 1598 spi11: spi@a8c000 {
1616 compatible = 1599 compatible = "qcom,geni-spi";
1617 reg = <0x0 0x 1600 reg = <0x0 0x00a8c000 0x0 0x4000>;
1618 clock-names = 1601 clock-names = "se";
1619 clocks = <&gc 1602 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1620 interrupts = 1603 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1621 pinctrl-names 1604 pinctrl-names = "default";
1622 pinctrl-0 = < 1605 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1623 interconnects 1606 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1624 1607 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1625 1608 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1626 interconnect- 1609 interconnect-names = "qup-core", "qup-config", "qup-memory";
1627 dmas = <&gpi_ 1610 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1628 <&gpi_ 1611 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1629 dma-names = " 1612 dma-names = "tx", "rx";
1630 #address-cell 1613 #address-cells = <1>;
1631 #size-cells = 1614 #size-cells = <0>;
1632 status = "dis 1615 status = "disabled";
1633 }; 1616 };
1634 1617
1635 i2c12: i2c@a90000 { 1618 i2c12: i2c@a90000 {
1636 compatible = 1619 compatible = "qcom,geni-i2c";
1637 reg = <0x0 0x 1620 reg = <0x0 0x00a90000 0x0 0x4000>;
1638 clock-names = 1621 clock-names = "se";
1639 clocks = <&gc 1622 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1640 pinctrl-names 1623 pinctrl-names = "default";
1641 pinctrl-0 = < 1624 pinctrl-0 = <&qup_i2c12_data_clk>;
1642 interrupts = 1625 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1643 #address-cell 1626 #address-cells = <1>;
1644 #size-cells = 1627 #size-cells = <0>;
1645 interconnects 1628 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1646 1629 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1647 1630 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1648 interconnect- 1631 interconnect-names = "qup-core", "qup-config", "qup-memory";
1649 dmas = <&gpi_ 1632 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1650 <&gpi_ 1633 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1651 dma-names = " 1634 dma-names = "tx", "rx";
1652 status = "dis 1635 status = "disabled";
1653 }; 1636 };
1654 1637
1655 spi12: spi@a90000 { 1638 spi12: spi@a90000 {
1656 compatible = 1639 compatible = "qcom,geni-spi";
1657 reg = <0x0 0x 1640 reg = <0x0 0x00a90000 0x0 0x4000>;
1658 clock-names = 1641 clock-names = "se";
1659 clocks = <&gc 1642 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1660 interrupts = 1643 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1661 pinctrl-names 1644 pinctrl-names = "default";
1662 pinctrl-0 = < 1645 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1663 interconnects 1646 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1664 1647 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1665 1648 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1666 interconnect- 1649 interconnect-names = "qup-core", "qup-config", "qup-memory";
1667 dmas = <&gpi_ 1650 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1668 <&gpi_ 1651 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1669 dma-names = " 1652 dma-names = "tx", "rx";
1670 #address-cell 1653 #address-cells = <1>;
1671 #size-cells = 1654 #size-cells = <0>;
1672 status = "dis 1655 status = "disabled";
1673 }; 1656 };
1674 1657
1675 i2c13: i2c@a94000 { 1658 i2c13: i2c@a94000 {
1676 compatible = 1659 compatible = "qcom,geni-i2c";
1677 reg = <0 0x00 1660 reg = <0 0x00a94000 0 0x4000>;
1678 clock-names = 1661 clock-names = "se";
1679 clocks = <&gc 1662 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1680 pinctrl-names 1663 pinctrl-names = "default";
1681 pinctrl-0 = < 1664 pinctrl-0 = <&qup_i2c13_data_clk>;
1682 interrupts = 1665 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1683 interconnects 1666 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1684 1667 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1685 1668 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1686 interconnect- 1669 interconnect-names = "qup-core", "qup-config", "qup-memory";
1687 dmas = <&gpi_ 1670 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1688 <&gpi_ 1671 <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1689 dma-names = " 1672 dma-names = "tx", "rx";
1690 #address-cell 1673 #address-cells = <1>;
1691 #size-cells = 1674 #size-cells = <0>;
1692 status = "dis 1675 status = "disabled";
1693 }; 1676 };
1694 1677
1695 spi13: spi@a94000 { 1678 spi13: spi@a94000 {
1696 compatible = 1679 compatible = "qcom,geni-spi";
1697 reg = <0x0 0x 1680 reg = <0x0 0x00a94000 0x0 0x4000>;
1698 clock-names = 1681 clock-names = "se";
1699 clocks = <&gc 1682 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1700 interrupts = 1683 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1701 pinctrl-names 1684 pinctrl-names = "default";
1702 pinctrl-0 = < 1685 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1703 interconnects 1686 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1704 1687 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1705 1688 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1706 interconnect- 1689 interconnect-names = "qup-core", "qup-config", "qup-memory";
1707 dmas = <&gpi_ 1690 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1708 <&gpi_ 1691 <&gpi_dma1 1 5 QCOM_GPI_SPI>;
1709 dma-names = " 1692 dma-names = "tx", "rx";
1710 #address-cell 1693 #address-cells = <1>;
1711 #size-cells = 1694 #size-cells = <0>;
1712 status = "dis 1695 status = "disabled";
1713 }; 1696 };
1714 1697
1715 i2c14: i2c@a98000 { 1698 i2c14: i2c@a98000 {
1716 compatible = 1699 compatible = "qcom,geni-i2c";
1717 reg = <0 0x00 1700 reg = <0 0x00a98000 0 0x4000>;
1718 clock-names = 1701 clock-names = "se";
1719 clocks = <&gc 1702 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1720 pinctrl-names 1703 pinctrl-names = "default";
1721 pinctrl-0 = < 1704 pinctrl-0 = <&qup_i2c14_data_clk>;
1722 interrupts = 1705 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
1723 interconnects 1706 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1724 1707 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1725 1708 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1726 interconnect- 1709 interconnect-names = "qup-core", "qup-config", "qup-memory";
1727 dmas = <&gpi_ 1710 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
1728 <&gpi_ 1711 <&gpi_dma1 1 6 QCOM_GPI_I2C>;
1729 dma-names = " 1712 dma-names = "tx", "rx";
1730 #address-cell 1713 #address-cells = <1>;
1731 #size-cells = 1714 #size-cells = <0>;
1732 status = "dis 1715 status = "disabled";
1733 }; 1716 };
1734 1717
1735 spi14: spi@a98000 { 1718 spi14: spi@a98000 {
1736 compatible = 1719 compatible = "qcom,geni-spi";
1737 reg = <0x0 0x 1720 reg = <0x0 0x00a98000 0x0 0x4000>;
1738 clock-names = 1721 clock-names = "se";
1739 clocks = <&gc 1722 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1740 interrupts = 1723 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
1741 pinctrl-names 1724 pinctrl-names = "default";
1742 pinctrl-0 = < 1725 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
1743 interconnects 1726 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1744 1727 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1745 1728 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1746 interconnect- 1729 interconnect-names = "qup-core", "qup-config", "qup-memory";
1747 dmas = <&gpi_ 1730 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
1748 <&gpi_ 1731 <&gpi_dma1 1 6 QCOM_GPI_SPI>;
1749 dma-names = " 1732 dma-names = "tx", "rx";
1750 #address-cell 1733 #address-cells = <1>;
1751 #size-cells = 1734 #size-cells = <0>;
1752 status = "dis 1735 status = "disabled";
1753 }; 1736 };
1754 }; 1737 };
1755 1738
1756 rng: rng@10c3000 { !! 1739 pcie0: pci@1c00000 {
1757 compatible = "qcom,sm <<
1758 reg = <0 0x010c3000 0 <<
1759 }; <<
1760 <<
1761 pcie0: pcie@1c00000 { <<
1762 compatible = "qcom,pc 1740 compatible = "qcom,pcie-sm8450-pcie0";
1763 reg = <0 0x01c00000 0 1741 reg = <0 0x01c00000 0 0x3000>,
1764 <0 0x60000000 0 1742 <0 0x60000000 0 0xf1d>,
1765 <0 0x60000f20 0 1743 <0 0x60000f20 0 0xa8>,
1766 <0 0x60001000 0 1744 <0 0x60001000 0 0x1000>,
1767 <0 0x60100000 0 1745 <0 0x60100000 0 0x100000>;
1768 reg-names = "parf", " 1746 reg-names = "parf", "dbi", "elbi", "atu", "config";
1769 device_type = "pci"; 1747 device_type = "pci";
1770 linux,pci-domain = <0 1748 linux,pci-domain = <0>;
1771 bus-range = <0x00 0xf 1749 bus-range = <0x00 0xff>;
1772 num-lanes = <1>; 1750 num-lanes = <1>;
1773 1751
1774 #address-cells = <3>; 1752 #address-cells = <3>;
1775 #size-cells = <2>; 1753 #size-cells = <2>;
1776 1754
1777 ranges = <0x01000000 1755 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
1778 <0x02000000 1756 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1779 1757
1780 msi-map = <0x0 &gic_i !! 1758 /*
1781 <0x100 &gic !! 1759 * MSIs for BDF (1:0.0) only works with Device ID 0x5980.
>> 1760 * Hence, the IDs are swapped.
>> 1761 */
>> 1762 msi-map = <0x0 &gic_its 0x5981 0x1>,
>> 1763 <0x100 &gic_its 0x5980 0x1>;
1782 msi-map-mask = <0xff0 1764 msi-map-mask = <0xff00>;
1783 interrupts = <GIC_SPI !! 1765 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
1784 <GIC_SPI !! 1766 interrupt-names = "msi";
1785 <GIC_SPI <<
1786 <GIC_SPI <<
1787 <GIC_SPI <<
1788 <GIC_SPI <<
1789 <GIC_SPI <<
1790 <GIC_SPI <<
1791 interrupt-names = "ms <<
1792 "ms <<
1793 "ms <<
1794 "ms <<
1795 "ms <<
1796 "ms <<
1797 "ms <<
1798 "ms <<
1799 #interrupt-cells = <1 1767 #interrupt-cells = <1>;
1800 interrupt-map-mask = 1768 interrupt-map-mask = <0 0 0 0x7>;
1801 interrupt-map = <0 0 1769 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1802 <0 0 1770 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1803 <0 0 1771 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1804 <0 0 1772 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1805 1773
1806 interconnects = <&pci <<
1807 &mc_ <<
1808 <&gem <<
1809 &con <<
1810 interconnect-names = <<
1811 <<
1812 clocks = <&gcc GCC_PC 1774 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1813 <&gcc GCC_PC 1775 <&gcc GCC_PCIE_0_PIPE_CLK_SRC>,
1814 <&pcie0_phy> !! 1776 <&pcie0_lane>,
1815 <&rpmhcc RPM 1777 <&rpmhcc RPMH_CXO_CLK>,
1816 <&gcc GCC_PC 1778 <&gcc GCC_PCIE_0_AUX_CLK>,
1817 <&gcc GCC_PC 1779 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1818 <&gcc GCC_PC 1780 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1819 <&gcc GCC_PC 1781 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1820 <&gcc GCC_PC 1782 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
1821 <&gcc GCC_DD 1783 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1822 <&gcc GCC_AG 1784 <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
1823 <&gcc GCC_AG 1785 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
1824 clock-names = "pipe", 1786 clock-names = "pipe",
1825 "pipe_m 1787 "pipe_mux",
1826 "phy_pi 1788 "phy_pipe",
1827 "ref", 1789 "ref",
1828 "aux", 1790 "aux",
1829 "cfg", 1791 "cfg",
1830 "bus_ma 1792 "bus_master",
1831 "bus_sl 1793 "bus_slave",
1832 "slave_ 1794 "slave_q2a",
1833 "ddrss_ 1795 "ddrss_sf_tbu",
1834 "aggre0 1796 "aggre0",
1835 "aggre1 1797 "aggre1";
1836 1798
1837 iommu-map = <0x0 &a 1799 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
1838 <0x100 &a 1800 <0x100 &apps_smmu 0x1c01 0x1>;
1839 1801
1840 resets = <&gcc GCC_PC 1802 resets = <&gcc GCC_PCIE_0_BCR>;
1841 reset-names = "pci"; 1803 reset-names = "pci";
1842 1804
1843 power-domains = <&gcc 1805 power-domains = <&gcc PCIE_0_GDSC>;
1844 1806
1845 phys = <&pcie0_phy>; !! 1807 phys = <&pcie0_lane>;
1846 phy-names = "pciephy" 1808 phy-names = "pciephy";
1847 1809
1848 perst-gpios = <&tlmm 1810 perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
1849 wake-gpios = <&tlmm 9 1811 wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
1850 1812
1851 pinctrl-names = "defa 1813 pinctrl-names = "default";
1852 pinctrl-0 = <&pcie0_d 1814 pinctrl-0 = <&pcie0_default_state>;
1853 1815
1854 operating-points-v2 = <<
1855 <<
1856 status = "disabled"; 1816 status = "disabled";
1857 <<
1858 pcie0_opp_table: opp- <<
1859 compatible = <<
1860 <<
1861 /* GEN 1 x1 * <<
1862 opp-2500000 { <<
1863 opp-h <<
1864 requi <<
1865 opp-p <<
1866 }; <<
1867 <<
1868 /* GEN 2 x1 * <<
1869 opp-5000000 { <<
1870 opp-h <<
1871 requi <<
1872 opp-p <<
1873 }; <<
1874 <<
1875 /* GEN 3 x1 * <<
1876 opp-8000000 { <<
1877 opp-h <<
1878 requi <<
1879 opp-p <<
1880 }; <<
1881 }; <<
1882 <<
1883 pcie@0 { <<
1884 device_type = <<
1885 reg = <0x0 0x <<
1886 bus-range = < <<
1887 <<
1888 #address-cell <<
1889 #size-cells = <<
1890 ranges; <<
1891 }; <<
1892 }; 1817 };
1893 1818
1894 pcie0_phy: phy@1c06000 { 1819 pcie0_phy: phy@1c06000 {
1895 compatible = "qcom,sm 1820 compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy";
1896 reg = <0 0x01c06000 0 !! 1821 reg = <0 0x01c06000 0 0x200>;
1897 !! 1822 #address-cells = <2>;
>> 1823 #size-cells = <2>;
>> 1824 ranges;
1898 clocks = <&gcc GCC_PC 1825 clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
1899 <&gcc GCC_PC 1826 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1900 <&gcc GCC_PC 1827 <&gcc GCC_PCIE_0_CLKREF_EN>,
1901 <&gcc GCC_PC !! 1828 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
1902 <&gcc GCC_PC !! 1829 clock-names = "aux", "cfg_ahb", "ref", "refgen";
1903 clock-names = "aux", <<
1904 "cfg_ah <<
1905 "ref", <<
1906 "rchng" <<
1907 "pipe"; <<
1908 <<
1909 clock-output-names = <<
1910 #clock-cells = <0>; <<
1911 <<
1912 #phy-cells = <0>; <<
1913 1830
1914 resets = <&gcc GCC_PC 1831 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1915 reset-names = "phy"; 1832 reset-names = "phy";
1916 1833
1917 assigned-clocks = <&g 1834 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
1918 assigned-clock-rates 1835 assigned-clock-rates = <100000000>;
1919 1836
1920 status = "disabled"; 1837 status = "disabled";
>> 1838
>> 1839 pcie0_lane: phy@1c06200 {
>> 1840 reg = <0 0x01c06e00 0 0x200>, /* tx */
>> 1841 <0 0x01c07000 0 0x200>, /* rx */
>> 1842 <0 0x01c06200 0 0x200>, /* pcs */
>> 1843 <0 0x01c06600 0 0x200>; /* pcs_pcie */
>> 1844 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
>> 1845 clock-names = "pipe0";
>> 1846
>> 1847 #clock-cells = <0>;
>> 1848 #phy-cells = <0>;
>> 1849 clock-output-names = "pcie_0_pipe_clk";
>> 1850 };
1921 }; 1851 };
1922 1852
1923 pcie1: pcie@1c08000 { !! 1853 pcie1: pci@1c08000 {
1924 compatible = "qcom,pc 1854 compatible = "qcom,pcie-sm8450-pcie1";
1925 reg = <0 0x01c08000 0 1855 reg = <0 0x01c08000 0 0x3000>,
1926 <0 0x40000000 0 1856 <0 0x40000000 0 0xf1d>,
1927 <0 0x40000f20 0 1857 <0 0x40000f20 0 0xa8>,
1928 <0 0x40001000 0 1858 <0 0x40001000 0 0x1000>,
1929 <0 0x40100000 0 1859 <0 0x40100000 0 0x100000>;
1930 reg-names = "parf", " 1860 reg-names = "parf", "dbi", "elbi", "atu", "config";
1931 device_type = "pci"; 1861 device_type = "pci";
1932 linux,pci-domain = <1 1862 linux,pci-domain = <1>;
1933 bus-range = <0x00 0xf 1863 bus-range = <0x00 0xff>;
1934 num-lanes = <2>; 1864 num-lanes = <2>;
1935 1865
1936 #address-cells = <3>; 1866 #address-cells = <3>;
1937 #size-cells = <2>; 1867 #size-cells = <2>;
1938 1868
1939 ranges = <0x01000000 1869 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
1940 <0x02000000 1870 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1941 1871
1942 msi-map = <0x0 &gic_i !! 1872 /*
1943 <0x100 &gic !! 1873 * MSIs for BDF (1:0.0) only works with Device ID 0x5a00.
>> 1874 * Hence, the IDs are swapped.
>> 1875 */
>> 1876 msi-map = <0x0 &gic_its 0x5a01 0x1>,
>> 1877 <0x100 &gic_its 0x5a00 0x1>;
1944 msi-map-mask = <0xff0 1878 msi-map-mask = <0xff00>;
1945 interrupts = <GIC_SPI !! 1879 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
1946 <GIC_SPI !! 1880 interrupt-names = "msi";
1947 <GIC_SPI <<
1948 <GIC_SPI <<
1949 <GIC_SPI <<
1950 <GIC_SPI <<
1951 <GIC_SPI <<
1952 <GIC_SPI <<
1953 interrupt-names = "ms <<
1954 "ms <<
1955 "ms <<
1956 "ms <<
1957 "ms <<
1958 "ms <<
1959 "ms <<
1960 "ms <<
1961 #interrupt-cells = <1 1881 #interrupt-cells = <1>;
1962 interrupt-map-mask = 1882 interrupt-map-mask = <0 0 0 0x7>;
1963 interrupt-map = <0 0 1883 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1964 <0 0 1884 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1965 <0 0 1885 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1966 <0 0 1886 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1967 1887
1968 interconnects = <&pci <<
1969 &mc_ <<
1970 <&gem <<
1971 &con <<
1972 interconnect-names = <<
1973 <<
1974 clocks = <&gcc GCC_PC 1888 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1975 <&gcc GCC_PC 1889 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>,
1976 <&pcie1_phy !! 1890 <&pcie1_lane>,
1977 <&rpmhcc RPM 1891 <&rpmhcc RPMH_CXO_CLK>,
1978 <&gcc GCC_PC 1892 <&gcc GCC_PCIE_1_AUX_CLK>,
1979 <&gcc GCC_PC 1893 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1980 <&gcc GCC_PC 1894 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1981 <&gcc GCC_PC 1895 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
1982 <&gcc GCC_PC 1896 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
1983 <&gcc GCC_DD 1897 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1984 <&gcc GCC_AG 1898 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
1985 clock-names = "pipe", 1899 clock-names = "pipe",
1986 "pipe_m 1900 "pipe_mux",
1987 "phy_pi 1901 "phy_pipe",
1988 "ref", 1902 "ref",
1989 "aux", 1903 "aux",
1990 "cfg", 1904 "cfg",
1991 "bus_ma 1905 "bus_master",
1992 "bus_sl 1906 "bus_slave",
1993 "slave_ 1907 "slave_q2a",
1994 "ddrss_ 1908 "ddrss_sf_tbu",
1995 "aggre1 1909 "aggre1";
1996 1910
1997 iommu-map = <0x0 &a 1911 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
1998 <0x100 &a 1912 <0x100 &apps_smmu 0x1c81 0x1>;
1999 1913
2000 resets = <&gcc GCC_PC 1914 resets = <&gcc GCC_PCIE_1_BCR>;
2001 reset-names = "pci"; 1915 reset-names = "pci";
2002 1916
2003 power-domains = <&gcc 1917 power-domains = <&gcc PCIE_1_GDSC>;
2004 1918
2005 phys = <&pcie1_phy>; !! 1919 phys = <&pcie1_lane>;
2006 phy-names = "pciephy" 1920 phy-names = "pciephy";
2007 1921
2008 perst-gpios = <&tlmm 1922 perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
2009 wake-gpios = <&tlmm 9 1923 wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
2010 1924
2011 pinctrl-names = "defa 1925 pinctrl-names = "default";
2012 pinctrl-0 = <&pcie1_d 1926 pinctrl-0 = <&pcie1_default_state>;
2013 1927
2014 operating-points-v2 = <<
2015 <<
2016 status = "disabled"; 1928 status = "disabled";
2017 <<
2018 pcie1_opp_table: opp- <<
2019 compatible = <<
2020 <<
2021 /* GEN 1 x1 * <<
2022 opp-2500000 { <<
2023 opp-h <<
2024 requi <<
2025 opp-p <<
2026 }; <<
2027 <<
2028 /* GEN 1 x2 a <<
2029 opp-5000000 { <<
2030 opp-h <<
2031 requi <<
2032 opp-p <<
2033 }; <<
2034 <<
2035 /* GEN 2 x2 * <<
2036 opp-10000000 <<
2037 opp-h <<
2038 requi <<
2039 opp-p <<
2040 }; <<
2041 <<
2042 /* GEN 3 x1 * <<
2043 opp-8000000 { <<
2044 opp-h <<
2045 requi <<
2046 opp-p <<
2047 }; <<
2048 <<
2049 /* GEN 3 x2 a <<
2050 opp-16000000 <<
2051 opp-h <<
2052 requi <<
2053 opp-p <<
2054 }; <<
2055 <<
2056 /* GEN 4 x2 * <<
2057 opp-32000000 <<
2058 opp-h <<
2059 requi <<
2060 opp-p <<
2061 }; <<
2062 }; <<
2063 <<
2064 pcie@0 { <<
2065 device_type = <<
2066 reg = <0x0 0x <<
2067 bus-range = < <<
2068 <<
2069 #address-cell <<
2070 #size-cells = <<
2071 ranges; <<
2072 }; <<
2073 }; 1929 };
2074 1930
2075 pcie1_phy: phy@1c0e000 { !! 1931 pcie1_phy: phy@1c0f000 {
2076 compatible = "qcom,sm 1932 compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy";
2077 reg = <0 0x01c0e000 0 !! 1933 reg = <0 0x01c0f000 0 0x200>;
2078 !! 1934 #address-cells = <2>;
>> 1935 #size-cells = <2>;
>> 1936 ranges;
2079 clocks = <&gcc GCC_PC 1937 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>,
2080 <&gcc GCC_PC 1938 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2081 <&gcc GCC_PC 1939 <&gcc GCC_PCIE_1_CLKREF_EN>,
2082 <&gcc GCC_PC !! 1940 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
2083 <&gcc GCC_PC !! 1941 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2084 clock-names = "aux", <<
2085 "cfg_ah <<
2086 "ref", <<
2087 "rchng" <<
2088 "pipe"; <<
2089 <<
2090 clock-output-names = <<
2091 #clock-cells = <1>; <<
2092 <<
2093 #phy-cells = <0>; <<
2094 1942
2095 resets = <&gcc GCC_PC 1943 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2096 reset-names = "phy"; 1944 reset-names = "phy";
2097 1945
2098 assigned-clocks = <&g 1946 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
2099 assigned-clock-rates 1947 assigned-clock-rates = <100000000>;
2100 1948
2101 status = "disabled"; 1949 status = "disabled";
>> 1950
>> 1951 pcie1_lane: phy@1c0e000 {
>> 1952 reg = <0 0x01c0e000 0 0x200>, /* tx */
>> 1953 <0 0x01c0e200 0 0x300>, /* rx */
>> 1954 <0 0x01c0f200 0 0x200>, /* pcs */
>> 1955 <0 0x01c0e800 0 0x200>, /* tx */
>> 1956 <0 0x01c0ea00 0 0x300>, /* rx */
>> 1957 <0 0x01c0f400 0 0xc00>; /* pcs_pcie */
>> 1958 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
>> 1959 clock-names = "pipe0";
>> 1960
>> 1961 #clock-cells = <0>;
>> 1962 #phy-cells = <0>;
>> 1963 clock-output-names = "pcie_1_pipe_clk";
>> 1964 };
2102 }; 1965 };
2103 1966
2104 config_noc: interconnect@1500 1967 config_noc: interconnect@1500000 {
2105 compatible = "qcom,sm 1968 compatible = "qcom,sm8450-config-noc";
2106 reg = <0 0x01500000 0 1969 reg = <0 0x01500000 0 0x1c000>;
2107 #interconnect-cells = 1970 #interconnect-cells = <2>;
2108 qcom,bcm-voters = <&a 1971 qcom,bcm-voters = <&apps_bcm_voter>;
2109 }; 1972 };
2110 1973
2111 system_noc: interconnect@1680 1974 system_noc: interconnect@1680000 {
2112 compatible = "qcom,sm 1975 compatible = "qcom,sm8450-system-noc";
2113 reg = <0 0x01680000 0 1976 reg = <0 0x01680000 0 0x1e200>;
2114 #interconnect-cells = 1977 #interconnect-cells = <2>;
2115 qcom,bcm-voters = <&a 1978 qcom,bcm-voters = <&apps_bcm_voter>;
2116 }; 1979 };
2117 1980
2118 pcie_noc: interconnect@16c000 1981 pcie_noc: interconnect@16c0000 {
2119 compatible = "qcom,sm 1982 compatible = "qcom,sm8450-pcie-anoc";
2120 reg = <0 0x016c0000 0 1983 reg = <0 0x016c0000 0 0xe280>;
2121 #interconnect-cells = 1984 #interconnect-cells = <2>;
2122 qcom,bcm-voters = <&a 1985 qcom,bcm-voters = <&apps_bcm_voter>;
2123 }; 1986 };
2124 1987
2125 aggre1_noc: interconnect@16e0 1988 aggre1_noc: interconnect@16e0000 {
2126 compatible = "qcom,sm 1989 compatible = "qcom,sm8450-aggre1-noc";
2127 reg = <0 0x016e0000 0 1990 reg = <0 0x016e0000 0 0x1c080>;
2128 #interconnect-cells = 1991 #interconnect-cells = <2>;
2129 clocks = <&gcc GCC_AG 1992 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2130 <&gcc GCC_AG 1993 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
2131 qcom,bcm-voters = <&a 1994 qcom,bcm-voters = <&apps_bcm_voter>;
2132 }; 1995 };
2133 1996
2134 aggre2_noc: interconnect@1700 1997 aggre2_noc: interconnect@1700000 {
2135 compatible = "qcom,sm 1998 compatible = "qcom,sm8450-aggre2-noc";
2136 reg = <0 0x01700000 0 1999 reg = <0 0x01700000 0 0x31080>;
2137 #interconnect-cells = 2000 #interconnect-cells = <2>;
2138 qcom,bcm-voters = <&a 2001 qcom,bcm-voters = <&apps_bcm_voter>;
2139 clocks = <&gcc GCC_AG 2002 clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
2140 <&gcc GCC_AG 2003 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
2141 <&gcc GCC_AG 2004 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2142 <&rpmhcc RPM 2005 <&rpmhcc RPMH_IPA_CLK>;
2143 }; 2006 };
2144 2007
2145 mmss_noc: interconnect@174000 2008 mmss_noc: interconnect@1740000 {
2146 compatible = "qcom,sm 2009 compatible = "qcom,sm8450-mmss-noc";
2147 reg = <0 0x01740000 0 2010 reg = <0 0x01740000 0 0x1f080>;
2148 #interconnect-cells = 2011 #interconnect-cells = <2>;
2149 qcom,bcm-voters = <&a 2012 qcom,bcm-voters = <&apps_bcm_voter>;
2150 }; 2013 };
2151 2014
2152 tcsr_mutex: hwlock@1f40000 { 2015 tcsr_mutex: hwlock@1f40000 {
2153 compatible = "qcom,tc 2016 compatible = "qcom,tcsr-mutex";
2154 reg = <0x0 0x01f40000 2017 reg = <0x0 0x01f40000 0x0 0x40000>;
2155 #hwlock-cells = <1>; 2018 #hwlock-cells = <1>;
2156 }; 2019 };
2157 2020
2158 tcsr: syscon@1fc0000 { 2021 tcsr: syscon@1fc0000 {
2159 compatible = "qcom,sm 2022 compatible = "qcom,sm8450-tcsr", "syscon";
2160 reg = <0x0 0x1fc0000 2023 reg = <0x0 0x1fc0000 0x0 0x30000>;
2161 }; 2024 };
2162 2025
2163 gpu: gpu@3d00000 { <<
2164 compatible = "qcom,ad <<
2165 reg = <0x0 0x03d00000 <<
2166 <0x0 0x03d9e000 <<
2167 <0x0 0x03d61000 <<
2168 reg-names = "kgsl_3d0 <<
2169 "cx_mem", <<
2170 "cx_dbgc" <<
2171 <<
2172 interrupts = <GIC_SPI <<
2173 <<
2174 iommus = <&adreno_smm <<
2175 <&adreno_smm <<
2176 <<
2177 operating-points-v2 = <<
2178 <<
2179 qcom,gmu = <&gmu>; <<
2180 #cooling-cells = <2>; <<
2181 <<
2182 status = "disabled"; <<
2183 <<
2184 zap-shader { <<
2185 memory-region <<
2186 }; <<
2187 <<
2188 gpu_opp_table: opp-ta <<
2189 compatible = <<
2190 <<
2191 opp-818000000 <<
2192 opp-h <<
2193 opp-l <<
2194 }; <<
2195 <<
2196 opp-791000000 <<
2197 opp-h <<
2198 opp-l <<
2199 }; <<
2200 <<
2201 opp-734000000 <<
2202 opp-h <<
2203 opp-l <<
2204 }; <<
2205 <<
2206 opp-640000000 <<
2207 opp-h <<
2208 opp-l <<
2209 }; <<
2210 <<
2211 opp-599000000 <<
2212 opp-h <<
2213 opp-l <<
2214 }; <<
2215 <<
2216 opp-545000000 <<
2217 opp-h <<
2218 opp-l <<
2219 }; <<
2220 <<
2221 opp-492000000 <<
2222 opp-h <<
2223 opp-l <<
2224 }; <<
2225 <<
2226 opp-421000000 <<
2227 opp-h <<
2228 opp-l <<
2229 }; <<
2230 <<
2231 opp-350000000 <<
2232 opp-h <<
2233 opp-l <<
2234 }; <<
2235 <<
2236 opp-317000000 <<
2237 opp-h <<
2238 opp-l <<
2239 }; <<
2240 <<
2241 opp-285000000 <<
2242 opp-h <<
2243 opp-l <<
2244 }; <<
2245 <<
2246 opp-220000000 <<
2247 opp-h <<
2248 opp-l <<
2249 }; <<
2250 }; <<
2251 }; <<
2252 <<
2253 gmu: gmu@3d6a000 { <<
2254 compatible = "qcom,ad <<
2255 reg = <0x0 0x03d6a000 <<
2256 <0x0 0x03d50000 <<
2257 <0x0 0x0b290000 <<
2258 reg-names = "gmu", "r <<
2259 <<
2260 interrupts = <GIC_SPI <<
2261 <GIC_SPI <<
2262 interrupt-names = "hf <<
2263 <<
2264 clocks = <&gpucc GPU_ <<
2265 <&gpucc GPU_ <<
2266 <&gpucc GPU_ <<
2267 <&gcc GCC_DD <<
2268 <&gcc GCC_GP <<
2269 <&gpucc GPU_ <<
2270 <&gpucc GPU_ <<
2271 clock-names = "ahb", <<
2272 "gmu", <<
2273 "cxo", <<
2274 "axi", <<
2275 "memnoc <<
2276 "hub", <<
2277 "demet" <<
2278 <<
2279 power-domains = <&gpu <<
2280 <&gpu <<
2281 power-domain-names = <<
2282 <<
2283 <<
2284 iommus = <&adreno_smm <<
2285 <<
2286 qcom,qmp = <&aoss_qmp <<
2287 <<
2288 operating-points-v2 = <<
2289 <<
2290 gmu_opp_table: opp-ta <<
2291 compatible = <<
2292 <<
2293 opp-500000000 <<
2294 opp-h <<
2295 opp-l <<
2296 }; <<
2297 <<
2298 opp-200000000 <<
2299 opp-h <<
2300 opp-l <<
2301 }; <<
2302 }; <<
2303 }; <<
2304 <<
2305 gpucc: clock-controller@3d900 <<
2306 compatible = "qcom,sm <<
2307 reg = <0x0 0x03d90000 <<
2308 clocks = <&rpmhcc RPM <<
2309 <&gcc GCC_GP <<
2310 <&gcc GCC_GP <<
2311 #clock-cells = <1>; <<
2312 #reset-cells = <1>; <<
2313 #power-domain-cells = <<
2314 }; <<
2315 <<
2316 adreno_smmu: iommu@3da0000 { <<
2317 compatible = "qcom,sm <<
2318 "qcom,sm <<
2319 reg = <0x0 0x03da0000 <<
2320 #iommu-cells = <2>; <<
2321 #global-interrupts = <<
2322 interrupts = <GIC_SPI <<
2323 <GIC_SPI <<
2324 <GIC_SPI <<
2325 <GIC_SPI <<
2326 <GIC_SPI <<
2327 <GIC_SPI <<
2328 <GIC_SPI <<
2329 <GIC_SPI <<
2330 <GIC_SPI <<
2331 <GIC_SPI <<
2332 <GIC_SPI <<
2333 <GIC_SPI <<
2334 <GIC_SPI <<
2335 <GIC_SPI <<
2336 <GIC_SPI <<
2337 <GIC_SPI <<
2338 <GIC_SPI <<
2339 <GIC_SPI <<
2340 <GIC_SPI <<
2341 <GIC_SPI <<
2342 <GIC_SPI <<
2343 <GIC_SPI <<
2344 <GIC_SPI <<
2345 <GIC_SPI <<
2346 <GIC_SPI <<
2347 <GIC_SPI <<
2348 clocks = <&gpucc GPU_ <<
2349 <&gpucc GPU_ <<
2350 <&gpucc GPU_ <<
2351 <&gcc GCC_GP <<
2352 <&gcc GCC_GP <<
2353 <&gpucc GPU_ <<
2354 clock-names = "gmu", <<
2355 "hub", <<
2356 "hlos", <<
2357 "bus", <<
2358 "iface" <<
2359 "ahb"; <<
2360 power-domains = <&gpu <<
2361 dma-coherent; <<
2362 }; <<
2363 <<
2364 usb_1_hsphy: phy@88e3000 { 2026 usb_1_hsphy: phy@88e3000 {
2365 compatible = "qcom,sm 2027 compatible = "qcom,sm8450-usb-hs-phy",
2366 "qcom,us 2028 "qcom,usb-snps-hs-7nm-phy";
2367 reg = <0 0x088e3000 0 2029 reg = <0 0x088e3000 0 0x400>;
2368 status = "disabled"; 2030 status = "disabled";
2369 #phy-cells = <0>; 2031 #phy-cells = <0>;
2370 2032
2371 clocks = <&rpmhcc RPM 2033 clocks = <&rpmhcc RPMH_CXO_CLK>;
2372 clock-names = "ref"; 2034 clock-names = "ref";
2373 2035
2374 resets = <&gcc GCC_QU 2036 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2375 }; 2037 };
2376 2038
2377 usb_1_qmpphy: phy@88e8000 { 2039 usb_1_qmpphy: phy@88e8000 {
2378 compatible = "qcom,sm 2040 compatible = "qcom,sm8450-qmp-usb3-dp-phy";
2379 reg = <0 0x088e8000 0 2041 reg = <0 0x088e8000 0 0x3000>;
2380 2042
2381 clocks = <&gcc GCC_US 2043 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2382 <&rpmhcc RPM 2044 <&rpmhcc RPMH_CXO_CLK>,
2383 <&gcc GCC_US 2045 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
2384 <&gcc GCC_US 2046 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2385 clock-names = "aux", 2047 clock-names = "aux", "ref", "com_aux", "usb3_pipe";
2386 2048
2387 resets = <&gcc GCC_US 2049 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
2388 <&gcc GCC_US 2050 <&gcc GCC_USB3_PHY_PRIM_BCR>;
2389 reset-names = "phy", 2051 reset-names = "phy", "common";
2390 2052
2391 #clock-cells = <1>; 2053 #clock-cells = <1>;
2392 #phy-cells = <1>; 2054 #phy-cells = <1>;
2393 2055
2394 orientation-switch; <<
2395 <<
2396 status = "disabled"; 2056 status = "disabled";
2397 2057
2398 ports { 2058 ports {
2399 #address-cell 2059 #address-cells = <1>;
2400 #size-cells = 2060 #size-cells = <0>;
2401 2061
2402 port@0 { 2062 port@0 {
2403 reg = 2063 reg = <0>;
2404 2064
2405 usb_1 2065 usb_1_qmpphy_out: endpoint {
2406 }; 2066 };
2407 }; 2067 };
2408 2068
2409 port@1 { 2069 port@1 {
2410 reg = 2070 reg = <1>;
2411 2071
2412 usb_1 2072 usb_1_qmpphy_usb_ss_in: endpoint {
2413 <<
2414 }; 2073 };
2415 }; 2074 };
2416 2075
2417 port@2 { 2076 port@2 {
2418 reg = 2077 reg = <2>;
2419 2078
2420 usb_1 2079 usb_1_qmpphy_dp_in: endpoint {
2421 <<
2422 }; 2080 };
2423 }; 2081 };
2424 }; 2082 };
2425 }; 2083 };
2426 2084
2427 remoteproc_slpi: remoteproc@2 2085 remoteproc_slpi: remoteproc@2400000 {
2428 compatible = "qcom,sm 2086 compatible = "qcom,sm8450-slpi-pas";
2429 reg = <0 0x02400000 0 2087 reg = <0 0x02400000 0 0x4000>;
2430 2088
2431 interrupts-extended = 2089 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>,
2432 2090 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
2433 2091 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
2434 2092 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
2435 2093 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
2436 interrupt-names = "wd 2094 interrupt-names = "wdog", "fatal", "ready",
2437 "ha 2095 "handover", "stop-ack";
2438 2096
2439 clocks = <&rpmhcc RPM 2097 clocks = <&rpmhcc RPMH_CXO_CLK>;
2440 clock-names = "xo"; 2098 clock-names = "xo";
2441 2099
2442 power-domains = <&rpm !! 2100 power-domains = <&rpmhpd SM8450_LCX>,
2443 <&rpm !! 2101 <&rpmhpd SM8450_LMX>;
2444 power-domain-names = 2102 power-domain-names = "lcx", "lmx";
2445 2103
2446 memory-region = <&slp 2104 memory-region = <&slpi_mem>;
2447 2105
2448 qcom,qmp = <&aoss_qmp 2106 qcom,qmp = <&aoss_qmp>;
2449 2107
2450 qcom,smem-states = <& 2108 qcom,smem-states = <&smp2p_slpi_out 0>;
2451 qcom,smem-state-names 2109 qcom,smem-state-names = "stop";
2452 2110
2453 status = "disabled"; 2111 status = "disabled";
2454 2112
2455 glink-edge { 2113 glink-edge {
2456 interrupts-ex 2114 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
2457 2115 IPCC_MPROC_SIGNAL_GLINK_QMP
2458 2116 IRQ_TYPE_EDGE_RISING>;
2459 mboxes = <&ip 2117 mboxes = <&ipcc IPCC_CLIENT_SLPI
2460 2118 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2461 2119
2462 label = "slpi 2120 label = "slpi";
2463 qcom,remote-p 2121 qcom,remote-pid = <3>;
2464 2122
2465 fastrpc { 2123 fastrpc {
2466 compa 2124 compatible = "qcom,fastrpc";
2467 qcom, 2125 qcom,glink-channels = "fastrpcglink-apps-dsp";
2468 label 2126 label = "sdsp";
2469 qcom, <<
2470 #addr 2127 #address-cells = <1>;
2471 #size 2128 #size-cells = <0>;
2472 2129
2473 compu 2130 compute-cb@1 {
2474 2131 compatible = "qcom,fastrpc-compute-cb";
2475 2132 reg = <1>;
2476 2133 iommus = <&apps_smmu 0x0541 0x0>;
2477 }; 2134 };
2478 2135
2479 compu 2136 compute-cb@2 {
2480 2137 compatible = "qcom,fastrpc-compute-cb";
2481 2138 reg = <2>;
2482 2139 iommus = <&apps_smmu 0x0542 0x0>;
2483 }; 2140 };
2484 2141
2485 compu 2142 compute-cb@3 {
2486 2143 compatible = "qcom,fastrpc-compute-cb";
2487 2144 reg = <3>;
2488 2145 iommus = <&apps_smmu 0x0543 0x0>;
2489 2146 /* note: shared-cb = <4> in downstream */
2490 }; 2147 };
2491 }; 2148 };
2492 }; 2149 };
2493 }; 2150 };
2494 2151
2495 wsa2macro: codec@31e0000 { 2152 wsa2macro: codec@31e0000 {
2496 compatible = "qcom,sm 2153 compatible = "qcom,sm8450-lpass-wsa-macro";
2497 reg = <0 0x031e0000 0 2154 reg = <0 0x031e0000 0 0x1000>;
2498 clocks = <&q6prmcc LP 2155 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2499 <&q6prmcc LP 2156 <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2500 <&q6prmcc LP 2157 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2501 <&q6prmcc LP 2158 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2502 <&vamacro>; 2159 <&vamacro>;
2503 clock-names = "mclk", 2160 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
>> 2161 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 2162 <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
>> 2163 assigned-clock-rates = <19200000>, <19200000>;
2504 2164
2505 #clock-cells = <0>; 2165 #clock-cells = <0>;
2506 clock-output-names = 2166 clock-output-names = "wsa2-mclk";
>> 2167 pinctrl-names = "default";
>> 2168 pinctrl-0 = <&wsa2_swr_active>;
2507 #sound-dai-cells = <1 2169 #sound-dai-cells = <1>;
2508 }; 2170 };
2509 2171
2510 swr4: soundwire@31f0000 { !! 2172 swr4: soundwire-controller@31f0000 {
2511 compatible = "qcom,so 2173 compatible = "qcom,soundwire-v1.7.0";
2512 reg = <0 0x031f0000 0 2174 reg = <0 0x031f0000 0 0x2000>;
2513 interrupts = <GIC_SPI 2175 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
2514 clocks = <&wsa2macro> 2176 clocks = <&wsa2macro>;
2515 clock-names = "iface" 2177 clock-names = "iface";
2516 label = "WSA2"; 2178 label = "WSA2";
2517 2179
2518 pinctrl-0 = <&wsa2_sw <<
2519 pinctrl-names = "defa <<
2520 <<
2521 qcom,din-ports = <2>; 2180 qcom,din-ports = <2>;
2522 qcom,dout-ports = <6> 2181 qcom,dout-ports = <6>;
2523 2182
2524 qcom,ports-sinterval- 2183 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2525 qcom,ports-offset1 = 2184 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2526 qcom,ports-offset2 = 2185 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2527 qcom,ports-hstart = 2186 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2528 qcom,ports-hstop = 2187 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2529 qcom,ports-word-lengt 2188 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2530 qcom,ports-block-pack 2189 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
2531 qcom,ports-block-grou 2190 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2532 qcom,ports-lane-contr 2191 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2533 2192
2534 #address-cells = <2>; 2193 #address-cells = <2>;
2535 #size-cells = <0>; 2194 #size-cells = <0>;
2536 #sound-dai-cells = <1 2195 #sound-dai-cells = <1>;
2537 status = "disabled"; 2196 status = "disabled";
2538 }; 2197 };
2539 2198
2540 rxmacro: codec@3200000 { 2199 rxmacro: codec@3200000 {
2541 compatible = "qcom,sm 2200 compatible = "qcom,sm8450-lpass-rx-macro";
2542 reg = <0 0x03200000 0 2201 reg = <0 0x03200000 0 0x1000>;
2543 clocks = <&q6prmcc LP 2202 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2544 <&q6prmcc LP 2203 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2545 <&q6prmcc LP 2204 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2546 <&q6prmcc LP 2205 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2547 <&vamacro>; 2206 <&vamacro>;
2548 clock-names = "mclk", 2207 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2549 2208
>> 2209 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 2210 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
>> 2211 assigned-clock-rates = <19200000>, <19200000>;
>> 2212
2550 #clock-cells = <0>; 2213 #clock-cells = <0>;
2551 clock-output-names = 2214 clock-output-names = "mclk";
>> 2215 pinctrl-names = "default";
>> 2216 pinctrl-0 = <&rx_swr_active>;
2552 #sound-dai-cells = <1 2217 #sound-dai-cells = <1>;
2553 }; 2218 };
2554 2219
2555 swr1: soundwire@3210000 { !! 2220 swr1: soundwire-controller@3210000 {
2556 compatible = "qcom,so 2221 compatible = "qcom,soundwire-v1.7.0";
2557 reg = <0 0x03210000 0 2222 reg = <0 0x03210000 0 0x2000>;
2558 interrupts = <GIC_SPI 2223 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
2559 clocks = <&rxmacro>; 2224 clocks = <&rxmacro>;
2560 clock-names = "iface" 2225 clock-names = "iface";
2561 label = "RX"; 2226 label = "RX";
2562 qcom,din-ports = <0>; 2227 qcom,din-ports = <0>;
2563 qcom,dout-ports = <5> 2228 qcom,dout-ports = <5>;
2564 2229
2565 pinctrl-0 = <&rx_swr_ <<
2566 pinctrl-names = "defa <<
2567 <<
2568 qcom,ports-sinterval- 2230 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
2569 qcom,ports-offset1 = 2231 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>;
2570 qcom,ports-offset2 = 2232 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
2571 qcom,ports-hstart = 2233 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
2572 qcom,ports-hstop = 2234 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
2573 qcom,ports-word-lengt 2235 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2574 qcom,ports-block-pack 2236 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
2575 qcom,ports-block-grou 2237 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
2576 qcom,ports-lane-contr 2238 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2577 2239
2578 #address-cells = <2>; 2240 #address-cells = <2>;
2579 #size-cells = <0>; 2241 #size-cells = <0>;
2580 #sound-dai-cells = <1 2242 #sound-dai-cells = <1>;
2581 status = "disabled"; 2243 status = "disabled";
2582 }; 2244 };
2583 2245
2584 txmacro: codec@3220000 { 2246 txmacro: codec@3220000 {
2585 compatible = "qcom,sm 2247 compatible = "qcom,sm8450-lpass-tx-macro";
2586 reg = <0 0x03220000 0 2248 reg = <0 0x03220000 0 0x1000>;
2587 clocks = <&q6prmcc LP 2249 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2588 <&q6prmcc LP 2250 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2589 <&q6prmcc LP 2251 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2590 <&q6prmcc LP 2252 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2591 <&vamacro>; 2253 <&vamacro>;
2592 clock-names = "mclk", 2254 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
>> 2255 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 2256 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
>> 2257 assigned-clock-rates = <19200000>, <19200000>;
2593 2258
2594 #clock-cells = <0>; 2259 #clock-cells = <0>;
2595 clock-output-names = 2260 clock-output-names = "mclk";
>> 2261 pinctrl-names = "default";
>> 2262 pinctrl-0 = <&tx_swr_active>;
2596 #sound-dai-cells = <1 2263 #sound-dai-cells = <1>;
2597 }; 2264 };
2598 2265
2599 wsamacro: codec@3240000 { 2266 wsamacro: codec@3240000 {
2600 compatible = "qcom,sm 2267 compatible = "qcom,sm8450-lpass-wsa-macro";
2601 reg = <0 0x03240000 0 2268 reg = <0 0x03240000 0 0x1000>;
2602 clocks = <&q6prmcc LP 2269 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2603 <&q6prmcc LP 2270 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2604 <&q6prmcc LP 2271 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2605 <&q6prmcc LP 2272 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2606 <&vamacro>; 2273 <&vamacro>;
2607 clock-names = "mclk", 2274 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2608 2275
>> 2276 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 2277 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
>> 2278 assigned-clock-rates = <19200000>, <19200000>;
>> 2279
2609 #clock-cells = <0>; 2280 #clock-cells = <0>;
2610 clock-output-names = 2281 clock-output-names = "mclk";
>> 2282 pinctrl-names = "default";
>> 2283 pinctrl-0 = <&wsa_swr_active>;
2611 #sound-dai-cells = <1 2284 #sound-dai-cells = <1>;
2612 }; 2285 };
2613 2286
2614 swr0: soundwire@3250000 { !! 2287 swr0: soundwire-controller@3250000 {
2615 compatible = "qcom,so 2288 compatible = "qcom,soundwire-v1.7.0";
2616 reg = <0 0x03250000 0 2289 reg = <0 0x03250000 0 0x2000>;
2617 interrupts = <GIC_SPI 2290 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
2618 clocks = <&wsamacro>; 2291 clocks = <&wsamacro>;
2619 clock-names = "iface" 2292 clock-names = "iface";
2620 label = "WSA"; 2293 label = "WSA";
2621 2294
2622 pinctrl-0 = <&wsa_swr <<
2623 pinctrl-names = "defa <<
2624 <<
2625 qcom,din-ports = <2>; 2295 qcom,din-ports = <2>;
2626 qcom,dout-ports = <6> 2296 qcom,dout-ports = <6>;
2627 2297
2628 qcom,ports-sinterval- 2298 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2629 qcom,ports-offset1 = 2299 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2630 qcom,ports-offset2 = 2300 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2631 qcom,ports-hstart = 2301 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2632 qcom,ports-hstop = 2302 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2633 qcom,ports-word-lengt 2303 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2634 qcom,ports-block-pack 2304 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
2635 qcom,ports-block-grou 2305 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2636 qcom,ports-lane-contr 2306 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2637 2307
2638 #address-cells = <2>; 2308 #address-cells = <2>;
2639 #size-cells = <0>; 2309 #size-cells = <0>;
2640 #sound-dai-cells = <1 2310 #sound-dai-cells = <1>;
2641 status = "disabled"; 2311 status = "disabled";
2642 }; 2312 };
2643 2313
2644 swr2: soundwire@33b0000 { !! 2314 swr2: soundwire-controller@33b0000 {
2645 compatible = "qcom,so 2315 compatible = "qcom,soundwire-v1.7.0";
2646 reg = <0 0x033b0000 0 2316 reg = <0 0x033b0000 0 0x2000>;
2647 interrupts = <GIC_SPI 2317 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
2648 <GIC_SPI 2318 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>;
2649 interrupt-names = "co 2319 interrupt-names = "core", "wakeup";
2650 2320
2651 clocks = <&txmacro>; !! 2321 clocks = <&vamacro>;
2652 clock-names = "iface" 2322 clock-names = "iface";
2653 label = "TX"; 2323 label = "TX";
2654 2324
2655 pinctrl-0 = <&tx_swr_ <<
2656 pinctrl-names = "defa <<
2657 <<
2658 qcom,din-ports = <4>; 2325 qcom,din-ports = <4>;
2659 qcom,dout-ports = <0> 2326 qcom,dout-ports = <0>;
2660 qcom,ports-sinterval- 2327 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
2661 qcom,ports-offset1 = 2328 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>;
2662 qcom,ports-offset2 = 2329 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
2663 qcom,ports-hstart = 2330 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
2664 qcom,ports-hstop = 2331 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
2665 qcom,ports-word-lengt 2332 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
2666 qcom,ports-block-pack 2333 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
2667 qcom,ports-block-grou 2334 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
2668 qcom,ports-lane-contr 2335 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>;
2669 2336
2670 #address-cells = <2>; 2337 #address-cells = <2>;
2671 #size-cells = <0>; 2338 #size-cells = <0>;
2672 #sound-dai-cells = <1 2339 #sound-dai-cells = <1>;
2673 status = "disabled"; 2340 status = "disabled";
2674 }; 2341 };
2675 2342
2676 vamacro: codec@33f0000 { 2343 vamacro: codec@33f0000 {
2677 compatible = "qcom,sm 2344 compatible = "qcom,sm8450-lpass-va-macro";
2678 reg = <0 0x033f0000 0 2345 reg = <0 0x033f0000 0 0x1000>;
2679 clocks = <&q6prmcc LP 2346 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2680 <&q6prmcc LP 2347 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2681 <&q6prmcc LP 2348 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2682 <&q6prmcc LP 2349 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2683 clock-names = "mclk", 2350 clock-names = "mclk", "macro", "dcodec", "npl";
>> 2351 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
>> 2352 assigned-clock-rates = <19200000>;
2684 2353
2685 #clock-cells = <0>; 2354 #clock-cells = <0>;
2686 clock-output-names = 2355 clock-output-names = "fsgen";
2687 #sound-dai-cells = <1 2356 #sound-dai-cells = <1>;
2688 status = "disabled"; 2357 status = "disabled";
2689 }; 2358 };
2690 2359
2691 remoteproc_adsp: remoteproc@3 2360 remoteproc_adsp: remoteproc@30000000 {
2692 compatible = "qcom,sm 2361 compatible = "qcom,sm8450-adsp-pas";
2693 reg = <0 0x30000000 0 2362 reg = <0 0x30000000 0 0x100>;
2694 2363
2695 interrupts-extended = 2364 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
2696 2365 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
2697 2366 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
2698 2367 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
2699 2368 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
2700 interrupt-names = "wd 2369 interrupt-names = "wdog", "fatal", "ready",
2701 "ha 2370 "handover", "stop-ack";
2702 2371
2703 clocks = <&rpmhcc RPM 2372 clocks = <&rpmhcc RPMH_CXO_CLK>;
2704 clock-names = "xo"; 2373 clock-names = "xo";
2705 2374
2706 power-domains = <&rpm !! 2375 power-domains = <&rpmhpd SM8450_LCX>,
2707 <&rpm !! 2376 <&rpmhpd SM8450_LMX>;
2708 power-domain-names = 2377 power-domain-names = "lcx", "lmx";
2709 2378
2710 memory-region = <&ads 2379 memory-region = <&adsp_mem>;
2711 2380
2712 qcom,qmp = <&aoss_qmp 2381 qcom,qmp = <&aoss_qmp>;
2713 2382
2714 qcom,smem-states = <& 2383 qcom,smem-states = <&smp2p_adsp_out 0>;
2715 qcom,smem-state-names 2384 qcom,smem-state-names = "stop";
2716 2385
2717 status = "disabled"; 2386 status = "disabled";
2718 2387
2719 remoteproc_adsp_glink 2388 remoteproc_adsp_glink: glink-edge {
2720 interrupts-ex 2389 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
2721 2390 IPCC_MPROC_SIGNAL_GLINK_QMP
2722 2391 IRQ_TYPE_EDGE_RISING>;
2723 mboxes = <&ip 2392 mboxes = <&ipcc IPCC_CLIENT_LPASS
2724 2393 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2725 2394
2726 label = "lpas 2395 label = "lpass";
2727 qcom,remote-p 2396 qcom,remote-pid = <2>;
2728 2397
2729 gpr { 2398 gpr {
2730 compa 2399 compatible = "qcom,gpr";
2731 qcom, 2400 qcom,glink-channels = "adsp_apps";
2732 qcom, 2401 qcom,domain = <GPR_DOMAIN_ID_ADSP>;
2733 qcom, 2402 qcom,intents = <512 20>;
2734 #addr 2403 #address-cells = <1>;
2735 #size 2404 #size-cells = <0>;
2736 2405
2737 q6apm 2406 q6apm: service@1 {
2738 2407 compatible = "qcom,q6apm";
2739 2408 reg = <GPR_APM_MODULE_IID>;
2740 2409 #sound-dai-cells = <0>;
2741 2410 qcom,protection-domain = "avs/audio",
2742 2411 "msm/adsp/audio_pd";
2743 2412
2744 2413 q6apmdai: dais {
2745 2414 compatible = "qcom,q6apm-dais";
2746 2415 iommus = <&apps_smmu 0x1801 0x0>;
2747 2416 };
2748 2417
2749 2418 q6apmbedai: bedais {
2750 2419 compatible = "qcom,q6apm-lpass-dais";
2751 2420 #sound-dai-cells = <1>;
2752 2421 };
2753 }; 2422 };
2754 2423
2755 q6prm 2424 q6prm: service@2 {
2756 2425 compatible = "qcom,q6prm";
2757 2426 reg = <GPR_PRM_MODULE_IID>;
2758 2427 qcom,protection-domain = "avs/audio",
2759 2428 "msm/adsp/audio_pd";
2760 2429
2761 2430 q6prmcc: clock-controller {
2762 2431 compatible = "qcom,q6prm-lpass-clocks";
2763 2432 #clock-cells = <2>;
2764 2433 };
2765 }; 2434 };
2766 }; 2435 };
2767 2436
2768 fastrpc { 2437 fastrpc {
2769 compa 2438 compatible = "qcom,fastrpc";
2770 qcom, 2439 qcom,glink-channels = "fastrpcglink-apps-dsp";
2771 label 2440 label = "adsp";
2772 qcom, <<
2773 #addr 2441 #address-cells = <1>;
2774 #size 2442 #size-cells = <0>;
2775 2443
2776 compu 2444 compute-cb@3 {
2777 2445 compatible = "qcom,fastrpc-compute-cb";
2778 2446 reg = <3>;
2779 2447 iommus = <&apps_smmu 0x1803 0x0>;
2780 }; 2448 };
2781 2449
2782 compu 2450 compute-cb@4 {
2783 2451 compatible = "qcom,fastrpc-compute-cb";
2784 2452 reg = <4>;
2785 2453 iommus = <&apps_smmu 0x1804 0x0>;
2786 }; 2454 };
2787 2455
2788 compu 2456 compute-cb@5 {
2789 2457 compatible = "qcom,fastrpc-compute-cb";
2790 2458 reg = <5>;
2791 2459 iommus = <&apps_smmu 0x1805 0x0>;
2792 }; 2460 };
2793 }; 2461 };
2794 }; 2462 };
2795 }; 2463 };
2796 2464
2797 remoteproc_cdsp: remoteproc@3 2465 remoteproc_cdsp: remoteproc@32300000 {
2798 compatible = "qcom,sm 2466 compatible = "qcom,sm8450-cdsp-pas";
2799 reg = <0 0x32300000 0 2467 reg = <0 0x32300000 0 0x1400000>;
2800 2468
2801 interrupts-extended = 2469 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
2802 2470 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
2803 2471 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
2804 2472 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
2805 2473 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
2806 interrupt-names = "wd 2474 interrupt-names = "wdog", "fatal", "ready",
2807 "ha 2475 "handover", "stop-ack";
2808 2476
2809 clocks = <&rpmhcc RPM 2477 clocks = <&rpmhcc RPMH_CXO_CLK>;
2810 clock-names = "xo"; 2478 clock-names = "xo";
2811 2479
2812 power-domains = <&rpm !! 2480 power-domains = <&rpmhpd SM8450_CX>,
2813 <&rpm !! 2481 <&rpmhpd SM8450_MXC>;
2814 power-domain-names = 2482 power-domain-names = "cx", "mxc";
2815 2483
2816 memory-region = <&cds 2484 memory-region = <&cdsp_mem>;
2817 2485
2818 qcom,qmp = <&aoss_qmp 2486 qcom,qmp = <&aoss_qmp>;
2819 2487
2820 qcom,smem-states = <& 2488 qcom,smem-states = <&smp2p_cdsp_out 0>;
2821 qcom,smem-state-names 2489 qcom,smem-state-names = "stop";
2822 2490
2823 status = "disabled"; 2491 status = "disabled";
2824 2492
2825 glink-edge { 2493 glink-edge {
2826 interrupts-ex 2494 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
2827 2495 IPCC_MPROC_SIGNAL_GLINK_QMP
2828 2496 IRQ_TYPE_EDGE_RISING>;
2829 mboxes = <&ip 2497 mboxes = <&ipcc IPCC_CLIENT_CDSP
2830 2498 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2831 2499
2832 label = "cdsp 2500 label = "cdsp";
2833 qcom,remote-p 2501 qcom,remote-pid = <5>;
2834 2502
2835 fastrpc { 2503 fastrpc {
2836 compa 2504 compatible = "qcom,fastrpc";
2837 qcom, 2505 qcom,glink-channels = "fastrpcglink-apps-dsp";
2838 label 2506 label = "cdsp";
2839 qcom, <<
2840 #addr 2507 #address-cells = <1>;
2841 #size 2508 #size-cells = <0>;
2842 2509
2843 compu 2510 compute-cb@1 {
2844 2511 compatible = "qcom,fastrpc-compute-cb";
2845 2512 reg = <1>;
2846 2513 iommus = <&apps_smmu 0x2161 0x0400>,
2847 2514 <&apps_smmu 0x1021 0x1420>;
2848 }; 2515 };
2849 2516
2850 compu 2517 compute-cb@2 {
2851 2518 compatible = "qcom,fastrpc-compute-cb";
2852 2519 reg = <2>;
2853 2520 iommus = <&apps_smmu 0x2162 0x0400>,
2854 2521 <&apps_smmu 0x1022 0x1420>;
2855 }; 2522 };
2856 2523
2857 compu 2524 compute-cb@3 {
2858 2525 compatible = "qcom,fastrpc-compute-cb";
2859 2526 reg = <3>;
2860 2527 iommus = <&apps_smmu 0x2163 0x0400>,
2861 2528 <&apps_smmu 0x1023 0x1420>;
2862 }; 2529 };
2863 2530
2864 compu 2531 compute-cb@4 {
2865 2532 compatible = "qcom,fastrpc-compute-cb";
2866 2533 reg = <4>;
2867 2534 iommus = <&apps_smmu 0x2164 0x0400>,
2868 2535 <&apps_smmu 0x1024 0x1420>;
2869 }; 2536 };
2870 2537
2871 compu 2538 compute-cb@5 {
2872 2539 compatible = "qcom,fastrpc-compute-cb";
2873 2540 reg = <5>;
2874 2541 iommus = <&apps_smmu 0x2165 0x0400>,
2875 2542 <&apps_smmu 0x1025 0x1420>;
2876 }; 2543 };
2877 2544
2878 compu 2545 compute-cb@6 {
2879 2546 compatible = "qcom,fastrpc-compute-cb";
2880 2547 reg = <6>;
2881 2548 iommus = <&apps_smmu 0x2166 0x0400>,
2882 2549 <&apps_smmu 0x1026 0x1420>;
2883 }; 2550 };
2884 2551
2885 compu 2552 compute-cb@7 {
2886 2553 compatible = "qcom,fastrpc-compute-cb";
2887 2554 reg = <7>;
2888 2555 iommus = <&apps_smmu 0x2167 0x0400>,
2889 2556 <&apps_smmu 0x1027 0x1420>;
2890 }; 2557 };
2891 2558
2892 compu 2559 compute-cb@8 {
2893 2560 compatible = "qcom,fastrpc-compute-cb";
2894 2561 reg = <8>;
2895 2562 iommus = <&apps_smmu 0x2168 0x0400>,
2896 2563 <&apps_smmu 0x1028 0x1420>;
2897 }; 2564 };
2898 2565
2899 /* no 2566 /* note: secure cb9 in downstream */
2900 }; 2567 };
2901 }; 2568 };
2902 }; 2569 };
2903 2570
2904 remoteproc_mpss: remoteproc@4 2571 remoteproc_mpss: remoteproc@4080000 {
2905 compatible = "qcom,sm 2572 compatible = "qcom,sm8450-mpss-pas";
2906 reg = <0x0 0x04080000 2573 reg = <0x0 0x04080000 0x0 0x4040>;
2907 2574
2908 interrupts-extended = 2575 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
2909 2576 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
2910 2577 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
2911 2578 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
2912 2579 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>,
2913 2580 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>;
2914 interrupt-names = "wd 2581 interrupt-names = "wdog", "fatal", "ready", "handover",
2915 "st 2582 "stop-ack", "shutdown-ack";
2916 2583
2917 clocks = <&rpmhcc RPM 2584 clocks = <&rpmhcc RPMH_CXO_CLK>;
2918 clock-names = "xo"; 2585 clock-names = "xo";
2919 2586
2920 power-domains = <&rpm !! 2587 power-domains = <&rpmhpd SM8450_CX>,
2921 <&rpm !! 2588 <&rpmhpd SM8450_MSS>;
2922 power-domain-names = 2589 power-domain-names = "cx", "mss";
2923 2590
2924 memory-region = <&mps 2591 memory-region = <&mpss_mem>;
2925 2592
2926 qcom,qmp = <&aoss_qmp 2593 qcom,qmp = <&aoss_qmp>;
2927 2594
2928 qcom,smem-states = <& 2595 qcom,smem-states = <&smp2p_modem_out 0>;
2929 qcom,smem-state-names 2596 qcom,smem-state-names = "stop";
2930 2597
2931 status = "disabled"; 2598 status = "disabled";
2932 2599
2933 glink-edge { 2600 glink-edge {
2934 interrupts-ex 2601 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
2935 2602 IPCC_MPROC_SIGNAL_GLINK_QMP
2936 2603 IRQ_TYPE_EDGE_RISING>;
2937 mboxes = <&ip 2604 mboxes = <&ipcc IPCC_CLIENT_MPSS
2938 2605 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2939 label = "mode 2606 label = "modem";
2940 qcom,remote-p 2607 qcom,remote-pid = <1>;
2941 }; 2608 };
2942 }; 2609 };
2943 2610
2944 videocc: clock-controller@aaf 2611 videocc: clock-controller@aaf0000 {
2945 compatible = "qcom,sm 2612 compatible = "qcom,sm8450-videocc";
2946 reg = <0 0x0aaf0000 0 2613 reg = <0 0x0aaf0000 0 0x10000>;
2947 clocks = <&rpmhcc RPM 2614 clocks = <&rpmhcc RPMH_CXO_CLK>,
2948 <&gcc GCC_VI 2615 <&gcc GCC_VIDEO_AHB_CLK>;
2949 power-domains = <&rpm !! 2616 power-domains = <&rpmhpd SM8450_MMCX>;
2950 required-opps = <&rpm 2617 required-opps = <&rpmhpd_opp_low_svs>;
2951 #clock-cells = <1>; 2618 #clock-cells = <1>;
2952 #reset-cells = <1>; 2619 #reset-cells = <1>;
2953 #power-domain-cells = 2620 #power-domain-cells = <1>;
2954 }; 2621 };
2955 2622
2956 cci0: cci@ac15000 { 2623 cci0: cci@ac15000 {
2957 compatible = "qcom,sm 2624 compatible = "qcom,sm8450-cci", "qcom,msm8996-cci";
2958 reg = <0 0x0ac15000 0 2625 reg = <0 0x0ac15000 0 0x1000>;
2959 interrupts = <GIC_SPI 2626 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
2960 power-domains = <&cam 2627 power-domains = <&camcc TITAN_TOP_GDSC>;
2961 2628
2962 clocks = <&camcc CAM_ 2629 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
2963 <&camcc CAM_ 2630 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
2964 <&camcc CAM_ 2631 <&camcc CAM_CC_CPAS_AHB_CLK>,
2965 <&camcc CAM_ 2632 <&camcc CAM_CC_CCI_0_CLK>,
2966 <&camcc CAM_ 2633 <&camcc CAM_CC_CCI_0_CLK_SRC>;
2967 clock-names = "camnoc 2634 clock-names = "camnoc_axi",
2968 "slow_a 2635 "slow_ahb_src",
2969 "cpas_a 2636 "cpas_ahb",
2970 "cci", 2637 "cci",
2971 "cci_sr 2638 "cci_src";
2972 pinctrl-0 = <&cci0_de 2639 pinctrl-0 = <&cci0_default &cci1_default>;
2973 pinctrl-1 = <&cci0_sl 2640 pinctrl-1 = <&cci0_sleep &cci1_sleep>;
2974 pinctrl-names = "defa 2641 pinctrl-names = "default", "sleep";
2975 2642
2976 status = "disabled"; 2643 status = "disabled";
2977 #address-cells = <1>; 2644 #address-cells = <1>;
2978 #size-cells = <0>; 2645 #size-cells = <0>;
2979 2646
2980 cci0_i2c0: i2c-bus@0 2647 cci0_i2c0: i2c-bus@0 {
2981 reg = <0>; 2648 reg = <0>;
2982 clock-frequen 2649 clock-frequency = <1000000>;
2983 #address-cell 2650 #address-cells = <1>;
2984 #size-cells = 2651 #size-cells = <0>;
2985 }; 2652 };
2986 2653
2987 cci0_i2c1: i2c-bus@1 2654 cci0_i2c1: i2c-bus@1 {
2988 reg = <1>; 2655 reg = <1>;
2989 clock-frequen 2656 clock-frequency = <1000000>;
2990 #address-cell 2657 #address-cells = <1>;
2991 #size-cells = 2658 #size-cells = <0>;
2992 }; 2659 };
2993 }; 2660 };
2994 2661
2995 cci1: cci@ac16000 { 2662 cci1: cci@ac16000 {
2996 compatible = "qcom,sm 2663 compatible = "qcom,sm8450-cci", "qcom,msm8996-cci";
2997 reg = <0 0x0ac16000 0 2664 reg = <0 0x0ac16000 0 0x1000>;
2998 interrupts = <GIC_SPI 2665 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>;
2999 power-domains = <&cam 2666 power-domains = <&camcc TITAN_TOP_GDSC>;
3000 2667
3001 clocks = <&camcc CAM_ 2668 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
3002 <&camcc CAM_ 2669 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
3003 <&camcc CAM_ 2670 <&camcc CAM_CC_CPAS_AHB_CLK>,
3004 <&camcc CAM_ 2671 <&camcc CAM_CC_CCI_1_CLK>,
3005 <&camcc CAM_ 2672 <&camcc CAM_CC_CCI_1_CLK_SRC>;
3006 clock-names = "camnoc 2673 clock-names = "camnoc_axi",
3007 "slow_a 2674 "slow_ahb_src",
3008 "cpas_a 2675 "cpas_ahb",
3009 "cci", 2676 "cci",
3010 "cci_sr 2677 "cci_src";
3011 pinctrl-0 = <&cci2_de 2678 pinctrl-0 = <&cci2_default &cci3_default>;
3012 pinctrl-1 = <&cci2_sl 2679 pinctrl-1 = <&cci2_sleep &cci3_sleep>;
3013 pinctrl-names = "defa 2680 pinctrl-names = "default", "sleep";
3014 2681
3015 status = "disabled"; 2682 status = "disabled";
3016 #address-cells = <1>; 2683 #address-cells = <1>;
3017 #size-cells = <0>; 2684 #size-cells = <0>;
3018 2685
3019 cci1_i2c0: i2c-bus@0 2686 cci1_i2c0: i2c-bus@0 {
3020 reg = <0>; 2687 reg = <0>;
3021 clock-frequen 2688 clock-frequency = <1000000>;
3022 #address-cell 2689 #address-cells = <1>;
3023 #size-cells = 2690 #size-cells = <0>;
3024 }; 2691 };
3025 2692
3026 cci1_i2c1: i2c-bus@1 2693 cci1_i2c1: i2c-bus@1 {
3027 reg = <1>; 2694 reg = <1>;
3028 clock-frequen 2695 clock-frequency = <1000000>;
3029 #address-cell 2696 #address-cells = <1>;
3030 #size-cells = 2697 #size-cells = <0>;
3031 }; 2698 };
3032 }; 2699 };
3033 2700
3034 camcc: clock-controller@ade00 2701 camcc: clock-controller@ade0000 {
3035 compatible = "qcom,sm 2702 compatible = "qcom,sm8450-camcc";
3036 reg = <0 0x0ade0000 0 2703 reg = <0 0x0ade0000 0 0x20000>;
3037 clocks = <&gcc GCC_CA 2704 clocks = <&gcc GCC_CAMERA_AHB_CLK>,
3038 <&rpmhcc RPM 2705 <&rpmhcc RPMH_CXO_CLK>,
3039 <&rpmhcc RPM 2706 <&rpmhcc RPMH_CXO_CLK_A>,
3040 <&sleep_clk> 2707 <&sleep_clk>;
3041 power-domains = <&rpm !! 2708 power-domains = <&rpmhpd SM8450_MMCX>;
3042 required-opps = <&rpm 2709 required-opps = <&rpmhpd_opp_low_svs>;
3043 #clock-cells = <1>; 2710 #clock-cells = <1>;
3044 #reset-cells = <1>; 2711 #reset-cells = <1>;
3045 #power-domain-cells = 2712 #power-domain-cells = <1>;
3046 status = "disabled"; 2713 status = "disabled";
3047 }; 2714 };
3048 2715
3049 mdss: display-subsystem@ae000 2716 mdss: display-subsystem@ae00000 {
3050 compatible = "qcom,sm 2717 compatible = "qcom,sm8450-mdss";
3051 reg = <0 0x0ae00000 0 2718 reg = <0 0x0ae00000 0 0x1000>;
3052 reg-names = "mdss"; 2719 reg-names = "mdss";
3053 2720
3054 /* same path used twi 2721 /* same path used twice */
3055 interconnects = <&mms 2722 interconnects = <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>,
3056 <&mms !! 2723 <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>;
3057 <&gem !! 2724 interconnect-names = "mdp0-mem", "mdp1-mem";
3058 &con <<
3059 interconnect-names = <<
3060 <<
3061 <<
3062 2725
3063 resets = <&dispcc DIS 2726 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
3064 2727
3065 power-domains = <&dis 2728 power-domains = <&dispcc MDSS_GDSC>;
3066 2729
3067 clocks = <&dispcc DIS 2730 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3068 <&gcc GCC_DI 2731 <&gcc GCC_DISP_HF_AXI_CLK>,
3069 <&gcc GCC_DI 2732 <&gcc GCC_DISP_SF_AXI_CLK>,
3070 <&dispcc DIS 2733 <&dispcc DISP_CC_MDSS_MDP_CLK>;
3071 2734
3072 interrupts = <GIC_SPI 2735 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
3073 interrupt-controller; 2736 interrupt-controller;
3074 #interrupt-cells = <1 2737 #interrupt-cells = <1>;
3075 2738
3076 iommus = <&apps_smmu 2739 iommus = <&apps_smmu 0x2800 0x402>;
3077 2740
3078 #address-cells = <2>; 2741 #address-cells = <2>;
3079 #size-cells = <2>; 2742 #size-cells = <2>;
3080 ranges; 2743 ranges;
3081 2744
3082 status = "disabled"; 2745 status = "disabled";
3083 2746
3084 mdss_mdp: display-con 2747 mdss_mdp: display-controller@ae01000 {
3085 compatible = 2748 compatible = "qcom,sm8450-dpu";
3086 reg = <0 0x0a 2749 reg = <0 0x0ae01000 0 0x8f000>,
3087 <0 0x0a 2750 <0 0x0aeb0000 0 0x2008>;
3088 reg-names = " 2751 reg-names = "mdp", "vbif";
3089 2752
3090 clocks = <&gc 2753 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
3091 <&gcc 2754 <&gcc GCC_DISP_SF_AXI_CLK>,
3092 <&dis 2755 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3093 <&dis 2756 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
3094 <&dis 2757 <&dispcc DISP_CC_MDSS_MDP_CLK>,
3095 <&dis 2758 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3096 clock-names = 2759 clock-names = "bus",
3097 2760 "nrt_bus",
3098 2761 "iface",
3099 2762 "lut",
3100 2763 "core",
3101 2764 "vsync";
3102 2765
3103 assigned-cloc 2766 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3104 assigned-cloc 2767 assigned-clock-rates = <19200000>;
3105 2768
3106 operating-poi 2769 operating-points-v2 = <&mdp_opp_table>;
3107 power-domains !! 2770 power-domains = <&rpmhpd SM8450_MMCX>;
3108 2771
3109 interrupt-par 2772 interrupt-parent = <&mdss>;
3110 interrupts = 2773 interrupts = <0>;
3111 2774
3112 ports { 2775 ports {
3113 #addr 2776 #address-cells = <1>;
3114 #size 2777 #size-cells = <0>;
3115 2778
3116 port@ 2779 port@0 {
3117 2780 reg = <0>;
3118 2781 dpu_intf1_out: endpoint {
3119 2782 remote-endpoint = <&mdss_dsi0_in>;
3120 2783 };
3121 }; 2784 };
3122 2785
3123 port@ 2786 port@1 {
3124 2787 reg = <1>;
3125 2788 dpu_intf2_out: endpoint {
3126 2789 remote-endpoint = <&mdss_dsi1_in>;
3127 2790 };
3128 }; 2791 };
3129 2792
3130 port@ 2793 port@2 {
3131 2794 reg = <2>;
3132 2795 dpu_intf0_out: endpoint {
3133 2796 remote-endpoint = <&mdss_dp0_in>;
3134 2797 };
3135 }; 2798 };
3136 }; 2799 };
3137 2800
3138 mdp_opp_table 2801 mdp_opp_table: opp-table {
3139 compa 2802 compatible = "operating-points-v2";
3140 2803
3141 opp-1 2804 opp-172000000 {
3142 2805 opp-hz = /bits/ 64 <172000000>;
3143 2806 required-opps = <&rpmhpd_opp_low_svs_d1>;
3144 }; 2807 };
3145 2808
3146 opp-2 2809 opp-200000000 {
3147 2810 opp-hz = /bits/ 64 <200000000>;
3148 2811 required-opps = <&rpmhpd_opp_low_svs>;
3149 }; 2812 };
3150 2813
3151 opp-3 2814 opp-325000000 {
3152 2815 opp-hz = /bits/ 64 <325000000>;
3153 2816 required-opps = <&rpmhpd_opp_svs>;
3154 }; 2817 };
3155 2818
3156 opp-3 2819 opp-375000000 {
3157 2820 opp-hz = /bits/ 64 <375000000>;
3158 2821 required-opps = <&rpmhpd_opp_svs_l1>;
3159 }; 2822 };
3160 2823
3161 opp-5 2824 opp-500000000 {
3162 2825 opp-hz = /bits/ 64 <500000000>;
3163 2826 required-opps = <&rpmhpd_opp_nom>;
3164 }; 2827 };
3165 }; 2828 };
3166 }; 2829 };
3167 2830
3168 mdss_dp0: displayport 2831 mdss_dp0: displayport-controller@ae90000 {
3169 compatible = 2832 compatible = "qcom,sm8450-dp", "qcom,sm8350-dp";
3170 reg = <0 0xae 2833 reg = <0 0xae90000 0 0x200>,
3171 <0 0xae 2834 <0 0xae90200 0 0x200>,
3172 <0 0xae 2835 <0 0xae90400 0 0xc00>,
3173 <0 0xae 2836 <0 0xae91000 0 0x400>,
3174 <0 0xae 2837 <0 0xae91400 0 0x400>;
3175 interrupt-par 2838 interrupt-parent = <&mdss>;
3176 interrupts = 2839 interrupts = <12>;
3177 clocks = <&di 2840 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3178 <&di 2841 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
3179 <&di 2842 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
3180 <&di 2843 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
3181 <&di 2844 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
3182 clock-names = 2845 clock-names = "core_iface",
3183 2846 "core_aux",
3184 2847 "ctrl_link",
3185 2848 "ctrl_link_iface",
3186 2849 "stream_pixel";
3187 2850
3188 assigned-cloc 2851 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
3189 2852 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
3190 assigned-cloc 2853 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3191 2854 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
3192 2855
3193 phys = <&usb_ 2856 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
3194 phy-names = " 2857 phy-names = "dp";
3195 2858
3196 #sound-dai-ce 2859 #sound-dai-cells = <0>;
3197 2860
3198 operating-poi 2861 operating-points-v2 = <&dp_opp_table>;
3199 power-domains !! 2862 power-domains = <&rpmhpd SM8450_MMCX>;
3200 2863
3201 status = "dis 2864 status = "disabled";
3202 2865
3203 ports { 2866 ports {
3204 #addr 2867 #address-cells = <1>;
3205 #size 2868 #size-cells = <0>;
3206 2869
3207 port@ 2870 port@0 {
3208 2871 reg = <0>;
3209 2872 mdss_dp0_in: endpoint {
3210 2873 remote-endpoint = <&dpu_intf0_out>;
3211 2874 };
3212 }; 2875 };
3213 <<
3214 port@ <<
3215 <<
3216 <<
3217 <<
3218 <<
3219 <<
3220 }; <<
3221 }; 2876 };
3222 2877
3223 dp_opp_table: 2878 dp_opp_table: opp-table {
3224 compa 2879 compatible = "operating-points-v2";
3225 2880
3226 opp-1 2881 opp-160000000 {
3227 2882 opp-hz = /bits/ 64 <160000000>;
3228 2883 required-opps = <&rpmhpd_opp_low_svs>;
3229 }; 2884 };
3230 2885
3231 opp-2 2886 opp-270000000 {
3232 2887 opp-hz = /bits/ 64 <270000000>;
3233 2888 required-opps = <&rpmhpd_opp_svs>;
3234 }; 2889 };
3235 2890
3236 opp-5 2891 opp-540000000 {
3237 2892 opp-hz = /bits/ 64 <540000000>;
3238 2893 required-opps = <&rpmhpd_opp_svs_l1>;
3239 }; 2894 };
3240 2895
3241 opp-8 2896 opp-810000000 {
3242 2897 opp-hz = /bits/ 64 <810000000>;
3243 2898 required-opps = <&rpmhpd_opp_nom>;
3244 }; 2899 };
3245 }; 2900 };
3246 }; 2901 };
3247 2902
3248 mdss_dsi0: dsi@ae9400 2903 mdss_dsi0: dsi@ae94000 {
3249 compatible = 2904 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3250 reg = <0 0x0a 2905 reg = <0 0x0ae94000 0 0x400>;
3251 reg-names = " 2906 reg-names = "dsi_ctrl";
3252 2907
3253 interrupt-par 2908 interrupt-parent = <&mdss>;
3254 interrupts = 2909 interrupts = <4>;
3255 2910
3256 clocks = <&di 2911 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
3257 <&di 2912 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
3258 <&di 2913 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
3259 <&di 2914 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
3260 <&di 2915 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3261 <&gcc 2916 <&gcc GCC_DISP_HF_AXI_CLK>;
3262 clock-names = 2917 clock-names = "byte",
3263 2918 "byte_intf",
3264 2919 "pixel",
3265 2920 "core",
3266 2921 "iface",
3267 2922 "bus";
3268 2923
3269 assigned-cloc 2924 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
3270 assigned-cloc 2925 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
3271 2926
3272 operating-poi 2927 operating-points-v2 = <&mdss_dsi_opp_table>;
3273 power-domains !! 2928 power-domains = <&rpmhpd SM8450_MMCX>;
3274 2929
3275 phys = <&mdss 2930 phys = <&mdss_dsi0_phy>;
3276 phy-names = " 2931 phy-names = "dsi";
3277 2932
3278 #address-cell 2933 #address-cells = <1>;
3279 #size-cells = 2934 #size-cells = <0>;
3280 2935
3281 status = "dis 2936 status = "disabled";
3282 2937
3283 ports { 2938 ports {
3284 #addr 2939 #address-cells = <1>;
3285 #size 2940 #size-cells = <0>;
3286 2941
3287 port@ 2942 port@0 {
3288 2943 reg = <0>;
3289 2944 mdss_dsi0_in: endpoint {
3290 2945 remote-endpoint = <&dpu_intf1_out>;
3291 2946 };
3292 }; 2947 };
3293 2948
3294 port@ 2949 port@1 {
3295 2950 reg = <1>;
3296 2951 mdss_dsi0_out: endpoint {
3297 2952 };
3298 }; 2953 };
3299 }; 2954 };
3300 2955
3301 mdss_dsi_opp_ 2956 mdss_dsi_opp_table: opp-table {
3302 compa 2957 compatible = "operating-points-v2";
3303 2958
3304 opp-1 2959 opp-187500000 {
3305 2960 opp-hz = /bits/ 64 <187500000>;
3306 2961 required-opps = <&rpmhpd_opp_low_svs>;
3307 }; 2962 };
3308 2963
3309 opp-3 2964 opp-300000000 {
3310 2965 opp-hz = /bits/ 64 <300000000>;
3311 2966 required-opps = <&rpmhpd_opp_svs>;
3312 }; 2967 };
3313 2968
3314 opp-3 2969 opp-358000000 {
3315 2970 opp-hz = /bits/ 64 <358000000>;
3316 2971 required-opps = <&rpmhpd_opp_svs_l1>;
3317 }; 2972 };
3318 }; 2973 };
3319 }; 2974 };
3320 2975
3321 mdss_dsi0_phy: phy@ae 2976 mdss_dsi0_phy: phy@ae94400 {
3322 compatible = 2977 compatible = "qcom,sm8450-dsi-phy-5nm";
3323 reg = <0 0x0a 2978 reg = <0 0x0ae94400 0 0x200>,
3324 <0 0x0a 2979 <0 0x0ae94600 0 0x280>,
3325 <0 0x0a 2980 <0 0x0ae94900 0 0x260>;
3326 reg-names = " 2981 reg-names = "dsi_phy",
3327 " 2982 "dsi_phy_lane",
3328 " 2983 "dsi_pll";
3329 2984
3330 #clock-cells 2985 #clock-cells = <1>;
3331 #phy-cells = 2986 #phy-cells = <0>;
3332 2987
3333 clocks = <&di 2988 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3334 <&rp 2989 <&rpmhcc RPMH_CXO_CLK>;
3335 clock-names = 2990 clock-names = "iface", "ref";
3336 2991
3337 status = "dis 2992 status = "disabled";
3338 }; 2993 };
3339 2994
3340 mdss_dsi1: dsi@ae9600 2995 mdss_dsi1: dsi@ae96000 {
3341 compatible = 2996 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3342 reg = <0 0x0a 2997 reg = <0 0x0ae96000 0 0x400>;
3343 reg-names = " 2998 reg-names = "dsi_ctrl";
3344 2999
3345 interrupt-par 3000 interrupt-parent = <&mdss>;
3346 interrupts = 3001 interrupts = <5>;
3347 3002
3348 clocks = <&di 3003 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
3349 <&di 3004 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
3350 <&di 3005 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
3351 <&di 3006 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
3352 <&di 3007 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3353 <&gc 3008 <&gcc GCC_DISP_HF_AXI_CLK>;
3354 clock-names = 3009 clock-names = "byte",
3355 3010 "byte_intf",
3356 3011 "pixel",
3357 3012 "core",
3358 3013 "iface",
3359 3014 "bus";
3360 3015
3361 assigned-cloc 3016 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
3362 assigned-cloc 3017 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
3363 3018
3364 operating-poi 3019 operating-points-v2 = <&mdss_dsi_opp_table>;
3365 power-domains !! 3020 power-domains = <&rpmhpd SM8450_MMCX>;
3366 3021
3367 phys = <&mdss 3022 phys = <&mdss_dsi1_phy>;
3368 phy-names = " 3023 phy-names = "dsi";
3369 3024
3370 #address-cell 3025 #address-cells = <1>;
3371 #size-cells = 3026 #size-cells = <0>;
3372 3027
3373 status = "dis 3028 status = "disabled";
3374 3029
3375 ports { 3030 ports {
3376 #addr 3031 #address-cells = <1>;
3377 #size 3032 #size-cells = <0>;
3378 3033
3379 port@ 3034 port@0 {
3380 3035 reg = <0>;
3381 3036 mdss_dsi1_in: endpoint {
3382 3037 remote-endpoint = <&dpu_intf2_out>;
3383 3038 };
3384 }; 3039 };
3385 3040
3386 port@ 3041 port@1 {
3387 3042 reg = <1>;
3388 3043 mdss_dsi1_out: endpoint {
3389 3044 };
3390 }; 3045 };
3391 }; 3046 };
3392 }; 3047 };
3393 3048
3394 mdss_dsi1_phy: phy@ae 3049 mdss_dsi1_phy: phy@ae96400 {
3395 compatible = 3050 compatible = "qcom,sm8450-dsi-phy-5nm";
3396 reg = <0 0x0a 3051 reg = <0 0x0ae96400 0 0x200>,
3397 <0 0x0a 3052 <0 0x0ae96600 0 0x280>,
3398 <0 0x0a 3053 <0 0x0ae96900 0 0x260>;
3399 reg-names = " 3054 reg-names = "dsi_phy",
3400 " 3055 "dsi_phy_lane",
3401 " 3056 "dsi_pll";
3402 3057
3403 #clock-cells 3058 #clock-cells = <1>;
3404 #phy-cells = 3059 #phy-cells = <0>;
3405 3060
3406 clocks = <&di 3061 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3407 <&rp 3062 <&rpmhcc RPMH_CXO_CLK>;
3408 clock-names = 3063 clock-names = "iface", "ref";
3409 3064
3410 status = "dis 3065 status = "disabled";
3411 }; 3066 };
3412 }; 3067 };
3413 3068
3414 dispcc: clock-controller@af00 3069 dispcc: clock-controller@af00000 {
3415 compatible = "qcom,sm 3070 compatible = "qcom,sm8450-dispcc";
3416 reg = <0 0x0af00000 0 3071 reg = <0 0x0af00000 0 0x20000>;
3417 clocks = <&rpmhcc RPM 3072 clocks = <&rpmhcc RPMH_CXO_CLK>,
3418 <&rpmhcc RPM 3073 <&rpmhcc RPMH_CXO_CLK_A>,
3419 <&gcc GCC_DI 3074 <&gcc GCC_DISP_AHB_CLK>,
3420 <&sleep_clk> 3075 <&sleep_clk>,
3421 <&mdss_dsi0_ 3076 <&mdss_dsi0_phy 0>,
3422 <&mdss_dsi0_ 3077 <&mdss_dsi0_phy 1>,
3423 <&mdss_dsi1_ 3078 <&mdss_dsi1_phy 0>,
3424 <&mdss_dsi1_ 3079 <&mdss_dsi1_phy 1>,
3425 <&usb_1_qmpp 3080 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3426 <&usb_1_qmpp 3081 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
3427 <0>, /* dp1 3082 <0>, /* dp1 */
3428 <0>, 3083 <0>,
3429 <0>, /* dp2 3084 <0>, /* dp2 */
3430 <0>, 3085 <0>,
3431 <0>, /* dp3 3086 <0>, /* dp3 */
3432 <0>; 3087 <0>;
3433 power-domains = <&rpm !! 3088 power-domains = <&rpmhpd SM8450_MMCX>;
3434 required-opps = <&rpm 3089 required-opps = <&rpmhpd_opp_low_svs>;
3435 #clock-cells = <1>; 3090 #clock-cells = <1>;
3436 #reset-cells = <1>; 3091 #reset-cells = <1>;
3437 #power-domain-cells = 3092 #power-domain-cells = <1>;
3438 status = "disabled"; 3093 status = "disabled";
3439 }; 3094 };
3440 3095
3441 pdc: interrupt-controller@b22 3096 pdc: interrupt-controller@b220000 {
3442 compatible = "qcom,sm 3097 compatible = "qcom,sm8450-pdc", "qcom,pdc";
3443 reg = <0 0x0b220000 0 3098 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
3444 qcom,pdc-ranges = <0 3099 qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>,
3445 <94 3100 <94 609 31>, <125 63 1>, <126 716 12>;
3446 #interrupt-cells = <2 3101 #interrupt-cells = <2>;
3447 interrupt-parent = <& 3102 interrupt-parent = <&intc>;
3448 interrupt-controller; 3103 interrupt-controller;
3449 }; 3104 };
3450 3105
3451 tsens0: thermal-sensor@c26300 3106 tsens0: thermal-sensor@c263000 {
3452 compatible = "qcom,sm 3107 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2";
3453 reg = <0 0x0c263000 0 3108 reg = <0 0x0c263000 0 0x1000>, /* TM */
3454 <0 0x0c222000 0 3109 <0 0x0c222000 0 0x1000>; /* SROT */
3455 #qcom,sensors = <16>; 3110 #qcom,sensors = <16>;
3456 interrupts = <GIC_SPI 3111 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
3457 <GIC_SPI 3112 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
3458 interrupt-names = "up 3113 interrupt-names = "uplow", "critical";
3459 #thermal-sensor-cells 3114 #thermal-sensor-cells = <1>;
3460 }; 3115 };
3461 3116
3462 tsens1: thermal-sensor@c26500 3117 tsens1: thermal-sensor@c265000 {
3463 compatible = "qcom,sm 3118 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2";
3464 reg = <0 0x0c265000 0 3119 reg = <0 0x0c265000 0 0x1000>, /* TM */
3465 <0 0x0c223000 0 3120 <0 0x0c223000 0 0x1000>; /* SROT */
3466 #qcom,sensors = <16>; 3121 #qcom,sensors = <16>;
3467 interrupts = <GIC_SPI 3122 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
3468 <GIC_SPI 3123 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
3469 interrupt-names = "up 3124 interrupt-names = "uplow", "critical";
3470 #thermal-sensor-cells 3125 #thermal-sensor-cells = <1>;
3471 }; 3126 };
3472 3127
3473 aoss_qmp: power-management@c3 3128 aoss_qmp: power-management@c300000 {
3474 compatible = "qcom,sm 3129 compatible = "qcom,sm8450-aoss-qmp", "qcom,aoss-qmp";
3475 reg = <0 0x0c300000 0 3130 reg = <0 0x0c300000 0 0x400>;
3476 interrupts-extended = 3131 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
3477 3132 IRQ_TYPE_EDGE_RISING>;
3478 mboxes = <&ipcc IPCC_ 3133 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
3479 3134
3480 #clock-cells = <0>; 3135 #clock-cells = <0>;
3481 }; 3136 };
3482 3137
3483 sram@c3f0000 { <<
3484 compatible = "qcom,rp <<
3485 reg = <0 0x0c3f0000 0 <<
3486 }; <<
3487 <<
3488 spmi_bus: spmi@c400000 { 3138 spmi_bus: spmi@c400000 {
3489 compatible = "qcom,sp 3139 compatible = "qcom,spmi-pmic-arb";
3490 reg = <0 0x0c400000 0 3140 reg = <0 0x0c400000 0 0x00003000>,
3491 <0 0x0c500000 0 3141 <0 0x0c500000 0 0x00400000>,
3492 <0 0x0c440000 0 3142 <0 0x0c440000 0 0x00080000>,
3493 <0 0x0c4c0000 0 3143 <0 0x0c4c0000 0 0x00010000>,
3494 <0 0x0c42d000 0 3144 <0 0x0c42d000 0 0x00010000>;
3495 reg-names = "core", 3145 reg-names = "core",
3496 "chnls", 3146 "chnls",
3497 "obsrvr", 3147 "obsrvr",
3498 "intr", 3148 "intr",
3499 "cnfg"; 3149 "cnfg";
3500 interrupt-names = "pe 3150 interrupt-names = "periph_irq";
3501 interrupts-extended = 3151 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3502 qcom,ee = <0>; 3152 qcom,ee = <0>;
3503 qcom,channel = <0>; 3153 qcom,channel = <0>;
3504 interrupt-controller; 3154 interrupt-controller;
3505 #interrupt-cells = <4 3155 #interrupt-cells = <4>;
3506 #address-cells = <2>; 3156 #address-cells = <2>;
3507 #size-cells = <0>; 3157 #size-cells = <0>;
3508 }; 3158 };
3509 3159
3510 ipcc: mailbox@ed18000 { 3160 ipcc: mailbox@ed18000 {
3511 compatible = "qcom,sm 3161 compatible = "qcom,sm8450-ipcc", "qcom,ipcc";
3512 reg = <0 0x0ed18000 0 3162 reg = <0 0x0ed18000 0 0x1000>;
3513 interrupts = <GIC_SPI 3163 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
3514 interrupt-controller; 3164 interrupt-controller;
3515 #interrupt-cells = <3 3165 #interrupt-cells = <3>;
3516 #mbox-cells = <2>; 3166 #mbox-cells = <2>;
3517 }; 3167 };
3518 3168
3519 tlmm: pinctrl@f100000 { 3169 tlmm: pinctrl@f100000 {
3520 compatible = "qcom,sm 3170 compatible = "qcom,sm8450-tlmm";
3521 reg = <0 0x0f100000 0 3171 reg = <0 0x0f100000 0 0x300000>;
3522 interrupts = <GIC_SPI 3172 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
3523 gpio-controller; 3173 gpio-controller;
3524 #gpio-cells = <2>; 3174 #gpio-cells = <2>;
3525 interrupt-controller; 3175 interrupt-controller;
3526 #interrupt-cells = <2 3176 #interrupt-cells = <2>;
3527 gpio-ranges = <&tlmm 3177 gpio-ranges = <&tlmm 0 0 211>;
3528 wakeup-parent = <&pdc 3178 wakeup-parent = <&pdc>;
3529 3179
3530 sdc2_default_state: s 3180 sdc2_default_state: sdc2-default-state {
3531 clk-pins { 3181 clk-pins {
3532 pins 3182 pins = "sdc2_clk";
3533 drive 3183 drive-strength = <16>;
3534 bias- 3184 bias-disable;
3535 }; 3185 };
3536 3186
3537 cmd-pins { 3187 cmd-pins {
3538 pins 3188 pins = "sdc2_cmd";
3539 drive 3189 drive-strength = <16>;
3540 bias- 3190 bias-pull-up;
3541 }; 3191 };
3542 3192
3543 data-pins { 3193 data-pins {
3544 pins 3194 pins = "sdc2_data";
3545 drive 3195 drive-strength = <16>;
3546 bias- 3196 bias-pull-up;
3547 }; 3197 };
3548 }; 3198 };
3549 3199
3550 sdc2_sleep_state: sdc 3200 sdc2_sleep_state: sdc2-sleep-state {
3551 clk-pins { 3201 clk-pins {
3552 pins 3202 pins = "sdc2_clk";
3553 drive 3203 drive-strength = <2>;
3554 bias- 3204 bias-disable;
3555 }; 3205 };
3556 3206
3557 cmd-pins { 3207 cmd-pins {
3558 pins 3208 pins = "sdc2_cmd";
3559 drive 3209 drive-strength = <2>;
3560 bias- 3210 bias-pull-up;
3561 }; 3211 };
3562 3212
3563 data-pins { 3213 data-pins {
3564 pins 3214 pins = "sdc2_data";
3565 drive 3215 drive-strength = <2>;
3566 bias- 3216 bias-pull-up;
3567 }; 3217 };
3568 }; 3218 };
3569 3219
3570 cci0_default: cci0-de 3220 cci0_default: cci0-default-state {
3571 /* SDA, SCL * 3221 /* SDA, SCL */
3572 pins = "gpio1 3222 pins = "gpio110", "gpio111";
3573 function = "c 3223 function = "cci_i2c";
3574 drive-strengt 3224 drive-strength = <2>;
3575 bias-pull-up; 3225 bias-pull-up;
3576 }; 3226 };
3577 3227
3578 cci0_sleep: cci0-slee 3228 cci0_sleep: cci0-sleep-state {
3579 /* SDA, SCL * 3229 /* SDA, SCL */
3580 pins = "gpio1 3230 pins = "gpio110", "gpio111";
3581 function = "c 3231 function = "cci_i2c";
3582 drive-strengt 3232 drive-strength = <2>;
3583 bias-pull-dow 3233 bias-pull-down;
3584 }; 3234 };
3585 3235
3586 cci1_default: cci1-de 3236 cci1_default: cci1-default-state {
3587 /* SDA, SCL * 3237 /* SDA, SCL */
3588 pins = "gpio1 3238 pins = "gpio112", "gpio113";
3589 function = "c 3239 function = "cci_i2c";
3590 drive-strengt 3240 drive-strength = <2>;
3591 bias-pull-up; 3241 bias-pull-up;
3592 }; 3242 };
3593 3243
3594 cci1_sleep: cci1-slee 3244 cci1_sleep: cci1-sleep-state {
3595 /* SDA, SCL * 3245 /* SDA, SCL */
3596 pins = "gpio1 3246 pins = "gpio112", "gpio113";
3597 function = "c 3247 function = "cci_i2c";
3598 drive-strengt 3248 drive-strength = <2>;
3599 bias-pull-dow 3249 bias-pull-down;
3600 }; 3250 };
3601 3251
3602 cci2_default: cci2-de 3252 cci2_default: cci2-default-state {
3603 /* SDA, SCL * 3253 /* SDA, SCL */
3604 pins = "gpio1 3254 pins = "gpio114", "gpio115";
3605 function = "c 3255 function = "cci_i2c";
3606 drive-strengt 3256 drive-strength = <2>;
3607 bias-pull-up; 3257 bias-pull-up;
3608 }; 3258 };
3609 3259
3610 cci2_sleep: cci2-slee 3260 cci2_sleep: cci2-sleep-state {
3611 /* SDA, SCL * 3261 /* SDA, SCL */
3612 pins = "gpio1 3262 pins = "gpio114", "gpio115";
3613 function = "c 3263 function = "cci_i2c";
3614 drive-strengt 3264 drive-strength = <2>;
3615 bias-pull-dow 3265 bias-pull-down;
3616 }; 3266 };
3617 3267
3618 cci3_default: cci3-de 3268 cci3_default: cci3-default-state {
3619 /* SDA, SCL * 3269 /* SDA, SCL */
3620 pins = "gpio2 3270 pins = "gpio208", "gpio209";
3621 function = "c 3271 function = "cci_i2c";
3622 drive-strengt 3272 drive-strength = <2>;
3623 bias-pull-up; 3273 bias-pull-up;
3624 }; 3274 };
3625 3275
3626 cci3_sleep: cci3-slee 3276 cci3_sleep: cci3-sleep-state {
3627 /* SDA, SCL * 3277 /* SDA, SCL */
3628 pins = "gpio2 3278 pins = "gpio208", "gpio209";
3629 function = "c 3279 function = "cci_i2c";
3630 drive-strengt 3280 drive-strength = <2>;
3631 bias-pull-dow 3281 bias-pull-down;
3632 }; 3282 };
3633 3283
3634 pcie0_default_state: 3284 pcie0_default_state: pcie0-default-state {
3635 perst-pins { 3285 perst-pins {
3636 pins 3286 pins = "gpio94";
3637 funct 3287 function = "gpio";
3638 drive 3288 drive-strength = <2>;
3639 bias- 3289 bias-pull-down;
3640 }; 3290 };
3641 3291
3642 clkreq-pins { 3292 clkreq-pins {
3643 pins 3293 pins = "gpio95";
3644 funct 3294 function = "pcie0_clkreqn";
3645 drive 3295 drive-strength = <2>;
3646 bias- 3296 bias-pull-up;
3647 }; 3297 };
3648 3298
3649 wake-pins { 3299 wake-pins {
3650 pins 3300 pins = "gpio96";
3651 funct 3301 function = "gpio";
3652 drive 3302 drive-strength = <2>;
3653 bias- 3303 bias-pull-up;
3654 }; 3304 };
3655 }; 3305 };
3656 3306
3657 pcie1_default_state: 3307 pcie1_default_state: pcie1-default-state {
3658 perst-pins { 3308 perst-pins {
3659 pins 3309 pins = "gpio97";
3660 funct 3310 function = "gpio";
3661 drive 3311 drive-strength = <2>;
3662 bias- 3312 bias-pull-down;
3663 }; 3313 };
3664 3314
3665 clkreq-pins { 3315 clkreq-pins {
3666 pins 3316 pins = "gpio98";
3667 funct 3317 function = "pcie1_clkreqn";
3668 drive 3318 drive-strength = <2>;
3669 bias- 3319 bias-pull-up;
3670 }; 3320 };
3671 3321
3672 wake-pins { 3322 wake-pins {
3673 pins 3323 pins = "gpio99";
3674 funct 3324 function = "gpio";
3675 drive 3325 drive-strength = <2>;
3676 bias- 3326 bias-pull-up;
3677 }; 3327 };
3678 }; 3328 };
3679 3329
3680 qup_i2c0_data_clk: qu 3330 qup_i2c0_data_clk: qup-i2c0-data-clk-state {
3681 pins = "gpio0 3331 pins = "gpio0", "gpio1";
3682 function = "q 3332 function = "qup0";
3683 }; 3333 };
3684 3334
3685 qup_i2c1_data_clk: qu 3335 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
3686 pins = "gpio4 3336 pins = "gpio4", "gpio5";
3687 function = "q 3337 function = "qup1";
3688 }; 3338 };
3689 3339
3690 qup_i2c2_data_clk: qu 3340 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
3691 pins = "gpio8 3341 pins = "gpio8", "gpio9";
3692 function = "q 3342 function = "qup2";
3693 }; 3343 };
3694 3344
3695 qup_i2c3_data_clk: qu 3345 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
3696 pins = "gpio1 3346 pins = "gpio12", "gpio13";
3697 function = "q 3347 function = "qup3";
3698 }; 3348 };
3699 3349
3700 qup_i2c4_data_clk: qu 3350 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
3701 pins = "gpio1 3351 pins = "gpio16", "gpio17";
3702 function = "q 3352 function = "qup4";
3703 }; 3353 };
3704 3354
3705 qup_i2c5_data_clk: qu 3355 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
3706 pins = "gpio2 3356 pins = "gpio206", "gpio207";
3707 function = "q 3357 function = "qup5";
3708 }; 3358 };
3709 3359
3710 qup_i2c6_data_clk: qu 3360 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
3711 pins = "gpio2 3361 pins = "gpio20", "gpio21";
3712 function = "q 3362 function = "qup6";
3713 }; 3363 };
3714 3364
3715 qup_i2c8_data_clk: qu 3365 qup_i2c8_data_clk: qup-i2c8-data-clk-state {
3716 pins = "gpio2 3366 pins = "gpio28", "gpio29";
3717 function = "q 3367 function = "qup8";
3718 }; 3368 };
3719 3369
3720 qup_i2c9_data_clk: qu 3370 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
3721 pins = "gpio3 3371 pins = "gpio32", "gpio33";
3722 function = "q 3372 function = "qup9";
3723 }; 3373 };
3724 3374
3725 qup_i2c10_data_clk: q 3375 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
3726 pins = "gpio3 3376 pins = "gpio36", "gpio37";
3727 function = "q 3377 function = "qup10";
3728 }; 3378 };
3729 3379
3730 qup_i2c11_data_clk: q 3380 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
3731 pins = "gpio4 3381 pins = "gpio40", "gpio41";
3732 function = "q 3382 function = "qup11";
3733 }; 3383 };
3734 3384
3735 qup_i2c12_data_clk: q 3385 qup_i2c12_data_clk: qup-i2c12-data-clk-state {
3736 pins = "gpio4 3386 pins = "gpio44", "gpio45";
3737 function = "q 3387 function = "qup12";
3738 }; 3388 };
3739 3389
3740 qup_i2c13_data_clk: q 3390 qup_i2c13_data_clk: qup-i2c13-data-clk-state {
3741 pins = "gpio4 3391 pins = "gpio48", "gpio49";
3742 function = "q 3392 function = "qup13";
3743 drive-strengt 3393 drive-strength = <2>;
3744 bias-pull-up; 3394 bias-pull-up;
3745 }; 3395 };
3746 3396
3747 qup_i2c14_data_clk: q 3397 qup_i2c14_data_clk: qup-i2c14-data-clk-state {
3748 pins = "gpio5 3398 pins = "gpio52", "gpio53";
3749 function = "q 3399 function = "qup14";
3750 drive-strengt 3400 drive-strength = <2>;
3751 bias-pull-up; 3401 bias-pull-up;
3752 }; 3402 };
3753 3403
3754 qup_i2c15_data_clk: q 3404 qup_i2c15_data_clk: qup-i2c15-data-clk-state {
3755 pins = "gpio5 3405 pins = "gpio56", "gpio57";
3756 function = "q 3406 function = "qup15";
3757 }; 3407 };
3758 3408
3759 qup_i2c16_data_clk: q 3409 qup_i2c16_data_clk: qup-i2c16-data-clk-state {
3760 pins = "gpio6 3410 pins = "gpio60", "gpio61";
3761 function = "q 3411 function = "qup16";
3762 }; 3412 };
3763 3413
3764 qup_i2c17_data_clk: q 3414 qup_i2c17_data_clk: qup-i2c17-data-clk-state {
3765 pins = "gpio6 3415 pins = "gpio64", "gpio65";
3766 function = "q 3416 function = "qup17";
3767 }; 3417 };
3768 3418
3769 qup_i2c18_data_clk: q 3419 qup_i2c18_data_clk: qup-i2c18-data-clk-state {
3770 pins = "gpio6 3420 pins = "gpio68", "gpio69";
3771 function = "q 3421 function = "qup18";
3772 }; 3422 };
3773 3423
3774 qup_i2c19_data_clk: q 3424 qup_i2c19_data_clk: qup-i2c19-data-clk-state {
3775 pins = "gpio7 3425 pins = "gpio72", "gpio73";
3776 function = "q 3426 function = "qup19";
3777 }; 3427 };
3778 3428
3779 qup_i2c20_data_clk: q 3429 qup_i2c20_data_clk: qup-i2c20-data-clk-state {
3780 pins = "gpio7 3430 pins = "gpio76", "gpio77";
3781 function = "q 3431 function = "qup20";
3782 }; 3432 };
3783 3433
3784 qup_i2c21_data_clk: q 3434 qup_i2c21_data_clk: qup-i2c21-data-clk-state {
3785 pins = "gpio8 3435 pins = "gpio80", "gpio81";
3786 function = "q 3436 function = "qup21";
3787 }; 3437 };
3788 3438
3789 qup_spi0_cs: qup-spi0 3439 qup_spi0_cs: qup-spi0-cs-state {
3790 pins = "gpio3 3440 pins = "gpio3";
3791 function = "q 3441 function = "qup0";
3792 }; 3442 };
3793 3443
3794 qup_spi0_data_clk: qu 3444 qup_spi0_data_clk: qup-spi0-data-clk-state {
3795 pins = "gpio0 3445 pins = "gpio0", "gpio1", "gpio2";
3796 function = "q 3446 function = "qup0";
3797 }; 3447 };
3798 3448
3799 qup_spi1_cs: qup-spi1 3449 qup_spi1_cs: qup-spi1-cs-state {
3800 pins = "gpio7 3450 pins = "gpio7";
3801 function = "q 3451 function = "qup1";
3802 }; 3452 };
3803 3453
3804 qup_spi1_data_clk: qu 3454 qup_spi1_data_clk: qup-spi1-data-clk-state {
3805 pins = "gpio4 3455 pins = "gpio4", "gpio5", "gpio6";
3806 function = "q 3456 function = "qup1";
3807 }; 3457 };
3808 3458
3809 qup_spi2_cs: qup-spi2 3459 qup_spi2_cs: qup-spi2-cs-state {
3810 pins = "gpio1 3460 pins = "gpio11";
3811 function = "q 3461 function = "qup2";
3812 }; 3462 };
3813 3463
3814 qup_spi2_data_clk: qu 3464 qup_spi2_data_clk: qup-spi2-data-clk-state {
3815 pins = "gpio8 3465 pins = "gpio8", "gpio9", "gpio10";
3816 function = "q 3466 function = "qup2";
3817 }; 3467 };
3818 3468
3819 qup_spi3_cs: qup-spi3 3469 qup_spi3_cs: qup-spi3-cs-state {
3820 pins = "gpio1 3470 pins = "gpio15";
3821 function = "q 3471 function = "qup3";
3822 }; 3472 };
3823 3473
3824 qup_spi3_data_clk: qu 3474 qup_spi3_data_clk: qup-spi3-data-clk-state {
3825 pins = "gpio1 3475 pins = "gpio12", "gpio13", "gpio14";
3826 function = "q 3476 function = "qup3";
3827 }; 3477 };
3828 3478
3829 qup_spi4_cs: qup-spi4 3479 qup_spi4_cs: qup-spi4-cs-state {
3830 pins = "gpio1 3480 pins = "gpio19";
3831 function = "q 3481 function = "qup4";
3832 drive-strengt 3482 drive-strength = <6>;
3833 bias-disable; 3483 bias-disable;
3834 }; 3484 };
3835 3485
3836 qup_spi4_data_clk: qu 3486 qup_spi4_data_clk: qup-spi4-data-clk-state {
3837 pins = "gpio1 3487 pins = "gpio16", "gpio17", "gpio18";
3838 function = "q 3488 function = "qup4";
3839 }; 3489 };
3840 3490
3841 qup_spi5_cs: qup-spi5 3491 qup_spi5_cs: qup-spi5-cs-state {
3842 pins = "gpio8 3492 pins = "gpio85";
3843 function = "q 3493 function = "qup5";
3844 }; 3494 };
3845 3495
3846 qup_spi5_data_clk: qu 3496 qup_spi5_data_clk: qup-spi5-data-clk-state {
3847 pins = "gpio2 3497 pins = "gpio206", "gpio207", "gpio84";
3848 function = "q 3498 function = "qup5";
3849 }; 3499 };
3850 3500
3851 qup_spi6_cs: qup-spi6 3501 qup_spi6_cs: qup-spi6-cs-state {
3852 pins = "gpio2 3502 pins = "gpio23";
3853 function = "q 3503 function = "qup6";
3854 }; 3504 };
3855 3505
3856 qup_spi6_data_clk: qu 3506 qup_spi6_data_clk: qup-spi6-data-clk-state {
3857 pins = "gpio2 3507 pins = "gpio20", "gpio21", "gpio22";
3858 function = "q 3508 function = "qup6";
3859 }; 3509 };
3860 3510
3861 qup_spi8_cs: qup-spi8 3511 qup_spi8_cs: qup-spi8-cs-state {
3862 pins = "gpio3 3512 pins = "gpio31";
3863 function = "q 3513 function = "qup8";
3864 }; 3514 };
3865 3515
3866 qup_spi8_data_clk: qu 3516 qup_spi8_data_clk: qup-spi8-data-clk-state {
3867 pins = "gpio2 3517 pins = "gpio28", "gpio29", "gpio30";
3868 function = "q 3518 function = "qup8";
3869 }; 3519 };
3870 3520
3871 qup_spi9_cs: qup-spi9 3521 qup_spi9_cs: qup-spi9-cs-state {
3872 pins = "gpio3 3522 pins = "gpio35";
3873 function = "q 3523 function = "qup9";
3874 }; 3524 };
3875 3525
3876 qup_spi9_data_clk: qu 3526 qup_spi9_data_clk: qup-spi9-data-clk-state {
3877 pins = "gpio3 3527 pins = "gpio32", "gpio33", "gpio34";
3878 function = "q 3528 function = "qup9";
3879 }; 3529 };
3880 3530
3881 qup_spi10_cs: qup-spi 3531 qup_spi10_cs: qup-spi10-cs-state {
3882 pins = "gpio3 3532 pins = "gpio39";
3883 function = "q 3533 function = "qup10";
3884 }; 3534 };
3885 3535
3886 qup_spi10_data_clk: q 3536 qup_spi10_data_clk: qup-spi10-data-clk-state {
3887 pins = "gpio3 3537 pins = "gpio36", "gpio37", "gpio38";
3888 function = "q 3538 function = "qup10";
3889 }; 3539 };
3890 3540
3891 qup_spi11_cs: qup-spi 3541 qup_spi11_cs: qup-spi11-cs-state {
3892 pins = "gpio4 3542 pins = "gpio43";
3893 function = "q 3543 function = "qup11";
3894 }; 3544 };
3895 3545
3896 qup_spi11_data_clk: q 3546 qup_spi11_data_clk: qup-spi11-data-clk-state {
3897 pins = "gpio4 3547 pins = "gpio40", "gpio41", "gpio42";
3898 function = "q 3548 function = "qup11";
3899 }; 3549 };
3900 3550
3901 qup_spi12_cs: qup-spi 3551 qup_spi12_cs: qup-spi12-cs-state {
3902 pins = "gpio4 3552 pins = "gpio47";
3903 function = "q 3553 function = "qup12";
3904 }; 3554 };
3905 3555
3906 qup_spi12_data_clk: q 3556 qup_spi12_data_clk: qup-spi12-data-clk-state {
3907 pins = "gpio4 3557 pins = "gpio44", "gpio45", "gpio46";
3908 function = "q 3558 function = "qup12";
3909 }; 3559 };
3910 3560
3911 qup_spi13_cs: qup-spi 3561 qup_spi13_cs: qup-spi13-cs-state {
3912 pins = "gpio5 3562 pins = "gpio51";
3913 function = "q 3563 function = "qup13";
3914 }; 3564 };
3915 3565
3916 qup_spi13_data_clk: q 3566 qup_spi13_data_clk: qup-spi13-data-clk-state {
3917 pins = "gpio4 3567 pins = "gpio48", "gpio49", "gpio50";
3918 function = "q 3568 function = "qup13";
3919 }; 3569 };
3920 3570
3921 qup_spi14_cs: qup-spi 3571 qup_spi14_cs: qup-spi14-cs-state {
3922 pins = "gpio5 3572 pins = "gpio55";
3923 function = "q 3573 function = "qup14";
3924 }; 3574 };
3925 3575
3926 qup_spi14_data_clk: q 3576 qup_spi14_data_clk: qup-spi14-data-clk-state {
3927 pins = "gpio5 3577 pins = "gpio52", "gpio53", "gpio54";
3928 function = "q 3578 function = "qup14";
3929 }; 3579 };
3930 3580
3931 qup_spi15_cs: qup-spi 3581 qup_spi15_cs: qup-spi15-cs-state {
3932 pins = "gpio5 3582 pins = "gpio59";
3933 function = "q 3583 function = "qup15";
3934 }; 3584 };
3935 3585
3936 qup_spi15_data_clk: q 3586 qup_spi15_data_clk: qup-spi15-data-clk-state {
3937 pins = "gpio5 3587 pins = "gpio56", "gpio57", "gpio58";
3938 function = "q 3588 function = "qup15";
3939 }; 3589 };
3940 3590
3941 qup_spi16_cs: qup-spi 3591 qup_spi16_cs: qup-spi16-cs-state {
3942 pins = "gpio6 3592 pins = "gpio63";
3943 function = "q 3593 function = "qup16";
3944 }; 3594 };
3945 3595
3946 qup_spi16_data_clk: q 3596 qup_spi16_data_clk: qup-spi16-data-clk-state {
3947 pins = "gpio6 3597 pins = "gpio60", "gpio61", "gpio62";
3948 function = "q 3598 function = "qup16";
3949 }; 3599 };
3950 3600
3951 qup_spi17_cs: qup-spi 3601 qup_spi17_cs: qup-spi17-cs-state {
3952 pins = "gpio6 3602 pins = "gpio67";
3953 function = "q 3603 function = "qup17";
3954 }; 3604 };
3955 3605
3956 qup_spi17_data_clk: q 3606 qup_spi17_data_clk: qup-spi17-data-clk-state {
3957 pins = "gpio6 3607 pins = "gpio64", "gpio65", "gpio66";
3958 function = "q 3608 function = "qup17";
3959 }; 3609 };
3960 3610
3961 qup_spi18_cs: qup-spi 3611 qup_spi18_cs: qup-spi18-cs-state {
3962 pins = "gpio7 3612 pins = "gpio71";
3963 function = "q 3613 function = "qup18";
3964 drive-strengt 3614 drive-strength = <6>;
3965 bias-disable; 3615 bias-disable;
3966 }; 3616 };
3967 3617
3968 qup_spi18_data_clk: q 3618 qup_spi18_data_clk: qup-spi18-data-clk-state {
3969 pins = "gpio6 3619 pins = "gpio68", "gpio69", "gpio70";
3970 function = "q 3620 function = "qup18";
3971 drive-strengt 3621 drive-strength = <6>;
3972 bias-disable; 3622 bias-disable;
3973 }; 3623 };
3974 3624
3975 qup_spi19_cs: qup-spi 3625 qup_spi19_cs: qup-spi19-cs-state {
3976 pins = "gpio7 3626 pins = "gpio75";
3977 function = "q 3627 function = "qup19";
3978 drive-strengt 3628 drive-strength = <6>;
3979 bias-disable; 3629 bias-disable;
3980 }; 3630 };
3981 3631
3982 qup_spi19_data_clk: q 3632 qup_spi19_data_clk: qup-spi19-data-clk-state {
3983 pins = "gpio7 3633 pins = "gpio72", "gpio73", "gpio74";
3984 function = "q 3634 function = "qup19";
3985 drive-strengt 3635 drive-strength = <6>;
3986 bias-disable; 3636 bias-disable;
3987 }; 3637 };
3988 3638
3989 qup_spi20_cs: qup-spi 3639 qup_spi20_cs: qup-spi20-cs-state {
3990 pins = "gpio7 3640 pins = "gpio79";
3991 function = "q 3641 function = "qup20";
3992 }; 3642 };
3993 3643
3994 qup_spi20_data_clk: q 3644 qup_spi20_data_clk: qup-spi20-data-clk-state {
3995 pins = "gpio7 3645 pins = "gpio76", "gpio77", "gpio78";
3996 function = "q 3646 function = "qup20";
3997 }; 3647 };
3998 3648
3999 qup_spi21_cs: qup-spi 3649 qup_spi21_cs: qup-spi21-cs-state {
4000 pins = "gpio8 3650 pins = "gpio83";
4001 function = "q 3651 function = "qup21";
4002 }; 3652 };
4003 3653
4004 qup_spi21_data_clk: q 3654 qup_spi21_data_clk: qup-spi21-data-clk-state {
4005 pins = "gpio8 3655 pins = "gpio80", "gpio81", "gpio82";
4006 function = "q 3656 function = "qup21";
4007 }; 3657 };
4008 3658
4009 qup_uart7_rx: qup-uar 3659 qup_uart7_rx: qup-uart7-rx-state {
4010 pins = "gpio2 3660 pins = "gpio26";
4011 function = "q 3661 function = "qup7";
4012 drive-strengt 3662 drive-strength = <2>;
4013 bias-disable; 3663 bias-disable;
4014 }; 3664 };
4015 3665
4016 qup_uart7_tx: qup-uar 3666 qup_uart7_tx: qup-uart7-tx-state {
4017 pins = "gpio2 3667 pins = "gpio27";
4018 function = "q 3668 function = "qup7";
4019 drive-strengt 3669 drive-strength = <2>;
4020 bias-disable; 3670 bias-disable;
4021 }; 3671 };
4022 3672
4023 qup_uart20_default: q 3673 qup_uart20_default: qup-uart20-default-state {
4024 pins = "gpio7 3674 pins = "gpio76", "gpio77", "gpio78", "gpio79";
4025 function = "q 3675 function = "qup20";
4026 }; 3676 };
4027 }; 3677 };
4028 3678
4029 lpass_tlmm: pinctrl@3440000 { 3679 lpass_tlmm: pinctrl@3440000 {
4030 compatible = "qcom,sm 3680 compatible = "qcom,sm8450-lpass-lpi-pinctrl";
4031 reg = <0 0x03440000 0 3681 reg = <0 0x03440000 0x0 0x20000>,
4032 <0 0x034d0000 0 3682 <0 0x034d0000 0x0 0x10000>;
4033 gpio-controller; 3683 gpio-controller;
4034 #gpio-cells = <2>; 3684 #gpio-cells = <2>;
4035 gpio-ranges = <&lpass 3685 gpio-ranges = <&lpass_tlmm 0 0 23>;
4036 3686
4037 clocks = <&q6prmcc LP 3687 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
4038 <&q6prmcc LP 3688 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
4039 clock-names = "core", 3689 clock-names = "core", "audio";
4040 3690
4041 tx_swr_active: tx-swr 3691 tx_swr_active: tx-swr-active-state {
4042 clk-pins { 3692 clk-pins {
4043 pins 3693 pins = "gpio0";
4044 funct 3694 function = "swr_tx_clk";
4045 drive 3695 drive-strength = <2>;
4046 slew- 3696 slew-rate = <1>;
4047 bias- 3697 bias-disable;
4048 }; 3698 };
4049 3699
4050 data-pins { 3700 data-pins {
4051 pins 3701 pins = "gpio1", "gpio2", "gpio14";
4052 funct 3702 function = "swr_tx_data";
4053 drive 3703 drive-strength = <2>;
4054 slew- 3704 slew-rate = <1>;
4055 bias- 3705 bias-bus-hold;
4056 }; 3706 };
4057 }; 3707 };
4058 3708
4059 rx_swr_active: rx-swr 3709 rx_swr_active: rx-swr-active-state {
4060 clk-pins { 3710 clk-pins {
4061 pins 3711 pins = "gpio3";
4062 funct 3712 function = "swr_rx_clk";
4063 drive 3713 drive-strength = <2>;
4064 slew- 3714 slew-rate = <1>;
4065 bias- 3715 bias-disable;
4066 }; 3716 };
4067 3717
4068 data-pins { 3718 data-pins {
4069 pins 3719 pins = "gpio4", "gpio5";
4070 funct 3720 function = "swr_rx_data";
4071 drive 3721 drive-strength = <2>;
4072 slew- 3722 slew-rate = <1>;
4073 bias- 3723 bias-bus-hold;
4074 }; 3724 };
4075 }; 3725 };
4076 3726
4077 dmic01_default: dmic0 3727 dmic01_default: dmic01-default-state {
4078 clk-pins { 3728 clk-pins {
4079 pins 3729 pins = "gpio6";
4080 funct 3730 function = "dmic1_clk";
4081 drive 3731 drive-strength = <8>;
4082 outpu 3732 output-high;
4083 }; 3733 };
4084 3734
4085 data-pins { 3735 data-pins {
4086 pins 3736 pins = "gpio7";
4087 funct 3737 function = "dmic1_data";
4088 drive 3738 drive-strength = <8>;
4089 }; 3739 };
4090 }; 3740 };
4091 3741
4092 dmic23_default: dmic2 !! 3742 dmic02_default: dmic02-default-state {
4093 clk-pins { 3743 clk-pins {
4094 pins 3744 pins = "gpio8";
4095 funct 3745 function = "dmic2_clk";
4096 drive 3746 drive-strength = <8>;
4097 outpu 3747 output-high;
4098 }; 3748 };
4099 3749
4100 data-pins { 3750 data-pins {
4101 pins 3751 pins = "gpio9";
4102 funct 3752 function = "dmic2_data";
4103 drive 3753 drive-strength = <8>;
4104 }; 3754 };
4105 }; 3755 };
4106 3756
4107 wsa_swr_active: wsa-s 3757 wsa_swr_active: wsa-swr-active-state {
4108 clk-pins { 3758 clk-pins {
4109 pins 3759 pins = "gpio10";
4110 funct 3760 function = "wsa_swr_clk";
4111 drive 3761 drive-strength = <2>;
4112 slew- 3762 slew-rate = <1>;
4113 bias- 3763 bias-disable;
4114 }; 3764 };
4115 3765
4116 data-pins { 3766 data-pins {
4117 pins 3767 pins = "gpio11";
4118 funct 3768 function = "wsa_swr_data";
4119 drive 3769 drive-strength = <2>;
4120 slew- 3770 slew-rate = <1>;
4121 bias- 3771 bias-bus-hold;
4122 }; 3772 };
4123 }; 3773 };
4124 3774
4125 wsa2_swr_active: wsa2 3775 wsa2_swr_active: wsa2-swr-active-state {
4126 clk-pins { 3776 clk-pins {
4127 pins 3777 pins = "gpio15";
4128 funct 3778 function = "wsa2_swr_clk";
4129 drive 3779 drive-strength = <2>;
4130 slew- 3780 slew-rate = <1>;
4131 bias- 3781 bias-disable;
4132 }; 3782 };
4133 3783
4134 data-pins { 3784 data-pins {
4135 pins 3785 pins = "gpio16";
4136 funct 3786 function = "wsa2_swr_data";
4137 drive 3787 drive-strength = <2>;
4138 slew- 3788 slew-rate = <1>;
4139 bias- 3789 bias-bus-hold;
4140 }; 3790 };
4141 }; 3791 };
4142 }; 3792 };
4143 3793
4144 sram@146aa000 { 3794 sram@146aa000 {
4145 compatible = "qcom,sm 3795 compatible = "qcom,sm8450-imem", "syscon", "simple-mfd";
4146 reg = <0 0x146aa000 0 3796 reg = <0 0x146aa000 0 0x1000>;
4147 ranges = <0 0 0x146aa 3797 ranges = <0 0 0x146aa000 0x1000>;
4148 3798
4149 #address-cells = <1>; 3799 #address-cells = <1>;
4150 #size-cells = <1>; 3800 #size-cells = <1>;
4151 3801
4152 pil-reloc@94c { 3802 pil-reloc@94c {
4153 compatible = 3803 compatible = "qcom,pil-reloc-info";
4154 reg = <0x94c 3804 reg = <0x94c 0xc8>;
4155 }; 3805 };
4156 }; 3806 };
4157 3807
4158 apps_smmu: iommu@15000000 { 3808 apps_smmu: iommu@15000000 {
4159 compatible = "qcom,sm 3809 compatible = "qcom,sm8450-smmu-500", "arm,mmu-500";
4160 reg = <0 0x15000000 0 3810 reg = <0 0x15000000 0 0x100000>;
4161 #iommu-cells = <2>; 3811 #iommu-cells = <2>;
4162 #global-interrupts = 3812 #global-interrupts = <1>;
4163 interrupts = <GIC_SPI 3813 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
4164 <GIC_SPI 3814 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
4165 <GIC_SPI 3815 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
4166 <GIC_SPI 3816 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
4167 <GIC_SPI 3817 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
4168 <GIC_SPI 3818 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
4169 <GIC_SPI 3819 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
4170 <GIC_SPI 3820 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
4171 <GIC_SPI 3821 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
4172 <GIC_SPI 3822 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
4173 <GIC_SPI 3823 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
4174 <GIC_SPI 3824 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
4175 <GIC_SPI 3825 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
4176 <GIC_SPI 3826 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
4177 <GIC_SPI 3827 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
4178 <GIC_SPI 3828 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
4179 <GIC_SPI 3829 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
4180 <GIC_SPI 3830 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
4181 <GIC_SPI 3831 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
4182 <GIC_SPI 3832 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
4183 <GIC_SPI 3833 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
4184 <GIC_SPI 3834 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
4185 <GIC_SPI 3835 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
4186 <GIC_SPI 3836 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
4187 <GIC_SPI 3837 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
4188 <GIC_SPI 3838 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
4189 <GIC_SPI 3839 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
4190 <GIC_SPI 3840 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
4191 <GIC_SPI 3841 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
4192 <GIC_SPI 3842 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
4193 <GIC_SPI 3843 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
4194 <GIC_SPI 3844 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
4195 <GIC_SPI 3845 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
4196 <GIC_SPI 3846 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
4197 <GIC_SPI 3847 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
4198 <GIC_SPI 3848 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
4199 <GIC_SPI 3849 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
4200 <GIC_SPI 3850 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
4201 <GIC_SPI 3851 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
4202 <GIC_SPI 3852 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
4203 <GIC_SPI 3853 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
4204 <GIC_SPI 3854 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
4205 <GIC_SPI 3855 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
4206 <GIC_SPI 3856 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
4207 <GIC_SPI 3857 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
4208 <GIC_SPI 3858 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
4209 <GIC_SPI 3859 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
4210 <GIC_SPI 3860 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
4211 <GIC_SPI 3861 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
4212 <GIC_SPI 3862 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
4213 <GIC_SPI 3863 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
4214 <GIC_SPI 3864 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
4215 <GIC_SPI 3865 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
4216 <GIC_SPI 3866 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
4217 <GIC_SPI 3867 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
4218 <GIC_SPI 3868 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
4219 <GIC_SPI 3869 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
4220 <GIC_SPI 3870 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
4221 <GIC_SPI 3871 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
4222 <GIC_SPI 3872 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
4223 <GIC_SPI 3873 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
4224 <GIC_SPI 3874 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
4225 <GIC_SPI 3875 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
4226 <GIC_SPI 3876 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
4227 <GIC_SPI 3877 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
4228 <GIC_SPI 3878 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
4229 <GIC_SPI 3879 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
4230 <GIC_SPI 3880 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
4231 <GIC_SPI 3881 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
4232 <GIC_SPI 3882 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
4233 <GIC_SPI 3883 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
4234 <GIC_SPI 3884 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
4235 <GIC_SPI 3885 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
4236 <GIC_SPI 3886 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
4237 <GIC_SPI 3887 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
4238 <GIC_SPI 3888 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
4239 <GIC_SPI 3889 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
4240 <GIC_SPI 3890 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
4241 <GIC_SPI 3891 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
4242 <GIC_SPI 3892 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
4243 <GIC_SPI 3893 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
4244 <GIC_SPI 3894 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
4245 <GIC_SPI 3895 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
4246 <GIC_SPI 3896 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
4247 <GIC_SPI 3897 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
4248 <GIC_SPI 3898 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
4249 <GIC_SPI 3899 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
4250 <GIC_SPI 3900 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
4251 <GIC_SPI 3901 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
4252 <GIC_SPI 3902 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
4253 <GIC_SPI 3903 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
4254 <GIC_SPI 3904 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
4255 <GIC_SPI 3905 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
4256 <GIC_SPI 3906 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
4257 <GIC_SPI 3907 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
4258 <GIC_SPI 3908 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
4259 <GIC_SPI 3909 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>;
4260 }; 3910 };
4261 3911
4262 intc: interrupt-controller@17 3912 intc: interrupt-controller@17100000 {
4263 compatible = "arm,gic 3913 compatible = "arm,gic-v3";
4264 #interrupt-cells = <3 3914 #interrupt-cells = <3>;
4265 interrupt-controller; 3915 interrupt-controller;
4266 #redistributor-region 3916 #redistributor-regions = <1>;
4267 redistributor-stride 3917 redistributor-stride = <0x0 0x40000>;
4268 reg = <0x0 0x17100000 3918 reg = <0x0 0x17100000 0x0 0x10000>, /* GICD */
4269 <0x0 0x17180000 3919 <0x0 0x17180000 0x0 0x200000>; /* GICR * 8 */
4270 interrupts = <GIC_PPI 3920 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
4271 #address-cells = <2>; 3921 #address-cells = <2>;
4272 #size-cells = <2>; 3922 #size-cells = <2>;
4273 ranges; 3923 ranges;
4274 3924
4275 gic_its: msi-controll 3925 gic_its: msi-controller@17140000 {
4276 compatible = 3926 compatible = "arm,gic-v3-its";
4277 reg = <0x0 0x 3927 reg = <0x0 0x17140000 0x0 0x20000>;
4278 msi-controlle 3928 msi-controller;
4279 #msi-cells = 3929 #msi-cells = <1>;
4280 }; 3930 };
4281 }; 3931 };
4282 3932
4283 timer@17420000 { 3933 timer@17420000 {
4284 compatible = "arm,arm 3934 compatible = "arm,armv7-timer-mem";
4285 #address-cells = <1>; 3935 #address-cells = <1>;
4286 #size-cells = <1>; 3936 #size-cells = <1>;
4287 ranges = <0 0 0 0x200 3937 ranges = <0 0 0 0x20000000>;
4288 reg = <0x0 0x17420000 3938 reg = <0x0 0x17420000 0x0 0x1000>;
4289 clock-frequency = <19 3939 clock-frequency = <19200000>;
4290 3940
4291 frame@17421000 { 3941 frame@17421000 {
4292 frame-number 3942 frame-number = <0>;
4293 interrupts = 3943 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
4294 3944 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
4295 reg = <0x1742 3945 reg = <0x17421000 0x1000>,
4296 <0x1742 3946 <0x17422000 0x1000>;
4297 }; 3947 };
4298 3948
4299 frame@17423000 { 3949 frame@17423000 {
4300 frame-number 3950 frame-number = <1>;
4301 interrupts = 3951 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
4302 reg = <0x1742 3952 reg = <0x17423000 0x1000>;
4303 status = "dis 3953 status = "disabled";
4304 }; 3954 };
4305 3955
4306 frame@17425000 { 3956 frame@17425000 {
4307 frame-number 3957 frame-number = <2>;
4308 interrupts = 3958 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
4309 reg = <0x1742 3959 reg = <0x17425000 0x1000>;
4310 status = "dis 3960 status = "disabled";
4311 }; 3961 };
4312 3962
4313 frame@17427000 { 3963 frame@17427000 {
4314 frame-number 3964 frame-number = <3>;
4315 interrupts = 3965 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
4316 reg = <0x1742 3966 reg = <0x17427000 0x1000>;
4317 status = "dis 3967 status = "disabled";
4318 }; 3968 };
4319 3969
4320 frame@17429000 { 3970 frame@17429000 {
4321 frame-number 3971 frame-number = <4>;
4322 interrupts = 3972 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
4323 reg = <0x1742 3973 reg = <0x17429000 0x1000>;
4324 status = "dis 3974 status = "disabled";
4325 }; 3975 };
4326 3976
4327 frame@1742b000 { 3977 frame@1742b000 {
4328 frame-number 3978 frame-number = <5>;
4329 interrupts = 3979 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
4330 reg = <0x1742 3980 reg = <0x1742b000 0x1000>;
4331 status = "dis 3981 status = "disabled";
4332 }; 3982 };
4333 3983
4334 frame@1742d000 { 3984 frame@1742d000 {
4335 frame-number 3985 frame-number = <6>;
4336 interrupts = 3986 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
4337 reg = <0x1742 3987 reg = <0x1742d000 0x1000>;
4338 status = "dis 3988 status = "disabled";
4339 }; 3989 };
4340 }; 3990 };
4341 3991
4342 apps_rsc: rsc@17a00000 { 3992 apps_rsc: rsc@17a00000 {
4343 label = "apps_rsc"; 3993 label = "apps_rsc";
4344 compatible = "qcom,rp 3994 compatible = "qcom,rpmh-rsc";
4345 reg = <0x0 0x17a00000 3995 reg = <0x0 0x17a00000 0x0 0x10000>,
4346 <0x0 0x17a10000 3996 <0x0 0x17a10000 0x0 0x10000>,
4347 <0x0 0x17a20000 3997 <0x0 0x17a20000 0x0 0x10000>,
4348 <0x0 0x17a30000 3998 <0x0 0x17a30000 0x0 0x10000>;
4349 reg-names = "drv-0", 3999 reg-names = "drv-0", "drv-1", "drv-2", "drv-3";
4350 interrupts = <GIC_SPI 4000 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
4351 <GIC_SPI 4001 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
4352 <GIC_SPI 4002 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
4353 qcom,tcs-offset = <0x 4003 qcom,tcs-offset = <0xd00>;
4354 qcom,drv-id = <2>; 4004 qcom,drv-id = <2>;
4355 qcom,tcs-config = <AC 4005 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
4356 <WA 4006 <WAKE_TCS 2>, <CONTROL_TCS 0>;
4357 power-domains = <&CLU 4007 power-domains = <&CLUSTER_PD>;
4358 4008
4359 apps_bcm_voter: bcm-v 4009 apps_bcm_voter: bcm-voter {
4360 compatible = 4010 compatible = "qcom,bcm-voter";
4361 }; 4011 };
4362 4012
4363 rpmhcc: clock-control 4013 rpmhcc: clock-controller {
4364 compatible = 4014 compatible = "qcom,sm8450-rpmh-clk";
4365 #clock-cells 4015 #clock-cells = <1>;
4366 clock-names = 4016 clock-names = "xo";
4367 clocks = <&xo 4017 clocks = <&xo_board>;
4368 }; 4018 };
4369 4019
4370 rpmhpd: power-control 4020 rpmhpd: power-controller {
4371 compatible = 4021 compatible = "qcom,sm8450-rpmhpd";
4372 #power-domain 4022 #power-domain-cells = <1>;
4373 operating-poi 4023 operating-points-v2 = <&rpmhpd_opp_table>;
4374 4024
4375 rpmhpd_opp_ta 4025 rpmhpd_opp_table: opp-table {
4376 compa 4026 compatible = "operating-points-v2";
4377 4027
4378 rpmhp 4028 rpmhpd_opp_ret: opp1 {
4379 4029 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4380 }; 4030 };
4381 4031
4382 rpmhp 4032 rpmhpd_opp_min_svs: opp2 {
4383 4033 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4384 }; 4034 };
4385 4035
4386 rpmhp 4036 rpmhpd_opp_low_svs_d1: opp3 {
4387 4037 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
4388 }; 4038 };
4389 4039
4390 rpmhp 4040 rpmhpd_opp_low_svs: opp4 {
4391 4041 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4392 }; 4042 };
4393 4043
4394 rpmhp 4044 rpmhpd_opp_low_svs_l1: opp5 {
4395 4045 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
4396 }; 4046 };
4397 4047
4398 rpmhp 4048 rpmhpd_opp_svs: opp6 {
4399 4049 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4400 }; 4050 };
4401 4051
4402 rpmhp 4052 rpmhpd_opp_svs_l0: opp7 {
4403 4053 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
4404 }; 4054 };
4405 4055
4406 rpmhp 4056 rpmhpd_opp_svs_l1: opp8 {
4407 4057 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4408 }; 4058 };
4409 4059
4410 rpmhp 4060 rpmhpd_opp_svs_l2: opp9 {
4411 4061 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
4412 }; 4062 };
4413 4063
4414 rpmhp 4064 rpmhpd_opp_nom: opp10 {
4415 4065 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4416 }; 4066 };
4417 4067
4418 rpmhp 4068 rpmhpd_opp_nom_l1: opp11 {
4419 4069 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4420 }; 4070 };
4421 4071
4422 rpmhp 4072 rpmhpd_opp_nom_l2: opp12 {
4423 4073 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4424 }; 4074 };
4425 4075
4426 rpmhp 4076 rpmhpd_opp_turbo: opp13 {
4427 4077 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4428 }; 4078 };
4429 4079
4430 rpmhp 4080 rpmhpd_opp_turbo_l1: opp14 {
4431 4081 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4432 }; 4082 };
4433 }; 4083 };
4434 }; 4084 };
4435 }; 4085 };
4436 4086
4437 cpufreq_hw: cpufreq@17d91000 4087 cpufreq_hw: cpufreq@17d91000 {
4438 compatible = "qcom,sm 4088 compatible = "qcom,sm8450-cpufreq-epss", "qcom,cpufreq-epss";
4439 reg = <0 0x17d91000 0 4089 reg = <0 0x17d91000 0 0x1000>,
4440 <0 0x17d92000 0 4090 <0 0x17d92000 0 0x1000>,
4441 <0 0x17d93000 0 4091 <0 0x17d93000 0 0x1000>;
4442 reg-names = "freq-dom 4092 reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
4443 clocks = <&rpmhcc RPM 4093 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
4444 clock-names = "xo", " 4094 clock-names = "xo", "alternate";
4445 interrupts = <GIC_SPI 4095 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
4446 <GIC_SPI 4096 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
4447 <GIC_SPI 4097 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
4448 interrupt-names = "dc 4098 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
4449 #freq-domain-cells = 4099 #freq-domain-cells = <1>;
4450 #clock-cells = <1>; 4100 #clock-cells = <1>;
4451 }; 4101 };
4452 4102
4453 gem_noc: interconnect@1910000 4103 gem_noc: interconnect@19100000 {
4454 compatible = "qcom,sm 4104 compatible = "qcom,sm8450-gem-noc";
4455 reg = <0 0x19100000 0 4105 reg = <0 0x19100000 0 0xbb800>;
4456 #interconnect-cells = 4106 #interconnect-cells = <2>;
4457 qcom,bcm-voters = <&a 4107 qcom,bcm-voters = <&apps_bcm_voter>;
4458 }; 4108 };
4459 4109
4460 system-cache-controller@19200 4110 system-cache-controller@19200000 {
4461 compatible = "qcom,sm 4111 compatible = "qcom,sm8450-llcc";
4462 reg = <0 0x19200000 0 4112 reg = <0 0x19200000 0 0x80000>, <0 0x19600000 0 0x80000>,
4463 <0 0x19300000 0 4113 <0 0x19300000 0 0x80000>, <0 0x19700000 0 0x80000>,
4464 <0 0x19a00000 0 !! 4114 <0 0x19a00000 0 0x80000>;
4465 reg-names = "llcc0_ba 4115 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
4466 "llcc3_ba !! 4116 "llcc3_base", "llcc_broadcast_base";
4467 "llcc_bro <<
4468 interrupts = <GIC_SPI 4117 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
4469 }; 4118 };
4470 4119
4471 ufs_mem_hc: ufshc@1d84000 { 4120 ufs_mem_hc: ufshc@1d84000 {
4472 compatible = "qcom,sm 4121 compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
4473 "jedec,u 4122 "jedec,ufs-2.0";
4474 reg = <0 0x01d84000 0 !! 4123 reg = <0 0x01d84000 0 0x3000>,
>> 4124 <0 0x01d88000 0 0x8000>;
>> 4125 reg-names = "std", "ice";
4475 interrupts = <GIC_SPI 4126 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
4476 phys = <&ufs_mem_phy> !! 4127 phys = <&ufs_mem_phy_lanes>;
4477 phy-names = "ufsphy"; 4128 phy-names = "ufsphy";
4478 lanes-per-direction = 4129 lanes-per-direction = <2>;
4479 #reset-cells = <1>; 4130 #reset-cells = <1>;
4480 resets = <&gcc GCC_UF 4131 resets = <&gcc GCC_UFS_PHY_BCR>;
4481 reset-names = "rst"; 4132 reset-names = "rst";
4482 4133
4483 power-domains = <&gcc 4134 power-domains = <&gcc UFS_PHY_GDSC>;
4484 4135
4485 iommus = <&apps_smmu 4136 iommus = <&apps_smmu 0xe0 0x0>;
4486 dma-coherent; 4137 dma-coherent;
4487 4138
4488 interconnects = <&agg 4139 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>,
4489 <&gem 4140 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
4490 interconnect-names = 4141 interconnect-names = "ufs-ddr", "cpu-ufs";
4491 clock-names = 4142 clock-names =
4492 "core_clk", 4143 "core_clk",
4493 "bus_aggr_clk 4144 "bus_aggr_clk",
4494 "iface_clk", 4145 "iface_clk",
4495 "core_clk_uni 4146 "core_clk_unipro",
4496 "ref_clk", 4147 "ref_clk",
4497 "tx_lane0_syn 4148 "tx_lane0_sync_clk",
4498 "rx_lane0_syn 4149 "rx_lane0_sync_clk",
4499 "rx_lane1_syn !! 4150 "rx_lane1_sync_clk",
>> 4151 "ice_core_clk";
4500 clocks = 4152 clocks =
4501 <&gcc GCC_UFS 4153 <&gcc GCC_UFS_PHY_AXI_CLK>,
4502 <&gcc GCC_AGG 4154 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
4503 <&gcc GCC_UFS 4155 <&gcc GCC_UFS_PHY_AHB_CLK>,
4504 <&gcc GCC_UFS 4156 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
4505 <&rpmhcc RPMH 4157 <&rpmhcc RPMH_CXO_CLK>,
4506 <&gcc GCC_UFS 4158 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
4507 <&gcc GCC_UFS 4159 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
4508 <&gcc GCC_UFS !! 4160 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
>> 4161 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
4509 freq-table-hz = 4162 freq-table-hz =
4510 <75000000 300 4163 <75000000 300000000>,
4511 <0 0>, 4164 <0 0>,
4512 <0 0>, 4165 <0 0>,
4513 <75000000 300 4166 <75000000 300000000>,
4514 <75000000 300 4167 <75000000 300000000>,
4515 <0 0>, 4168 <0 0>,
4516 <0 0>, 4169 <0 0>,
4517 <0 0>; !! 4170 <0 0>,
4518 qcom,ice = <&ice>; !! 4171 <75000000 300000000>;
4519 <<
4520 status = "disabled"; 4172 status = "disabled";
4521 }; 4173 };
4522 4174
4523 ufs_mem_phy: phy@1d87000 { 4175 ufs_mem_phy: phy@1d87000 {
4524 compatible = "qcom,sm 4176 compatible = "qcom,sm8450-qmp-ufs-phy";
4525 reg = <0 0x01d87000 0 !! 4177 reg = <0 0x01d87000 0 0x1c4>;
4526 !! 4178 #address-cells = <2>;
>> 4179 #size-cells = <2>;
>> 4180 ranges;
4527 clock-names = "ref", 4181 clock-names = "ref", "ref_aux", "qref";
4528 clocks = <&rpmhcc RPM 4182 clocks = <&rpmhcc RPMH_CXO_CLK>,
4529 <&gcc GCC_UF 4183 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
4530 <&gcc GCC_UF 4184 <&gcc GCC_UFS_0_CLKREF_EN>;
4531 4185
4532 power-domains = <&gcc <<
4533 <<
4534 resets = <&ufs_mem_hc 4186 resets = <&ufs_mem_hc 0>;
4535 reset-names = "ufsphy 4187 reset-names = "ufsphy";
4536 <<
4537 #clock-cells = <1>; <<
4538 #phy-cells = <0>; <<
4539 <<
4540 status = "disabled"; 4188 status = "disabled";
4541 }; <<
4542 4189
4543 ice: crypto@1d88000 { !! 4190 ufs_mem_phy_lanes: phy@1d87400 {
4544 compatible = "qcom,sm !! 4191 reg = <0 0x01d87400 0 0x188>,
4545 "qcom,in !! 4192 <0 0x01d87600 0 0x200>,
4546 reg = <0 0x01d88000 0 !! 4193 <0 0x01d87c00 0 0x200>,
4547 clocks = <&gcc GCC_UF !! 4194 <0 0x01d87800 0 0x188>,
>> 4195 <0 0x01d87a00 0 0x200>;
>> 4196 #clock-cells = <1>;
>> 4197 #phy-cells = <0>;
>> 4198 };
4548 }; 4199 };
4549 4200
4550 cryptobam: dma-controller@1dc 4201 cryptobam: dma-controller@1dc4000 {
4551 compatible = "qcom,ba 4202 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
4552 reg = <0 0x01dc4000 0 4203 reg = <0 0x01dc4000 0 0x28000>;
4553 interrupts = <GIC_SPI 4204 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
4554 #dma-cells = <1>; 4205 #dma-cells = <1>;
4555 qcom,ee = <0>; 4206 qcom,ee = <0>;
4556 qcom,controlled-remot 4207 qcom,controlled-remotely;
4557 iommus = <&apps_smmu 4208 iommus = <&apps_smmu 0x584 0x11>,
4558 <&apps_smmu 4209 <&apps_smmu 0x588 0x0>,
4559 <&apps_smmu 4210 <&apps_smmu 0x598 0x5>,
4560 <&apps_smmu 4211 <&apps_smmu 0x59a 0x0>,
4561 <&apps_smmu 4212 <&apps_smmu 0x59f 0x0>;
4562 }; 4213 };
4563 4214
4564 crypto: crypto@1dfa000 { 4215 crypto: crypto@1dfa000 {
4565 compatible = "qcom,sm 4216 compatible = "qcom,sm8450-qce", "qcom,sm8150-qce", "qcom,qce";
4566 reg = <0 0x01dfa000 0 4217 reg = <0 0x01dfa000 0 0x6000>;
4567 dmas = <&cryptobam 4> 4218 dmas = <&cryptobam 4>, <&cryptobam 5>;
4568 dma-names = "rx", "tx 4219 dma-names = "rx", "tx";
4569 iommus = <&apps_smmu 4220 iommus = <&apps_smmu 0x584 0x11>,
4570 <&apps_smmu 4221 <&apps_smmu 0x588 0x0>,
4571 <&apps_smmu 4222 <&apps_smmu 0x598 0x5>,
4572 <&apps_smmu 4223 <&apps_smmu 0x59a 0x0>,
4573 <&apps_smmu 4224 <&apps_smmu 0x59f 0x0>;
4574 interconnects = <&agg 4225 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
4575 interconnect-names = 4226 interconnect-names = "memory";
4576 }; 4227 };
4577 4228
4578 sdhc_2: mmc@8804000 { 4229 sdhc_2: mmc@8804000 {
4579 compatible = "qcom,sm 4230 compatible = "qcom,sm8450-sdhci", "qcom,sdhci-msm-v5";
4580 reg = <0 0x08804000 0 4231 reg = <0 0x08804000 0 0x1000>;
4581 4232
4582 interrupts = <GIC_SPI 4233 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
4583 <GIC_SPI 4234 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
4584 interrupt-names = "hc 4235 interrupt-names = "hc_irq", "pwr_irq";
4585 4236
4586 clocks = <&gcc GCC_SD 4237 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
4587 <&gcc GCC_SD 4238 <&gcc GCC_SDCC2_APPS_CLK>,
4588 <&rpmhcc RPM 4239 <&rpmhcc RPMH_CXO_CLK>;
4589 clock-names = "iface" 4240 clock-names = "iface", "core", "xo";
4590 resets = <&gcc GCC_SD 4241 resets = <&gcc GCC_SDCC2_BCR>;
4591 interconnects = <&agg 4242 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
4592 <&gem 4243 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
4593 interconnect-names = 4244 interconnect-names = "sdhc-ddr","cpu-sdhc";
4594 iommus = <&apps_smmu 4245 iommus = <&apps_smmu 0x4a0 0x0>;
4595 power-domains = <&rpm !! 4246 power-domains = <&rpmhpd SM8450_CX>;
4596 operating-points-v2 = 4247 operating-points-v2 = <&sdhc2_opp_table>;
4597 bus-width = <4>; 4248 bus-width = <4>;
4598 dma-coherent; 4249 dma-coherent;
4599 4250
4600 /* Forbid SDR104/SDR5 4251 /* Forbid SDR104/SDR50 - broken hw! */
4601 sdhci-caps-mask = <0x 4252 sdhci-caps-mask = <0x3 0x0>;
4602 4253
4603 status = "disabled"; 4254 status = "disabled";
4604 4255
4605 sdhc2_opp_table: opp- 4256 sdhc2_opp_table: opp-table {
4606 compatible = 4257 compatible = "operating-points-v2";
4607 4258
4608 opp-100000000 4259 opp-100000000 {
4609 opp-h 4260 opp-hz = /bits/ 64 <100000000>;
4610 requi 4261 required-opps = <&rpmhpd_opp_low_svs>;
4611 }; 4262 };
4612 4263
4613 opp-202000000 4264 opp-202000000 {
4614 opp-h 4265 opp-hz = /bits/ 64 <202000000>;
4615 requi 4266 required-opps = <&rpmhpd_opp_svs_l1>;
4616 }; 4267 };
4617 }; 4268 };
4618 }; 4269 };
4619 4270
4620 usb_1: usb@a6f8800 { 4271 usb_1: usb@a6f8800 {
4621 compatible = "qcom,sm 4272 compatible = "qcom,sm8450-dwc3", "qcom,dwc3";
4622 reg = <0 0x0a6f8800 0 4273 reg = <0 0x0a6f8800 0 0x400>;
4623 status = "disabled"; 4274 status = "disabled";
4624 #address-cells = <2>; 4275 #address-cells = <2>;
4625 #size-cells = <2>; 4276 #size-cells = <2>;
4626 ranges; 4277 ranges;
4627 4278
4628 clocks = <&gcc GCC_CF 4279 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
4629 <&gcc GCC_US 4280 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
4630 <&gcc GCC_AG 4281 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
4631 <&gcc GCC_US 4282 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
4632 <&gcc GCC_US 4283 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4633 <&gcc GCC_US 4284 <&gcc GCC_USB3_0_CLKREF_EN>;
4634 clock-names = "cfg_no 4285 clock-names = "cfg_noc",
4635 "core", 4286 "core",
4636 "iface" 4287 "iface",
4637 "sleep" 4288 "sleep",
4638 "mock_u 4289 "mock_utmi",
4639 "xo"; 4290 "xo";
4640 4291
4641 assigned-clocks = <&g 4292 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4642 <&g 4293 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
4643 assigned-clock-rates 4294 assigned-clock-rates = <19200000>, <200000000>;
4644 4295
4645 interrupts-extended = 4296 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
4646 !! 4297 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
4647 <<
4648 4298 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
4649 !! 4299 <&pdc 14 IRQ_TYPE_EDGE_BOTH>;
4650 interrupt-names = "pw !! 4300 interrupt-names = "hs_phy_irq",
4651 "hs !! 4301 "ss_phy_irq",
4652 "dp <<
4653 "dm 4302 "dm_hs_phy_irq",
4654 "ss !! 4303 "dp_hs_phy_irq";
4655 4304
4656 power-domains = <&gcc 4305 power-domains = <&gcc USB30_PRIM_GDSC>;
4657 4306
4658 resets = <&gcc GCC_US 4307 resets = <&gcc GCC_USB30_PRIM_BCR>;
4659 4308
4660 interconnects = <&agg 4309 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
4661 <&gem 4310 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
4662 interconnect-names = 4311 interconnect-names = "usb-ddr", "apps-usb";
4663 4312
4664 usb_1_dwc3: usb@a6000 4313 usb_1_dwc3: usb@a600000 {
4665 compatible = 4314 compatible = "snps,dwc3";
4666 reg = <0 0x0a 4315 reg = <0 0x0a600000 0 0xcd00>;
4667 interrupts = 4316 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
4668 iommus = <&ap 4317 iommus = <&apps_smmu 0x0 0x0>;
4669 snps,dis_u2_s 4318 snps,dis_u2_susphy_quirk;
4670 snps,dis_enbl 4319 snps,dis_enblslpm_quirk;
4671 phys = <&usb_ 4320 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
4672 phy-names = " 4321 phy-names = "usb2-phy", "usb3-phy";
4673 4322
4674 ports { 4323 ports {
4675 #addr 4324 #address-cells = <1>;
4676 #size 4325 #size-cells = <0>;
4677 4326
4678 port@ 4327 port@0 {
4679 4328 reg = <0>;
4680 4329
4681 4330 usb_1_dwc3_hs: endpoint {
4682 4331 };
4683 }; 4332 };
4684 4333
4685 port@ 4334 port@1 {
4686 4335 reg = <1>;
4687 4336
4688 4337 usb_1_dwc3_ss: endpoint {
4689 <<
4690 4338 };
4691 }; 4339 };
4692 }; 4340 };
4693 }; 4341 };
4694 }; 4342 };
4695 4343
4696 nsp_noc: interconnect@320c000 4344 nsp_noc: interconnect@320c0000 {
4697 compatible = "qcom,sm 4345 compatible = "qcom,sm8450-nsp-noc";
4698 reg = <0 0x320c0000 0 4346 reg = <0 0x320c0000 0 0x10000>;
4699 #interconnect-cells = 4347 #interconnect-cells = <2>;
4700 qcom,bcm-voters = <&a 4348 qcom,bcm-voters = <&apps_bcm_voter>;
4701 }; 4349 };
4702 4350
4703 lpass_ag_noc: interconnect@3c 4351 lpass_ag_noc: interconnect@3c40000 {
4704 compatible = "qcom,sm 4352 compatible = "qcom,sm8450-lpass-ag-noc";
4705 reg = <0 0x03c40000 0 4353 reg = <0 0x03c40000 0 0x17200>;
4706 #interconnect-cells = 4354 #interconnect-cells = <2>;
4707 qcom,bcm-voters = <&a 4355 qcom,bcm-voters = <&apps_bcm_voter>;
4708 }; 4356 };
4709 }; 4357 };
4710 4358
4711 sound: sound { 4359 sound: sound {
4712 }; 4360 };
4713 4361
4714 thermal-zones { 4362 thermal-zones {
4715 aoss0-thermal { 4363 aoss0-thermal {
>> 4364 polling-delay-passive = <0>;
>> 4365 polling-delay = <0>;
4716 thermal-sensors = <&t 4366 thermal-sensors = <&tsens0 0>;
4717 4367
4718 trips { 4368 trips {
4719 thermal-engin 4369 thermal-engine-config {
4720 tempe 4370 temperature = <125000>;
4721 hyste 4371 hysteresis = <1000>;
4722 type 4372 type = "passive";
4723 }; 4373 };
4724 4374
4725 reset-mon-cfg 4375 reset-mon-cfg {
4726 tempe 4376 temperature = <115000>;
4727 hyste 4377 hysteresis = <5000>;
4728 type 4378 type = "passive";
4729 }; 4379 };
4730 }; 4380 };
4731 }; 4381 };
4732 4382
4733 cpuss0-thermal { 4383 cpuss0-thermal {
>> 4384 polling-delay-passive = <0>;
>> 4385 polling-delay = <0>;
4734 thermal-sensors = <&t 4386 thermal-sensors = <&tsens0 1>;
4735 4387
4736 trips { 4388 trips {
4737 thermal-engin 4389 thermal-engine-config {
4738 tempe 4390 temperature = <125000>;
4739 hyste 4391 hysteresis = <1000>;
4740 type 4392 type = "passive";
4741 }; 4393 };
4742 4394
4743 reset-mon-cfg 4395 reset-mon-cfg {
4744 tempe 4396 temperature = <115000>;
4745 hyste 4397 hysteresis = <5000>;
4746 type 4398 type = "passive";
4747 }; 4399 };
4748 }; 4400 };
4749 }; 4401 };
4750 4402
4751 cpuss1-thermal { 4403 cpuss1-thermal {
>> 4404 polling-delay-passive = <0>;
>> 4405 polling-delay = <0>;
4752 thermal-sensors = <&t 4406 thermal-sensors = <&tsens0 2>;
4753 4407
4754 trips { 4408 trips {
4755 thermal-engin 4409 thermal-engine-config {
4756 tempe 4410 temperature = <125000>;
4757 hyste 4411 hysteresis = <1000>;
4758 type 4412 type = "passive";
4759 }; 4413 };
4760 4414
4761 reset-mon-cfg 4415 reset-mon-cfg {
4762 tempe 4416 temperature = <115000>;
4763 hyste 4417 hysteresis = <5000>;
4764 type 4418 type = "passive";
4765 }; 4419 };
4766 }; 4420 };
4767 }; 4421 };
4768 4422
4769 cpuss3-thermal { 4423 cpuss3-thermal {
>> 4424 polling-delay-passive = <0>;
>> 4425 polling-delay = <0>;
4770 thermal-sensors = <&t 4426 thermal-sensors = <&tsens0 3>;
4771 4427
4772 trips { 4428 trips {
4773 thermal-engin 4429 thermal-engine-config {
4774 tempe 4430 temperature = <125000>;
4775 hyste 4431 hysteresis = <1000>;
4776 type 4432 type = "passive";
4777 }; 4433 };
4778 4434
4779 reset-mon-cfg 4435 reset-mon-cfg {
4780 tempe 4436 temperature = <115000>;
4781 hyste 4437 hysteresis = <5000>;
4782 type 4438 type = "passive";
4783 }; 4439 };
4784 }; 4440 };
4785 }; 4441 };
4786 4442
4787 cpuss4-thermal { 4443 cpuss4-thermal {
>> 4444 polling-delay-passive = <0>;
>> 4445 polling-delay = <0>;
4788 thermal-sensors = <&t 4446 thermal-sensors = <&tsens0 4>;
4789 4447
4790 trips { 4448 trips {
4791 thermal-engin 4449 thermal-engine-config {
4792 tempe 4450 temperature = <125000>;
4793 hyste 4451 hysteresis = <1000>;
4794 type 4452 type = "passive";
4795 }; 4453 };
4796 4454
4797 reset-mon-cfg 4455 reset-mon-cfg {
4798 tempe 4456 temperature = <115000>;
4799 hyste 4457 hysteresis = <5000>;
4800 type 4458 type = "passive";
4801 }; 4459 };
4802 }; 4460 };
4803 }; 4461 };
4804 4462
4805 cpu4-top-thermal { 4463 cpu4-top-thermal {
>> 4464 polling-delay-passive = <0>;
>> 4465 polling-delay = <0>;
4806 thermal-sensors = <&t 4466 thermal-sensors = <&tsens0 5>;
4807 4467
4808 trips { 4468 trips {
4809 cpu4_top_aler 4469 cpu4_top_alert0: trip-point0 {
4810 tempe 4470 temperature = <90000>;
4811 hyste 4471 hysteresis = <2000>;
4812 type 4472 type = "passive";
4813 }; 4473 };
4814 4474
4815 cpu4_top_aler 4475 cpu4_top_alert1: trip-point1 {
4816 tempe 4476 temperature = <95000>;
4817 hyste 4477 hysteresis = <2000>;
4818 type 4478 type = "passive";
4819 }; 4479 };
4820 4480
4821 cpu4_top_crit 4481 cpu4_top_crit: cpu-crit {
4822 tempe 4482 temperature = <110000>;
4823 hyste 4483 hysteresis = <1000>;
4824 type 4484 type = "critical";
4825 }; 4485 };
4826 }; 4486 };
4827 }; 4487 };
4828 4488
4829 cpu4-bottom-thermal { 4489 cpu4-bottom-thermal {
>> 4490 polling-delay-passive = <0>;
>> 4491 polling-delay = <0>;
4830 thermal-sensors = <&t 4492 thermal-sensors = <&tsens0 6>;
4831 4493
4832 trips { 4494 trips {
4833 cpu4_bottom_a 4495 cpu4_bottom_alert0: trip-point0 {
4834 tempe 4496 temperature = <90000>;
4835 hyste 4497 hysteresis = <2000>;
4836 type 4498 type = "passive";
4837 }; 4499 };
4838 4500
4839 cpu4_bottom_a 4501 cpu4_bottom_alert1: trip-point1 {
4840 tempe 4502 temperature = <95000>;
4841 hyste 4503 hysteresis = <2000>;
4842 type 4504 type = "passive";
4843 }; 4505 };
4844 4506
4845 cpu4_bottom_c 4507 cpu4_bottom_crit: cpu-crit {
4846 tempe 4508 temperature = <110000>;
4847 hyste 4509 hysteresis = <1000>;
4848 type 4510 type = "critical";
4849 }; 4511 };
4850 }; 4512 };
4851 }; 4513 };
4852 4514
4853 cpu5-top-thermal { 4515 cpu5-top-thermal {
>> 4516 polling-delay-passive = <0>;
>> 4517 polling-delay = <0>;
4854 thermal-sensors = <&t 4518 thermal-sensors = <&tsens0 7>;
4855 4519
4856 trips { 4520 trips {
4857 cpu5_top_aler 4521 cpu5_top_alert0: trip-point0 {
4858 tempe 4522 temperature = <90000>;
4859 hyste 4523 hysteresis = <2000>;
4860 type 4524 type = "passive";
4861 }; 4525 };
4862 4526
4863 cpu5_top_aler 4527 cpu5_top_alert1: trip-point1 {
4864 tempe 4528 temperature = <95000>;
4865 hyste 4529 hysteresis = <2000>;
4866 type 4530 type = "passive";
4867 }; 4531 };
4868 4532
4869 cpu5_top_crit 4533 cpu5_top_crit: cpu-crit {
4870 tempe 4534 temperature = <110000>;
4871 hyste 4535 hysteresis = <1000>;
4872 type 4536 type = "critical";
4873 }; 4537 };
4874 }; 4538 };
4875 }; 4539 };
4876 4540
4877 cpu5-bottom-thermal { 4541 cpu5-bottom-thermal {
>> 4542 polling-delay-passive = <0>;
>> 4543 polling-delay = <0>;
4878 thermal-sensors = <&t 4544 thermal-sensors = <&tsens0 8>;
4879 4545
4880 trips { 4546 trips {
4881 cpu5_bottom_a 4547 cpu5_bottom_alert0: trip-point0 {
4882 tempe 4548 temperature = <90000>;
4883 hyste 4549 hysteresis = <2000>;
4884 type 4550 type = "passive";
4885 }; 4551 };
4886 4552
4887 cpu5_bottom_a 4553 cpu5_bottom_alert1: trip-point1 {
4888 tempe 4554 temperature = <95000>;
4889 hyste 4555 hysteresis = <2000>;
4890 type 4556 type = "passive";
4891 }; 4557 };
4892 4558
4893 cpu5_bottom_c 4559 cpu5_bottom_crit: cpu-crit {
4894 tempe 4560 temperature = <110000>;
4895 hyste 4561 hysteresis = <1000>;
4896 type 4562 type = "critical";
4897 }; 4563 };
4898 }; 4564 };
4899 }; 4565 };
4900 4566
4901 cpu6-top-thermal { 4567 cpu6-top-thermal {
>> 4568 polling-delay-passive = <0>;
>> 4569 polling-delay = <0>;
4902 thermal-sensors = <&t 4570 thermal-sensors = <&tsens0 9>;
4903 4571
4904 trips { 4572 trips {
4905 cpu6_top_aler 4573 cpu6_top_alert0: trip-point0 {
4906 tempe 4574 temperature = <90000>;
4907 hyste 4575 hysteresis = <2000>;
4908 type 4576 type = "passive";
4909 }; 4577 };
4910 4578
4911 cpu6_top_aler 4579 cpu6_top_alert1: trip-point1 {
4912 tempe 4580 temperature = <95000>;
4913 hyste 4581 hysteresis = <2000>;
4914 type 4582 type = "passive";
4915 }; 4583 };
4916 4584
4917 cpu6_top_crit 4585 cpu6_top_crit: cpu-crit {
4918 tempe 4586 temperature = <110000>;
4919 hyste 4587 hysteresis = <1000>;
4920 type 4588 type = "critical";
4921 }; 4589 };
4922 }; 4590 };
4923 }; 4591 };
4924 4592
4925 cpu6-bottom-thermal { 4593 cpu6-bottom-thermal {
>> 4594 polling-delay-passive = <0>;
>> 4595 polling-delay = <0>;
4926 thermal-sensors = <&t 4596 thermal-sensors = <&tsens0 10>;
4927 4597
4928 trips { 4598 trips {
4929 cpu6_bottom_a 4599 cpu6_bottom_alert0: trip-point0 {
4930 tempe 4600 temperature = <90000>;
4931 hyste 4601 hysteresis = <2000>;
4932 type 4602 type = "passive";
4933 }; 4603 };
4934 4604
4935 cpu6_bottom_a 4605 cpu6_bottom_alert1: trip-point1 {
4936 tempe 4606 temperature = <95000>;
4937 hyste 4607 hysteresis = <2000>;
4938 type 4608 type = "passive";
4939 }; 4609 };
4940 4610
4941 cpu6_bottom_c 4611 cpu6_bottom_crit: cpu-crit {
4942 tempe 4612 temperature = <110000>;
4943 hyste 4613 hysteresis = <1000>;
4944 type 4614 type = "critical";
4945 }; 4615 };
4946 }; 4616 };
4947 }; 4617 };
4948 4618
4949 cpu7-top-thermal { 4619 cpu7-top-thermal {
>> 4620 polling-delay-passive = <0>;
>> 4621 polling-delay = <0>;
4950 thermal-sensors = <&t 4622 thermal-sensors = <&tsens0 11>;
4951 4623
4952 trips { 4624 trips {
4953 cpu7_top_aler 4625 cpu7_top_alert0: trip-point0 {
4954 tempe 4626 temperature = <90000>;
4955 hyste 4627 hysteresis = <2000>;
4956 type 4628 type = "passive";
4957 }; 4629 };
4958 4630
4959 cpu7_top_aler 4631 cpu7_top_alert1: trip-point1 {
4960 tempe 4632 temperature = <95000>;
4961 hyste 4633 hysteresis = <2000>;
4962 type 4634 type = "passive";
4963 }; 4635 };
4964 4636
4965 cpu7_top_crit 4637 cpu7_top_crit: cpu-crit {
4966 tempe 4638 temperature = <110000>;
4967 hyste 4639 hysteresis = <1000>;
4968 type 4640 type = "critical";
4969 }; 4641 };
4970 }; 4642 };
4971 }; 4643 };
4972 4644
4973 cpu7-middle-thermal { 4645 cpu7-middle-thermal {
>> 4646 polling-delay-passive = <0>;
>> 4647 polling-delay = <0>;
4974 thermal-sensors = <&t 4648 thermal-sensors = <&tsens0 12>;
4975 4649
4976 trips { 4650 trips {
4977 cpu7_middle_a 4651 cpu7_middle_alert0: trip-point0 {
4978 tempe 4652 temperature = <90000>;
4979 hyste 4653 hysteresis = <2000>;
4980 type 4654 type = "passive";
4981 }; 4655 };
4982 4656
4983 cpu7_middle_a 4657 cpu7_middle_alert1: trip-point1 {
4984 tempe 4658 temperature = <95000>;
4985 hyste 4659 hysteresis = <2000>;
4986 type 4660 type = "passive";
4987 }; 4661 };
4988 4662
4989 cpu7_middle_c 4663 cpu7_middle_crit: cpu-crit {
4990 tempe 4664 temperature = <110000>;
4991 hyste 4665 hysteresis = <1000>;
4992 type 4666 type = "critical";
4993 }; 4667 };
4994 }; 4668 };
4995 }; 4669 };
4996 4670
4997 cpu7-bottom-thermal { 4671 cpu7-bottom-thermal {
>> 4672 polling-delay-passive = <0>;
>> 4673 polling-delay = <0>;
4998 thermal-sensors = <&t 4674 thermal-sensors = <&tsens0 13>;
4999 4675
5000 trips { 4676 trips {
5001 cpu7_bottom_a 4677 cpu7_bottom_alert0: trip-point0 {
5002 tempe 4678 temperature = <90000>;
5003 hyste 4679 hysteresis = <2000>;
5004 type 4680 type = "passive";
5005 }; 4681 };
5006 4682
5007 cpu7_bottom_a 4683 cpu7_bottom_alert1: trip-point1 {
5008 tempe 4684 temperature = <95000>;
5009 hyste 4685 hysteresis = <2000>;
5010 type 4686 type = "passive";
5011 }; 4687 };
5012 4688
5013 cpu7_bottom_c 4689 cpu7_bottom_crit: cpu-crit {
5014 tempe 4690 temperature = <110000>;
5015 hyste 4691 hysteresis = <1000>;
5016 type 4692 type = "critical";
5017 }; 4693 };
5018 }; 4694 };
5019 }; 4695 };
5020 4696
5021 gpu-top-thermal { 4697 gpu-top-thermal {
5022 polling-delay-passive 4698 polling-delay-passive = <10>;
5023 !! 4699 polling-delay = <0>;
5024 thermal-sensors = <&t 4700 thermal-sensors = <&tsens0 14>;
5025 4701
5026 cooling-maps { <<
5027 map0 { <<
5028 trip <<
5029 cooli <<
5030 }; <<
5031 }; <<
5032 <<
5033 trips { 4702 trips {
5034 gpu_top_alert !! 4703 thermal-engine-config {
5035 tempe !! 4704 temperature = <125000>;
5036 hyste 4705 hysteresis = <1000>;
5037 type 4706 type = "passive";
5038 }; 4707 };
5039 4708
5040 trip-point1 { !! 4709 thermal-hal-config {
5041 tempe !! 4710 temperature = <125000>;
5042 hyste 4711 hysteresis = <1000>;
5043 type !! 4712 type = "passive";
5044 }; 4713 };
5045 4714
5046 trip-point2 { !! 4715 reset-mon-cfg {
5047 tempe !! 4716 temperature = <115000>;
5048 hyste !! 4717 hysteresis = <5000>;
5049 type !! 4718 type = "passive";
>> 4719 };
>> 4720
>> 4721 gpu0_tj_cfg: tj-cfg {
>> 4722 temperature = <95000>;
>> 4723 hysteresis = <5000>;
>> 4724 type = "passive";
5050 }; 4725 };
5051 }; 4726 };
5052 }; 4727 };
5053 4728
5054 gpu-bottom-thermal { 4729 gpu-bottom-thermal {
5055 polling-delay-passive 4730 polling-delay-passive = <10>;
5056 !! 4731 polling-delay = <0>;
5057 thermal-sensors = <&t 4732 thermal-sensors = <&tsens0 15>;
5058 4733
5059 cooling-maps { <<
5060 map0 { <<
5061 trip <<
5062 cooli <<
5063 }; <<
5064 }; <<
5065 <<
5066 trips { 4734 trips {
5067 gpu_bottom_al !! 4735 thermal-engine-config {
5068 tempe !! 4736 temperature = <125000>;
5069 hyste 4737 hysteresis = <1000>;
5070 type 4738 type = "passive";
5071 }; 4739 };
5072 4740
5073 trip-point1 { !! 4741 thermal-hal-config {
5074 tempe !! 4742 temperature = <125000>;
5075 hyste 4743 hysteresis = <1000>;
5076 type !! 4744 type = "passive";
5077 }; 4745 };
5078 4746
5079 trip-point2 { !! 4747 reset-mon-cfg {
5080 tempe !! 4748 temperature = <115000>;
5081 hyste !! 4749 hysteresis = <5000>;
5082 type !! 4750 type = "passive";
>> 4751 };
>> 4752
>> 4753 gpu1_tj_cfg: tj-cfg {
>> 4754 temperature = <95000>;
>> 4755 hysteresis = <5000>;
>> 4756 type = "passive";
5083 }; 4757 };
5084 }; 4758 };
5085 }; 4759 };
5086 4760
5087 aoss1-thermal { 4761 aoss1-thermal {
>> 4762 polling-delay-passive = <0>;
>> 4763 polling-delay = <0>;
5088 thermal-sensors = <&t 4764 thermal-sensors = <&tsens1 0>;
5089 4765
5090 trips { 4766 trips {
5091 thermal-engin 4767 thermal-engine-config {
5092 tempe 4768 temperature = <125000>;
5093 hyste 4769 hysteresis = <1000>;
5094 type 4770 type = "passive";
5095 }; 4771 };
5096 4772
5097 reset-mon-cfg 4773 reset-mon-cfg {
5098 tempe 4774 temperature = <115000>;
5099 hyste 4775 hysteresis = <5000>;
5100 type 4776 type = "passive";
5101 }; 4777 };
5102 }; 4778 };
5103 }; 4779 };
5104 4780
5105 cpu0-thermal { 4781 cpu0-thermal {
>> 4782 polling-delay-passive = <0>;
>> 4783 polling-delay = <0>;
5106 thermal-sensors = <&t 4784 thermal-sensors = <&tsens1 1>;
5107 4785
5108 trips { 4786 trips {
5109 cpu0_alert0: 4787 cpu0_alert0: trip-point0 {
5110 tempe 4788 temperature = <90000>;
5111 hyste 4789 hysteresis = <2000>;
5112 type 4790 type = "passive";
5113 }; 4791 };
5114 4792
5115 cpu0_alert1: 4793 cpu0_alert1: trip-point1 {
5116 tempe 4794 temperature = <95000>;
5117 hyste 4795 hysteresis = <2000>;
5118 type 4796 type = "passive";
5119 }; 4797 };
5120 4798
5121 cpu0_crit: cp 4799 cpu0_crit: cpu-crit {
5122 tempe 4800 temperature = <110000>;
5123 hyste 4801 hysteresis = <1000>;
5124 type 4802 type = "critical";
5125 }; 4803 };
5126 }; 4804 };
5127 }; 4805 };
5128 4806
5129 cpu1-thermal { 4807 cpu1-thermal {
>> 4808 polling-delay-passive = <0>;
>> 4809 polling-delay = <0>;
5130 thermal-sensors = <&t 4810 thermal-sensors = <&tsens1 2>;
5131 4811
5132 trips { 4812 trips {
5133 cpu1_alert0: 4813 cpu1_alert0: trip-point0 {
5134 tempe 4814 temperature = <90000>;
5135 hyste 4815 hysteresis = <2000>;
5136 type 4816 type = "passive";
5137 }; 4817 };
5138 4818
5139 cpu1_alert1: 4819 cpu1_alert1: trip-point1 {
5140 tempe 4820 temperature = <95000>;
5141 hyste 4821 hysteresis = <2000>;
5142 type 4822 type = "passive";
5143 }; 4823 };
5144 4824
5145 cpu1_crit: cp 4825 cpu1_crit: cpu-crit {
5146 tempe 4826 temperature = <110000>;
5147 hyste 4827 hysteresis = <1000>;
5148 type 4828 type = "critical";
5149 }; 4829 };
5150 }; 4830 };
5151 }; 4831 };
5152 4832
5153 cpu2-thermal { 4833 cpu2-thermal {
>> 4834 polling-delay-passive = <0>;
>> 4835 polling-delay = <0>;
5154 thermal-sensors = <&t 4836 thermal-sensors = <&tsens1 3>;
5155 4837
5156 trips { 4838 trips {
5157 cpu2_alert0: 4839 cpu2_alert0: trip-point0 {
5158 tempe 4840 temperature = <90000>;
5159 hyste 4841 hysteresis = <2000>;
5160 type 4842 type = "passive";
5161 }; 4843 };
5162 4844
5163 cpu2_alert1: 4845 cpu2_alert1: trip-point1 {
5164 tempe 4846 temperature = <95000>;
5165 hyste 4847 hysteresis = <2000>;
5166 type 4848 type = "passive";
5167 }; 4849 };
5168 4850
5169 cpu2_crit: cp 4851 cpu2_crit: cpu-crit {
5170 tempe 4852 temperature = <110000>;
5171 hyste 4853 hysteresis = <1000>;
5172 type 4854 type = "critical";
5173 }; 4855 };
5174 }; 4856 };
5175 }; 4857 };
5176 4858
5177 cpu3-thermal { 4859 cpu3-thermal {
>> 4860 polling-delay-passive = <0>;
>> 4861 polling-delay = <0>;
5178 thermal-sensors = <&t 4862 thermal-sensors = <&tsens1 4>;
5179 4863
5180 trips { 4864 trips {
5181 cpu3_alert0: 4865 cpu3_alert0: trip-point0 {
5182 tempe 4866 temperature = <90000>;
5183 hyste 4867 hysteresis = <2000>;
5184 type 4868 type = "passive";
5185 }; 4869 };
5186 4870
5187 cpu3_alert1: 4871 cpu3_alert1: trip-point1 {
5188 tempe 4872 temperature = <95000>;
5189 hyste 4873 hysteresis = <2000>;
5190 type 4874 type = "passive";
5191 }; 4875 };
5192 4876
5193 cpu3_crit: cp 4877 cpu3_crit: cpu-crit {
5194 tempe 4878 temperature = <110000>;
5195 hyste 4879 hysteresis = <1000>;
5196 type 4880 type = "critical";
5197 }; 4881 };
5198 }; 4882 };
5199 }; 4883 };
5200 4884
5201 cdsp0-thermal { 4885 cdsp0-thermal {
5202 polling-delay-passive 4886 polling-delay-passive = <10>;
5203 !! 4887 polling-delay = <0>;
5204 thermal-sensors = <&t 4888 thermal-sensors = <&tsens1 5>;
5205 4889
5206 trips { 4890 trips {
5207 thermal-engin 4891 thermal-engine-config {
5208 tempe 4892 temperature = <125000>;
5209 hyste 4893 hysteresis = <1000>;
5210 type 4894 type = "passive";
5211 }; 4895 };
5212 4896
5213 thermal-hal-c 4897 thermal-hal-config {
5214 tempe 4898 temperature = <125000>;
5215 hyste 4899 hysteresis = <1000>;
5216 type 4900 type = "passive";
5217 }; 4901 };
5218 4902
5219 reset-mon-cfg 4903 reset-mon-cfg {
5220 tempe 4904 temperature = <115000>;
5221 hyste 4905 hysteresis = <5000>;
5222 type 4906 type = "passive";
5223 }; 4907 };
5224 4908
5225 cdsp_0_config 4909 cdsp_0_config: junction-config {
5226 tempe 4910 temperature = <95000>;
5227 hyste 4911 hysteresis = <5000>;
5228 type 4912 type = "passive";
5229 }; 4913 };
5230 }; 4914 };
5231 }; 4915 };
5232 4916
5233 cdsp1-thermal { 4917 cdsp1-thermal {
5234 polling-delay-passive 4918 polling-delay-passive = <10>;
5235 !! 4919 polling-delay = <0>;
5236 thermal-sensors = <&t 4920 thermal-sensors = <&tsens1 6>;
5237 4921
5238 trips { 4922 trips {
5239 thermal-engin 4923 thermal-engine-config {
5240 tempe 4924 temperature = <125000>;
5241 hyste 4925 hysteresis = <1000>;
5242 type 4926 type = "passive";
5243 }; 4927 };
5244 4928
5245 thermal-hal-c 4929 thermal-hal-config {
5246 tempe 4930 temperature = <125000>;
5247 hyste 4931 hysteresis = <1000>;
5248 type 4932 type = "passive";
5249 }; 4933 };
5250 4934
5251 reset-mon-cfg 4935 reset-mon-cfg {
5252 tempe 4936 temperature = <115000>;
5253 hyste 4937 hysteresis = <5000>;
5254 type 4938 type = "passive";
5255 }; 4939 };
5256 4940
5257 cdsp_1_config 4941 cdsp_1_config: junction-config {
5258 tempe 4942 temperature = <95000>;
5259 hyste 4943 hysteresis = <5000>;
5260 type 4944 type = "passive";
5261 }; 4945 };
5262 }; 4946 };
5263 }; 4947 };
5264 4948
5265 cdsp2-thermal { 4949 cdsp2-thermal {
5266 polling-delay-passive 4950 polling-delay-passive = <10>;
5267 !! 4951 polling-delay = <0>;
5268 thermal-sensors = <&t 4952 thermal-sensors = <&tsens1 7>;
5269 4953
5270 trips { 4954 trips {
5271 thermal-engin 4955 thermal-engine-config {
5272 tempe 4956 temperature = <125000>;
5273 hyste 4957 hysteresis = <1000>;
5274 type 4958 type = "passive";
5275 }; 4959 };
5276 4960
5277 thermal-hal-c 4961 thermal-hal-config {
5278 tempe 4962 temperature = <125000>;
5279 hyste 4963 hysteresis = <1000>;
5280 type 4964 type = "passive";
5281 }; 4965 };
5282 4966
5283 reset-mon-cfg 4967 reset-mon-cfg {
5284 tempe 4968 temperature = <115000>;
5285 hyste 4969 hysteresis = <5000>;
5286 type 4970 type = "passive";
5287 }; 4971 };
5288 4972
5289 cdsp_2_config 4973 cdsp_2_config: junction-config {
5290 tempe 4974 temperature = <95000>;
5291 hyste 4975 hysteresis = <5000>;
5292 type 4976 type = "passive";
5293 }; 4977 };
5294 }; 4978 };
5295 }; 4979 };
5296 4980
5297 video-thermal { 4981 video-thermal {
>> 4982 polling-delay-passive = <0>;
>> 4983 polling-delay = <0>;
5298 thermal-sensors = <&t 4984 thermal-sensors = <&tsens1 8>;
5299 4985
5300 trips { 4986 trips {
5301 thermal-engin 4987 thermal-engine-config {
5302 tempe 4988 temperature = <125000>;
5303 hyste 4989 hysteresis = <1000>;
5304 type 4990 type = "passive";
5305 }; 4991 };
5306 4992
5307 reset-mon-cfg 4993 reset-mon-cfg {
5308 tempe 4994 temperature = <115000>;
5309 hyste 4995 hysteresis = <5000>;
5310 type 4996 type = "passive";
5311 }; 4997 };
5312 }; 4998 };
5313 }; 4999 };
5314 5000
5315 mem-thermal { 5001 mem-thermal {
5316 polling-delay-passive 5002 polling-delay-passive = <10>;
5317 !! 5003 polling-delay = <0>;
5318 thermal-sensors = <&t 5004 thermal-sensors = <&tsens1 9>;
5319 5005
5320 trips { 5006 trips {
5321 thermal-engin 5007 thermal-engine-config {
5322 tempe 5008 temperature = <125000>;
5323 hyste 5009 hysteresis = <1000>;
5324 type 5010 type = "passive";
5325 }; 5011 };
5326 5012
5327 ddr_config0: 5013 ddr_config0: ddr0-config {
5328 tempe 5014 temperature = <90000>;
5329 hyste 5015 hysteresis = <5000>;
5330 type 5016 type = "passive";
5331 }; 5017 };
5332 5018
5333 reset-mon-cfg 5019 reset-mon-cfg {
5334 tempe 5020 temperature = <115000>;
5335 hyste 5021 hysteresis = <5000>;
5336 type 5022 type = "passive";
5337 }; 5023 };
5338 }; 5024 };
5339 }; 5025 };
5340 5026
5341 modem0-thermal { 5027 modem0-thermal {
>> 5028 polling-delay-passive = <0>;
>> 5029 polling-delay = <0>;
5342 thermal-sensors = <&t 5030 thermal-sensors = <&tsens1 10>;
5343 5031
5344 trips { 5032 trips {
5345 thermal-engin 5033 thermal-engine-config {
5346 tempe 5034 temperature = <125000>;
5347 hyste 5035 hysteresis = <1000>;
5348 type 5036 type = "passive";
5349 }; 5037 };
5350 5038
5351 mdmss0_config 5039 mdmss0_config0: mdmss0-config0 {
5352 tempe 5040 temperature = <102000>;
5353 hyste 5041 hysteresis = <3000>;
5354 type 5042 type = "passive";
5355 }; 5043 };
5356 5044
5357 mdmss0_config 5045 mdmss0_config1: mdmss0-config1 {
5358 tempe 5046 temperature = <105000>;
5359 hyste 5047 hysteresis = <3000>;
5360 type 5048 type = "passive";
5361 }; 5049 };
5362 5050
5363 reset-mon-cfg 5051 reset-mon-cfg {
5364 tempe 5052 temperature = <115000>;
5365 hyste 5053 hysteresis = <5000>;
5366 type 5054 type = "passive";
5367 }; 5055 };
5368 }; 5056 };
5369 }; 5057 };
5370 5058
5371 modem1-thermal { 5059 modem1-thermal {
>> 5060 polling-delay-passive = <0>;
>> 5061 polling-delay = <0>;
5372 thermal-sensors = <&t 5062 thermal-sensors = <&tsens1 11>;
5373 5063
5374 trips { 5064 trips {
5375 thermal-engin 5065 thermal-engine-config {
5376 tempe 5066 temperature = <125000>;
5377 hyste 5067 hysteresis = <1000>;
5378 type 5068 type = "passive";
5379 }; 5069 };
5380 5070
5381 mdmss1_config 5071 mdmss1_config0: mdmss1-config0 {
5382 tempe 5072 temperature = <102000>;
5383 hyste 5073 hysteresis = <3000>;
5384 type 5074 type = "passive";
5385 }; 5075 };
5386 5076
5387 mdmss1_config 5077 mdmss1_config1: mdmss1-config1 {
5388 tempe 5078 temperature = <105000>;
5389 hyste 5079 hysteresis = <3000>;
5390 type 5080 type = "passive";
5391 }; 5081 };
5392 5082
5393 reset-mon-cfg 5083 reset-mon-cfg {
5394 tempe 5084 temperature = <115000>;
5395 hyste 5085 hysteresis = <5000>;
5396 type 5086 type = "passive";
5397 }; 5087 };
5398 }; 5088 };
5399 }; 5089 };
5400 5090
5401 modem2-thermal { 5091 modem2-thermal {
>> 5092 polling-delay-passive = <0>;
>> 5093 polling-delay = <0>;
5402 thermal-sensors = <&t 5094 thermal-sensors = <&tsens1 12>;
5403 5095
5404 trips { 5096 trips {
5405 thermal-engin 5097 thermal-engine-config {
5406 tempe 5098 temperature = <125000>;
5407 hyste 5099 hysteresis = <1000>;
5408 type 5100 type = "passive";
5409 }; 5101 };
5410 5102
5411 mdmss2_config 5103 mdmss2_config0: mdmss2-config0 {
5412 tempe 5104 temperature = <102000>;
5413 hyste 5105 hysteresis = <3000>;
5414 type 5106 type = "passive";
5415 }; 5107 };
5416 5108
5417 mdmss2_config 5109 mdmss2_config1: mdmss2-config1 {
5418 tempe 5110 temperature = <105000>;
5419 hyste 5111 hysteresis = <3000>;
5420 type 5112 type = "passive";
5421 }; 5113 };
5422 5114
5423 reset-mon-cfg 5115 reset-mon-cfg {
5424 tempe 5116 temperature = <115000>;
5425 hyste 5117 hysteresis = <5000>;
5426 type 5118 type = "passive";
5427 }; 5119 };
5428 }; 5120 };
5429 }; 5121 };
5430 5122
5431 modem3-thermal { 5123 modem3-thermal {
>> 5124 polling-delay-passive = <0>;
>> 5125 polling-delay = <0>;
5432 thermal-sensors = <&t 5126 thermal-sensors = <&tsens1 13>;
5433 5127
5434 trips { 5128 trips {
5435 thermal-engin 5129 thermal-engine-config {
5436 tempe 5130 temperature = <125000>;
5437 hyste 5131 hysteresis = <1000>;
5438 type 5132 type = "passive";
5439 }; 5133 };
5440 5134
5441 mdmss3_config 5135 mdmss3_config0: mdmss3-config0 {
5442 tempe 5136 temperature = <102000>;
5443 hyste 5137 hysteresis = <3000>;
5444 type 5138 type = "passive";
5445 }; 5139 };
5446 5140
5447 mdmss3_config 5141 mdmss3_config1: mdmss3-config1 {
5448 tempe 5142 temperature = <105000>;
5449 hyste 5143 hysteresis = <3000>;
5450 type 5144 type = "passive";
5451 }; 5145 };
5452 5146
5453 reset-mon-cfg 5147 reset-mon-cfg {
5454 tempe 5148 temperature = <115000>;
5455 hyste 5149 hysteresis = <5000>;
5456 type 5150 type = "passive";
5457 }; 5151 };
5458 }; 5152 };
5459 }; 5153 };
5460 5154
5461 camera0-thermal { 5155 camera0-thermal {
>> 5156 polling-delay-passive = <0>;
>> 5157 polling-delay = <0>;
5462 thermal-sensors = <&t 5158 thermal-sensors = <&tsens1 14>;
5463 5159
5464 trips { 5160 trips {
5465 thermal-engin 5161 thermal-engine-config {
5466 tempe 5162 temperature = <125000>;
5467 hyste 5163 hysteresis = <1000>;
5468 type 5164 type = "passive";
5469 }; 5165 };
5470 5166
5471 reset-mon-cfg 5167 reset-mon-cfg {
5472 tempe 5168 temperature = <115000>;
5473 hyste 5169 hysteresis = <5000>;
5474 type 5170 type = "passive";
5475 }; 5171 };
5476 }; 5172 };
5477 }; 5173 };
5478 5174
5479 camera1-thermal { 5175 camera1-thermal {
>> 5176 polling-delay-passive = <0>;
>> 5177 polling-delay = <0>;
5480 thermal-sensors = <&t 5178 thermal-sensors = <&tsens1 15>;
5481 5179
5482 trips { 5180 trips {
5483 thermal-engin 5181 thermal-engine-config {
5484 tempe 5182 temperature = <125000>;
5485 hyste 5183 hysteresis = <1000>;
5486 type 5184 type = "passive";
5487 }; 5185 };
5488 5186
5489 reset-mon-cfg 5187 reset-mon-cfg {
5490 tempe 5188 temperature = <115000>;
5491 hyste 5189 hysteresis = <5000>;
5492 type 5190 type = "passive";
5493 }; 5191 };
5494 }; 5192 };
5495 }; 5193 };
5496 }; 5194 };
5497 5195
5498 timer { 5196 timer {
5499 compatible = "arm,armv8-timer 5197 compatible = "arm,armv8-timer";
5500 interrupts = <GIC_PPI 13 (GIC 5198 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5501 <GIC_PPI 14 (GIC 5199 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5502 <GIC_PPI 11 (GIC 5200 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5503 <GIC_PPI 10 (GIC 5201 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
5504 clock-frequency = <19200000>; 5202 clock-frequency = <19200000>;
5505 }; 5203 };
5506 }; 5204 };
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