1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * Copyright (c) 2021, Linaro Limited 3 * Copyright (c) 2021, Linaro Limited
4 */ 4 */
5 5
6 #include <dt-bindings/interrupt-controller/arm 6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-sm8450.h> 7 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
8 #include <dt-bindings/clock/qcom,rpmh.h> 8 #include <dt-bindings/clock/qcom,rpmh.h>
9 #include <dt-bindings/clock/qcom,sm8450-camcc. 9 #include <dt-bindings/clock/qcom,sm8450-camcc.h>
10 #include <dt-bindings/clock/qcom,sm8450-dispcc 10 #include <dt-bindings/clock/qcom,sm8450-dispcc.h>
11 #include <dt-bindings/clock/qcom,sm8450-gpucc. <<
12 #include <dt-bindings/clock/qcom,sm8450-videoc 11 #include <dt-bindings/clock/qcom,sm8450-videocc.h>
13 #include <dt-bindings/dma/qcom-gpi.h> 12 #include <dt-bindings/dma/qcom-gpi.h>
14 #include <dt-bindings/firmware/qcom,scm.h> <<
15 #include <dt-bindings/gpio/gpio.h> 13 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/mailbox/qcom-ipcc.h> 14 #include <dt-bindings/mailbox/qcom-ipcc.h>
17 #include <dt-bindings/phy/phy-qcom-qmp.h> 15 #include <dt-bindings/phy/phy-qcom-qmp.h>
18 #include <dt-bindings/power/qcom,rpmhpd.h> 16 #include <dt-bindings/power/qcom,rpmhpd.h>
19 #include <dt-bindings/power/qcom-rpmpd.h> 17 #include <dt-bindings/power/qcom-rpmpd.h>
20 #include <dt-bindings/interconnect/qcom,icc.h> 18 #include <dt-bindings/interconnect/qcom,icc.h>
21 #include <dt-bindings/interconnect/qcom,sm8450 19 #include <dt-bindings/interconnect/qcom,sm8450.h>
22 #include <dt-bindings/reset/qcom,sm8450-gpucc. <<
23 #include <dt-bindings/soc/qcom,gpr.h> 20 #include <dt-bindings/soc/qcom,gpr.h>
24 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 21 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
25 #include <dt-bindings/sound/qcom,q6dsp-lpass-p 22 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
26 #include <dt-bindings/thermal/thermal.h> 23 #include <dt-bindings/thermal/thermal.h>
27 24
28 / { 25 / {
29 interrupt-parent = <&intc>; 26 interrupt-parent = <&intc>;
30 27
31 #address-cells = <2>; 28 #address-cells = <2>;
32 #size-cells = <2>; 29 #size-cells = <2>;
33 30
34 chosen { }; 31 chosen { };
35 32
36 clocks { 33 clocks {
37 xo_board: xo-board { 34 xo_board: xo-board {
38 compatible = "fixed-cl 35 compatible = "fixed-clock";
39 #clock-cells = <0>; 36 #clock-cells = <0>;
40 clock-frequency = <768 37 clock-frequency = <76800000>;
41 }; 38 };
42 39
43 sleep_clk: sleep-clk { 40 sleep_clk: sleep-clk {
44 compatible = "fixed-cl 41 compatible = "fixed-clock";
45 #clock-cells = <0>; 42 #clock-cells = <0>;
46 clock-frequency = <320 43 clock-frequency = <32000>;
47 }; 44 };
48 }; 45 };
49 46
50 cpus { 47 cpus {
51 #address-cells = <2>; 48 #address-cells = <2>;
52 #size-cells = <0>; 49 #size-cells = <0>;
53 50
54 CPU0: cpu@0 { 51 CPU0: cpu@0 {
55 device_type = "cpu"; 52 device_type = "cpu";
56 compatible = "qcom,kry 53 compatible = "qcom,kryo780";
57 reg = <0x0 0x0>; 54 reg = <0x0 0x0>;
58 enable-method = "psci" 55 enable-method = "psci";
59 next-level-cache = <&L 56 next-level-cache = <&L2_0>;
60 power-domains = <&CPU_ 57 power-domains = <&CPU_PD0>;
61 power-domain-names = " 58 power-domain-names = "psci";
62 qcom,freq-domain = <&c 59 qcom,freq-domain = <&cpufreq_hw 0>;
63 #cooling-cells = <2>; 60 #cooling-cells = <2>;
64 clocks = <&cpufreq_hw 61 clocks = <&cpufreq_hw 0>;
65 L2_0: l2-cache { 62 L2_0: l2-cache {
66 compatible = " 63 compatible = "cache";
67 cache-level = 64 cache-level = <2>;
68 cache-unified; 65 cache-unified;
69 next-level-cac 66 next-level-cache = <&L3_0>;
70 L3_0: l3-cache 67 L3_0: l3-cache {
71 compat 68 compatible = "cache";
72 cache- 69 cache-level = <3>;
73 cache- 70 cache-unified;
74 }; 71 };
75 }; 72 };
76 }; 73 };
77 74
78 CPU1: cpu@100 { 75 CPU1: cpu@100 {
79 device_type = "cpu"; 76 device_type = "cpu";
80 compatible = "qcom,kry 77 compatible = "qcom,kryo780";
81 reg = <0x0 0x100>; 78 reg = <0x0 0x100>;
82 enable-method = "psci" 79 enable-method = "psci";
83 next-level-cache = <&L 80 next-level-cache = <&L2_100>;
84 power-domains = <&CPU_ 81 power-domains = <&CPU_PD1>;
85 power-domain-names = " 82 power-domain-names = "psci";
86 qcom,freq-domain = <&c 83 qcom,freq-domain = <&cpufreq_hw 0>;
87 #cooling-cells = <2>; 84 #cooling-cells = <2>;
88 clocks = <&cpufreq_hw 85 clocks = <&cpufreq_hw 0>;
89 L2_100: l2-cache { 86 L2_100: l2-cache {
90 compatible = " 87 compatible = "cache";
91 cache-level = 88 cache-level = <2>;
92 cache-unified; 89 cache-unified;
93 next-level-cac 90 next-level-cache = <&L3_0>;
94 }; 91 };
95 }; 92 };
96 93
97 CPU2: cpu@200 { 94 CPU2: cpu@200 {
98 device_type = "cpu"; 95 device_type = "cpu";
99 compatible = "qcom,kry 96 compatible = "qcom,kryo780";
100 reg = <0x0 0x200>; 97 reg = <0x0 0x200>;
101 enable-method = "psci" 98 enable-method = "psci";
102 next-level-cache = <&L 99 next-level-cache = <&L2_200>;
103 power-domains = <&CPU_ 100 power-domains = <&CPU_PD2>;
104 power-domain-names = " 101 power-domain-names = "psci";
105 qcom,freq-domain = <&c 102 qcom,freq-domain = <&cpufreq_hw 0>;
106 #cooling-cells = <2>; 103 #cooling-cells = <2>;
107 clocks = <&cpufreq_hw 104 clocks = <&cpufreq_hw 0>;
108 L2_200: l2-cache { 105 L2_200: l2-cache {
109 compatible = " 106 compatible = "cache";
110 cache-level = 107 cache-level = <2>;
111 cache-unified; 108 cache-unified;
112 next-level-cac 109 next-level-cache = <&L3_0>;
113 }; 110 };
114 }; 111 };
115 112
116 CPU3: cpu@300 { 113 CPU3: cpu@300 {
117 device_type = "cpu"; 114 device_type = "cpu";
118 compatible = "qcom,kry 115 compatible = "qcom,kryo780";
119 reg = <0x0 0x300>; 116 reg = <0x0 0x300>;
120 enable-method = "psci" 117 enable-method = "psci";
121 next-level-cache = <&L 118 next-level-cache = <&L2_300>;
122 power-domains = <&CPU_ 119 power-domains = <&CPU_PD3>;
123 power-domain-names = " 120 power-domain-names = "psci";
124 qcom,freq-domain = <&c 121 qcom,freq-domain = <&cpufreq_hw 0>;
125 #cooling-cells = <2>; 122 #cooling-cells = <2>;
126 clocks = <&cpufreq_hw 123 clocks = <&cpufreq_hw 0>;
127 L2_300: l2-cache { 124 L2_300: l2-cache {
128 compatible = " 125 compatible = "cache";
129 cache-level = 126 cache-level = <2>;
130 cache-unified; 127 cache-unified;
131 next-level-cac 128 next-level-cache = <&L3_0>;
132 }; 129 };
133 }; 130 };
134 131
135 CPU4: cpu@400 { 132 CPU4: cpu@400 {
136 device_type = "cpu"; 133 device_type = "cpu";
137 compatible = "qcom,kry 134 compatible = "qcom,kryo780";
138 reg = <0x0 0x400>; 135 reg = <0x0 0x400>;
139 enable-method = "psci" 136 enable-method = "psci";
140 next-level-cache = <&L 137 next-level-cache = <&L2_400>;
141 power-domains = <&CPU_ 138 power-domains = <&CPU_PD4>;
142 power-domain-names = " 139 power-domain-names = "psci";
143 qcom,freq-domain = <&c 140 qcom,freq-domain = <&cpufreq_hw 1>;
144 #cooling-cells = <2>; 141 #cooling-cells = <2>;
145 clocks = <&cpufreq_hw 142 clocks = <&cpufreq_hw 1>;
146 L2_400: l2-cache { 143 L2_400: l2-cache {
147 compatible = " 144 compatible = "cache";
148 cache-level = 145 cache-level = <2>;
149 cache-unified; 146 cache-unified;
150 next-level-cac 147 next-level-cache = <&L3_0>;
151 }; 148 };
152 }; 149 };
153 150
154 CPU5: cpu@500 { 151 CPU5: cpu@500 {
155 device_type = "cpu"; 152 device_type = "cpu";
156 compatible = "qcom,kry 153 compatible = "qcom,kryo780";
157 reg = <0x0 0x500>; 154 reg = <0x0 0x500>;
158 enable-method = "psci" 155 enable-method = "psci";
159 next-level-cache = <&L 156 next-level-cache = <&L2_500>;
160 power-domains = <&CPU_ 157 power-domains = <&CPU_PD5>;
161 power-domain-names = " 158 power-domain-names = "psci";
162 qcom,freq-domain = <&c 159 qcom,freq-domain = <&cpufreq_hw 1>;
163 #cooling-cells = <2>; 160 #cooling-cells = <2>;
164 clocks = <&cpufreq_hw 161 clocks = <&cpufreq_hw 1>;
165 L2_500: l2-cache { 162 L2_500: l2-cache {
166 compatible = " 163 compatible = "cache";
167 cache-level = 164 cache-level = <2>;
168 cache-unified; 165 cache-unified;
169 next-level-cac 166 next-level-cache = <&L3_0>;
170 }; 167 };
171 }; 168 };
172 169
173 CPU6: cpu@600 { 170 CPU6: cpu@600 {
174 device_type = "cpu"; 171 device_type = "cpu";
175 compatible = "qcom,kry 172 compatible = "qcom,kryo780";
176 reg = <0x0 0x600>; 173 reg = <0x0 0x600>;
177 enable-method = "psci" 174 enable-method = "psci";
178 next-level-cache = <&L 175 next-level-cache = <&L2_600>;
179 power-domains = <&CPU_ 176 power-domains = <&CPU_PD6>;
180 power-domain-names = " 177 power-domain-names = "psci";
181 qcom,freq-domain = <&c 178 qcom,freq-domain = <&cpufreq_hw 1>;
182 #cooling-cells = <2>; 179 #cooling-cells = <2>;
183 clocks = <&cpufreq_hw 180 clocks = <&cpufreq_hw 1>;
184 L2_600: l2-cache { 181 L2_600: l2-cache {
185 compatible = " 182 compatible = "cache";
186 cache-level = 183 cache-level = <2>;
187 cache-unified; 184 cache-unified;
188 next-level-cac 185 next-level-cache = <&L3_0>;
189 }; 186 };
190 }; 187 };
191 188
192 CPU7: cpu@700 { 189 CPU7: cpu@700 {
193 device_type = "cpu"; 190 device_type = "cpu";
194 compatible = "qcom,kry 191 compatible = "qcom,kryo780";
195 reg = <0x0 0x700>; 192 reg = <0x0 0x700>;
196 enable-method = "psci" 193 enable-method = "psci";
197 next-level-cache = <&L 194 next-level-cache = <&L2_700>;
198 power-domains = <&CPU_ 195 power-domains = <&CPU_PD7>;
199 power-domain-names = " 196 power-domain-names = "psci";
200 qcom,freq-domain = <&c 197 qcom,freq-domain = <&cpufreq_hw 2>;
201 #cooling-cells = <2>; 198 #cooling-cells = <2>;
202 clocks = <&cpufreq_hw 199 clocks = <&cpufreq_hw 2>;
203 L2_700: l2-cache { 200 L2_700: l2-cache {
204 compatible = " 201 compatible = "cache";
205 cache-level = 202 cache-level = <2>;
206 cache-unified; 203 cache-unified;
207 next-level-cac 204 next-level-cache = <&L3_0>;
208 }; 205 };
209 }; 206 };
210 207
211 cpu-map { 208 cpu-map {
212 cluster0 { 209 cluster0 {
213 core0 { 210 core0 {
214 cpu = 211 cpu = <&CPU0>;
215 }; 212 };
216 213
217 core1 { 214 core1 {
218 cpu = 215 cpu = <&CPU1>;
219 }; 216 };
220 217
221 core2 { 218 core2 {
222 cpu = 219 cpu = <&CPU2>;
223 }; 220 };
224 221
225 core3 { 222 core3 {
226 cpu = 223 cpu = <&CPU3>;
227 }; 224 };
228 225
229 core4 { 226 core4 {
230 cpu = 227 cpu = <&CPU4>;
231 }; 228 };
232 229
233 core5 { 230 core5 {
234 cpu = 231 cpu = <&CPU5>;
235 }; 232 };
236 233
237 core6 { 234 core6 {
238 cpu = 235 cpu = <&CPU6>;
239 }; 236 };
240 237
241 core7 { 238 core7 {
242 cpu = 239 cpu = <&CPU7>;
243 }; 240 };
244 }; 241 };
245 }; 242 };
246 243
247 idle-states { 244 idle-states {
248 entry-method = "psci"; 245 entry-method = "psci";
249 246
250 LITTLE_CPU_SLEEP_0: cp 247 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
251 compatible = " 248 compatible = "arm,idle-state";
252 idle-state-nam 249 idle-state-name = "silver-rail-power-collapse";
253 arm,psci-suspe 250 arm,psci-suspend-param = <0x40000004>;
254 entry-latency- 251 entry-latency-us = <800>;
255 exit-latency-u 252 exit-latency-us = <750>;
256 min-residency- 253 min-residency-us = <4090>;
257 local-timer-st 254 local-timer-stop;
258 }; 255 };
259 256
260 BIG_CPU_SLEEP_0: cpu-s 257 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
261 compatible = " 258 compatible = "arm,idle-state";
262 idle-state-nam 259 idle-state-name = "gold-rail-power-collapse";
263 arm,psci-suspe 260 arm,psci-suspend-param = <0x40000004>;
264 entry-latency- 261 entry-latency-us = <600>;
265 exit-latency-u 262 exit-latency-us = <1550>;
266 min-residency- 263 min-residency-us = <4791>;
267 local-timer-st 264 local-timer-stop;
268 }; 265 };
269 }; 266 };
270 267
271 domain-idle-states { 268 domain-idle-states {
272 CLUSTER_SLEEP_0: clust 269 CLUSTER_SLEEP_0: cluster-sleep-0 {
273 compatible = " 270 compatible = "domain-idle-state";
274 arm,psci-suspe 271 arm,psci-suspend-param = <0x41000044>;
275 entry-latency- 272 entry-latency-us = <1050>;
276 exit-latency-u 273 exit-latency-us = <2500>;
277 min-residency- 274 min-residency-us = <5309>;
278 }; 275 };
279 276
280 CLUSTER_SLEEP_1: clust 277 CLUSTER_SLEEP_1: cluster-sleep-1 {
281 compatible = " 278 compatible = "domain-idle-state";
282 arm,psci-suspe 279 arm,psci-suspend-param = <0x4100c344>;
283 entry-latency- 280 entry-latency-us = <2700>;
284 exit-latency-u 281 exit-latency-us = <3500>;
285 min-residency- 282 min-residency-us = <13959>;
286 }; 283 };
287 }; 284 };
288 }; 285 };
289 286
290 firmware { 287 firmware {
291 scm: scm { 288 scm: scm {
292 compatible = "qcom,scm 289 compatible = "qcom,scm-sm8450", "qcom,scm";
293 qcom,dload-mode = <&tc 290 qcom,dload-mode = <&tcsr 0x13000>;
294 interconnects = <&aggr 291 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
295 #reset-cells = <1>; 292 #reset-cells = <1>;
296 }; 293 };
297 }; 294 };
298 295
299 clk_virt: interconnect-0 { 296 clk_virt: interconnect-0 {
300 compatible = "qcom,sm8450-clk- 297 compatible = "qcom,sm8450-clk-virt";
301 #interconnect-cells = <2>; 298 #interconnect-cells = <2>;
302 qcom,bcm-voters = <&apps_bcm_v 299 qcom,bcm-voters = <&apps_bcm_voter>;
303 }; 300 };
304 301
305 mc_virt: interconnect-1 { 302 mc_virt: interconnect-1 {
306 compatible = "qcom,sm8450-mc-v 303 compatible = "qcom,sm8450-mc-virt";
307 #interconnect-cells = <2>; 304 #interconnect-cells = <2>;
308 qcom,bcm-voters = <&apps_bcm_v 305 qcom,bcm-voters = <&apps_bcm_voter>;
309 }; 306 };
310 307
311 memory@a0000000 { 308 memory@a0000000 {
312 device_type = "memory"; 309 device_type = "memory";
313 /* We expect the bootloader to 310 /* We expect the bootloader to fill in the size */
314 reg = <0x0 0xa0000000 0x0 0x0> 311 reg = <0x0 0xa0000000 0x0 0x0>;
315 }; 312 };
316 313
317 pmu { 314 pmu {
318 compatible = "arm,armv8-pmuv3" 315 compatible = "arm,armv8-pmuv3";
319 interrupts = <GIC_PPI 7 IRQ_TY 316 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
320 }; 317 };
321 318
322 psci { 319 psci {
323 compatible = "arm,psci-1.0"; 320 compatible = "arm,psci-1.0";
324 method = "smc"; 321 method = "smc";
325 322
326 CPU_PD0: power-domain-cpu0 { 323 CPU_PD0: power-domain-cpu0 {
327 #power-domain-cells = 324 #power-domain-cells = <0>;
328 power-domains = <&CLUS 325 power-domains = <&CLUSTER_PD>;
329 domain-idle-states = < 326 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
330 }; 327 };
331 328
332 CPU_PD1: power-domain-cpu1 { 329 CPU_PD1: power-domain-cpu1 {
333 #power-domain-cells = 330 #power-domain-cells = <0>;
334 power-domains = <&CLUS 331 power-domains = <&CLUSTER_PD>;
335 domain-idle-states = < 332 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
336 }; 333 };
337 334
338 CPU_PD2: power-domain-cpu2 { 335 CPU_PD2: power-domain-cpu2 {
339 #power-domain-cells = 336 #power-domain-cells = <0>;
340 power-domains = <&CLUS 337 power-domains = <&CLUSTER_PD>;
341 domain-idle-states = < 338 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
342 }; 339 };
343 340
344 CPU_PD3: power-domain-cpu3 { 341 CPU_PD3: power-domain-cpu3 {
345 #power-domain-cells = 342 #power-domain-cells = <0>;
346 power-domains = <&CLUS 343 power-domains = <&CLUSTER_PD>;
347 domain-idle-states = < 344 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
348 }; 345 };
349 346
350 CPU_PD4: power-domain-cpu4 { 347 CPU_PD4: power-domain-cpu4 {
351 #power-domain-cells = 348 #power-domain-cells = <0>;
352 power-domains = <&CLUS 349 power-domains = <&CLUSTER_PD>;
353 domain-idle-states = < 350 domain-idle-states = <&BIG_CPU_SLEEP_0>;
354 }; 351 };
355 352
356 CPU_PD5: power-domain-cpu5 { 353 CPU_PD5: power-domain-cpu5 {
357 #power-domain-cells = 354 #power-domain-cells = <0>;
358 power-domains = <&CLUS 355 power-domains = <&CLUSTER_PD>;
359 domain-idle-states = < 356 domain-idle-states = <&BIG_CPU_SLEEP_0>;
360 }; 357 };
361 358
362 CPU_PD6: power-domain-cpu6 { 359 CPU_PD6: power-domain-cpu6 {
363 #power-domain-cells = 360 #power-domain-cells = <0>;
364 power-domains = <&CLUS 361 power-domains = <&CLUSTER_PD>;
365 domain-idle-states = < 362 domain-idle-states = <&BIG_CPU_SLEEP_0>;
366 }; 363 };
367 364
368 CPU_PD7: power-domain-cpu7 { 365 CPU_PD7: power-domain-cpu7 {
369 #power-domain-cells = 366 #power-domain-cells = <0>;
370 power-domains = <&CLUS 367 power-domains = <&CLUSTER_PD>;
371 domain-idle-states = < 368 domain-idle-states = <&BIG_CPU_SLEEP_0>;
372 }; 369 };
373 370
374 CLUSTER_PD: power-domain-cpu-c 371 CLUSTER_PD: power-domain-cpu-cluster0 {
375 #power-domain-cells = 372 #power-domain-cells = <0>;
376 domain-idle-states = < 373 domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>;
377 }; 374 };
378 }; 375 };
379 376
380 qup_opp_table_100mhz: opp-table-qup { 377 qup_opp_table_100mhz: opp-table-qup {
381 compatible = "operating-points 378 compatible = "operating-points-v2";
382 379
383 opp-50000000 { 380 opp-50000000 {
384 opp-hz = /bits/ 64 <50 381 opp-hz = /bits/ 64 <50000000>;
385 required-opps = <&rpmh 382 required-opps = <&rpmhpd_opp_min_svs>;
386 }; 383 };
387 384
388 opp-75000000 { 385 opp-75000000 {
389 opp-hz = /bits/ 64 <75 386 opp-hz = /bits/ 64 <75000000>;
390 required-opps = <&rpmh 387 required-opps = <&rpmhpd_opp_low_svs>;
391 }; 388 };
392 389
393 opp-100000000 { 390 opp-100000000 {
394 opp-hz = /bits/ 64 <10 391 opp-hz = /bits/ 64 <100000000>;
395 required-opps = <&rpmh 392 required-opps = <&rpmhpd_opp_svs>;
396 }; 393 };
397 }; 394 };
398 395
399 reserved_memory: reserved-memory { 396 reserved_memory: reserved-memory {
400 #address-cells = <2>; 397 #address-cells = <2>;
401 #size-cells = <2>; 398 #size-cells = <2>;
402 ranges; 399 ranges;
403 400
404 hyp_mem: memory@80000000 { 401 hyp_mem: memory@80000000 {
405 reg = <0x0 0x80000000 402 reg = <0x0 0x80000000 0x0 0x600000>;
406 no-map; 403 no-map;
407 }; 404 };
408 405
409 xbl_dt_log_mem: memory@8060000 406 xbl_dt_log_mem: memory@80600000 {
410 reg = <0x0 0x80600000 407 reg = <0x0 0x80600000 0x0 0x40000>;
411 no-map; 408 no-map;
412 }; 409 };
413 410
414 xbl_ramdump_mem: memory@806400 411 xbl_ramdump_mem: memory@80640000 {
415 reg = <0x0 0x80640000 412 reg = <0x0 0x80640000 0x0 0x180000>;
416 no-map; 413 no-map;
417 }; 414 };
418 415
419 xbl_sc_mem: memory@807c0000 { 416 xbl_sc_mem: memory@807c0000 {
420 reg = <0x0 0x807c0000 417 reg = <0x0 0x807c0000 0x0 0x40000>;
421 no-map; 418 no-map;
422 }; 419 };
423 420
424 aop_image_mem: memory@80800000 421 aop_image_mem: memory@80800000 {
425 reg = <0x0 0x80800000 422 reg = <0x0 0x80800000 0x0 0x60000>;
426 no-map; 423 no-map;
427 }; 424 };
428 425
429 aop_cmd_db_mem: memory@8086000 426 aop_cmd_db_mem: memory@80860000 {
430 compatible = "qcom,cmd 427 compatible = "qcom,cmd-db";
431 reg = <0x0 0x80860000 428 reg = <0x0 0x80860000 0x0 0x20000>;
432 no-map; 429 no-map;
433 }; 430 };
434 431
435 aop_config_mem: memory@8088000 432 aop_config_mem: memory@80880000 {
436 reg = <0x0 0x80880000 433 reg = <0x0 0x80880000 0x0 0x20000>;
437 no-map; 434 no-map;
438 }; 435 };
439 436
440 tme_crash_dump_mem: memory@808 437 tme_crash_dump_mem: memory@808a0000 {
441 reg = <0x0 0x808a0000 438 reg = <0x0 0x808a0000 0x0 0x40000>;
442 no-map; 439 no-map;
443 }; 440 };
444 441
445 tme_log_mem: memory@808e0000 { 442 tme_log_mem: memory@808e0000 {
446 reg = <0x0 0x808e0000 443 reg = <0x0 0x808e0000 0x0 0x4000>;
447 no-map; 444 no-map;
448 }; 445 };
449 446
450 uefi_log_mem: memory@808e4000 447 uefi_log_mem: memory@808e4000 {
451 reg = <0x0 0x808e4000 448 reg = <0x0 0x808e4000 0x0 0x10000>;
452 no-map; 449 no-map;
453 }; 450 };
454 451
455 /* secdata region can be reuse 452 /* secdata region can be reused by apps */
456 smem: memory@80900000 { 453 smem: memory@80900000 {
457 compatible = "qcom,sme 454 compatible = "qcom,smem";
458 reg = <0x0 0x80900000 455 reg = <0x0 0x80900000 0x0 0x200000>;
459 hwlocks = <&tcsr_mutex 456 hwlocks = <&tcsr_mutex 3>;
460 no-map; 457 no-map;
461 }; 458 };
462 459
463 cpucp_fw_mem: memory@80b00000 460 cpucp_fw_mem: memory@80b00000 {
464 reg = <0x0 0x80b00000 461 reg = <0x0 0x80b00000 0x0 0x100000>;
465 no-map; 462 no-map;
466 }; 463 };
467 464
468 cdsp_secure_heap: memory@80c00 465 cdsp_secure_heap: memory@80c00000 {
469 reg = <0x0 0x80c00000 466 reg = <0x0 0x80c00000 0x0 0x4600000>;
470 no-map; 467 no-map;
471 }; 468 };
472 469
473 video_mem: memory@85700000 { 470 video_mem: memory@85700000 {
474 reg = <0x0 0x85700000 471 reg = <0x0 0x85700000 0x0 0x700000>;
475 no-map; 472 no-map;
476 }; 473 };
477 474
478 adsp_mem: memory@85e00000 { 475 adsp_mem: memory@85e00000 {
479 reg = <0x0 0x85e00000 476 reg = <0x0 0x85e00000 0x0 0x2100000>;
480 no-map; 477 no-map;
481 }; 478 };
482 479
483 slpi_mem: memory@88000000 { 480 slpi_mem: memory@88000000 {
484 reg = <0x0 0x88000000 481 reg = <0x0 0x88000000 0x0 0x1900000>;
485 no-map; 482 no-map;
486 }; 483 };
487 484
488 cdsp_mem: memory@89900000 { 485 cdsp_mem: memory@89900000 {
489 reg = <0x0 0x89900000 486 reg = <0x0 0x89900000 0x0 0x2000000>;
490 no-map; 487 no-map;
491 }; 488 };
492 489
493 ipa_fw_mem: memory@8b900000 { 490 ipa_fw_mem: memory@8b900000 {
494 reg = <0x0 0x8b900000 491 reg = <0x0 0x8b900000 0x0 0x10000>;
495 no-map; 492 no-map;
496 }; 493 };
497 494
498 ipa_gsi_mem: memory@8b910000 { 495 ipa_gsi_mem: memory@8b910000 {
499 reg = <0x0 0x8b910000 496 reg = <0x0 0x8b910000 0x0 0xa000>;
500 no-map; 497 no-map;
501 }; 498 };
502 499
503 gpu_micro_code_mem: memory@8b9 500 gpu_micro_code_mem: memory@8b91a000 {
504 reg = <0x0 0x8b91a000 501 reg = <0x0 0x8b91a000 0x0 0x2000>;
505 no-map; 502 no-map;
506 }; 503 };
507 504
508 spss_region_mem: memory@8ba000 505 spss_region_mem: memory@8ba00000 {
509 reg = <0x0 0x8ba00000 506 reg = <0x0 0x8ba00000 0x0 0x180000>;
510 no-map; 507 no-map;
511 }; 508 };
512 509
513 /* First part of the "SPU secu 510 /* First part of the "SPU secure shared memory" region */
514 spu_tz_shared_mem: memory@8bb8 511 spu_tz_shared_mem: memory@8bb80000 {
515 reg = <0x0 0x8bb80000 512 reg = <0x0 0x8bb80000 0x0 0x60000>;
516 no-map; 513 no-map;
517 }; 514 };
518 515
519 /* Second part of the "SPU sec 516 /* Second part of the "SPU secure shared memory" region */
520 spu_modem_shared_mem: memory@8 517 spu_modem_shared_mem: memory@8bbe0000 {
521 reg = <0x0 0x8bbe0000 518 reg = <0x0 0x8bbe0000 0x0 0x20000>;
522 no-map; 519 no-map;
523 }; 520 };
524 521
525 mpss_mem: memory@8bc00000 { 522 mpss_mem: memory@8bc00000 {
526 reg = <0x0 0x8bc00000 523 reg = <0x0 0x8bc00000 0x0 0x13200000>;
527 no-map; 524 no-map;
528 }; 525 };
529 526
530 cvp_mem: memory@9ee00000 { 527 cvp_mem: memory@9ee00000 {
531 reg = <0x0 0x9ee00000 528 reg = <0x0 0x9ee00000 0x0 0x700000>;
532 no-map; 529 no-map;
533 }; 530 };
534 531
535 camera_mem: memory@9f500000 { 532 camera_mem: memory@9f500000 {
536 reg = <0x0 0x9f500000 533 reg = <0x0 0x9f500000 0x0 0x800000>;
537 no-map; 534 no-map;
538 }; 535 };
539 536
540 rmtfs_mem: memory@9fd00000 { 537 rmtfs_mem: memory@9fd00000 {
541 compatible = "qcom,rmt 538 compatible = "qcom,rmtfs-mem";
542 reg = <0x0 0x9fd00000 539 reg = <0x0 0x9fd00000 0x0 0x280000>;
543 no-map; 540 no-map;
544 541
545 qcom,client-id = <1>; 542 qcom,client-id = <1>;
546 qcom,vmid = <QCOM_SCM_ !! 543 qcom,vmid = <15>;
547 }; 544 };
548 545
549 xbl_sc_mem2: memory@a6e00000 { 546 xbl_sc_mem2: memory@a6e00000 {
550 reg = <0x0 0xa6e00000 547 reg = <0x0 0xa6e00000 0x0 0x40000>;
551 no-map; 548 no-map;
552 }; 549 };
553 550
554 global_sync_mem: memory@a6f000 551 global_sync_mem: memory@a6f00000 {
555 reg = <0x0 0xa6f00000 552 reg = <0x0 0xa6f00000 0x0 0x100000>;
556 no-map; 553 no-map;
557 }; 554 };
558 555
559 /* uefi region can be reused b 556 /* uefi region can be reused by APPS */
560 557
561 /* Linux kernel image is loade 558 /* Linux kernel image is loaded at 0xa0000000 */
562 559
563 oem_vm_mem: memory@bb000000 { 560 oem_vm_mem: memory@bb000000 {
564 reg = <0x0 0xbb000000 561 reg = <0x0 0xbb000000 0x0 0x5000000>;
565 no-map; 562 no-map;
566 }; 563 };
567 564
568 mte_mem: memory@c0000000 { 565 mte_mem: memory@c0000000 {
569 reg = <0x0 0xc0000000 566 reg = <0x0 0xc0000000 0x0 0x20000000>;
570 no-map; 567 no-map;
571 }; 568 };
572 569
573 qheebsp_reserved_mem: memory@e 570 qheebsp_reserved_mem: memory@e0000000 {
574 reg = <0x0 0xe0000000 571 reg = <0x0 0xe0000000 0x0 0x600000>;
575 no-map; 572 no-map;
576 }; 573 };
577 574
578 cpusys_vm_mem: memory@e0600000 575 cpusys_vm_mem: memory@e0600000 {
579 reg = <0x0 0xe0600000 576 reg = <0x0 0xe0600000 0x0 0x400000>;
580 no-map; 577 no-map;
581 }; 578 };
582 579
583 hyp_reserved_mem: memory@e0a00 580 hyp_reserved_mem: memory@e0a00000 {
584 reg = <0x0 0xe0a00000 581 reg = <0x0 0xe0a00000 0x0 0x100000>;
585 no-map; 582 no-map;
586 }; 583 };
587 584
588 trust_ui_vm_mem: memory@e0b000 585 trust_ui_vm_mem: memory@e0b00000 {
589 reg = <0x0 0xe0b00000 586 reg = <0x0 0xe0b00000 0x0 0x4af3000>;
590 no-map; 587 no-map;
591 }; 588 };
592 589
593 trust_ui_vm_qrtr: memory@e55f3 590 trust_ui_vm_qrtr: memory@e55f3000 {
594 reg = <0x0 0xe55f3000 591 reg = <0x0 0xe55f3000 0x0 0x9000>;
595 no-map; 592 no-map;
596 }; 593 };
597 594
598 trust_ui_vm_vblk0_ring: memory 595 trust_ui_vm_vblk0_ring: memory@e55fc000 {
599 reg = <0x0 0xe55fc000 596 reg = <0x0 0xe55fc000 0x0 0x4000>;
600 no-map; 597 no-map;
601 }; 598 };
602 599
603 trust_ui_vm_swiotlb: memory@e5 600 trust_ui_vm_swiotlb: memory@e5600000 {
604 reg = <0x0 0xe5600000 601 reg = <0x0 0xe5600000 0x0 0x100000>;
605 no-map; 602 no-map;
606 }; 603 };
607 604
608 tz_stat_mem: memory@e8800000 { 605 tz_stat_mem: memory@e8800000 {
609 reg = <0x0 0xe8800000 606 reg = <0x0 0xe8800000 0x0 0x100000>;
610 no-map; 607 no-map;
611 }; 608 };
612 609
613 tags_mem: memory@e8900000 { 610 tags_mem: memory@e8900000 {
614 reg = <0x0 0xe8900000 611 reg = <0x0 0xe8900000 0x0 0x1200000>;
615 no-map; 612 no-map;
616 }; 613 };
617 614
618 qtee_mem: memory@e9b00000 { 615 qtee_mem: memory@e9b00000 {
619 reg = <0x0 0xe9b00000 616 reg = <0x0 0xe9b00000 0x0 0x500000>;
620 no-map; 617 no-map;
621 }; 618 };
622 619
623 trusted_apps_mem: memory@ea000 620 trusted_apps_mem: memory@ea000000 {
624 reg = <0x0 0xea000000 621 reg = <0x0 0xea000000 0x0 0x3900000>;
625 no-map; 622 no-map;
626 }; 623 };
627 624
628 trusted_apps_ext_mem: memory@e 625 trusted_apps_ext_mem: memory@ed900000 {
629 reg = <0x0 0xed900000 626 reg = <0x0 0xed900000 0x0 0x3b00000>;
630 no-map; 627 no-map;
631 }; 628 };
632 }; 629 };
633 630
634 smp2p-adsp { 631 smp2p-adsp {
635 compatible = "qcom,smp2p"; 632 compatible = "qcom,smp2p";
636 qcom,smem = <443>, <429>; 633 qcom,smem = <443>, <429>;
637 interrupts-extended = <&ipcc I 634 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
638 I 635 IPCC_MPROC_SIGNAL_SMP2P
639 I 636 IRQ_TYPE_EDGE_RISING>;
640 mboxes = <&ipcc IPCC_CLIENT_LP 637 mboxes = <&ipcc IPCC_CLIENT_LPASS
641 IPCC_MPROC_SIG 638 IPCC_MPROC_SIGNAL_SMP2P>;
642 639
643 qcom,local-pid = <0>; 640 qcom,local-pid = <0>;
644 qcom,remote-pid = <2>; 641 qcom,remote-pid = <2>;
645 642
646 smp2p_adsp_out: master-kernel 643 smp2p_adsp_out: master-kernel {
647 qcom,entry-name = "mas 644 qcom,entry-name = "master-kernel";
648 #qcom,smem-state-cells 645 #qcom,smem-state-cells = <1>;
649 }; 646 };
650 647
651 smp2p_adsp_in: slave-kernel { 648 smp2p_adsp_in: slave-kernel {
652 qcom,entry-name = "sla 649 qcom,entry-name = "slave-kernel";
653 interrupt-controller; 650 interrupt-controller;
654 #interrupt-cells = <2> 651 #interrupt-cells = <2>;
655 }; 652 };
656 }; 653 };
657 654
658 smp2p-cdsp { 655 smp2p-cdsp {
659 compatible = "qcom,smp2p"; 656 compatible = "qcom,smp2p";
660 qcom,smem = <94>, <432>; 657 qcom,smem = <94>, <432>;
661 interrupts-extended = <&ipcc I 658 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
662 I 659 IPCC_MPROC_SIGNAL_SMP2P
663 I 660 IRQ_TYPE_EDGE_RISING>;
664 mboxes = <&ipcc IPCC_CLIENT_CD 661 mboxes = <&ipcc IPCC_CLIENT_CDSP
665 IPCC_MPROC_SIG 662 IPCC_MPROC_SIGNAL_SMP2P>;
666 663
667 qcom,local-pid = <0>; 664 qcom,local-pid = <0>;
668 qcom,remote-pid = <5>; 665 qcom,remote-pid = <5>;
669 666
670 smp2p_cdsp_out: master-kernel 667 smp2p_cdsp_out: master-kernel {
671 qcom,entry-name = "mas 668 qcom,entry-name = "master-kernel";
672 #qcom,smem-state-cells 669 #qcom,smem-state-cells = <1>;
673 }; 670 };
674 671
675 smp2p_cdsp_in: slave-kernel { 672 smp2p_cdsp_in: slave-kernel {
676 qcom,entry-name = "sla 673 qcom,entry-name = "slave-kernel";
677 interrupt-controller; 674 interrupt-controller;
678 #interrupt-cells = <2> 675 #interrupt-cells = <2>;
679 }; 676 };
680 }; 677 };
681 678
682 smp2p-modem { 679 smp2p-modem {
683 compatible = "qcom,smp2p"; 680 compatible = "qcom,smp2p";
684 qcom,smem = <435>, <428>; 681 qcom,smem = <435>, <428>;
685 interrupts-extended = <&ipcc I 682 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
686 I 683 IPCC_MPROC_SIGNAL_SMP2P
687 I 684 IRQ_TYPE_EDGE_RISING>;
688 mboxes = <&ipcc IPCC_CLIENT_MP 685 mboxes = <&ipcc IPCC_CLIENT_MPSS
689 IPCC_MPROC_SIG 686 IPCC_MPROC_SIGNAL_SMP2P>;
690 687
691 qcom,local-pid = <0>; 688 qcom,local-pid = <0>;
692 qcom,remote-pid = <1>; 689 qcom,remote-pid = <1>;
693 690
694 smp2p_modem_out: master-kernel 691 smp2p_modem_out: master-kernel {
695 qcom,entry-name = "mas 692 qcom,entry-name = "master-kernel";
696 #qcom,smem-state-cells 693 #qcom,smem-state-cells = <1>;
697 }; 694 };
698 695
699 smp2p_modem_in: slave-kernel { 696 smp2p_modem_in: slave-kernel {
700 qcom,entry-name = "sla 697 qcom,entry-name = "slave-kernel";
701 interrupt-controller; 698 interrupt-controller;
702 #interrupt-cells = <2> 699 #interrupt-cells = <2>;
703 }; 700 };
704 701
705 ipa_smp2p_out: ipa-ap-to-modem 702 ipa_smp2p_out: ipa-ap-to-modem {
706 qcom,entry-name = "ipa 703 qcom,entry-name = "ipa";
707 #qcom,smem-state-cells 704 #qcom,smem-state-cells = <1>;
708 }; 705 };
709 706
710 ipa_smp2p_in: ipa-modem-to-ap 707 ipa_smp2p_in: ipa-modem-to-ap {
711 qcom,entry-name = "ipa 708 qcom,entry-name = "ipa";
712 interrupt-controller; 709 interrupt-controller;
713 #interrupt-cells = <2> 710 #interrupt-cells = <2>;
714 }; 711 };
715 }; 712 };
716 713
717 smp2p-slpi { 714 smp2p-slpi {
718 compatible = "qcom,smp2p"; 715 compatible = "qcom,smp2p";
719 qcom,smem = <481>, <430>; 716 qcom,smem = <481>, <430>;
720 interrupts-extended = <&ipcc I 717 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
721 I 718 IPCC_MPROC_SIGNAL_SMP2P
722 I 719 IRQ_TYPE_EDGE_RISING>;
723 mboxes = <&ipcc IPCC_CLIENT_SL 720 mboxes = <&ipcc IPCC_CLIENT_SLPI
724 IPCC_MPROC_SIG 721 IPCC_MPROC_SIGNAL_SMP2P>;
725 722
726 qcom,local-pid = <0>; 723 qcom,local-pid = <0>;
727 qcom,remote-pid = <3>; 724 qcom,remote-pid = <3>;
728 725
729 smp2p_slpi_out: master-kernel 726 smp2p_slpi_out: master-kernel {
730 qcom,entry-name = "mas 727 qcom,entry-name = "master-kernel";
731 #qcom,smem-state-cells 728 #qcom,smem-state-cells = <1>;
732 }; 729 };
733 730
734 smp2p_slpi_in: slave-kernel { 731 smp2p_slpi_in: slave-kernel {
735 qcom,entry-name = "sla 732 qcom,entry-name = "slave-kernel";
736 interrupt-controller; 733 interrupt-controller;
737 #interrupt-cells = <2> 734 #interrupt-cells = <2>;
738 }; 735 };
739 }; 736 };
740 737
741 soc: soc@0 { 738 soc: soc@0 {
742 #address-cells = <2>; 739 #address-cells = <2>;
743 #size-cells = <2>; 740 #size-cells = <2>;
744 ranges = <0 0 0 0 0x10 0>; 741 ranges = <0 0 0 0 0x10 0>;
745 dma-ranges = <0 0 0 0 0x10 0>; 742 dma-ranges = <0 0 0 0 0x10 0>;
746 compatible = "simple-bus"; 743 compatible = "simple-bus";
747 744
748 gcc: clock-controller@100000 { 745 gcc: clock-controller@100000 {
749 compatible = "qcom,gcc 746 compatible = "qcom,gcc-sm8450";
750 reg = <0x0 0x00100000 747 reg = <0x0 0x00100000 0x0 0x1f4200>;
751 #clock-cells = <1>; 748 #clock-cells = <1>;
752 #reset-cells = <1>; 749 #reset-cells = <1>;
753 #power-domain-cells = 750 #power-domain-cells = <1>;
754 clocks = <&rpmhcc RPMH 751 clocks = <&rpmhcc RPMH_CXO_CLK>,
755 <&sleep_clk>, 752 <&sleep_clk>,
756 <&pcie0_phy>, !! 753 <&pcie0_lane>,
757 <&pcie1_phy Q !! 754 <&pcie1_lane>,
758 <&pcie1_phy Q !! 755 <0>,
759 <&ufs_mem_phy !! 756 <&ufs_mem_phy_lanes 0>,
760 <&ufs_mem_phy !! 757 <&ufs_mem_phy_lanes 1>,
761 <&ufs_mem_phy !! 758 <&ufs_mem_phy_lanes 2>,
762 <&usb_1_qmpph 759 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
763 clock-names = "bi_tcxo 760 clock-names = "bi_tcxo",
764 "sleep_c 761 "sleep_clk",
765 "pcie_0_ 762 "pcie_0_pipe_clk",
766 "pcie_1_ 763 "pcie_1_pipe_clk",
767 "pcie_1_ 764 "pcie_1_phy_aux_clk",
768 "ufs_phy 765 "ufs_phy_rx_symbol_0_clk",
769 "ufs_phy 766 "ufs_phy_rx_symbol_1_clk",
770 "ufs_phy 767 "ufs_phy_tx_symbol_0_clk",
771 "usb3_ph 768 "usb3_phy_wrapper_gcc_usb30_pipe_clk";
772 }; 769 };
773 770
774 gpi_dma2: dma-controller@80000 771 gpi_dma2: dma-controller@800000 {
775 compatible = "qcom,sm8 772 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
776 #dma-cells = <3>; 773 #dma-cells = <3>;
777 reg = <0 0x00800000 0 774 reg = <0 0x00800000 0 0x60000>;
778 interrupts = <GIC_SPI 775 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
779 <GIC_SPI 776 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
780 <GIC_SPI 777 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
781 <GIC_SPI 778 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
782 <GIC_SPI 779 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
783 <GIC_SPI 780 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
784 <GIC_SPI 781 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
785 <GIC_SPI 782 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
786 <GIC_SPI 783 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
787 <GIC_SPI 784 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
788 <GIC_SPI 785 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
789 <GIC_SPI 786 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
790 dma-channels = <12>; 787 dma-channels = <12>;
791 dma-channel-mask = <0x 788 dma-channel-mask = <0x7e>;
792 iommus = <&apps_smmu 0 789 iommus = <&apps_smmu 0x496 0x0>;
793 status = "disabled"; 790 status = "disabled";
794 }; 791 };
795 792
796 qupv3_id_2: geniqup@8c0000 { 793 qupv3_id_2: geniqup@8c0000 {
797 compatible = "qcom,gen 794 compatible = "qcom,geni-se-qup";
798 reg = <0x0 0x008c0000 795 reg = <0x0 0x008c0000 0x0 0x2000>;
799 clock-names = "m-ahb", 796 clock-names = "m-ahb", "s-ahb";
800 clocks = <&gcc GCC_QUP 797 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
801 <&gcc GCC_QUP 798 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
802 iommus = <&apps_smmu 0 799 iommus = <&apps_smmu 0x483 0x0>;
803 #address-cells = <2>; 800 #address-cells = <2>;
804 #size-cells = <2>; 801 #size-cells = <2>;
805 ranges; 802 ranges;
806 status = "disabled"; 803 status = "disabled";
807 804
808 i2c15: i2c@880000 { 805 i2c15: i2c@880000 {
809 compatible = " 806 compatible = "qcom,geni-i2c";
810 reg = <0x0 0x0 807 reg = <0x0 0x00880000 0x0 0x4000>;
811 clock-names = 808 clock-names = "se";
812 clocks = <&gcc 809 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
813 pinctrl-names 810 pinctrl-names = "default";
814 pinctrl-0 = <& 811 pinctrl-0 = <&qup_i2c15_data_clk>;
815 interrupts = < 812 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
816 #address-cells 813 #address-cells = <1>;
817 #size-cells = 814 #size-cells = <0>;
818 interconnects 815 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
819 816 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
820 817 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
821 interconnect-n 818 interconnect-names = "qup-core", "qup-config", "qup-memory";
822 dmas = <&gpi_d 819 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
823 <&gpi_d 820 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
824 dma-names = "t 821 dma-names = "tx", "rx";
825 status = "disa 822 status = "disabled";
826 }; 823 };
827 824
828 spi15: spi@880000 { 825 spi15: spi@880000 {
829 compatible = " 826 compatible = "qcom,geni-spi";
830 reg = <0x0 0x0 827 reg = <0x0 0x00880000 0x0 0x4000>;
831 clock-names = 828 clock-names = "se";
832 clocks = <&gcc 829 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
833 interrupts = < 830 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
834 pinctrl-names 831 pinctrl-names = "default";
835 pinctrl-0 = <& 832 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
836 interconnects 833 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
837 834 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
838 interconnect-n 835 interconnect-names = "qup-core", "qup-config";
839 dmas = <&gpi_d 836 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
840 <&gpi_d 837 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
841 dma-names = "t 838 dma-names = "tx", "rx";
842 #address-cells 839 #address-cells = <1>;
843 #size-cells = 840 #size-cells = <0>;
844 status = "disa 841 status = "disabled";
845 }; 842 };
846 843
847 i2c16: i2c@884000 { 844 i2c16: i2c@884000 {
848 compatible = " 845 compatible = "qcom,geni-i2c";
849 reg = <0x0 0x0 846 reg = <0x0 0x00884000 0x0 0x4000>;
850 clock-names = 847 clock-names = "se";
851 clocks = <&gcc 848 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
852 pinctrl-names 849 pinctrl-names = "default";
853 pinctrl-0 = <& 850 pinctrl-0 = <&qup_i2c16_data_clk>;
854 interrupts = < 851 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
855 #address-cells 852 #address-cells = <1>;
856 #size-cells = 853 #size-cells = <0>;
857 interconnects 854 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
858 855 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
859 856 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
860 interconnect-n 857 interconnect-names = "qup-core", "qup-config", "qup-memory";
861 dmas = <&gpi_d 858 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
862 <&gpi_d 859 <&gpi_dma2 1 1 QCOM_GPI_I2C>;
863 dma-names = "t 860 dma-names = "tx", "rx";
864 status = "disa 861 status = "disabled";
865 }; 862 };
866 863
867 spi16: spi@884000 { 864 spi16: spi@884000 {
868 compatible = " 865 compatible = "qcom,geni-spi";
869 reg = <0x0 0x0 866 reg = <0x0 0x00884000 0x0 0x4000>;
870 clock-names = 867 clock-names = "se";
871 clocks = <&gcc 868 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
872 interrupts = < 869 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
873 pinctrl-names 870 pinctrl-names = "default";
874 pinctrl-0 = <& 871 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>;
875 interconnects 872 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
876 873 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
877 interconnect-n 874 interconnect-names = "qup-core", "qup-config";
878 dmas = <&gpi_d 875 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
879 <&gpi_d 876 <&gpi_dma2 1 1 QCOM_GPI_SPI>;
880 dma-names = "t 877 dma-names = "tx", "rx";
881 #address-cells 878 #address-cells = <1>;
882 #size-cells = 879 #size-cells = <0>;
883 status = "disa 880 status = "disabled";
884 }; 881 };
885 882
886 i2c17: i2c@888000 { 883 i2c17: i2c@888000 {
887 compatible = " 884 compatible = "qcom,geni-i2c";
888 reg = <0x0 0x0 885 reg = <0x0 0x00888000 0x0 0x4000>;
889 clock-names = 886 clock-names = "se";
890 clocks = <&gcc 887 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
891 pinctrl-names 888 pinctrl-names = "default";
892 pinctrl-0 = <& 889 pinctrl-0 = <&qup_i2c17_data_clk>;
893 interrupts = < 890 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
894 #address-cells 891 #address-cells = <1>;
895 #size-cells = 892 #size-cells = <0>;
896 interconnects 893 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
897 894 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
898 895 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
899 interconnect-n 896 interconnect-names = "qup-core", "qup-config", "qup-memory";
900 dmas = <&gpi_d 897 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
901 <&gpi_d 898 <&gpi_dma2 1 2 QCOM_GPI_I2C>;
902 dma-names = "t 899 dma-names = "tx", "rx";
903 status = "disa 900 status = "disabled";
904 }; 901 };
905 902
906 spi17: spi@888000 { 903 spi17: spi@888000 {
907 compatible = " 904 compatible = "qcom,geni-spi";
908 reg = <0x0 0x0 905 reg = <0x0 0x00888000 0x0 0x4000>;
909 clock-names = 906 clock-names = "se";
910 clocks = <&gcc 907 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
911 interrupts = < 908 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
912 pinctrl-names 909 pinctrl-names = "default";
913 pinctrl-0 = <& 910 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>;
914 interconnects 911 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
915 912 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
916 interconnect-n 913 interconnect-names = "qup-core", "qup-config";
917 dmas = <&gpi_d 914 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
918 <&gpi_d 915 <&gpi_dma2 1 2 QCOM_GPI_SPI>;
919 dma-names = "t 916 dma-names = "tx", "rx";
920 #address-cells 917 #address-cells = <1>;
921 #size-cells = 918 #size-cells = <0>;
922 status = "disa 919 status = "disabled";
923 }; 920 };
924 921
925 i2c18: i2c@88c000 { 922 i2c18: i2c@88c000 {
926 compatible = " 923 compatible = "qcom,geni-i2c";
927 reg = <0x0 0x0 924 reg = <0x0 0x0088c000 0x0 0x4000>;
928 clock-names = 925 clock-names = "se";
929 clocks = <&gcc 926 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
930 pinctrl-names 927 pinctrl-names = "default";
931 pinctrl-0 = <& 928 pinctrl-0 = <&qup_i2c18_data_clk>;
932 interrupts = < 929 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
933 #address-cells 930 #address-cells = <1>;
934 #size-cells = 931 #size-cells = <0>;
935 interconnects 932 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
936 933 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
937 934 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
938 interconnect-n 935 interconnect-names = "qup-core", "qup-config", "qup-memory";
939 dmas = <&gpi_d 936 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
940 <&gpi_d 937 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
941 dma-names = "t 938 dma-names = "tx", "rx";
942 status = "disa 939 status = "disabled";
943 }; 940 };
944 941
945 spi18: spi@88c000 { 942 spi18: spi@88c000 {
946 compatible = " 943 compatible = "qcom,geni-spi";
947 reg = <0 0x008 944 reg = <0 0x0088c000 0 0x4000>;
948 clock-names = 945 clock-names = "se";
949 clocks = <&gcc 946 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
950 interrupts = < 947 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
951 pinctrl-names 948 pinctrl-names = "default";
952 pinctrl-0 = <& 949 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>;
953 interconnects 950 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
954 951 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
955 interconnect-n 952 interconnect-names = "qup-core", "qup-config";
956 dmas = <&gpi_d 953 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
957 <&gpi_d 954 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
958 dma-names = "t 955 dma-names = "tx", "rx";
959 #address-cells 956 #address-cells = <1>;
960 #size-cells = 957 #size-cells = <0>;
961 status = "disa 958 status = "disabled";
962 }; 959 };
963 960
964 i2c19: i2c@890000 { 961 i2c19: i2c@890000 {
965 compatible = " 962 compatible = "qcom,geni-i2c";
966 reg = <0x0 0x0 963 reg = <0x0 0x00890000 0x0 0x4000>;
967 clock-names = 964 clock-names = "se";
968 clocks = <&gcc 965 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
969 pinctrl-names 966 pinctrl-names = "default";
970 pinctrl-0 = <& 967 pinctrl-0 = <&qup_i2c19_data_clk>;
971 interrupts = < 968 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
972 #address-cells 969 #address-cells = <1>;
973 #size-cells = 970 #size-cells = <0>;
974 interconnects 971 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
975 972 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
976 973 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
977 interconnect-n 974 interconnect-names = "qup-core", "qup-config", "qup-memory";
978 dmas = <&gpi_d 975 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
979 <&gpi_d 976 <&gpi_dma2 1 4 QCOM_GPI_I2C>;
980 dma-names = "t 977 dma-names = "tx", "rx";
981 status = "disa 978 status = "disabled";
982 }; 979 };
983 980
984 spi19: spi@890000 { 981 spi19: spi@890000 {
985 compatible = " 982 compatible = "qcom,geni-spi";
986 reg = <0 0x008 983 reg = <0 0x00890000 0 0x4000>;
987 clock-names = 984 clock-names = "se";
988 clocks = <&gcc 985 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
989 interrupts = < 986 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
990 pinctrl-names 987 pinctrl-names = "default";
991 pinctrl-0 = <& 988 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>;
992 interconnects 989 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
993 990 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
994 interconnect-n 991 interconnect-names = "qup-core", "qup-config";
995 dmas = <&gpi_d 992 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
996 <&gpi_d 993 <&gpi_dma2 1 4 QCOM_GPI_I2C>;
997 dma-names = "t 994 dma-names = "tx", "rx";
998 #address-cells 995 #address-cells = <1>;
999 #size-cells = 996 #size-cells = <0>;
1000 status = "dis 997 status = "disabled";
1001 }; 998 };
1002 999
1003 i2c20: i2c@894000 { 1000 i2c20: i2c@894000 {
1004 compatible = 1001 compatible = "qcom,geni-i2c";
1005 reg = <0x0 0x 1002 reg = <0x0 0x00894000 0x0 0x4000>;
1006 clock-names = 1003 clock-names = "se";
1007 clocks = <&gc 1004 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1008 pinctrl-names 1005 pinctrl-names = "default";
1009 pinctrl-0 = < 1006 pinctrl-0 = <&qup_i2c20_data_clk>;
1010 interrupts = 1007 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1011 #address-cell 1008 #address-cells = <1>;
1012 #size-cells = 1009 #size-cells = <0>;
1013 interconnects 1010 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1014 1011 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1015 1012 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1016 interconnect- 1013 interconnect-names = "qup-core", "qup-config", "qup-memory";
1017 dmas = <&gpi_ 1014 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1018 <&gpi_ 1015 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1019 dma-names = " 1016 dma-names = "tx", "rx";
1020 status = "dis 1017 status = "disabled";
1021 }; 1018 };
1022 1019
1023 uart20: serial@894000 1020 uart20: serial@894000 {
1024 compatible = 1021 compatible = "qcom,geni-uart";
1025 reg = <0 0x00 1022 reg = <0 0x00894000 0 0x4000>;
1026 clock-names = 1023 clock-names = "se";
1027 clocks = <&gc 1024 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1028 pinctrl-names 1025 pinctrl-names = "default";
1029 pinctrl-0 = < 1026 pinctrl-0 = <&qup_uart20_default>;
1030 interrupts = 1027 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1031 interconnects 1028 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1032 1029 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1033 1030 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1034 1031 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
1035 interconnect- 1032 interconnect-names = "qup-core",
1036 1033 "qup-config";
1037 status = "dis 1034 status = "disabled";
1038 }; 1035 };
1039 1036
1040 spi20: spi@894000 { 1037 spi20: spi@894000 {
1041 compatible = 1038 compatible = "qcom,geni-spi";
1042 reg = <0 0x00 1039 reg = <0 0x00894000 0 0x4000>;
1043 clock-names = 1040 clock-names = "se";
1044 clocks = <&gc 1041 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1045 interrupts = 1042 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1046 pinctrl-names 1043 pinctrl-names = "default";
1047 pinctrl-0 = < 1044 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>;
1048 interconnects 1045 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1049 1046 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
1050 interconnect- 1047 interconnect-names = "qup-core", "qup-config";
1051 dmas = <&gpi_ 1048 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1052 <&gpi_ 1049 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1053 dma-names = " 1050 dma-names = "tx", "rx";
1054 #address-cell 1051 #address-cells = <1>;
1055 #size-cells = 1052 #size-cells = <0>;
1056 status = "dis 1053 status = "disabled";
1057 }; 1054 };
1058 1055
1059 i2c21: i2c@898000 { 1056 i2c21: i2c@898000 {
1060 compatible = 1057 compatible = "qcom,geni-i2c";
1061 reg = <0x0 0x 1058 reg = <0x0 0x00898000 0x0 0x4000>;
1062 clock-names = 1059 clock-names = "se";
1063 clocks = <&gc 1060 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1064 pinctrl-names 1061 pinctrl-names = "default";
1065 pinctrl-0 = < 1062 pinctrl-0 = <&qup_i2c21_data_clk>;
1066 interrupts = 1063 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
1067 #address-cell 1064 #address-cells = <1>;
1068 #size-cells = 1065 #size-cells = <0>;
1069 interconnects 1066 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1070 1067 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1071 1068 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1072 interconnect- 1069 interconnect-names = "qup-core", "qup-config", "qup-memory";
1073 dmas = <&gpi_ 1070 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>,
1074 <&gpi_ 1071 <&gpi_dma2 1 6 QCOM_GPI_I2C>;
1075 dma-names = " 1072 dma-names = "tx", "rx";
1076 status = "dis 1073 status = "disabled";
1077 }; 1074 };
1078 1075
1079 spi21: spi@898000 { 1076 spi21: spi@898000 {
1080 compatible = 1077 compatible = "qcom,geni-spi";
1081 reg = <0 0x00 1078 reg = <0 0x00898000 0 0x4000>;
1082 clock-names = 1079 clock-names = "se";
1083 clocks = <&gc 1080 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1084 interrupts = 1081 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
1085 pinctrl-names 1082 pinctrl-names = "default";
1086 pinctrl-0 = < 1083 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>;
1087 interconnects 1084 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1088 1085 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
1089 interconnect- 1086 interconnect-names = "qup-core", "qup-config";
1090 dmas = <&gpi_ 1087 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>,
1091 <&gpi_ 1088 <&gpi_dma2 1 6 QCOM_GPI_SPI>;
1092 dma-names = " 1089 dma-names = "tx", "rx";
1093 #address-cell 1090 #address-cells = <1>;
1094 #size-cells = 1091 #size-cells = <0>;
1095 status = "dis 1092 status = "disabled";
1096 }; 1093 };
1097 }; 1094 };
1098 1095
1099 gpi_dma0: dma-controller@9000 1096 gpi_dma0: dma-controller@900000 {
1100 compatible = "qcom,sm 1097 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
1101 #dma-cells = <3>; 1098 #dma-cells = <3>;
1102 reg = <0 0x00900000 0 1099 reg = <0 0x00900000 0 0x60000>;
1103 interrupts = <GIC_SPI 1100 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
1104 <GIC_SPI 1101 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
1105 <GIC_SPI 1102 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
1106 <GIC_SPI 1103 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
1107 <GIC_SPI 1104 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
1108 <GIC_SPI 1105 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
1109 <GIC_SPI 1106 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
1110 <GIC_SPI 1107 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
1111 <GIC_SPI 1108 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
1112 <GIC_SPI 1109 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
1113 <GIC_SPI 1110 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
1114 <GIC_SPI 1111 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
1115 dma-channels = <12>; 1112 dma-channels = <12>;
1116 dma-channel-mask = <0 1113 dma-channel-mask = <0x7e>;
1117 iommus = <&apps_smmu 1114 iommus = <&apps_smmu 0x5b6 0x0>;
1118 status = "disabled"; 1115 status = "disabled";
1119 }; 1116 };
1120 1117
1121 qupv3_id_0: geniqup@9c0000 { 1118 qupv3_id_0: geniqup@9c0000 {
1122 compatible = "qcom,ge 1119 compatible = "qcom,geni-se-qup";
1123 reg = <0x0 0x009c0000 1120 reg = <0x0 0x009c0000 0x0 0x2000>;
1124 clock-names = "m-ahb" 1121 clock-names = "m-ahb", "s-ahb";
1125 clocks = <&gcc GCC_QU 1122 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1126 <&gcc GCC_QU 1123 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1127 iommus = <&apps_smmu 1124 iommus = <&apps_smmu 0x5a3 0x0>;
1128 interconnects = <&clk 1125 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>;
1129 interconnect-names = 1126 interconnect-names = "qup-core";
1130 #address-cells = <2>; 1127 #address-cells = <2>;
1131 #size-cells = <2>; 1128 #size-cells = <2>;
1132 ranges; 1129 ranges;
1133 status = "disabled"; 1130 status = "disabled";
1134 1131
1135 i2c0: i2c@980000 { 1132 i2c0: i2c@980000 {
1136 compatible = 1133 compatible = "qcom,geni-i2c";
1137 reg = <0x0 0x 1134 reg = <0x0 0x00980000 0x0 0x4000>;
1138 clock-names = 1135 clock-names = "se";
1139 clocks = <&gc 1136 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1140 pinctrl-names 1137 pinctrl-names = "default";
1141 pinctrl-0 = < 1138 pinctrl-0 = <&qup_i2c0_data_clk>;
1142 interrupts = 1139 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1143 #address-cell 1140 #address-cells = <1>;
1144 #size-cells = 1141 #size-cells = <0>;
1145 interconnects 1142 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1146 1143 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1147 1144 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1148 interconnect- 1145 interconnect-names = "qup-core", "qup-config", "qup-memory";
1149 dmas = <&gpi_ 1146 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1150 <&gpi_ 1147 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1151 dma-names = " 1148 dma-names = "tx", "rx";
1152 status = "dis 1149 status = "disabled";
1153 }; 1150 };
1154 1151
1155 spi0: spi@980000 { 1152 spi0: spi@980000 {
1156 compatible = 1153 compatible = "qcom,geni-spi";
1157 reg = <0x0 0x 1154 reg = <0x0 0x00980000 0x0 0x4000>;
1158 clock-names = 1155 clock-names = "se";
1159 clocks = <&gc 1156 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1160 interrupts = 1157 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1161 pinctrl-names 1158 pinctrl-names = "default";
1162 pinctrl-0 = < 1159 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1163 power-domains 1160 power-domains = <&rpmhpd RPMHPD_CX>;
1164 operating-poi 1161 operating-points-v2 = <&qup_opp_table_100mhz>;
1165 interconnects 1162 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1166 1163 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1167 1164 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1168 interconnect- 1165 interconnect-names = "qup-core", "qup-config", "qup-memory";
1169 dmas = <&gpi_ 1166 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1170 <&gpi_ 1167 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1171 dma-names = " 1168 dma-names = "tx", "rx";
1172 #address-cell 1169 #address-cells = <1>;
1173 #size-cells = 1170 #size-cells = <0>;
1174 status = "dis 1171 status = "disabled";
1175 }; 1172 };
1176 1173
1177 i2c1: i2c@984000 { 1174 i2c1: i2c@984000 {
1178 compatible = 1175 compatible = "qcom,geni-i2c";
1179 reg = <0x0 0x 1176 reg = <0x0 0x00984000 0x0 0x4000>;
1180 clock-names = 1177 clock-names = "se";
1181 clocks = <&gc 1178 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1182 pinctrl-names 1179 pinctrl-names = "default";
1183 pinctrl-0 = < 1180 pinctrl-0 = <&qup_i2c1_data_clk>;
1184 interrupts = 1181 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1185 #address-cell 1182 #address-cells = <1>;
1186 #size-cells = 1183 #size-cells = <0>;
1187 interconnects 1184 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1188 1185 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1189 1186 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1190 interconnect- 1187 interconnect-names = "qup-core", "qup-config", "qup-memory";
1191 dmas = <&gpi_ 1188 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1192 <&gpi_ 1189 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1193 dma-names = " 1190 dma-names = "tx", "rx";
1194 status = "dis 1191 status = "disabled";
1195 }; 1192 };
1196 1193
1197 spi1: spi@984000 { 1194 spi1: spi@984000 {
1198 compatible = 1195 compatible = "qcom,geni-spi";
1199 reg = <0x0 0x 1196 reg = <0x0 0x00984000 0x0 0x4000>;
1200 clock-names = 1197 clock-names = "se";
1201 clocks = <&gc 1198 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1202 interrupts = 1199 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1203 pinctrl-names 1200 pinctrl-names = "default";
1204 pinctrl-0 = < 1201 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1205 interconnects 1202 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1206 1203 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1207 1204 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1208 interconnect- 1205 interconnect-names = "qup-core", "qup-config", "qup-memory";
1209 dmas = <&gpi_ 1206 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1210 <&gpi_ 1207 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1211 dma-names = " 1208 dma-names = "tx", "rx";
1212 #address-cell 1209 #address-cells = <1>;
1213 #size-cells = 1210 #size-cells = <0>;
1214 status = "dis 1211 status = "disabled";
1215 }; 1212 };
1216 1213
1217 i2c2: i2c@988000 { 1214 i2c2: i2c@988000 {
1218 compatible = 1215 compatible = "qcom,geni-i2c";
1219 reg = <0x0 0x 1216 reg = <0x0 0x00988000 0x0 0x4000>;
1220 clock-names = 1217 clock-names = "se";
1221 clocks = <&gc 1218 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1222 pinctrl-names 1219 pinctrl-names = "default";
1223 pinctrl-0 = < 1220 pinctrl-0 = <&qup_i2c2_data_clk>;
1224 interrupts = 1221 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1225 #address-cell 1222 #address-cells = <1>;
1226 #size-cells = 1223 #size-cells = <0>;
1227 interconnects 1224 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1228 1225 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1229 1226 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1230 interconnect- 1227 interconnect-names = "qup-core", "qup-config", "qup-memory";
1231 dmas = <&gpi_ 1228 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1232 <&gpi_ 1229 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1233 dma-names = " 1230 dma-names = "tx", "rx";
1234 status = "dis 1231 status = "disabled";
1235 }; 1232 };
1236 1233
1237 spi2: spi@988000 { 1234 spi2: spi@988000 {
1238 compatible = 1235 compatible = "qcom,geni-spi";
1239 reg = <0x0 0x 1236 reg = <0x0 0x00988000 0x0 0x4000>;
1240 clock-names = 1237 clock-names = "se";
1241 clocks = <&gc 1238 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1242 interrupts = 1239 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1243 pinctrl-names 1240 pinctrl-names = "default";
1244 pinctrl-0 = < 1241 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1245 interconnects 1242 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1246 1243 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1247 1244 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1248 interconnect- 1245 interconnect-names = "qup-core", "qup-config", "qup-memory";
1249 dmas = <&gpi_ 1246 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1250 <&gpi_ 1247 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1251 dma-names = " 1248 dma-names = "tx", "rx";
1252 #address-cell 1249 #address-cells = <1>;
1253 #size-cells = 1250 #size-cells = <0>;
1254 status = "dis 1251 status = "disabled";
1255 }; 1252 };
1256 1253
1257 1254
1258 i2c3: i2c@98c000 { 1255 i2c3: i2c@98c000 {
1259 compatible = 1256 compatible = "qcom,geni-i2c";
1260 reg = <0x0 0x 1257 reg = <0x0 0x0098c000 0x0 0x4000>;
1261 clock-names = 1258 clock-names = "se";
1262 clocks = <&gc 1259 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1263 pinctrl-names 1260 pinctrl-names = "default";
1264 pinctrl-0 = < 1261 pinctrl-0 = <&qup_i2c3_data_clk>;
1265 interrupts = 1262 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1266 #address-cell 1263 #address-cells = <1>;
1267 #size-cells = 1264 #size-cells = <0>;
1268 interconnects 1265 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1269 1266 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1270 1267 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1271 interconnect- 1268 interconnect-names = "qup-core", "qup-config", "qup-memory";
1272 dmas = <&gpi_ 1269 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1273 <&gpi_ 1270 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1274 dma-names = " 1271 dma-names = "tx", "rx";
1275 status = "dis 1272 status = "disabled";
1276 }; 1273 };
1277 1274
1278 spi3: spi@98c000 { 1275 spi3: spi@98c000 {
1279 compatible = 1276 compatible = "qcom,geni-spi";
1280 reg = <0x0 0x 1277 reg = <0x0 0x0098c000 0x0 0x4000>;
1281 clock-names = 1278 clock-names = "se";
1282 clocks = <&gc 1279 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1283 interrupts = 1280 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1284 pinctrl-names 1281 pinctrl-names = "default";
1285 pinctrl-0 = < 1282 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1286 interconnects 1283 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1287 1284 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1288 1285 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1289 interconnect- 1286 interconnect-names = "qup-core", "qup-config", "qup-memory";
1290 dmas = <&gpi_ 1287 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1291 <&gpi_ 1288 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1292 dma-names = " 1289 dma-names = "tx", "rx";
1293 #address-cell 1290 #address-cells = <1>;
1294 #size-cells = 1291 #size-cells = <0>;
1295 status = "dis 1292 status = "disabled";
1296 }; 1293 };
1297 1294
1298 i2c4: i2c@990000 { 1295 i2c4: i2c@990000 {
1299 compatible = 1296 compatible = "qcom,geni-i2c";
1300 reg = <0x0 0x 1297 reg = <0x0 0x00990000 0x0 0x4000>;
1301 clock-names = 1298 clock-names = "se";
1302 clocks = <&gc 1299 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1303 pinctrl-names 1300 pinctrl-names = "default";
1304 pinctrl-0 = < 1301 pinctrl-0 = <&qup_i2c4_data_clk>;
1305 interrupts = 1302 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1306 #address-cell 1303 #address-cells = <1>;
1307 #size-cells = 1304 #size-cells = <0>;
1308 interconnects 1305 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1309 1306 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1310 1307 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1311 interconnect- 1308 interconnect-names = "qup-core", "qup-config", "qup-memory";
1312 dmas = <&gpi_ 1309 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1313 <&gpi_ 1310 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1314 dma-names = " 1311 dma-names = "tx", "rx";
1315 status = "dis 1312 status = "disabled";
1316 }; 1313 };
1317 1314
1318 spi4: spi@990000 { 1315 spi4: spi@990000 {
1319 compatible = 1316 compatible = "qcom,geni-spi";
1320 reg = <0x0 0x 1317 reg = <0x0 0x00990000 0x0 0x4000>;
1321 clock-names = 1318 clock-names = "se";
1322 clocks = <&gc 1319 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1323 interrupts = 1320 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1324 pinctrl-names 1321 pinctrl-names = "default";
1325 pinctrl-0 = < 1322 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1326 power-domains 1323 power-domains = <&rpmhpd RPMHPD_CX>;
1327 operating-poi 1324 operating-points-v2 = <&qup_opp_table_100mhz>;
1328 interconnects 1325 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1329 1326 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1330 1327 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1331 interconnect- 1328 interconnect-names = "qup-core", "qup-config", "qup-memory";
1332 dmas = <&gpi_ 1329 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1333 <&gpi_ 1330 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1334 dma-names = " 1331 dma-names = "tx", "rx";
1335 #address-cell 1332 #address-cells = <1>;
1336 #size-cells = 1333 #size-cells = <0>;
1337 status = "dis 1334 status = "disabled";
1338 }; 1335 };
1339 1336
1340 i2c5: i2c@994000 { 1337 i2c5: i2c@994000 {
1341 compatible = 1338 compatible = "qcom,geni-i2c";
1342 reg = <0x0 0x 1339 reg = <0x0 0x00994000 0x0 0x4000>;
1343 clock-names = 1340 clock-names = "se";
1344 clocks = <&gc 1341 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1345 pinctrl-names 1342 pinctrl-names = "default";
1346 pinctrl-0 = < 1343 pinctrl-0 = <&qup_i2c5_data_clk>;
1347 interrupts = 1344 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1348 #address-cell 1345 #address-cells = <1>;
1349 #size-cells = 1346 #size-cells = <0>;
1350 interconnects 1347 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1351 1348 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1352 1349 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1353 interconnect- 1350 interconnect-names = "qup-core", "qup-config", "qup-memory";
1354 dmas = <&gpi_ 1351 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1355 <&gpi_ 1352 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1356 dma-names = " 1353 dma-names = "tx", "rx";
1357 status = "dis 1354 status = "disabled";
1358 }; 1355 };
1359 1356
1360 spi5: spi@994000 { 1357 spi5: spi@994000 {
1361 compatible = 1358 compatible = "qcom,geni-spi";
1362 reg = <0x0 0x 1359 reg = <0x0 0x00994000 0x0 0x4000>;
1363 clock-names = 1360 clock-names = "se";
1364 clocks = <&gc 1361 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1365 interrupts = 1362 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1366 pinctrl-names 1363 pinctrl-names = "default";
1367 pinctrl-0 = < 1364 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1368 interconnects 1365 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1369 1366 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1370 1367 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1371 interconnect- 1368 interconnect-names = "qup-core", "qup-config", "qup-memory";
1372 dmas = <&gpi_ 1369 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1373 <&gpi_ 1370 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1374 dma-names = " 1371 dma-names = "tx", "rx";
1375 #address-cell 1372 #address-cells = <1>;
1376 #size-cells = 1373 #size-cells = <0>;
1377 status = "dis 1374 status = "disabled";
1378 }; 1375 };
1379 1376
1380 1377
1381 i2c6: i2c@998000 { 1378 i2c6: i2c@998000 {
1382 compatible = 1379 compatible = "qcom,geni-i2c";
1383 reg = <0x0 0x 1380 reg = <0x0 0x00998000 0x0 0x4000>;
1384 clock-names = 1381 clock-names = "se";
1385 clocks = <&gc 1382 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1386 pinctrl-names 1383 pinctrl-names = "default";
1387 pinctrl-0 = < 1384 pinctrl-0 = <&qup_i2c6_data_clk>;
1388 interrupts = 1385 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1389 #address-cell 1386 #address-cells = <1>;
1390 #size-cells = 1387 #size-cells = <0>;
1391 interconnects 1388 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1392 1389 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1393 1390 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1394 interconnect- 1391 interconnect-names = "qup-core", "qup-config", "qup-memory";
1395 dmas = <&gpi_ 1392 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1396 <&gpi_ 1393 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1397 dma-names = " 1394 dma-names = "tx", "rx";
1398 status = "dis 1395 status = "disabled";
1399 }; 1396 };
1400 1397
1401 spi6: spi@998000 { 1398 spi6: spi@998000 {
1402 compatible = 1399 compatible = "qcom,geni-spi";
1403 reg = <0x0 0x 1400 reg = <0x0 0x00998000 0x0 0x4000>;
1404 clock-names = 1401 clock-names = "se";
1405 clocks = <&gc 1402 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1406 interrupts = 1403 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1407 pinctrl-names 1404 pinctrl-names = "default";
1408 pinctrl-0 = < 1405 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1409 interconnects 1406 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1410 1407 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1411 1408 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1412 interconnect- 1409 interconnect-names = "qup-core", "qup-config", "qup-memory";
1413 dmas = <&gpi_ 1410 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1414 <&gpi_ 1411 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1415 dma-names = " 1412 dma-names = "tx", "rx";
1416 #address-cell 1413 #address-cells = <1>;
1417 #size-cells = 1414 #size-cells = <0>;
1418 status = "dis 1415 status = "disabled";
1419 }; 1416 };
1420 1417
1421 uart7: serial@99c000 1418 uart7: serial@99c000 {
1422 compatible = 1419 compatible = "qcom,geni-debug-uart";
1423 reg = <0 0x00 1420 reg = <0 0x0099c000 0 0x4000>;
1424 clock-names = 1421 clock-names = "se";
1425 clocks = <&gc 1422 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1426 pinctrl-names 1423 pinctrl-names = "default";
1427 pinctrl-0 = < 1424 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>;
1428 interrupts = 1425 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1429 interconnects 1426 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1430 1427 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1431 1428 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1432 1429 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
1433 interconnect- 1430 interconnect-names = "qup-core",
1434 1431 "qup-config";
1435 status = "dis 1432 status = "disabled";
1436 }; 1433 };
1437 }; 1434 };
1438 1435
1439 gpi_dma1: dma-controller@a000 1436 gpi_dma1: dma-controller@a00000 {
1440 compatible = "qcom,sm 1437 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
1441 #dma-cells = <3>; 1438 #dma-cells = <3>;
1442 reg = <0 0x00a00000 0 1439 reg = <0 0x00a00000 0 0x60000>;
1443 interrupts = <GIC_SPI 1440 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1444 <GIC_SPI 1441 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1445 <GIC_SPI 1442 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1446 <GIC_SPI 1443 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1447 <GIC_SPI 1444 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1448 <GIC_SPI 1445 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1449 <GIC_SPI 1446 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1450 <GIC_SPI 1447 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1451 <GIC_SPI 1448 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1452 <GIC_SPI 1449 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1453 <GIC_SPI 1450 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1454 <GIC_SPI 1451 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
1455 dma-channels = <12>; 1452 dma-channels = <12>;
1456 dma-channel-mask = <0 1453 dma-channel-mask = <0x7e>;
1457 iommus = <&apps_smmu 1454 iommus = <&apps_smmu 0x56 0x0>;
1458 status = "disabled"; 1455 status = "disabled";
1459 }; 1456 };
1460 1457
1461 qupv3_id_1: geniqup@ac0000 { 1458 qupv3_id_1: geniqup@ac0000 {
1462 compatible = "qcom,ge 1459 compatible = "qcom,geni-se-qup";
1463 reg = <0x0 0x00ac0000 1460 reg = <0x0 0x00ac0000 0x0 0x6000>;
1464 clock-names = "m-ahb" 1461 clock-names = "m-ahb", "s-ahb";
1465 clocks = <&gcc GCC_QU 1462 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1466 <&gcc GCC_QU 1463 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1467 iommus = <&apps_smmu 1464 iommus = <&apps_smmu 0x43 0x0>;
1468 interconnects = <&clk 1465 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>;
1469 interconnect-names = 1466 interconnect-names = "qup-core";
1470 #address-cells = <2>; 1467 #address-cells = <2>;
1471 #size-cells = <2>; 1468 #size-cells = <2>;
1472 ranges; 1469 ranges;
1473 status = "disabled"; 1470 status = "disabled";
1474 1471
1475 i2c8: i2c@a80000 { 1472 i2c8: i2c@a80000 {
1476 compatible = 1473 compatible = "qcom,geni-i2c";
1477 reg = <0x0 0x 1474 reg = <0x0 0x00a80000 0x0 0x4000>;
1478 clock-names = 1475 clock-names = "se";
1479 clocks = <&gc 1476 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1480 pinctrl-names 1477 pinctrl-names = "default";
1481 pinctrl-0 = < 1478 pinctrl-0 = <&qup_i2c8_data_clk>;
1482 interrupts = 1479 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1483 #address-cell 1480 #address-cells = <1>;
1484 #size-cells = 1481 #size-cells = <0>;
1485 interconnects 1482 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1486 1483 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1487 1484 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1488 interconnect- 1485 interconnect-names = "qup-core", "qup-config", "qup-memory";
1489 dmas = <&gpi_ 1486 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1490 <&gpi_ 1487 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1491 dma-names = " 1488 dma-names = "tx", "rx";
1492 status = "dis 1489 status = "disabled";
1493 }; 1490 };
1494 1491
1495 spi8: spi@a80000 { 1492 spi8: spi@a80000 {
1496 compatible = 1493 compatible = "qcom,geni-spi";
1497 reg = <0x0 0x 1494 reg = <0x0 0x00a80000 0x0 0x4000>;
1498 clock-names = 1495 clock-names = "se";
1499 clocks = <&gc 1496 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1500 interrupts = 1497 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1501 pinctrl-names 1498 pinctrl-names = "default";
1502 pinctrl-0 = < 1499 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1503 interconnects 1500 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1504 1501 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1505 1502 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1506 interconnect- 1503 interconnect-names = "qup-core", "qup-config", "qup-memory";
1507 dmas = <&gpi_ 1504 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1508 <&gpi_ 1505 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1509 dma-names = " 1506 dma-names = "tx", "rx";
1510 #address-cell 1507 #address-cells = <1>;
1511 #size-cells = 1508 #size-cells = <0>;
1512 status = "dis 1509 status = "disabled";
1513 }; 1510 };
1514 1511
1515 i2c9: i2c@a84000 { 1512 i2c9: i2c@a84000 {
1516 compatible = 1513 compatible = "qcom,geni-i2c";
1517 reg = <0x0 0x 1514 reg = <0x0 0x00a84000 0x0 0x4000>;
1518 clock-names = 1515 clock-names = "se";
1519 clocks = <&gc 1516 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1520 pinctrl-names 1517 pinctrl-names = "default";
1521 pinctrl-0 = < 1518 pinctrl-0 = <&qup_i2c9_data_clk>;
1522 interrupts = 1519 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1523 #address-cell 1520 #address-cells = <1>;
1524 #size-cells = 1521 #size-cells = <0>;
1525 interconnects 1522 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1526 1523 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1527 1524 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1528 interconnect- 1525 interconnect-names = "qup-core", "qup-config", "qup-memory";
1529 dmas = <&gpi_ 1526 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1530 <&gpi_ 1527 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1531 dma-names = " 1528 dma-names = "tx", "rx";
1532 status = "dis 1529 status = "disabled";
1533 }; 1530 };
1534 1531
1535 spi9: spi@a84000 { 1532 spi9: spi@a84000 {
1536 compatible = 1533 compatible = "qcom,geni-spi";
1537 reg = <0x0 0x 1534 reg = <0x0 0x00a84000 0x0 0x4000>;
1538 clock-names = 1535 clock-names = "se";
1539 clocks = <&gc 1536 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1540 interrupts = 1537 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1541 pinctrl-names 1538 pinctrl-names = "default";
1542 pinctrl-0 = < 1539 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1543 interconnects 1540 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1544 1541 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1545 1542 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1546 interconnect- 1543 interconnect-names = "qup-core", "qup-config", "qup-memory";
1547 dmas = <&gpi_ 1544 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1548 <&gpi_ 1545 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1549 dma-names = " 1546 dma-names = "tx", "rx";
1550 #address-cell 1547 #address-cells = <1>;
1551 #size-cells = 1548 #size-cells = <0>;
1552 status = "dis 1549 status = "disabled";
1553 }; 1550 };
1554 1551
1555 i2c10: i2c@a88000 { 1552 i2c10: i2c@a88000 {
1556 compatible = 1553 compatible = "qcom,geni-i2c";
1557 reg = <0x0 0x 1554 reg = <0x0 0x00a88000 0x0 0x4000>;
1558 clock-names = 1555 clock-names = "se";
1559 clocks = <&gc 1556 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1560 pinctrl-names 1557 pinctrl-names = "default";
1561 pinctrl-0 = < 1558 pinctrl-0 = <&qup_i2c10_data_clk>;
1562 interrupts = 1559 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1563 #address-cell 1560 #address-cells = <1>;
1564 #size-cells = 1561 #size-cells = <0>;
1565 interconnects 1562 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1566 1563 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1567 1564 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1568 interconnect- 1565 interconnect-names = "qup-core", "qup-config", "qup-memory";
1569 dmas = <&gpi_ 1566 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1570 <&gpi_ 1567 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1571 dma-names = " 1568 dma-names = "tx", "rx";
1572 status = "dis 1569 status = "disabled";
1573 }; 1570 };
1574 1571
1575 spi10: spi@a88000 { 1572 spi10: spi@a88000 {
1576 compatible = 1573 compatible = "qcom,geni-spi";
1577 reg = <0x0 0x 1574 reg = <0x0 0x00a88000 0x0 0x4000>;
1578 clock-names = 1575 clock-names = "se";
1579 clocks = <&gc 1576 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1580 interrupts = 1577 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1581 pinctrl-names 1578 pinctrl-names = "default";
1582 pinctrl-0 = < 1579 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1583 interconnects 1580 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1584 1581 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1585 1582 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1586 interconnect- 1583 interconnect-names = "qup-core", "qup-config", "qup-memory";
1587 dmas = <&gpi_ 1584 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1588 <&gpi_ 1585 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1589 dma-names = " 1586 dma-names = "tx", "rx";
1590 #address-cell 1587 #address-cells = <1>;
1591 #size-cells = 1588 #size-cells = <0>;
1592 status = "dis 1589 status = "disabled";
1593 }; 1590 };
1594 1591
1595 i2c11: i2c@a8c000 { 1592 i2c11: i2c@a8c000 {
1596 compatible = 1593 compatible = "qcom,geni-i2c";
1597 reg = <0x0 0x 1594 reg = <0x0 0x00a8c000 0x0 0x4000>;
1598 clock-names = 1595 clock-names = "se";
1599 clocks = <&gc 1596 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1600 pinctrl-names 1597 pinctrl-names = "default";
1601 pinctrl-0 = < 1598 pinctrl-0 = <&qup_i2c11_data_clk>;
1602 interrupts = 1599 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1603 #address-cell 1600 #address-cells = <1>;
1604 #size-cells = 1601 #size-cells = <0>;
1605 interconnects 1602 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1606 1603 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1607 1604 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1608 interconnect- 1605 interconnect-names = "qup-core", "qup-config", "qup-memory";
1609 dmas = <&gpi_ 1606 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1610 <&gpi_ 1607 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1611 dma-names = " 1608 dma-names = "tx", "rx";
1612 status = "dis 1609 status = "disabled";
1613 }; 1610 };
1614 1611
1615 spi11: spi@a8c000 { 1612 spi11: spi@a8c000 {
1616 compatible = 1613 compatible = "qcom,geni-spi";
1617 reg = <0x0 0x 1614 reg = <0x0 0x00a8c000 0x0 0x4000>;
1618 clock-names = 1615 clock-names = "se";
1619 clocks = <&gc 1616 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1620 interrupts = 1617 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1621 pinctrl-names 1618 pinctrl-names = "default";
1622 pinctrl-0 = < 1619 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1623 interconnects 1620 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1624 1621 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1625 1622 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1626 interconnect- 1623 interconnect-names = "qup-core", "qup-config", "qup-memory";
1627 dmas = <&gpi_ 1624 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1628 <&gpi_ 1625 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1629 dma-names = " 1626 dma-names = "tx", "rx";
1630 #address-cell 1627 #address-cells = <1>;
1631 #size-cells = 1628 #size-cells = <0>;
1632 status = "dis 1629 status = "disabled";
1633 }; 1630 };
1634 1631
1635 i2c12: i2c@a90000 { 1632 i2c12: i2c@a90000 {
1636 compatible = 1633 compatible = "qcom,geni-i2c";
1637 reg = <0x0 0x 1634 reg = <0x0 0x00a90000 0x0 0x4000>;
1638 clock-names = 1635 clock-names = "se";
1639 clocks = <&gc 1636 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1640 pinctrl-names 1637 pinctrl-names = "default";
1641 pinctrl-0 = < 1638 pinctrl-0 = <&qup_i2c12_data_clk>;
1642 interrupts = 1639 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1643 #address-cell 1640 #address-cells = <1>;
1644 #size-cells = 1641 #size-cells = <0>;
1645 interconnects 1642 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1646 1643 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1647 1644 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1648 interconnect- 1645 interconnect-names = "qup-core", "qup-config", "qup-memory";
1649 dmas = <&gpi_ 1646 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1650 <&gpi_ 1647 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1651 dma-names = " 1648 dma-names = "tx", "rx";
1652 status = "dis 1649 status = "disabled";
1653 }; 1650 };
1654 1651
1655 spi12: spi@a90000 { 1652 spi12: spi@a90000 {
1656 compatible = 1653 compatible = "qcom,geni-spi";
1657 reg = <0x0 0x 1654 reg = <0x0 0x00a90000 0x0 0x4000>;
1658 clock-names = 1655 clock-names = "se";
1659 clocks = <&gc 1656 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1660 interrupts = 1657 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1661 pinctrl-names 1658 pinctrl-names = "default";
1662 pinctrl-0 = < 1659 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1663 interconnects 1660 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1664 1661 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1665 1662 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1666 interconnect- 1663 interconnect-names = "qup-core", "qup-config", "qup-memory";
1667 dmas = <&gpi_ 1664 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1668 <&gpi_ 1665 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1669 dma-names = " 1666 dma-names = "tx", "rx";
1670 #address-cell 1667 #address-cells = <1>;
1671 #size-cells = 1668 #size-cells = <0>;
1672 status = "dis 1669 status = "disabled";
1673 }; 1670 };
1674 1671
1675 i2c13: i2c@a94000 { 1672 i2c13: i2c@a94000 {
1676 compatible = 1673 compatible = "qcom,geni-i2c";
1677 reg = <0 0x00 1674 reg = <0 0x00a94000 0 0x4000>;
1678 clock-names = 1675 clock-names = "se";
1679 clocks = <&gc 1676 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1680 pinctrl-names 1677 pinctrl-names = "default";
1681 pinctrl-0 = < 1678 pinctrl-0 = <&qup_i2c13_data_clk>;
1682 interrupts = 1679 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1683 interconnects 1680 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1684 1681 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1685 1682 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1686 interconnect- 1683 interconnect-names = "qup-core", "qup-config", "qup-memory";
1687 dmas = <&gpi_ 1684 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1688 <&gpi_ 1685 <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1689 dma-names = " 1686 dma-names = "tx", "rx";
1690 #address-cell 1687 #address-cells = <1>;
1691 #size-cells = 1688 #size-cells = <0>;
1692 status = "dis 1689 status = "disabled";
1693 }; 1690 };
1694 1691
1695 spi13: spi@a94000 { 1692 spi13: spi@a94000 {
1696 compatible = 1693 compatible = "qcom,geni-spi";
1697 reg = <0x0 0x 1694 reg = <0x0 0x00a94000 0x0 0x4000>;
1698 clock-names = 1695 clock-names = "se";
1699 clocks = <&gc 1696 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1700 interrupts = 1697 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1701 pinctrl-names 1698 pinctrl-names = "default";
1702 pinctrl-0 = < 1699 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1703 interconnects 1700 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1704 1701 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1705 1702 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1706 interconnect- 1703 interconnect-names = "qup-core", "qup-config", "qup-memory";
1707 dmas = <&gpi_ 1704 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1708 <&gpi_ 1705 <&gpi_dma1 1 5 QCOM_GPI_SPI>;
1709 dma-names = " 1706 dma-names = "tx", "rx";
1710 #address-cell 1707 #address-cells = <1>;
1711 #size-cells = 1708 #size-cells = <0>;
1712 status = "dis 1709 status = "disabled";
1713 }; 1710 };
1714 1711
1715 i2c14: i2c@a98000 { 1712 i2c14: i2c@a98000 {
1716 compatible = 1713 compatible = "qcom,geni-i2c";
1717 reg = <0 0x00 1714 reg = <0 0x00a98000 0 0x4000>;
1718 clock-names = 1715 clock-names = "se";
1719 clocks = <&gc 1716 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1720 pinctrl-names 1717 pinctrl-names = "default";
1721 pinctrl-0 = < 1718 pinctrl-0 = <&qup_i2c14_data_clk>;
1722 interrupts = 1719 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
1723 interconnects 1720 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1724 1721 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1725 1722 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1726 interconnect- 1723 interconnect-names = "qup-core", "qup-config", "qup-memory";
1727 dmas = <&gpi_ 1724 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
1728 <&gpi_ 1725 <&gpi_dma1 1 6 QCOM_GPI_I2C>;
1729 dma-names = " 1726 dma-names = "tx", "rx";
1730 #address-cell 1727 #address-cells = <1>;
1731 #size-cells = 1728 #size-cells = <0>;
1732 status = "dis 1729 status = "disabled";
1733 }; 1730 };
1734 1731
1735 spi14: spi@a98000 { 1732 spi14: spi@a98000 {
1736 compatible = 1733 compatible = "qcom,geni-spi";
1737 reg = <0x0 0x 1734 reg = <0x0 0x00a98000 0x0 0x4000>;
1738 clock-names = 1735 clock-names = "se";
1739 clocks = <&gc 1736 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1740 interrupts = 1737 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
1741 pinctrl-names 1738 pinctrl-names = "default";
1742 pinctrl-0 = < 1739 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
1743 interconnects 1740 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1744 1741 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1745 1742 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1746 interconnect- 1743 interconnect-names = "qup-core", "qup-config", "qup-memory";
1747 dmas = <&gpi_ 1744 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
1748 <&gpi_ 1745 <&gpi_dma1 1 6 QCOM_GPI_SPI>;
1749 dma-names = " 1746 dma-names = "tx", "rx";
1750 #address-cell 1747 #address-cells = <1>;
1751 #size-cells = 1748 #size-cells = <0>;
1752 status = "dis 1749 status = "disabled";
1753 }; 1750 };
1754 }; 1751 };
1755 1752
1756 rng: rng@10c3000 { 1753 rng: rng@10c3000 {
1757 compatible = "qcom,sm !! 1754 compatible = "qcom,sm8450-prng-ee", "qcom,prng-ee";
1758 reg = <0 0x010c3000 0 1755 reg = <0 0x010c3000 0 0x1000>;
1759 }; 1756 };
1760 1757
1761 pcie0: pcie@1c00000 { !! 1758 pcie0: pci@1c00000 {
1762 compatible = "qcom,pc 1759 compatible = "qcom,pcie-sm8450-pcie0";
1763 reg = <0 0x01c00000 0 1760 reg = <0 0x01c00000 0 0x3000>,
1764 <0 0x60000000 0 1761 <0 0x60000000 0 0xf1d>,
1765 <0 0x60000f20 0 1762 <0 0x60000f20 0 0xa8>,
1766 <0 0x60001000 0 1763 <0 0x60001000 0 0x1000>,
1767 <0 0x60100000 0 1764 <0 0x60100000 0 0x100000>;
1768 reg-names = "parf", " 1765 reg-names = "parf", "dbi", "elbi", "atu", "config";
1769 device_type = "pci"; 1766 device_type = "pci";
1770 linux,pci-domain = <0 1767 linux,pci-domain = <0>;
1771 bus-range = <0x00 0xf 1768 bus-range = <0x00 0xff>;
1772 num-lanes = <1>; 1769 num-lanes = <1>;
1773 1770
1774 #address-cells = <3>; 1771 #address-cells = <3>;
1775 #size-cells = <2>; 1772 #size-cells = <2>;
1776 1773
1777 ranges = <0x01000000 1774 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
1778 <0x02000000 1775 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1779 1776
1780 msi-map = <0x0 &gic_i 1777 msi-map = <0x0 &gic_its 0x5980 0x1>,
1781 <0x100 &gic 1778 <0x100 &gic_its 0x5981 0x1>;
1782 msi-map-mask = <0xff0 1779 msi-map-mask = <0xff00>;
1783 interrupts = <GIC_SPI !! 1780 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
1784 <GIC_SPI !! 1781 interrupt-names = "msi";
1785 <GIC_SPI <<
1786 <GIC_SPI <<
1787 <GIC_SPI <<
1788 <GIC_SPI <<
1789 <GIC_SPI <<
1790 <GIC_SPI <<
1791 interrupt-names = "ms <<
1792 "ms <<
1793 "ms <<
1794 "ms <<
1795 "ms <<
1796 "ms <<
1797 "ms <<
1798 "ms <<
1799 #interrupt-cells = <1 1782 #interrupt-cells = <1>;
1800 interrupt-map-mask = 1783 interrupt-map-mask = <0 0 0 0x7>;
1801 interrupt-map = <0 0 1784 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1802 <0 0 1785 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1803 <0 0 1786 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1804 <0 0 1787 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1805 1788
1806 interconnects = <&pci <<
1807 &mc_ <<
1808 <&gem <<
1809 &con <<
1810 interconnect-names = <<
1811 <<
1812 clocks = <&gcc GCC_PC 1789 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1813 <&gcc GCC_PC 1790 <&gcc GCC_PCIE_0_PIPE_CLK_SRC>,
1814 <&pcie0_phy> !! 1791 <&pcie0_lane>,
1815 <&rpmhcc RPM 1792 <&rpmhcc RPMH_CXO_CLK>,
1816 <&gcc GCC_PC 1793 <&gcc GCC_PCIE_0_AUX_CLK>,
1817 <&gcc GCC_PC 1794 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1818 <&gcc GCC_PC 1795 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1819 <&gcc GCC_PC 1796 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1820 <&gcc GCC_PC 1797 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
1821 <&gcc GCC_DD 1798 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1822 <&gcc GCC_AG 1799 <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
1823 <&gcc GCC_AG 1800 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
1824 clock-names = "pipe", 1801 clock-names = "pipe",
1825 "pipe_m 1802 "pipe_mux",
1826 "phy_pi 1803 "phy_pipe",
1827 "ref", 1804 "ref",
1828 "aux", 1805 "aux",
1829 "cfg", 1806 "cfg",
1830 "bus_ma 1807 "bus_master",
1831 "bus_sl 1808 "bus_slave",
1832 "slave_ 1809 "slave_q2a",
1833 "ddrss_ 1810 "ddrss_sf_tbu",
1834 "aggre0 1811 "aggre0",
1835 "aggre1 1812 "aggre1";
1836 1813
1837 iommu-map = <0x0 &a 1814 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
1838 <0x100 &a 1815 <0x100 &apps_smmu 0x1c01 0x1>;
1839 1816
1840 resets = <&gcc GCC_PC 1817 resets = <&gcc GCC_PCIE_0_BCR>;
1841 reset-names = "pci"; 1818 reset-names = "pci";
1842 1819
1843 power-domains = <&gcc 1820 power-domains = <&gcc PCIE_0_GDSC>;
1844 1821
1845 phys = <&pcie0_phy>; !! 1822 phys = <&pcie0_lane>;
1846 phy-names = "pciephy" 1823 phy-names = "pciephy";
1847 1824
1848 perst-gpios = <&tlmm 1825 perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
1849 wake-gpios = <&tlmm 9 1826 wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
1850 1827
1851 pinctrl-names = "defa 1828 pinctrl-names = "default";
1852 pinctrl-0 = <&pcie0_d 1829 pinctrl-0 = <&pcie0_default_state>;
1853 1830
1854 operating-points-v2 = <<
1855 <<
1856 status = "disabled"; 1831 status = "disabled";
1857 <<
1858 pcie0_opp_table: opp- <<
1859 compatible = <<
1860 <<
1861 /* GEN 1 x1 * <<
1862 opp-2500000 { <<
1863 opp-h <<
1864 requi <<
1865 opp-p <<
1866 }; <<
1867 <<
1868 /* GEN 2 x1 * <<
1869 opp-5000000 { <<
1870 opp-h <<
1871 requi <<
1872 opp-p <<
1873 }; <<
1874 <<
1875 /* GEN 3 x1 * <<
1876 opp-8000000 { <<
1877 opp-h <<
1878 requi <<
1879 opp-p <<
1880 }; <<
1881 }; <<
1882 <<
1883 pcie@0 { <<
1884 device_type = <<
1885 reg = <0x0 0x <<
1886 bus-range = < <<
1887 <<
1888 #address-cell <<
1889 #size-cells = <<
1890 ranges; <<
1891 }; <<
1892 }; 1832 };
1893 1833
1894 pcie0_phy: phy@1c06000 { 1834 pcie0_phy: phy@1c06000 {
1895 compatible = "qcom,sm 1835 compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy";
1896 reg = <0 0x01c06000 0 !! 1836 reg = <0 0x01c06000 0 0x200>;
1897 !! 1837 #address-cells = <2>;
>> 1838 #size-cells = <2>;
>> 1839 ranges;
1898 clocks = <&gcc GCC_PC 1840 clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
1899 <&gcc GCC_PC 1841 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1900 <&gcc GCC_PC 1842 <&gcc GCC_PCIE_0_CLKREF_EN>,
1901 <&gcc GCC_PC !! 1843 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
1902 <&gcc GCC_PC !! 1844 clock-names = "aux", "cfg_ahb", "ref", "refgen";
1903 clock-names = "aux", <<
1904 "cfg_ah <<
1905 "ref", <<
1906 "rchng" <<
1907 "pipe"; <<
1908 <<
1909 clock-output-names = <<
1910 #clock-cells = <0>; <<
1911 <<
1912 #phy-cells = <0>; <<
1913 1845
1914 resets = <&gcc GCC_PC 1846 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1915 reset-names = "phy"; 1847 reset-names = "phy";
1916 1848
1917 assigned-clocks = <&g 1849 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
1918 assigned-clock-rates 1850 assigned-clock-rates = <100000000>;
1919 1851
1920 status = "disabled"; 1852 status = "disabled";
>> 1853
>> 1854 pcie0_lane: phy@1c06200 {
>> 1855 reg = <0 0x01c06e00 0 0x200>, /* tx */
>> 1856 <0 0x01c07000 0 0x200>, /* rx */
>> 1857 <0 0x01c06200 0 0x200>, /* pcs */
>> 1858 <0 0x01c06600 0 0x200>; /* pcs_pcie */
>> 1859 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
>> 1860 clock-names = "pipe0";
>> 1861
>> 1862 #clock-cells = <0>;
>> 1863 #phy-cells = <0>;
>> 1864 clock-output-names = "pcie_0_pipe_clk";
>> 1865 };
1921 }; 1866 };
1922 1867
1923 pcie1: pcie@1c08000 { !! 1868 pcie1: pci@1c08000 {
1924 compatible = "qcom,pc 1869 compatible = "qcom,pcie-sm8450-pcie1";
1925 reg = <0 0x01c08000 0 1870 reg = <0 0x01c08000 0 0x3000>,
1926 <0 0x40000000 0 1871 <0 0x40000000 0 0xf1d>,
1927 <0 0x40000f20 0 1872 <0 0x40000f20 0 0xa8>,
1928 <0 0x40001000 0 1873 <0 0x40001000 0 0x1000>,
1929 <0 0x40100000 0 1874 <0 0x40100000 0 0x100000>;
1930 reg-names = "parf", " 1875 reg-names = "parf", "dbi", "elbi", "atu", "config";
1931 device_type = "pci"; 1876 device_type = "pci";
1932 linux,pci-domain = <1 1877 linux,pci-domain = <1>;
1933 bus-range = <0x00 0xf 1878 bus-range = <0x00 0xff>;
1934 num-lanes = <2>; 1879 num-lanes = <2>;
1935 1880
1936 #address-cells = <3>; 1881 #address-cells = <3>;
1937 #size-cells = <2>; 1882 #size-cells = <2>;
1938 1883
1939 ranges = <0x01000000 1884 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
1940 <0x02000000 1885 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1941 1886
1942 msi-map = <0x0 &gic_i 1887 msi-map = <0x0 &gic_its 0x5a00 0x1>,
1943 <0x100 &gic 1888 <0x100 &gic_its 0x5a01 0x1>;
1944 msi-map-mask = <0xff0 1889 msi-map-mask = <0xff00>;
1945 interrupts = <GIC_SPI !! 1890 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
1946 <GIC_SPI !! 1891 interrupt-names = "msi";
1947 <GIC_SPI <<
1948 <GIC_SPI <<
1949 <GIC_SPI <<
1950 <GIC_SPI <<
1951 <GIC_SPI <<
1952 <GIC_SPI <<
1953 interrupt-names = "ms <<
1954 "ms <<
1955 "ms <<
1956 "ms <<
1957 "ms <<
1958 "ms <<
1959 "ms <<
1960 "ms <<
1961 #interrupt-cells = <1 1892 #interrupt-cells = <1>;
1962 interrupt-map-mask = 1893 interrupt-map-mask = <0 0 0 0x7>;
1963 interrupt-map = <0 0 1894 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1964 <0 0 1895 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1965 <0 0 1896 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1966 <0 0 1897 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1967 1898
1968 interconnects = <&pci <<
1969 &mc_ <<
1970 <&gem <<
1971 &con <<
1972 interconnect-names = <<
1973 <<
1974 clocks = <&gcc GCC_PC 1899 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1975 <&gcc GCC_PC 1900 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>,
1976 <&pcie1_phy !! 1901 <&pcie1_lane>,
1977 <&rpmhcc RPM 1902 <&rpmhcc RPMH_CXO_CLK>,
1978 <&gcc GCC_PC 1903 <&gcc GCC_PCIE_1_AUX_CLK>,
1979 <&gcc GCC_PC 1904 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1980 <&gcc GCC_PC 1905 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1981 <&gcc GCC_PC 1906 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
1982 <&gcc GCC_PC 1907 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
1983 <&gcc GCC_DD 1908 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1984 <&gcc GCC_AG 1909 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
1985 clock-names = "pipe", 1910 clock-names = "pipe",
1986 "pipe_m 1911 "pipe_mux",
1987 "phy_pi 1912 "phy_pipe",
1988 "ref", 1913 "ref",
1989 "aux", 1914 "aux",
1990 "cfg", 1915 "cfg",
1991 "bus_ma 1916 "bus_master",
1992 "bus_sl 1917 "bus_slave",
1993 "slave_ 1918 "slave_q2a",
1994 "ddrss_ 1919 "ddrss_sf_tbu",
1995 "aggre1 1920 "aggre1";
1996 1921
1997 iommu-map = <0x0 &a 1922 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
1998 <0x100 &a 1923 <0x100 &apps_smmu 0x1c81 0x1>;
1999 1924
2000 resets = <&gcc GCC_PC 1925 resets = <&gcc GCC_PCIE_1_BCR>;
2001 reset-names = "pci"; 1926 reset-names = "pci";
2002 1927
2003 power-domains = <&gcc 1928 power-domains = <&gcc PCIE_1_GDSC>;
2004 1929
2005 phys = <&pcie1_phy>; !! 1930 phys = <&pcie1_lane>;
2006 phy-names = "pciephy" 1931 phy-names = "pciephy";
2007 1932
2008 perst-gpios = <&tlmm 1933 perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
2009 wake-gpios = <&tlmm 9 1934 wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
2010 1935
2011 pinctrl-names = "defa 1936 pinctrl-names = "default";
2012 pinctrl-0 = <&pcie1_d 1937 pinctrl-0 = <&pcie1_default_state>;
2013 1938
2014 operating-points-v2 = <<
2015 <<
2016 status = "disabled"; 1939 status = "disabled";
2017 <<
2018 pcie1_opp_table: opp- <<
2019 compatible = <<
2020 <<
2021 /* GEN 1 x1 * <<
2022 opp-2500000 { <<
2023 opp-h <<
2024 requi <<
2025 opp-p <<
2026 }; <<
2027 <<
2028 /* GEN 1 x2 a <<
2029 opp-5000000 { <<
2030 opp-h <<
2031 requi <<
2032 opp-p <<
2033 }; <<
2034 <<
2035 /* GEN 2 x2 * <<
2036 opp-10000000 <<
2037 opp-h <<
2038 requi <<
2039 opp-p <<
2040 }; <<
2041 <<
2042 /* GEN 3 x1 * <<
2043 opp-8000000 { <<
2044 opp-h <<
2045 requi <<
2046 opp-p <<
2047 }; <<
2048 <<
2049 /* GEN 3 x2 a <<
2050 opp-16000000 <<
2051 opp-h <<
2052 requi <<
2053 opp-p <<
2054 }; <<
2055 <<
2056 /* GEN 4 x2 * <<
2057 opp-32000000 <<
2058 opp-h <<
2059 requi <<
2060 opp-p <<
2061 }; <<
2062 }; <<
2063 <<
2064 pcie@0 { <<
2065 device_type = <<
2066 reg = <0x0 0x <<
2067 bus-range = < <<
2068 <<
2069 #address-cell <<
2070 #size-cells = <<
2071 ranges; <<
2072 }; <<
2073 }; 1940 };
2074 1941
2075 pcie1_phy: phy@1c0e000 { !! 1942 pcie1_phy: phy@1c0f000 {
2076 compatible = "qcom,sm 1943 compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy";
2077 reg = <0 0x01c0e000 0 !! 1944 reg = <0 0x01c0f000 0 0x200>;
2078 !! 1945 #address-cells = <2>;
>> 1946 #size-cells = <2>;
>> 1947 ranges;
2079 clocks = <&gcc GCC_PC 1948 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>,
2080 <&gcc GCC_PC 1949 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2081 <&gcc GCC_PC 1950 <&gcc GCC_PCIE_1_CLKREF_EN>,
2082 <&gcc GCC_PC !! 1951 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
2083 <&gcc GCC_PC !! 1952 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2084 clock-names = "aux", <<
2085 "cfg_ah <<
2086 "ref", <<
2087 "rchng" <<
2088 "pipe"; <<
2089 <<
2090 clock-output-names = <<
2091 #clock-cells = <1>; <<
2092 <<
2093 #phy-cells = <0>; <<
2094 1953
2095 resets = <&gcc GCC_PC 1954 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2096 reset-names = "phy"; 1955 reset-names = "phy";
2097 1956
2098 assigned-clocks = <&g 1957 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
2099 assigned-clock-rates 1958 assigned-clock-rates = <100000000>;
2100 1959
2101 status = "disabled"; 1960 status = "disabled";
>> 1961
>> 1962 pcie1_lane: phy@1c0e000 {
>> 1963 reg = <0 0x01c0e000 0 0x200>, /* tx */
>> 1964 <0 0x01c0e200 0 0x300>, /* rx */
>> 1965 <0 0x01c0f200 0 0x200>, /* pcs */
>> 1966 <0 0x01c0e800 0 0x200>, /* tx */
>> 1967 <0 0x01c0ea00 0 0x300>, /* rx */
>> 1968 <0 0x01c0f400 0 0xc00>; /* pcs_pcie */
>> 1969 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
>> 1970 clock-names = "pipe0";
>> 1971
>> 1972 #clock-cells = <0>;
>> 1973 #phy-cells = <0>;
>> 1974 clock-output-names = "pcie_1_pipe_clk";
>> 1975 };
2102 }; 1976 };
2103 1977
2104 config_noc: interconnect@1500 1978 config_noc: interconnect@1500000 {
2105 compatible = "qcom,sm 1979 compatible = "qcom,sm8450-config-noc";
2106 reg = <0 0x01500000 0 1980 reg = <0 0x01500000 0 0x1c000>;
2107 #interconnect-cells = 1981 #interconnect-cells = <2>;
2108 qcom,bcm-voters = <&a 1982 qcom,bcm-voters = <&apps_bcm_voter>;
2109 }; 1983 };
2110 1984
2111 system_noc: interconnect@1680 1985 system_noc: interconnect@1680000 {
2112 compatible = "qcom,sm 1986 compatible = "qcom,sm8450-system-noc";
2113 reg = <0 0x01680000 0 1987 reg = <0 0x01680000 0 0x1e200>;
2114 #interconnect-cells = 1988 #interconnect-cells = <2>;
2115 qcom,bcm-voters = <&a 1989 qcom,bcm-voters = <&apps_bcm_voter>;
2116 }; 1990 };
2117 1991
2118 pcie_noc: interconnect@16c000 1992 pcie_noc: interconnect@16c0000 {
2119 compatible = "qcom,sm 1993 compatible = "qcom,sm8450-pcie-anoc";
2120 reg = <0 0x016c0000 0 1994 reg = <0 0x016c0000 0 0xe280>;
2121 #interconnect-cells = 1995 #interconnect-cells = <2>;
2122 qcom,bcm-voters = <&a 1996 qcom,bcm-voters = <&apps_bcm_voter>;
2123 }; 1997 };
2124 1998
2125 aggre1_noc: interconnect@16e0 1999 aggre1_noc: interconnect@16e0000 {
2126 compatible = "qcom,sm 2000 compatible = "qcom,sm8450-aggre1-noc";
2127 reg = <0 0x016e0000 0 2001 reg = <0 0x016e0000 0 0x1c080>;
2128 #interconnect-cells = 2002 #interconnect-cells = <2>;
2129 clocks = <&gcc GCC_AG 2003 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2130 <&gcc GCC_AG 2004 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
2131 qcom,bcm-voters = <&a 2005 qcom,bcm-voters = <&apps_bcm_voter>;
2132 }; 2006 };
2133 2007
2134 aggre2_noc: interconnect@1700 2008 aggre2_noc: interconnect@1700000 {
2135 compatible = "qcom,sm 2009 compatible = "qcom,sm8450-aggre2-noc";
2136 reg = <0 0x01700000 0 2010 reg = <0 0x01700000 0 0x31080>;
2137 #interconnect-cells = 2011 #interconnect-cells = <2>;
2138 qcom,bcm-voters = <&a 2012 qcom,bcm-voters = <&apps_bcm_voter>;
2139 clocks = <&gcc GCC_AG 2013 clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
2140 <&gcc GCC_AG 2014 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
2141 <&gcc GCC_AG 2015 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2142 <&rpmhcc RPM 2016 <&rpmhcc RPMH_IPA_CLK>;
2143 }; 2017 };
2144 2018
2145 mmss_noc: interconnect@174000 2019 mmss_noc: interconnect@1740000 {
2146 compatible = "qcom,sm 2020 compatible = "qcom,sm8450-mmss-noc";
2147 reg = <0 0x01740000 0 2021 reg = <0 0x01740000 0 0x1f080>;
2148 #interconnect-cells = 2022 #interconnect-cells = <2>;
2149 qcom,bcm-voters = <&a 2023 qcom,bcm-voters = <&apps_bcm_voter>;
2150 }; 2024 };
2151 2025
2152 tcsr_mutex: hwlock@1f40000 { 2026 tcsr_mutex: hwlock@1f40000 {
2153 compatible = "qcom,tc 2027 compatible = "qcom,tcsr-mutex";
2154 reg = <0x0 0x01f40000 2028 reg = <0x0 0x01f40000 0x0 0x40000>;
2155 #hwlock-cells = <1>; 2029 #hwlock-cells = <1>;
2156 }; 2030 };
2157 2031
2158 tcsr: syscon@1fc0000 { 2032 tcsr: syscon@1fc0000 {
2159 compatible = "qcom,sm 2033 compatible = "qcom,sm8450-tcsr", "syscon";
2160 reg = <0x0 0x1fc0000 2034 reg = <0x0 0x1fc0000 0x0 0x30000>;
2161 }; 2035 };
2162 2036
2163 gpu: gpu@3d00000 { <<
2164 compatible = "qcom,ad <<
2165 reg = <0x0 0x03d00000 <<
2166 <0x0 0x03d9e000 <<
2167 <0x0 0x03d61000 <<
2168 reg-names = "kgsl_3d0 <<
2169 "cx_mem", <<
2170 "cx_dbgc" <<
2171 <<
2172 interrupts = <GIC_SPI <<
2173 <<
2174 iommus = <&adreno_smm <<
2175 <&adreno_smm <<
2176 <<
2177 operating-points-v2 = <<
2178 <<
2179 qcom,gmu = <&gmu>; <<
2180 #cooling-cells = <2>; <<
2181 <<
2182 status = "disabled"; <<
2183 <<
2184 zap-shader { <<
2185 memory-region <<
2186 }; <<
2187 <<
2188 gpu_opp_table: opp-ta <<
2189 compatible = <<
2190 <<
2191 opp-818000000 <<
2192 opp-h <<
2193 opp-l <<
2194 }; <<
2195 <<
2196 opp-791000000 <<
2197 opp-h <<
2198 opp-l <<
2199 }; <<
2200 <<
2201 opp-734000000 <<
2202 opp-h <<
2203 opp-l <<
2204 }; <<
2205 <<
2206 opp-640000000 <<
2207 opp-h <<
2208 opp-l <<
2209 }; <<
2210 <<
2211 opp-599000000 <<
2212 opp-h <<
2213 opp-l <<
2214 }; <<
2215 <<
2216 opp-545000000 <<
2217 opp-h <<
2218 opp-l <<
2219 }; <<
2220 <<
2221 opp-492000000 <<
2222 opp-h <<
2223 opp-l <<
2224 }; <<
2225 <<
2226 opp-421000000 <<
2227 opp-h <<
2228 opp-l <<
2229 }; <<
2230 <<
2231 opp-350000000 <<
2232 opp-h <<
2233 opp-l <<
2234 }; <<
2235 <<
2236 opp-317000000 <<
2237 opp-h <<
2238 opp-l <<
2239 }; <<
2240 <<
2241 opp-285000000 <<
2242 opp-h <<
2243 opp-l <<
2244 }; <<
2245 <<
2246 opp-220000000 <<
2247 opp-h <<
2248 opp-l <<
2249 }; <<
2250 }; <<
2251 }; <<
2252 <<
2253 gmu: gmu@3d6a000 { <<
2254 compatible = "qcom,ad <<
2255 reg = <0x0 0x03d6a000 <<
2256 <0x0 0x03d50000 <<
2257 <0x0 0x0b290000 <<
2258 reg-names = "gmu", "r <<
2259 <<
2260 interrupts = <GIC_SPI <<
2261 <GIC_SPI <<
2262 interrupt-names = "hf <<
2263 <<
2264 clocks = <&gpucc GPU_ <<
2265 <&gpucc GPU_ <<
2266 <&gpucc GPU_ <<
2267 <&gcc GCC_DD <<
2268 <&gcc GCC_GP <<
2269 <&gpucc GPU_ <<
2270 <&gpucc GPU_ <<
2271 clock-names = "ahb", <<
2272 "gmu", <<
2273 "cxo", <<
2274 "axi", <<
2275 "memnoc <<
2276 "hub", <<
2277 "demet" <<
2278 <<
2279 power-domains = <&gpu <<
2280 <&gpu <<
2281 power-domain-names = <<
2282 <<
2283 <<
2284 iommus = <&adreno_smm <<
2285 <<
2286 qcom,qmp = <&aoss_qmp <<
2287 <<
2288 operating-points-v2 = <<
2289 <<
2290 gmu_opp_table: opp-ta <<
2291 compatible = <<
2292 <<
2293 opp-500000000 <<
2294 opp-h <<
2295 opp-l <<
2296 }; <<
2297 <<
2298 opp-200000000 <<
2299 opp-h <<
2300 opp-l <<
2301 }; <<
2302 }; <<
2303 }; <<
2304 <<
2305 gpucc: clock-controller@3d900 <<
2306 compatible = "qcom,sm <<
2307 reg = <0x0 0x03d90000 <<
2308 clocks = <&rpmhcc RPM <<
2309 <&gcc GCC_GP <<
2310 <&gcc GCC_GP <<
2311 #clock-cells = <1>; <<
2312 #reset-cells = <1>; <<
2313 #power-domain-cells = <<
2314 }; <<
2315 <<
2316 adreno_smmu: iommu@3da0000 { <<
2317 compatible = "qcom,sm <<
2318 "qcom,sm <<
2319 reg = <0x0 0x03da0000 <<
2320 #iommu-cells = <2>; <<
2321 #global-interrupts = <<
2322 interrupts = <GIC_SPI <<
2323 <GIC_SPI <<
2324 <GIC_SPI <<
2325 <GIC_SPI <<
2326 <GIC_SPI <<
2327 <GIC_SPI <<
2328 <GIC_SPI <<
2329 <GIC_SPI <<
2330 <GIC_SPI <<
2331 <GIC_SPI <<
2332 <GIC_SPI <<
2333 <GIC_SPI <<
2334 <GIC_SPI <<
2335 <GIC_SPI <<
2336 <GIC_SPI <<
2337 <GIC_SPI <<
2338 <GIC_SPI <<
2339 <GIC_SPI <<
2340 <GIC_SPI <<
2341 <GIC_SPI <<
2342 <GIC_SPI <<
2343 <GIC_SPI <<
2344 <GIC_SPI <<
2345 <GIC_SPI <<
2346 <GIC_SPI <<
2347 <GIC_SPI <<
2348 clocks = <&gpucc GPU_ <<
2349 <&gpucc GPU_ <<
2350 <&gpucc GPU_ <<
2351 <&gcc GCC_GP <<
2352 <&gcc GCC_GP <<
2353 <&gpucc GPU_ <<
2354 clock-names = "gmu", <<
2355 "hub", <<
2356 "hlos", <<
2357 "bus", <<
2358 "iface" <<
2359 "ahb"; <<
2360 power-domains = <&gpu <<
2361 dma-coherent; <<
2362 }; <<
2363 <<
2364 usb_1_hsphy: phy@88e3000 { 2037 usb_1_hsphy: phy@88e3000 {
2365 compatible = "qcom,sm 2038 compatible = "qcom,sm8450-usb-hs-phy",
2366 "qcom,us 2039 "qcom,usb-snps-hs-7nm-phy";
2367 reg = <0 0x088e3000 0 2040 reg = <0 0x088e3000 0 0x400>;
2368 status = "disabled"; 2041 status = "disabled";
2369 #phy-cells = <0>; 2042 #phy-cells = <0>;
2370 2043
2371 clocks = <&rpmhcc RPM 2044 clocks = <&rpmhcc RPMH_CXO_CLK>;
2372 clock-names = "ref"; 2045 clock-names = "ref";
2373 2046
2374 resets = <&gcc GCC_QU 2047 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2375 }; 2048 };
2376 2049
2377 usb_1_qmpphy: phy@88e8000 { 2050 usb_1_qmpphy: phy@88e8000 {
2378 compatible = "qcom,sm 2051 compatible = "qcom,sm8450-qmp-usb3-dp-phy";
2379 reg = <0 0x088e8000 0 2052 reg = <0 0x088e8000 0 0x3000>;
2380 2053
2381 clocks = <&gcc GCC_US 2054 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2382 <&rpmhcc RPM 2055 <&rpmhcc RPMH_CXO_CLK>,
2383 <&gcc GCC_US 2056 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
2384 <&gcc GCC_US 2057 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2385 clock-names = "aux", 2058 clock-names = "aux", "ref", "com_aux", "usb3_pipe";
2386 2059
2387 resets = <&gcc GCC_US 2060 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
2388 <&gcc GCC_US 2061 <&gcc GCC_USB3_PHY_PRIM_BCR>;
2389 reset-names = "phy", 2062 reset-names = "phy", "common";
2390 2063
2391 #clock-cells = <1>; 2064 #clock-cells = <1>;
2392 #phy-cells = <1>; 2065 #phy-cells = <1>;
2393 2066
2394 orientation-switch; <<
2395 <<
2396 status = "disabled"; 2067 status = "disabled";
2397 2068
2398 ports { 2069 ports {
2399 #address-cell 2070 #address-cells = <1>;
2400 #size-cells = 2071 #size-cells = <0>;
2401 2072
2402 port@0 { 2073 port@0 {
2403 reg = 2074 reg = <0>;
2404 2075
2405 usb_1 2076 usb_1_qmpphy_out: endpoint {
2406 }; 2077 };
2407 }; 2078 };
2408 2079
2409 port@1 { 2080 port@1 {
2410 reg = 2081 reg = <1>;
2411 2082
2412 usb_1 2083 usb_1_qmpphy_usb_ss_in: endpoint {
2413 <<
2414 }; 2084 };
2415 }; 2085 };
2416 2086
2417 port@2 { 2087 port@2 {
2418 reg = 2088 reg = <2>;
2419 2089
2420 usb_1 2090 usb_1_qmpphy_dp_in: endpoint {
2421 <<
2422 }; 2091 };
2423 }; 2092 };
2424 }; 2093 };
2425 }; 2094 };
2426 2095
2427 remoteproc_slpi: remoteproc@2 2096 remoteproc_slpi: remoteproc@2400000 {
2428 compatible = "qcom,sm 2097 compatible = "qcom,sm8450-slpi-pas";
2429 reg = <0 0x02400000 0 2098 reg = <0 0x02400000 0 0x4000>;
2430 2099
2431 interrupts-extended = 2100 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>,
2432 2101 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
2433 2102 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
2434 2103 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
2435 2104 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
2436 interrupt-names = "wd 2105 interrupt-names = "wdog", "fatal", "ready",
2437 "ha 2106 "handover", "stop-ack";
2438 2107
2439 clocks = <&rpmhcc RPM 2108 clocks = <&rpmhcc RPMH_CXO_CLK>;
2440 clock-names = "xo"; 2109 clock-names = "xo";
2441 2110
2442 power-domains = <&rpm 2111 power-domains = <&rpmhpd RPMHPD_LCX>,
2443 <&rpm 2112 <&rpmhpd RPMHPD_LMX>;
2444 power-domain-names = 2113 power-domain-names = "lcx", "lmx";
2445 2114
2446 memory-region = <&slp 2115 memory-region = <&slpi_mem>;
2447 2116
2448 qcom,qmp = <&aoss_qmp 2117 qcom,qmp = <&aoss_qmp>;
2449 2118
2450 qcom,smem-states = <& 2119 qcom,smem-states = <&smp2p_slpi_out 0>;
2451 qcom,smem-state-names 2120 qcom,smem-state-names = "stop";
2452 2121
2453 status = "disabled"; 2122 status = "disabled";
2454 2123
2455 glink-edge { 2124 glink-edge {
2456 interrupts-ex 2125 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
2457 2126 IPCC_MPROC_SIGNAL_GLINK_QMP
2458 2127 IRQ_TYPE_EDGE_RISING>;
2459 mboxes = <&ip 2128 mboxes = <&ipcc IPCC_CLIENT_SLPI
2460 2129 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2461 2130
2462 label = "slpi 2131 label = "slpi";
2463 qcom,remote-p 2132 qcom,remote-pid = <3>;
2464 2133
2465 fastrpc { 2134 fastrpc {
2466 compa 2135 compatible = "qcom,fastrpc";
2467 qcom, 2136 qcom,glink-channels = "fastrpcglink-apps-dsp";
2468 label 2137 label = "sdsp";
2469 qcom, <<
2470 #addr 2138 #address-cells = <1>;
2471 #size 2139 #size-cells = <0>;
2472 2140
2473 compu 2141 compute-cb@1 {
2474 2142 compatible = "qcom,fastrpc-compute-cb";
2475 2143 reg = <1>;
2476 2144 iommus = <&apps_smmu 0x0541 0x0>;
2477 }; 2145 };
2478 2146
2479 compu 2147 compute-cb@2 {
2480 2148 compatible = "qcom,fastrpc-compute-cb";
2481 2149 reg = <2>;
2482 2150 iommus = <&apps_smmu 0x0542 0x0>;
2483 }; 2151 };
2484 2152
2485 compu 2153 compute-cb@3 {
2486 2154 compatible = "qcom,fastrpc-compute-cb";
2487 2155 reg = <3>;
2488 2156 iommus = <&apps_smmu 0x0543 0x0>;
2489 2157 /* note: shared-cb = <4> in downstream */
2490 }; 2158 };
2491 }; 2159 };
2492 }; 2160 };
2493 }; 2161 };
2494 2162
2495 wsa2macro: codec@31e0000 { 2163 wsa2macro: codec@31e0000 {
2496 compatible = "qcom,sm 2164 compatible = "qcom,sm8450-lpass-wsa-macro";
2497 reg = <0 0x031e0000 0 2165 reg = <0 0x031e0000 0 0x1000>;
2498 clocks = <&q6prmcc LP 2166 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2499 <&q6prmcc LP 2167 <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2500 <&q6prmcc LP 2168 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2501 <&q6prmcc LP 2169 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2502 <&vamacro>; 2170 <&vamacro>;
2503 clock-names = "mclk", 2171 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
>> 2172 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 2173 <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
>> 2174 assigned-clock-rates = <19200000>, <19200000>;
2504 2175
2505 #clock-cells = <0>; 2176 #clock-cells = <0>;
2506 clock-output-names = 2177 clock-output-names = "wsa2-mclk";
>> 2178 pinctrl-names = "default";
>> 2179 pinctrl-0 = <&wsa2_swr_active>;
2507 #sound-dai-cells = <1 2180 #sound-dai-cells = <1>;
2508 }; 2181 };
2509 2182
2510 swr4: soundwire@31f0000 { 2183 swr4: soundwire@31f0000 {
2511 compatible = "qcom,so 2184 compatible = "qcom,soundwire-v1.7.0";
2512 reg = <0 0x031f0000 0 2185 reg = <0 0x031f0000 0 0x2000>;
2513 interrupts = <GIC_SPI 2186 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
2514 clocks = <&wsa2macro> 2187 clocks = <&wsa2macro>;
2515 clock-names = "iface" 2188 clock-names = "iface";
2516 label = "WSA2"; 2189 label = "WSA2";
2517 2190
2518 pinctrl-0 = <&wsa2_sw <<
2519 pinctrl-names = "defa <<
2520 <<
2521 qcom,din-ports = <2>; 2191 qcom,din-ports = <2>;
2522 qcom,dout-ports = <6> 2192 qcom,dout-ports = <6>;
2523 2193
2524 qcom,ports-sinterval- 2194 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2525 qcom,ports-offset1 = 2195 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2526 qcom,ports-offset2 = 2196 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2527 qcom,ports-hstart = 2197 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2528 qcom,ports-hstop = 2198 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2529 qcom,ports-word-lengt 2199 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2530 qcom,ports-block-pack 2200 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
2531 qcom,ports-block-grou 2201 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2532 qcom,ports-lane-contr 2202 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2533 2203
2534 #address-cells = <2>; 2204 #address-cells = <2>;
2535 #size-cells = <0>; 2205 #size-cells = <0>;
2536 #sound-dai-cells = <1 2206 #sound-dai-cells = <1>;
2537 status = "disabled"; 2207 status = "disabled";
2538 }; 2208 };
2539 2209
2540 rxmacro: codec@3200000 { 2210 rxmacro: codec@3200000 {
2541 compatible = "qcom,sm 2211 compatible = "qcom,sm8450-lpass-rx-macro";
2542 reg = <0 0x03200000 0 2212 reg = <0 0x03200000 0 0x1000>;
2543 clocks = <&q6prmcc LP 2213 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2544 <&q6prmcc LP 2214 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2545 <&q6prmcc LP 2215 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2546 <&q6prmcc LP 2216 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2547 <&vamacro>; 2217 <&vamacro>;
2548 clock-names = "mclk", 2218 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2549 2219
>> 2220 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 2221 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
>> 2222 assigned-clock-rates = <19200000>, <19200000>;
>> 2223
2550 #clock-cells = <0>; 2224 #clock-cells = <0>;
2551 clock-output-names = 2225 clock-output-names = "mclk";
>> 2226 pinctrl-names = "default";
>> 2227 pinctrl-0 = <&rx_swr_active>;
2552 #sound-dai-cells = <1 2228 #sound-dai-cells = <1>;
2553 }; 2229 };
2554 2230
2555 swr1: soundwire@3210000 { 2231 swr1: soundwire@3210000 {
2556 compatible = "qcom,so 2232 compatible = "qcom,soundwire-v1.7.0";
2557 reg = <0 0x03210000 0 2233 reg = <0 0x03210000 0 0x2000>;
2558 interrupts = <GIC_SPI 2234 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
2559 clocks = <&rxmacro>; 2235 clocks = <&rxmacro>;
2560 clock-names = "iface" 2236 clock-names = "iface";
2561 label = "RX"; 2237 label = "RX";
2562 qcom,din-ports = <0>; 2238 qcom,din-ports = <0>;
2563 qcom,dout-ports = <5> 2239 qcom,dout-ports = <5>;
2564 2240
2565 pinctrl-0 = <&rx_swr_ <<
2566 pinctrl-names = "defa <<
2567 <<
2568 qcom,ports-sinterval- 2241 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
2569 qcom,ports-offset1 = 2242 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>;
2570 qcom,ports-offset2 = 2243 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
2571 qcom,ports-hstart = 2244 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
2572 qcom,ports-hstop = 2245 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
2573 qcom,ports-word-lengt 2246 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2574 qcom,ports-block-pack 2247 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
2575 qcom,ports-block-grou 2248 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
2576 qcom,ports-lane-contr 2249 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2577 2250
2578 #address-cells = <2>; 2251 #address-cells = <2>;
2579 #size-cells = <0>; 2252 #size-cells = <0>;
2580 #sound-dai-cells = <1 2253 #sound-dai-cells = <1>;
2581 status = "disabled"; 2254 status = "disabled";
2582 }; 2255 };
2583 2256
2584 txmacro: codec@3220000 { 2257 txmacro: codec@3220000 {
2585 compatible = "qcom,sm 2258 compatible = "qcom,sm8450-lpass-tx-macro";
2586 reg = <0 0x03220000 0 2259 reg = <0 0x03220000 0 0x1000>;
2587 clocks = <&q6prmcc LP 2260 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2588 <&q6prmcc LP 2261 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2589 <&q6prmcc LP 2262 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2590 <&q6prmcc LP 2263 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2591 <&vamacro>; 2264 <&vamacro>;
2592 clock-names = "mclk", 2265 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
>> 2266 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 2267 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
>> 2268 assigned-clock-rates = <19200000>, <19200000>;
2593 2269
2594 #clock-cells = <0>; 2270 #clock-cells = <0>;
2595 clock-output-names = 2271 clock-output-names = "mclk";
>> 2272 pinctrl-names = "default";
>> 2273 pinctrl-0 = <&tx_swr_active>;
2596 #sound-dai-cells = <1 2274 #sound-dai-cells = <1>;
2597 }; 2275 };
2598 2276
2599 wsamacro: codec@3240000 { 2277 wsamacro: codec@3240000 {
2600 compatible = "qcom,sm 2278 compatible = "qcom,sm8450-lpass-wsa-macro";
2601 reg = <0 0x03240000 0 2279 reg = <0 0x03240000 0 0x1000>;
2602 clocks = <&q6prmcc LP 2280 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2603 <&q6prmcc LP 2281 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2604 <&q6prmcc LP 2282 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2605 <&q6prmcc LP 2283 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2606 <&vamacro>; 2284 <&vamacro>;
2607 clock-names = "mclk", 2285 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2608 2286
>> 2287 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 2288 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
>> 2289 assigned-clock-rates = <19200000>, <19200000>;
>> 2290
2609 #clock-cells = <0>; 2291 #clock-cells = <0>;
2610 clock-output-names = 2292 clock-output-names = "mclk";
>> 2293 pinctrl-names = "default";
>> 2294 pinctrl-0 = <&wsa_swr_active>;
2611 #sound-dai-cells = <1 2295 #sound-dai-cells = <1>;
2612 }; 2296 };
2613 2297
2614 swr0: soundwire@3250000 { 2298 swr0: soundwire@3250000 {
2615 compatible = "qcom,so 2299 compatible = "qcom,soundwire-v1.7.0";
2616 reg = <0 0x03250000 0 2300 reg = <0 0x03250000 0 0x2000>;
2617 interrupts = <GIC_SPI 2301 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
2618 clocks = <&wsamacro>; 2302 clocks = <&wsamacro>;
2619 clock-names = "iface" 2303 clock-names = "iface";
2620 label = "WSA"; 2304 label = "WSA";
2621 2305
2622 pinctrl-0 = <&wsa_swr <<
2623 pinctrl-names = "defa <<
2624 <<
2625 qcom,din-ports = <2>; 2306 qcom,din-ports = <2>;
2626 qcom,dout-ports = <6> 2307 qcom,dout-ports = <6>;
2627 2308
2628 qcom,ports-sinterval- 2309 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2629 qcom,ports-offset1 = 2310 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2630 qcom,ports-offset2 = 2311 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2631 qcom,ports-hstart = 2312 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2632 qcom,ports-hstop = 2313 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2633 qcom,ports-word-lengt 2314 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2634 qcom,ports-block-pack 2315 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
2635 qcom,ports-block-grou 2316 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2636 qcom,ports-lane-contr 2317 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2637 2318
2638 #address-cells = <2>; 2319 #address-cells = <2>;
2639 #size-cells = <0>; 2320 #size-cells = <0>;
2640 #sound-dai-cells = <1 2321 #sound-dai-cells = <1>;
2641 status = "disabled"; 2322 status = "disabled";
2642 }; 2323 };
2643 2324
2644 swr2: soundwire@33b0000 { 2325 swr2: soundwire@33b0000 {
2645 compatible = "qcom,so 2326 compatible = "qcom,soundwire-v1.7.0";
2646 reg = <0 0x033b0000 0 2327 reg = <0 0x033b0000 0 0x2000>;
2647 interrupts = <GIC_SPI 2328 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
2648 <GIC_SPI 2329 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>;
2649 interrupt-names = "co 2330 interrupt-names = "core", "wakeup";
2650 2331
2651 clocks = <&txmacro>; 2332 clocks = <&txmacro>;
2652 clock-names = "iface" 2333 clock-names = "iface";
2653 label = "TX"; 2334 label = "TX";
2654 2335
2655 pinctrl-0 = <&tx_swr_ <<
2656 pinctrl-names = "defa <<
2657 <<
2658 qcom,din-ports = <4>; 2336 qcom,din-ports = <4>;
2659 qcom,dout-ports = <0> 2337 qcom,dout-ports = <0>;
2660 qcom,ports-sinterval- 2338 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
2661 qcom,ports-offset1 = 2339 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>;
2662 qcom,ports-offset2 = 2340 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
2663 qcom,ports-hstart = 2341 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
2664 qcom,ports-hstop = 2342 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
2665 qcom,ports-word-lengt 2343 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
2666 qcom,ports-block-pack 2344 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
2667 qcom,ports-block-grou 2345 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
2668 qcom,ports-lane-contr 2346 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>;
2669 2347
2670 #address-cells = <2>; 2348 #address-cells = <2>;
2671 #size-cells = <0>; 2349 #size-cells = <0>;
2672 #sound-dai-cells = <1 2350 #sound-dai-cells = <1>;
2673 status = "disabled"; 2351 status = "disabled";
2674 }; 2352 };
2675 2353
2676 vamacro: codec@33f0000 { 2354 vamacro: codec@33f0000 {
2677 compatible = "qcom,sm 2355 compatible = "qcom,sm8450-lpass-va-macro";
2678 reg = <0 0x033f0000 0 2356 reg = <0 0x033f0000 0 0x1000>;
2679 clocks = <&q6prmcc LP 2357 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2680 <&q6prmcc LP 2358 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2681 <&q6prmcc LP 2359 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2682 <&q6prmcc LP 2360 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2683 clock-names = "mclk", 2361 clock-names = "mclk", "macro", "dcodec", "npl";
>> 2362 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
>> 2363 assigned-clock-rates = <19200000>;
2684 2364
2685 #clock-cells = <0>; 2365 #clock-cells = <0>;
2686 clock-output-names = 2366 clock-output-names = "fsgen";
2687 #sound-dai-cells = <1 2367 #sound-dai-cells = <1>;
2688 status = "disabled"; 2368 status = "disabled";
2689 }; 2369 };
2690 2370
2691 remoteproc_adsp: remoteproc@3 2371 remoteproc_adsp: remoteproc@30000000 {
2692 compatible = "qcom,sm 2372 compatible = "qcom,sm8450-adsp-pas";
2693 reg = <0 0x30000000 0 2373 reg = <0 0x30000000 0 0x100>;
2694 2374
2695 interrupts-extended = 2375 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
2696 2376 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
2697 2377 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
2698 2378 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
2699 2379 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
2700 interrupt-names = "wd 2380 interrupt-names = "wdog", "fatal", "ready",
2701 "ha 2381 "handover", "stop-ack";
2702 2382
2703 clocks = <&rpmhcc RPM 2383 clocks = <&rpmhcc RPMH_CXO_CLK>;
2704 clock-names = "xo"; 2384 clock-names = "xo";
2705 2385
2706 power-domains = <&rpm 2386 power-domains = <&rpmhpd RPMHPD_LCX>,
2707 <&rpm 2387 <&rpmhpd RPMHPD_LMX>;
2708 power-domain-names = 2388 power-domain-names = "lcx", "lmx";
2709 2389
2710 memory-region = <&ads 2390 memory-region = <&adsp_mem>;
2711 2391
2712 qcom,qmp = <&aoss_qmp 2392 qcom,qmp = <&aoss_qmp>;
2713 2393
2714 qcom,smem-states = <& 2394 qcom,smem-states = <&smp2p_adsp_out 0>;
2715 qcom,smem-state-names 2395 qcom,smem-state-names = "stop";
2716 2396
2717 status = "disabled"; 2397 status = "disabled";
2718 2398
2719 remoteproc_adsp_glink 2399 remoteproc_adsp_glink: glink-edge {
2720 interrupts-ex 2400 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
2721 2401 IPCC_MPROC_SIGNAL_GLINK_QMP
2722 2402 IRQ_TYPE_EDGE_RISING>;
2723 mboxes = <&ip 2403 mboxes = <&ipcc IPCC_CLIENT_LPASS
2724 2404 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2725 2405
2726 label = "lpas 2406 label = "lpass";
2727 qcom,remote-p 2407 qcom,remote-pid = <2>;
2728 2408
2729 gpr { 2409 gpr {
2730 compa 2410 compatible = "qcom,gpr";
2731 qcom, 2411 qcom,glink-channels = "adsp_apps";
2732 qcom, 2412 qcom,domain = <GPR_DOMAIN_ID_ADSP>;
2733 qcom, 2413 qcom,intents = <512 20>;
2734 #addr 2414 #address-cells = <1>;
2735 #size 2415 #size-cells = <0>;
2736 2416
2737 q6apm 2417 q6apm: service@1 {
2738 2418 compatible = "qcom,q6apm";
2739 2419 reg = <GPR_APM_MODULE_IID>;
2740 2420 #sound-dai-cells = <0>;
2741 2421 qcom,protection-domain = "avs/audio",
2742 2422 "msm/adsp/audio_pd";
2743 2423
2744 2424 q6apmdai: dais {
2745 2425 compatible = "qcom,q6apm-dais";
2746 2426 iommus = <&apps_smmu 0x1801 0x0>;
2747 2427 };
2748 2428
2749 2429 q6apmbedai: bedais {
2750 2430 compatible = "qcom,q6apm-lpass-dais";
2751 2431 #sound-dai-cells = <1>;
2752 2432 };
2753 }; 2433 };
2754 2434
2755 q6prm 2435 q6prm: service@2 {
2756 2436 compatible = "qcom,q6prm";
2757 2437 reg = <GPR_PRM_MODULE_IID>;
2758 2438 qcom,protection-domain = "avs/audio",
2759 2439 "msm/adsp/audio_pd";
2760 2440
2761 2441 q6prmcc: clock-controller {
2762 2442 compatible = "qcom,q6prm-lpass-clocks";
2763 2443 #clock-cells = <2>;
2764 2444 };
2765 }; 2445 };
2766 }; 2446 };
2767 2447
2768 fastrpc { 2448 fastrpc {
2769 compa 2449 compatible = "qcom,fastrpc";
2770 qcom, 2450 qcom,glink-channels = "fastrpcglink-apps-dsp";
2771 label 2451 label = "adsp";
2772 qcom, <<
2773 #addr 2452 #address-cells = <1>;
2774 #size 2453 #size-cells = <0>;
2775 2454
2776 compu 2455 compute-cb@3 {
2777 2456 compatible = "qcom,fastrpc-compute-cb";
2778 2457 reg = <3>;
2779 2458 iommus = <&apps_smmu 0x1803 0x0>;
2780 }; 2459 };
2781 2460
2782 compu 2461 compute-cb@4 {
2783 2462 compatible = "qcom,fastrpc-compute-cb";
2784 2463 reg = <4>;
2785 2464 iommus = <&apps_smmu 0x1804 0x0>;
2786 }; 2465 };
2787 2466
2788 compu 2467 compute-cb@5 {
2789 2468 compatible = "qcom,fastrpc-compute-cb";
2790 2469 reg = <5>;
2791 2470 iommus = <&apps_smmu 0x1805 0x0>;
2792 }; 2471 };
2793 }; 2472 };
2794 }; 2473 };
2795 }; 2474 };
2796 2475
2797 remoteproc_cdsp: remoteproc@3 2476 remoteproc_cdsp: remoteproc@32300000 {
2798 compatible = "qcom,sm 2477 compatible = "qcom,sm8450-cdsp-pas";
2799 reg = <0 0x32300000 0 2478 reg = <0 0x32300000 0 0x1400000>;
2800 2479
2801 interrupts-extended = 2480 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
2802 2481 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
2803 2482 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
2804 2483 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
2805 2484 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
2806 interrupt-names = "wd 2485 interrupt-names = "wdog", "fatal", "ready",
2807 "ha 2486 "handover", "stop-ack";
2808 2487
2809 clocks = <&rpmhcc RPM 2488 clocks = <&rpmhcc RPMH_CXO_CLK>;
2810 clock-names = "xo"; 2489 clock-names = "xo";
2811 2490
2812 power-domains = <&rpm 2491 power-domains = <&rpmhpd RPMHPD_CX>,
2813 <&rpm 2492 <&rpmhpd RPMHPD_MXC>;
2814 power-domain-names = 2493 power-domain-names = "cx", "mxc";
2815 2494
2816 memory-region = <&cds 2495 memory-region = <&cdsp_mem>;
2817 2496
2818 qcom,qmp = <&aoss_qmp 2497 qcom,qmp = <&aoss_qmp>;
2819 2498
2820 qcom,smem-states = <& 2499 qcom,smem-states = <&smp2p_cdsp_out 0>;
2821 qcom,smem-state-names 2500 qcom,smem-state-names = "stop";
2822 2501
2823 status = "disabled"; 2502 status = "disabled";
2824 2503
2825 glink-edge { 2504 glink-edge {
2826 interrupts-ex 2505 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
2827 2506 IPCC_MPROC_SIGNAL_GLINK_QMP
2828 2507 IRQ_TYPE_EDGE_RISING>;
2829 mboxes = <&ip 2508 mboxes = <&ipcc IPCC_CLIENT_CDSP
2830 2509 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2831 2510
2832 label = "cdsp 2511 label = "cdsp";
2833 qcom,remote-p 2512 qcom,remote-pid = <5>;
2834 2513
2835 fastrpc { 2514 fastrpc {
2836 compa 2515 compatible = "qcom,fastrpc";
2837 qcom, 2516 qcom,glink-channels = "fastrpcglink-apps-dsp";
2838 label 2517 label = "cdsp";
2839 qcom, <<
2840 #addr 2518 #address-cells = <1>;
2841 #size 2519 #size-cells = <0>;
2842 2520
2843 compu 2521 compute-cb@1 {
2844 2522 compatible = "qcom,fastrpc-compute-cb";
2845 2523 reg = <1>;
2846 2524 iommus = <&apps_smmu 0x2161 0x0400>,
2847 2525 <&apps_smmu 0x1021 0x1420>;
2848 }; 2526 };
2849 2527
2850 compu 2528 compute-cb@2 {
2851 2529 compatible = "qcom,fastrpc-compute-cb";
2852 2530 reg = <2>;
2853 2531 iommus = <&apps_smmu 0x2162 0x0400>,
2854 2532 <&apps_smmu 0x1022 0x1420>;
2855 }; 2533 };
2856 2534
2857 compu 2535 compute-cb@3 {
2858 2536 compatible = "qcom,fastrpc-compute-cb";
2859 2537 reg = <3>;
2860 2538 iommus = <&apps_smmu 0x2163 0x0400>,
2861 2539 <&apps_smmu 0x1023 0x1420>;
2862 }; 2540 };
2863 2541
2864 compu 2542 compute-cb@4 {
2865 2543 compatible = "qcom,fastrpc-compute-cb";
2866 2544 reg = <4>;
2867 2545 iommus = <&apps_smmu 0x2164 0x0400>,
2868 2546 <&apps_smmu 0x1024 0x1420>;
2869 }; 2547 };
2870 2548
2871 compu 2549 compute-cb@5 {
2872 2550 compatible = "qcom,fastrpc-compute-cb";
2873 2551 reg = <5>;
2874 2552 iommus = <&apps_smmu 0x2165 0x0400>,
2875 2553 <&apps_smmu 0x1025 0x1420>;
2876 }; 2554 };
2877 2555
2878 compu 2556 compute-cb@6 {
2879 2557 compatible = "qcom,fastrpc-compute-cb";
2880 2558 reg = <6>;
2881 2559 iommus = <&apps_smmu 0x2166 0x0400>,
2882 2560 <&apps_smmu 0x1026 0x1420>;
2883 }; 2561 };
2884 2562
2885 compu 2563 compute-cb@7 {
2886 2564 compatible = "qcom,fastrpc-compute-cb";
2887 2565 reg = <7>;
2888 2566 iommus = <&apps_smmu 0x2167 0x0400>,
2889 2567 <&apps_smmu 0x1027 0x1420>;
2890 }; 2568 };
2891 2569
2892 compu 2570 compute-cb@8 {
2893 2571 compatible = "qcom,fastrpc-compute-cb";
2894 2572 reg = <8>;
2895 2573 iommus = <&apps_smmu 0x2168 0x0400>,
2896 2574 <&apps_smmu 0x1028 0x1420>;
2897 }; 2575 };
2898 2576
2899 /* no 2577 /* note: secure cb9 in downstream */
2900 }; 2578 };
2901 }; 2579 };
2902 }; 2580 };
2903 2581
2904 remoteproc_mpss: remoteproc@4 2582 remoteproc_mpss: remoteproc@4080000 {
2905 compatible = "qcom,sm 2583 compatible = "qcom,sm8450-mpss-pas";
2906 reg = <0x0 0x04080000 2584 reg = <0x0 0x04080000 0x0 0x4040>;
2907 2585
2908 interrupts-extended = 2586 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
2909 2587 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
2910 2588 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
2911 2589 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
2912 2590 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>,
2913 2591 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>;
2914 interrupt-names = "wd 2592 interrupt-names = "wdog", "fatal", "ready", "handover",
2915 "st 2593 "stop-ack", "shutdown-ack";
2916 2594
2917 clocks = <&rpmhcc RPM 2595 clocks = <&rpmhcc RPMH_CXO_CLK>;
2918 clock-names = "xo"; 2596 clock-names = "xo";
2919 2597
2920 power-domains = <&rpm 2598 power-domains = <&rpmhpd RPMHPD_CX>,
2921 <&rpm 2599 <&rpmhpd RPMHPD_MSS>;
2922 power-domain-names = 2600 power-domain-names = "cx", "mss";
2923 2601
2924 memory-region = <&mps 2602 memory-region = <&mpss_mem>;
2925 2603
2926 qcom,qmp = <&aoss_qmp 2604 qcom,qmp = <&aoss_qmp>;
2927 2605
2928 qcom,smem-states = <& 2606 qcom,smem-states = <&smp2p_modem_out 0>;
2929 qcom,smem-state-names 2607 qcom,smem-state-names = "stop";
2930 2608
2931 status = "disabled"; 2609 status = "disabled";
2932 2610
2933 glink-edge { 2611 glink-edge {
2934 interrupts-ex 2612 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
2935 2613 IPCC_MPROC_SIGNAL_GLINK_QMP
2936 2614 IRQ_TYPE_EDGE_RISING>;
2937 mboxes = <&ip 2615 mboxes = <&ipcc IPCC_CLIENT_MPSS
2938 2616 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2939 label = "mode 2617 label = "modem";
2940 qcom,remote-p 2618 qcom,remote-pid = <1>;
2941 }; 2619 };
2942 }; 2620 };
2943 2621
2944 videocc: clock-controller@aaf 2622 videocc: clock-controller@aaf0000 {
2945 compatible = "qcom,sm 2623 compatible = "qcom,sm8450-videocc";
2946 reg = <0 0x0aaf0000 0 2624 reg = <0 0x0aaf0000 0 0x10000>;
2947 clocks = <&rpmhcc RPM 2625 clocks = <&rpmhcc RPMH_CXO_CLK>,
2948 <&gcc GCC_VI 2626 <&gcc GCC_VIDEO_AHB_CLK>;
2949 power-domains = <&rpm 2627 power-domains = <&rpmhpd RPMHPD_MMCX>;
2950 required-opps = <&rpm 2628 required-opps = <&rpmhpd_opp_low_svs>;
2951 #clock-cells = <1>; 2629 #clock-cells = <1>;
2952 #reset-cells = <1>; 2630 #reset-cells = <1>;
2953 #power-domain-cells = 2631 #power-domain-cells = <1>;
2954 }; 2632 };
2955 2633
2956 cci0: cci@ac15000 { 2634 cci0: cci@ac15000 {
2957 compatible = "qcom,sm 2635 compatible = "qcom,sm8450-cci", "qcom,msm8996-cci";
2958 reg = <0 0x0ac15000 0 2636 reg = <0 0x0ac15000 0 0x1000>;
2959 interrupts = <GIC_SPI 2637 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
2960 power-domains = <&cam 2638 power-domains = <&camcc TITAN_TOP_GDSC>;
2961 2639
2962 clocks = <&camcc CAM_ 2640 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
2963 <&camcc CAM_ 2641 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
2964 <&camcc CAM_ 2642 <&camcc CAM_CC_CPAS_AHB_CLK>,
2965 <&camcc CAM_ 2643 <&camcc CAM_CC_CCI_0_CLK>,
2966 <&camcc CAM_ 2644 <&camcc CAM_CC_CCI_0_CLK_SRC>;
2967 clock-names = "camnoc 2645 clock-names = "camnoc_axi",
2968 "slow_a 2646 "slow_ahb_src",
2969 "cpas_a 2647 "cpas_ahb",
2970 "cci", 2648 "cci",
2971 "cci_sr 2649 "cci_src";
2972 pinctrl-0 = <&cci0_de 2650 pinctrl-0 = <&cci0_default &cci1_default>;
2973 pinctrl-1 = <&cci0_sl 2651 pinctrl-1 = <&cci0_sleep &cci1_sleep>;
2974 pinctrl-names = "defa 2652 pinctrl-names = "default", "sleep";
2975 2653
2976 status = "disabled"; 2654 status = "disabled";
2977 #address-cells = <1>; 2655 #address-cells = <1>;
2978 #size-cells = <0>; 2656 #size-cells = <0>;
2979 2657
2980 cci0_i2c0: i2c-bus@0 2658 cci0_i2c0: i2c-bus@0 {
2981 reg = <0>; 2659 reg = <0>;
2982 clock-frequen 2660 clock-frequency = <1000000>;
2983 #address-cell 2661 #address-cells = <1>;
2984 #size-cells = 2662 #size-cells = <0>;
2985 }; 2663 };
2986 2664
2987 cci0_i2c1: i2c-bus@1 2665 cci0_i2c1: i2c-bus@1 {
2988 reg = <1>; 2666 reg = <1>;
2989 clock-frequen 2667 clock-frequency = <1000000>;
2990 #address-cell 2668 #address-cells = <1>;
2991 #size-cells = 2669 #size-cells = <0>;
2992 }; 2670 };
2993 }; 2671 };
2994 2672
2995 cci1: cci@ac16000 { 2673 cci1: cci@ac16000 {
2996 compatible = "qcom,sm 2674 compatible = "qcom,sm8450-cci", "qcom,msm8996-cci";
2997 reg = <0 0x0ac16000 0 2675 reg = <0 0x0ac16000 0 0x1000>;
2998 interrupts = <GIC_SPI 2676 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>;
2999 power-domains = <&cam 2677 power-domains = <&camcc TITAN_TOP_GDSC>;
3000 2678
3001 clocks = <&camcc CAM_ 2679 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
3002 <&camcc CAM_ 2680 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
3003 <&camcc CAM_ 2681 <&camcc CAM_CC_CPAS_AHB_CLK>,
3004 <&camcc CAM_ 2682 <&camcc CAM_CC_CCI_1_CLK>,
3005 <&camcc CAM_ 2683 <&camcc CAM_CC_CCI_1_CLK_SRC>;
3006 clock-names = "camnoc 2684 clock-names = "camnoc_axi",
3007 "slow_a 2685 "slow_ahb_src",
3008 "cpas_a 2686 "cpas_ahb",
3009 "cci", 2687 "cci",
3010 "cci_sr 2688 "cci_src";
3011 pinctrl-0 = <&cci2_de 2689 pinctrl-0 = <&cci2_default &cci3_default>;
3012 pinctrl-1 = <&cci2_sl 2690 pinctrl-1 = <&cci2_sleep &cci3_sleep>;
3013 pinctrl-names = "defa 2691 pinctrl-names = "default", "sleep";
3014 2692
3015 status = "disabled"; 2693 status = "disabled";
3016 #address-cells = <1>; 2694 #address-cells = <1>;
3017 #size-cells = <0>; 2695 #size-cells = <0>;
3018 2696
3019 cci1_i2c0: i2c-bus@0 2697 cci1_i2c0: i2c-bus@0 {
3020 reg = <0>; 2698 reg = <0>;
3021 clock-frequen 2699 clock-frequency = <1000000>;
3022 #address-cell 2700 #address-cells = <1>;
3023 #size-cells = 2701 #size-cells = <0>;
3024 }; 2702 };
3025 2703
3026 cci1_i2c1: i2c-bus@1 2704 cci1_i2c1: i2c-bus@1 {
3027 reg = <1>; 2705 reg = <1>;
3028 clock-frequen 2706 clock-frequency = <1000000>;
3029 #address-cell 2707 #address-cells = <1>;
3030 #size-cells = 2708 #size-cells = <0>;
3031 }; 2709 };
3032 }; 2710 };
3033 2711
3034 camcc: clock-controller@ade00 2712 camcc: clock-controller@ade0000 {
3035 compatible = "qcom,sm 2713 compatible = "qcom,sm8450-camcc";
3036 reg = <0 0x0ade0000 0 2714 reg = <0 0x0ade0000 0 0x20000>;
3037 clocks = <&gcc GCC_CA 2715 clocks = <&gcc GCC_CAMERA_AHB_CLK>,
3038 <&rpmhcc RPM 2716 <&rpmhcc RPMH_CXO_CLK>,
3039 <&rpmhcc RPM 2717 <&rpmhcc RPMH_CXO_CLK_A>,
3040 <&sleep_clk> 2718 <&sleep_clk>;
3041 power-domains = <&rpm 2719 power-domains = <&rpmhpd RPMHPD_MMCX>;
3042 required-opps = <&rpm 2720 required-opps = <&rpmhpd_opp_low_svs>;
3043 #clock-cells = <1>; 2721 #clock-cells = <1>;
3044 #reset-cells = <1>; 2722 #reset-cells = <1>;
3045 #power-domain-cells = 2723 #power-domain-cells = <1>;
3046 status = "disabled"; 2724 status = "disabled";
3047 }; 2725 };
3048 2726
3049 mdss: display-subsystem@ae000 2727 mdss: display-subsystem@ae00000 {
3050 compatible = "qcom,sm 2728 compatible = "qcom,sm8450-mdss";
3051 reg = <0 0x0ae00000 0 2729 reg = <0 0x0ae00000 0 0x1000>;
3052 reg-names = "mdss"; 2730 reg-names = "mdss";
3053 2731
3054 /* same path used twi 2732 /* same path used twice */
3055 interconnects = <&mms 2733 interconnects = <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>,
3056 <&mms 2734 <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>,
3057 <&gem 2735 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
3058 &con 2736 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
3059 interconnect-names = 2737 interconnect-names = "mdp0-mem",
3060 2738 "mdp1-mem",
3061 2739 "cpu-cfg";
3062 2740
3063 resets = <&dispcc DIS 2741 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
3064 2742
3065 power-domains = <&dis 2743 power-domains = <&dispcc MDSS_GDSC>;
3066 2744
3067 clocks = <&dispcc DIS 2745 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3068 <&gcc GCC_DI 2746 <&gcc GCC_DISP_HF_AXI_CLK>,
3069 <&gcc GCC_DI 2747 <&gcc GCC_DISP_SF_AXI_CLK>,
3070 <&dispcc DIS 2748 <&dispcc DISP_CC_MDSS_MDP_CLK>;
3071 2749
3072 interrupts = <GIC_SPI 2750 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
3073 interrupt-controller; 2751 interrupt-controller;
3074 #interrupt-cells = <1 2752 #interrupt-cells = <1>;
3075 2753
3076 iommus = <&apps_smmu 2754 iommus = <&apps_smmu 0x2800 0x402>;
3077 2755
3078 #address-cells = <2>; 2756 #address-cells = <2>;
3079 #size-cells = <2>; 2757 #size-cells = <2>;
3080 ranges; 2758 ranges;
3081 2759
3082 status = "disabled"; 2760 status = "disabled";
3083 2761
3084 mdss_mdp: display-con 2762 mdss_mdp: display-controller@ae01000 {
3085 compatible = 2763 compatible = "qcom,sm8450-dpu";
3086 reg = <0 0x0a 2764 reg = <0 0x0ae01000 0 0x8f000>,
3087 <0 0x0a 2765 <0 0x0aeb0000 0 0x2008>;
3088 reg-names = " 2766 reg-names = "mdp", "vbif";
3089 2767
3090 clocks = <&gc 2768 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
3091 <&gcc 2769 <&gcc GCC_DISP_SF_AXI_CLK>,
3092 <&dis 2770 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3093 <&dis 2771 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
3094 <&dis 2772 <&dispcc DISP_CC_MDSS_MDP_CLK>,
3095 <&dis 2773 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3096 clock-names = 2774 clock-names = "bus",
3097 2775 "nrt_bus",
3098 2776 "iface",
3099 2777 "lut",
3100 2778 "core",
3101 2779 "vsync";
3102 2780
3103 assigned-cloc 2781 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3104 assigned-cloc 2782 assigned-clock-rates = <19200000>;
3105 2783
3106 operating-poi 2784 operating-points-v2 = <&mdp_opp_table>;
3107 power-domains 2785 power-domains = <&rpmhpd RPMHPD_MMCX>;
3108 2786
3109 interrupt-par 2787 interrupt-parent = <&mdss>;
3110 interrupts = 2788 interrupts = <0>;
3111 2789
3112 ports { 2790 ports {
3113 #addr 2791 #address-cells = <1>;
3114 #size 2792 #size-cells = <0>;
3115 2793
3116 port@ 2794 port@0 {
3117 2795 reg = <0>;
3118 2796 dpu_intf1_out: endpoint {
3119 2797 remote-endpoint = <&mdss_dsi0_in>;
3120 2798 };
3121 }; 2799 };
3122 2800
3123 port@ 2801 port@1 {
3124 2802 reg = <1>;
3125 2803 dpu_intf2_out: endpoint {
3126 2804 remote-endpoint = <&mdss_dsi1_in>;
3127 2805 };
3128 }; 2806 };
3129 2807
3130 port@ 2808 port@2 {
3131 2809 reg = <2>;
3132 2810 dpu_intf0_out: endpoint {
3133 2811 remote-endpoint = <&mdss_dp0_in>;
3134 2812 };
3135 }; 2813 };
3136 }; 2814 };
3137 2815
3138 mdp_opp_table 2816 mdp_opp_table: opp-table {
3139 compa 2817 compatible = "operating-points-v2";
3140 2818
3141 opp-1 2819 opp-172000000 {
3142 2820 opp-hz = /bits/ 64 <172000000>;
3143 2821 required-opps = <&rpmhpd_opp_low_svs_d1>;
3144 }; 2822 };
3145 2823
3146 opp-2 2824 opp-200000000 {
3147 2825 opp-hz = /bits/ 64 <200000000>;
3148 2826 required-opps = <&rpmhpd_opp_low_svs>;
3149 }; 2827 };
3150 2828
3151 opp-3 2829 opp-325000000 {
3152 2830 opp-hz = /bits/ 64 <325000000>;
3153 2831 required-opps = <&rpmhpd_opp_svs>;
3154 }; 2832 };
3155 2833
3156 opp-3 2834 opp-375000000 {
3157 2835 opp-hz = /bits/ 64 <375000000>;
3158 2836 required-opps = <&rpmhpd_opp_svs_l1>;
3159 }; 2837 };
3160 2838
3161 opp-5 2839 opp-500000000 {
3162 2840 opp-hz = /bits/ 64 <500000000>;
3163 2841 required-opps = <&rpmhpd_opp_nom>;
3164 }; 2842 };
3165 }; 2843 };
3166 }; 2844 };
3167 2845
3168 mdss_dp0: displayport 2846 mdss_dp0: displayport-controller@ae90000 {
3169 compatible = 2847 compatible = "qcom,sm8450-dp", "qcom,sm8350-dp";
3170 reg = <0 0xae 2848 reg = <0 0xae90000 0 0x200>,
3171 <0 0xae 2849 <0 0xae90200 0 0x200>,
3172 <0 0xae 2850 <0 0xae90400 0 0xc00>,
3173 <0 0xae 2851 <0 0xae91000 0 0x400>,
3174 <0 0xae 2852 <0 0xae91400 0 0x400>;
3175 interrupt-par 2853 interrupt-parent = <&mdss>;
3176 interrupts = 2854 interrupts = <12>;
3177 clocks = <&di 2855 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3178 <&di 2856 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
3179 <&di 2857 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
3180 <&di 2858 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
3181 <&di 2859 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
3182 clock-names = 2860 clock-names = "core_iface",
3183 2861 "core_aux",
3184 2862 "ctrl_link",
3185 2863 "ctrl_link_iface",
3186 2864 "stream_pixel";
3187 2865
3188 assigned-cloc 2866 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
3189 2867 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
3190 assigned-cloc 2868 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3191 2869 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
3192 2870
3193 phys = <&usb_ 2871 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
3194 phy-names = " 2872 phy-names = "dp";
3195 2873
3196 #sound-dai-ce 2874 #sound-dai-cells = <0>;
3197 2875
3198 operating-poi 2876 operating-points-v2 = <&dp_opp_table>;
3199 power-domains 2877 power-domains = <&rpmhpd RPMHPD_MMCX>;
3200 2878
3201 status = "dis 2879 status = "disabled";
3202 2880
3203 ports { 2881 ports {
3204 #addr 2882 #address-cells = <1>;
3205 #size 2883 #size-cells = <0>;
3206 2884
3207 port@ 2885 port@0 {
3208 2886 reg = <0>;
3209 2887 mdss_dp0_in: endpoint {
3210 2888 remote-endpoint = <&dpu_intf0_out>;
3211 2889 };
3212 }; 2890 };
3213 <<
3214 port@ <<
3215 <<
3216 <<
3217 <<
3218 <<
3219 <<
3220 }; <<
3221 }; 2891 };
3222 2892
3223 dp_opp_table: 2893 dp_opp_table: opp-table {
3224 compa 2894 compatible = "operating-points-v2";
3225 2895
3226 opp-1 2896 opp-160000000 {
3227 2897 opp-hz = /bits/ 64 <160000000>;
3228 2898 required-opps = <&rpmhpd_opp_low_svs>;
3229 }; 2899 };
3230 2900
3231 opp-2 2901 opp-270000000 {
3232 2902 opp-hz = /bits/ 64 <270000000>;
3233 2903 required-opps = <&rpmhpd_opp_svs>;
3234 }; 2904 };
3235 2905
3236 opp-5 2906 opp-540000000 {
3237 2907 opp-hz = /bits/ 64 <540000000>;
3238 2908 required-opps = <&rpmhpd_opp_svs_l1>;
3239 }; 2909 };
3240 2910
3241 opp-8 2911 opp-810000000 {
3242 2912 opp-hz = /bits/ 64 <810000000>;
3243 2913 required-opps = <&rpmhpd_opp_nom>;
3244 }; 2914 };
3245 }; 2915 };
3246 }; 2916 };
3247 2917
3248 mdss_dsi0: dsi@ae9400 2918 mdss_dsi0: dsi@ae94000 {
3249 compatible = 2919 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3250 reg = <0 0x0a 2920 reg = <0 0x0ae94000 0 0x400>;
3251 reg-names = " 2921 reg-names = "dsi_ctrl";
3252 2922
3253 interrupt-par 2923 interrupt-parent = <&mdss>;
3254 interrupts = 2924 interrupts = <4>;
3255 2925
3256 clocks = <&di 2926 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
3257 <&di 2927 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
3258 <&di 2928 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
3259 <&di 2929 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
3260 <&di 2930 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3261 <&gcc 2931 <&gcc GCC_DISP_HF_AXI_CLK>;
3262 clock-names = 2932 clock-names = "byte",
3263 2933 "byte_intf",
3264 2934 "pixel",
3265 2935 "core",
3266 2936 "iface",
3267 2937 "bus";
3268 2938
3269 assigned-cloc 2939 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
3270 assigned-cloc 2940 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
3271 2941
3272 operating-poi 2942 operating-points-v2 = <&mdss_dsi_opp_table>;
3273 power-domains 2943 power-domains = <&rpmhpd RPMHPD_MMCX>;
3274 2944
3275 phys = <&mdss 2945 phys = <&mdss_dsi0_phy>;
3276 phy-names = " 2946 phy-names = "dsi";
3277 2947
3278 #address-cell 2948 #address-cells = <1>;
3279 #size-cells = 2949 #size-cells = <0>;
3280 2950
3281 status = "dis 2951 status = "disabled";
3282 2952
3283 ports { 2953 ports {
3284 #addr 2954 #address-cells = <1>;
3285 #size 2955 #size-cells = <0>;
3286 2956
3287 port@ 2957 port@0 {
3288 2958 reg = <0>;
3289 2959 mdss_dsi0_in: endpoint {
3290 2960 remote-endpoint = <&dpu_intf1_out>;
3291 2961 };
3292 }; 2962 };
3293 2963
3294 port@ 2964 port@1 {
3295 2965 reg = <1>;
3296 2966 mdss_dsi0_out: endpoint {
3297 2967 };
3298 }; 2968 };
3299 }; 2969 };
3300 2970
3301 mdss_dsi_opp_ 2971 mdss_dsi_opp_table: opp-table {
3302 compa 2972 compatible = "operating-points-v2";
3303 2973
3304 opp-1 2974 opp-187500000 {
3305 2975 opp-hz = /bits/ 64 <187500000>;
3306 2976 required-opps = <&rpmhpd_opp_low_svs>;
3307 }; 2977 };
3308 2978
3309 opp-3 2979 opp-300000000 {
3310 2980 opp-hz = /bits/ 64 <300000000>;
3311 2981 required-opps = <&rpmhpd_opp_svs>;
3312 }; 2982 };
3313 2983
3314 opp-3 2984 opp-358000000 {
3315 2985 opp-hz = /bits/ 64 <358000000>;
3316 2986 required-opps = <&rpmhpd_opp_svs_l1>;
3317 }; 2987 };
3318 }; 2988 };
3319 }; 2989 };
3320 2990
3321 mdss_dsi0_phy: phy@ae 2991 mdss_dsi0_phy: phy@ae94400 {
3322 compatible = 2992 compatible = "qcom,sm8450-dsi-phy-5nm";
3323 reg = <0 0x0a 2993 reg = <0 0x0ae94400 0 0x200>,
3324 <0 0x0a 2994 <0 0x0ae94600 0 0x280>,
3325 <0 0x0a 2995 <0 0x0ae94900 0 0x260>;
3326 reg-names = " 2996 reg-names = "dsi_phy",
3327 " 2997 "dsi_phy_lane",
3328 " 2998 "dsi_pll";
3329 2999
3330 #clock-cells 3000 #clock-cells = <1>;
3331 #phy-cells = 3001 #phy-cells = <0>;
3332 3002
3333 clocks = <&di 3003 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3334 <&rp 3004 <&rpmhcc RPMH_CXO_CLK>;
3335 clock-names = 3005 clock-names = "iface", "ref";
3336 3006
3337 status = "dis 3007 status = "disabled";
3338 }; 3008 };
3339 3009
3340 mdss_dsi1: dsi@ae9600 3010 mdss_dsi1: dsi@ae96000 {
3341 compatible = 3011 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3342 reg = <0 0x0a 3012 reg = <0 0x0ae96000 0 0x400>;
3343 reg-names = " 3013 reg-names = "dsi_ctrl";
3344 3014
3345 interrupt-par 3015 interrupt-parent = <&mdss>;
3346 interrupts = 3016 interrupts = <5>;
3347 3017
3348 clocks = <&di 3018 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
3349 <&di 3019 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
3350 <&di 3020 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
3351 <&di 3021 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
3352 <&di 3022 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3353 <&gc 3023 <&gcc GCC_DISP_HF_AXI_CLK>;
3354 clock-names = 3024 clock-names = "byte",
3355 3025 "byte_intf",
3356 3026 "pixel",
3357 3027 "core",
3358 3028 "iface",
3359 3029 "bus";
3360 3030
3361 assigned-cloc 3031 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
3362 assigned-cloc 3032 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
3363 3033
3364 operating-poi 3034 operating-points-v2 = <&mdss_dsi_opp_table>;
3365 power-domains 3035 power-domains = <&rpmhpd RPMHPD_MMCX>;
3366 3036
3367 phys = <&mdss 3037 phys = <&mdss_dsi1_phy>;
3368 phy-names = " 3038 phy-names = "dsi";
3369 3039
3370 #address-cell 3040 #address-cells = <1>;
3371 #size-cells = 3041 #size-cells = <0>;
3372 3042
3373 status = "dis 3043 status = "disabled";
3374 3044
3375 ports { 3045 ports {
3376 #addr 3046 #address-cells = <1>;
3377 #size 3047 #size-cells = <0>;
3378 3048
3379 port@ 3049 port@0 {
3380 3050 reg = <0>;
3381 3051 mdss_dsi1_in: endpoint {
3382 3052 remote-endpoint = <&dpu_intf2_out>;
3383 3053 };
3384 }; 3054 };
3385 3055
3386 port@ 3056 port@1 {
3387 3057 reg = <1>;
3388 3058 mdss_dsi1_out: endpoint {
3389 3059 };
3390 }; 3060 };
3391 }; 3061 };
3392 }; 3062 };
3393 3063
3394 mdss_dsi1_phy: phy@ae 3064 mdss_dsi1_phy: phy@ae96400 {
3395 compatible = 3065 compatible = "qcom,sm8450-dsi-phy-5nm";
3396 reg = <0 0x0a 3066 reg = <0 0x0ae96400 0 0x200>,
3397 <0 0x0a 3067 <0 0x0ae96600 0 0x280>,
3398 <0 0x0a 3068 <0 0x0ae96900 0 0x260>;
3399 reg-names = " 3069 reg-names = "dsi_phy",
3400 " 3070 "dsi_phy_lane",
3401 " 3071 "dsi_pll";
3402 3072
3403 #clock-cells 3073 #clock-cells = <1>;
3404 #phy-cells = 3074 #phy-cells = <0>;
3405 3075
3406 clocks = <&di 3076 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3407 <&rp 3077 <&rpmhcc RPMH_CXO_CLK>;
3408 clock-names = 3078 clock-names = "iface", "ref";
3409 3079
3410 status = "dis 3080 status = "disabled";
3411 }; 3081 };
3412 }; 3082 };
3413 3083
3414 dispcc: clock-controller@af00 3084 dispcc: clock-controller@af00000 {
3415 compatible = "qcom,sm 3085 compatible = "qcom,sm8450-dispcc";
3416 reg = <0 0x0af00000 0 3086 reg = <0 0x0af00000 0 0x20000>;
3417 clocks = <&rpmhcc RPM 3087 clocks = <&rpmhcc RPMH_CXO_CLK>,
3418 <&rpmhcc RPM 3088 <&rpmhcc RPMH_CXO_CLK_A>,
3419 <&gcc GCC_DI 3089 <&gcc GCC_DISP_AHB_CLK>,
3420 <&sleep_clk> 3090 <&sleep_clk>,
3421 <&mdss_dsi0_ 3091 <&mdss_dsi0_phy 0>,
3422 <&mdss_dsi0_ 3092 <&mdss_dsi0_phy 1>,
3423 <&mdss_dsi1_ 3093 <&mdss_dsi1_phy 0>,
3424 <&mdss_dsi1_ 3094 <&mdss_dsi1_phy 1>,
3425 <&usb_1_qmpp 3095 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3426 <&usb_1_qmpp 3096 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
3427 <0>, /* dp1 3097 <0>, /* dp1 */
3428 <0>, 3098 <0>,
3429 <0>, /* dp2 3099 <0>, /* dp2 */
3430 <0>, 3100 <0>,
3431 <0>, /* dp3 3101 <0>, /* dp3 */
3432 <0>; 3102 <0>;
3433 power-domains = <&rpm 3103 power-domains = <&rpmhpd RPMHPD_MMCX>;
3434 required-opps = <&rpm 3104 required-opps = <&rpmhpd_opp_low_svs>;
3435 #clock-cells = <1>; 3105 #clock-cells = <1>;
3436 #reset-cells = <1>; 3106 #reset-cells = <1>;
3437 #power-domain-cells = 3107 #power-domain-cells = <1>;
3438 status = "disabled"; 3108 status = "disabled";
3439 }; 3109 };
3440 3110
3441 pdc: interrupt-controller@b22 3111 pdc: interrupt-controller@b220000 {
3442 compatible = "qcom,sm 3112 compatible = "qcom,sm8450-pdc", "qcom,pdc";
3443 reg = <0 0x0b220000 0 3113 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
3444 qcom,pdc-ranges = <0 3114 qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>,
3445 <94 3115 <94 609 31>, <125 63 1>, <126 716 12>;
3446 #interrupt-cells = <2 3116 #interrupt-cells = <2>;
3447 interrupt-parent = <& 3117 interrupt-parent = <&intc>;
3448 interrupt-controller; 3118 interrupt-controller;
3449 }; 3119 };
3450 3120
3451 tsens0: thermal-sensor@c26300 3121 tsens0: thermal-sensor@c263000 {
3452 compatible = "qcom,sm 3122 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2";
3453 reg = <0 0x0c263000 0 3123 reg = <0 0x0c263000 0 0x1000>, /* TM */
3454 <0 0x0c222000 0 3124 <0 0x0c222000 0 0x1000>; /* SROT */
3455 #qcom,sensors = <16>; 3125 #qcom,sensors = <16>;
3456 interrupts = <GIC_SPI 3126 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
3457 <GIC_SPI 3127 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
3458 interrupt-names = "up 3128 interrupt-names = "uplow", "critical";
3459 #thermal-sensor-cells 3129 #thermal-sensor-cells = <1>;
3460 }; 3130 };
3461 3131
3462 tsens1: thermal-sensor@c26500 3132 tsens1: thermal-sensor@c265000 {
3463 compatible = "qcom,sm 3133 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2";
3464 reg = <0 0x0c265000 0 3134 reg = <0 0x0c265000 0 0x1000>, /* TM */
3465 <0 0x0c223000 0 3135 <0 0x0c223000 0 0x1000>; /* SROT */
3466 #qcom,sensors = <16>; 3136 #qcom,sensors = <16>;
3467 interrupts = <GIC_SPI 3137 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
3468 <GIC_SPI 3138 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
3469 interrupt-names = "up 3139 interrupt-names = "uplow", "critical";
3470 #thermal-sensor-cells 3140 #thermal-sensor-cells = <1>;
3471 }; 3141 };
3472 3142
3473 aoss_qmp: power-management@c3 3143 aoss_qmp: power-management@c300000 {
3474 compatible = "qcom,sm 3144 compatible = "qcom,sm8450-aoss-qmp", "qcom,aoss-qmp";
3475 reg = <0 0x0c300000 0 3145 reg = <0 0x0c300000 0 0x400>;
3476 interrupts-extended = 3146 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
3477 3147 IRQ_TYPE_EDGE_RISING>;
3478 mboxes = <&ipcc IPCC_ 3148 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
3479 3149
3480 #clock-cells = <0>; 3150 #clock-cells = <0>;
3481 }; 3151 };
3482 3152
3483 sram@c3f0000 { 3153 sram@c3f0000 {
3484 compatible = "qcom,rp 3154 compatible = "qcom,rpmh-stats";
3485 reg = <0 0x0c3f0000 0 3155 reg = <0 0x0c3f0000 0 0x400>;
3486 }; 3156 };
3487 3157
3488 spmi_bus: spmi@c400000 { 3158 spmi_bus: spmi@c400000 {
3489 compatible = "qcom,sp 3159 compatible = "qcom,spmi-pmic-arb";
3490 reg = <0 0x0c400000 0 3160 reg = <0 0x0c400000 0 0x00003000>,
3491 <0 0x0c500000 0 3161 <0 0x0c500000 0 0x00400000>,
3492 <0 0x0c440000 0 3162 <0 0x0c440000 0 0x00080000>,
3493 <0 0x0c4c0000 0 3163 <0 0x0c4c0000 0 0x00010000>,
3494 <0 0x0c42d000 0 3164 <0 0x0c42d000 0 0x00010000>;
3495 reg-names = "core", 3165 reg-names = "core",
3496 "chnls", 3166 "chnls",
3497 "obsrvr", 3167 "obsrvr",
3498 "intr", 3168 "intr",
3499 "cnfg"; 3169 "cnfg";
3500 interrupt-names = "pe 3170 interrupt-names = "periph_irq";
3501 interrupts-extended = 3171 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3502 qcom,ee = <0>; 3172 qcom,ee = <0>;
3503 qcom,channel = <0>; 3173 qcom,channel = <0>;
3504 interrupt-controller; 3174 interrupt-controller;
3505 #interrupt-cells = <4 3175 #interrupt-cells = <4>;
3506 #address-cells = <2>; 3176 #address-cells = <2>;
3507 #size-cells = <0>; 3177 #size-cells = <0>;
3508 }; 3178 };
3509 3179
3510 ipcc: mailbox@ed18000 { 3180 ipcc: mailbox@ed18000 {
3511 compatible = "qcom,sm 3181 compatible = "qcom,sm8450-ipcc", "qcom,ipcc";
3512 reg = <0 0x0ed18000 0 3182 reg = <0 0x0ed18000 0 0x1000>;
3513 interrupts = <GIC_SPI 3183 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
3514 interrupt-controller; 3184 interrupt-controller;
3515 #interrupt-cells = <3 3185 #interrupt-cells = <3>;
3516 #mbox-cells = <2>; 3186 #mbox-cells = <2>;
3517 }; 3187 };
3518 3188
3519 tlmm: pinctrl@f100000 { 3189 tlmm: pinctrl@f100000 {
3520 compatible = "qcom,sm 3190 compatible = "qcom,sm8450-tlmm";
3521 reg = <0 0x0f100000 0 3191 reg = <0 0x0f100000 0 0x300000>;
3522 interrupts = <GIC_SPI 3192 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
3523 gpio-controller; 3193 gpio-controller;
3524 #gpio-cells = <2>; 3194 #gpio-cells = <2>;
3525 interrupt-controller; 3195 interrupt-controller;
3526 #interrupt-cells = <2 3196 #interrupt-cells = <2>;
3527 gpio-ranges = <&tlmm 3197 gpio-ranges = <&tlmm 0 0 211>;
3528 wakeup-parent = <&pdc 3198 wakeup-parent = <&pdc>;
3529 3199
3530 sdc2_default_state: s 3200 sdc2_default_state: sdc2-default-state {
3531 clk-pins { 3201 clk-pins {
3532 pins 3202 pins = "sdc2_clk";
3533 drive 3203 drive-strength = <16>;
3534 bias- 3204 bias-disable;
3535 }; 3205 };
3536 3206
3537 cmd-pins { 3207 cmd-pins {
3538 pins 3208 pins = "sdc2_cmd";
3539 drive 3209 drive-strength = <16>;
3540 bias- 3210 bias-pull-up;
3541 }; 3211 };
3542 3212
3543 data-pins { 3213 data-pins {
3544 pins 3214 pins = "sdc2_data";
3545 drive 3215 drive-strength = <16>;
3546 bias- 3216 bias-pull-up;
3547 }; 3217 };
3548 }; 3218 };
3549 3219
3550 sdc2_sleep_state: sdc 3220 sdc2_sleep_state: sdc2-sleep-state {
3551 clk-pins { 3221 clk-pins {
3552 pins 3222 pins = "sdc2_clk";
3553 drive 3223 drive-strength = <2>;
3554 bias- 3224 bias-disable;
3555 }; 3225 };
3556 3226
3557 cmd-pins { 3227 cmd-pins {
3558 pins 3228 pins = "sdc2_cmd";
3559 drive 3229 drive-strength = <2>;
3560 bias- 3230 bias-pull-up;
3561 }; 3231 };
3562 3232
3563 data-pins { 3233 data-pins {
3564 pins 3234 pins = "sdc2_data";
3565 drive 3235 drive-strength = <2>;
3566 bias- 3236 bias-pull-up;
3567 }; 3237 };
3568 }; 3238 };
3569 3239
3570 cci0_default: cci0-de 3240 cci0_default: cci0-default-state {
3571 /* SDA, SCL * 3241 /* SDA, SCL */
3572 pins = "gpio1 3242 pins = "gpio110", "gpio111";
3573 function = "c 3243 function = "cci_i2c";
3574 drive-strengt 3244 drive-strength = <2>;
3575 bias-pull-up; 3245 bias-pull-up;
3576 }; 3246 };
3577 3247
3578 cci0_sleep: cci0-slee 3248 cci0_sleep: cci0-sleep-state {
3579 /* SDA, SCL * 3249 /* SDA, SCL */
3580 pins = "gpio1 3250 pins = "gpio110", "gpio111";
3581 function = "c 3251 function = "cci_i2c";
3582 drive-strengt 3252 drive-strength = <2>;
3583 bias-pull-dow 3253 bias-pull-down;
3584 }; 3254 };
3585 3255
3586 cci1_default: cci1-de 3256 cci1_default: cci1-default-state {
3587 /* SDA, SCL * 3257 /* SDA, SCL */
3588 pins = "gpio1 3258 pins = "gpio112", "gpio113";
3589 function = "c 3259 function = "cci_i2c";
3590 drive-strengt 3260 drive-strength = <2>;
3591 bias-pull-up; 3261 bias-pull-up;
3592 }; 3262 };
3593 3263
3594 cci1_sleep: cci1-slee 3264 cci1_sleep: cci1-sleep-state {
3595 /* SDA, SCL * 3265 /* SDA, SCL */
3596 pins = "gpio1 3266 pins = "gpio112", "gpio113";
3597 function = "c 3267 function = "cci_i2c";
3598 drive-strengt 3268 drive-strength = <2>;
3599 bias-pull-dow 3269 bias-pull-down;
3600 }; 3270 };
3601 3271
3602 cci2_default: cci2-de 3272 cci2_default: cci2-default-state {
3603 /* SDA, SCL * 3273 /* SDA, SCL */
3604 pins = "gpio1 3274 pins = "gpio114", "gpio115";
3605 function = "c 3275 function = "cci_i2c";
3606 drive-strengt 3276 drive-strength = <2>;
3607 bias-pull-up; 3277 bias-pull-up;
3608 }; 3278 };
3609 3279
3610 cci2_sleep: cci2-slee 3280 cci2_sleep: cci2-sleep-state {
3611 /* SDA, SCL * 3281 /* SDA, SCL */
3612 pins = "gpio1 3282 pins = "gpio114", "gpio115";
3613 function = "c 3283 function = "cci_i2c";
3614 drive-strengt 3284 drive-strength = <2>;
3615 bias-pull-dow 3285 bias-pull-down;
3616 }; 3286 };
3617 3287
3618 cci3_default: cci3-de 3288 cci3_default: cci3-default-state {
3619 /* SDA, SCL * 3289 /* SDA, SCL */
3620 pins = "gpio2 3290 pins = "gpio208", "gpio209";
3621 function = "c 3291 function = "cci_i2c";
3622 drive-strengt 3292 drive-strength = <2>;
3623 bias-pull-up; 3293 bias-pull-up;
3624 }; 3294 };
3625 3295
3626 cci3_sleep: cci3-slee 3296 cci3_sleep: cci3-sleep-state {
3627 /* SDA, SCL * 3297 /* SDA, SCL */
3628 pins = "gpio2 3298 pins = "gpio208", "gpio209";
3629 function = "c 3299 function = "cci_i2c";
3630 drive-strengt 3300 drive-strength = <2>;
3631 bias-pull-dow 3301 bias-pull-down;
3632 }; 3302 };
3633 3303
3634 pcie0_default_state: 3304 pcie0_default_state: pcie0-default-state {
3635 perst-pins { 3305 perst-pins {
3636 pins 3306 pins = "gpio94";
3637 funct 3307 function = "gpio";
3638 drive 3308 drive-strength = <2>;
3639 bias- 3309 bias-pull-down;
3640 }; 3310 };
3641 3311
3642 clkreq-pins { 3312 clkreq-pins {
3643 pins 3313 pins = "gpio95";
3644 funct 3314 function = "pcie0_clkreqn";
3645 drive 3315 drive-strength = <2>;
3646 bias- 3316 bias-pull-up;
3647 }; 3317 };
3648 3318
3649 wake-pins { 3319 wake-pins {
3650 pins 3320 pins = "gpio96";
3651 funct 3321 function = "gpio";
3652 drive 3322 drive-strength = <2>;
3653 bias- 3323 bias-pull-up;
3654 }; 3324 };
3655 }; 3325 };
3656 3326
3657 pcie1_default_state: 3327 pcie1_default_state: pcie1-default-state {
3658 perst-pins { 3328 perst-pins {
3659 pins 3329 pins = "gpio97";
3660 funct 3330 function = "gpio";
3661 drive 3331 drive-strength = <2>;
3662 bias- 3332 bias-pull-down;
3663 }; 3333 };
3664 3334
3665 clkreq-pins { 3335 clkreq-pins {
3666 pins 3336 pins = "gpio98";
3667 funct 3337 function = "pcie1_clkreqn";
3668 drive 3338 drive-strength = <2>;
3669 bias- 3339 bias-pull-up;
3670 }; 3340 };
3671 3341
3672 wake-pins { 3342 wake-pins {
3673 pins 3343 pins = "gpio99";
3674 funct 3344 function = "gpio";
3675 drive 3345 drive-strength = <2>;
3676 bias- 3346 bias-pull-up;
3677 }; 3347 };
3678 }; 3348 };
3679 3349
3680 qup_i2c0_data_clk: qu 3350 qup_i2c0_data_clk: qup-i2c0-data-clk-state {
3681 pins = "gpio0 3351 pins = "gpio0", "gpio1";
3682 function = "q 3352 function = "qup0";
3683 }; 3353 };
3684 3354
3685 qup_i2c1_data_clk: qu 3355 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
3686 pins = "gpio4 3356 pins = "gpio4", "gpio5";
3687 function = "q 3357 function = "qup1";
3688 }; 3358 };
3689 3359
3690 qup_i2c2_data_clk: qu 3360 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
3691 pins = "gpio8 3361 pins = "gpio8", "gpio9";
3692 function = "q 3362 function = "qup2";
3693 }; 3363 };
3694 3364
3695 qup_i2c3_data_clk: qu 3365 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
3696 pins = "gpio1 3366 pins = "gpio12", "gpio13";
3697 function = "q 3367 function = "qup3";
3698 }; 3368 };
3699 3369
3700 qup_i2c4_data_clk: qu 3370 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
3701 pins = "gpio1 3371 pins = "gpio16", "gpio17";
3702 function = "q 3372 function = "qup4";
3703 }; 3373 };
3704 3374
3705 qup_i2c5_data_clk: qu 3375 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
3706 pins = "gpio2 3376 pins = "gpio206", "gpio207";
3707 function = "q 3377 function = "qup5";
3708 }; 3378 };
3709 3379
3710 qup_i2c6_data_clk: qu 3380 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
3711 pins = "gpio2 3381 pins = "gpio20", "gpio21";
3712 function = "q 3382 function = "qup6";
3713 }; 3383 };
3714 3384
3715 qup_i2c8_data_clk: qu 3385 qup_i2c8_data_clk: qup-i2c8-data-clk-state {
3716 pins = "gpio2 3386 pins = "gpio28", "gpio29";
3717 function = "q 3387 function = "qup8";
3718 }; 3388 };
3719 3389
3720 qup_i2c9_data_clk: qu 3390 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
3721 pins = "gpio3 3391 pins = "gpio32", "gpio33";
3722 function = "q 3392 function = "qup9";
3723 }; 3393 };
3724 3394
3725 qup_i2c10_data_clk: q 3395 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
3726 pins = "gpio3 3396 pins = "gpio36", "gpio37";
3727 function = "q 3397 function = "qup10";
3728 }; 3398 };
3729 3399
3730 qup_i2c11_data_clk: q 3400 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
3731 pins = "gpio4 3401 pins = "gpio40", "gpio41";
3732 function = "q 3402 function = "qup11";
3733 }; 3403 };
3734 3404
3735 qup_i2c12_data_clk: q 3405 qup_i2c12_data_clk: qup-i2c12-data-clk-state {
3736 pins = "gpio4 3406 pins = "gpio44", "gpio45";
3737 function = "q 3407 function = "qup12";
3738 }; 3408 };
3739 3409
3740 qup_i2c13_data_clk: q 3410 qup_i2c13_data_clk: qup-i2c13-data-clk-state {
3741 pins = "gpio4 3411 pins = "gpio48", "gpio49";
3742 function = "q 3412 function = "qup13";
3743 drive-strengt 3413 drive-strength = <2>;
3744 bias-pull-up; 3414 bias-pull-up;
3745 }; 3415 };
3746 3416
3747 qup_i2c14_data_clk: q 3417 qup_i2c14_data_clk: qup-i2c14-data-clk-state {
3748 pins = "gpio5 3418 pins = "gpio52", "gpio53";
3749 function = "q 3419 function = "qup14";
3750 drive-strengt 3420 drive-strength = <2>;
3751 bias-pull-up; 3421 bias-pull-up;
3752 }; 3422 };
3753 3423
3754 qup_i2c15_data_clk: q 3424 qup_i2c15_data_clk: qup-i2c15-data-clk-state {
3755 pins = "gpio5 3425 pins = "gpio56", "gpio57";
3756 function = "q 3426 function = "qup15";
3757 }; 3427 };
3758 3428
3759 qup_i2c16_data_clk: q 3429 qup_i2c16_data_clk: qup-i2c16-data-clk-state {
3760 pins = "gpio6 3430 pins = "gpio60", "gpio61";
3761 function = "q 3431 function = "qup16";
3762 }; 3432 };
3763 3433
3764 qup_i2c17_data_clk: q 3434 qup_i2c17_data_clk: qup-i2c17-data-clk-state {
3765 pins = "gpio6 3435 pins = "gpio64", "gpio65";
3766 function = "q 3436 function = "qup17";
3767 }; 3437 };
3768 3438
3769 qup_i2c18_data_clk: q 3439 qup_i2c18_data_clk: qup-i2c18-data-clk-state {
3770 pins = "gpio6 3440 pins = "gpio68", "gpio69";
3771 function = "q 3441 function = "qup18";
3772 }; 3442 };
3773 3443
3774 qup_i2c19_data_clk: q 3444 qup_i2c19_data_clk: qup-i2c19-data-clk-state {
3775 pins = "gpio7 3445 pins = "gpio72", "gpio73";
3776 function = "q 3446 function = "qup19";
3777 }; 3447 };
3778 3448
3779 qup_i2c20_data_clk: q 3449 qup_i2c20_data_clk: qup-i2c20-data-clk-state {
3780 pins = "gpio7 3450 pins = "gpio76", "gpio77";
3781 function = "q 3451 function = "qup20";
3782 }; 3452 };
3783 3453
3784 qup_i2c21_data_clk: q 3454 qup_i2c21_data_clk: qup-i2c21-data-clk-state {
3785 pins = "gpio8 3455 pins = "gpio80", "gpio81";
3786 function = "q 3456 function = "qup21";
3787 }; 3457 };
3788 3458
3789 qup_spi0_cs: qup-spi0 3459 qup_spi0_cs: qup-spi0-cs-state {
3790 pins = "gpio3 3460 pins = "gpio3";
3791 function = "q 3461 function = "qup0";
3792 }; 3462 };
3793 3463
3794 qup_spi0_data_clk: qu 3464 qup_spi0_data_clk: qup-spi0-data-clk-state {
3795 pins = "gpio0 3465 pins = "gpio0", "gpio1", "gpio2";
3796 function = "q 3466 function = "qup0";
3797 }; 3467 };
3798 3468
3799 qup_spi1_cs: qup-spi1 3469 qup_spi1_cs: qup-spi1-cs-state {
3800 pins = "gpio7 3470 pins = "gpio7";
3801 function = "q 3471 function = "qup1";
3802 }; 3472 };
3803 3473
3804 qup_spi1_data_clk: qu 3474 qup_spi1_data_clk: qup-spi1-data-clk-state {
3805 pins = "gpio4 3475 pins = "gpio4", "gpio5", "gpio6";
3806 function = "q 3476 function = "qup1";
3807 }; 3477 };
3808 3478
3809 qup_spi2_cs: qup-spi2 3479 qup_spi2_cs: qup-spi2-cs-state {
3810 pins = "gpio1 3480 pins = "gpio11";
3811 function = "q 3481 function = "qup2";
3812 }; 3482 };
3813 3483
3814 qup_spi2_data_clk: qu 3484 qup_spi2_data_clk: qup-spi2-data-clk-state {
3815 pins = "gpio8 3485 pins = "gpio8", "gpio9", "gpio10";
3816 function = "q 3486 function = "qup2";
3817 }; 3487 };
3818 3488
3819 qup_spi3_cs: qup-spi3 3489 qup_spi3_cs: qup-spi3-cs-state {
3820 pins = "gpio1 3490 pins = "gpio15";
3821 function = "q 3491 function = "qup3";
3822 }; 3492 };
3823 3493
3824 qup_spi3_data_clk: qu 3494 qup_spi3_data_clk: qup-spi3-data-clk-state {
3825 pins = "gpio1 3495 pins = "gpio12", "gpio13", "gpio14";
3826 function = "q 3496 function = "qup3";
3827 }; 3497 };
3828 3498
3829 qup_spi4_cs: qup-spi4 3499 qup_spi4_cs: qup-spi4-cs-state {
3830 pins = "gpio1 3500 pins = "gpio19";
3831 function = "q 3501 function = "qup4";
3832 drive-strengt 3502 drive-strength = <6>;
3833 bias-disable; 3503 bias-disable;
3834 }; 3504 };
3835 3505
3836 qup_spi4_data_clk: qu 3506 qup_spi4_data_clk: qup-spi4-data-clk-state {
3837 pins = "gpio1 3507 pins = "gpio16", "gpio17", "gpio18";
3838 function = "q 3508 function = "qup4";
3839 }; 3509 };
3840 3510
3841 qup_spi5_cs: qup-spi5 3511 qup_spi5_cs: qup-spi5-cs-state {
3842 pins = "gpio8 3512 pins = "gpio85";
3843 function = "q 3513 function = "qup5";
3844 }; 3514 };
3845 3515
3846 qup_spi5_data_clk: qu 3516 qup_spi5_data_clk: qup-spi5-data-clk-state {
3847 pins = "gpio2 3517 pins = "gpio206", "gpio207", "gpio84";
3848 function = "q 3518 function = "qup5";
3849 }; 3519 };
3850 3520
3851 qup_spi6_cs: qup-spi6 3521 qup_spi6_cs: qup-spi6-cs-state {
3852 pins = "gpio2 3522 pins = "gpio23";
3853 function = "q 3523 function = "qup6";
3854 }; 3524 };
3855 3525
3856 qup_spi6_data_clk: qu 3526 qup_spi6_data_clk: qup-spi6-data-clk-state {
3857 pins = "gpio2 3527 pins = "gpio20", "gpio21", "gpio22";
3858 function = "q 3528 function = "qup6";
3859 }; 3529 };
3860 3530
3861 qup_spi8_cs: qup-spi8 3531 qup_spi8_cs: qup-spi8-cs-state {
3862 pins = "gpio3 3532 pins = "gpio31";
3863 function = "q 3533 function = "qup8";
3864 }; 3534 };
3865 3535
3866 qup_spi8_data_clk: qu 3536 qup_spi8_data_clk: qup-spi8-data-clk-state {
3867 pins = "gpio2 3537 pins = "gpio28", "gpio29", "gpio30";
3868 function = "q 3538 function = "qup8";
3869 }; 3539 };
3870 3540
3871 qup_spi9_cs: qup-spi9 3541 qup_spi9_cs: qup-spi9-cs-state {
3872 pins = "gpio3 3542 pins = "gpio35";
3873 function = "q 3543 function = "qup9";
3874 }; 3544 };
3875 3545
3876 qup_spi9_data_clk: qu 3546 qup_spi9_data_clk: qup-spi9-data-clk-state {
3877 pins = "gpio3 3547 pins = "gpio32", "gpio33", "gpio34";
3878 function = "q 3548 function = "qup9";
3879 }; 3549 };
3880 3550
3881 qup_spi10_cs: qup-spi 3551 qup_spi10_cs: qup-spi10-cs-state {
3882 pins = "gpio3 3552 pins = "gpio39";
3883 function = "q 3553 function = "qup10";
3884 }; 3554 };
3885 3555
3886 qup_spi10_data_clk: q 3556 qup_spi10_data_clk: qup-spi10-data-clk-state {
3887 pins = "gpio3 3557 pins = "gpio36", "gpio37", "gpio38";
3888 function = "q 3558 function = "qup10";
3889 }; 3559 };
3890 3560
3891 qup_spi11_cs: qup-spi 3561 qup_spi11_cs: qup-spi11-cs-state {
3892 pins = "gpio4 3562 pins = "gpio43";
3893 function = "q 3563 function = "qup11";
3894 }; 3564 };
3895 3565
3896 qup_spi11_data_clk: q 3566 qup_spi11_data_clk: qup-spi11-data-clk-state {
3897 pins = "gpio4 3567 pins = "gpio40", "gpio41", "gpio42";
3898 function = "q 3568 function = "qup11";
3899 }; 3569 };
3900 3570
3901 qup_spi12_cs: qup-spi 3571 qup_spi12_cs: qup-spi12-cs-state {
3902 pins = "gpio4 3572 pins = "gpio47";
3903 function = "q 3573 function = "qup12";
3904 }; 3574 };
3905 3575
3906 qup_spi12_data_clk: q 3576 qup_spi12_data_clk: qup-spi12-data-clk-state {
3907 pins = "gpio4 3577 pins = "gpio44", "gpio45", "gpio46";
3908 function = "q 3578 function = "qup12";
3909 }; 3579 };
3910 3580
3911 qup_spi13_cs: qup-spi 3581 qup_spi13_cs: qup-spi13-cs-state {
3912 pins = "gpio5 3582 pins = "gpio51";
3913 function = "q 3583 function = "qup13";
3914 }; 3584 };
3915 3585
3916 qup_spi13_data_clk: q 3586 qup_spi13_data_clk: qup-spi13-data-clk-state {
3917 pins = "gpio4 3587 pins = "gpio48", "gpio49", "gpio50";
3918 function = "q 3588 function = "qup13";
3919 }; 3589 };
3920 3590
3921 qup_spi14_cs: qup-spi 3591 qup_spi14_cs: qup-spi14-cs-state {
3922 pins = "gpio5 3592 pins = "gpio55";
3923 function = "q 3593 function = "qup14";
3924 }; 3594 };
3925 3595
3926 qup_spi14_data_clk: q 3596 qup_spi14_data_clk: qup-spi14-data-clk-state {
3927 pins = "gpio5 3597 pins = "gpio52", "gpio53", "gpio54";
3928 function = "q 3598 function = "qup14";
3929 }; 3599 };
3930 3600
3931 qup_spi15_cs: qup-spi 3601 qup_spi15_cs: qup-spi15-cs-state {
3932 pins = "gpio5 3602 pins = "gpio59";
3933 function = "q 3603 function = "qup15";
3934 }; 3604 };
3935 3605
3936 qup_spi15_data_clk: q 3606 qup_spi15_data_clk: qup-spi15-data-clk-state {
3937 pins = "gpio5 3607 pins = "gpio56", "gpio57", "gpio58";
3938 function = "q 3608 function = "qup15";
3939 }; 3609 };
3940 3610
3941 qup_spi16_cs: qup-spi 3611 qup_spi16_cs: qup-spi16-cs-state {
3942 pins = "gpio6 3612 pins = "gpio63";
3943 function = "q 3613 function = "qup16";
3944 }; 3614 };
3945 3615
3946 qup_spi16_data_clk: q 3616 qup_spi16_data_clk: qup-spi16-data-clk-state {
3947 pins = "gpio6 3617 pins = "gpio60", "gpio61", "gpio62";
3948 function = "q 3618 function = "qup16";
3949 }; 3619 };
3950 3620
3951 qup_spi17_cs: qup-spi 3621 qup_spi17_cs: qup-spi17-cs-state {
3952 pins = "gpio6 3622 pins = "gpio67";
3953 function = "q 3623 function = "qup17";
3954 }; 3624 };
3955 3625
3956 qup_spi17_data_clk: q 3626 qup_spi17_data_clk: qup-spi17-data-clk-state {
3957 pins = "gpio6 3627 pins = "gpio64", "gpio65", "gpio66";
3958 function = "q 3628 function = "qup17";
3959 }; 3629 };
3960 3630
3961 qup_spi18_cs: qup-spi 3631 qup_spi18_cs: qup-spi18-cs-state {
3962 pins = "gpio7 3632 pins = "gpio71";
3963 function = "q 3633 function = "qup18";
3964 drive-strengt 3634 drive-strength = <6>;
3965 bias-disable; 3635 bias-disable;
3966 }; 3636 };
3967 3637
3968 qup_spi18_data_clk: q 3638 qup_spi18_data_clk: qup-spi18-data-clk-state {
3969 pins = "gpio6 3639 pins = "gpio68", "gpio69", "gpio70";
3970 function = "q 3640 function = "qup18";
3971 drive-strengt 3641 drive-strength = <6>;
3972 bias-disable; 3642 bias-disable;
3973 }; 3643 };
3974 3644
3975 qup_spi19_cs: qup-spi 3645 qup_spi19_cs: qup-spi19-cs-state {
3976 pins = "gpio7 3646 pins = "gpio75";
3977 function = "q 3647 function = "qup19";
3978 drive-strengt 3648 drive-strength = <6>;
3979 bias-disable; 3649 bias-disable;
3980 }; 3650 };
3981 3651
3982 qup_spi19_data_clk: q 3652 qup_spi19_data_clk: qup-spi19-data-clk-state {
3983 pins = "gpio7 3653 pins = "gpio72", "gpio73", "gpio74";
3984 function = "q 3654 function = "qup19";
3985 drive-strengt 3655 drive-strength = <6>;
3986 bias-disable; 3656 bias-disable;
3987 }; 3657 };
3988 3658
3989 qup_spi20_cs: qup-spi 3659 qup_spi20_cs: qup-spi20-cs-state {
3990 pins = "gpio7 3660 pins = "gpio79";
3991 function = "q 3661 function = "qup20";
3992 }; 3662 };
3993 3663
3994 qup_spi20_data_clk: q 3664 qup_spi20_data_clk: qup-spi20-data-clk-state {
3995 pins = "gpio7 3665 pins = "gpio76", "gpio77", "gpio78";
3996 function = "q 3666 function = "qup20";
3997 }; 3667 };
3998 3668
3999 qup_spi21_cs: qup-spi 3669 qup_spi21_cs: qup-spi21-cs-state {
4000 pins = "gpio8 3670 pins = "gpio83";
4001 function = "q 3671 function = "qup21";
4002 }; 3672 };
4003 3673
4004 qup_spi21_data_clk: q 3674 qup_spi21_data_clk: qup-spi21-data-clk-state {
4005 pins = "gpio8 3675 pins = "gpio80", "gpio81", "gpio82";
4006 function = "q 3676 function = "qup21";
4007 }; 3677 };
4008 3678
4009 qup_uart7_rx: qup-uar 3679 qup_uart7_rx: qup-uart7-rx-state {
4010 pins = "gpio2 3680 pins = "gpio26";
4011 function = "q 3681 function = "qup7";
4012 drive-strengt 3682 drive-strength = <2>;
4013 bias-disable; 3683 bias-disable;
4014 }; 3684 };
4015 3685
4016 qup_uart7_tx: qup-uar 3686 qup_uart7_tx: qup-uart7-tx-state {
4017 pins = "gpio2 3687 pins = "gpio27";
4018 function = "q 3688 function = "qup7";
4019 drive-strengt 3689 drive-strength = <2>;
4020 bias-disable; 3690 bias-disable;
4021 }; 3691 };
4022 3692
4023 qup_uart20_default: q 3693 qup_uart20_default: qup-uart20-default-state {
4024 pins = "gpio7 3694 pins = "gpio76", "gpio77", "gpio78", "gpio79";
4025 function = "q 3695 function = "qup20";
4026 }; 3696 };
4027 }; 3697 };
4028 3698
4029 lpass_tlmm: pinctrl@3440000 { 3699 lpass_tlmm: pinctrl@3440000 {
4030 compatible = "qcom,sm 3700 compatible = "qcom,sm8450-lpass-lpi-pinctrl";
4031 reg = <0 0x03440000 0 3701 reg = <0 0x03440000 0x0 0x20000>,
4032 <0 0x034d0000 0 3702 <0 0x034d0000 0x0 0x10000>;
4033 gpio-controller; 3703 gpio-controller;
4034 #gpio-cells = <2>; 3704 #gpio-cells = <2>;
4035 gpio-ranges = <&lpass 3705 gpio-ranges = <&lpass_tlmm 0 0 23>;
4036 3706
4037 clocks = <&q6prmcc LP 3707 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
4038 <&q6prmcc LP 3708 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
4039 clock-names = "core", 3709 clock-names = "core", "audio";
4040 3710
4041 tx_swr_active: tx-swr 3711 tx_swr_active: tx-swr-active-state {
4042 clk-pins { 3712 clk-pins {
4043 pins 3713 pins = "gpio0";
4044 funct 3714 function = "swr_tx_clk";
4045 drive 3715 drive-strength = <2>;
4046 slew- 3716 slew-rate = <1>;
4047 bias- 3717 bias-disable;
4048 }; 3718 };
4049 3719
4050 data-pins { 3720 data-pins {
4051 pins 3721 pins = "gpio1", "gpio2", "gpio14";
4052 funct 3722 function = "swr_tx_data";
4053 drive 3723 drive-strength = <2>;
4054 slew- 3724 slew-rate = <1>;
4055 bias- 3725 bias-bus-hold;
4056 }; 3726 };
4057 }; 3727 };
4058 3728
4059 rx_swr_active: rx-swr 3729 rx_swr_active: rx-swr-active-state {
4060 clk-pins { 3730 clk-pins {
4061 pins 3731 pins = "gpio3";
4062 funct 3732 function = "swr_rx_clk";
4063 drive 3733 drive-strength = <2>;
4064 slew- 3734 slew-rate = <1>;
4065 bias- 3735 bias-disable;
4066 }; 3736 };
4067 3737
4068 data-pins { 3738 data-pins {
4069 pins 3739 pins = "gpio4", "gpio5";
4070 funct 3740 function = "swr_rx_data";
4071 drive 3741 drive-strength = <2>;
4072 slew- 3742 slew-rate = <1>;
4073 bias- 3743 bias-bus-hold;
4074 }; 3744 };
4075 }; 3745 };
4076 3746
4077 dmic01_default: dmic0 3747 dmic01_default: dmic01-default-state {
4078 clk-pins { 3748 clk-pins {
4079 pins 3749 pins = "gpio6";
4080 funct 3750 function = "dmic1_clk";
4081 drive 3751 drive-strength = <8>;
4082 outpu 3752 output-high;
4083 }; 3753 };
4084 3754
4085 data-pins { 3755 data-pins {
4086 pins 3756 pins = "gpio7";
4087 funct 3757 function = "dmic1_data";
4088 drive 3758 drive-strength = <8>;
4089 }; 3759 };
4090 }; 3760 };
4091 3761
4092 dmic23_default: dmic2 !! 3762 dmic02_default: dmic02-default-state {
4093 clk-pins { 3763 clk-pins {
4094 pins 3764 pins = "gpio8";
4095 funct 3765 function = "dmic2_clk";
4096 drive 3766 drive-strength = <8>;
4097 outpu 3767 output-high;
4098 }; 3768 };
4099 3769
4100 data-pins { 3770 data-pins {
4101 pins 3771 pins = "gpio9";
4102 funct 3772 function = "dmic2_data";
4103 drive 3773 drive-strength = <8>;
4104 }; 3774 };
4105 }; 3775 };
4106 3776
4107 wsa_swr_active: wsa-s 3777 wsa_swr_active: wsa-swr-active-state {
4108 clk-pins { 3778 clk-pins {
4109 pins 3779 pins = "gpio10";
4110 funct 3780 function = "wsa_swr_clk";
4111 drive 3781 drive-strength = <2>;
4112 slew- 3782 slew-rate = <1>;
4113 bias- 3783 bias-disable;
4114 }; 3784 };
4115 3785
4116 data-pins { 3786 data-pins {
4117 pins 3787 pins = "gpio11";
4118 funct 3788 function = "wsa_swr_data";
4119 drive 3789 drive-strength = <2>;
4120 slew- 3790 slew-rate = <1>;
4121 bias- 3791 bias-bus-hold;
4122 }; 3792 };
4123 }; 3793 };
4124 3794
4125 wsa2_swr_active: wsa2 3795 wsa2_swr_active: wsa2-swr-active-state {
4126 clk-pins { 3796 clk-pins {
4127 pins 3797 pins = "gpio15";
4128 funct 3798 function = "wsa2_swr_clk";
4129 drive 3799 drive-strength = <2>;
4130 slew- 3800 slew-rate = <1>;
4131 bias- 3801 bias-disable;
4132 }; 3802 };
4133 3803
4134 data-pins { 3804 data-pins {
4135 pins 3805 pins = "gpio16";
4136 funct 3806 function = "wsa2_swr_data";
4137 drive 3807 drive-strength = <2>;
4138 slew- 3808 slew-rate = <1>;
4139 bias- 3809 bias-bus-hold;
4140 }; 3810 };
4141 }; 3811 };
4142 }; 3812 };
4143 3813
4144 sram@146aa000 { 3814 sram@146aa000 {
4145 compatible = "qcom,sm 3815 compatible = "qcom,sm8450-imem", "syscon", "simple-mfd";
4146 reg = <0 0x146aa000 0 3816 reg = <0 0x146aa000 0 0x1000>;
4147 ranges = <0 0 0x146aa 3817 ranges = <0 0 0x146aa000 0x1000>;
4148 3818
4149 #address-cells = <1>; 3819 #address-cells = <1>;
4150 #size-cells = <1>; 3820 #size-cells = <1>;
4151 3821
4152 pil-reloc@94c { 3822 pil-reloc@94c {
4153 compatible = 3823 compatible = "qcom,pil-reloc-info";
4154 reg = <0x94c 3824 reg = <0x94c 0xc8>;
4155 }; 3825 };
4156 }; 3826 };
4157 3827
4158 apps_smmu: iommu@15000000 { 3828 apps_smmu: iommu@15000000 {
4159 compatible = "qcom,sm 3829 compatible = "qcom,sm8450-smmu-500", "arm,mmu-500";
4160 reg = <0 0x15000000 0 3830 reg = <0 0x15000000 0 0x100000>;
4161 #iommu-cells = <2>; 3831 #iommu-cells = <2>;
4162 #global-interrupts = 3832 #global-interrupts = <1>;
4163 interrupts = <GIC_SPI 3833 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
4164 <GIC_SPI 3834 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
4165 <GIC_SPI 3835 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
4166 <GIC_SPI 3836 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
4167 <GIC_SPI 3837 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
4168 <GIC_SPI 3838 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
4169 <GIC_SPI 3839 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
4170 <GIC_SPI 3840 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
4171 <GIC_SPI 3841 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
4172 <GIC_SPI 3842 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
4173 <GIC_SPI 3843 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
4174 <GIC_SPI 3844 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
4175 <GIC_SPI 3845 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
4176 <GIC_SPI 3846 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
4177 <GIC_SPI 3847 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
4178 <GIC_SPI 3848 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
4179 <GIC_SPI 3849 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
4180 <GIC_SPI 3850 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
4181 <GIC_SPI 3851 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
4182 <GIC_SPI 3852 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
4183 <GIC_SPI 3853 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
4184 <GIC_SPI 3854 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
4185 <GIC_SPI 3855 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
4186 <GIC_SPI 3856 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
4187 <GIC_SPI 3857 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
4188 <GIC_SPI 3858 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
4189 <GIC_SPI 3859 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
4190 <GIC_SPI 3860 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
4191 <GIC_SPI 3861 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
4192 <GIC_SPI 3862 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
4193 <GIC_SPI 3863 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
4194 <GIC_SPI 3864 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
4195 <GIC_SPI 3865 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
4196 <GIC_SPI 3866 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
4197 <GIC_SPI 3867 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
4198 <GIC_SPI 3868 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
4199 <GIC_SPI 3869 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
4200 <GIC_SPI 3870 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
4201 <GIC_SPI 3871 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
4202 <GIC_SPI 3872 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
4203 <GIC_SPI 3873 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
4204 <GIC_SPI 3874 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
4205 <GIC_SPI 3875 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
4206 <GIC_SPI 3876 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
4207 <GIC_SPI 3877 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
4208 <GIC_SPI 3878 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
4209 <GIC_SPI 3879 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
4210 <GIC_SPI 3880 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
4211 <GIC_SPI 3881 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
4212 <GIC_SPI 3882 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
4213 <GIC_SPI 3883 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
4214 <GIC_SPI 3884 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
4215 <GIC_SPI 3885 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
4216 <GIC_SPI 3886 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
4217 <GIC_SPI 3887 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
4218 <GIC_SPI 3888 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
4219 <GIC_SPI 3889 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
4220 <GIC_SPI 3890 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
4221 <GIC_SPI 3891 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
4222 <GIC_SPI 3892 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
4223 <GIC_SPI 3893 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
4224 <GIC_SPI 3894 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
4225 <GIC_SPI 3895 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
4226 <GIC_SPI 3896 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
4227 <GIC_SPI 3897 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
4228 <GIC_SPI 3898 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
4229 <GIC_SPI 3899 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
4230 <GIC_SPI 3900 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
4231 <GIC_SPI 3901 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
4232 <GIC_SPI 3902 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
4233 <GIC_SPI 3903 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
4234 <GIC_SPI 3904 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
4235 <GIC_SPI 3905 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
4236 <GIC_SPI 3906 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
4237 <GIC_SPI 3907 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
4238 <GIC_SPI 3908 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
4239 <GIC_SPI 3909 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
4240 <GIC_SPI 3910 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
4241 <GIC_SPI 3911 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
4242 <GIC_SPI 3912 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
4243 <GIC_SPI 3913 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
4244 <GIC_SPI 3914 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
4245 <GIC_SPI 3915 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
4246 <GIC_SPI 3916 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
4247 <GIC_SPI 3917 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
4248 <GIC_SPI 3918 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
4249 <GIC_SPI 3919 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
4250 <GIC_SPI 3920 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
4251 <GIC_SPI 3921 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
4252 <GIC_SPI 3922 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
4253 <GIC_SPI 3923 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
4254 <GIC_SPI 3924 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
4255 <GIC_SPI 3925 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
4256 <GIC_SPI 3926 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
4257 <GIC_SPI 3927 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
4258 <GIC_SPI 3928 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
4259 <GIC_SPI 3929 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>;
4260 }; 3930 };
4261 3931
4262 intc: interrupt-controller@17 3932 intc: interrupt-controller@17100000 {
4263 compatible = "arm,gic 3933 compatible = "arm,gic-v3";
4264 #interrupt-cells = <3 3934 #interrupt-cells = <3>;
4265 interrupt-controller; 3935 interrupt-controller;
4266 #redistributor-region 3936 #redistributor-regions = <1>;
4267 redistributor-stride 3937 redistributor-stride = <0x0 0x40000>;
4268 reg = <0x0 0x17100000 3938 reg = <0x0 0x17100000 0x0 0x10000>, /* GICD */
4269 <0x0 0x17180000 3939 <0x0 0x17180000 0x0 0x200000>; /* GICR * 8 */
4270 interrupts = <GIC_PPI 3940 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
4271 #address-cells = <2>; 3941 #address-cells = <2>;
4272 #size-cells = <2>; 3942 #size-cells = <2>;
4273 ranges; 3943 ranges;
4274 3944
4275 gic_its: msi-controll 3945 gic_its: msi-controller@17140000 {
4276 compatible = 3946 compatible = "arm,gic-v3-its";
4277 reg = <0x0 0x 3947 reg = <0x0 0x17140000 0x0 0x20000>;
4278 msi-controlle 3948 msi-controller;
4279 #msi-cells = 3949 #msi-cells = <1>;
4280 }; 3950 };
4281 }; 3951 };
4282 3952
4283 timer@17420000 { 3953 timer@17420000 {
4284 compatible = "arm,arm 3954 compatible = "arm,armv7-timer-mem";
4285 #address-cells = <1>; 3955 #address-cells = <1>;
4286 #size-cells = <1>; 3956 #size-cells = <1>;
4287 ranges = <0 0 0 0x200 3957 ranges = <0 0 0 0x20000000>;
4288 reg = <0x0 0x17420000 3958 reg = <0x0 0x17420000 0x0 0x1000>;
4289 clock-frequency = <19 3959 clock-frequency = <19200000>;
4290 3960
4291 frame@17421000 { 3961 frame@17421000 {
4292 frame-number 3962 frame-number = <0>;
4293 interrupts = 3963 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
4294 3964 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
4295 reg = <0x1742 3965 reg = <0x17421000 0x1000>,
4296 <0x1742 3966 <0x17422000 0x1000>;
4297 }; 3967 };
4298 3968
4299 frame@17423000 { 3969 frame@17423000 {
4300 frame-number 3970 frame-number = <1>;
4301 interrupts = 3971 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
4302 reg = <0x1742 3972 reg = <0x17423000 0x1000>;
4303 status = "dis 3973 status = "disabled";
4304 }; 3974 };
4305 3975
4306 frame@17425000 { 3976 frame@17425000 {
4307 frame-number 3977 frame-number = <2>;
4308 interrupts = 3978 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
4309 reg = <0x1742 3979 reg = <0x17425000 0x1000>;
4310 status = "dis 3980 status = "disabled";
4311 }; 3981 };
4312 3982
4313 frame@17427000 { 3983 frame@17427000 {
4314 frame-number 3984 frame-number = <3>;
4315 interrupts = 3985 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
4316 reg = <0x1742 3986 reg = <0x17427000 0x1000>;
4317 status = "dis 3987 status = "disabled";
4318 }; 3988 };
4319 3989
4320 frame@17429000 { 3990 frame@17429000 {
4321 frame-number 3991 frame-number = <4>;
4322 interrupts = 3992 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
4323 reg = <0x1742 3993 reg = <0x17429000 0x1000>;
4324 status = "dis 3994 status = "disabled";
4325 }; 3995 };
4326 3996
4327 frame@1742b000 { 3997 frame@1742b000 {
4328 frame-number 3998 frame-number = <5>;
4329 interrupts = 3999 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
4330 reg = <0x1742 4000 reg = <0x1742b000 0x1000>;
4331 status = "dis 4001 status = "disabled";
4332 }; 4002 };
4333 4003
4334 frame@1742d000 { 4004 frame@1742d000 {
4335 frame-number 4005 frame-number = <6>;
4336 interrupts = 4006 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
4337 reg = <0x1742 4007 reg = <0x1742d000 0x1000>;
4338 status = "dis 4008 status = "disabled";
4339 }; 4009 };
4340 }; 4010 };
4341 4011
4342 apps_rsc: rsc@17a00000 { 4012 apps_rsc: rsc@17a00000 {
4343 label = "apps_rsc"; 4013 label = "apps_rsc";
4344 compatible = "qcom,rp 4014 compatible = "qcom,rpmh-rsc";
4345 reg = <0x0 0x17a00000 4015 reg = <0x0 0x17a00000 0x0 0x10000>,
4346 <0x0 0x17a10000 4016 <0x0 0x17a10000 0x0 0x10000>,
4347 <0x0 0x17a20000 4017 <0x0 0x17a20000 0x0 0x10000>,
4348 <0x0 0x17a30000 4018 <0x0 0x17a30000 0x0 0x10000>;
4349 reg-names = "drv-0", 4019 reg-names = "drv-0", "drv-1", "drv-2", "drv-3";
4350 interrupts = <GIC_SPI 4020 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
4351 <GIC_SPI 4021 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
4352 <GIC_SPI 4022 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
4353 qcom,tcs-offset = <0x 4023 qcom,tcs-offset = <0xd00>;
4354 qcom,drv-id = <2>; 4024 qcom,drv-id = <2>;
4355 qcom,tcs-config = <AC 4025 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
4356 <WA 4026 <WAKE_TCS 2>, <CONTROL_TCS 0>;
4357 power-domains = <&CLU 4027 power-domains = <&CLUSTER_PD>;
4358 4028
4359 apps_bcm_voter: bcm-v 4029 apps_bcm_voter: bcm-voter {
4360 compatible = 4030 compatible = "qcom,bcm-voter";
4361 }; 4031 };
4362 4032
4363 rpmhcc: clock-control 4033 rpmhcc: clock-controller {
4364 compatible = 4034 compatible = "qcom,sm8450-rpmh-clk";
4365 #clock-cells 4035 #clock-cells = <1>;
4366 clock-names = 4036 clock-names = "xo";
4367 clocks = <&xo 4037 clocks = <&xo_board>;
4368 }; 4038 };
4369 4039
4370 rpmhpd: power-control 4040 rpmhpd: power-controller {
4371 compatible = 4041 compatible = "qcom,sm8450-rpmhpd";
4372 #power-domain 4042 #power-domain-cells = <1>;
4373 operating-poi 4043 operating-points-v2 = <&rpmhpd_opp_table>;
4374 4044
4375 rpmhpd_opp_ta 4045 rpmhpd_opp_table: opp-table {
4376 compa 4046 compatible = "operating-points-v2";
4377 4047
4378 rpmhp 4048 rpmhpd_opp_ret: opp1 {
4379 4049 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4380 }; 4050 };
4381 4051
4382 rpmhp 4052 rpmhpd_opp_min_svs: opp2 {
4383 4053 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4384 }; 4054 };
4385 4055
4386 rpmhp 4056 rpmhpd_opp_low_svs_d1: opp3 {
4387 4057 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
4388 }; 4058 };
4389 4059
4390 rpmhp 4060 rpmhpd_opp_low_svs: opp4 {
4391 4061 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4392 }; 4062 };
4393 4063
4394 rpmhp 4064 rpmhpd_opp_low_svs_l1: opp5 {
4395 4065 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
4396 }; 4066 };
4397 4067
4398 rpmhp 4068 rpmhpd_opp_svs: opp6 {
4399 4069 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4400 }; 4070 };
4401 4071
4402 rpmhp 4072 rpmhpd_opp_svs_l0: opp7 {
4403 4073 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
4404 }; 4074 };
4405 4075
4406 rpmhp 4076 rpmhpd_opp_svs_l1: opp8 {
4407 4077 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4408 }; 4078 };
4409 4079
4410 rpmhp 4080 rpmhpd_opp_svs_l2: opp9 {
4411 4081 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
4412 }; 4082 };
4413 4083
4414 rpmhp 4084 rpmhpd_opp_nom: opp10 {
4415 4085 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4416 }; 4086 };
4417 4087
4418 rpmhp 4088 rpmhpd_opp_nom_l1: opp11 {
4419 4089 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4420 }; 4090 };
4421 4091
4422 rpmhp 4092 rpmhpd_opp_nom_l2: opp12 {
4423 4093 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4424 }; 4094 };
4425 4095
4426 rpmhp 4096 rpmhpd_opp_turbo: opp13 {
4427 4097 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4428 }; 4098 };
4429 4099
4430 rpmhp 4100 rpmhpd_opp_turbo_l1: opp14 {
4431 4101 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4432 }; 4102 };
4433 }; 4103 };
4434 }; 4104 };
4435 }; 4105 };
4436 4106
4437 cpufreq_hw: cpufreq@17d91000 4107 cpufreq_hw: cpufreq@17d91000 {
4438 compatible = "qcom,sm 4108 compatible = "qcom,sm8450-cpufreq-epss", "qcom,cpufreq-epss";
4439 reg = <0 0x17d91000 0 4109 reg = <0 0x17d91000 0 0x1000>,
4440 <0 0x17d92000 0 4110 <0 0x17d92000 0 0x1000>,
4441 <0 0x17d93000 0 4111 <0 0x17d93000 0 0x1000>;
4442 reg-names = "freq-dom 4112 reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
4443 clocks = <&rpmhcc RPM 4113 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
4444 clock-names = "xo", " 4114 clock-names = "xo", "alternate";
4445 interrupts = <GIC_SPI 4115 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
4446 <GIC_SPI 4116 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
4447 <GIC_SPI 4117 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
4448 interrupt-names = "dc 4118 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
4449 #freq-domain-cells = 4119 #freq-domain-cells = <1>;
4450 #clock-cells = <1>; 4120 #clock-cells = <1>;
4451 }; 4121 };
4452 4122
4453 gem_noc: interconnect@1910000 4123 gem_noc: interconnect@19100000 {
4454 compatible = "qcom,sm 4124 compatible = "qcom,sm8450-gem-noc";
4455 reg = <0 0x19100000 0 4125 reg = <0 0x19100000 0 0xbb800>;
4456 #interconnect-cells = 4126 #interconnect-cells = <2>;
4457 qcom,bcm-voters = <&a 4127 qcom,bcm-voters = <&apps_bcm_voter>;
4458 }; 4128 };
4459 4129
4460 system-cache-controller@19200 4130 system-cache-controller@19200000 {
4461 compatible = "qcom,sm 4131 compatible = "qcom,sm8450-llcc";
4462 reg = <0 0x19200000 0 4132 reg = <0 0x19200000 0 0x80000>, <0 0x19600000 0 0x80000>,
4463 <0 0x19300000 0 4133 <0 0x19300000 0 0x80000>, <0 0x19700000 0 0x80000>,
4464 <0 0x19a00000 0 !! 4134 <0 0x19a00000 0 0x80000>;
4465 reg-names = "llcc0_ba 4135 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
4466 "llcc3_ba !! 4136 "llcc3_base", "llcc_broadcast_base";
4467 "llcc_bro <<
4468 interrupts = <GIC_SPI 4137 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
4469 }; 4138 };
4470 4139
4471 ufs_mem_hc: ufshc@1d84000 { 4140 ufs_mem_hc: ufshc@1d84000 {
4472 compatible = "qcom,sm 4141 compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
4473 "jedec,u 4142 "jedec,ufs-2.0";
4474 reg = <0 0x01d84000 0 4143 reg = <0 0x01d84000 0 0x3000>;
4475 interrupts = <GIC_SPI 4144 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
4476 phys = <&ufs_mem_phy> !! 4145 phys = <&ufs_mem_phy_lanes>;
4477 phy-names = "ufsphy"; 4146 phy-names = "ufsphy";
4478 lanes-per-direction = 4147 lanes-per-direction = <2>;
4479 #reset-cells = <1>; 4148 #reset-cells = <1>;
4480 resets = <&gcc GCC_UF 4149 resets = <&gcc GCC_UFS_PHY_BCR>;
4481 reset-names = "rst"; 4150 reset-names = "rst";
4482 4151
4483 power-domains = <&gcc 4152 power-domains = <&gcc UFS_PHY_GDSC>;
4484 4153
4485 iommus = <&apps_smmu 4154 iommus = <&apps_smmu 0xe0 0x0>;
4486 dma-coherent; 4155 dma-coherent;
4487 4156
4488 interconnects = <&agg 4157 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>,
4489 <&gem 4158 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
4490 interconnect-names = 4159 interconnect-names = "ufs-ddr", "cpu-ufs";
4491 clock-names = 4160 clock-names =
4492 "core_clk", 4161 "core_clk",
4493 "bus_aggr_clk 4162 "bus_aggr_clk",
4494 "iface_clk", 4163 "iface_clk",
4495 "core_clk_uni 4164 "core_clk_unipro",
4496 "ref_clk", 4165 "ref_clk",
4497 "tx_lane0_syn 4166 "tx_lane0_sync_clk",
4498 "rx_lane0_syn 4167 "rx_lane0_sync_clk",
4499 "rx_lane1_syn 4168 "rx_lane1_sync_clk";
4500 clocks = 4169 clocks =
4501 <&gcc GCC_UFS 4170 <&gcc GCC_UFS_PHY_AXI_CLK>,
4502 <&gcc GCC_AGG 4171 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
4503 <&gcc GCC_UFS 4172 <&gcc GCC_UFS_PHY_AHB_CLK>,
4504 <&gcc GCC_UFS 4173 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
4505 <&rpmhcc RPMH 4174 <&rpmhcc RPMH_CXO_CLK>,
4506 <&gcc GCC_UFS 4175 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
4507 <&gcc GCC_UFS 4176 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
4508 <&gcc GCC_UFS 4177 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
4509 freq-table-hz = 4178 freq-table-hz =
4510 <75000000 300 4179 <75000000 300000000>,
4511 <0 0>, 4180 <0 0>,
4512 <0 0>, 4181 <0 0>,
4513 <75000000 300 4182 <75000000 300000000>,
4514 <75000000 300 4183 <75000000 300000000>,
4515 <0 0>, 4184 <0 0>,
4516 <0 0>, 4185 <0 0>,
4517 <0 0>; 4186 <0 0>;
4518 qcom,ice = <&ice>; 4187 qcom,ice = <&ice>;
4519 4188
4520 status = "disabled"; 4189 status = "disabled";
4521 }; 4190 };
4522 4191
4523 ufs_mem_phy: phy@1d87000 { 4192 ufs_mem_phy: phy@1d87000 {
4524 compatible = "qcom,sm 4193 compatible = "qcom,sm8450-qmp-ufs-phy";
4525 reg = <0 0x01d87000 0 !! 4194 reg = <0 0x01d87000 0 0x1c4>;
4526 !! 4195 #address-cells = <2>;
>> 4196 #size-cells = <2>;
>> 4197 ranges;
4527 clock-names = "ref", 4198 clock-names = "ref", "ref_aux", "qref";
4528 clocks = <&rpmhcc RPM 4199 clocks = <&rpmhcc RPMH_CXO_CLK>,
4529 <&gcc GCC_UF 4200 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
4530 <&gcc GCC_UF 4201 <&gcc GCC_UFS_0_CLKREF_EN>;
4531 4202
4532 power-domains = <&gcc 4203 power-domains = <&gcc UFS_PHY_GDSC>;
4533 4204
4534 resets = <&ufs_mem_hc 4205 resets = <&ufs_mem_hc 0>;
4535 reset-names = "ufsphy 4206 reset-names = "ufsphy";
4536 <<
4537 #clock-cells = <1>; <<
4538 #phy-cells = <0>; <<
4539 <<
4540 status = "disabled"; 4207 status = "disabled";
>> 4208
>> 4209 ufs_mem_phy_lanes: phy@1d87400 {
>> 4210 reg = <0 0x01d87400 0 0x188>,
>> 4211 <0 0x01d87600 0 0x200>,
>> 4212 <0 0x01d87c00 0 0x200>,
>> 4213 <0 0x01d87800 0 0x188>,
>> 4214 <0 0x01d87a00 0 0x200>;
>> 4215 #clock-cells = <1>;
>> 4216 #phy-cells = <0>;
>> 4217 };
4541 }; 4218 };
4542 4219
4543 ice: crypto@1d88000 { 4220 ice: crypto@1d88000 {
4544 compatible = "qcom,sm 4221 compatible = "qcom,sm8450-inline-crypto-engine",
4545 "qcom,in 4222 "qcom,inline-crypto-engine";
4546 reg = <0 0x01d88000 0 4223 reg = <0 0x01d88000 0 0x8000>;
4547 clocks = <&gcc GCC_UF 4224 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
4548 }; 4225 };
4549 4226
4550 cryptobam: dma-controller@1dc 4227 cryptobam: dma-controller@1dc4000 {
4551 compatible = "qcom,ba 4228 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
4552 reg = <0 0x01dc4000 0 4229 reg = <0 0x01dc4000 0 0x28000>;
4553 interrupts = <GIC_SPI 4230 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
4554 #dma-cells = <1>; 4231 #dma-cells = <1>;
4555 qcom,ee = <0>; 4232 qcom,ee = <0>;
4556 qcom,controlled-remot 4233 qcom,controlled-remotely;
4557 iommus = <&apps_smmu 4234 iommus = <&apps_smmu 0x584 0x11>,
4558 <&apps_smmu 4235 <&apps_smmu 0x588 0x0>,
4559 <&apps_smmu 4236 <&apps_smmu 0x598 0x5>,
4560 <&apps_smmu 4237 <&apps_smmu 0x59a 0x0>,
4561 <&apps_smmu 4238 <&apps_smmu 0x59f 0x0>;
4562 }; 4239 };
4563 4240
4564 crypto: crypto@1dfa000 { 4241 crypto: crypto@1dfa000 {
4565 compatible = "qcom,sm 4242 compatible = "qcom,sm8450-qce", "qcom,sm8150-qce", "qcom,qce";
4566 reg = <0 0x01dfa000 0 4243 reg = <0 0x01dfa000 0 0x6000>;
4567 dmas = <&cryptobam 4> 4244 dmas = <&cryptobam 4>, <&cryptobam 5>;
4568 dma-names = "rx", "tx 4245 dma-names = "rx", "tx";
4569 iommus = <&apps_smmu 4246 iommus = <&apps_smmu 0x584 0x11>,
4570 <&apps_smmu 4247 <&apps_smmu 0x588 0x0>,
4571 <&apps_smmu 4248 <&apps_smmu 0x598 0x5>,
4572 <&apps_smmu 4249 <&apps_smmu 0x59a 0x0>,
4573 <&apps_smmu 4250 <&apps_smmu 0x59f 0x0>;
4574 interconnects = <&agg 4251 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
4575 interconnect-names = 4252 interconnect-names = "memory";
4576 }; 4253 };
4577 4254
4578 sdhc_2: mmc@8804000 { 4255 sdhc_2: mmc@8804000 {
4579 compatible = "qcom,sm 4256 compatible = "qcom,sm8450-sdhci", "qcom,sdhci-msm-v5";
4580 reg = <0 0x08804000 0 4257 reg = <0 0x08804000 0 0x1000>;
4581 4258
4582 interrupts = <GIC_SPI 4259 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
4583 <GIC_SPI 4260 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
4584 interrupt-names = "hc 4261 interrupt-names = "hc_irq", "pwr_irq";
4585 4262
4586 clocks = <&gcc GCC_SD 4263 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
4587 <&gcc GCC_SD 4264 <&gcc GCC_SDCC2_APPS_CLK>,
4588 <&rpmhcc RPM 4265 <&rpmhcc RPMH_CXO_CLK>;
4589 clock-names = "iface" 4266 clock-names = "iface", "core", "xo";
4590 resets = <&gcc GCC_SD 4267 resets = <&gcc GCC_SDCC2_BCR>;
4591 interconnects = <&agg 4268 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
4592 <&gem 4269 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
4593 interconnect-names = 4270 interconnect-names = "sdhc-ddr","cpu-sdhc";
4594 iommus = <&apps_smmu 4271 iommus = <&apps_smmu 0x4a0 0x0>;
4595 power-domains = <&rpm 4272 power-domains = <&rpmhpd RPMHPD_CX>;
4596 operating-points-v2 = 4273 operating-points-v2 = <&sdhc2_opp_table>;
4597 bus-width = <4>; 4274 bus-width = <4>;
4598 dma-coherent; 4275 dma-coherent;
4599 4276
4600 /* Forbid SDR104/SDR5 4277 /* Forbid SDR104/SDR50 - broken hw! */
4601 sdhci-caps-mask = <0x 4278 sdhci-caps-mask = <0x3 0x0>;
4602 4279
4603 status = "disabled"; 4280 status = "disabled";
4604 4281
4605 sdhc2_opp_table: opp- 4282 sdhc2_opp_table: opp-table {
4606 compatible = 4283 compatible = "operating-points-v2";
4607 4284
4608 opp-100000000 4285 opp-100000000 {
4609 opp-h 4286 opp-hz = /bits/ 64 <100000000>;
4610 requi 4287 required-opps = <&rpmhpd_opp_low_svs>;
4611 }; 4288 };
4612 4289
4613 opp-202000000 4290 opp-202000000 {
4614 opp-h 4291 opp-hz = /bits/ 64 <202000000>;
4615 requi 4292 required-opps = <&rpmhpd_opp_svs_l1>;
4616 }; 4293 };
4617 }; 4294 };
4618 }; 4295 };
4619 4296
4620 usb_1: usb@a6f8800 { 4297 usb_1: usb@a6f8800 {
4621 compatible = "qcom,sm 4298 compatible = "qcom,sm8450-dwc3", "qcom,dwc3";
4622 reg = <0 0x0a6f8800 0 4299 reg = <0 0x0a6f8800 0 0x400>;
4623 status = "disabled"; 4300 status = "disabled";
4624 #address-cells = <2>; 4301 #address-cells = <2>;
4625 #size-cells = <2>; 4302 #size-cells = <2>;
4626 ranges; 4303 ranges;
4627 4304
4628 clocks = <&gcc GCC_CF 4305 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
4629 <&gcc GCC_US 4306 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
4630 <&gcc GCC_AG 4307 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
4631 <&gcc GCC_US 4308 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
4632 <&gcc GCC_US 4309 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4633 <&gcc GCC_US 4310 <&gcc GCC_USB3_0_CLKREF_EN>;
4634 clock-names = "cfg_no 4311 clock-names = "cfg_noc",
4635 "core", 4312 "core",
4636 "iface" 4313 "iface",
4637 "sleep" 4314 "sleep",
4638 "mock_u 4315 "mock_utmi",
4639 "xo"; 4316 "xo";
4640 4317
4641 assigned-clocks = <&g 4318 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4642 <&g 4319 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
4643 assigned-clock-rates 4320 assigned-clock-rates = <19200000>, <200000000>;
4644 4321
4645 interrupts-extended = 4322 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
4646 !! 4323 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
4647 <<
4648 4324 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
4649 !! 4325 <&pdc 14 IRQ_TYPE_EDGE_BOTH>;
4650 interrupt-names = "pw !! 4326 interrupt-names = "hs_phy_irq",
4651 "hs !! 4327 "ss_phy_irq",
4652 "dp <<
4653 "dm 4328 "dm_hs_phy_irq",
4654 "ss !! 4329 "dp_hs_phy_irq";
4655 4330
4656 power-domains = <&gcc 4331 power-domains = <&gcc USB30_PRIM_GDSC>;
4657 4332
4658 resets = <&gcc GCC_US 4333 resets = <&gcc GCC_USB30_PRIM_BCR>;
4659 4334
4660 interconnects = <&agg 4335 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
4661 <&gem 4336 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
4662 interconnect-names = 4337 interconnect-names = "usb-ddr", "apps-usb";
4663 4338
4664 usb_1_dwc3: usb@a6000 4339 usb_1_dwc3: usb@a600000 {
4665 compatible = 4340 compatible = "snps,dwc3";
4666 reg = <0 0x0a 4341 reg = <0 0x0a600000 0 0xcd00>;
4667 interrupts = 4342 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
4668 iommus = <&ap 4343 iommus = <&apps_smmu 0x0 0x0>;
4669 snps,dis_u2_s 4344 snps,dis_u2_susphy_quirk;
4670 snps,dis_enbl 4345 snps,dis_enblslpm_quirk;
4671 phys = <&usb_ 4346 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
4672 phy-names = " 4347 phy-names = "usb2-phy", "usb3-phy";
4673 4348
4674 ports { 4349 ports {
4675 #addr 4350 #address-cells = <1>;
4676 #size 4351 #size-cells = <0>;
4677 4352
4678 port@ 4353 port@0 {
4679 4354 reg = <0>;
4680 4355
4681 4356 usb_1_dwc3_hs: endpoint {
4682 4357 };
4683 }; 4358 };
4684 4359
4685 port@ 4360 port@1 {
4686 4361 reg = <1>;
4687 4362
4688 4363 usb_1_dwc3_ss: endpoint {
4689 <<
4690 4364 };
4691 }; 4365 };
4692 }; 4366 };
4693 }; 4367 };
4694 }; 4368 };
4695 4369
4696 nsp_noc: interconnect@320c000 4370 nsp_noc: interconnect@320c0000 {
4697 compatible = "qcom,sm 4371 compatible = "qcom,sm8450-nsp-noc";
4698 reg = <0 0x320c0000 0 4372 reg = <0 0x320c0000 0 0x10000>;
4699 #interconnect-cells = 4373 #interconnect-cells = <2>;
4700 qcom,bcm-voters = <&a 4374 qcom,bcm-voters = <&apps_bcm_voter>;
4701 }; 4375 };
4702 4376
4703 lpass_ag_noc: interconnect@3c 4377 lpass_ag_noc: interconnect@3c40000 {
4704 compatible = "qcom,sm 4378 compatible = "qcom,sm8450-lpass-ag-noc";
4705 reg = <0 0x03c40000 0 4379 reg = <0 0x03c40000 0 0x17200>;
4706 #interconnect-cells = 4380 #interconnect-cells = <2>;
4707 qcom,bcm-voters = <&a 4381 qcom,bcm-voters = <&apps_bcm_voter>;
4708 }; 4382 };
4709 }; 4383 };
4710 4384
4711 sound: sound { 4385 sound: sound {
4712 }; 4386 };
4713 4387
4714 thermal-zones { 4388 thermal-zones {
4715 aoss0-thermal { 4389 aoss0-thermal {
>> 4390 polling-delay-passive = <0>;
>> 4391 polling-delay = <0>;
4716 thermal-sensors = <&t 4392 thermal-sensors = <&tsens0 0>;
4717 4393
4718 trips { 4394 trips {
4719 thermal-engin 4395 thermal-engine-config {
4720 tempe 4396 temperature = <125000>;
4721 hyste 4397 hysteresis = <1000>;
4722 type 4398 type = "passive";
4723 }; 4399 };
4724 4400
4725 reset-mon-cfg 4401 reset-mon-cfg {
4726 tempe 4402 temperature = <115000>;
4727 hyste 4403 hysteresis = <5000>;
4728 type 4404 type = "passive";
4729 }; 4405 };
4730 }; 4406 };
4731 }; 4407 };
4732 4408
4733 cpuss0-thermal { 4409 cpuss0-thermal {
>> 4410 polling-delay-passive = <0>;
>> 4411 polling-delay = <0>;
4734 thermal-sensors = <&t 4412 thermal-sensors = <&tsens0 1>;
4735 4413
4736 trips { 4414 trips {
4737 thermal-engin 4415 thermal-engine-config {
4738 tempe 4416 temperature = <125000>;
4739 hyste 4417 hysteresis = <1000>;
4740 type 4418 type = "passive";
4741 }; 4419 };
4742 4420
4743 reset-mon-cfg 4421 reset-mon-cfg {
4744 tempe 4422 temperature = <115000>;
4745 hyste 4423 hysteresis = <5000>;
4746 type 4424 type = "passive";
4747 }; 4425 };
4748 }; 4426 };
4749 }; 4427 };
4750 4428
4751 cpuss1-thermal { 4429 cpuss1-thermal {
>> 4430 polling-delay-passive = <0>;
>> 4431 polling-delay = <0>;
4752 thermal-sensors = <&t 4432 thermal-sensors = <&tsens0 2>;
4753 4433
4754 trips { 4434 trips {
4755 thermal-engin 4435 thermal-engine-config {
4756 tempe 4436 temperature = <125000>;
4757 hyste 4437 hysteresis = <1000>;
4758 type 4438 type = "passive";
4759 }; 4439 };
4760 4440
4761 reset-mon-cfg 4441 reset-mon-cfg {
4762 tempe 4442 temperature = <115000>;
4763 hyste 4443 hysteresis = <5000>;
4764 type 4444 type = "passive";
4765 }; 4445 };
4766 }; 4446 };
4767 }; 4447 };
4768 4448
4769 cpuss3-thermal { 4449 cpuss3-thermal {
>> 4450 polling-delay-passive = <0>;
>> 4451 polling-delay = <0>;
4770 thermal-sensors = <&t 4452 thermal-sensors = <&tsens0 3>;
4771 4453
4772 trips { 4454 trips {
4773 thermal-engin 4455 thermal-engine-config {
4774 tempe 4456 temperature = <125000>;
4775 hyste 4457 hysteresis = <1000>;
4776 type 4458 type = "passive";
4777 }; 4459 };
4778 4460
4779 reset-mon-cfg 4461 reset-mon-cfg {
4780 tempe 4462 temperature = <115000>;
4781 hyste 4463 hysteresis = <5000>;
4782 type 4464 type = "passive";
4783 }; 4465 };
4784 }; 4466 };
4785 }; 4467 };
4786 4468
4787 cpuss4-thermal { 4469 cpuss4-thermal {
>> 4470 polling-delay-passive = <0>;
>> 4471 polling-delay = <0>;
4788 thermal-sensors = <&t 4472 thermal-sensors = <&tsens0 4>;
4789 4473
4790 trips { 4474 trips {
4791 thermal-engin 4475 thermal-engine-config {
4792 tempe 4476 temperature = <125000>;
4793 hyste 4477 hysteresis = <1000>;
4794 type 4478 type = "passive";
4795 }; 4479 };
4796 4480
4797 reset-mon-cfg 4481 reset-mon-cfg {
4798 tempe 4482 temperature = <115000>;
4799 hyste 4483 hysteresis = <5000>;
4800 type 4484 type = "passive";
4801 }; 4485 };
4802 }; 4486 };
4803 }; 4487 };
4804 4488
4805 cpu4-top-thermal { 4489 cpu4-top-thermal {
>> 4490 polling-delay-passive = <0>;
>> 4491 polling-delay = <0>;
4806 thermal-sensors = <&t 4492 thermal-sensors = <&tsens0 5>;
4807 4493
4808 trips { 4494 trips {
4809 cpu4_top_aler 4495 cpu4_top_alert0: trip-point0 {
4810 tempe 4496 temperature = <90000>;
4811 hyste 4497 hysteresis = <2000>;
4812 type 4498 type = "passive";
4813 }; 4499 };
4814 4500
4815 cpu4_top_aler 4501 cpu4_top_alert1: trip-point1 {
4816 tempe 4502 temperature = <95000>;
4817 hyste 4503 hysteresis = <2000>;
4818 type 4504 type = "passive";
4819 }; 4505 };
4820 4506
4821 cpu4_top_crit 4507 cpu4_top_crit: cpu-crit {
4822 tempe 4508 temperature = <110000>;
4823 hyste 4509 hysteresis = <1000>;
4824 type 4510 type = "critical";
4825 }; 4511 };
4826 }; 4512 };
4827 }; 4513 };
4828 4514
4829 cpu4-bottom-thermal { 4515 cpu4-bottom-thermal {
>> 4516 polling-delay-passive = <0>;
>> 4517 polling-delay = <0>;
4830 thermal-sensors = <&t 4518 thermal-sensors = <&tsens0 6>;
4831 4519
4832 trips { 4520 trips {
4833 cpu4_bottom_a 4521 cpu4_bottom_alert0: trip-point0 {
4834 tempe 4522 temperature = <90000>;
4835 hyste 4523 hysteresis = <2000>;
4836 type 4524 type = "passive";
4837 }; 4525 };
4838 4526
4839 cpu4_bottom_a 4527 cpu4_bottom_alert1: trip-point1 {
4840 tempe 4528 temperature = <95000>;
4841 hyste 4529 hysteresis = <2000>;
4842 type 4530 type = "passive";
4843 }; 4531 };
4844 4532
4845 cpu4_bottom_c 4533 cpu4_bottom_crit: cpu-crit {
4846 tempe 4534 temperature = <110000>;
4847 hyste 4535 hysteresis = <1000>;
4848 type 4536 type = "critical";
4849 }; 4537 };
4850 }; 4538 };
4851 }; 4539 };
4852 4540
4853 cpu5-top-thermal { 4541 cpu5-top-thermal {
>> 4542 polling-delay-passive = <0>;
>> 4543 polling-delay = <0>;
4854 thermal-sensors = <&t 4544 thermal-sensors = <&tsens0 7>;
4855 4545
4856 trips { 4546 trips {
4857 cpu5_top_aler 4547 cpu5_top_alert0: trip-point0 {
4858 tempe 4548 temperature = <90000>;
4859 hyste 4549 hysteresis = <2000>;
4860 type 4550 type = "passive";
4861 }; 4551 };
4862 4552
4863 cpu5_top_aler 4553 cpu5_top_alert1: trip-point1 {
4864 tempe 4554 temperature = <95000>;
4865 hyste 4555 hysteresis = <2000>;
4866 type 4556 type = "passive";
4867 }; 4557 };
4868 4558
4869 cpu5_top_crit 4559 cpu5_top_crit: cpu-crit {
4870 tempe 4560 temperature = <110000>;
4871 hyste 4561 hysteresis = <1000>;
4872 type 4562 type = "critical";
4873 }; 4563 };
4874 }; 4564 };
4875 }; 4565 };
4876 4566
4877 cpu5-bottom-thermal { 4567 cpu5-bottom-thermal {
>> 4568 polling-delay-passive = <0>;
>> 4569 polling-delay = <0>;
4878 thermal-sensors = <&t 4570 thermal-sensors = <&tsens0 8>;
4879 4571
4880 trips { 4572 trips {
4881 cpu5_bottom_a 4573 cpu5_bottom_alert0: trip-point0 {
4882 tempe 4574 temperature = <90000>;
4883 hyste 4575 hysteresis = <2000>;
4884 type 4576 type = "passive";
4885 }; 4577 };
4886 4578
4887 cpu5_bottom_a 4579 cpu5_bottom_alert1: trip-point1 {
4888 tempe 4580 temperature = <95000>;
4889 hyste 4581 hysteresis = <2000>;
4890 type 4582 type = "passive";
4891 }; 4583 };
4892 4584
4893 cpu5_bottom_c 4585 cpu5_bottom_crit: cpu-crit {
4894 tempe 4586 temperature = <110000>;
4895 hyste 4587 hysteresis = <1000>;
4896 type 4588 type = "critical";
4897 }; 4589 };
4898 }; 4590 };
4899 }; 4591 };
4900 4592
4901 cpu6-top-thermal { 4593 cpu6-top-thermal {
>> 4594 polling-delay-passive = <0>;
>> 4595 polling-delay = <0>;
4902 thermal-sensors = <&t 4596 thermal-sensors = <&tsens0 9>;
4903 4597
4904 trips { 4598 trips {
4905 cpu6_top_aler 4599 cpu6_top_alert0: trip-point0 {
4906 tempe 4600 temperature = <90000>;
4907 hyste 4601 hysteresis = <2000>;
4908 type 4602 type = "passive";
4909 }; 4603 };
4910 4604
4911 cpu6_top_aler 4605 cpu6_top_alert1: trip-point1 {
4912 tempe 4606 temperature = <95000>;
4913 hyste 4607 hysteresis = <2000>;
4914 type 4608 type = "passive";
4915 }; 4609 };
4916 4610
4917 cpu6_top_crit 4611 cpu6_top_crit: cpu-crit {
4918 tempe 4612 temperature = <110000>;
4919 hyste 4613 hysteresis = <1000>;
4920 type 4614 type = "critical";
4921 }; 4615 };
4922 }; 4616 };
4923 }; 4617 };
4924 4618
4925 cpu6-bottom-thermal { 4619 cpu6-bottom-thermal {
>> 4620 polling-delay-passive = <0>;
>> 4621 polling-delay = <0>;
4926 thermal-sensors = <&t 4622 thermal-sensors = <&tsens0 10>;
4927 4623
4928 trips { 4624 trips {
4929 cpu6_bottom_a 4625 cpu6_bottom_alert0: trip-point0 {
4930 tempe 4626 temperature = <90000>;
4931 hyste 4627 hysteresis = <2000>;
4932 type 4628 type = "passive";
4933 }; 4629 };
4934 4630
4935 cpu6_bottom_a 4631 cpu6_bottom_alert1: trip-point1 {
4936 tempe 4632 temperature = <95000>;
4937 hyste 4633 hysteresis = <2000>;
4938 type 4634 type = "passive";
4939 }; 4635 };
4940 4636
4941 cpu6_bottom_c 4637 cpu6_bottom_crit: cpu-crit {
4942 tempe 4638 temperature = <110000>;
4943 hyste 4639 hysteresis = <1000>;
4944 type 4640 type = "critical";
4945 }; 4641 };
4946 }; 4642 };
4947 }; 4643 };
4948 4644
4949 cpu7-top-thermal { 4645 cpu7-top-thermal {
>> 4646 polling-delay-passive = <0>;
>> 4647 polling-delay = <0>;
4950 thermal-sensors = <&t 4648 thermal-sensors = <&tsens0 11>;
4951 4649
4952 trips { 4650 trips {
4953 cpu7_top_aler 4651 cpu7_top_alert0: trip-point0 {
4954 tempe 4652 temperature = <90000>;
4955 hyste 4653 hysteresis = <2000>;
4956 type 4654 type = "passive";
4957 }; 4655 };
4958 4656
4959 cpu7_top_aler 4657 cpu7_top_alert1: trip-point1 {
4960 tempe 4658 temperature = <95000>;
4961 hyste 4659 hysteresis = <2000>;
4962 type 4660 type = "passive";
4963 }; 4661 };
4964 4662
4965 cpu7_top_crit 4663 cpu7_top_crit: cpu-crit {
4966 tempe 4664 temperature = <110000>;
4967 hyste 4665 hysteresis = <1000>;
4968 type 4666 type = "critical";
4969 }; 4667 };
4970 }; 4668 };
4971 }; 4669 };
4972 4670
4973 cpu7-middle-thermal { 4671 cpu7-middle-thermal {
>> 4672 polling-delay-passive = <0>;
>> 4673 polling-delay = <0>;
4974 thermal-sensors = <&t 4674 thermal-sensors = <&tsens0 12>;
4975 4675
4976 trips { 4676 trips {
4977 cpu7_middle_a 4677 cpu7_middle_alert0: trip-point0 {
4978 tempe 4678 temperature = <90000>;
4979 hyste 4679 hysteresis = <2000>;
4980 type 4680 type = "passive";
4981 }; 4681 };
4982 4682
4983 cpu7_middle_a 4683 cpu7_middle_alert1: trip-point1 {
4984 tempe 4684 temperature = <95000>;
4985 hyste 4685 hysteresis = <2000>;
4986 type 4686 type = "passive";
4987 }; 4687 };
4988 4688
4989 cpu7_middle_c 4689 cpu7_middle_crit: cpu-crit {
4990 tempe 4690 temperature = <110000>;
4991 hyste 4691 hysteresis = <1000>;
4992 type 4692 type = "critical";
4993 }; 4693 };
4994 }; 4694 };
4995 }; 4695 };
4996 4696
4997 cpu7-bottom-thermal { 4697 cpu7-bottom-thermal {
>> 4698 polling-delay-passive = <0>;
>> 4699 polling-delay = <0>;
4998 thermal-sensors = <&t 4700 thermal-sensors = <&tsens0 13>;
4999 4701
5000 trips { 4702 trips {
5001 cpu7_bottom_a 4703 cpu7_bottom_alert0: trip-point0 {
5002 tempe 4704 temperature = <90000>;
5003 hyste 4705 hysteresis = <2000>;
5004 type 4706 type = "passive";
5005 }; 4707 };
5006 4708
5007 cpu7_bottom_a 4709 cpu7_bottom_alert1: trip-point1 {
5008 tempe 4710 temperature = <95000>;
5009 hyste 4711 hysteresis = <2000>;
5010 type 4712 type = "passive";
5011 }; 4713 };
5012 4714
5013 cpu7_bottom_c 4715 cpu7_bottom_crit: cpu-crit {
5014 tempe 4716 temperature = <110000>;
5015 hyste 4717 hysteresis = <1000>;
5016 type 4718 type = "critical";
5017 }; 4719 };
5018 }; 4720 };
5019 }; 4721 };
5020 4722
5021 gpu-top-thermal { 4723 gpu-top-thermal {
5022 polling-delay-passive 4724 polling-delay-passive = <10>;
5023 !! 4725 polling-delay = <0>;
5024 thermal-sensors = <&t 4726 thermal-sensors = <&tsens0 14>;
5025 4727
5026 cooling-maps { <<
5027 map0 { <<
5028 trip <<
5029 cooli <<
5030 }; <<
5031 }; <<
5032 <<
5033 trips { 4728 trips {
5034 gpu_top_alert !! 4729 thermal-engine-config {
5035 tempe !! 4730 temperature = <125000>;
5036 hyste 4731 hysteresis = <1000>;
5037 type 4732 type = "passive";
5038 }; 4733 };
5039 4734
5040 trip-point1 { !! 4735 thermal-hal-config {
5041 tempe !! 4736 temperature = <125000>;
5042 hyste 4737 hysteresis = <1000>;
5043 type !! 4738 type = "passive";
5044 }; 4739 };
5045 4740
5046 trip-point2 { !! 4741 reset-mon-cfg {
5047 tempe !! 4742 temperature = <115000>;
5048 hyste !! 4743 hysteresis = <5000>;
5049 type !! 4744 type = "passive";
>> 4745 };
>> 4746
>> 4747 gpu0_tj_cfg: tj-cfg {
>> 4748 temperature = <95000>;
>> 4749 hysteresis = <5000>;
>> 4750 type = "passive";
5050 }; 4751 };
5051 }; 4752 };
5052 }; 4753 };
5053 4754
5054 gpu-bottom-thermal { 4755 gpu-bottom-thermal {
5055 polling-delay-passive 4756 polling-delay-passive = <10>;
5056 !! 4757 polling-delay = <0>;
5057 thermal-sensors = <&t 4758 thermal-sensors = <&tsens0 15>;
5058 4759
5059 cooling-maps { <<
5060 map0 { <<
5061 trip <<
5062 cooli <<
5063 }; <<
5064 }; <<
5065 <<
5066 trips { 4760 trips {
5067 gpu_bottom_al !! 4761 thermal-engine-config {
5068 tempe !! 4762 temperature = <125000>;
5069 hyste 4763 hysteresis = <1000>;
5070 type 4764 type = "passive";
5071 }; 4765 };
5072 4766
5073 trip-point1 { !! 4767 thermal-hal-config {
5074 tempe !! 4768 temperature = <125000>;
5075 hyste 4769 hysteresis = <1000>;
5076 type !! 4770 type = "passive";
5077 }; 4771 };
5078 4772
5079 trip-point2 { !! 4773 reset-mon-cfg {
5080 tempe !! 4774 temperature = <115000>;
5081 hyste !! 4775 hysteresis = <5000>;
5082 type !! 4776 type = "passive";
>> 4777 };
>> 4778
>> 4779 gpu1_tj_cfg: tj-cfg {
>> 4780 temperature = <95000>;
>> 4781 hysteresis = <5000>;
>> 4782 type = "passive";
5083 }; 4783 };
5084 }; 4784 };
5085 }; 4785 };
5086 4786
5087 aoss1-thermal { 4787 aoss1-thermal {
>> 4788 polling-delay-passive = <0>;
>> 4789 polling-delay = <0>;
5088 thermal-sensors = <&t 4790 thermal-sensors = <&tsens1 0>;
5089 4791
5090 trips { 4792 trips {
5091 thermal-engin 4793 thermal-engine-config {
5092 tempe 4794 temperature = <125000>;
5093 hyste 4795 hysteresis = <1000>;
5094 type 4796 type = "passive";
5095 }; 4797 };
5096 4798
5097 reset-mon-cfg 4799 reset-mon-cfg {
5098 tempe 4800 temperature = <115000>;
5099 hyste 4801 hysteresis = <5000>;
5100 type 4802 type = "passive";
5101 }; 4803 };
5102 }; 4804 };
5103 }; 4805 };
5104 4806
5105 cpu0-thermal { 4807 cpu0-thermal {
>> 4808 polling-delay-passive = <0>;
>> 4809 polling-delay = <0>;
5106 thermal-sensors = <&t 4810 thermal-sensors = <&tsens1 1>;
5107 4811
5108 trips { 4812 trips {
5109 cpu0_alert0: 4813 cpu0_alert0: trip-point0 {
5110 tempe 4814 temperature = <90000>;
5111 hyste 4815 hysteresis = <2000>;
5112 type 4816 type = "passive";
5113 }; 4817 };
5114 4818
5115 cpu0_alert1: 4819 cpu0_alert1: trip-point1 {
5116 tempe 4820 temperature = <95000>;
5117 hyste 4821 hysteresis = <2000>;
5118 type 4822 type = "passive";
5119 }; 4823 };
5120 4824
5121 cpu0_crit: cp 4825 cpu0_crit: cpu-crit {
5122 tempe 4826 temperature = <110000>;
5123 hyste 4827 hysteresis = <1000>;
5124 type 4828 type = "critical";
5125 }; 4829 };
5126 }; 4830 };
5127 }; 4831 };
5128 4832
5129 cpu1-thermal { 4833 cpu1-thermal {
>> 4834 polling-delay-passive = <0>;
>> 4835 polling-delay = <0>;
5130 thermal-sensors = <&t 4836 thermal-sensors = <&tsens1 2>;
5131 4837
5132 trips { 4838 trips {
5133 cpu1_alert0: 4839 cpu1_alert0: trip-point0 {
5134 tempe 4840 temperature = <90000>;
5135 hyste 4841 hysteresis = <2000>;
5136 type 4842 type = "passive";
5137 }; 4843 };
5138 4844
5139 cpu1_alert1: 4845 cpu1_alert1: trip-point1 {
5140 tempe 4846 temperature = <95000>;
5141 hyste 4847 hysteresis = <2000>;
5142 type 4848 type = "passive";
5143 }; 4849 };
5144 4850
5145 cpu1_crit: cp 4851 cpu1_crit: cpu-crit {
5146 tempe 4852 temperature = <110000>;
5147 hyste 4853 hysteresis = <1000>;
5148 type 4854 type = "critical";
5149 }; 4855 };
5150 }; 4856 };
5151 }; 4857 };
5152 4858
5153 cpu2-thermal { 4859 cpu2-thermal {
>> 4860 polling-delay-passive = <0>;
>> 4861 polling-delay = <0>;
5154 thermal-sensors = <&t 4862 thermal-sensors = <&tsens1 3>;
5155 4863
5156 trips { 4864 trips {
5157 cpu2_alert0: 4865 cpu2_alert0: trip-point0 {
5158 tempe 4866 temperature = <90000>;
5159 hyste 4867 hysteresis = <2000>;
5160 type 4868 type = "passive";
5161 }; 4869 };
5162 4870
5163 cpu2_alert1: 4871 cpu2_alert1: trip-point1 {
5164 tempe 4872 temperature = <95000>;
5165 hyste 4873 hysteresis = <2000>;
5166 type 4874 type = "passive";
5167 }; 4875 };
5168 4876
5169 cpu2_crit: cp 4877 cpu2_crit: cpu-crit {
5170 tempe 4878 temperature = <110000>;
5171 hyste 4879 hysteresis = <1000>;
5172 type 4880 type = "critical";
5173 }; 4881 };
5174 }; 4882 };
5175 }; 4883 };
5176 4884
5177 cpu3-thermal { 4885 cpu3-thermal {
>> 4886 polling-delay-passive = <0>;
>> 4887 polling-delay = <0>;
5178 thermal-sensors = <&t 4888 thermal-sensors = <&tsens1 4>;
5179 4889
5180 trips { 4890 trips {
5181 cpu3_alert0: 4891 cpu3_alert0: trip-point0 {
5182 tempe 4892 temperature = <90000>;
5183 hyste 4893 hysteresis = <2000>;
5184 type 4894 type = "passive";
5185 }; 4895 };
5186 4896
5187 cpu3_alert1: 4897 cpu3_alert1: trip-point1 {
5188 tempe 4898 temperature = <95000>;
5189 hyste 4899 hysteresis = <2000>;
5190 type 4900 type = "passive";
5191 }; 4901 };
5192 4902
5193 cpu3_crit: cp 4903 cpu3_crit: cpu-crit {
5194 tempe 4904 temperature = <110000>;
5195 hyste 4905 hysteresis = <1000>;
5196 type 4906 type = "critical";
5197 }; 4907 };
5198 }; 4908 };
5199 }; 4909 };
5200 4910
5201 cdsp0-thermal { 4911 cdsp0-thermal {
5202 polling-delay-passive 4912 polling-delay-passive = <10>;
5203 !! 4913 polling-delay = <0>;
5204 thermal-sensors = <&t 4914 thermal-sensors = <&tsens1 5>;
5205 4915
5206 trips { 4916 trips {
5207 thermal-engin 4917 thermal-engine-config {
5208 tempe 4918 temperature = <125000>;
5209 hyste 4919 hysteresis = <1000>;
5210 type 4920 type = "passive";
5211 }; 4921 };
5212 4922
5213 thermal-hal-c 4923 thermal-hal-config {
5214 tempe 4924 temperature = <125000>;
5215 hyste 4925 hysteresis = <1000>;
5216 type 4926 type = "passive";
5217 }; 4927 };
5218 4928
5219 reset-mon-cfg 4929 reset-mon-cfg {
5220 tempe 4930 temperature = <115000>;
5221 hyste 4931 hysteresis = <5000>;
5222 type 4932 type = "passive";
5223 }; 4933 };
5224 4934
5225 cdsp_0_config 4935 cdsp_0_config: junction-config {
5226 tempe 4936 temperature = <95000>;
5227 hyste 4937 hysteresis = <5000>;
5228 type 4938 type = "passive";
5229 }; 4939 };
5230 }; 4940 };
5231 }; 4941 };
5232 4942
5233 cdsp1-thermal { 4943 cdsp1-thermal {
5234 polling-delay-passive 4944 polling-delay-passive = <10>;
5235 !! 4945 polling-delay = <0>;
5236 thermal-sensors = <&t 4946 thermal-sensors = <&tsens1 6>;
5237 4947
5238 trips { 4948 trips {
5239 thermal-engin 4949 thermal-engine-config {
5240 tempe 4950 temperature = <125000>;
5241 hyste 4951 hysteresis = <1000>;
5242 type 4952 type = "passive";
5243 }; 4953 };
5244 4954
5245 thermal-hal-c 4955 thermal-hal-config {
5246 tempe 4956 temperature = <125000>;
5247 hyste 4957 hysteresis = <1000>;
5248 type 4958 type = "passive";
5249 }; 4959 };
5250 4960
5251 reset-mon-cfg 4961 reset-mon-cfg {
5252 tempe 4962 temperature = <115000>;
5253 hyste 4963 hysteresis = <5000>;
5254 type 4964 type = "passive";
5255 }; 4965 };
5256 4966
5257 cdsp_1_config 4967 cdsp_1_config: junction-config {
5258 tempe 4968 temperature = <95000>;
5259 hyste 4969 hysteresis = <5000>;
5260 type 4970 type = "passive";
5261 }; 4971 };
5262 }; 4972 };
5263 }; 4973 };
5264 4974
5265 cdsp2-thermal { 4975 cdsp2-thermal {
5266 polling-delay-passive 4976 polling-delay-passive = <10>;
5267 !! 4977 polling-delay = <0>;
5268 thermal-sensors = <&t 4978 thermal-sensors = <&tsens1 7>;
5269 4979
5270 trips { 4980 trips {
5271 thermal-engin 4981 thermal-engine-config {
5272 tempe 4982 temperature = <125000>;
5273 hyste 4983 hysteresis = <1000>;
5274 type 4984 type = "passive";
5275 }; 4985 };
5276 4986
5277 thermal-hal-c 4987 thermal-hal-config {
5278 tempe 4988 temperature = <125000>;
5279 hyste 4989 hysteresis = <1000>;
5280 type 4990 type = "passive";
5281 }; 4991 };
5282 4992
5283 reset-mon-cfg 4993 reset-mon-cfg {
5284 tempe 4994 temperature = <115000>;
5285 hyste 4995 hysteresis = <5000>;
5286 type 4996 type = "passive";
5287 }; 4997 };
5288 4998
5289 cdsp_2_config 4999 cdsp_2_config: junction-config {
5290 tempe 5000 temperature = <95000>;
5291 hyste 5001 hysteresis = <5000>;
5292 type 5002 type = "passive";
5293 }; 5003 };
5294 }; 5004 };
5295 }; 5005 };
5296 5006
5297 video-thermal { 5007 video-thermal {
>> 5008 polling-delay-passive = <0>;
>> 5009 polling-delay = <0>;
5298 thermal-sensors = <&t 5010 thermal-sensors = <&tsens1 8>;
5299 5011
5300 trips { 5012 trips {
5301 thermal-engin 5013 thermal-engine-config {
5302 tempe 5014 temperature = <125000>;
5303 hyste 5015 hysteresis = <1000>;
5304 type 5016 type = "passive";
5305 }; 5017 };
5306 5018
5307 reset-mon-cfg 5019 reset-mon-cfg {
5308 tempe 5020 temperature = <115000>;
5309 hyste 5021 hysteresis = <5000>;
5310 type 5022 type = "passive";
5311 }; 5023 };
5312 }; 5024 };
5313 }; 5025 };
5314 5026
5315 mem-thermal { 5027 mem-thermal {
5316 polling-delay-passive 5028 polling-delay-passive = <10>;
5317 !! 5029 polling-delay = <0>;
5318 thermal-sensors = <&t 5030 thermal-sensors = <&tsens1 9>;
5319 5031
5320 trips { 5032 trips {
5321 thermal-engin 5033 thermal-engine-config {
5322 tempe 5034 temperature = <125000>;
5323 hyste 5035 hysteresis = <1000>;
5324 type 5036 type = "passive";
5325 }; 5037 };
5326 5038
5327 ddr_config0: 5039 ddr_config0: ddr0-config {
5328 tempe 5040 temperature = <90000>;
5329 hyste 5041 hysteresis = <5000>;
5330 type 5042 type = "passive";
5331 }; 5043 };
5332 5044
5333 reset-mon-cfg 5045 reset-mon-cfg {
5334 tempe 5046 temperature = <115000>;
5335 hyste 5047 hysteresis = <5000>;
5336 type 5048 type = "passive";
5337 }; 5049 };
5338 }; 5050 };
5339 }; 5051 };
5340 5052
5341 modem0-thermal { 5053 modem0-thermal {
>> 5054 polling-delay-passive = <0>;
>> 5055 polling-delay = <0>;
5342 thermal-sensors = <&t 5056 thermal-sensors = <&tsens1 10>;
5343 5057
5344 trips { 5058 trips {
5345 thermal-engin 5059 thermal-engine-config {
5346 tempe 5060 temperature = <125000>;
5347 hyste 5061 hysteresis = <1000>;
5348 type 5062 type = "passive";
5349 }; 5063 };
5350 5064
5351 mdmss0_config 5065 mdmss0_config0: mdmss0-config0 {
5352 tempe 5066 temperature = <102000>;
5353 hyste 5067 hysteresis = <3000>;
5354 type 5068 type = "passive";
5355 }; 5069 };
5356 5070
5357 mdmss0_config 5071 mdmss0_config1: mdmss0-config1 {
5358 tempe 5072 temperature = <105000>;
5359 hyste 5073 hysteresis = <3000>;
5360 type 5074 type = "passive";
5361 }; 5075 };
5362 5076
5363 reset-mon-cfg 5077 reset-mon-cfg {
5364 tempe 5078 temperature = <115000>;
5365 hyste 5079 hysteresis = <5000>;
5366 type 5080 type = "passive";
5367 }; 5081 };
5368 }; 5082 };
5369 }; 5083 };
5370 5084
5371 modem1-thermal { 5085 modem1-thermal {
>> 5086 polling-delay-passive = <0>;
>> 5087 polling-delay = <0>;
5372 thermal-sensors = <&t 5088 thermal-sensors = <&tsens1 11>;
5373 5089
5374 trips { 5090 trips {
5375 thermal-engin 5091 thermal-engine-config {
5376 tempe 5092 temperature = <125000>;
5377 hyste 5093 hysteresis = <1000>;
5378 type 5094 type = "passive";
5379 }; 5095 };
5380 5096
5381 mdmss1_config 5097 mdmss1_config0: mdmss1-config0 {
5382 tempe 5098 temperature = <102000>;
5383 hyste 5099 hysteresis = <3000>;
5384 type 5100 type = "passive";
5385 }; 5101 };
5386 5102
5387 mdmss1_config 5103 mdmss1_config1: mdmss1-config1 {
5388 tempe 5104 temperature = <105000>;
5389 hyste 5105 hysteresis = <3000>;
5390 type 5106 type = "passive";
5391 }; 5107 };
5392 5108
5393 reset-mon-cfg 5109 reset-mon-cfg {
5394 tempe 5110 temperature = <115000>;
5395 hyste 5111 hysteresis = <5000>;
5396 type 5112 type = "passive";
5397 }; 5113 };
5398 }; 5114 };
5399 }; 5115 };
5400 5116
5401 modem2-thermal { 5117 modem2-thermal {
>> 5118 polling-delay-passive = <0>;
>> 5119 polling-delay = <0>;
5402 thermal-sensors = <&t 5120 thermal-sensors = <&tsens1 12>;
5403 5121
5404 trips { 5122 trips {
5405 thermal-engin 5123 thermal-engine-config {
5406 tempe 5124 temperature = <125000>;
5407 hyste 5125 hysteresis = <1000>;
5408 type 5126 type = "passive";
5409 }; 5127 };
5410 5128
5411 mdmss2_config 5129 mdmss2_config0: mdmss2-config0 {
5412 tempe 5130 temperature = <102000>;
5413 hyste 5131 hysteresis = <3000>;
5414 type 5132 type = "passive";
5415 }; 5133 };
5416 5134
5417 mdmss2_config 5135 mdmss2_config1: mdmss2-config1 {
5418 tempe 5136 temperature = <105000>;
5419 hyste 5137 hysteresis = <3000>;
5420 type 5138 type = "passive";
5421 }; 5139 };
5422 5140
5423 reset-mon-cfg 5141 reset-mon-cfg {
5424 tempe 5142 temperature = <115000>;
5425 hyste 5143 hysteresis = <5000>;
5426 type 5144 type = "passive";
5427 }; 5145 };
5428 }; 5146 };
5429 }; 5147 };
5430 5148
5431 modem3-thermal { 5149 modem3-thermal {
>> 5150 polling-delay-passive = <0>;
>> 5151 polling-delay = <0>;
5432 thermal-sensors = <&t 5152 thermal-sensors = <&tsens1 13>;
5433 5153
5434 trips { 5154 trips {
5435 thermal-engin 5155 thermal-engine-config {
5436 tempe 5156 temperature = <125000>;
5437 hyste 5157 hysteresis = <1000>;
5438 type 5158 type = "passive";
5439 }; 5159 };
5440 5160
5441 mdmss3_config 5161 mdmss3_config0: mdmss3-config0 {
5442 tempe 5162 temperature = <102000>;
5443 hyste 5163 hysteresis = <3000>;
5444 type 5164 type = "passive";
5445 }; 5165 };
5446 5166
5447 mdmss3_config 5167 mdmss3_config1: mdmss3-config1 {
5448 tempe 5168 temperature = <105000>;
5449 hyste 5169 hysteresis = <3000>;
5450 type 5170 type = "passive";
5451 }; 5171 };
5452 5172
5453 reset-mon-cfg 5173 reset-mon-cfg {
5454 tempe 5174 temperature = <115000>;
5455 hyste 5175 hysteresis = <5000>;
5456 type 5176 type = "passive";
5457 }; 5177 };
5458 }; 5178 };
5459 }; 5179 };
5460 5180
5461 camera0-thermal { 5181 camera0-thermal {
>> 5182 polling-delay-passive = <0>;
>> 5183 polling-delay = <0>;
5462 thermal-sensors = <&t 5184 thermal-sensors = <&tsens1 14>;
5463 5185
5464 trips { 5186 trips {
5465 thermal-engin 5187 thermal-engine-config {
5466 tempe 5188 temperature = <125000>;
5467 hyste 5189 hysteresis = <1000>;
5468 type 5190 type = "passive";
5469 }; 5191 };
5470 5192
5471 reset-mon-cfg 5193 reset-mon-cfg {
5472 tempe 5194 temperature = <115000>;
5473 hyste 5195 hysteresis = <5000>;
5474 type 5196 type = "passive";
5475 }; 5197 };
5476 }; 5198 };
5477 }; 5199 };
5478 5200
5479 camera1-thermal { 5201 camera1-thermal {
>> 5202 polling-delay-passive = <0>;
>> 5203 polling-delay = <0>;
5480 thermal-sensors = <&t 5204 thermal-sensors = <&tsens1 15>;
5481 5205
5482 trips { 5206 trips {
5483 thermal-engin 5207 thermal-engine-config {
5484 tempe 5208 temperature = <125000>;
5485 hyste 5209 hysteresis = <1000>;
5486 type 5210 type = "passive";
5487 }; 5211 };
5488 5212
5489 reset-mon-cfg 5213 reset-mon-cfg {
5490 tempe 5214 temperature = <115000>;
5491 hyste 5215 hysteresis = <5000>;
5492 type 5216 type = "passive";
5493 }; 5217 };
5494 }; 5218 };
5495 }; 5219 };
5496 }; 5220 };
5497 5221
5498 timer { 5222 timer {
5499 compatible = "arm,armv8-timer 5223 compatible = "arm,armv8-timer";
5500 interrupts = <GIC_PPI 13 (GIC 5224 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5501 <GIC_PPI 14 (GIC 5225 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5502 <GIC_PPI 11 (GIC 5226 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5503 <GIC_PPI 10 (GIC 5227 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
5504 clock-frequency = <19200000>; 5228 clock-frequency = <19200000>;
5505 }; 5229 };
5506 }; 5230 };
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