1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * Copyright (c) 2021, Linaro Limited 3 * Copyright (c) 2021, Linaro Limited
4 */ 4 */
5 5
6 #include <dt-bindings/interrupt-controller/arm 6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-sm8450.h> 7 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
8 #include <dt-bindings/clock/qcom,rpmh.h> 8 #include <dt-bindings/clock/qcom,rpmh.h>
9 #include <dt-bindings/clock/qcom,sm8450-camcc. 9 #include <dt-bindings/clock/qcom,sm8450-camcc.h>
10 #include <dt-bindings/clock/qcom,sm8450-dispcc 10 #include <dt-bindings/clock/qcom,sm8450-dispcc.h>
11 #include <dt-bindings/clock/qcom,sm8450-gpucc. <<
12 #include <dt-bindings/clock/qcom,sm8450-videoc 11 #include <dt-bindings/clock/qcom,sm8450-videocc.h>
13 #include <dt-bindings/dma/qcom-gpi.h> 12 #include <dt-bindings/dma/qcom-gpi.h>
14 #include <dt-bindings/firmware/qcom,scm.h> 13 #include <dt-bindings/firmware/qcom,scm.h>
15 #include <dt-bindings/gpio/gpio.h> 14 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/mailbox/qcom-ipcc.h> 15 #include <dt-bindings/mailbox/qcom-ipcc.h>
17 #include <dt-bindings/phy/phy-qcom-qmp.h> 16 #include <dt-bindings/phy/phy-qcom-qmp.h>
18 #include <dt-bindings/power/qcom,rpmhpd.h> 17 #include <dt-bindings/power/qcom,rpmhpd.h>
19 #include <dt-bindings/power/qcom-rpmpd.h> 18 #include <dt-bindings/power/qcom-rpmpd.h>
20 #include <dt-bindings/interconnect/qcom,icc.h> 19 #include <dt-bindings/interconnect/qcom,icc.h>
21 #include <dt-bindings/interconnect/qcom,sm8450 20 #include <dt-bindings/interconnect/qcom,sm8450.h>
22 #include <dt-bindings/reset/qcom,sm8450-gpucc. <<
23 #include <dt-bindings/soc/qcom,gpr.h> 21 #include <dt-bindings/soc/qcom,gpr.h>
24 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 22 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
25 #include <dt-bindings/sound/qcom,q6dsp-lpass-p 23 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
26 #include <dt-bindings/thermal/thermal.h> 24 #include <dt-bindings/thermal/thermal.h>
27 25
28 / { 26 / {
29 interrupt-parent = <&intc>; 27 interrupt-parent = <&intc>;
30 28
31 #address-cells = <2>; 29 #address-cells = <2>;
32 #size-cells = <2>; 30 #size-cells = <2>;
33 31
34 chosen { }; 32 chosen { };
35 33
36 clocks { 34 clocks {
37 xo_board: xo-board { 35 xo_board: xo-board {
38 compatible = "fixed-cl 36 compatible = "fixed-clock";
39 #clock-cells = <0>; 37 #clock-cells = <0>;
40 clock-frequency = <768 38 clock-frequency = <76800000>;
41 }; 39 };
42 40
43 sleep_clk: sleep-clk { 41 sleep_clk: sleep-clk {
44 compatible = "fixed-cl 42 compatible = "fixed-clock";
45 #clock-cells = <0>; 43 #clock-cells = <0>;
46 clock-frequency = <320 44 clock-frequency = <32000>;
47 }; 45 };
48 }; 46 };
49 47
50 cpus { 48 cpus {
51 #address-cells = <2>; 49 #address-cells = <2>;
52 #size-cells = <0>; 50 #size-cells = <0>;
53 51
54 CPU0: cpu@0 { 52 CPU0: cpu@0 {
55 device_type = "cpu"; 53 device_type = "cpu";
56 compatible = "qcom,kry 54 compatible = "qcom,kryo780";
57 reg = <0x0 0x0>; 55 reg = <0x0 0x0>;
58 enable-method = "psci" 56 enable-method = "psci";
59 next-level-cache = <&L 57 next-level-cache = <&L2_0>;
60 power-domains = <&CPU_ 58 power-domains = <&CPU_PD0>;
61 power-domain-names = " 59 power-domain-names = "psci";
62 qcom,freq-domain = <&c 60 qcom,freq-domain = <&cpufreq_hw 0>;
63 #cooling-cells = <2>; 61 #cooling-cells = <2>;
64 clocks = <&cpufreq_hw 62 clocks = <&cpufreq_hw 0>;
65 L2_0: l2-cache { 63 L2_0: l2-cache {
66 compatible = " 64 compatible = "cache";
67 cache-level = 65 cache-level = <2>;
68 cache-unified; 66 cache-unified;
69 next-level-cac 67 next-level-cache = <&L3_0>;
70 L3_0: l3-cache 68 L3_0: l3-cache {
71 compat 69 compatible = "cache";
72 cache- 70 cache-level = <3>;
73 cache- 71 cache-unified;
74 }; 72 };
75 }; 73 };
76 }; 74 };
77 75
78 CPU1: cpu@100 { 76 CPU1: cpu@100 {
79 device_type = "cpu"; 77 device_type = "cpu";
80 compatible = "qcom,kry 78 compatible = "qcom,kryo780";
81 reg = <0x0 0x100>; 79 reg = <0x0 0x100>;
82 enable-method = "psci" 80 enable-method = "psci";
83 next-level-cache = <&L 81 next-level-cache = <&L2_100>;
84 power-domains = <&CPU_ 82 power-domains = <&CPU_PD1>;
85 power-domain-names = " 83 power-domain-names = "psci";
86 qcom,freq-domain = <&c 84 qcom,freq-domain = <&cpufreq_hw 0>;
87 #cooling-cells = <2>; 85 #cooling-cells = <2>;
88 clocks = <&cpufreq_hw 86 clocks = <&cpufreq_hw 0>;
89 L2_100: l2-cache { 87 L2_100: l2-cache {
90 compatible = " 88 compatible = "cache";
91 cache-level = 89 cache-level = <2>;
92 cache-unified; 90 cache-unified;
93 next-level-cac 91 next-level-cache = <&L3_0>;
94 }; 92 };
95 }; 93 };
96 94
97 CPU2: cpu@200 { 95 CPU2: cpu@200 {
98 device_type = "cpu"; 96 device_type = "cpu";
99 compatible = "qcom,kry 97 compatible = "qcom,kryo780";
100 reg = <0x0 0x200>; 98 reg = <0x0 0x200>;
101 enable-method = "psci" 99 enable-method = "psci";
102 next-level-cache = <&L 100 next-level-cache = <&L2_200>;
103 power-domains = <&CPU_ 101 power-domains = <&CPU_PD2>;
104 power-domain-names = " 102 power-domain-names = "psci";
105 qcom,freq-domain = <&c 103 qcom,freq-domain = <&cpufreq_hw 0>;
106 #cooling-cells = <2>; 104 #cooling-cells = <2>;
107 clocks = <&cpufreq_hw 105 clocks = <&cpufreq_hw 0>;
108 L2_200: l2-cache { 106 L2_200: l2-cache {
109 compatible = " 107 compatible = "cache";
110 cache-level = 108 cache-level = <2>;
111 cache-unified; 109 cache-unified;
112 next-level-cac 110 next-level-cache = <&L3_0>;
113 }; 111 };
114 }; 112 };
115 113
116 CPU3: cpu@300 { 114 CPU3: cpu@300 {
117 device_type = "cpu"; 115 device_type = "cpu";
118 compatible = "qcom,kry 116 compatible = "qcom,kryo780";
119 reg = <0x0 0x300>; 117 reg = <0x0 0x300>;
120 enable-method = "psci" 118 enable-method = "psci";
121 next-level-cache = <&L 119 next-level-cache = <&L2_300>;
122 power-domains = <&CPU_ 120 power-domains = <&CPU_PD3>;
123 power-domain-names = " 121 power-domain-names = "psci";
124 qcom,freq-domain = <&c 122 qcom,freq-domain = <&cpufreq_hw 0>;
125 #cooling-cells = <2>; 123 #cooling-cells = <2>;
126 clocks = <&cpufreq_hw 124 clocks = <&cpufreq_hw 0>;
127 L2_300: l2-cache { 125 L2_300: l2-cache {
128 compatible = " 126 compatible = "cache";
129 cache-level = 127 cache-level = <2>;
130 cache-unified; 128 cache-unified;
131 next-level-cac 129 next-level-cache = <&L3_0>;
132 }; 130 };
133 }; 131 };
134 132
135 CPU4: cpu@400 { 133 CPU4: cpu@400 {
136 device_type = "cpu"; 134 device_type = "cpu";
137 compatible = "qcom,kry 135 compatible = "qcom,kryo780";
138 reg = <0x0 0x400>; 136 reg = <0x0 0x400>;
139 enable-method = "psci" 137 enable-method = "psci";
140 next-level-cache = <&L 138 next-level-cache = <&L2_400>;
141 power-domains = <&CPU_ 139 power-domains = <&CPU_PD4>;
142 power-domain-names = " 140 power-domain-names = "psci";
143 qcom,freq-domain = <&c 141 qcom,freq-domain = <&cpufreq_hw 1>;
144 #cooling-cells = <2>; 142 #cooling-cells = <2>;
145 clocks = <&cpufreq_hw 143 clocks = <&cpufreq_hw 1>;
146 L2_400: l2-cache { 144 L2_400: l2-cache {
147 compatible = " 145 compatible = "cache";
148 cache-level = 146 cache-level = <2>;
149 cache-unified; 147 cache-unified;
150 next-level-cac 148 next-level-cache = <&L3_0>;
151 }; 149 };
152 }; 150 };
153 151
154 CPU5: cpu@500 { 152 CPU5: cpu@500 {
155 device_type = "cpu"; 153 device_type = "cpu";
156 compatible = "qcom,kry 154 compatible = "qcom,kryo780";
157 reg = <0x0 0x500>; 155 reg = <0x0 0x500>;
158 enable-method = "psci" 156 enable-method = "psci";
159 next-level-cache = <&L 157 next-level-cache = <&L2_500>;
160 power-domains = <&CPU_ 158 power-domains = <&CPU_PD5>;
161 power-domain-names = " 159 power-domain-names = "psci";
162 qcom,freq-domain = <&c 160 qcom,freq-domain = <&cpufreq_hw 1>;
163 #cooling-cells = <2>; 161 #cooling-cells = <2>;
164 clocks = <&cpufreq_hw 162 clocks = <&cpufreq_hw 1>;
165 L2_500: l2-cache { 163 L2_500: l2-cache {
166 compatible = " 164 compatible = "cache";
167 cache-level = 165 cache-level = <2>;
168 cache-unified; 166 cache-unified;
169 next-level-cac 167 next-level-cache = <&L3_0>;
170 }; 168 };
171 }; 169 };
172 170
173 CPU6: cpu@600 { 171 CPU6: cpu@600 {
174 device_type = "cpu"; 172 device_type = "cpu";
175 compatible = "qcom,kry 173 compatible = "qcom,kryo780";
176 reg = <0x0 0x600>; 174 reg = <0x0 0x600>;
177 enable-method = "psci" 175 enable-method = "psci";
178 next-level-cache = <&L 176 next-level-cache = <&L2_600>;
179 power-domains = <&CPU_ 177 power-domains = <&CPU_PD6>;
180 power-domain-names = " 178 power-domain-names = "psci";
181 qcom,freq-domain = <&c 179 qcom,freq-domain = <&cpufreq_hw 1>;
182 #cooling-cells = <2>; 180 #cooling-cells = <2>;
183 clocks = <&cpufreq_hw 181 clocks = <&cpufreq_hw 1>;
184 L2_600: l2-cache { 182 L2_600: l2-cache {
185 compatible = " 183 compatible = "cache";
186 cache-level = 184 cache-level = <2>;
187 cache-unified; 185 cache-unified;
188 next-level-cac 186 next-level-cache = <&L3_0>;
189 }; 187 };
190 }; 188 };
191 189
192 CPU7: cpu@700 { 190 CPU7: cpu@700 {
193 device_type = "cpu"; 191 device_type = "cpu";
194 compatible = "qcom,kry 192 compatible = "qcom,kryo780";
195 reg = <0x0 0x700>; 193 reg = <0x0 0x700>;
196 enable-method = "psci" 194 enable-method = "psci";
197 next-level-cache = <&L 195 next-level-cache = <&L2_700>;
198 power-domains = <&CPU_ 196 power-domains = <&CPU_PD7>;
199 power-domain-names = " 197 power-domain-names = "psci";
200 qcom,freq-domain = <&c 198 qcom,freq-domain = <&cpufreq_hw 2>;
201 #cooling-cells = <2>; 199 #cooling-cells = <2>;
202 clocks = <&cpufreq_hw 200 clocks = <&cpufreq_hw 2>;
203 L2_700: l2-cache { 201 L2_700: l2-cache {
204 compatible = " 202 compatible = "cache";
205 cache-level = 203 cache-level = <2>;
206 cache-unified; 204 cache-unified;
207 next-level-cac 205 next-level-cache = <&L3_0>;
208 }; 206 };
209 }; 207 };
210 208
211 cpu-map { 209 cpu-map {
212 cluster0 { 210 cluster0 {
213 core0 { 211 core0 {
214 cpu = 212 cpu = <&CPU0>;
215 }; 213 };
216 214
217 core1 { 215 core1 {
218 cpu = 216 cpu = <&CPU1>;
219 }; 217 };
220 218
221 core2 { 219 core2 {
222 cpu = 220 cpu = <&CPU2>;
223 }; 221 };
224 222
225 core3 { 223 core3 {
226 cpu = 224 cpu = <&CPU3>;
227 }; 225 };
228 226
229 core4 { 227 core4 {
230 cpu = 228 cpu = <&CPU4>;
231 }; 229 };
232 230
233 core5 { 231 core5 {
234 cpu = 232 cpu = <&CPU5>;
235 }; 233 };
236 234
237 core6 { 235 core6 {
238 cpu = 236 cpu = <&CPU6>;
239 }; 237 };
240 238
241 core7 { 239 core7 {
242 cpu = 240 cpu = <&CPU7>;
243 }; 241 };
244 }; 242 };
245 }; 243 };
246 244
247 idle-states { 245 idle-states {
248 entry-method = "psci"; 246 entry-method = "psci";
249 247
250 LITTLE_CPU_SLEEP_0: cp 248 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
251 compatible = " 249 compatible = "arm,idle-state";
252 idle-state-nam 250 idle-state-name = "silver-rail-power-collapse";
253 arm,psci-suspe 251 arm,psci-suspend-param = <0x40000004>;
254 entry-latency- 252 entry-latency-us = <800>;
255 exit-latency-u 253 exit-latency-us = <750>;
256 min-residency- 254 min-residency-us = <4090>;
257 local-timer-st 255 local-timer-stop;
258 }; 256 };
259 257
260 BIG_CPU_SLEEP_0: cpu-s 258 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
261 compatible = " 259 compatible = "arm,idle-state";
262 idle-state-nam 260 idle-state-name = "gold-rail-power-collapse";
263 arm,psci-suspe 261 arm,psci-suspend-param = <0x40000004>;
264 entry-latency- 262 entry-latency-us = <600>;
265 exit-latency-u 263 exit-latency-us = <1550>;
266 min-residency- 264 min-residency-us = <4791>;
267 local-timer-st 265 local-timer-stop;
268 }; 266 };
269 }; 267 };
270 268
271 domain-idle-states { 269 domain-idle-states {
272 CLUSTER_SLEEP_0: clust 270 CLUSTER_SLEEP_0: cluster-sleep-0 {
273 compatible = " 271 compatible = "domain-idle-state";
274 arm,psci-suspe 272 arm,psci-suspend-param = <0x41000044>;
275 entry-latency- 273 entry-latency-us = <1050>;
276 exit-latency-u 274 exit-latency-us = <2500>;
277 min-residency- 275 min-residency-us = <5309>;
278 }; 276 };
279 277
280 CLUSTER_SLEEP_1: clust 278 CLUSTER_SLEEP_1: cluster-sleep-1 {
281 compatible = " 279 compatible = "domain-idle-state";
282 arm,psci-suspe 280 arm,psci-suspend-param = <0x4100c344>;
283 entry-latency- 281 entry-latency-us = <2700>;
284 exit-latency-u 282 exit-latency-us = <3500>;
285 min-residency- 283 min-residency-us = <13959>;
286 }; 284 };
287 }; 285 };
288 }; 286 };
289 287
290 firmware { 288 firmware {
291 scm: scm { 289 scm: scm {
292 compatible = "qcom,scm 290 compatible = "qcom,scm-sm8450", "qcom,scm";
293 qcom,dload-mode = <&tc 291 qcom,dload-mode = <&tcsr 0x13000>;
294 interconnects = <&aggr 292 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
295 #reset-cells = <1>; 293 #reset-cells = <1>;
296 }; 294 };
297 }; 295 };
298 296
299 clk_virt: interconnect-0 { 297 clk_virt: interconnect-0 {
300 compatible = "qcom,sm8450-clk- 298 compatible = "qcom,sm8450-clk-virt";
301 #interconnect-cells = <2>; 299 #interconnect-cells = <2>;
302 qcom,bcm-voters = <&apps_bcm_v 300 qcom,bcm-voters = <&apps_bcm_voter>;
303 }; 301 };
304 302
305 mc_virt: interconnect-1 { 303 mc_virt: interconnect-1 {
306 compatible = "qcom,sm8450-mc-v 304 compatible = "qcom,sm8450-mc-virt";
307 #interconnect-cells = <2>; 305 #interconnect-cells = <2>;
308 qcom,bcm-voters = <&apps_bcm_v 306 qcom,bcm-voters = <&apps_bcm_voter>;
309 }; 307 };
310 308
311 memory@a0000000 { 309 memory@a0000000 {
312 device_type = "memory"; 310 device_type = "memory";
313 /* We expect the bootloader to 311 /* We expect the bootloader to fill in the size */
314 reg = <0x0 0xa0000000 0x0 0x0> 312 reg = <0x0 0xa0000000 0x0 0x0>;
315 }; 313 };
316 314
317 pmu { 315 pmu {
318 compatible = "arm,armv8-pmuv3" 316 compatible = "arm,armv8-pmuv3";
319 interrupts = <GIC_PPI 7 IRQ_TY 317 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
320 }; 318 };
321 319
322 psci { 320 psci {
323 compatible = "arm,psci-1.0"; 321 compatible = "arm,psci-1.0";
324 method = "smc"; 322 method = "smc";
325 323
326 CPU_PD0: power-domain-cpu0 { 324 CPU_PD0: power-domain-cpu0 {
327 #power-domain-cells = 325 #power-domain-cells = <0>;
328 power-domains = <&CLUS 326 power-domains = <&CLUSTER_PD>;
329 domain-idle-states = < 327 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
330 }; 328 };
331 329
332 CPU_PD1: power-domain-cpu1 { 330 CPU_PD1: power-domain-cpu1 {
333 #power-domain-cells = 331 #power-domain-cells = <0>;
334 power-domains = <&CLUS 332 power-domains = <&CLUSTER_PD>;
335 domain-idle-states = < 333 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
336 }; 334 };
337 335
338 CPU_PD2: power-domain-cpu2 { 336 CPU_PD2: power-domain-cpu2 {
339 #power-domain-cells = 337 #power-domain-cells = <0>;
340 power-domains = <&CLUS 338 power-domains = <&CLUSTER_PD>;
341 domain-idle-states = < 339 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
342 }; 340 };
343 341
344 CPU_PD3: power-domain-cpu3 { 342 CPU_PD3: power-domain-cpu3 {
345 #power-domain-cells = 343 #power-domain-cells = <0>;
346 power-domains = <&CLUS 344 power-domains = <&CLUSTER_PD>;
347 domain-idle-states = < 345 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
348 }; 346 };
349 347
350 CPU_PD4: power-domain-cpu4 { 348 CPU_PD4: power-domain-cpu4 {
351 #power-domain-cells = 349 #power-domain-cells = <0>;
352 power-domains = <&CLUS 350 power-domains = <&CLUSTER_PD>;
353 domain-idle-states = < 351 domain-idle-states = <&BIG_CPU_SLEEP_0>;
354 }; 352 };
355 353
356 CPU_PD5: power-domain-cpu5 { 354 CPU_PD5: power-domain-cpu5 {
357 #power-domain-cells = 355 #power-domain-cells = <0>;
358 power-domains = <&CLUS 356 power-domains = <&CLUSTER_PD>;
359 domain-idle-states = < 357 domain-idle-states = <&BIG_CPU_SLEEP_0>;
360 }; 358 };
361 359
362 CPU_PD6: power-domain-cpu6 { 360 CPU_PD6: power-domain-cpu6 {
363 #power-domain-cells = 361 #power-domain-cells = <0>;
364 power-domains = <&CLUS 362 power-domains = <&CLUSTER_PD>;
365 domain-idle-states = < 363 domain-idle-states = <&BIG_CPU_SLEEP_0>;
366 }; 364 };
367 365
368 CPU_PD7: power-domain-cpu7 { 366 CPU_PD7: power-domain-cpu7 {
369 #power-domain-cells = 367 #power-domain-cells = <0>;
370 power-domains = <&CLUS 368 power-domains = <&CLUSTER_PD>;
371 domain-idle-states = < 369 domain-idle-states = <&BIG_CPU_SLEEP_0>;
372 }; 370 };
373 371
374 CLUSTER_PD: power-domain-cpu-c 372 CLUSTER_PD: power-domain-cpu-cluster0 {
375 #power-domain-cells = 373 #power-domain-cells = <0>;
376 domain-idle-states = < 374 domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>;
377 }; 375 };
378 }; 376 };
379 377
380 qup_opp_table_100mhz: opp-table-qup { 378 qup_opp_table_100mhz: opp-table-qup {
381 compatible = "operating-points 379 compatible = "operating-points-v2";
382 380
383 opp-50000000 { 381 opp-50000000 {
384 opp-hz = /bits/ 64 <50 382 opp-hz = /bits/ 64 <50000000>;
385 required-opps = <&rpmh 383 required-opps = <&rpmhpd_opp_min_svs>;
386 }; 384 };
387 385
388 opp-75000000 { 386 opp-75000000 {
389 opp-hz = /bits/ 64 <75 387 opp-hz = /bits/ 64 <75000000>;
390 required-opps = <&rpmh 388 required-opps = <&rpmhpd_opp_low_svs>;
391 }; 389 };
392 390
393 opp-100000000 { 391 opp-100000000 {
394 opp-hz = /bits/ 64 <10 392 opp-hz = /bits/ 64 <100000000>;
395 required-opps = <&rpmh 393 required-opps = <&rpmhpd_opp_svs>;
396 }; 394 };
397 }; 395 };
398 396
399 reserved_memory: reserved-memory { 397 reserved_memory: reserved-memory {
400 #address-cells = <2>; 398 #address-cells = <2>;
401 #size-cells = <2>; 399 #size-cells = <2>;
402 ranges; 400 ranges;
403 401
404 hyp_mem: memory@80000000 { 402 hyp_mem: memory@80000000 {
405 reg = <0x0 0x80000000 403 reg = <0x0 0x80000000 0x0 0x600000>;
406 no-map; 404 no-map;
407 }; 405 };
408 406
409 xbl_dt_log_mem: memory@8060000 407 xbl_dt_log_mem: memory@80600000 {
410 reg = <0x0 0x80600000 408 reg = <0x0 0x80600000 0x0 0x40000>;
411 no-map; 409 no-map;
412 }; 410 };
413 411
414 xbl_ramdump_mem: memory@806400 412 xbl_ramdump_mem: memory@80640000 {
415 reg = <0x0 0x80640000 413 reg = <0x0 0x80640000 0x0 0x180000>;
416 no-map; 414 no-map;
417 }; 415 };
418 416
419 xbl_sc_mem: memory@807c0000 { 417 xbl_sc_mem: memory@807c0000 {
420 reg = <0x0 0x807c0000 418 reg = <0x0 0x807c0000 0x0 0x40000>;
421 no-map; 419 no-map;
422 }; 420 };
423 421
424 aop_image_mem: memory@80800000 422 aop_image_mem: memory@80800000 {
425 reg = <0x0 0x80800000 423 reg = <0x0 0x80800000 0x0 0x60000>;
426 no-map; 424 no-map;
427 }; 425 };
428 426
429 aop_cmd_db_mem: memory@8086000 427 aop_cmd_db_mem: memory@80860000 {
430 compatible = "qcom,cmd 428 compatible = "qcom,cmd-db";
431 reg = <0x0 0x80860000 429 reg = <0x0 0x80860000 0x0 0x20000>;
432 no-map; 430 no-map;
433 }; 431 };
434 432
435 aop_config_mem: memory@8088000 433 aop_config_mem: memory@80880000 {
436 reg = <0x0 0x80880000 434 reg = <0x0 0x80880000 0x0 0x20000>;
437 no-map; 435 no-map;
438 }; 436 };
439 437
440 tme_crash_dump_mem: memory@808 438 tme_crash_dump_mem: memory@808a0000 {
441 reg = <0x0 0x808a0000 439 reg = <0x0 0x808a0000 0x0 0x40000>;
442 no-map; 440 no-map;
443 }; 441 };
444 442
445 tme_log_mem: memory@808e0000 { 443 tme_log_mem: memory@808e0000 {
446 reg = <0x0 0x808e0000 444 reg = <0x0 0x808e0000 0x0 0x4000>;
447 no-map; 445 no-map;
448 }; 446 };
449 447
450 uefi_log_mem: memory@808e4000 448 uefi_log_mem: memory@808e4000 {
451 reg = <0x0 0x808e4000 449 reg = <0x0 0x808e4000 0x0 0x10000>;
452 no-map; 450 no-map;
453 }; 451 };
454 452
455 /* secdata region can be reuse 453 /* secdata region can be reused by apps */
456 smem: memory@80900000 { 454 smem: memory@80900000 {
457 compatible = "qcom,sme 455 compatible = "qcom,smem";
458 reg = <0x0 0x80900000 456 reg = <0x0 0x80900000 0x0 0x200000>;
459 hwlocks = <&tcsr_mutex 457 hwlocks = <&tcsr_mutex 3>;
460 no-map; 458 no-map;
461 }; 459 };
462 460
463 cpucp_fw_mem: memory@80b00000 461 cpucp_fw_mem: memory@80b00000 {
464 reg = <0x0 0x80b00000 462 reg = <0x0 0x80b00000 0x0 0x100000>;
465 no-map; 463 no-map;
466 }; 464 };
467 465
468 cdsp_secure_heap: memory@80c00 466 cdsp_secure_heap: memory@80c00000 {
469 reg = <0x0 0x80c00000 467 reg = <0x0 0x80c00000 0x0 0x4600000>;
470 no-map; 468 no-map;
471 }; 469 };
472 470
473 video_mem: memory@85700000 { 471 video_mem: memory@85700000 {
474 reg = <0x0 0x85700000 472 reg = <0x0 0x85700000 0x0 0x700000>;
475 no-map; 473 no-map;
476 }; 474 };
477 475
478 adsp_mem: memory@85e00000 { 476 adsp_mem: memory@85e00000 {
479 reg = <0x0 0x85e00000 477 reg = <0x0 0x85e00000 0x0 0x2100000>;
480 no-map; 478 no-map;
481 }; 479 };
482 480
483 slpi_mem: memory@88000000 { 481 slpi_mem: memory@88000000 {
484 reg = <0x0 0x88000000 482 reg = <0x0 0x88000000 0x0 0x1900000>;
485 no-map; 483 no-map;
486 }; 484 };
487 485
488 cdsp_mem: memory@89900000 { 486 cdsp_mem: memory@89900000 {
489 reg = <0x0 0x89900000 487 reg = <0x0 0x89900000 0x0 0x2000000>;
490 no-map; 488 no-map;
491 }; 489 };
492 490
493 ipa_fw_mem: memory@8b900000 { 491 ipa_fw_mem: memory@8b900000 {
494 reg = <0x0 0x8b900000 492 reg = <0x0 0x8b900000 0x0 0x10000>;
495 no-map; 493 no-map;
496 }; 494 };
497 495
498 ipa_gsi_mem: memory@8b910000 { 496 ipa_gsi_mem: memory@8b910000 {
499 reg = <0x0 0x8b910000 497 reg = <0x0 0x8b910000 0x0 0xa000>;
500 no-map; 498 no-map;
501 }; 499 };
502 500
503 gpu_micro_code_mem: memory@8b9 501 gpu_micro_code_mem: memory@8b91a000 {
504 reg = <0x0 0x8b91a000 502 reg = <0x0 0x8b91a000 0x0 0x2000>;
505 no-map; 503 no-map;
506 }; 504 };
507 505
508 spss_region_mem: memory@8ba000 506 spss_region_mem: memory@8ba00000 {
509 reg = <0x0 0x8ba00000 507 reg = <0x0 0x8ba00000 0x0 0x180000>;
510 no-map; 508 no-map;
511 }; 509 };
512 510
513 /* First part of the "SPU secu 511 /* First part of the "SPU secure shared memory" region */
514 spu_tz_shared_mem: memory@8bb8 512 spu_tz_shared_mem: memory@8bb80000 {
515 reg = <0x0 0x8bb80000 513 reg = <0x0 0x8bb80000 0x0 0x60000>;
516 no-map; 514 no-map;
517 }; 515 };
518 516
519 /* Second part of the "SPU sec 517 /* Second part of the "SPU secure shared memory" region */
520 spu_modem_shared_mem: memory@8 518 spu_modem_shared_mem: memory@8bbe0000 {
521 reg = <0x0 0x8bbe0000 519 reg = <0x0 0x8bbe0000 0x0 0x20000>;
522 no-map; 520 no-map;
523 }; 521 };
524 522
525 mpss_mem: memory@8bc00000 { 523 mpss_mem: memory@8bc00000 {
526 reg = <0x0 0x8bc00000 524 reg = <0x0 0x8bc00000 0x0 0x13200000>;
527 no-map; 525 no-map;
528 }; 526 };
529 527
530 cvp_mem: memory@9ee00000 { 528 cvp_mem: memory@9ee00000 {
531 reg = <0x0 0x9ee00000 529 reg = <0x0 0x9ee00000 0x0 0x700000>;
532 no-map; 530 no-map;
533 }; 531 };
534 532
535 camera_mem: memory@9f500000 { 533 camera_mem: memory@9f500000 {
536 reg = <0x0 0x9f500000 534 reg = <0x0 0x9f500000 0x0 0x800000>;
537 no-map; 535 no-map;
538 }; 536 };
539 537
540 rmtfs_mem: memory@9fd00000 { 538 rmtfs_mem: memory@9fd00000 {
541 compatible = "qcom,rmt 539 compatible = "qcom,rmtfs-mem";
542 reg = <0x0 0x9fd00000 540 reg = <0x0 0x9fd00000 0x0 0x280000>;
543 no-map; 541 no-map;
544 542
545 qcom,client-id = <1>; 543 qcom,client-id = <1>;
546 qcom,vmid = <QCOM_SCM_ 544 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
547 }; 545 };
548 546
549 xbl_sc_mem2: memory@a6e00000 { 547 xbl_sc_mem2: memory@a6e00000 {
550 reg = <0x0 0xa6e00000 548 reg = <0x0 0xa6e00000 0x0 0x40000>;
551 no-map; 549 no-map;
552 }; 550 };
553 551
554 global_sync_mem: memory@a6f000 552 global_sync_mem: memory@a6f00000 {
555 reg = <0x0 0xa6f00000 553 reg = <0x0 0xa6f00000 0x0 0x100000>;
556 no-map; 554 no-map;
557 }; 555 };
558 556
559 /* uefi region can be reused b 557 /* uefi region can be reused by APPS */
560 558
561 /* Linux kernel image is loade 559 /* Linux kernel image is loaded at 0xa0000000 */
562 560
563 oem_vm_mem: memory@bb000000 { 561 oem_vm_mem: memory@bb000000 {
564 reg = <0x0 0xbb000000 562 reg = <0x0 0xbb000000 0x0 0x5000000>;
565 no-map; 563 no-map;
566 }; 564 };
567 565
568 mte_mem: memory@c0000000 { 566 mte_mem: memory@c0000000 {
569 reg = <0x0 0xc0000000 567 reg = <0x0 0xc0000000 0x0 0x20000000>;
570 no-map; 568 no-map;
571 }; 569 };
572 570
573 qheebsp_reserved_mem: memory@e 571 qheebsp_reserved_mem: memory@e0000000 {
574 reg = <0x0 0xe0000000 572 reg = <0x0 0xe0000000 0x0 0x600000>;
575 no-map; 573 no-map;
576 }; 574 };
577 575
578 cpusys_vm_mem: memory@e0600000 576 cpusys_vm_mem: memory@e0600000 {
579 reg = <0x0 0xe0600000 577 reg = <0x0 0xe0600000 0x0 0x400000>;
580 no-map; 578 no-map;
581 }; 579 };
582 580
583 hyp_reserved_mem: memory@e0a00 581 hyp_reserved_mem: memory@e0a00000 {
584 reg = <0x0 0xe0a00000 582 reg = <0x0 0xe0a00000 0x0 0x100000>;
585 no-map; 583 no-map;
586 }; 584 };
587 585
588 trust_ui_vm_mem: memory@e0b000 586 trust_ui_vm_mem: memory@e0b00000 {
589 reg = <0x0 0xe0b00000 587 reg = <0x0 0xe0b00000 0x0 0x4af3000>;
590 no-map; 588 no-map;
591 }; 589 };
592 590
593 trust_ui_vm_qrtr: memory@e55f3 591 trust_ui_vm_qrtr: memory@e55f3000 {
594 reg = <0x0 0xe55f3000 592 reg = <0x0 0xe55f3000 0x0 0x9000>;
595 no-map; 593 no-map;
596 }; 594 };
597 595
598 trust_ui_vm_vblk0_ring: memory 596 trust_ui_vm_vblk0_ring: memory@e55fc000 {
599 reg = <0x0 0xe55fc000 597 reg = <0x0 0xe55fc000 0x0 0x4000>;
600 no-map; 598 no-map;
601 }; 599 };
602 600
603 trust_ui_vm_swiotlb: memory@e5 601 trust_ui_vm_swiotlb: memory@e5600000 {
604 reg = <0x0 0xe5600000 602 reg = <0x0 0xe5600000 0x0 0x100000>;
605 no-map; 603 no-map;
606 }; 604 };
607 605
608 tz_stat_mem: memory@e8800000 { 606 tz_stat_mem: memory@e8800000 {
609 reg = <0x0 0xe8800000 607 reg = <0x0 0xe8800000 0x0 0x100000>;
610 no-map; 608 no-map;
611 }; 609 };
612 610
613 tags_mem: memory@e8900000 { 611 tags_mem: memory@e8900000 {
614 reg = <0x0 0xe8900000 612 reg = <0x0 0xe8900000 0x0 0x1200000>;
615 no-map; 613 no-map;
616 }; 614 };
617 615
618 qtee_mem: memory@e9b00000 { 616 qtee_mem: memory@e9b00000 {
619 reg = <0x0 0xe9b00000 617 reg = <0x0 0xe9b00000 0x0 0x500000>;
620 no-map; 618 no-map;
621 }; 619 };
622 620
623 trusted_apps_mem: memory@ea000 621 trusted_apps_mem: memory@ea000000 {
624 reg = <0x0 0xea000000 622 reg = <0x0 0xea000000 0x0 0x3900000>;
625 no-map; 623 no-map;
626 }; 624 };
627 625
628 trusted_apps_ext_mem: memory@e 626 trusted_apps_ext_mem: memory@ed900000 {
629 reg = <0x0 0xed900000 627 reg = <0x0 0xed900000 0x0 0x3b00000>;
630 no-map; 628 no-map;
631 }; 629 };
632 }; 630 };
633 631
634 smp2p-adsp { 632 smp2p-adsp {
635 compatible = "qcom,smp2p"; 633 compatible = "qcom,smp2p";
636 qcom,smem = <443>, <429>; 634 qcom,smem = <443>, <429>;
637 interrupts-extended = <&ipcc I 635 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
638 I 636 IPCC_MPROC_SIGNAL_SMP2P
639 I 637 IRQ_TYPE_EDGE_RISING>;
640 mboxes = <&ipcc IPCC_CLIENT_LP 638 mboxes = <&ipcc IPCC_CLIENT_LPASS
641 IPCC_MPROC_SIG 639 IPCC_MPROC_SIGNAL_SMP2P>;
642 640
643 qcom,local-pid = <0>; 641 qcom,local-pid = <0>;
644 qcom,remote-pid = <2>; 642 qcom,remote-pid = <2>;
645 643
646 smp2p_adsp_out: master-kernel 644 smp2p_adsp_out: master-kernel {
647 qcom,entry-name = "mas 645 qcom,entry-name = "master-kernel";
648 #qcom,smem-state-cells 646 #qcom,smem-state-cells = <1>;
649 }; 647 };
650 648
651 smp2p_adsp_in: slave-kernel { 649 smp2p_adsp_in: slave-kernel {
652 qcom,entry-name = "sla 650 qcom,entry-name = "slave-kernel";
653 interrupt-controller; 651 interrupt-controller;
654 #interrupt-cells = <2> 652 #interrupt-cells = <2>;
655 }; 653 };
656 }; 654 };
657 655
658 smp2p-cdsp { 656 smp2p-cdsp {
659 compatible = "qcom,smp2p"; 657 compatible = "qcom,smp2p";
660 qcom,smem = <94>, <432>; 658 qcom,smem = <94>, <432>;
661 interrupts-extended = <&ipcc I 659 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
662 I 660 IPCC_MPROC_SIGNAL_SMP2P
663 I 661 IRQ_TYPE_EDGE_RISING>;
664 mboxes = <&ipcc IPCC_CLIENT_CD 662 mboxes = <&ipcc IPCC_CLIENT_CDSP
665 IPCC_MPROC_SIG 663 IPCC_MPROC_SIGNAL_SMP2P>;
666 664
667 qcom,local-pid = <0>; 665 qcom,local-pid = <0>;
668 qcom,remote-pid = <5>; 666 qcom,remote-pid = <5>;
669 667
670 smp2p_cdsp_out: master-kernel 668 smp2p_cdsp_out: master-kernel {
671 qcom,entry-name = "mas 669 qcom,entry-name = "master-kernel";
672 #qcom,smem-state-cells 670 #qcom,smem-state-cells = <1>;
673 }; 671 };
674 672
675 smp2p_cdsp_in: slave-kernel { 673 smp2p_cdsp_in: slave-kernel {
676 qcom,entry-name = "sla 674 qcom,entry-name = "slave-kernel";
677 interrupt-controller; 675 interrupt-controller;
678 #interrupt-cells = <2> 676 #interrupt-cells = <2>;
679 }; 677 };
680 }; 678 };
681 679
682 smp2p-modem { 680 smp2p-modem {
683 compatible = "qcom,smp2p"; 681 compatible = "qcom,smp2p";
684 qcom,smem = <435>, <428>; 682 qcom,smem = <435>, <428>;
685 interrupts-extended = <&ipcc I 683 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
686 I 684 IPCC_MPROC_SIGNAL_SMP2P
687 I 685 IRQ_TYPE_EDGE_RISING>;
688 mboxes = <&ipcc IPCC_CLIENT_MP 686 mboxes = <&ipcc IPCC_CLIENT_MPSS
689 IPCC_MPROC_SIG 687 IPCC_MPROC_SIGNAL_SMP2P>;
690 688
691 qcom,local-pid = <0>; 689 qcom,local-pid = <0>;
692 qcom,remote-pid = <1>; 690 qcom,remote-pid = <1>;
693 691
694 smp2p_modem_out: master-kernel 692 smp2p_modem_out: master-kernel {
695 qcom,entry-name = "mas 693 qcom,entry-name = "master-kernel";
696 #qcom,smem-state-cells 694 #qcom,smem-state-cells = <1>;
697 }; 695 };
698 696
699 smp2p_modem_in: slave-kernel { 697 smp2p_modem_in: slave-kernel {
700 qcom,entry-name = "sla 698 qcom,entry-name = "slave-kernel";
701 interrupt-controller; 699 interrupt-controller;
702 #interrupt-cells = <2> 700 #interrupt-cells = <2>;
703 }; 701 };
704 702
705 ipa_smp2p_out: ipa-ap-to-modem 703 ipa_smp2p_out: ipa-ap-to-modem {
706 qcom,entry-name = "ipa 704 qcom,entry-name = "ipa";
707 #qcom,smem-state-cells 705 #qcom,smem-state-cells = <1>;
708 }; 706 };
709 707
710 ipa_smp2p_in: ipa-modem-to-ap 708 ipa_smp2p_in: ipa-modem-to-ap {
711 qcom,entry-name = "ipa 709 qcom,entry-name = "ipa";
712 interrupt-controller; 710 interrupt-controller;
713 #interrupt-cells = <2> 711 #interrupt-cells = <2>;
714 }; 712 };
715 }; 713 };
716 714
717 smp2p-slpi { 715 smp2p-slpi {
718 compatible = "qcom,smp2p"; 716 compatible = "qcom,smp2p";
719 qcom,smem = <481>, <430>; 717 qcom,smem = <481>, <430>;
720 interrupts-extended = <&ipcc I 718 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
721 I 719 IPCC_MPROC_SIGNAL_SMP2P
722 I 720 IRQ_TYPE_EDGE_RISING>;
723 mboxes = <&ipcc IPCC_CLIENT_SL 721 mboxes = <&ipcc IPCC_CLIENT_SLPI
724 IPCC_MPROC_SIG 722 IPCC_MPROC_SIGNAL_SMP2P>;
725 723
726 qcom,local-pid = <0>; 724 qcom,local-pid = <0>;
727 qcom,remote-pid = <3>; 725 qcom,remote-pid = <3>;
728 726
729 smp2p_slpi_out: master-kernel 727 smp2p_slpi_out: master-kernel {
730 qcom,entry-name = "mas 728 qcom,entry-name = "master-kernel";
731 #qcom,smem-state-cells 729 #qcom,smem-state-cells = <1>;
732 }; 730 };
733 731
734 smp2p_slpi_in: slave-kernel { 732 smp2p_slpi_in: slave-kernel {
735 qcom,entry-name = "sla 733 qcom,entry-name = "slave-kernel";
736 interrupt-controller; 734 interrupt-controller;
737 #interrupt-cells = <2> 735 #interrupt-cells = <2>;
738 }; 736 };
739 }; 737 };
740 738
741 soc: soc@0 { 739 soc: soc@0 {
742 #address-cells = <2>; 740 #address-cells = <2>;
743 #size-cells = <2>; 741 #size-cells = <2>;
744 ranges = <0 0 0 0 0x10 0>; 742 ranges = <0 0 0 0 0x10 0>;
745 dma-ranges = <0 0 0 0 0x10 0>; 743 dma-ranges = <0 0 0 0 0x10 0>;
746 compatible = "simple-bus"; 744 compatible = "simple-bus";
747 745
748 gcc: clock-controller@100000 { 746 gcc: clock-controller@100000 {
749 compatible = "qcom,gcc 747 compatible = "qcom,gcc-sm8450";
750 reg = <0x0 0x00100000 748 reg = <0x0 0x00100000 0x0 0x1f4200>;
751 #clock-cells = <1>; 749 #clock-cells = <1>;
752 #reset-cells = <1>; 750 #reset-cells = <1>;
753 #power-domain-cells = 751 #power-domain-cells = <1>;
754 clocks = <&rpmhcc RPMH 752 clocks = <&rpmhcc RPMH_CXO_CLK>,
755 <&sleep_clk>, 753 <&sleep_clk>,
756 <&pcie0_phy>, 754 <&pcie0_phy>,
757 <&pcie1_phy Q !! 755 <&pcie1_phy>,
758 <&pcie1_phy Q !! 756 <0>,
759 <&ufs_mem_phy !! 757 <&ufs_mem_phy_lanes 0>,
760 <&ufs_mem_phy !! 758 <&ufs_mem_phy_lanes 1>,
761 <&ufs_mem_phy !! 759 <&ufs_mem_phy_lanes 2>,
762 <&usb_1_qmpph 760 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
763 clock-names = "bi_tcxo 761 clock-names = "bi_tcxo",
764 "sleep_c 762 "sleep_clk",
765 "pcie_0_ 763 "pcie_0_pipe_clk",
766 "pcie_1_ 764 "pcie_1_pipe_clk",
767 "pcie_1_ 765 "pcie_1_phy_aux_clk",
768 "ufs_phy 766 "ufs_phy_rx_symbol_0_clk",
769 "ufs_phy 767 "ufs_phy_rx_symbol_1_clk",
770 "ufs_phy 768 "ufs_phy_tx_symbol_0_clk",
771 "usb3_ph 769 "usb3_phy_wrapper_gcc_usb30_pipe_clk";
772 }; 770 };
773 771
774 gpi_dma2: dma-controller@80000 772 gpi_dma2: dma-controller@800000 {
775 compatible = "qcom,sm8 773 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
776 #dma-cells = <3>; 774 #dma-cells = <3>;
777 reg = <0 0x00800000 0 775 reg = <0 0x00800000 0 0x60000>;
778 interrupts = <GIC_SPI 776 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
779 <GIC_SPI 777 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
780 <GIC_SPI 778 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
781 <GIC_SPI 779 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
782 <GIC_SPI 780 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
783 <GIC_SPI 781 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
784 <GIC_SPI 782 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
785 <GIC_SPI 783 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
786 <GIC_SPI 784 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
787 <GIC_SPI 785 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
788 <GIC_SPI 786 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
789 <GIC_SPI 787 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
790 dma-channels = <12>; 788 dma-channels = <12>;
791 dma-channel-mask = <0x 789 dma-channel-mask = <0x7e>;
792 iommus = <&apps_smmu 0 790 iommus = <&apps_smmu 0x496 0x0>;
793 status = "disabled"; 791 status = "disabled";
794 }; 792 };
795 793
796 qupv3_id_2: geniqup@8c0000 { 794 qupv3_id_2: geniqup@8c0000 {
797 compatible = "qcom,gen 795 compatible = "qcom,geni-se-qup";
798 reg = <0x0 0x008c0000 796 reg = <0x0 0x008c0000 0x0 0x2000>;
799 clock-names = "m-ahb", 797 clock-names = "m-ahb", "s-ahb";
800 clocks = <&gcc GCC_QUP 798 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
801 <&gcc GCC_QUP 799 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
802 iommus = <&apps_smmu 0 800 iommus = <&apps_smmu 0x483 0x0>;
803 #address-cells = <2>; 801 #address-cells = <2>;
804 #size-cells = <2>; 802 #size-cells = <2>;
805 ranges; 803 ranges;
806 status = "disabled"; 804 status = "disabled";
807 805
808 i2c15: i2c@880000 { 806 i2c15: i2c@880000 {
809 compatible = " 807 compatible = "qcom,geni-i2c";
810 reg = <0x0 0x0 808 reg = <0x0 0x00880000 0x0 0x4000>;
811 clock-names = 809 clock-names = "se";
812 clocks = <&gcc 810 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
813 pinctrl-names 811 pinctrl-names = "default";
814 pinctrl-0 = <& 812 pinctrl-0 = <&qup_i2c15_data_clk>;
815 interrupts = < 813 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
816 #address-cells 814 #address-cells = <1>;
817 #size-cells = 815 #size-cells = <0>;
818 interconnects 816 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
819 817 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
820 818 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
821 interconnect-n 819 interconnect-names = "qup-core", "qup-config", "qup-memory";
822 dmas = <&gpi_d 820 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
823 <&gpi_d 821 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
824 dma-names = "t 822 dma-names = "tx", "rx";
825 status = "disa 823 status = "disabled";
826 }; 824 };
827 825
828 spi15: spi@880000 { 826 spi15: spi@880000 {
829 compatible = " 827 compatible = "qcom,geni-spi";
830 reg = <0x0 0x0 828 reg = <0x0 0x00880000 0x0 0x4000>;
831 clock-names = 829 clock-names = "se";
832 clocks = <&gcc 830 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
833 interrupts = < 831 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
834 pinctrl-names 832 pinctrl-names = "default";
835 pinctrl-0 = <& 833 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
836 interconnects 834 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
837 835 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
838 interconnect-n 836 interconnect-names = "qup-core", "qup-config";
839 dmas = <&gpi_d 837 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
840 <&gpi_d 838 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
841 dma-names = "t 839 dma-names = "tx", "rx";
842 #address-cells 840 #address-cells = <1>;
843 #size-cells = 841 #size-cells = <0>;
844 status = "disa 842 status = "disabled";
845 }; 843 };
846 844
847 i2c16: i2c@884000 { 845 i2c16: i2c@884000 {
848 compatible = " 846 compatible = "qcom,geni-i2c";
849 reg = <0x0 0x0 847 reg = <0x0 0x00884000 0x0 0x4000>;
850 clock-names = 848 clock-names = "se";
851 clocks = <&gcc 849 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
852 pinctrl-names 850 pinctrl-names = "default";
853 pinctrl-0 = <& 851 pinctrl-0 = <&qup_i2c16_data_clk>;
854 interrupts = < 852 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
855 #address-cells 853 #address-cells = <1>;
856 #size-cells = 854 #size-cells = <0>;
857 interconnects 855 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
858 856 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
859 857 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
860 interconnect-n 858 interconnect-names = "qup-core", "qup-config", "qup-memory";
861 dmas = <&gpi_d 859 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
862 <&gpi_d 860 <&gpi_dma2 1 1 QCOM_GPI_I2C>;
863 dma-names = "t 861 dma-names = "tx", "rx";
864 status = "disa 862 status = "disabled";
865 }; 863 };
866 864
867 spi16: spi@884000 { 865 spi16: spi@884000 {
868 compatible = " 866 compatible = "qcom,geni-spi";
869 reg = <0x0 0x0 867 reg = <0x0 0x00884000 0x0 0x4000>;
870 clock-names = 868 clock-names = "se";
871 clocks = <&gcc 869 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
872 interrupts = < 870 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
873 pinctrl-names 871 pinctrl-names = "default";
874 pinctrl-0 = <& 872 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>;
875 interconnects 873 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
876 874 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
877 interconnect-n 875 interconnect-names = "qup-core", "qup-config";
878 dmas = <&gpi_d 876 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
879 <&gpi_d 877 <&gpi_dma2 1 1 QCOM_GPI_SPI>;
880 dma-names = "t 878 dma-names = "tx", "rx";
881 #address-cells 879 #address-cells = <1>;
882 #size-cells = 880 #size-cells = <0>;
883 status = "disa 881 status = "disabled";
884 }; 882 };
885 883
886 i2c17: i2c@888000 { 884 i2c17: i2c@888000 {
887 compatible = " 885 compatible = "qcom,geni-i2c";
888 reg = <0x0 0x0 886 reg = <0x0 0x00888000 0x0 0x4000>;
889 clock-names = 887 clock-names = "se";
890 clocks = <&gcc 888 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
891 pinctrl-names 889 pinctrl-names = "default";
892 pinctrl-0 = <& 890 pinctrl-0 = <&qup_i2c17_data_clk>;
893 interrupts = < 891 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
894 #address-cells 892 #address-cells = <1>;
895 #size-cells = 893 #size-cells = <0>;
896 interconnects 894 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
897 895 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
898 896 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
899 interconnect-n 897 interconnect-names = "qup-core", "qup-config", "qup-memory";
900 dmas = <&gpi_d 898 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
901 <&gpi_d 899 <&gpi_dma2 1 2 QCOM_GPI_I2C>;
902 dma-names = "t 900 dma-names = "tx", "rx";
903 status = "disa 901 status = "disabled";
904 }; 902 };
905 903
906 spi17: spi@888000 { 904 spi17: spi@888000 {
907 compatible = " 905 compatible = "qcom,geni-spi";
908 reg = <0x0 0x0 906 reg = <0x0 0x00888000 0x0 0x4000>;
909 clock-names = 907 clock-names = "se";
910 clocks = <&gcc 908 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
911 interrupts = < 909 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
912 pinctrl-names 910 pinctrl-names = "default";
913 pinctrl-0 = <& 911 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>;
914 interconnects 912 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
915 913 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
916 interconnect-n 914 interconnect-names = "qup-core", "qup-config";
917 dmas = <&gpi_d 915 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
918 <&gpi_d 916 <&gpi_dma2 1 2 QCOM_GPI_SPI>;
919 dma-names = "t 917 dma-names = "tx", "rx";
920 #address-cells 918 #address-cells = <1>;
921 #size-cells = 919 #size-cells = <0>;
922 status = "disa 920 status = "disabled";
923 }; 921 };
924 922
925 i2c18: i2c@88c000 { 923 i2c18: i2c@88c000 {
926 compatible = " 924 compatible = "qcom,geni-i2c";
927 reg = <0x0 0x0 925 reg = <0x0 0x0088c000 0x0 0x4000>;
928 clock-names = 926 clock-names = "se";
929 clocks = <&gcc 927 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
930 pinctrl-names 928 pinctrl-names = "default";
931 pinctrl-0 = <& 929 pinctrl-0 = <&qup_i2c18_data_clk>;
932 interrupts = < 930 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
933 #address-cells 931 #address-cells = <1>;
934 #size-cells = 932 #size-cells = <0>;
935 interconnects 933 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
936 934 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
937 935 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
938 interconnect-n 936 interconnect-names = "qup-core", "qup-config", "qup-memory";
939 dmas = <&gpi_d 937 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
940 <&gpi_d 938 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
941 dma-names = "t 939 dma-names = "tx", "rx";
942 status = "disa 940 status = "disabled";
943 }; 941 };
944 942
945 spi18: spi@88c000 { 943 spi18: spi@88c000 {
946 compatible = " 944 compatible = "qcom,geni-spi";
947 reg = <0 0x008 945 reg = <0 0x0088c000 0 0x4000>;
948 clock-names = 946 clock-names = "se";
949 clocks = <&gcc 947 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
950 interrupts = < 948 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
951 pinctrl-names 949 pinctrl-names = "default";
952 pinctrl-0 = <& 950 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>;
953 interconnects 951 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
954 952 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
955 interconnect-n 953 interconnect-names = "qup-core", "qup-config";
956 dmas = <&gpi_d 954 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
957 <&gpi_d 955 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
958 dma-names = "t 956 dma-names = "tx", "rx";
959 #address-cells 957 #address-cells = <1>;
960 #size-cells = 958 #size-cells = <0>;
961 status = "disa 959 status = "disabled";
962 }; 960 };
963 961
964 i2c19: i2c@890000 { 962 i2c19: i2c@890000 {
965 compatible = " 963 compatible = "qcom,geni-i2c";
966 reg = <0x0 0x0 964 reg = <0x0 0x00890000 0x0 0x4000>;
967 clock-names = 965 clock-names = "se";
968 clocks = <&gcc 966 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
969 pinctrl-names 967 pinctrl-names = "default";
970 pinctrl-0 = <& 968 pinctrl-0 = <&qup_i2c19_data_clk>;
971 interrupts = < 969 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
972 #address-cells 970 #address-cells = <1>;
973 #size-cells = 971 #size-cells = <0>;
974 interconnects 972 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
975 973 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
976 974 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
977 interconnect-n 975 interconnect-names = "qup-core", "qup-config", "qup-memory";
978 dmas = <&gpi_d 976 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
979 <&gpi_d 977 <&gpi_dma2 1 4 QCOM_GPI_I2C>;
980 dma-names = "t 978 dma-names = "tx", "rx";
981 status = "disa 979 status = "disabled";
982 }; 980 };
983 981
984 spi19: spi@890000 { 982 spi19: spi@890000 {
985 compatible = " 983 compatible = "qcom,geni-spi";
986 reg = <0 0x008 984 reg = <0 0x00890000 0 0x4000>;
987 clock-names = 985 clock-names = "se";
988 clocks = <&gcc 986 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
989 interrupts = < 987 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
990 pinctrl-names 988 pinctrl-names = "default";
991 pinctrl-0 = <& 989 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>;
992 interconnects 990 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
993 991 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
994 interconnect-n 992 interconnect-names = "qup-core", "qup-config";
995 dmas = <&gpi_d 993 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
996 <&gpi_d 994 <&gpi_dma2 1 4 QCOM_GPI_I2C>;
997 dma-names = "t 995 dma-names = "tx", "rx";
998 #address-cells 996 #address-cells = <1>;
999 #size-cells = 997 #size-cells = <0>;
1000 status = "dis 998 status = "disabled";
1001 }; 999 };
1002 1000
1003 i2c20: i2c@894000 { 1001 i2c20: i2c@894000 {
1004 compatible = 1002 compatible = "qcom,geni-i2c";
1005 reg = <0x0 0x 1003 reg = <0x0 0x00894000 0x0 0x4000>;
1006 clock-names = 1004 clock-names = "se";
1007 clocks = <&gc 1005 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1008 pinctrl-names 1006 pinctrl-names = "default";
1009 pinctrl-0 = < 1007 pinctrl-0 = <&qup_i2c20_data_clk>;
1010 interrupts = 1008 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1011 #address-cell 1009 #address-cells = <1>;
1012 #size-cells = 1010 #size-cells = <0>;
1013 interconnects 1011 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1014 1012 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1015 1013 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1016 interconnect- 1014 interconnect-names = "qup-core", "qup-config", "qup-memory";
1017 dmas = <&gpi_ 1015 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1018 <&gpi_ 1016 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1019 dma-names = " 1017 dma-names = "tx", "rx";
1020 status = "dis 1018 status = "disabled";
1021 }; 1019 };
1022 1020
1023 uart20: serial@894000 1021 uart20: serial@894000 {
1024 compatible = 1022 compatible = "qcom,geni-uart";
1025 reg = <0 0x00 1023 reg = <0 0x00894000 0 0x4000>;
1026 clock-names = 1024 clock-names = "se";
1027 clocks = <&gc 1025 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1028 pinctrl-names 1026 pinctrl-names = "default";
1029 pinctrl-0 = < 1027 pinctrl-0 = <&qup_uart20_default>;
1030 interrupts = 1028 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1031 interconnects 1029 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1032 1030 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1033 1031 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1034 1032 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
1035 interconnect- 1033 interconnect-names = "qup-core",
1036 1034 "qup-config";
1037 status = "dis 1035 status = "disabled";
1038 }; 1036 };
1039 1037
1040 spi20: spi@894000 { 1038 spi20: spi@894000 {
1041 compatible = 1039 compatible = "qcom,geni-spi";
1042 reg = <0 0x00 1040 reg = <0 0x00894000 0 0x4000>;
1043 clock-names = 1041 clock-names = "se";
1044 clocks = <&gc 1042 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1045 interrupts = 1043 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1046 pinctrl-names 1044 pinctrl-names = "default";
1047 pinctrl-0 = < 1045 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>;
1048 interconnects 1046 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1049 1047 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
1050 interconnect- 1048 interconnect-names = "qup-core", "qup-config";
1051 dmas = <&gpi_ 1049 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1052 <&gpi_ 1050 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1053 dma-names = " 1051 dma-names = "tx", "rx";
1054 #address-cell 1052 #address-cells = <1>;
1055 #size-cells = 1053 #size-cells = <0>;
1056 status = "dis 1054 status = "disabled";
1057 }; 1055 };
1058 1056
1059 i2c21: i2c@898000 { 1057 i2c21: i2c@898000 {
1060 compatible = 1058 compatible = "qcom,geni-i2c";
1061 reg = <0x0 0x 1059 reg = <0x0 0x00898000 0x0 0x4000>;
1062 clock-names = 1060 clock-names = "se";
1063 clocks = <&gc 1061 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1064 pinctrl-names 1062 pinctrl-names = "default";
1065 pinctrl-0 = < 1063 pinctrl-0 = <&qup_i2c21_data_clk>;
1066 interrupts = 1064 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
1067 #address-cell 1065 #address-cells = <1>;
1068 #size-cells = 1066 #size-cells = <0>;
1069 interconnects 1067 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1070 1068 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1071 1069 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1072 interconnect- 1070 interconnect-names = "qup-core", "qup-config", "qup-memory";
1073 dmas = <&gpi_ 1071 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>,
1074 <&gpi_ 1072 <&gpi_dma2 1 6 QCOM_GPI_I2C>;
1075 dma-names = " 1073 dma-names = "tx", "rx";
1076 status = "dis 1074 status = "disabled";
1077 }; 1075 };
1078 1076
1079 spi21: spi@898000 { 1077 spi21: spi@898000 {
1080 compatible = 1078 compatible = "qcom,geni-spi";
1081 reg = <0 0x00 1079 reg = <0 0x00898000 0 0x4000>;
1082 clock-names = 1080 clock-names = "se";
1083 clocks = <&gc 1081 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1084 interrupts = 1082 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
1085 pinctrl-names 1083 pinctrl-names = "default";
1086 pinctrl-0 = < 1084 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>;
1087 interconnects 1085 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1088 1086 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
1089 interconnect- 1087 interconnect-names = "qup-core", "qup-config";
1090 dmas = <&gpi_ 1088 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>,
1091 <&gpi_ 1089 <&gpi_dma2 1 6 QCOM_GPI_SPI>;
1092 dma-names = " 1090 dma-names = "tx", "rx";
1093 #address-cell 1091 #address-cells = <1>;
1094 #size-cells = 1092 #size-cells = <0>;
1095 status = "dis 1093 status = "disabled";
1096 }; 1094 };
1097 }; 1095 };
1098 1096
1099 gpi_dma0: dma-controller@9000 1097 gpi_dma0: dma-controller@900000 {
1100 compatible = "qcom,sm 1098 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
1101 #dma-cells = <3>; 1099 #dma-cells = <3>;
1102 reg = <0 0x00900000 0 1100 reg = <0 0x00900000 0 0x60000>;
1103 interrupts = <GIC_SPI 1101 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
1104 <GIC_SPI 1102 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
1105 <GIC_SPI 1103 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
1106 <GIC_SPI 1104 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
1107 <GIC_SPI 1105 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
1108 <GIC_SPI 1106 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
1109 <GIC_SPI 1107 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
1110 <GIC_SPI 1108 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
1111 <GIC_SPI 1109 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
1112 <GIC_SPI 1110 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
1113 <GIC_SPI 1111 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
1114 <GIC_SPI 1112 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
1115 dma-channels = <12>; 1113 dma-channels = <12>;
1116 dma-channel-mask = <0 1114 dma-channel-mask = <0x7e>;
1117 iommus = <&apps_smmu 1115 iommus = <&apps_smmu 0x5b6 0x0>;
1118 status = "disabled"; 1116 status = "disabled";
1119 }; 1117 };
1120 1118
1121 qupv3_id_0: geniqup@9c0000 { 1119 qupv3_id_0: geniqup@9c0000 {
1122 compatible = "qcom,ge 1120 compatible = "qcom,geni-se-qup";
1123 reg = <0x0 0x009c0000 1121 reg = <0x0 0x009c0000 0x0 0x2000>;
1124 clock-names = "m-ahb" 1122 clock-names = "m-ahb", "s-ahb";
1125 clocks = <&gcc GCC_QU 1123 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1126 <&gcc GCC_QU 1124 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1127 iommus = <&apps_smmu 1125 iommus = <&apps_smmu 0x5a3 0x0>;
1128 interconnects = <&clk 1126 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>;
1129 interconnect-names = 1127 interconnect-names = "qup-core";
1130 #address-cells = <2>; 1128 #address-cells = <2>;
1131 #size-cells = <2>; 1129 #size-cells = <2>;
1132 ranges; 1130 ranges;
1133 status = "disabled"; 1131 status = "disabled";
1134 1132
1135 i2c0: i2c@980000 { 1133 i2c0: i2c@980000 {
1136 compatible = 1134 compatible = "qcom,geni-i2c";
1137 reg = <0x0 0x 1135 reg = <0x0 0x00980000 0x0 0x4000>;
1138 clock-names = 1136 clock-names = "se";
1139 clocks = <&gc 1137 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1140 pinctrl-names 1138 pinctrl-names = "default";
1141 pinctrl-0 = < 1139 pinctrl-0 = <&qup_i2c0_data_clk>;
1142 interrupts = 1140 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1143 #address-cell 1141 #address-cells = <1>;
1144 #size-cells = 1142 #size-cells = <0>;
1145 interconnects 1143 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1146 1144 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1147 1145 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1148 interconnect- 1146 interconnect-names = "qup-core", "qup-config", "qup-memory";
1149 dmas = <&gpi_ 1147 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1150 <&gpi_ 1148 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1151 dma-names = " 1149 dma-names = "tx", "rx";
1152 status = "dis 1150 status = "disabled";
1153 }; 1151 };
1154 1152
1155 spi0: spi@980000 { 1153 spi0: spi@980000 {
1156 compatible = 1154 compatible = "qcom,geni-spi";
1157 reg = <0x0 0x 1155 reg = <0x0 0x00980000 0x0 0x4000>;
1158 clock-names = 1156 clock-names = "se";
1159 clocks = <&gc 1157 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1160 interrupts = 1158 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1161 pinctrl-names 1159 pinctrl-names = "default";
1162 pinctrl-0 = < 1160 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1163 power-domains 1161 power-domains = <&rpmhpd RPMHPD_CX>;
1164 operating-poi 1162 operating-points-v2 = <&qup_opp_table_100mhz>;
1165 interconnects 1163 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1166 1164 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1167 1165 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1168 interconnect- 1166 interconnect-names = "qup-core", "qup-config", "qup-memory";
1169 dmas = <&gpi_ 1167 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1170 <&gpi_ 1168 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1171 dma-names = " 1169 dma-names = "tx", "rx";
1172 #address-cell 1170 #address-cells = <1>;
1173 #size-cells = 1171 #size-cells = <0>;
1174 status = "dis 1172 status = "disabled";
1175 }; 1173 };
1176 1174
1177 i2c1: i2c@984000 { 1175 i2c1: i2c@984000 {
1178 compatible = 1176 compatible = "qcom,geni-i2c";
1179 reg = <0x0 0x 1177 reg = <0x0 0x00984000 0x0 0x4000>;
1180 clock-names = 1178 clock-names = "se";
1181 clocks = <&gc 1179 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1182 pinctrl-names 1180 pinctrl-names = "default";
1183 pinctrl-0 = < 1181 pinctrl-0 = <&qup_i2c1_data_clk>;
1184 interrupts = 1182 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1185 #address-cell 1183 #address-cells = <1>;
1186 #size-cells = 1184 #size-cells = <0>;
1187 interconnects 1185 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1188 1186 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1189 1187 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1190 interconnect- 1188 interconnect-names = "qup-core", "qup-config", "qup-memory";
1191 dmas = <&gpi_ 1189 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1192 <&gpi_ 1190 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1193 dma-names = " 1191 dma-names = "tx", "rx";
1194 status = "dis 1192 status = "disabled";
1195 }; 1193 };
1196 1194
1197 spi1: spi@984000 { 1195 spi1: spi@984000 {
1198 compatible = 1196 compatible = "qcom,geni-spi";
1199 reg = <0x0 0x 1197 reg = <0x0 0x00984000 0x0 0x4000>;
1200 clock-names = 1198 clock-names = "se";
1201 clocks = <&gc 1199 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1202 interrupts = 1200 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1203 pinctrl-names 1201 pinctrl-names = "default";
1204 pinctrl-0 = < 1202 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1205 interconnects 1203 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1206 1204 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1207 1205 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1208 interconnect- 1206 interconnect-names = "qup-core", "qup-config", "qup-memory";
1209 dmas = <&gpi_ 1207 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1210 <&gpi_ 1208 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1211 dma-names = " 1209 dma-names = "tx", "rx";
1212 #address-cell 1210 #address-cells = <1>;
1213 #size-cells = 1211 #size-cells = <0>;
1214 status = "dis 1212 status = "disabled";
1215 }; 1213 };
1216 1214
1217 i2c2: i2c@988000 { 1215 i2c2: i2c@988000 {
1218 compatible = 1216 compatible = "qcom,geni-i2c";
1219 reg = <0x0 0x 1217 reg = <0x0 0x00988000 0x0 0x4000>;
1220 clock-names = 1218 clock-names = "se";
1221 clocks = <&gc 1219 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1222 pinctrl-names 1220 pinctrl-names = "default";
1223 pinctrl-0 = < 1221 pinctrl-0 = <&qup_i2c2_data_clk>;
1224 interrupts = 1222 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1225 #address-cell 1223 #address-cells = <1>;
1226 #size-cells = 1224 #size-cells = <0>;
1227 interconnects 1225 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1228 1226 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1229 1227 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1230 interconnect- 1228 interconnect-names = "qup-core", "qup-config", "qup-memory";
1231 dmas = <&gpi_ 1229 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1232 <&gpi_ 1230 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1233 dma-names = " 1231 dma-names = "tx", "rx";
1234 status = "dis 1232 status = "disabled";
1235 }; 1233 };
1236 1234
1237 spi2: spi@988000 { 1235 spi2: spi@988000 {
1238 compatible = 1236 compatible = "qcom,geni-spi";
1239 reg = <0x0 0x 1237 reg = <0x0 0x00988000 0x0 0x4000>;
1240 clock-names = 1238 clock-names = "se";
1241 clocks = <&gc 1239 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1242 interrupts = 1240 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1243 pinctrl-names 1241 pinctrl-names = "default";
1244 pinctrl-0 = < 1242 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1245 interconnects 1243 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1246 1244 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1247 1245 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1248 interconnect- 1246 interconnect-names = "qup-core", "qup-config", "qup-memory";
1249 dmas = <&gpi_ 1247 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1250 <&gpi_ 1248 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1251 dma-names = " 1249 dma-names = "tx", "rx";
1252 #address-cell 1250 #address-cells = <1>;
1253 #size-cells = 1251 #size-cells = <0>;
1254 status = "dis 1252 status = "disabled";
1255 }; 1253 };
1256 1254
1257 1255
1258 i2c3: i2c@98c000 { 1256 i2c3: i2c@98c000 {
1259 compatible = 1257 compatible = "qcom,geni-i2c";
1260 reg = <0x0 0x 1258 reg = <0x0 0x0098c000 0x0 0x4000>;
1261 clock-names = 1259 clock-names = "se";
1262 clocks = <&gc 1260 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1263 pinctrl-names 1261 pinctrl-names = "default";
1264 pinctrl-0 = < 1262 pinctrl-0 = <&qup_i2c3_data_clk>;
1265 interrupts = 1263 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1266 #address-cell 1264 #address-cells = <1>;
1267 #size-cells = 1265 #size-cells = <0>;
1268 interconnects 1266 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1269 1267 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1270 1268 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1271 interconnect- 1269 interconnect-names = "qup-core", "qup-config", "qup-memory";
1272 dmas = <&gpi_ 1270 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1273 <&gpi_ 1271 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1274 dma-names = " 1272 dma-names = "tx", "rx";
1275 status = "dis 1273 status = "disabled";
1276 }; 1274 };
1277 1275
1278 spi3: spi@98c000 { 1276 spi3: spi@98c000 {
1279 compatible = 1277 compatible = "qcom,geni-spi";
1280 reg = <0x0 0x 1278 reg = <0x0 0x0098c000 0x0 0x4000>;
1281 clock-names = 1279 clock-names = "se";
1282 clocks = <&gc 1280 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1283 interrupts = 1281 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1284 pinctrl-names 1282 pinctrl-names = "default";
1285 pinctrl-0 = < 1283 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1286 interconnects 1284 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1287 1285 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1288 1286 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1289 interconnect- 1287 interconnect-names = "qup-core", "qup-config", "qup-memory";
1290 dmas = <&gpi_ 1288 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1291 <&gpi_ 1289 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1292 dma-names = " 1290 dma-names = "tx", "rx";
1293 #address-cell 1291 #address-cells = <1>;
1294 #size-cells = 1292 #size-cells = <0>;
1295 status = "dis 1293 status = "disabled";
1296 }; 1294 };
1297 1295
1298 i2c4: i2c@990000 { 1296 i2c4: i2c@990000 {
1299 compatible = 1297 compatible = "qcom,geni-i2c";
1300 reg = <0x0 0x 1298 reg = <0x0 0x00990000 0x0 0x4000>;
1301 clock-names = 1299 clock-names = "se";
1302 clocks = <&gc 1300 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1303 pinctrl-names 1301 pinctrl-names = "default";
1304 pinctrl-0 = < 1302 pinctrl-0 = <&qup_i2c4_data_clk>;
1305 interrupts = 1303 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1306 #address-cell 1304 #address-cells = <1>;
1307 #size-cells = 1305 #size-cells = <0>;
1308 interconnects 1306 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1309 1307 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1310 1308 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1311 interconnect- 1309 interconnect-names = "qup-core", "qup-config", "qup-memory";
1312 dmas = <&gpi_ 1310 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1313 <&gpi_ 1311 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1314 dma-names = " 1312 dma-names = "tx", "rx";
1315 status = "dis 1313 status = "disabled";
1316 }; 1314 };
1317 1315
1318 spi4: spi@990000 { 1316 spi4: spi@990000 {
1319 compatible = 1317 compatible = "qcom,geni-spi";
1320 reg = <0x0 0x 1318 reg = <0x0 0x00990000 0x0 0x4000>;
1321 clock-names = 1319 clock-names = "se";
1322 clocks = <&gc 1320 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1323 interrupts = 1321 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1324 pinctrl-names 1322 pinctrl-names = "default";
1325 pinctrl-0 = < 1323 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1326 power-domains 1324 power-domains = <&rpmhpd RPMHPD_CX>;
1327 operating-poi 1325 operating-points-v2 = <&qup_opp_table_100mhz>;
1328 interconnects 1326 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1329 1327 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1330 1328 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1331 interconnect- 1329 interconnect-names = "qup-core", "qup-config", "qup-memory";
1332 dmas = <&gpi_ 1330 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1333 <&gpi_ 1331 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1334 dma-names = " 1332 dma-names = "tx", "rx";
1335 #address-cell 1333 #address-cells = <1>;
1336 #size-cells = 1334 #size-cells = <0>;
1337 status = "dis 1335 status = "disabled";
1338 }; 1336 };
1339 1337
1340 i2c5: i2c@994000 { 1338 i2c5: i2c@994000 {
1341 compatible = 1339 compatible = "qcom,geni-i2c";
1342 reg = <0x0 0x 1340 reg = <0x0 0x00994000 0x0 0x4000>;
1343 clock-names = 1341 clock-names = "se";
1344 clocks = <&gc 1342 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1345 pinctrl-names 1343 pinctrl-names = "default";
1346 pinctrl-0 = < 1344 pinctrl-0 = <&qup_i2c5_data_clk>;
1347 interrupts = 1345 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1348 #address-cell 1346 #address-cells = <1>;
1349 #size-cells = 1347 #size-cells = <0>;
1350 interconnects 1348 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1351 1349 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1352 1350 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1353 interconnect- 1351 interconnect-names = "qup-core", "qup-config", "qup-memory";
1354 dmas = <&gpi_ 1352 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1355 <&gpi_ 1353 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1356 dma-names = " 1354 dma-names = "tx", "rx";
1357 status = "dis 1355 status = "disabled";
1358 }; 1356 };
1359 1357
1360 spi5: spi@994000 { 1358 spi5: spi@994000 {
1361 compatible = 1359 compatible = "qcom,geni-spi";
1362 reg = <0x0 0x 1360 reg = <0x0 0x00994000 0x0 0x4000>;
1363 clock-names = 1361 clock-names = "se";
1364 clocks = <&gc 1362 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1365 interrupts = 1363 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1366 pinctrl-names 1364 pinctrl-names = "default";
1367 pinctrl-0 = < 1365 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1368 interconnects 1366 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1369 1367 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1370 1368 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1371 interconnect- 1369 interconnect-names = "qup-core", "qup-config", "qup-memory";
1372 dmas = <&gpi_ 1370 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1373 <&gpi_ 1371 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1374 dma-names = " 1372 dma-names = "tx", "rx";
1375 #address-cell 1373 #address-cells = <1>;
1376 #size-cells = 1374 #size-cells = <0>;
1377 status = "dis 1375 status = "disabled";
1378 }; 1376 };
1379 1377
1380 1378
1381 i2c6: i2c@998000 { 1379 i2c6: i2c@998000 {
1382 compatible = 1380 compatible = "qcom,geni-i2c";
1383 reg = <0x0 0x 1381 reg = <0x0 0x00998000 0x0 0x4000>;
1384 clock-names = 1382 clock-names = "se";
1385 clocks = <&gc 1383 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1386 pinctrl-names 1384 pinctrl-names = "default";
1387 pinctrl-0 = < 1385 pinctrl-0 = <&qup_i2c6_data_clk>;
1388 interrupts = 1386 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1389 #address-cell 1387 #address-cells = <1>;
1390 #size-cells = 1388 #size-cells = <0>;
1391 interconnects 1389 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1392 1390 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1393 1391 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1394 interconnect- 1392 interconnect-names = "qup-core", "qup-config", "qup-memory";
1395 dmas = <&gpi_ 1393 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1396 <&gpi_ 1394 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1397 dma-names = " 1395 dma-names = "tx", "rx";
1398 status = "dis 1396 status = "disabled";
1399 }; 1397 };
1400 1398
1401 spi6: spi@998000 { 1399 spi6: spi@998000 {
1402 compatible = 1400 compatible = "qcom,geni-spi";
1403 reg = <0x0 0x 1401 reg = <0x0 0x00998000 0x0 0x4000>;
1404 clock-names = 1402 clock-names = "se";
1405 clocks = <&gc 1403 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1406 interrupts = 1404 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1407 pinctrl-names 1405 pinctrl-names = "default";
1408 pinctrl-0 = < 1406 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1409 interconnects 1407 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1410 1408 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1411 1409 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1412 interconnect- 1410 interconnect-names = "qup-core", "qup-config", "qup-memory";
1413 dmas = <&gpi_ 1411 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1414 <&gpi_ 1412 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1415 dma-names = " 1413 dma-names = "tx", "rx";
1416 #address-cell 1414 #address-cells = <1>;
1417 #size-cells = 1415 #size-cells = <0>;
1418 status = "dis 1416 status = "disabled";
1419 }; 1417 };
1420 1418
1421 uart7: serial@99c000 1419 uart7: serial@99c000 {
1422 compatible = 1420 compatible = "qcom,geni-debug-uart";
1423 reg = <0 0x00 1421 reg = <0 0x0099c000 0 0x4000>;
1424 clock-names = 1422 clock-names = "se";
1425 clocks = <&gc 1423 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1426 pinctrl-names 1424 pinctrl-names = "default";
1427 pinctrl-0 = < 1425 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>;
1428 interrupts = 1426 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1429 interconnects 1427 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1430 1428 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1431 1429 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1432 1430 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
1433 interconnect- 1431 interconnect-names = "qup-core",
1434 1432 "qup-config";
1435 status = "dis 1433 status = "disabled";
1436 }; 1434 };
1437 }; 1435 };
1438 1436
1439 gpi_dma1: dma-controller@a000 1437 gpi_dma1: dma-controller@a00000 {
1440 compatible = "qcom,sm 1438 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
1441 #dma-cells = <3>; 1439 #dma-cells = <3>;
1442 reg = <0 0x00a00000 0 1440 reg = <0 0x00a00000 0 0x60000>;
1443 interrupts = <GIC_SPI 1441 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1444 <GIC_SPI 1442 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1445 <GIC_SPI 1443 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1446 <GIC_SPI 1444 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1447 <GIC_SPI 1445 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1448 <GIC_SPI 1446 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1449 <GIC_SPI 1447 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1450 <GIC_SPI 1448 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1451 <GIC_SPI 1449 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1452 <GIC_SPI 1450 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1453 <GIC_SPI 1451 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1454 <GIC_SPI 1452 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
1455 dma-channels = <12>; 1453 dma-channels = <12>;
1456 dma-channel-mask = <0 1454 dma-channel-mask = <0x7e>;
1457 iommus = <&apps_smmu 1455 iommus = <&apps_smmu 0x56 0x0>;
1458 status = "disabled"; 1456 status = "disabled";
1459 }; 1457 };
1460 1458
1461 qupv3_id_1: geniqup@ac0000 { 1459 qupv3_id_1: geniqup@ac0000 {
1462 compatible = "qcom,ge 1460 compatible = "qcom,geni-se-qup";
1463 reg = <0x0 0x00ac0000 1461 reg = <0x0 0x00ac0000 0x0 0x6000>;
1464 clock-names = "m-ahb" 1462 clock-names = "m-ahb", "s-ahb";
1465 clocks = <&gcc GCC_QU 1463 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1466 <&gcc GCC_QU 1464 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1467 iommus = <&apps_smmu 1465 iommus = <&apps_smmu 0x43 0x0>;
1468 interconnects = <&clk 1466 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>;
1469 interconnect-names = 1467 interconnect-names = "qup-core";
1470 #address-cells = <2>; 1468 #address-cells = <2>;
1471 #size-cells = <2>; 1469 #size-cells = <2>;
1472 ranges; 1470 ranges;
1473 status = "disabled"; 1471 status = "disabled";
1474 1472
1475 i2c8: i2c@a80000 { 1473 i2c8: i2c@a80000 {
1476 compatible = 1474 compatible = "qcom,geni-i2c";
1477 reg = <0x0 0x 1475 reg = <0x0 0x00a80000 0x0 0x4000>;
1478 clock-names = 1476 clock-names = "se";
1479 clocks = <&gc 1477 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1480 pinctrl-names 1478 pinctrl-names = "default";
1481 pinctrl-0 = < 1479 pinctrl-0 = <&qup_i2c8_data_clk>;
1482 interrupts = 1480 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1483 #address-cell 1481 #address-cells = <1>;
1484 #size-cells = 1482 #size-cells = <0>;
1485 interconnects 1483 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1486 1484 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1487 1485 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1488 interconnect- 1486 interconnect-names = "qup-core", "qup-config", "qup-memory";
1489 dmas = <&gpi_ 1487 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1490 <&gpi_ 1488 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1491 dma-names = " 1489 dma-names = "tx", "rx";
1492 status = "dis 1490 status = "disabled";
1493 }; 1491 };
1494 1492
1495 spi8: spi@a80000 { 1493 spi8: spi@a80000 {
1496 compatible = 1494 compatible = "qcom,geni-spi";
1497 reg = <0x0 0x 1495 reg = <0x0 0x00a80000 0x0 0x4000>;
1498 clock-names = 1496 clock-names = "se";
1499 clocks = <&gc 1497 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1500 interrupts = 1498 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1501 pinctrl-names 1499 pinctrl-names = "default";
1502 pinctrl-0 = < 1500 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1503 interconnects 1501 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1504 1502 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1505 1503 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1506 interconnect- 1504 interconnect-names = "qup-core", "qup-config", "qup-memory";
1507 dmas = <&gpi_ 1505 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1508 <&gpi_ 1506 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1509 dma-names = " 1507 dma-names = "tx", "rx";
1510 #address-cell 1508 #address-cells = <1>;
1511 #size-cells = 1509 #size-cells = <0>;
1512 status = "dis 1510 status = "disabled";
1513 }; 1511 };
1514 1512
1515 i2c9: i2c@a84000 { 1513 i2c9: i2c@a84000 {
1516 compatible = 1514 compatible = "qcom,geni-i2c";
1517 reg = <0x0 0x 1515 reg = <0x0 0x00a84000 0x0 0x4000>;
1518 clock-names = 1516 clock-names = "se";
1519 clocks = <&gc 1517 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1520 pinctrl-names 1518 pinctrl-names = "default";
1521 pinctrl-0 = < 1519 pinctrl-0 = <&qup_i2c9_data_clk>;
1522 interrupts = 1520 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1523 #address-cell 1521 #address-cells = <1>;
1524 #size-cells = 1522 #size-cells = <0>;
1525 interconnects 1523 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1526 1524 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1527 1525 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1528 interconnect- 1526 interconnect-names = "qup-core", "qup-config", "qup-memory";
1529 dmas = <&gpi_ 1527 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1530 <&gpi_ 1528 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1531 dma-names = " 1529 dma-names = "tx", "rx";
1532 status = "dis 1530 status = "disabled";
1533 }; 1531 };
1534 1532
1535 spi9: spi@a84000 { 1533 spi9: spi@a84000 {
1536 compatible = 1534 compatible = "qcom,geni-spi";
1537 reg = <0x0 0x 1535 reg = <0x0 0x00a84000 0x0 0x4000>;
1538 clock-names = 1536 clock-names = "se";
1539 clocks = <&gc 1537 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1540 interrupts = 1538 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1541 pinctrl-names 1539 pinctrl-names = "default";
1542 pinctrl-0 = < 1540 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1543 interconnects 1541 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1544 1542 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1545 1543 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1546 interconnect- 1544 interconnect-names = "qup-core", "qup-config", "qup-memory";
1547 dmas = <&gpi_ 1545 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1548 <&gpi_ 1546 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1549 dma-names = " 1547 dma-names = "tx", "rx";
1550 #address-cell 1548 #address-cells = <1>;
1551 #size-cells = 1549 #size-cells = <0>;
1552 status = "dis 1550 status = "disabled";
1553 }; 1551 };
1554 1552
1555 i2c10: i2c@a88000 { 1553 i2c10: i2c@a88000 {
1556 compatible = 1554 compatible = "qcom,geni-i2c";
1557 reg = <0x0 0x 1555 reg = <0x0 0x00a88000 0x0 0x4000>;
1558 clock-names = 1556 clock-names = "se";
1559 clocks = <&gc 1557 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1560 pinctrl-names 1558 pinctrl-names = "default";
1561 pinctrl-0 = < 1559 pinctrl-0 = <&qup_i2c10_data_clk>;
1562 interrupts = 1560 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1563 #address-cell 1561 #address-cells = <1>;
1564 #size-cells = 1562 #size-cells = <0>;
1565 interconnects 1563 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1566 1564 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1567 1565 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1568 interconnect- 1566 interconnect-names = "qup-core", "qup-config", "qup-memory";
1569 dmas = <&gpi_ 1567 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1570 <&gpi_ 1568 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1571 dma-names = " 1569 dma-names = "tx", "rx";
1572 status = "dis 1570 status = "disabled";
1573 }; 1571 };
1574 1572
1575 spi10: spi@a88000 { 1573 spi10: spi@a88000 {
1576 compatible = 1574 compatible = "qcom,geni-spi";
1577 reg = <0x0 0x 1575 reg = <0x0 0x00a88000 0x0 0x4000>;
1578 clock-names = 1576 clock-names = "se";
1579 clocks = <&gc 1577 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1580 interrupts = 1578 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1581 pinctrl-names 1579 pinctrl-names = "default";
1582 pinctrl-0 = < 1580 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1583 interconnects 1581 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1584 1582 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1585 1583 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1586 interconnect- 1584 interconnect-names = "qup-core", "qup-config", "qup-memory";
1587 dmas = <&gpi_ 1585 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1588 <&gpi_ 1586 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1589 dma-names = " 1587 dma-names = "tx", "rx";
1590 #address-cell 1588 #address-cells = <1>;
1591 #size-cells = 1589 #size-cells = <0>;
1592 status = "dis 1590 status = "disabled";
1593 }; 1591 };
1594 1592
1595 i2c11: i2c@a8c000 { 1593 i2c11: i2c@a8c000 {
1596 compatible = 1594 compatible = "qcom,geni-i2c";
1597 reg = <0x0 0x 1595 reg = <0x0 0x00a8c000 0x0 0x4000>;
1598 clock-names = 1596 clock-names = "se";
1599 clocks = <&gc 1597 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1600 pinctrl-names 1598 pinctrl-names = "default";
1601 pinctrl-0 = < 1599 pinctrl-0 = <&qup_i2c11_data_clk>;
1602 interrupts = 1600 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1603 #address-cell 1601 #address-cells = <1>;
1604 #size-cells = 1602 #size-cells = <0>;
1605 interconnects 1603 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1606 1604 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1607 1605 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1608 interconnect- 1606 interconnect-names = "qup-core", "qup-config", "qup-memory";
1609 dmas = <&gpi_ 1607 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1610 <&gpi_ 1608 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1611 dma-names = " 1609 dma-names = "tx", "rx";
1612 status = "dis 1610 status = "disabled";
1613 }; 1611 };
1614 1612
1615 spi11: spi@a8c000 { 1613 spi11: spi@a8c000 {
1616 compatible = 1614 compatible = "qcom,geni-spi";
1617 reg = <0x0 0x 1615 reg = <0x0 0x00a8c000 0x0 0x4000>;
1618 clock-names = 1616 clock-names = "se";
1619 clocks = <&gc 1617 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1620 interrupts = 1618 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1621 pinctrl-names 1619 pinctrl-names = "default";
1622 pinctrl-0 = < 1620 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1623 interconnects 1621 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1624 1622 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1625 1623 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1626 interconnect- 1624 interconnect-names = "qup-core", "qup-config", "qup-memory";
1627 dmas = <&gpi_ 1625 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1628 <&gpi_ 1626 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1629 dma-names = " 1627 dma-names = "tx", "rx";
1630 #address-cell 1628 #address-cells = <1>;
1631 #size-cells = 1629 #size-cells = <0>;
1632 status = "dis 1630 status = "disabled";
1633 }; 1631 };
1634 1632
1635 i2c12: i2c@a90000 { 1633 i2c12: i2c@a90000 {
1636 compatible = 1634 compatible = "qcom,geni-i2c";
1637 reg = <0x0 0x 1635 reg = <0x0 0x00a90000 0x0 0x4000>;
1638 clock-names = 1636 clock-names = "se";
1639 clocks = <&gc 1637 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1640 pinctrl-names 1638 pinctrl-names = "default";
1641 pinctrl-0 = < 1639 pinctrl-0 = <&qup_i2c12_data_clk>;
1642 interrupts = 1640 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1643 #address-cell 1641 #address-cells = <1>;
1644 #size-cells = 1642 #size-cells = <0>;
1645 interconnects 1643 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1646 1644 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1647 1645 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1648 interconnect- 1646 interconnect-names = "qup-core", "qup-config", "qup-memory";
1649 dmas = <&gpi_ 1647 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1650 <&gpi_ 1648 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1651 dma-names = " 1649 dma-names = "tx", "rx";
1652 status = "dis 1650 status = "disabled";
1653 }; 1651 };
1654 1652
1655 spi12: spi@a90000 { 1653 spi12: spi@a90000 {
1656 compatible = 1654 compatible = "qcom,geni-spi";
1657 reg = <0x0 0x 1655 reg = <0x0 0x00a90000 0x0 0x4000>;
1658 clock-names = 1656 clock-names = "se";
1659 clocks = <&gc 1657 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1660 interrupts = 1658 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1661 pinctrl-names 1659 pinctrl-names = "default";
1662 pinctrl-0 = < 1660 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1663 interconnects 1661 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1664 1662 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1665 1663 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1666 interconnect- 1664 interconnect-names = "qup-core", "qup-config", "qup-memory";
1667 dmas = <&gpi_ 1665 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1668 <&gpi_ 1666 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1669 dma-names = " 1667 dma-names = "tx", "rx";
1670 #address-cell 1668 #address-cells = <1>;
1671 #size-cells = 1669 #size-cells = <0>;
1672 status = "dis 1670 status = "disabled";
1673 }; 1671 };
1674 1672
1675 i2c13: i2c@a94000 { 1673 i2c13: i2c@a94000 {
1676 compatible = 1674 compatible = "qcom,geni-i2c";
1677 reg = <0 0x00 1675 reg = <0 0x00a94000 0 0x4000>;
1678 clock-names = 1676 clock-names = "se";
1679 clocks = <&gc 1677 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1680 pinctrl-names 1678 pinctrl-names = "default";
1681 pinctrl-0 = < 1679 pinctrl-0 = <&qup_i2c13_data_clk>;
1682 interrupts = 1680 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1683 interconnects 1681 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1684 1682 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1685 1683 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1686 interconnect- 1684 interconnect-names = "qup-core", "qup-config", "qup-memory";
1687 dmas = <&gpi_ 1685 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1688 <&gpi_ 1686 <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1689 dma-names = " 1687 dma-names = "tx", "rx";
1690 #address-cell 1688 #address-cells = <1>;
1691 #size-cells = 1689 #size-cells = <0>;
1692 status = "dis 1690 status = "disabled";
1693 }; 1691 };
1694 1692
1695 spi13: spi@a94000 { 1693 spi13: spi@a94000 {
1696 compatible = 1694 compatible = "qcom,geni-spi";
1697 reg = <0x0 0x 1695 reg = <0x0 0x00a94000 0x0 0x4000>;
1698 clock-names = 1696 clock-names = "se";
1699 clocks = <&gc 1697 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1700 interrupts = 1698 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1701 pinctrl-names 1699 pinctrl-names = "default";
1702 pinctrl-0 = < 1700 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1703 interconnects 1701 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1704 1702 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1705 1703 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1706 interconnect- 1704 interconnect-names = "qup-core", "qup-config", "qup-memory";
1707 dmas = <&gpi_ 1705 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1708 <&gpi_ 1706 <&gpi_dma1 1 5 QCOM_GPI_SPI>;
1709 dma-names = " 1707 dma-names = "tx", "rx";
1710 #address-cell 1708 #address-cells = <1>;
1711 #size-cells = 1709 #size-cells = <0>;
1712 status = "dis 1710 status = "disabled";
1713 }; 1711 };
1714 1712
1715 i2c14: i2c@a98000 { 1713 i2c14: i2c@a98000 {
1716 compatible = 1714 compatible = "qcom,geni-i2c";
1717 reg = <0 0x00 1715 reg = <0 0x00a98000 0 0x4000>;
1718 clock-names = 1716 clock-names = "se";
1719 clocks = <&gc 1717 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1720 pinctrl-names 1718 pinctrl-names = "default";
1721 pinctrl-0 = < 1719 pinctrl-0 = <&qup_i2c14_data_clk>;
1722 interrupts = 1720 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
1723 interconnects 1721 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1724 1722 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1725 1723 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1726 interconnect- 1724 interconnect-names = "qup-core", "qup-config", "qup-memory";
1727 dmas = <&gpi_ 1725 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
1728 <&gpi_ 1726 <&gpi_dma1 1 6 QCOM_GPI_I2C>;
1729 dma-names = " 1727 dma-names = "tx", "rx";
1730 #address-cell 1728 #address-cells = <1>;
1731 #size-cells = 1729 #size-cells = <0>;
1732 status = "dis 1730 status = "disabled";
1733 }; 1731 };
1734 1732
1735 spi14: spi@a98000 { 1733 spi14: spi@a98000 {
1736 compatible = 1734 compatible = "qcom,geni-spi";
1737 reg = <0x0 0x 1735 reg = <0x0 0x00a98000 0x0 0x4000>;
1738 clock-names = 1736 clock-names = "se";
1739 clocks = <&gc 1737 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1740 interrupts = 1738 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
1741 pinctrl-names 1739 pinctrl-names = "default";
1742 pinctrl-0 = < 1740 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
1743 interconnects 1741 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1744 1742 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1745 1743 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1746 interconnect- 1744 interconnect-names = "qup-core", "qup-config", "qup-memory";
1747 dmas = <&gpi_ 1745 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
1748 <&gpi_ 1746 <&gpi_dma1 1 6 QCOM_GPI_SPI>;
1749 dma-names = " 1747 dma-names = "tx", "rx";
1750 #address-cell 1748 #address-cells = <1>;
1751 #size-cells = 1749 #size-cells = <0>;
1752 status = "dis 1750 status = "disabled";
1753 }; 1751 };
1754 }; 1752 };
1755 1753
1756 rng: rng@10c3000 { !! 1754 pcie0: pci@1c00000 {
1757 compatible = "qcom,sm <<
1758 reg = <0 0x010c3000 0 <<
1759 }; <<
1760 <<
1761 pcie0: pcie@1c00000 { <<
1762 compatible = "qcom,pc 1755 compatible = "qcom,pcie-sm8450-pcie0";
1763 reg = <0 0x01c00000 0 1756 reg = <0 0x01c00000 0 0x3000>,
1764 <0 0x60000000 0 1757 <0 0x60000000 0 0xf1d>,
1765 <0 0x60000f20 0 1758 <0 0x60000f20 0 0xa8>,
1766 <0 0x60001000 0 1759 <0 0x60001000 0 0x1000>,
1767 <0 0x60100000 0 1760 <0 0x60100000 0 0x100000>;
1768 reg-names = "parf", " 1761 reg-names = "parf", "dbi", "elbi", "atu", "config";
1769 device_type = "pci"; 1762 device_type = "pci";
1770 linux,pci-domain = <0 1763 linux,pci-domain = <0>;
1771 bus-range = <0x00 0xf 1764 bus-range = <0x00 0xff>;
1772 num-lanes = <1>; 1765 num-lanes = <1>;
1773 1766
1774 #address-cells = <3>; 1767 #address-cells = <3>;
1775 #size-cells = <2>; 1768 #size-cells = <2>;
1776 1769
1777 ranges = <0x01000000 1770 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
1778 <0x02000000 1771 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1779 1772
1780 msi-map = <0x0 &gic_i !! 1773 /*
1781 <0x100 &gic !! 1774 * MSIs for BDF (1:0.0) only works with Device ID 0x5980.
>> 1775 * Hence, the IDs are swapped.
>> 1776 */
>> 1777 msi-map = <0x0 &gic_its 0x5981 0x1>,
>> 1778 <0x100 &gic_its 0x5980 0x1>;
1782 msi-map-mask = <0xff0 1779 msi-map-mask = <0xff00>;
1783 interrupts = <GIC_SPI !! 1780 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
1784 <GIC_SPI !! 1781 interrupt-names = "msi";
1785 <GIC_SPI <<
1786 <GIC_SPI <<
1787 <GIC_SPI <<
1788 <GIC_SPI <<
1789 <GIC_SPI <<
1790 <GIC_SPI <<
1791 interrupt-names = "ms <<
1792 "ms <<
1793 "ms <<
1794 "ms <<
1795 "ms <<
1796 "ms <<
1797 "ms <<
1798 "ms <<
1799 #interrupt-cells = <1 1782 #interrupt-cells = <1>;
1800 interrupt-map-mask = 1783 interrupt-map-mask = <0 0 0 0x7>;
1801 interrupt-map = <0 0 1784 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1802 <0 0 1785 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1803 <0 0 1786 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1804 <0 0 1787 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1805 1788
1806 interconnects = <&pci <<
1807 &mc_ <<
1808 <&gem <<
1809 &con <<
1810 interconnect-names = <<
1811 <<
1812 clocks = <&gcc GCC_PC 1789 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1813 <&gcc GCC_PC 1790 <&gcc GCC_PCIE_0_PIPE_CLK_SRC>,
1814 <&pcie0_phy> 1791 <&pcie0_phy>,
1815 <&rpmhcc RPM 1792 <&rpmhcc RPMH_CXO_CLK>,
1816 <&gcc GCC_PC 1793 <&gcc GCC_PCIE_0_AUX_CLK>,
1817 <&gcc GCC_PC 1794 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1818 <&gcc GCC_PC 1795 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1819 <&gcc GCC_PC 1796 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1820 <&gcc GCC_PC 1797 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
1821 <&gcc GCC_DD 1798 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1822 <&gcc GCC_AG 1799 <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
1823 <&gcc GCC_AG 1800 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
1824 clock-names = "pipe", 1801 clock-names = "pipe",
1825 "pipe_m 1802 "pipe_mux",
1826 "phy_pi 1803 "phy_pipe",
1827 "ref", 1804 "ref",
1828 "aux", 1805 "aux",
1829 "cfg", 1806 "cfg",
1830 "bus_ma 1807 "bus_master",
1831 "bus_sl 1808 "bus_slave",
1832 "slave_ 1809 "slave_q2a",
1833 "ddrss_ 1810 "ddrss_sf_tbu",
1834 "aggre0 1811 "aggre0",
1835 "aggre1 1812 "aggre1";
1836 1813
1837 iommu-map = <0x0 &a 1814 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
1838 <0x100 &a 1815 <0x100 &apps_smmu 0x1c01 0x1>;
1839 1816
1840 resets = <&gcc GCC_PC 1817 resets = <&gcc GCC_PCIE_0_BCR>;
1841 reset-names = "pci"; 1818 reset-names = "pci";
1842 1819
1843 power-domains = <&gcc 1820 power-domains = <&gcc PCIE_0_GDSC>;
1844 1821
1845 phys = <&pcie0_phy>; 1822 phys = <&pcie0_phy>;
1846 phy-names = "pciephy" 1823 phy-names = "pciephy";
1847 1824
1848 perst-gpios = <&tlmm 1825 perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
1849 wake-gpios = <&tlmm 9 1826 wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
1850 1827
1851 pinctrl-names = "defa 1828 pinctrl-names = "default";
1852 pinctrl-0 = <&pcie0_d 1829 pinctrl-0 = <&pcie0_default_state>;
1853 1830
1854 operating-points-v2 = <<
1855 <<
1856 status = "disabled"; 1831 status = "disabled";
1857 <<
1858 pcie0_opp_table: opp- <<
1859 compatible = <<
1860 <<
1861 /* GEN 1 x1 * <<
1862 opp-2500000 { <<
1863 opp-h <<
1864 requi <<
1865 opp-p <<
1866 }; <<
1867 <<
1868 /* GEN 2 x1 * <<
1869 opp-5000000 { <<
1870 opp-h <<
1871 requi <<
1872 opp-p <<
1873 }; <<
1874 <<
1875 /* GEN 3 x1 * <<
1876 opp-8000000 { <<
1877 opp-h <<
1878 requi <<
1879 opp-p <<
1880 }; <<
1881 }; <<
1882 <<
1883 pcie@0 { <<
1884 device_type = <<
1885 reg = <0x0 0x <<
1886 bus-range = < <<
1887 <<
1888 #address-cell <<
1889 #size-cells = <<
1890 ranges; <<
1891 }; <<
1892 }; 1832 };
1893 1833
1894 pcie0_phy: phy@1c06000 { 1834 pcie0_phy: phy@1c06000 {
1895 compatible = "qcom,sm 1835 compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy";
1896 reg = <0 0x01c06000 0 1836 reg = <0 0x01c06000 0 0x2000>;
1897 1837
1898 clocks = <&gcc GCC_PC 1838 clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
1899 <&gcc GCC_PC 1839 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1900 <&gcc GCC_PC 1840 <&gcc GCC_PCIE_0_CLKREF_EN>,
1901 <&gcc GCC_PC 1841 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
1902 <&gcc GCC_PC 1842 <&gcc GCC_PCIE_0_PIPE_CLK>;
1903 clock-names = "aux", 1843 clock-names = "aux",
1904 "cfg_ah 1844 "cfg_ahb",
1905 "ref", 1845 "ref",
1906 "rchng" 1846 "rchng",
1907 "pipe"; 1847 "pipe";
1908 1848
1909 clock-output-names = 1849 clock-output-names = "pcie_0_pipe_clk";
1910 #clock-cells = <0>; 1850 #clock-cells = <0>;
1911 1851
1912 #phy-cells = <0>; 1852 #phy-cells = <0>;
1913 1853
1914 resets = <&gcc GCC_PC 1854 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1915 reset-names = "phy"; 1855 reset-names = "phy";
1916 1856
1917 assigned-clocks = <&g 1857 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
1918 assigned-clock-rates 1858 assigned-clock-rates = <100000000>;
1919 1859
1920 status = "disabled"; 1860 status = "disabled";
1921 }; 1861 };
1922 1862
1923 pcie1: pcie@1c08000 { !! 1863 pcie1: pci@1c08000 {
1924 compatible = "qcom,pc 1864 compatible = "qcom,pcie-sm8450-pcie1";
1925 reg = <0 0x01c08000 0 1865 reg = <0 0x01c08000 0 0x3000>,
1926 <0 0x40000000 0 1866 <0 0x40000000 0 0xf1d>,
1927 <0 0x40000f20 0 1867 <0 0x40000f20 0 0xa8>,
1928 <0 0x40001000 0 1868 <0 0x40001000 0 0x1000>,
1929 <0 0x40100000 0 1869 <0 0x40100000 0 0x100000>;
1930 reg-names = "parf", " 1870 reg-names = "parf", "dbi", "elbi", "atu", "config";
1931 device_type = "pci"; 1871 device_type = "pci";
1932 linux,pci-domain = <1 1872 linux,pci-domain = <1>;
1933 bus-range = <0x00 0xf 1873 bus-range = <0x00 0xff>;
1934 num-lanes = <2>; 1874 num-lanes = <2>;
1935 1875
1936 #address-cells = <3>; 1876 #address-cells = <3>;
1937 #size-cells = <2>; 1877 #size-cells = <2>;
1938 1878
1939 ranges = <0x01000000 1879 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
1940 <0x02000000 1880 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1941 1881
1942 msi-map = <0x0 &gic_i !! 1882 /*
1943 <0x100 &gic !! 1883 * MSIs for BDF (1:0.0) only works with Device ID 0x5a00.
>> 1884 * Hence, the IDs are swapped.
>> 1885 */
>> 1886 msi-map = <0x0 &gic_its 0x5a01 0x1>,
>> 1887 <0x100 &gic_its 0x5a00 0x1>;
1944 msi-map-mask = <0xff0 1888 msi-map-mask = <0xff00>;
1945 interrupts = <GIC_SPI !! 1889 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
1946 <GIC_SPI !! 1890 interrupt-names = "msi";
1947 <GIC_SPI <<
1948 <GIC_SPI <<
1949 <GIC_SPI <<
1950 <GIC_SPI <<
1951 <GIC_SPI <<
1952 <GIC_SPI <<
1953 interrupt-names = "ms <<
1954 "ms <<
1955 "ms <<
1956 "ms <<
1957 "ms <<
1958 "ms <<
1959 "ms <<
1960 "ms <<
1961 #interrupt-cells = <1 1891 #interrupt-cells = <1>;
1962 interrupt-map-mask = 1892 interrupt-map-mask = <0 0 0 0x7>;
1963 interrupt-map = <0 0 1893 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1964 <0 0 1894 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1965 <0 0 1895 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1966 <0 0 1896 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1967 1897
1968 interconnects = <&pci <<
1969 &mc_ <<
1970 <&gem <<
1971 &con <<
1972 interconnect-names = <<
1973 <<
1974 clocks = <&gcc GCC_PC 1898 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1975 <&gcc GCC_PC 1899 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>,
1976 <&pcie1_phy !! 1900 <&pcie1_phy>,
1977 <&rpmhcc RPM 1901 <&rpmhcc RPMH_CXO_CLK>,
1978 <&gcc GCC_PC 1902 <&gcc GCC_PCIE_1_AUX_CLK>,
1979 <&gcc GCC_PC 1903 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1980 <&gcc GCC_PC 1904 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1981 <&gcc GCC_PC 1905 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
1982 <&gcc GCC_PC 1906 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
1983 <&gcc GCC_DD 1907 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1984 <&gcc GCC_AG 1908 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
1985 clock-names = "pipe", 1909 clock-names = "pipe",
1986 "pipe_m 1910 "pipe_mux",
1987 "phy_pi 1911 "phy_pipe",
1988 "ref", 1912 "ref",
1989 "aux", 1913 "aux",
1990 "cfg", 1914 "cfg",
1991 "bus_ma 1915 "bus_master",
1992 "bus_sl 1916 "bus_slave",
1993 "slave_ 1917 "slave_q2a",
1994 "ddrss_ 1918 "ddrss_sf_tbu",
1995 "aggre1 1919 "aggre1";
1996 1920
1997 iommu-map = <0x0 &a 1921 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
1998 <0x100 &a 1922 <0x100 &apps_smmu 0x1c81 0x1>;
1999 1923
2000 resets = <&gcc GCC_PC 1924 resets = <&gcc GCC_PCIE_1_BCR>;
2001 reset-names = "pci"; 1925 reset-names = "pci";
2002 1926
2003 power-domains = <&gcc 1927 power-domains = <&gcc PCIE_1_GDSC>;
2004 1928
2005 phys = <&pcie1_phy>; 1929 phys = <&pcie1_phy>;
2006 phy-names = "pciephy" 1930 phy-names = "pciephy";
2007 1931
2008 perst-gpios = <&tlmm 1932 perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
2009 wake-gpios = <&tlmm 9 1933 wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
2010 1934
2011 pinctrl-names = "defa 1935 pinctrl-names = "default";
2012 pinctrl-0 = <&pcie1_d 1936 pinctrl-0 = <&pcie1_default_state>;
2013 1937
2014 operating-points-v2 = <<
2015 <<
2016 status = "disabled"; 1938 status = "disabled";
2017 <<
2018 pcie1_opp_table: opp- <<
2019 compatible = <<
2020 <<
2021 /* GEN 1 x1 * <<
2022 opp-2500000 { <<
2023 opp-h <<
2024 requi <<
2025 opp-p <<
2026 }; <<
2027 <<
2028 /* GEN 1 x2 a <<
2029 opp-5000000 { <<
2030 opp-h <<
2031 requi <<
2032 opp-p <<
2033 }; <<
2034 <<
2035 /* GEN 2 x2 * <<
2036 opp-10000000 <<
2037 opp-h <<
2038 requi <<
2039 opp-p <<
2040 }; <<
2041 <<
2042 /* GEN 3 x1 * <<
2043 opp-8000000 { <<
2044 opp-h <<
2045 requi <<
2046 opp-p <<
2047 }; <<
2048 <<
2049 /* GEN 3 x2 a <<
2050 opp-16000000 <<
2051 opp-h <<
2052 requi <<
2053 opp-p <<
2054 }; <<
2055 <<
2056 /* GEN 4 x2 * <<
2057 opp-32000000 <<
2058 opp-h <<
2059 requi <<
2060 opp-p <<
2061 }; <<
2062 }; <<
2063 <<
2064 pcie@0 { <<
2065 device_type = <<
2066 reg = <0x0 0x <<
2067 bus-range = < <<
2068 <<
2069 #address-cell <<
2070 #size-cells = <<
2071 ranges; <<
2072 }; <<
2073 }; 1939 };
2074 1940
2075 pcie1_phy: phy@1c0e000 { 1941 pcie1_phy: phy@1c0e000 {
2076 compatible = "qcom,sm 1942 compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy";
2077 reg = <0 0x01c0e000 0 1943 reg = <0 0x01c0e000 0 0x2000>;
2078 1944
2079 clocks = <&gcc GCC_PC 1945 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>,
2080 <&gcc GCC_PC 1946 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2081 <&gcc GCC_PC 1947 <&gcc GCC_PCIE_1_CLKREF_EN>,
2082 <&gcc GCC_PC 1948 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
2083 <&gcc GCC_PC 1949 <&gcc GCC_PCIE_1_PIPE_CLK>;
2084 clock-names = "aux", 1950 clock-names = "aux",
2085 "cfg_ah 1951 "cfg_ahb",
2086 "ref", 1952 "ref",
2087 "rchng" 1953 "rchng",
2088 "pipe"; 1954 "pipe";
2089 1955
2090 clock-output-names = 1956 clock-output-names = "pcie_1_pipe_clk";
2091 #clock-cells = <1>; !! 1957 #clock-cells = <0>;
2092 1958
2093 #phy-cells = <0>; 1959 #phy-cells = <0>;
2094 1960
2095 resets = <&gcc GCC_PC 1961 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2096 reset-names = "phy"; 1962 reset-names = "phy";
2097 1963
2098 assigned-clocks = <&g 1964 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
2099 assigned-clock-rates 1965 assigned-clock-rates = <100000000>;
2100 1966
2101 status = "disabled"; 1967 status = "disabled";
2102 }; 1968 };
2103 1969
2104 config_noc: interconnect@1500 1970 config_noc: interconnect@1500000 {
2105 compatible = "qcom,sm 1971 compatible = "qcom,sm8450-config-noc";
2106 reg = <0 0x01500000 0 1972 reg = <0 0x01500000 0 0x1c000>;
2107 #interconnect-cells = 1973 #interconnect-cells = <2>;
2108 qcom,bcm-voters = <&a 1974 qcom,bcm-voters = <&apps_bcm_voter>;
2109 }; 1975 };
2110 1976
2111 system_noc: interconnect@1680 1977 system_noc: interconnect@1680000 {
2112 compatible = "qcom,sm 1978 compatible = "qcom,sm8450-system-noc";
2113 reg = <0 0x01680000 0 1979 reg = <0 0x01680000 0 0x1e200>;
2114 #interconnect-cells = 1980 #interconnect-cells = <2>;
2115 qcom,bcm-voters = <&a 1981 qcom,bcm-voters = <&apps_bcm_voter>;
2116 }; 1982 };
2117 1983
2118 pcie_noc: interconnect@16c000 1984 pcie_noc: interconnect@16c0000 {
2119 compatible = "qcom,sm 1985 compatible = "qcom,sm8450-pcie-anoc";
2120 reg = <0 0x016c0000 0 1986 reg = <0 0x016c0000 0 0xe280>;
2121 #interconnect-cells = 1987 #interconnect-cells = <2>;
2122 qcom,bcm-voters = <&a 1988 qcom,bcm-voters = <&apps_bcm_voter>;
2123 }; 1989 };
2124 1990
2125 aggre1_noc: interconnect@16e0 1991 aggre1_noc: interconnect@16e0000 {
2126 compatible = "qcom,sm 1992 compatible = "qcom,sm8450-aggre1-noc";
2127 reg = <0 0x016e0000 0 1993 reg = <0 0x016e0000 0 0x1c080>;
2128 #interconnect-cells = 1994 #interconnect-cells = <2>;
2129 clocks = <&gcc GCC_AG 1995 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2130 <&gcc GCC_AG 1996 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
2131 qcom,bcm-voters = <&a 1997 qcom,bcm-voters = <&apps_bcm_voter>;
2132 }; 1998 };
2133 1999
2134 aggre2_noc: interconnect@1700 2000 aggre2_noc: interconnect@1700000 {
2135 compatible = "qcom,sm 2001 compatible = "qcom,sm8450-aggre2-noc";
2136 reg = <0 0x01700000 0 2002 reg = <0 0x01700000 0 0x31080>;
2137 #interconnect-cells = 2003 #interconnect-cells = <2>;
2138 qcom,bcm-voters = <&a 2004 qcom,bcm-voters = <&apps_bcm_voter>;
2139 clocks = <&gcc GCC_AG 2005 clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
2140 <&gcc GCC_AG 2006 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
2141 <&gcc GCC_AG 2007 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2142 <&rpmhcc RPM 2008 <&rpmhcc RPMH_IPA_CLK>;
2143 }; 2009 };
2144 2010
2145 mmss_noc: interconnect@174000 2011 mmss_noc: interconnect@1740000 {
2146 compatible = "qcom,sm 2012 compatible = "qcom,sm8450-mmss-noc";
2147 reg = <0 0x01740000 0 2013 reg = <0 0x01740000 0 0x1f080>;
2148 #interconnect-cells = 2014 #interconnect-cells = <2>;
2149 qcom,bcm-voters = <&a 2015 qcom,bcm-voters = <&apps_bcm_voter>;
2150 }; 2016 };
2151 2017
2152 tcsr_mutex: hwlock@1f40000 { 2018 tcsr_mutex: hwlock@1f40000 {
2153 compatible = "qcom,tc 2019 compatible = "qcom,tcsr-mutex";
2154 reg = <0x0 0x01f40000 2020 reg = <0x0 0x01f40000 0x0 0x40000>;
2155 #hwlock-cells = <1>; 2021 #hwlock-cells = <1>;
2156 }; 2022 };
2157 2023
2158 tcsr: syscon@1fc0000 { 2024 tcsr: syscon@1fc0000 {
2159 compatible = "qcom,sm 2025 compatible = "qcom,sm8450-tcsr", "syscon";
2160 reg = <0x0 0x1fc0000 2026 reg = <0x0 0x1fc0000 0x0 0x30000>;
2161 }; 2027 };
2162 2028
2163 gpu: gpu@3d00000 { <<
2164 compatible = "qcom,ad <<
2165 reg = <0x0 0x03d00000 <<
2166 <0x0 0x03d9e000 <<
2167 <0x0 0x03d61000 <<
2168 reg-names = "kgsl_3d0 <<
2169 "cx_mem", <<
2170 "cx_dbgc" <<
2171 <<
2172 interrupts = <GIC_SPI <<
2173 <<
2174 iommus = <&adreno_smm <<
2175 <&adreno_smm <<
2176 <<
2177 operating-points-v2 = <<
2178 <<
2179 qcom,gmu = <&gmu>; <<
2180 #cooling-cells = <2>; <<
2181 <<
2182 status = "disabled"; <<
2183 <<
2184 zap-shader { <<
2185 memory-region <<
2186 }; <<
2187 <<
2188 gpu_opp_table: opp-ta <<
2189 compatible = <<
2190 <<
2191 opp-818000000 <<
2192 opp-h <<
2193 opp-l <<
2194 }; <<
2195 <<
2196 opp-791000000 <<
2197 opp-h <<
2198 opp-l <<
2199 }; <<
2200 <<
2201 opp-734000000 <<
2202 opp-h <<
2203 opp-l <<
2204 }; <<
2205 <<
2206 opp-640000000 <<
2207 opp-h <<
2208 opp-l <<
2209 }; <<
2210 <<
2211 opp-599000000 <<
2212 opp-h <<
2213 opp-l <<
2214 }; <<
2215 <<
2216 opp-545000000 <<
2217 opp-h <<
2218 opp-l <<
2219 }; <<
2220 <<
2221 opp-492000000 <<
2222 opp-h <<
2223 opp-l <<
2224 }; <<
2225 <<
2226 opp-421000000 <<
2227 opp-h <<
2228 opp-l <<
2229 }; <<
2230 <<
2231 opp-350000000 <<
2232 opp-h <<
2233 opp-l <<
2234 }; <<
2235 <<
2236 opp-317000000 <<
2237 opp-h <<
2238 opp-l <<
2239 }; <<
2240 <<
2241 opp-285000000 <<
2242 opp-h <<
2243 opp-l <<
2244 }; <<
2245 <<
2246 opp-220000000 <<
2247 opp-h <<
2248 opp-l <<
2249 }; <<
2250 }; <<
2251 }; <<
2252 <<
2253 gmu: gmu@3d6a000 { <<
2254 compatible = "qcom,ad <<
2255 reg = <0x0 0x03d6a000 <<
2256 <0x0 0x03d50000 <<
2257 <0x0 0x0b290000 <<
2258 reg-names = "gmu", "r <<
2259 <<
2260 interrupts = <GIC_SPI <<
2261 <GIC_SPI <<
2262 interrupt-names = "hf <<
2263 <<
2264 clocks = <&gpucc GPU_ <<
2265 <&gpucc GPU_ <<
2266 <&gpucc GPU_ <<
2267 <&gcc GCC_DD <<
2268 <&gcc GCC_GP <<
2269 <&gpucc GPU_ <<
2270 <&gpucc GPU_ <<
2271 clock-names = "ahb", <<
2272 "gmu", <<
2273 "cxo", <<
2274 "axi", <<
2275 "memnoc <<
2276 "hub", <<
2277 "demet" <<
2278 <<
2279 power-domains = <&gpu <<
2280 <&gpu <<
2281 power-domain-names = <<
2282 <<
2283 <<
2284 iommus = <&adreno_smm <<
2285 <<
2286 qcom,qmp = <&aoss_qmp <<
2287 <<
2288 operating-points-v2 = <<
2289 <<
2290 gmu_opp_table: opp-ta <<
2291 compatible = <<
2292 <<
2293 opp-500000000 <<
2294 opp-h <<
2295 opp-l <<
2296 }; <<
2297 <<
2298 opp-200000000 <<
2299 opp-h <<
2300 opp-l <<
2301 }; <<
2302 }; <<
2303 }; <<
2304 <<
2305 gpucc: clock-controller@3d900 <<
2306 compatible = "qcom,sm <<
2307 reg = <0x0 0x03d90000 <<
2308 clocks = <&rpmhcc RPM <<
2309 <&gcc GCC_GP <<
2310 <&gcc GCC_GP <<
2311 #clock-cells = <1>; <<
2312 #reset-cells = <1>; <<
2313 #power-domain-cells = <<
2314 }; <<
2315 <<
2316 adreno_smmu: iommu@3da0000 { <<
2317 compatible = "qcom,sm <<
2318 "qcom,sm <<
2319 reg = <0x0 0x03da0000 <<
2320 #iommu-cells = <2>; <<
2321 #global-interrupts = <<
2322 interrupts = <GIC_SPI <<
2323 <GIC_SPI <<
2324 <GIC_SPI <<
2325 <GIC_SPI <<
2326 <GIC_SPI <<
2327 <GIC_SPI <<
2328 <GIC_SPI <<
2329 <GIC_SPI <<
2330 <GIC_SPI <<
2331 <GIC_SPI <<
2332 <GIC_SPI <<
2333 <GIC_SPI <<
2334 <GIC_SPI <<
2335 <GIC_SPI <<
2336 <GIC_SPI <<
2337 <GIC_SPI <<
2338 <GIC_SPI <<
2339 <GIC_SPI <<
2340 <GIC_SPI <<
2341 <GIC_SPI <<
2342 <GIC_SPI <<
2343 <GIC_SPI <<
2344 <GIC_SPI <<
2345 <GIC_SPI <<
2346 <GIC_SPI <<
2347 <GIC_SPI <<
2348 clocks = <&gpucc GPU_ <<
2349 <&gpucc GPU_ <<
2350 <&gpucc GPU_ <<
2351 <&gcc GCC_GP <<
2352 <&gcc GCC_GP <<
2353 <&gpucc GPU_ <<
2354 clock-names = "gmu", <<
2355 "hub", <<
2356 "hlos", <<
2357 "bus", <<
2358 "iface" <<
2359 "ahb"; <<
2360 power-domains = <&gpu <<
2361 dma-coherent; <<
2362 }; <<
2363 <<
2364 usb_1_hsphy: phy@88e3000 { 2029 usb_1_hsphy: phy@88e3000 {
2365 compatible = "qcom,sm 2030 compatible = "qcom,sm8450-usb-hs-phy",
2366 "qcom,us 2031 "qcom,usb-snps-hs-7nm-phy";
2367 reg = <0 0x088e3000 0 2032 reg = <0 0x088e3000 0 0x400>;
2368 status = "disabled"; 2033 status = "disabled";
2369 #phy-cells = <0>; 2034 #phy-cells = <0>;
2370 2035
2371 clocks = <&rpmhcc RPM 2036 clocks = <&rpmhcc RPMH_CXO_CLK>;
2372 clock-names = "ref"; 2037 clock-names = "ref";
2373 2038
2374 resets = <&gcc GCC_QU 2039 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2375 }; 2040 };
2376 2041
2377 usb_1_qmpphy: phy@88e8000 { 2042 usb_1_qmpphy: phy@88e8000 {
2378 compatible = "qcom,sm 2043 compatible = "qcom,sm8450-qmp-usb3-dp-phy";
2379 reg = <0 0x088e8000 0 2044 reg = <0 0x088e8000 0 0x3000>;
2380 2045
2381 clocks = <&gcc GCC_US 2046 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2382 <&rpmhcc RPM 2047 <&rpmhcc RPMH_CXO_CLK>,
2383 <&gcc GCC_US 2048 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
2384 <&gcc GCC_US 2049 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2385 clock-names = "aux", 2050 clock-names = "aux", "ref", "com_aux", "usb3_pipe";
2386 2051
2387 resets = <&gcc GCC_US 2052 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
2388 <&gcc GCC_US 2053 <&gcc GCC_USB3_PHY_PRIM_BCR>;
2389 reset-names = "phy", 2054 reset-names = "phy", "common";
2390 2055
2391 #clock-cells = <1>; 2056 #clock-cells = <1>;
2392 #phy-cells = <1>; 2057 #phy-cells = <1>;
2393 2058
2394 orientation-switch; <<
2395 <<
2396 status = "disabled"; 2059 status = "disabled";
2397 2060
2398 ports { 2061 ports {
2399 #address-cell 2062 #address-cells = <1>;
2400 #size-cells = 2063 #size-cells = <0>;
2401 2064
2402 port@0 { 2065 port@0 {
2403 reg = 2066 reg = <0>;
2404 2067
2405 usb_1 2068 usb_1_qmpphy_out: endpoint {
2406 }; 2069 };
2407 }; 2070 };
2408 2071
2409 port@1 { 2072 port@1 {
2410 reg = 2073 reg = <1>;
2411 2074
2412 usb_1 2075 usb_1_qmpphy_usb_ss_in: endpoint {
2413 <<
2414 }; 2076 };
2415 }; 2077 };
2416 2078
2417 port@2 { 2079 port@2 {
2418 reg = 2080 reg = <2>;
2419 2081
2420 usb_1 2082 usb_1_qmpphy_dp_in: endpoint {
2421 <<
2422 }; 2083 };
2423 }; 2084 };
2424 }; 2085 };
2425 }; 2086 };
2426 2087
2427 remoteproc_slpi: remoteproc@2 2088 remoteproc_slpi: remoteproc@2400000 {
2428 compatible = "qcom,sm 2089 compatible = "qcom,sm8450-slpi-pas";
2429 reg = <0 0x02400000 0 2090 reg = <0 0x02400000 0 0x4000>;
2430 2091
2431 interrupts-extended = 2092 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>,
2432 2093 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
2433 2094 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
2434 2095 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
2435 2096 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
2436 interrupt-names = "wd 2097 interrupt-names = "wdog", "fatal", "ready",
2437 "ha 2098 "handover", "stop-ack";
2438 2099
2439 clocks = <&rpmhcc RPM 2100 clocks = <&rpmhcc RPMH_CXO_CLK>;
2440 clock-names = "xo"; 2101 clock-names = "xo";
2441 2102
2442 power-domains = <&rpm 2103 power-domains = <&rpmhpd RPMHPD_LCX>,
2443 <&rpm 2104 <&rpmhpd RPMHPD_LMX>;
2444 power-domain-names = 2105 power-domain-names = "lcx", "lmx";
2445 2106
2446 memory-region = <&slp 2107 memory-region = <&slpi_mem>;
2447 2108
2448 qcom,qmp = <&aoss_qmp 2109 qcom,qmp = <&aoss_qmp>;
2449 2110
2450 qcom,smem-states = <& 2111 qcom,smem-states = <&smp2p_slpi_out 0>;
2451 qcom,smem-state-names 2112 qcom,smem-state-names = "stop";
2452 2113
2453 status = "disabled"; 2114 status = "disabled";
2454 2115
2455 glink-edge { 2116 glink-edge {
2456 interrupts-ex 2117 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
2457 2118 IPCC_MPROC_SIGNAL_GLINK_QMP
2458 2119 IRQ_TYPE_EDGE_RISING>;
2459 mboxes = <&ip 2120 mboxes = <&ipcc IPCC_CLIENT_SLPI
2460 2121 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2461 2122
2462 label = "slpi 2123 label = "slpi";
2463 qcom,remote-p 2124 qcom,remote-pid = <3>;
2464 2125
2465 fastrpc { 2126 fastrpc {
2466 compa 2127 compatible = "qcom,fastrpc";
2467 qcom, 2128 qcom,glink-channels = "fastrpcglink-apps-dsp";
2468 label 2129 label = "sdsp";
2469 qcom, <<
2470 #addr 2130 #address-cells = <1>;
2471 #size 2131 #size-cells = <0>;
2472 2132
2473 compu 2133 compute-cb@1 {
2474 2134 compatible = "qcom,fastrpc-compute-cb";
2475 2135 reg = <1>;
2476 2136 iommus = <&apps_smmu 0x0541 0x0>;
2477 }; 2137 };
2478 2138
2479 compu 2139 compute-cb@2 {
2480 2140 compatible = "qcom,fastrpc-compute-cb";
2481 2141 reg = <2>;
2482 2142 iommus = <&apps_smmu 0x0542 0x0>;
2483 }; 2143 };
2484 2144
2485 compu 2145 compute-cb@3 {
2486 2146 compatible = "qcom,fastrpc-compute-cb";
2487 2147 reg = <3>;
2488 2148 iommus = <&apps_smmu 0x0543 0x0>;
2489 2149 /* note: shared-cb = <4> in downstream */
2490 }; 2150 };
2491 }; 2151 };
2492 }; 2152 };
2493 }; 2153 };
2494 2154
2495 wsa2macro: codec@31e0000 { 2155 wsa2macro: codec@31e0000 {
2496 compatible = "qcom,sm 2156 compatible = "qcom,sm8450-lpass-wsa-macro";
2497 reg = <0 0x031e0000 0 2157 reg = <0 0x031e0000 0 0x1000>;
2498 clocks = <&q6prmcc LP 2158 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2499 <&q6prmcc LP 2159 <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2500 <&q6prmcc LP 2160 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2501 <&q6prmcc LP 2161 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2502 <&vamacro>; 2162 <&vamacro>;
2503 clock-names = "mclk", 2163 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
>> 2164 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 2165 <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
>> 2166 assigned-clock-rates = <19200000>, <19200000>;
2504 2167
2505 #clock-cells = <0>; 2168 #clock-cells = <0>;
2506 clock-output-names = 2169 clock-output-names = "wsa2-mclk";
>> 2170 pinctrl-names = "default";
>> 2171 pinctrl-0 = <&wsa2_swr_active>;
2507 #sound-dai-cells = <1 2172 #sound-dai-cells = <1>;
2508 }; 2173 };
2509 2174
2510 swr4: soundwire@31f0000 { 2175 swr4: soundwire@31f0000 {
2511 compatible = "qcom,so 2176 compatible = "qcom,soundwire-v1.7.0";
2512 reg = <0 0x031f0000 0 2177 reg = <0 0x031f0000 0 0x2000>;
2513 interrupts = <GIC_SPI 2178 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
2514 clocks = <&wsa2macro> 2179 clocks = <&wsa2macro>;
2515 clock-names = "iface" 2180 clock-names = "iface";
2516 label = "WSA2"; 2181 label = "WSA2";
2517 2182
2518 pinctrl-0 = <&wsa2_sw <<
2519 pinctrl-names = "defa <<
2520 <<
2521 qcom,din-ports = <2>; 2183 qcom,din-ports = <2>;
2522 qcom,dout-ports = <6> 2184 qcom,dout-ports = <6>;
2523 2185
2524 qcom,ports-sinterval- 2186 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2525 qcom,ports-offset1 = 2187 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2526 qcom,ports-offset2 = 2188 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2527 qcom,ports-hstart = 2189 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2528 qcom,ports-hstop = 2190 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2529 qcom,ports-word-lengt 2191 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2530 qcom,ports-block-pack 2192 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
2531 qcom,ports-block-grou 2193 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2532 qcom,ports-lane-contr 2194 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2533 2195
2534 #address-cells = <2>; 2196 #address-cells = <2>;
2535 #size-cells = <0>; 2197 #size-cells = <0>;
2536 #sound-dai-cells = <1 2198 #sound-dai-cells = <1>;
2537 status = "disabled"; 2199 status = "disabled";
2538 }; 2200 };
2539 2201
2540 rxmacro: codec@3200000 { 2202 rxmacro: codec@3200000 {
2541 compatible = "qcom,sm 2203 compatible = "qcom,sm8450-lpass-rx-macro";
2542 reg = <0 0x03200000 0 2204 reg = <0 0x03200000 0 0x1000>;
2543 clocks = <&q6prmcc LP 2205 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2544 <&q6prmcc LP 2206 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2545 <&q6prmcc LP 2207 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2546 <&q6prmcc LP 2208 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2547 <&vamacro>; 2209 <&vamacro>;
2548 clock-names = "mclk", 2210 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2549 2211
>> 2212 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 2213 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
>> 2214 assigned-clock-rates = <19200000>, <19200000>;
>> 2215
2550 #clock-cells = <0>; 2216 #clock-cells = <0>;
2551 clock-output-names = 2217 clock-output-names = "mclk";
>> 2218 pinctrl-names = "default";
>> 2219 pinctrl-0 = <&rx_swr_active>;
2552 #sound-dai-cells = <1 2220 #sound-dai-cells = <1>;
2553 }; 2221 };
2554 2222
2555 swr1: soundwire@3210000 { 2223 swr1: soundwire@3210000 {
2556 compatible = "qcom,so 2224 compatible = "qcom,soundwire-v1.7.0";
2557 reg = <0 0x03210000 0 2225 reg = <0 0x03210000 0 0x2000>;
2558 interrupts = <GIC_SPI 2226 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
2559 clocks = <&rxmacro>; 2227 clocks = <&rxmacro>;
2560 clock-names = "iface" 2228 clock-names = "iface";
2561 label = "RX"; 2229 label = "RX";
2562 qcom,din-ports = <0>; 2230 qcom,din-ports = <0>;
2563 qcom,dout-ports = <5> 2231 qcom,dout-ports = <5>;
2564 2232
2565 pinctrl-0 = <&rx_swr_ <<
2566 pinctrl-names = "defa <<
2567 <<
2568 qcom,ports-sinterval- 2233 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
2569 qcom,ports-offset1 = 2234 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>;
2570 qcom,ports-offset2 = 2235 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
2571 qcom,ports-hstart = 2236 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
2572 qcom,ports-hstop = 2237 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
2573 qcom,ports-word-lengt 2238 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2574 qcom,ports-block-pack 2239 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
2575 qcom,ports-block-grou 2240 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
2576 qcom,ports-lane-contr 2241 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2577 2242
2578 #address-cells = <2>; 2243 #address-cells = <2>;
2579 #size-cells = <0>; 2244 #size-cells = <0>;
2580 #sound-dai-cells = <1 2245 #sound-dai-cells = <1>;
2581 status = "disabled"; 2246 status = "disabled";
2582 }; 2247 };
2583 2248
2584 txmacro: codec@3220000 { 2249 txmacro: codec@3220000 {
2585 compatible = "qcom,sm 2250 compatible = "qcom,sm8450-lpass-tx-macro";
2586 reg = <0 0x03220000 0 2251 reg = <0 0x03220000 0 0x1000>;
2587 clocks = <&q6prmcc LP 2252 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2588 <&q6prmcc LP 2253 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2589 <&q6prmcc LP 2254 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2590 <&q6prmcc LP 2255 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2591 <&vamacro>; 2256 <&vamacro>;
2592 clock-names = "mclk", 2257 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
>> 2258 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 2259 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
>> 2260 assigned-clock-rates = <19200000>, <19200000>;
2593 2261
2594 #clock-cells = <0>; 2262 #clock-cells = <0>;
2595 clock-output-names = 2263 clock-output-names = "mclk";
>> 2264 pinctrl-names = "default";
>> 2265 pinctrl-0 = <&tx_swr_active>;
2596 #sound-dai-cells = <1 2266 #sound-dai-cells = <1>;
2597 }; 2267 };
2598 2268
2599 wsamacro: codec@3240000 { 2269 wsamacro: codec@3240000 {
2600 compatible = "qcom,sm 2270 compatible = "qcom,sm8450-lpass-wsa-macro";
2601 reg = <0 0x03240000 0 2271 reg = <0 0x03240000 0 0x1000>;
2602 clocks = <&q6prmcc LP 2272 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2603 <&q6prmcc LP 2273 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2604 <&q6prmcc LP 2274 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2605 <&q6prmcc LP 2275 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2606 <&vamacro>; 2276 <&vamacro>;
2607 clock-names = "mclk", 2277 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2608 2278
>> 2279 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 2280 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
>> 2281 assigned-clock-rates = <19200000>, <19200000>;
>> 2282
2609 #clock-cells = <0>; 2283 #clock-cells = <0>;
2610 clock-output-names = 2284 clock-output-names = "mclk";
>> 2285 pinctrl-names = "default";
>> 2286 pinctrl-0 = <&wsa_swr_active>;
2611 #sound-dai-cells = <1 2287 #sound-dai-cells = <1>;
2612 }; 2288 };
2613 2289
2614 swr0: soundwire@3250000 { 2290 swr0: soundwire@3250000 {
2615 compatible = "qcom,so 2291 compatible = "qcom,soundwire-v1.7.0";
2616 reg = <0 0x03250000 0 2292 reg = <0 0x03250000 0 0x2000>;
2617 interrupts = <GIC_SPI 2293 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
2618 clocks = <&wsamacro>; 2294 clocks = <&wsamacro>;
2619 clock-names = "iface" 2295 clock-names = "iface";
2620 label = "WSA"; 2296 label = "WSA";
2621 2297
2622 pinctrl-0 = <&wsa_swr <<
2623 pinctrl-names = "defa <<
2624 <<
2625 qcom,din-ports = <2>; 2298 qcom,din-ports = <2>;
2626 qcom,dout-ports = <6> 2299 qcom,dout-ports = <6>;
2627 2300
2628 qcom,ports-sinterval- 2301 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2629 qcom,ports-offset1 = 2302 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2630 qcom,ports-offset2 = 2303 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2631 qcom,ports-hstart = 2304 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2632 qcom,ports-hstop = 2305 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2633 qcom,ports-word-lengt 2306 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2634 qcom,ports-block-pack 2307 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
2635 qcom,ports-block-grou 2308 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2636 qcom,ports-lane-contr 2309 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2637 2310
2638 #address-cells = <2>; 2311 #address-cells = <2>;
2639 #size-cells = <0>; 2312 #size-cells = <0>;
2640 #sound-dai-cells = <1 2313 #sound-dai-cells = <1>;
2641 status = "disabled"; 2314 status = "disabled";
2642 }; 2315 };
2643 2316
2644 swr2: soundwire@33b0000 { 2317 swr2: soundwire@33b0000 {
2645 compatible = "qcom,so 2318 compatible = "qcom,soundwire-v1.7.0";
2646 reg = <0 0x033b0000 0 2319 reg = <0 0x033b0000 0 0x2000>;
2647 interrupts = <GIC_SPI 2320 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
2648 <GIC_SPI 2321 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>;
2649 interrupt-names = "co 2322 interrupt-names = "core", "wakeup";
2650 2323
2651 clocks = <&txmacro>; 2324 clocks = <&txmacro>;
2652 clock-names = "iface" 2325 clock-names = "iface";
2653 label = "TX"; 2326 label = "TX";
2654 2327
2655 pinctrl-0 = <&tx_swr_ <<
2656 pinctrl-names = "defa <<
2657 <<
2658 qcom,din-ports = <4>; 2328 qcom,din-ports = <4>;
2659 qcom,dout-ports = <0> 2329 qcom,dout-ports = <0>;
2660 qcom,ports-sinterval- 2330 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
2661 qcom,ports-offset1 = 2331 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>;
2662 qcom,ports-offset2 = 2332 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
2663 qcom,ports-hstart = 2333 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
2664 qcom,ports-hstop = 2334 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
2665 qcom,ports-word-lengt 2335 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
2666 qcom,ports-block-pack 2336 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
2667 qcom,ports-block-grou 2337 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
2668 qcom,ports-lane-contr 2338 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>;
2669 2339
2670 #address-cells = <2>; 2340 #address-cells = <2>;
2671 #size-cells = <0>; 2341 #size-cells = <0>;
2672 #sound-dai-cells = <1 2342 #sound-dai-cells = <1>;
2673 status = "disabled"; 2343 status = "disabled";
2674 }; 2344 };
2675 2345
2676 vamacro: codec@33f0000 { 2346 vamacro: codec@33f0000 {
2677 compatible = "qcom,sm 2347 compatible = "qcom,sm8450-lpass-va-macro";
2678 reg = <0 0x033f0000 0 2348 reg = <0 0x033f0000 0 0x1000>;
2679 clocks = <&q6prmcc LP 2349 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2680 <&q6prmcc LP 2350 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2681 <&q6prmcc LP 2351 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2682 <&q6prmcc LP 2352 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2683 clock-names = "mclk", 2353 clock-names = "mclk", "macro", "dcodec", "npl";
>> 2354 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
>> 2355 assigned-clock-rates = <19200000>;
2684 2356
2685 #clock-cells = <0>; 2357 #clock-cells = <0>;
2686 clock-output-names = 2358 clock-output-names = "fsgen";
2687 #sound-dai-cells = <1 2359 #sound-dai-cells = <1>;
2688 status = "disabled"; 2360 status = "disabled";
2689 }; 2361 };
2690 2362
2691 remoteproc_adsp: remoteproc@3 2363 remoteproc_adsp: remoteproc@30000000 {
2692 compatible = "qcom,sm 2364 compatible = "qcom,sm8450-adsp-pas";
2693 reg = <0 0x30000000 0 2365 reg = <0 0x30000000 0 0x100>;
2694 2366
2695 interrupts-extended = 2367 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
2696 2368 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
2697 2369 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
2698 2370 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
2699 2371 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
2700 interrupt-names = "wd 2372 interrupt-names = "wdog", "fatal", "ready",
2701 "ha 2373 "handover", "stop-ack";
2702 2374
2703 clocks = <&rpmhcc RPM 2375 clocks = <&rpmhcc RPMH_CXO_CLK>;
2704 clock-names = "xo"; 2376 clock-names = "xo";
2705 2377
2706 power-domains = <&rpm 2378 power-domains = <&rpmhpd RPMHPD_LCX>,
2707 <&rpm 2379 <&rpmhpd RPMHPD_LMX>;
2708 power-domain-names = 2380 power-domain-names = "lcx", "lmx";
2709 2381
2710 memory-region = <&ads 2382 memory-region = <&adsp_mem>;
2711 2383
2712 qcom,qmp = <&aoss_qmp 2384 qcom,qmp = <&aoss_qmp>;
2713 2385
2714 qcom,smem-states = <& 2386 qcom,smem-states = <&smp2p_adsp_out 0>;
2715 qcom,smem-state-names 2387 qcom,smem-state-names = "stop";
2716 2388
2717 status = "disabled"; 2389 status = "disabled";
2718 2390
2719 remoteproc_adsp_glink 2391 remoteproc_adsp_glink: glink-edge {
2720 interrupts-ex 2392 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
2721 2393 IPCC_MPROC_SIGNAL_GLINK_QMP
2722 2394 IRQ_TYPE_EDGE_RISING>;
2723 mboxes = <&ip 2395 mboxes = <&ipcc IPCC_CLIENT_LPASS
2724 2396 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2725 2397
2726 label = "lpas 2398 label = "lpass";
2727 qcom,remote-p 2399 qcom,remote-pid = <2>;
2728 2400
2729 gpr { 2401 gpr {
2730 compa 2402 compatible = "qcom,gpr";
2731 qcom, 2403 qcom,glink-channels = "adsp_apps";
2732 qcom, 2404 qcom,domain = <GPR_DOMAIN_ID_ADSP>;
2733 qcom, 2405 qcom,intents = <512 20>;
2734 #addr 2406 #address-cells = <1>;
2735 #size 2407 #size-cells = <0>;
2736 2408
2737 q6apm 2409 q6apm: service@1 {
2738 2410 compatible = "qcom,q6apm";
2739 2411 reg = <GPR_APM_MODULE_IID>;
2740 2412 #sound-dai-cells = <0>;
2741 2413 qcom,protection-domain = "avs/audio",
2742 2414 "msm/adsp/audio_pd";
2743 2415
2744 2416 q6apmdai: dais {
2745 2417 compatible = "qcom,q6apm-dais";
2746 2418 iommus = <&apps_smmu 0x1801 0x0>;
2747 2419 };
2748 2420
2749 2421 q6apmbedai: bedais {
2750 2422 compatible = "qcom,q6apm-lpass-dais";
2751 2423 #sound-dai-cells = <1>;
2752 2424 };
2753 }; 2425 };
2754 2426
2755 q6prm 2427 q6prm: service@2 {
2756 2428 compatible = "qcom,q6prm";
2757 2429 reg = <GPR_PRM_MODULE_IID>;
2758 2430 qcom,protection-domain = "avs/audio",
2759 2431 "msm/adsp/audio_pd";
2760 2432
2761 2433 q6prmcc: clock-controller {
2762 2434 compatible = "qcom,q6prm-lpass-clocks";
2763 2435 #clock-cells = <2>;
2764 2436 };
2765 }; 2437 };
2766 }; 2438 };
2767 2439
2768 fastrpc { 2440 fastrpc {
2769 compa 2441 compatible = "qcom,fastrpc";
2770 qcom, 2442 qcom,glink-channels = "fastrpcglink-apps-dsp";
2771 label 2443 label = "adsp";
2772 qcom, <<
2773 #addr 2444 #address-cells = <1>;
2774 #size 2445 #size-cells = <0>;
2775 2446
2776 compu 2447 compute-cb@3 {
2777 2448 compatible = "qcom,fastrpc-compute-cb";
2778 2449 reg = <3>;
2779 2450 iommus = <&apps_smmu 0x1803 0x0>;
2780 }; 2451 };
2781 2452
2782 compu 2453 compute-cb@4 {
2783 2454 compatible = "qcom,fastrpc-compute-cb";
2784 2455 reg = <4>;
2785 2456 iommus = <&apps_smmu 0x1804 0x0>;
2786 }; 2457 };
2787 2458
2788 compu 2459 compute-cb@5 {
2789 2460 compatible = "qcom,fastrpc-compute-cb";
2790 2461 reg = <5>;
2791 2462 iommus = <&apps_smmu 0x1805 0x0>;
2792 }; 2463 };
2793 }; 2464 };
2794 }; 2465 };
2795 }; 2466 };
2796 2467
2797 remoteproc_cdsp: remoteproc@3 2468 remoteproc_cdsp: remoteproc@32300000 {
2798 compatible = "qcom,sm 2469 compatible = "qcom,sm8450-cdsp-pas";
2799 reg = <0 0x32300000 0 2470 reg = <0 0x32300000 0 0x1400000>;
2800 2471
2801 interrupts-extended = 2472 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
2802 2473 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
2803 2474 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
2804 2475 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
2805 2476 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
2806 interrupt-names = "wd 2477 interrupt-names = "wdog", "fatal", "ready",
2807 "ha 2478 "handover", "stop-ack";
2808 2479
2809 clocks = <&rpmhcc RPM 2480 clocks = <&rpmhcc RPMH_CXO_CLK>;
2810 clock-names = "xo"; 2481 clock-names = "xo";
2811 2482
2812 power-domains = <&rpm 2483 power-domains = <&rpmhpd RPMHPD_CX>,
2813 <&rpm 2484 <&rpmhpd RPMHPD_MXC>;
2814 power-domain-names = 2485 power-domain-names = "cx", "mxc";
2815 2486
2816 memory-region = <&cds 2487 memory-region = <&cdsp_mem>;
2817 2488
2818 qcom,qmp = <&aoss_qmp 2489 qcom,qmp = <&aoss_qmp>;
2819 2490
2820 qcom,smem-states = <& 2491 qcom,smem-states = <&smp2p_cdsp_out 0>;
2821 qcom,smem-state-names 2492 qcom,smem-state-names = "stop";
2822 2493
2823 status = "disabled"; 2494 status = "disabled";
2824 2495
2825 glink-edge { 2496 glink-edge {
2826 interrupts-ex 2497 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
2827 2498 IPCC_MPROC_SIGNAL_GLINK_QMP
2828 2499 IRQ_TYPE_EDGE_RISING>;
2829 mboxes = <&ip 2500 mboxes = <&ipcc IPCC_CLIENT_CDSP
2830 2501 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2831 2502
2832 label = "cdsp 2503 label = "cdsp";
2833 qcom,remote-p 2504 qcom,remote-pid = <5>;
2834 2505
2835 fastrpc { 2506 fastrpc {
2836 compa 2507 compatible = "qcom,fastrpc";
2837 qcom, 2508 qcom,glink-channels = "fastrpcglink-apps-dsp";
2838 label 2509 label = "cdsp";
2839 qcom, <<
2840 #addr 2510 #address-cells = <1>;
2841 #size 2511 #size-cells = <0>;
2842 2512
2843 compu 2513 compute-cb@1 {
2844 2514 compatible = "qcom,fastrpc-compute-cb";
2845 2515 reg = <1>;
2846 2516 iommus = <&apps_smmu 0x2161 0x0400>,
2847 2517 <&apps_smmu 0x1021 0x1420>;
2848 }; 2518 };
2849 2519
2850 compu 2520 compute-cb@2 {
2851 2521 compatible = "qcom,fastrpc-compute-cb";
2852 2522 reg = <2>;
2853 2523 iommus = <&apps_smmu 0x2162 0x0400>,
2854 2524 <&apps_smmu 0x1022 0x1420>;
2855 }; 2525 };
2856 2526
2857 compu 2527 compute-cb@3 {
2858 2528 compatible = "qcom,fastrpc-compute-cb";
2859 2529 reg = <3>;
2860 2530 iommus = <&apps_smmu 0x2163 0x0400>,
2861 2531 <&apps_smmu 0x1023 0x1420>;
2862 }; 2532 };
2863 2533
2864 compu 2534 compute-cb@4 {
2865 2535 compatible = "qcom,fastrpc-compute-cb";
2866 2536 reg = <4>;
2867 2537 iommus = <&apps_smmu 0x2164 0x0400>,
2868 2538 <&apps_smmu 0x1024 0x1420>;
2869 }; 2539 };
2870 2540
2871 compu 2541 compute-cb@5 {
2872 2542 compatible = "qcom,fastrpc-compute-cb";
2873 2543 reg = <5>;
2874 2544 iommus = <&apps_smmu 0x2165 0x0400>,
2875 2545 <&apps_smmu 0x1025 0x1420>;
2876 }; 2546 };
2877 2547
2878 compu 2548 compute-cb@6 {
2879 2549 compatible = "qcom,fastrpc-compute-cb";
2880 2550 reg = <6>;
2881 2551 iommus = <&apps_smmu 0x2166 0x0400>,
2882 2552 <&apps_smmu 0x1026 0x1420>;
2883 }; 2553 };
2884 2554
2885 compu 2555 compute-cb@7 {
2886 2556 compatible = "qcom,fastrpc-compute-cb";
2887 2557 reg = <7>;
2888 2558 iommus = <&apps_smmu 0x2167 0x0400>,
2889 2559 <&apps_smmu 0x1027 0x1420>;
2890 }; 2560 };
2891 2561
2892 compu 2562 compute-cb@8 {
2893 2563 compatible = "qcom,fastrpc-compute-cb";
2894 2564 reg = <8>;
2895 2565 iommus = <&apps_smmu 0x2168 0x0400>,
2896 2566 <&apps_smmu 0x1028 0x1420>;
2897 }; 2567 };
2898 2568
2899 /* no 2569 /* note: secure cb9 in downstream */
2900 }; 2570 };
2901 }; 2571 };
2902 }; 2572 };
2903 2573
2904 remoteproc_mpss: remoteproc@4 2574 remoteproc_mpss: remoteproc@4080000 {
2905 compatible = "qcom,sm 2575 compatible = "qcom,sm8450-mpss-pas";
2906 reg = <0x0 0x04080000 2576 reg = <0x0 0x04080000 0x0 0x4040>;
2907 2577
2908 interrupts-extended = 2578 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
2909 2579 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
2910 2580 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
2911 2581 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
2912 2582 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>,
2913 2583 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>;
2914 interrupt-names = "wd 2584 interrupt-names = "wdog", "fatal", "ready", "handover",
2915 "st 2585 "stop-ack", "shutdown-ack";
2916 2586
2917 clocks = <&rpmhcc RPM 2587 clocks = <&rpmhcc RPMH_CXO_CLK>;
2918 clock-names = "xo"; 2588 clock-names = "xo";
2919 2589
2920 power-domains = <&rpm 2590 power-domains = <&rpmhpd RPMHPD_CX>,
2921 <&rpm 2591 <&rpmhpd RPMHPD_MSS>;
2922 power-domain-names = 2592 power-domain-names = "cx", "mss";
2923 2593
2924 memory-region = <&mps 2594 memory-region = <&mpss_mem>;
2925 2595
2926 qcom,qmp = <&aoss_qmp 2596 qcom,qmp = <&aoss_qmp>;
2927 2597
2928 qcom,smem-states = <& 2598 qcom,smem-states = <&smp2p_modem_out 0>;
2929 qcom,smem-state-names 2599 qcom,smem-state-names = "stop";
2930 2600
2931 status = "disabled"; 2601 status = "disabled";
2932 2602
2933 glink-edge { 2603 glink-edge {
2934 interrupts-ex 2604 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
2935 2605 IPCC_MPROC_SIGNAL_GLINK_QMP
2936 2606 IRQ_TYPE_EDGE_RISING>;
2937 mboxes = <&ip 2607 mboxes = <&ipcc IPCC_CLIENT_MPSS
2938 2608 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2939 label = "mode 2609 label = "modem";
2940 qcom,remote-p 2610 qcom,remote-pid = <1>;
2941 }; 2611 };
2942 }; 2612 };
2943 2613
2944 videocc: clock-controller@aaf 2614 videocc: clock-controller@aaf0000 {
2945 compatible = "qcom,sm 2615 compatible = "qcom,sm8450-videocc";
2946 reg = <0 0x0aaf0000 0 2616 reg = <0 0x0aaf0000 0 0x10000>;
2947 clocks = <&rpmhcc RPM 2617 clocks = <&rpmhcc RPMH_CXO_CLK>,
2948 <&gcc GCC_VI 2618 <&gcc GCC_VIDEO_AHB_CLK>;
2949 power-domains = <&rpm 2619 power-domains = <&rpmhpd RPMHPD_MMCX>;
2950 required-opps = <&rpm 2620 required-opps = <&rpmhpd_opp_low_svs>;
2951 #clock-cells = <1>; 2621 #clock-cells = <1>;
2952 #reset-cells = <1>; 2622 #reset-cells = <1>;
2953 #power-domain-cells = 2623 #power-domain-cells = <1>;
2954 }; 2624 };
2955 2625
2956 cci0: cci@ac15000 { 2626 cci0: cci@ac15000 {
2957 compatible = "qcom,sm 2627 compatible = "qcom,sm8450-cci", "qcom,msm8996-cci";
2958 reg = <0 0x0ac15000 0 2628 reg = <0 0x0ac15000 0 0x1000>;
2959 interrupts = <GIC_SPI 2629 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
2960 power-domains = <&cam 2630 power-domains = <&camcc TITAN_TOP_GDSC>;
2961 2631
2962 clocks = <&camcc CAM_ 2632 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
2963 <&camcc CAM_ 2633 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
2964 <&camcc CAM_ 2634 <&camcc CAM_CC_CPAS_AHB_CLK>,
2965 <&camcc CAM_ 2635 <&camcc CAM_CC_CCI_0_CLK>,
2966 <&camcc CAM_ 2636 <&camcc CAM_CC_CCI_0_CLK_SRC>;
2967 clock-names = "camnoc 2637 clock-names = "camnoc_axi",
2968 "slow_a 2638 "slow_ahb_src",
2969 "cpas_a 2639 "cpas_ahb",
2970 "cci", 2640 "cci",
2971 "cci_sr 2641 "cci_src";
2972 pinctrl-0 = <&cci0_de 2642 pinctrl-0 = <&cci0_default &cci1_default>;
2973 pinctrl-1 = <&cci0_sl 2643 pinctrl-1 = <&cci0_sleep &cci1_sleep>;
2974 pinctrl-names = "defa 2644 pinctrl-names = "default", "sleep";
2975 2645
2976 status = "disabled"; 2646 status = "disabled";
2977 #address-cells = <1>; 2647 #address-cells = <1>;
2978 #size-cells = <0>; 2648 #size-cells = <0>;
2979 2649
2980 cci0_i2c0: i2c-bus@0 2650 cci0_i2c0: i2c-bus@0 {
2981 reg = <0>; 2651 reg = <0>;
2982 clock-frequen 2652 clock-frequency = <1000000>;
2983 #address-cell 2653 #address-cells = <1>;
2984 #size-cells = 2654 #size-cells = <0>;
2985 }; 2655 };
2986 2656
2987 cci0_i2c1: i2c-bus@1 2657 cci0_i2c1: i2c-bus@1 {
2988 reg = <1>; 2658 reg = <1>;
2989 clock-frequen 2659 clock-frequency = <1000000>;
2990 #address-cell 2660 #address-cells = <1>;
2991 #size-cells = 2661 #size-cells = <0>;
2992 }; 2662 };
2993 }; 2663 };
2994 2664
2995 cci1: cci@ac16000 { 2665 cci1: cci@ac16000 {
2996 compatible = "qcom,sm 2666 compatible = "qcom,sm8450-cci", "qcom,msm8996-cci";
2997 reg = <0 0x0ac16000 0 2667 reg = <0 0x0ac16000 0 0x1000>;
2998 interrupts = <GIC_SPI 2668 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>;
2999 power-domains = <&cam 2669 power-domains = <&camcc TITAN_TOP_GDSC>;
3000 2670
3001 clocks = <&camcc CAM_ 2671 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
3002 <&camcc CAM_ 2672 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
3003 <&camcc CAM_ 2673 <&camcc CAM_CC_CPAS_AHB_CLK>,
3004 <&camcc CAM_ 2674 <&camcc CAM_CC_CCI_1_CLK>,
3005 <&camcc CAM_ 2675 <&camcc CAM_CC_CCI_1_CLK_SRC>;
3006 clock-names = "camnoc 2676 clock-names = "camnoc_axi",
3007 "slow_a 2677 "slow_ahb_src",
3008 "cpas_a 2678 "cpas_ahb",
3009 "cci", 2679 "cci",
3010 "cci_sr 2680 "cci_src";
3011 pinctrl-0 = <&cci2_de 2681 pinctrl-0 = <&cci2_default &cci3_default>;
3012 pinctrl-1 = <&cci2_sl 2682 pinctrl-1 = <&cci2_sleep &cci3_sleep>;
3013 pinctrl-names = "defa 2683 pinctrl-names = "default", "sleep";
3014 2684
3015 status = "disabled"; 2685 status = "disabled";
3016 #address-cells = <1>; 2686 #address-cells = <1>;
3017 #size-cells = <0>; 2687 #size-cells = <0>;
3018 2688
3019 cci1_i2c0: i2c-bus@0 2689 cci1_i2c0: i2c-bus@0 {
3020 reg = <0>; 2690 reg = <0>;
3021 clock-frequen 2691 clock-frequency = <1000000>;
3022 #address-cell 2692 #address-cells = <1>;
3023 #size-cells = 2693 #size-cells = <0>;
3024 }; 2694 };
3025 2695
3026 cci1_i2c1: i2c-bus@1 2696 cci1_i2c1: i2c-bus@1 {
3027 reg = <1>; 2697 reg = <1>;
3028 clock-frequen 2698 clock-frequency = <1000000>;
3029 #address-cell 2699 #address-cells = <1>;
3030 #size-cells = 2700 #size-cells = <0>;
3031 }; 2701 };
3032 }; 2702 };
3033 2703
3034 camcc: clock-controller@ade00 2704 camcc: clock-controller@ade0000 {
3035 compatible = "qcom,sm 2705 compatible = "qcom,sm8450-camcc";
3036 reg = <0 0x0ade0000 0 2706 reg = <0 0x0ade0000 0 0x20000>;
3037 clocks = <&gcc GCC_CA 2707 clocks = <&gcc GCC_CAMERA_AHB_CLK>,
3038 <&rpmhcc RPM 2708 <&rpmhcc RPMH_CXO_CLK>,
3039 <&rpmhcc RPM 2709 <&rpmhcc RPMH_CXO_CLK_A>,
3040 <&sleep_clk> 2710 <&sleep_clk>;
3041 power-domains = <&rpm 2711 power-domains = <&rpmhpd RPMHPD_MMCX>;
3042 required-opps = <&rpm 2712 required-opps = <&rpmhpd_opp_low_svs>;
3043 #clock-cells = <1>; 2713 #clock-cells = <1>;
3044 #reset-cells = <1>; 2714 #reset-cells = <1>;
3045 #power-domain-cells = 2715 #power-domain-cells = <1>;
3046 status = "disabled"; 2716 status = "disabled";
3047 }; 2717 };
3048 2718
3049 mdss: display-subsystem@ae000 2719 mdss: display-subsystem@ae00000 {
3050 compatible = "qcom,sm 2720 compatible = "qcom,sm8450-mdss";
3051 reg = <0 0x0ae00000 0 2721 reg = <0 0x0ae00000 0 0x1000>;
3052 reg-names = "mdss"; 2722 reg-names = "mdss";
3053 2723
3054 /* same path used twi 2724 /* same path used twice */
3055 interconnects = <&mms 2725 interconnects = <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>,
3056 <&mms 2726 <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>,
3057 <&gem 2727 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
3058 &con 2728 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
3059 interconnect-names = 2729 interconnect-names = "mdp0-mem",
3060 2730 "mdp1-mem",
3061 2731 "cpu-cfg";
3062 2732
3063 resets = <&dispcc DIS 2733 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
3064 2734
3065 power-domains = <&dis 2735 power-domains = <&dispcc MDSS_GDSC>;
3066 2736
3067 clocks = <&dispcc DIS 2737 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3068 <&gcc GCC_DI 2738 <&gcc GCC_DISP_HF_AXI_CLK>,
3069 <&gcc GCC_DI 2739 <&gcc GCC_DISP_SF_AXI_CLK>,
3070 <&dispcc DIS 2740 <&dispcc DISP_CC_MDSS_MDP_CLK>;
3071 2741
3072 interrupts = <GIC_SPI 2742 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
3073 interrupt-controller; 2743 interrupt-controller;
3074 #interrupt-cells = <1 2744 #interrupt-cells = <1>;
3075 2745
3076 iommus = <&apps_smmu 2746 iommus = <&apps_smmu 0x2800 0x402>;
3077 2747
3078 #address-cells = <2>; 2748 #address-cells = <2>;
3079 #size-cells = <2>; 2749 #size-cells = <2>;
3080 ranges; 2750 ranges;
3081 2751
3082 status = "disabled"; 2752 status = "disabled";
3083 2753
3084 mdss_mdp: display-con 2754 mdss_mdp: display-controller@ae01000 {
3085 compatible = 2755 compatible = "qcom,sm8450-dpu";
3086 reg = <0 0x0a 2756 reg = <0 0x0ae01000 0 0x8f000>,
3087 <0 0x0a 2757 <0 0x0aeb0000 0 0x2008>;
3088 reg-names = " 2758 reg-names = "mdp", "vbif";
3089 2759
3090 clocks = <&gc 2760 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
3091 <&gcc 2761 <&gcc GCC_DISP_SF_AXI_CLK>,
3092 <&dis 2762 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3093 <&dis 2763 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
3094 <&dis 2764 <&dispcc DISP_CC_MDSS_MDP_CLK>,
3095 <&dis 2765 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3096 clock-names = 2766 clock-names = "bus",
3097 2767 "nrt_bus",
3098 2768 "iface",
3099 2769 "lut",
3100 2770 "core",
3101 2771 "vsync";
3102 2772
3103 assigned-cloc 2773 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3104 assigned-cloc 2774 assigned-clock-rates = <19200000>;
3105 2775
3106 operating-poi 2776 operating-points-v2 = <&mdp_opp_table>;
3107 power-domains 2777 power-domains = <&rpmhpd RPMHPD_MMCX>;
3108 2778
3109 interrupt-par 2779 interrupt-parent = <&mdss>;
3110 interrupts = 2780 interrupts = <0>;
3111 2781
3112 ports { 2782 ports {
3113 #addr 2783 #address-cells = <1>;
3114 #size 2784 #size-cells = <0>;
3115 2785
3116 port@ 2786 port@0 {
3117 2787 reg = <0>;
3118 2788 dpu_intf1_out: endpoint {
3119 2789 remote-endpoint = <&mdss_dsi0_in>;
3120 2790 };
3121 }; 2791 };
3122 2792
3123 port@ 2793 port@1 {
3124 2794 reg = <1>;
3125 2795 dpu_intf2_out: endpoint {
3126 2796 remote-endpoint = <&mdss_dsi1_in>;
3127 2797 };
3128 }; 2798 };
3129 2799
3130 port@ 2800 port@2 {
3131 2801 reg = <2>;
3132 2802 dpu_intf0_out: endpoint {
3133 2803 remote-endpoint = <&mdss_dp0_in>;
3134 2804 };
3135 }; 2805 };
3136 }; 2806 };
3137 2807
3138 mdp_opp_table 2808 mdp_opp_table: opp-table {
3139 compa 2809 compatible = "operating-points-v2";
3140 2810
3141 opp-1 2811 opp-172000000 {
3142 2812 opp-hz = /bits/ 64 <172000000>;
3143 2813 required-opps = <&rpmhpd_opp_low_svs_d1>;
3144 }; 2814 };
3145 2815
3146 opp-2 2816 opp-200000000 {
3147 2817 opp-hz = /bits/ 64 <200000000>;
3148 2818 required-opps = <&rpmhpd_opp_low_svs>;
3149 }; 2819 };
3150 2820
3151 opp-3 2821 opp-325000000 {
3152 2822 opp-hz = /bits/ 64 <325000000>;
3153 2823 required-opps = <&rpmhpd_opp_svs>;
3154 }; 2824 };
3155 2825
3156 opp-3 2826 opp-375000000 {
3157 2827 opp-hz = /bits/ 64 <375000000>;
3158 2828 required-opps = <&rpmhpd_opp_svs_l1>;
3159 }; 2829 };
3160 2830
3161 opp-5 2831 opp-500000000 {
3162 2832 opp-hz = /bits/ 64 <500000000>;
3163 2833 required-opps = <&rpmhpd_opp_nom>;
3164 }; 2834 };
3165 }; 2835 };
3166 }; 2836 };
3167 2837
3168 mdss_dp0: displayport 2838 mdss_dp0: displayport-controller@ae90000 {
3169 compatible = 2839 compatible = "qcom,sm8450-dp", "qcom,sm8350-dp";
3170 reg = <0 0xae 2840 reg = <0 0xae90000 0 0x200>,
3171 <0 0xae 2841 <0 0xae90200 0 0x200>,
3172 <0 0xae 2842 <0 0xae90400 0 0xc00>,
3173 <0 0xae 2843 <0 0xae91000 0 0x400>,
3174 <0 0xae 2844 <0 0xae91400 0 0x400>;
3175 interrupt-par 2845 interrupt-parent = <&mdss>;
3176 interrupts = 2846 interrupts = <12>;
3177 clocks = <&di 2847 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3178 <&di 2848 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
3179 <&di 2849 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
3180 <&di 2850 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
3181 <&di 2851 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
3182 clock-names = 2852 clock-names = "core_iface",
3183 2853 "core_aux",
3184 2854 "ctrl_link",
3185 2855 "ctrl_link_iface",
3186 2856 "stream_pixel";
3187 2857
3188 assigned-cloc 2858 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
3189 2859 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
3190 assigned-cloc 2860 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3191 2861 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
3192 2862
3193 phys = <&usb_ 2863 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
3194 phy-names = " 2864 phy-names = "dp";
3195 2865
3196 #sound-dai-ce 2866 #sound-dai-cells = <0>;
3197 2867
3198 operating-poi 2868 operating-points-v2 = <&dp_opp_table>;
3199 power-domains 2869 power-domains = <&rpmhpd RPMHPD_MMCX>;
3200 2870
3201 status = "dis 2871 status = "disabled";
3202 2872
3203 ports { 2873 ports {
3204 #addr 2874 #address-cells = <1>;
3205 #size 2875 #size-cells = <0>;
3206 2876
3207 port@ 2877 port@0 {
3208 2878 reg = <0>;
3209 2879 mdss_dp0_in: endpoint {
3210 2880 remote-endpoint = <&dpu_intf0_out>;
3211 2881 };
3212 }; 2882 };
3213 <<
3214 port@ <<
3215 <<
3216 <<
3217 <<
3218 <<
3219 <<
3220 }; <<
3221 }; 2883 };
3222 2884
3223 dp_opp_table: 2885 dp_opp_table: opp-table {
3224 compa 2886 compatible = "operating-points-v2";
3225 2887
3226 opp-1 2888 opp-160000000 {
3227 2889 opp-hz = /bits/ 64 <160000000>;
3228 2890 required-opps = <&rpmhpd_opp_low_svs>;
3229 }; 2891 };
3230 2892
3231 opp-2 2893 opp-270000000 {
3232 2894 opp-hz = /bits/ 64 <270000000>;
3233 2895 required-opps = <&rpmhpd_opp_svs>;
3234 }; 2896 };
3235 2897
3236 opp-5 2898 opp-540000000 {
3237 2899 opp-hz = /bits/ 64 <540000000>;
3238 2900 required-opps = <&rpmhpd_opp_svs_l1>;
3239 }; 2901 };
3240 2902
3241 opp-8 2903 opp-810000000 {
3242 2904 opp-hz = /bits/ 64 <810000000>;
3243 2905 required-opps = <&rpmhpd_opp_nom>;
3244 }; 2906 };
3245 }; 2907 };
3246 }; 2908 };
3247 2909
3248 mdss_dsi0: dsi@ae9400 2910 mdss_dsi0: dsi@ae94000 {
3249 compatible = 2911 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3250 reg = <0 0x0a 2912 reg = <0 0x0ae94000 0 0x400>;
3251 reg-names = " 2913 reg-names = "dsi_ctrl";
3252 2914
3253 interrupt-par 2915 interrupt-parent = <&mdss>;
3254 interrupts = 2916 interrupts = <4>;
3255 2917
3256 clocks = <&di 2918 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
3257 <&di 2919 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
3258 <&di 2920 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
3259 <&di 2921 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
3260 <&di 2922 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3261 <&gcc 2923 <&gcc GCC_DISP_HF_AXI_CLK>;
3262 clock-names = 2924 clock-names = "byte",
3263 2925 "byte_intf",
3264 2926 "pixel",
3265 2927 "core",
3266 2928 "iface",
3267 2929 "bus";
3268 2930
3269 assigned-cloc 2931 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
3270 assigned-cloc 2932 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
3271 2933
3272 operating-poi 2934 operating-points-v2 = <&mdss_dsi_opp_table>;
3273 power-domains 2935 power-domains = <&rpmhpd RPMHPD_MMCX>;
3274 2936
3275 phys = <&mdss 2937 phys = <&mdss_dsi0_phy>;
3276 phy-names = " 2938 phy-names = "dsi";
3277 2939
3278 #address-cell 2940 #address-cells = <1>;
3279 #size-cells = 2941 #size-cells = <0>;
3280 2942
3281 status = "dis 2943 status = "disabled";
3282 2944
3283 ports { 2945 ports {
3284 #addr 2946 #address-cells = <1>;
3285 #size 2947 #size-cells = <0>;
3286 2948
3287 port@ 2949 port@0 {
3288 2950 reg = <0>;
3289 2951 mdss_dsi0_in: endpoint {
3290 2952 remote-endpoint = <&dpu_intf1_out>;
3291 2953 };
3292 }; 2954 };
3293 2955
3294 port@ 2956 port@1 {
3295 2957 reg = <1>;
3296 2958 mdss_dsi0_out: endpoint {
3297 2959 };
3298 }; 2960 };
3299 }; 2961 };
3300 2962
3301 mdss_dsi_opp_ 2963 mdss_dsi_opp_table: opp-table {
3302 compa 2964 compatible = "operating-points-v2";
3303 2965
3304 opp-1 2966 opp-187500000 {
3305 2967 opp-hz = /bits/ 64 <187500000>;
3306 2968 required-opps = <&rpmhpd_opp_low_svs>;
3307 }; 2969 };
3308 2970
3309 opp-3 2971 opp-300000000 {
3310 2972 opp-hz = /bits/ 64 <300000000>;
3311 2973 required-opps = <&rpmhpd_opp_svs>;
3312 }; 2974 };
3313 2975
3314 opp-3 2976 opp-358000000 {
3315 2977 opp-hz = /bits/ 64 <358000000>;
3316 2978 required-opps = <&rpmhpd_opp_svs_l1>;
3317 }; 2979 };
3318 }; 2980 };
3319 }; 2981 };
3320 2982
3321 mdss_dsi0_phy: phy@ae 2983 mdss_dsi0_phy: phy@ae94400 {
3322 compatible = 2984 compatible = "qcom,sm8450-dsi-phy-5nm";
3323 reg = <0 0x0a 2985 reg = <0 0x0ae94400 0 0x200>,
3324 <0 0x0a 2986 <0 0x0ae94600 0 0x280>,
3325 <0 0x0a 2987 <0 0x0ae94900 0 0x260>;
3326 reg-names = " 2988 reg-names = "dsi_phy",
3327 " 2989 "dsi_phy_lane",
3328 " 2990 "dsi_pll";
3329 2991
3330 #clock-cells 2992 #clock-cells = <1>;
3331 #phy-cells = 2993 #phy-cells = <0>;
3332 2994
3333 clocks = <&di 2995 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3334 <&rp 2996 <&rpmhcc RPMH_CXO_CLK>;
3335 clock-names = 2997 clock-names = "iface", "ref";
3336 2998
3337 status = "dis 2999 status = "disabled";
3338 }; 3000 };
3339 3001
3340 mdss_dsi1: dsi@ae9600 3002 mdss_dsi1: dsi@ae96000 {
3341 compatible = 3003 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3342 reg = <0 0x0a 3004 reg = <0 0x0ae96000 0 0x400>;
3343 reg-names = " 3005 reg-names = "dsi_ctrl";
3344 3006
3345 interrupt-par 3007 interrupt-parent = <&mdss>;
3346 interrupts = 3008 interrupts = <5>;
3347 3009
3348 clocks = <&di 3010 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
3349 <&di 3011 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
3350 <&di 3012 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
3351 <&di 3013 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
3352 <&di 3014 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3353 <&gc 3015 <&gcc GCC_DISP_HF_AXI_CLK>;
3354 clock-names = 3016 clock-names = "byte",
3355 3017 "byte_intf",
3356 3018 "pixel",
3357 3019 "core",
3358 3020 "iface",
3359 3021 "bus";
3360 3022
3361 assigned-cloc 3023 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
3362 assigned-cloc 3024 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
3363 3025
3364 operating-poi 3026 operating-points-v2 = <&mdss_dsi_opp_table>;
3365 power-domains 3027 power-domains = <&rpmhpd RPMHPD_MMCX>;
3366 3028
3367 phys = <&mdss 3029 phys = <&mdss_dsi1_phy>;
3368 phy-names = " 3030 phy-names = "dsi";
3369 3031
3370 #address-cell 3032 #address-cells = <1>;
3371 #size-cells = 3033 #size-cells = <0>;
3372 3034
3373 status = "dis 3035 status = "disabled";
3374 3036
3375 ports { 3037 ports {
3376 #addr 3038 #address-cells = <1>;
3377 #size 3039 #size-cells = <0>;
3378 3040
3379 port@ 3041 port@0 {
3380 3042 reg = <0>;
3381 3043 mdss_dsi1_in: endpoint {
3382 3044 remote-endpoint = <&dpu_intf2_out>;
3383 3045 };
3384 }; 3046 };
3385 3047
3386 port@ 3048 port@1 {
3387 3049 reg = <1>;
3388 3050 mdss_dsi1_out: endpoint {
3389 3051 };
3390 }; 3052 };
3391 }; 3053 };
3392 }; 3054 };
3393 3055
3394 mdss_dsi1_phy: phy@ae 3056 mdss_dsi1_phy: phy@ae96400 {
3395 compatible = 3057 compatible = "qcom,sm8450-dsi-phy-5nm";
3396 reg = <0 0x0a 3058 reg = <0 0x0ae96400 0 0x200>,
3397 <0 0x0a 3059 <0 0x0ae96600 0 0x280>,
3398 <0 0x0a 3060 <0 0x0ae96900 0 0x260>;
3399 reg-names = " 3061 reg-names = "dsi_phy",
3400 " 3062 "dsi_phy_lane",
3401 " 3063 "dsi_pll";
3402 3064
3403 #clock-cells 3065 #clock-cells = <1>;
3404 #phy-cells = 3066 #phy-cells = <0>;
3405 3067
3406 clocks = <&di 3068 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3407 <&rp 3069 <&rpmhcc RPMH_CXO_CLK>;
3408 clock-names = 3070 clock-names = "iface", "ref";
3409 3071
3410 status = "dis 3072 status = "disabled";
3411 }; 3073 };
3412 }; 3074 };
3413 3075
3414 dispcc: clock-controller@af00 3076 dispcc: clock-controller@af00000 {
3415 compatible = "qcom,sm 3077 compatible = "qcom,sm8450-dispcc";
3416 reg = <0 0x0af00000 0 3078 reg = <0 0x0af00000 0 0x20000>;
3417 clocks = <&rpmhcc RPM 3079 clocks = <&rpmhcc RPMH_CXO_CLK>,
3418 <&rpmhcc RPM 3080 <&rpmhcc RPMH_CXO_CLK_A>,
3419 <&gcc GCC_DI 3081 <&gcc GCC_DISP_AHB_CLK>,
3420 <&sleep_clk> 3082 <&sleep_clk>,
3421 <&mdss_dsi0_ 3083 <&mdss_dsi0_phy 0>,
3422 <&mdss_dsi0_ 3084 <&mdss_dsi0_phy 1>,
3423 <&mdss_dsi1_ 3085 <&mdss_dsi1_phy 0>,
3424 <&mdss_dsi1_ 3086 <&mdss_dsi1_phy 1>,
3425 <&usb_1_qmpp 3087 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3426 <&usb_1_qmpp 3088 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
3427 <0>, /* dp1 3089 <0>, /* dp1 */
3428 <0>, 3090 <0>,
3429 <0>, /* dp2 3091 <0>, /* dp2 */
3430 <0>, 3092 <0>,
3431 <0>, /* dp3 3093 <0>, /* dp3 */
3432 <0>; 3094 <0>;
3433 power-domains = <&rpm 3095 power-domains = <&rpmhpd RPMHPD_MMCX>;
3434 required-opps = <&rpm 3096 required-opps = <&rpmhpd_opp_low_svs>;
3435 #clock-cells = <1>; 3097 #clock-cells = <1>;
3436 #reset-cells = <1>; 3098 #reset-cells = <1>;
3437 #power-domain-cells = 3099 #power-domain-cells = <1>;
3438 status = "disabled"; 3100 status = "disabled";
3439 }; 3101 };
3440 3102
3441 pdc: interrupt-controller@b22 3103 pdc: interrupt-controller@b220000 {
3442 compatible = "qcom,sm 3104 compatible = "qcom,sm8450-pdc", "qcom,pdc";
3443 reg = <0 0x0b220000 0 3105 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
3444 qcom,pdc-ranges = <0 3106 qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>,
3445 <94 3107 <94 609 31>, <125 63 1>, <126 716 12>;
3446 #interrupt-cells = <2 3108 #interrupt-cells = <2>;
3447 interrupt-parent = <& 3109 interrupt-parent = <&intc>;
3448 interrupt-controller; 3110 interrupt-controller;
3449 }; 3111 };
3450 3112
3451 tsens0: thermal-sensor@c26300 3113 tsens0: thermal-sensor@c263000 {
3452 compatible = "qcom,sm 3114 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2";
3453 reg = <0 0x0c263000 0 3115 reg = <0 0x0c263000 0 0x1000>, /* TM */
3454 <0 0x0c222000 0 3116 <0 0x0c222000 0 0x1000>; /* SROT */
3455 #qcom,sensors = <16>; 3117 #qcom,sensors = <16>;
3456 interrupts = <GIC_SPI 3118 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
3457 <GIC_SPI 3119 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
3458 interrupt-names = "up 3120 interrupt-names = "uplow", "critical";
3459 #thermal-sensor-cells 3121 #thermal-sensor-cells = <1>;
3460 }; 3122 };
3461 3123
3462 tsens1: thermal-sensor@c26500 3124 tsens1: thermal-sensor@c265000 {
3463 compatible = "qcom,sm 3125 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2";
3464 reg = <0 0x0c265000 0 3126 reg = <0 0x0c265000 0 0x1000>, /* TM */
3465 <0 0x0c223000 0 3127 <0 0x0c223000 0 0x1000>; /* SROT */
3466 #qcom,sensors = <16>; 3128 #qcom,sensors = <16>;
3467 interrupts = <GIC_SPI 3129 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
3468 <GIC_SPI 3130 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
3469 interrupt-names = "up 3131 interrupt-names = "uplow", "critical";
3470 #thermal-sensor-cells 3132 #thermal-sensor-cells = <1>;
3471 }; 3133 };
3472 3134
3473 aoss_qmp: power-management@c3 3135 aoss_qmp: power-management@c300000 {
3474 compatible = "qcom,sm 3136 compatible = "qcom,sm8450-aoss-qmp", "qcom,aoss-qmp";
3475 reg = <0 0x0c300000 0 3137 reg = <0 0x0c300000 0 0x400>;
3476 interrupts-extended = 3138 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
3477 3139 IRQ_TYPE_EDGE_RISING>;
3478 mboxes = <&ipcc IPCC_ 3140 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
3479 3141
3480 #clock-cells = <0>; 3142 #clock-cells = <0>;
3481 }; 3143 };
3482 3144
3483 sram@c3f0000 { 3145 sram@c3f0000 {
3484 compatible = "qcom,rp 3146 compatible = "qcom,rpmh-stats";
3485 reg = <0 0x0c3f0000 0 3147 reg = <0 0x0c3f0000 0 0x400>;
3486 }; 3148 };
3487 3149
3488 spmi_bus: spmi@c400000 { 3150 spmi_bus: spmi@c400000 {
3489 compatible = "qcom,sp 3151 compatible = "qcom,spmi-pmic-arb";
3490 reg = <0 0x0c400000 0 3152 reg = <0 0x0c400000 0 0x00003000>,
3491 <0 0x0c500000 0 3153 <0 0x0c500000 0 0x00400000>,
3492 <0 0x0c440000 0 3154 <0 0x0c440000 0 0x00080000>,
3493 <0 0x0c4c0000 0 3155 <0 0x0c4c0000 0 0x00010000>,
3494 <0 0x0c42d000 0 3156 <0 0x0c42d000 0 0x00010000>;
3495 reg-names = "core", 3157 reg-names = "core",
3496 "chnls", 3158 "chnls",
3497 "obsrvr", 3159 "obsrvr",
3498 "intr", 3160 "intr",
3499 "cnfg"; 3161 "cnfg";
3500 interrupt-names = "pe 3162 interrupt-names = "periph_irq";
3501 interrupts-extended = 3163 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3502 qcom,ee = <0>; 3164 qcom,ee = <0>;
3503 qcom,channel = <0>; 3165 qcom,channel = <0>;
3504 interrupt-controller; 3166 interrupt-controller;
3505 #interrupt-cells = <4 3167 #interrupt-cells = <4>;
3506 #address-cells = <2>; 3168 #address-cells = <2>;
3507 #size-cells = <0>; 3169 #size-cells = <0>;
3508 }; 3170 };
3509 3171
3510 ipcc: mailbox@ed18000 { 3172 ipcc: mailbox@ed18000 {
3511 compatible = "qcom,sm 3173 compatible = "qcom,sm8450-ipcc", "qcom,ipcc";
3512 reg = <0 0x0ed18000 0 3174 reg = <0 0x0ed18000 0 0x1000>;
3513 interrupts = <GIC_SPI 3175 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
3514 interrupt-controller; 3176 interrupt-controller;
3515 #interrupt-cells = <3 3177 #interrupt-cells = <3>;
3516 #mbox-cells = <2>; 3178 #mbox-cells = <2>;
3517 }; 3179 };
3518 3180
3519 tlmm: pinctrl@f100000 { 3181 tlmm: pinctrl@f100000 {
3520 compatible = "qcom,sm 3182 compatible = "qcom,sm8450-tlmm";
3521 reg = <0 0x0f100000 0 3183 reg = <0 0x0f100000 0 0x300000>;
3522 interrupts = <GIC_SPI 3184 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
3523 gpio-controller; 3185 gpio-controller;
3524 #gpio-cells = <2>; 3186 #gpio-cells = <2>;
3525 interrupt-controller; 3187 interrupt-controller;
3526 #interrupt-cells = <2 3188 #interrupt-cells = <2>;
3527 gpio-ranges = <&tlmm 3189 gpio-ranges = <&tlmm 0 0 211>;
3528 wakeup-parent = <&pdc 3190 wakeup-parent = <&pdc>;
3529 3191
3530 sdc2_default_state: s 3192 sdc2_default_state: sdc2-default-state {
3531 clk-pins { 3193 clk-pins {
3532 pins 3194 pins = "sdc2_clk";
3533 drive 3195 drive-strength = <16>;
3534 bias- 3196 bias-disable;
3535 }; 3197 };
3536 3198
3537 cmd-pins { 3199 cmd-pins {
3538 pins 3200 pins = "sdc2_cmd";
3539 drive 3201 drive-strength = <16>;
3540 bias- 3202 bias-pull-up;
3541 }; 3203 };
3542 3204
3543 data-pins { 3205 data-pins {
3544 pins 3206 pins = "sdc2_data";
3545 drive 3207 drive-strength = <16>;
3546 bias- 3208 bias-pull-up;
3547 }; 3209 };
3548 }; 3210 };
3549 3211
3550 sdc2_sleep_state: sdc 3212 sdc2_sleep_state: sdc2-sleep-state {
3551 clk-pins { 3213 clk-pins {
3552 pins 3214 pins = "sdc2_clk";
3553 drive 3215 drive-strength = <2>;
3554 bias- 3216 bias-disable;
3555 }; 3217 };
3556 3218
3557 cmd-pins { 3219 cmd-pins {
3558 pins 3220 pins = "sdc2_cmd";
3559 drive 3221 drive-strength = <2>;
3560 bias- 3222 bias-pull-up;
3561 }; 3223 };
3562 3224
3563 data-pins { 3225 data-pins {
3564 pins 3226 pins = "sdc2_data";
3565 drive 3227 drive-strength = <2>;
3566 bias- 3228 bias-pull-up;
3567 }; 3229 };
3568 }; 3230 };
3569 3231
3570 cci0_default: cci0-de 3232 cci0_default: cci0-default-state {
3571 /* SDA, SCL * 3233 /* SDA, SCL */
3572 pins = "gpio1 3234 pins = "gpio110", "gpio111";
3573 function = "c 3235 function = "cci_i2c";
3574 drive-strengt 3236 drive-strength = <2>;
3575 bias-pull-up; 3237 bias-pull-up;
3576 }; 3238 };
3577 3239
3578 cci0_sleep: cci0-slee 3240 cci0_sleep: cci0-sleep-state {
3579 /* SDA, SCL * 3241 /* SDA, SCL */
3580 pins = "gpio1 3242 pins = "gpio110", "gpio111";
3581 function = "c 3243 function = "cci_i2c";
3582 drive-strengt 3244 drive-strength = <2>;
3583 bias-pull-dow 3245 bias-pull-down;
3584 }; 3246 };
3585 3247
3586 cci1_default: cci1-de 3248 cci1_default: cci1-default-state {
3587 /* SDA, SCL * 3249 /* SDA, SCL */
3588 pins = "gpio1 3250 pins = "gpio112", "gpio113";
3589 function = "c 3251 function = "cci_i2c";
3590 drive-strengt 3252 drive-strength = <2>;
3591 bias-pull-up; 3253 bias-pull-up;
3592 }; 3254 };
3593 3255
3594 cci1_sleep: cci1-slee 3256 cci1_sleep: cci1-sleep-state {
3595 /* SDA, SCL * 3257 /* SDA, SCL */
3596 pins = "gpio1 3258 pins = "gpio112", "gpio113";
3597 function = "c 3259 function = "cci_i2c";
3598 drive-strengt 3260 drive-strength = <2>;
3599 bias-pull-dow 3261 bias-pull-down;
3600 }; 3262 };
3601 3263
3602 cci2_default: cci2-de 3264 cci2_default: cci2-default-state {
3603 /* SDA, SCL * 3265 /* SDA, SCL */
3604 pins = "gpio1 3266 pins = "gpio114", "gpio115";
3605 function = "c 3267 function = "cci_i2c";
3606 drive-strengt 3268 drive-strength = <2>;
3607 bias-pull-up; 3269 bias-pull-up;
3608 }; 3270 };
3609 3271
3610 cci2_sleep: cci2-slee 3272 cci2_sleep: cci2-sleep-state {
3611 /* SDA, SCL * 3273 /* SDA, SCL */
3612 pins = "gpio1 3274 pins = "gpio114", "gpio115";
3613 function = "c 3275 function = "cci_i2c";
3614 drive-strengt 3276 drive-strength = <2>;
3615 bias-pull-dow 3277 bias-pull-down;
3616 }; 3278 };
3617 3279
3618 cci3_default: cci3-de 3280 cci3_default: cci3-default-state {
3619 /* SDA, SCL * 3281 /* SDA, SCL */
3620 pins = "gpio2 3282 pins = "gpio208", "gpio209";
3621 function = "c 3283 function = "cci_i2c";
3622 drive-strengt 3284 drive-strength = <2>;
3623 bias-pull-up; 3285 bias-pull-up;
3624 }; 3286 };
3625 3287
3626 cci3_sleep: cci3-slee 3288 cci3_sleep: cci3-sleep-state {
3627 /* SDA, SCL * 3289 /* SDA, SCL */
3628 pins = "gpio2 3290 pins = "gpio208", "gpio209";
3629 function = "c 3291 function = "cci_i2c";
3630 drive-strengt 3292 drive-strength = <2>;
3631 bias-pull-dow 3293 bias-pull-down;
3632 }; 3294 };
3633 3295
3634 pcie0_default_state: 3296 pcie0_default_state: pcie0-default-state {
3635 perst-pins { 3297 perst-pins {
3636 pins 3298 pins = "gpio94";
3637 funct 3299 function = "gpio";
3638 drive 3300 drive-strength = <2>;
3639 bias- 3301 bias-pull-down;
3640 }; 3302 };
3641 3303
3642 clkreq-pins { 3304 clkreq-pins {
3643 pins 3305 pins = "gpio95";
3644 funct 3306 function = "pcie0_clkreqn";
3645 drive 3307 drive-strength = <2>;
3646 bias- 3308 bias-pull-up;
3647 }; 3309 };
3648 3310
3649 wake-pins { 3311 wake-pins {
3650 pins 3312 pins = "gpio96";
3651 funct 3313 function = "gpio";
3652 drive 3314 drive-strength = <2>;
3653 bias- 3315 bias-pull-up;
3654 }; 3316 };
3655 }; 3317 };
3656 3318
3657 pcie1_default_state: 3319 pcie1_default_state: pcie1-default-state {
3658 perst-pins { 3320 perst-pins {
3659 pins 3321 pins = "gpio97";
3660 funct 3322 function = "gpio";
3661 drive 3323 drive-strength = <2>;
3662 bias- 3324 bias-pull-down;
3663 }; 3325 };
3664 3326
3665 clkreq-pins { 3327 clkreq-pins {
3666 pins 3328 pins = "gpio98";
3667 funct 3329 function = "pcie1_clkreqn";
3668 drive 3330 drive-strength = <2>;
3669 bias- 3331 bias-pull-up;
3670 }; 3332 };
3671 3333
3672 wake-pins { 3334 wake-pins {
3673 pins 3335 pins = "gpio99";
3674 funct 3336 function = "gpio";
3675 drive 3337 drive-strength = <2>;
3676 bias- 3338 bias-pull-up;
3677 }; 3339 };
3678 }; 3340 };
3679 3341
3680 qup_i2c0_data_clk: qu 3342 qup_i2c0_data_clk: qup-i2c0-data-clk-state {
3681 pins = "gpio0 3343 pins = "gpio0", "gpio1";
3682 function = "q 3344 function = "qup0";
3683 }; 3345 };
3684 3346
3685 qup_i2c1_data_clk: qu 3347 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
3686 pins = "gpio4 3348 pins = "gpio4", "gpio5";
3687 function = "q 3349 function = "qup1";
3688 }; 3350 };
3689 3351
3690 qup_i2c2_data_clk: qu 3352 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
3691 pins = "gpio8 3353 pins = "gpio8", "gpio9";
3692 function = "q 3354 function = "qup2";
3693 }; 3355 };
3694 3356
3695 qup_i2c3_data_clk: qu 3357 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
3696 pins = "gpio1 3358 pins = "gpio12", "gpio13";
3697 function = "q 3359 function = "qup3";
3698 }; 3360 };
3699 3361
3700 qup_i2c4_data_clk: qu 3362 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
3701 pins = "gpio1 3363 pins = "gpio16", "gpio17";
3702 function = "q 3364 function = "qup4";
3703 }; 3365 };
3704 3366
3705 qup_i2c5_data_clk: qu 3367 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
3706 pins = "gpio2 3368 pins = "gpio206", "gpio207";
3707 function = "q 3369 function = "qup5";
3708 }; 3370 };
3709 3371
3710 qup_i2c6_data_clk: qu 3372 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
3711 pins = "gpio2 3373 pins = "gpio20", "gpio21";
3712 function = "q 3374 function = "qup6";
3713 }; 3375 };
3714 3376
3715 qup_i2c8_data_clk: qu 3377 qup_i2c8_data_clk: qup-i2c8-data-clk-state {
3716 pins = "gpio2 3378 pins = "gpio28", "gpio29";
3717 function = "q 3379 function = "qup8";
3718 }; 3380 };
3719 3381
3720 qup_i2c9_data_clk: qu 3382 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
3721 pins = "gpio3 3383 pins = "gpio32", "gpio33";
3722 function = "q 3384 function = "qup9";
3723 }; 3385 };
3724 3386
3725 qup_i2c10_data_clk: q 3387 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
3726 pins = "gpio3 3388 pins = "gpio36", "gpio37";
3727 function = "q 3389 function = "qup10";
3728 }; 3390 };
3729 3391
3730 qup_i2c11_data_clk: q 3392 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
3731 pins = "gpio4 3393 pins = "gpio40", "gpio41";
3732 function = "q 3394 function = "qup11";
3733 }; 3395 };
3734 3396
3735 qup_i2c12_data_clk: q 3397 qup_i2c12_data_clk: qup-i2c12-data-clk-state {
3736 pins = "gpio4 3398 pins = "gpio44", "gpio45";
3737 function = "q 3399 function = "qup12";
3738 }; 3400 };
3739 3401
3740 qup_i2c13_data_clk: q 3402 qup_i2c13_data_clk: qup-i2c13-data-clk-state {
3741 pins = "gpio4 3403 pins = "gpio48", "gpio49";
3742 function = "q 3404 function = "qup13";
3743 drive-strengt 3405 drive-strength = <2>;
3744 bias-pull-up; 3406 bias-pull-up;
3745 }; 3407 };
3746 3408
3747 qup_i2c14_data_clk: q 3409 qup_i2c14_data_clk: qup-i2c14-data-clk-state {
3748 pins = "gpio5 3410 pins = "gpio52", "gpio53";
3749 function = "q 3411 function = "qup14";
3750 drive-strengt 3412 drive-strength = <2>;
3751 bias-pull-up; 3413 bias-pull-up;
3752 }; 3414 };
3753 3415
3754 qup_i2c15_data_clk: q 3416 qup_i2c15_data_clk: qup-i2c15-data-clk-state {
3755 pins = "gpio5 3417 pins = "gpio56", "gpio57";
3756 function = "q 3418 function = "qup15";
3757 }; 3419 };
3758 3420
3759 qup_i2c16_data_clk: q 3421 qup_i2c16_data_clk: qup-i2c16-data-clk-state {
3760 pins = "gpio6 3422 pins = "gpio60", "gpio61";
3761 function = "q 3423 function = "qup16";
3762 }; 3424 };
3763 3425
3764 qup_i2c17_data_clk: q 3426 qup_i2c17_data_clk: qup-i2c17-data-clk-state {
3765 pins = "gpio6 3427 pins = "gpio64", "gpio65";
3766 function = "q 3428 function = "qup17";
3767 }; 3429 };
3768 3430
3769 qup_i2c18_data_clk: q 3431 qup_i2c18_data_clk: qup-i2c18-data-clk-state {
3770 pins = "gpio6 3432 pins = "gpio68", "gpio69";
3771 function = "q 3433 function = "qup18";
3772 }; 3434 };
3773 3435
3774 qup_i2c19_data_clk: q 3436 qup_i2c19_data_clk: qup-i2c19-data-clk-state {
3775 pins = "gpio7 3437 pins = "gpio72", "gpio73";
3776 function = "q 3438 function = "qup19";
3777 }; 3439 };
3778 3440
3779 qup_i2c20_data_clk: q 3441 qup_i2c20_data_clk: qup-i2c20-data-clk-state {
3780 pins = "gpio7 3442 pins = "gpio76", "gpio77";
3781 function = "q 3443 function = "qup20";
3782 }; 3444 };
3783 3445
3784 qup_i2c21_data_clk: q 3446 qup_i2c21_data_clk: qup-i2c21-data-clk-state {
3785 pins = "gpio8 3447 pins = "gpio80", "gpio81";
3786 function = "q 3448 function = "qup21";
3787 }; 3449 };
3788 3450
3789 qup_spi0_cs: qup-spi0 3451 qup_spi0_cs: qup-spi0-cs-state {
3790 pins = "gpio3 3452 pins = "gpio3";
3791 function = "q 3453 function = "qup0";
3792 }; 3454 };
3793 3455
3794 qup_spi0_data_clk: qu 3456 qup_spi0_data_clk: qup-spi0-data-clk-state {
3795 pins = "gpio0 3457 pins = "gpio0", "gpio1", "gpio2";
3796 function = "q 3458 function = "qup0";
3797 }; 3459 };
3798 3460
3799 qup_spi1_cs: qup-spi1 3461 qup_spi1_cs: qup-spi1-cs-state {
3800 pins = "gpio7 3462 pins = "gpio7";
3801 function = "q 3463 function = "qup1";
3802 }; 3464 };
3803 3465
3804 qup_spi1_data_clk: qu 3466 qup_spi1_data_clk: qup-spi1-data-clk-state {
3805 pins = "gpio4 3467 pins = "gpio4", "gpio5", "gpio6";
3806 function = "q 3468 function = "qup1";
3807 }; 3469 };
3808 3470
3809 qup_spi2_cs: qup-spi2 3471 qup_spi2_cs: qup-spi2-cs-state {
3810 pins = "gpio1 3472 pins = "gpio11";
3811 function = "q 3473 function = "qup2";
3812 }; 3474 };
3813 3475
3814 qup_spi2_data_clk: qu 3476 qup_spi2_data_clk: qup-spi2-data-clk-state {
3815 pins = "gpio8 3477 pins = "gpio8", "gpio9", "gpio10";
3816 function = "q 3478 function = "qup2";
3817 }; 3479 };
3818 3480
3819 qup_spi3_cs: qup-spi3 3481 qup_spi3_cs: qup-spi3-cs-state {
3820 pins = "gpio1 3482 pins = "gpio15";
3821 function = "q 3483 function = "qup3";
3822 }; 3484 };
3823 3485
3824 qup_spi3_data_clk: qu 3486 qup_spi3_data_clk: qup-spi3-data-clk-state {
3825 pins = "gpio1 3487 pins = "gpio12", "gpio13", "gpio14";
3826 function = "q 3488 function = "qup3";
3827 }; 3489 };
3828 3490
3829 qup_spi4_cs: qup-spi4 3491 qup_spi4_cs: qup-spi4-cs-state {
3830 pins = "gpio1 3492 pins = "gpio19";
3831 function = "q 3493 function = "qup4";
3832 drive-strengt 3494 drive-strength = <6>;
3833 bias-disable; 3495 bias-disable;
3834 }; 3496 };
3835 3497
3836 qup_spi4_data_clk: qu 3498 qup_spi4_data_clk: qup-spi4-data-clk-state {
3837 pins = "gpio1 3499 pins = "gpio16", "gpio17", "gpio18";
3838 function = "q 3500 function = "qup4";
3839 }; 3501 };
3840 3502
3841 qup_spi5_cs: qup-spi5 3503 qup_spi5_cs: qup-spi5-cs-state {
3842 pins = "gpio8 3504 pins = "gpio85";
3843 function = "q 3505 function = "qup5";
3844 }; 3506 };
3845 3507
3846 qup_spi5_data_clk: qu 3508 qup_spi5_data_clk: qup-spi5-data-clk-state {
3847 pins = "gpio2 3509 pins = "gpio206", "gpio207", "gpio84";
3848 function = "q 3510 function = "qup5";
3849 }; 3511 };
3850 3512
3851 qup_spi6_cs: qup-spi6 3513 qup_spi6_cs: qup-spi6-cs-state {
3852 pins = "gpio2 3514 pins = "gpio23";
3853 function = "q 3515 function = "qup6";
3854 }; 3516 };
3855 3517
3856 qup_spi6_data_clk: qu 3518 qup_spi6_data_clk: qup-spi6-data-clk-state {
3857 pins = "gpio2 3519 pins = "gpio20", "gpio21", "gpio22";
3858 function = "q 3520 function = "qup6";
3859 }; 3521 };
3860 3522
3861 qup_spi8_cs: qup-spi8 3523 qup_spi8_cs: qup-spi8-cs-state {
3862 pins = "gpio3 3524 pins = "gpio31";
3863 function = "q 3525 function = "qup8";
3864 }; 3526 };
3865 3527
3866 qup_spi8_data_clk: qu 3528 qup_spi8_data_clk: qup-spi8-data-clk-state {
3867 pins = "gpio2 3529 pins = "gpio28", "gpio29", "gpio30";
3868 function = "q 3530 function = "qup8";
3869 }; 3531 };
3870 3532
3871 qup_spi9_cs: qup-spi9 3533 qup_spi9_cs: qup-spi9-cs-state {
3872 pins = "gpio3 3534 pins = "gpio35";
3873 function = "q 3535 function = "qup9";
3874 }; 3536 };
3875 3537
3876 qup_spi9_data_clk: qu 3538 qup_spi9_data_clk: qup-spi9-data-clk-state {
3877 pins = "gpio3 3539 pins = "gpio32", "gpio33", "gpio34";
3878 function = "q 3540 function = "qup9";
3879 }; 3541 };
3880 3542
3881 qup_spi10_cs: qup-spi 3543 qup_spi10_cs: qup-spi10-cs-state {
3882 pins = "gpio3 3544 pins = "gpio39";
3883 function = "q 3545 function = "qup10";
3884 }; 3546 };
3885 3547
3886 qup_spi10_data_clk: q 3548 qup_spi10_data_clk: qup-spi10-data-clk-state {
3887 pins = "gpio3 3549 pins = "gpio36", "gpio37", "gpio38";
3888 function = "q 3550 function = "qup10";
3889 }; 3551 };
3890 3552
3891 qup_spi11_cs: qup-spi 3553 qup_spi11_cs: qup-spi11-cs-state {
3892 pins = "gpio4 3554 pins = "gpio43";
3893 function = "q 3555 function = "qup11";
3894 }; 3556 };
3895 3557
3896 qup_spi11_data_clk: q 3558 qup_spi11_data_clk: qup-spi11-data-clk-state {
3897 pins = "gpio4 3559 pins = "gpio40", "gpio41", "gpio42";
3898 function = "q 3560 function = "qup11";
3899 }; 3561 };
3900 3562
3901 qup_spi12_cs: qup-spi 3563 qup_spi12_cs: qup-spi12-cs-state {
3902 pins = "gpio4 3564 pins = "gpio47";
3903 function = "q 3565 function = "qup12";
3904 }; 3566 };
3905 3567
3906 qup_spi12_data_clk: q 3568 qup_spi12_data_clk: qup-spi12-data-clk-state {
3907 pins = "gpio4 3569 pins = "gpio44", "gpio45", "gpio46";
3908 function = "q 3570 function = "qup12";
3909 }; 3571 };
3910 3572
3911 qup_spi13_cs: qup-spi 3573 qup_spi13_cs: qup-spi13-cs-state {
3912 pins = "gpio5 3574 pins = "gpio51";
3913 function = "q 3575 function = "qup13";
3914 }; 3576 };
3915 3577
3916 qup_spi13_data_clk: q 3578 qup_spi13_data_clk: qup-spi13-data-clk-state {
3917 pins = "gpio4 3579 pins = "gpio48", "gpio49", "gpio50";
3918 function = "q 3580 function = "qup13";
3919 }; 3581 };
3920 3582
3921 qup_spi14_cs: qup-spi 3583 qup_spi14_cs: qup-spi14-cs-state {
3922 pins = "gpio5 3584 pins = "gpio55";
3923 function = "q 3585 function = "qup14";
3924 }; 3586 };
3925 3587
3926 qup_spi14_data_clk: q 3588 qup_spi14_data_clk: qup-spi14-data-clk-state {
3927 pins = "gpio5 3589 pins = "gpio52", "gpio53", "gpio54";
3928 function = "q 3590 function = "qup14";
3929 }; 3591 };
3930 3592
3931 qup_spi15_cs: qup-spi 3593 qup_spi15_cs: qup-spi15-cs-state {
3932 pins = "gpio5 3594 pins = "gpio59";
3933 function = "q 3595 function = "qup15";
3934 }; 3596 };
3935 3597
3936 qup_spi15_data_clk: q 3598 qup_spi15_data_clk: qup-spi15-data-clk-state {
3937 pins = "gpio5 3599 pins = "gpio56", "gpio57", "gpio58";
3938 function = "q 3600 function = "qup15";
3939 }; 3601 };
3940 3602
3941 qup_spi16_cs: qup-spi 3603 qup_spi16_cs: qup-spi16-cs-state {
3942 pins = "gpio6 3604 pins = "gpio63";
3943 function = "q 3605 function = "qup16";
3944 }; 3606 };
3945 3607
3946 qup_spi16_data_clk: q 3608 qup_spi16_data_clk: qup-spi16-data-clk-state {
3947 pins = "gpio6 3609 pins = "gpio60", "gpio61", "gpio62";
3948 function = "q 3610 function = "qup16";
3949 }; 3611 };
3950 3612
3951 qup_spi17_cs: qup-spi 3613 qup_spi17_cs: qup-spi17-cs-state {
3952 pins = "gpio6 3614 pins = "gpio67";
3953 function = "q 3615 function = "qup17";
3954 }; 3616 };
3955 3617
3956 qup_spi17_data_clk: q 3618 qup_spi17_data_clk: qup-spi17-data-clk-state {
3957 pins = "gpio6 3619 pins = "gpio64", "gpio65", "gpio66";
3958 function = "q 3620 function = "qup17";
3959 }; 3621 };
3960 3622
3961 qup_spi18_cs: qup-spi 3623 qup_spi18_cs: qup-spi18-cs-state {
3962 pins = "gpio7 3624 pins = "gpio71";
3963 function = "q 3625 function = "qup18";
3964 drive-strengt 3626 drive-strength = <6>;
3965 bias-disable; 3627 bias-disable;
3966 }; 3628 };
3967 3629
3968 qup_spi18_data_clk: q 3630 qup_spi18_data_clk: qup-spi18-data-clk-state {
3969 pins = "gpio6 3631 pins = "gpio68", "gpio69", "gpio70";
3970 function = "q 3632 function = "qup18";
3971 drive-strengt 3633 drive-strength = <6>;
3972 bias-disable; 3634 bias-disable;
3973 }; 3635 };
3974 3636
3975 qup_spi19_cs: qup-spi 3637 qup_spi19_cs: qup-spi19-cs-state {
3976 pins = "gpio7 3638 pins = "gpio75";
3977 function = "q 3639 function = "qup19";
3978 drive-strengt 3640 drive-strength = <6>;
3979 bias-disable; 3641 bias-disable;
3980 }; 3642 };
3981 3643
3982 qup_spi19_data_clk: q 3644 qup_spi19_data_clk: qup-spi19-data-clk-state {
3983 pins = "gpio7 3645 pins = "gpio72", "gpio73", "gpio74";
3984 function = "q 3646 function = "qup19";
3985 drive-strengt 3647 drive-strength = <6>;
3986 bias-disable; 3648 bias-disable;
3987 }; 3649 };
3988 3650
3989 qup_spi20_cs: qup-spi 3651 qup_spi20_cs: qup-spi20-cs-state {
3990 pins = "gpio7 3652 pins = "gpio79";
3991 function = "q 3653 function = "qup20";
3992 }; 3654 };
3993 3655
3994 qup_spi20_data_clk: q 3656 qup_spi20_data_clk: qup-spi20-data-clk-state {
3995 pins = "gpio7 3657 pins = "gpio76", "gpio77", "gpio78";
3996 function = "q 3658 function = "qup20";
3997 }; 3659 };
3998 3660
3999 qup_spi21_cs: qup-spi 3661 qup_spi21_cs: qup-spi21-cs-state {
4000 pins = "gpio8 3662 pins = "gpio83";
4001 function = "q 3663 function = "qup21";
4002 }; 3664 };
4003 3665
4004 qup_spi21_data_clk: q 3666 qup_spi21_data_clk: qup-spi21-data-clk-state {
4005 pins = "gpio8 3667 pins = "gpio80", "gpio81", "gpio82";
4006 function = "q 3668 function = "qup21";
4007 }; 3669 };
4008 3670
4009 qup_uart7_rx: qup-uar 3671 qup_uart7_rx: qup-uart7-rx-state {
4010 pins = "gpio2 3672 pins = "gpio26";
4011 function = "q 3673 function = "qup7";
4012 drive-strengt 3674 drive-strength = <2>;
4013 bias-disable; 3675 bias-disable;
4014 }; 3676 };
4015 3677
4016 qup_uart7_tx: qup-uar 3678 qup_uart7_tx: qup-uart7-tx-state {
4017 pins = "gpio2 3679 pins = "gpio27";
4018 function = "q 3680 function = "qup7";
4019 drive-strengt 3681 drive-strength = <2>;
4020 bias-disable; 3682 bias-disable;
4021 }; 3683 };
4022 3684
4023 qup_uart20_default: q 3685 qup_uart20_default: qup-uart20-default-state {
4024 pins = "gpio7 3686 pins = "gpio76", "gpio77", "gpio78", "gpio79";
4025 function = "q 3687 function = "qup20";
4026 }; 3688 };
4027 }; 3689 };
4028 3690
4029 lpass_tlmm: pinctrl@3440000 { 3691 lpass_tlmm: pinctrl@3440000 {
4030 compatible = "qcom,sm 3692 compatible = "qcom,sm8450-lpass-lpi-pinctrl";
4031 reg = <0 0x03440000 0 3693 reg = <0 0x03440000 0x0 0x20000>,
4032 <0 0x034d0000 0 3694 <0 0x034d0000 0x0 0x10000>;
4033 gpio-controller; 3695 gpio-controller;
4034 #gpio-cells = <2>; 3696 #gpio-cells = <2>;
4035 gpio-ranges = <&lpass 3697 gpio-ranges = <&lpass_tlmm 0 0 23>;
4036 3698
4037 clocks = <&q6prmcc LP 3699 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
4038 <&q6prmcc LP 3700 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
4039 clock-names = "core", 3701 clock-names = "core", "audio";
4040 3702
4041 tx_swr_active: tx-swr 3703 tx_swr_active: tx-swr-active-state {
4042 clk-pins { 3704 clk-pins {
4043 pins 3705 pins = "gpio0";
4044 funct 3706 function = "swr_tx_clk";
4045 drive 3707 drive-strength = <2>;
4046 slew- 3708 slew-rate = <1>;
4047 bias- 3709 bias-disable;
4048 }; 3710 };
4049 3711
4050 data-pins { 3712 data-pins {
4051 pins 3713 pins = "gpio1", "gpio2", "gpio14";
4052 funct 3714 function = "swr_tx_data";
4053 drive 3715 drive-strength = <2>;
4054 slew- 3716 slew-rate = <1>;
4055 bias- 3717 bias-bus-hold;
4056 }; 3718 };
4057 }; 3719 };
4058 3720
4059 rx_swr_active: rx-swr 3721 rx_swr_active: rx-swr-active-state {
4060 clk-pins { 3722 clk-pins {
4061 pins 3723 pins = "gpio3";
4062 funct 3724 function = "swr_rx_clk";
4063 drive 3725 drive-strength = <2>;
4064 slew- 3726 slew-rate = <1>;
4065 bias- 3727 bias-disable;
4066 }; 3728 };
4067 3729
4068 data-pins { 3730 data-pins {
4069 pins 3731 pins = "gpio4", "gpio5";
4070 funct 3732 function = "swr_rx_data";
4071 drive 3733 drive-strength = <2>;
4072 slew- 3734 slew-rate = <1>;
4073 bias- 3735 bias-bus-hold;
4074 }; 3736 };
4075 }; 3737 };
4076 3738
4077 dmic01_default: dmic0 3739 dmic01_default: dmic01-default-state {
4078 clk-pins { 3740 clk-pins {
4079 pins 3741 pins = "gpio6";
4080 funct 3742 function = "dmic1_clk";
4081 drive 3743 drive-strength = <8>;
4082 outpu 3744 output-high;
4083 }; 3745 };
4084 3746
4085 data-pins { 3747 data-pins {
4086 pins 3748 pins = "gpio7";
4087 funct 3749 function = "dmic1_data";
4088 drive 3750 drive-strength = <8>;
4089 }; 3751 };
4090 }; 3752 };
4091 3753
4092 dmic23_default: dmic2 !! 3754 dmic02_default: dmic02-default-state {
4093 clk-pins { 3755 clk-pins {
4094 pins 3756 pins = "gpio8";
4095 funct 3757 function = "dmic2_clk";
4096 drive 3758 drive-strength = <8>;
4097 outpu 3759 output-high;
4098 }; 3760 };
4099 3761
4100 data-pins { 3762 data-pins {
4101 pins 3763 pins = "gpio9";
4102 funct 3764 function = "dmic2_data";
4103 drive 3765 drive-strength = <8>;
4104 }; 3766 };
4105 }; 3767 };
4106 3768
4107 wsa_swr_active: wsa-s 3769 wsa_swr_active: wsa-swr-active-state {
4108 clk-pins { 3770 clk-pins {
4109 pins 3771 pins = "gpio10";
4110 funct 3772 function = "wsa_swr_clk";
4111 drive 3773 drive-strength = <2>;
4112 slew- 3774 slew-rate = <1>;
4113 bias- 3775 bias-disable;
4114 }; 3776 };
4115 3777
4116 data-pins { 3778 data-pins {
4117 pins 3779 pins = "gpio11";
4118 funct 3780 function = "wsa_swr_data";
4119 drive 3781 drive-strength = <2>;
4120 slew- 3782 slew-rate = <1>;
4121 bias- 3783 bias-bus-hold;
4122 }; 3784 };
4123 }; 3785 };
4124 3786
4125 wsa2_swr_active: wsa2 3787 wsa2_swr_active: wsa2-swr-active-state {
4126 clk-pins { 3788 clk-pins {
4127 pins 3789 pins = "gpio15";
4128 funct 3790 function = "wsa2_swr_clk";
4129 drive 3791 drive-strength = <2>;
4130 slew- 3792 slew-rate = <1>;
4131 bias- 3793 bias-disable;
4132 }; 3794 };
4133 3795
4134 data-pins { 3796 data-pins {
4135 pins 3797 pins = "gpio16";
4136 funct 3798 function = "wsa2_swr_data";
4137 drive 3799 drive-strength = <2>;
4138 slew- 3800 slew-rate = <1>;
4139 bias- 3801 bias-bus-hold;
4140 }; 3802 };
4141 }; 3803 };
4142 }; 3804 };
4143 3805
4144 sram@146aa000 { 3806 sram@146aa000 {
4145 compatible = "qcom,sm 3807 compatible = "qcom,sm8450-imem", "syscon", "simple-mfd";
4146 reg = <0 0x146aa000 0 3808 reg = <0 0x146aa000 0 0x1000>;
4147 ranges = <0 0 0x146aa 3809 ranges = <0 0 0x146aa000 0x1000>;
4148 3810
4149 #address-cells = <1>; 3811 #address-cells = <1>;
4150 #size-cells = <1>; 3812 #size-cells = <1>;
4151 3813
4152 pil-reloc@94c { 3814 pil-reloc@94c {
4153 compatible = 3815 compatible = "qcom,pil-reloc-info";
4154 reg = <0x94c 3816 reg = <0x94c 0xc8>;
4155 }; 3817 };
4156 }; 3818 };
4157 3819
4158 apps_smmu: iommu@15000000 { 3820 apps_smmu: iommu@15000000 {
4159 compatible = "qcom,sm 3821 compatible = "qcom,sm8450-smmu-500", "arm,mmu-500";
4160 reg = <0 0x15000000 0 3822 reg = <0 0x15000000 0 0x100000>;
4161 #iommu-cells = <2>; 3823 #iommu-cells = <2>;
4162 #global-interrupts = 3824 #global-interrupts = <1>;
4163 interrupts = <GIC_SPI 3825 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
4164 <GIC_SPI 3826 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
4165 <GIC_SPI 3827 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
4166 <GIC_SPI 3828 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
4167 <GIC_SPI 3829 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
4168 <GIC_SPI 3830 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
4169 <GIC_SPI 3831 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
4170 <GIC_SPI 3832 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
4171 <GIC_SPI 3833 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
4172 <GIC_SPI 3834 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
4173 <GIC_SPI 3835 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
4174 <GIC_SPI 3836 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
4175 <GIC_SPI 3837 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
4176 <GIC_SPI 3838 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
4177 <GIC_SPI 3839 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
4178 <GIC_SPI 3840 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
4179 <GIC_SPI 3841 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
4180 <GIC_SPI 3842 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
4181 <GIC_SPI 3843 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
4182 <GIC_SPI 3844 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
4183 <GIC_SPI 3845 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
4184 <GIC_SPI 3846 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
4185 <GIC_SPI 3847 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
4186 <GIC_SPI 3848 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
4187 <GIC_SPI 3849 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
4188 <GIC_SPI 3850 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
4189 <GIC_SPI 3851 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
4190 <GIC_SPI 3852 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
4191 <GIC_SPI 3853 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
4192 <GIC_SPI 3854 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
4193 <GIC_SPI 3855 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
4194 <GIC_SPI 3856 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
4195 <GIC_SPI 3857 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
4196 <GIC_SPI 3858 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
4197 <GIC_SPI 3859 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
4198 <GIC_SPI 3860 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
4199 <GIC_SPI 3861 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
4200 <GIC_SPI 3862 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
4201 <GIC_SPI 3863 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
4202 <GIC_SPI 3864 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
4203 <GIC_SPI 3865 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
4204 <GIC_SPI 3866 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
4205 <GIC_SPI 3867 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
4206 <GIC_SPI 3868 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
4207 <GIC_SPI 3869 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
4208 <GIC_SPI 3870 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
4209 <GIC_SPI 3871 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
4210 <GIC_SPI 3872 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
4211 <GIC_SPI 3873 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
4212 <GIC_SPI 3874 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
4213 <GIC_SPI 3875 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
4214 <GIC_SPI 3876 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
4215 <GIC_SPI 3877 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
4216 <GIC_SPI 3878 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
4217 <GIC_SPI 3879 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
4218 <GIC_SPI 3880 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
4219 <GIC_SPI 3881 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
4220 <GIC_SPI 3882 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
4221 <GIC_SPI 3883 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
4222 <GIC_SPI 3884 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
4223 <GIC_SPI 3885 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
4224 <GIC_SPI 3886 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
4225 <GIC_SPI 3887 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
4226 <GIC_SPI 3888 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
4227 <GIC_SPI 3889 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
4228 <GIC_SPI 3890 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
4229 <GIC_SPI 3891 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
4230 <GIC_SPI 3892 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
4231 <GIC_SPI 3893 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
4232 <GIC_SPI 3894 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
4233 <GIC_SPI 3895 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
4234 <GIC_SPI 3896 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
4235 <GIC_SPI 3897 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
4236 <GIC_SPI 3898 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
4237 <GIC_SPI 3899 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
4238 <GIC_SPI 3900 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
4239 <GIC_SPI 3901 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
4240 <GIC_SPI 3902 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
4241 <GIC_SPI 3903 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
4242 <GIC_SPI 3904 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
4243 <GIC_SPI 3905 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
4244 <GIC_SPI 3906 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
4245 <GIC_SPI 3907 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
4246 <GIC_SPI 3908 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
4247 <GIC_SPI 3909 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
4248 <GIC_SPI 3910 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
4249 <GIC_SPI 3911 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
4250 <GIC_SPI 3912 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
4251 <GIC_SPI 3913 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
4252 <GIC_SPI 3914 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
4253 <GIC_SPI 3915 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
4254 <GIC_SPI 3916 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
4255 <GIC_SPI 3917 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
4256 <GIC_SPI 3918 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
4257 <GIC_SPI 3919 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
4258 <GIC_SPI 3920 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
4259 <GIC_SPI 3921 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>;
4260 }; 3922 };
4261 3923
4262 intc: interrupt-controller@17 3924 intc: interrupt-controller@17100000 {
4263 compatible = "arm,gic 3925 compatible = "arm,gic-v3";
4264 #interrupt-cells = <3 3926 #interrupt-cells = <3>;
4265 interrupt-controller; 3927 interrupt-controller;
4266 #redistributor-region 3928 #redistributor-regions = <1>;
4267 redistributor-stride 3929 redistributor-stride = <0x0 0x40000>;
4268 reg = <0x0 0x17100000 3930 reg = <0x0 0x17100000 0x0 0x10000>, /* GICD */
4269 <0x0 0x17180000 3931 <0x0 0x17180000 0x0 0x200000>; /* GICR * 8 */
4270 interrupts = <GIC_PPI 3932 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
4271 #address-cells = <2>; 3933 #address-cells = <2>;
4272 #size-cells = <2>; 3934 #size-cells = <2>;
4273 ranges; 3935 ranges;
4274 3936
4275 gic_its: msi-controll 3937 gic_its: msi-controller@17140000 {
4276 compatible = 3938 compatible = "arm,gic-v3-its";
4277 reg = <0x0 0x 3939 reg = <0x0 0x17140000 0x0 0x20000>;
4278 msi-controlle 3940 msi-controller;
4279 #msi-cells = 3941 #msi-cells = <1>;
4280 }; 3942 };
4281 }; 3943 };
4282 3944
4283 timer@17420000 { 3945 timer@17420000 {
4284 compatible = "arm,arm 3946 compatible = "arm,armv7-timer-mem";
4285 #address-cells = <1>; 3947 #address-cells = <1>;
4286 #size-cells = <1>; 3948 #size-cells = <1>;
4287 ranges = <0 0 0 0x200 3949 ranges = <0 0 0 0x20000000>;
4288 reg = <0x0 0x17420000 3950 reg = <0x0 0x17420000 0x0 0x1000>;
4289 clock-frequency = <19 3951 clock-frequency = <19200000>;
4290 3952
4291 frame@17421000 { 3953 frame@17421000 {
4292 frame-number 3954 frame-number = <0>;
4293 interrupts = 3955 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
4294 3956 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
4295 reg = <0x1742 3957 reg = <0x17421000 0x1000>,
4296 <0x1742 3958 <0x17422000 0x1000>;
4297 }; 3959 };
4298 3960
4299 frame@17423000 { 3961 frame@17423000 {
4300 frame-number 3962 frame-number = <1>;
4301 interrupts = 3963 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
4302 reg = <0x1742 3964 reg = <0x17423000 0x1000>;
4303 status = "dis 3965 status = "disabled";
4304 }; 3966 };
4305 3967
4306 frame@17425000 { 3968 frame@17425000 {
4307 frame-number 3969 frame-number = <2>;
4308 interrupts = 3970 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
4309 reg = <0x1742 3971 reg = <0x17425000 0x1000>;
4310 status = "dis 3972 status = "disabled";
4311 }; 3973 };
4312 3974
4313 frame@17427000 { 3975 frame@17427000 {
4314 frame-number 3976 frame-number = <3>;
4315 interrupts = 3977 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
4316 reg = <0x1742 3978 reg = <0x17427000 0x1000>;
4317 status = "dis 3979 status = "disabled";
4318 }; 3980 };
4319 3981
4320 frame@17429000 { 3982 frame@17429000 {
4321 frame-number 3983 frame-number = <4>;
4322 interrupts = 3984 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
4323 reg = <0x1742 3985 reg = <0x17429000 0x1000>;
4324 status = "dis 3986 status = "disabled";
4325 }; 3987 };
4326 3988
4327 frame@1742b000 { 3989 frame@1742b000 {
4328 frame-number 3990 frame-number = <5>;
4329 interrupts = 3991 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
4330 reg = <0x1742 3992 reg = <0x1742b000 0x1000>;
4331 status = "dis 3993 status = "disabled";
4332 }; 3994 };
4333 3995
4334 frame@1742d000 { 3996 frame@1742d000 {
4335 frame-number 3997 frame-number = <6>;
4336 interrupts = 3998 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
4337 reg = <0x1742 3999 reg = <0x1742d000 0x1000>;
4338 status = "dis 4000 status = "disabled";
4339 }; 4001 };
4340 }; 4002 };
4341 4003
4342 apps_rsc: rsc@17a00000 { 4004 apps_rsc: rsc@17a00000 {
4343 label = "apps_rsc"; 4005 label = "apps_rsc";
4344 compatible = "qcom,rp 4006 compatible = "qcom,rpmh-rsc";
4345 reg = <0x0 0x17a00000 4007 reg = <0x0 0x17a00000 0x0 0x10000>,
4346 <0x0 0x17a10000 4008 <0x0 0x17a10000 0x0 0x10000>,
4347 <0x0 0x17a20000 4009 <0x0 0x17a20000 0x0 0x10000>,
4348 <0x0 0x17a30000 4010 <0x0 0x17a30000 0x0 0x10000>;
4349 reg-names = "drv-0", 4011 reg-names = "drv-0", "drv-1", "drv-2", "drv-3";
4350 interrupts = <GIC_SPI 4012 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
4351 <GIC_SPI 4013 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
4352 <GIC_SPI 4014 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
4353 qcom,tcs-offset = <0x 4015 qcom,tcs-offset = <0xd00>;
4354 qcom,drv-id = <2>; 4016 qcom,drv-id = <2>;
4355 qcom,tcs-config = <AC 4017 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
4356 <WA 4018 <WAKE_TCS 2>, <CONTROL_TCS 0>;
4357 power-domains = <&CLU 4019 power-domains = <&CLUSTER_PD>;
4358 4020
4359 apps_bcm_voter: bcm-v 4021 apps_bcm_voter: bcm-voter {
4360 compatible = 4022 compatible = "qcom,bcm-voter";
4361 }; 4023 };
4362 4024
4363 rpmhcc: clock-control 4025 rpmhcc: clock-controller {
4364 compatible = 4026 compatible = "qcom,sm8450-rpmh-clk";
4365 #clock-cells 4027 #clock-cells = <1>;
4366 clock-names = 4028 clock-names = "xo";
4367 clocks = <&xo 4029 clocks = <&xo_board>;
4368 }; 4030 };
4369 4031
4370 rpmhpd: power-control 4032 rpmhpd: power-controller {
4371 compatible = 4033 compatible = "qcom,sm8450-rpmhpd";
4372 #power-domain 4034 #power-domain-cells = <1>;
4373 operating-poi 4035 operating-points-v2 = <&rpmhpd_opp_table>;
4374 4036
4375 rpmhpd_opp_ta 4037 rpmhpd_opp_table: opp-table {
4376 compa 4038 compatible = "operating-points-v2";
4377 4039
4378 rpmhp 4040 rpmhpd_opp_ret: opp1 {
4379 4041 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4380 }; 4042 };
4381 4043
4382 rpmhp 4044 rpmhpd_opp_min_svs: opp2 {
4383 4045 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4384 }; 4046 };
4385 4047
4386 rpmhp 4048 rpmhpd_opp_low_svs_d1: opp3 {
4387 4049 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
4388 }; 4050 };
4389 4051
4390 rpmhp 4052 rpmhpd_opp_low_svs: opp4 {
4391 4053 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4392 }; 4054 };
4393 4055
4394 rpmhp 4056 rpmhpd_opp_low_svs_l1: opp5 {
4395 4057 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
4396 }; 4058 };
4397 4059
4398 rpmhp 4060 rpmhpd_opp_svs: opp6 {
4399 4061 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4400 }; 4062 };
4401 4063
4402 rpmhp 4064 rpmhpd_opp_svs_l0: opp7 {
4403 4065 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
4404 }; 4066 };
4405 4067
4406 rpmhp 4068 rpmhpd_opp_svs_l1: opp8 {
4407 4069 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4408 }; 4070 };
4409 4071
4410 rpmhp 4072 rpmhpd_opp_svs_l2: opp9 {
4411 4073 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
4412 }; 4074 };
4413 4075
4414 rpmhp 4076 rpmhpd_opp_nom: opp10 {
4415 4077 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4416 }; 4078 };
4417 4079
4418 rpmhp 4080 rpmhpd_opp_nom_l1: opp11 {
4419 4081 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4420 }; 4082 };
4421 4083
4422 rpmhp 4084 rpmhpd_opp_nom_l2: opp12 {
4423 4085 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4424 }; 4086 };
4425 4087
4426 rpmhp 4088 rpmhpd_opp_turbo: opp13 {
4427 4089 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4428 }; 4090 };
4429 4091
4430 rpmhp 4092 rpmhpd_opp_turbo_l1: opp14 {
4431 4093 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4432 }; 4094 };
4433 }; 4095 };
4434 }; 4096 };
4435 }; 4097 };
4436 4098
4437 cpufreq_hw: cpufreq@17d91000 4099 cpufreq_hw: cpufreq@17d91000 {
4438 compatible = "qcom,sm 4100 compatible = "qcom,sm8450-cpufreq-epss", "qcom,cpufreq-epss";
4439 reg = <0 0x17d91000 0 4101 reg = <0 0x17d91000 0 0x1000>,
4440 <0 0x17d92000 0 4102 <0 0x17d92000 0 0x1000>,
4441 <0 0x17d93000 0 4103 <0 0x17d93000 0 0x1000>;
4442 reg-names = "freq-dom 4104 reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
4443 clocks = <&rpmhcc RPM 4105 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
4444 clock-names = "xo", " 4106 clock-names = "xo", "alternate";
4445 interrupts = <GIC_SPI 4107 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
4446 <GIC_SPI 4108 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
4447 <GIC_SPI 4109 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
4448 interrupt-names = "dc 4110 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
4449 #freq-domain-cells = 4111 #freq-domain-cells = <1>;
4450 #clock-cells = <1>; 4112 #clock-cells = <1>;
4451 }; 4113 };
4452 4114
4453 gem_noc: interconnect@1910000 4115 gem_noc: interconnect@19100000 {
4454 compatible = "qcom,sm 4116 compatible = "qcom,sm8450-gem-noc";
4455 reg = <0 0x19100000 0 4117 reg = <0 0x19100000 0 0xbb800>;
4456 #interconnect-cells = 4118 #interconnect-cells = <2>;
4457 qcom,bcm-voters = <&a 4119 qcom,bcm-voters = <&apps_bcm_voter>;
4458 }; 4120 };
4459 4121
4460 system-cache-controller@19200 4122 system-cache-controller@19200000 {
4461 compatible = "qcom,sm 4123 compatible = "qcom,sm8450-llcc";
4462 reg = <0 0x19200000 0 4124 reg = <0 0x19200000 0 0x80000>, <0 0x19600000 0 0x80000>,
4463 <0 0x19300000 0 4125 <0 0x19300000 0 0x80000>, <0 0x19700000 0 0x80000>,
4464 <0 0x19a00000 0 !! 4126 <0 0x19a00000 0 0x80000>;
4465 reg-names = "llcc0_ba 4127 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
4466 "llcc3_ba !! 4128 "llcc3_base", "llcc_broadcast_base";
4467 "llcc_bro <<
4468 interrupts = <GIC_SPI 4129 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
4469 }; 4130 };
4470 4131
4471 ufs_mem_hc: ufshc@1d84000 { 4132 ufs_mem_hc: ufshc@1d84000 {
4472 compatible = "qcom,sm 4133 compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
4473 "jedec,u 4134 "jedec,ufs-2.0";
4474 reg = <0 0x01d84000 0 4135 reg = <0 0x01d84000 0 0x3000>;
4475 interrupts = <GIC_SPI 4136 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
4476 phys = <&ufs_mem_phy> !! 4137 phys = <&ufs_mem_phy_lanes>;
4477 phy-names = "ufsphy"; 4138 phy-names = "ufsphy";
4478 lanes-per-direction = 4139 lanes-per-direction = <2>;
4479 #reset-cells = <1>; 4140 #reset-cells = <1>;
4480 resets = <&gcc GCC_UF 4141 resets = <&gcc GCC_UFS_PHY_BCR>;
4481 reset-names = "rst"; 4142 reset-names = "rst";
4482 4143
4483 power-domains = <&gcc 4144 power-domains = <&gcc UFS_PHY_GDSC>;
4484 4145
4485 iommus = <&apps_smmu 4146 iommus = <&apps_smmu 0xe0 0x0>;
4486 dma-coherent; 4147 dma-coherent;
4487 4148
4488 interconnects = <&agg 4149 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>,
4489 <&gem 4150 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
4490 interconnect-names = 4151 interconnect-names = "ufs-ddr", "cpu-ufs";
4491 clock-names = 4152 clock-names =
4492 "core_clk", 4153 "core_clk",
4493 "bus_aggr_clk 4154 "bus_aggr_clk",
4494 "iface_clk", 4155 "iface_clk",
4495 "core_clk_uni 4156 "core_clk_unipro",
4496 "ref_clk", 4157 "ref_clk",
4497 "tx_lane0_syn 4158 "tx_lane0_sync_clk",
4498 "rx_lane0_syn 4159 "rx_lane0_sync_clk",
4499 "rx_lane1_syn 4160 "rx_lane1_sync_clk";
4500 clocks = 4161 clocks =
4501 <&gcc GCC_UFS 4162 <&gcc GCC_UFS_PHY_AXI_CLK>,
4502 <&gcc GCC_AGG 4163 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
4503 <&gcc GCC_UFS 4164 <&gcc GCC_UFS_PHY_AHB_CLK>,
4504 <&gcc GCC_UFS 4165 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
4505 <&rpmhcc RPMH 4166 <&rpmhcc RPMH_CXO_CLK>,
4506 <&gcc GCC_UFS 4167 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
4507 <&gcc GCC_UFS 4168 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
4508 <&gcc GCC_UFS 4169 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
4509 freq-table-hz = 4170 freq-table-hz =
4510 <75000000 300 4171 <75000000 300000000>,
4511 <0 0>, 4172 <0 0>,
4512 <0 0>, 4173 <0 0>,
4513 <75000000 300 4174 <75000000 300000000>,
4514 <75000000 300 4175 <75000000 300000000>,
4515 <0 0>, 4176 <0 0>,
4516 <0 0>, 4177 <0 0>,
4517 <0 0>; 4178 <0 0>;
4518 qcom,ice = <&ice>; 4179 qcom,ice = <&ice>;
4519 4180
4520 status = "disabled"; 4181 status = "disabled";
4521 }; 4182 };
4522 4183
4523 ufs_mem_phy: phy@1d87000 { 4184 ufs_mem_phy: phy@1d87000 {
4524 compatible = "qcom,sm 4185 compatible = "qcom,sm8450-qmp-ufs-phy";
4525 reg = <0 0x01d87000 0 !! 4186 reg = <0 0x01d87000 0 0x1c4>;
4526 !! 4187 #address-cells = <2>;
>> 4188 #size-cells = <2>;
>> 4189 ranges;
4527 clock-names = "ref", 4190 clock-names = "ref", "ref_aux", "qref";
4528 clocks = <&rpmhcc RPM 4191 clocks = <&rpmhcc RPMH_CXO_CLK>,
4529 <&gcc GCC_UF 4192 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
4530 <&gcc GCC_UF 4193 <&gcc GCC_UFS_0_CLKREF_EN>;
4531 4194
4532 power-domains = <&gcc <<
4533 <<
4534 resets = <&ufs_mem_hc 4195 resets = <&ufs_mem_hc 0>;
4535 reset-names = "ufsphy 4196 reset-names = "ufsphy";
4536 <<
4537 #clock-cells = <1>; <<
4538 #phy-cells = <0>; <<
4539 <<
4540 status = "disabled"; 4197 status = "disabled";
>> 4198
>> 4199 ufs_mem_phy_lanes: phy@1d87400 {
>> 4200 reg = <0 0x01d87400 0 0x188>,
>> 4201 <0 0x01d87600 0 0x200>,
>> 4202 <0 0x01d87c00 0 0x200>,
>> 4203 <0 0x01d87800 0 0x188>,
>> 4204 <0 0x01d87a00 0 0x200>;
>> 4205 #clock-cells = <1>;
>> 4206 #phy-cells = <0>;
>> 4207 };
4541 }; 4208 };
4542 4209
4543 ice: crypto@1d88000 { 4210 ice: crypto@1d88000 {
4544 compatible = "qcom,sm 4211 compatible = "qcom,sm8450-inline-crypto-engine",
4545 "qcom,in 4212 "qcom,inline-crypto-engine";
4546 reg = <0 0x01d88000 0 4213 reg = <0 0x01d88000 0 0x8000>;
4547 clocks = <&gcc GCC_UF 4214 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
4548 }; 4215 };
4549 4216
4550 cryptobam: dma-controller@1dc 4217 cryptobam: dma-controller@1dc4000 {
4551 compatible = "qcom,ba 4218 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
4552 reg = <0 0x01dc4000 0 4219 reg = <0 0x01dc4000 0 0x28000>;
4553 interrupts = <GIC_SPI 4220 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
4554 #dma-cells = <1>; 4221 #dma-cells = <1>;
4555 qcom,ee = <0>; 4222 qcom,ee = <0>;
4556 qcom,controlled-remot 4223 qcom,controlled-remotely;
4557 iommus = <&apps_smmu 4224 iommus = <&apps_smmu 0x584 0x11>,
4558 <&apps_smmu 4225 <&apps_smmu 0x588 0x0>,
4559 <&apps_smmu 4226 <&apps_smmu 0x598 0x5>,
4560 <&apps_smmu 4227 <&apps_smmu 0x59a 0x0>,
4561 <&apps_smmu 4228 <&apps_smmu 0x59f 0x0>;
4562 }; 4229 };
4563 4230
4564 crypto: crypto@1dfa000 { 4231 crypto: crypto@1dfa000 {
4565 compatible = "qcom,sm 4232 compatible = "qcom,sm8450-qce", "qcom,sm8150-qce", "qcom,qce";
4566 reg = <0 0x01dfa000 0 4233 reg = <0 0x01dfa000 0 0x6000>;
4567 dmas = <&cryptobam 4> 4234 dmas = <&cryptobam 4>, <&cryptobam 5>;
4568 dma-names = "rx", "tx 4235 dma-names = "rx", "tx";
4569 iommus = <&apps_smmu 4236 iommus = <&apps_smmu 0x584 0x11>,
4570 <&apps_smmu 4237 <&apps_smmu 0x588 0x0>,
4571 <&apps_smmu 4238 <&apps_smmu 0x598 0x5>,
4572 <&apps_smmu 4239 <&apps_smmu 0x59a 0x0>,
4573 <&apps_smmu 4240 <&apps_smmu 0x59f 0x0>;
4574 interconnects = <&agg 4241 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
4575 interconnect-names = 4242 interconnect-names = "memory";
4576 }; 4243 };
4577 4244
4578 sdhc_2: mmc@8804000 { 4245 sdhc_2: mmc@8804000 {
4579 compatible = "qcom,sm 4246 compatible = "qcom,sm8450-sdhci", "qcom,sdhci-msm-v5";
4580 reg = <0 0x08804000 0 4247 reg = <0 0x08804000 0 0x1000>;
4581 4248
4582 interrupts = <GIC_SPI 4249 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
4583 <GIC_SPI 4250 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
4584 interrupt-names = "hc 4251 interrupt-names = "hc_irq", "pwr_irq";
4585 4252
4586 clocks = <&gcc GCC_SD 4253 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
4587 <&gcc GCC_SD 4254 <&gcc GCC_SDCC2_APPS_CLK>,
4588 <&rpmhcc RPM 4255 <&rpmhcc RPMH_CXO_CLK>;
4589 clock-names = "iface" 4256 clock-names = "iface", "core", "xo";
4590 resets = <&gcc GCC_SD 4257 resets = <&gcc GCC_SDCC2_BCR>;
4591 interconnects = <&agg 4258 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
4592 <&gem 4259 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
4593 interconnect-names = 4260 interconnect-names = "sdhc-ddr","cpu-sdhc";
4594 iommus = <&apps_smmu 4261 iommus = <&apps_smmu 0x4a0 0x0>;
4595 power-domains = <&rpm 4262 power-domains = <&rpmhpd RPMHPD_CX>;
4596 operating-points-v2 = 4263 operating-points-v2 = <&sdhc2_opp_table>;
4597 bus-width = <4>; 4264 bus-width = <4>;
4598 dma-coherent; 4265 dma-coherent;
4599 4266
4600 /* Forbid SDR104/SDR5 4267 /* Forbid SDR104/SDR50 - broken hw! */
4601 sdhci-caps-mask = <0x 4268 sdhci-caps-mask = <0x3 0x0>;
4602 4269
4603 status = "disabled"; 4270 status = "disabled";
4604 4271
4605 sdhc2_opp_table: opp- 4272 sdhc2_opp_table: opp-table {
4606 compatible = 4273 compatible = "operating-points-v2";
4607 4274
4608 opp-100000000 4275 opp-100000000 {
4609 opp-h 4276 opp-hz = /bits/ 64 <100000000>;
4610 requi 4277 required-opps = <&rpmhpd_opp_low_svs>;
4611 }; 4278 };
4612 4279
4613 opp-202000000 4280 opp-202000000 {
4614 opp-h 4281 opp-hz = /bits/ 64 <202000000>;
4615 requi 4282 required-opps = <&rpmhpd_opp_svs_l1>;
4616 }; 4283 };
4617 }; 4284 };
4618 }; 4285 };
4619 4286
4620 usb_1: usb@a6f8800 { 4287 usb_1: usb@a6f8800 {
4621 compatible = "qcom,sm 4288 compatible = "qcom,sm8450-dwc3", "qcom,dwc3";
4622 reg = <0 0x0a6f8800 0 4289 reg = <0 0x0a6f8800 0 0x400>;
4623 status = "disabled"; 4290 status = "disabled";
4624 #address-cells = <2>; 4291 #address-cells = <2>;
4625 #size-cells = <2>; 4292 #size-cells = <2>;
4626 ranges; 4293 ranges;
4627 4294
4628 clocks = <&gcc GCC_CF 4295 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
4629 <&gcc GCC_US 4296 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
4630 <&gcc GCC_AG 4297 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
4631 <&gcc GCC_US 4298 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
4632 <&gcc GCC_US 4299 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4633 <&gcc GCC_US 4300 <&gcc GCC_USB3_0_CLKREF_EN>;
4634 clock-names = "cfg_no 4301 clock-names = "cfg_noc",
4635 "core", 4302 "core",
4636 "iface" 4303 "iface",
4637 "sleep" 4304 "sleep",
4638 "mock_u 4305 "mock_utmi",
4639 "xo"; 4306 "xo";
4640 4307
4641 assigned-clocks = <&g 4308 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4642 <&g 4309 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
4643 assigned-clock-rates 4310 assigned-clock-rates = <19200000>, <200000000>;
4644 4311
4645 interrupts-extended = 4312 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
4646 !! 4313 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
4647 <<
4648 4314 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
4649 !! 4315 <&pdc 14 IRQ_TYPE_EDGE_BOTH>;
4650 interrupt-names = "pw !! 4316 interrupt-names = "hs_phy_irq",
4651 "hs !! 4317 "ss_phy_irq",
4652 "dp <<
4653 "dm 4318 "dm_hs_phy_irq",
4654 "ss !! 4319 "dp_hs_phy_irq";
4655 4320
4656 power-domains = <&gcc 4321 power-domains = <&gcc USB30_PRIM_GDSC>;
4657 4322
4658 resets = <&gcc GCC_US 4323 resets = <&gcc GCC_USB30_PRIM_BCR>;
4659 4324
4660 interconnects = <&agg 4325 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
4661 <&gem 4326 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
4662 interconnect-names = 4327 interconnect-names = "usb-ddr", "apps-usb";
4663 4328
4664 usb_1_dwc3: usb@a6000 4329 usb_1_dwc3: usb@a600000 {
4665 compatible = 4330 compatible = "snps,dwc3";
4666 reg = <0 0x0a 4331 reg = <0 0x0a600000 0 0xcd00>;
4667 interrupts = 4332 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
4668 iommus = <&ap 4333 iommus = <&apps_smmu 0x0 0x0>;
4669 snps,dis_u2_s 4334 snps,dis_u2_susphy_quirk;
4670 snps,dis_enbl 4335 snps,dis_enblslpm_quirk;
4671 phys = <&usb_ 4336 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
4672 phy-names = " 4337 phy-names = "usb2-phy", "usb3-phy";
4673 4338
4674 ports { 4339 ports {
4675 #addr 4340 #address-cells = <1>;
4676 #size 4341 #size-cells = <0>;
4677 4342
4678 port@ 4343 port@0 {
4679 4344 reg = <0>;
4680 4345
4681 4346 usb_1_dwc3_hs: endpoint {
4682 4347 };
4683 }; 4348 };
4684 4349
4685 port@ 4350 port@1 {
4686 4351 reg = <1>;
4687 4352
4688 4353 usb_1_dwc3_ss: endpoint {
4689 <<
4690 4354 };
4691 }; 4355 };
4692 }; 4356 };
4693 }; 4357 };
4694 }; 4358 };
4695 4359
4696 nsp_noc: interconnect@320c000 4360 nsp_noc: interconnect@320c0000 {
4697 compatible = "qcom,sm 4361 compatible = "qcom,sm8450-nsp-noc";
4698 reg = <0 0x320c0000 0 4362 reg = <0 0x320c0000 0 0x10000>;
4699 #interconnect-cells = 4363 #interconnect-cells = <2>;
4700 qcom,bcm-voters = <&a 4364 qcom,bcm-voters = <&apps_bcm_voter>;
4701 }; 4365 };
4702 4366
4703 lpass_ag_noc: interconnect@3c 4367 lpass_ag_noc: interconnect@3c40000 {
4704 compatible = "qcom,sm 4368 compatible = "qcom,sm8450-lpass-ag-noc";
4705 reg = <0 0x03c40000 0 4369 reg = <0 0x03c40000 0 0x17200>;
4706 #interconnect-cells = 4370 #interconnect-cells = <2>;
4707 qcom,bcm-voters = <&a 4371 qcom,bcm-voters = <&apps_bcm_voter>;
4708 }; 4372 };
4709 }; 4373 };
4710 4374
4711 sound: sound { 4375 sound: sound {
4712 }; 4376 };
4713 4377
4714 thermal-zones { 4378 thermal-zones {
4715 aoss0-thermal { 4379 aoss0-thermal {
>> 4380 polling-delay-passive = <0>;
>> 4381 polling-delay = <0>;
4716 thermal-sensors = <&t 4382 thermal-sensors = <&tsens0 0>;
4717 4383
4718 trips { 4384 trips {
4719 thermal-engin 4385 thermal-engine-config {
4720 tempe 4386 temperature = <125000>;
4721 hyste 4387 hysteresis = <1000>;
4722 type 4388 type = "passive";
4723 }; 4389 };
4724 4390
4725 reset-mon-cfg 4391 reset-mon-cfg {
4726 tempe 4392 temperature = <115000>;
4727 hyste 4393 hysteresis = <5000>;
4728 type 4394 type = "passive";
4729 }; 4395 };
4730 }; 4396 };
4731 }; 4397 };
4732 4398
4733 cpuss0-thermal { 4399 cpuss0-thermal {
>> 4400 polling-delay-passive = <0>;
>> 4401 polling-delay = <0>;
4734 thermal-sensors = <&t 4402 thermal-sensors = <&tsens0 1>;
4735 4403
4736 trips { 4404 trips {
4737 thermal-engin 4405 thermal-engine-config {
4738 tempe 4406 temperature = <125000>;
4739 hyste 4407 hysteresis = <1000>;
4740 type 4408 type = "passive";
4741 }; 4409 };
4742 4410
4743 reset-mon-cfg 4411 reset-mon-cfg {
4744 tempe 4412 temperature = <115000>;
4745 hyste 4413 hysteresis = <5000>;
4746 type 4414 type = "passive";
4747 }; 4415 };
4748 }; 4416 };
4749 }; 4417 };
4750 4418
4751 cpuss1-thermal { 4419 cpuss1-thermal {
>> 4420 polling-delay-passive = <0>;
>> 4421 polling-delay = <0>;
4752 thermal-sensors = <&t 4422 thermal-sensors = <&tsens0 2>;
4753 4423
4754 trips { 4424 trips {
4755 thermal-engin 4425 thermal-engine-config {
4756 tempe 4426 temperature = <125000>;
4757 hyste 4427 hysteresis = <1000>;
4758 type 4428 type = "passive";
4759 }; 4429 };
4760 4430
4761 reset-mon-cfg 4431 reset-mon-cfg {
4762 tempe 4432 temperature = <115000>;
4763 hyste 4433 hysteresis = <5000>;
4764 type 4434 type = "passive";
4765 }; 4435 };
4766 }; 4436 };
4767 }; 4437 };
4768 4438
4769 cpuss3-thermal { 4439 cpuss3-thermal {
>> 4440 polling-delay-passive = <0>;
>> 4441 polling-delay = <0>;
4770 thermal-sensors = <&t 4442 thermal-sensors = <&tsens0 3>;
4771 4443
4772 trips { 4444 trips {
4773 thermal-engin 4445 thermal-engine-config {
4774 tempe 4446 temperature = <125000>;
4775 hyste 4447 hysteresis = <1000>;
4776 type 4448 type = "passive";
4777 }; 4449 };
4778 4450
4779 reset-mon-cfg 4451 reset-mon-cfg {
4780 tempe 4452 temperature = <115000>;
4781 hyste 4453 hysteresis = <5000>;
4782 type 4454 type = "passive";
4783 }; 4455 };
4784 }; 4456 };
4785 }; 4457 };
4786 4458
4787 cpuss4-thermal { 4459 cpuss4-thermal {
>> 4460 polling-delay-passive = <0>;
>> 4461 polling-delay = <0>;
4788 thermal-sensors = <&t 4462 thermal-sensors = <&tsens0 4>;
4789 4463
4790 trips { 4464 trips {
4791 thermal-engin 4465 thermal-engine-config {
4792 tempe 4466 temperature = <125000>;
4793 hyste 4467 hysteresis = <1000>;
4794 type 4468 type = "passive";
4795 }; 4469 };
4796 4470
4797 reset-mon-cfg 4471 reset-mon-cfg {
4798 tempe 4472 temperature = <115000>;
4799 hyste 4473 hysteresis = <5000>;
4800 type 4474 type = "passive";
4801 }; 4475 };
4802 }; 4476 };
4803 }; 4477 };
4804 4478
4805 cpu4-top-thermal { 4479 cpu4-top-thermal {
>> 4480 polling-delay-passive = <0>;
>> 4481 polling-delay = <0>;
4806 thermal-sensors = <&t 4482 thermal-sensors = <&tsens0 5>;
4807 4483
4808 trips { 4484 trips {
4809 cpu4_top_aler 4485 cpu4_top_alert0: trip-point0 {
4810 tempe 4486 temperature = <90000>;
4811 hyste 4487 hysteresis = <2000>;
4812 type 4488 type = "passive";
4813 }; 4489 };
4814 4490
4815 cpu4_top_aler 4491 cpu4_top_alert1: trip-point1 {
4816 tempe 4492 temperature = <95000>;
4817 hyste 4493 hysteresis = <2000>;
4818 type 4494 type = "passive";
4819 }; 4495 };
4820 4496
4821 cpu4_top_crit 4497 cpu4_top_crit: cpu-crit {
4822 tempe 4498 temperature = <110000>;
4823 hyste 4499 hysteresis = <1000>;
4824 type 4500 type = "critical";
4825 }; 4501 };
4826 }; 4502 };
4827 }; 4503 };
4828 4504
4829 cpu4-bottom-thermal { 4505 cpu4-bottom-thermal {
>> 4506 polling-delay-passive = <0>;
>> 4507 polling-delay = <0>;
4830 thermal-sensors = <&t 4508 thermal-sensors = <&tsens0 6>;
4831 4509
4832 trips { 4510 trips {
4833 cpu4_bottom_a 4511 cpu4_bottom_alert0: trip-point0 {
4834 tempe 4512 temperature = <90000>;
4835 hyste 4513 hysteresis = <2000>;
4836 type 4514 type = "passive";
4837 }; 4515 };
4838 4516
4839 cpu4_bottom_a 4517 cpu4_bottom_alert1: trip-point1 {
4840 tempe 4518 temperature = <95000>;
4841 hyste 4519 hysteresis = <2000>;
4842 type 4520 type = "passive";
4843 }; 4521 };
4844 4522
4845 cpu4_bottom_c 4523 cpu4_bottom_crit: cpu-crit {
4846 tempe 4524 temperature = <110000>;
4847 hyste 4525 hysteresis = <1000>;
4848 type 4526 type = "critical";
4849 }; 4527 };
4850 }; 4528 };
4851 }; 4529 };
4852 4530
4853 cpu5-top-thermal { 4531 cpu5-top-thermal {
>> 4532 polling-delay-passive = <0>;
>> 4533 polling-delay = <0>;
4854 thermal-sensors = <&t 4534 thermal-sensors = <&tsens0 7>;
4855 4535
4856 trips { 4536 trips {
4857 cpu5_top_aler 4537 cpu5_top_alert0: trip-point0 {
4858 tempe 4538 temperature = <90000>;
4859 hyste 4539 hysteresis = <2000>;
4860 type 4540 type = "passive";
4861 }; 4541 };
4862 4542
4863 cpu5_top_aler 4543 cpu5_top_alert1: trip-point1 {
4864 tempe 4544 temperature = <95000>;
4865 hyste 4545 hysteresis = <2000>;
4866 type 4546 type = "passive";
4867 }; 4547 };
4868 4548
4869 cpu5_top_crit 4549 cpu5_top_crit: cpu-crit {
4870 tempe 4550 temperature = <110000>;
4871 hyste 4551 hysteresis = <1000>;
4872 type 4552 type = "critical";
4873 }; 4553 };
4874 }; 4554 };
4875 }; 4555 };
4876 4556
4877 cpu5-bottom-thermal { 4557 cpu5-bottom-thermal {
>> 4558 polling-delay-passive = <0>;
>> 4559 polling-delay = <0>;
4878 thermal-sensors = <&t 4560 thermal-sensors = <&tsens0 8>;
4879 4561
4880 trips { 4562 trips {
4881 cpu5_bottom_a 4563 cpu5_bottom_alert0: trip-point0 {
4882 tempe 4564 temperature = <90000>;
4883 hyste 4565 hysteresis = <2000>;
4884 type 4566 type = "passive";
4885 }; 4567 };
4886 4568
4887 cpu5_bottom_a 4569 cpu5_bottom_alert1: trip-point1 {
4888 tempe 4570 temperature = <95000>;
4889 hyste 4571 hysteresis = <2000>;
4890 type 4572 type = "passive";
4891 }; 4573 };
4892 4574
4893 cpu5_bottom_c 4575 cpu5_bottom_crit: cpu-crit {
4894 tempe 4576 temperature = <110000>;
4895 hyste 4577 hysteresis = <1000>;
4896 type 4578 type = "critical";
4897 }; 4579 };
4898 }; 4580 };
4899 }; 4581 };
4900 4582
4901 cpu6-top-thermal { 4583 cpu6-top-thermal {
>> 4584 polling-delay-passive = <0>;
>> 4585 polling-delay = <0>;
4902 thermal-sensors = <&t 4586 thermal-sensors = <&tsens0 9>;
4903 4587
4904 trips { 4588 trips {
4905 cpu6_top_aler 4589 cpu6_top_alert0: trip-point0 {
4906 tempe 4590 temperature = <90000>;
4907 hyste 4591 hysteresis = <2000>;
4908 type 4592 type = "passive";
4909 }; 4593 };
4910 4594
4911 cpu6_top_aler 4595 cpu6_top_alert1: trip-point1 {
4912 tempe 4596 temperature = <95000>;
4913 hyste 4597 hysteresis = <2000>;
4914 type 4598 type = "passive";
4915 }; 4599 };
4916 4600
4917 cpu6_top_crit 4601 cpu6_top_crit: cpu-crit {
4918 tempe 4602 temperature = <110000>;
4919 hyste 4603 hysteresis = <1000>;
4920 type 4604 type = "critical";
4921 }; 4605 };
4922 }; 4606 };
4923 }; 4607 };
4924 4608
4925 cpu6-bottom-thermal { 4609 cpu6-bottom-thermal {
>> 4610 polling-delay-passive = <0>;
>> 4611 polling-delay = <0>;
4926 thermal-sensors = <&t 4612 thermal-sensors = <&tsens0 10>;
4927 4613
4928 trips { 4614 trips {
4929 cpu6_bottom_a 4615 cpu6_bottom_alert0: trip-point0 {
4930 tempe 4616 temperature = <90000>;
4931 hyste 4617 hysteresis = <2000>;
4932 type 4618 type = "passive";
4933 }; 4619 };
4934 4620
4935 cpu6_bottom_a 4621 cpu6_bottom_alert1: trip-point1 {
4936 tempe 4622 temperature = <95000>;
4937 hyste 4623 hysteresis = <2000>;
4938 type 4624 type = "passive";
4939 }; 4625 };
4940 4626
4941 cpu6_bottom_c 4627 cpu6_bottom_crit: cpu-crit {
4942 tempe 4628 temperature = <110000>;
4943 hyste 4629 hysteresis = <1000>;
4944 type 4630 type = "critical";
4945 }; 4631 };
4946 }; 4632 };
4947 }; 4633 };
4948 4634
4949 cpu7-top-thermal { 4635 cpu7-top-thermal {
>> 4636 polling-delay-passive = <0>;
>> 4637 polling-delay = <0>;
4950 thermal-sensors = <&t 4638 thermal-sensors = <&tsens0 11>;
4951 4639
4952 trips { 4640 trips {
4953 cpu7_top_aler 4641 cpu7_top_alert0: trip-point0 {
4954 tempe 4642 temperature = <90000>;
4955 hyste 4643 hysteresis = <2000>;
4956 type 4644 type = "passive";
4957 }; 4645 };
4958 4646
4959 cpu7_top_aler 4647 cpu7_top_alert1: trip-point1 {
4960 tempe 4648 temperature = <95000>;
4961 hyste 4649 hysteresis = <2000>;
4962 type 4650 type = "passive";
4963 }; 4651 };
4964 4652
4965 cpu7_top_crit 4653 cpu7_top_crit: cpu-crit {
4966 tempe 4654 temperature = <110000>;
4967 hyste 4655 hysteresis = <1000>;
4968 type 4656 type = "critical";
4969 }; 4657 };
4970 }; 4658 };
4971 }; 4659 };
4972 4660
4973 cpu7-middle-thermal { 4661 cpu7-middle-thermal {
>> 4662 polling-delay-passive = <0>;
>> 4663 polling-delay = <0>;
4974 thermal-sensors = <&t 4664 thermal-sensors = <&tsens0 12>;
4975 4665
4976 trips { 4666 trips {
4977 cpu7_middle_a 4667 cpu7_middle_alert0: trip-point0 {
4978 tempe 4668 temperature = <90000>;
4979 hyste 4669 hysteresis = <2000>;
4980 type 4670 type = "passive";
4981 }; 4671 };
4982 4672
4983 cpu7_middle_a 4673 cpu7_middle_alert1: trip-point1 {
4984 tempe 4674 temperature = <95000>;
4985 hyste 4675 hysteresis = <2000>;
4986 type 4676 type = "passive";
4987 }; 4677 };
4988 4678
4989 cpu7_middle_c 4679 cpu7_middle_crit: cpu-crit {
4990 tempe 4680 temperature = <110000>;
4991 hyste 4681 hysteresis = <1000>;
4992 type 4682 type = "critical";
4993 }; 4683 };
4994 }; 4684 };
4995 }; 4685 };
4996 4686
4997 cpu7-bottom-thermal { 4687 cpu7-bottom-thermal {
>> 4688 polling-delay-passive = <0>;
>> 4689 polling-delay = <0>;
4998 thermal-sensors = <&t 4690 thermal-sensors = <&tsens0 13>;
4999 4691
5000 trips { 4692 trips {
5001 cpu7_bottom_a 4693 cpu7_bottom_alert0: trip-point0 {
5002 tempe 4694 temperature = <90000>;
5003 hyste 4695 hysteresis = <2000>;
5004 type 4696 type = "passive";
5005 }; 4697 };
5006 4698
5007 cpu7_bottom_a 4699 cpu7_bottom_alert1: trip-point1 {
5008 tempe 4700 temperature = <95000>;
5009 hyste 4701 hysteresis = <2000>;
5010 type 4702 type = "passive";
5011 }; 4703 };
5012 4704
5013 cpu7_bottom_c 4705 cpu7_bottom_crit: cpu-crit {
5014 tempe 4706 temperature = <110000>;
5015 hyste 4707 hysteresis = <1000>;
5016 type 4708 type = "critical";
5017 }; 4709 };
5018 }; 4710 };
5019 }; 4711 };
5020 4712
5021 gpu-top-thermal { 4713 gpu-top-thermal {
5022 polling-delay-passive 4714 polling-delay-passive = <10>;
5023 !! 4715 polling-delay = <0>;
5024 thermal-sensors = <&t 4716 thermal-sensors = <&tsens0 14>;
5025 4717
5026 cooling-maps { <<
5027 map0 { <<
5028 trip <<
5029 cooli <<
5030 }; <<
5031 }; <<
5032 <<
5033 trips { 4718 trips {
5034 gpu_top_alert !! 4719 thermal-engine-config {
5035 tempe !! 4720 temperature = <125000>;
5036 hyste 4721 hysteresis = <1000>;
5037 type 4722 type = "passive";
5038 }; 4723 };
5039 4724
5040 trip-point1 { !! 4725 thermal-hal-config {
5041 tempe !! 4726 temperature = <125000>;
5042 hyste 4727 hysteresis = <1000>;
5043 type !! 4728 type = "passive";
5044 }; 4729 };
5045 4730
5046 trip-point2 { !! 4731 reset-mon-cfg {
5047 tempe !! 4732 temperature = <115000>;
5048 hyste !! 4733 hysteresis = <5000>;
5049 type !! 4734 type = "passive";
>> 4735 };
>> 4736
>> 4737 gpu0_tj_cfg: tj-cfg {
>> 4738 temperature = <95000>;
>> 4739 hysteresis = <5000>;
>> 4740 type = "passive";
5050 }; 4741 };
5051 }; 4742 };
5052 }; 4743 };
5053 4744
5054 gpu-bottom-thermal { 4745 gpu-bottom-thermal {
5055 polling-delay-passive 4746 polling-delay-passive = <10>;
5056 !! 4747 polling-delay = <0>;
5057 thermal-sensors = <&t 4748 thermal-sensors = <&tsens0 15>;
5058 4749
5059 cooling-maps { <<
5060 map0 { <<
5061 trip <<
5062 cooli <<
5063 }; <<
5064 }; <<
5065 <<
5066 trips { 4750 trips {
5067 gpu_bottom_al !! 4751 thermal-engine-config {
5068 tempe !! 4752 temperature = <125000>;
5069 hyste 4753 hysteresis = <1000>;
5070 type 4754 type = "passive";
5071 }; 4755 };
5072 4756
5073 trip-point1 { !! 4757 thermal-hal-config {
5074 tempe !! 4758 temperature = <125000>;
5075 hyste 4759 hysteresis = <1000>;
5076 type !! 4760 type = "passive";
5077 }; 4761 };
5078 4762
5079 trip-point2 { !! 4763 reset-mon-cfg {
5080 tempe !! 4764 temperature = <115000>;
5081 hyste !! 4765 hysteresis = <5000>;
5082 type !! 4766 type = "passive";
>> 4767 };
>> 4768
>> 4769 gpu1_tj_cfg: tj-cfg {
>> 4770 temperature = <95000>;
>> 4771 hysteresis = <5000>;
>> 4772 type = "passive";
5083 }; 4773 };
5084 }; 4774 };
5085 }; 4775 };
5086 4776
5087 aoss1-thermal { 4777 aoss1-thermal {
>> 4778 polling-delay-passive = <0>;
>> 4779 polling-delay = <0>;
5088 thermal-sensors = <&t 4780 thermal-sensors = <&tsens1 0>;
5089 4781
5090 trips { 4782 trips {
5091 thermal-engin 4783 thermal-engine-config {
5092 tempe 4784 temperature = <125000>;
5093 hyste 4785 hysteresis = <1000>;
5094 type 4786 type = "passive";
5095 }; 4787 };
5096 4788
5097 reset-mon-cfg 4789 reset-mon-cfg {
5098 tempe 4790 temperature = <115000>;
5099 hyste 4791 hysteresis = <5000>;
5100 type 4792 type = "passive";
5101 }; 4793 };
5102 }; 4794 };
5103 }; 4795 };
5104 4796
5105 cpu0-thermal { 4797 cpu0-thermal {
>> 4798 polling-delay-passive = <0>;
>> 4799 polling-delay = <0>;
5106 thermal-sensors = <&t 4800 thermal-sensors = <&tsens1 1>;
5107 4801
5108 trips { 4802 trips {
5109 cpu0_alert0: 4803 cpu0_alert0: trip-point0 {
5110 tempe 4804 temperature = <90000>;
5111 hyste 4805 hysteresis = <2000>;
5112 type 4806 type = "passive";
5113 }; 4807 };
5114 4808
5115 cpu0_alert1: 4809 cpu0_alert1: trip-point1 {
5116 tempe 4810 temperature = <95000>;
5117 hyste 4811 hysteresis = <2000>;
5118 type 4812 type = "passive";
5119 }; 4813 };
5120 4814
5121 cpu0_crit: cp 4815 cpu0_crit: cpu-crit {
5122 tempe 4816 temperature = <110000>;
5123 hyste 4817 hysteresis = <1000>;
5124 type 4818 type = "critical";
5125 }; 4819 };
5126 }; 4820 };
5127 }; 4821 };
5128 4822
5129 cpu1-thermal { 4823 cpu1-thermal {
>> 4824 polling-delay-passive = <0>;
>> 4825 polling-delay = <0>;
5130 thermal-sensors = <&t 4826 thermal-sensors = <&tsens1 2>;
5131 4827
5132 trips { 4828 trips {
5133 cpu1_alert0: 4829 cpu1_alert0: trip-point0 {
5134 tempe 4830 temperature = <90000>;
5135 hyste 4831 hysteresis = <2000>;
5136 type 4832 type = "passive";
5137 }; 4833 };
5138 4834
5139 cpu1_alert1: 4835 cpu1_alert1: trip-point1 {
5140 tempe 4836 temperature = <95000>;
5141 hyste 4837 hysteresis = <2000>;
5142 type 4838 type = "passive";
5143 }; 4839 };
5144 4840
5145 cpu1_crit: cp 4841 cpu1_crit: cpu-crit {
5146 tempe 4842 temperature = <110000>;
5147 hyste 4843 hysteresis = <1000>;
5148 type 4844 type = "critical";
5149 }; 4845 };
5150 }; 4846 };
5151 }; 4847 };
5152 4848
5153 cpu2-thermal { 4849 cpu2-thermal {
>> 4850 polling-delay-passive = <0>;
>> 4851 polling-delay = <0>;
5154 thermal-sensors = <&t 4852 thermal-sensors = <&tsens1 3>;
5155 4853
5156 trips { 4854 trips {
5157 cpu2_alert0: 4855 cpu2_alert0: trip-point0 {
5158 tempe 4856 temperature = <90000>;
5159 hyste 4857 hysteresis = <2000>;
5160 type 4858 type = "passive";
5161 }; 4859 };
5162 4860
5163 cpu2_alert1: 4861 cpu2_alert1: trip-point1 {
5164 tempe 4862 temperature = <95000>;
5165 hyste 4863 hysteresis = <2000>;
5166 type 4864 type = "passive";
5167 }; 4865 };
5168 4866
5169 cpu2_crit: cp 4867 cpu2_crit: cpu-crit {
5170 tempe 4868 temperature = <110000>;
5171 hyste 4869 hysteresis = <1000>;
5172 type 4870 type = "critical";
5173 }; 4871 };
5174 }; 4872 };
5175 }; 4873 };
5176 4874
5177 cpu3-thermal { 4875 cpu3-thermal {
>> 4876 polling-delay-passive = <0>;
>> 4877 polling-delay = <0>;
5178 thermal-sensors = <&t 4878 thermal-sensors = <&tsens1 4>;
5179 4879
5180 trips { 4880 trips {
5181 cpu3_alert0: 4881 cpu3_alert0: trip-point0 {
5182 tempe 4882 temperature = <90000>;
5183 hyste 4883 hysteresis = <2000>;
5184 type 4884 type = "passive";
5185 }; 4885 };
5186 4886
5187 cpu3_alert1: 4887 cpu3_alert1: trip-point1 {
5188 tempe 4888 temperature = <95000>;
5189 hyste 4889 hysteresis = <2000>;
5190 type 4890 type = "passive";
5191 }; 4891 };
5192 4892
5193 cpu3_crit: cp 4893 cpu3_crit: cpu-crit {
5194 tempe 4894 temperature = <110000>;
5195 hyste 4895 hysteresis = <1000>;
5196 type 4896 type = "critical";
5197 }; 4897 };
5198 }; 4898 };
5199 }; 4899 };
5200 4900
5201 cdsp0-thermal { 4901 cdsp0-thermal {
5202 polling-delay-passive 4902 polling-delay-passive = <10>;
5203 !! 4903 polling-delay = <0>;
5204 thermal-sensors = <&t 4904 thermal-sensors = <&tsens1 5>;
5205 4905
5206 trips { 4906 trips {
5207 thermal-engin 4907 thermal-engine-config {
5208 tempe 4908 temperature = <125000>;
5209 hyste 4909 hysteresis = <1000>;
5210 type 4910 type = "passive";
5211 }; 4911 };
5212 4912
5213 thermal-hal-c 4913 thermal-hal-config {
5214 tempe 4914 temperature = <125000>;
5215 hyste 4915 hysteresis = <1000>;
5216 type 4916 type = "passive";
5217 }; 4917 };
5218 4918
5219 reset-mon-cfg 4919 reset-mon-cfg {
5220 tempe 4920 temperature = <115000>;
5221 hyste 4921 hysteresis = <5000>;
5222 type 4922 type = "passive";
5223 }; 4923 };
5224 4924
5225 cdsp_0_config 4925 cdsp_0_config: junction-config {
5226 tempe 4926 temperature = <95000>;
5227 hyste 4927 hysteresis = <5000>;
5228 type 4928 type = "passive";
5229 }; 4929 };
5230 }; 4930 };
5231 }; 4931 };
5232 4932
5233 cdsp1-thermal { 4933 cdsp1-thermal {
5234 polling-delay-passive 4934 polling-delay-passive = <10>;
5235 !! 4935 polling-delay = <0>;
5236 thermal-sensors = <&t 4936 thermal-sensors = <&tsens1 6>;
5237 4937
5238 trips { 4938 trips {
5239 thermal-engin 4939 thermal-engine-config {
5240 tempe 4940 temperature = <125000>;
5241 hyste 4941 hysteresis = <1000>;
5242 type 4942 type = "passive";
5243 }; 4943 };
5244 4944
5245 thermal-hal-c 4945 thermal-hal-config {
5246 tempe 4946 temperature = <125000>;
5247 hyste 4947 hysteresis = <1000>;
5248 type 4948 type = "passive";
5249 }; 4949 };
5250 4950
5251 reset-mon-cfg 4951 reset-mon-cfg {
5252 tempe 4952 temperature = <115000>;
5253 hyste 4953 hysteresis = <5000>;
5254 type 4954 type = "passive";
5255 }; 4955 };
5256 4956
5257 cdsp_1_config 4957 cdsp_1_config: junction-config {
5258 tempe 4958 temperature = <95000>;
5259 hyste 4959 hysteresis = <5000>;
5260 type 4960 type = "passive";
5261 }; 4961 };
5262 }; 4962 };
5263 }; 4963 };
5264 4964
5265 cdsp2-thermal { 4965 cdsp2-thermal {
5266 polling-delay-passive 4966 polling-delay-passive = <10>;
5267 !! 4967 polling-delay = <0>;
5268 thermal-sensors = <&t 4968 thermal-sensors = <&tsens1 7>;
5269 4969
5270 trips { 4970 trips {
5271 thermal-engin 4971 thermal-engine-config {
5272 tempe 4972 temperature = <125000>;
5273 hyste 4973 hysteresis = <1000>;
5274 type 4974 type = "passive";
5275 }; 4975 };
5276 4976
5277 thermal-hal-c 4977 thermal-hal-config {
5278 tempe 4978 temperature = <125000>;
5279 hyste 4979 hysteresis = <1000>;
5280 type 4980 type = "passive";
5281 }; 4981 };
5282 4982
5283 reset-mon-cfg 4983 reset-mon-cfg {
5284 tempe 4984 temperature = <115000>;
5285 hyste 4985 hysteresis = <5000>;
5286 type 4986 type = "passive";
5287 }; 4987 };
5288 4988
5289 cdsp_2_config 4989 cdsp_2_config: junction-config {
5290 tempe 4990 temperature = <95000>;
5291 hyste 4991 hysteresis = <5000>;
5292 type 4992 type = "passive";
5293 }; 4993 };
5294 }; 4994 };
5295 }; 4995 };
5296 4996
5297 video-thermal { 4997 video-thermal {
>> 4998 polling-delay-passive = <0>;
>> 4999 polling-delay = <0>;
5298 thermal-sensors = <&t 5000 thermal-sensors = <&tsens1 8>;
5299 5001
5300 trips { 5002 trips {
5301 thermal-engin 5003 thermal-engine-config {
5302 tempe 5004 temperature = <125000>;
5303 hyste 5005 hysteresis = <1000>;
5304 type 5006 type = "passive";
5305 }; 5007 };
5306 5008
5307 reset-mon-cfg 5009 reset-mon-cfg {
5308 tempe 5010 temperature = <115000>;
5309 hyste 5011 hysteresis = <5000>;
5310 type 5012 type = "passive";
5311 }; 5013 };
5312 }; 5014 };
5313 }; 5015 };
5314 5016
5315 mem-thermal { 5017 mem-thermal {
5316 polling-delay-passive 5018 polling-delay-passive = <10>;
5317 !! 5019 polling-delay = <0>;
5318 thermal-sensors = <&t 5020 thermal-sensors = <&tsens1 9>;
5319 5021
5320 trips { 5022 trips {
5321 thermal-engin 5023 thermal-engine-config {
5322 tempe 5024 temperature = <125000>;
5323 hyste 5025 hysteresis = <1000>;
5324 type 5026 type = "passive";
5325 }; 5027 };
5326 5028
5327 ddr_config0: 5029 ddr_config0: ddr0-config {
5328 tempe 5030 temperature = <90000>;
5329 hyste 5031 hysteresis = <5000>;
5330 type 5032 type = "passive";
5331 }; 5033 };
5332 5034
5333 reset-mon-cfg 5035 reset-mon-cfg {
5334 tempe 5036 temperature = <115000>;
5335 hyste 5037 hysteresis = <5000>;
5336 type 5038 type = "passive";
5337 }; 5039 };
5338 }; 5040 };
5339 }; 5041 };
5340 5042
5341 modem0-thermal { 5043 modem0-thermal {
>> 5044 polling-delay-passive = <0>;
>> 5045 polling-delay = <0>;
5342 thermal-sensors = <&t 5046 thermal-sensors = <&tsens1 10>;
5343 5047
5344 trips { 5048 trips {
5345 thermal-engin 5049 thermal-engine-config {
5346 tempe 5050 temperature = <125000>;
5347 hyste 5051 hysteresis = <1000>;
5348 type 5052 type = "passive";
5349 }; 5053 };
5350 5054
5351 mdmss0_config 5055 mdmss0_config0: mdmss0-config0 {
5352 tempe 5056 temperature = <102000>;
5353 hyste 5057 hysteresis = <3000>;
5354 type 5058 type = "passive";
5355 }; 5059 };
5356 5060
5357 mdmss0_config 5061 mdmss0_config1: mdmss0-config1 {
5358 tempe 5062 temperature = <105000>;
5359 hyste 5063 hysteresis = <3000>;
5360 type 5064 type = "passive";
5361 }; 5065 };
5362 5066
5363 reset-mon-cfg 5067 reset-mon-cfg {
5364 tempe 5068 temperature = <115000>;
5365 hyste 5069 hysteresis = <5000>;
5366 type 5070 type = "passive";
5367 }; 5071 };
5368 }; 5072 };
5369 }; 5073 };
5370 5074
5371 modem1-thermal { 5075 modem1-thermal {
>> 5076 polling-delay-passive = <0>;
>> 5077 polling-delay = <0>;
5372 thermal-sensors = <&t 5078 thermal-sensors = <&tsens1 11>;
5373 5079
5374 trips { 5080 trips {
5375 thermal-engin 5081 thermal-engine-config {
5376 tempe 5082 temperature = <125000>;
5377 hyste 5083 hysteresis = <1000>;
5378 type 5084 type = "passive";
5379 }; 5085 };
5380 5086
5381 mdmss1_config 5087 mdmss1_config0: mdmss1-config0 {
5382 tempe 5088 temperature = <102000>;
5383 hyste 5089 hysteresis = <3000>;
5384 type 5090 type = "passive";
5385 }; 5091 };
5386 5092
5387 mdmss1_config 5093 mdmss1_config1: mdmss1-config1 {
5388 tempe 5094 temperature = <105000>;
5389 hyste 5095 hysteresis = <3000>;
5390 type 5096 type = "passive";
5391 }; 5097 };
5392 5098
5393 reset-mon-cfg 5099 reset-mon-cfg {
5394 tempe 5100 temperature = <115000>;
5395 hyste 5101 hysteresis = <5000>;
5396 type 5102 type = "passive";
5397 }; 5103 };
5398 }; 5104 };
5399 }; 5105 };
5400 5106
5401 modem2-thermal { 5107 modem2-thermal {
>> 5108 polling-delay-passive = <0>;
>> 5109 polling-delay = <0>;
5402 thermal-sensors = <&t 5110 thermal-sensors = <&tsens1 12>;
5403 5111
5404 trips { 5112 trips {
5405 thermal-engin 5113 thermal-engine-config {
5406 tempe 5114 temperature = <125000>;
5407 hyste 5115 hysteresis = <1000>;
5408 type 5116 type = "passive";
5409 }; 5117 };
5410 5118
5411 mdmss2_config 5119 mdmss2_config0: mdmss2-config0 {
5412 tempe 5120 temperature = <102000>;
5413 hyste 5121 hysteresis = <3000>;
5414 type 5122 type = "passive";
5415 }; 5123 };
5416 5124
5417 mdmss2_config 5125 mdmss2_config1: mdmss2-config1 {
5418 tempe 5126 temperature = <105000>;
5419 hyste 5127 hysteresis = <3000>;
5420 type 5128 type = "passive";
5421 }; 5129 };
5422 5130
5423 reset-mon-cfg 5131 reset-mon-cfg {
5424 tempe 5132 temperature = <115000>;
5425 hyste 5133 hysteresis = <5000>;
5426 type 5134 type = "passive";
5427 }; 5135 };
5428 }; 5136 };
5429 }; 5137 };
5430 5138
5431 modem3-thermal { 5139 modem3-thermal {
>> 5140 polling-delay-passive = <0>;
>> 5141 polling-delay = <0>;
5432 thermal-sensors = <&t 5142 thermal-sensors = <&tsens1 13>;
5433 5143
5434 trips { 5144 trips {
5435 thermal-engin 5145 thermal-engine-config {
5436 tempe 5146 temperature = <125000>;
5437 hyste 5147 hysteresis = <1000>;
5438 type 5148 type = "passive";
5439 }; 5149 };
5440 5150
5441 mdmss3_config 5151 mdmss3_config0: mdmss3-config0 {
5442 tempe 5152 temperature = <102000>;
5443 hyste 5153 hysteresis = <3000>;
5444 type 5154 type = "passive";
5445 }; 5155 };
5446 5156
5447 mdmss3_config 5157 mdmss3_config1: mdmss3-config1 {
5448 tempe 5158 temperature = <105000>;
5449 hyste 5159 hysteresis = <3000>;
5450 type 5160 type = "passive";
5451 }; 5161 };
5452 5162
5453 reset-mon-cfg 5163 reset-mon-cfg {
5454 tempe 5164 temperature = <115000>;
5455 hyste 5165 hysteresis = <5000>;
5456 type 5166 type = "passive";
5457 }; 5167 };
5458 }; 5168 };
5459 }; 5169 };
5460 5170
5461 camera0-thermal { 5171 camera0-thermal {
>> 5172 polling-delay-passive = <0>;
>> 5173 polling-delay = <0>;
5462 thermal-sensors = <&t 5174 thermal-sensors = <&tsens1 14>;
5463 5175
5464 trips { 5176 trips {
5465 thermal-engin 5177 thermal-engine-config {
5466 tempe 5178 temperature = <125000>;
5467 hyste 5179 hysteresis = <1000>;
5468 type 5180 type = "passive";
5469 }; 5181 };
5470 5182
5471 reset-mon-cfg 5183 reset-mon-cfg {
5472 tempe 5184 temperature = <115000>;
5473 hyste 5185 hysteresis = <5000>;
5474 type 5186 type = "passive";
5475 }; 5187 };
5476 }; 5188 };
5477 }; 5189 };
5478 5190
5479 camera1-thermal { 5191 camera1-thermal {
>> 5192 polling-delay-passive = <0>;
>> 5193 polling-delay = <0>;
5480 thermal-sensors = <&t 5194 thermal-sensors = <&tsens1 15>;
5481 5195
5482 trips { 5196 trips {
5483 thermal-engin 5197 thermal-engine-config {
5484 tempe 5198 temperature = <125000>;
5485 hyste 5199 hysteresis = <1000>;
5486 type 5200 type = "passive";
5487 }; 5201 };
5488 5202
5489 reset-mon-cfg 5203 reset-mon-cfg {
5490 tempe 5204 temperature = <115000>;
5491 hyste 5205 hysteresis = <5000>;
5492 type 5206 type = "passive";
5493 }; 5207 };
5494 }; 5208 };
5495 }; 5209 };
5496 }; 5210 };
5497 5211
5498 timer { 5212 timer {
5499 compatible = "arm,armv8-timer 5213 compatible = "arm,armv8-timer";
5500 interrupts = <GIC_PPI 13 (GIC 5214 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5501 <GIC_PPI 14 (GIC 5215 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5502 <GIC_PPI 11 (GIC 5216 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5503 <GIC_PPI 10 (GIC 5217 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
5504 clock-frequency = <19200000>; 5218 clock-frequency = <19200000>;
5505 }; 5219 };
5506 }; 5220 };
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