1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * Copyright (c) 2023 Qualcomm Innovation Cent 3 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
4 */ 4 */
5 5
6 #include <dt-bindings/clock/qcom,rpmh.h> 6 #include <dt-bindings/clock/qcom,rpmh.h>
7 #include <dt-bindings/clock/qcom,sc8280xp-lpas <<
8 #include <dt-bindings/clock/qcom,x1e80100-disp 7 #include <dt-bindings/clock/qcom,x1e80100-dispcc.h>
9 #include <dt-bindings/clock/qcom,x1e80100-gcc. 8 #include <dt-bindings/clock/qcom,x1e80100-gcc.h>
10 #include <dt-bindings/clock/qcom,x1e80100-gpuc <<
11 #include <dt-bindings/clock/qcom,x1e80100-tcsr 9 #include <dt-bindings/clock/qcom,x1e80100-tcsr.h>
12 #include <dt-bindings/dma/qcom-gpi.h> 10 #include <dt-bindings/dma/qcom-gpi.h>
13 #include <dt-bindings/interconnect/qcom,icc.h> 11 #include <dt-bindings/interconnect/qcom,icc.h>
14 #include <dt-bindings/interconnect/qcom,x1e801 12 #include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h>
15 #include <dt-bindings/interrupt-controller/arm 13 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/mailbox/qcom-ipcc.h> 14 #include <dt-bindings/mailbox/qcom-ipcc.h>
17 #include <dt-bindings/phy/phy-qcom-qmp.h> 15 #include <dt-bindings/phy/phy-qcom-qmp.h>
18 #include <dt-bindings/power/qcom,rpmhpd.h> 16 #include <dt-bindings/power/qcom,rpmhpd.h>
19 #include <dt-bindings/power/qcom-rpmpd.h> 17 #include <dt-bindings/power/qcom-rpmpd.h>
20 #include <dt-bindings/soc/qcom,gpr.h> 18 #include <dt-bindings/soc/qcom,gpr.h>
21 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 19 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
22 #include <dt-bindings/sound/qcom,q6dsp-lpass-p 20 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
23 21
24 / { 22 / {
25 interrupt-parent = <&intc>; 23 interrupt-parent = <&intc>;
26 24
27 #address-cells = <2>; 25 #address-cells = <2>;
28 #size-cells = <2>; 26 #size-cells = <2>;
29 27
30 chosen { }; 28 chosen { };
31 29
32 clocks { 30 clocks {
33 xo_board: xo-board { 31 xo_board: xo-board {
34 compatible = "fixed-cl 32 compatible = "fixed-clock";
35 clock-frequency = <768 33 clock-frequency = <76800000>;
36 #clock-cells = <0>; 34 #clock-cells = <0>;
37 }; 35 };
38 36
39 sleep_clk: sleep-clk { 37 sleep_clk: sleep-clk {
40 compatible = "fixed-cl 38 compatible = "fixed-clock";
41 clock-frequency = <320 39 clock-frequency = <32000>;
42 #clock-cells = <0>; 40 #clock-cells = <0>;
43 }; 41 };
44 42
45 bi_tcxo_div2: bi-tcxo-div2-clk 43 bi_tcxo_div2: bi-tcxo-div2-clk {
46 compatible = "fixed-fa 44 compatible = "fixed-factor-clock";
47 #clock-cells = <0>; 45 #clock-cells = <0>;
48 46
49 clocks = <&rpmhcc RPMH 47 clocks = <&rpmhcc RPMH_CXO_CLK>;
50 clock-mult = <1>; 48 clock-mult = <1>;
51 clock-div = <2>; 49 clock-div = <2>;
52 }; 50 };
53 51
54 bi_tcxo_ao_div2: bi-tcxo-ao-di 52 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
55 compatible = "fixed-fa 53 compatible = "fixed-factor-clock";
56 #clock-cells = <0>; 54 #clock-cells = <0>;
57 55
58 clocks = <&rpmhcc RPMH 56 clocks = <&rpmhcc RPMH_CXO_CLK_A>;
59 clock-mult = <1>; 57 clock-mult = <1>;
60 clock-div = <2>; 58 clock-div = <2>;
61 }; 59 };
62 }; 60 };
63 61
64 cpus { 62 cpus {
65 #address-cells = <2>; 63 #address-cells = <2>;
66 #size-cells = <0>; 64 #size-cells = <0>;
67 65
68 CPU0: cpu@0 { 66 CPU0: cpu@0 {
69 device_type = "cpu"; 67 device_type = "cpu";
70 compatible = "qcom,ory 68 compatible = "qcom,oryon";
71 reg = <0x0 0x0>; 69 reg = <0x0 0x0>;
72 enable-method = "psci" 70 enable-method = "psci";
73 next-level-cache = <&L 71 next-level-cache = <&L2_0>;
74 power-domains = <&CPU_ 72 power-domains = <&CPU_PD0>;
75 power-domain-names = " 73 power-domain-names = "psci";
76 cpu-idle-states = <&CL 74 cpu-idle-states = <&CLUSTER_C4>;
77 75
78 L2_0: l2-cache { 76 L2_0: l2-cache {
79 compatible = " 77 compatible = "cache";
80 cache-level = 78 cache-level = <2>;
81 cache-unified; 79 cache-unified;
82 }; 80 };
83 }; 81 };
84 82
85 CPU1: cpu@100 { 83 CPU1: cpu@100 {
86 device_type = "cpu"; 84 device_type = "cpu";
87 compatible = "qcom,ory 85 compatible = "qcom,oryon";
88 reg = <0x0 0x100>; 86 reg = <0x0 0x100>;
89 enable-method = "psci" 87 enable-method = "psci";
90 next-level-cache = <&L 88 next-level-cache = <&L2_0>;
91 power-domains = <&CPU_ 89 power-domains = <&CPU_PD1>;
92 power-domain-names = " 90 power-domain-names = "psci";
93 cpu-idle-states = <&CL 91 cpu-idle-states = <&CLUSTER_C4>;
94 }; 92 };
95 93
96 CPU2: cpu@200 { 94 CPU2: cpu@200 {
97 device_type = "cpu"; 95 device_type = "cpu";
98 compatible = "qcom,ory 96 compatible = "qcom,oryon";
99 reg = <0x0 0x200>; 97 reg = <0x0 0x200>;
100 enable-method = "psci" 98 enable-method = "psci";
101 next-level-cache = <&L 99 next-level-cache = <&L2_0>;
102 power-domains = <&CPU_ 100 power-domains = <&CPU_PD2>;
103 power-domain-names = " 101 power-domain-names = "psci";
104 cpu-idle-states = <&CL 102 cpu-idle-states = <&CLUSTER_C4>;
105 }; 103 };
106 104
107 CPU3: cpu@300 { 105 CPU3: cpu@300 {
108 device_type = "cpu"; 106 device_type = "cpu";
109 compatible = "qcom,ory 107 compatible = "qcom,oryon";
110 reg = <0x0 0x300>; 108 reg = <0x0 0x300>;
111 enable-method = "psci" 109 enable-method = "psci";
112 next-level-cache = <&L 110 next-level-cache = <&L2_0>;
113 power-domains = <&CPU_ 111 power-domains = <&CPU_PD3>;
114 power-domain-names = " 112 power-domain-names = "psci";
115 cpu-idle-states = <&CL 113 cpu-idle-states = <&CLUSTER_C4>;
116 }; 114 };
117 115
118 CPU4: cpu@10000 { 116 CPU4: cpu@10000 {
119 device_type = "cpu"; 117 device_type = "cpu";
120 compatible = "qcom,ory 118 compatible = "qcom,oryon";
121 reg = <0x0 0x10000>; 119 reg = <0x0 0x10000>;
122 enable-method = "psci" 120 enable-method = "psci";
123 next-level-cache = <&L 121 next-level-cache = <&L2_1>;
124 power-domains = <&CPU_ 122 power-domains = <&CPU_PD4>;
125 power-domain-names = " 123 power-domain-names = "psci";
126 cpu-idle-states = <&CL 124 cpu-idle-states = <&CLUSTER_C4>;
127 125
128 L2_1: l2-cache { 126 L2_1: l2-cache {
129 compatible = " 127 compatible = "cache";
130 cache-level = 128 cache-level = <2>;
131 cache-unified; 129 cache-unified;
132 }; 130 };
133 }; 131 };
134 132
135 CPU5: cpu@10100 { 133 CPU5: cpu@10100 {
136 device_type = "cpu"; 134 device_type = "cpu";
137 compatible = "qcom,ory 135 compatible = "qcom,oryon";
138 reg = <0x0 0x10100>; 136 reg = <0x0 0x10100>;
139 enable-method = "psci" 137 enable-method = "psci";
140 next-level-cache = <&L 138 next-level-cache = <&L2_1>;
141 power-domains = <&CPU_ 139 power-domains = <&CPU_PD5>;
142 power-domain-names = " 140 power-domain-names = "psci";
143 cpu-idle-states = <&CL 141 cpu-idle-states = <&CLUSTER_C4>;
144 }; 142 };
145 143
146 CPU6: cpu@10200 { 144 CPU6: cpu@10200 {
147 device_type = "cpu"; 145 device_type = "cpu";
148 compatible = "qcom,ory 146 compatible = "qcom,oryon";
149 reg = <0x0 0x10200>; 147 reg = <0x0 0x10200>;
150 enable-method = "psci" 148 enable-method = "psci";
151 next-level-cache = <&L 149 next-level-cache = <&L2_1>;
152 power-domains = <&CPU_ 150 power-domains = <&CPU_PD6>;
153 power-domain-names = " 151 power-domain-names = "psci";
154 cpu-idle-states = <&CL 152 cpu-idle-states = <&CLUSTER_C4>;
155 }; 153 };
156 154
157 CPU7: cpu@10300 { 155 CPU7: cpu@10300 {
158 device_type = "cpu"; 156 device_type = "cpu";
159 compatible = "qcom,ory 157 compatible = "qcom,oryon";
160 reg = <0x0 0x10300>; 158 reg = <0x0 0x10300>;
161 enable-method = "psci" 159 enable-method = "psci";
162 next-level-cache = <&L 160 next-level-cache = <&L2_1>;
163 power-domains = <&CPU_ 161 power-domains = <&CPU_PD7>;
164 power-domain-names = " 162 power-domain-names = "psci";
165 cpu-idle-states = <&CL 163 cpu-idle-states = <&CLUSTER_C4>;
166 }; 164 };
167 165
168 CPU8: cpu@20000 { 166 CPU8: cpu@20000 {
169 device_type = "cpu"; 167 device_type = "cpu";
170 compatible = "qcom,ory 168 compatible = "qcom,oryon";
171 reg = <0x0 0x20000>; 169 reg = <0x0 0x20000>;
172 enable-method = "psci" 170 enable-method = "psci";
173 next-level-cache = <&L 171 next-level-cache = <&L2_2>;
174 power-domains = <&CPU_ 172 power-domains = <&CPU_PD8>;
175 power-domain-names = " 173 power-domain-names = "psci";
176 cpu-idle-states = <&CL 174 cpu-idle-states = <&CLUSTER_C4>;
177 175
178 L2_2: l2-cache { 176 L2_2: l2-cache {
179 compatible = " 177 compatible = "cache";
180 cache-level = 178 cache-level = <2>;
181 cache-unified; 179 cache-unified;
182 }; 180 };
183 }; 181 };
184 182
185 CPU9: cpu@20100 { 183 CPU9: cpu@20100 {
186 device_type = "cpu"; 184 device_type = "cpu";
187 compatible = "qcom,ory 185 compatible = "qcom,oryon";
188 reg = <0x0 0x20100>; 186 reg = <0x0 0x20100>;
189 enable-method = "psci" 187 enable-method = "psci";
190 next-level-cache = <&L 188 next-level-cache = <&L2_2>;
191 power-domains = <&CPU_ 189 power-domains = <&CPU_PD9>;
192 power-domain-names = " 190 power-domain-names = "psci";
193 cpu-idle-states = <&CL 191 cpu-idle-states = <&CLUSTER_C4>;
194 }; 192 };
195 193
196 CPU10: cpu@20200 { 194 CPU10: cpu@20200 {
197 device_type = "cpu"; 195 device_type = "cpu";
198 compatible = "qcom,ory 196 compatible = "qcom,oryon";
199 reg = <0x0 0x20200>; 197 reg = <0x0 0x20200>;
200 enable-method = "psci" 198 enable-method = "psci";
201 next-level-cache = <&L 199 next-level-cache = <&L2_2>;
202 power-domains = <&CPU_ 200 power-domains = <&CPU_PD10>;
203 power-domain-names = " 201 power-domain-names = "psci";
204 cpu-idle-states = <&CL 202 cpu-idle-states = <&CLUSTER_C4>;
205 }; 203 };
206 204
207 CPU11: cpu@20300 { 205 CPU11: cpu@20300 {
208 device_type = "cpu"; 206 device_type = "cpu";
209 compatible = "qcom,ory 207 compatible = "qcom,oryon";
210 reg = <0x0 0x20300>; 208 reg = <0x0 0x20300>;
211 enable-method = "psci" 209 enable-method = "psci";
212 next-level-cache = <&L 210 next-level-cache = <&L2_2>;
213 power-domains = <&CPU_ 211 power-domains = <&CPU_PD11>;
214 power-domain-names = " 212 power-domain-names = "psci";
215 cpu-idle-states = <&CL 213 cpu-idle-states = <&CLUSTER_C4>;
216 }; 214 };
217 215
218 cpu-map { 216 cpu-map {
219 cluster0 { 217 cluster0 {
220 core0 { 218 core0 {
221 cpu = 219 cpu = <&CPU0>;
222 }; 220 };
223 221
224 core1 { 222 core1 {
225 cpu = 223 cpu = <&CPU1>;
226 }; 224 };
227 225
228 core2 { 226 core2 {
229 cpu = 227 cpu = <&CPU2>;
230 }; 228 };
231 229
232 core3 { 230 core3 {
233 cpu = 231 cpu = <&CPU3>;
234 }; 232 };
235 }; 233 };
236 234
237 cluster1 { 235 cluster1 {
238 core0 { 236 core0 {
239 cpu = 237 cpu = <&CPU4>;
240 }; 238 };
241 239
242 core1 { 240 core1 {
243 cpu = 241 cpu = <&CPU5>;
244 }; 242 };
245 243
246 core2 { 244 core2 {
247 cpu = 245 cpu = <&CPU6>;
248 }; 246 };
249 247
250 core3 { 248 core3 {
251 cpu = 249 cpu = <&CPU7>;
252 }; 250 };
253 }; 251 };
254 252
255 cluster2 { 253 cluster2 {
256 core0 { 254 core0 {
257 cpu = 255 cpu = <&CPU8>;
258 }; 256 };
259 257
260 core1 { 258 core1 {
261 cpu = 259 cpu = <&CPU9>;
262 }; 260 };
263 261
264 core2 { 262 core2 {
265 cpu = 263 cpu = <&CPU10>;
266 }; 264 };
267 265
268 core3 { 266 core3 {
269 cpu = 267 cpu = <&CPU11>;
270 }; 268 };
271 }; 269 };
272 }; 270 };
273 271
274 idle-states { 272 idle-states {
275 entry-method = "psci"; 273 entry-method = "psci";
276 274
277 CLUSTER_C4: cpu-sleep- 275 CLUSTER_C4: cpu-sleep-0 {
278 compatible = " 276 compatible = "arm,idle-state";
279 idle-state-nam 277 idle-state-name = "ret";
280 arm,psci-suspe 278 arm,psci-suspend-param = <0x00000004>;
281 entry-latency- 279 entry-latency-us = <180>;
282 exit-latency-u 280 exit-latency-us = <320>;
283 min-residency- 281 min-residency-us = <1000>;
284 }; 282 };
285 }; 283 };
286 284
287 domain-idle-states { 285 domain-idle-states {
288 CLUSTER_CL4: cluster-s 286 CLUSTER_CL4: cluster-sleep-0 {
289 compatible = " 287 compatible = "domain-idle-state";
290 idle-state-nam 288 idle-state-name = "l2-ret";
291 arm,psci-suspe 289 arm,psci-suspend-param = <0x01000044>;
292 entry-latency- 290 entry-latency-us = <350>;
293 exit-latency-u 291 exit-latency-us = <500>;
294 min-residency- 292 min-residency-us = <2500>;
295 }; 293 };
296 294
297 CLUSTER_CL5: cluster-s 295 CLUSTER_CL5: cluster-sleep-1 {
298 compatible = " 296 compatible = "domain-idle-state";
299 idle-state-nam 297 idle-state-name = "ret-pll-off";
300 arm,psci-suspe 298 arm,psci-suspend-param = <0x01000054>;
301 entry-latency- 299 entry-latency-us = <2200>;
302 exit-latency-u 300 exit-latency-us = <2500>;
303 min-residency- 301 min-residency-us = <7000>;
304 }; 302 };
305 }; 303 };
306 }; 304 };
307 305
308 firmware { 306 firmware {
309 scm: scm { 307 scm: scm {
310 compatible = "qcom,scm 308 compatible = "qcom,scm-x1e80100", "qcom,scm";
311 interconnects = <&aggr 309 interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS
312 &mc_v 310 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
313 }; 311 };
314 }; 312 };
315 313
316 clk_virt: interconnect-0 { 314 clk_virt: interconnect-0 {
317 compatible = "qcom,x1e80100-cl 315 compatible = "qcom,x1e80100-clk-virt";
318 #interconnect-cells = <2>; 316 #interconnect-cells = <2>;
319 qcom,bcm-voters = <&apps_bcm_v 317 qcom,bcm-voters = <&apps_bcm_voter>;
320 }; 318 };
321 319
322 mc_virt: interconnect-1 { 320 mc_virt: interconnect-1 {
323 compatible = "qcom,x1e80100-mc 321 compatible = "qcom,x1e80100-mc-virt";
324 #interconnect-cells = <2>; 322 #interconnect-cells = <2>;
325 qcom,bcm-voters = <&apps_bcm_v 323 qcom,bcm-voters = <&apps_bcm_voter>;
326 }; 324 };
327 325
328 memory@80000000 { 326 memory@80000000 {
329 device_type = "memory"; 327 device_type = "memory";
330 /* We expect the bootloader to 328 /* We expect the bootloader to fill in the size */
331 reg = <0 0x80000000 0 0>; 329 reg = <0 0x80000000 0 0>;
332 }; 330 };
333 331
334 pmu { 332 pmu {
335 compatible = "arm,armv8-pmuv3" 333 compatible = "arm,armv8-pmuv3";
336 interrupts = <GIC_PPI 7 IRQ_TY 334 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
337 }; 335 };
338 336
339 psci { 337 psci {
340 compatible = "arm,psci-1.0"; 338 compatible = "arm,psci-1.0";
341 method = "smc"; 339 method = "smc";
342 340
343 CPU_PD0: power-domain-cpu0 { 341 CPU_PD0: power-domain-cpu0 {
344 #power-domain-cells = 342 #power-domain-cells = <0>;
345 power-domains = <&CLUS 343 power-domains = <&CLUSTER_PD0>;
346 }; 344 };
347 345
348 CPU_PD1: power-domain-cpu1 { 346 CPU_PD1: power-domain-cpu1 {
349 #power-domain-cells = 347 #power-domain-cells = <0>;
350 power-domains = <&CLUS 348 power-domains = <&CLUSTER_PD0>;
351 }; 349 };
352 350
353 CPU_PD2: power-domain-cpu2 { 351 CPU_PD2: power-domain-cpu2 {
354 #power-domain-cells = 352 #power-domain-cells = <0>;
355 power-domains = <&CLUS 353 power-domains = <&CLUSTER_PD0>;
356 }; 354 };
357 355
358 CPU_PD3: power-domain-cpu3 { 356 CPU_PD3: power-domain-cpu3 {
359 #power-domain-cells = 357 #power-domain-cells = <0>;
360 power-domains = <&CLUS 358 power-domains = <&CLUSTER_PD0>;
361 }; 359 };
362 360
363 CPU_PD4: power-domain-cpu4 { 361 CPU_PD4: power-domain-cpu4 {
364 #power-domain-cells = 362 #power-domain-cells = <0>;
365 power-domains = <&CLUS 363 power-domains = <&CLUSTER_PD1>;
366 }; 364 };
367 365
368 CPU_PD5: power-domain-cpu5 { 366 CPU_PD5: power-domain-cpu5 {
369 #power-domain-cells = 367 #power-domain-cells = <0>;
370 power-domains = <&CLUS 368 power-domains = <&CLUSTER_PD1>;
371 }; 369 };
372 370
373 CPU_PD6: power-domain-cpu6 { 371 CPU_PD6: power-domain-cpu6 {
374 #power-domain-cells = 372 #power-domain-cells = <0>;
375 power-domains = <&CLUS 373 power-domains = <&CLUSTER_PD1>;
376 }; 374 };
377 375
378 CPU_PD7: power-domain-cpu7 { 376 CPU_PD7: power-domain-cpu7 {
379 #power-domain-cells = 377 #power-domain-cells = <0>;
380 power-domains = <&CLUS 378 power-domains = <&CLUSTER_PD1>;
381 }; 379 };
382 380
383 CPU_PD8: power-domain-cpu8 { 381 CPU_PD8: power-domain-cpu8 {
384 #power-domain-cells = 382 #power-domain-cells = <0>;
385 power-domains = <&CLUS 383 power-domains = <&CLUSTER_PD2>;
386 }; 384 };
387 385
388 CPU_PD9: power-domain-cpu9 { 386 CPU_PD9: power-domain-cpu9 {
389 #power-domain-cells = 387 #power-domain-cells = <0>;
390 power-domains = <&CLUS 388 power-domains = <&CLUSTER_PD2>;
391 }; 389 };
392 390
393 CPU_PD10: power-domain-cpu10 { 391 CPU_PD10: power-domain-cpu10 {
394 #power-domain-cells = 392 #power-domain-cells = <0>;
395 power-domains = <&CLUS 393 power-domains = <&CLUSTER_PD2>;
396 }; 394 };
397 395
398 CPU_PD11: power-domain-cpu11 { 396 CPU_PD11: power-domain-cpu11 {
399 #power-domain-cells = 397 #power-domain-cells = <0>;
400 power-domains = <&CLUS 398 power-domains = <&CLUSTER_PD2>;
401 }; 399 };
402 400
403 CLUSTER_PD0: power-domain-cpu- 401 CLUSTER_PD0: power-domain-cpu-cluster0 {
404 #power-domain-cells = 402 #power-domain-cells = <0>;
405 domain-idle-states = < 403 domain-idle-states = <&CLUSTER_CL4>, <&CLUSTER_CL5>;
406 power-domains = <&SYST 404 power-domains = <&SYSTEM_PD>;
407 }; 405 };
408 406
409 CLUSTER_PD1: power-domain-cpu- 407 CLUSTER_PD1: power-domain-cpu-cluster1 {
410 #power-domain-cells = 408 #power-domain-cells = <0>;
411 domain-idle-states = < 409 domain-idle-states = <&CLUSTER_CL4>, <&CLUSTER_CL5>;
412 power-domains = <&SYST 410 power-domains = <&SYSTEM_PD>;
413 }; 411 };
414 412
415 CLUSTER_PD2: power-domain-cpu- 413 CLUSTER_PD2: power-domain-cpu-cluster2 {
416 #power-domain-cells = 414 #power-domain-cells = <0>;
417 domain-idle-states = < 415 domain-idle-states = <&CLUSTER_CL4>, <&CLUSTER_CL5>;
418 power-domains = <&SYST 416 power-domains = <&SYSTEM_PD>;
419 }; 417 };
420 418
421 SYSTEM_PD: power-domain-system 419 SYSTEM_PD: power-domain-system {
422 #power-domain-cells = 420 #power-domain-cells = <0>;
423 /* TODO: system-wide i 421 /* TODO: system-wide idle states */
424 }; 422 };
425 }; 423 };
426 424
427 reserved-memory { 425 reserved-memory {
428 #address-cells = <2>; 426 #address-cells = <2>;
429 #size-cells = <2>; 427 #size-cells = <2>;
430 ranges; 428 ranges;
431 429
432 gunyah_hyp_mem: gunyah-hyp@800 430 gunyah_hyp_mem: gunyah-hyp@80000000 {
433 reg = <0x0 0x80000000 431 reg = <0x0 0x80000000 0x0 0x800000>;
434 no-map; 432 no-map;
435 }; 433 };
436 434
437 hyp_elf_package_mem: hyp-elf-p 435 hyp_elf_package_mem: hyp-elf-package@80800000 {
438 reg = <0x0 0x80800000 436 reg = <0x0 0x80800000 0x0 0x200000>;
439 no-map; 437 no-map;
440 }; 438 };
441 439
442 ncc_mem: ncc@80a00000 { 440 ncc_mem: ncc@80a00000 {
443 reg = <0x0 0x80a00000 441 reg = <0x0 0x80a00000 0x0 0x400000>;
444 no-map; 442 no-map;
445 }; 443 };
446 444
447 cpucp_log_mem: cpucp-log@80e00 445 cpucp_log_mem: cpucp-log@80e00000 {
448 reg = <0x0 0x80e00000 446 reg = <0x0 0x80e00000 0x0 0x40000>;
449 no-map; 447 no-map;
450 }; 448 };
451 449
452 cpucp_mem: cpucp@80e40000 { 450 cpucp_mem: cpucp@80e40000 {
453 reg = <0x0 0x80e40000 451 reg = <0x0 0x80e40000 0x0 0x540000>;
454 no-map; 452 no-map;
455 }; 453 };
456 454
457 reserved-region@81380000 { 455 reserved-region@81380000 {
458 reg = <0x0 0x81380000 456 reg = <0x0 0x81380000 0x0 0x80000>;
459 no-map; 457 no-map;
460 }; 458 };
461 459
462 tags_mem: tags-region@81400000 460 tags_mem: tags-region@81400000 {
463 reg = <0x0 0x81400000 461 reg = <0x0 0x81400000 0x0 0x1a0000>;
464 no-map; 462 no-map;
465 }; 463 };
466 464
467 xbl_dtlog_mem: xbl-dtlog@81a00 465 xbl_dtlog_mem: xbl-dtlog@81a00000 {
468 reg = <0x0 0x81a00000 466 reg = <0x0 0x81a00000 0x0 0x40000>;
469 no-map; 467 no-map;
470 }; 468 };
471 469
472 xbl_ramdump_mem: xbl-ramdump@8 470 xbl_ramdump_mem: xbl-ramdump@81a40000 {
473 reg = <0x0 0x81a40000 471 reg = <0x0 0x81a40000 0x0 0x1c0000>;
474 no-map; 472 no-map;
475 }; 473 };
476 474
477 aop_image_mem: aop-image@81c00 475 aop_image_mem: aop-image@81c00000 {
478 reg = <0x0 0x81c00000 476 reg = <0x0 0x81c00000 0x0 0x60000>;
479 no-map; 477 no-map;
480 }; 478 };
481 479
482 aop_cmd_db_mem: aop-cmd-db@81c 480 aop_cmd_db_mem: aop-cmd-db@81c60000 {
483 compatible = "qcom,cmd 481 compatible = "qcom,cmd-db";
484 reg = <0x0 0x81c60000 482 reg = <0x0 0x81c60000 0x0 0x20000>;
485 no-map; 483 no-map;
486 }; 484 };
487 485
488 aop_config_mem: aop-config@81c 486 aop_config_mem: aop-config@81c80000 {
489 reg = <0x0 0x81c80000 487 reg = <0x0 0x81c80000 0x0 0x20000>;
490 no-map; 488 no-map;
491 }; 489 };
492 490
493 tme_crash_dump_mem: tme-crash- 491 tme_crash_dump_mem: tme-crash-dump@81ca0000 {
494 reg = <0x0 0x81ca0000 492 reg = <0x0 0x81ca0000 0x0 0x40000>;
495 no-map; 493 no-map;
496 }; 494 };
497 495
498 tme_log_mem: tme-log@81ce0000 496 tme_log_mem: tme-log@81ce0000 {
499 reg = <0x0 0x81ce0000 497 reg = <0x0 0x81ce0000 0x0 0x4000>;
500 no-map; 498 no-map;
501 }; 499 };
502 500
503 uefi_log_mem: uefi-log@81ce400 501 uefi_log_mem: uefi-log@81ce4000 {
504 reg = <0x0 0x81ce4000 502 reg = <0x0 0x81ce4000 0x0 0x10000>;
505 no-map; 503 no-map;
506 }; 504 };
507 505
508 secdata_apss_mem: secdata-apss 506 secdata_apss_mem: secdata-apss@81cff000 {
509 reg = <0x0 0x81cff000 507 reg = <0x0 0x81cff000 0x0 0x1000>;
510 no-map; 508 no-map;
511 }; 509 };
512 510
513 pdp_ns_shared_mem: pdp-ns-shar 511 pdp_ns_shared_mem: pdp-ns-shared@81e00000 {
514 reg = <0x0 0x81e00000 512 reg = <0x0 0x81e00000 0x0 0x100000>;
515 no-map; 513 no-map;
516 }; 514 };
517 515
518 gpu_prr_mem: gpu-prr@81f00000 516 gpu_prr_mem: gpu-prr@81f00000 {
519 reg = <0x0 0x81f00000 517 reg = <0x0 0x81f00000 0x0 0x10000>;
520 no-map; 518 no-map;
521 }; 519 };
522 520
523 tpm_control_mem: tpm-control@8 521 tpm_control_mem: tpm-control@81f10000 {
524 reg = <0x0 0x81f10000 522 reg = <0x0 0x81f10000 0x0 0x10000>;
525 no-map; 523 no-map;
526 }; 524 };
527 525
528 usb_ucsi_shared_mem: usb-ucsi- 526 usb_ucsi_shared_mem: usb-ucsi-shared@81f20000 {
529 reg = <0x0 0x81f20000 527 reg = <0x0 0x81f20000 0x0 0x10000>;
530 no-map; 528 no-map;
531 }; 529 };
532 530
533 pld_pep_mem: pld-pep@81f30000 531 pld_pep_mem: pld-pep@81f30000 {
534 reg = <0x0 0x81f30000 532 reg = <0x0 0x81f30000 0x0 0x6000>;
535 no-map; 533 no-map;
536 }; 534 };
537 535
538 pld_gmu_mem: pld-gmu@81f36000 536 pld_gmu_mem: pld-gmu@81f36000 {
539 reg = <0x0 0x81f36000 537 reg = <0x0 0x81f36000 0x0 0x1000>;
540 no-map; 538 no-map;
541 }; 539 };
542 540
543 pld_pdp_mem: pld-pdp@81f37000 541 pld_pdp_mem: pld-pdp@81f37000 {
544 reg = <0x0 0x81f37000 542 reg = <0x0 0x81f37000 0x0 0x1000>;
545 no-map; 543 no-map;
546 }; 544 };
547 545
548 tz_stat_mem: tz-stat@82700000 546 tz_stat_mem: tz-stat@82700000 {
549 reg = <0x0 0x82700000 547 reg = <0x0 0x82700000 0x0 0x100000>;
550 no-map; 548 no-map;
551 }; 549 };
552 550
553 xbl_tmp_buffer_mem: xbl-tmp-bu 551 xbl_tmp_buffer_mem: xbl-tmp-buffer@82800000 {
554 reg = <0x0 0x82800000 552 reg = <0x0 0x82800000 0x0 0xc00000>;
555 no-map; 553 no-map;
556 }; 554 };
557 555
558 adsp_rpc_remote_heap_mem: adsp 556 adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@84b00000 {
559 reg = <0x0 0x84b00000 557 reg = <0x0 0x84b00000 0x0 0x800000>;
560 no-map; 558 no-map;
561 }; 559 };
562 560
563 spu_secure_shared_memory_mem: 561 spu_secure_shared_memory_mem: spu-secure-shared-memory@85300000 {
564 reg = <0x0 0x85300000 562 reg = <0x0 0x85300000 0x0 0x80000>;
565 no-map; 563 no-map;
566 }; 564 };
567 565
568 adsp_boot_dtb_mem: adsp-boot-d 566 adsp_boot_dtb_mem: adsp-boot-dtb@866c0000 {
569 reg = <0x0 0x866c0000 567 reg = <0x0 0x866c0000 0x0 0x40000>;
570 no-map; 568 no-map;
571 }; 569 };
572 570
573 spss_region_mem: spss-region@8 571 spss_region_mem: spss-region@86700000 {
574 reg = <0x0 0x86700000 572 reg = <0x0 0x86700000 0x0 0x400000>;
575 no-map; 573 no-map;
576 }; 574 };
577 575
578 adsp_boot_mem: adsp-boot@86b00 576 adsp_boot_mem: adsp-boot@86b00000 {
579 reg = <0x0 0x86b00000 577 reg = <0x0 0x86b00000 0x0 0xc00000>;
580 no-map; 578 no-map;
581 }; 579 };
582 580
583 video_mem: video@87700000 { 581 video_mem: video@87700000 {
584 reg = <0x0 0x87700000 582 reg = <0x0 0x87700000 0x0 0x700000>;
585 no-map; 583 no-map;
586 }; 584 };
587 585
588 adspslpi_mem: adspslpi@87e0000 586 adspslpi_mem: adspslpi@87e00000 {
589 reg = <0x0 0x87e00000 587 reg = <0x0 0x87e00000 0x0 0x3a00000>;
590 no-map; 588 no-map;
591 }; 589 };
592 590
593 q6_adsp_dtb_mem: q6-adsp-dtb@8 591 q6_adsp_dtb_mem: q6-adsp-dtb@8b800000 {
594 reg = <0x0 0x8b800000 592 reg = <0x0 0x8b800000 0x0 0x80000>;
595 no-map; 593 no-map;
596 }; 594 };
597 595
598 cdsp_mem: cdsp@8b900000 { 596 cdsp_mem: cdsp@8b900000 {
599 reg = <0x0 0x8b900000 597 reg = <0x0 0x8b900000 0x0 0x2000000>;
600 no-map; 598 no-map;
601 }; 599 };
602 600
603 q6_cdsp_dtb_mem: q6-cdsp-dtb@8 601 q6_cdsp_dtb_mem: q6-cdsp-dtb@8d900000 {
604 reg = <0x0 0x8d900000 602 reg = <0x0 0x8d900000 0x0 0x80000>;
605 no-map; 603 no-map;
606 }; 604 };
607 605
608 gpu_microcode_mem: gpu-microco 606 gpu_microcode_mem: gpu-microcode@8d9fe000 {
609 reg = <0x0 0x8d9fe000 607 reg = <0x0 0x8d9fe000 0x0 0x2000>;
610 no-map; 608 no-map;
611 }; 609 };
612 610
613 cvp_mem: cvp@8da00000 { 611 cvp_mem: cvp@8da00000 {
614 reg = <0x0 0x8da00000 612 reg = <0x0 0x8da00000 0x0 0x700000>;
615 no-map; 613 no-map;
616 }; 614 };
617 615
618 camera_mem: camera@8e100000 { 616 camera_mem: camera@8e100000 {
619 reg = <0x0 0x8e100000 617 reg = <0x0 0x8e100000 0x0 0x800000>;
620 no-map; 618 no-map;
621 }; 619 };
622 620
623 av1_encoder_mem: av1-encoder@8 621 av1_encoder_mem: av1-encoder@8e900000 {
624 reg = <0x0 0x8e900000 622 reg = <0x0 0x8e900000 0x0 0x700000>;
625 no-map; 623 no-map;
626 }; 624 };
627 625
628 reserved-region@8f000000 { 626 reserved-region@8f000000 {
629 reg = <0x0 0x8f000000 627 reg = <0x0 0x8f000000 0x0 0xa00000>;
630 no-map; 628 no-map;
631 }; 629 };
632 630
633 wpss_mem: wpss@8fa00000 { 631 wpss_mem: wpss@8fa00000 {
634 reg = <0x0 0x8fa00000 632 reg = <0x0 0x8fa00000 0x0 0x1900000>;
635 no-map; 633 no-map;
636 }; 634 };
637 635
638 q6_wpss_dtb_mem: q6-wpss-dtb@9 636 q6_wpss_dtb_mem: q6-wpss-dtb@91300000 {
639 reg = <0x0 0x91300000 637 reg = <0x0 0x91300000 0x0 0x80000>;
640 no-map; 638 no-map;
641 }; 639 };
642 640
643 xbl_sc_mem: xbl-sc@d8000000 { 641 xbl_sc_mem: xbl-sc@d8000000 {
644 reg = <0x0 0xd8000000 642 reg = <0x0 0xd8000000 0x0 0x40000>;
645 no-map; 643 no-map;
646 }; 644 };
647 645
648 reserved-region@d8040000 { 646 reserved-region@d8040000 {
649 reg = <0x0 0xd8040000 647 reg = <0x0 0xd8040000 0x0 0xa0000>;
650 no-map; 648 no-map;
651 }; 649 };
652 650
653 qtee_mem: qtee@d80e0000 { 651 qtee_mem: qtee@d80e0000 {
654 reg = <0x0 0xd80e0000 652 reg = <0x0 0xd80e0000 0x0 0x520000>;
655 no-map; 653 no-map;
656 }; 654 };
657 655
658 ta_mem: ta@d8600000 { 656 ta_mem: ta@d8600000 {
659 reg = <0x0 0xd8600000 657 reg = <0x0 0xd8600000 0x0 0x8a00000>;
660 no-map; 658 no-map;
661 }; 659 };
662 660
663 tags_mem1: tags@e1000000 { 661 tags_mem1: tags@e1000000 {
664 reg = <0x0 0xe1000000 662 reg = <0x0 0xe1000000 0x0 0x26a0000>;
665 no-map; 663 no-map;
666 }; 664 };
667 665
668 llcc_lpi_mem: llcc-lpi@ff80000 666 llcc_lpi_mem: llcc-lpi@ff800000 {
669 reg = <0x0 0xff800000 667 reg = <0x0 0xff800000 0x0 0x600000>;
670 no-map; 668 no-map;
671 }; 669 };
672 670
673 smem_mem: smem@ffe00000 { 671 smem_mem: smem@ffe00000 {
674 compatible = "qcom,sme 672 compatible = "qcom,smem";
675 reg = <0x0 0xffe00000 673 reg = <0x0 0xffe00000 0x0 0x200000>;
676 hwlocks = <&tcsr_mutex 674 hwlocks = <&tcsr_mutex 3>;
677 no-map; 675 no-map;
678 }; 676 };
679 }; 677 };
680 678
681 smp2p-adsp { 679 smp2p-adsp {
682 compatible = "qcom,smp2p"; 680 compatible = "qcom,smp2p";
683 681
684 interrupts-extended = <&ipcc I 682 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
685 I 683 IPCC_MPROC_SIGNAL_SMP2P
686 I 684 IRQ_TYPE_EDGE_RISING>;
687 685
688 mboxes = <&ipcc IPCC_CLIENT_LP 686 mboxes = <&ipcc IPCC_CLIENT_LPASS
689 IPCC_MPROC_SIG 687 IPCC_MPROC_SIGNAL_SMP2P>;
690 688
691 qcom,smem = <443>, <429>; 689 qcom,smem = <443>, <429>;
692 qcom,local-pid = <0>; 690 qcom,local-pid = <0>;
693 qcom,remote-pid = <2>; 691 qcom,remote-pid = <2>;
694 692
695 smp2p_adsp_out: master-kernel 693 smp2p_adsp_out: master-kernel {
696 qcom,entry-name = "mas 694 qcom,entry-name = "master-kernel";
697 #qcom,smem-state-cells 695 #qcom,smem-state-cells = <1>;
698 }; 696 };
699 697
700 smp2p_adsp_in: slave-kernel { 698 smp2p_adsp_in: slave-kernel {
701 qcom,entry-name = "sla 699 qcom,entry-name = "slave-kernel";
702 interrupt-controller; 700 interrupt-controller;
703 #interrupt-cells = <2> 701 #interrupt-cells = <2>;
704 }; 702 };
705 }; 703 };
706 704
707 smp2p-cdsp { 705 smp2p-cdsp {
708 compatible = "qcom,smp2p"; 706 compatible = "qcom,smp2p";
709 707
710 interrupts-extended = <&ipcc I 708 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
711 I 709 IPCC_MPROC_SIGNAL_SMP2P
712 I 710 IRQ_TYPE_EDGE_RISING>;
713 711
714 mboxes = <&ipcc IPCC_CLIENT_CD 712 mboxes = <&ipcc IPCC_CLIENT_CDSP
715 IPCC_MPROC_SIG 713 IPCC_MPROC_SIGNAL_SMP2P>;
716 714
717 qcom,smem = <94>, <432>; 715 qcom,smem = <94>, <432>;
718 qcom,local-pid = <0>; 716 qcom,local-pid = <0>;
719 qcom,remote-pid = <5>; 717 qcom,remote-pid = <5>;
720 718
721 smp2p_cdsp_out: master-kernel 719 smp2p_cdsp_out: master-kernel {
722 qcom,entry-name = "mas 720 qcom,entry-name = "master-kernel";
723 #qcom,smem-state-cells 721 #qcom,smem-state-cells = <1>;
724 }; 722 };
725 723
726 smp2p_cdsp_in: slave-kernel { 724 smp2p_cdsp_in: slave-kernel {
727 qcom,entry-name = "sla 725 qcom,entry-name = "slave-kernel";
728 interrupt-controller; 726 interrupt-controller;
729 #interrupt-cells = <2> 727 #interrupt-cells = <2>;
730 }; 728 };
731 }; 729 };
732 730
733 soc: soc@0 { 731 soc: soc@0 {
734 compatible = "simple-bus"; 732 compatible = "simple-bus";
735 733
736 #address-cells = <2>; 734 #address-cells = <2>;
737 #size-cells = <2>; 735 #size-cells = <2>;
738 dma-ranges = <0 0 0 0 0x10 0>; 736 dma-ranges = <0 0 0 0 0x10 0>;
739 ranges = <0 0 0 0 0x10 0>; 737 ranges = <0 0 0 0 0x10 0>;
740 738
741 gcc: clock-controller@100000 { 739 gcc: clock-controller@100000 {
742 compatible = "qcom,x1e 740 compatible = "qcom,x1e80100-gcc";
743 reg = <0 0x00100000 0 741 reg = <0 0x00100000 0 0x200000>;
744 742
745 clocks = <&bi_tcxo_div 743 clocks = <&bi_tcxo_div2>,
746 <&sleep_clk>, 744 <&sleep_clk>,
747 <0>, 745 <0>,
748 <&pcie4_phy>, 746 <&pcie4_phy>,
749 <&pcie5_phy>, !! 747 <0>,
750 <&pcie6a_phy> 748 <&pcie6a_phy>,
751 <0>, 749 <0>,
752 <&usb_1_ss0_q 750 <&usb_1_ss0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
753 <&usb_1_ss1_q 751 <&usb_1_ss1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
754 <&usb_1_ss2_q 752 <&usb_1_ss2_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
755 753
756 power-domains = <&rpmh 754 power-domains = <&rpmhpd RPMHPD_CX>;
757 #clock-cells = <1>; 755 #clock-cells = <1>;
758 #reset-cells = <1>; 756 #reset-cells = <1>;
759 #power-domain-cells = 757 #power-domain-cells = <1>;
760 }; 758 };
761 759
762 ipcc: mailbox@408000 { 760 ipcc: mailbox@408000 {
763 compatible = "qcom,x1e 761 compatible = "qcom,x1e80100-ipcc", "qcom,ipcc";
764 reg = <0 0x00408000 0 762 reg = <0 0x00408000 0 0x1000>;
765 763
766 interrupts = <GIC_SPI 764 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
767 interrupt-controller; 765 interrupt-controller;
768 #interrupt-cells = <3> 766 #interrupt-cells = <3>;
769 767
770 #mbox-cells = <2>; 768 #mbox-cells = <2>;
771 }; 769 };
772 770
773 gpi_dma2: dma-controller@80000 771 gpi_dma2: dma-controller@800000 {
774 compatible = "qcom,x1e 772 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma";
775 reg = <0 0x00800000 0 773 reg = <0 0x00800000 0 0x60000>;
776 774
777 interrupts = <GIC_SPI 775 interrupts = <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>,
778 <GIC_SPI 776 <GIC_SPI 789 IRQ_TYPE_LEVEL_HIGH>,
779 <GIC_SPI 777 <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>,
780 <GIC_SPI 778 <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>,
781 <GIC_SPI 779 <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>,
782 <GIC_SPI 780 <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>,
783 <GIC_SPI 781 <GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>,
784 <GIC_SPI 782 <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>,
785 <GIC_SPI 783 <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>,
786 <GIC_SPI 784 <GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH>,
787 <GIC_SPI 785 <GIC_SPI 798 IRQ_TYPE_LEVEL_HIGH>,
788 <GIC_SPI 786 <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH>;
789 787
790 dma-channels = <12>; 788 dma-channels = <12>;
791 dma-channel-mask = <0x 789 dma-channel-mask = <0x3e>;
792 #dma-cells = <3>; 790 #dma-cells = <3>;
793 791
794 iommus = <&apps_smmu 0 792 iommus = <&apps_smmu 0x436 0x0>;
795 793
796 status = "disabled"; 794 status = "disabled";
797 }; 795 };
798 796
799 qupv3_2: geniqup@8c0000 { 797 qupv3_2: geniqup@8c0000 {
800 compatible = "qcom,gen 798 compatible = "qcom,geni-se-qup";
801 reg = <0 0x008c0000 0 799 reg = <0 0x008c0000 0 0x2000>;
802 800
803 clocks = <&gcc GCC_QUP 801 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
804 <&gcc GCC_QUP 802 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
805 clock-names = "m-ahb", 803 clock-names = "m-ahb",
806 "s-ahb"; 804 "s-ahb";
807 805
808 iommus = <&apps_smmu 0 806 iommus = <&apps_smmu 0x423 0x0>;
809 807
810 #address-cells = <2>; 808 #address-cells = <2>;
811 #size-cells = <2>; 809 #size-cells = <2>;
812 ranges; 810 ranges;
813 811
814 status = "disabled"; 812 status = "disabled";
815 813
816 i2c16: i2c@880000 { 814 i2c16: i2c@880000 {
817 compatible = " 815 compatible = "qcom,geni-i2c";
818 reg = <0 0x008 816 reg = <0 0x00880000 0 0x4000>;
819 817
820 interrupts = < 818 interrupts = <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>;
821 819
822 clocks = <&gcc 820 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
823 clock-names = 821 clock-names = "se";
824 822
825 interconnects 823 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
826 824 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
827 825 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
828 826 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
829 827 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
830 828 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
831 interconnect-n 829 interconnect-names = "qup-core",
832 830 "qup-config",
833 831 "qup-memory";
834 832
835 dmas = <&gpi_d 833 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
836 <&gpi_d 834 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
837 dma-names = "t 835 dma-names = "tx",
838 "r 836 "rx";
839 837
840 pinctrl-0 = <& 838 pinctrl-0 = <&qup_i2c16_data_clk>;
841 pinctrl-names 839 pinctrl-names = "default";
842 840
843 #address-cells 841 #address-cells = <1>;
844 #size-cells = 842 #size-cells = <0>;
845 843
846 status = "disa 844 status = "disabled";
847 }; 845 };
848 846
849 spi16: spi@880000 { 847 spi16: spi@880000 {
850 compatible = " 848 compatible = "qcom,geni-spi";
851 reg = <0 0x008 849 reg = <0 0x00880000 0 0x4000>;
852 850
853 interrupts = < 851 interrupts = <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>;
854 852
855 clocks = <&gcc 853 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
856 clock-names = 854 clock-names = "se";
857 855
858 interconnects 856 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
859 857 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
860 858 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
861 859 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
862 860 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
863 861 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
864 interconnect-n 862 interconnect-names = "qup-core",
865 863 "qup-config",
866 864 "qup-memory";
867 865
868 dmas = <&gpi_d 866 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
869 <&gpi_d 867 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
870 dma-names = "t 868 dma-names = "tx",
871 "r 869 "rx";
872 870
873 pinctrl-0 = <& 871 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>;
874 pinctrl-names 872 pinctrl-names = "default";
875 873
876 #address-cells 874 #address-cells = <1>;
877 #size-cells = 875 #size-cells = <0>;
878 876
879 status = "disa 877 status = "disabled";
880 }; 878 };
881 879
882 i2c17: i2c@884000 { 880 i2c17: i2c@884000 {
883 compatible = " 881 compatible = "qcom,geni-i2c";
884 reg = <0 0x008 882 reg = <0 0x00884000 0 0x4000>;
885 883
886 interrupts = < 884 interrupts = <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>;
887 885
888 clocks = <&gcc 886 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
889 clock-names = 887 clock-names = "se";
890 888
891 interconnects 889 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
892 890 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
893 891 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
894 892 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
895 893 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
896 894 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
897 interconnect-n 895 interconnect-names = "qup-core",
898 896 "qup-config",
899 897 "qup-memory";
900 898
901 dmas = <&gpi_d 899 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
902 <&gpi_d 900 <&gpi_dma2 1 1 QCOM_GPI_I2C>;
903 dma-names = "t 901 dma-names = "tx",
904 "r 902 "rx";
905 903
906 pinctrl-0 = <& 904 pinctrl-0 = <&qup_i2c17_data_clk>;
907 pinctrl-names 905 pinctrl-names = "default";
908 906
909 #address-cells 907 #address-cells = <1>;
910 #size-cells = 908 #size-cells = <0>;
911 909
912 status = "disa 910 status = "disabled";
913 }; 911 };
914 912
915 spi17: spi@884000 { 913 spi17: spi@884000 {
916 compatible = " 914 compatible = "qcom,geni-spi";
917 reg = <0 0x008 915 reg = <0 0x00884000 0 0x4000>;
918 916
919 interrupts = < 917 interrupts = <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>;
920 918
921 clocks = <&gcc 919 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
922 clock-names = 920 clock-names = "se";
923 921
924 interconnects 922 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
925 923 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
926 924 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
927 925 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
928 926 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
929 927 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
930 interconnect-n 928 interconnect-names = "qup-core",
931 929 "qup-config",
932 930 "qup-memory";
933 931
934 dmas = <&gpi_d 932 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
935 <&gpi_d 933 <&gpi_dma2 1 1 QCOM_GPI_SPI>;
936 dma-names = "t 934 dma-names = "tx",
937 "r 935 "rx";
938 936
939 pinctrl-0 = <& 937 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>;
940 pinctrl-names 938 pinctrl-names = "default";
941 939
942 #address-cells 940 #address-cells = <1>;
943 #size-cells = 941 #size-cells = <0>;
944 942
945 status = "disa 943 status = "disabled";
946 }; 944 };
947 945
948 i2c18: i2c@888000 { 946 i2c18: i2c@888000 {
949 compatible = " 947 compatible = "qcom,geni-i2c";
950 reg = <0 0x008 948 reg = <0 0x00888000 0 0x4000>;
951 949
952 interrupts = < 950 interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>;
953 951
954 clocks = <&gcc 952 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
955 clock-names = 953 clock-names = "se";
956 954
957 interconnects 955 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
958 956 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
959 957 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
960 958 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
961 959 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
962 960 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
963 interconnect-n 961 interconnect-names = "qup-core",
964 962 "qup-config",
965 963 "qup-memory";
966 964
967 dmas = <&gpi_d 965 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
968 <&gpi_d 966 <&gpi_dma2 1 2 QCOM_GPI_I2C>;
969 dma-names = "t 967 dma-names = "tx",
970 "r 968 "rx";
971 969
972 pinctrl-0 = <& 970 pinctrl-0 = <&qup_i2c18_data_clk>;
973 pinctrl-names 971 pinctrl-names = "default";
974 972
975 #address-cells 973 #address-cells = <1>;
976 #size-cells = 974 #size-cells = <0>;
977 975
978 status = "disa 976 status = "disabled";
979 }; 977 };
980 978
981 spi18: spi@888000 { 979 spi18: spi@888000 {
982 compatible = " 980 compatible = "qcom,geni-spi";
983 reg = <0 0x008 981 reg = <0 0x00888000 0 0x4000>;
984 982
985 interrupts = < 983 interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>;
986 984
987 clocks = <&gcc 985 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
988 clock-names = 986 clock-names = "se";
989 987
990 interconnects 988 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
991 989 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
992 990 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
993 991 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
994 992 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
995 993 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
996 interconnect-n 994 interconnect-names = "qup-core",
997 995 "qup-config",
998 996 "qup-memory";
999 997
1000 dmas = <&gpi_ 998 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
1001 <&gpi_ 999 <&gpi_dma2 1 2 QCOM_GPI_SPI>;
1002 dma-names = " 1000 dma-names = "tx",
1003 " 1001 "rx";
1004 1002
1005 pinctrl-0 = < 1003 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>;
1006 pinctrl-names 1004 pinctrl-names = "default";
1007 1005
1008 #address-cell 1006 #address-cells = <1>;
1009 #size-cells = 1007 #size-cells = <0>;
1010 1008
1011 status = "dis 1009 status = "disabled";
1012 }; 1010 };
1013 1011
1014 i2c19: i2c@88c000 { 1012 i2c19: i2c@88c000 {
1015 compatible = 1013 compatible = "qcom,geni-i2c";
1016 reg = <0 0x00 1014 reg = <0 0x0088c000 0 0x4000>;
1017 1015
1018 interrupts = 1016 interrupts = <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>;
1019 1017
1020 clocks = <&gc 1018 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1021 clock-names = 1019 clock-names = "se";
1022 1020
1023 interconnects 1021 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1024 1022 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1025 1023 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1026 1024 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1027 1025 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1028 1026 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1029 interconnect- 1027 interconnect-names = "qup-core",
1030 1028 "qup-config",
1031 1029 "qup-memory";
1032 1030
1033 dmas = <&gpi_ 1031 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
1034 <&gpi_ 1032 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
1035 dma-names = " 1033 dma-names = "tx",
1036 " 1034 "rx";
1037 1035
1038 pinctrl-0 = < 1036 pinctrl-0 = <&qup_i2c19_data_clk>;
1039 pinctrl-names 1037 pinctrl-names = "default";
1040 1038
1041 #address-cell 1039 #address-cells = <1>;
1042 #size-cells = 1040 #size-cells = <0>;
1043 1041
1044 status = "dis 1042 status = "disabled";
1045 }; 1043 };
1046 1044
1047 spi19: spi@88c000 { 1045 spi19: spi@88c000 {
1048 compatible = 1046 compatible = "qcom,geni-spi";
1049 reg = <0 0x00 1047 reg = <0 0x0088c000 0 0x4000>;
1050 1048
1051 interrupts = 1049 interrupts = <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>;
1052 1050
1053 clocks = <&gc 1051 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1054 clock-names = 1052 clock-names = "se";
1055 1053
1056 interconnects 1054 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1057 1055 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1058 1056 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1059 1057 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1060 1058 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1061 1059 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1062 interconnect- 1060 interconnect-names = "qup-core",
1063 1061 "qup-config",
1064 1062 "qup-memory";
1065 1063
1066 dmas = <&gpi_ 1064 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
1067 <&gpi_ 1065 <&gpi_dma2 1 3 QCOM_GPI_SPI>;
1068 dma-names = " 1066 dma-names = "tx",
1069 " 1067 "rx";
1070 1068
1071 pinctrl-0 = < 1069 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>;
1072 pinctrl-names 1070 pinctrl-names = "default";
1073 1071
1074 #address-cell 1072 #address-cells = <1>;
1075 #size-cells = 1073 #size-cells = <0>;
1076 1074
1077 status = "dis 1075 status = "disabled";
1078 }; 1076 };
1079 1077
1080 i2c20: i2c@890000 { 1078 i2c20: i2c@890000 {
1081 compatible = 1079 compatible = "qcom,geni-i2c";
1082 reg = <0 0x00 1080 reg = <0 0x00890000 0 0x4000>;
1083 1081
1084 interrupts = 1082 interrupts = <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>;
1085 1083
1086 clocks = <&gc 1084 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1087 clock-names = 1085 clock-names = "se";
1088 1086
1089 interconnects 1087 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1090 1088 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1091 1089 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1092 1090 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1093 1091 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1094 1092 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1095 interconnect- 1093 interconnect-names = "qup-core",
1096 1094 "qup-config",
1097 1095 "qup-memory";
1098 1096
1099 dmas = <&gpi_ 1097 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1100 <&gpi_ 1098 <&gpi_dma2 1 4 QCOM_GPI_I2C>;
1101 dma-names = " 1099 dma-names = "tx",
1102 " 1100 "rx";
1103 1101
1104 pinctrl-0 = < 1102 pinctrl-0 = <&qup_i2c20_data_clk>;
1105 pinctrl-names 1103 pinctrl-names = "default";
1106 1104
1107 #address-cell 1105 #address-cells = <1>;
1108 #size-cells = 1106 #size-cells = <0>;
1109 1107
1110 status = "dis 1108 status = "disabled";
1111 }; 1109 };
1112 1110
1113 spi20: spi@890000 { 1111 spi20: spi@890000 {
1114 compatible = 1112 compatible = "qcom,geni-spi";
1115 reg = <0 0x00 1113 reg = <0 0x00890000 0 0x4000>;
1116 1114
1117 interrupts = 1115 interrupts = <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>;
1118 1116
1119 clocks = <&gc 1117 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1120 clock-names = 1118 clock-names = "se";
1121 1119
1122 interconnects 1120 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1123 1121 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1124 1122 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1125 1123 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1126 1124 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1127 1125 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1128 interconnect- 1126 interconnect-names = "qup-core",
1129 1127 "qup-config",
1130 1128 "qup-memory";
1131 1129
1132 dmas = <&gpi_ 1130 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
1133 <&gpi_ 1131 <&gpi_dma2 1 4 QCOM_GPI_SPI>;
1134 dma-names = " 1132 dma-names = "tx",
1135 " 1133 "rx";
1136 1134
1137 pinctrl-0 = < 1135 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>;
1138 pinctrl-names 1136 pinctrl-names = "default";
1139 1137
1140 #address-cell 1138 #address-cells = <1>;
1141 #size-cells = 1139 #size-cells = <0>;
1142 1140
1143 status = "dis 1141 status = "disabled";
1144 }; 1142 };
1145 1143
1146 i2c21: i2c@894000 { 1144 i2c21: i2c@894000 {
1147 compatible = 1145 compatible = "qcom,geni-i2c";
1148 reg = <0 0x00 1146 reg = <0 0x00894000 0 0x4000>;
1149 1147
1150 interrupts = 1148 interrupts = <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>;
1151 1149
1152 clocks = <&gc 1150 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1153 clock-names = 1151 clock-names = "se";
1154 1152
1155 interconnects 1153 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1156 1154 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1157 1155 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1158 1156 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1159 1157 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1160 1158 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1161 interconnect- 1159 interconnect-names = "qup-core",
1162 1160 "qup-config",
1163 1161 "qup-memory";
1164 1162
1165 dmas = <&gpi_ 1163 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1166 <&gpi_ 1164 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1167 dma-names = " 1165 dma-names = "tx",
1168 " 1166 "rx";
1169 1167
1170 pinctrl-0 = < 1168 pinctrl-0 = <&qup_i2c21_data_clk>;
1171 pinctrl-names 1169 pinctrl-names = "default";
1172 1170
1173 #address-cell 1171 #address-cells = <1>;
1174 #size-cells = 1172 #size-cells = <0>;
1175 1173
1176 status = "dis 1174 status = "disabled";
1177 }; 1175 };
1178 1176
1179 spi21: spi@894000 { 1177 spi21: spi@894000 {
1180 compatible = 1178 compatible = "qcom,geni-spi";
1181 reg = <0 0x00 1179 reg = <0 0x00894000 0 0x4000>;
1182 1180
1183 interrupts = 1181 interrupts = <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>;
1184 1182
1185 clocks = <&gc 1183 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1186 clock-names = 1184 clock-names = "se";
1187 1185
1188 interconnects 1186 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1189 1187 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1190 1188 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1191 1189 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1192 1190 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1193 1191 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1194 interconnect- 1192 interconnect-names = "qup-core",
1195 1193 "qup-config",
1196 1194 "qup-memory";
1197 1195
1198 dmas = <&gpi_ 1196 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1199 <&gpi_ 1197 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1200 dma-names = " 1198 dma-names = "tx",
1201 " 1199 "rx";
1202 1200
1203 pinctrl-0 = < 1201 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>;
1204 pinctrl-names 1202 pinctrl-names = "default";
1205 1203
1206 #address-cell 1204 #address-cells = <1>;
1207 #size-cells = 1205 #size-cells = <0>;
1208 1206
1209 status = "dis 1207 status = "disabled";
1210 }; 1208 };
1211 1209
1212 uart21: serial@894000 1210 uart21: serial@894000 {
1213 compatible = 1211 compatible = "qcom,geni-uart";
1214 reg = <0 0x00 1212 reg = <0 0x00894000 0 0x4000>;
1215 1213
1216 interrupts = 1214 interrupts = <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>;
1217 1215
1218 clocks = <&gc 1216 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1219 clock-names = 1217 clock-names = "se";
1220 1218
1221 interconnects 1219 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1222 1220 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1223 1221 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1224 1222 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
1225 interconnect- 1223 interconnect-names = "qup-core",
1226 1224 "qup-config";
1227 1225
1228 pinctrl-0 = < 1226 pinctrl-0 = <&qup_uart21_default>;
1229 pinctrl-names 1227 pinctrl-names = "default";
1230 1228
1231 status = "dis 1229 status = "disabled";
1232 }; 1230 };
1233 1231
1234 i2c22: i2c@898000 { 1232 i2c22: i2c@898000 {
1235 compatible = 1233 compatible = "qcom,geni-i2c";
1236 reg = <0 0x00 1234 reg = <0 0x00898000 0 0x4000>;
1237 1235
1238 interrupts = 1236 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
1239 1237
1240 clocks = <&gc 1238 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1241 clock-names = 1239 clock-names = "se";
1242 1240
1243 interconnects 1241 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1244 1242 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1245 1243 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1246 1244 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1247 1245 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1248 1246 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1249 interconnect- 1247 interconnect-names = "qup-core",
1250 1248 "qup-config",
1251 1249 "qup-memory";
1252 1250
1253 dmas = <&gpi_ 1251 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>,
1254 <&gpi_ 1252 <&gpi_dma2 1 6 QCOM_GPI_I2C>;
1255 dma-names = " 1253 dma-names = "tx",
1256 " 1254 "rx";
1257 1255
1258 pinctrl-0 = < 1256 pinctrl-0 = <&qup_i2c22_data_clk>;
1259 pinctrl-names 1257 pinctrl-names = "default";
1260 1258
1261 #address-cell 1259 #address-cells = <1>;
1262 #size-cells = 1260 #size-cells = <0>;
1263 1261
1264 status = "dis 1262 status = "disabled";
1265 }; 1263 };
1266 1264
1267 spi22: spi@898000 { 1265 spi22: spi@898000 {
1268 compatible = 1266 compatible = "qcom,geni-spi";
1269 reg = <0 0x00 1267 reg = <0 0x00898000 0 0x4000>;
1270 1268
1271 interrupts = 1269 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
1272 1270
1273 clocks = <&gc 1271 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1274 clock-names = 1272 clock-names = "se";
1275 1273
1276 interconnects 1274 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1277 1275 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1278 1276 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1279 1277 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1280 1278 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1281 1279 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1282 interconnect- 1280 interconnect-names = "qup-core",
1283 1281 "qup-config",
1284 1282 "qup-memory";
1285 1283
1286 dmas = <&gpi_ 1284 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>,
1287 <&gpi_ 1285 <&gpi_dma2 1 6 QCOM_GPI_SPI>;
1288 dma-names = " 1286 dma-names = "tx",
1289 " 1287 "rx";
1290 1288
1291 pinctrl-0 = < 1289 pinctrl-0 = <&qup_spi22_data_clk>, <&qup_spi22_cs>;
1292 pinctrl-names 1290 pinctrl-names = "default";
1293 1291
1294 #address-cell 1292 #address-cells = <1>;
1295 #size-cells = 1293 #size-cells = <0>;
1296 1294
1297 status = "dis 1295 status = "disabled";
1298 }; 1296 };
1299 1297
1300 i2c23: i2c@89c000 { 1298 i2c23: i2c@89c000 {
1301 compatible = 1299 compatible = "qcom,geni-i2c";
1302 reg = <0 0x00 1300 reg = <0 0x0089c000 0 0x4000>;
1303 1301
1304 interrupts = 1302 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
1305 1303
1306 clocks = <&gc 1304 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
1307 clock-names = 1305 clock-names = "se";
1308 1306
1309 interconnects 1307 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1310 1308 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1311 1309 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1312 1310 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1313 1311 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1314 1312 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1315 interconnect- 1313 interconnect-names = "qup-core",
1316 1314 "qup-config",
1317 1315 "qup-memory";
1318 1316
1319 dmas = <&gpi_ 1317 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>,
1320 <&gpi_ 1318 <&gpi_dma2 1 7 QCOM_GPI_I2C>;
1321 dma-names = " 1319 dma-names = "tx",
1322 " 1320 "rx";
1323 1321
1324 pinctrl-0 = < 1322 pinctrl-0 = <&qup_i2c23_data_clk>;
1325 pinctrl-names 1323 pinctrl-names = "default";
1326 1324
1327 #address-cell 1325 #address-cells = <1>;
1328 #size-cells = 1326 #size-cells = <0>;
1329 1327
1330 status = "dis 1328 status = "disabled";
1331 }; 1329 };
1332 1330
1333 spi23: spi@89c000 { 1331 spi23: spi@89c000 {
1334 compatible = 1332 compatible = "qcom,geni-spi";
1335 reg = <0 0x00 1333 reg = <0 0x0089c000 0 0x4000>;
1336 1334
1337 interrupts = 1335 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
1338 1336
1339 clocks = <&gc 1337 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
1340 clock-names = 1338 clock-names = "se";
1341 1339
1342 interconnects 1340 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1343 1341 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1344 1342 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1345 1343 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1346 1344 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1347 1345 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1348 interconnect- 1346 interconnect-names = "qup-core",
1349 1347 "qup-config",
1350 1348 "qup-memory";
1351 1349
1352 dmas = <&gpi_ 1350 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>,
1353 <&gpi_ 1351 <&gpi_dma2 1 7 QCOM_GPI_SPI>;
1354 dma-names = " 1352 dma-names = "tx",
1355 " 1353 "rx";
1356 1354
1357 pinctrl-0 = < 1355 pinctrl-0 = <&qup_spi23_data_clk>, <&qup_spi23_cs>;
1358 pinctrl-names 1356 pinctrl-names = "default";
1359 1357
1360 #address-cell 1358 #address-cells = <1>;
1361 #size-cells = 1359 #size-cells = <0>;
1362 1360
1363 status = "dis 1361 status = "disabled";
1364 }; 1362 };
1365 }; 1363 };
1366 1364
1367 gpi_dma1: dma-controller@a000 1365 gpi_dma1: dma-controller@a00000 {
1368 compatible = "qcom,x1 1366 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma";
1369 reg = <0 0x00a00000 0 1367 reg = <0 0x00a00000 0 0x60000>;
1370 1368
1371 interrupts = <GIC_SPI 1369 interrupts = <GIC_SPI 776 IRQ_TYPE_LEVEL_HIGH>,
1372 <GIC_SPI 1370 <GIC_SPI 777 IRQ_TYPE_LEVEL_HIGH>,
1373 <GIC_SPI 1371 <GIC_SPI 778 IRQ_TYPE_LEVEL_HIGH>,
1374 <GIC_SPI 1372 <GIC_SPI 779 IRQ_TYPE_LEVEL_HIGH>,
1375 <GIC_SPI 1373 <GIC_SPI 780 IRQ_TYPE_LEVEL_HIGH>,
1376 <GIC_SPI 1374 <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>,
1377 <GIC_SPI 1375 <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>,
1378 <GIC_SPI 1376 <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>,
1379 <GIC_SPI 1377 <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>,
1380 <GIC_SPI 1378 <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>,
1381 <GIC_SPI 1379 <GIC_SPI 786 IRQ_TYPE_LEVEL_HIGH>,
1382 <GIC_SPI 1380 <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>;
1383 1381
1384 dma-channels = <12>; 1382 dma-channels = <12>;
1385 dma-channel-mask = <0 1383 dma-channel-mask = <0x3e>;
1386 #dma-cells = <3>; 1384 #dma-cells = <3>;
1387 1385
1388 iommus = <&apps_smmu 1386 iommus = <&apps_smmu 0x136 0x0>;
1389 1387
1390 status = "disabled"; 1388 status = "disabled";
1391 }; 1389 };
1392 1390
1393 qupv3_1: geniqup@ac0000 { 1391 qupv3_1: geniqup@ac0000 {
1394 compatible = "qcom,ge 1392 compatible = "qcom,geni-se-qup";
1395 reg = <0 0x00ac0000 0 1393 reg = <0 0x00ac0000 0 0x2000>;
1396 1394
1397 clocks = <&gcc GCC_QU 1395 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1398 <&gcc GCC_QU 1396 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1399 clock-names = "m-ahb" 1397 clock-names = "m-ahb",
1400 "s-ahb" 1398 "s-ahb";
1401 1399
1402 iommus = <&apps_smmu 1400 iommus = <&apps_smmu 0x123 0x0>;
1403 1401
1404 #address-cells = <2>; 1402 #address-cells = <2>;
1405 #size-cells = <2>; 1403 #size-cells = <2>;
1406 ranges; 1404 ranges;
1407 1405
1408 status = "disabled"; 1406 status = "disabled";
1409 1407
1410 i2c8: i2c@a80000 { 1408 i2c8: i2c@a80000 {
1411 compatible = 1409 compatible = "qcom,geni-i2c";
1412 reg = <0 0x00 1410 reg = <0 0x00a80000 0 0x4000>;
1413 1411
1414 interrupts = 1412 interrupts = <GIC_SPI 800 IRQ_TYPE_LEVEL_HIGH>;
1415 1413
1416 clocks = <&gc 1414 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1417 clock-names = 1415 clock-names = "se";
1418 1416
1419 interconnects 1417 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1420 1418 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1421 1419 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1422 1420 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1423 1421 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1424 1422 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1425 interconnect- 1423 interconnect-names = "qup-core",
1426 1424 "qup-config",
1427 1425 "qup-memory";
1428 1426
1429 dmas = <&gpi_ 1427 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1430 <&gpi_ 1428 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1431 dma-names = " 1429 dma-names = "tx",
1432 " 1430 "rx";
1433 1431
1434 pinctrl-0 = < 1432 pinctrl-0 = <&qup_i2c8_data_clk>;
1435 pinctrl-names 1433 pinctrl-names = "default";
1436 1434
1437 #address-cell 1435 #address-cells = <1>;
1438 #size-cells = 1436 #size-cells = <0>;
1439 1437
1440 status = "dis 1438 status = "disabled";
1441 }; 1439 };
1442 1440
1443 spi8: spi@a80000 { 1441 spi8: spi@a80000 {
1444 compatible = 1442 compatible = "qcom,geni-spi";
1445 reg = <0 0x00 1443 reg = <0 0x00a80000 0 0x4000>;
1446 1444
1447 interrupts = 1445 interrupts = <GIC_SPI 800 IRQ_TYPE_LEVEL_HIGH>;
1448 1446
1449 clocks = <&gc 1447 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1450 clock-names = 1448 clock-names = "se";
1451 1449
1452 interconnects 1450 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1453 1451 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1454 1452 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1455 1453 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1456 1454 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1457 1455 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1458 interconnect- 1456 interconnect-names = "qup-core",
1459 1457 "qup-config",
1460 1458 "qup-memory";
1461 1459
1462 dmas = <&gpi_ 1460 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1463 <&gpi_ 1461 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1464 dma-names = " 1462 dma-names = "tx",
1465 " 1463 "rx";
1466 1464
1467 pinctrl-0 = < 1465 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1468 pinctrl-names 1466 pinctrl-names = "default";
1469 1467
1470 #address-cell 1468 #address-cells = <1>;
1471 #size-cells = 1469 #size-cells = <0>;
1472 1470
1473 status = "dis 1471 status = "disabled";
1474 }; 1472 };
1475 1473
1476 i2c9: i2c@a84000 { 1474 i2c9: i2c@a84000 {
1477 compatible = 1475 compatible = "qcom,geni-i2c";
1478 reg = <0 0x00 1476 reg = <0 0x00a84000 0 0x4000>;
1479 1477
1480 interrupts = 1478 interrupts = <GIC_SPI 801 IRQ_TYPE_LEVEL_HIGH>;
1481 1479
1482 clocks = <&gc 1480 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1483 clock-names = 1481 clock-names = "se";
1484 1482
1485 interconnects 1483 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1486 1484 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1487 1485 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1488 1486 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1489 1487 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1490 1488 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1491 interconnect- 1489 interconnect-names = "qup-core",
1492 1490 "qup-config",
1493 1491 "qup-memory";
1494 1492
1495 dmas = <&gpi_ 1493 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1496 <&gpi_ 1494 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1497 dma-names = " 1495 dma-names = "tx",
1498 " 1496 "rx";
1499 1497
1500 pinctrl-0 = < 1498 pinctrl-0 = <&qup_i2c9_data_clk>;
1501 pinctrl-names 1499 pinctrl-names = "default";
1502 1500
1503 #address-cell 1501 #address-cells = <1>;
1504 #size-cells = 1502 #size-cells = <0>;
1505 1503
1506 status = "dis 1504 status = "disabled";
1507 }; 1505 };
1508 1506
1509 spi9: spi@a84000 { 1507 spi9: spi@a84000 {
1510 compatible = 1508 compatible = "qcom,geni-spi";
1511 reg = <0 0x00 1509 reg = <0 0x00a84000 0 0x4000>;
1512 1510
1513 interrupts = 1511 interrupts = <GIC_SPI 801 IRQ_TYPE_LEVEL_HIGH>;
1514 1512
1515 clocks = <&gc 1513 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1516 clock-names = 1514 clock-names = "se";
1517 1515
1518 interconnects 1516 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1519 1517 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1520 1518 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1521 1519 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1522 1520 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1523 1521 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1524 interconnect- 1522 interconnect-names = "qup-core",
1525 1523 "qup-config",
1526 1524 "qup-memory";
1527 1525
1528 dmas = <&gpi_ 1526 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1529 <&gpi_ 1527 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1530 dma-names = " 1528 dma-names = "tx",
1531 " 1529 "rx";
1532 1530
1533 pinctrl-0 = < 1531 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1534 pinctrl-names 1532 pinctrl-names = "default";
1535 1533
1536 #address-cell 1534 #address-cells = <1>;
1537 #size-cells = 1535 #size-cells = <0>;
1538 1536
1539 status = "dis 1537 status = "disabled";
1540 }; 1538 };
1541 1539
1542 i2c10: i2c@a88000 { 1540 i2c10: i2c@a88000 {
1543 compatible = 1541 compatible = "qcom,geni-i2c";
1544 reg = <0 0x00 1542 reg = <0 0x00a88000 0 0x4000>;
1545 1543
1546 interrupts = 1544 interrupts = <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>;
1547 1545
1548 clocks = <&gc 1546 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1549 clock-names = 1547 clock-names = "se";
1550 1548
1551 interconnects 1549 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1552 1550 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1553 1551 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1554 1552 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1555 1553 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1556 1554 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1557 interconnect- 1555 interconnect-names = "qup-core",
1558 1556 "qup-config",
1559 1557 "qup-memory";
1560 1558
1561 dmas = <&gpi_ 1559 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1562 <&gpi_ 1560 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1563 dma-names = " 1561 dma-names = "tx",
1564 " 1562 "rx";
1565 1563
1566 pinctrl-0 = < 1564 pinctrl-0 = <&qup_i2c10_data_clk>;
1567 pinctrl-names 1565 pinctrl-names = "default";
1568 1566
1569 #address-cell 1567 #address-cells = <1>;
1570 #size-cells = 1568 #size-cells = <0>;
1571 1569
1572 status = "dis 1570 status = "disabled";
1573 }; 1571 };
1574 1572
1575 spi10: spi@a88000 { 1573 spi10: spi@a88000 {
1576 compatible = 1574 compatible = "qcom,geni-spi";
1577 reg = <0 0x00 1575 reg = <0 0x00a88000 0 0x4000>;
1578 1576
1579 interrupts = 1577 interrupts = <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>;
1580 1578
1581 clocks = <&gc 1579 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1582 clock-names = 1580 clock-names = "se";
1583 1581
1584 interconnects 1582 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1585 1583 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1586 1584 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1587 1585 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1588 1586 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1589 1587 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1590 interconnect- 1588 interconnect-names = "qup-core",
1591 1589 "qup-config",
1592 1590 "qup-memory";
1593 1591
1594 dmas = <&gpi_ 1592 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1595 <&gpi_ 1593 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1596 dma-names = " 1594 dma-names = "tx",
1597 " 1595 "rx";
1598 1596
1599 pinctrl-0 = < 1597 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1600 pinctrl-names 1598 pinctrl-names = "default";
1601 1599
1602 #address-cell 1600 #address-cells = <1>;
1603 #size-cells = 1601 #size-cells = <0>;
1604 1602
1605 status = "dis 1603 status = "disabled";
1606 }; 1604 };
1607 1605
1608 i2c11: i2c@a8c000 { 1606 i2c11: i2c@a8c000 {
1609 compatible = 1607 compatible = "qcom,geni-i2c";
1610 reg = <0 0x00 1608 reg = <0 0x00a8c000 0 0x4000>;
1611 1609
1612 interrupts = 1610 interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>;
1613 1611
1614 clocks = <&gc 1612 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1615 clock-names = 1613 clock-names = "se";
1616 1614
1617 interconnects 1615 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1618 1616 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1619 1617 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1620 1618 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1621 1619 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1622 1620 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1623 interconnect- 1621 interconnect-names = "qup-core",
1624 1622 "qup-config",
1625 1623 "qup-memory";
1626 1624
1627 dmas = <&gpi_ 1625 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1628 <&gpi_ 1626 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1629 dma-names = " 1627 dma-names = "tx",
1630 " 1628 "rx";
1631 1629
1632 pinctrl-0 = < 1630 pinctrl-0 = <&qup_i2c11_data_clk>;
1633 pinctrl-names 1631 pinctrl-names = "default";
1634 1632
1635 #address-cell 1633 #address-cells = <1>;
1636 #size-cells = 1634 #size-cells = <0>;
1637 1635
1638 status = "dis 1636 status = "disabled";
1639 }; 1637 };
1640 1638
1641 spi11: spi@a8c000 { 1639 spi11: spi@a8c000 {
1642 compatible = 1640 compatible = "qcom,geni-spi";
1643 reg = <0 0x00 1641 reg = <0 0x00a8c000 0 0x4000>;
1644 1642
1645 interrupts = 1643 interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>;
1646 1644
1647 clocks = <&gc 1645 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1648 clock-names = 1646 clock-names = "se";
1649 1647
1650 interconnects 1648 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1651 1649 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1652 1650 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1653 1651 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1654 1652 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1655 1653 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1656 interconnect- 1654 interconnect-names = "qup-core",
1657 1655 "qup-config",
1658 1656 "qup-memory";
1659 1657
1660 dmas = <&gpi_ 1658 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1661 <&gpi_ 1659 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1662 dma-names = " 1660 dma-names = "tx",
1663 " 1661 "rx";
1664 1662
1665 pinctrl-0 = < 1663 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1666 pinctrl-names 1664 pinctrl-names = "default";
1667 1665
1668 #address-cell 1666 #address-cells = <1>;
1669 #size-cells = 1667 #size-cells = <0>;
1670 1668
1671 status = "dis 1669 status = "disabled";
1672 }; 1670 };
1673 1671
1674 i2c12: i2c@a90000 { 1672 i2c12: i2c@a90000 {
1675 compatible = 1673 compatible = "qcom,geni-i2c";
1676 reg = <0 0x00 1674 reg = <0 0x00a90000 0 0x4000>;
1677 1675
1678 interrupts = 1676 interrupts = <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>;
1679 1677
1680 clocks = <&gc 1678 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1681 clock-names = 1679 clock-names = "se";
1682 1680
1683 interconnects 1681 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1684 1682 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1685 1683 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1686 1684 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1687 1685 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1688 1686 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1689 interconnect- 1687 interconnect-names = "qup-core",
1690 1688 "qup-config",
1691 1689 "qup-memory";
1692 1690
1693 dmas = <&gpi_ 1691 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1694 <&gpi_ 1692 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1695 dma-names = " 1693 dma-names = "tx",
1696 " 1694 "rx";
1697 1695
1698 pinctrl-0 = < 1696 pinctrl-0 = <&qup_i2c12_data_clk>;
1699 pinctrl-names 1697 pinctrl-names = "default";
1700 1698
1701 #address-cell 1699 #address-cells = <1>;
1702 #size-cells = 1700 #size-cells = <0>;
1703 1701
1704 status = "dis 1702 status = "disabled";
1705 }; 1703 };
1706 1704
1707 spi12: spi@a90000 { 1705 spi12: spi@a90000 {
1708 compatible = 1706 compatible = "qcom,geni-spi";
1709 reg = <0 0x00 1707 reg = <0 0x00a90000 0 0x4000>;
1710 1708
1711 interrupts = 1709 interrupts = <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>;
1712 1710
1713 clocks = <&gc 1711 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1714 clock-names = 1712 clock-names = "se";
1715 1713
1716 interconnects 1714 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1717 1715 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1718 1716 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1719 1717 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1720 1718 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1721 1719 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1722 interconnect- 1720 interconnect-names = "qup-core",
1723 1721 "qup-config",
1724 1722 "qup-memory";
1725 1723
1726 dmas = <&gpi_ 1724 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1727 <&gpi_ 1725 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1728 dma-names = " 1726 dma-names = "tx",
1729 " 1727 "rx";
1730 1728
1731 pinctrl-0 = < 1729 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1732 pinctrl-names 1730 pinctrl-names = "default";
1733 1731
1734 #address-cell 1732 #address-cells = <1>;
1735 #size-cells = 1733 #size-cells = <0>;
1736 1734
1737 status = "dis 1735 status = "disabled";
1738 }; 1736 };
1739 1737
1740 i2c13: i2c@a94000 { 1738 i2c13: i2c@a94000 {
1741 compatible = 1739 compatible = "qcom,geni-i2c";
1742 reg = <0 0x00 1740 reg = <0 0x00a94000 0 0x4000>;
1743 1741
1744 interrupts = 1742 interrupts = <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>;
1745 1743
1746 clocks = <&gc 1744 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1747 clock-names = 1745 clock-names = "se";
1748 1746
1749 interconnects 1747 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1750 1748 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1751 1749 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1752 1750 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1753 1751 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1754 1752 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1755 interconnect- 1753 interconnect-names = "qup-core",
1756 1754 "qup-config",
1757 1755 "qup-memory";
1758 1756
1759 dmas = <&gpi_ 1757 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1760 <&gpi_ 1758 <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1761 dma-names = " 1759 dma-names = "tx",
1762 " 1760 "rx";
1763 1761
1764 pinctrl-0 = < 1762 pinctrl-0 = <&qup_i2c13_data_clk>;
1765 pinctrl-names 1763 pinctrl-names = "default";
1766 1764
1767 #address-cell 1765 #address-cells = <1>;
1768 #size-cells = 1766 #size-cells = <0>;
1769 1767
1770 status = "dis 1768 status = "disabled";
1771 }; 1769 };
1772 1770
1773 spi13: spi@a94000 { 1771 spi13: spi@a94000 {
1774 compatible = 1772 compatible = "qcom,geni-spi";
1775 reg = <0 0x00 1773 reg = <0 0x00a94000 0 0x4000>;
1776 1774
1777 interrupts = 1775 interrupts = <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>;
1778 1776
1779 clocks = <&gc 1777 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1780 clock-names = 1778 clock-names = "se";
1781 1779
1782 interconnects 1780 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1783 1781 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1784 1782 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1785 1783 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1786 1784 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1787 1785 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1788 interconnect- 1786 interconnect-names = "qup-core",
1789 1787 "qup-config",
1790 1788 "qup-memory";
1791 1789
1792 dmas = <&gpi_ 1790 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1793 <&gpi_ 1791 <&gpi_dma1 1 5 QCOM_GPI_SPI>;
1794 dma-names = " 1792 dma-names = "tx",
1795 " 1793 "rx";
1796 1794
1797 pinctrl-0 = < 1795 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1798 pinctrl-names 1796 pinctrl-names = "default";
1799 1797
1800 #address-cell 1798 #address-cells = <1>;
1801 #size-cells = 1799 #size-cells = <0>;
1802 1800
1803 status = "dis 1801 status = "disabled";
1804 }; 1802 };
1805 1803
1806 i2c14: i2c@a98000 { 1804 i2c14: i2c@a98000 {
1807 compatible = 1805 compatible = "qcom,geni-i2c";
1808 reg = <0 0x00 1806 reg = <0 0x00a98000 0 0x4000>;
1809 1807
1810 interrupts = 1808 interrupts = <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>;
1811 1809
1812 clocks = <&gc 1810 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1813 clock-names = 1811 clock-names = "se";
1814 1812
1815 interconnects 1813 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1816 1814 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1817 1815 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1818 1816 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1819 1817 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1820 1818 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1821 interconnect- 1819 interconnect-names = "qup-core",
1822 1820 "qup-config",
1823 1821 "qup-memory";
1824 1822
1825 dmas = <&gpi_ 1823 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
1826 <&gpi_ 1824 <&gpi_dma1 1 6 QCOM_GPI_I2C>;
1827 dma-names = " 1825 dma-names = "tx",
1828 " 1826 "rx";
1829 1827
1830 pinctrl-0 = < 1828 pinctrl-0 = <&qup_i2c14_data_clk>;
1831 pinctrl-names 1829 pinctrl-names = "default";
1832 1830
1833 #address-cell 1831 #address-cells = <1>;
1834 #size-cells = 1832 #size-cells = <0>;
1835 1833
1836 status = "dis 1834 status = "disabled";
1837 }; 1835 };
1838 1836
1839 spi14: spi@a98000 { 1837 spi14: spi@a98000 {
1840 compatible = 1838 compatible = "qcom,geni-spi";
1841 reg = <0 0x00 1839 reg = <0 0x00a98000 0 0x4000>;
1842 1840
1843 interrupts = 1841 interrupts = <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>;
1844 1842
1845 clocks = <&gc 1843 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1846 clock-names = 1844 clock-names = "se";
1847 1845
1848 interconnects 1846 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1849 1847 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1850 1848 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1851 1849 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1852 1850 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1853 1851 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1854 interconnect- 1852 interconnect-names = "qup-core",
1855 1853 "qup-config",
1856 1854 "qup-memory";
1857 1855
1858 dmas = <&gpi_ 1856 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
1859 <&gpi_ 1857 <&gpi_dma1 1 6 QCOM_GPI_SPI>;
1860 dma-names = " 1858 dma-names = "tx",
1861 " 1859 "rx";
1862 1860
1863 pinctrl-0 = < 1861 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
1864 pinctrl-names 1862 pinctrl-names = "default";
1865 1863
1866 #address-cell 1864 #address-cells = <1>;
1867 #size-cells = 1865 #size-cells = <0>;
1868 1866
1869 status = "dis 1867 status = "disabled";
1870 }; 1868 };
1871 1869
1872 i2c15: i2c@a9c000 { 1870 i2c15: i2c@a9c000 {
1873 compatible = 1871 compatible = "qcom,geni-i2c";
1874 reg = <0 0x00 1872 reg = <0 0x00a9c000 0 0x4000>;
1875 1873
1876 interrupts = 1874 interrupts = <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>;
1877 1875
1878 clocks = <&gc 1876 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1879 clock-names = 1877 clock-names = "se";
1880 1878
1881 interconnects 1879 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1882 1880 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1883 1881 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1884 1882 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1885 1883 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1886 1884 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1887 interconnect- 1885 interconnect-names = "qup-core",
1888 1886 "qup-config",
1889 1887 "qup-memory";
1890 1888
1891 dmas = <&gpi_ 1889 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
1892 <&gpi_ 1890 <&gpi_dma1 1 7 QCOM_GPI_I2C>;
1893 dma-names = " 1891 dma-names = "tx",
1894 " 1892 "rx";
1895 1893
1896 pinctrl-0 = < 1894 pinctrl-0 = <&qup_i2c15_data_clk>;
1897 pinctrl-names 1895 pinctrl-names = "default";
1898 1896
1899 #address-cell 1897 #address-cells = <1>;
1900 #size-cells = 1898 #size-cells = <0>;
1901 1899
1902 status = "dis 1900 status = "disabled";
1903 }; 1901 };
1904 1902
1905 spi15: spi@a9c000 { 1903 spi15: spi@a9c000 {
1906 compatible = 1904 compatible = "qcom,geni-spi";
1907 reg = <0 0x00 1905 reg = <0 0x00a9c000 0 0x4000>;
1908 1906
1909 interrupts = 1907 interrupts = <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>;
1910 1908
1911 clocks = <&gc 1909 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1912 clock-names = 1910 clock-names = "se";
1913 1911
1914 interconnects 1912 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1915 1913 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1916 1914 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1917 1915 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1918 1916 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1919 1917 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1920 interconnect- 1918 interconnect-names = "qup-core",
1921 1919 "qup-config",
1922 1920 "qup-memory";
1923 1921
1924 dmas = <&gpi_ 1922 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>,
1925 <&gpi_ 1923 <&gpi_dma1 1 7 QCOM_GPI_SPI>;
1926 dma-names = " 1924 dma-names = "tx",
1927 " 1925 "rx";
1928 1926
1929 pinctrl-0 = < 1927 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
1930 pinctrl-names 1928 pinctrl-names = "default";
1931 1929
1932 #address-cell 1930 #address-cells = <1>;
1933 #size-cells = 1931 #size-cells = <0>;
1934 1932
1935 status = "dis 1933 status = "disabled";
1936 }; 1934 };
1937 }; 1935 };
1938 1936
1939 gpi_dma0: dma-controller@b000 1937 gpi_dma0: dma-controller@b00000 {
1940 compatible = "qcom,x1 1938 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma";
1941 reg = <0 0x00b00000 0 1939 reg = <0 0x00b00000 0 0x60000>;
1942 1940
1943 interrupts = <GIC_SPI 1941 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
1944 <GIC_SPI 1942 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
1945 <GIC_SPI 1943 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
1946 <GIC_SPI 1944 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
1947 <GIC_SPI 1945 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
1948 <GIC_SPI 1946 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
1949 <GIC_SPI 1947 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
1950 <GIC_SPI 1948 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
1951 <GIC_SPI 1949 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
1952 <GIC_SPI 1950 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
1953 <GIC_SPI 1951 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
1954 <GIC_SPI 1952 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
1955 1953
1956 dma-channels = <12>; 1954 dma-channels = <12>;
1957 dma-channel-mask = <0 1955 dma-channel-mask = <0x3e>;
1958 #dma-cells = <3>; 1956 #dma-cells = <3>;
1959 1957
1960 iommus = <&apps_smmu 1958 iommus = <&apps_smmu 0x456 0x0>;
1961 1959
1962 status = "disabled"; 1960 status = "disabled";
1963 }; 1961 };
1964 1962
1965 qupv3_0: geniqup@bc0000 { 1963 qupv3_0: geniqup@bc0000 {
1966 compatible = "qcom,ge 1964 compatible = "qcom,geni-se-qup";
1967 reg = <0 0x00bc0000 0 1965 reg = <0 0x00bc0000 0 0x2000>;
1968 1966
1969 clocks = <&gcc GCC_QU 1967 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1970 <&gcc GCC_QU 1968 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1971 clock-names = "m-ahb" 1969 clock-names = "m-ahb",
1972 "s-ahb" 1970 "s-ahb";
1973 1971
1974 iommus = <&apps_smmu 1972 iommus = <&apps_smmu 0x443 0x0>;
1975 #address-cells = <2>; 1973 #address-cells = <2>;
1976 #size-cells = <2>; 1974 #size-cells = <2>;
1977 ranges; 1975 ranges;
1978 1976
1979 status = "disabled"; 1977 status = "disabled";
1980 1978
1981 i2c0: i2c@b80000 { 1979 i2c0: i2c@b80000 {
1982 compatible = 1980 compatible = "qcom,geni-i2c";
1983 reg = <0 0x00 !! 1981 reg = <0 0xb80000 0 0x4000>;
1984 1982
1985 interrupts = 1983 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1986 1984
1987 clocks = <&gc 1985 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1988 clock-names = 1986 clock-names = "se";
1989 1987
1990 interconnects 1988 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1991 1989 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1992 1990 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1993 1991 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
1994 1992 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
1995 1993 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1996 interconnect- 1994 interconnect-names = "qup-core",
1997 1995 "qup-config",
1998 1996 "qup-memory";
1999 1997
2000 dmas = <&gpi_ 1998 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
2001 <&gpi_ 1999 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
2002 dma-names = " 2000 dma-names = "tx",
2003 " 2001 "rx";
2004 2002
2005 pinctrl-0 = < 2003 pinctrl-0 = <&qup_i2c0_data_clk>;
2006 pinctrl-names 2004 pinctrl-names = "default";
2007 2005
2008 #address-cell 2006 #address-cells = <1>;
2009 #size-cells = 2007 #size-cells = <0>;
2010 2008
2011 status = "dis 2009 status = "disabled";
2012 }; 2010 };
2013 2011
2014 spi0: spi@b80000 { 2012 spi0: spi@b80000 {
2015 compatible = 2013 compatible = "qcom,geni-spi";
2016 reg = <0 0x00 2014 reg = <0 0x00b80000 0 0x4000>;
2017 2015
2018 interrupts = 2016 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
2019 2017
2020 clocks = <&gc 2018 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
2021 clock-names = 2019 clock-names = "se";
2022 2020
2023 interconnects 2021 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2024 2022 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2025 2023 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2026 2024 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2027 2025 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2028 2026 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2029 interconnect- 2027 interconnect-names = "qup-core",
2030 2028 "qup-config",
2031 2029 "qup-memory";
2032 2030
2033 dmas = <&gpi_ 2031 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
2034 <&gpi_ 2032 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
2035 dma-names = " 2033 dma-names = "tx",
2036 " 2034 "rx";
2037 2035
2038 pinctrl-0 = < 2036 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
2039 pinctrl-names 2037 pinctrl-names = "default";
2040 2038
2041 #address-cell 2039 #address-cells = <1>;
2042 #size-cells = 2040 #size-cells = <0>;
2043 2041
2044 status = "dis 2042 status = "disabled";
2045 }; 2043 };
2046 2044
2047 i2c1: i2c@b84000 { 2045 i2c1: i2c@b84000 {
2048 compatible = 2046 compatible = "qcom,geni-i2c";
2049 reg = <0 0x00 2047 reg = <0 0x00b84000 0 0x4000>;
2050 2048
2051 interrupts = 2049 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
2052 2050
2053 clocks = <&gc 2051 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
2054 clock-names = 2052 clock-names = "se";
2055 2053
2056 interconnects 2054 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2057 2055 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2058 2056 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2059 2057 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2060 2058 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2061 2059 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2062 interconnect- 2060 interconnect-names = "qup-core",
2063 2061 "qup-config",
2064 2062 "qup-memory";
2065 2063
2066 dmas = <&gpi_ 2064 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
2067 <&gpi_ 2065 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
2068 dma-names = " 2066 dma-names = "tx",
2069 " 2067 "rx";
2070 2068
2071 pinctrl-0 = < 2069 pinctrl-0 = <&qup_i2c1_data_clk>;
2072 pinctrl-names 2070 pinctrl-names = "default";
2073 2071
2074 #address-cell 2072 #address-cells = <1>;
2075 #size-cells = 2073 #size-cells = <0>;
2076 2074
2077 status = "dis 2075 status = "disabled";
2078 }; 2076 };
2079 2077
2080 spi1: spi@b84000 { 2078 spi1: spi@b84000 {
2081 compatible = 2079 compatible = "qcom,geni-spi";
2082 reg = <0 0x00 2080 reg = <0 0x00b84000 0 0x4000>;
2083 2081
2084 interrupts = 2082 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
2085 2083
2086 clocks = <&gc 2084 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
2087 clock-names = 2085 clock-names = "se";
2088 2086
2089 interconnects 2087 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2090 2088 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2091 2089 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2092 2090 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2093 2091 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2094 2092 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2095 interconnect- 2093 interconnect-names = "qup-core",
2096 2094 "qup-config",
2097 2095 "qup-memory";
2098 2096
2099 dmas = <&gpi_ 2097 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
2100 <&gpi_ 2098 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
2101 dma-names = " 2099 dma-names = "tx",
2102 " 2100 "rx";
2103 2101
2104 pinctrl-0 = < 2102 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
2105 pinctrl-names 2103 pinctrl-names = "default";
2106 2104
2107 #address-cell 2105 #address-cells = <1>;
2108 #size-cells = 2106 #size-cells = <0>;
2109 2107
2110 status = "dis 2108 status = "disabled";
2111 }; 2109 };
2112 2110
2113 i2c2: i2c@b88000 { 2111 i2c2: i2c@b88000 {
2114 compatible = 2112 compatible = "qcom,geni-i2c";
2115 reg = <0 0x00 2113 reg = <0 0x00b88000 0 0x4000>;
2116 2114
2117 interrupts = 2115 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
2118 2116
2119 clocks = <&gc 2117 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
2120 clock-names = 2118 clock-names = "se";
2121 2119
2122 interconnects 2120 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2123 2121 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2124 2122 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2125 2123 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2126 2124 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2127 2125 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2128 interconnect- 2126 interconnect-names = "qup-core",
2129 2127 "qup-config",
2130 2128 "qup-memory";
2131 2129
2132 dmas = <&gpi_ 2130 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
2133 <&gpi_ 2131 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
2134 dma-names = " 2132 dma-names = "tx",
2135 " 2133 "rx";
2136 2134
2137 pinctrl-0 = < 2135 pinctrl-0 = <&qup_i2c2_data_clk>;
2138 pinctrl-names 2136 pinctrl-names = "default";
2139 2137
2140 #address-cell 2138 #address-cells = <1>;
2141 #size-cells = 2139 #size-cells = <0>;
2142 2140
2143 status = "dis 2141 status = "disabled";
2144 }; 2142 };
2145 2143
2146 uart2: serial@b88000 <<
2147 compatible = <<
2148 reg = <0 0x00 <<
2149 <<
2150 interrupts = <<
2151 <<
2152 clocks = <&gc <<
2153 clock-names = <<
2154 <<
2155 interconnects <<
2156 <<
2157 <<
2158 <<
2159 interconnect- <<
2160 <<
2161 <<
2162 pinctrl-0 = < <<
2163 pinctrl-names <<
2164 <<
2165 status = "dis <<
2166 }; <<
2167 <<
2168 spi2: spi@b88000 { 2144 spi2: spi@b88000 {
2169 compatible = 2145 compatible = "qcom,geni-spi";
2170 reg = <0 0x00 !! 2146 reg = <0 0xb88000 0 0x4000>;
2171 2147
2172 interrupts = 2148 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
2173 2149
2174 clocks = <&gc 2150 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
2175 clock-names = 2151 clock-names = "se";
2176 2152
2177 interconnects 2153 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2178 2154 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2179 2155 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2180 2156 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2181 2157 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2182 2158 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2183 interconnect- 2159 interconnect-names = "qup-core",
2184 2160 "qup-config",
2185 2161 "qup-memory";
2186 2162
2187 dmas = <&gpi_ 2163 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
2188 <&gpi_ 2164 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
2189 dma-names = " 2165 dma-names = "tx",
2190 " 2166 "rx";
2191 2167
2192 pinctrl-0 = < 2168 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
2193 pinctrl-names 2169 pinctrl-names = "default";
2194 2170
2195 #address-cell 2171 #address-cells = <1>;
2196 #size-cells = 2172 #size-cells = <0>;
2197 2173
2198 status = "dis 2174 status = "disabled";
2199 }; 2175 };
2200 2176
2201 i2c3: i2c@b8c000 { 2177 i2c3: i2c@b8c000 {
2202 compatible = 2178 compatible = "qcom,geni-i2c";
2203 reg = <0 0x00 2179 reg = <0 0x00b8c000 0 0x4000>;
2204 2180
2205 interrupts = 2181 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
2206 2182
2207 clocks = <&gc 2183 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
2208 clock-names = 2184 clock-names = "se";
2209 2185
2210 interconnects 2186 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2211 2187 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2212 2188 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2213 2189 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2214 2190 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2215 2191 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2216 interconnect- 2192 interconnect-names = "qup-core",
2217 2193 "qup-config",
2218 2194 "qup-memory";
2219 2195
2220 dmas = <&gpi_ 2196 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
2221 <&gpi_ 2197 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
2222 dma-names = " 2198 dma-names = "tx",
2223 " 2199 "rx";
2224 2200
2225 pinctrl-0 = < 2201 pinctrl-0 = <&qup_i2c3_data_clk>;
2226 pinctrl-names 2202 pinctrl-names = "default";
2227 2203
2228 #address-cell 2204 #address-cells = <1>;
2229 #size-cells = 2205 #size-cells = <0>;
2230 2206
2231 status = "dis 2207 status = "disabled";
2232 }; 2208 };
2233 2209
2234 spi3: spi@b8c000 { 2210 spi3: spi@b8c000 {
2235 compatible = 2211 compatible = "qcom,geni-spi";
2236 reg = <0 0x00 2212 reg = <0 0x00b8c000 0 0x4000>;
2237 2213
2238 interrupts = 2214 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
2239 2215
2240 clocks = <&gc 2216 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
2241 clock-names = 2217 clock-names = "se";
2242 2218
2243 interconnects 2219 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2244 2220 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2245 2221 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2246 2222 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2247 2223 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2248 2224 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2249 interconnect- 2225 interconnect-names = "qup-core",
2250 2226 "qup-config",
2251 2227 "qup-memory";
2252 2228
2253 dmas = <&gpi_ 2229 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
2254 <&gpi_ 2230 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
2255 dma-names = " 2231 dma-names = "tx",
2256 " 2232 "rx";
2257 2233
2258 pinctrl-0 = < 2234 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
2259 pinctrl-names 2235 pinctrl-names = "default";
2260 2236
2261 #address-cell 2237 #address-cells = <1>;
2262 #size-cells = 2238 #size-cells = <0>;
2263 2239
2264 status = "dis 2240 status = "disabled";
2265 }; 2241 };
2266 2242
2267 i2c4: i2c@b90000 { 2243 i2c4: i2c@b90000 {
2268 compatible = 2244 compatible = "qcom,geni-i2c";
2269 reg = <0 0x00 !! 2245 reg = <0 0xb90000 0 0x4000>;
2270 2246
2271 interrupts = 2247 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
2272 2248
2273 clocks = <&gc 2249 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
2274 clock-names = 2250 clock-names = "se";
2275 2251
2276 interconnects 2252 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2277 2253 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2278 2254 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2279 2255 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2280 2256 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2281 2257 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2282 interconnect- 2258 interconnect-names = "qup-core",
2283 2259 "qup-config",
2284 2260 "qup-memory";
2285 2261
2286 dmas = <&gpi_ 2262 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
2287 <&gpi_ 2263 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
2288 dma-names = " 2264 dma-names = "tx",
2289 " 2265 "rx";
2290 2266
2291 pinctrl-0 = < 2267 pinctrl-0 = <&qup_i2c4_data_clk>;
2292 pinctrl-names 2268 pinctrl-names = "default";
2293 2269
2294 #address-cell 2270 #address-cells = <1>;
2295 #size-cells = 2271 #size-cells = <0>;
2296 2272
2297 status = "dis 2273 status = "disabled";
2298 }; 2274 };
2299 2275
2300 spi4: spi@b90000 { 2276 spi4: spi@b90000 {
2301 compatible = 2277 compatible = "qcom,geni-spi";
2302 reg = <0 0x00 2278 reg = <0 0x00b90000 0 0x4000>;
2303 2279
2304 interrupts = 2280 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
2305 2281
2306 clocks = <&gc 2282 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
2307 clock-names = 2283 clock-names = "se";
2308 2284
2309 interconnects 2285 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2310 2286 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2311 2287 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2312 2288 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2313 2289 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2314 2290 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2315 interconnect- 2291 interconnect-names = "qup-core",
2316 2292 "qup-config",
2317 2293 "qup-memory";
2318 2294
2319 dmas = <&gpi_ 2295 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
2320 <&gpi_ 2296 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
2321 dma-names = " 2297 dma-names = "tx",
2322 " 2298 "rx";
2323 2299
2324 pinctrl-0 = < 2300 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
2325 pinctrl-names 2301 pinctrl-names = "default";
2326 2302
2327 #address-cell 2303 #address-cells = <1>;
2328 #size-cells = 2304 #size-cells = <0>;
2329 2305
2330 status = "dis 2306 status = "disabled";
2331 }; 2307 };
2332 2308
2333 i2c5: i2c@b94000 { 2309 i2c5: i2c@b94000 {
2334 compatible = 2310 compatible = "qcom,geni-i2c";
2335 reg = <0 0x00 2311 reg = <0 0x00b94000 0 0x4000>;
2336 2312
2337 interrupts = 2313 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
2338 2314
2339 clocks = <&gc 2315 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
2340 clock-names = 2316 clock-names = "se";
2341 2317
2342 interconnects 2318 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2343 2319 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2344 2320 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2345 2321 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2346 2322 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2347 2323 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2348 interconnect- 2324 interconnect-names = "qup-core",
2349 2325 "qup-config",
2350 2326 "qup-memory";
2351 2327
2352 dmas = <&gpi_ 2328 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
2353 <&gpi_ 2329 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
2354 dma-names = " 2330 dma-names = "tx",
2355 " 2331 "rx";
2356 2332
2357 pinctrl-0 = < 2333 pinctrl-0 = <&qup_i2c5_data_clk>;
2358 pinctrl-names 2334 pinctrl-names = "default";
2359 2335
2360 #address-cell 2336 #address-cells = <1>;
2361 #size-cells = 2337 #size-cells = <0>;
2362 2338
2363 status = "dis 2339 status = "disabled";
2364 }; 2340 };
2365 2341
2366 spi5: spi@b94000 { 2342 spi5: spi@b94000 {
2367 compatible = 2343 compatible = "qcom,geni-spi";
2368 reg = <0 0x00 2344 reg = <0 0x00b94000 0 0x4000>;
2369 2345
2370 interrupts = 2346 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
2371 2347
2372 clocks = <&gc 2348 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
2373 clock-names = 2349 clock-names = "se";
2374 2350
2375 interconnects 2351 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2376 2352 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2377 2353 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2378 2354 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2379 2355 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2380 2356 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2381 interconnect- 2357 interconnect-names = "qup-core",
2382 2358 "qup-config",
2383 2359 "qup-memory";
2384 2360
2385 dmas = <&gpi_ 2361 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
2386 <&gpi_ 2362 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
2387 dma-names = " 2363 dma-names = "tx",
2388 " 2364 "rx";
2389 2365
2390 pinctrl-0 = < 2366 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
2391 pinctrl-names 2367 pinctrl-names = "default";
2392 2368
2393 #address-cell 2369 #address-cells = <1>;
2394 #size-cells = 2370 #size-cells = <0>;
2395 2371
2396 status = "dis 2372 status = "disabled";
2397 }; 2373 };
2398 2374
2399 i2c6: i2c@b98000 { 2375 i2c6: i2c@b98000 {
2400 compatible = 2376 compatible = "qcom,geni-i2c";
2401 reg = <0 0x00 2377 reg = <0 0x00b98000 0 0x4000>;
2402 2378
2403 interrupts = 2379 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
2404 2380
2405 clocks = <&gc 2381 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
2406 clock-names = 2382 clock-names = "se";
2407 2383
2408 interconnects 2384 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2409 2385 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2410 2386 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2411 2387 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2412 2388 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2413 2389 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2414 interconnect- 2390 interconnect-names = "qup-core",
2415 2391 "qup-config",
2416 2392 "qup-memory";
2417 2393
2418 dmas = <&gpi_ 2394 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
2419 <&gpi_ 2395 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
2420 dma-names = " 2396 dma-names = "tx",
2421 " 2397 "rx";
2422 2398
2423 pinctrl-0 = < 2399 pinctrl-0 = <&qup_i2c6_data_clk>;
2424 pinctrl-names 2400 pinctrl-names = "default";
2425 2401
2426 #address-cell 2402 #address-cells = <1>;
2427 #size-cells = 2403 #size-cells = <0>;
2428 2404
2429 status = "dis 2405 status = "disabled";
2430 }; 2406 };
2431 2407
2432 spi6: spi@b98000 { 2408 spi6: spi@b98000 {
2433 compatible = 2409 compatible = "qcom,geni-spi";
2434 reg = <0 0x00 2410 reg = <0 0x00b98000 0 0x4000>;
2435 2411
2436 interrupts = 2412 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
2437 2413
2438 clocks = <&gc 2414 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
2439 clock-names = 2415 clock-names = "se";
2440 2416
2441 interconnects 2417 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2442 2418 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2443 2419 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2444 2420 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2445 2421 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2446 2422 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2447 interconnect- 2423 interconnect-names = "qup-core",
2448 2424 "qup-config",
2449 2425 "qup-memory";
2450 2426
2451 dmas = <&gpi_ 2427 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
2452 <&gpi_ 2428 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
2453 dma-names = " 2429 dma-names = "tx",
2454 " 2430 "rx";
2455 2431
2456 pinctrl-0 = < 2432 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
2457 pinctrl-names 2433 pinctrl-names = "default";
2458 2434
2459 #address-cell 2435 #address-cells = <1>;
2460 #size-cells = 2436 #size-cells = <0>;
2461 2437
2462 status = "dis 2438 status = "disabled";
2463 }; 2439 };
2464 2440
2465 i2c7: i2c@b9c000 { 2441 i2c7: i2c@b9c000 {
2466 compatible = 2442 compatible = "qcom,geni-i2c";
2467 reg = <0 0x00 2443 reg = <0 0x00b9c000 0 0x4000>;
2468 2444
2469 interrupts = 2445 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
2470 2446
2471 clocks = <&gc 2447 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
2472 clock-names = 2448 clock-names = "se";
2473 2449
2474 interconnects 2450 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2475 2451 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2476 2452 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2477 2453 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2478 2454 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2479 2455 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2480 interconnect- 2456 interconnect-names = "qup-core",
2481 2457 "qup-config",
2482 2458 "qup-memory";
2483 2459
2484 dmas = <&gpi_ 2460 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
2485 <&gpi_ 2461 <&gpi_dma0 1 7 QCOM_GPI_I2C>;
2486 dma-names = " 2462 dma-names = "tx",
2487 " 2463 "rx";
2488 2464
2489 pinctrl-0 = < 2465 pinctrl-0 = <&qup_i2c7_data_clk>;
2490 pinctrl-names 2466 pinctrl-names = "default";
2491 2467
2492 #address-cell 2468 #address-cells = <1>;
2493 #size-cells = 2469 #size-cells = <0>;
2494 2470
2495 status = "dis 2471 status = "disabled";
2496 }; 2472 };
2497 2473
2498 spi7: spi@b9c000 { 2474 spi7: spi@b9c000 {
2499 compatible = 2475 compatible = "qcom,geni-spi";
2500 reg = <0 0x00 2476 reg = <0 0x00b9c000 0 0x4000>;
2501 2477
2502 interrupts = 2478 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
2503 2479
2504 clocks = <&gc 2480 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
2505 clock-names = 2481 clock-names = "se";
2506 2482
2507 interconnects 2483 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2508 2484 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2509 2485 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2510 2486 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2511 2487 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2512 2488 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2513 interconnect- 2489 interconnect-names = "qup-core",
2514 2490 "qup-config",
2515 2491 "qup-memory";
2516 2492
2517 dmas = <&gpi_ 2493 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
2518 <&gpi_ 2494 <&gpi_dma0 1 7 QCOM_GPI_SPI>;
2519 dma-names = " 2495 dma-names = "tx",
2520 " 2496 "rx";
2521 2497
2522 pinctrl-0 = < 2498 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
2523 pinctrl-names 2499 pinctrl-names = "default";
2524 2500
2525 #address-cell 2501 #address-cells = <1>;
2526 #size-cells = 2502 #size-cells = <0>;
2527 2503
2528 status = "dis 2504 status = "disabled";
2529 }; 2505 };
2530 }; 2506 };
2531 2507
2532 tsens0: thermal-sensor@c27100 <<
2533 compatible = "qcom,x1 <<
2534 reg = <0 0x0c271000 0 <<
2535 <0 0x0c222000 0 <<
2536 <<
2537 interrupts-extended = <<
2538 <<
2539 interrupt-names = "up <<
2540 "cr <<
2541 <<
2542 #qcom,sensors = <16>; <<
2543 <<
2544 #thermal-sensor-cells <<
2545 }; <<
2546 <<
2547 tsens1: thermal-sensor@c27200 <<
2548 compatible = "qcom,x1 <<
2549 reg = <0 0x0c272000 0 <<
2550 <0 0x0c223000 0 <<
2551 <<
2552 interrupts-extended = <<
2553 <<
2554 interrupt-names = "up <<
2555 "cr <<
2556 <<
2557 #qcom,sensors = <16>; <<
2558 <<
2559 #thermal-sensor-cells <<
2560 }; <<
2561 <<
2562 tsens2: thermal-sensor@c27300 <<
2563 compatible = "qcom,x1 <<
2564 reg = <0 0x0c273000 0 <<
2565 <0 0x0c224000 0 <<
2566 <<
2567 interrupts-extended = <<
2568 <<
2569 interrupt-names = "up <<
2570 "cr <<
2571 <<
2572 #qcom,sensors = <16>; <<
2573 <<
2574 #thermal-sensor-cells <<
2575 }; <<
2576 <<
2577 tsens3: thermal-sensor@c27400 <<
2578 compatible = "qcom,x1 <<
2579 reg = <0 0x0c274000 0 <<
2580 <0 0x0c225000 0 <<
2581 <<
2582 interrupts-extended = <<
2583 <<
2584 interrupt-names = "up <<
2585 "cr <<
2586 <<
2587 #qcom,sensors = <16>; <<
2588 <<
2589 #thermal-sensor-cells <<
2590 }; <<
2591 <<
2592 usb_1_ss0_hsphy: phy@fd3000 { 2508 usb_1_ss0_hsphy: phy@fd3000 {
2593 compatible = "qcom,x1 2509 compatible = "qcom,x1e80100-snps-eusb2-phy",
2594 "qcom,sm 2510 "qcom,sm8550-snps-eusb2-phy";
2595 reg = <0 0x00fd3000 0 2511 reg = <0 0x00fd3000 0 0x154>;
2596 #phy-cells = <0>; 2512 #phy-cells = <0>;
2597 2513
2598 clocks = <&tcsr TCSR_ 2514 clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>;
2599 clock-names = "ref"; 2515 clock-names = "ref";
2600 2516
2601 resets = <&gcc GCC_QU 2517 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2602 2518
2603 status = "disabled"; 2519 status = "disabled";
2604 }; 2520 };
2605 2521
2606 usb_1_ss0_qmpphy: phy@fd5000 2522 usb_1_ss0_qmpphy: phy@fd5000 {
2607 compatible = "qcom,x1 2523 compatible = "qcom,x1e80100-qmp-usb3-dp-phy";
2608 reg = <0 0x00fd5000 0 2524 reg = <0 0x00fd5000 0 0x4000>;
2609 2525
2610 clocks = <&gcc GCC_US 2526 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2611 <&rpmhcc RPM 2527 <&rpmhcc RPMH_CXO_CLK>,
2612 <&gcc GCC_US 2528 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
2613 <&gcc GCC_US 2529 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2614 clock-names = "aux", 2530 clock-names = "aux",
2615 "ref", 2531 "ref",
2616 "com_au 2532 "com_aux",
2617 "usb3_p 2533 "usb3_pipe";
2618 2534
2619 power-domains = <&gcc 2535 power-domains = <&gcc GCC_USB_0_PHY_GDSC>;
2620 2536
2621 resets = <&gcc GCC_US 2537 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
2622 <&gcc GCC_US 2538 <&gcc GCC_USB4_0_DP0_PHY_PRIM_BCR>;
2623 reset-names = "phy", 2539 reset-names = "phy",
2624 "common 2540 "common";
2625 2541
2626 #clock-cells = <1>; 2542 #clock-cells = <1>;
2627 #phy-cells = <1>; 2543 #phy-cells = <1>;
2628 2544
2629 orientation-switch; <<
2630 <<
2631 status = "disabled"; 2545 status = "disabled";
2632 <<
2633 ports { <<
2634 #address-cell <<
2635 #size-cells = <<
2636 <<
2637 port@0 { <<
2638 reg = <<
2639 <<
2640 usb_1 <<
2641 }; <<
2642 }; <<
2643 <<
2644 port@1 { <<
2645 reg = <<
2646 <<
2647 usb_1 <<
2648 <<
2649 }; <<
2650 }; <<
2651 <<
2652 port@2 { <<
2653 reg = <<
2654 <<
2655 usb_1 <<
2656 <<
2657 }; <<
2658 }; <<
2659 }; <<
2660 }; 2546 };
2661 2547
2662 usb_1_ss1_hsphy: phy@fd9000 { 2548 usb_1_ss1_hsphy: phy@fd9000 {
2663 compatible = "qcom,x1 2549 compatible = "qcom,x1e80100-snps-eusb2-phy",
2664 "qcom,sm 2550 "qcom,sm8550-snps-eusb2-phy";
2665 reg = <0 0x00fd9000 0 2551 reg = <0 0x00fd9000 0 0x154>;
2666 #phy-cells = <0>; 2552 #phy-cells = <0>;
2667 2553
2668 clocks = <&tcsr TCSR_ 2554 clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>;
2669 clock-names = "ref"; 2555 clock-names = "ref";
2670 2556
2671 resets = <&gcc GCC_QU 2557 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
2672 2558
2673 status = "disabled"; 2559 status = "disabled";
2674 }; 2560 };
2675 2561
2676 usb_1_ss1_qmpphy: phy@fda000 2562 usb_1_ss1_qmpphy: phy@fda000 {
2677 compatible = "qcom,x1 2563 compatible = "qcom,x1e80100-qmp-usb3-dp-phy";
2678 reg = <0 0x00fda000 0 2564 reg = <0 0x00fda000 0 0x4000>;
2679 2565
2680 clocks = <&gcc GCC_US 2566 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
2681 <&rpmhcc RPM 2567 <&rpmhcc RPMH_CXO_CLK>,
2682 <&gcc GCC_US 2568 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
2683 <&gcc GCC_US 2569 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
2684 clock-names = "aux", 2570 clock-names = "aux",
2685 "ref", 2571 "ref",
2686 "com_au 2572 "com_aux",
2687 "usb3_p 2573 "usb3_pipe";
2688 2574
2689 power-domains = <&gcc 2575 power-domains = <&gcc GCC_USB_1_PHY_GDSC>;
2690 2576
2691 resets = <&gcc GCC_US 2577 resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
2692 <&gcc GCC_US 2578 <&gcc GCC_USB4_1_DP0_PHY_SEC_BCR>;
2693 reset-names = "phy", 2579 reset-names = "phy",
2694 "common 2580 "common";
2695 2581
2696 #clock-cells = <1>; 2582 #clock-cells = <1>;
2697 #phy-cells = <1>; 2583 #phy-cells = <1>;
2698 2584
2699 orientation-switch; <<
2700 <<
2701 status = "disabled"; 2585 status = "disabled";
2702 <<
2703 ports { <<
2704 #address-cell <<
2705 #size-cells = <<
2706 <<
2707 port@0 { <<
2708 reg = <<
2709 <<
2710 usb_1 <<
2711 }; <<
2712 }; <<
2713 <<
2714 port@1 { <<
2715 reg = <<
2716 <<
2717 usb_1 <<
2718 <<
2719 }; <<
2720 }; <<
2721 <<
2722 port@2 { <<
2723 reg = <<
2724 <<
2725 usb_1 <<
2726 <<
2727 }; <<
2728 }; <<
2729 }; <<
2730 }; 2586 };
2731 2587
2732 usb_1_ss2_hsphy: phy@fde000 { 2588 usb_1_ss2_hsphy: phy@fde000 {
2733 compatible = "qcom,x1 2589 compatible = "qcom,x1e80100-snps-eusb2-phy",
2734 "qcom,sm 2590 "qcom,sm8550-snps-eusb2-phy";
2735 reg = <0 0x00fde000 0 2591 reg = <0 0x00fde000 0 0x154>;
2736 #phy-cells = <0>; 2592 #phy-cells = <0>;
2737 2593
2738 clocks = <&tcsr TCSR_ 2594 clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>;
2739 clock-names = "ref"; 2595 clock-names = "ref";
2740 2596
2741 resets = <&gcc GCC_QU 2597 resets = <&gcc GCC_QUSB2PHY_TERT_BCR>;
2742 2598
2743 status = "disabled"; 2599 status = "disabled";
2744 }; 2600 };
2745 2601
2746 usb_1_ss2_qmpphy: phy@fdf000 2602 usb_1_ss2_qmpphy: phy@fdf000 {
2747 compatible = "qcom,x1 2603 compatible = "qcom,x1e80100-qmp-usb3-dp-phy";
2748 reg = <0 0x00fdf000 0 2604 reg = <0 0x00fdf000 0 0x4000>;
2749 2605
2750 clocks = <&gcc GCC_US 2606 clocks = <&gcc GCC_USB3_TERT_PHY_AUX_CLK>,
2751 <&rpmhcc RPM 2607 <&rpmhcc RPMH_CXO_CLK>,
2752 <&gcc GCC_US 2608 <&gcc GCC_USB3_TERT_PHY_COM_AUX_CLK>,
2753 <&gcc GCC_US 2609 <&gcc GCC_USB3_TERT_PHY_PIPE_CLK>;
2754 clock-names = "aux", 2610 clock-names = "aux",
2755 "ref", 2611 "ref",
2756 "com_au 2612 "com_aux",
2757 "usb3_p 2613 "usb3_pipe";
2758 2614
2759 power-domains = <&gcc 2615 power-domains = <&gcc GCC_USB_2_PHY_GDSC>;
2760 2616
2761 resets = <&gcc GCC_US 2617 resets = <&gcc GCC_USB3_PHY_TERT_BCR>,
2762 <&gcc GCC_US 2618 <&gcc GCC_USB4_2_DP0_PHY_TERT_BCR>;
2763 reset-names = "phy", 2619 reset-names = "phy",
2764 "common 2620 "common";
2765 2621
2766 #clock-cells = <1>; 2622 #clock-cells = <1>;
2767 #phy-cells = <1>; 2623 #phy-cells = <1>;
2768 2624
2769 orientation-switch; <<
2770 <<
2771 status = "disabled"; 2625 status = "disabled";
2772 <<
2773 ports { <<
2774 #address-cell <<
2775 #size-cells = <<
2776 <<
2777 port@0 { <<
2778 reg = <<
2779 <<
2780 usb_1 <<
2781 }; <<
2782 }; <<
2783 <<
2784 port@1 { <<
2785 reg = <<
2786 <<
2787 usb_1 <<
2788 <<
2789 }; <<
2790 }; <<
2791 <<
2792 port@2 { <<
2793 reg = <<
2794 <<
2795 usb_1 <<
2796 <<
2797 }; <<
2798 }; <<
2799 }; <<
2800 }; 2626 };
2801 2627
2802 cnoc_main: interconnect@15000 2628 cnoc_main: interconnect@1500000 {
2803 compatible = "qcom,x1 2629 compatible = "qcom,x1e80100-cnoc-main";
2804 reg = <0 0x01500000 0 !! 2630 reg = <0 0x1500000 0 0x14400>;
2805 2631
2806 qcom,bcm-voters = <&a 2632 qcom,bcm-voters = <&apps_bcm_voter>;
2807 2633
2808 #interconnect-cells = 2634 #interconnect-cells = <2>;
2809 }; 2635 };
2810 2636
2811 config_noc: interconnect@1600 2637 config_noc: interconnect@1600000 {
2812 compatible = "qcom,x1 2638 compatible = "qcom,x1e80100-cnoc-cfg";
2813 reg = <0 0x01600000 0 !! 2639 reg = <0 0x1600000 0 0x6600>;
2814 2640
2815 qcom,bcm-voters = <&a 2641 qcom,bcm-voters = <&apps_bcm_voter>;
2816 2642
2817 #interconnect-cells = 2643 #interconnect-cells = <2>;
2818 }; 2644 };
2819 2645
2820 system_noc: interconnect@1680 2646 system_noc: interconnect@1680000 {
2821 compatible = "qcom,x1 2647 compatible = "qcom,x1e80100-system-noc";
2822 reg = <0 0x01680000 0 !! 2648 reg = <0 0x1680000 0 0x1c080>;
2823 2649
2824 qcom,bcm-voters = <&a 2650 qcom,bcm-voters = <&apps_bcm_voter>;
2825 2651
2826 #interconnect-cells = 2652 #interconnect-cells = <2>;
2827 }; 2653 };
2828 2654
2829 pcie_south_anoc: interconnect 2655 pcie_south_anoc: interconnect@16c0000 {
2830 compatible = "qcom,x1 2656 compatible = "qcom,x1e80100-pcie-south-anoc";
2831 reg = <0 0x016c0000 0 !! 2657 reg = <0 0x16c0000 0 0xd080>;
2832 2658
2833 qcom,bcm-voters = <&a 2659 qcom,bcm-voters = <&apps_bcm_voter>;
2834 2660
2835 #interconnect-cells = 2661 #interconnect-cells = <2>;
2836 }; 2662 };
2837 2663
2838 pcie_center_anoc: interconnec 2664 pcie_center_anoc: interconnect@16d0000 {
2839 compatible = "qcom,x1 2665 compatible = "qcom,x1e80100-pcie-center-anoc";
2840 reg = <0 0x016d0000 0 !! 2666 reg = <0 0x16d0000 0 0x7000>;
2841 2667
2842 qcom,bcm-voters = <&a 2668 qcom,bcm-voters = <&apps_bcm_voter>;
2843 2669
2844 #interconnect-cells = 2670 #interconnect-cells = <2>;
2845 }; 2671 };
2846 2672
2847 aggre1_noc: interconnect@16e0 2673 aggre1_noc: interconnect@16e0000 {
2848 compatible = "qcom,x1 2674 compatible = "qcom,x1e80100-aggre1-noc";
2849 reg = <0 0x016e0000 0 !! 2675 reg = <0 0x16E0000 0 0x14400>;
2850 2676
2851 qcom,bcm-voters = <&a 2677 qcom,bcm-voters = <&apps_bcm_voter>;
2852 2678
2853 #interconnect-cells = 2679 #interconnect-cells = <2>;
2854 }; 2680 };
2855 2681
2856 aggre2_noc: interconnect@1700 2682 aggre2_noc: interconnect@1700000 {
2857 compatible = "qcom,x1 2683 compatible = "qcom,x1e80100-aggre2-noc";
2858 reg = <0 0x01700000 0 !! 2684 reg = <0 0x1700000 0 0x1c400>;
2859 2685
2860 qcom,bcm-voters = <&a 2686 qcom,bcm-voters = <&apps_bcm_voter>;
2861 2687
2862 #interconnect-cells = 2688 #interconnect-cells = <2>;
2863 }; 2689 };
2864 2690
2865 pcie_north_anoc: interconnect 2691 pcie_north_anoc: interconnect@1740000 {
2866 compatible = "qcom,x1 2692 compatible = "qcom,x1e80100-pcie-north-anoc";
2867 reg = <0 0x01740000 0 !! 2693 reg = <0 0x1740000 0 0x9080>;
2868 2694
2869 qcom,bcm-voters = <&a 2695 qcom,bcm-voters = <&apps_bcm_voter>;
2870 2696
2871 #interconnect-cells = 2697 #interconnect-cells = <2>;
2872 }; 2698 };
2873 2699
2874 usb_center_anoc: interconnect 2700 usb_center_anoc: interconnect@1750000 {
2875 compatible = "qcom,x1 2701 compatible = "qcom,x1e80100-usb-center-anoc";
2876 reg = <0 0x01750000 0 !! 2702 reg = <0 0x1750000 0 0x8800>;
2877 2703
2878 qcom,bcm-voters = <&a 2704 qcom,bcm-voters = <&apps_bcm_voter>;
2879 2705
2880 #interconnect-cells = 2706 #interconnect-cells = <2>;
2881 }; 2707 };
2882 2708
2883 usb_north_anoc: interconnect@ 2709 usb_north_anoc: interconnect@1760000 {
2884 compatible = "qcom,x1 2710 compatible = "qcom,x1e80100-usb-north-anoc";
2885 reg = <0 0x01760000 0 !! 2711 reg = <0 0x1760000 0 0x7080>;
2886 2712
2887 qcom,bcm-voters = <&a 2713 qcom,bcm-voters = <&apps_bcm_voter>;
2888 2714
2889 #interconnect-cells = 2715 #interconnect-cells = <2>;
2890 }; 2716 };
2891 2717
2892 usb_south_anoc: interconnect@ 2718 usb_south_anoc: interconnect@1770000 {
2893 compatible = "qcom,x1 2719 compatible = "qcom,x1e80100-usb-south-anoc";
2894 reg = <0 0x01770000 0 !! 2720 reg = <0 0x1770000 0 0xf080>;
2895 2721
2896 qcom,bcm-voters = <&a 2722 qcom,bcm-voters = <&apps_bcm_voter>;
2897 2723
2898 #interconnect-cells = 2724 #interconnect-cells = <2>;
2899 }; 2725 };
2900 2726
2901 mmss_noc: interconnect@178000 2727 mmss_noc: interconnect@1780000 {
2902 compatible = "qcom,x1 2728 compatible = "qcom,x1e80100-mmss-noc";
2903 reg = <0 0x01780000 0 !! 2729 reg = <0 0x1780000 0 0x5B800>;
2904 2730
2905 qcom,bcm-voters = <&a 2731 qcom,bcm-voters = <&apps_bcm_voter>;
2906 2732
2907 #interconnect-cells = 2733 #interconnect-cells = <2>;
2908 }; 2734 };
2909 2735
2910 pcie6a: pci@1bf8000 { 2736 pcie6a: pci@1bf8000 {
2911 device_type = "pci"; 2737 device_type = "pci";
2912 compatible = "qcom,pc 2738 compatible = "qcom,pcie-x1e80100";
2913 reg = <0 0x01bf8000 0 2739 reg = <0 0x01bf8000 0 0x3000>,
2914 <0 0x70000000 0 2740 <0 0x70000000 0 0xf20>,
2915 <0 0x70000f40 0 2741 <0 0x70000f40 0 0xa8>,
2916 <0 0x70001000 0 2742 <0 0x70001000 0 0x1000>,
2917 <0 0x70100000 0 2743 <0 0x70100000 0 0x100000>,
2918 <0 0x01bfb000 0 2744 <0 0x01bfb000 0 0x1000>;
2919 reg-names = "parf", 2745 reg-names = "parf",
2920 "dbi", 2746 "dbi",
2921 "elbi", 2747 "elbi",
2922 "atu", 2748 "atu",
2923 "config", 2749 "config",
2924 "mhi"; 2750 "mhi";
2925 #address-cells = <3>; 2751 #address-cells = <3>;
2926 #size-cells = <2>; 2752 #size-cells = <2>;
2927 ranges = <0x01000000 !! 2753 ranges = <0x01000000 0 0x00000000 0 0x70200000 0 0x100000>,
2928 <0x02000000 !! 2754 <0x02000000 0 0x70300000 0 0x70300000 0 0x3d00000>;
2929 bus-range = <0x00 0xf !! 2755 bus-range = <0 0xff>;
2930 2756
2931 dma-coherent; 2757 dma-coherent;
2932 2758
2933 linux,pci-domain = <6 2759 linux,pci-domain = <6>;
2934 num-lanes = <4>; !! 2760 num-lanes = <2>;
2935 2761
2936 interrupts = <GIC_SPI 2762 interrupts = <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,
2937 <GIC_SPI 2763 <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>,
2938 <GIC_SPI 2764 <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>,
2939 <GIC_SPI 2765 <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>,
2940 <GIC_SPI 2766 <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>,
2941 <GIC_SPI 2767 <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>,
2942 <GIC_SPI 2768 <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>,
2943 <GIC_SPI 2769 <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>;
2944 interrupt-names = "ms 2770 interrupt-names = "msi0",
2945 "ms 2771 "msi1",
2946 "ms 2772 "msi2",
2947 "ms 2773 "msi3",
2948 "ms 2774 "msi4",
2949 "ms 2775 "msi5",
2950 "ms 2776 "msi6",
2951 "ms 2777 "msi7";
2952 2778
2953 #interrupt-cells = <1 2779 #interrupt-cells = <1>;
2954 interrupt-map-mask = 2780 interrupt-map-mask = <0 0 0 0x7>;
2955 interrupt-map = <0 0 2781 interrupt-map = <0 0 0 1 &intc 0 0 0 843 IRQ_TYPE_LEVEL_HIGH>,
2956 <0 0 2782 <0 0 0 2 &intc 0 0 0 844 IRQ_TYPE_LEVEL_HIGH>,
2957 <0 0 2783 <0 0 0 3 &intc 0 0 0 845 IRQ_TYPE_LEVEL_HIGH>,
2958 <0 0 2784 <0 0 0 4 &intc 0 0 0 772 IRQ_TYPE_LEVEL_HIGH>;
2959 2785
2960 clocks = <&gcc GCC_PC 2786 clocks = <&gcc GCC_PCIE_6A_AUX_CLK>,
2961 <&gcc GCC_PC 2787 <&gcc GCC_PCIE_6A_CFG_AHB_CLK>,
2962 <&gcc GCC_PC 2788 <&gcc GCC_PCIE_6A_MSTR_AXI_CLK>,
2963 <&gcc GCC_PC 2789 <&gcc GCC_PCIE_6A_SLV_AXI_CLK>,
2964 <&gcc GCC_PC 2790 <&gcc GCC_PCIE_6A_SLV_Q2A_AXI_CLK>,
2965 <&gcc GCC_CF 2791 <&gcc GCC_CFG_NOC_PCIE_ANOC_SOUTH_AHB_CLK>,
2966 <&gcc GCC_CN 2792 <&gcc GCC_CNOC_PCIE_SOUTH_SF_AXI_CLK>;
2967 clock-names = "aux", 2793 clock-names = "aux",
2968 "cfg", 2794 "cfg",
2969 "bus_ma 2795 "bus_master",
2970 "bus_sl 2796 "bus_slave",
2971 "slave_ 2797 "slave_q2a",
2972 "noc_ag 2798 "noc_aggr",
2973 "cnoc_s 2799 "cnoc_sf_axi";
2974 2800
2975 assigned-clocks = <&g 2801 assigned-clocks = <&gcc GCC_PCIE_6A_AUX_CLK>;
2976 assigned-clock-rates 2802 assigned-clock-rates = <19200000>;
2977 2803
2978 interconnects = <&pci 2804 interconnects = <&pcie_south_anoc MASTER_PCIE_6A QCOM_ICC_TAG_ALWAYS
2979 &mc_ 2805 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
2980 <&gem 2806 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2981 &cno 2807 &cnoc_main SLAVE_PCIE_6A QCOM_ICC_TAG_ALWAYS>;
2982 interconnect-names = 2808 interconnect-names = "pcie-mem",
2983 2809 "cpu-pcie";
2984 2810
2985 resets = <&gcc GCC_PC 2811 resets = <&gcc GCC_PCIE_6A_BCR>,
2986 <&gcc GCC_PC 2812 <&gcc GCC_PCIE_6A_LINK_DOWN_BCR>;
2987 reset-names = "pci", 2813 reset-names = "pci",
2988 "link_d 2814 "link_down";
2989 2815
2990 power-domains = <&gcc 2816 power-domains = <&gcc GCC_PCIE_6A_GDSC>;
2991 required-opps = <&rpm 2817 required-opps = <&rpmhpd_opp_nom>;
2992 2818
2993 phys = <&pcie6a_phy>; 2819 phys = <&pcie6a_phy>;
2994 phy-names = "pciephy" 2820 phy-names = "pciephy";
2995 2821
2996 status = "disabled"; 2822 status = "disabled";
2997 }; 2823 };
2998 2824
2999 pcie6a_phy: phy@1bfc000 { 2825 pcie6a_phy: phy@1bfc000 {
3000 compatible = "qcom,x1 !! 2826 compatible = "qcom,x1e80100-qmp-gen4x2-pcie-phy";
3001 reg = <0 0x01bfc000 0 !! 2827 reg = <0 0x01bfc000 0 0x2000>;
3002 <0 0x01bfe000 0 <<
3003 2828
3004 clocks = <&gcc GCC_PC 2829 clocks = <&gcc GCC_PCIE_6A_PHY_AUX_CLK>,
3005 <&gcc GCC_PC 2830 <&gcc GCC_PCIE_6A_CFG_AHB_CLK>,
3006 <&tcsr TCSR_ !! 2831 <&rpmhcc RPMH_CXO_CLK>,
3007 <&gcc GCC_PC 2832 <&gcc GCC_PCIE_6A_PHY_RCHNG_CLK>,
3008 <&gcc GCC_PC !! 2833 <&gcc GCC_PCIE_6A_PIPE_CLK>;
3009 <&gcc GCC_PC <<
3010 clock-names = "aux", 2834 clock-names = "aux",
3011 "cfg_ah 2835 "cfg_ahb",
3012 "ref", 2836 "ref",
3013 "rchng" 2837 "rchng",
3014 "pipe", !! 2838 "pipe";
3015 "pipedi <<
3016 2839
3017 resets = <&gcc GCC_PC 2840 resets = <&gcc GCC_PCIE_6A_PHY_BCR>,
3018 <&gcc GCC_PC 2841 <&gcc GCC_PCIE_6A_NOCSR_COM_PHY_BCR>;
3019 reset-names = "phy", 2842 reset-names = "phy",
3020 "phy_no 2843 "phy_nocsr";
3021 2844
3022 assigned-clocks = <&g 2845 assigned-clocks = <&gcc GCC_PCIE_6A_PHY_RCHNG_CLK>;
3023 assigned-clock-rates 2846 assigned-clock-rates = <100000000>;
3024 2847
3025 power-domains = <&gcc 2848 power-domains = <&gcc GCC_PCIE_6_PHY_GDSC>;
3026 2849
3027 qcom,4ln-config-sel = <<
3028 <<
3029 #clock-cells = <0>; 2850 #clock-cells = <0>;
3030 clock-output-names = 2851 clock-output-names = "pcie6a_pipe_clk";
3031 2852
3032 #phy-cells = <0>; 2853 #phy-cells = <0>;
3033 2854
3034 status = "disabled"; 2855 status = "disabled";
3035 }; 2856 };
3036 2857
3037 pcie5: pci@1c00000 { <<
3038 device_type = "pci"; <<
3039 compatible = "qcom,pc <<
3040 reg = <0 0x01c00000 0 <<
3041 <0 0x7e000000 0 <<
3042 <0 0x7e000f40 0 <<
3043 <0 0x7e001000 0 <<
3044 <0 0x7e100000 0 <<
3045 <0 0x01c03000 0 <<
3046 reg-names = "parf", <<
3047 "dbi", <<
3048 "elbi", <<
3049 "atu", <<
3050 "config", <<
3051 "mhi"; <<
3052 #address-cells = <3>; <<
3053 #size-cells = <2>; <<
3054 ranges = <0x01000000 <<
3055 <0x02000000 <<
3056 bus-range = <0x00 0xf <<
3057 <<
3058 dma-coherent; <<
3059 <<
3060 linux,pci-domain = <5 <<
3061 num-lanes = <2>; <<
3062 <<
3063 interrupts = <GIC_SPI <<
3064 <GIC_SPI <<
3065 <GIC_SPI <<
3066 <GIC_SPI <<
3067 <GIC_SPI <<
3068 <GIC_SPI <<
3069 <GIC_SPI <<
3070 <GIC_SPI <<
3071 interrupt-names = "ms <<
3072 "ms <<
3073 "ms <<
3074 "ms <<
3075 "ms <<
3076 "ms <<
3077 "ms <<
3078 "ms <<
3079 <<
3080 #interrupt-cells = <1 <<
3081 interrupt-map-mask = <<
3082 interrupt-map = <0 0 <<
3083 <0 0 <<
3084 <0 0 <<
3085 <0 0 <<
3086 <<
3087 clocks = <&gcc GCC_PC <<
3088 <&gcc GCC_PC <<
3089 <&gcc GCC_PC <<
3090 <&gcc GCC_PC <<
3091 <&gcc GCC_PC <<
3092 <&gcc GCC_CF <<
3093 <&gcc GCC_CN <<
3094 clock-names = "aux", <<
3095 "cfg", <<
3096 "bus_ma <<
3097 "bus_sl <<
3098 "slave_ <<
3099 "noc_ag <<
3100 "cnoc_s <<
3101 <<
3102 assigned-clocks = <&g <<
3103 assigned-clock-rates <<
3104 <<
3105 interconnects = <&pci <<
3106 &mc_ <<
3107 <&gem <<
3108 &cno <<
3109 interconnect-names = <<
3110 <<
3111 <<
3112 resets = <&gcc GCC_PC <<
3113 <&gcc GCC_PC <<
3114 reset-names = "pci", <<
3115 "link_d <<
3116 <<
3117 power-domains = <&gcc <<
3118 required-opps = <&rpm <<
3119 <<
3120 phys = <&pcie5_phy>; <<
3121 phy-names = "pciephy" <<
3122 <<
3123 status = "disabled"; <<
3124 }; <<
3125 <<
3126 pcie5_phy: phy@1c06000 { <<
3127 compatible = "qcom,x1 <<
3128 reg = <0 0x01c06000 0 <<
3129 <<
3130 clocks = <&gcc GCC_PC <<
3131 <&gcc GCC_PC <<
3132 <&tcsr TCSR_ <<
3133 <&gcc GCC_PC <<
3134 <&gcc GCC_PC <<
3135 <&gcc GCC_PC <<
3136 clock-names = "aux", <<
3137 "cfg_ah <<
3138 "ref", <<
3139 "rchng" <<
3140 "pipe", <<
3141 "pipedi <<
3142 <<
3143 resets = <&gcc GCC_PC <<
3144 reset-names = "phy"; <<
3145 <<
3146 assigned-clocks = <&g <<
3147 assigned-clock-rates <<
3148 <<
3149 power-domains = <&gcc <<
3150 <<
3151 #clock-cells = <0>; <<
3152 clock-output-names = <<
3153 <<
3154 #phy-cells = <0>; <<
3155 <<
3156 status = "disabled"; <<
3157 }; <<
3158 <<
3159 pcie4: pci@1c08000 { 2858 pcie4: pci@1c08000 {
3160 device_type = "pci"; 2859 device_type = "pci";
3161 compatible = "qcom,pc 2860 compatible = "qcom,pcie-x1e80100";
3162 reg = <0 0x01c08000 0 2861 reg = <0 0x01c08000 0 0x3000>,
3163 <0 0x7c000000 0 2862 <0 0x7c000000 0 0xf1d>,
3164 <0 0x7c000f40 0 2863 <0 0x7c000f40 0 0xa8>,
3165 <0 0x7c001000 0 2864 <0 0x7c001000 0 0x1000>,
3166 <0 0x7c100000 0 2865 <0 0x7c100000 0 0x100000>,
3167 <0 0x01c0b000 0 2866 <0 0x01c0b000 0 0x1000>;
3168 reg-names = "parf", 2867 reg-names = "parf",
3169 "dbi", 2868 "dbi",
3170 "elbi", 2869 "elbi",
3171 "atu", 2870 "atu",
3172 "config", 2871 "config",
3173 "mhi"; 2872 "mhi";
3174 #address-cells = <3>; 2873 #address-cells = <3>;
3175 #size-cells = <2>; 2874 #size-cells = <2>;
3176 ranges = <0x01000000 !! 2875 ranges = <0x01000000 0 0x00000000 0 0x7c200000 0 0x100000>,
3177 <0x02000000 !! 2876 <0x02000000 0 0x7c300000 0 0x7c300000 0 0x3d00000>;
3178 bus-range = <0x00 0xf 2877 bus-range = <0x00 0xff>;
3179 2878
3180 dma-coherent; 2879 dma-coherent;
3181 2880
3182 linux,pci-domain = <4 2881 linux,pci-domain = <4>;
3183 num-lanes = <2>; 2882 num-lanes = <2>;
3184 2883
3185 interrupts = <GIC_SPI 2884 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
3186 <GIC_SPI 2885 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
3187 <GIC_SPI 2886 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
3188 <GIC_SPI 2887 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
3189 <GIC_SPI 2888 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
3190 <GIC_SPI 2889 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
3191 <GIC_SPI 2890 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
3192 <GIC_SPI 2891 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
3193 interrupt-names = "ms 2892 interrupt-names = "msi0",
3194 "ms 2893 "msi1",
3195 "ms 2894 "msi2",
3196 "ms 2895 "msi3",
3197 "ms 2896 "msi4",
3198 "ms 2897 "msi5",
3199 "ms 2898 "msi6",
3200 "ms 2899 "msi7";
3201 2900
3202 #interrupt-cells = <1 2901 #interrupt-cells = <1>;
3203 interrupt-map-mask = 2902 interrupt-map-mask = <0 0 0 0x7>;
3204 interrupt-map = <0 0 2903 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>,
3205 <0 0 2904 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>,
3206 <0 0 2905 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>,
3207 <0 0 2906 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>;
3208 2907
3209 clocks = <&gcc GCC_PC 2908 clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
3210 <&gcc GCC_PC 2909 <&gcc GCC_PCIE_4_CFG_AHB_CLK>,
3211 <&gcc GCC_PC 2910 <&gcc GCC_PCIE_4_MSTR_AXI_CLK>,
3212 <&gcc GCC_PC 2911 <&gcc GCC_PCIE_4_SLV_AXI_CLK>,
3213 <&gcc GCC_PC 2912 <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>,
3214 <&gcc GCC_CF 2913 <&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>,
3215 <&gcc GCC_CN 2914 <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>;
3216 clock-names = "aux", 2915 clock-names = "aux",
3217 "cfg", 2916 "cfg",
3218 "bus_ma 2917 "bus_master",
3219 "bus_sl 2918 "bus_slave",
3220 "slave_ 2919 "slave_q2a",
3221 "noc_ag 2920 "noc_aggr",
3222 "cnoc_s 2921 "cnoc_sf_axi";
3223 2922
3224 assigned-clocks = <&g 2923 assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>;
3225 assigned-clock-rates 2924 assigned-clock-rates = <19200000>;
3226 2925
3227 interconnects = <&pci !! 2926 interconnects = <&pcie_south_anoc MASTER_PCIE_4 QCOM_ICC_TAG_ALWAYS
3228 &mc_ 2927 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
3229 <&gem 2928 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
3230 &cno 2929 &cnoc_main SLAVE_PCIE_4 QCOM_ICC_TAG_ALWAYS>;
3231 interconnect-names = 2930 interconnect-names = "pcie-mem",
3232 2931 "cpu-pcie";
3233 2932
3234 resets = <&gcc GCC_PC 2933 resets = <&gcc GCC_PCIE_4_BCR>,
3235 <&gcc GCC_PC 2934 <&gcc GCC_PCIE_4_LINK_DOWN_BCR>;
3236 reset-names = "pci", 2935 reset-names = "pci",
3237 "link_d 2936 "link_down";
3238 2937
3239 power-domains = <&gcc 2938 power-domains = <&gcc GCC_PCIE_4_GDSC>;
3240 required-opps = <&rpm 2939 required-opps = <&rpmhpd_opp_nom>;
3241 2940
3242 phys = <&pcie4_phy>; 2941 phys = <&pcie4_phy>;
3243 phy-names = "pciephy" 2942 phy-names = "pciephy";
3244 2943
3245 status = "disabled"; 2944 status = "disabled";
3246 <<
3247 pcie4_port0: pcie@0 { <<
3248 device_type = <<
3249 reg = <0x0 0x <<
3250 bus-range = < <<
3251 <<
3252 #address-cell <<
3253 #size-cells = <<
3254 ranges; <<
3255 }; <<
3256 }; 2945 };
3257 2946
3258 pcie4_phy: phy@1c0e000 { 2947 pcie4_phy: phy@1c0e000 {
3259 compatible = "qcom,x1 2948 compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy";
3260 reg = <0 0x01c0e000 0 2949 reg = <0 0x01c0e000 0 0x2000>;
3261 2950
3262 clocks = <&gcc GCC_PC 2951 clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
3263 <&gcc GCC_PC 2952 <&gcc GCC_PCIE_4_CFG_AHB_CLK>,
3264 <&tcsr TCSR_ !! 2953 <&rpmhcc RPMH_CXO_CLK>,
3265 <&gcc GCC_PC 2954 <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>,
3266 <&gcc GCC_PC !! 2955 <&gcc GCC_PCIE_4_PIPE_CLK>;
3267 <&gcc GCC_PC <<
3268 clock-names = "aux", 2956 clock-names = "aux",
3269 "cfg_ah 2957 "cfg_ahb",
3270 "ref", 2958 "ref",
3271 "rchng" 2959 "rchng",
3272 "pipe", !! 2960 "pipe";
3273 "pipedi <<
3274 2961
3275 resets = <&gcc GCC_PC 2962 resets = <&gcc GCC_PCIE_4_PHY_BCR>;
3276 reset-names = "phy"; 2963 reset-names = "phy";
3277 2964
3278 assigned-clocks = <&g 2965 assigned-clocks = <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>;
3279 assigned-clock-rates 2966 assigned-clock-rates = <100000000>;
3280 2967
3281 power-domains = <&gcc 2968 power-domains = <&gcc GCC_PCIE_4_PHY_GDSC>;
3282 2969
3283 #clock-cells = <0>; 2970 #clock-cells = <0>;
3284 clock-output-names = 2971 clock-output-names = "pcie4_pipe_clk";
3285 2972
3286 #phy-cells = <0>; 2973 #phy-cells = <0>;
3287 2974
3288 status = "disabled"; 2975 status = "disabled";
3289 }; 2976 };
3290 2977
3291 tcsr_mutex: hwlock@1f40000 { 2978 tcsr_mutex: hwlock@1f40000 {
3292 compatible = "qcom,tc 2979 compatible = "qcom,tcsr-mutex";
3293 reg = <0 0x01f40000 0 2980 reg = <0 0x01f40000 0 0x20000>;
3294 #hwlock-cells = <1>; 2981 #hwlock-cells = <1>;
3295 }; 2982 };
3296 2983
3297 tcsr: clock-controller@1fc000 2984 tcsr: clock-controller@1fc0000 {
3298 compatible = "qcom,x1 2985 compatible = "qcom,x1e80100-tcsr", "syscon";
3299 reg = <0 0x01fc0000 0 2986 reg = <0 0x01fc0000 0 0x30000>;
3300 clocks = <&rpmhcc RPM 2987 clocks = <&rpmhcc RPMH_CXO_CLK>;
3301 #clock-cells = <1>; 2988 #clock-cells = <1>;
3302 #reset-cells = <1>; 2989 #reset-cells = <1>;
3303 }; 2990 };
3304 2991
3305 gpu: gpu@3d00000 { <<
3306 compatible = "qcom,ad <<
3307 reg = <0x0 0x03d00000 <<
3308 <0x0 0x03d9e000 <<
3309 <0x0 0x03d61000 <<
3310 <<
3311 reg-names = "kgsl_3d0 <<
3312 "cx_mem", <<
3313 "cx_dbgc" <<
3314 <<
3315 interrupts = <GIC_SPI <<
3316 <<
3317 iommus = <&adreno_smm <<
3318 <&adreno_smm <<
3319 <<
3320 operating-points-v2 = <<
3321 <<
3322 qcom,gmu = <&gmu>; <<
3323 #cooling-cells = <2>; <<
3324 <<
3325 interconnects = <&gem <<
3326 interconnect-names = <<
3327 <<
3328 status = "disabled"; <<
3329 <<
3330 zap-shader { <<
3331 memory-region <<
3332 }; <<
3333 <<
3334 gpu_opp_table: opp-ta <<
3335 compatible = <<
3336 <<
3337 opp-110000000 <<
3338 opp-h <<
3339 opp-l <<
3340 opp-p <<
3341 }; <<
3342 <<
3343 opp-100000000 <<
3344 opp-h <<
3345 opp-l <<
3346 opp-p <<
3347 }; <<
3348 <<
3349 opp-925000000 <<
3350 opp-h <<
3351 opp-l <<
3352 opp-p <<
3353 }; <<
3354 <<
3355 opp-800000000 <<
3356 opp-h <<
3357 opp-l <<
3358 opp-p <<
3359 }; <<
3360 <<
3361 opp-744000000 <<
3362 opp-h <<
3363 opp-l <<
3364 opp-p <<
3365 }; <<
3366 <<
3367 opp-687000000 <<
3368 opp-h <<
3369 opp-l <<
3370 opp-p <<
3371 }; <<
3372 <<
3373 opp-550000000 <<
3374 opp-h <<
3375 opp-l <<
3376 opp-p <<
3377 }; <<
3378 <<
3379 opp-390000000 <<
3380 opp-h <<
3381 opp-l <<
3382 opp-p <<
3383 }; <<
3384 <<
3385 opp-300000000 <<
3386 opp-h <<
3387 opp-l <<
3388 opp-p <<
3389 }; <<
3390 }; <<
3391 }; <<
3392 <<
3393 gmu: gmu@3d6a000 { <<
3394 compatible = "qcom,ad <<
3395 reg = <0x0 0x03d6a000 <<
3396 <0x0 0x03d50000 <<
3397 <0x0 0x0b280000 <<
3398 reg-names = "gmu", " <<
3399 <<
3400 interrupts = <GIC_SPI <<
3401 <GIC_SPI <<
3402 interrupt-names = "hf <<
3403 <<
3404 clocks = <&gpucc GPU_ <<
3405 <&gpucc GPU_ <<
3406 <&gpucc GPU_ <<
3407 <&gcc GCC_DD <<
3408 <&gcc GCC_GP <<
3409 <&gpucc GPU_ <<
3410 <&gpucc GPU_ <<
3411 clock-names = "ahb", <<
3412 "gmu", <<
3413 "cxo", <<
3414 "axi", <<
3415 "memnoc <<
3416 "hub", <<
3417 "demet" <<
3418 <<
3419 power-domains = <&gpu <<
3420 <&gpu <<
3421 power-domain-names = <<
3422 <<
3423 <<
3424 iommus = <&adreno_smm <<
3425 <<
3426 qcom,qmp = <&aoss_qmp <<
3427 <<
3428 operating-points-v2 = <<
3429 <<
3430 gmu_opp_table: opp-ta <<
3431 compatible = <<
3432 <<
3433 opp-550000000 <<
3434 opp-h <<
3435 opp-l <<
3436 }; <<
3437 <<
3438 opp-220000000 <<
3439 opp-h <<
3440 opp-l <<
3441 }; <<
3442 }; <<
3443 }; <<
3444 <<
3445 gpucc: clock-controller@3d900 <<
3446 compatible = "qcom,x1 <<
3447 reg = <0 0x03d90000 0 <<
3448 clocks = <&bi_tcxo_di <<
3449 <&gcc GCC_GP <<
3450 <&gcc GCC_GP <<
3451 #clock-cells = <1>; <<
3452 #reset-cells = <1>; <<
3453 #power-domain-cells = <<
3454 }; <<
3455 <<
3456 adreno_smmu: iommu@3da0000 { <<
3457 compatible = "qcom,x1 <<
3458 "qcom,sm <<
3459 reg = <0x0 0x03da0000 <<
3460 #iommu-cells = <2>; <<
3461 #global-interrupts = <<
3462 interrupts = <GIC_SPI <<
3463 <GIC_SPI <<
3464 <GIC_SPI <<
3465 <GIC_SPI <<
3466 <GIC_SPI <<
3467 <GIC_SPI <<
3468 <GIC_SPI <<
3469 <GIC_SPI <<
3470 <GIC_SPI <<
3471 <GIC_SPI <<
3472 <GIC_SPI <<
3473 <GIC_SPI <<
3474 <GIC_SPI <<
3475 <GIC_SPI <<
3476 <GIC_SPI <<
3477 <GIC_SPI <<
3478 <GIC_SPI <<
3479 <GIC_SPI <<
3480 <GIC_SPI <<
3481 <GIC_SPI <<
3482 <GIC_SPI <<
3483 <GIC_SPI <<
3484 <GIC_SPI <<
3485 <GIC_SPI <<
3486 <GIC_SPI <<
3487 <GIC_SPI <<
3488 clocks = <&gpucc GPU_ <<
3489 <&gcc GCC_GP <<
3490 <&gcc GCC_GP <<
3491 <&gpucc GPU_ <<
3492 clock-names = "hlos", <<
3493 "bus", <<
3494 "iface" <<
3495 "ahb"; <<
3496 power-domains = <&gpu <<
3497 dma-coherent; <<
3498 }; <<
3499 <<
3500 gem_noc: interconnect@2640000 2992 gem_noc: interconnect@26400000 {
3501 compatible = "qcom,x1 2993 compatible = "qcom,x1e80100-gem-noc";
3502 reg = <0 0x26400000 0 2994 reg = <0 0x26400000 0 0x311200>;
3503 2995
3504 qcom,bcm-voters = <&a 2996 qcom,bcm-voters = <&apps_bcm_voter>;
3505 2997
3506 #interconnect-cells = 2998 #interconnect-cells = <2>;
3507 }; 2999 };
3508 3000
3509 nsp_noc: interconnect@320c000 3001 nsp_noc: interconnect@320c0000 {
3510 compatible = "qcom,x1 3002 compatible = "qcom,x1e80100-nsp-noc";
3511 reg = <0 0x320C0000 0 !! 3003 reg = <0 0x320C0000 0 0xE080>;
3512 3004
3513 qcom,bcm-voters = <&a 3005 qcom,bcm-voters = <&apps_bcm_voter>;
3514 3006
3515 #interconnect-cells = 3007 #interconnect-cells = <2>;
3516 }; 3008 };
3517 3009
3518 lpass_wsa2macro: codec@6aa000 3010 lpass_wsa2macro: codec@6aa0000 {
3519 compatible = "qcom,x1 3011 compatible = "qcom,x1e80100-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro";
3520 reg = <0 0x06aa0000 0 3012 reg = <0 0x06aa0000 0 0x1000>;
3521 clocks = <&q6prmcc LP 3013 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3522 <&q6prmcc LP 3014 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3523 <&q6prmcc LP 3015 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3524 <&lpass_vama 3016 <&lpass_vamacro>;
3525 clock-names = "mclk", 3017 clock-names = "mclk",
3526 "macro" 3018 "macro",
3527 "dcodec 3019 "dcodec",
3528 "fsgen" 3020 "fsgen";
3529 3021
3530 #clock-cells = <0>; 3022 #clock-cells = <0>;
3531 clock-output-names = 3023 clock-output-names = "wsa2-mclk";
3532 #sound-dai-cells = <1 3024 #sound-dai-cells = <1>;
3533 sound-name-prefix = " 3025 sound-name-prefix = "WSA2";
3534 }; 3026 };
3535 3027
3536 swr3: soundwire@6ab0000 { 3028 swr3: soundwire@6ab0000 {
3537 compatible = "qcom,so 3029 compatible = "qcom,soundwire-v2.0.0";
3538 reg = <0 0x06ab0000 0 3030 reg = <0 0x06ab0000 0 0x10000>;
3539 clocks = <&lpass_wsa2 3031 clocks = <&lpass_wsa2macro>;
3540 clock-names = "iface" 3032 clock-names = "iface";
3541 interrupts = <GIC_SPI 3033 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
3542 label = "WSA2"; 3034 label = "WSA2";
3543 3035
3544 pinctrl-0 = <&wsa2_sw 3036 pinctrl-0 = <&wsa2_swr_active>;
3545 pinctrl-names = "defa 3037 pinctrl-names = "default";
3546 resets = <&lpass_audi <<
3547 reset-names = "swr_au <<
3548 3038
3549 qcom,din-ports = <4>; 3039 qcom,din-ports = <4>;
3550 qcom,dout-ports = <9> 3040 qcom,dout-ports = <9>;
3551 3041
3552 qcom,ports-sinterval 3042 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0x0f 0x0f 0xff 0x31f>;
3553 qcom,ports-offset1 = 3043 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
3554 qcom,ports-offset2 = 3044 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3555 qcom,ports-hstart = 3045 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
3556 qcom,ports-hstop = 3046 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
3557 qcom,ports-word-lengt 3047 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>;
3558 qcom,ports-block-pack 3048 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>;
3559 qcom,ports-block-grou 3049 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3560 qcom,ports-lane-contr 3050 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3561 3051
3562 #address-cells = <2>; 3052 #address-cells = <2>;
3563 #size-cells = <0>; 3053 #size-cells = <0>;
3564 #sound-dai-cells = <1 3054 #sound-dai-cells = <1>;
3565 status = "disabled"; 3055 status = "disabled";
3566 }; 3056 };
3567 3057
3568 lpass_rxmacro: codec@6ac0000 3058 lpass_rxmacro: codec@6ac0000 {
3569 compatible = "qcom,x1 3059 compatible = "qcom,x1e80100-lpass-rx-macro", "qcom,sm8550-lpass-rx-macro";
3570 reg = <0 0x06ac0000 0 3060 reg = <0 0x06ac0000 0 0x1000>;
3571 clocks = <&q6prmcc LP 3061 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3572 <&q6prmcc LP 3062 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3573 <&q6prmcc LP 3063 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3574 <&lpass_vama 3064 <&lpass_vamacro>;
3575 clock-names = "mclk", 3065 clock-names = "mclk",
3576 "macro" 3066 "macro",
3577 "dcodec 3067 "dcodec",
3578 "fsgen" 3068 "fsgen";
3579 3069
3580 #clock-cells = <0>; 3070 #clock-cells = <0>;
3581 clock-output-names = 3071 clock-output-names = "mclk";
3582 #sound-dai-cells = <1 3072 #sound-dai-cells = <1>;
3583 }; 3073 };
3584 3074
3585 swr1: soundwire@6ad0000 { 3075 swr1: soundwire@6ad0000 {
3586 compatible = "qcom,so 3076 compatible = "qcom,soundwire-v2.0.0";
3587 reg = <0 0x06ad0000 0 3077 reg = <0 0x06ad0000 0 0x10000>;
3588 clocks = <&lpass_rxma 3078 clocks = <&lpass_rxmacro>;
3589 clock-names = "iface" 3079 clock-names = "iface";
3590 interrupts = <GIC_SPI 3080 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
3591 label = "RX"; 3081 label = "RX";
3592 3082
3593 pinctrl-0 = <&rx_swr_ 3083 pinctrl-0 = <&rx_swr_active>;
3594 pinctrl-names = "defa 3084 pinctrl-names = "default";
3595 3085
3596 resets = <&lpass_audi <<
3597 reset-names = "swr_au <<
3598 qcom,din-ports = <1>; 3086 qcom,din-ports = <1>;
3599 qcom,dout-ports = <11 3087 qcom,dout-ports = <11>;
3600 3088
3601 qcom,ports-sinterval 3089 qcom,ports-sinterval = /bits/ 16 <0x03 0x1f 0x1f 0x07 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3602 qcom,ports-offset1 = 3090 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3603 qcom,ports-offset2 = 3091 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3604 qcom,ports-hstart = 3092 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3605 qcom,ports-hstop = 3093 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3606 qcom,ports-word-lengt 3094 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3607 qcom,ports-block-pack 3095 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3608 qcom,ports-block-grou 3096 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3609 qcom,ports-lane-contr 3097 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3610 3098
3611 #address-cells = <2>; 3099 #address-cells = <2>;
3612 #size-cells = <0>; 3100 #size-cells = <0>;
3613 #sound-dai-cells = <1 3101 #sound-dai-cells = <1>;
3614 status = "disabled"; 3102 status = "disabled";
3615 }; 3103 };
3616 3104
3617 lpass_txmacro: codec@6ae0000 3105 lpass_txmacro: codec@6ae0000 {
3618 compatible = "qcom,x1 3106 compatible = "qcom,x1e80100-lpass-tx-macro", "qcom,sm8550-lpass-tx-macro";
3619 reg = <0 0x06ae0000 0 3107 reg = <0 0x06ae0000 0 0x1000>;
3620 clocks = <&q6prmcc LP 3108 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3621 <&q6prmcc LP 3109 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3622 <&q6prmcc LP 3110 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3623 <&lpass_vama 3111 <&lpass_vamacro>;
3624 clock-names = "mclk", 3112 clock-names = "mclk",
3625 "macro" 3113 "macro",
3626 "dcodec 3114 "dcodec",
3627 "fsgen" 3115 "fsgen";
3628 3116
3629 #clock-cells = <0>; 3117 #clock-cells = <0>;
3630 clock-output-names = 3118 clock-output-names = "mclk";
3631 #sound-dai-cells = <1 3119 #sound-dai-cells = <1>;
3632 }; 3120 };
3633 3121
3634 lpass_wsamacro: codec@6b00000 3122 lpass_wsamacro: codec@6b00000 {
3635 compatible = "qcom,x1 3123 compatible = "qcom,x1e80100-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro";
3636 reg = <0 0x06b00000 0 3124 reg = <0 0x06b00000 0 0x1000>;
3637 clocks = <&q6prmcc LP 3125 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3638 <&q6prmcc LP 3126 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3639 <&q6prmcc LP 3127 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3640 <&lpass_vama 3128 <&lpass_vamacro>;
3641 clock-names = "mclk", 3129 clock-names = "mclk",
3642 "macro" 3130 "macro",
3643 "dcodec 3131 "dcodec",
3644 "fsgen" 3132 "fsgen";
3645 3133
3646 #clock-cells = <0>; 3134 #clock-cells = <0>;
3647 clock-output-names = 3135 clock-output-names = "mclk";
3648 #sound-dai-cells = <1 3136 #sound-dai-cells = <1>;
3649 sound-name-prefix = " 3137 sound-name-prefix = "WSA";
3650 }; 3138 };
3651 3139
3652 swr0: soundwire@6b10000 { 3140 swr0: soundwire@6b10000 {
3653 compatible = "qcom,so 3141 compatible = "qcom,soundwire-v2.0.0";
3654 reg = <0 0x06b10000 0 3142 reg = <0 0x06b10000 0 0x10000>;
3655 clocks = <&lpass_wsam 3143 clocks = <&lpass_wsamacro>;
3656 clock-names = "iface" 3144 clock-names = "iface";
3657 interrupts = <GIC_SPI 3145 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
3658 label = "WSA"; 3146 label = "WSA";
3659 3147
3660 pinctrl-0 = <&wsa_swr 3148 pinctrl-0 = <&wsa_swr_active>;
3661 pinctrl-names = "defa 3149 pinctrl-names = "default";
3662 resets = <&lpass_audi <<
3663 reset-names = "swr_au <<
3664 3150
3665 qcom,din-ports = <4>; 3151 qcom,din-ports = <4>;
3666 qcom,dout-ports = <9> 3152 qcom,dout-ports = <9>;
3667 3153
3668 qcom,ports-sinterval 3154 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0x0f 0x0f 0xff 0x31f>;
3669 qcom,ports-offset1 = 3155 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
3670 qcom,ports-offset2 = 3156 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3671 qcom,ports-hstart = 3157 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
3672 qcom,ports-hstop = 3158 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
3673 qcom,ports-word-lengt 3159 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>;
3674 qcom,ports-block-pack 3160 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>;
3675 qcom,ports-block-grou 3161 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3676 qcom,ports-lane-contr 3162 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3677 3163
3678 #address-cells = <2>; 3164 #address-cells = <2>;
3679 #size-cells = <0>; 3165 #size-cells = <0>;
3680 #sound-dai-cells = <1 3166 #sound-dai-cells = <1>;
3681 status = "disabled"; 3167 status = "disabled";
3682 }; 3168 };
3683 3169
3684 lpass_audiocc: clock-controll <<
3685 compatible = "qcom,x1 <<
3686 reg = <0 0x06b6c000 0 <<
3687 #clock-cells = <1>; <<
3688 #reset-cells = <1>; <<
3689 }; <<
3690 <<
3691 swr2: soundwire@6d30000 { 3170 swr2: soundwire@6d30000 {
3692 compatible = "qcom,so 3171 compatible = "qcom,soundwire-v2.0.0";
3693 reg = <0 0x06d30000 0 3172 reg = <0 0x06d30000 0 0x10000>;
3694 clocks = <&lpass_txma 3173 clocks = <&lpass_txmacro>;
3695 clock-names = "iface" 3174 clock-names = "iface";
3696 interrupts = <GIC_SPI 3175 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
3697 <GIC_SPI 3176 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>;
3698 interrupt-names = "co 3177 interrupt-names = "core", "wakeup";
3699 label = "TX"; 3178 label = "TX";
3700 resets = <&lpasscc LP <<
3701 reset-names = "swr_au <<
3702 3179
3703 pinctrl-0 = <&tx_swr_ 3180 pinctrl-0 = <&tx_swr_active>;
3704 pinctrl-names = "defa 3181 pinctrl-names = "default";
3705 3182
3706 qcom,din-ports = <4>; 3183 qcom,din-ports = <4>;
3707 qcom,dout-ports = <1> 3184 qcom,dout-ports = <1>;
3708 3185
3709 qcom,ports-sinterval- 3186 qcom,ports-sinterval-low = /bits/ 8 <0x00 0x01 0x03 0x03 0x00>;
3710 qcom,ports-offset1 = 3187 qcom,ports-offset1 = /bits/ 8 <0x00 0x01 0x02 0x00 0x00>;
3711 qcom,ports-offset2 = 3188 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00 0xff>;
3712 qcom,ports-hstart = 3189 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
3713 qcom,ports-hstop = 3190 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
3714 qcom,ports-word-lengt 3191 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
3715 qcom,ports-block-pack 3192 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
3716 qcom,ports-block-grou 3193 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
3717 qcom,ports-lane-contr 3194 qcom,ports-lane-control = /bits/ 8 <0xff 0x00 0x00 0x01 0xff>;
3718 3195
3719 #address-cells = <2>; 3196 #address-cells = <2>;
3720 #size-cells = <0>; 3197 #size-cells = <0>;
3721 #sound-dai-cells = <1 3198 #sound-dai-cells = <1>;
3722 status = "disabled"; 3199 status = "disabled";
3723 }; 3200 };
3724 3201
3725 lpass_vamacro: codec@6d44000 3202 lpass_vamacro: codec@6d44000 {
3726 compatible = "qcom,x1 3203 compatible = "qcom,x1e80100-lpass-va-macro", "qcom,sm8550-lpass-va-macro";
3727 reg = <0 0x06d44000 0 3204 reg = <0 0x06d44000 0 0x1000>;
3728 clocks = <&q6prmcc LP 3205 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3729 <&q6prmcc LP 3206 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3730 <&q6prmcc LP 3207 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
3731 clock-names = "mclk", 3208 clock-names = "mclk",
3732 "macro" 3209 "macro",
3733 "dcodec 3210 "dcodec";
3734 3211
3735 #clock-cells = <0>; 3212 #clock-cells = <0>;
3736 clock-output-names = 3213 clock-output-names = "fsgen";
3737 #sound-dai-cells = <1 3214 #sound-dai-cells = <1>;
3738 }; 3215 };
3739 3216
3740 lpass_tlmm: pinctrl@6e80000 { 3217 lpass_tlmm: pinctrl@6e80000 {
3741 compatible = "qcom,x1 3218 compatible = "qcom,x1e80100-lpass-lpi-pinctrl", "qcom,sm8550-lpass-lpi-pinctrl";
3742 reg = <0 0x06e80000 0 3219 reg = <0 0x06e80000 0 0x20000>,
3743 <0 0x07250000 0 3220 <0 0x07250000 0 0x10000>;
3744 3221
3745 clocks = <&q6prmcc LP 3222 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3746 <&q6prmcc LP 3223 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
3747 clock-names = "core", 3224 clock-names = "core", "audio";
3748 3225
3749 gpio-controller; 3226 gpio-controller;
3750 #gpio-cells = <2>; 3227 #gpio-cells = <2>;
3751 gpio-ranges = <&lpass 3228 gpio-ranges = <&lpass_tlmm 0 0 23>;
3752 3229
3753 tx_swr_active: tx-swr 3230 tx_swr_active: tx-swr-active-state {
3754 clk-pins { 3231 clk-pins {
3755 pins 3232 pins = "gpio0";
3756 funct 3233 function = "swr_tx_clk";
3757 drive 3234 drive-strength = <2>;
3758 slew- 3235 slew-rate = <1>;
3759 bias- 3236 bias-disable;
3760 }; 3237 };
3761 3238
3762 data-pins { 3239 data-pins {
3763 pins 3240 pins = "gpio1", "gpio2";
3764 funct 3241 function = "swr_tx_data";
3765 drive 3242 drive-strength = <2>;
3766 slew- 3243 slew-rate = <1>;
3767 bias- 3244 bias-bus-hold;
3768 }; 3245 };
3769 }; 3246 };
3770 3247
3771 rx_swr_active: rx-swr 3248 rx_swr_active: rx-swr-active-state {
3772 clk-pins { 3249 clk-pins {
3773 pins 3250 pins = "gpio3";
3774 funct 3251 function = "swr_rx_clk";
3775 drive 3252 drive-strength = <2>;
3776 slew- 3253 slew-rate = <1>;
3777 bias- 3254 bias-disable;
3778 }; 3255 };
3779 3256
3780 data-pins { 3257 data-pins {
3781 pins 3258 pins = "gpio4", "gpio5";
3782 funct 3259 function = "swr_rx_data";
3783 drive 3260 drive-strength = <2>;
3784 slew- 3261 slew-rate = <1>;
3785 bias- 3262 bias-bus-hold;
3786 }; 3263 };
3787 }; 3264 };
3788 3265
3789 dmic01_default: dmic0 3266 dmic01_default: dmic01-default-state {
3790 clk-pins { 3267 clk-pins {
3791 pins 3268 pins = "gpio6";
3792 funct 3269 function = "dmic1_clk";
3793 drive 3270 drive-strength = <8>;
3794 outpu 3271 output-high;
3795 }; 3272 };
3796 3273
3797 data-pins { 3274 data-pins {
3798 pins 3275 pins = "gpio7";
3799 funct 3276 function = "dmic1_data";
3800 drive 3277 drive-strength = <8>;
3801 input 3278 input-enable;
3802 }; 3279 };
3803 }; 3280 };
3804 3281
3805 dmic23_default: dmic2 3282 dmic23_default: dmic23-default-state {
3806 clk-pins { 3283 clk-pins {
3807 pins 3284 pins = "gpio8";
3808 funct 3285 function = "dmic2_clk";
3809 drive 3286 drive-strength = <8>;
3810 outpu 3287 output-high;
3811 }; 3288 };
3812 3289
3813 data-pins { 3290 data-pins {
3814 pins 3291 pins = "gpio9";
3815 funct 3292 function = "dmic2_data";
3816 drive 3293 drive-strength = <8>;
3817 input 3294 input-enable;
3818 }; 3295 };
3819 }; 3296 };
3820 3297
3821 wsa_swr_active: wsa-s 3298 wsa_swr_active: wsa-swr-active-state {
3822 clk-pins { 3299 clk-pins {
3823 pins 3300 pins = "gpio10";
3824 funct 3301 function = "wsa_swr_clk";
3825 drive 3302 drive-strength = <2>;
3826 slew- 3303 slew-rate = <1>;
3827 bias- 3304 bias-disable;
3828 }; 3305 };
3829 3306
3830 data-pins { 3307 data-pins {
3831 pins 3308 pins = "gpio11";
3832 funct 3309 function = "wsa_swr_data";
3833 drive 3310 drive-strength = <2>;
3834 slew- 3311 slew-rate = <1>;
3835 bias- 3312 bias-bus-hold;
3836 }; 3313 };
3837 }; 3314 };
3838 3315
3839 wsa2_swr_active: wsa2 3316 wsa2_swr_active: wsa2-swr-active-state {
3840 clk-pins { 3317 clk-pins {
3841 pins 3318 pins = "gpio15";
3842 funct 3319 function = "wsa2_swr_clk";
3843 drive 3320 drive-strength = <2>;
3844 slew- 3321 slew-rate = <1>;
3845 bias- 3322 bias-disable;
3846 }; 3323 };
3847 3324
3848 data-pins { 3325 data-pins {
3849 pins 3326 pins = "gpio16";
3850 funct 3327 function = "wsa2_swr_data";
3851 drive 3328 drive-strength = <2>;
3852 slew- 3329 slew-rate = <1>;
3853 bias- 3330 bias-bus-hold;
3854 }; 3331 };
3855 }; 3332 };
3856 }; 3333 };
3857 3334
3858 lpasscc: clock-controller@6ea <<
3859 compatible = "qcom,x1 <<
3860 reg = <0 0x06ea0000 0 <<
3861 #clock-cells = <1>; <<
3862 #reset-cells = <1>; <<
3863 }; <<
3864 <<
3865 lpass_ag_noc: interconnect@7e 3335 lpass_ag_noc: interconnect@7e40000 {
3866 compatible = "qcom,x1 3336 compatible = "qcom,x1e80100-lpass-ag-noc";
3867 reg = <0 0x07e40000 0 !! 3337 reg = <0 0x7e40000 0 0xE080>;
3868 3338
3869 qcom,bcm-voters = <&a 3339 qcom,bcm-voters = <&apps_bcm_voter>;
3870 3340
3871 #interconnect-cells = 3341 #interconnect-cells = <2>;
3872 }; 3342 };
3873 3343
3874 lpass_lpiaon_noc: interconnec 3344 lpass_lpiaon_noc: interconnect@7400000 {
3875 compatible = "qcom,x1 3345 compatible = "qcom,x1e80100-lpass-lpiaon-noc";
3876 reg = <0 0x07400000 0 !! 3346 reg = <0 0x7400000 0 0x19080>;
3877 3347
3878 qcom,bcm-voters = <&a 3348 qcom,bcm-voters = <&apps_bcm_voter>;
3879 3349
3880 #interconnect-cells = 3350 #interconnect-cells = <2>;
3881 }; 3351 };
3882 3352
3883 lpass_lpicx_noc: interconnect 3353 lpass_lpicx_noc: interconnect@7430000 {
3884 compatible = "qcom,x1 3354 compatible = "qcom,x1e80100-lpass-lpicx-noc";
3885 reg = <0 0x07430000 0 !! 3355 reg = <0 0x7430000 0 0x3A200>;
3886 3356
3887 qcom,bcm-voters = <&a 3357 qcom,bcm-voters = <&apps_bcm_voter>;
3888 3358
3889 #interconnect-cells = 3359 #interconnect-cells = <2>;
3890 }; 3360 };
3891 3361
3892 usb_2_hsphy: phy@88e0000 { 3362 usb_2_hsphy: phy@88e0000 {
3893 compatible = "qcom,x1 3363 compatible = "qcom,x1e80100-snps-eusb2-phy",
3894 "qcom,sm 3364 "qcom,sm8550-snps-eusb2-phy";
3895 reg = <0 0x088e0000 0 3365 reg = <0 0x088e0000 0 0x154>;
3896 #phy-cells = <0>; 3366 #phy-cells = <0>;
3897 3367
3898 clocks = <&tcsr TCSR_ 3368 clocks = <&tcsr TCSR_USB2_2_CLKREF_EN>;
3899 clock-names = "ref"; 3369 clock-names = "ref";
3900 3370
3901 resets = <&gcc GCC_QU 3371 resets = <&gcc GCC_QUSB2PHY_USB20_HS_BCR>;
3902 3372
3903 status = "disabled"; 3373 status = "disabled";
3904 }; 3374 };
3905 3375
3906 usb_mp_hsphy0: phy@88e1000 { <<
3907 compatible = "qcom,x1 <<
3908 "qcom,sm <<
3909 reg = <0 0x088e1000 0 <<
3910 #phy-cells = <0>; <<
3911 <<
3912 clocks = <&tcsr TCSR_ <<
3913 clock-names = "ref"; <<
3914 <<
3915 resets = <&gcc GCC_QU <<
3916 <<
3917 status = "disabled"; <<
3918 }; <<
3919 <<
3920 usb_mp_hsphy1: phy@88e2000 { <<
3921 compatible = "qcom,x1 <<
3922 "qcom,sm <<
3923 reg = <0 0x088e2000 0 <<
3924 #phy-cells = <0>; <<
3925 <<
3926 clocks = <&tcsr TCSR_ <<
3927 clock-names = "ref"; <<
3928 <<
3929 resets = <&gcc GCC_QU <<
3930 <<
3931 status = "disabled"; <<
3932 }; <<
3933 <<
3934 usb_mp_qmpphy0: phy@88e3000 { <<
3935 compatible = "qcom,x1 <<
3936 reg = <0 0x088e3000 0 <<
3937 <<
3938 clocks = <&gcc GCC_US <<
3939 <&rpmhcc RPM <<
3940 <&gcc GCC_US <<
3941 <&gcc GCC_US <<
3942 clock-names = "aux", <<
3943 "ref", <<
3944 "com_au <<
3945 "pipe"; <<
3946 <<
3947 resets = <&gcc GCC_US <<
3948 <&gcc GCC_US <<
3949 reset-names = "phy", <<
3950 "phy_ph <<
3951 <<
3952 power-domains = <&gcc <<
3953 <<
3954 #clock-cells = <0>; <<
3955 clock-output-names = <<
3956 <<
3957 #phy-cells = <0>; <<
3958 <<
3959 status = "disabled"; <<
3960 }; <<
3961 <<
3962 usb_mp_qmpphy1: phy@88e5000 { <<
3963 compatible = "qcom,x1 <<
3964 reg = <0 0x088e5000 0 <<
3965 <<
3966 clocks = <&gcc GCC_US <<
3967 <&rpmhcc RPM <<
3968 <&gcc GCC_US <<
3969 <&gcc GCC_US <<
3970 clock-names = "aux", <<
3971 "ref", <<
3972 "com_au <<
3973 "pipe"; <<
3974 <<
3975 resets = <&gcc GCC_US <<
3976 <&gcc GCC_US <<
3977 reset-names = "phy", <<
3978 "phy_ph <<
3979 <<
3980 power-domains = <&gcc <<
3981 <<
3982 #clock-cells = <0>; <<
3983 clock-output-names = <<
3984 <<
3985 #phy-cells = <0>; <<
3986 <<
3987 status = "disabled"; <<
3988 }; <<
3989 <<
3990 usb_1_ss2: usb@a0f8800 { 3376 usb_1_ss2: usb@a0f8800 {
3991 compatible = "qcom,x1 3377 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3";
3992 reg = <0 0x0a0f8800 0 3378 reg = <0 0x0a0f8800 0 0x400>;
3993 3379
3994 clocks = <&gcc GCC_CF 3380 clocks = <&gcc GCC_CFG_NOC_USB3_TERT_AXI_CLK>,
3995 <&gcc GCC_US 3381 <&gcc GCC_USB30_TERT_MASTER_CLK>,
3996 <&gcc GCC_AG 3382 <&gcc GCC_AGGRE_USB3_TERT_AXI_CLK>,
3997 <&gcc GCC_US 3383 <&gcc GCC_USB30_TERT_SLEEP_CLK>,
3998 <&gcc GCC_US 3384 <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>,
3999 <&gcc GCC_AG 3385 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
4000 <&gcc GCC_AG 3386 <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>,
4001 <&gcc GCC_AG 3387 <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>,
4002 <&gcc GCC_SY 3388 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
4003 clock-names = "cfg_no 3389 clock-names = "cfg_noc",
4004 "core", 3390 "core",
4005 "iface" 3391 "iface",
4006 "sleep" 3392 "sleep",
4007 "mock_u 3393 "mock_utmi",
4008 "noc_ag 3394 "noc_aggr",
4009 "noc_ag 3395 "noc_aggr_north",
4010 "noc_ag 3396 "noc_aggr_south",
4011 "noc_sy 3397 "noc_sys";
4012 3398
4013 assigned-clocks = <&g 3399 assigned-clocks = <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>,
4014 <&g 3400 <&gcc GCC_USB30_TERT_MASTER_CLK>;
4015 assigned-clock-rates 3401 assigned-clock-rates = <19200000>,
4016 3402 <200000000>;
4017 3403
4018 interrupts-extended = 3404 interrupts-extended = <&intc GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
4019 3405 <&pdc 58 IRQ_TYPE_EDGE_BOTH>,
4020 3406 <&pdc 57 IRQ_TYPE_EDGE_BOTH>,
4021 3407 <&pdc 10 IRQ_TYPE_LEVEL_HIGH>;
4022 interrupt-names = "pw 3408 interrupt-names = "pwr_event",
4023 "dp 3409 "dp_hs_phy_irq",
4024 "dm 3410 "dm_hs_phy_irq",
4025 "ss 3411 "ss_phy_irq";
4026 3412
4027 power-domains = <&gcc 3413 power-domains = <&gcc GCC_USB30_TERT_GDSC>;
4028 required-opps = <&rpm 3414 required-opps = <&rpmhpd_opp_nom>;
4029 3415
4030 resets = <&gcc GCC_US 3416 resets = <&gcc GCC_USB30_TERT_BCR>;
4031 3417
4032 interconnects = <&usb 3418 interconnects = <&usb_south_anoc MASTER_USB3_2 QCOM_ICC_TAG_ALWAYS
4033 &mc_ 3419 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
4034 <&gem 3420 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
4035 &con 3421 &config_noc SLAVE_USB3_2 QCOM_ICC_TAG_ALWAYS>;
4036 interconnect-names = 3422 interconnect-names = "usb-ddr",
4037 3423 "apps-usb";
4038 3424
4039 wakeup-source; 3425 wakeup-source;
4040 3426
4041 #address-cells = <2>; 3427 #address-cells = <2>;
4042 #size-cells = <2>; 3428 #size-cells = <2>;
4043 ranges; 3429 ranges;
4044 3430
4045 status = "disabled"; 3431 status = "disabled";
4046 3432
4047 usb_1_ss2_dwc3: usb@a 3433 usb_1_ss2_dwc3: usb@a000000 {
4048 compatible = 3434 compatible = "snps,dwc3";
4049 reg = <0 0x0a 3435 reg = <0 0x0a000000 0 0xcd00>;
4050 3436
4051 interrupts = 3437 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
4052 3438
4053 iommus = <&ap 3439 iommus = <&apps_smmu 0x14a0 0x0>;
4054 3440
4055 phys = <&usb_ 3441 phys = <&usb_1_ss2_hsphy>,
4056 <&usb_ 3442 <&usb_1_ss2_qmpphy QMP_USB43DP_USB3_PHY>;
4057 phy-names = " 3443 phy-names = "usb2-phy",
4058 " 3444 "usb3-phy";
4059 3445
4060 snps,dis_u2_s 3446 snps,dis_u2_susphy_quirk;
4061 snps,dis_enbl 3447 snps,dis_enblslpm_quirk;
4062 snps,usb3_lpm 3448 snps,usb3_lpm_capable;
4063 3449
4064 dma-coherent; 3450 dma-coherent;
4065 3451
4066 ports { !! 3452 port {
4067 #addr !! 3453 usb_1_ss2_role_switch: endpoint {
4068 #size <<
4069 <<
4070 port@ <<
4071 <<
4072 <<
4073 <<
4074 <<
4075 }; <<
4076 <<
4077 port@ <<
4078 <<
4079 <<
4080 <<
4081 <<
4082 <<
4083 }; 3454 };
4084 }; 3455 };
4085 }; 3456 };
4086 }; 3457 };
4087 3458
4088 usb_2: usb@a2f8800 { 3459 usb_2: usb@a2f8800 {
4089 compatible = "qcom,x1 3460 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3";
4090 reg = <0 0x0a2f8800 0 3461 reg = <0 0x0a2f8800 0 0x400>;
4091 #address-cells = <2>; 3462 #address-cells = <2>;
4092 #size-cells = <2>; 3463 #size-cells = <2>;
4093 ranges; 3464 ranges;
4094 3465
4095 clocks = <&gcc GCC_CF 3466 clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>,
4096 <&gcc GCC_US 3467 <&gcc GCC_USB20_MASTER_CLK>,
4097 <&gcc GCC_AG 3468 <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>,
4098 <&gcc GCC_US 3469 <&gcc GCC_USB20_SLEEP_CLK>,
4099 <&gcc GCC_US 3470 <&gcc GCC_USB20_MOCK_UTMI_CLK>,
4100 <&gcc GCC_AG 3471 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
4101 <&gcc GCC_AG 3472 <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>,
4102 <&gcc GCC_AG 3473 <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>,
4103 <&gcc GCC_SY 3474 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
4104 clock-names = "cfg_no 3475 clock-names = "cfg_noc",
4105 "core", 3476 "core",
4106 "iface" 3477 "iface",
4107 "sleep" 3478 "sleep",
4108 "mock_u 3479 "mock_utmi",
4109 "noc_ag 3480 "noc_aggr",
4110 "noc_ag 3481 "noc_aggr_north",
4111 "noc_ag 3482 "noc_aggr_south",
4112 "noc_sy 3483 "noc_sys";
4113 3484
4114 assigned-clocks = <&g 3485 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
4115 <&g 3486 <&gcc GCC_USB20_MASTER_CLK>;
4116 assigned-clock-rates 3487 assigned-clock-rates = <19200000>, <200000000>;
4117 3488
4118 interrupts-extended = 3489 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4119 3490 <&pdc 50 IRQ_TYPE_EDGE_BOTH>,
4120 3491 <&pdc 49 IRQ_TYPE_EDGE_BOTH>;
4121 interrupt-names = "pw 3492 interrupt-names = "pwr_event",
4122 "dp 3493 "dp_hs_phy_irq",
4123 "dm 3494 "dm_hs_phy_irq";
4124 3495
4125 power-domains = <&gcc 3496 power-domains = <&gcc GCC_USB20_PRIM_GDSC>;
4126 required-opps = <&rpm 3497 required-opps = <&rpmhpd_opp_nom>;
4127 3498
4128 resets = <&gcc GCC_US 3499 resets = <&gcc GCC_USB20_PRIM_BCR>;
4129 3500
4130 interconnects = <&usb 3501 interconnects = <&usb_north_anoc MASTER_USB2 QCOM_ICC_TAG_ALWAYS
4131 &mc_ 3502 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
4132 <&gem 3503 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
4133 &con 3504 &config_noc SLAVE_USB2 QCOM_ICC_TAG_ALWAYS>;
4134 interconnect-names = 3505 interconnect-names = "usb-ddr",
4135 3506 "apps-usb";
4136 3507
4137 wakeup-source; 3508 wakeup-source;
4138 3509
4139 status = "disabled"; 3510 status = "disabled";
4140 3511
4141 usb_2_dwc3: usb@a2000 3512 usb_2_dwc3: usb@a200000 {
4142 compatible = 3513 compatible = "snps,dwc3";
4143 reg = <0 0x0a 3514 reg = <0 0x0a200000 0 0xcd00>;
4144 interrupts = 3515 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
4145 iommus = <&ap 3516 iommus = <&apps_smmu 0x14e0 0x0>;
4146 phys = <&usb_ 3517 phys = <&usb_2_hsphy>;
4147 phy-names = " 3518 phy-names = "usb2-phy";
4148 maximum-speed 3519 maximum-speed = "high-speed";
4149 3520
4150 ports { !! 3521 port {
4151 #addr !! 3522 usb_2_role_switch: endpoint {
4152 #size <<
4153 <<
4154 port@ <<
4155 <<
4156 <<
4157 <<
4158 <<
4159 }; 3523 };
4160 }; 3524 };
4161 }; 3525 };
4162 }; 3526 };
4163 3527
4164 usb_mp: usb@a4f8800 { <<
4165 compatible = "qcom,x1 <<
4166 reg = <0 0x0a4f8800 0 <<
4167 <<
4168 clocks = <&gcc GCC_CF <<
4169 <&gcc GCC_US <<
4170 <&gcc GCC_AG <<
4171 <&gcc GCC_US <<
4172 <&gcc GCC_US <<
4173 <&gcc GCC_AG <<
4174 <&gcc GCC_AG <<
4175 <&gcc GCC_AG <<
4176 <&gcc GCC_SY <<
4177 clock-names = "cfg_no <<
4178 "core", <<
4179 "iface" <<
4180 "sleep" <<
4181 "mock_u <<
4182 "noc_ag <<
4183 "noc_ag <<
4184 "noc_ag <<
4185 "noc_sy <<
4186 <<
4187 assigned-clocks = <&g <<
4188 <&g <<
4189 assigned-clock-rates <<
4190 <<
4191 <<
4192 interrupts-extended = <<
4193 <<
4194 <<
4195 <<
4196 <<
4197 <<
4198 <<
4199 <<
4200 <<
4201 <<
4202 interrupt-names = "pw <<
4203 "hs <<
4204 "dp <<
4205 "dp <<
4206 "ss <<
4207 <<
4208 power-domains = <&gcc <<
4209 required-opps = <&rpm <<
4210 <<
4211 resets = <&gcc GCC_US <<
4212 <<
4213 interconnects = <&usb <<
4214 &mc_ <<
4215 <&gem <<
4216 &con <<
4217 interconnect-names = <<
4218 <<
4219 <<
4220 wakeup-source; <<
4221 <<
4222 #address-cells = <2>; <<
4223 #size-cells = <2>; <<
4224 ranges; <<
4225 <<
4226 status = "disabled"; <<
4227 <<
4228 usb_mp_dwc3: usb@a400 <<
4229 compatible = <<
4230 reg = <0 0x0a <<
4231 <<
4232 interrupts = <<
4233 <<
4234 iommus = <&ap <<
4235 <<
4236 phys = <&usb_ <<
4237 <&usb_ <<
4238 phy-names = " <<
4239 " <<
4240 dr_mode = "ho <<
4241 <<
4242 snps,dis_u2_s <<
4243 snps,dis_enbl <<
4244 snps,usb3_lpm <<
4245 <<
4246 dma-coherent; <<
4247 }; <<
4248 }; <<
4249 <<
4250 usb_1_ss0: usb@a6f8800 { 3528 usb_1_ss0: usb@a6f8800 {
4251 compatible = "qcom,x1 3529 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3";
4252 reg = <0 0x0a6f8800 0 3530 reg = <0 0x0a6f8800 0 0x400>;
4253 3531
4254 clocks = <&gcc GCC_CF 3532 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
4255 <&gcc GCC_US 3533 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
4256 <&gcc GCC_AG 3534 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
4257 <&gcc GCC_US 3535 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
4258 <&gcc GCC_US 3536 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4259 <&gcc GCC_AG 3537 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
4260 <&gcc GCC_CF 3538 <&gcc GCC_CFG_NOC_USB_ANOC_NORTH_AHB_CLK>,
4261 <&gcc GCC_CF 3539 <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>,
4262 <&gcc GCC_SY 3540 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
4263 clock-names = "cfg_no 3541 clock-names = "cfg_noc",
4264 "core", 3542 "core",
4265 "iface" 3543 "iface",
4266 "sleep" 3544 "sleep",
4267 "mock_u 3545 "mock_utmi",
4268 "noc_ag 3546 "noc_aggr",
4269 "noc_ag 3547 "noc_aggr_north",
4270 "noc_ag 3548 "noc_aggr_south",
4271 "noc_sy 3549 "noc_sys";
4272 3550
4273 assigned-clocks = <&g 3551 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4274 <&g 3552 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
4275 assigned-clock-rates 3553 assigned-clock-rates = <19200000>,
4276 3554 <200000000>;
4277 3555
4278 interrupts-extended = 3556 interrupts-extended = <&intc GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>,
4279 3557 <&pdc 61 IRQ_TYPE_EDGE_BOTH>,
4280 3558 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
4281 3559 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
4282 interrupt-names = "pw 3560 interrupt-names = "pwr_event",
4283 "dp 3561 "dp_hs_phy_irq",
4284 "dm 3562 "dm_hs_phy_irq",
4285 "ss 3563 "ss_phy_irq";
4286 3564
4287 power-domains = <&gcc 3565 power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
4288 required-opps = <&rpm 3566 required-opps = <&rpmhpd_opp_nom>;
4289 3567
4290 resets = <&gcc GCC_US 3568 resets = <&gcc GCC_USB30_PRIM_BCR>;
4291 3569
4292 wakeup-source; 3570 wakeup-source;
4293 3571
4294 #address-cells = <2>; 3572 #address-cells = <2>;
4295 #size-cells = <2>; 3573 #size-cells = <2>;
4296 ranges; 3574 ranges;
4297 3575
4298 status = "disabled"; 3576 status = "disabled";
4299 3577
4300 usb_1_ss0_dwc3: usb@a 3578 usb_1_ss0_dwc3: usb@a600000 {
4301 compatible = 3579 compatible = "snps,dwc3";
4302 reg = <0 0x0a 3580 reg = <0 0x0a600000 0 0xcd00>;
4303 3581
4304 interrupts = 3582 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
4305 3583
4306 iommus = <&ap 3584 iommus = <&apps_smmu 0x1420 0x0>;
4307 3585
4308 phys = <&usb_ 3586 phys = <&usb_1_ss0_hsphy>,
4309 <&usb_ 3587 <&usb_1_ss0_qmpphy QMP_USB43DP_USB3_PHY>;
4310 phy-names = " 3588 phy-names = "usb2-phy",
4311 " 3589 "usb3-phy";
4312 3590
4313 snps,dis_u2_s 3591 snps,dis_u2_susphy_quirk;
4314 snps,dis_enbl 3592 snps,dis_enblslpm_quirk;
4315 snps,usb3_lpm 3593 snps,usb3_lpm_capable;
4316 3594
4317 dma-coherent; 3595 dma-coherent;
4318 3596
4319 ports { !! 3597 port {
4320 #addr !! 3598 usb_1_ss0_role_switch: endpoint {
4321 #size <<
4322 <<
4323 port@ <<
4324 <<
4325 <<
4326 <<
4327 <<
4328 }; <<
4329 <<
4330 port@ <<
4331 <<
4332 <<
4333 <<
4334 <<
4335 <<
4336 }; 3599 };
4337 }; 3600 };
4338 }; 3601 };
4339 }; 3602 };
4340 3603
4341 usb_1_ss1: usb@a8f8800 { 3604 usb_1_ss1: usb@a8f8800 {
4342 compatible = "qcom,x1 3605 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3";
4343 reg = <0 0x0a8f8800 0 3606 reg = <0 0x0a8f8800 0 0x400>;
4344 3607
4345 clocks = <&gcc GCC_CF 3608 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
4346 <&gcc GCC_US 3609 <&gcc GCC_USB30_SEC_MASTER_CLK>,
4347 <&gcc GCC_AG 3610 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
4348 <&gcc GCC_US 3611 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
4349 <&gcc GCC_US 3612 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4350 <&gcc GCC_AG 3613 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
4351 <&gcc GCC_AG 3614 <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>,
4352 <&gcc GCC_AG 3615 <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>,
4353 <&gcc GCC_SY 3616 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
4354 clock-names = "cfg_no 3617 clock-names = "cfg_noc",
4355 "core", 3618 "core",
4356 "iface" 3619 "iface",
4357 "sleep" 3620 "sleep",
4358 "mock_u 3621 "mock_utmi",
4359 "noc_ag 3622 "noc_aggr",
4360 "noc_ag 3623 "noc_aggr_north",
4361 "noc_ag 3624 "noc_aggr_south",
4362 "noc_sy 3625 "noc_sys";
4363 3626
4364 assigned-clocks = <&g 3627 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4365 <&g 3628 <&gcc GCC_USB30_SEC_MASTER_CLK>;
4366 assigned-clock-rates 3629 assigned-clock-rates = <19200000>,
4367 3630 <200000000>;
4368 3631
4369 interrupts-extended = 3632 interrupts-extended = <&intc GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>,
4370 3633 <&pdc 60 IRQ_TYPE_EDGE_BOTH>,
4371 3634 <&pdc 11 IRQ_TYPE_EDGE_BOTH>,
4372 3635 <&pdc 47 IRQ_TYPE_LEVEL_HIGH>;
4373 interrupt-names = "pw 3636 interrupt-names = "pwr_event",
4374 "dp 3637 "dp_hs_phy_irq",
4375 "dm 3638 "dm_hs_phy_irq",
4376 "ss 3639 "ss_phy_irq";
4377 3640
4378 power-domains = <&gcc 3641 power-domains = <&gcc GCC_USB30_SEC_GDSC>;
4379 required-opps = <&rpm 3642 required-opps = <&rpmhpd_opp_nom>;
4380 3643
4381 resets = <&gcc GCC_US 3644 resets = <&gcc GCC_USB30_SEC_BCR>;
4382 3645
4383 interconnects = <&usb 3646 interconnects = <&usb_south_anoc MASTER_USB3_1 QCOM_ICC_TAG_ALWAYS
4384 &mc_ 3647 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
4385 <&gem 3648 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
4386 &con 3649 &config_noc SLAVE_USB3_1 QCOM_ICC_TAG_ALWAYS>;
4387 interconnect-names = 3650 interconnect-names = "usb-ddr",
4388 3651 "apps-usb";
4389 3652
4390 wakeup-source; 3653 wakeup-source;
4391 3654
4392 #address-cells = <2>; 3655 #address-cells = <2>;
4393 #size-cells = <2>; 3656 #size-cells = <2>;
4394 ranges; 3657 ranges;
4395 3658
4396 status = "disabled"; 3659 status = "disabled";
4397 3660
4398 usb_1_ss1_dwc3: usb@a 3661 usb_1_ss1_dwc3: usb@a800000 {
4399 compatible = 3662 compatible = "snps,dwc3";
4400 reg = <0 0x0a 3663 reg = <0 0x0a800000 0 0xcd00>;
4401 3664
4402 interrupts = 3665 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
4403 3666
4404 iommus = <&ap 3667 iommus = <&apps_smmu 0x1460 0x0>;
4405 3668
4406 phys = <&usb_ 3669 phys = <&usb_1_ss1_hsphy>,
4407 <&usb_ 3670 <&usb_1_ss1_qmpphy QMP_USB43DP_USB3_PHY>;
4408 phy-names = " 3671 phy-names = "usb2-phy",
4409 " 3672 "usb3-phy";
4410 3673
4411 snps,dis_u2_s 3674 snps,dis_u2_susphy_quirk;
4412 snps,dis_enbl 3675 snps,dis_enblslpm_quirk;
4413 snps,usb3_lpm 3676 snps,usb3_lpm_capable;
4414 3677
4415 dma-coherent; 3678 dma-coherent;
4416 3679
4417 ports { !! 3680 port {
4418 #addr !! 3681 usb_1_ss1_role_switch: endpoint {
4419 #size <<
4420 <<
4421 port@ <<
4422 <<
4423 <<
4424 <<
4425 <<
4426 }; <<
4427 <<
4428 port@ <<
4429 <<
4430 <<
4431 <<
4432 <<
4433 <<
4434 }; 3682 };
4435 }; 3683 };
4436 }; 3684 };
4437 }; 3685 };
4438 3686
4439 mdss: display-subsystem@ae000 3687 mdss: display-subsystem@ae00000 {
4440 compatible = "qcom,x1 3688 compatible = "qcom,x1e80100-mdss";
4441 reg = <0 0x0ae00000 0 3689 reg = <0 0x0ae00000 0 0x1000>;
4442 reg-names = "mdss"; 3690 reg-names = "mdss";
4443 3691
4444 interrupts = <GIC_SPI 3692 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
4445 3693
4446 clocks = <&dispcc DIS 3694 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4447 <&gcc GCC_DI 3695 <&gcc GCC_DISP_HF_AXI_CLK>,
4448 <&dispcc DIS 3696 <&dispcc DISP_CC_MDSS_MDP_CLK>;
4449 3697
4450 resets = <&dispcc DIS 3698 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
4451 3699
4452 interconnects = <&mms 3700 interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS
4453 &gem 3701 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
4454 <&mc_ 3702 <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS
4455 &mc_ 3703 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
4456 <&gem 3704 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
4457 &con 3705 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
4458 interconnect-names = 3706 interconnect-names = "mdp0-mem",
4459 3707 "mdp1-mem",
4460 3708 "cpu-cfg";
4461 3709
4462 power-domains = <&dis 3710 power-domains = <&dispcc MDSS_GDSC>;
4463 3711
4464 iommus = <&apps_smmu 3712 iommus = <&apps_smmu 0x1c00 0x2>;
4465 3713
4466 interrupt-controller; 3714 interrupt-controller;
4467 #interrupt-cells = <1 3715 #interrupt-cells = <1>;
4468 3716
4469 #address-cells = <2>; 3717 #address-cells = <2>;
4470 #size-cells = <2>; 3718 #size-cells = <2>;
4471 ranges; 3719 ranges;
4472 3720
4473 status = "disabled"; 3721 status = "disabled";
4474 3722
4475 mdss_mdp: display-con 3723 mdss_mdp: display-controller@ae01000 {
4476 compatible = 3724 compatible = "qcom,x1e80100-dpu";
4477 reg = <0 0x0a 3725 reg = <0 0x0ae01000 0 0x8f000>,
4478 <0 0x0a 3726 <0 0x0aeb0000 0 0x2008>;
4479 reg-names = " 3727 reg-names = "mdp",
4480 " 3728 "vbif";
4481 3729
4482 interrupts-ex 3730 interrupts-extended = <&mdss 0>;
4483 3731
4484 clocks = <&gc 3732 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
4485 <&di 3733 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4486 <&di 3734 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
4487 <&di 3735 <&dispcc DISP_CC_MDSS_MDP_CLK>,
4488 <&di 3736 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4489 clock-names = 3737 clock-names = "nrt_bus",
4490 3738 "iface",
4491 3739 "lut",
4492 3740 "core",
4493 3741 "vsync";
4494 3742
4495 operating-poi 3743 operating-points-v2 = <&mdp_opp_table>;
4496 3744
4497 power-domains 3745 power-domains = <&rpmhpd RPMHPD_MMCX>;
4498 3746
4499 ports { 3747 ports {
4500 #addr 3748 #address-cells = <1>;
4501 #size 3749 #size-cells = <0>;
4502 3750
4503 port@ 3751 port@0 {
4504 3752 reg = <0>;
4505 3753
4506 3754 mdss_intf0_out: endpoint {
4507 3755 remote-endpoint = <&mdss_dp0_in>;
4508 3756 };
4509 }; 3757 };
4510 3758
4511 port@ 3759 port@4 {
4512 3760 reg = <4>;
4513 3761
4514 3762 mdss_intf4_out: endpoint {
4515 3763 remote-endpoint = <&mdss_dp1_in>;
4516 3764 };
4517 }; 3765 };
4518 3766
4519 port@ 3767 port@5 {
4520 3768 reg = <5>;
4521 3769
4522 3770 mdss_intf5_out: endpoint {
4523 3771 remote-endpoint = <&mdss_dp3_in>;
4524 3772 };
4525 }; 3773 };
4526 3774
4527 port@ 3775 port@6 {
4528 3776 reg = <6>;
4529 3777
4530 3778 mdss_intf6_out: endpoint {
4531 3779 remote-endpoint = <&mdss_dp2_in>;
4532 3780 };
4533 }; 3781 };
4534 }; 3782 };
4535 3783
4536 mdp_opp_table 3784 mdp_opp_table: opp-table {
4537 compa 3785 compatible = "operating-points-v2";
4538 3786
4539 opp-2 3787 opp-200000000 {
4540 3788 opp-hz = /bits/ 64 <200000000>;
4541 3789 required-opps = <&rpmhpd_opp_low_svs>;
4542 }; 3790 };
4543 3791
4544 opp-3 3792 opp-325000000 {
4545 3793 opp-hz = /bits/ 64 <325000000>;
4546 3794 required-opps = <&rpmhpd_opp_svs>;
4547 }; 3795 };
4548 3796
4549 opp-3 3797 opp-375000000 {
4550 3798 opp-hz = /bits/ 64 <375000000>;
4551 3799 required-opps = <&rpmhpd_opp_svs_l1>;
4552 }; 3800 };
4553 3801
4554 opp-5 3802 opp-514000000 {
4555 3803 opp-hz = /bits/ 64 <514000000>;
4556 3804 required-opps = <&rpmhpd_opp_nom>;
4557 }; 3805 };
4558 3806
4559 opp-5 3807 opp-575000000 {
4560 3808 opp-hz = /bits/ 64 <575000000>;
4561 3809 required-opps = <&rpmhpd_opp_nom_l1>;
4562 }; 3810 };
4563 }; 3811 };
4564 }; 3812 };
4565 3813
4566 mdss_dp0: displayport 3814 mdss_dp0: displayport-controller@ae90000 {
4567 compatible = 3815 compatible = "qcom,x1e80100-dp";
4568 reg = <0 0x0a !! 3816 reg = <0 0xae90000 0 0x200>,
4569 <0 0x0a !! 3817 <0 0xae90200 0 0x200>,
4570 <0 0x0a !! 3818 <0 0xae90400 0 0x600>,
4571 <0 0x0a !! 3819 <0 0xae91000 0 0x400>,
4572 <0 0x0a !! 3820 <0 0xae91400 0 0x400>;
4573 3821
4574 interrupts-ex 3822 interrupts-extended = <&mdss 12>;
4575 3823
4576 clocks = <&di 3824 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4577 <&di 3825 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
4578 <&di 3826 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
4579 <&di 3827 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
4580 <&di 3828 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
4581 clock-names = 3829 clock-names = "core_iface",
4582 3830 "core_aux",
4583 3831 "ctrl_link",
4584 3832 "ctrl_link_iface",
4585 3833 "stream_pixel";
4586 3834
4587 assigned-cloc 3835 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
4588 3836 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
4589 assigned-cloc 3837 assigned-clock-parents = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4590 3838 <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
4591 3839
4592 operating-poi 3840 operating-points-v2 = <&mdss_dp0_opp_table>;
4593 3841
4594 power-domains 3842 power-domains = <&rpmhpd RPMHPD_MMCX>;
4595 3843
4596 phys = <&usb_ 3844 phys = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_PHY>;
4597 phy-names = " 3845 phy-names = "dp";
4598 3846
4599 #sound-dai-ce 3847 #sound-dai-cells = <0>;
4600 3848
4601 status = "dis 3849 status = "disabled";
4602 3850
4603 ports { 3851 ports {
4604 #addr 3852 #address-cells = <1>;
4605 #size 3853 #size-cells = <0>;
4606 3854
4607 port@ 3855 port@0 {
4608 3856 reg = <0>;
4609 3857
4610 3858 mdss_dp0_in: endpoint {
4611 3859 remote-endpoint = <&mdss_intf0_out>;
4612 3860 };
4613 }; 3861 };
4614 3862
4615 port@ 3863 port@1 {
4616 3864 reg = <1>;
4617 3865
4618 3866 mdss_dp0_out: endpoint {
4619 <<
4620 3867 };
4621 }; 3868 };
4622 }; 3869 };
4623 3870
4624 mdss_dp0_opp_ 3871 mdss_dp0_opp_table: opp-table {
4625 compa 3872 compatible = "operating-points-v2";
4626 3873
4627 opp-1 3874 opp-160000000 {
4628 3875 opp-hz = /bits/ 64 <160000000>;
4629 3876 required-opps = <&rpmhpd_opp_low_svs>;
4630 }; 3877 };
4631 3878
4632 opp-2 3879 opp-270000000 {
4633 3880 opp-hz = /bits/ 64 <270000000>;
4634 3881 required-opps = <&rpmhpd_opp_svs>;
4635 }; 3882 };
4636 3883
4637 opp-5 3884 opp-540000000 {
4638 3885 opp-hz = /bits/ 64 <540000000>;
4639 3886 required-opps = <&rpmhpd_opp_svs_l1>;
4640 }; 3887 };
4641 3888
4642 opp-8 3889 opp-810000000 {
4643 3890 opp-hz = /bits/ 64 <810000000>;
4644 3891 required-opps = <&rpmhpd_opp_nom>;
4645 }; 3892 };
4646 }; 3893 };
4647 }; 3894 };
4648 3895
4649 mdss_dp1: displayport 3896 mdss_dp1: displayport-controller@ae98000 {
4650 compatible = 3897 compatible = "qcom,x1e80100-dp";
4651 reg = <0 0x0a !! 3898 reg = <0 0xae98000 0 0x200>,
4652 <0 0x0a !! 3899 <0 0xae98200 0 0x200>,
4653 <0 0x0a !! 3900 <0 0xae98400 0 0x600>,
4654 <0 0x0a !! 3901 <0 0xae99000 0 0x400>,
4655 <0 0x0a !! 3902 <0 0xae99400 0 0x400>;
4656 3903
4657 interrupts-ex 3904 interrupts-extended = <&mdss 13>;
4658 3905
4659 clocks = <&di 3906 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4660 <&di 3907 <&dispcc DISP_CC_MDSS_DPTX1_AUX_CLK>,
4661 <&di 3908 <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK>,
4662 <&di 3909 <&dispcc DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
4663 <&di 3910 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK>;
4664 clock-names = 3911 clock-names = "core_iface",
4665 3912 "core_aux",
4666 3913 "ctrl_link",
4667 3914 "ctrl_link_iface",
4668 3915 "stream_pixel";
4669 3916
4670 assigned-cloc 3917 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
4671 3918 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>;
4672 assigned-cloc 3919 assigned-clock-parents = <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4673 3920 <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
4674 3921
4675 operating-poi 3922 operating-points-v2 = <&mdss_dp1_opp_table>;
4676 3923
4677 power-domains 3924 power-domains = <&rpmhpd RPMHPD_MMCX>;
4678 3925
4679 phys = <&usb_ 3926 phys = <&usb_1_ss1_qmpphy QMP_USB43DP_DP_PHY>;
4680 phy-names = " 3927 phy-names = "dp";
4681 3928
4682 #sound-dai-ce 3929 #sound-dai-cells = <0>;
4683 3930
4684 status = "dis 3931 status = "disabled";
4685 3932
4686 ports { 3933 ports {
4687 #addr 3934 #address-cells = <1>;
4688 #size 3935 #size-cells = <0>;
4689 3936
4690 port@ 3937 port@0 {
4691 3938 reg = <0>;
4692 3939
4693 3940 mdss_dp1_in: endpoint {
4694 3941 remote-endpoint = <&mdss_intf4_out>;
4695 3942 };
4696 }; 3943 };
4697 3944
4698 port@ 3945 port@1 {
4699 3946 reg = <1>;
4700 3947
4701 3948 mdss_dp1_out: endpoint {
4702 <<
4703 3949 };
4704 }; 3950 };
4705 }; 3951 };
4706 3952
4707 mdss_dp1_opp_ 3953 mdss_dp1_opp_table: opp-table {
4708 compa 3954 compatible = "operating-points-v2";
4709 3955
4710 opp-1 3956 opp-160000000 {
4711 3957 opp-hz = /bits/ 64 <160000000>;
4712 3958 required-opps = <&rpmhpd_opp_low_svs>;
4713 }; 3959 };
4714 3960
4715 opp-2 3961 opp-270000000 {
4716 3962 opp-hz = /bits/ 64 <270000000>;
4717 3963 required-opps = <&rpmhpd_opp_svs>;
4718 }; 3964 };
4719 3965
4720 opp-5 3966 opp-540000000 {
4721 3967 opp-hz = /bits/ 64 <540000000>;
4722 3968 required-opps = <&rpmhpd_opp_svs_l1>;
4723 }; 3969 };
4724 3970
4725 opp-8 3971 opp-810000000 {
4726 3972 opp-hz = /bits/ 64 <810000000>;
4727 3973 required-opps = <&rpmhpd_opp_nom>;
4728 }; 3974 };
4729 }; 3975 };
4730 }; 3976 };
4731 3977
4732 mdss_dp2: displayport 3978 mdss_dp2: displayport-controller@ae9a000 {
4733 compatible = 3979 compatible = "qcom,x1e80100-dp";
4734 reg = <0 0x0a !! 3980 reg = <0 0xae9a000 0 0x200>,
4735 <0 0x0a !! 3981 <0 0xae9a200 0 0x200>,
4736 <0 0x0a !! 3982 <0 0xae9a400 0 0x600>,
4737 <0 0x0a !! 3983 <0 0xae9b000 0 0x400>,
4738 <0 0x0a !! 3984 <0 0xae9b400 0 0x400>;
4739 3985
4740 interrupts-ex 3986 interrupts-extended = <&mdss 14>;
4741 3987
4742 clocks = <&di 3988 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4743 <&di 3989 <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>,
4744 <&di 3990 <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK>,
4745 <&di 3991 <&dispcc DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>,
4746 <&di 3992 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK>;
4747 clock-names = 3993 clock-names = "core_iface",
4748 3994 "core_aux",
4749 3995 "ctrl_link",
4750 3996 "ctrl_link_iface",
4751 3997 "stream_pixel";
4752 3998
4753 assigned-cloc 3999 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
4754 4000 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>;
4755 assigned-cloc 4001 assigned-clock-parents = <&usb_1_ss2_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4756 4002 <&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
4757 4003
4758 operating-poi 4004 operating-points-v2 = <&mdss_dp2_opp_table>;
4759 4005
4760 power-domains 4006 power-domains = <&rpmhpd RPMHPD_MMCX>;
4761 4007
4762 phys = <&usb_ 4008 phys = <&usb_1_ss2_qmpphy QMP_USB43DP_DP_PHY>;
4763 phy-names = " 4009 phy-names = "dp";
4764 4010
4765 #sound-dai-ce 4011 #sound-dai-cells = <0>;
4766 4012
4767 status = "dis 4013 status = "disabled";
4768 4014
4769 ports { 4015 ports {
4770 #addr 4016 #address-cells = <1>;
4771 #size 4017 #size-cells = <0>;
4772 4018
4773 port@ 4019 port@0 {
4774 4020 reg = <0>;
4775 4021 mdss_dp2_in: endpoint {
4776 4022 remote-endpoint = <&mdss_intf6_out>;
4777 4023 };
4778 }; 4024 };
4779 4025
4780 port@ 4026 port@1 {
4781 4027 reg = <1>;
4782 <<
4783 <<
4784 <<
4785 <<
4786 }; 4028 };
4787 }; 4029 };
4788 4030
4789 mdss_dp2_opp_ 4031 mdss_dp2_opp_table: opp-table {
4790 compa 4032 compatible = "operating-points-v2";
4791 4033
4792 opp-1 4034 opp-160000000 {
4793 4035 opp-hz = /bits/ 64 <160000000>;
4794 4036 required-opps = <&rpmhpd_opp_low_svs>;
4795 }; 4037 };
4796 4038
4797 opp-2 4039 opp-270000000 {
4798 4040 opp-hz = /bits/ 64 <270000000>;
4799 4041 required-opps = <&rpmhpd_opp_svs>;
4800 }; 4042 };
4801 4043
4802 opp-5 4044 opp-540000000 {
4803 4045 opp-hz = /bits/ 64 <540000000>;
4804 4046 required-opps = <&rpmhpd_opp_svs_l1>;
4805 }; 4047 };
4806 4048
4807 opp-8 4049 opp-810000000 {
4808 4050 opp-hz = /bits/ 64 <810000000>;
4809 4051 required-opps = <&rpmhpd_opp_nom>;
4810 }; 4052 };
4811 }; 4053 };
4812 }; 4054 };
4813 4055
4814 mdss_dp3: displayport 4056 mdss_dp3: displayport-controller@aea0000 {
4815 compatible = 4057 compatible = "qcom,x1e80100-dp";
4816 reg = <0 0x0a !! 4058 reg = <0 0xaea0000 0 0x200>,
4817 <0 0x0a !! 4059 <0 0xaea0200 0 0x200>,
4818 <0 0x0a !! 4060 <0 0xaea0400 0 0x600>,
4819 <0 0x0a !! 4061 <0 0xaea1000 0 0x400>,
4820 <0 0x0a !! 4062 <0 0xaea1400 0 0x400>;
4821 4063
4822 interrupts-ex 4064 interrupts-extended = <&mdss 15>;
4823 4065
4824 clocks = <&di 4066 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4825 <&di 4067 <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>,
4826 <&di 4068 <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK>,
4827 <&di 4069 <&dispcc DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>,
4828 <&di 4070 <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK>;
4829 clock-names = 4071 clock-names = "core_iface",
4830 4072 "core_aux",
4831 4073 "ctrl_link",
4832 4074 "ctrl_link_iface",
4833 4075 "stream_pixel";
4834 4076
4835 assigned-cloc 4077 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>,
4836 4078 <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>;
4837 assigned-cloc 4079 assigned-clock-parents = <&mdss_dp3_phy 0>,
4838 4080 <&mdss_dp3_phy 1>;
4839 4081
4840 operating-poi 4082 operating-points-v2 = <&mdss_dp3_opp_table>;
4841 4083
4842 power-domains 4084 power-domains = <&rpmhpd RPMHPD_MMCX>;
4843 4085
4844 phys = <&mdss 4086 phys = <&mdss_dp3_phy>;
4845 phy-names = " 4087 phy-names = "dp";
4846 4088
4847 #sound-dai-ce 4089 #sound-dai-cells = <0>;
4848 4090
4849 status = "dis 4091 status = "disabled";
4850 4092
4851 ports { 4093 ports {
4852 #addr 4094 #address-cells = <1>;
4853 #size 4095 #size-cells = <0>;
4854 4096
4855 port@ 4097 port@0 {
4856 4098 reg = <0>;
4857 4099
4858 4100 mdss_dp3_in: endpoint {
4859 4101 remote-endpoint = <&mdss_intf5_out>;
4860 4102 };
4861 }; 4103 };
4862 4104
4863 port@ 4105 port@1 {
4864 4106 reg = <1>;
4865 }; 4107 };
4866 }; 4108 };
4867 4109
4868 mdss_dp3_opp_ 4110 mdss_dp3_opp_table: opp-table {
4869 compa 4111 compatible = "operating-points-v2";
4870 4112
4871 opp-1 4113 opp-160000000 {
4872 4114 opp-hz = /bits/ 64 <160000000>;
4873 4115 required-opps = <&rpmhpd_opp_low_svs>;
4874 }; 4116 };
4875 4117
4876 opp-2 4118 opp-270000000 {
4877 4119 opp-hz = /bits/ 64 <270000000>;
4878 4120 required-opps = <&rpmhpd_opp_svs>;
4879 }; 4121 };
4880 4122
4881 opp-5 4123 opp-540000000 {
4882 4124 opp-hz = /bits/ 64 <540000000>;
4883 4125 required-opps = <&rpmhpd_opp_svs_l1>;
4884 }; 4126 };
4885 4127
4886 opp-8 4128 opp-810000000 {
4887 4129 opp-hz = /bits/ 64 <810000000>;
4888 4130 required-opps = <&rpmhpd_opp_nom>;
4889 }; 4131 };
4890 }; 4132 };
4891 }; 4133 };
4892 4134
4893 }; 4135 };
4894 4136
4895 mdss_dp2_phy: phy@aec2a00 { 4137 mdss_dp2_phy: phy@aec2a00 {
4896 compatible = "qcom,x1 4138 compatible = "qcom,x1e80100-dp-phy";
4897 reg = <0 0x0aec2a00 0 4139 reg = <0 0x0aec2a00 0 0x19c>,
4898 <0 0x0aec2200 0 4140 <0 0x0aec2200 0 0xec>,
4899 <0 0x0aec2600 0 4141 <0 0x0aec2600 0 0xec>,
4900 <0 0x0aec2000 0 4142 <0 0x0aec2000 0 0x1c8>;
4901 4143
4902 clocks = <&dispcc DIS 4144 clocks = <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>,
4903 <&dispcc DIS 4145 <&dispcc DISP_CC_MDSS_AHB_CLK>;
4904 clock-names = "aux", 4146 clock-names = "aux",
4905 "cfg_ah 4147 "cfg_ahb";
4906 4148
4907 power-domains = <&rpm 4149 power-domains = <&rpmhpd RPMHPD_MX>;
4908 4150
4909 #clock-cells = <1>; 4151 #clock-cells = <1>;
4910 #phy-cells = <0>; 4152 #phy-cells = <0>;
4911 4153
4912 status = "disabled"; 4154 status = "disabled";
4913 }; 4155 };
4914 4156
4915 mdss_dp3_phy: phy@aec5a00 { 4157 mdss_dp3_phy: phy@aec5a00 {
4916 compatible = "qcom,x1 4158 compatible = "qcom,x1e80100-dp-phy";
4917 reg = <0 0x0aec5a00 0 4159 reg = <0 0x0aec5a00 0 0x19c>,
4918 <0 0x0aec5200 0 4160 <0 0x0aec5200 0 0xec>,
4919 <0 0x0aec5600 0 4161 <0 0x0aec5600 0 0xec>,
4920 <0 0x0aec5000 0 4162 <0 0x0aec5000 0 0x1c8>;
4921 4163
4922 clocks = <&dispcc DIS 4164 clocks = <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>,
4923 <&dispcc DIS 4165 <&dispcc DISP_CC_MDSS_AHB_CLK>;
4924 clock-names = "aux", 4166 clock-names = "aux",
4925 "cfg_ah 4167 "cfg_ahb";
4926 4168
4927 power-domains = <&rpm 4169 power-domains = <&rpmhpd RPMHPD_MX>;
4928 4170
4929 #clock-cells = <1>; 4171 #clock-cells = <1>;
4930 #phy-cells = <0>; 4172 #phy-cells = <0>;
4931 4173
4932 status = "disabled"; 4174 status = "disabled";
4933 }; 4175 };
4934 4176
4935 dispcc: clock-controller@af00 4177 dispcc: clock-controller@af00000 {
4936 compatible = "qcom,x1 4178 compatible = "qcom,x1e80100-dispcc";
4937 reg = <0 0x0af00000 0 4179 reg = <0 0x0af00000 0 0x20000>;
4938 clocks = <&bi_tcxo_di 4180 clocks = <&bi_tcxo_div2>,
4939 <&bi_tcxo_ao 4181 <&bi_tcxo_ao_div2>,
4940 <&gcc GCC_DI 4182 <&gcc GCC_DISP_AHB_CLK>,
4941 <&sleep_clk> 4183 <&sleep_clk>,
4942 <0>, /* dsi0 4184 <0>, /* dsi0 */
4943 <0>, 4185 <0>,
4944 <0>, /* dsi1 4186 <0>, /* dsi1 */
4945 <0>, 4187 <0>,
4946 <&usb_1_ss0_ 4188 <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp0 */
4947 <&usb_1_ss0_ 4189 <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
4948 <&usb_1_ss1_ 4190 <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp1 */
4949 <&usb_1_ss1_ 4191 <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
4950 <&usb_1_ss2_ 4192 <&usb_1_ss2_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp2 */
4951 <&usb_1_ss2_ 4193 <&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
4952 <&mdss_dp3_p 4194 <&mdss_dp3_phy 0>, /* dp3 */
4953 <&mdss_dp3_p 4195 <&mdss_dp3_phy 1>;
4954 power-domains = <&rpm 4196 power-domains = <&rpmhpd RPMHPD_MMCX>;
4955 required-opps = <&rpm 4197 required-opps = <&rpmhpd_opp_low_svs>;
4956 #clock-cells = <1>; 4198 #clock-cells = <1>;
4957 #reset-cells = <1>; 4199 #reset-cells = <1>;
4958 #power-domain-cells = 4200 #power-domain-cells = <1>;
4959 }; 4201 };
4960 4202
4961 pdc: interrupt-controller@b22 4203 pdc: interrupt-controller@b220000 {
4962 compatible = "qcom,x1 4204 compatible = "qcom,x1e80100-pdc", "qcom,pdc";
4963 reg = <0 0x0b220000 0 4205 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
4964 4206
4965 qcom,pdc-ranges = <0 4207 qcom,pdc-ranges = <0 480 42>, <42 251 5>,
4966 <47 4208 <47 522 52>, <99 609 32>,
4967 <13 4209 <131 717 12>, <143 816 19>;
4968 #interrupt-cells = <2 4210 #interrupt-cells = <2>;
4969 interrupt-parent = <& 4211 interrupt-parent = <&intc>;
4970 interrupt-controller; 4212 interrupt-controller;
4971 }; 4213 };
4972 4214
4973 aoss_qmp: power-management@c3 4215 aoss_qmp: power-management@c300000 {
4974 compatible = "qcom,x1 4216 compatible = "qcom,x1e80100-aoss-qmp", "qcom,aoss-qmp";
4975 reg = <0 0x0c300000 0 4217 reg = <0 0x0c300000 0 0x400>;
4976 interrupt-parent = <& 4218 interrupt-parent = <&ipcc>;
4977 interrupts-extended = 4219 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
4978 4220 IRQ_TYPE_EDGE_RISING>;
4979 mboxes = <&ipcc IPCC_ 4221 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
4980 4222
4981 #clock-cells = <0>; 4223 #clock-cells = <0>;
4982 }; 4224 };
4983 4225
4984 sram@c3f0000 { <<
4985 compatible = "qcom,rp <<
4986 reg = <0 0x0c3f0000 0 <<
4987 }; <<
4988 <<
4989 spmi: arbiter@c400000 { 4226 spmi: arbiter@c400000 {
4990 compatible = "qcom,x1 4227 compatible = "qcom,x1e80100-spmi-pmic-arb";
4991 reg = <0 0x0c400000 0 4228 reg = <0 0x0c400000 0 0x3000>,
4992 <0 0x0c500000 0 4229 <0 0x0c500000 0 0x400000>,
4993 <0 0x0c440000 0 4230 <0 0x0c440000 0 0x80000>;
4994 reg-names = "core", " 4231 reg-names = "core", "chnls", "obsrvr";
4995 4232
4996 qcom,ee = <0>; 4233 qcom,ee = <0>;
4997 qcom,channel = <0>; 4234 qcom,channel = <0>;
4998 4235
4999 #address-cells = <2>; 4236 #address-cells = <2>;
5000 #size-cells = <2>; 4237 #size-cells = <2>;
5001 ranges; 4238 ranges;
5002 4239
5003 spmi_bus0: spmi@c42d0 4240 spmi_bus0: spmi@c42d000 {
5004 reg = <0 0x0c 4241 reg = <0 0x0c42d000 0 0x4000>,
5005 <0 0x0c 4242 <0 0x0c4c0000 0 0x10000>;
5006 reg-names = " 4243 reg-names = "cnfg", "intr";
5007 4244
5008 interrupt-nam 4245 interrupt-names = "periph_irq";
5009 interrupts-ex 4246 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
5010 interrupt-con 4247 interrupt-controller;
5011 #interrupt-ce 4248 #interrupt-cells = <4>;
5012 4249
5013 #address-cell 4250 #address-cells = <2>;
5014 #size-cells = 4251 #size-cells = <0>;
5015 }; 4252 };
5016 4253
5017 spmi_bus1: spmi@c4320 4254 spmi_bus1: spmi@c432000 {
5018 reg = <0 0x0c 4255 reg = <0 0x0c432000 0 0x4000>,
5019 <0 0x0c 4256 <0 0x0c4d0000 0 0x10000>;
5020 reg-names = " 4257 reg-names = "cnfg", "intr";
5021 4258
5022 interrupt-nam 4259 interrupt-names = "periph_irq";
5023 interrupts-ex 4260 interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>;
5024 interrupt-con 4261 interrupt-controller;
5025 #interrupt-ce 4262 #interrupt-cells = <4>;
5026 4263
5027 #address-cell 4264 #address-cells = <2>;
5028 #size-cells = 4265 #size-cells = <0>;
5029 }; 4266 };
5030 }; 4267 };
5031 4268
5032 tlmm: pinctrl@f100000 { 4269 tlmm: pinctrl@f100000 {
5033 compatible = "qcom,x1 4270 compatible = "qcom,x1e80100-tlmm";
5034 reg = <0 0x0f100000 0 4271 reg = <0 0x0f100000 0 0xf00000>;
5035 4272
5036 interrupts = <GIC_SPI 4273 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
5037 4274
5038 gpio-controller; 4275 gpio-controller;
5039 #gpio-cells = <2>; 4276 #gpio-cells = <2>;
5040 4277
5041 interrupt-controller; 4278 interrupt-controller;
5042 #interrupt-cells = <2 4279 #interrupt-cells = <2>;
5043 4280
5044 gpio-ranges = <&tlmm 4281 gpio-ranges = <&tlmm 0 0 239>;
5045 wakeup-parent = <&pdc 4282 wakeup-parent = <&pdc>;
5046 4283
5047 qup_i2c0_data_clk: qu 4284 qup_i2c0_data_clk: qup-i2c0-data-clk-state {
5048 /* SDA, SCL * 4285 /* SDA, SCL */
5049 pins = "gpio0 4286 pins = "gpio0", "gpio1";
5050 function = "q 4287 function = "qup0_se0";
5051 drive-strengt 4288 drive-strength = <2>;
5052 bias-pull-up 4289 bias-pull-up = <2200>;
5053 }; 4290 };
5054 4291
5055 qup_i2c1_data_clk: qu 4292 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
5056 /* SDA, SCL * 4293 /* SDA, SCL */
5057 pins = "gpio4 4294 pins = "gpio4", "gpio5";
5058 function = "q 4295 function = "qup0_se1";
5059 drive-strengt 4296 drive-strength = <2>;
5060 bias-pull-up 4297 bias-pull-up = <2200>;
5061 }; 4298 };
5062 4299
5063 qup_i2c2_data_clk: qu 4300 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
5064 /* SDA, SCL * 4301 /* SDA, SCL */
5065 pins = "gpio8 4302 pins = "gpio8", "gpio9";
5066 function = "q 4303 function = "qup0_se2";
5067 drive-strengt 4304 drive-strength = <2>;
5068 bias-pull-up 4305 bias-pull-up = <2200>;
5069 }; 4306 };
5070 4307
5071 qup_i2c3_data_clk: qu 4308 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
5072 /* SDA, SCL * 4309 /* SDA, SCL */
5073 pins = "gpio1 4310 pins = "gpio12", "gpio13";
5074 function = "q 4311 function = "qup0_se3";
5075 drive-strengt 4312 drive-strength = <2>;
5076 bias-pull-up 4313 bias-pull-up = <2200>;
5077 }; 4314 };
5078 4315
5079 qup_i2c4_data_clk: qu 4316 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
5080 /* SDA, SCL * 4317 /* SDA, SCL */
5081 pins = "gpio1 4318 pins = "gpio16", "gpio17";
5082 function = "q 4319 function = "qup0_se4";
5083 drive-strengt 4320 drive-strength = <2>;
5084 bias-pull-up 4321 bias-pull-up = <2200>;
5085 }; 4322 };
5086 4323
5087 qup_i2c5_data_clk: qu 4324 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
5088 /* SDA, SCL * 4325 /* SDA, SCL */
5089 pins = "gpio2 4326 pins = "gpio20", "gpio21";
5090 function = "q 4327 function = "qup0_se5";
5091 drive-strengt 4328 drive-strength = <2>;
5092 bias-pull-up 4329 bias-pull-up = <2200>;
5093 }; 4330 };
5094 4331
5095 qup_i2c6_data_clk: qu 4332 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
5096 /* SDA, SCL * 4333 /* SDA, SCL */
5097 pins = "gpio2 4334 pins = "gpio24", "gpio25";
5098 function = "q 4335 function = "qup0_se6";
5099 drive-strengt 4336 drive-strength = <2>;
5100 bias-pull-up 4337 bias-pull-up = <2200>;
5101 }; 4338 };
5102 4339
5103 qup_i2c7_data_clk: qu 4340 qup_i2c7_data_clk: qup-i2c7-data-clk-state {
5104 /* SDA, SCL * 4341 /* SDA, SCL */
5105 pins = "gpio1 4342 pins = "gpio14", "gpio15";
5106 function = "q 4343 function = "qup0_se7";
5107 drive-strengt 4344 drive-strength = <2>;
5108 bias-pull-up 4345 bias-pull-up = <2200>;
5109 }; 4346 };
5110 4347
5111 qup_i2c8_data_clk: qu 4348 qup_i2c8_data_clk: qup-i2c8-data-clk-state {
5112 /* SDA, SCL * 4349 /* SDA, SCL */
5113 pins = "gpio3 4350 pins = "gpio32", "gpio33";
5114 function = "q 4351 function = "qup1_se0";
5115 drive-strengt 4352 drive-strength = <2>;
5116 bias-pull-up 4353 bias-pull-up = <2200>;
5117 }; 4354 };
5118 4355
5119 qup_i2c9_data_clk: qu 4356 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
5120 /* SDA, SCL * 4357 /* SDA, SCL */
5121 pins = "gpio3 4358 pins = "gpio36", "gpio37";
5122 function = "q 4359 function = "qup1_se1";
5123 drive-strengt 4360 drive-strength = <2>;
5124 bias-pull-up 4361 bias-pull-up = <2200>;
5125 }; 4362 };
5126 4363
5127 qup_i2c10_data_clk: q 4364 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
5128 /* SDA, SCL * 4365 /* SDA, SCL */
5129 pins = "gpio4 4366 pins = "gpio40", "gpio41";
5130 function = "q 4367 function = "qup1_se2";
5131 drive-strengt 4368 drive-strength = <2>;
5132 bias-pull-up 4369 bias-pull-up = <2200>;
5133 }; 4370 };
5134 4371
5135 qup_i2c11_data_clk: q 4372 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
5136 /* SDA, SCL * 4373 /* SDA, SCL */
5137 pins = "gpio4 4374 pins = "gpio44", "gpio45";
5138 function = "q 4375 function = "qup1_se3";
5139 drive-strengt 4376 drive-strength = <2>;
5140 bias-pull-up 4377 bias-pull-up = <2200>;
5141 }; 4378 };
5142 4379
5143 qup_i2c12_data_clk: q 4380 qup_i2c12_data_clk: qup-i2c12-data-clk-state {
5144 /* SDA, SCL * 4381 /* SDA, SCL */
5145 pins = "gpio4 4382 pins = "gpio48", "gpio49";
5146 function = "q 4383 function = "qup1_se4";
5147 drive-strengt 4384 drive-strength = <2>;
5148 bias-pull-up 4385 bias-pull-up = <2200>;
5149 }; 4386 };
5150 4387
5151 qup_i2c13_data_clk: q 4388 qup_i2c13_data_clk: qup-i2c13-data-clk-state {
5152 /* SDA, SCL * 4389 /* SDA, SCL */
5153 pins = "gpio5 4390 pins = "gpio52", "gpio53";
5154 function = "q 4391 function = "qup1_se5";
5155 drive-strengt 4392 drive-strength = <2>;
5156 bias-pull-up 4393 bias-pull-up = <2200>;
5157 }; 4394 };
5158 4395
5159 qup_i2c14_data_clk: q 4396 qup_i2c14_data_clk: qup-i2c14-data-clk-state {
5160 /* SDA, SCL * 4397 /* SDA, SCL */
5161 pins = "gpio5 4398 pins = "gpio56", "gpio57";
5162 function = "q 4399 function = "qup1_se6";
5163 drive-strengt 4400 drive-strength = <2>;
5164 bias-pull-up 4401 bias-pull-up = <2200>;
5165 }; 4402 };
5166 4403
5167 qup_i2c15_data_clk: q 4404 qup_i2c15_data_clk: qup-i2c15-data-clk-state {
5168 /* SDA, SCL * 4405 /* SDA, SCL */
5169 pins = "gpio5 4406 pins = "gpio54", "gpio55";
5170 function = "q 4407 function = "qup1_se7";
5171 drive-strengt 4408 drive-strength = <2>;
5172 bias-pull-up 4409 bias-pull-up = <2200>;
5173 }; 4410 };
5174 4411
5175 qup_i2c16_data_clk: q 4412 qup_i2c16_data_clk: qup-i2c16-data-clk-state {
5176 /* SDA, SCL * 4413 /* SDA, SCL */
5177 pins = "gpio6 4414 pins = "gpio64", "gpio65";
5178 function = "q 4415 function = "qup2_se0";
5179 drive-strengt 4416 drive-strength = <2>;
5180 bias-pull-up 4417 bias-pull-up = <2200>;
5181 }; 4418 };
5182 4419
5183 qup_i2c17_data_clk: q 4420 qup_i2c17_data_clk: qup-i2c17-data-clk-state {
5184 /* SDA, SCL * 4421 /* SDA, SCL */
5185 pins = "gpio6 4422 pins = "gpio68", "gpio69";
5186 function = "q 4423 function = "qup2_se1";
5187 drive-strengt 4424 drive-strength = <2>;
5188 bias-pull-up 4425 bias-pull-up = <2200>;
5189 }; 4426 };
5190 4427
5191 qup_i2c18_data_clk: q 4428 qup_i2c18_data_clk: qup-i2c18-data-clk-state {
5192 /* SDA, SCL * 4429 /* SDA, SCL */
5193 pins = "gpio7 4430 pins = "gpio72", "gpio73";
5194 function = "q 4431 function = "qup2_se2";
5195 drive-strengt 4432 drive-strength = <2>;
5196 bias-pull-up 4433 bias-pull-up = <2200>;
5197 }; 4434 };
5198 4435
5199 qup_i2c19_data_clk: q 4436 qup_i2c19_data_clk: qup-i2c19-data-clk-state {
5200 /* SDA, SCL * 4437 /* SDA, SCL */
5201 pins = "gpio7 4438 pins = "gpio76", "gpio77";
5202 function = "q 4439 function = "qup2_se3";
5203 drive-strengt 4440 drive-strength = <2>;
5204 bias-pull-up 4441 bias-pull-up = <2200>;
5205 }; 4442 };
5206 4443
5207 qup_i2c20_data_clk: q 4444 qup_i2c20_data_clk: qup-i2c20-data-clk-state {
5208 /* SDA, SCL * 4445 /* SDA, SCL */
5209 pins = "gpio8 4446 pins = "gpio80", "gpio81";
5210 function = "q 4447 function = "qup2_se4";
5211 drive-strengt 4448 drive-strength = <2>;
5212 bias-pull-up 4449 bias-pull-up = <2200>;
5213 }; 4450 };
5214 4451
5215 qup_i2c21_data_clk: q 4452 qup_i2c21_data_clk: qup-i2c21-data-clk-state {
5216 /* SDA, SCL * 4453 /* SDA, SCL */
5217 pins = "gpio8 4454 pins = "gpio84", "gpio85";
5218 function = "q 4455 function = "qup2_se5";
5219 drive-strengt 4456 drive-strength = <2>;
5220 bias-pull-up 4457 bias-pull-up = <2200>;
5221 }; 4458 };
5222 4459
5223 qup_i2c22_data_clk: q 4460 qup_i2c22_data_clk: qup-i2c22-data-clk-state {
5224 /* SDA, SCL * 4461 /* SDA, SCL */
5225 pins = "gpio8 4462 pins = "gpio88", "gpio89";
5226 function = "q 4463 function = "qup2_se6";
5227 drive-strengt 4464 drive-strength = <2>;
5228 bias-pull-up 4465 bias-pull-up = <2200>;
5229 }; 4466 };
5230 4467
5231 qup_i2c23_data_clk: q 4468 qup_i2c23_data_clk: qup-i2c23-data-clk-state {
5232 /* SDA, SCL * 4469 /* SDA, SCL */
5233 pins = "gpio8 4470 pins = "gpio86", "gpio87";
5234 function = "q 4471 function = "qup2_se7";
5235 drive-strengt 4472 drive-strength = <2>;
5236 bias-pull-up 4473 bias-pull-up = <2200>;
5237 }; 4474 };
5238 4475
5239 qup_spi0_cs: qup-spi0 4476 qup_spi0_cs: qup-spi0-cs-state {
5240 pins = "gpio3 4477 pins = "gpio3";
5241 function = "q 4478 function = "qup0_se0";
5242 drive-strengt 4479 drive-strength = <6>;
5243 bias-disable; 4480 bias-disable;
5244 }; 4481 };
5245 4482
5246 qup_spi0_data_clk: qu 4483 qup_spi0_data_clk: qup-spi0-data-clk-state {
5247 /* MISO, MOSI 4484 /* MISO, MOSI, CLK */
5248 pins = "gpio0 4485 pins = "gpio0", "gpio1", "gpio2";
5249 function = "q 4486 function = "qup0_se0";
5250 drive-strengt 4487 drive-strength = <6>;
5251 bias-disable; 4488 bias-disable;
5252 }; 4489 };
5253 4490
5254 qup_spi1_cs: qup-spi1 4491 qup_spi1_cs: qup-spi1-cs-state {
5255 pins = "gpio7 4492 pins = "gpio7";
5256 function = "q 4493 function = "qup0_se1";
5257 drive-strengt 4494 drive-strength = <6>;
5258 bias-disable; 4495 bias-disable;
5259 }; 4496 };
5260 4497
5261 qup_spi1_data_clk: qu 4498 qup_spi1_data_clk: qup-spi1-data-clk-state {
5262 /* MISO, MOSI 4499 /* MISO, MOSI, CLK */
5263 pins = "gpio4 4500 pins = "gpio4", "gpio5", "gpio6";
5264 function = "q 4501 function = "qup0_se1";
5265 drive-strengt 4502 drive-strength = <6>;
5266 bias-disable; 4503 bias-disable;
5267 }; 4504 };
5268 4505
5269 qup_spi2_cs: qup-spi2 4506 qup_spi2_cs: qup-spi2-cs-state {
5270 pins = "gpio1 4507 pins = "gpio11";
5271 function = "q 4508 function = "qup0_se2";
5272 drive-strengt 4509 drive-strength = <6>;
5273 bias-disable; 4510 bias-disable;
5274 }; 4511 };
5275 4512
5276 qup_spi2_data_clk: qu 4513 qup_spi2_data_clk: qup-spi2-data-clk-state {
5277 /* MISO, MOSI 4514 /* MISO, MOSI, CLK */
5278 pins = "gpio8 4515 pins = "gpio8", "gpio9", "gpio10";
5279 function = "q 4516 function = "qup0_se2";
5280 drive-strengt 4517 drive-strength = <6>;
5281 bias-disable; 4518 bias-disable;
5282 }; 4519 };
5283 4520
5284 qup_spi3_cs: qup-spi3 4521 qup_spi3_cs: qup-spi3-cs-state {
5285 pins = "gpio1 4522 pins = "gpio15";
5286 function = "q 4523 function = "qup0_se3";
5287 drive-strengt 4524 drive-strength = <6>;
5288 bias-disable; 4525 bias-disable;
5289 }; 4526 };
5290 4527
5291 qup_spi3_data_clk: qu 4528 qup_spi3_data_clk: qup-spi3-data-clk-state {
5292 /* MISO, MOSI 4529 /* MISO, MOSI, CLK */
5293 pins = "gpio1 4530 pins = "gpio12", "gpio13", "gpio14";
5294 function = "q 4531 function = "qup0_se3";
5295 drive-strengt 4532 drive-strength = <6>;
5296 bias-disable; 4533 bias-disable;
5297 }; 4534 };
5298 4535
5299 qup_spi4_cs: qup-spi4 4536 qup_spi4_cs: qup-spi4-cs-state {
5300 pins = "gpio1 4537 pins = "gpio19";
5301 function = "q 4538 function = "qup0_se4";
5302 drive-strengt 4539 drive-strength = <6>;
5303 bias-disable; 4540 bias-disable;
5304 }; 4541 };
5305 4542
5306 qup_spi4_data_clk: qu 4543 qup_spi4_data_clk: qup-spi4-data-clk-state {
5307 /* MISO, MOSI 4544 /* MISO, MOSI, CLK */
5308 pins = "gpio1 4545 pins = "gpio16", "gpio17", "gpio18";
5309 function = "q 4546 function = "qup0_se4";
5310 drive-strengt 4547 drive-strength = <6>;
5311 bias-disable; 4548 bias-disable;
5312 }; 4549 };
5313 4550
5314 qup_spi5_cs: qup-spi5 4551 qup_spi5_cs: qup-spi5-cs-state {
5315 pins = "gpio2 4552 pins = "gpio23";
5316 function = "q 4553 function = "qup0_se5";
5317 drive-strengt 4554 drive-strength = <6>;
5318 bias-disable; 4555 bias-disable;
5319 }; 4556 };
5320 4557
5321 qup_spi5_data_clk: qu 4558 qup_spi5_data_clk: qup-spi5-data-clk-state {
5322 /* MISO, MOSI 4559 /* MISO, MOSI, CLK */
5323 pins = "gpio2 4560 pins = "gpio20", "gpio21", "gpio22";
5324 function = "q 4561 function = "qup0_se5";
5325 drive-strengt 4562 drive-strength = <6>;
5326 bias-disable; 4563 bias-disable;
5327 }; 4564 };
5328 4565
5329 qup_spi6_cs: qup-spi6 4566 qup_spi6_cs: qup-spi6-cs-state {
5330 pins = "gpio2 4567 pins = "gpio27";
5331 function = "q 4568 function = "qup0_se6";
5332 drive-strengt 4569 drive-strength = <6>;
5333 bias-disable; 4570 bias-disable;
5334 }; 4571 };
5335 4572
5336 qup_spi6_data_clk: qu 4573 qup_spi6_data_clk: qup-spi6-data-clk-state {
5337 /* MISO, MOSI 4574 /* MISO, MOSI, CLK */
5338 pins = "gpio2 4575 pins = "gpio24", "gpio25", "gpio26";
5339 function = "q 4576 function = "qup0_se6";
5340 drive-strengt 4577 drive-strength = <6>;
5341 bias-disable; 4578 bias-disable;
5342 }; 4579 };
5343 4580
5344 qup_spi7_cs: qup-spi7 4581 qup_spi7_cs: qup-spi7-cs-state {
5345 pins = "gpio1 4582 pins = "gpio13";
5346 function = "q 4583 function = "qup0_se7";
5347 drive-strengt 4584 drive-strength = <6>;
5348 bias-disable; 4585 bias-disable;
5349 }; 4586 };
5350 4587
5351 qup_spi7_data_clk: qu 4588 qup_spi7_data_clk: qup-spi7-data-clk-state {
5352 /* MISO, MOSI 4589 /* MISO, MOSI, CLK */
5353 pins = "gpio1 4590 pins = "gpio14", "gpio15", "gpio12";
5354 function = "q 4591 function = "qup0_se7";
5355 drive-strengt 4592 drive-strength = <6>;
5356 bias-disable; 4593 bias-disable;
5357 }; 4594 };
5358 4595
5359 qup_spi8_cs: qup-spi8 4596 qup_spi8_cs: qup-spi8-cs-state {
5360 pins = "gpio3 4597 pins = "gpio35";
5361 function = "q 4598 function = "qup1_se0";
5362 drive-strengt 4599 drive-strength = <6>;
5363 bias-disable; 4600 bias-disable;
5364 }; 4601 };
5365 4602
5366 qup_spi8_data_clk: qu 4603 qup_spi8_data_clk: qup-spi8-data-clk-state {
5367 /* MISO, MOSI 4604 /* MISO, MOSI, CLK */
5368 pins = "gpio3 4605 pins = "gpio32", "gpio33", "gpio34";
5369 function = "q 4606 function = "qup1_se0";
5370 drive-strengt 4607 drive-strength = <6>;
5371 bias-disable; 4608 bias-disable;
5372 }; 4609 };
5373 4610
5374 qup_spi9_cs: qup-spi9 4611 qup_spi9_cs: qup-spi9-cs-state {
5375 pins = "gpio3 4612 pins = "gpio39";
5376 function = "q 4613 function = "qup1_se1";
5377 drive-strengt 4614 drive-strength = <6>;
5378 bias-disable; 4615 bias-disable;
5379 }; 4616 };
5380 4617
5381 qup_spi9_data_clk: qu 4618 qup_spi9_data_clk: qup-spi9-data-clk-state {
5382 /* MISO, MOSI 4619 /* MISO, MOSI, CLK */
5383 pins = "gpio3 4620 pins = "gpio36", "gpio37", "gpio38";
5384 function = "q 4621 function = "qup1_se1";
5385 drive-strengt 4622 drive-strength = <6>;
5386 bias-disable; 4623 bias-disable;
5387 }; 4624 };
5388 4625
5389 qup_spi10_cs: qup-spi 4626 qup_spi10_cs: qup-spi10-cs-state {
5390 pins = "gpio4 4627 pins = "gpio43";
5391 function = "q 4628 function = "qup1_se2";
5392 drive-strengt 4629 drive-strength = <6>;
5393 bias-disable; 4630 bias-disable;
5394 }; 4631 };
5395 4632
5396 qup_spi10_data_clk: q 4633 qup_spi10_data_clk: qup-spi10-data-clk-state {
5397 /* MISO, MOSI 4634 /* MISO, MOSI, CLK */
5398 pins = "gpio4 4635 pins = "gpio40", "gpio41", "gpio42";
5399 function = "q 4636 function = "qup1_se2";
5400 drive-strengt 4637 drive-strength = <6>;
5401 bias-disable; 4638 bias-disable;
5402 }; 4639 };
5403 4640
5404 qup_spi11_cs: qup-spi 4641 qup_spi11_cs: qup-spi11-cs-state {
5405 pins = "gpio4 4642 pins = "gpio47";
5406 function = "q 4643 function = "qup1_se3";
5407 drive-strengt 4644 drive-strength = <6>;
5408 bias-disable; 4645 bias-disable;
5409 }; 4646 };
5410 4647
5411 qup_spi11_data_clk: q 4648 qup_spi11_data_clk: qup-spi11-data-clk-state {
5412 /* MISO, MOSI 4649 /* MISO, MOSI, CLK */
5413 pins = "gpio4 4650 pins = "gpio44", "gpio45", "gpio46";
5414 function = "q 4651 function = "qup1_se3";
5415 drive-strengt 4652 drive-strength = <6>;
5416 bias-disable; 4653 bias-disable;
5417 }; 4654 };
5418 4655
5419 qup_spi12_cs: qup-spi 4656 qup_spi12_cs: qup-spi12-cs-state {
5420 pins = "gpio5 4657 pins = "gpio51";
5421 function = "q 4658 function = "qup1_se4";
5422 drive-strengt 4659 drive-strength = <6>;
5423 bias-disable; 4660 bias-disable;
5424 }; 4661 };
5425 4662
5426 qup_spi12_data_clk: q 4663 qup_spi12_data_clk: qup-spi12-data-clk-state {
5427 /* MISO, MOSI 4664 /* MISO, MOSI, CLK */
5428 pins = "gpio4 4665 pins = "gpio48", "gpio49", "gpio50";
5429 function = "q 4666 function = "qup1_se4";
5430 drive-strengt 4667 drive-strength = <6>;
5431 bias-disable; 4668 bias-disable;
5432 }; 4669 };
5433 4670
5434 qup_spi13_cs: qup-spi 4671 qup_spi13_cs: qup-spi13-cs-state {
5435 pins = "gpio5 4672 pins = "gpio55";
5436 function = "q 4673 function = "qup1_se5";
5437 drive-strengt 4674 drive-strength = <6>;
5438 bias-disable; 4675 bias-disable;
5439 }; 4676 };
5440 4677
5441 qup_spi13_data_clk: q 4678 qup_spi13_data_clk: qup-spi13-data-clk-state {
5442 /* MISO, MOSI 4679 /* MISO, MOSI, CLK */
5443 pins = "gpio5 4680 pins = "gpio52", "gpio53", "gpio54";
5444 function = "q 4681 function = "qup1_se5";
5445 drive-strengt 4682 drive-strength = <6>;
5446 bias-disable; 4683 bias-disable;
5447 }; 4684 };
5448 4685
5449 qup_spi14_cs: qup-spi 4686 qup_spi14_cs: qup-spi14-cs-state {
5450 pins = "gpio5 4687 pins = "gpio59";
5451 function = "q 4688 function = "qup1_se6";
5452 drive-strengt 4689 drive-strength = <6>;
5453 bias-disable; 4690 bias-disable;
5454 }; 4691 };
5455 4692
5456 qup_spi14_data_clk: q 4693 qup_spi14_data_clk: qup-spi14-data-clk-state {
5457 /* MISO, MOSI 4694 /* MISO, MOSI, CLK */
5458 pins = "gpio5 4695 pins = "gpio56", "gpio57", "gpio58";
5459 function = "q 4696 function = "qup1_se6";
5460 drive-strengt 4697 drive-strength = <6>;
5461 bias-disable; 4698 bias-disable;
5462 }; 4699 };
5463 4700
5464 qup_spi15_cs: qup-spi 4701 qup_spi15_cs: qup-spi15-cs-state {
5465 pins = "gpio5 4702 pins = "gpio53";
5466 function = "q 4703 function = "qup1_se7";
5467 drive-strengt 4704 drive-strength = <6>;
5468 bias-disable; 4705 bias-disable;
5469 }; 4706 };
5470 4707
5471 qup_spi15_data_clk: q 4708 qup_spi15_data_clk: qup-spi15-data-clk-state {
5472 /* MISO, MOSI 4709 /* MISO, MOSI, CLK */
5473 pins = "gpio5 4710 pins = "gpio54", "gpio55", "gpio52";
5474 function = "q 4711 function = "qup1_se7";
5475 drive-strengt 4712 drive-strength = <6>;
5476 bias-disable; 4713 bias-disable;
5477 }; 4714 };
5478 4715
5479 qup_spi16_cs: qup-spi 4716 qup_spi16_cs: qup-spi16-cs-state {
5480 pins = "gpio6 4717 pins = "gpio67";
5481 function = "q 4718 function = "qup2_se0";
5482 drive-strengt 4719 drive-strength = <6>;
5483 bias-disable; 4720 bias-disable;
5484 }; 4721 };
5485 4722
5486 qup_spi16_data_clk: q 4723 qup_spi16_data_clk: qup-spi16-data-clk-state {
5487 /* MISO, MOSI 4724 /* MISO, MOSI, CLK */
5488 pins = "gpio6 4725 pins = "gpio64", "gpio65", "gpio66";
5489 function = "q 4726 function = "qup2_se0";
5490 drive-strengt 4727 drive-strength = <6>;
5491 bias-disable; 4728 bias-disable;
5492 }; 4729 };
5493 4730
5494 qup_spi17_cs: qup-spi 4731 qup_spi17_cs: qup-spi17-cs-state {
5495 pins = "gpio7 4732 pins = "gpio71";
5496 function = "q 4733 function = "qup2_se1";
5497 drive-strengt 4734 drive-strength = <6>;
5498 bias-disable; 4735 bias-disable;
5499 }; 4736 };
5500 4737
5501 qup_spi17_data_clk: q 4738 qup_spi17_data_clk: qup-spi17-data-clk-state {
5502 /* MISO, MOSI 4739 /* MISO, MOSI, CLK */
5503 pins = "gpio6 4740 pins = "gpio68", "gpio69", "gpio70";
5504 function = "q 4741 function = "qup2_se1";
5505 drive-strengt 4742 drive-strength = <6>;
5506 bias-disable; 4743 bias-disable;
5507 }; 4744 };
5508 4745
5509 qup_spi18_cs: qup-spi 4746 qup_spi18_cs: qup-spi18-cs-state {
5510 pins = "gpio7 4747 pins = "gpio75";
5511 function = "q 4748 function = "qup2_se2";
5512 drive-strengt 4749 drive-strength = <6>;
5513 bias-disable; 4750 bias-disable;
5514 }; 4751 };
5515 4752
5516 qup_spi18_data_clk: q 4753 qup_spi18_data_clk: qup-spi18-data-clk-state {
5517 /* MISO, MOSI 4754 /* MISO, MOSI, CLK */
5518 pins = "gpio7 4755 pins = "gpio72", "gpio73", "gpio74";
5519 function = "q 4756 function = "qup2_se2";
5520 drive-strengt 4757 drive-strength = <6>;
5521 bias-disable; 4758 bias-disable;
5522 }; 4759 };
5523 4760
5524 qup_spi19_cs: qup-spi 4761 qup_spi19_cs: qup-spi19-cs-state {
5525 pins = "gpio7 4762 pins = "gpio79";
5526 function = "q 4763 function = "qup2_se3";
5527 drive-strengt 4764 drive-strength = <6>;
5528 bias-disable; 4765 bias-disable;
5529 }; 4766 };
5530 4767
5531 qup_spi19_data_clk: q 4768 qup_spi19_data_clk: qup-spi19-data-clk-state {
5532 /* MISO, MOSI 4769 /* MISO, MOSI, CLK */
5533 pins = "gpio7 4770 pins = "gpio76", "gpio77", "gpio78";
5534 function = "q 4771 function = "qup2_se3";
5535 drive-strengt 4772 drive-strength = <6>;
5536 bias-disable; 4773 bias-disable;
5537 }; 4774 };
5538 4775
5539 qup_spi20_cs: qup-spi 4776 qup_spi20_cs: qup-spi20-cs-state {
5540 pins = "gpio8 4777 pins = "gpio83";
5541 function = "q 4778 function = "qup2_se4";
5542 drive-strengt 4779 drive-strength = <6>;
5543 bias-disable; 4780 bias-disable;
5544 }; 4781 };
5545 4782
5546 qup_spi20_data_clk: q 4783 qup_spi20_data_clk: qup-spi20-data-clk-state {
5547 /* MISO, MOSI 4784 /* MISO, MOSI, CLK */
5548 pins = "gpio8 4785 pins = "gpio80", "gpio81", "gpio82";
5549 function = "q 4786 function = "qup2_se4";
5550 drive-strengt 4787 drive-strength = <6>;
5551 bias-disable; 4788 bias-disable;
5552 }; 4789 };
5553 4790
5554 qup_spi21_cs: qup-spi 4791 qup_spi21_cs: qup-spi21-cs-state {
5555 pins = "gpio8 4792 pins = "gpio87";
5556 function = "q 4793 function = "qup2_se5";
5557 drive-strengt 4794 drive-strength = <6>;
5558 bias-disable; 4795 bias-disable;
5559 }; 4796 };
5560 4797
5561 qup_spi21_data_clk: q 4798 qup_spi21_data_clk: qup-spi21-data-clk-state {
5562 /* MISO, MOSI 4799 /* MISO, MOSI, CLK */
5563 pins = "gpio8 4800 pins = "gpio84", "gpio85", "gpio86";
5564 function = "q 4801 function = "qup2_se5";
5565 drive-strengt 4802 drive-strength = <6>;
5566 bias-disable; 4803 bias-disable;
5567 }; 4804 };
5568 4805
5569 qup_spi22_cs: qup-spi 4806 qup_spi22_cs: qup-spi22-cs-state {
5570 pins = "gpio9 4807 pins = "gpio91";
5571 function = "q 4808 function = "qup2_se6";
5572 drive-strengt 4809 drive-strength = <6>;
5573 bias-disable; 4810 bias-disable;
5574 }; 4811 };
5575 4812
5576 qup_spi22_data_clk: q 4813 qup_spi22_data_clk: qup-spi22-data-clk-state {
5577 /* MISO, MOSI 4814 /* MISO, MOSI, CLK */
5578 pins = "gpio8 4815 pins = "gpio88", "gpio89", "gpio90";
5579 function = "q 4816 function = "qup2_se6";
5580 drive-strengt 4817 drive-strength = <6>;
5581 bias-disable; 4818 bias-disable;
5582 }; 4819 };
5583 4820
5584 qup_spi23_cs: qup-spi 4821 qup_spi23_cs: qup-spi23-cs-state {
5585 pins = "gpio8 4822 pins = "gpio85";
5586 function = "q 4823 function = "qup2_se7";
5587 drive-strengt 4824 drive-strength = <6>;
5588 bias-disable; 4825 bias-disable;
5589 }; 4826 };
5590 4827
5591 qup_spi23_data_clk: q 4828 qup_spi23_data_clk: qup-spi23-data-clk-state {
5592 /* MISO, MOSI 4829 /* MISO, MOSI, CLK */
5593 pins = "gpio8 4830 pins = "gpio86", "gpio87", "gpio84";
5594 function = "q 4831 function = "qup2_se7";
5595 drive-strengt 4832 drive-strength = <6>;
5596 bias-disable; 4833 bias-disable;
5597 }; 4834 };
5598 4835
5599 qup_uart2_default: qu <<
5600 cts-pins { <<
5601 pins <<
5602 funct <<
5603 drive <<
5604 bias- <<
5605 }; <<
5606 <<
5607 rts-pins { <<
5608 pins <<
5609 funct <<
5610 drive <<
5611 bias- <<
5612 }; <<
5613 <<
5614 tx-pins { <<
5615 pins <<
5616 funct <<
5617 drive <<
5618 bias- <<
5619 }; <<
5620 <<
5621 rx-pins { <<
5622 pins <<
5623 funct <<
5624 drive <<
5625 bias- <<
5626 }; <<
5627 }; <<
5628 <<
5629 qup_uart21_default: q 4836 qup_uart21_default: qup-uart21-default-state {
5630 tx-pins { !! 4837 /* TX, RX */
5631 pins !! 4838 pins = "gpio86", "gpio87";
5632 funct !! 4839 function = "qup2_se5";
5633 drive !! 4840 drive-strength = <2>;
5634 bias- !! 4841 bias-disable;
5635 }; <<
5636 <<
5637 rx-pins { <<
5638 pins <<
5639 funct <<
5640 drive <<
5641 bias- <<
5642 }; <<
5643 }; 4842 };
5644 }; 4843 };
5645 4844
5646 apps_smmu: iommu@15000000 { 4845 apps_smmu: iommu@15000000 {
5647 compatible = "qcom,x1 4846 compatible = "qcom,x1e80100-smmu-500", "qcom,smmu-500", "arm,mmu-500";
5648 reg = <0 0x15000000 0 4847 reg = <0 0x15000000 0 0x100000>;
5649 4848
5650 interrupts = <GIC_SPI 4849 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
5651 <GIC_SPI 4850 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
5652 <GIC_SPI 4851 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
5653 <GIC_SPI 4852 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
5654 <GIC_SPI 4853 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
5655 <GIC_SPI 4854 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
5656 <GIC_SPI 4855 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
5657 <GIC_SPI 4856 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
5658 <GIC_SPI 4857 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
5659 <GIC_SPI 4858 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
5660 <GIC_SPI 4859 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
5661 <GIC_SPI 4860 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
5662 <GIC_SPI 4861 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
5663 <GIC_SPI 4862 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
5664 <GIC_SPI 4863 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
5665 <GIC_SPI 4864 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
5666 <GIC_SPI 4865 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
5667 <GIC_SPI 4866 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
5668 <GIC_SPI 4867 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
5669 <GIC_SPI 4868 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
5670 <GIC_SPI 4869 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
5671 <GIC_SPI 4870 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
5672 <GIC_SPI 4871 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
5673 <GIC_SPI 4872 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
5674 <GIC_SPI 4873 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
5675 <GIC_SPI 4874 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
5676 <GIC_SPI 4875 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
5677 <GIC_SPI 4876 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
5678 <GIC_SPI 4877 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
5679 <GIC_SPI 4878 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
5680 <GIC_SPI 4879 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
5681 <GIC_SPI 4880 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
5682 <GIC_SPI 4881 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
5683 <GIC_SPI 4882 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
5684 <GIC_SPI 4883 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
5685 <GIC_SPI 4884 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
5686 <GIC_SPI 4885 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
5687 <GIC_SPI 4886 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
5688 <GIC_SPI 4887 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
5689 <GIC_SPI 4888 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
5690 <GIC_SPI 4889 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
5691 <GIC_SPI 4890 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
5692 <GIC_SPI 4891 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
5693 <GIC_SPI 4892 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
5694 <GIC_SPI 4893 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
5695 <GIC_SPI 4894 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
5696 <GIC_SPI 4895 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
5697 <GIC_SPI 4896 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
5698 <GIC_SPI 4897 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
5699 <GIC_SPI 4898 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
5700 <GIC_SPI 4899 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
5701 <GIC_SPI 4900 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
5702 <GIC_SPI 4901 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
5703 <GIC_SPI 4902 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
5704 <GIC_SPI 4903 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
5705 <GIC_SPI 4904 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
5706 <GIC_SPI 4905 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
5707 <GIC_SPI 4906 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
5708 <GIC_SPI 4907 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
5709 <GIC_SPI 4908 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
5710 <GIC_SPI 4909 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
5711 <GIC_SPI 4910 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
5712 <GIC_SPI 4911 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
5713 <GIC_SPI 4912 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
5714 <GIC_SPI 4913 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
5715 <GIC_SPI 4914 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
5716 <GIC_SPI 4915 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
5717 <GIC_SPI 4916 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
5718 <GIC_SPI 4917 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
5719 <GIC_SPI 4918 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
5720 <GIC_SPI 4919 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
5721 <GIC_SPI 4920 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
5722 <GIC_SPI 4921 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
5723 <GIC_SPI 4922 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
5724 <GIC_SPI 4923 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
5725 <GIC_SPI 4924 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
5726 <GIC_SPI 4925 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
5727 <GIC_SPI 4926 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
5728 <GIC_SPI 4927 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
5729 <GIC_SPI 4928 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
5730 <GIC_SPI 4929 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
5731 <GIC_SPI 4930 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
5732 <GIC_SPI 4931 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
5733 <GIC_SPI 4932 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
5734 <GIC_SPI 4933 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
5735 <GIC_SPI 4934 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
5736 <GIC_SPI 4935 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
5737 <GIC_SPI 4936 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
5738 <GIC_SPI 4937 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
5739 <GIC_SPI 4938 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
5740 <GIC_SPI 4939 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
5741 <GIC_SPI 4940 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
5742 <GIC_SPI 4941 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
5743 <GIC_SPI 4942 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
5744 <GIC_SPI 4943 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
5745 <GIC_SPI 4944 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
5746 <GIC_SPI 4945 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>;
5747 4946
5748 #iommu-cells = <2>; 4947 #iommu-cells = <2>;
5749 #global-interrupts = 4948 #global-interrupts = <1>;
5750 }; 4949 };
5751 4950
5752 intc: interrupt-controller@17 4951 intc: interrupt-controller@17000000 {
5753 compatible = "arm,gic 4952 compatible = "arm,gic-v3";
5754 reg = <0 0x17000000 0 4953 reg = <0 0x17000000 0 0x10000>, /* GICD */
5755 <0 0x17080000 0 4954 <0 0x17080000 0 0x480000>; /* GICR * 12 */
5756 4955
5757 interrupts = <GIC_PPI 4956 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
5758 4957
5759 #interrupt-cells = <3 4958 #interrupt-cells = <3>;
5760 interrupt-controller; 4959 interrupt-controller;
5761 4960
5762 #redistributor-region 4961 #redistributor-regions = <1>;
5763 redistributor-stride 4962 redistributor-stride = <0x0 0x40000>;
5764 4963
5765 #address-cells = <2>; 4964 #address-cells = <2>;
5766 #size-cells = <2>; 4965 #size-cells = <2>;
5767 ranges; 4966 ranges;
5768 4967
5769 gic_its: msi-controll 4968 gic_its: msi-controller@17040000 {
5770 compatible = 4969 compatible = "arm,gic-v3-its";
5771 reg = <0 0x17 4970 reg = <0 0x17040000 0 0x40000>;
5772 4971
5773 msi-controlle 4972 msi-controller;
5774 #msi-cells = 4973 #msi-cells = <1>;
5775 4974
5776 status = "dis 4975 status = "disabled";
5777 }; 4976 };
5778 }; 4977 };
5779 4978
5780 apps_rsc: rsc@17500000 { 4979 apps_rsc: rsc@17500000 {
5781 compatible = "qcom,rp 4980 compatible = "qcom,rpmh-rsc";
5782 reg = <0 0x17500000 0 4981 reg = <0 0x17500000 0 0x10000>,
5783 <0 0x17510000 0 4982 <0 0x17510000 0 0x10000>,
5784 <0 0x17520000 0 4983 <0 0x17520000 0 0x10000>;
5785 reg-names = "drv-0", 4984 reg-names = "drv-0", "drv-1", "drv-2";
5786 4985
5787 interrupts = <GIC_SPI 4986 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
5788 <GIC_SPI 4987 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
5789 <GIC_SPI 4988 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
5790 qcom,tcs-offset = <0x 4989 qcom,tcs-offset = <0xd00>;
5791 qcom,drv-id = <2>; 4990 qcom,drv-id = <2>;
5792 qcom,tcs-config = <AC 4991 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
5793 <WA 4992 <WAKE_TCS 2>, <CONTROL_TCS 0>;
5794 4993
5795 label = "apps_rsc"; 4994 label = "apps_rsc";
5796 power-domains = <&SYS 4995 power-domains = <&SYSTEM_PD>;
5797 4996
5798 apps_bcm_voter: bcm-v 4997 apps_bcm_voter: bcm-voter {
5799 compatible = 4998 compatible = "qcom,bcm-voter";
5800 }; 4999 };
5801 5000
5802 rpmhcc: clock-control 5001 rpmhcc: clock-controller {
5803 compatible = 5002 compatible = "qcom,x1e80100-rpmh-clk";
5804 5003
5805 clocks = <&xo 5004 clocks = <&xo_board>;
5806 clock-names = 5005 clock-names = "xo";
5807 5006
5808 #clock-cells 5007 #clock-cells = <1>;
5809 }; 5008 };
5810 5009
5811 rpmhpd: power-control 5010 rpmhpd: power-controller {
5812 compatible = 5011 compatible = "qcom,x1e80100-rpmhpd";
5813 5012
5814 operating-poi 5013 operating-points-v2 = <&rpmhpd_opp_table>;
5815 5014
5816 #power-domain 5015 #power-domain-cells = <1>;
5817 5016
5818 rpmhpd_opp_ta 5017 rpmhpd_opp_table: opp-table {
5819 compa 5018 compatible = "operating-points-v2";
5820 5019
5821 rpmhp 5020 rpmhpd_opp_ret: opp-16 {
5822 5021 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
5823 }; 5022 };
5824 5023
5825 rpmhp 5024 rpmhpd_opp_min_svs: opp-48 {
5826 5025 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
5827 }; 5026 };
5828 5027
5829 rpmhp 5028 rpmhpd_opp_low_svs_d2: opp-52 {
5830 5029 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
5831 }; 5030 };
5832 5031
5833 rpmhp 5032 rpmhpd_opp_low_svs_d1: opp-56 {
5834 5033 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
5835 }; 5034 };
5836 5035
5837 rpmhp 5036 rpmhpd_opp_low_svs_d0: opp-60 {
5838 5037 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
5839 }; 5038 };
5840 5039
5841 rpmhp 5040 rpmhpd_opp_low_svs: opp-64 {
5842 5041 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
5843 }; 5042 };
5844 5043
5845 rpmhp 5044 rpmhpd_opp_low_svs_l1: opp-80 {
5846 5045 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
5847 }; 5046 };
5848 5047
5849 rpmhp 5048 rpmhpd_opp_svs: opp-128 {
5850 5049 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
5851 }; 5050 };
5852 5051
5853 rpmhp 5052 rpmhpd_opp_svs_l0: opp-144 {
5854 5053 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
5855 }; 5054 };
5856 5055
5857 rpmhp 5056 rpmhpd_opp_svs_l1: opp-192 {
5858 5057 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
5859 }; 5058 };
5860 5059
5861 rpmhp 5060 rpmhpd_opp_nom: opp-256 {
5862 5061 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
5863 }; 5062 };
5864 5063
5865 rpmhp 5064 rpmhpd_opp_nom_l1: opp-320 {
5866 5065 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
5867 }; 5066 };
5868 5067
5869 rpmhp 5068 rpmhpd_opp_nom_l2: opp-336 {
5870 5069 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
5871 }; 5070 };
5872 5071
5873 rpmhp 5072 rpmhpd_opp_turbo: opp-384 {
5874 5073 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
5875 }; 5074 };
5876 5075
5877 rpmhp 5076 rpmhpd_opp_turbo_l1: opp-416 {
5878 5077 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
5879 }; 5078 };
5880 }; 5079 };
5881 }; 5080 };
5882 }; 5081 };
5883 5082
5884 timer@17800000 { 5083 timer@17800000 {
5885 compatible = "arm,arm 5084 compatible = "arm,armv7-timer-mem";
5886 reg = <0 0x17800000 0 5085 reg = <0 0x17800000 0 0x1000>;
5887 5086
5888 #address-cells = <2>; 5087 #address-cells = <2>;
5889 #size-cells = <1>; 5088 #size-cells = <1>;
5890 ranges = <0 0 0 0 0x2 5089 ranges = <0 0 0 0 0x20000000>;
5891 5090
5892 frame@17801000 { 5091 frame@17801000 {
5893 reg = <0 0x17 5092 reg = <0 0x17801000 0x1000>,
5894 <0 0x17 5093 <0 0x17802000 0x1000>;
5895 5094
5896 interrupts = 5095 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
5897 5096 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
5898 5097
5899 frame-number 5098 frame-number = <0>;
5900 }; 5099 };
5901 5100
5902 frame@17803000 { 5101 frame@17803000 {
5903 reg = <0 0x17 5102 reg = <0 0x17803000 0x1000>;
5904 5103
5905 interrupts = 5104 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
5906 5105
5907 frame-number 5106 frame-number = <1>;
5908 5107
5909 status = "dis 5108 status = "disabled";
5910 }; 5109 };
5911 5110
5912 frame@17805000 { 5111 frame@17805000 {
5913 reg = <0 0x17 5112 reg = <0 0x17805000 0x1000>;
5914 5113
5915 interrupts = 5114 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
5916 5115
5917 frame-number 5116 frame-number = <2>;
5918 5117
5919 status = "dis 5118 status = "disabled";
5920 }; 5119 };
5921 5120
5922 frame@17807000 { 5121 frame@17807000 {
5923 reg = <0 0x17 5122 reg = <0 0x17807000 0x1000>;
5924 5123
5925 interrupts = 5124 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
5926 5125
5927 frame-number 5126 frame-number = <3>;
5928 5127
5929 status = "dis 5128 status = "disabled";
5930 }; 5129 };
5931 5130
5932 frame@17809000 { 5131 frame@17809000 {
5933 reg = <0 0x17 5132 reg = <0 0x17809000 0x1000>;
5934 5133
5935 interrupts = 5134 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
5936 5135
5937 frame-number 5136 frame-number = <4>;
5938 5137
5939 status = "dis 5138 status = "disabled";
5940 }; 5139 };
5941 5140
5942 frame@1780b000 { 5141 frame@1780b000 {
5943 reg = <0 0x17 5142 reg = <0 0x1780b000 0x1000>;
5944 5143
5945 interrupts = 5144 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
5946 5145
5947 frame-number 5146 frame-number = <5>;
5948 5147
5949 status = "dis 5148 status = "disabled";
5950 }; 5149 };
5951 5150
5952 frame@1780d000 { 5151 frame@1780d000 {
5953 reg = <0 0x17 5152 reg = <0 0x1780d000 0x1000>;
5954 5153
5955 interrupts = 5154 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
5956 5155
5957 frame-number 5156 frame-number = <6>;
5958 5157
5959 status = "dis 5158 status = "disabled";
5960 }; 5159 };
5961 }; 5160 };
5962 5161
5963 pmu@24091000 { <<
5964 compatible = "qcom,x1 <<
5965 reg = <0 0x24091000 0 <<
5966 <<
5967 interrupts = <GIC_SPI <<
5968 <<
5969 interconnects = <&mc_ <<
5970 &mc_ <<
5971 <<
5972 operating-points-v2 = <<
5973 <<
5974 llcc_bwmon_opp_table: <<
5975 compatible = <<
5976 <<
5977 opp-0 { <<
5978 opp-p <<
5979 }; <<
5980 <<
5981 opp-1 { <<
5982 opp-p <<
5983 }; <<
5984 <<
5985 opp-2 { <<
5986 opp-p <<
5987 }; <<
5988 <<
5989 opp-3 { <<
5990 opp-p <<
5991 }; <<
5992 <<
5993 opp-4 { <<
5994 opp-p <<
5995 }; <<
5996 <<
5997 opp-5 { <<
5998 opp-p <<
5999 }; <<
6000 <<
6001 opp-6 { <<
6002 opp-p <<
6003 }; <<
6004 <<
6005 opp-7 { <<
6006 opp-p <<
6007 }; <<
6008 <<
6009 opp-8 { <<
6010 opp-p <<
6011 }; <<
6012 <<
6013 opp-9 { <<
6014 opp-p <<
6015 }; <<
6016 }; <<
6017 }; <<
6018 <<
6019 /* cluster0 */ <<
6020 pmu@240b3400 { <<
6021 compatible = "qcom,x1 <<
6022 reg = <0 0x240b3400 0 <<
6023 <<
6024 interrupts = <GIC_SPI <<
6025 <<
6026 interconnects = <&gem <<
6027 &gem <<
6028 <<
6029 operating-points-v2 = <<
6030 <<
6031 cpu_bwmon_opp_table: <<
6032 compatible = <<
6033 <<
6034 opp-0 { <<
6035 opp-p <<
6036 }; <<
6037 <<
6038 opp-1 { <<
6039 opp-p <<
6040 }; <<
6041 <<
6042 opp-2 { <<
6043 opp-p <<
6044 }; <<
6045 <<
6046 opp-3 { <<
6047 opp-p <<
6048 }; <<
6049 <<
6050 opp-4 { <<
6051 opp-p <<
6052 }; <<
6053 <<
6054 opp-5 { <<
6055 opp-p <<
6056 }; <<
6057 }; <<
6058 }; <<
6059 <<
6060 /* cluster2 */ <<
6061 pmu@240b5400 { <<
6062 compatible = "qcom,x1 <<
6063 reg = <0 0x240b5400 0 <<
6064 <<
6065 interrupts = <GIC_SPI <<
6066 <<
6067 interconnects = <&gem <<
6068 &gem <<
6069 <<
6070 operating-points-v2 = <<
6071 }; <<
6072 <<
6073 /* cluster1 */ <<
6074 pmu@240b6400 { <<
6075 compatible = "qcom,x1 <<
6076 reg = <0 0x240b6400 0 <<
6077 <<
6078 interrupts = <GIC_SPI <<
6079 <<
6080 interconnects = <&gem <<
6081 &gem <<
6082 <<
6083 operating-points-v2 = <<
6084 }; <<
6085 <<
6086 system-cache-controller@25000 5162 system-cache-controller@25000000 {
6087 compatible = "qcom,x1 5163 compatible = "qcom,x1e80100-llcc";
6088 reg = <0 0x25000000 0 5164 reg = <0 0x25000000 0 0x200000>,
6089 <0 0x25200000 0 5165 <0 0x25200000 0 0x200000>,
6090 <0 0x25400000 0 5166 <0 0x25400000 0 0x200000>,
6091 <0 0x25600000 0 5167 <0 0x25600000 0 0x200000>,
6092 <0 0x25800000 0 5168 <0 0x25800000 0 0x200000>,
6093 <0 0x25a00000 0 5169 <0 0x25a00000 0 0x200000>,
6094 <0 0x25c00000 0 5170 <0 0x25c00000 0 0x200000>,
6095 <0 0x25e00000 0 5171 <0 0x25e00000 0 0x200000>,
6096 <0 0x26000000 0 !! 5172 <0 0x26000000 0 0x200000>;
6097 <0 0x26200000 0 <<
6098 reg-names = "llcc0_ba 5173 reg-names = "llcc0_base",
6099 "llcc1_ba 5174 "llcc1_base",
6100 "llcc2_ba 5175 "llcc2_base",
6101 "llcc3_ba 5176 "llcc3_base",
6102 "llcc4_ba 5177 "llcc4_base",
6103 "llcc5_ba 5178 "llcc5_base",
6104 "llcc6_ba 5179 "llcc6_base",
6105 "llcc7_ba 5180 "llcc7_base",
6106 "llcc_bro !! 5181 "llcc_broadcast_base";
6107 "llcc_bro <<
6108 interrupts = <GIC_SPI 5182 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
6109 }; 5183 };
6110 5184
6111 remoteproc_adsp: remoteproc@3 5185 remoteproc_adsp: remoteproc@30000000 {
6112 compatible = "qcom,x1 5186 compatible = "qcom,x1e80100-adsp-pas";
6113 reg = <0 0x30000000 0 5187 reg = <0 0x30000000 0 0x100>;
6114 5188
6115 interrupts-extended = 5189 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
6116 5190 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
6117 5191 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
6118 5192 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
6119 5193 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
6120 interrupt-names = "wd 5194 interrupt-names = "wdog",
6121 "fa 5195 "fatal",
6122 "re 5196 "ready",
6123 "ha 5197 "handover",
6124 "st 5198 "stop-ack";
6125 5199
6126 clocks = <&rpmhcc RPM 5200 clocks = <&rpmhcc RPMH_CXO_CLK>;
6127 clock-names = "xo"; 5201 clock-names = "xo";
6128 5202
6129 power-domains = <&rpm 5203 power-domains = <&rpmhpd RPMHPD_LCX>,
6130 <&rpm 5204 <&rpmhpd RPMHPD_LMX>;
6131 power-domain-names = 5205 power-domain-names = "lcx",
6132 5206 "lmx";
6133 5207
6134 interconnects = <&lpa 5208 interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS
6135 &mc_ 5209 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
6136 5210
6137 memory-region = <&ads 5211 memory-region = <&adspslpi_mem>,
6138 <&q6_ 5212 <&q6_adsp_dtb_mem>;
6139 5213
6140 qcom,qmp = <&aoss_qmp 5214 qcom,qmp = <&aoss_qmp>;
6141 5215
6142 qcom,smem-states = <& 5216 qcom,smem-states = <&smp2p_adsp_out 0>;
6143 qcom,smem-state-names 5217 qcom,smem-state-names = "stop";
6144 5218
6145 status = "disabled"; 5219 status = "disabled";
6146 5220
6147 glink-edge { 5221 glink-edge {
6148 interrupts-ex 5222 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
6149 5223 IPCC_MPROC_SIGNAL_GLINK_QMP
6150 5224 IRQ_TYPE_EDGE_RISING>;
6151 mboxes = <&ip 5225 mboxes = <&ipcc IPCC_CLIENT_LPASS
6152 5226 IPCC_MPROC_SIGNAL_GLINK_QMP>;
6153 5227
6154 label = "lpas 5228 label = "lpass";
6155 qcom,remote-p 5229 qcom,remote-pid = <2>;
6156 5230
6157 fastrpc { <<
6158 compa <<
6159 qcom, <<
6160 label <<
6161 qcom, <<
6162 #addr <<
6163 #size <<
6164 <<
6165 compu <<
6166 <<
6167 <<
6168 <<
6169 <<
6170 <<
6171 }; <<
6172 <<
6173 compu <<
6174 <<
6175 <<
6176 <<
6177 <<
6178 <<
6179 }; <<
6180 <<
6181 compu <<
6182 <<
6183 <<
6184 <<
6185 <<
6186 <<
6187 }; <<
6188 <<
6189 compu <<
6190 <<
6191 <<
6192 <<
6193 <<
6194 <<
6195 }; <<
6196 <<
6197 compu <<
6198 <<
6199 <<
6200 <<
6201 <<
6202 <<
6203 }; <<
6204 }; <<
6205 <<
6206 gpr { 5231 gpr {
6207 compa 5232 compatible = "qcom,gpr";
6208 qcom, 5233 qcom,glink-channels = "adsp_apps";
6209 qcom, 5234 qcom,domain = <GPR_DOMAIN_ID_ADSP>;
6210 qcom, 5235 qcom,intents = <512 20>;
6211 #addr 5236 #address-cells = <1>;
6212 #size 5237 #size-cells = <0>;
6213 5238
6214 q6apm 5239 q6apm: service@1 {
6215 5240 compatible = "qcom,q6apm";
6216 5241 reg = <GPR_APM_MODULE_IID>;
6217 5242 #sound-dai-cells = <0>;
6218 5243 qcom,protection-domain = "avs/audio",
6219 5244 "msm/adsp/audio_pd";
6220 5245
6221 5246 q6apmbedai: bedais {
6222 5247 compatible = "qcom,q6apm-lpass-dais";
6223 5248 #sound-dai-cells = <1>;
6224 5249 };
6225 5250
6226 5251 q6apmdai: dais {
6227 5252 compatible = "qcom,q6apm-dais";
6228 5253 iommus = <&apps_smmu 0x1001 0x80>,
6229 5254 <&apps_smmu 0x1061 0x0>;
6230 5255 };
6231 }; 5256 };
6232 5257
6233 q6prm 5258 q6prm: service@2 {
6234 5259 compatible = "qcom,q6prm";
6235 5260 reg = <GPR_PRM_MODULE_IID>;
6236 5261 qcom,protection-domain = "avs/audio",
6237 5262 "msm/adsp/audio_pd";
6238 5263
6239 5264 q6prmcc: clock-controller {
6240 5265 compatible = "qcom,q6prm-lpass-clocks";
6241 5266 #clock-cells = <2>;
6242 5267 };
6243 }; 5268 };
6244 }; 5269 };
6245 }; 5270 };
6246 }; 5271 };
6247 5272
6248 remoteproc_cdsp: remoteproc@3 5273 remoteproc_cdsp: remoteproc@32300000 {
6249 compatible = "qcom,x1 5274 compatible = "qcom,x1e80100-cdsp-pas";
6250 reg = <0 0x32300000 0 5275 reg = <0 0x32300000 0 0x1400000>;
6251 5276
6252 interrupts-extended = 5277 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
6253 5278 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
6254 5279 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
6255 5280 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
6256 5281 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
6257 interrupt-names = "wd 5282 interrupt-names = "wdog",
6258 "fa 5283 "fatal",
6259 "re 5284 "ready",
6260 "ha 5285 "handover",
6261 "st 5286 "stop-ack";
6262 5287
6263 clocks = <&rpmhcc RPM 5288 clocks = <&rpmhcc RPMH_CXO_CLK>;
6264 clock-names = "xo"; 5289 clock-names = "xo";
6265 5290
6266 power-domains = <&rpm 5291 power-domains = <&rpmhpd RPMHPD_CX>,
6267 <&rpm 5292 <&rpmhpd RPMHPD_MXC>,
6268 <&rpm 5293 <&rpmhpd RPMHPD_NSP>;
6269 power-domain-names = 5294 power-domain-names = "cx",
6270 5295 "mxc",
6271 5296 "nsp";
6272 5297
6273 interconnects = <&nsp 5298 interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS
6274 &mc_ 5299 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
6275 5300
6276 memory-region = <&cds 5301 memory-region = <&cdsp_mem>,
6277 <&q6_ 5302 <&q6_cdsp_dtb_mem>;
6278 5303
6279 qcom,qmp = <&aoss_qmp 5304 qcom,qmp = <&aoss_qmp>;
6280 5305
6281 qcom,smem-states = <& 5306 qcom,smem-states = <&smp2p_cdsp_out 0>;
6282 qcom,smem-state-names 5307 qcom,smem-state-names = "stop";
6283 5308
6284 status = "disabled"; 5309 status = "disabled";
6285 5310
6286 glink-edge { 5311 glink-edge {
6287 interrupts-ex 5312 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
6288 5313 IPCC_MPROC_SIGNAL_GLINK_QMP
6289 5314 IRQ_TYPE_EDGE_RISING>;
6290 mboxes = <&ip 5315 mboxes = <&ipcc IPCC_CLIENT_CDSP
6291 5316 IPCC_MPROC_SIGNAL_GLINK_QMP>;
6292 5317
6293 label = "cdsp 5318 label = "cdsp";
6294 qcom,remote-p 5319 qcom,remote-pid = <5>;
6295 <<
6296 fastrpc { <<
6297 compa <<
6298 qcom, <<
6299 label <<
6300 qcom, <<
6301 #addr <<
6302 #size <<
6303 <<
6304 compu <<
6305 <<
6306 <<
6307 <<
6308 <<
6309 }; <<
6310 <<
6311 compu <<
6312 <<
6313 <<
6314 <<
6315 <<
6316 }; <<
6317 <<
6318 compu <<
6319 <<
6320 <<
6321 <<
6322 <<
6323 }; <<
6324 <<
6325 compu <<
6326 <<
6327 <<
6328 <<
6329 <<
6330 }; <<
6331 <<
6332 compu <<
6333 <<
6334 <<
6335 <<
6336 <<
6337 }; <<
6338 <<
6339 compu <<
6340 <<
6341 <<
6342 <<
6343 <<
6344 }; <<
6345 <<
6346 compu <<
6347 <<
6348 <<
6349 <<
6350 <<
6351 }; <<
6352 <<
6353 compu <<
6354 <<
6355 <<
6356 <<
6357 <<
6358 }; <<
6359 <<
6360 /* no <<
6361 <<
6362 compu <<
6363 <<
6364 <<
6365 <<
6366 <<
6367 }; <<
6368 <<
6369 compu <<
6370 <<
6371 <<
6372 <<
6373 <<
6374 }; <<
6375 <<
6376 compu <<
6377 <<
6378 <<
6379 <<
6380 <<
6381 }; <<
6382 <<
6383 compu <<
6384 <<
6385 <<
6386 <<
6387 <<
6388 }; <<
6389 }; <<
6390 }; 5320 };
6391 }; 5321 };
6392 }; 5322 };
6393 5323
6394 timer { 5324 timer {
6395 compatible = "arm,armv8-timer 5325 compatible = "arm,armv8-timer";
6396 5326
6397 interrupts = <GIC_PPI 13 IRQ_ 5327 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
6398 <GIC_PPI 14 IRQ_ 5328 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
6399 <GIC_PPI 11 IRQ_ 5329 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
6400 <GIC_PPI 10 IRQ_ 5330 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
6401 }; <<
6402 <<
6403 thermal-zones { <<
6404 aoss0-thermal { <<
6405 thermal-sensors = <&t <<
6406 <<
6407 trips { <<
6408 trip-point0 { <<
6409 tempe <<
6410 hyste <<
6411 type <<
6412 }; <<
6413 <<
6414 aoss0-critica <<
6415 tempe <<
6416 hyste <<
6417 type <<
6418 }; <<
6419 }; <<
6420 }; <<
6421 <<
6422 cpu0-0-top-thermal { <<
6423 polling-delay-passive <<
6424 <<
6425 thermal-sensors = <&t <<
6426 <<
6427 trips { <<
6428 trip-point0 { <<
6429 tempe <<
6430 hyste <<
6431 type <<
6432 }; <<
6433 <<
6434 trip-point1 { <<
6435 tempe <<
6436 hyste <<
6437 type <<
6438 }; <<
6439 <<
6440 cpu-critical <<
6441 tempe <<
6442 hyste <<
6443 type <<
6444 }; <<
6445 }; <<
6446 }; <<
6447 <<
6448 cpu0-0-btm-thermal { <<
6449 polling-delay-passive <<
6450 <<
6451 thermal-sensors = <&t <<
6452 <<
6453 trips { <<
6454 trip-point0 { <<
6455 tempe <<
6456 hyste <<
6457 type <<
6458 }; <<
6459 <<
6460 trip-point1 { <<
6461 tempe <<
6462 hyste <<
6463 type <<
6464 }; <<
6465 <<
6466 cpu-critical <<
6467 tempe <<
6468 hyste <<
6469 type <<
6470 }; <<
6471 }; <<
6472 }; <<
6473 <<
6474 cpu0-1-top-thermal { <<
6475 polling-delay-passive <<
6476 <<
6477 thermal-sensors = <&t <<
6478 <<
6479 trips { <<
6480 trip-point0 { <<
6481 tempe <<
6482 hyste <<
6483 type <<
6484 }; <<
6485 <<
6486 trip-point1 { <<
6487 tempe <<
6488 hyste <<
6489 type <<
6490 }; <<
6491 <<
6492 cpu-critical <<
6493 tempe <<
6494 hyste <<
6495 type <<
6496 }; <<
6497 }; <<
6498 }; <<
6499 <<
6500 cpu0-1-btm-thermal { <<
6501 polling-delay-passive <<
6502 <<
6503 thermal-sensors = <&t <<
6504 <<
6505 trips { <<
6506 trip-point0 { <<
6507 tempe <<
6508 hyste <<
6509 type <<
6510 }; <<
6511 <<
6512 trip-point1 { <<
6513 tempe <<
6514 hyste <<
6515 type <<
6516 }; <<
6517 <<
6518 cpu-critical <<
6519 tempe <<
6520 hyste <<
6521 type <<
6522 }; <<
6523 }; <<
6524 }; <<
6525 <<
6526 cpu0-2-top-thermal { <<
6527 polling-delay-passive <<
6528 <<
6529 thermal-sensors = <&t <<
6530 <<
6531 trips { <<
6532 trip-point0 { <<
6533 tempe <<
6534 hyste <<
6535 type <<
6536 }; <<
6537 <<
6538 trip-point1 { <<
6539 tempe <<
6540 hyste <<
6541 type <<
6542 }; <<
6543 <<
6544 cpu-critical <<
6545 tempe <<
6546 hyste <<
6547 type <<
6548 }; <<
6549 }; <<
6550 }; <<
6551 <<
6552 cpu0-2-btm-thermal { <<
6553 polling-delay-passive <<
6554 <<
6555 thermal-sensors = <&t <<
6556 <<
6557 trips { <<
6558 trip-point0 { <<
6559 tempe <<
6560 hyste <<
6561 type <<
6562 }; <<
6563 <<
6564 trip-point1 { <<
6565 tempe <<
6566 hyste <<
6567 type <<
6568 }; <<
6569 <<
6570 cpu-critical <<
6571 tempe <<
6572 hyste <<
6573 type <<
6574 }; <<
6575 }; <<
6576 }; <<
6577 <<
6578 cpu0-3-top-thermal { <<
6579 polling-delay-passive <<
6580 <<
6581 thermal-sensors = <&t <<
6582 <<
6583 trips { <<
6584 trip-point0 { <<
6585 tempe <<
6586 hyste <<
6587 type <<
6588 }; <<
6589 <<
6590 trip-point1 { <<
6591 tempe <<
6592 hyste <<
6593 type <<
6594 }; <<
6595 <<
6596 cpu-critical <<
6597 tempe <<
6598 hyste <<
6599 type <<
6600 }; <<
6601 }; <<
6602 }; <<
6603 <<
6604 cpu0-3-btm-thermal { <<
6605 polling-delay-passive <<
6606 <<
6607 thermal-sensors = <&t <<
6608 <<
6609 trips { <<
6610 trip-point0 { <<
6611 tempe <<
6612 hyste <<
6613 type <<
6614 }; <<
6615 <<
6616 trip-point1 { <<
6617 tempe <<
6618 hyste <<
6619 type <<
6620 }; <<
6621 <<
6622 cpu-critical <<
6623 tempe <<
6624 hyste <<
6625 type <<
6626 }; <<
6627 }; <<
6628 }; <<
6629 <<
6630 cpuss0-top-thermal { <<
6631 thermal-sensors = <&t <<
6632 <<
6633 trips { <<
6634 trip-point0 { <<
6635 tempe <<
6636 hyste <<
6637 type <<
6638 }; <<
6639 <<
6640 cpuss2-critic <<
6641 tempe <<
6642 hyste <<
6643 type <<
6644 }; <<
6645 }; <<
6646 }; <<
6647 <<
6648 cpuss0-btm-thermal { <<
6649 thermal-sensors = <&t <<
6650 <<
6651 trips { <<
6652 trip-point0 { <<
6653 tempe <<
6654 hyste <<
6655 type <<
6656 }; <<
6657 <<
6658 cpuss2-critic <<
6659 tempe <<
6660 hyste <<
6661 type <<
6662 }; <<
6663 }; <<
6664 }; <<
6665 <<
6666 mem-thermal { <<
6667 thermal-sensors = <&t <<
6668 <<
6669 trips { <<
6670 trip-point0 { <<
6671 tempe <<
6672 hyste <<
6673 type <<
6674 }; <<
6675 <<
6676 mem-critical <<
6677 tempe <<
6678 hyste <<
6679 type <<
6680 }; <<
6681 }; <<
6682 }; <<
6683 <<
6684 video-thermal { <<
6685 polling-delay-passive <<
6686 <<
6687 thermal-sensors = <&t <<
6688 <<
6689 trips { <<
6690 trip-point0 { <<
6691 tempe <<
6692 hyste <<
6693 type <<
6694 }; <<
6695 }; <<
6696 }; <<
6697 <<
6698 aoss1-thermal { <<
6699 thermal-sensors = <&t <<
6700 <<
6701 trips { <<
6702 trip-point0 { <<
6703 tempe <<
6704 hyste <<
6705 type <<
6706 }; <<
6707 <<
6708 aoss0-critica <<
6709 tempe <<
6710 hyste <<
6711 type <<
6712 }; <<
6713 }; <<
6714 }; <<
6715 <<
6716 cpu1-0-top-thermal { <<
6717 polling-delay-passive <<
6718 <<
6719 thermal-sensors = <&t <<
6720 <<
6721 trips { <<
6722 trip-point0 { <<
6723 tempe <<
6724 hyste <<
6725 type <<
6726 }; <<
6727 <<
6728 trip-point1 { <<
6729 tempe <<
6730 hyste <<
6731 type <<
6732 }; <<
6733 <<
6734 cpu-critical <<
6735 tempe <<
6736 hyste <<
6737 type <<
6738 }; <<
6739 }; <<
6740 }; <<
6741 <<
6742 cpu1-0-btm-thermal { <<
6743 polling-delay-passive <<
6744 <<
6745 thermal-sensors = <&t <<
6746 <<
6747 trips { <<
6748 trip-point0 { <<
6749 tempe <<
6750 hyste <<
6751 type <<
6752 }; <<
6753 <<
6754 trip-point1 { <<
6755 tempe <<
6756 hyste <<
6757 type <<
6758 }; <<
6759 <<
6760 cpu-critical <<
6761 tempe <<
6762 hyste <<
6763 type <<
6764 }; <<
6765 }; <<
6766 }; <<
6767 <<
6768 cpu1-1-top-thermal { <<
6769 polling-delay-passive <<
6770 <<
6771 thermal-sensors = <&t <<
6772 <<
6773 trips { <<
6774 trip-point0 { <<
6775 tempe <<
6776 hyste <<
6777 type <<
6778 }; <<
6779 <<
6780 trip-point1 { <<
6781 tempe <<
6782 hyste <<
6783 type <<
6784 }; <<
6785 <<
6786 cpu-critical <<
6787 tempe <<
6788 hyste <<
6789 type <<
6790 }; <<
6791 }; <<
6792 }; <<
6793 <<
6794 cpu1-1-btm-thermal { <<
6795 polling-delay-passive <<
6796 <<
6797 thermal-sensors = <&t <<
6798 <<
6799 trips { <<
6800 trip-point0 { <<
6801 tempe <<
6802 hyste <<
6803 type <<
6804 }; <<
6805 <<
6806 trip-point1 { <<
6807 tempe <<
6808 hyste <<
6809 type <<
6810 }; <<
6811 <<
6812 cpu-critical <<
6813 tempe <<
6814 hyste <<
6815 type <<
6816 }; <<
6817 }; <<
6818 }; <<
6819 <<
6820 cpu1-2-top-thermal { <<
6821 polling-delay-passive <<
6822 <<
6823 thermal-sensors = <&t <<
6824 <<
6825 trips { <<
6826 trip-point0 { <<
6827 tempe <<
6828 hyste <<
6829 type <<
6830 }; <<
6831 <<
6832 trip-point1 { <<
6833 tempe <<
6834 hyste <<
6835 type <<
6836 }; <<
6837 <<
6838 cpu-critical <<
6839 tempe <<
6840 hyste <<
6841 type <<
6842 }; <<
6843 }; <<
6844 }; <<
6845 <<
6846 cpu1-2-btm-thermal { <<
6847 polling-delay-passive <<
6848 <<
6849 thermal-sensors = <&t <<
6850 <<
6851 trips { <<
6852 trip-point0 { <<
6853 tempe <<
6854 hyste <<
6855 type <<
6856 }; <<
6857 <<
6858 trip-point1 { <<
6859 tempe <<
6860 hyste <<
6861 type <<
6862 }; <<
6863 <<
6864 cpu-critical <<
6865 tempe <<
6866 hyste <<
6867 type <<
6868 }; <<
6869 }; <<
6870 }; <<
6871 <<
6872 cpu1-3-top-thermal { <<
6873 polling-delay-passive <<
6874 <<
6875 thermal-sensors = <&t <<
6876 <<
6877 trips { <<
6878 trip-point0 { <<
6879 tempe <<
6880 hyste <<
6881 type <<
6882 }; <<
6883 <<
6884 trip-point1 { <<
6885 tempe <<
6886 hyste <<
6887 type <<
6888 }; <<
6889 <<
6890 cpu-critical <<
6891 tempe <<
6892 hyste <<
6893 type <<
6894 }; <<
6895 }; <<
6896 }; <<
6897 <<
6898 cpu1-3-btm-thermal { <<
6899 polling-delay-passive <<
6900 <<
6901 thermal-sensors = <&t <<
6902 <<
6903 trips { <<
6904 trip-point0 { <<
6905 tempe <<
6906 hyste <<
6907 type <<
6908 }; <<
6909 <<
6910 trip-point1 { <<
6911 tempe <<
6912 hyste <<
6913 type <<
6914 }; <<
6915 <<
6916 cpu-critical <<
6917 tempe <<
6918 hyste <<
6919 type <<
6920 }; <<
6921 }; <<
6922 }; <<
6923 <<
6924 cpuss1-top-thermal { <<
6925 thermal-sensors = <&t <<
6926 <<
6927 trips { <<
6928 trip-point0 { <<
6929 tempe <<
6930 hyste <<
6931 type <<
6932 }; <<
6933 <<
6934 cpuss2-critic <<
6935 tempe <<
6936 hyste <<
6937 type <<
6938 }; <<
6939 }; <<
6940 }; <<
6941 <<
6942 cpuss1-btm-thermal { <<
6943 thermal-sensors = <&t <<
6944 <<
6945 trips { <<
6946 trip-point0 { <<
6947 tempe <<
6948 hyste <<
6949 type <<
6950 }; <<
6951 <<
6952 cpuss2-critic <<
6953 tempe <<
6954 hyste <<
6955 type <<
6956 }; <<
6957 }; <<
6958 }; <<
6959 <<
6960 aoss2-thermal { <<
6961 thermal-sensors = <&t <<
6962 <<
6963 trips { <<
6964 trip-point0 { <<
6965 tempe <<
6966 hyste <<
6967 type <<
6968 }; <<
6969 <<
6970 aoss0-critica <<
6971 tempe <<
6972 hyste <<
6973 type <<
6974 }; <<
6975 }; <<
6976 }; <<
6977 <<
6978 cpu2-0-top-thermal { <<
6979 polling-delay-passive <<
6980 <<
6981 thermal-sensors = <&t <<
6982 <<
6983 trips { <<
6984 trip-point0 { <<
6985 tempe <<
6986 hyste <<
6987 type <<
6988 }; <<
6989 <<
6990 trip-point1 { <<
6991 tempe <<
6992 hyste <<
6993 type <<
6994 }; <<
6995 <<
6996 cpu-critical <<
6997 tempe <<
6998 hyste <<
6999 type <<
7000 }; <<
7001 }; <<
7002 }; <<
7003 <<
7004 cpu2-0-btm-thermal { <<
7005 polling-delay-passive <<
7006 <<
7007 thermal-sensors = <&t <<
7008 <<
7009 trips { <<
7010 trip-point0 { <<
7011 tempe <<
7012 hyste <<
7013 type <<
7014 }; <<
7015 <<
7016 trip-point1 { <<
7017 tempe <<
7018 hyste <<
7019 type <<
7020 }; <<
7021 <<
7022 cpu-critical <<
7023 tempe <<
7024 hyste <<
7025 type <<
7026 }; <<
7027 }; <<
7028 }; <<
7029 <<
7030 cpu2-1-top-thermal { <<
7031 polling-delay-passive <<
7032 <<
7033 thermal-sensors = <&t <<
7034 <<
7035 trips { <<
7036 trip-point0 { <<
7037 tempe <<
7038 hyste <<
7039 type <<
7040 }; <<
7041 <<
7042 trip-point1 { <<
7043 tempe <<
7044 hyste <<
7045 type <<
7046 }; <<
7047 <<
7048 cpu-critical <<
7049 tempe <<
7050 hyste <<
7051 type <<
7052 }; <<
7053 }; <<
7054 }; <<
7055 <<
7056 cpu2-1-btm-thermal { <<
7057 polling-delay-passive <<
7058 <<
7059 thermal-sensors = <&t <<
7060 <<
7061 trips { <<
7062 trip-point0 { <<
7063 tempe <<
7064 hyste <<
7065 type <<
7066 }; <<
7067 <<
7068 trip-point1 { <<
7069 tempe <<
7070 hyste <<
7071 type <<
7072 }; <<
7073 <<
7074 cpu-critical <<
7075 tempe <<
7076 hyste <<
7077 type <<
7078 }; <<
7079 }; <<
7080 }; <<
7081 <<
7082 cpu2-2-top-thermal { <<
7083 polling-delay-passive <<
7084 <<
7085 thermal-sensors = <&t <<
7086 <<
7087 trips { <<
7088 trip-point0 { <<
7089 tempe <<
7090 hyste <<
7091 type <<
7092 }; <<
7093 <<
7094 trip-point1 { <<
7095 tempe <<
7096 hyste <<
7097 type <<
7098 }; <<
7099 <<
7100 cpu-critical <<
7101 tempe <<
7102 hyste <<
7103 type <<
7104 }; <<
7105 }; <<
7106 }; <<
7107 <<
7108 cpu2-2-btm-thermal { <<
7109 polling-delay-passive <<
7110 <<
7111 thermal-sensors = <&t <<
7112 <<
7113 trips { <<
7114 trip-point0 { <<
7115 tempe <<
7116 hyste <<
7117 type <<
7118 }; <<
7119 <<
7120 trip-point1 { <<
7121 tempe <<
7122 hyste <<
7123 type <<
7124 }; <<
7125 <<
7126 cpu-critical <<
7127 tempe <<
7128 hyste <<
7129 type <<
7130 }; <<
7131 }; <<
7132 }; <<
7133 <<
7134 cpu2-3-top-thermal { <<
7135 polling-delay-passive <<
7136 <<
7137 thermal-sensors = <&t <<
7138 <<
7139 trips { <<
7140 trip-point0 { <<
7141 tempe <<
7142 hyste <<
7143 type <<
7144 }; <<
7145 <<
7146 trip-point1 { <<
7147 tempe <<
7148 hyste <<
7149 type <<
7150 }; <<
7151 <<
7152 cpu-critical <<
7153 tempe <<
7154 hyste <<
7155 type <<
7156 }; <<
7157 }; <<
7158 }; <<
7159 <<
7160 cpu2-3-btm-thermal { <<
7161 polling-delay-passive <<
7162 <<
7163 thermal-sensors = <&t <<
7164 <<
7165 trips { <<
7166 trip-point0 { <<
7167 tempe <<
7168 hyste <<
7169 type <<
7170 }; <<
7171 <<
7172 trip-point1 { <<
7173 tempe <<
7174 hyste <<
7175 type <<
7176 }; <<
7177 <<
7178 cpu-critical <<
7179 tempe <<
7180 hyste <<
7181 type <<
7182 }; <<
7183 }; <<
7184 }; <<
7185 <<
7186 cpuss2-top-thermal { <<
7187 thermal-sensors = <&t <<
7188 <<
7189 trips { <<
7190 trip-point0 { <<
7191 tempe <<
7192 hyste <<
7193 type <<
7194 }; <<
7195 <<
7196 cpuss2-critic <<
7197 tempe <<
7198 hyste <<
7199 type <<
7200 }; <<
7201 }; <<
7202 }; <<
7203 <<
7204 cpuss2-btm-thermal { <<
7205 thermal-sensors = <&t <<
7206 <<
7207 trips { <<
7208 trip-point0 { <<
7209 tempe <<
7210 hyste <<
7211 type <<
7212 }; <<
7213 <<
7214 cpuss2-critic <<
7215 tempe <<
7216 hyste <<
7217 type <<
7218 }; <<
7219 }; <<
7220 }; <<
7221 <<
7222 aoss3-thermal { <<
7223 thermal-sensors = <&t <<
7224 <<
7225 trips { <<
7226 trip-point0 { <<
7227 tempe <<
7228 hyste <<
7229 type <<
7230 }; <<
7231 <<
7232 aoss0-critica <<
7233 tempe <<
7234 hyste <<
7235 type <<
7236 }; <<
7237 }; <<
7238 }; <<
7239 <<
7240 nsp0-thermal { <<
7241 thermal-sensors = <&t <<
7242 <<
7243 trips { <<
7244 trip-point0 { <<
7245 tempe <<
7246 hyste <<
7247 type <<
7248 }; <<
7249 <<
7250 nsp0-critical <<
7251 tempe <<
7252 hyste <<
7253 type <<
7254 }; <<
7255 }; <<
7256 }; <<
7257 <<
7258 nsp1-thermal { <<
7259 thermal-sensors = <&t <<
7260 <<
7261 trips { <<
7262 trip-point0 { <<
7263 tempe <<
7264 hyste <<
7265 type <<
7266 }; <<
7267 <<
7268 nsp1-critical <<
7269 tempe <<
7270 hyste <<
7271 type <<
7272 }; <<
7273 }; <<
7274 }; <<
7275 <<
7276 nsp2-thermal { <<
7277 thermal-sensors = <&t <<
7278 <<
7279 trips { <<
7280 trip-point0 { <<
7281 tempe <<
7282 hyste <<
7283 type <<
7284 }; <<
7285 <<
7286 nsp2-critical <<
7287 tempe <<
7288 hyste <<
7289 type <<
7290 }; <<
7291 }; <<
7292 }; <<
7293 <<
7294 nsp3-thermal { <<
7295 thermal-sensors = <&t <<
7296 <<
7297 trips { <<
7298 trip-point0 { <<
7299 tempe <<
7300 hyste <<
7301 type <<
7302 }; <<
7303 <<
7304 nsp3-critical <<
7305 tempe <<
7306 hyste <<
7307 type <<
7308 }; <<
7309 }; <<
7310 }; <<
7311 <<
7312 gpuss-0-thermal { <<
7313 polling-delay-passive <<
7314 <<
7315 thermal-sensors = <&t <<
7316 <<
7317 trips { <<
7318 trip-point0 { <<
7319 tempe <<
7320 hyste <<
7321 type <<
7322 }; <<
7323 <<
7324 trip-point1 { <<
7325 tempe <<
7326 hyste <<
7327 type <<
7328 }; <<
7329 <<
7330 trip-point2 { <<
7331 tempe <<
7332 hyste <<
7333 type <<
7334 }; <<
7335 }; <<
7336 }; <<
7337 <<
7338 gpuss-1-thermal { <<
7339 polling-delay-passive <<
7340 <<
7341 thermal-sensors = <&t <<
7342 <<
7343 trips { <<
7344 trip-point0 { <<
7345 tempe <<
7346 hyste <<
7347 type <<
7348 }; <<
7349 <<
7350 trip-point1 { <<
7351 tempe <<
7352 hyste <<
7353 type <<
7354 }; <<
7355 <<
7356 trip-point2 { <<
7357 tempe <<
7358 hyste <<
7359 type <<
7360 }; <<
7361 }; <<
7362 }; <<
7363 <<
7364 gpuss-2-thermal { <<
7365 polling-delay-passive <<
7366 <<
7367 thermal-sensors = <&t <<
7368 <<
7369 trips { <<
7370 trip-point0 { <<
7371 tempe <<
7372 hyste <<
7373 type <<
7374 }; <<
7375 <<
7376 trip-point1 { <<
7377 tempe <<
7378 hyste <<
7379 type <<
7380 }; <<
7381 <<
7382 trip-point2 { <<
7383 tempe <<
7384 hyste <<
7385 type <<
7386 }; <<
7387 }; <<
7388 }; <<
7389 <<
7390 gpuss-3-thermal { <<
7391 polling-delay-passive <<
7392 <<
7393 thermal-sensors = <&t <<
7394 <<
7395 trips { <<
7396 trip-point0 { <<
7397 tempe <<
7398 hyste <<
7399 type <<
7400 }; <<
7401 <<
7402 trip-point1 { <<
7403 tempe <<
7404 hyste <<
7405 type <<
7406 }; <<
7407 <<
7408 trip-point2 { <<
7409 tempe <<
7410 hyste <<
7411 type <<
7412 }; <<
7413 }; <<
7414 }; <<
7415 <<
7416 gpuss-4-thermal { <<
7417 polling-delay-passive <<
7418 <<
7419 thermal-sensors = <&t <<
7420 <<
7421 trips { <<
7422 trip-point0 { <<
7423 tempe <<
7424 hyste <<
7425 type <<
7426 }; <<
7427 <<
7428 trip-point1 { <<
7429 tempe <<
7430 hyste <<
7431 type <<
7432 }; <<
7433 <<
7434 trip-point2 { <<
7435 tempe <<
7436 hyste <<
7437 type <<
7438 }; <<
7439 }; <<
7440 }; <<
7441 <<
7442 gpuss-5-thermal { <<
7443 polling-delay-passive <<
7444 <<
7445 thermal-sensors = <&t <<
7446 <<
7447 trips { <<
7448 trip-point0 { <<
7449 tempe <<
7450 hyste <<
7451 type <<
7452 }; <<
7453 <<
7454 trip-point1 { <<
7455 tempe <<
7456 hyste <<
7457 type <<
7458 }; <<
7459 <<
7460 trip-point2 { <<
7461 tempe <<
7462 hyste <<
7463 type <<
7464 }; <<
7465 }; <<
7466 }; <<
7467 <<
7468 gpuss-6-thermal { <<
7469 polling-delay-passive <<
7470 <<
7471 thermal-sensors = <&t <<
7472 <<
7473 trips { <<
7474 trip-point0 { <<
7475 tempe <<
7476 hyste <<
7477 type <<
7478 }; <<
7479 <<
7480 trip-point1 { <<
7481 tempe <<
7482 hyste <<
7483 type <<
7484 }; <<
7485 <<
7486 trip-point2 { <<
7487 tempe <<
7488 hyste <<
7489 type <<
7490 }; <<
7491 }; <<
7492 }; <<
7493 <<
7494 gpuss-7-thermal { <<
7495 polling-delay-passive <<
7496 <<
7497 thermal-sensors = <&t <<
7498 <<
7499 trips { <<
7500 trip-point0 { <<
7501 tempe <<
7502 hyste <<
7503 type <<
7504 }; <<
7505 <<
7506 trip-point1 { <<
7507 tempe <<
7508 hyste <<
7509 type <<
7510 }; <<
7511 <<
7512 trip-point2 { <<
7513 tempe <<
7514 hyste <<
7515 type <<
7516 }; <<
7517 }; <<
7518 }; <<
7519 <<
7520 camera0-thermal { <<
7521 thermal-sensors = <&t <<
7522 <<
7523 trips { <<
7524 trip-point0 { <<
7525 tempe <<
7526 hyste <<
7527 type <<
7528 }; <<
7529 <<
7530 camera0-criti <<
7531 tempe <<
7532 hyste <<
7533 type <<
7534 }; <<
7535 }; <<
7536 }; <<
7537 <<
7538 camera1-thermal { <<
7539 thermal-sensors = <&t <<
7540 <<
7541 trips { <<
7542 trip-point0 { <<
7543 tempe <<
7544 hyste <<
7545 type <<
7546 }; <<
7547 <<
7548 camera0-criti <<
7549 tempe <<
7550 hyste <<
7551 type <<
7552 }; <<
7553 }; <<
7554 }; <<
7555 }; 5331 };
7556 }; 5332 };
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