1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * Copyright (c) 2023 Qualcomm Innovation Cent 3 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
4 */ 4 */
5 5
6 #include <dt-bindings/clock/qcom,rpmh.h> 6 #include <dt-bindings/clock/qcom,rpmh.h>
7 #include <dt-bindings/clock/qcom,sc8280xp-lpas <<
8 #include <dt-bindings/clock/qcom,x1e80100-disp 7 #include <dt-bindings/clock/qcom,x1e80100-dispcc.h>
9 #include <dt-bindings/clock/qcom,x1e80100-gcc. 8 #include <dt-bindings/clock/qcom,x1e80100-gcc.h>
10 #include <dt-bindings/clock/qcom,x1e80100-gpuc 9 #include <dt-bindings/clock/qcom,x1e80100-gpucc.h>
11 #include <dt-bindings/clock/qcom,x1e80100-tcsr 10 #include <dt-bindings/clock/qcom,x1e80100-tcsr.h>
12 #include <dt-bindings/dma/qcom-gpi.h> 11 #include <dt-bindings/dma/qcom-gpi.h>
13 #include <dt-bindings/interconnect/qcom,icc.h> 12 #include <dt-bindings/interconnect/qcom,icc.h>
14 #include <dt-bindings/interconnect/qcom,x1e801 13 #include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h>
15 #include <dt-bindings/interrupt-controller/arm 14 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/mailbox/qcom-ipcc.h> 15 #include <dt-bindings/mailbox/qcom-ipcc.h>
17 #include <dt-bindings/phy/phy-qcom-qmp.h> 16 #include <dt-bindings/phy/phy-qcom-qmp.h>
18 #include <dt-bindings/power/qcom,rpmhpd.h> 17 #include <dt-bindings/power/qcom,rpmhpd.h>
19 #include <dt-bindings/power/qcom-rpmpd.h> 18 #include <dt-bindings/power/qcom-rpmpd.h>
20 #include <dt-bindings/soc/qcom,gpr.h> 19 #include <dt-bindings/soc/qcom,gpr.h>
21 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 20 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
22 #include <dt-bindings/sound/qcom,q6dsp-lpass-p 21 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
23 22
24 / { 23 / {
25 interrupt-parent = <&intc>; 24 interrupt-parent = <&intc>;
26 25
27 #address-cells = <2>; 26 #address-cells = <2>;
28 #size-cells = <2>; 27 #size-cells = <2>;
29 28
30 chosen { }; 29 chosen { };
31 30
32 clocks { 31 clocks {
33 xo_board: xo-board { 32 xo_board: xo-board {
34 compatible = "fixed-cl 33 compatible = "fixed-clock";
35 clock-frequency = <768 34 clock-frequency = <76800000>;
36 #clock-cells = <0>; 35 #clock-cells = <0>;
37 }; 36 };
38 37
39 sleep_clk: sleep-clk { 38 sleep_clk: sleep-clk {
40 compatible = "fixed-cl 39 compatible = "fixed-clock";
41 clock-frequency = <320 40 clock-frequency = <32000>;
42 #clock-cells = <0>; 41 #clock-cells = <0>;
43 }; 42 };
44 43
45 bi_tcxo_div2: bi-tcxo-div2-clk 44 bi_tcxo_div2: bi-tcxo-div2-clk {
46 compatible = "fixed-fa 45 compatible = "fixed-factor-clock";
47 #clock-cells = <0>; 46 #clock-cells = <0>;
48 47
49 clocks = <&rpmhcc RPMH 48 clocks = <&rpmhcc RPMH_CXO_CLK>;
50 clock-mult = <1>; 49 clock-mult = <1>;
51 clock-div = <2>; 50 clock-div = <2>;
52 }; 51 };
53 52
54 bi_tcxo_ao_div2: bi-tcxo-ao-di 53 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
55 compatible = "fixed-fa 54 compatible = "fixed-factor-clock";
56 #clock-cells = <0>; 55 #clock-cells = <0>;
57 56
58 clocks = <&rpmhcc RPMH 57 clocks = <&rpmhcc RPMH_CXO_CLK_A>;
59 clock-mult = <1>; 58 clock-mult = <1>;
60 clock-div = <2>; 59 clock-div = <2>;
61 }; 60 };
62 }; 61 };
63 62
64 cpus { 63 cpus {
65 #address-cells = <2>; 64 #address-cells = <2>;
66 #size-cells = <0>; 65 #size-cells = <0>;
67 66
68 CPU0: cpu@0 { 67 CPU0: cpu@0 {
69 device_type = "cpu"; 68 device_type = "cpu";
70 compatible = "qcom,ory 69 compatible = "qcom,oryon";
71 reg = <0x0 0x0>; 70 reg = <0x0 0x0>;
72 enable-method = "psci" 71 enable-method = "psci";
73 next-level-cache = <&L 72 next-level-cache = <&L2_0>;
74 power-domains = <&CPU_ 73 power-domains = <&CPU_PD0>;
75 power-domain-names = " 74 power-domain-names = "psci";
76 cpu-idle-states = <&CL 75 cpu-idle-states = <&CLUSTER_C4>;
77 76
78 L2_0: l2-cache { 77 L2_0: l2-cache {
79 compatible = " 78 compatible = "cache";
80 cache-level = 79 cache-level = <2>;
81 cache-unified; 80 cache-unified;
82 }; 81 };
83 }; 82 };
84 83
85 CPU1: cpu@100 { 84 CPU1: cpu@100 {
86 device_type = "cpu"; 85 device_type = "cpu";
87 compatible = "qcom,ory 86 compatible = "qcom,oryon";
88 reg = <0x0 0x100>; 87 reg = <0x0 0x100>;
89 enable-method = "psci" 88 enable-method = "psci";
90 next-level-cache = <&L 89 next-level-cache = <&L2_0>;
91 power-domains = <&CPU_ 90 power-domains = <&CPU_PD1>;
92 power-domain-names = " 91 power-domain-names = "psci";
93 cpu-idle-states = <&CL 92 cpu-idle-states = <&CLUSTER_C4>;
94 }; 93 };
95 94
96 CPU2: cpu@200 { 95 CPU2: cpu@200 {
97 device_type = "cpu"; 96 device_type = "cpu";
98 compatible = "qcom,ory 97 compatible = "qcom,oryon";
99 reg = <0x0 0x200>; 98 reg = <0x0 0x200>;
100 enable-method = "psci" 99 enable-method = "psci";
101 next-level-cache = <&L 100 next-level-cache = <&L2_0>;
102 power-domains = <&CPU_ 101 power-domains = <&CPU_PD2>;
103 power-domain-names = " 102 power-domain-names = "psci";
104 cpu-idle-states = <&CL 103 cpu-idle-states = <&CLUSTER_C4>;
105 }; 104 };
106 105
107 CPU3: cpu@300 { 106 CPU3: cpu@300 {
108 device_type = "cpu"; 107 device_type = "cpu";
109 compatible = "qcom,ory 108 compatible = "qcom,oryon";
110 reg = <0x0 0x300>; 109 reg = <0x0 0x300>;
111 enable-method = "psci" 110 enable-method = "psci";
112 next-level-cache = <&L 111 next-level-cache = <&L2_0>;
113 power-domains = <&CPU_ 112 power-domains = <&CPU_PD3>;
114 power-domain-names = " 113 power-domain-names = "psci";
115 cpu-idle-states = <&CL 114 cpu-idle-states = <&CLUSTER_C4>;
116 }; 115 };
117 116
118 CPU4: cpu@10000 { 117 CPU4: cpu@10000 {
119 device_type = "cpu"; 118 device_type = "cpu";
120 compatible = "qcom,ory 119 compatible = "qcom,oryon";
121 reg = <0x0 0x10000>; 120 reg = <0x0 0x10000>;
122 enable-method = "psci" 121 enable-method = "psci";
123 next-level-cache = <&L 122 next-level-cache = <&L2_1>;
124 power-domains = <&CPU_ 123 power-domains = <&CPU_PD4>;
125 power-domain-names = " 124 power-domain-names = "psci";
126 cpu-idle-states = <&CL 125 cpu-idle-states = <&CLUSTER_C4>;
127 126
128 L2_1: l2-cache { 127 L2_1: l2-cache {
129 compatible = " 128 compatible = "cache";
130 cache-level = 129 cache-level = <2>;
131 cache-unified; 130 cache-unified;
132 }; 131 };
133 }; 132 };
134 133
135 CPU5: cpu@10100 { 134 CPU5: cpu@10100 {
136 device_type = "cpu"; 135 device_type = "cpu";
137 compatible = "qcom,ory 136 compatible = "qcom,oryon";
138 reg = <0x0 0x10100>; 137 reg = <0x0 0x10100>;
139 enable-method = "psci" 138 enable-method = "psci";
140 next-level-cache = <&L 139 next-level-cache = <&L2_1>;
141 power-domains = <&CPU_ 140 power-domains = <&CPU_PD5>;
142 power-domain-names = " 141 power-domain-names = "psci";
143 cpu-idle-states = <&CL 142 cpu-idle-states = <&CLUSTER_C4>;
144 }; 143 };
145 144
146 CPU6: cpu@10200 { 145 CPU6: cpu@10200 {
147 device_type = "cpu"; 146 device_type = "cpu";
148 compatible = "qcom,ory 147 compatible = "qcom,oryon";
149 reg = <0x0 0x10200>; 148 reg = <0x0 0x10200>;
150 enable-method = "psci" 149 enable-method = "psci";
151 next-level-cache = <&L 150 next-level-cache = <&L2_1>;
152 power-domains = <&CPU_ 151 power-domains = <&CPU_PD6>;
153 power-domain-names = " 152 power-domain-names = "psci";
154 cpu-idle-states = <&CL 153 cpu-idle-states = <&CLUSTER_C4>;
155 }; 154 };
156 155
157 CPU7: cpu@10300 { 156 CPU7: cpu@10300 {
158 device_type = "cpu"; 157 device_type = "cpu";
159 compatible = "qcom,ory 158 compatible = "qcom,oryon";
160 reg = <0x0 0x10300>; 159 reg = <0x0 0x10300>;
161 enable-method = "psci" 160 enable-method = "psci";
162 next-level-cache = <&L 161 next-level-cache = <&L2_1>;
163 power-domains = <&CPU_ 162 power-domains = <&CPU_PD7>;
164 power-domain-names = " 163 power-domain-names = "psci";
165 cpu-idle-states = <&CL 164 cpu-idle-states = <&CLUSTER_C4>;
166 }; 165 };
167 166
168 CPU8: cpu@20000 { 167 CPU8: cpu@20000 {
169 device_type = "cpu"; 168 device_type = "cpu";
170 compatible = "qcom,ory 169 compatible = "qcom,oryon";
171 reg = <0x0 0x20000>; 170 reg = <0x0 0x20000>;
172 enable-method = "psci" 171 enable-method = "psci";
173 next-level-cache = <&L 172 next-level-cache = <&L2_2>;
174 power-domains = <&CPU_ 173 power-domains = <&CPU_PD8>;
175 power-domain-names = " 174 power-domain-names = "psci";
176 cpu-idle-states = <&CL 175 cpu-idle-states = <&CLUSTER_C4>;
177 176
178 L2_2: l2-cache { 177 L2_2: l2-cache {
179 compatible = " 178 compatible = "cache";
180 cache-level = 179 cache-level = <2>;
181 cache-unified; 180 cache-unified;
182 }; 181 };
183 }; 182 };
184 183
185 CPU9: cpu@20100 { 184 CPU9: cpu@20100 {
186 device_type = "cpu"; 185 device_type = "cpu";
187 compatible = "qcom,ory 186 compatible = "qcom,oryon";
188 reg = <0x0 0x20100>; 187 reg = <0x0 0x20100>;
189 enable-method = "psci" 188 enable-method = "psci";
190 next-level-cache = <&L 189 next-level-cache = <&L2_2>;
191 power-domains = <&CPU_ 190 power-domains = <&CPU_PD9>;
192 power-domain-names = " 191 power-domain-names = "psci";
193 cpu-idle-states = <&CL 192 cpu-idle-states = <&CLUSTER_C4>;
194 }; 193 };
195 194
196 CPU10: cpu@20200 { 195 CPU10: cpu@20200 {
197 device_type = "cpu"; 196 device_type = "cpu";
198 compatible = "qcom,ory 197 compatible = "qcom,oryon";
199 reg = <0x0 0x20200>; 198 reg = <0x0 0x20200>;
200 enable-method = "psci" 199 enable-method = "psci";
201 next-level-cache = <&L 200 next-level-cache = <&L2_2>;
202 power-domains = <&CPU_ 201 power-domains = <&CPU_PD10>;
203 power-domain-names = " 202 power-domain-names = "psci";
204 cpu-idle-states = <&CL 203 cpu-idle-states = <&CLUSTER_C4>;
205 }; 204 };
206 205
207 CPU11: cpu@20300 { 206 CPU11: cpu@20300 {
208 device_type = "cpu"; 207 device_type = "cpu";
209 compatible = "qcom,ory 208 compatible = "qcom,oryon";
210 reg = <0x0 0x20300>; 209 reg = <0x0 0x20300>;
211 enable-method = "psci" 210 enable-method = "psci";
212 next-level-cache = <&L 211 next-level-cache = <&L2_2>;
213 power-domains = <&CPU_ 212 power-domains = <&CPU_PD11>;
214 power-domain-names = " 213 power-domain-names = "psci";
215 cpu-idle-states = <&CL 214 cpu-idle-states = <&CLUSTER_C4>;
216 }; 215 };
217 216
218 cpu-map { 217 cpu-map {
219 cluster0 { 218 cluster0 {
220 core0 { 219 core0 {
221 cpu = 220 cpu = <&CPU0>;
222 }; 221 };
223 222
224 core1 { 223 core1 {
225 cpu = 224 cpu = <&CPU1>;
226 }; 225 };
227 226
228 core2 { 227 core2 {
229 cpu = 228 cpu = <&CPU2>;
230 }; 229 };
231 230
232 core3 { 231 core3 {
233 cpu = 232 cpu = <&CPU3>;
234 }; 233 };
235 }; 234 };
236 235
237 cluster1 { 236 cluster1 {
238 core0 { 237 core0 {
239 cpu = 238 cpu = <&CPU4>;
240 }; 239 };
241 240
242 core1 { 241 core1 {
243 cpu = 242 cpu = <&CPU5>;
244 }; 243 };
245 244
246 core2 { 245 core2 {
247 cpu = 246 cpu = <&CPU6>;
248 }; 247 };
249 248
250 core3 { 249 core3 {
251 cpu = 250 cpu = <&CPU7>;
252 }; 251 };
253 }; 252 };
254 253
255 cluster2 { 254 cluster2 {
256 core0 { 255 core0 {
257 cpu = 256 cpu = <&CPU8>;
258 }; 257 };
259 258
260 core1 { 259 core1 {
261 cpu = 260 cpu = <&CPU9>;
262 }; 261 };
263 262
264 core2 { 263 core2 {
265 cpu = 264 cpu = <&CPU10>;
266 }; 265 };
267 266
268 core3 { 267 core3 {
269 cpu = 268 cpu = <&CPU11>;
270 }; 269 };
271 }; 270 };
272 }; 271 };
273 272
274 idle-states { 273 idle-states {
275 entry-method = "psci"; 274 entry-method = "psci";
276 275
277 CLUSTER_C4: cpu-sleep- 276 CLUSTER_C4: cpu-sleep-0 {
278 compatible = " 277 compatible = "arm,idle-state";
279 idle-state-nam 278 idle-state-name = "ret";
280 arm,psci-suspe 279 arm,psci-suspend-param = <0x00000004>;
281 entry-latency- 280 entry-latency-us = <180>;
282 exit-latency-u 281 exit-latency-us = <320>;
283 min-residency- 282 min-residency-us = <1000>;
284 }; 283 };
285 }; 284 };
286 285
287 domain-idle-states { 286 domain-idle-states {
288 CLUSTER_CL4: cluster-s 287 CLUSTER_CL4: cluster-sleep-0 {
289 compatible = " 288 compatible = "domain-idle-state";
290 idle-state-nam 289 idle-state-name = "l2-ret";
291 arm,psci-suspe 290 arm,psci-suspend-param = <0x01000044>;
292 entry-latency- 291 entry-latency-us = <350>;
293 exit-latency-u 292 exit-latency-us = <500>;
294 min-residency- 293 min-residency-us = <2500>;
295 }; 294 };
296 295
297 CLUSTER_CL5: cluster-s 296 CLUSTER_CL5: cluster-sleep-1 {
298 compatible = " 297 compatible = "domain-idle-state";
299 idle-state-nam 298 idle-state-name = "ret-pll-off";
300 arm,psci-suspe 299 arm,psci-suspend-param = <0x01000054>;
301 entry-latency- 300 entry-latency-us = <2200>;
302 exit-latency-u 301 exit-latency-us = <2500>;
303 min-residency- 302 min-residency-us = <7000>;
304 }; 303 };
305 }; 304 };
306 }; 305 };
307 306
308 firmware { 307 firmware {
309 scm: scm { 308 scm: scm {
310 compatible = "qcom,scm 309 compatible = "qcom,scm-x1e80100", "qcom,scm";
311 interconnects = <&aggr 310 interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS
312 &mc_v 311 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
313 }; 312 };
314 }; 313 };
315 314
316 clk_virt: interconnect-0 { 315 clk_virt: interconnect-0 {
317 compatible = "qcom,x1e80100-cl 316 compatible = "qcom,x1e80100-clk-virt";
318 #interconnect-cells = <2>; 317 #interconnect-cells = <2>;
319 qcom,bcm-voters = <&apps_bcm_v 318 qcom,bcm-voters = <&apps_bcm_voter>;
320 }; 319 };
321 320
322 mc_virt: interconnect-1 { 321 mc_virt: interconnect-1 {
323 compatible = "qcom,x1e80100-mc 322 compatible = "qcom,x1e80100-mc-virt";
324 #interconnect-cells = <2>; 323 #interconnect-cells = <2>;
325 qcom,bcm-voters = <&apps_bcm_v 324 qcom,bcm-voters = <&apps_bcm_voter>;
326 }; 325 };
327 326
328 memory@80000000 { 327 memory@80000000 {
329 device_type = "memory"; 328 device_type = "memory";
330 /* We expect the bootloader to 329 /* We expect the bootloader to fill in the size */
331 reg = <0 0x80000000 0 0>; 330 reg = <0 0x80000000 0 0>;
332 }; 331 };
333 332
334 pmu { 333 pmu {
335 compatible = "arm,armv8-pmuv3" 334 compatible = "arm,armv8-pmuv3";
336 interrupts = <GIC_PPI 7 IRQ_TY 335 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
337 }; 336 };
338 337
339 psci { 338 psci {
340 compatible = "arm,psci-1.0"; 339 compatible = "arm,psci-1.0";
341 method = "smc"; 340 method = "smc";
342 341
343 CPU_PD0: power-domain-cpu0 { 342 CPU_PD0: power-domain-cpu0 {
344 #power-domain-cells = 343 #power-domain-cells = <0>;
345 power-domains = <&CLUS 344 power-domains = <&CLUSTER_PD0>;
346 }; 345 };
347 346
348 CPU_PD1: power-domain-cpu1 { 347 CPU_PD1: power-domain-cpu1 {
349 #power-domain-cells = 348 #power-domain-cells = <0>;
350 power-domains = <&CLUS 349 power-domains = <&CLUSTER_PD0>;
351 }; 350 };
352 351
353 CPU_PD2: power-domain-cpu2 { 352 CPU_PD2: power-domain-cpu2 {
354 #power-domain-cells = 353 #power-domain-cells = <0>;
355 power-domains = <&CLUS 354 power-domains = <&CLUSTER_PD0>;
356 }; 355 };
357 356
358 CPU_PD3: power-domain-cpu3 { 357 CPU_PD3: power-domain-cpu3 {
359 #power-domain-cells = 358 #power-domain-cells = <0>;
360 power-domains = <&CLUS 359 power-domains = <&CLUSTER_PD0>;
361 }; 360 };
362 361
363 CPU_PD4: power-domain-cpu4 { 362 CPU_PD4: power-domain-cpu4 {
364 #power-domain-cells = 363 #power-domain-cells = <0>;
365 power-domains = <&CLUS 364 power-domains = <&CLUSTER_PD1>;
366 }; 365 };
367 366
368 CPU_PD5: power-domain-cpu5 { 367 CPU_PD5: power-domain-cpu5 {
369 #power-domain-cells = 368 #power-domain-cells = <0>;
370 power-domains = <&CLUS 369 power-domains = <&CLUSTER_PD1>;
371 }; 370 };
372 371
373 CPU_PD6: power-domain-cpu6 { 372 CPU_PD6: power-domain-cpu6 {
374 #power-domain-cells = 373 #power-domain-cells = <0>;
375 power-domains = <&CLUS 374 power-domains = <&CLUSTER_PD1>;
376 }; 375 };
377 376
378 CPU_PD7: power-domain-cpu7 { 377 CPU_PD7: power-domain-cpu7 {
379 #power-domain-cells = 378 #power-domain-cells = <0>;
380 power-domains = <&CLUS 379 power-domains = <&CLUSTER_PD1>;
381 }; 380 };
382 381
383 CPU_PD8: power-domain-cpu8 { 382 CPU_PD8: power-domain-cpu8 {
384 #power-domain-cells = 383 #power-domain-cells = <0>;
385 power-domains = <&CLUS 384 power-domains = <&CLUSTER_PD2>;
386 }; 385 };
387 386
388 CPU_PD9: power-domain-cpu9 { 387 CPU_PD9: power-domain-cpu9 {
389 #power-domain-cells = 388 #power-domain-cells = <0>;
390 power-domains = <&CLUS 389 power-domains = <&CLUSTER_PD2>;
391 }; 390 };
392 391
393 CPU_PD10: power-domain-cpu10 { 392 CPU_PD10: power-domain-cpu10 {
394 #power-domain-cells = 393 #power-domain-cells = <0>;
395 power-domains = <&CLUS 394 power-domains = <&CLUSTER_PD2>;
396 }; 395 };
397 396
398 CPU_PD11: power-domain-cpu11 { 397 CPU_PD11: power-domain-cpu11 {
399 #power-domain-cells = 398 #power-domain-cells = <0>;
400 power-domains = <&CLUS 399 power-domains = <&CLUSTER_PD2>;
401 }; 400 };
402 401
403 CLUSTER_PD0: power-domain-cpu- 402 CLUSTER_PD0: power-domain-cpu-cluster0 {
404 #power-domain-cells = 403 #power-domain-cells = <0>;
405 domain-idle-states = < 404 domain-idle-states = <&CLUSTER_CL4>, <&CLUSTER_CL5>;
406 power-domains = <&SYST 405 power-domains = <&SYSTEM_PD>;
407 }; 406 };
408 407
409 CLUSTER_PD1: power-domain-cpu- 408 CLUSTER_PD1: power-domain-cpu-cluster1 {
410 #power-domain-cells = 409 #power-domain-cells = <0>;
411 domain-idle-states = < 410 domain-idle-states = <&CLUSTER_CL4>, <&CLUSTER_CL5>;
412 power-domains = <&SYST 411 power-domains = <&SYSTEM_PD>;
413 }; 412 };
414 413
415 CLUSTER_PD2: power-domain-cpu- 414 CLUSTER_PD2: power-domain-cpu-cluster2 {
416 #power-domain-cells = 415 #power-domain-cells = <0>;
417 domain-idle-states = < 416 domain-idle-states = <&CLUSTER_CL4>, <&CLUSTER_CL5>;
418 power-domains = <&SYST 417 power-domains = <&SYSTEM_PD>;
419 }; 418 };
420 419
421 SYSTEM_PD: power-domain-system 420 SYSTEM_PD: power-domain-system {
422 #power-domain-cells = 421 #power-domain-cells = <0>;
423 /* TODO: system-wide i 422 /* TODO: system-wide idle states */
424 }; 423 };
425 }; 424 };
426 425
427 reserved-memory { 426 reserved-memory {
428 #address-cells = <2>; 427 #address-cells = <2>;
429 #size-cells = <2>; 428 #size-cells = <2>;
430 ranges; 429 ranges;
431 430
432 gunyah_hyp_mem: gunyah-hyp@800 431 gunyah_hyp_mem: gunyah-hyp@80000000 {
433 reg = <0x0 0x80000000 432 reg = <0x0 0x80000000 0x0 0x800000>;
434 no-map; 433 no-map;
435 }; 434 };
436 435
437 hyp_elf_package_mem: hyp-elf-p 436 hyp_elf_package_mem: hyp-elf-package@80800000 {
438 reg = <0x0 0x80800000 437 reg = <0x0 0x80800000 0x0 0x200000>;
439 no-map; 438 no-map;
440 }; 439 };
441 440
442 ncc_mem: ncc@80a00000 { 441 ncc_mem: ncc@80a00000 {
443 reg = <0x0 0x80a00000 442 reg = <0x0 0x80a00000 0x0 0x400000>;
444 no-map; 443 no-map;
445 }; 444 };
446 445
447 cpucp_log_mem: cpucp-log@80e00 446 cpucp_log_mem: cpucp-log@80e00000 {
448 reg = <0x0 0x80e00000 447 reg = <0x0 0x80e00000 0x0 0x40000>;
449 no-map; 448 no-map;
450 }; 449 };
451 450
452 cpucp_mem: cpucp@80e40000 { 451 cpucp_mem: cpucp@80e40000 {
453 reg = <0x0 0x80e40000 452 reg = <0x0 0x80e40000 0x0 0x540000>;
454 no-map; 453 no-map;
455 }; 454 };
456 455
457 reserved-region@81380000 { 456 reserved-region@81380000 {
458 reg = <0x0 0x81380000 457 reg = <0x0 0x81380000 0x0 0x80000>;
459 no-map; 458 no-map;
460 }; 459 };
461 460
462 tags_mem: tags-region@81400000 461 tags_mem: tags-region@81400000 {
463 reg = <0x0 0x81400000 462 reg = <0x0 0x81400000 0x0 0x1a0000>;
464 no-map; 463 no-map;
465 }; 464 };
466 465
467 xbl_dtlog_mem: xbl-dtlog@81a00 466 xbl_dtlog_mem: xbl-dtlog@81a00000 {
468 reg = <0x0 0x81a00000 467 reg = <0x0 0x81a00000 0x0 0x40000>;
469 no-map; 468 no-map;
470 }; 469 };
471 470
472 xbl_ramdump_mem: xbl-ramdump@8 471 xbl_ramdump_mem: xbl-ramdump@81a40000 {
473 reg = <0x0 0x81a40000 472 reg = <0x0 0x81a40000 0x0 0x1c0000>;
474 no-map; 473 no-map;
475 }; 474 };
476 475
477 aop_image_mem: aop-image@81c00 476 aop_image_mem: aop-image@81c00000 {
478 reg = <0x0 0x81c00000 477 reg = <0x0 0x81c00000 0x0 0x60000>;
479 no-map; 478 no-map;
480 }; 479 };
481 480
482 aop_cmd_db_mem: aop-cmd-db@81c 481 aop_cmd_db_mem: aop-cmd-db@81c60000 {
483 compatible = "qcom,cmd 482 compatible = "qcom,cmd-db";
484 reg = <0x0 0x81c60000 483 reg = <0x0 0x81c60000 0x0 0x20000>;
485 no-map; 484 no-map;
486 }; 485 };
487 486
488 aop_config_mem: aop-config@81c 487 aop_config_mem: aop-config@81c80000 {
489 reg = <0x0 0x81c80000 488 reg = <0x0 0x81c80000 0x0 0x20000>;
490 no-map; 489 no-map;
491 }; 490 };
492 491
493 tme_crash_dump_mem: tme-crash- 492 tme_crash_dump_mem: tme-crash-dump@81ca0000 {
494 reg = <0x0 0x81ca0000 493 reg = <0x0 0x81ca0000 0x0 0x40000>;
495 no-map; 494 no-map;
496 }; 495 };
497 496
498 tme_log_mem: tme-log@81ce0000 497 tme_log_mem: tme-log@81ce0000 {
499 reg = <0x0 0x81ce0000 498 reg = <0x0 0x81ce0000 0x0 0x4000>;
500 no-map; 499 no-map;
501 }; 500 };
502 501
503 uefi_log_mem: uefi-log@81ce400 502 uefi_log_mem: uefi-log@81ce4000 {
504 reg = <0x0 0x81ce4000 503 reg = <0x0 0x81ce4000 0x0 0x10000>;
505 no-map; 504 no-map;
506 }; 505 };
507 506
508 secdata_apss_mem: secdata-apss 507 secdata_apss_mem: secdata-apss@81cff000 {
509 reg = <0x0 0x81cff000 508 reg = <0x0 0x81cff000 0x0 0x1000>;
510 no-map; 509 no-map;
511 }; 510 };
512 511
513 pdp_ns_shared_mem: pdp-ns-shar 512 pdp_ns_shared_mem: pdp-ns-shared@81e00000 {
514 reg = <0x0 0x81e00000 513 reg = <0x0 0x81e00000 0x0 0x100000>;
515 no-map; 514 no-map;
516 }; 515 };
517 516
518 gpu_prr_mem: gpu-prr@81f00000 517 gpu_prr_mem: gpu-prr@81f00000 {
519 reg = <0x0 0x81f00000 518 reg = <0x0 0x81f00000 0x0 0x10000>;
520 no-map; 519 no-map;
521 }; 520 };
522 521
523 tpm_control_mem: tpm-control@8 522 tpm_control_mem: tpm-control@81f10000 {
524 reg = <0x0 0x81f10000 523 reg = <0x0 0x81f10000 0x0 0x10000>;
525 no-map; 524 no-map;
526 }; 525 };
527 526
528 usb_ucsi_shared_mem: usb-ucsi- 527 usb_ucsi_shared_mem: usb-ucsi-shared@81f20000 {
529 reg = <0x0 0x81f20000 528 reg = <0x0 0x81f20000 0x0 0x10000>;
530 no-map; 529 no-map;
531 }; 530 };
532 531
533 pld_pep_mem: pld-pep@81f30000 532 pld_pep_mem: pld-pep@81f30000 {
534 reg = <0x0 0x81f30000 533 reg = <0x0 0x81f30000 0x0 0x6000>;
535 no-map; 534 no-map;
536 }; 535 };
537 536
538 pld_gmu_mem: pld-gmu@81f36000 537 pld_gmu_mem: pld-gmu@81f36000 {
539 reg = <0x0 0x81f36000 538 reg = <0x0 0x81f36000 0x0 0x1000>;
540 no-map; 539 no-map;
541 }; 540 };
542 541
543 pld_pdp_mem: pld-pdp@81f37000 542 pld_pdp_mem: pld-pdp@81f37000 {
544 reg = <0x0 0x81f37000 543 reg = <0x0 0x81f37000 0x0 0x1000>;
545 no-map; 544 no-map;
546 }; 545 };
547 546
548 tz_stat_mem: tz-stat@82700000 547 tz_stat_mem: tz-stat@82700000 {
549 reg = <0x0 0x82700000 548 reg = <0x0 0x82700000 0x0 0x100000>;
550 no-map; 549 no-map;
551 }; 550 };
552 551
553 xbl_tmp_buffer_mem: xbl-tmp-bu 552 xbl_tmp_buffer_mem: xbl-tmp-buffer@82800000 {
554 reg = <0x0 0x82800000 553 reg = <0x0 0x82800000 0x0 0xc00000>;
555 no-map; 554 no-map;
556 }; 555 };
557 556
558 adsp_rpc_remote_heap_mem: adsp 557 adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@84b00000 {
559 reg = <0x0 0x84b00000 558 reg = <0x0 0x84b00000 0x0 0x800000>;
560 no-map; 559 no-map;
561 }; 560 };
562 561
563 spu_secure_shared_memory_mem: 562 spu_secure_shared_memory_mem: spu-secure-shared-memory@85300000 {
564 reg = <0x0 0x85300000 563 reg = <0x0 0x85300000 0x0 0x80000>;
565 no-map; 564 no-map;
566 }; 565 };
567 566
568 adsp_boot_dtb_mem: adsp-boot-d 567 adsp_boot_dtb_mem: adsp-boot-dtb@866c0000 {
569 reg = <0x0 0x866c0000 568 reg = <0x0 0x866c0000 0x0 0x40000>;
570 no-map; 569 no-map;
571 }; 570 };
572 571
573 spss_region_mem: spss-region@8 572 spss_region_mem: spss-region@86700000 {
574 reg = <0x0 0x86700000 573 reg = <0x0 0x86700000 0x0 0x400000>;
575 no-map; 574 no-map;
576 }; 575 };
577 576
578 adsp_boot_mem: adsp-boot@86b00 577 adsp_boot_mem: adsp-boot@86b00000 {
579 reg = <0x0 0x86b00000 578 reg = <0x0 0x86b00000 0x0 0xc00000>;
580 no-map; 579 no-map;
581 }; 580 };
582 581
583 video_mem: video@87700000 { 582 video_mem: video@87700000 {
584 reg = <0x0 0x87700000 583 reg = <0x0 0x87700000 0x0 0x700000>;
585 no-map; 584 no-map;
586 }; 585 };
587 586
588 adspslpi_mem: adspslpi@87e0000 587 adspslpi_mem: adspslpi@87e00000 {
589 reg = <0x0 0x87e00000 588 reg = <0x0 0x87e00000 0x0 0x3a00000>;
590 no-map; 589 no-map;
591 }; 590 };
592 591
593 q6_adsp_dtb_mem: q6-adsp-dtb@8 592 q6_adsp_dtb_mem: q6-adsp-dtb@8b800000 {
594 reg = <0x0 0x8b800000 593 reg = <0x0 0x8b800000 0x0 0x80000>;
595 no-map; 594 no-map;
596 }; 595 };
597 596
598 cdsp_mem: cdsp@8b900000 { 597 cdsp_mem: cdsp@8b900000 {
599 reg = <0x0 0x8b900000 598 reg = <0x0 0x8b900000 0x0 0x2000000>;
600 no-map; 599 no-map;
601 }; 600 };
602 601
603 q6_cdsp_dtb_mem: q6-cdsp-dtb@8 602 q6_cdsp_dtb_mem: q6-cdsp-dtb@8d900000 {
604 reg = <0x0 0x8d900000 603 reg = <0x0 0x8d900000 0x0 0x80000>;
605 no-map; 604 no-map;
606 }; 605 };
607 606
608 gpu_microcode_mem: gpu-microco 607 gpu_microcode_mem: gpu-microcode@8d9fe000 {
609 reg = <0x0 0x8d9fe000 608 reg = <0x0 0x8d9fe000 0x0 0x2000>;
610 no-map; 609 no-map;
611 }; 610 };
612 611
613 cvp_mem: cvp@8da00000 { 612 cvp_mem: cvp@8da00000 {
614 reg = <0x0 0x8da00000 613 reg = <0x0 0x8da00000 0x0 0x700000>;
615 no-map; 614 no-map;
616 }; 615 };
617 616
618 camera_mem: camera@8e100000 { 617 camera_mem: camera@8e100000 {
619 reg = <0x0 0x8e100000 618 reg = <0x0 0x8e100000 0x0 0x800000>;
620 no-map; 619 no-map;
621 }; 620 };
622 621
623 av1_encoder_mem: av1-encoder@8 622 av1_encoder_mem: av1-encoder@8e900000 {
624 reg = <0x0 0x8e900000 623 reg = <0x0 0x8e900000 0x0 0x700000>;
625 no-map; 624 no-map;
626 }; 625 };
627 626
628 reserved-region@8f000000 { 627 reserved-region@8f000000 {
629 reg = <0x0 0x8f000000 628 reg = <0x0 0x8f000000 0x0 0xa00000>;
630 no-map; 629 no-map;
631 }; 630 };
632 631
633 wpss_mem: wpss@8fa00000 { 632 wpss_mem: wpss@8fa00000 {
634 reg = <0x0 0x8fa00000 633 reg = <0x0 0x8fa00000 0x0 0x1900000>;
635 no-map; 634 no-map;
636 }; 635 };
637 636
638 q6_wpss_dtb_mem: q6-wpss-dtb@9 637 q6_wpss_dtb_mem: q6-wpss-dtb@91300000 {
639 reg = <0x0 0x91300000 638 reg = <0x0 0x91300000 0x0 0x80000>;
640 no-map; 639 no-map;
641 }; 640 };
642 641
643 xbl_sc_mem: xbl-sc@d8000000 { 642 xbl_sc_mem: xbl-sc@d8000000 {
644 reg = <0x0 0xd8000000 643 reg = <0x0 0xd8000000 0x0 0x40000>;
645 no-map; 644 no-map;
646 }; 645 };
647 646
648 reserved-region@d8040000 { 647 reserved-region@d8040000 {
649 reg = <0x0 0xd8040000 648 reg = <0x0 0xd8040000 0x0 0xa0000>;
650 no-map; 649 no-map;
651 }; 650 };
652 651
653 qtee_mem: qtee@d80e0000 { 652 qtee_mem: qtee@d80e0000 {
654 reg = <0x0 0xd80e0000 653 reg = <0x0 0xd80e0000 0x0 0x520000>;
655 no-map; 654 no-map;
656 }; 655 };
657 656
658 ta_mem: ta@d8600000 { 657 ta_mem: ta@d8600000 {
659 reg = <0x0 0xd8600000 658 reg = <0x0 0xd8600000 0x0 0x8a00000>;
660 no-map; 659 no-map;
661 }; 660 };
662 661
663 tags_mem1: tags@e1000000 { 662 tags_mem1: tags@e1000000 {
664 reg = <0x0 0xe1000000 663 reg = <0x0 0xe1000000 0x0 0x26a0000>;
665 no-map; 664 no-map;
666 }; 665 };
667 666
668 llcc_lpi_mem: llcc-lpi@ff80000 667 llcc_lpi_mem: llcc-lpi@ff800000 {
669 reg = <0x0 0xff800000 668 reg = <0x0 0xff800000 0x0 0x600000>;
670 no-map; 669 no-map;
671 }; 670 };
672 671
673 smem_mem: smem@ffe00000 { 672 smem_mem: smem@ffe00000 {
674 compatible = "qcom,sme 673 compatible = "qcom,smem";
675 reg = <0x0 0xffe00000 674 reg = <0x0 0xffe00000 0x0 0x200000>;
676 hwlocks = <&tcsr_mutex 675 hwlocks = <&tcsr_mutex 3>;
677 no-map; 676 no-map;
678 }; 677 };
679 }; 678 };
680 679
681 smp2p-adsp { 680 smp2p-adsp {
682 compatible = "qcom,smp2p"; 681 compatible = "qcom,smp2p";
683 682
684 interrupts-extended = <&ipcc I 683 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
685 I 684 IPCC_MPROC_SIGNAL_SMP2P
686 I 685 IRQ_TYPE_EDGE_RISING>;
687 686
688 mboxes = <&ipcc IPCC_CLIENT_LP 687 mboxes = <&ipcc IPCC_CLIENT_LPASS
689 IPCC_MPROC_SIG 688 IPCC_MPROC_SIGNAL_SMP2P>;
690 689
691 qcom,smem = <443>, <429>; 690 qcom,smem = <443>, <429>;
692 qcom,local-pid = <0>; 691 qcom,local-pid = <0>;
693 qcom,remote-pid = <2>; 692 qcom,remote-pid = <2>;
694 693
695 smp2p_adsp_out: master-kernel 694 smp2p_adsp_out: master-kernel {
696 qcom,entry-name = "mas 695 qcom,entry-name = "master-kernel";
697 #qcom,smem-state-cells 696 #qcom,smem-state-cells = <1>;
698 }; 697 };
699 698
700 smp2p_adsp_in: slave-kernel { 699 smp2p_adsp_in: slave-kernel {
701 qcom,entry-name = "sla 700 qcom,entry-name = "slave-kernel";
702 interrupt-controller; 701 interrupt-controller;
703 #interrupt-cells = <2> 702 #interrupt-cells = <2>;
704 }; 703 };
705 }; 704 };
706 705
707 smp2p-cdsp { 706 smp2p-cdsp {
708 compatible = "qcom,smp2p"; 707 compatible = "qcom,smp2p";
709 708
710 interrupts-extended = <&ipcc I 709 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
711 I 710 IPCC_MPROC_SIGNAL_SMP2P
712 I 711 IRQ_TYPE_EDGE_RISING>;
713 712
714 mboxes = <&ipcc IPCC_CLIENT_CD 713 mboxes = <&ipcc IPCC_CLIENT_CDSP
715 IPCC_MPROC_SIG 714 IPCC_MPROC_SIGNAL_SMP2P>;
716 715
717 qcom,smem = <94>, <432>; 716 qcom,smem = <94>, <432>;
718 qcom,local-pid = <0>; 717 qcom,local-pid = <0>;
719 qcom,remote-pid = <5>; 718 qcom,remote-pid = <5>;
720 719
721 smp2p_cdsp_out: master-kernel 720 smp2p_cdsp_out: master-kernel {
722 qcom,entry-name = "mas 721 qcom,entry-name = "master-kernel";
723 #qcom,smem-state-cells 722 #qcom,smem-state-cells = <1>;
724 }; 723 };
725 724
726 smp2p_cdsp_in: slave-kernel { 725 smp2p_cdsp_in: slave-kernel {
727 qcom,entry-name = "sla 726 qcom,entry-name = "slave-kernel";
728 interrupt-controller; 727 interrupt-controller;
729 #interrupt-cells = <2> 728 #interrupt-cells = <2>;
730 }; 729 };
731 }; 730 };
732 731
733 soc: soc@0 { 732 soc: soc@0 {
734 compatible = "simple-bus"; 733 compatible = "simple-bus";
735 734
736 #address-cells = <2>; 735 #address-cells = <2>;
737 #size-cells = <2>; 736 #size-cells = <2>;
738 dma-ranges = <0 0 0 0 0x10 0>; 737 dma-ranges = <0 0 0 0 0x10 0>;
739 ranges = <0 0 0 0 0x10 0>; 738 ranges = <0 0 0 0 0x10 0>;
740 739
741 gcc: clock-controller@100000 { 740 gcc: clock-controller@100000 {
742 compatible = "qcom,x1e 741 compatible = "qcom,x1e80100-gcc";
743 reg = <0 0x00100000 0 742 reg = <0 0x00100000 0 0x200000>;
744 743
745 clocks = <&bi_tcxo_div 744 clocks = <&bi_tcxo_div2>,
746 <&sleep_clk>, 745 <&sleep_clk>,
747 <0>, 746 <0>,
748 <&pcie4_phy>, 747 <&pcie4_phy>,
749 <&pcie5_phy>, !! 748 <0>,
750 <&pcie6a_phy> 749 <&pcie6a_phy>,
751 <0>, 750 <0>,
752 <&usb_1_ss0_q 751 <&usb_1_ss0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
753 <&usb_1_ss1_q 752 <&usb_1_ss1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
754 <&usb_1_ss2_q 753 <&usb_1_ss2_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
755 754
756 power-domains = <&rpmh 755 power-domains = <&rpmhpd RPMHPD_CX>;
757 #clock-cells = <1>; 756 #clock-cells = <1>;
758 #reset-cells = <1>; 757 #reset-cells = <1>;
759 #power-domain-cells = 758 #power-domain-cells = <1>;
760 }; 759 };
761 760
762 ipcc: mailbox@408000 { 761 ipcc: mailbox@408000 {
763 compatible = "qcom,x1e 762 compatible = "qcom,x1e80100-ipcc", "qcom,ipcc";
764 reg = <0 0x00408000 0 763 reg = <0 0x00408000 0 0x1000>;
765 764
766 interrupts = <GIC_SPI 765 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
767 interrupt-controller; 766 interrupt-controller;
768 #interrupt-cells = <3> 767 #interrupt-cells = <3>;
769 768
770 #mbox-cells = <2>; 769 #mbox-cells = <2>;
771 }; 770 };
772 771
773 gpi_dma2: dma-controller@80000 772 gpi_dma2: dma-controller@800000 {
774 compatible = "qcom,x1e 773 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma";
775 reg = <0 0x00800000 0 774 reg = <0 0x00800000 0 0x60000>;
776 775
777 interrupts = <GIC_SPI 776 interrupts = <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>,
778 <GIC_SPI 777 <GIC_SPI 789 IRQ_TYPE_LEVEL_HIGH>,
779 <GIC_SPI 778 <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>,
780 <GIC_SPI 779 <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>,
781 <GIC_SPI 780 <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>,
782 <GIC_SPI 781 <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>,
783 <GIC_SPI 782 <GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>,
784 <GIC_SPI 783 <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>,
785 <GIC_SPI 784 <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>,
786 <GIC_SPI 785 <GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH>,
787 <GIC_SPI 786 <GIC_SPI 798 IRQ_TYPE_LEVEL_HIGH>,
788 <GIC_SPI 787 <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH>;
789 788
790 dma-channels = <12>; 789 dma-channels = <12>;
791 dma-channel-mask = <0x 790 dma-channel-mask = <0x3e>;
792 #dma-cells = <3>; 791 #dma-cells = <3>;
793 792
794 iommus = <&apps_smmu 0 793 iommus = <&apps_smmu 0x436 0x0>;
795 794
796 status = "disabled"; 795 status = "disabled";
797 }; 796 };
798 797
799 qupv3_2: geniqup@8c0000 { 798 qupv3_2: geniqup@8c0000 {
800 compatible = "qcom,gen 799 compatible = "qcom,geni-se-qup";
801 reg = <0 0x008c0000 0 800 reg = <0 0x008c0000 0 0x2000>;
802 801
803 clocks = <&gcc GCC_QUP 802 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
804 <&gcc GCC_QUP 803 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
805 clock-names = "m-ahb", 804 clock-names = "m-ahb",
806 "s-ahb"; 805 "s-ahb";
807 806
808 iommus = <&apps_smmu 0 807 iommus = <&apps_smmu 0x423 0x0>;
809 808
810 #address-cells = <2>; 809 #address-cells = <2>;
811 #size-cells = <2>; 810 #size-cells = <2>;
812 ranges; 811 ranges;
813 812
814 status = "disabled"; 813 status = "disabled";
815 814
816 i2c16: i2c@880000 { 815 i2c16: i2c@880000 {
817 compatible = " 816 compatible = "qcom,geni-i2c";
818 reg = <0 0x008 817 reg = <0 0x00880000 0 0x4000>;
819 818
820 interrupts = < 819 interrupts = <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>;
821 820
822 clocks = <&gcc 821 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
823 clock-names = 822 clock-names = "se";
824 823
825 interconnects 824 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
826 825 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
827 826 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
828 827 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
829 828 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
830 829 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
831 interconnect-n 830 interconnect-names = "qup-core",
832 831 "qup-config",
833 832 "qup-memory";
834 833
835 dmas = <&gpi_d 834 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
836 <&gpi_d 835 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
837 dma-names = "t 836 dma-names = "tx",
838 "r 837 "rx";
839 838
840 pinctrl-0 = <& 839 pinctrl-0 = <&qup_i2c16_data_clk>;
841 pinctrl-names 840 pinctrl-names = "default";
842 841
843 #address-cells 842 #address-cells = <1>;
844 #size-cells = 843 #size-cells = <0>;
845 844
846 status = "disa 845 status = "disabled";
847 }; 846 };
848 847
849 spi16: spi@880000 { 848 spi16: spi@880000 {
850 compatible = " 849 compatible = "qcom,geni-spi";
851 reg = <0 0x008 850 reg = <0 0x00880000 0 0x4000>;
852 851
853 interrupts = < 852 interrupts = <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>;
854 853
855 clocks = <&gcc 854 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
856 clock-names = 855 clock-names = "se";
857 856
858 interconnects 857 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
859 858 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
860 859 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
861 860 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
862 861 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
863 862 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
864 interconnect-n 863 interconnect-names = "qup-core",
865 864 "qup-config",
866 865 "qup-memory";
867 866
868 dmas = <&gpi_d 867 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
869 <&gpi_d 868 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
870 dma-names = "t 869 dma-names = "tx",
871 "r 870 "rx";
872 871
873 pinctrl-0 = <& 872 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>;
874 pinctrl-names 873 pinctrl-names = "default";
875 874
876 #address-cells 875 #address-cells = <1>;
877 #size-cells = 876 #size-cells = <0>;
878 877
879 status = "disa 878 status = "disabled";
880 }; 879 };
881 880
882 i2c17: i2c@884000 { 881 i2c17: i2c@884000 {
883 compatible = " 882 compatible = "qcom,geni-i2c";
884 reg = <0 0x008 883 reg = <0 0x00884000 0 0x4000>;
885 884
886 interrupts = < 885 interrupts = <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>;
887 886
888 clocks = <&gcc 887 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
889 clock-names = 888 clock-names = "se";
890 889
891 interconnects 890 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
892 891 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
893 892 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
894 893 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
895 894 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
896 895 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
897 interconnect-n 896 interconnect-names = "qup-core",
898 897 "qup-config",
899 898 "qup-memory";
900 899
901 dmas = <&gpi_d 900 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
902 <&gpi_d 901 <&gpi_dma2 1 1 QCOM_GPI_I2C>;
903 dma-names = "t 902 dma-names = "tx",
904 "r 903 "rx";
905 904
906 pinctrl-0 = <& 905 pinctrl-0 = <&qup_i2c17_data_clk>;
907 pinctrl-names 906 pinctrl-names = "default";
908 907
909 #address-cells 908 #address-cells = <1>;
910 #size-cells = 909 #size-cells = <0>;
911 910
912 status = "disa 911 status = "disabled";
913 }; 912 };
914 913
915 spi17: spi@884000 { 914 spi17: spi@884000 {
916 compatible = " 915 compatible = "qcom,geni-spi";
917 reg = <0 0x008 916 reg = <0 0x00884000 0 0x4000>;
918 917
919 interrupts = < 918 interrupts = <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>;
920 919
921 clocks = <&gcc 920 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
922 clock-names = 921 clock-names = "se";
923 922
924 interconnects 923 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
925 924 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
926 925 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
927 926 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
928 927 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
929 928 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
930 interconnect-n 929 interconnect-names = "qup-core",
931 930 "qup-config",
932 931 "qup-memory";
933 932
934 dmas = <&gpi_d 933 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
935 <&gpi_d 934 <&gpi_dma2 1 1 QCOM_GPI_SPI>;
936 dma-names = "t 935 dma-names = "tx",
937 "r 936 "rx";
938 937
939 pinctrl-0 = <& 938 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>;
940 pinctrl-names 939 pinctrl-names = "default";
941 940
942 #address-cells 941 #address-cells = <1>;
943 #size-cells = 942 #size-cells = <0>;
944 943
945 status = "disa 944 status = "disabled";
946 }; 945 };
947 946
948 i2c18: i2c@888000 { 947 i2c18: i2c@888000 {
949 compatible = " 948 compatible = "qcom,geni-i2c";
950 reg = <0 0x008 949 reg = <0 0x00888000 0 0x4000>;
951 950
952 interrupts = < 951 interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>;
953 952
954 clocks = <&gcc 953 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
955 clock-names = 954 clock-names = "se";
956 955
957 interconnects 956 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
958 957 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
959 958 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
960 959 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
961 960 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
962 961 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
963 interconnect-n 962 interconnect-names = "qup-core",
964 963 "qup-config",
965 964 "qup-memory";
966 965
967 dmas = <&gpi_d 966 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
968 <&gpi_d 967 <&gpi_dma2 1 2 QCOM_GPI_I2C>;
969 dma-names = "t 968 dma-names = "tx",
970 "r 969 "rx";
971 970
972 pinctrl-0 = <& 971 pinctrl-0 = <&qup_i2c18_data_clk>;
973 pinctrl-names 972 pinctrl-names = "default";
974 973
975 #address-cells 974 #address-cells = <1>;
976 #size-cells = 975 #size-cells = <0>;
977 976
978 status = "disa 977 status = "disabled";
979 }; 978 };
980 979
981 spi18: spi@888000 { 980 spi18: spi@888000 {
982 compatible = " 981 compatible = "qcom,geni-spi";
983 reg = <0 0x008 982 reg = <0 0x00888000 0 0x4000>;
984 983
985 interrupts = < 984 interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>;
986 985
987 clocks = <&gcc 986 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
988 clock-names = 987 clock-names = "se";
989 988
990 interconnects 989 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
991 990 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
992 991 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
993 992 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
994 993 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
995 994 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
996 interconnect-n 995 interconnect-names = "qup-core",
997 996 "qup-config",
998 997 "qup-memory";
999 998
1000 dmas = <&gpi_ 999 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
1001 <&gpi_ 1000 <&gpi_dma2 1 2 QCOM_GPI_SPI>;
1002 dma-names = " 1001 dma-names = "tx",
1003 " 1002 "rx";
1004 1003
1005 pinctrl-0 = < 1004 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>;
1006 pinctrl-names 1005 pinctrl-names = "default";
1007 1006
1008 #address-cell 1007 #address-cells = <1>;
1009 #size-cells = 1008 #size-cells = <0>;
1010 1009
1011 status = "dis 1010 status = "disabled";
1012 }; 1011 };
1013 1012
1014 i2c19: i2c@88c000 { 1013 i2c19: i2c@88c000 {
1015 compatible = 1014 compatible = "qcom,geni-i2c";
1016 reg = <0 0x00 1015 reg = <0 0x0088c000 0 0x4000>;
1017 1016
1018 interrupts = 1017 interrupts = <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>;
1019 1018
1020 clocks = <&gc 1019 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1021 clock-names = 1020 clock-names = "se";
1022 1021
1023 interconnects 1022 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1024 1023 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1025 1024 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1026 1025 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1027 1026 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1028 1027 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1029 interconnect- 1028 interconnect-names = "qup-core",
1030 1029 "qup-config",
1031 1030 "qup-memory";
1032 1031
1033 dmas = <&gpi_ 1032 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
1034 <&gpi_ 1033 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
1035 dma-names = " 1034 dma-names = "tx",
1036 " 1035 "rx";
1037 1036
1038 pinctrl-0 = < 1037 pinctrl-0 = <&qup_i2c19_data_clk>;
1039 pinctrl-names 1038 pinctrl-names = "default";
1040 1039
1041 #address-cell 1040 #address-cells = <1>;
1042 #size-cells = 1041 #size-cells = <0>;
1043 1042
1044 status = "dis 1043 status = "disabled";
1045 }; 1044 };
1046 1045
1047 spi19: spi@88c000 { 1046 spi19: spi@88c000 {
1048 compatible = 1047 compatible = "qcom,geni-spi";
1049 reg = <0 0x00 1048 reg = <0 0x0088c000 0 0x4000>;
1050 1049
1051 interrupts = 1050 interrupts = <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>;
1052 1051
1053 clocks = <&gc 1052 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1054 clock-names = 1053 clock-names = "se";
1055 1054
1056 interconnects 1055 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1057 1056 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1058 1057 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1059 1058 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1060 1059 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1061 1060 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1062 interconnect- 1061 interconnect-names = "qup-core",
1063 1062 "qup-config",
1064 1063 "qup-memory";
1065 1064
1066 dmas = <&gpi_ 1065 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
1067 <&gpi_ 1066 <&gpi_dma2 1 3 QCOM_GPI_SPI>;
1068 dma-names = " 1067 dma-names = "tx",
1069 " 1068 "rx";
1070 1069
1071 pinctrl-0 = < 1070 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>;
1072 pinctrl-names 1071 pinctrl-names = "default";
1073 1072
1074 #address-cell 1073 #address-cells = <1>;
1075 #size-cells = 1074 #size-cells = <0>;
1076 1075
1077 status = "dis 1076 status = "disabled";
1078 }; 1077 };
1079 1078
1080 i2c20: i2c@890000 { 1079 i2c20: i2c@890000 {
1081 compatible = 1080 compatible = "qcom,geni-i2c";
1082 reg = <0 0x00 1081 reg = <0 0x00890000 0 0x4000>;
1083 1082
1084 interrupts = 1083 interrupts = <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>;
1085 1084
1086 clocks = <&gc 1085 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1087 clock-names = 1086 clock-names = "se";
1088 1087
1089 interconnects 1088 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1090 1089 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1091 1090 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1092 1091 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1093 1092 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1094 1093 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1095 interconnect- 1094 interconnect-names = "qup-core",
1096 1095 "qup-config",
1097 1096 "qup-memory";
1098 1097
1099 dmas = <&gpi_ 1098 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1100 <&gpi_ 1099 <&gpi_dma2 1 4 QCOM_GPI_I2C>;
1101 dma-names = " 1100 dma-names = "tx",
1102 " 1101 "rx";
1103 1102
1104 pinctrl-0 = < 1103 pinctrl-0 = <&qup_i2c20_data_clk>;
1105 pinctrl-names 1104 pinctrl-names = "default";
1106 1105
1107 #address-cell 1106 #address-cells = <1>;
1108 #size-cells = 1107 #size-cells = <0>;
1109 1108
1110 status = "dis 1109 status = "disabled";
1111 }; 1110 };
1112 1111
1113 spi20: spi@890000 { 1112 spi20: spi@890000 {
1114 compatible = 1113 compatible = "qcom,geni-spi";
1115 reg = <0 0x00 1114 reg = <0 0x00890000 0 0x4000>;
1116 1115
1117 interrupts = 1116 interrupts = <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>;
1118 1117
1119 clocks = <&gc 1118 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1120 clock-names = 1119 clock-names = "se";
1121 1120
1122 interconnects 1121 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1123 1122 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1124 1123 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1125 1124 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1126 1125 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1127 1126 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1128 interconnect- 1127 interconnect-names = "qup-core",
1129 1128 "qup-config",
1130 1129 "qup-memory";
1131 1130
1132 dmas = <&gpi_ 1131 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
1133 <&gpi_ 1132 <&gpi_dma2 1 4 QCOM_GPI_SPI>;
1134 dma-names = " 1133 dma-names = "tx",
1135 " 1134 "rx";
1136 1135
1137 pinctrl-0 = < 1136 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>;
1138 pinctrl-names 1137 pinctrl-names = "default";
1139 1138
1140 #address-cell 1139 #address-cells = <1>;
1141 #size-cells = 1140 #size-cells = <0>;
1142 1141
1143 status = "dis 1142 status = "disabled";
1144 }; 1143 };
1145 1144
1146 i2c21: i2c@894000 { 1145 i2c21: i2c@894000 {
1147 compatible = 1146 compatible = "qcom,geni-i2c";
1148 reg = <0 0x00 1147 reg = <0 0x00894000 0 0x4000>;
1149 1148
1150 interrupts = 1149 interrupts = <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>;
1151 1150
1152 clocks = <&gc 1151 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1153 clock-names = 1152 clock-names = "se";
1154 1153
1155 interconnects 1154 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1156 1155 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1157 1156 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1158 1157 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1159 1158 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1160 1159 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1161 interconnect- 1160 interconnect-names = "qup-core",
1162 1161 "qup-config",
1163 1162 "qup-memory";
1164 1163
1165 dmas = <&gpi_ 1164 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1166 <&gpi_ 1165 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1167 dma-names = " 1166 dma-names = "tx",
1168 " 1167 "rx";
1169 1168
1170 pinctrl-0 = < 1169 pinctrl-0 = <&qup_i2c21_data_clk>;
1171 pinctrl-names 1170 pinctrl-names = "default";
1172 1171
1173 #address-cell 1172 #address-cells = <1>;
1174 #size-cells = 1173 #size-cells = <0>;
1175 1174
1176 status = "dis 1175 status = "disabled";
1177 }; 1176 };
1178 1177
1179 spi21: spi@894000 { 1178 spi21: spi@894000 {
1180 compatible = 1179 compatible = "qcom,geni-spi";
1181 reg = <0 0x00 1180 reg = <0 0x00894000 0 0x4000>;
1182 1181
1183 interrupts = 1182 interrupts = <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>;
1184 1183
1185 clocks = <&gc 1184 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1186 clock-names = 1185 clock-names = "se";
1187 1186
1188 interconnects 1187 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1189 1188 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1190 1189 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1191 1190 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1192 1191 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1193 1192 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1194 interconnect- 1193 interconnect-names = "qup-core",
1195 1194 "qup-config",
1196 1195 "qup-memory";
1197 1196
1198 dmas = <&gpi_ 1197 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1199 <&gpi_ 1198 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1200 dma-names = " 1199 dma-names = "tx",
1201 " 1200 "rx";
1202 1201
1203 pinctrl-0 = < 1202 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>;
1204 pinctrl-names 1203 pinctrl-names = "default";
1205 1204
1206 #address-cell 1205 #address-cells = <1>;
1207 #size-cells = 1206 #size-cells = <0>;
1208 1207
1209 status = "dis 1208 status = "disabled";
1210 }; 1209 };
1211 1210
1212 uart21: serial@894000 1211 uart21: serial@894000 {
1213 compatible = 1212 compatible = "qcom,geni-uart";
1214 reg = <0 0x00 1213 reg = <0 0x00894000 0 0x4000>;
1215 1214
1216 interrupts = 1215 interrupts = <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>;
1217 1216
1218 clocks = <&gc 1217 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1219 clock-names = 1218 clock-names = "se";
1220 1219
1221 interconnects 1220 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1222 1221 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1223 1222 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1224 1223 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
1225 interconnect- 1224 interconnect-names = "qup-core",
1226 1225 "qup-config";
1227 1226
1228 pinctrl-0 = < 1227 pinctrl-0 = <&qup_uart21_default>;
1229 pinctrl-names 1228 pinctrl-names = "default";
1230 1229
1231 status = "dis 1230 status = "disabled";
1232 }; 1231 };
1233 1232
1234 i2c22: i2c@898000 { 1233 i2c22: i2c@898000 {
1235 compatible = 1234 compatible = "qcom,geni-i2c";
1236 reg = <0 0x00 1235 reg = <0 0x00898000 0 0x4000>;
1237 1236
1238 interrupts = 1237 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
1239 1238
1240 clocks = <&gc 1239 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1241 clock-names = 1240 clock-names = "se";
1242 1241
1243 interconnects 1242 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1244 1243 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1245 1244 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1246 1245 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1247 1246 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1248 1247 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1249 interconnect- 1248 interconnect-names = "qup-core",
1250 1249 "qup-config",
1251 1250 "qup-memory";
1252 1251
1253 dmas = <&gpi_ 1252 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>,
1254 <&gpi_ 1253 <&gpi_dma2 1 6 QCOM_GPI_I2C>;
1255 dma-names = " 1254 dma-names = "tx",
1256 " 1255 "rx";
1257 1256
1258 pinctrl-0 = < 1257 pinctrl-0 = <&qup_i2c22_data_clk>;
1259 pinctrl-names 1258 pinctrl-names = "default";
1260 1259
1261 #address-cell 1260 #address-cells = <1>;
1262 #size-cells = 1261 #size-cells = <0>;
1263 1262
1264 status = "dis 1263 status = "disabled";
1265 }; 1264 };
1266 1265
1267 spi22: spi@898000 { 1266 spi22: spi@898000 {
1268 compatible = 1267 compatible = "qcom,geni-spi";
1269 reg = <0 0x00 1268 reg = <0 0x00898000 0 0x4000>;
1270 1269
1271 interrupts = 1270 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
1272 1271
1273 clocks = <&gc 1272 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1274 clock-names = 1273 clock-names = "se";
1275 1274
1276 interconnects 1275 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1277 1276 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1278 1277 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1279 1278 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1280 1279 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1281 1280 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1282 interconnect- 1281 interconnect-names = "qup-core",
1283 1282 "qup-config",
1284 1283 "qup-memory";
1285 1284
1286 dmas = <&gpi_ 1285 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>,
1287 <&gpi_ 1286 <&gpi_dma2 1 6 QCOM_GPI_SPI>;
1288 dma-names = " 1287 dma-names = "tx",
1289 " 1288 "rx";
1290 1289
1291 pinctrl-0 = < 1290 pinctrl-0 = <&qup_spi22_data_clk>, <&qup_spi22_cs>;
1292 pinctrl-names 1291 pinctrl-names = "default";
1293 1292
1294 #address-cell 1293 #address-cells = <1>;
1295 #size-cells = 1294 #size-cells = <0>;
1296 1295
1297 status = "dis 1296 status = "disabled";
1298 }; 1297 };
1299 1298
1300 i2c23: i2c@89c000 { 1299 i2c23: i2c@89c000 {
1301 compatible = 1300 compatible = "qcom,geni-i2c";
1302 reg = <0 0x00 1301 reg = <0 0x0089c000 0 0x4000>;
1303 1302
1304 interrupts = 1303 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
1305 1304
1306 clocks = <&gc 1305 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
1307 clock-names = 1306 clock-names = "se";
1308 1307
1309 interconnects 1308 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1310 1309 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1311 1310 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1312 1311 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1313 1312 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1314 1313 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1315 interconnect- 1314 interconnect-names = "qup-core",
1316 1315 "qup-config",
1317 1316 "qup-memory";
1318 1317
1319 dmas = <&gpi_ 1318 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>,
1320 <&gpi_ 1319 <&gpi_dma2 1 7 QCOM_GPI_I2C>;
1321 dma-names = " 1320 dma-names = "tx",
1322 " 1321 "rx";
1323 1322
1324 pinctrl-0 = < 1323 pinctrl-0 = <&qup_i2c23_data_clk>;
1325 pinctrl-names 1324 pinctrl-names = "default";
1326 1325
1327 #address-cell 1326 #address-cells = <1>;
1328 #size-cells = 1327 #size-cells = <0>;
1329 1328
1330 status = "dis 1329 status = "disabled";
1331 }; 1330 };
1332 1331
1333 spi23: spi@89c000 { 1332 spi23: spi@89c000 {
1334 compatible = 1333 compatible = "qcom,geni-spi";
1335 reg = <0 0x00 1334 reg = <0 0x0089c000 0 0x4000>;
1336 1335
1337 interrupts = 1336 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
1338 1337
1339 clocks = <&gc 1338 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
1340 clock-names = 1339 clock-names = "se";
1341 1340
1342 interconnects 1341 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1343 1342 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1344 1343 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1345 1344 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1346 1345 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1347 1346 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1348 interconnect- 1347 interconnect-names = "qup-core",
1349 1348 "qup-config",
1350 1349 "qup-memory";
1351 1350
1352 dmas = <&gpi_ 1351 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>,
1353 <&gpi_ 1352 <&gpi_dma2 1 7 QCOM_GPI_SPI>;
1354 dma-names = " 1353 dma-names = "tx",
1355 " 1354 "rx";
1356 1355
1357 pinctrl-0 = < 1356 pinctrl-0 = <&qup_spi23_data_clk>, <&qup_spi23_cs>;
1358 pinctrl-names 1357 pinctrl-names = "default";
1359 1358
1360 #address-cell 1359 #address-cells = <1>;
1361 #size-cells = 1360 #size-cells = <0>;
1362 1361
1363 status = "dis 1362 status = "disabled";
1364 }; 1363 };
1365 }; 1364 };
1366 1365
1367 gpi_dma1: dma-controller@a000 1366 gpi_dma1: dma-controller@a00000 {
1368 compatible = "qcom,x1 1367 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma";
1369 reg = <0 0x00a00000 0 1368 reg = <0 0x00a00000 0 0x60000>;
1370 1369
1371 interrupts = <GIC_SPI 1370 interrupts = <GIC_SPI 776 IRQ_TYPE_LEVEL_HIGH>,
1372 <GIC_SPI 1371 <GIC_SPI 777 IRQ_TYPE_LEVEL_HIGH>,
1373 <GIC_SPI 1372 <GIC_SPI 778 IRQ_TYPE_LEVEL_HIGH>,
1374 <GIC_SPI 1373 <GIC_SPI 779 IRQ_TYPE_LEVEL_HIGH>,
1375 <GIC_SPI 1374 <GIC_SPI 780 IRQ_TYPE_LEVEL_HIGH>,
1376 <GIC_SPI 1375 <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>,
1377 <GIC_SPI 1376 <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>,
1378 <GIC_SPI 1377 <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>,
1379 <GIC_SPI 1378 <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>,
1380 <GIC_SPI 1379 <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>,
1381 <GIC_SPI 1380 <GIC_SPI 786 IRQ_TYPE_LEVEL_HIGH>,
1382 <GIC_SPI 1381 <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>;
1383 1382
1384 dma-channels = <12>; 1383 dma-channels = <12>;
1385 dma-channel-mask = <0 1384 dma-channel-mask = <0x3e>;
1386 #dma-cells = <3>; 1385 #dma-cells = <3>;
1387 1386
1388 iommus = <&apps_smmu 1387 iommus = <&apps_smmu 0x136 0x0>;
1389 1388
1390 status = "disabled"; 1389 status = "disabled";
1391 }; 1390 };
1392 1391
1393 qupv3_1: geniqup@ac0000 { 1392 qupv3_1: geniqup@ac0000 {
1394 compatible = "qcom,ge 1393 compatible = "qcom,geni-se-qup";
1395 reg = <0 0x00ac0000 0 1394 reg = <0 0x00ac0000 0 0x2000>;
1396 1395
1397 clocks = <&gcc GCC_QU 1396 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1398 <&gcc GCC_QU 1397 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1399 clock-names = "m-ahb" 1398 clock-names = "m-ahb",
1400 "s-ahb" 1399 "s-ahb";
1401 1400
1402 iommus = <&apps_smmu 1401 iommus = <&apps_smmu 0x123 0x0>;
1403 1402
1404 #address-cells = <2>; 1403 #address-cells = <2>;
1405 #size-cells = <2>; 1404 #size-cells = <2>;
1406 ranges; 1405 ranges;
1407 1406
1408 status = "disabled"; 1407 status = "disabled";
1409 1408
1410 i2c8: i2c@a80000 { 1409 i2c8: i2c@a80000 {
1411 compatible = 1410 compatible = "qcom,geni-i2c";
1412 reg = <0 0x00 1411 reg = <0 0x00a80000 0 0x4000>;
1413 1412
1414 interrupts = 1413 interrupts = <GIC_SPI 800 IRQ_TYPE_LEVEL_HIGH>;
1415 1414
1416 clocks = <&gc 1415 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1417 clock-names = 1416 clock-names = "se";
1418 1417
1419 interconnects 1418 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1420 1419 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1421 1420 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1422 1421 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1423 1422 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1424 1423 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1425 interconnect- 1424 interconnect-names = "qup-core",
1426 1425 "qup-config",
1427 1426 "qup-memory";
1428 1427
1429 dmas = <&gpi_ 1428 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1430 <&gpi_ 1429 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1431 dma-names = " 1430 dma-names = "tx",
1432 " 1431 "rx";
1433 1432
1434 pinctrl-0 = < 1433 pinctrl-0 = <&qup_i2c8_data_clk>;
1435 pinctrl-names 1434 pinctrl-names = "default";
1436 1435
1437 #address-cell 1436 #address-cells = <1>;
1438 #size-cells = 1437 #size-cells = <0>;
1439 1438
1440 status = "dis 1439 status = "disabled";
1441 }; 1440 };
1442 1441
1443 spi8: spi@a80000 { 1442 spi8: spi@a80000 {
1444 compatible = 1443 compatible = "qcom,geni-spi";
1445 reg = <0 0x00 1444 reg = <0 0x00a80000 0 0x4000>;
1446 1445
1447 interrupts = 1446 interrupts = <GIC_SPI 800 IRQ_TYPE_LEVEL_HIGH>;
1448 1447
1449 clocks = <&gc 1448 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1450 clock-names = 1449 clock-names = "se";
1451 1450
1452 interconnects 1451 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1453 1452 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1454 1453 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1455 1454 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1456 1455 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1457 1456 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1458 interconnect- 1457 interconnect-names = "qup-core",
1459 1458 "qup-config",
1460 1459 "qup-memory";
1461 1460
1462 dmas = <&gpi_ 1461 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1463 <&gpi_ 1462 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1464 dma-names = " 1463 dma-names = "tx",
1465 " 1464 "rx";
1466 1465
1467 pinctrl-0 = < 1466 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1468 pinctrl-names 1467 pinctrl-names = "default";
1469 1468
1470 #address-cell 1469 #address-cells = <1>;
1471 #size-cells = 1470 #size-cells = <0>;
1472 1471
1473 status = "dis 1472 status = "disabled";
1474 }; 1473 };
1475 1474
1476 i2c9: i2c@a84000 { 1475 i2c9: i2c@a84000 {
1477 compatible = 1476 compatible = "qcom,geni-i2c";
1478 reg = <0 0x00 1477 reg = <0 0x00a84000 0 0x4000>;
1479 1478
1480 interrupts = 1479 interrupts = <GIC_SPI 801 IRQ_TYPE_LEVEL_HIGH>;
1481 1480
1482 clocks = <&gc 1481 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1483 clock-names = 1482 clock-names = "se";
1484 1483
1485 interconnects 1484 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1486 1485 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1487 1486 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1488 1487 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1489 1488 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1490 1489 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1491 interconnect- 1490 interconnect-names = "qup-core",
1492 1491 "qup-config",
1493 1492 "qup-memory";
1494 1493
1495 dmas = <&gpi_ 1494 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1496 <&gpi_ 1495 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1497 dma-names = " 1496 dma-names = "tx",
1498 " 1497 "rx";
1499 1498
1500 pinctrl-0 = < 1499 pinctrl-0 = <&qup_i2c9_data_clk>;
1501 pinctrl-names 1500 pinctrl-names = "default";
1502 1501
1503 #address-cell 1502 #address-cells = <1>;
1504 #size-cells = 1503 #size-cells = <0>;
1505 1504
1506 status = "dis 1505 status = "disabled";
1507 }; 1506 };
1508 1507
1509 spi9: spi@a84000 { 1508 spi9: spi@a84000 {
1510 compatible = 1509 compatible = "qcom,geni-spi";
1511 reg = <0 0x00 1510 reg = <0 0x00a84000 0 0x4000>;
1512 1511
1513 interrupts = 1512 interrupts = <GIC_SPI 801 IRQ_TYPE_LEVEL_HIGH>;
1514 1513
1515 clocks = <&gc 1514 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1516 clock-names = 1515 clock-names = "se";
1517 1516
1518 interconnects 1517 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1519 1518 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1520 1519 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1521 1520 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1522 1521 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1523 1522 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1524 interconnect- 1523 interconnect-names = "qup-core",
1525 1524 "qup-config",
1526 1525 "qup-memory";
1527 1526
1528 dmas = <&gpi_ 1527 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1529 <&gpi_ 1528 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1530 dma-names = " 1529 dma-names = "tx",
1531 " 1530 "rx";
1532 1531
1533 pinctrl-0 = < 1532 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1534 pinctrl-names 1533 pinctrl-names = "default";
1535 1534
1536 #address-cell 1535 #address-cells = <1>;
1537 #size-cells = 1536 #size-cells = <0>;
1538 1537
1539 status = "dis 1538 status = "disabled";
1540 }; 1539 };
1541 1540
1542 i2c10: i2c@a88000 { 1541 i2c10: i2c@a88000 {
1543 compatible = 1542 compatible = "qcom,geni-i2c";
1544 reg = <0 0x00 1543 reg = <0 0x00a88000 0 0x4000>;
1545 1544
1546 interrupts = 1545 interrupts = <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>;
1547 1546
1548 clocks = <&gc 1547 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1549 clock-names = 1548 clock-names = "se";
1550 1549
1551 interconnects 1550 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1552 1551 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1553 1552 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1554 1553 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1555 1554 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1556 1555 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1557 interconnect- 1556 interconnect-names = "qup-core",
1558 1557 "qup-config",
1559 1558 "qup-memory";
1560 1559
1561 dmas = <&gpi_ 1560 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1562 <&gpi_ 1561 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1563 dma-names = " 1562 dma-names = "tx",
1564 " 1563 "rx";
1565 1564
1566 pinctrl-0 = < 1565 pinctrl-0 = <&qup_i2c10_data_clk>;
1567 pinctrl-names 1566 pinctrl-names = "default";
1568 1567
1569 #address-cell 1568 #address-cells = <1>;
1570 #size-cells = 1569 #size-cells = <0>;
1571 1570
1572 status = "dis 1571 status = "disabled";
1573 }; 1572 };
1574 1573
1575 spi10: spi@a88000 { 1574 spi10: spi@a88000 {
1576 compatible = 1575 compatible = "qcom,geni-spi";
1577 reg = <0 0x00 1576 reg = <0 0x00a88000 0 0x4000>;
1578 1577
1579 interrupts = 1578 interrupts = <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>;
1580 1579
1581 clocks = <&gc 1580 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1582 clock-names = 1581 clock-names = "se";
1583 1582
1584 interconnects 1583 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1585 1584 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1586 1585 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1587 1586 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1588 1587 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1589 1588 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1590 interconnect- 1589 interconnect-names = "qup-core",
1591 1590 "qup-config",
1592 1591 "qup-memory";
1593 1592
1594 dmas = <&gpi_ 1593 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1595 <&gpi_ 1594 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1596 dma-names = " 1595 dma-names = "tx",
1597 " 1596 "rx";
1598 1597
1599 pinctrl-0 = < 1598 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1600 pinctrl-names 1599 pinctrl-names = "default";
1601 1600
1602 #address-cell 1601 #address-cells = <1>;
1603 #size-cells = 1602 #size-cells = <0>;
1604 1603
1605 status = "dis 1604 status = "disabled";
1606 }; 1605 };
1607 1606
1608 i2c11: i2c@a8c000 { 1607 i2c11: i2c@a8c000 {
1609 compatible = 1608 compatible = "qcom,geni-i2c";
1610 reg = <0 0x00 1609 reg = <0 0x00a8c000 0 0x4000>;
1611 1610
1612 interrupts = 1611 interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>;
1613 1612
1614 clocks = <&gc 1613 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1615 clock-names = 1614 clock-names = "se";
1616 1615
1617 interconnects 1616 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1618 1617 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1619 1618 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1620 1619 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1621 1620 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1622 1621 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1623 interconnect- 1622 interconnect-names = "qup-core",
1624 1623 "qup-config",
1625 1624 "qup-memory";
1626 1625
1627 dmas = <&gpi_ 1626 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1628 <&gpi_ 1627 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1629 dma-names = " 1628 dma-names = "tx",
1630 " 1629 "rx";
1631 1630
1632 pinctrl-0 = < 1631 pinctrl-0 = <&qup_i2c11_data_clk>;
1633 pinctrl-names 1632 pinctrl-names = "default";
1634 1633
1635 #address-cell 1634 #address-cells = <1>;
1636 #size-cells = 1635 #size-cells = <0>;
1637 1636
1638 status = "dis 1637 status = "disabled";
1639 }; 1638 };
1640 1639
1641 spi11: spi@a8c000 { 1640 spi11: spi@a8c000 {
1642 compatible = 1641 compatible = "qcom,geni-spi";
1643 reg = <0 0x00 1642 reg = <0 0x00a8c000 0 0x4000>;
1644 1643
1645 interrupts = 1644 interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>;
1646 1645
1647 clocks = <&gc 1646 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1648 clock-names = 1647 clock-names = "se";
1649 1648
1650 interconnects 1649 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1651 1650 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1652 1651 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1653 1652 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1654 1653 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1655 1654 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1656 interconnect- 1655 interconnect-names = "qup-core",
1657 1656 "qup-config",
1658 1657 "qup-memory";
1659 1658
1660 dmas = <&gpi_ 1659 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1661 <&gpi_ 1660 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1662 dma-names = " 1661 dma-names = "tx",
1663 " 1662 "rx";
1664 1663
1665 pinctrl-0 = < 1664 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1666 pinctrl-names 1665 pinctrl-names = "default";
1667 1666
1668 #address-cell 1667 #address-cells = <1>;
1669 #size-cells = 1668 #size-cells = <0>;
1670 1669
1671 status = "dis 1670 status = "disabled";
1672 }; 1671 };
1673 1672
1674 i2c12: i2c@a90000 { 1673 i2c12: i2c@a90000 {
1675 compatible = 1674 compatible = "qcom,geni-i2c";
1676 reg = <0 0x00 1675 reg = <0 0x00a90000 0 0x4000>;
1677 1676
1678 interrupts = 1677 interrupts = <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>;
1679 1678
1680 clocks = <&gc 1679 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1681 clock-names = 1680 clock-names = "se";
1682 1681
1683 interconnects 1682 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1684 1683 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1685 1684 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1686 1685 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1687 1686 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1688 1687 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1689 interconnect- 1688 interconnect-names = "qup-core",
1690 1689 "qup-config",
1691 1690 "qup-memory";
1692 1691
1693 dmas = <&gpi_ 1692 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1694 <&gpi_ 1693 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1695 dma-names = " 1694 dma-names = "tx",
1696 " 1695 "rx";
1697 1696
1698 pinctrl-0 = < 1697 pinctrl-0 = <&qup_i2c12_data_clk>;
1699 pinctrl-names 1698 pinctrl-names = "default";
1700 1699
1701 #address-cell 1700 #address-cells = <1>;
1702 #size-cells = 1701 #size-cells = <0>;
1703 1702
1704 status = "dis 1703 status = "disabled";
1705 }; 1704 };
1706 1705
1707 spi12: spi@a90000 { 1706 spi12: spi@a90000 {
1708 compatible = 1707 compatible = "qcom,geni-spi";
1709 reg = <0 0x00 1708 reg = <0 0x00a90000 0 0x4000>;
1710 1709
1711 interrupts = 1710 interrupts = <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>;
1712 1711
1713 clocks = <&gc 1712 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1714 clock-names = 1713 clock-names = "se";
1715 1714
1716 interconnects 1715 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1717 1716 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1718 1717 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1719 1718 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1720 1719 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1721 1720 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1722 interconnect- 1721 interconnect-names = "qup-core",
1723 1722 "qup-config",
1724 1723 "qup-memory";
1725 1724
1726 dmas = <&gpi_ 1725 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1727 <&gpi_ 1726 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1728 dma-names = " 1727 dma-names = "tx",
1729 " 1728 "rx";
1730 1729
1731 pinctrl-0 = < 1730 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1732 pinctrl-names 1731 pinctrl-names = "default";
1733 1732
1734 #address-cell 1733 #address-cells = <1>;
1735 #size-cells = 1734 #size-cells = <0>;
1736 1735
1737 status = "dis 1736 status = "disabled";
1738 }; 1737 };
1739 1738
1740 i2c13: i2c@a94000 { 1739 i2c13: i2c@a94000 {
1741 compatible = 1740 compatible = "qcom,geni-i2c";
1742 reg = <0 0x00 1741 reg = <0 0x00a94000 0 0x4000>;
1743 1742
1744 interrupts = 1743 interrupts = <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>;
1745 1744
1746 clocks = <&gc 1745 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1747 clock-names = 1746 clock-names = "se";
1748 1747
1749 interconnects 1748 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1750 1749 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1751 1750 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1752 1751 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1753 1752 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1754 1753 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1755 interconnect- 1754 interconnect-names = "qup-core",
1756 1755 "qup-config",
1757 1756 "qup-memory";
1758 1757
1759 dmas = <&gpi_ 1758 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1760 <&gpi_ 1759 <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1761 dma-names = " 1760 dma-names = "tx",
1762 " 1761 "rx";
1763 1762
1764 pinctrl-0 = < 1763 pinctrl-0 = <&qup_i2c13_data_clk>;
1765 pinctrl-names 1764 pinctrl-names = "default";
1766 1765
1767 #address-cell 1766 #address-cells = <1>;
1768 #size-cells = 1767 #size-cells = <0>;
1769 1768
1770 status = "dis 1769 status = "disabled";
1771 }; 1770 };
1772 1771
1773 spi13: spi@a94000 { 1772 spi13: spi@a94000 {
1774 compatible = 1773 compatible = "qcom,geni-spi";
1775 reg = <0 0x00 1774 reg = <0 0x00a94000 0 0x4000>;
1776 1775
1777 interrupts = 1776 interrupts = <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>;
1778 1777
1779 clocks = <&gc 1778 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1780 clock-names = 1779 clock-names = "se";
1781 1780
1782 interconnects 1781 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1783 1782 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1784 1783 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1785 1784 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1786 1785 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1787 1786 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1788 interconnect- 1787 interconnect-names = "qup-core",
1789 1788 "qup-config",
1790 1789 "qup-memory";
1791 1790
1792 dmas = <&gpi_ 1791 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1793 <&gpi_ 1792 <&gpi_dma1 1 5 QCOM_GPI_SPI>;
1794 dma-names = " 1793 dma-names = "tx",
1795 " 1794 "rx";
1796 1795
1797 pinctrl-0 = < 1796 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1798 pinctrl-names 1797 pinctrl-names = "default";
1799 1798
1800 #address-cell 1799 #address-cells = <1>;
1801 #size-cells = 1800 #size-cells = <0>;
1802 1801
1803 status = "dis 1802 status = "disabled";
1804 }; 1803 };
1805 1804
1806 i2c14: i2c@a98000 { 1805 i2c14: i2c@a98000 {
1807 compatible = 1806 compatible = "qcom,geni-i2c";
1808 reg = <0 0x00 1807 reg = <0 0x00a98000 0 0x4000>;
1809 1808
1810 interrupts = 1809 interrupts = <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>;
1811 1810
1812 clocks = <&gc 1811 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1813 clock-names = 1812 clock-names = "se";
1814 1813
1815 interconnects 1814 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1816 1815 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1817 1816 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1818 1817 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1819 1818 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1820 1819 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1821 interconnect- 1820 interconnect-names = "qup-core",
1822 1821 "qup-config",
1823 1822 "qup-memory";
1824 1823
1825 dmas = <&gpi_ 1824 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
1826 <&gpi_ 1825 <&gpi_dma1 1 6 QCOM_GPI_I2C>;
1827 dma-names = " 1826 dma-names = "tx",
1828 " 1827 "rx";
1829 1828
1830 pinctrl-0 = < 1829 pinctrl-0 = <&qup_i2c14_data_clk>;
1831 pinctrl-names 1830 pinctrl-names = "default";
1832 1831
1833 #address-cell 1832 #address-cells = <1>;
1834 #size-cells = 1833 #size-cells = <0>;
1835 1834
1836 status = "dis 1835 status = "disabled";
1837 }; 1836 };
1838 1837
1839 spi14: spi@a98000 { 1838 spi14: spi@a98000 {
1840 compatible = 1839 compatible = "qcom,geni-spi";
1841 reg = <0 0x00 1840 reg = <0 0x00a98000 0 0x4000>;
1842 1841
1843 interrupts = 1842 interrupts = <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>;
1844 1843
1845 clocks = <&gc 1844 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1846 clock-names = 1845 clock-names = "se";
1847 1846
1848 interconnects 1847 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1849 1848 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1850 1849 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1851 1850 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1852 1851 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1853 1852 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1854 interconnect- 1853 interconnect-names = "qup-core",
1855 1854 "qup-config",
1856 1855 "qup-memory";
1857 1856
1858 dmas = <&gpi_ 1857 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
1859 <&gpi_ 1858 <&gpi_dma1 1 6 QCOM_GPI_SPI>;
1860 dma-names = " 1859 dma-names = "tx",
1861 " 1860 "rx";
1862 1861
1863 pinctrl-0 = < 1862 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
1864 pinctrl-names 1863 pinctrl-names = "default";
1865 1864
1866 #address-cell 1865 #address-cells = <1>;
1867 #size-cells = 1866 #size-cells = <0>;
1868 1867
1869 status = "dis 1868 status = "disabled";
1870 }; 1869 };
1871 1870
1872 i2c15: i2c@a9c000 { 1871 i2c15: i2c@a9c000 {
1873 compatible = 1872 compatible = "qcom,geni-i2c";
1874 reg = <0 0x00 1873 reg = <0 0x00a9c000 0 0x4000>;
1875 1874
1876 interrupts = 1875 interrupts = <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>;
1877 1876
1878 clocks = <&gc 1877 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1879 clock-names = 1878 clock-names = "se";
1880 1879
1881 interconnects 1880 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1882 1881 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1883 1882 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1884 1883 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1885 1884 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1886 1885 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1887 interconnect- 1886 interconnect-names = "qup-core",
1888 1887 "qup-config",
1889 1888 "qup-memory";
1890 1889
1891 dmas = <&gpi_ 1890 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
1892 <&gpi_ 1891 <&gpi_dma1 1 7 QCOM_GPI_I2C>;
1893 dma-names = " 1892 dma-names = "tx",
1894 " 1893 "rx";
1895 1894
1896 pinctrl-0 = < 1895 pinctrl-0 = <&qup_i2c15_data_clk>;
1897 pinctrl-names 1896 pinctrl-names = "default";
1898 1897
1899 #address-cell 1898 #address-cells = <1>;
1900 #size-cells = 1899 #size-cells = <0>;
1901 1900
1902 status = "dis 1901 status = "disabled";
1903 }; 1902 };
1904 1903
1905 spi15: spi@a9c000 { 1904 spi15: spi@a9c000 {
1906 compatible = 1905 compatible = "qcom,geni-spi";
1907 reg = <0 0x00 1906 reg = <0 0x00a9c000 0 0x4000>;
1908 1907
1909 interrupts = 1908 interrupts = <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>;
1910 1909
1911 clocks = <&gc 1910 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1912 clock-names = 1911 clock-names = "se";
1913 1912
1914 interconnects 1913 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1915 1914 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1916 1915 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1917 1916 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1918 1917 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1919 1918 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1920 interconnect- 1919 interconnect-names = "qup-core",
1921 1920 "qup-config",
1922 1921 "qup-memory";
1923 1922
1924 dmas = <&gpi_ 1923 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>,
1925 <&gpi_ 1924 <&gpi_dma1 1 7 QCOM_GPI_SPI>;
1926 dma-names = " 1925 dma-names = "tx",
1927 " 1926 "rx";
1928 1927
1929 pinctrl-0 = < 1928 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
1930 pinctrl-names 1929 pinctrl-names = "default";
1931 1930
1932 #address-cell 1931 #address-cells = <1>;
1933 #size-cells = 1932 #size-cells = <0>;
1934 1933
1935 status = "dis 1934 status = "disabled";
1936 }; 1935 };
1937 }; 1936 };
1938 1937
1939 gpi_dma0: dma-controller@b000 1938 gpi_dma0: dma-controller@b00000 {
1940 compatible = "qcom,x1 1939 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma";
1941 reg = <0 0x00b00000 0 1940 reg = <0 0x00b00000 0 0x60000>;
1942 1941
1943 interrupts = <GIC_SPI 1942 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
1944 <GIC_SPI 1943 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
1945 <GIC_SPI 1944 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
1946 <GIC_SPI 1945 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
1947 <GIC_SPI 1946 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
1948 <GIC_SPI 1947 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
1949 <GIC_SPI 1948 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
1950 <GIC_SPI 1949 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
1951 <GIC_SPI 1950 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
1952 <GIC_SPI 1951 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
1953 <GIC_SPI 1952 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
1954 <GIC_SPI 1953 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
1955 1954
1956 dma-channels = <12>; 1955 dma-channels = <12>;
1957 dma-channel-mask = <0 1956 dma-channel-mask = <0x3e>;
1958 #dma-cells = <3>; 1957 #dma-cells = <3>;
1959 1958
1960 iommus = <&apps_smmu 1959 iommus = <&apps_smmu 0x456 0x0>;
1961 1960
1962 status = "disabled"; 1961 status = "disabled";
1963 }; 1962 };
1964 1963
1965 qupv3_0: geniqup@bc0000 { 1964 qupv3_0: geniqup@bc0000 {
1966 compatible = "qcom,ge 1965 compatible = "qcom,geni-se-qup";
1967 reg = <0 0x00bc0000 0 1966 reg = <0 0x00bc0000 0 0x2000>;
1968 1967
1969 clocks = <&gcc GCC_QU 1968 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1970 <&gcc GCC_QU 1969 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1971 clock-names = "m-ahb" 1970 clock-names = "m-ahb",
1972 "s-ahb" 1971 "s-ahb";
1973 1972
1974 iommus = <&apps_smmu 1973 iommus = <&apps_smmu 0x443 0x0>;
1975 #address-cells = <2>; 1974 #address-cells = <2>;
1976 #size-cells = <2>; 1975 #size-cells = <2>;
1977 ranges; 1976 ranges;
1978 1977
1979 status = "disabled"; 1978 status = "disabled";
1980 1979
1981 i2c0: i2c@b80000 { 1980 i2c0: i2c@b80000 {
1982 compatible = 1981 compatible = "qcom,geni-i2c";
1983 reg = <0 0x00 !! 1982 reg = <0 0xb80000 0 0x4000>;
1984 1983
1985 interrupts = 1984 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1986 1985
1987 clocks = <&gc 1986 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1988 clock-names = 1987 clock-names = "se";
1989 1988
1990 interconnects 1989 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1991 1990 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1992 1991 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1993 1992 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
1994 1993 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
1995 1994 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1996 interconnect- 1995 interconnect-names = "qup-core",
1997 1996 "qup-config",
1998 1997 "qup-memory";
1999 1998
2000 dmas = <&gpi_ 1999 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
2001 <&gpi_ 2000 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
2002 dma-names = " 2001 dma-names = "tx",
2003 " 2002 "rx";
2004 2003
2005 pinctrl-0 = < 2004 pinctrl-0 = <&qup_i2c0_data_clk>;
2006 pinctrl-names 2005 pinctrl-names = "default";
2007 2006
2008 #address-cell 2007 #address-cells = <1>;
2009 #size-cells = 2008 #size-cells = <0>;
2010 2009
2011 status = "dis 2010 status = "disabled";
2012 }; 2011 };
2013 2012
2014 spi0: spi@b80000 { 2013 spi0: spi@b80000 {
2015 compatible = 2014 compatible = "qcom,geni-spi";
2016 reg = <0 0x00 2015 reg = <0 0x00b80000 0 0x4000>;
2017 2016
2018 interrupts = 2017 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
2019 2018
2020 clocks = <&gc 2019 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
2021 clock-names = 2020 clock-names = "se";
2022 2021
2023 interconnects 2022 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2024 2023 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2025 2024 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2026 2025 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2027 2026 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2028 2027 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2029 interconnect- 2028 interconnect-names = "qup-core",
2030 2029 "qup-config",
2031 2030 "qup-memory";
2032 2031
2033 dmas = <&gpi_ 2032 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
2034 <&gpi_ 2033 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
2035 dma-names = " 2034 dma-names = "tx",
2036 " 2035 "rx";
2037 2036
2038 pinctrl-0 = < 2037 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
2039 pinctrl-names 2038 pinctrl-names = "default";
2040 2039
2041 #address-cell 2040 #address-cells = <1>;
2042 #size-cells = 2041 #size-cells = <0>;
2043 2042
2044 status = "dis 2043 status = "disabled";
2045 }; 2044 };
2046 2045
2047 i2c1: i2c@b84000 { 2046 i2c1: i2c@b84000 {
2048 compatible = 2047 compatible = "qcom,geni-i2c";
2049 reg = <0 0x00 2048 reg = <0 0x00b84000 0 0x4000>;
2050 2049
2051 interrupts = 2050 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
2052 2051
2053 clocks = <&gc 2052 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
2054 clock-names = 2053 clock-names = "se";
2055 2054
2056 interconnects 2055 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2057 2056 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2058 2057 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2059 2058 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2060 2059 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2061 2060 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2062 interconnect- 2061 interconnect-names = "qup-core",
2063 2062 "qup-config",
2064 2063 "qup-memory";
2065 2064
2066 dmas = <&gpi_ 2065 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
2067 <&gpi_ 2066 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
2068 dma-names = " 2067 dma-names = "tx",
2069 " 2068 "rx";
2070 2069
2071 pinctrl-0 = < 2070 pinctrl-0 = <&qup_i2c1_data_clk>;
2072 pinctrl-names 2071 pinctrl-names = "default";
2073 2072
2074 #address-cell 2073 #address-cells = <1>;
2075 #size-cells = 2074 #size-cells = <0>;
2076 2075
2077 status = "dis 2076 status = "disabled";
2078 }; 2077 };
2079 2078
2080 spi1: spi@b84000 { 2079 spi1: spi@b84000 {
2081 compatible = 2080 compatible = "qcom,geni-spi";
2082 reg = <0 0x00 2081 reg = <0 0x00b84000 0 0x4000>;
2083 2082
2084 interrupts = 2083 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
2085 2084
2086 clocks = <&gc 2085 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
2087 clock-names = 2086 clock-names = "se";
2088 2087
2089 interconnects 2088 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2090 2089 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2091 2090 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2092 2091 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2093 2092 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2094 2093 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2095 interconnect- 2094 interconnect-names = "qup-core",
2096 2095 "qup-config",
2097 2096 "qup-memory";
2098 2097
2099 dmas = <&gpi_ 2098 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
2100 <&gpi_ 2099 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
2101 dma-names = " 2100 dma-names = "tx",
2102 " 2101 "rx";
2103 2102
2104 pinctrl-0 = < 2103 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
2105 pinctrl-names 2104 pinctrl-names = "default";
2106 2105
2107 #address-cell 2106 #address-cells = <1>;
2108 #size-cells = 2107 #size-cells = <0>;
2109 2108
2110 status = "dis 2109 status = "disabled";
2111 }; 2110 };
2112 2111
2113 i2c2: i2c@b88000 { 2112 i2c2: i2c@b88000 {
2114 compatible = 2113 compatible = "qcom,geni-i2c";
2115 reg = <0 0x00 2114 reg = <0 0x00b88000 0 0x4000>;
2116 2115
2117 interrupts = 2116 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
2118 2117
2119 clocks = <&gc 2118 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
2120 clock-names = 2119 clock-names = "se";
2121 2120
2122 interconnects 2121 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2123 2122 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2124 2123 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2125 2124 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2126 2125 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2127 2126 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2128 interconnect- 2127 interconnect-names = "qup-core",
2129 2128 "qup-config",
2130 2129 "qup-memory";
2131 2130
2132 dmas = <&gpi_ 2131 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
2133 <&gpi_ 2132 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
2134 dma-names = " 2133 dma-names = "tx",
2135 " 2134 "rx";
2136 2135
2137 pinctrl-0 = < 2136 pinctrl-0 = <&qup_i2c2_data_clk>;
2138 pinctrl-names 2137 pinctrl-names = "default";
2139 2138
2140 #address-cell 2139 #address-cells = <1>;
2141 #size-cells = 2140 #size-cells = <0>;
2142 2141
2143 status = "dis 2142 status = "disabled";
2144 }; 2143 };
2145 2144
2146 uart2: serial@b88000 <<
2147 compatible = <<
2148 reg = <0 0x00 <<
2149 <<
2150 interrupts = <<
2151 <<
2152 clocks = <&gc <<
2153 clock-names = <<
2154 <<
2155 interconnects <<
2156 <<
2157 <<
2158 <<
2159 interconnect- <<
2160 <<
2161 <<
2162 pinctrl-0 = < <<
2163 pinctrl-names <<
2164 <<
2165 status = "dis <<
2166 }; <<
2167 <<
2168 spi2: spi@b88000 { 2145 spi2: spi@b88000 {
2169 compatible = 2146 compatible = "qcom,geni-spi";
2170 reg = <0 0x00 !! 2147 reg = <0 0xb88000 0 0x4000>;
2171 2148
2172 interrupts = 2149 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
2173 2150
2174 clocks = <&gc 2151 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
2175 clock-names = 2152 clock-names = "se";
2176 2153
2177 interconnects 2154 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2178 2155 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2179 2156 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2180 2157 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2181 2158 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2182 2159 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2183 interconnect- 2160 interconnect-names = "qup-core",
2184 2161 "qup-config",
2185 2162 "qup-memory";
2186 2163
2187 dmas = <&gpi_ 2164 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
2188 <&gpi_ 2165 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
2189 dma-names = " 2166 dma-names = "tx",
2190 " 2167 "rx";
2191 2168
2192 pinctrl-0 = < 2169 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
2193 pinctrl-names 2170 pinctrl-names = "default";
2194 2171
2195 #address-cell 2172 #address-cells = <1>;
2196 #size-cells = 2173 #size-cells = <0>;
2197 2174
2198 status = "dis 2175 status = "disabled";
2199 }; 2176 };
2200 2177
2201 i2c3: i2c@b8c000 { 2178 i2c3: i2c@b8c000 {
2202 compatible = 2179 compatible = "qcom,geni-i2c";
2203 reg = <0 0x00 2180 reg = <0 0x00b8c000 0 0x4000>;
2204 2181
2205 interrupts = 2182 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
2206 2183
2207 clocks = <&gc 2184 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
2208 clock-names = 2185 clock-names = "se";
2209 2186
2210 interconnects 2187 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2211 2188 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2212 2189 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2213 2190 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2214 2191 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2215 2192 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2216 interconnect- 2193 interconnect-names = "qup-core",
2217 2194 "qup-config",
2218 2195 "qup-memory";
2219 2196
2220 dmas = <&gpi_ 2197 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
2221 <&gpi_ 2198 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
2222 dma-names = " 2199 dma-names = "tx",
2223 " 2200 "rx";
2224 2201
2225 pinctrl-0 = < 2202 pinctrl-0 = <&qup_i2c3_data_clk>;
2226 pinctrl-names 2203 pinctrl-names = "default";
2227 2204
2228 #address-cell 2205 #address-cells = <1>;
2229 #size-cells = 2206 #size-cells = <0>;
2230 2207
2231 status = "dis 2208 status = "disabled";
2232 }; 2209 };
2233 2210
2234 spi3: spi@b8c000 { 2211 spi3: spi@b8c000 {
2235 compatible = 2212 compatible = "qcom,geni-spi";
2236 reg = <0 0x00 2213 reg = <0 0x00b8c000 0 0x4000>;
2237 2214
2238 interrupts = 2215 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
2239 2216
2240 clocks = <&gc 2217 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
2241 clock-names = 2218 clock-names = "se";
2242 2219
2243 interconnects 2220 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2244 2221 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2245 2222 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2246 2223 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2247 2224 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2248 2225 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2249 interconnect- 2226 interconnect-names = "qup-core",
2250 2227 "qup-config",
2251 2228 "qup-memory";
2252 2229
2253 dmas = <&gpi_ 2230 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
2254 <&gpi_ 2231 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
2255 dma-names = " 2232 dma-names = "tx",
2256 " 2233 "rx";
2257 2234
2258 pinctrl-0 = < 2235 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
2259 pinctrl-names 2236 pinctrl-names = "default";
2260 2237
2261 #address-cell 2238 #address-cells = <1>;
2262 #size-cells = 2239 #size-cells = <0>;
2263 2240
2264 status = "dis 2241 status = "disabled";
2265 }; 2242 };
2266 2243
2267 i2c4: i2c@b90000 { 2244 i2c4: i2c@b90000 {
2268 compatible = 2245 compatible = "qcom,geni-i2c";
2269 reg = <0 0x00 !! 2246 reg = <0 0xb90000 0 0x4000>;
2270 2247
2271 interrupts = 2248 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
2272 2249
2273 clocks = <&gc 2250 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
2274 clock-names = 2251 clock-names = "se";
2275 2252
2276 interconnects 2253 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2277 2254 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2278 2255 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2279 2256 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2280 2257 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2281 2258 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2282 interconnect- 2259 interconnect-names = "qup-core",
2283 2260 "qup-config",
2284 2261 "qup-memory";
2285 2262
2286 dmas = <&gpi_ 2263 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
2287 <&gpi_ 2264 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
2288 dma-names = " 2265 dma-names = "tx",
2289 " 2266 "rx";
2290 2267
2291 pinctrl-0 = < 2268 pinctrl-0 = <&qup_i2c4_data_clk>;
2292 pinctrl-names 2269 pinctrl-names = "default";
2293 2270
2294 #address-cell 2271 #address-cells = <1>;
2295 #size-cells = 2272 #size-cells = <0>;
2296 2273
2297 status = "dis 2274 status = "disabled";
2298 }; 2275 };
2299 2276
2300 spi4: spi@b90000 { 2277 spi4: spi@b90000 {
2301 compatible = 2278 compatible = "qcom,geni-spi";
2302 reg = <0 0x00 2279 reg = <0 0x00b90000 0 0x4000>;
2303 2280
2304 interrupts = 2281 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
2305 2282
2306 clocks = <&gc 2283 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
2307 clock-names = 2284 clock-names = "se";
2308 2285
2309 interconnects 2286 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2310 2287 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2311 2288 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2312 2289 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2313 2290 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2314 2291 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2315 interconnect- 2292 interconnect-names = "qup-core",
2316 2293 "qup-config",
2317 2294 "qup-memory";
2318 2295
2319 dmas = <&gpi_ 2296 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
2320 <&gpi_ 2297 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
2321 dma-names = " 2298 dma-names = "tx",
2322 " 2299 "rx";
2323 2300
2324 pinctrl-0 = < 2301 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
2325 pinctrl-names 2302 pinctrl-names = "default";
2326 2303
2327 #address-cell 2304 #address-cells = <1>;
2328 #size-cells = 2305 #size-cells = <0>;
2329 2306
2330 status = "dis 2307 status = "disabled";
2331 }; 2308 };
2332 2309
2333 i2c5: i2c@b94000 { 2310 i2c5: i2c@b94000 {
2334 compatible = 2311 compatible = "qcom,geni-i2c";
2335 reg = <0 0x00 2312 reg = <0 0x00b94000 0 0x4000>;
2336 2313
2337 interrupts = 2314 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
2338 2315
2339 clocks = <&gc 2316 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
2340 clock-names = 2317 clock-names = "se";
2341 2318
2342 interconnects 2319 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2343 2320 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2344 2321 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2345 2322 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2346 2323 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2347 2324 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2348 interconnect- 2325 interconnect-names = "qup-core",
2349 2326 "qup-config",
2350 2327 "qup-memory";
2351 2328
2352 dmas = <&gpi_ 2329 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
2353 <&gpi_ 2330 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
2354 dma-names = " 2331 dma-names = "tx",
2355 " 2332 "rx";
2356 2333
2357 pinctrl-0 = < 2334 pinctrl-0 = <&qup_i2c5_data_clk>;
2358 pinctrl-names 2335 pinctrl-names = "default";
2359 2336
2360 #address-cell 2337 #address-cells = <1>;
2361 #size-cells = 2338 #size-cells = <0>;
2362 2339
2363 status = "dis 2340 status = "disabled";
2364 }; 2341 };
2365 2342
2366 spi5: spi@b94000 { 2343 spi5: spi@b94000 {
2367 compatible = 2344 compatible = "qcom,geni-spi";
2368 reg = <0 0x00 2345 reg = <0 0x00b94000 0 0x4000>;
2369 2346
2370 interrupts = 2347 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
2371 2348
2372 clocks = <&gc 2349 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
2373 clock-names = 2350 clock-names = "se";
2374 2351
2375 interconnects 2352 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2376 2353 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2377 2354 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2378 2355 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2379 2356 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2380 2357 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2381 interconnect- 2358 interconnect-names = "qup-core",
2382 2359 "qup-config",
2383 2360 "qup-memory";
2384 2361
2385 dmas = <&gpi_ 2362 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
2386 <&gpi_ 2363 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
2387 dma-names = " 2364 dma-names = "tx",
2388 " 2365 "rx";
2389 2366
2390 pinctrl-0 = < 2367 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
2391 pinctrl-names 2368 pinctrl-names = "default";
2392 2369
2393 #address-cell 2370 #address-cells = <1>;
2394 #size-cells = 2371 #size-cells = <0>;
2395 2372
2396 status = "dis 2373 status = "disabled";
2397 }; 2374 };
2398 2375
2399 i2c6: i2c@b98000 { 2376 i2c6: i2c@b98000 {
2400 compatible = 2377 compatible = "qcom,geni-i2c";
2401 reg = <0 0x00 2378 reg = <0 0x00b98000 0 0x4000>;
2402 2379
2403 interrupts = 2380 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
2404 2381
2405 clocks = <&gc 2382 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
2406 clock-names = 2383 clock-names = "se";
2407 2384
2408 interconnects 2385 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2409 2386 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2410 2387 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2411 2388 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2412 2389 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2413 2390 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2414 interconnect- 2391 interconnect-names = "qup-core",
2415 2392 "qup-config",
2416 2393 "qup-memory";
2417 2394
2418 dmas = <&gpi_ 2395 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
2419 <&gpi_ 2396 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
2420 dma-names = " 2397 dma-names = "tx",
2421 " 2398 "rx";
2422 2399
2423 pinctrl-0 = < 2400 pinctrl-0 = <&qup_i2c6_data_clk>;
2424 pinctrl-names 2401 pinctrl-names = "default";
2425 2402
2426 #address-cell 2403 #address-cells = <1>;
2427 #size-cells = 2404 #size-cells = <0>;
2428 2405
2429 status = "dis 2406 status = "disabled";
2430 }; 2407 };
2431 2408
2432 spi6: spi@b98000 { 2409 spi6: spi@b98000 {
2433 compatible = 2410 compatible = "qcom,geni-spi";
2434 reg = <0 0x00 2411 reg = <0 0x00b98000 0 0x4000>;
2435 2412
2436 interrupts = 2413 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
2437 2414
2438 clocks = <&gc 2415 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
2439 clock-names = 2416 clock-names = "se";
2440 2417
2441 interconnects 2418 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2442 2419 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2443 2420 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2444 2421 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2445 2422 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2446 2423 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2447 interconnect- 2424 interconnect-names = "qup-core",
2448 2425 "qup-config",
2449 2426 "qup-memory";
2450 2427
2451 dmas = <&gpi_ 2428 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
2452 <&gpi_ 2429 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
2453 dma-names = " 2430 dma-names = "tx",
2454 " 2431 "rx";
2455 2432
2456 pinctrl-0 = < 2433 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
2457 pinctrl-names 2434 pinctrl-names = "default";
2458 2435
2459 #address-cell 2436 #address-cells = <1>;
2460 #size-cells = 2437 #size-cells = <0>;
2461 2438
2462 status = "dis 2439 status = "disabled";
2463 }; 2440 };
2464 2441
2465 i2c7: i2c@b9c000 { 2442 i2c7: i2c@b9c000 {
2466 compatible = 2443 compatible = "qcom,geni-i2c";
2467 reg = <0 0x00 2444 reg = <0 0x00b9c000 0 0x4000>;
2468 2445
2469 interrupts = 2446 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
2470 2447
2471 clocks = <&gc 2448 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
2472 clock-names = 2449 clock-names = "se";
2473 2450
2474 interconnects 2451 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2475 2452 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2476 2453 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2477 2454 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2478 2455 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2479 2456 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2480 interconnect- 2457 interconnect-names = "qup-core",
2481 2458 "qup-config",
2482 2459 "qup-memory";
2483 2460
2484 dmas = <&gpi_ 2461 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
2485 <&gpi_ 2462 <&gpi_dma0 1 7 QCOM_GPI_I2C>;
2486 dma-names = " 2463 dma-names = "tx",
2487 " 2464 "rx";
2488 2465
2489 pinctrl-0 = < 2466 pinctrl-0 = <&qup_i2c7_data_clk>;
2490 pinctrl-names 2467 pinctrl-names = "default";
2491 2468
2492 #address-cell 2469 #address-cells = <1>;
2493 #size-cells = 2470 #size-cells = <0>;
2494 2471
2495 status = "dis 2472 status = "disabled";
2496 }; 2473 };
2497 2474
2498 spi7: spi@b9c000 { 2475 spi7: spi@b9c000 {
2499 compatible = 2476 compatible = "qcom,geni-spi";
2500 reg = <0 0x00 2477 reg = <0 0x00b9c000 0 0x4000>;
2501 2478
2502 interrupts = 2479 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
2503 2480
2504 clocks = <&gc 2481 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
2505 clock-names = 2482 clock-names = "se";
2506 2483
2507 interconnects 2484 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2508 2485 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2509 2486 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2510 2487 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2511 2488 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2512 2489 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2513 interconnect- 2490 interconnect-names = "qup-core",
2514 2491 "qup-config",
2515 2492 "qup-memory";
2516 2493
2517 dmas = <&gpi_ 2494 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
2518 <&gpi_ 2495 <&gpi_dma0 1 7 QCOM_GPI_SPI>;
2519 dma-names = " 2496 dma-names = "tx",
2520 " 2497 "rx";
2521 2498
2522 pinctrl-0 = < 2499 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
2523 pinctrl-names 2500 pinctrl-names = "default";
2524 2501
2525 #address-cell 2502 #address-cells = <1>;
2526 #size-cells = 2503 #size-cells = <0>;
2527 2504
2528 status = "dis 2505 status = "disabled";
2529 }; 2506 };
2530 }; 2507 };
2531 2508
2532 tsens0: thermal-sensor@c27100 2509 tsens0: thermal-sensor@c271000 {
2533 compatible = "qcom,x1 2510 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2";
2534 reg = <0 0x0c271000 0 2511 reg = <0 0x0c271000 0 0x1000>,
2535 <0 0x0c222000 0 2512 <0 0x0c222000 0 0x1000>;
2536 2513
2537 interrupts-extended = 2514 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
2538 2515 <&intc GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>;
2539 interrupt-names = "up 2516 interrupt-names = "uplow",
2540 "cr 2517 "critical";
2541 2518
2542 #qcom,sensors = <16>; 2519 #qcom,sensors = <16>;
2543 2520
2544 #thermal-sensor-cells 2521 #thermal-sensor-cells = <1>;
2545 }; 2522 };
2546 2523
2547 tsens1: thermal-sensor@c27200 2524 tsens1: thermal-sensor@c272000 {
2548 compatible = "qcom,x1 2525 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2";
2549 reg = <0 0x0c272000 0 2526 reg = <0 0x0c272000 0 0x1000>,
2550 <0 0x0c223000 0 2527 <0 0x0c223000 0 0x1000>;
2551 2528
2552 interrupts-extended = 2529 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
2553 2530 <&intc GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>;
2554 interrupt-names = "up 2531 interrupt-names = "uplow",
2555 "cr 2532 "critical";
2556 2533
2557 #qcom,sensors = <16>; 2534 #qcom,sensors = <16>;
2558 2535
2559 #thermal-sensor-cells 2536 #thermal-sensor-cells = <1>;
2560 }; 2537 };
2561 2538
2562 tsens2: thermal-sensor@c27300 2539 tsens2: thermal-sensor@c273000 {
2563 compatible = "qcom,x1 2540 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2";
2564 reg = <0 0x0c273000 0 2541 reg = <0 0x0c273000 0 0x1000>,
2565 <0 0x0c224000 0 2542 <0 0x0c224000 0 0x1000>;
2566 2543
2567 interrupts-extended = 2544 interrupts-extended = <&pdc 28 IRQ_TYPE_LEVEL_HIGH>,
2568 2545 <&intc GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH>;
2569 interrupt-names = "up 2546 interrupt-names = "uplow",
2570 "cr 2547 "critical";
2571 2548
2572 #qcom,sensors = <16>; 2549 #qcom,sensors = <16>;
2573 2550
2574 #thermal-sensor-cells 2551 #thermal-sensor-cells = <1>;
2575 }; 2552 };
2576 2553
2577 tsens3: thermal-sensor@c27400 2554 tsens3: thermal-sensor@c274000 {
2578 compatible = "qcom,x1 2555 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2";
2579 reg = <0 0x0c274000 0 2556 reg = <0 0x0c274000 0 0x1000>,
2580 <0 0x0c225000 0 2557 <0 0x0c225000 0 0x1000>;
2581 2558
2582 interrupts-extended = 2559 interrupts-extended = <&pdc 29 IRQ_TYPE_LEVEL_HIGH>,
2583 2560 <&intc GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>;
2584 interrupt-names = "up 2561 interrupt-names = "uplow",
2585 "cr 2562 "critical";
2586 2563
2587 #qcom,sensors = <16>; 2564 #qcom,sensors = <16>;
2588 2565
2589 #thermal-sensor-cells 2566 #thermal-sensor-cells = <1>;
2590 }; 2567 };
2591 2568
2592 usb_1_ss0_hsphy: phy@fd3000 { 2569 usb_1_ss0_hsphy: phy@fd3000 {
2593 compatible = "qcom,x1 2570 compatible = "qcom,x1e80100-snps-eusb2-phy",
2594 "qcom,sm 2571 "qcom,sm8550-snps-eusb2-phy";
2595 reg = <0 0x00fd3000 0 2572 reg = <0 0x00fd3000 0 0x154>;
2596 #phy-cells = <0>; 2573 #phy-cells = <0>;
2597 2574
2598 clocks = <&tcsr TCSR_ 2575 clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>;
2599 clock-names = "ref"; 2576 clock-names = "ref";
2600 2577
2601 resets = <&gcc GCC_QU 2578 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2602 2579
2603 status = "disabled"; 2580 status = "disabled";
2604 }; 2581 };
2605 2582
2606 usb_1_ss0_qmpphy: phy@fd5000 2583 usb_1_ss0_qmpphy: phy@fd5000 {
2607 compatible = "qcom,x1 2584 compatible = "qcom,x1e80100-qmp-usb3-dp-phy";
2608 reg = <0 0x00fd5000 0 2585 reg = <0 0x00fd5000 0 0x4000>;
2609 2586
2610 clocks = <&gcc GCC_US 2587 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2611 <&rpmhcc RPM 2588 <&rpmhcc RPMH_CXO_CLK>,
2612 <&gcc GCC_US 2589 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
2613 <&gcc GCC_US 2590 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2614 clock-names = "aux", 2591 clock-names = "aux",
2615 "ref", 2592 "ref",
2616 "com_au 2593 "com_aux",
2617 "usb3_p 2594 "usb3_pipe";
2618 2595
2619 power-domains = <&gcc 2596 power-domains = <&gcc GCC_USB_0_PHY_GDSC>;
2620 2597
2621 resets = <&gcc GCC_US 2598 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
2622 <&gcc GCC_US 2599 <&gcc GCC_USB4_0_DP0_PHY_PRIM_BCR>;
2623 reset-names = "phy", 2600 reset-names = "phy",
2624 "common 2601 "common";
2625 2602
2626 #clock-cells = <1>; 2603 #clock-cells = <1>;
2627 #phy-cells = <1>; 2604 #phy-cells = <1>;
2628 2605
2629 orientation-switch; <<
2630 <<
2631 status = "disabled"; 2606 status = "disabled";
2632 2607
2633 ports { 2608 ports {
2634 #address-cell 2609 #address-cells = <1>;
2635 #size-cells = 2610 #size-cells = <0>;
2636 2611
2637 port@0 { 2612 port@0 {
2638 reg = 2613 reg = <0>;
2639 2614
2640 usb_1 2615 usb_1_ss0_qmpphy_out: endpoint {
2641 }; 2616 };
2642 }; 2617 };
2643 2618
2644 port@1 { 2619 port@1 {
2645 reg = 2620 reg = <1>;
2646 2621
2647 usb_1 2622 usb_1_ss0_qmpphy_usb_ss_in: endpoint {
2648 2623 remote-endpoint = <&usb_1_ss0_dwc3_ss>;
2649 }; 2624 };
2650 }; 2625 };
2651 2626
2652 port@2 { 2627 port@2 {
2653 reg = 2628 reg = <2>;
2654 2629
2655 usb_1 2630 usb_1_ss0_qmpphy_dp_in: endpoint {
2656 2631 remote-endpoint = <&mdss_dp0_out>;
2657 }; 2632 };
2658 }; 2633 };
2659 }; 2634 };
2660 }; 2635 };
2661 2636
2662 usb_1_ss1_hsphy: phy@fd9000 { 2637 usb_1_ss1_hsphy: phy@fd9000 {
2663 compatible = "qcom,x1 2638 compatible = "qcom,x1e80100-snps-eusb2-phy",
2664 "qcom,sm 2639 "qcom,sm8550-snps-eusb2-phy";
2665 reg = <0 0x00fd9000 0 2640 reg = <0 0x00fd9000 0 0x154>;
2666 #phy-cells = <0>; 2641 #phy-cells = <0>;
2667 2642
2668 clocks = <&tcsr TCSR_ 2643 clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>;
2669 clock-names = "ref"; 2644 clock-names = "ref";
2670 2645
2671 resets = <&gcc GCC_QU 2646 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
2672 2647
2673 status = "disabled"; 2648 status = "disabled";
2674 }; 2649 };
2675 2650
2676 usb_1_ss1_qmpphy: phy@fda000 2651 usb_1_ss1_qmpphy: phy@fda000 {
2677 compatible = "qcom,x1 2652 compatible = "qcom,x1e80100-qmp-usb3-dp-phy";
2678 reg = <0 0x00fda000 0 2653 reg = <0 0x00fda000 0 0x4000>;
2679 2654
2680 clocks = <&gcc GCC_US 2655 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
2681 <&rpmhcc RPM 2656 <&rpmhcc RPMH_CXO_CLK>,
2682 <&gcc GCC_US 2657 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
2683 <&gcc GCC_US 2658 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
2684 clock-names = "aux", 2659 clock-names = "aux",
2685 "ref", 2660 "ref",
2686 "com_au 2661 "com_aux",
2687 "usb3_p 2662 "usb3_pipe";
2688 2663
2689 power-domains = <&gcc 2664 power-domains = <&gcc GCC_USB_1_PHY_GDSC>;
2690 2665
2691 resets = <&gcc GCC_US 2666 resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
2692 <&gcc GCC_US 2667 <&gcc GCC_USB4_1_DP0_PHY_SEC_BCR>;
2693 reset-names = "phy", 2668 reset-names = "phy",
2694 "common 2669 "common";
2695 2670
2696 #clock-cells = <1>; 2671 #clock-cells = <1>;
2697 #phy-cells = <1>; 2672 #phy-cells = <1>;
2698 2673
2699 orientation-switch; <<
2700 <<
2701 status = "disabled"; 2674 status = "disabled";
2702 2675
2703 ports { 2676 ports {
2704 #address-cell 2677 #address-cells = <1>;
2705 #size-cells = 2678 #size-cells = <0>;
2706 2679
2707 port@0 { 2680 port@0 {
2708 reg = 2681 reg = <0>;
2709 2682
2710 usb_1 2683 usb_1_ss1_qmpphy_out: endpoint {
2711 }; 2684 };
2712 }; 2685 };
2713 2686
2714 port@1 { 2687 port@1 {
2715 reg = 2688 reg = <1>;
2716 2689
2717 usb_1 2690 usb_1_ss1_qmpphy_usb_ss_in: endpoint {
2718 2691 remote-endpoint = <&usb_1_ss1_dwc3_ss>;
2719 }; 2692 };
2720 }; 2693 };
2721 2694
2722 port@2 { 2695 port@2 {
2723 reg = 2696 reg = <2>;
2724 2697
2725 usb_1 2698 usb_1_ss1_qmpphy_dp_in: endpoint {
2726 2699 remote-endpoint = <&mdss_dp1_out>;
2727 }; 2700 };
2728 }; 2701 };
2729 }; 2702 };
2730 }; 2703 };
2731 2704
2732 usb_1_ss2_hsphy: phy@fde000 { 2705 usb_1_ss2_hsphy: phy@fde000 {
2733 compatible = "qcom,x1 2706 compatible = "qcom,x1e80100-snps-eusb2-phy",
2734 "qcom,sm 2707 "qcom,sm8550-snps-eusb2-phy";
2735 reg = <0 0x00fde000 0 2708 reg = <0 0x00fde000 0 0x154>;
2736 #phy-cells = <0>; 2709 #phy-cells = <0>;
2737 2710
2738 clocks = <&tcsr TCSR_ 2711 clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>;
2739 clock-names = "ref"; 2712 clock-names = "ref";
2740 2713
2741 resets = <&gcc GCC_QU 2714 resets = <&gcc GCC_QUSB2PHY_TERT_BCR>;
2742 2715
2743 status = "disabled"; 2716 status = "disabled";
2744 }; 2717 };
2745 2718
2746 usb_1_ss2_qmpphy: phy@fdf000 2719 usb_1_ss2_qmpphy: phy@fdf000 {
2747 compatible = "qcom,x1 2720 compatible = "qcom,x1e80100-qmp-usb3-dp-phy";
2748 reg = <0 0x00fdf000 0 2721 reg = <0 0x00fdf000 0 0x4000>;
2749 2722
2750 clocks = <&gcc GCC_US 2723 clocks = <&gcc GCC_USB3_TERT_PHY_AUX_CLK>,
2751 <&rpmhcc RPM 2724 <&rpmhcc RPMH_CXO_CLK>,
2752 <&gcc GCC_US 2725 <&gcc GCC_USB3_TERT_PHY_COM_AUX_CLK>,
2753 <&gcc GCC_US 2726 <&gcc GCC_USB3_TERT_PHY_PIPE_CLK>;
2754 clock-names = "aux", 2727 clock-names = "aux",
2755 "ref", 2728 "ref",
2756 "com_au 2729 "com_aux",
2757 "usb3_p 2730 "usb3_pipe";
2758 2731
2759 power-domains = <&gcc 2732 power-domains = <&gcc GCC_USB_2_PHY_GDSC>;
2760 2733
2761 resets = <&gcc GCC_US 2734 resets = <&gcc GCC_USB3_PHY_TERT_BCR>,
2762 <&gcc GCC_US 2735 <&gcc GCC_USB4_2_DP0_PHY_TERT_BCR>;
2763 reset-names = "phy", 2736 reset-names = "phy",
2764 "common 2737 "common";
2765 2738
2766 #clock-cells = <1>; 2739 #clock-cells = <1>;
2767 #phy-cells = <1>; 2740 #phy-cells = <1>;
2768 2741
2769 orientation-switch; <<
2770 <<
2771 status = "disabled"; 2742 status = "disabled";
2772 2743
2773 ports { 2744 ports {
2774 #address-cell 2745 #address-cells = <1>;
2775 #size-cells = 2746 #size-cells = <0>;
2776 2747
2777 port@0 { 2748 port@0 {
2778 reg = 2749 reg = <0>;
2779 2750
2780 usb_1 2751 usb_1_ss2_qmpphy_out: endpoint {
2781 }; 2752 };
2782 }; 2753 };
2783 2754
2784 port@1 { 2755 port@1 {
2785 reg = 2756 reg = <1>;
2786 2757
2787 usb_1 2758 usb_1_ss2_qmpphy_usb_ss_in: endpoint {
2788 2759 remote-endpoint = <&usb_1_ss2_dwc3_ss>;
2789 }; 2760 };
2790 }; 2761 };
2791 2762
2792 port@2 { 2763 port@2 {
2793 reg = 2764 reg = <2>;
2794 2765
2795 usb_1 2766 usb_1_ss2_qmpphy_dp_in: endpoint {
2796 2767 remote-endpoint = <&mdss_dp2_out>;
2797 }; 2768 };
2798 }; 2769 };
2799 }; 2770 };
2800 }; 2771 };
2801 2772
2802 cnoc_main: interconnect@15000 2773 cnoc_main: interconnect@1500000 {
2803 compatible = "qcom,x1 2774 compatible = "qcom,x1e80100-cnoc-main";
2804 reg = <0 0x01500000 0 !! 2775 reg = <0 0x1500000 0 0x14400>;
2805 2776
2806 qcom,bcm-voters = <&a 2777 qcom,bcm-voters = <&apps_bcm_voter>;
2807 2778
2808 #interconnect-cells = 2779 #interconnect-cells = <2>;
2809 }; 2780 };
2810 2781
2811 config_noc: interconnect@1600 2782 config_noc: interconnect@1600000 {
2812 compatible = "qcom,x1 2783 compatible = "qcom,x1e80100-cnoc-cfg";
2813 reg = <0 0x01600000 0 !! 2784 reg = <0 0x1600000 0 0x6600>;
2814 2785
2815 qcom,bcm-voters = <&a 2786 qcom,bcm-voters = <&apps_bcm_voter>;
2816 2787
2817 #interconnect-cells = 2788 #interconnect-cells = <2>;
2818 }; 2789 };
2819 2790
2820 system_noc: interconnect@1680 2791 system_noc: interconnect@1680000 {
2821 compatible = "qcom,x1 2792 compatible = "qcom,x1e80100-system-noc";
2822 reg = <0 0x01680000 0 !! 2793 reg = <0 0x1680000 0 0x1c080>;
2823 2794
2824 qcom,bcm-voters = <&a 2795 qcom,bcm-voters = <&apps_bcm_voter>;
2825 2796
2826 #interconnect-cells = 2797 #interconnect-cells = <2>;
2827 }; 2798 };
2828 2799
2829 pcie_south_anoc: interconnect 2800 pcie_south_anoc: interconnect@16c0000 {
2830 compatible = "qcom,x1 2801 compatible = "qcom,x1e80100-pcie-south-anoc";
2831 reg = <0 0x016c0000 0 !! 2802 reg = <0 0x16c0000 0 0xd080>;
2832 2803
2833 qcom,bcm-voters = <&a 2804 qcom,bcm-voters = <&apps_bcm_voter>;
2834 2805
2835 #interconnect-cells = 2806 #interconnect-cells = <2>;
2836 }; 2807 };
2837 2808
2838 pcie_center_anoc: interconnec 2809 pcie_center_anoc: interconnect@16d0000 {
2839 compatible = "qcom,x1 2810 compatible = "qcom,x1e80100-pcie-center-anoc";
2840 reg = <0 0x016d0000 0 !! 2811 reg = <0 0x16d0000 0 0x7000>;
2841 2812
2842 qcom,bcm-voters = <&a 2813 qcom,bcm-voters = <&apps_bcm_voter>;
2843 2814
2844 #interconnect-cells = 2815 #interconnect-cells = <2>;
2845 }; 2816 };
2846 2817
2847 aggre1_noc: interconnect@16e0 2818 aggre1_noc: interconnect@16e0000 {
2848 compatible = "qcom,x1 2819 compatible = "qcom,x1e80100-aggre1-noc";
2849 reg = <0 0x016e0000 0 !! 2820 reg = <0 0x16E0000 0 0x14400>;
2850 2821
2851 qcom,bcm-voters = <&a 2822 qcom,bcm-voters = <&apps_bcm_voter>;
2852 2823
2853 #interconnect-cells = 2824 #interconnect-cells = <2>;
2854 }; 2825 };
2855 2826
2856 aggre2_noc: interconnect@1700 2827 aggre2_noc: interconnect@1700000 {
2857 compatible = "qcom,x1 2828 compatible = "qcom,x1e80100-aggre2-noc";
2858 reg = <0 0x01700000 0 !! 2829 reg = <0 0x1700000 0 0x1c400>;
2859 2830
2860 qcom,bcm-voters = <&a 2831 qcom,bcm-voters = <&apps_bcm_voter>;
2861 2832
2862 #interconnect-cells = 2833 #interconnect-cells = <2>;
2863 }; 2834 };
2864 2835
2865 pcie_north_anoc: interconnect 2836 pcie_north_anoc: interconnect@1740000 {
2866 compatible = "qcom,x1 2837 compatible = "qcom,x1e80100-pcie-north-anoc";
2867 reg = <0 0x01740000 0 !! 2838 reg = <0 0x1740000 0 0x9080>;
2868 2839
2869 qcom,bcm-voters = <&a 2840 qcom,bcm-voters = <&apps_bcm_voter>;
2870 2841
2871 #interconnect-cells = 2842 #interconnect-cells = <2>;
2872 }; 2843 };
2873 2844
2874 usb_center_anoc: interconnect 2845 usb_center_anoc: interconnect@1750000 {
2875 compatible = "qcom,x1 2846 compatible = "qcom,x1e80100-usb-center-anoc";
2876 reg = <0 0x01750000 0 !! 2847 reg = <0 0x1750000 0 0x8800>;
2877 2848
2878 qcom,bcm-voters = <&a 2849 qcom,bcm-voters = <&apps_bcm_voter>;
2879 2850
2880 #interconnect-cells = 2851 #interconnect-cells = <2>;
2881 }; 2852 };
2882 2853
2883 usb_north_anoc: interconnect@ 2854 usb_north_anoc: interconnect@1760000 {
2884 compatible = "qcom,x1 2855 compatible = "qcom,x1e80100-usb-north-anoc";
2885 reg = <0 0x01760000 0 !! 2856 reg = <0 0x1760000 0 0x7080>;
2886 2857
2887 qcom,bcm-voters = <&a 2858 qcom,bcm-voters = <&apps_bcm_voter>;
2888 2859
2889 #interconnect-cells = 2860 #interconnect-cells = <2>;
2890 }; 2861 };
2891 2862
2892 usb_south_anoc: interconnect@ 2863 usb_south_anoc: interconnect@1770000 {
2893 compatible = "qcom,x1 2864 compatible = "qcom,x1e80100-usb-south-anoc";
2894 reg = <0 0x01770000 0 !! 2865 reg = <0 0x1770000 0 0xf080>;
2895 2866
2896 qcom,bcm-voters = <&a 2867 qcom,bcm-voters = <&apps_bcm_voter>;
2897 2868
2898 #interconnect-cells = 2869 #interconnect-cells = <2>;
2899 }; 2870 };
2900 2871
2901 mmss_noc: interconnect@178000 2872 mmss_noc: interconnect@1780000 {
2902 compatible = "qcom,x1 2873 compatible = "qcom,x1e80100-mmss-noc";
2903 reg = <0 0x01780000 0 !! 2874 reg = <0 0x1780000 0 0x5B800>;
2904 2875
2905 qcom,bcm-voters = <&a 2876 qcom,bcm-voters = <&apps_bcm_voter>;
2906 2877
2907 #interconnect-cells = 2878 #interconnect-cells = <2>;
2908 }; 2879 };
2909 2880
2910 pcie6a: pci@1bf8000 { 2881 pcie6a: pci@1bf8000 {
2911 device_type = "pci"; 2882 device_type = "pci";
2912 compatible = "qcom,pc 2883 compatible = "qcom,pcie-x1e80100";
2913 reg = <0 0x01bf8000 0 2884 reg = <0 0x01bf8000 0 0x3000>,
2914 <0 0x70000000 0 2885 <0 0x70000000 0 0xf20>,
2915 <0 0x70000f40 0 2886 <0 0x70000f40 0 0xa8>,
2916 <0 0x70001000 0 2887 <0 0x70001000 0 0x1000>,
2917 <0 0x70100000 0 2888 <0 0x70100000 0 0x100000>,
2918 <0 0x01bfb000 0 2889 <0 0x01bfb000 0 0x1000>;
2919 reg-names = "parf", 2890 reg-names = "parf",
2920 "dbi", 2891 "dbi",
2921 "elbi", 2892 "elbi",
2922 "atu", 2893 "atu",
2923 "config", 2894 "config",
2924 "mhi"; 2895 "mhi";
2925 #address-cells = <3>; 2896 #address-cells = <3>;
2926 #size-cells = <2>; 2897 #size-cells = <2>;
2927 ranges = <0x01000000 2898 ranges = <0x01000000 0x0 0x00000000 0x0 0x70200000 0x0 0x100000>,
2928 <0x02000000 2899 <0x02000000 0x0 0x70300000 0x0 0x70300000 0x0 0x1d00000>;
2929 bus-range = <0x00 0xf 2900 bus-range = <0x00 0xff>;
2930 2901
2931 dma-coherent; 2902 dma-coherent;
2932 2903
2933 linux,pci-domain = <6 2904 linux,pci-domain = <6>;
2934 num-lanes = <4>; !! 2905 num-lanes = <2>;
2935 2906
2936 interrupts = <GIC_SPI 2907 interrupts = <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,
2937 <GIC_SPI 2908 <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>,
2938 <GIC_SPI 2909 <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>,
2939 <GIC_SPI 2910 <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>,
2940 <GIC_SPI 2911 <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>,
2941 <GIC_SPI 2912 <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>,
2942 <GIC_SPI 2913 <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>,
2943 <GIC_SPI 2914 <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>;
2944 interrupt-names = "ms 2915 interrupt-names = "msi0",
2945 "ms 2916 "msi1",
2946 "ms 2917 "msi2",
2947 "ms 2918 "msi3",
2948 "ms 2919 "msi4",
2949 "ms 2920 "msi5",
2950 "ms 2921 "msi6",
2951 "ms 2922 "msi7";
2952 2923
2953 #interrupt-cells = <1 2924 #interrupt-cells = <1>;
2954 interrupt-map-mask = 2925 interrupt-map-mask = <0 0 0 0x7>;
2955 interrupt-map = <0 0 2926 interrupt-map = <0 0 0 1 &intc 0 0 0 843 IRQ_TYPE_LEVEL_HIGH>,
2956 <0 0 2927 <0 0 0 2 &intc 0 0 0 844 IRQ_TYPE_LEVEL_HIGH>,
2957 <0 0 2928 <0 0 0 3 &intc 0 0 0 845 IRQ_TYPE_LEVEL_HIGH>,
2958 <0 0 2929 <0 0 0 4 &intc 0 0 0 772 IRQ_TYPE_LEVEL_HIGH>;
2959 2930
2960 clocks = <&gcc GCC_PC 2931 clocks = <&gcc GCC_PCIE_6A_AUX_CLK>,
2961 <&gcc GCC_PC 2932 <&gcc GCC_PCIE_6A_CFG_AHB_CLK>,
2962 <&gcc GCC_PC 2933 <&gcc GCC_PCIE_6A_MSTR_AXI_CLK>,
2963 <&gcc GCC_PC 2934 <&gcc GCC_PCIE_6A_SLV_AXI_CLK>,
2964 <&gcc GCC_PC 2935 <&gcc GCC_PCIE_6A_SLV_Q2A_AXI_CLK>,
2965 <&gcc GCC_CF 2936 <&gcc GCC_CFG_NOC_PCIE_ANOC_SOUTH_AHB_CLK>,
2966 <&gcc GCC_CN 2937 <&gcc GCC_CNOC_PCIE_SOUTH_SF_AXI_CLK>;
2967 clock-names = "aux", 2938 clock-names = "aux",
2968 "cfg", 2939 "cfg",
2969 "bus_ma 2940 "bus_master",
2970 "bus_sl 2941 "bus_slave",
2971 "slave_ 2942 "slave_q2a",
2972 "noc_ag 2943 "noc_aggr",
2973 "cnoc_s 2944 "cnoc_sf_axi";
2974 2945
2975 assigned-clocks = <&g 2946 assigned-clocks = <&gcc GCC_PCIE_6A_AUX_CLK>;
2976 assigned-clock-rates 2947 assigned-clock-rates = <19200000>;
2977 2948
2978 interconnects = <&pci 2949 interconnects = <&pcie_south_anoc MASTER_PCIE_6A QCOM_ICC_TAG_ALWAYS
2979 &mc_ 2950 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
2980 <&gem 2951 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2981 &cno 2952 &cnoc_main SLAVE_PCIE_6A QCOM_ICC_TAG_ALWAYS>;
2982 interconnect-names = 2953 interconnect-names = "pcie-mem",
2983 2954 "cpu-pcie";
2984 2955
2985 resets = <&gcc GCC_PC 2956 resets = <&gcc GCC_PCIE_6A_BCR>,
2986 <&gcc GCC_PC 2957 <&gcc GCC_PCIE_6A_LINK_DOWN_BCR>;
2987 reset-names = "pci", 2958 reset-names = "pci",
2988 "link_d 2959 "link_down";
2989 2960
2990 power-domains = <&gcc 2961 power-domains = <&gcc GCC_PCIE_6A_GDSC>;
2991 required-opps = <&rpm 2962 required-opps = <&rpmhpd_opp_nom>;
2992 2963
2993 phys = <&pcie6a_phy>; 2964 phys = <&pcie6a_phy>;
2994 phy-names = "pciephy" 2965 phy-names = "pciephy";
2995 2966
2996 status = "disabled"; 2967 status = "disabled";
2997 }; 2968 };
2998 2969
2999 pcie6a_phy: phy@1bfc000 { 2970 pcie6a_phy: phy@1bfc000 {
3000 compatible = "qcom,x1 !! 2971 compatible = "qcom,x1e80100-qmp-gen4x2-pcie-phy";
3001 reg = <0 0x01bfc000 0 !! 2972 reg = <0 0x01bfc000 0 0x2000>;
3002 <0 0x01bfe000 0 <<
3003 2973
3004 clocks = <&gcc GCC_PC 2974 clocks = <&gcc GCC_PCIE_6A_PHY_AUX_CLK>,
3005 <&gcc GCC_PC 2975 <&gcc GCC_PCIE_6A_CFG_AHB_CLK>,
3006 <&tcsr TCSR_ 2976 <&tcsr TCSR_PCIE_4L_CLKREF_EN>,
3007 <&gcc GCC_PC 2977 <&gcc GCC_PCIE_6A_PHY_RCHNG_CLK>,
3008 <&gcc GCC_PC 2978 <&gcc GCC_PCIE_6A_PIPE_CLK>,
3009 <&gcc GCC_PC 2979 <&gcc GCC_PCIE_6A_PIPEDIV2_CLK>;
3010 clock-names = "aux", 2980 clock-names = "aux",
3011 "cfg_ah 2981 "cfg_ahb",
3012 "ref", 2982 "ref",
3013 "rchng" 2983 "rchng",
3014 "pipe", 2984 "pipe",
3015 "pipedi 2985 "pipediv2";
3016 2986
3017 resets = <&gcc GCC_PC 2987 resets = <&gcc GCC_PCIE_6A_PHY_BCR>,
3018 <&gcc GCC_PC 2988 <&gcc GCC_PCIE_6A_NOCSR_COM_PHY_BCR>;
3019 reset-names = "phy", 2989 reset-names = "phy",
3020 "phy_no 2990 "phy_nocsr";
3021 2991
3022 assigned-clocks = <&g 2992 assigned-clocks = <&gcc GCC_PCIE_6A_PHY_RCHNG_CLK>;
3023 assigned-clock-rates 2993 assigned-clock-rates = <100000000>;
3024 2994
3025 power-domains = <&gcc 2995 power-domains = <&gcc GCC_PCIE_6_PHY_GDSC>;
3026 2996
3027 qcom,4ln-config-sel = <<
3028 <<
3029 #clock-cells = <0>; 2997 #clock-cells = <0>;
3030 clock-output-names = 2998 clock-output-names = "pcie6a_pipe_clk";
3031 2999
3032 #phy-cells = <0>; 3000 #phy-cells = <0>;
3033 3001
3034 status = "disabled"; 3002 status = "disabled";
3035 }; 3003 };
3036 3004
3037 pcie5: pci@1c00000 { <<
3038 device_type = "pci"; <<
3039 compatible = "qcom,pc <<
3040 reg = <0 0x01c00000 0 <<
3041 <0 0x7e000000 0 <<
3042 <0 0x7e000f40 0 <<
3043 <0 0x7e001000 0 <<
3044 <0 0x7e100000 0 <<
3045 <0 0x01c03000 0 <<
3046 reg-names = "parf", <<
3047 "dbi", <<
3048 "elbi", <<
3049 "atu", <<
3050 "config", <<
3051 "mhi"; <<
3052 #address-cells = <3>; <<
3053 #size-cells = <2>; <<
3054 ranges = <0x01000000 <<
3055 <0x02000000 <<
3056 bus-range = <0x00 0xf <<
3057 <<
3058 dma-coherent; <<
3059 <<
3060 linux,pci-domain = <5 <<
3061 num-lanes = <2>; <<
3062 <<
3063 interrupts = <GIC_SPI <<
3064 <GIC_SPI <<
3065 <GIC_SPI <<
3066 <GIC_SPI <<
3067 <GIC_SPI <<
3068 <GIC_SPI <<
3069 <GIC_SPI <<
3070 <GIC_SPI <<
3071 interrupt-names = "ms <<
3072 "ms <<
3073 "ms <<
3074 "ms <<
3075 "ms <<
3076 "ms <<
3077 "ms <<
3078 "ms <<
3079 <<
3080 #interrupt-cells = <1 <<
3081 interrupt-map-mask = <<
3082 interrupt-map = <0 0 <<
3083 <0 0 <<
3084 <0 0 <<
3085 <0 0 <<
3086 <<
3087 clocks = <&gcc GCC_PC <<
3088 <&gcc GCC_PC <<
3089 <&gcc GCC_PC <<
3090 <&gcc GCC_PC <<
3091 <&gcc GCC_PC <<
3092 <&gcc GCC_CF <<
3093 <&gcc GCC_CN <<
3094 clock-names = "aux", <<
3095 "cfg", <<
3096 "bus_ma <<
3097 "bus_sl <<
3098 "slave_ <<
3099 "noc_ag <<
3100 "cnoc_s <<
3101 <<
3102 assigned-clocks = <&g <<
3103 assigned-clock-rates <<
3104 <<
3105 interconnects = <&pci <<
3106 &mc_ <<
3107 <&gem <<
3108 &cno <<
3109 interconnect-names = <<
3110 <<
3111 <<
3112 resets = <&gcc GCC_PC <<
3113 <&gcc GCC_PC <<
3114 reset-names = "pci", <<
3115 "link_d <<
3116 <<
3117 power-domains = <&gcc <<
3118 required-opps = <&rpm <<
3119 <<
3120 phys = <&pcie5_phy>; <<
3121 phy-names = "pciephy" <<
3122 <<
3123 status = "disabled"; <<
3124 }; <<
3125 <<
3126 pcie5_phy: phy@1c06000 { <<
3127 compatible = "qcom,x1 <<
3128 reg = <0 0x01c06000 0 <<
3129 <<
3130 clocks = <&gcc GCC_PC <<
3131 <&gcc GCC_PC <<
3132 <&tcsr TCSR_ <<
3133 <&gcc GCC_PC <<
3134 <&gcc GCC_PC <<
3135 <&gcc GCC_PC <<
3136 clock-names = "aux", <<
3137 "cfg_ah <<
3138 "ref", <<
3139 "rchng" <<
3140 "pipe", <<
3141 "pipedi <<
3142 <<
3143 resets = <&gcc GCC_PC <<
3144 reset-names = "phy"; <<
3145 <<
3146 assigned-clocks = <&g <<
3147 assigned-clock-rates <<
3148 <<
3149 power-domains = <&gcc <<
3150 <<
3151 #clock-cells = <0>; <<
3152 clock-output-names = <<
3153 <<
3154 #phy-cells = <0>; <<
3155 <<
3156 status = "disabled"; <<
3157 }; <<
3158 <<
3159 pcie4: pci@1c08000 { 3005 pcie4: pci@1c08000 {
3160 device_type = "pci"; 3006 device_type = "pci";
3161 compatible = "qcom,pc 3007 compatible = "qcom,pcie-x1e80100";
3162 reg = <0 0x01c08000 0 3008 reg = <0 0x01c08000 0 0x3000>,
3163 <0 0x7c000000 0 3009 <0 0x7c000000 0 0xf1d>,
3164 <0 0x7c000f40 0 3010 <0 0x7c000f40 0 0xa8>,
3165 <0 0x7c001000 0 3011 <0 0x7c001000 0 0x1000>,
3166 <0 0x7c100000 0 3012 <0 0x7c100000 0 0x100000>,
3167 <0 0x01c0b000 0 3013 <0 0x01c0b000 0 0x1000>;
3168 reg-names = "parf", 3014 reg-names = "parf",
3169 "dbi", 3015 "dbi",
3170 "elbi", 3016 "elbi",
3171 "atu", 3017 "atu",
3172 "config", 3018 "config",
3173 "mhi"; 3019 "mhi";
3174 #address-cells = <3>; 3020 #address-cells = <3>;
3175 #size-cells = <2>; 3021 #size-cells = <2>;
3176 ranges = <0x01000000 3022 ranges = <0x01000000 0x0 0x00000000 0x0 0x7c200000 0x0 0x100000>,
3177 <0x02000000 3023 <0x02000000 0x0 0x7c300000 0x0 0x7c300000 0x0 0x1d00000>;
3178 bus-range = <0x00 0xf 3024 bus-range = <0x00 0xff>;
3179 3025
3180 dma-coherent; 3026 dma-coherent;
3181 3027
3182 linux,pci-domain = <4 3028 linux,pci-domain = <4>;
3183 num-lanes = <2>; 3029 num-lanes = <2>;
3184 3030
3185 interrupts = <GIC_SPI 3031 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
3186 <GIC_SPI 3032 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
3187 <GIC_SPI 3033 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
3188 <GIC_SPI 3034 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
3189 <GIC_SPI 3035 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
3190 <GIC_SPI 3036 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
3191 <GIC_SPI 3037 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
3192 <GIC_SPI 3038 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
3193 interrupt-names = "ms 3039 interrupt-names = "msi0",
3194 "ms 3040 "msi1",
3195 "ms 3041 "msi2",
3196 "ms 3042 "msi3",
3197 "ms 3043 "msi4",
3198 "ms 3044 "msi5",
3199 "ms 3045 "msi6",
3200 "ms 3046 "msi7";
3201 3047
3202 #interrupt-cells = <1 3048 #interrupt-cells = <1>;
3203 interrupt-map-mask = 3049 interrupt-map-mask = <0 0 0 0x7>;
3204 interrupt-map = <0 0 3050 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>,
3205 <0 0 3051 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>,
3206 <0 0 3052 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>,
3207 <0 0 3053 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>;
3208 3054
3209 clocks = <&gcc GCC_PC 3055 clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
3210 <&gcc GCC_PC 3056 <&gcc GCC_PCIE_4_CFG_AHB_CLK>,
3211 <&gcc GCC_PC 3057 <&gcc GCC_PCIE_4_MSTR_AXI_CLK>,
3212 <&gcc GCC_PC 3058 <&gcc GCC_PCIE_4_SLV_AXI_CLK>,
3213 <&gcc GCC_PC 3059 <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>,
3214 <&gcc GCC_CF 3060 <&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>,
3215 <&gcc GCC_CN 3061 <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>;
3216 clock-names = "aux", 3062 clock-names = "aux",
3217 "cfg", 3063 "cfg",
3218 "bus_ma 3064 "bus_master",
3219 "bus_sl 3065 "bus_slave",
3220 "slave_ 3066 "slave_q2a",
3221 "noc_ag 3067 "noc_aggr",
3222 "cnoc_s 3068 "cnoc_sf_axi";
3223 3069
3224 assigned-clocks = <&g 3070 assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>;
3225 assigned-clock-rates 3071 assigned-clock-rates = <19200000>;
3226 3072
3227 interconnects = <&pci 3073 interconnects = <&pcie_north_anoc MASTER_PCIE_4 QCOM_ICC_TAG_ALWAYS
3228 &mc_ 3074 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
3229 <&gem 3075 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
3230 &cno 3076 &cnoc_main SLAVE_PCIE_4 QCOM_ICC_TAG_ALWAYS>;
3231 interconnect-names = 3077 interconnect-names = "pcie-mem",
3232 3078 "cpu-pcie";
3233 3079
3234 resets = <&gcc GCC_PC 3080 resets = <&gcc GCC_PCIE_4_BCR>,
3235 <&gcc GCC_PC 3081 <&gcc GCC_PCIE_4_LINK_DOWN_BCR>;
3236 reset-names = "pci", 3082 reset-names = "pci",
3237 "link_d 3083 "link_down";
3238 3084
3239 power-domains = <&gcc 3085 power-domains = <&gcc GCC_PCIE_4_GDSC>;
3240 required-opps = <&rpm 3086 required-opps = <&rpmhpd_opp_nom>;
3241 3087
3242 phys = <&pcie4_phy>; 3088 phys = <&pcie4_phy>;
3243 phy-names = "pciephy" 3089 phy-names = "pciephy";
3244 3090
3245 status = "disabled"; 3091 status = "disabled";
3246 3092
3247 pcie4_port0: pcie@0 { 3093 pcie4_port0: pcie@0 {
3248 device_type = 3094 device_type = "pci";
3249 reg = <0x0 0x 3095 reg = <0x0 0x0 0x0 0x0 0x0>;
3250 bus-range = < 3096 bus-range = <0x01 0xff>;
3251 3097
3252 #address-cell 3098 #address-cells = <3>;
3253 #size-cells = 3099 #size-cells = <2>;
3254 ranges; 3100 ranges;
3255 }; 3101 };
3256 }; 3102 };
3257 3103
3258 pcie4_phy: phy@1c0e000 { 3104 pcie4_phy: phy@1c0e000 {
3259 compatible = "qcom,x1 3105 compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy";
3260 reg = <0 0x01c0e000 0 3106 reg = <0 0x01c0e000 0 0x2000>;
3261 3107
3262 clocks = <&gcc GCC_PC 3108 clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
3263 <&gcc GCC_PC 3109 <&gcc GCC_PCIE_4_CFG_AHB_CLK>,
3264 <&tcsr TCSR_ 3110 <&tcsr TCSR_PCIE_2L_4_CLKREF_EN>,
3265 <&gcc GCC_PC 3111 <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>,
3266 <&gcc GCC_PC 3112 <&gcc GCC_PCIE_4_PIPE_CLK>,
3267 <&gcc GCC_PC 3113 <&gcc GCC_PCIE_4_PIPEDIV2_CLK>;
3268 clock-names = "aux", 3114 clock-names = "aux",
3269 "cfg_ah 3115 "cfg_ahb",
3270 "ref", 3116 "ref",
3271 "rchng" 3117 "rchng",
3272 "pipe", 3118 "pipe",
3273 "pipedi 3119 "pipediv2";
3274 3120
3275 resets = <&gcc GCC_PC 3121 resets = <&gcc GCC_PCIE_4_PHY_BCR>;
3276 reset-names = "phy"; 3122 reset-names = "phy";
3277 3123
3278 assigned-clocks = <&g 3124 assigned-clocks = <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>;
3279 assigned-clock-rates 3125 assigned-clock-rates = <100000000>;
3280 3126
3281 power-domains = <&gcc 3127 power-domains = <&gcc GCC_PCIE_4_PHY_GDSC>;
3282 3128
3283 #clock-cells = <0>; 3129 #clock-cells = <0>;
3284 clock-output-names = 3130 clock-output-names = "pcie4_pipe_clk";
3285 3131
3286 #phy-cells = <0>; 3132 #phy-cells = <0>;
3287 3133
3288 status = "disabled"; 3134 status = "disabled";
3289 }; 3135 };
3290 3136
3291 tcsr_mutex: hwlock@1f40000 { 3137 tcsr_mutex: hwlock@1f40000 {
3292 compatible = "qcom,tc 3138 compatible = "qcom,tcsr-mutex";
3293 reg = <0 0x01f40000 0 3139 reg = <0 0x01f40000 0 0x20000>;
3294 #hwlock-cells = <1>; 3140 #hwlock-cells = <1>;
3295 }; 3141 };
3296 3142
3297 tcsr: clock-controller@1fc000 3143 tcsr: clock-controller@1fc0000 {
3298 compatible = "qcom,x1 3144 compatible = "qcom,x1e80100-tcsr", "syscon";
3299 reg = <0 0x01fc0000 0 3145 reg = <0 0x01fc0000 0 0x30000>;
3300 clocks = <&rpmhcc RPM 3146 clocks = <&rpmhcc RPMH_CXO_CLK>;
3301 #clock-cells = <1>; 3147 #clock-cells = <1>;
3302 #reset-cells = <1>; 3148 #reset-cells = <1>;
3303 }; 3149 };
3304 3150
3305 gpu: gpu@3d00000 { 3151 gpu: gpu@3d00000 {
3306 compatible = "qcom,ad 3152 compatible = "qcom,adreno-43050c01", "qcom,adreno";
3307 reg = <0x0 0x03d00000 3153 reg = <0x0 0x03d00000 0x0 0x40000>,
3308 <0x0 0x03d9e000 3154 <0x0 0x03d9e000 0x0 0x1000>,
3309 <0x0 0x03d61000 3155 <0x0 0x03d61000 0x0 0x800>;
3310 3156
3311 reg-names = "kgsl_3d0 3157 reg-names = "kgsl_3d0_reg_memory",
3312 "cx_mem", 3158 "cx_mem",
3313 "cx_dbgc" 3159 "cx_dbgc";
3314 3160
3315 interrupts = <GIC_SPI 3161 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
3316 3162
3317 iommus = <&adreno_smm 3163 iommus = <&adreno_smmu 0 0x0>,
3318 <&adreno_smm 3164 <&adreno_smmu 1 0x0>;
3319 3165
3320 operating-points-v2 = 3166 operating-points-v2 = <&gpu_opp_table>;
3321 3167
3322 qcom,gmu = <&gmu>; 3168 qcom,gmu = <&gmu>;
3323 #cooling-cells = <2>; 3169 #cooling-cells = <2>;
3324 3170
3325 interconnects = <&gem 3171 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
3326 interconnect-names = 3172 interconnect-names = "gfx-mem";
3327 3173
3328 status = "disabled"; 3174 status = "disabled";
3329 3175
3330 zap-shader { 3176 zap-shader {
3331 memory-region 3177 memory-region = <&gpu_microcode_mem>;
3332 }; 3178 };
3333 3179
3334 gpu_opp_table: opp-ta 3180 gpu_opp_table: opp-table {
3335 compatible = 3181 compatible = "operating-points-v2";
3336 3182
3337 opp-110000000 3183 opp-1100000000 {
3338 opp-h 3184 opp-hz = /bits/ 64 <1100000000>;
3339 opp-l 3185 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3340 opp-p 3186 opp-peak-kBps = <16500000>;
3341 }; 3187 };
3342 3188
3343 opp-100000000 3189 opp-1000000000 {
3344 opp-h 3190 opp-hz = /bits/ 64 <1000000000>;
3345 opp-l 3191 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3346 opp-p 3192 opp-peak-kBps = <14398438>;
3347 }; 3193 };
3348 3194
3349 opp-925000000 3195 opp-925000000 {
3350 opp-h 3196 opp-hz = /bits/ 64 <925000000>;
3351 opp-l 3197 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3352 opp-p 3198 opp-peak-kBps = <14398438>;
3353 }; 3199 };
3354 3200
3355 opp-800000000 3201 opp-800000000 {
3356 opp-h 3202 opp-hz = /bits/ 64 <800000000>;
3357 opp-l 3203 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3358 opp-p 3204 opp-peak-kBps = <12449219>;
3359 }; 3205 };
3360 3206
3361 opp-744000000 3207 opp-744000000 {
3362 opp-h 3208 opp-hz = /bits/ 64 <744000000>;
3363 opp-l 3209 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
3364 opp-p 3210 opp-peak-kBps = <10687500>;
3365 }; 3211 };
3366 3212
3367 opp-687000000 3213 opp-687000000 {
3368 opp-h 3214 opp-hz = /bits/ 64 <687000000>;
3369 opp-l 3215 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3370 opp-p 3216 opp-peak-kBps = <8171875>;
3371 }; 3217 };
3372 3218
3373 opp-550000000 3219 opp-550000000 {
3374 opp-h 3220 opp-hz = /bits/ 64 <550000000>;
3375 opp-l 3221 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3376 opp-p 3222 opp-peak-kBps = <6074219>;
3377 }; 3223 };
3378 3224
3379 opp-390000000 3225 opp-390000000 {
3380 opp-h 3226 opp-hz = /bits/ 64 <390000000>;
3381 opp-l 3227 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3382 opp-p 3228 opp-peak-kBps = <3000000>;
3383 }; 3229 };
3384 3230
3385 opp-300000000 3231 opp-300000000 {
3386 opp-h 3232 opp-hz = /bits/ 64 <300000000>;
3387 opp-l 3233 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
3388 opp-p 3234 opp-peak-kBps = <2136719>;
3389 }; 3235 };
3390 }; 3236 };
3391 }; 3237 };
3392 3238
3393 gmu: gmu@3d6a000 { 3239 gmu: gmu@3d6a000 {
3394 compatible = "qcom,ad 3240 compatible = "qcom,adreno-gmu-x185.1", "qcom,adreno-gmu";
3395 reg = <0x0 0x03d6a000 3241 reg = <0x0 0x03d6a000 0x0 0x35000>,
3396 <0x0 0x03d50000 3242 <0x0 0x03d50000 0x0 0x10000>,
3397 <0x0 0x0b280000 3243 <0x0 0x0b280000 0x0 0x10000>;
3398 reg-names = "gmu", " 3244 reg-names = "gmu", "rscc", "gmu_pdc";
3399 3245
3400 interrupts = <GIC_SPI 3246 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
3401 <GIC_SPI 3247 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
3402 interrupt-names = "hf 3248 interrupt-names = "hfi", "gmu";
3403 3249
3404 clocks = <&gpucc GPU_ 3250 clocks = <&gpucc GPU_CC_AHB_CLK>,
3405 <&gpucc GPU_ 3251 <&gpucc GPU_CC_CX_GMU_CLK>,
3406 <&gpucc GPU_ 3252 <&gpucc GPU_CC_CXO_CLK>,
3407 <&gcc GCC_DD 3253 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
3408 <&gcc GCC_GP 3254 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
3409 <&gpucc GPU_ 3255 <&gpucc GPU_CC_HUB_CX_INT_CLK>,
3410 <&gpucc GPU_ 3256 <&gpucc GPU_CC_DEMET_CLK>;
3411 clock-names = "ahb", 3257 clock-names = "ahb",
3412 "gmu", 3258 "gmu",
3413 "cxo", 3259 "cxo",
3414 "axi", 3260 "axi",
3415 "memnoc 3261 "memnoc",
3416 "hub", 3262 "hub",
3417 "demet" 3263 "demet";
3418 3264
3419 power-domains = <&gpu 3265 power-domains = <&gpucc GPU_CX_GDSC>,
3420 <&gpu 3266 <&gpucc GPU_GX_GDSC>;
3421 power-domain-names = 3267 power-domain-names = "cx",
3422 3268 "gx";
3423 3269
3424 iommus = <&adreno_smm 3270 iommus = <&adreno_smmu 5 0x0>;
3425 3271
3426 qcom,qmp = <&aoss_qmp 3272 qcom,qmp = <&aoss_qmp>;
3427 3273
3428 operating-points-v2 = 3274 operating-points-v2 = <&gmu_opp_table>;
3429 3275
3430 gmu_opp_table: opp-ta 3276 gmu_opp_table: opp-table {
3431 compatible = 3277 compatible = "operating-points-v2";
3432 3278
3433 opp-550000000 3279 opp-550000000 {
3434 opp-h 3280 opp-hz = /bits/ 64 <550000000>;
3435 opp-l 3281 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3436 }; 3282 };
3437 3283
3438 opp-220000000 3284 opp-220000000 {
3439 opp-h 3285 opp-hz = /bits/ 64 <220000000>;
3440 opp-l 3286 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3441 }; 3287 };
3442 }; 3288 };
3443 }; 3289 };
3444 3290
3445 gpucc: clock-controller@3d900 3291 gpucc: clock-controller@3d90000 {
3446 compatible = "qcom,x1 3292 compatible = "qcom,x1e80100-gpucc";
3447 reg = <0 0x03d90000 0 3293 reg = <0 0x03d90000 0 0xa000>;
3448 clocks = <&bi_tcxo_di 3294 clocks = <&bi_tcxo_div2>,
3449 <&gcc GCC_GP 3295 <&gcc GCC_GPU_GPLL0_CPH_CLK_SRC>,
3450 <&gcc GCC_GP 3296 <&gcc GCC_GPU_GPLL0_DIV_CPH_CLK_SRC>;
3451 #clock-cells = <1>; 3297 #clock-cells = <1>;
3452 #reset-cells = <1>; 3298 #reset-cells = <1>;
3453 #power-domain-cells = 3299 #power-domain-cells = <1>;
3454 }; 3300 };
3455 3301
3456 adreno_smmu: iommu@3da0000 { 3302 adreno_smmu: iommu@3da0000 {
3457 compatible = "qcom,x1 3303 compatible = "qcom,x1e80100-smmu-500", "qcom,adreno-smmu",
3458 "qcom,sm 3304 "qcom,smmu-500", "arm,mmu-500";
3459 reg = <0x0 0x03da0000 3305 reg = <0x0 0x03da0000 0x0 0x40000>;
3460 #iommu-cells = <2>; 3306 #iommu-cells = <2>;
3461 #global-interrupts = 3307 #global-interrupts = <1>;
3462 interrupts = <GIC_SPI 3308 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
3463 <GIC_SPI 3309 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
3464 <GIC_SPI 3310 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
3465 <GIC_SPI 3311 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
3466 <GIC_SPI 3312 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
3467 <GIC_SPI 3313 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
3468 <GIC_SPI 3314 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
3469 <GIC_SPI 3315 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
3470 <GIC_SPI 3316 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
3471 <GIC_SPI 3317 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
3472 <GIC_SPI 3318 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
3473 <GIC_SPI 3319 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>,
3474 <GIC_SPI 3320 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
3475 <GIC_SPI 3321 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
3476 <GIC_SPI 3322 <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>,
3477 <GIC_SPI 3323 <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>,
3478 <GIC_SPI 3324 <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
3479 <GIC_SPI 3325 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>,
3480 <GIC_SPI 3326 <GIC_SPI 660 IRQ_TYPE_LEVEL_HIGH>,
3481 <GIC_SPI 3327 <GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH>,
3482 <GIC_SPI 3328 <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>,
3483 <GIC_SPI 3329 <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>,
3484 <GIC_SPI 3330 <GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH>,
3485 <GIC_SPI 3331 <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>,
3486 <GIC_SPI 3332 <GIC_SPI 670 IRQ_TYPE_LEVEL_HIGH>,
3487 <GIC_SPI 3333 <GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH>;
3488 clocks = <&gpucc GPU_ 3334 clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
3489 <&gcc GCC_GP 3335 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
3490 <&gcc GCC_GP 3336 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
3491 <&gpucc GPU_ 3337 <&gpucc GPU_CC_AHB_CLK>;
3492 clock-names = "hlos", 3338 clock-names = "hlos",
3493 "bus", 3339 "bus",
3494 "iface" 3340 "iface",
3495 "ahb"; 3341 "ahb";
3496 power-domains = <&gpu 3342 power-domains = <&gpucc GPU_CX_GDSC>;
3497 dma-coherent; 3343 dma-coherent;
3498 }; 3344 };
3499 3345
3500 gem_noc: interconnect@2640000 3346 gem_noc: interconnect@26400000 {
3501 compatible = "qcom,x1 3347 compatible = "qcom,x1e80100-gem-noc";
3502 reg = <0 0x26400000 0 3348 reg = <0 0x26400000 0 0x311200>;
3503 3349
3504 qcom,bcm-voters = <&a 3350 qcom,bcm-voters = <&apps_bcm_voter>;
3505 3351
3506 #interconnect-cells = 3352 #interconnect-cells = <2>;
3507 }; 3353 };
3508 3354
3509 nsp_noc: interconnect@320c000 3355 nsp_noc: interconnect@320c0000 {
3510 compatible = "qcom,x1 3356 compatible = "qcom,x1e80100-nsp-noc";
3511 reg = <0 0x320C0000 0 !! 3357 reg = <0 0x320C0000 0 0xE080>;
3512 3358
3513 qcom,bcm-voters = <&a 3359 qcom,bcm-voters = <&apps_bcm_voter>;
3514 3360
3515 #interconnect-cells = 3361 #interconnect-cells = <2>;
3516 }; 3362 };
3517 3363
3518 lpass_wsa2macro: codec@6aa000 3364 lpass_wsa2macro: codec@6aa0000 {
3519 compatible = "qcom,x1 3365 compatible = "qcom,x1e80100-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro";
3520 reg = <0 0x06aa0000 0 3366 reg = <0 0x06aa0000 0 0x1000>;
3521 clocks = <&q6prmcc LP 3367 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3522 <&q6prmcc LP 3368 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3523 <&q6prmcc LP 3369 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3524 <&lpass_vama 3370 <&lpass_vamacro>;
3525 clock-names = "mclk", 3371 clock-names = "mclk",
3526 "macro" 3372 "macro",
3527 "dcodec 3373 "dcodec",
3528 "fsgen" 3374 "fsgen";
3529 3375
3530 #clock-cells = <0>; 3376 #clock-cells = <0>;
3531 clock-output-names = 3377 clock-output-names = "wsa2-mclk";
3532 #sound-dai-cells = <1 3378 #sound-dai-cells = <1>;
3533 sound-name-prefix = " 3379 sound-name-prefix = "WSA2";
3534 }; 3380 };
3535 3381
3536 swr3: soundwire@6ab0000 { 3382 swr3: soundwire@6ab0000 {
3537 compatible = "qcom,so 3383 compatible = "qcom,soundwire-v2.0.0";
3538 reg = <0 0x06ab0000 0 3384 reg = <0 0x06ab0000 0 0x10000>;
3539 clocks = <&lpass_wsa2 3385 clocks = <&lpass_wsa2macro>;
3540 clock-names = "iface" 3386 clock-names = "iface";
3541 interrupts = <GIC_SPI 3387 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
3542 label = "WSA2"; 3388 label = "WSA2";
3543 3389
3544 pinctrl-0 = <&wsa2_sw 3390 pinctrl-0 = <&wsa2_swr_active>;
3545 pinctrl-names = "defa 3391 pinctrl-names = "default";
3546 resets = <&lpass_audi <<
3547 reset-names = "swr_au <<
3548 3392
3549 qcom,din-ports = <4>; 3393 qcom,din-ports = <4>;
3550 qcom,dout-ports = <9> 3394 qcom,dout-ports = <9>;
3551 3395
3552 qcom,ports-sinterval 3396 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0x0f 0x0f 0xff 0x31f>;
3553 qcom,ports-offset1 = 3397 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
3554 qcom,ports-offset2 = 3398 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3555 qcom,ports-hstart = 3399 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
3556 qcom,ports-hstop = 3400 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
3557 qcom,ports-word-lengt 3401 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>;
3558 qcom,ports-block-pack 3402 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>;
3559 qcom,ports-block-grou 3403 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3560 qcom,ports-lane-contr 3404 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3561 3405
3562 #address-cells = <2>; 3406 #address-cells = <2>;
3563 #size-cells = <0>; 3407 #size-cells = <0>;
3564 #sound-dai-cells = <1 3408 #sound-dai-cells = <1>;
3565 status = "disabled"; 3409 status = "disabled";
3566 }; 3410 };
3567 3411
3568 lpass_rxmacro: codec@6ac0000 3412 lpass_rxmacro: codec@6ac0000 {
3569 compatible = "qcom,x1 3413 compatible = "qcom,x1e80100-lpass-rx-macro", "qcom,sm8550-lpass-rx-macro";
3570 reg = <0 0x06ac0000 0 3414 reg = <0 0x06ac0000 0 0x1000>;
3571 clocks = <&q6prmcc LP 3415 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3572 <&q6prmcc LP 3416 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3573 <&q6prmcc LP 3417 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3574 <&lpass_vama 3418 <&lpass_vamacro>;
3575 clock-names = "mclk", 3419 clock-names = "mclk",
3576 "macro" 3420 "macro",
3577 "dcodec 3421 "dcodec",
3578 "fsgen" 3422 "fsgen";
3579 3423
3580 #clock-cells = <0>; 3424 #clock-cells = <0>;
3581 clock-output-names = 3425 clock-output-names = "mclk";
3582 #sound-dai-cells = <1 3426 #sound-dai-cells = <1>;
3583 }; 3427 };
3584 3428
3585 swr1: soundwire@6ad0000 { 3429 swr1: soundwire@6ad0000 {
3586 compatible = "qcom,so 3430 compatible = "qcom,soundwire-v2.0.0";
3587 reg = <0 0x06ad0000 0 3431 reg = <0 0x06ad0000 0 0x10000>;
3588 clocks = <&lpass_rxma 3432 clocks = <&lpass_rxmacro>;
3589 clock-names = "iface" 3433 clock-names = "iface";
3590 interrupts = <GIC_SPI 3434 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
3591 label = "RX"; 3435 label = "RX";
3592 3436
3593 pinctrl-0 = <&rx_swr_ 3437 pinctrl-0 = <&rx_swr_active>;
3594 pinctrl-names = "defa 3438 pinctrl-names = "default";
3595 3439
3596 resets = <&lpass_audi <<
3597 reset-names = "swr_au <<
3598 qcom,din-ports = <1>; 3440 qcom,din-ports = <1>;
3599 qcom,dout-ports = <11 3441 qcom,dout-ports = <11>;
3600 3442
3601 qcom,ports-sinterval 3443 qcom,ports-sinterval = /bits/ 16 <0x03 0x1f 0x1f 0x07 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3602 qcom,ports-offset1 = 3444 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3603 qcom,ports-offset2 = 3445 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3604 qcom,ports-hstart = 3446 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3605 qcom,ports-hstop = 3447 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3606 qcom,ports-word-lengt 3448 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3607 qcom,ports-block-pack 3449 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3608 qcom,ports-block-grou 3450 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3609 qcom,ports-lane-contr 3451 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3610 3452
3611 #address-cells = <2>; 3453 #address-cells = <2>;
3612 #size-cells = <0>; 3454 #size-cells = <0>;
3613 #sound-dai-cells = <1 3455 #sound-dai-cells = <1>;
3614 status = "disabled"; 3456 status = "disabled";
3615 }; 3457 };
3616 3458
3617 lpass_txmacro: codec@6ae0000 3459 lpass_txmacro: codec@6ae0000 {
3618 compatible = "qcom,x1 3460 compatible = "qcom,x1e80100-lpass-tx-macro", "qcom,sm8550-lpass-tx-macro";
3619 reg = <0 0x06ae0000 0 3461 reg = <0 0x06ae0000 0 0x1000>;
3620 clocks = <&q6prmcc LP 3462 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3621 <&q6prmcc LP 3463 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3622 <&q6prmcc LP 3464 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3623 <&lpass_vama 3465 <&lpass_vamacro>;
3624 clock-names = "mclk", 3466 clock-names = "mclk",
3625 "macro" 3467 "macro",
3626 "dcodec 3468 "dcodec",
3627 "fsgen" 3469 "fsgen";
3628 3470
3629 #clock-cells = <0>; 3471 #clock-cells = <0>;
3630 clock-output-names = 3472 clock-output-names = "mclk";
3631 #sound-dai-cells = <1 3473 #sound-dai-cells = <1>;
3632 }; 3474 };
3633 3475
3634 lpass_wsamacro: codec@6b00000 3476 lpass_wsamacro: codec@6b00000 {
3635 compatible = "qcom,x1 3477 compatible = "qcom,x1e80100-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro";
3636 reg = <0 0x06b00000 0 3478 reg = <0 0x06b00000 0 0x1000>;
3637 clocks = <&q6prmcc LP 3479 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3638 <&q6prmcc LP 3480 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3639 <&q6prmcc LP 3481 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3640 <&lpass_vama 3482 <&lpass_vamacro>;
3641 clock-names = "mclk", 3483 clock-names = "mclk",
3642 "macro" 3484 "macro",
3643 "dcodec 3485 "dcodec",
3644 "fsgen" 3486 "fsgen";
3645 3487
3646 #clock-cells = <0>; 3488 #clock-cells = <0>;
3647 clock-output-names = 3489 clock-output-names = "mclk";
3648 #sound-dai-cells = <1 3490 #sound-dai-cells = <1>;
3649 sound-name-prefix = " 3491 sound-name-prefix = "WSA";
3650 }; 3492 };
3651 3493
3652 swr0: soundwire@6b10000 { 3494 swr0: soundwire@6b10000 {
3653 compatible = "qcom,so 3495 compatible = "qcom,soundwire-v2.0.0";
3654 reg = <0 0x06b10000 0 3496 reg = <0 0x06b10000 0 0x10000>;
3655 clocks = <&lpass_wsam 3497 clocks = <&lpass_wsamacro>;
3656 clock-names = "iface" 3498 clock-names = "iface";
3657 interrupts = <GIC_SPI 3499 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
3658 label = "WSA"; 3500 label = "WSA";
3659 3501
3660 pinctrl-0 = <&wsa_swr 3502 pinctrl-0 = <&wsa_swr_active>;
3661 pinctrl-names = "defa 3503 pinctrl-names = "default";
3662 resets = <&lpass_audi <<
3663 reset-names = "swr_au <<
3664 3504
3665 qcom,din-ports = <4>; 3505 qcom,din-ports = <4>;
3666 qcom,dout-ports = <9> 3506 qcom,dout-ports = <9>;
3667 3507
3668 qcom,ports-sinterval 3508 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0x0f 0x0f 0xff 0x31f>;
3669 qcom,ports-offset1 = 3509 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
3670 qcom,ports-offset2 = 3510 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3671 qcom,ports-hstart = 3511 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
3672 qcom,ports-hstop = 3512 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
3673 qcom,ports-word-lengt 3513 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>;
3674 qcom,ports-block-pack 3514 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>;
3675 qcom,ports-block-grou 3515 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3676 qcom,ports-lane-contr 3516 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3677 3517
3678 #address-cells = <2>; 3518 #address-cells = <2>;
3679 #size-cells = <0>; 3519 #size-cells = <0>;
3680 #sound-dai-cells = <1 3520 #sound-dai-cells = <1>;
3681 status = "disabled"; 3521 status = "disabled";
3682 }; 3522 };
3683 3523
3684 lpass_audiocc: clock-controll <<
3685 compatible = "qcom,x1 <<
3686 reg = <0 0x06b6c000 0 <<
3687 #clock-cells = <1>; <<
3688 #reset-cells = <1>; <<
3689 }; <<
3690 <<
3691 swr2: soundwire@6d30000 { 3524 swr2: soundwire@6d30000 {
3692 compatible = "qcom,so 3525 compatible = "qcom,soundwire-v2.0.0";
3693 reg = <0 0x06d30000 0 3526 reg = <0 0x06d30000 0 0x10000>;
3694 clocks = <&lpass_txma 3527 clocks = <&lpass_txmacro>;
3695 clock-names = "iface" 3528 clock-names = "iface";
3696 interrupts = <GIC_SPI 3529 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
3697 <GIC_SPI 3530 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>;
3698 interrupt-names = "co 3531 interrupt-names = "core", "wakeup";
3699 label = "TX"; 3532 label = "TX";
3700 resets = <&lpasscc LP <<
3701 reset-names = "swr_au <<
3702 3533
3703 pinctrl-0 = <&tx_swr_ 3534 pinctrl-0 = <&tx_swr_active>;
3704 pinctrl-names = "defa 3535 pinctrl-names = "default";
3705 3536
3706 qcom,din-ports = <4>; 3537 qcom,din-ports = <4>;
3707 qcom,dout-ports = <1> 3538 qcom,dout-ports = <1>;
3708 3539
3709 qcom,ports-sinterval- 3540 qcom,ports-sinterval-low = /bits/ 8 <0x00 0x01 0x03 0x03 0x00>;
3710 qcom,ports-offset1 = 3541 qcom,ports-offset1 = /bits/ 8 <0x00 0x01 0x02 0x00 0x00>;
3711 qcom,ports-offset2 = 3542 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00 0xff>;
3712 qcom,ports-hstart = 3543 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
3713 qcom,ports-hstop = 3544 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
3714 qcom,ports-word-lengt 3545 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
3715 qcom,ports-block-pack 3546 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
3716 qcom,ports-block-grou 3547 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
3717 qcom,ports-lane-contr 3548 qcom,ports-lane-control = /bits/ 8 <0xff 0x00 0x00 0x01 0xff>;
3718 3549
3719 #address-cells = <2>; 3550 #address-cells = <2>;
3720 #size-cells = <0>; 3551 #size-cells = <0>;
3721 #sound-dai-cells = <1 3552 #sound-dai-cells = <1>;
3722 status = "disabled"; 3553 status = "disabled";
3723 }; 3554 };
3724 3555
3725 lpass_vamacro: codec@6d44000 3556 lpass_vamacro: codec@6d44000 {
3726 compatible = "qcom,x1 3557 compatible = "qcom,x1e80100-lpass-va-macro", "qcom,sm8550-lpass-va-macro";
3727 reg = <0 0x06d44000 0 3558 reg = <0 0x06d44000 0 0x1000>;
3728 clocks = <&q6prmcc LP 3559 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3729 <&q6prmcc LP 3560 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3730 <&q6prmcc LP 3561 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
3731 clock-names = "mclk", 3562 clock-names = "mclk",
3732 "macro" 3563 "macro",
3733 "dcodec 3564 "dcodec";
3734 3565
3735 #clock-cells = <0>; 3566 #clock-cells = <0>;
3736 clock-output-names = 3567 clock-output-names = "fsgen";
3737 #sound-dai-cells = <1 3568 #sound-dai-cells = <1>;
3738 }; 3569 };
3739 3570
3740 lpass_tlmm: pinctrl@6e80000 { 3571 lpass_tlmm: pinctrl@6e80000 {
3741 compatible = "qcom,x1 3572 compatible = "qcom,x1e80100-lpass-lpi-pinctrl", "qcom,sm8550-lpass-lpi-pinctrl";
3742 reg = <0 0x06e80000 0 3573 reg = <0 0x06e80000 0 0x20000>,
3743 <0 0x07250000 0 3574 <0 0x07250000 0 0x10000>;
3744 3575
3745 clocks = <&q6prmcc LP 3576 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3746 <&q6prmcc LP 3577 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
3747 clock-names = "core", 3578 clock-names = "core", "audio";
3748 3579
3749 gpio-controller; 3580 gpio-controller;
3750 #gpio-cells = <2>; 3581 #gpio-cells = <2>;
3751 gpio-ranges = <&lpass 3582 gpio-ranges = <&lpass_tlmm 0 0 23>;
3752 3583
3753 tx_swr_active: tx-swr 3584 tx_swr_active: tx-swr-active-state {
3754 clk-pins { 3585 clk-pins {
3755 pins 3586 pins = "gpio0";
3756 funct 3587 function = "swr_tx_clk";
3757 drive 3588 drive-strength = <2>;
3758 slew- 3589 slew-rate = <1>;
3759 bias- 3590 bias-disable;
3760 }; 3591 };
3761 3592
3762 data-pins { 3593 data-pins {
3763 pins 3594 pins = "gpio1", "gpio2";
3764 funct 3595 function = "swr_tx_data";
3765 drive 3596 drive-strength = <2>;
3766 slew- 3597 slew-rate = <1>;
3767 bias- 3598 bias-bus-hold;
3768 }; 3599 };
3769 }; 3600 };
3770 3601
3771 rx_swr_active: rx-swr 3602 rx_swr_active: rx-swr-active-state {
3772 clk-pins { 3603 clk-pins {
3773 pins 3604 pins = "gpio3";
3774 funct 3605 function = "swr_rx_clk";
3775 drive 3606 drive-strength = <2>;
3776 slew- 3607 slew-rate = <1>;
3777 bias- 3608 bias-disable;
3778 }; 3609 };
3779 3610
3780 data-pins { 3611 data-pins {
3781 pins 3612 pins = "gpio4", "gpio5";
3782 funct 3613 function = "swr_rx_data";
3783 drive 3614 drive-strength = <2>;
3784 slew- 3615 slew-rate = <1>;
3785 bias- 3616 bias-bus-hold;
3786 }; 3617 };
3787 }; 3618 };
3788 3619
3789 dmic01_default: dmic0 3620 dmic01_default: dmic01-default-state {
3790 clk-pins { 3621 clk-pins {
3791 pins 3622 pins = "gpio6";
3792 funct 3623 function = "dmic1_clk";
3793 drive 3624 drive-strength = <8>;
3794 outpu 3625 output-high;
3795 }; 3626 };
3796 3627
3797 data-pins { 3628 data-pins {
3798 pins 3629 pins = "gpio7";
3799 funct 3630 function = "dmic1_data";
3800 drive 3631 drive-strength = <8>;
3801 input 3632 input-enable;
3802 }; 3633 };
3803 }; 3634 };
3804 3635
3805 dmic23_default: dmic2 3636 dmic23_default: dmic23-default-state {
3806 clk-pins { 3637 clk-pins {
3807 pins 3638 pins = "gpio8";
3808 funct 3639 function = "dmic2_clk";
3809 drive 3640 drive-strength = <8>;
3810 outpu 3641 output-high;
3811 }; 3642 };
3812 3643
3813 data-pins { 3644 data-pins {
3814 pins 3645 pins = "gpio9";
3815 funct 3646 function = "dmic2_data";
3816 drive 3647 drive-strength = <8>;
3817 input 3648 input-enable;
3818 }; 3649 };
3819 }; 3650 };
3820 3651
3821 wsa_swr_active: wsa-s 3652 wsa_swr_active: wsa-swr-active-state {
3822 clk-pins { 3653 clk-pins {
3823 pins 3654 pins = "gpio10";
3824 funct 3655 function = "wsa_swr_clk";
3825 drive 3656 drive-strength = <2>;
3826 slew- 3657 slew-rate = <1>;
3827 bias- 3658 bias-disable;
3828 }; 3659 };
3829 3660
3830 data-pins { 3661 data-pins {
3831 pins 3662 pins = "gpio11";
3832 funct 3663 function = "wsa_swr_data";
3833 drive 3664 drive-strength = <2>;
3834 slew- 3665 slew-rate = <1>;
3835 bias- 3666 bias-bus-hold;
3836 }; 3667 };
3837 }; 3668 };
3838 3669
3839 wsa2_swr_active: wsa2 3670 wsa2_swr_active: wsa2-swr-active-state {
3840 clk-pins { 3671 clk-pins {
3841 pins 3672 pins = "gpio15";
3842 funct 3673 function = "wsa2_swr_clk";
3843 drive 3674 drive-strength = <2>;
3844 slew- 3675 slew-rate = <1>;
3845 bias- 3676 bias-disable;
3846 }; 3677 };
3847 3678
3848 data-pins { 3679 data-pins {
3849 pins 3680 pins = "gpio16";
3850 funct 3681 function = "wsa2_swr_data";
3851 drive 3682 drive-strength = <2>;
3852 slew- 3683 slew-rate = <1>;
3853 bias- 3684 bias-bus-hold;
3854 }; 3685 };
3855 }; 3686 };
3856 }; 3687 };
3857 3688
3858 lpasscc: clock-controller@6ea <<
3859 compatible = "qcom,x1 <<
3860 reg = <0 0x06ea0000 0 <<
3861 #clock-cells = <1>; <<
3862 #reset-cells = <1>; <<
3863 }; <<
3864 <<
3865 lpass_ag_noc: interconnect@7e 3689 lpass_ag_noc: interconnect@7e40000 {
3866 compatible = "qcom,x1 3690 compatible = "qcom,x1e80100-lpass-ag-noc";
3867 reg = <0 0x07e40000 0 !! 3691 reg = <0 0x7e40000 0 0xE080>;
3868 3692
3869 qcom,bcm-voters = <&a 3693 qcom,bcm-voters = <&apps_bcm_voter>;
3870 3694
3871 #interconnect-cells = 3695 #interconnect-cells = <2>;
3872 }; 3696 };
3873 3697
3874 lpass_lpiaon_noc: interconnec 3698 lpass_lpiaon_noc: interconnect@7400000 {
3875 compatible = "qcom,x1 3699 compatible = "qcom,x1e80100-lpass-lpiaon-noc";
3876 reg = <0 0x07400000 0 !! 3700 reg = <0 0x7400000 0 0x19080>;
3877 3701
3878 qcom,bcm-voters = <&a 3702 qcom,bcm-voters = <&apps_bcm_voter>;
3879 3703
3880 #interconnect-cells = 3704 #interconnect-cells = <2>;
3881 }; 3705 };
3882 3706
3883 lpass_lpicx_noc: interconnect 3707 lpass_lpicx_noc: interconnect@7430000 {
3884 compatible = "qcom,x1 3708 compatible = "qcom,x1e80100-lpass-lpicx-noc";
3885 reg = <0 0x07430000 0 !! 3709 reg = <0 0x7430000 0 0x3A200>;
3886 3710
3887 qcom,bcm-voters = <&a 3711 qcom,bcm-voters = <&apps_bcm_voter>;
3888 3712
3889 #interconnect-cells = 3713 #interconnect-cells = <2>;
3890 }; 3714 };
3891 3715
3892 usb_2_hsphy: phy@88e0000 { 3716 usb_2_hsphy: phy@88e0000 {
3893 compatible = "qcom,x1 3717 compatible = "qcom,x1e80100-snps-eusb2-phy",
3894 "qcom,sm 3718 "qcom,sm8550-snps-eusb2-phy";
3895 reg = <0 0x088e0000 0 3719 reg = <0 0x088e0000 0 0x154>;
3896 #phy-cells = <0>; 3720 #phy-cells = <0>;
3897 3721
3898 clocks = <&tcsr TCSR_ 3722 clocks = <&tcsr TCSR_USB2_2_CLKREF_EN>;
3899 clock-names = "ref"; 3723 clock-names = "ref";
3900 3724
3901 resets = <&gcc GCC_QU 3725 resets = <&gcc GCC_QUSB2PHY_USB20_HS_BCR>;
3902 3726
3903 status = "disabled"; 3727 status = "disabled";
3904 }; 3728 };
3905 3729
3906 usb_mp_hsphy0: phy@88e1000 { <<
3907 compatible = "qcom,x1 <<
3908 "qcom,sm <<
3909 reg = <0 0x088e1000 0 <<
3910 #phy-cells = <0>; <<
3911 <<
3912 clocks = <&tcsr TCSR_ <<
3913 clock-names = "ref"; <<
3914 <<
3915 resets = <&gcc GCC_QU <<
3916 <<
3917 status = "disabled"; <<
3918 }; <<
3919 <<
3920 usb_mp_hsphy1: phy@88e2000 { <<
3921 compatible = "qcom,x1 <<
3922 "qcom,sm <<
3923 reg = <0 0x088e2000 0 <<
3924 #phy-cells = <0>; <<
3925 <<
3926 clocks = <&tcsr TCSR_ <<
3927 clock-names = "ref"; <<
3928 <<
3929 resets = <&gcc GCC_QU <<
3930 <<
3931 status = "disabled"; <<
3932 }; <<
3933 <<
3934 usb_mp_qmpphy0: phy@88e3000 { <<
3935 compatible = "qcom,x1 <<
3936 reg = <0 0x088e3000 0 <<
3937 <<
3938 clocks = <&gcc GCC_US <<
3939 <&rpmhcc RPM <<
3940 <&gcc GCC_US <<
3941 <&gcc GCC_US <<
3942 clock-names = "aux", <<
3943 "ref", <<
3944 "com_au <<
3945 "pipe"; <<
3946 <<
3947 resets = <&gcc GCC_US <<
3948 <&gcc GCC_US <<
3949 reset-names = "phy", <<
3950 "phy_ph <<
3951 <<
3952 power-domains = <&gcc <<
3953 <<
3954 #clock-cells = <0>; <<
3955 clock-output-names = <<
3956 <<
3957 #phy-cells = <0>; <<
3958 <<
3959 status = "disabled"; <<
3960 }; <<
3961 <<
3962 usb_mp_qmpphy1: phy@88e5000 { <<
3963 compatible = "qcom,x1 <<
3964 reg = <0 0x088e5000 0 <<
3965 <<
3966 clocks = <&gcc GCC_US <<
3967 <&rpmhcc RPM <<
3968 <&gcc GCC_US <<
3969 <&gcc GCC_US <<
3970 clock-names = "aux", <<
3971 "ref", <<
3972 "com_au <<
3973 "pipe"; <<
3974 <<
3975 resets = <&gcc GCC_US <<
3976 <&gcc GCC_US <<
3977 reset-names = "phy", <<
3978 "phy_ph <<
3979 <<
3980 power-domains = <&gcc <<
3981 <<
3982 #clock-cells = <0>; <<
3983 clock-output-names = <<
3984 <<
3985 #phy-cells = <0>; <<
3986 <<
3987 status = "disabled"; <<
3988 }; <<
3989 <<
3990 usb_1_ss2: usb@a0f8800 { 3730 usb_1_ss2: usb@a0f8800 {
3991 compatible = "qcom,x1 3731 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3";
3992 reg = <0 0x0a0f8800 0 3732 reg = <0 0x0a0f8800 0 0x400>;
3993 3733
3994 clocks = <&gcc GCC_CF 3734 clocks = <&gcc GCC_CFG_NOC_USB3_TERT_AXI_CLK>,
3995 <&gcc GCC_US 3735 <&gcc GCC_USB30_TERT_MASTER_CLK>,
3996 <&gcc GCC_AG 3736 <&gcc GCC_AGGRE_USB3_TERT_AXI_CLK>,
3997 <&gcc GCC_US 3737 <&gcc GCC_USB30_TERT_SLEEP_CLK>,
3998 <&gcc GCC_US 3738 <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>,
3999 <&gcc GCC_AG 3739 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
4000 <&gcc GCC_AG 3740 <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>,
4001 <&gcc GCC_AG 3741 <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>,
4002 <&gcc GCC_SY 3742 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
4003 clock-names = "cfg_no 3743 clock-names = "cfg_noc",
4004 "core", 3744 "core",
4005 "iface" 3745 "iface",
4006 "sleep" 3746 "sleep",
4007 "mock_u 3747 "mock_utmi",
4008 "noc_ag 3748 "noc_aggr",
4009 "noc_ag 3749 "noc_aggr_north",
4010 "noc_ag 3750 "noc_aggr_south",
4011 "noc_sy 3751 "noc_sys";
4012 3752
4013 assigned-clocks = <&g 3753 assigned-clocks = <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>,
4014 <&g 3754 <&gcc GCC_USB30_TERT_MASTER_CLK>;
4015 assigned-clock-rates 3755 assigned-clock-rates = <19200000>,
4016 3756 <200000000>;
4017 3757
4018 interrupts-extended = 3758 interrupts-extended = <&intc GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
4019 3759 <&pdc 58 IRQ_TYPE_EDGE_BOTH>,
4020 3760 <&pdc 57 IRQ_TYPE_EDGE_BOTH>,
4021 3761 <&pdc 10 IRQ_TYPE_LEVEL_HIGH>;
4022 interrupt-names = "pw 3762 interrupt-names = "pwr_event",
4023 "dp 3763 "dp_hs_phy_irq",
4024 "dm 3764 "dm_hs_phy_irq",
4025 "ss 3765 "ss_phy_irq";
4026 3766
4027 power-domains = <&gcc 3767 power-domains = <&gcc GCC_USB30_TERT_GDSC>;
4028 required-opps = <&rpm 3768 required-opps = <&rpmhpd_opp_nom>;
4029 3769
4030 resets = <&gcc GCC_US 3770 resets = <&gcc GCC_USB30_TERT_BCR>;
4031 3771
4032 interconnects = <&usb 3772 interconnects = <&usb_south_anoc MASTER_USB3_2 QCOM_ICC_TAG_ALWAYS
4033 &mc_ 3773 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
4034 <&gem 3774 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
4035 &con 3775 &config_noc SLAVE_USB3_2 QCOM_ICC_TAG_ALWAYS>;
4036 interconnect-names = 3776 interconnect-names = "usb-ddr",
4037 3777 "apps-usb";
4038 3778
4039 wakeup-source; 3779 wakeup-source;
4040 3780
4041 #address-cells = <2>; 3781 #address-cells = <2>;
4042 #size-cells = <2>; 3782 #size-cells = <2>;
4043 ranges; 3783 ranges;
4044 3784
4045 status = "disabled"; 3785 status = "disabled";
4046 3786
4047 usb_1_ss2_dwc3: usb@a 3787 usb_1_ss2_dwc3: usb@a000000 {
4048 compatible = 3788 compatible = "snps,dwc3";
4049 reg = <0 0x0a 3789 reg = <0 0x0a000000 0 0xcd00>;
4050 3790
4051 interrupts = 3791 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
4052 3792
4053 iommus = <&ap 3793 iommus = <&apps_smmu 0x14a0 0x0>;
4054 3794
4055 phys = <&usb_ 3795 phys = <&usb_1_ss2_hsphy>,
4056 <&usb_ 3796 <&usb_1_ss2_qmpphy QMP_USB43DP_USB3_PHY>;
4057 phy-names = " 3797 phy-names = "usb2-phy",
4058 " 3798 "usb3-phy";
4059 3799
4060 snps,dis_u2_s 3800 snps,dis_u2_susphy_quirk;
4061 snps,dis_enbl 3801 snps,dis_enblslpm_quirk;
4062 snps,usb3_lpm 3802 snps,usb3_lpm_capable;
4063 3803
4064 dma-coherent; 3804 dma-coherent;
4065 3805
4066 ports { 3806 ports {
4067 #addr 3807 #address-cells = <1>;
4068 #size 3808 #size-cells = <0>;
4069 3809
4070 port@ 3810 port@0 {
4071 3811 reg = <0>;
4072 3812
4073 3813 usb_1_ss2_dwc3_hs: endpoint {
4074 3814 };
4075 }; 3815 };
4076 3816
4077 port@ 3817 port@1 {
4078 3818 reg = <1>;
4079 3819
4080 3820 usb_1_ss2_dwc3_ss: endpoint {
4081 3821 remote-endpoint = <&usb_1_ss2_qmpphy_usb_ss_in>;
4082 3822 };
4083 }; 3823 };
4084 }; 3824 };
4085 }; 3825 };
4086 }; 3826 };
4087 3827
4088 usb_2: usb@a2f8800 { 3828 usb_2: usb@a2f8800 {
4089 compatible = "qcom,x1 3829 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3";
4090 reg = <0 0x0a2f8800 0 3830 reg = <0 0x0a2f8800 0 0x400>;
4091 #address-cells = <2>; 3831 #address-cells = <2>;
4092 #size-cells = <2>; 3832 #size-cells = <2>;
4093 ranges; 3833 ranges;
4094 3834
4095 clocks = <&gcc GCC_CF 3835 clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>,
4096 <&gcc GCC_US 3836 <&gcc GCC_USB20_MASTER_CLK>,
4097 <&gcc GCC_AG 3837 <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>,
4098 <&gcc GCC_US 3838 <&gcc GCC_USB20_SLEEP_CLK>,
4099 <&gcc GCC_US 3839 <&gcc GCC_USB20_MOCK_UTMI_CLK>,
4100 <&gcc GCC_AG 3840 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
4101 <&gcc GCC_AG 3841 <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>,
4102 <&gcc GCC_AG 3842 <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>,
4103 <&gcc GCC_SY 3843 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
4104 clock-names = "cfg_no 3844 clock-names = "cfg_noc",
4105 "core", 3845 "core",
4106 "iface" 3846 "iface",
4107 "sleep" 3847 "sleep",
4108 "mock_u 3848 "mock_utmi",
4109 "noc_ag 3849 "noc_aggr",
4110 "noc_ag 3850 "noc_aggr_north",
4111 "noc_ag 3851 "noc_aggr_south",
4112 "noc_sy 3852 "noc_sys";
4113 3853
4114 assigned-clocks = <&g 3854 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
4115 <&g 3855 <&gcc GCC_USB20_MASTER_CLK>;
4116 assigned-clock-rates 3856 assigned-clock-rates = <19200000>, <200000000>;
4117 3857
4118 interrupts-extended = 3858 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4119 3859 <&pdc 50 IRQ_TYPE_EDGE_BOTH>,
4120 3860 <&pdc 49 IRQ_TYPE_EDGE_BOTH>;
4121 interrupt-names = "pw 3861 interrupt-names = "pwr_event",
4122 "dp 3862 "dp_hs_phy_irq",
4123 "dm 3863 "dm_hs_phy_irq";
4124 3864
4125 power-domains = <&gcc 3865 power-domains = <&gcc GCC_USB20_PRIM_GDSC>;
4126 required-opps = <&rpm 3866 required-opps = <&rpmhpd_opp_nom>;
4127 3867
4128 resets = <&gcc GCC_US 3868 resets = <&gcc GCC_USB20_PRIM_BCR>;
4129 3869
4130 interconnects = <&usb 3870 interconnects = <&usb_north_anoc MASTER_USB2 QCOM_ICC_TAG_ALWAYS
4131 &mc_ 3871 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
4132 <&gem 3872 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
4133 &con 3873 &config_noc SLAVE_USB2 QCOM_ICC_TAG_ALWAYS>;
4134 interconnect-names = 3874 interconnect-names = "usb-ddr",
4135 3875 "apps-usb";
4136 3876
4137 wakeup-source; 3877 wakeup-source;
4138 3878
4139 status = "disabled"; 3879 status = "disabled";
4140 3880
4141 usb_2_dwc3: usb@a2000 3881 usb_2_dwc3: usb@a200000 {
4142 compatible = 3882 compatible = "snps,dwc3";
4143 reg = <0 0x0a 3883 reg = <0 0x0a200000 0 0xcd00>;
4144 interrupts = 3884 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
4145 iommus = <&ap 3885 iommus = <&apps_smmu 0x14e0 0x0>;
4146 phys = <&usb_ 3886 phys = <&usb_2_hsphy>;
4147 phy-names = " 3887 phy-names = "usb2-phy";
4148 maximum-speed 3888 maximum-speed = "high-speed";
4149 3889
4150 ports { 3890 ports {
4151 #addr 3891 #address-cells = <1>;
4152 #size 3892 #size-cells = <0>;
4153 3893
4154 port@ 3894 port@0 {
4155 3895 reg = <0>;
4156 3896
4157 3897 usb_2_dwc3_hs: endpoint {
4158 3898 };
4159 }; 3899 };
4160 }; 3900 };
4161 }; 3901 };
4162 }; 3902 };
4163 3903
4164 usb_mp: usb@a4f8800 { <<
4165 compatible = "qcom,x1 <<
4166 reg = <0 0x0a4f8800 0 <<
4167 <<
4168 clocks = <&gcc GCC_CF <<
4169 <&gcc GCC_US <<
4170 <&gcc GCC_AG <<
4171 <&gcc GCC_US <<
4172 <&gcc GCC_US <<
4173 <&gcc GCC_AG <<
4174 <&gcc GCC_AG <<
4175 <&gcc GCC_AG <<
4176 <&gcc GCC_SY <<
4177 clock-names = "cfg_no <<
4178 "core", <<
4179 "iface" <<
4180 "sleep" <<
4181 "mock_u <<
4182 "noc_ag <<
4183 "noc_ag <<
4184 "noc_ag <<
4185 "noc_sy <<
4186 <<
4187 assigned-clocks = <&g <<
4188 <&g <<
4189 assigned-clock-rates <<
4190 <<
4191 <<
4192 interrupts-extended = <<
4193 <<
4194 <<
4195 <<
4196 <<
4197 <<
4198 <<
4199 <<
4200 <<
4201 <<
4202 interrupt-names = "pw <<
4203 "hs <<
4204 "dp <<
4205 "dp <<
4206 "ss <<
4207 <<
4208 power-domains = <&gcc <<
4209 required-opps = <&rpm <<
4210 <<
4211 resets = <&gcc GCC_US <<
4212 <<
4213 interconnects = <&usb <<
4214 &mc_ <<
4215 <&gem <<
4216 &con <<
4217 interconnect-names = <<
4218 <<
4219 <<
4220 wakeup-source; <<
4221 <<
4222 #address-cells = <2>; <<
4223 #size-cells = <2>; <<
4224 ranges; <<
4225 <<
4226 status = "disabled"; <<
4227 <<
4228 usb_mp_dwc3: usb@a400 <<
4229 compatible = <<
4230 reg = <0 0x0a <<
4231 <<
4232 interrupts = <<
4233 <<
4234 iommus = <&ap <<
4235 <<
4236 phys = <&usb_ <<
4237 <&usb_ <<
4238 phy-names = " <<
4239 " <<
4240 dr_mode = "ho <<
4241 <<
4242 snps,dis_u2_s <<
4243 snps,dis_enbl <<
4244 snps,usb3_lpm <<
4245 <<
4246 dma-coherent; <<
4247 }; <<
4248 }; <<
4249 <<
4250 usb_1_ss0: usb@a6f8800 { 3904 usb_1_ss0: usb@a6f8800 {
4251 compatible = "qcom,x1 3905 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3";
4252 reg = <0 0x0a6f8800 0 3906 reg = <0 0x0a6f8800 0 0x400>;
4253 3907
4254 clocks = <&gcc GCC_CF 3908 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
4255 <&gcc GCC_US 3909 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
4256 <&gcc GCC_AG 3910 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
4257 <&gcc GCC_US 3911 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
4258 <&gcc GCC_US 3912 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4259 <&gcc GCC_AG 3913 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
4260 <&gcc GCC_CF 3914 <&gcc GCC_CFG_NOC_USB_ANOC_NORTH_AHB_CLK>,
4261 <&gcc GCC_CF 3915 <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>,
4262 <&gcc GCC_SY 3916 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
4263 clock-names = "cfg_no 3917 clock-names = "cfg_noc",
4264 "core", 3918 "core",
4265 "iface" 3919 "iface",
4266 "sleep" 3920 "sleep",
4267 "mock_u 3921 "mock_utmi",
4268 "noc_ag 3922 "noc_aggr",
4269 "noc_ag 3923 "noc_aggr_north",
4270 "noc_ag 3924 "noc_aggr_south",
4271 "noc_sy 3925 "noc_sys";
4272 3926
4273 assigned-clocks = <&g 3927 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4274 <&g 3928 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
4275 assigned-clock-rates 3929 assigned-clock-rates = <19200000>,
4276 3930 <200000000>;
4277 3931
4278 interrupts-extended = 3932 interrupts-extended = <&intc GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>,
4279 3933 <&pdc 61 IRQ_TYPE_EDGE_BOTH>,
4280 3934 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
4281 3935 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
4282 interrupt-names = "pw 3936 interrupt-names = "pwr_event",
4283 "dp 3937 "dp_hs_phy_irq",
4284 "dm 3938 "dm_hs_phy_irq",
4285 "ss 3939 "ss_phy_irq";
4286 3940
4287 power-domains = <&gcc 3941 power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
4288 required-opps = <&rpm 3942 required-opps = <&rpmhpd_opp_nom>;
4289 3943
4290 resets = <&gcc GCC_US 3944 resets = <&gcc GCC_USB30_PRIM_BCR>;
4291 3945
4292 wakeup-source; 3946 wakeup-source;
4293 3947
4294 #address-cells = <2>; 3948 #address-cells = <2>;
4295 #size-cells = <2>; 3949 #size-cells = <2>;
4296 ranges; 3950 ranges;
4297 3951
4298 status = "disabled"; 3952 status = "disabled";
4299 3953
4300 usb_1_ss0_dwc3: usb@a 3954 usb_1_ss0_dwc3: usb@a600000 {
4301 compatible = 3955 compatible = "snps,dwc3";
4302 reg = <0 0x0a 3956 reg = <0 0x0a600000 0 0xcd00>;
4303 3957
4304 interrupts = 3958 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
4305 3959
4306 iommus = <&ap 3960 iommus = <&apps_smmu 0x1420 0x0>;
4307 3961
4308 phys = <&usb_ 3962 phys = <&usb_1_ss0_hsphy>,
4309 <&usb_ 3963 <&usb_1_ss0_qmpphy QMP_USB43DP_USB3_PHY>;
4310 phy-names = " 3964 phy-names = "usb2-phy",
4311 " 3965 "usb3-phy";
4312 3966
4313 snps,dis_u2_s 3967 snps,dis_u2_susphy_quirk;
4314 snps,dis_enbl 3968 snps,dis_enblslpm_quirk;
4315 snps,usb3_lpm 3969 snps,usb3_lpm_capable;
4316 3970
4317 dma-coherent; 3971 dma-coherent;
4318 3972
4319 ports { 3973 ports {
4320 #addr 3974 #address-cells = <1>;
4321 #size 3975 #size-cells = <0>;
4322 3976
4323 port@ 3977 port@0 {
4324 3978 reg = <0>;
4325 3979
4326 3980 usb_1_ss0_dwc3_hs: endpoint {
4327 3981 };
4328 }; 3982 };
4329 3983
4330 port@ 3984 port@1 {
4331 3985 reg = <1>;
4332 3986
4333 3987 usb_1_ss0_dwc3_ss: endpoint {
4334 3988 remote-endpoint = <&usb_1_ss0_qmpphy_usb_ss_in>;
4335 3989 };
4336 }; 3990 };
4337 }; 3991 };
4338 }; 3992 };
4339 }; 3993 };
4340 3994
4341 usb_1_ss1: usb@a8f8800 { 3995 usb_1_ss1: usb@a8f8800 {
4342 compatible = "qcom,x1 3996 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3";
4343 reg = <0 0x0a8f8800 0 3997 reg = <0 0x0a8f8800 0 0x400>;
4344 3998
4345 clocks = <&gcc GCC_CF 3999 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
4346 <&gcc GCC_US 4000 <&gcc GCC_USB30_SEC_MASTER_CLK>,
4347 <&gcc GCC_AG 4001 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
4348 <&gcc GCC_US 4002 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
4349 <&gcc GCC_US 4003 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4350 <&gcc GCC_AG 4004 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
4351 <&gcc GCC_AG 4005 <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>,
4352 <&gcc GCC_AG 4006 <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>,
4353 <&gcc GCC_SY 4007 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
4354 clock-names = "cfg_no 4008 clock-names = "cfg_noc",
4355 "core", 4009 "core",
4356 "iface" 4010 "iface",
4357 "sleep" 4011 "sleep",
4358 "mock_u 4012 "mock_utmi",
4359 "noc_ag 4013 "noc_aggr",
4360 "noc_ag 4014 "noc_aggr_north",
4361 "noc_ag 4015 "noc_aggr_south",
4362 "noc_sy 4016 "noc_sys";
4363 4017
4364 assigned-clocks = <&g 4018 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4365 <&g 4019 <&gcc GCC_USB30_SEC_MASTER_CLK>;
4366 assigned-clock-rates 4020 assigned-clock-rates = <19200000>,
4367 4021 <200000000>;
4368 4022
4369 interrupts-extended = 4023 interrupts-extended = <&intc GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>,
4370 4024 <&pdc 60 IRQ_TYPE_EDGE_BOTH>,
4371 4025 <&pdc 11 IRQ_TYPE_EDGE_BOTH>,
4372 4026 <&pdc 47 IRQ_TYPE_LEVEL_HIGH>;
4373 interrupt-names = "pw 4027 interrupt-names = "pwr_event",
4374 "dp 4028 "dp_hs_phy_irq",
4375 "dm 4029 "dm_hs_phy_irq",
4376 "ss 4030 "ss_phy_irq";
4377 4031
4378 power-domains = <&gcc 4032 power-domains = <&gcc GCC_USB30_SEC_GDSC>;
4379 required-opps = <&rpm 4033 required-opps = <&rpmhpd_opp_nom>;
4380 4034
4381 resets = <&gcc GCC_US 4035 resets = <&gcc GCC_USB30_SEC_BCR>;
4382 4036
4383 interconnects = <&usb 4037 interconnects = <&usb_south_anoc MASTER_USB3_1 QCOM_ICC_TAG_ALWAYS
4384 &mc_ 4038 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
4385 <&gem 4039 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
4386 &con 4040 &config_noc SLAVE_USB3_1 QCOM_ICC_TAG_ALWAYS>;
4387 interconnect-names = 4041 interconnect-names = "usb-ddr",
4388 4042 "apps-usb";
4389 4043
4390 wakeup-source; 4044 wakeup-source;
4391 4045
4392 #address-cells = <2>; 4046 #address-cells = <2>;
4393 #size-cells = <2>; 4047 #size-cells = <2>;
4394 ranges; 4048 ranges;
4395 4049
4396 status = "disabled"; 4050 status = "disabled";
4397 4051
4398 usb_1_ss1_dwc3: usb@a 4052 usb_1_ss1_dwc3: usb@a800000 {
4399 compatible = 4053 compatible = "snps,dwc3";
4400 reg = <0 0x0a 4054 reg = <0 0x0a800000 0 0xcd00>;
4401 4055
4402 interrupts = 4056 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
4403 4057
4404 iommus = <&ap 4058 iommus = <&apps_smmu 0x1460 0x0>;
4405 4059
4406 phys = <&usb_ 4060 phys = <&usb_1_ss1_hsphy>,
4407 <&usb_ 4061 <&usb_1_ss1_qmpphy QMP_USB43DP_USB3_PHY>;
4408 phy-names = " 4062 phy-names = "usb2-phy",
4409 " 4063 "usb3-phy";
4410 4064
4411 snps,dis_u2_s 4065 snps,dis_u2_susphy_quirk;
4412 snps,dis_enbl 4066 snps,dis_enblslpm_quirk;
4413 snps,usb3_lpm 4067 snps,usb3_lpm_capable;
4414 4068
4415 dma-coherent; 4069 dma-coherent;
4416 4070
4417 ports { 4071 ports {
4418 #addr 4072 #address-cells = <1>;
4419 #size 4073 #size-cells = <0>;
4420 4074
4421 port@ 4075 port@0 {
4422 4076 reg = <0>;
4423 4077
4424 4078 usb_1_ss1_dwc3_hs: endpoint {
4425 4079 };
4426 }; 4080 };
4427 4081
4428 port@ 4082 port@1 {
4429 4083 reg = <1>;
4430 4084
4431 4085 usb_1_ss1_dwc3_ss: endpoint {
4432 4086 remote-endpoint = <&usb_1_ss1_qmpphy_usb_ss_in>;
4433 4087 };
4434 }; 4088 };
4435 }; 4089 };
4436 }; 4090 };
4437 }; 4091 };
4438 4092
4439 mdss: display-subsystem@ae000 4093 mdss: display-subsystem@ae00000 {
4440 compatible = "qcom,x1 4094 compatible = "qcom,x1e80100-mdss";
4441 reg = <0 0x0ae00000 0 4095 reg = <0 0x0ae00000 0 0x1000>;
4442 reg-names = "mdss"; 4096 reg-names = "mdss";
4443 4097
4444 interrupts = <GIC_SPI 4098 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
4445 4099
4446 clocks = <&dispcc DIS 4100 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4447 <&gcc GCC_DI 4101 <&gcc GCC_DISP_HF_AXI_CLK>,
4448 <&dispcc DIS 4102 <&dispcc DISP_CC_MDSS_MDP_CLK>;
4449 4103
4450 resets = <&dispcc DIS 4104 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
4451 4105
4452 interconnects = <&mms 4106 interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS
4453 &gem 4107 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
4454 <&mc_ 4108 <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS
4455 &mc_ 4109 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
4456 <&gem 4110 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
4457 &con 4111 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
4458 interconnect-names = 4112 interconnect-names = "mdp0-mem",
4459 4113 "mdp1-mem",
4460 4114 "cpu-cfg";
4461 4115
4462 power-domains = <&dis 4116 power-domains = <&dispcc MDSS_GDSC>;
4463 4117
4464 iommus = <&apps_smmu 4118 iommus = <&apps_smmu 0x1c00 0x2>;
4465 4119
4466 interrupt-controller; 4120 interrupt-controller;
4467 #interrupt-cells = <1 4121 #interrupt-cells = <1>;
4468 4122
4469 #address-cells = <2>; 4123 #address-cells = <2>;
4470 #size-cells = <2>; 4124 #size-cells = <2>;
4471 ranges; 4125 ranges;
4472 4126
4473 status = "disabled"; 4127 status = "disabled";
4474 4128
4475 mdss_mdp: display-con 4129 mdss_mdp: display-controller@ae01000 {
4476 compatible = 4130 compatible = "qcom,x1e80100-dpu";
4477 reg = <0 0x0a 4131 reg = <0 0x0ae01000 0 0x8f000>,
4478 <0 0x0a 4132 <0 0x0aeb0000 0 0x2008>;
4479 reg-names = " 4133 reg-names = "mdp",
4480 " 4134 "vbif";
4481 4135
4482 interrupts-ex 4136 interrupts-extended = <&mdss 0>;
4483 4137
4484 clocks = <&gc 4138 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
4485 <&di 4139 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4486 <&di 4140 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
4487 <&di 4141 <&dispcc DISP_CC_MDSS_MDP_CLK>,
4488 <&di 4142 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4489 clock-names = 4143 clock-names = "nrt_bus",
4490 4144 "iface",
4491 4145 "lut",
4492 4146 "core",
4493 4147 "vsync";
4494 4148
4495 operating-poi 4149 operating-points-v2 = <&mdp_opp_table>;
4496 4150
4497 power-domains 4151 power-domains = <&rpmhpd RPMHPD_MMCX>;
4498 4152
4499 ports { 4153 ports {
4500 #addr 4154 #address-cells = <1>;
4501 #size 4155 #size-cells = <0>;
4502 4156
4503 port@ 4157 port@0 {
4504 4158 reg = <0>;
4505 4159
4506 4160 mdss_intf0_out: endpoint {
4507 4161 remote-endpoint = <&mdss_dp0_in>;
4508 4162 };
4509 }; 4163 };
4510 4164
4511 port@ 4165 port@4 {
4512 4166 reg = <4>;
4513 4167
4514 4168 mdss_intf4_out: endpoint {
4515 4169 remote-endpoint = <&mdss_dp1_in>;
4516 4170 };
4517 }; 4171 };
4518 4172
4519 port@ 4173 port@5 {
4520 4174 reg = <5>;
4521 4175
4522 4176 mdss_intf5_out: endpoint {
4523 4177 remote-endpoint = <&mdss_dp3_in>;
4524 4178 };
4525 }; 4179 };
4526 4180
4527 port@ 4181 port@6 {
4528 4182 reg = <6>;
4529 4183
4530 4184 mdss_intf6_out: endpoint {
4531 4185 remote-endpoint = <&mdss_dp2_in>;
4532 4186 };
4533 }; 4187 };
4534 }; 4188 };
4535 4189
4536 mdp_opp_table 4190 mdp_opp_table: opp-table {
4537 compa 4191 compatible = "operating-points-v2";
4538 4192
4539 opp-2 4193 opp-200000000 {
4540 4194 opp-hz = /bits/ 64 <200000000>;
4541 4195 required-opps = <&rpmhpd_opp_low_svs>;
4542 }; 4196 };
4543 4197
4544 opp-3 4198 opp-325000000 {
4545 4199 opp-hz = /bits/ 64 <325000000>;
4546 4200 required-opps = <&rpmhpd_opp_svs>;
4547 }; 4201 };
4548 4202
4549 opp-3 4203 opp-375000000 {
4550 4204 opp-hz = /bits/ 64 <375000000>;
4551 4205 required-opps = <&rpmhpd_opp_svs_l1>;
4552 }; 4206 };
4553 4207
4554 opp-5 4208 opp-514000000 {
4555 4209 opp-hz = /bits/ 64 <514000000>;
4556 4210 required-opps = <&rpmhpd_opp_nom>;
4557 }; 4211 };
4558 4212
4559 opp-5 4213 opp-575000000 {
4560 4214 opp-hz = /bits/ 64 <575000000>;
4561 4215 required-opps = <&rpmhpd_opp_nom_l1>;
4562 }; 4216 };
4563 }; 4217 };
4564 }; 4218 };
4565 4219
4566 mdss_dp0: displayport 4220 mdss_dp0: displayport-controller@ae90000 {
4567 compatible = 4221 compatible = "qcom,x1e80100-dp";
4568 reg = <0 0x0a !! 4222 reg = <0 0xae90000 0 0x200>,
4569 <0 0x0a !! 4223 <0 0xae90200 0 0x200>,
4570 <0 0x0a !! 4224 <0 0xae90400 0 0x600>,
4571 <0 0x0a !! 4225 <0 0xae91000 0 0x400>,
4572 <0 0x0a !! 4226 <0 0xae91400 0 0x400>;
4573 4227
4574 interrupts-ex 4228 interrupts-extended = <&mdss 12>;
4575 4229
4576 clocks = <&di 4230 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4577 <&di 4231 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
4578 <&di 4232 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
4579 <&di 4233 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
4580 <&di 4234 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
4581 clock-names = 4235 clock-names = "core_iface",
4582 4236 "core_aux",
4583 4237 "ctrl_link",
4584 4238 "ctrl_link_iface",
4585 4239 "stream_pixel";
4586 4240
4587 assigned-cloc 4241 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
4588 4242 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
4589 assigned-cloc 4243 assigned-clock-parents = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4590 4244 <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
4591 4245
4592 operating-poi 4246 operating-points-v2 = <&mdss_dp0_opp_table>;
4593 4247
4594 power-domains 4248 power-domains = <&rpmhpd RPMHPD_MMCX>;
4595 4249
4596 phys = <&usb_ 4250 phys = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_PHY>;
4597 phy-names = " 4251 phy-names = "dp";
4598 4252
4599 #sound-dai-ce 4253 #sound-dai-cells = <0>;
4600 4254
4601 status = "dis 4255 status = "disabled";
4602 4256
4603 ports { 4257 ports {
4604 #addr 4258 #address-cells = <1>;
4605 #size 4259 #size-cells = <0>;
4606 4260
4607 port@ 4261 port@0 {
4608 4262 reg = <0>;
4609 4263
4610 4264 mdss_dp0_in: endpoint {
4611 4265 remote-endpoint = <&mdss_intf0_out>;
4612 4266 };
4613 }; 4267 };
4614 4268
4615 port@ 4269 port@1 {
4616 4270 reg = <1>;
4617 4271
4618 4272 mdss_dp0_out: endpoint {
4619 4273 remote-endpoint = <&usb_1_ss0_qmpphy_dp_in>;
4620 4274 };
4621 }; 4275 };
4622 }; 4276 };
4623 4277
4624 mdss_dp0_opp_ 4278 mdss_dp0_opp_table: opp-table {
4625 compa 4279 compatible = "operating-points-v2";
4626 4280
4627 opp-1 4281 opp-160000000 {
4628 4282 opp-hz = /bits/ 64 <160000000>;
4629 4283 required-opps = <&rpmhpd_opp_low_svs>;
4630 }; 4284 };
4631 4285
4632 opp-2 4286 opp-270000000 {
4633 4287 opp-hz = /bits/ 64 <270000000>;
4634 4288 required-opps = <&rpmhpd_opp_svs>;
4635 }; 4289 };
4636 4290
4637 opp-5 4291 opp-540000000 {
4638 4292 opp-hz = /bits/ 64 <540000000>;
4639 4293 required-opps = <&rpmhpd_opp_svs_l1>;
4640 }; 4294 };
4641 4295
4642 opp-8 4296 opp-810000000 {
4643 4297 opp-hz = /bits/ 64 <810000000>;
4644 4298 required-opps = <&rpmhpd_opp_nom>;
4645 }; 4299 };
4646 }; 4300 };
4647 }; 4301 };
4648 4302
4649 mdss_dp1: displayport 4303 mdss_dp1: displayport-controller@ae98000 {
4650 compatible = 4304 compatible = "qcom,x1e80100-dp";
4651 reg = <0 0x0a !! 4305 reg = <0 0xae98000 0 0x200>,
4652 <0 0x0a !! 4306 <0 0xae98200 0 0x200>,
4653 <0 0x0a !! 4307 <0 0xae98400 0 0x600>,
4654 <0 0x0a !! 4308 <0 0xae99000 0 0x400>,
4655 <0 0x0a !! 4309 <0 0xae99400 0 0x400>;
4656 4310
4657 interrupts-ex 4311 interrupts-extended = <&mdss 13>;
4658 4312
4659 clocks = <&di 4313 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4660 <&di 4314 <&dispcc DISP_CC_MDSS_DPTX1_AUX_CLK>,
4661 <&di 4315 <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK>,
4662 <&di 4316 <&dispcc DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
4663 <&di 4317 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK>;
4664 clock-names = 4318 clock-names = "core_iface",
4665 4319 "core_aux",
4666 4320 "ctrl_link",
4667 4321 "ctrl_link_iface",
4668 4322 "stream_pixel";
4669 4323
4670 assigned-cloc 4324 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
4671 4325 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>;
4672 assigned-cloc 4326 assigned-clock-parents = <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4673 4327 <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
4674 4328
4675 operating-poi 4329 operating-points-v2 = <&mdss_dp1_opp_table>;
4676 4330
4677 power-domains 4331 power-domains = <&rpmhpd RPMHPD_MMCX>;
4678 4332
4679 phys = <&usb_ 4333 phys = <&usb_1_ss1_qmpphy QMP_USB43DP_DP_PHY>;
4680 phy-names = " 4334 phy-names = "dp";
4681 4335
4682 #sound-dai-ce 4336 #sound-dai-cells = <0>;
4683 4337
4684 status = "dis 4338 status = "disabled";
4685 4339
4686 ports { 4340 ports {
4687 #addr 4341 #address-cells = <1>;
4688 #size 4342 #size-cells = <0>;
4689 4343
4690 port@ 4344 port@0 {
4691 4345 reg = <0>;
4692 4346
4693 4347 mdss_dp1_in: endpoint {
4694 4348 remote-endpoint = <&mdss_intf4_out>;
4695 4349 };
4696 }; 4350 };
4697 4351
4698 port@ 4352 port@1 {
4699 4353 reg = <1>;
4700 4354
4701 4355 mdss_dp1_out: endpoint {
4702 4356 remote-endpoint = <&usb_1_ss1_qmpphy_dp_in>;
4703 4357 };
4704 }; 4358 };
4705 }; 4359 };
4706 4360
4707 mdss_dp1_opp_ 4361 mdss_dp1_opp_table: opp-table {
4708 compa 4362 compatible = "operating-points-v2";
4709 4363
4710 opp-1 4364 opp-160000000 {
4711 4365 opp-hz = /bits/ 64 <160000000>;
4712 4366 required-opps = <&rpmhpd_opp_low_svs>;
4713 }; 4367 };
4714 4368
4715 opp-2 4369 opp-270000000 {
4716 4370 opp-hz = /bits/ 64 <270000000>;
4717 4371 required-opps = <&rpmhpd_opp_svs>;
4718 }; 4372 };
4719 4373
4720 opp-5 4374 opp-540000000 {
4721 4375 opp-hz = /bits/ 64 <540000000>;
4722 4376 required-opps = <&rpmhpd_opp_svs_l1>;
4723 }; 4377 };
4724 4378
4725 opp-8 4379 opp-810000000 {
4726 4380 opp-hz = /bits/ 64 <810000000>;
4727 4381 required-opps = <&rpmhpd_opp_nom>;
4728 }; 4382 };
4729 }; 4383 };
4730 }; 4384 };
4731 4385
4732 mdss_dp2: displayport 4386 mdss_dp2: displayport-controller@ae9a000 {
4733 compatible = 4387 compatible = "qcom,x1e80100-dp";
4734 reg = <0 0x0a !! 4388 reg = <0 0xae9a000 0 0x200>,
4735 <0 0x0a !! 4389 <0 0xae9a200 0 0x200>,
4736 <0 0x0a !! 4390 <0 0xae9a400 0 0x600>,
4737 <0 0x0a !! 4391 <0 0xae9b000 0 0x400>,
4738 <0 0x0a !! 4392 <0 0xae9b400 0 0x400>;
4739 4393
4740 interrupts-ex 4394 interrupts-extended = <&mdss 14>;
4741 4395
4742 clocks = <&di 4396 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4743 <&di 4397 <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>,
4744 <&di 4398 <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK>,
4745 <&di 4399 <&dispcc DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>,
4746 <&di 4400 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK>;
4747 clock-names = 4401 clock-names = "core_iface",
4748 4402 "core_aux",
4749 4403 "ctrl_link",
4750 4404 "ctrl_link_iface",
4751 4405 "stream_pixel";
4752 4406
4753 assigned-cloc 4407 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
4754 4408 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>;
4755 assigned-cloc 4409 assigned-clock-parents = <&usb_1_ss2_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4756 4410 <&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
4757 4411
4758 operating-poi 4412 operating-points-v2 = <&mdss_dp2_opp_table>;
4759 4413
4760 power-domains 4414 power-domains = <&rpmhpd RPMHPD_MMCX>;
4761 4415
4762 phys = <&usb_ 4416 phys = <&usb_1_ss2_qmpphy QMP_USB43DP_DP_PHY>;
4763 phy-names = " 4417 phy-names = "dp";
4764 4418
4765 #sound-dai-ce 4419 #sound-dai-cells = <0>;
4766 4420
4767 status = "dis 4421 status = "disabled";
4768 4422
4769 ports { 4423 ports {
4770 #addr 4424 #address-cells = <1>;
4771 #size 4425 #size-cells = <0>;
4772 4426
4773 port@ 4427 port@0 {
4774 4428 reg = <0>;
4775 4429 mdss_dp2_in: endpoint {
4776 4430 remote-endpoint = <&mdss_intf6_out>;
4777 4431 };
4778 }; 4432 };
4779 4433
4780 port@ 4434 port@1 {
4781 4435 reg = <1>;
4782 4436
4783 4437 mdss_dp2_out: endpoint {
4784 4438 remote-endpoint = <&usb_1_ss2_qmpphy_dp_in>;
4785 4439 };
4786 }; 4440 };
4787 }; 4441 };
4788 4442
4789 mdss_dp2_opp_ 4443 mdss_dp2_opp_table: opp-table {
4790 compa 4444 compatible = "operating-points-v2";
4791 4445
4792 opp-1 4446 opp-160000000 {
4793 4447 opp-hz = /bits/ 64 <160000000>;
4794 4448 required-opps = <&rpmhpd_opp_low_svs>;
4795 }; 4449 };
4796 4450
4797 opp-2 4451 opp-270000000 {
4798 4452 opp-hz = /bits/ 64 <270000000>;
4799 4453 required-opps = <&rpmhpd_opp_svs>;
4800 }; 4454 };
4801 4455
4802 opp-5 4456 opp-540000000 {
4803 4457 opp-hz = /bits/ 64 <540000000>;
4804 4458 required-opps = <&rpmhpd_opp_svs_l1>;
4805 }; 4459 };
4806 4460
4807 opp-8 4461 opp-810000000 {
4808 4462 opp-hz = /bits/ 64 <810000000>;
4809 4463 required-opps = <&rpmhpd_opp_nom>;
4810 }; 4464 };
4811 }; 4465 };
4812 }; 4466 };
4813 4467
4814 mdss_dp3: displayport 4468 mdss_dp3: displayport-controller@aea0000 {
4815 compatible = 4469 compatible = "qcom,x1e80100-dp";
4816 reg = <0 0x0a !! 4470 reg = <0 0xaea0000 0 0x200>,
4817 <0 0x0a !! 4471 <0 0xaea0200 0 0x200>,
4818 <0 0x0a !! 4472 <0 0xaea0400 0 0x600>,
4819 <0 0x0a !! 4473 <0 0xaea1000 0 0x400>,
4820 <0 0x0a !! 4474 <0 0xaea1400 0 0x400>;
4821 4475
4822 interrupts-ex 4476 interrupts-extended = <&mdss 15>;
4823 4477
4824 clocks = <&di 4478 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4825 <&di 4479 <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>,
4826 <&di 4480 <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK>,
4827 <&di 4481 <&dispcc DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>,
4828 <&di 4482 <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK>;
4829 clock-names = 4483 clock-names = "core_iface",
4830 4484 "core_aux",
4831 4485 "ctrl_link",
4832 4486 "ctrl_link_iface",
4833 4487 "stream_pixel";
4834 4488
4835 assigned-cloc 4489 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>,
4836 4490 <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>;
4837 assigned-cloc 4491 assigned-clock-parents = <&mdss_dp3_phy 0>,
4838 4492 <&mdss_dp3_phy 1>;
4839 4493
4840 operating-poi 4494 operating-points-v2 = <&mdss_dp3_opp_table>;
4841 4495
4842 power-domains 4496 power-domains = <&rpmhpd RPMHPD_MMCX>;
4843 4497
4844 phys = <&mdss 4498 phys = <&mdss_dp3_phy>;
4845 phy-names = " 4499 phy-names = "dp";
4846 4500
4847 #sound-dai-ce 4501 #sound-dai-cells = <0>;
4848 4502
4849 status = "dis 4503 status = "disabled";
4850 4504
4851 ports { 4505 ports {
4852 #addr 4506 #address-cells = <1>;
4853 #size 4507 #size-cells = <0>;
4854 4508
4855 port@ 4509 port@0 {
4856 4510 reg = <0>;
4857 4511
4858 4512 mdss_dp3_in: endpoint {
4859 4513 remote-endpoint = <&mdss_intf5_out>;
4860 4514 };
4861 }; 4515 };
4862 4516
4863 port@ 4517 port@1 {
4864 4518 reg = <1>;
4865 }; 4519 };
4866 }; 4520 };
4867 4521
4868 mdss_dp3_opp_ 4522 mdss_dp3_opp_table: opp-table {
4869 compa 4523 compatible = "operating-points-v2";
4870 4524
4871 opp-1 4525 opp-160000000 {
4872 4526 opp-hz = /bits/ 64 <160000000>;
4873 4527 required-opps = <&rpmhpd_opp_low_svs>;
4874 }; 4528 };
4875 4529
4876 opp-2 4530 opp-270000000 {
4877 4531 opp-hz = /bits/ 64 <270000000>;
4878 4532 required-opps = <&rpmhpd_opp_svs>;
4879 }; 4533 };
4880 4534
4881 opp-5 4535 opp-540000000 {
4882 4536 opp-hz = /bits/ 64 <540000000>;
4883 4537 required-opps = <&rpmhpd_opp_svs_l1>;
4884 }; 4538 };
4885 4539
4886 opp-8 4540 opp-810000000 {
4887 4541 opp-hz = /bits/ 64 <810000000>;
4888 4542 required-opps = <&rpmhpd_opp_nom>;
4889 }; 4543 };
4890 }; 4544 };
4891 }; 4545 };
4892 4546
4893 }; 4547 };
4894 4548
4895 mdss_dp2_phy: phy@aec2a00 { 4549 mdss_dp2_phy: phy@aec2a00 {
4896 compatible = "qcom,x1 4550 compatible = "qcom,x1e80100-dp-phy";
4897 reg = <0 0x0aec2a00 0 4551 reg = <0 0x0aec2a00 0 0x19c>,
4898 <0 0x0aec2200 0 4552 <0 0x0aec2200 0 0xec>,
4899 <0 0x0aec2600 0 4553 <0 0x0aec2600 0 0xec>,
4900 <0 0x0aec2000 0 4554 <0 0x0aec2000 0 0x1c8>;
4901 4555
4902 clocks = <&dispcc DIS 4556 clocks = <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>,
4903 <&dispcc DIS 4557 <&dispcc DISP_CC_MDSS_AHB_CLK>;
4904 clock-names = "aux", 4558 clock-names = "aux",
4905 "cfg_ah 4559 "cfg_ahb";
4906 4560
4907 power-domains = <&rpm 4561 power-domains = <&rpmhpd RPMHPD_MX>;
4908 4562
4909 #clock-cells = <1>; 4563 #clock-cells = <1>;
4910 #phy-cells = <0>; 4564 #phy-cells = <0>;
4911 4565
4912 status = "disabled"; 4566 status = "disabled";
4913 }; 4567 };
4914 4568
4915 mdss_dp3_phy: phy@aec5a00 { 4569 mdss_dp3_phy: phy@aec5a00 {
4916 compatible = "qcom,x1 4570 compatible = "qcom,x1e80100-dp-phy";
4917 reg = <0 0x0aec5a00 0 4571 reg = <0 0x0aec5a00 0 0x19c>,
4918 <0 0x0aec5200 0 4572 <0 0x0aec5200 0 0xec>,
4919 <0 0x0aec5600 0 4573 <0 0x0aec5600 0 0xec>,
4920 <0 0x0aec5000 0 4574 <0 0x0aec5000 0 0x1c8>;
4921 4575
4922 clocks = <&dispcc DIS 4576 clocks = <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>,
4923 <&dispcc DIS 4577 <&dispcc DISP_CC_MDSS_AHB_CLK>;
4924 clock-names = "aux", 4578 clock-names = "aux",
4925 "cfg_ah 4579 "cfg_ahb";
4926 4580
4927 power-domains = <&rpm 4581 power-domains = <&rpmhpd RPMHPD_MX>;
4928 4582
4929 #clock-cells = <1>; 4583 #clock-cells = <1>;
4930 #phy-cells = <0>; 4584 #phy-cells = <0>;
4931 4585
4932 status = "disabled"; 4586 status = "disabled";
4933 }; 4587 };
4934 4588
4935 dispcc: clock-controller@af00 4589 dispcc: clock-controller@af00000 {
4936 compatible = "qcom,x1 4590 compatible = "qcom,x1e80100-dispcc";
4937 reg = <0 0x0af00000 0 4591 reg = <0 0x0af00000 0 0x20000>;
4938 clocks = <&bi_tcxo_di 4592 clocks = <&bi_tcxo_div2>,
4939 <&bi_tcxo_ao 4593 <&bi_tcxo_ao_div2>,
4940 <&gcc GCC_DI 4594 <&gcc GCC_DISP_AHB_CLK>,
4941 <&sleep_clk> 4595 <&sleep_clk>,
4942 <0>, /* dsi0 4596 <0>, /* dsi0 */
4943 <0>, 4597 <0>,
4944 <0>, /* dsi1 4598 <0>, /* dsi1 */
4945 <0>, 4599 <0>,
4946 <&usb_1_ss0_ 4600 <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp0 */
4947 <&usb_1_ss0_ 4601 <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
4948 <&usb_1_ss1_ 4602 <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp1 */
4949 <&usb_1_ss1_ 4603 <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
4950 <&usb_1_ss2_ 4604 <&usb_1_ss2_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp2 */
4951 <&usb_1_ss2_ 4605 <&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
4952 <&mdss_dp3_p 4606 <&mdss_dp3_phy 0>, /* dp3 */
4953 <&mdss_dp3_p 4607 <&mdss_dp3_phy 1>;
4954 power-domains = <&rpm 4608 power-domains = <&rpmhpd RPMHPD_MMCX>;
4955 required-opps = <&rpm 4609 required-opps = <&rpmhpd_opp_low_svs>;
4956 #clock-cells = <1>; 4610 #clock-cells = <1>;
4957 #reset-cells = <1>; 4611 #reset-cells = <1>;
4958 #power-domain-cells = 4612 #power-domain-cells = <1>;
4959 }; 4613 };
4960 4614
4961 pdc: interrupt-controller@b22 4615 pdc: interrupt-controller@b220000 {
4962 compatible = "qcom,x1 4616 compatible = "qcom,x1e80100-pdc", "qcom,pdc";
4963 reg = <0 0x0b220000 0 4617 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
4964 4618
4965 qcom,pdc-ranges = <0 4619 qcom,pdc-ranges = <0 480 42>, <42 251 5>,
4966 <47 4620 <47 522 52>, <99 609 32>,
4967 <13 4621 <131 717 12>, <143 816 19>;
4968 #interrupt-cells = <2 4622 #interrupt-cells = <2>;
4969 interrupt-parent = <& 4623 interrupt-parent = <&intc>;
4970 interrupt-controller; 4624 interrupt-controller;
4971 }; 4625 };
4972 4626
4973 aoss_qmp: power-management@c3 4627 aoss_qmp: power-management@c300000 {
4974 compatible = "qcom,x1 4628 compatible = "qcom,x1e80100-aoss-qmp", "qcom,aoss-qmp";
4975 reg = <0 0x0c300000 0 4629 reg = <0 0x0c300000 0 0x400>;
4976 interrupt-parent = <& 4630 interrupt-parent = <&ipcc>;
4977 interrupts-extended = 4631 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
4978 4632 IRQ_TYPE_EDGE_RISING>;
4979 mboxes = <&ipcc IPCC_ 4633 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
4980 4634
4981 #clock-cells = <0>; 4635 #clock-cells = <0>;
4982 }; 4636 };
4983 4637
4984 sram@c3f0000 { <<
4985 compatible = "qcom,rp <<
4986 reg = <0 0x0c3f0000 0 <<
4987 }; <<
4988 <<
4989 spmi: arbiter@c400000 { 4638 spmi: arbiter@c400000 {
4990 compatible = "qcom,x1 4639 compatible = "qcom,x1e80100-spmi-pmic-arb";
4991 reg = <0 0x0c400000 0 4640 reg = <0 0x0c400000 0 0x3000>,
4992 <0 0x0c500000 0 4641 <0 0x0c500000 0 0x400000>,
4993 <0 0x0c440000 0 4642 <0 0x0c440000 0 0x80000>;
4994 reg-names = "core", " 4643 reg-names = "core", "chnls", "obsrvr";
4995 4644
4996 qcom,ee = <0>; 4645 qcom,ee = <0>;
4997 qcom,channel = <0>; 4646 qcom,channel = <0>;
4998 4647
4999 #address-cells = <2>; 4648 #address-cells = <2>;
5000 #size-cells = <2>; 4649 #size-cells = <2>;
5001 ranges; 4650 ranges;
5002 4651
5003 spmi_bus0: spmi@c42d0 4652 spmi_bus0: spmi@c42d000 {
5004 reg = <0 0x0c 4653 reg = <0 0x0c42d000 0 0x4000>,
5005 <0 0x0c 4654 <0 0x0c4c0000 0 0x10000>;
5006 reg-names = " 4655 reg-names = "cnfg", "intr";
5007 4656
5008 interrupt-nam 4657 interrupt-names = "periph_irq";
5009 interrupts-ex 4658 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
5010 interrupt-con 4659 interrupt-controller;
5011 #interrupt-ce 4660 #interrupt-cells = <4>;
5012 4661
5013 #address-cell 4662 #address-cells = <2>;
5014 #size-cells = 4663 #size-cells = <0>;
5015 }; 4664 };
5016 4665
5017 spmi_bus1: spmi@c4320 4666 spmi_bus1: spmi@c432000 {
5018 reg = <0 0x0c 4667 reg = <0 0x0c432000 0 0x4000>,
5019 <0 0x0c 4668 <0 0x0c4d0000 0 0x10000>;
5020 reg-names = " 4669 reg-names = "cnfg", "intr";
5021 4670
5022 interrupt-nam 4671 interrupt-names = "periph_irq";
5023 interrupts-ex 4672 interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>;
5024 interrupt-con 4673 interrupt-controller;
5025 #interrupt-ce 4674 #interrupt-cells = <4>;
5026 4675
5027 #address-cell 4676 #address-cells = <2>;
5028 #size-cells = 4677 #size-cells = <0>;
5029 }; 4678 };
5030 }; 4679 };
5031 4680
5032 tlmm: pinctrl@f100000 { 4681 tlmm: pinctrl@f100000 {
5033 compatible = "qcom,x1 4682 compatible = "qcom,x1e80100-tlmm";
5034 reg = <0 0x0f100000 0 4683 reg = <0 0x0f100000 0 0xf00000>;
5035 4684
5036 interrupts = <GIC_SPI 4685 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
5037 4686
5038 gpio-controller; 4687 gpio-controller;
5039 #gpio-cells = <2>; 4688 #gpio-cells = <2>;
5040 4689
5041 interrupt-controller; 4690 interrupt-controller;
5042 #interrupt-cells = <2 4691 #interrupt-cells = <2>;
5043 4692
5044 gpio-ranges = <&tlmm 4693 gpio-ranges = <&tlmm 0 0 239>;
5045 wakeup-parent = <&pdc 4694 wakeup-parent = <&pdc>;
5046 4695
5047 qup_i2c0_data_clk: qu 4696 qup_i2c0_data_clk: qup-i2c0-data-clk-state {
5048 /* SDA, SCL * 4697 /* SDA, SCL */
5049 pins = "gpio0 4698 pins = "gpio0", "gpio1";
5050 function = "q 4699 function = "qup0_se0";
5051 drive-strengt 4700 drive-strength = <2>;
5052 bias-pull-up 4701 bias-pull-up = <2200>;
5053 }; 4702 };
5054 4703
5055 qup_i2c1_data_clk: qu 4704 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
5056 /* SDA, SCL * 4705 /* SDA, SCL */
5057 pins = "gpio4 4706 pins = "gpio4", "gpio5";
5058 function = "q 4707 function = "qup0_se1";
5059 drive-strengt 4708 drive-strength = <2>;
5060 bias-pull-up 4709 bias-pull-up = <2200>;
5061 }; 4710 };
5062 4711
5063 qup_i2c2_data_clk: qu 4712 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
5064 /* SDA, SCL * 4713 /* SDA, SCL */
5065 pins = "gpio8 4714 pins = "gpio8", "gpio9";
5066 function = "q 4715 function = "qup0_se2";
5067 drive-strengt 4716 drive-strength = <2>;
5068 bias-pull-up 4717 bias-pull-up = <2200>;
5069 }; 4718 };
5070 4719
5071 qup_i2c3_data_clk: qu 4720 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
5072 /* SDA, SCL * 4721 /* SDA, SCL */
5073 pins = "gpio1 4722 pins = "gpio12", "gpio13";
5074 function = "q 4723 function = "qup0_se3";
5075 drive-strengt 4724 drive-strength = <2>;
5076 bias-pull-up 4725 bias-pull-up = <2200>;
5077 }; 4726 };
5078 4727
5079 qup_i2c4_data_clk: qu 4728 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
5080 /* SDA, SCL * 4729 /* SDA, SCL */
5081 pins = "gpio1 4730 pins = "gpio16", "gpio17";
5082 function = "q 4731 function = "qup0_se4";
5083 drive-strengt 4732 drive-strength = <2>;
5084 bias-pull-up 4733 bias-pull-up = <2200>;
5085 }; 4734 };
5086 4735
5087 qup_i2c5_data_clk: qu 4736 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
5088 /* SDA, SCL * 4737 /* SDA, SCL */
5089 pins = "gpio2 4738 pins = "gpio20", "gpio21";
5090 function = "q 4739 function = "qup0_se5";
5091 drive-strengt 4740 drive-strength = <2>;
5092 bias-pull-up 4741 bias-pull-up = <2200>;
5093 }; 4742 };
5094 4743
5095 qup_i2c6_data_clk: qu 4744 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
5096 /* SDA, SCL * 4745 /* SDA, SCL */
5097 pins = "gpio2 4746 pins = "gpio24", "gpio25";
5098 function = "q 4747 function = "qup0_se6";
5099 drive-strengt 4748 drive-strength = <2>;
5100 bias-pull-up 4749 bias-pull-up = <2200>;
5101 }; 4750 };
5102 4751
5103 qup_i2c7_data_clk: qu 4752 qup_i2c7_data_clk: qup-i2c7-data-clk-state {
5104 /* SDA, SCL * 4753 /* SDA, SCL */
5105 pins = "gpio1 4754 pins = "gpio14", "gpio15";
5106 function = "q 4755 function = "qup0_se7";
5107 drive-strengt 4756 drive-strength = <2>;
5108 bias-pull-up 4757 bias-pull-up = <2200>;
5109 }; 4758 };
5110 4759
5111 qup_i2c8_data_clk: qu 4760 qup_i2c8_data_clk: qup-i2c8-data-clk-state {
5112 /* SDA, SCL * 4761 /* SDA, SCL */
5113 pins = "gpio3 4762 pins = "gpio32", "gpio33";
5114 function = "q 4763 function = "qup1_se0";
5115 drive-strengt 4764 drive-strength = <2>;
5116 bias-pull-up 4765 bias-pull-up = <2200>;
5117 }; 4766 };
5118 4767
5119 qup_i2c9_data_clk: qu 4768 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
5120 /* SDA, SCL * 4769 /* SDA, SCL */
5121 pins = "gpio3 4770 pins = "gpio36", "gpio37";
5122 function = "q 4771 function = "qup1_se1";
5123 drive-strengt 4772 drive-strength = <2>;
5124 bias-pull-up 4773 bias-pull-up = <2200>;
5125 }; 4774 };
5126 4775
5127 qup_i2c10_data_clk: q 4776 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
5128 /* SDA, SCL * 4777 /* SDA, SCL */
5129 pins = "gpio4 4778 pins = "gpio40", "gpio41";
5130 function = "q 4779 function = "qup1_se2";
5131 drive-strengt 4780 drive-strength = <2>;
5132 bias-pull-up 4781 bias-pull-up = <2200>;
5133 }; 4782 };
5134 4783
5135 qup_i2c11_data_clk: q 4784 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
5136 /* SDA, SCL * 4785 /* SDA, SCL */
5137 pins = "gpio4 4786 pins = "gpio44", "gpio45";
5138 function = "q 4787 function = "qup1_se3";
5139 drive-strengt 4788 drive-strength = <2>;
5140 bias-pull-up 4789 bias-pull-up = <2200>;
5141 }; 4790 };
5142 4791
5143 qup_i2c12_data_clk: q 4792 qup_i2c12_data_clk: qup-i2c12-data-clk-state {
5144 /* SDA, SCL * 4793 /* SDA, SCL */
5145 pins = "gpio4 4794 pins = "gpio48", "gpio49";
5146 function = "q 4795 function = "qup1_se4";
5147 drive-strengt 4796 drive-strength = <2>;
5148 bias-pull-up 4797 bias-pull-up = <2200>;
5149 }; 4798 };
5150 4799
5151 qup_i2c13_data_clk: q 4800 qup_i2c13_data_clk: qup-i2c13-data-clk-state {
5152 /* SDA, SCL * 4801 /* SDA, SCL */
5153 pins = "gpio5 4802 pins = "gpio52", "gpio53";
5154 function = "q 4803 function = "qup1_se5";
5155 drive-strengt 4804 drive-strength = <2>;
5156 bias-pull-up 4805 bias-pull-up = <2200>;
5157 }; 4806 };
5158 4807
5159 qup_i2c14_data_clk: q 4808 qup_i2c14_data_clk: qup-i2c14-data-clk-state {
5160 /* SDA, SCL * 4809 /* SDA, SCL */
5161 pins = "gpio5 4810 pins = "gpio56", "gpio57";
5162 function = "q 4811 function = "qup1_se6";
5163 drive-strengt 4812 drive-strength = <2>;
5164 bias-pull-up 4813 bias-pull-up = <2200>;
5165 }; 4814 };
5166 4815
5167 qup_i2c15_data_clk: q 4816 qup_i2c15_data_clk: qup-i2c15-data-clk-state {
5168 /* SDA, SCL * 4817 /* SDA, SCL */
5169 pins = "gpio5 4818 pins = "gpio54", "gpio55";
5170 function = "q 4819 function = "qup1_se7";
5171 drive-strengt 4820 drive-strength = <2>;
5172 bias-pull-up 4821 bias-pull-up = <2200>;
5173 }; 4822 };
5174 4823
5175 qup_i2c16_data_clk: q 4824 qup_i2c16_data_clk: qup-i2c16-data-clk-state {
5176 /* SDA, SCL * 4825 /* SDA, SCL */
5177 pins = "gpio6 4826 pins = "gpio64", "gpio65";
5178 function = "q 4827 function = "qup2_se0";
5179 drive-strengt 4828 drive-strength = <2>;
5180 bias-pull-up 4829 bias-pull-up = <2200>;
5181 }; 4830 };
5182 4831
5183 qup_i2c17_data_clk: q 4832 qup_i2c17_data_clk: qup-i2c17-data-clk-state {
5184 /* SDA, SCL * 4833 /* SDA, SCL */
5185 pins = "gpio6 4834 pins = "gpio68", "gpio69";
5186 function = "q 4835 function = "qup2_se1";
5187 drive-strengt 4836 drive-strength = <2>;
5188 bias-pull-up 4837 bias-pull-up = <2200>;
5189 }; 4838 };
5190 4839
5191 qup_i2c18_data_clk: q 4840 qup_i2c18_data_clk: qup-i2c18-data-clk-state {
5192 /* SDA, SCL * 4841 /* SDA, SCL */
5193 pins = "gpio7 4842 pins = "gpio72", "gpio73";
5194 function = "q 4843 function = "qup2_se2";
5195 drive-strengt 4844 drive-strength = <2>;
5196 bias-pull-up 4845 bias-pull-up = <2200>;
5197 }; 4846 };
5198 4847
5199 qup_i2c19_data_clk: q 4848 qup_i2c19_data_clk: qup-i2c19-data-clk-state {
5200 /* SDA, SCL * 4849 /* SDA, SCL */
5201 pins = "gpio7 4850 pins = "gpio76", "gpio77";
5202 function = "q 4851 function = "qup2_se3";
5203 drive-strengt 4852 drive-strength = <2>;
5204 bias-pull-up 4853 bias-pull-up = <2200>;
5205 }; 4854 };
5206 4855
5207 qup_i2c20_data_clk: q 4856 qup_i2c20_data_clk: qup-i2c20-data-clk-state {
5208 /* SDA, SCL * 4857 /* SDA, SCL */
5209 pins = "gpio8 4858 pins = "gpio80", "gpio81";
5210 function = "q 4859 function = "qup2_se4";
5211 drive-strengt 4860 drive-strength = <2>;
5212 bias-pull-up 4861 bias-pull-up = <2200>;
5213 }; 4862 };
5214 4863
5215 qup_i2c21_data_clk: q 4864 qup_i2c21_data_clk: qup-i2c21-data-clk-state {
5216 /* SDA, SCL * 4865 /* SDA, SCL */
5217 pins = "gpio8 4866 pins = "gpio84", "gpio85";
5218 function = "q 4867 function = "qup2_se5";
5219 drive-strengt 4868 drive-strength = <2>;
5220 bias-pull-up 4869 bias-pull-up = <2200>;
5221 }; 4870 };
5222 4871
5223 qup_i2c22_data_clk: q 4872 qup_i2c22_data_clk: qup-i2c22-data-clk-state {
5224 /* SDA, SCL * 4873 /* SDA, SCL */
5225 pins = "gpio8 4874 pins = "gpio88", "gpio89";
5226 function = "q 4875 function = "qup2_se6";
5227 drive-strengt 4876 drive-strength = <2>;
5228 bias-pull-up 4877 bias-pull-up = <2200>;
5229 }; 4878 };
5230 4879
5231 qup_i2c23_data_clk: q 4880 qup_i2c23_data_clk: qup-i2c23-data-clk-state {
5232 /* SDA, SCL * 4881 /* SDA, SCL */
5233 pins = "gpio8 4882 pins = "gpio86", "gpio87";
5234 function = "q 4883 function = "qup2_se7";
5235 drive-strengt 4884 drive-strength = <2>;
5236 bias-pull-up 4885 bias-pull-up = <2200>;
5237 }; 4886 };
5238 4887
5239 qup_spi0_cs: qup-spi0 4888 qup_spi0_cs: qup-spi0-cs-state {
5240 pins = "gpio3 4889 pins = "gpio3";
5241 function = "q 4890 function = "qup0_se0";
5242 drive-strengt 4891 drive-strength = <6>;
5243 bias-disable; 4892 bias-disable;
5244 }; 4893 };
5245 4894
5246 qup_spi0_data_clk: qu 4895 qup_spi0_data_clk: qup-spi0-data-clk-state {
5247 /* MISO, MOSI 4896 /* MISO, MOSI, CLK */
5248 pins = "gpio0 4897 pins = "gpio0", "gpio1", "gpio2";
5249 function = "q 4898 function = "qup0_se0";
5250 drive-strengt 4899 drive-strength = <6>;
5251 bias-disable; 4900 bias-disable;
5252 }; 4901 };
5253 4902
5254 qup_spi1_cs: qup-spi1 4903 qup_spi1_cs: qup-spi1-cs-state {
5255 pins = "gpio7 4904 pins = "gpio7";
5256 function = "q 4905 function = "qup0_se1";
5257 drive-strengt 4906 drive-strength = <6>;
5258 bias-disable; 4907 bias-disable;
5259 }; 4908 };
5260 4909
5261 qup_spi1_data_clk: qu 4910 qup_spi1_data_clk: qup-spi1-data-clk-state {
5262 /* MISO, MOSI 4911 /* MISO, MOSI, CLK */
5263 pins = "gpio4 4912 pins = "gpio4", "gpio5", "gpio6";
5264 function = "q 4913 function = "qup0_se1";
5265 drive-strengt 4914 drive-strength = <6>;
5266 bias-disable; 4915 bias-disable;
5267 }; 4916 };
5268 4917
5269 qup_spi2_cs: qup-spi2 4918 qup_spi2_cs: qup-spi2-cs-state {
5270 pins = "gpio1 4919 pins = "gpio11";
5271 function = "q 4920 function = "qup0_se2";
5272 drive-strengt 4921 drive-strength = <6>;
5273 bias-disable; 4922 bias-disable;
5274 }; 4923 };
5275 4924
5276 qup_spi2_data_clk: qu 4925 qup_spi2_data_clk: qup-spi2-data-clk-state {
5277 /* MISO, MOSI 4926 /* MISO, MOSI, CLK */
5278 pins = "gpio8 4927 pins = "gpio8", "gpio9", "gpio10";
5279 function = "q 4928 function = "qup0_se2";
5280 drive-strengt 4929 drive-strength = <6>;
5281 bias-disable; 4930 bias-disable;
5282 }; 4931 };
5283 4932
5284 qup_spi3_cs: qup-spi3 4933 qup_spi3_cs: qup-spi3-cs-state {
5285 pins = "gpio1 4934 pins = "gpio15";
5286 function = "q 4935 function = "qup0_se3";
5287 drive-strengt 4936 drive-strength = <6>;
5288 bias-disable; 4937 bias-disable;
5289 }; 4938 };
5290 4939
5291 qup_spi3_data_clk: qu 4940 qup_spi3_data_clk: qup-spi3-data-clk-state {
5292 /* MISO, MOSI 4941 /* MISO, MOSI, CLK */
5293 pins = "gpio1 4942 pins = "gpio12", "gpio13", "gpio14";
5294 function = "q 4943 function = "qup0_se3";
5295 drive-strengt 4944 drive-strength = <6>;
5296 bias-disable; 4945 bias-disable;
5297 }; 4946 };
5298 4947
5299 qup_spi4_cs: qup-spi4 4948 qup_spi4_cs: qup-spi4-cs-state {
5300 pins = "gpio1 4949 pins = "gpio19";
5301 function = "q 4950 function = "qup0_se4";
5302 drive-strengt 4951 drive-strength = <6>;
5303 bias-disable; 4952 bias-disable;
5304 }; 4953 };
5305 4954
5306 qup_spi4_data_clk: qu 4955 qup_spi4_data_clk: qup-spi4-data-clk-state {
5307 /* MISO, MOSI 4956 /* MISO, MOSI, CLK */
5308 pins = "gpio1 4957 pins = "gpio16", "gpio17", "gpio18";
5309 function = "q 4958 function = "qup0_se4";
5310 drive-strengt 4959 drive-strength = <6>;
5311 bias-disable; 4960 bias-disable;
5312 }; 4961 };
5313 4962
5314 qup_spi5_cs: qup-spi5 4963 qup_spi5_cs: qup-spi5-cs-state {
5315 pins = "gpio2 4964 pins = "gpio23";
5316 function = "q 4965 function = "qup0_se5";
5317 drive-strengt 4966 drive-strength = <6>;
5318 bias-disable; 4967 bias-disable;
5319 }; 4968 };
5320 4969
5321 qup_spi5_data_clk: qu 4970 qup_spi5_data_clk: qup-spi5-data-clk-state {
5322 /* MISO, MOSI 4971 /* MISO, MOSI, CLK */
5323 pins = "gpio2 4972 pins = "gpio20", "gpio21", "gpio22";
5324 function = "q 4973 function = "qup0_se5";
5325 drive-strengt 4974 drive-strength = <6>;
5326 bias-disable; 4975 bias-disable;
5327 }; 4976 };
5328 4977
5329 qup_spi6_cs: qup-spi6 4978 qup_spi6_cs: qup-spi6-cs-state {
5330 pins = "gpio2 4979 pins = "gpio27";
5331 function = "q 4980 function = "qup0_se6";
5332 drive-strengt 4981 drive-strength = <6>;
5333 bias-disable; 4982 bias-disable;
5334 }; 4983 };
5335 4984
5336 qup_spi6_data_clk: qu 4985 qup_spi6_data_clk: qup-spi6-data-clk-state {
5337 /* MISO, MOSI 4986 /* MISO, MOSI, CLK */
5338 pins = "gpio2 4987 pins = "gpio24", "gpio25", "gpio26";
5339 function = "q 4988 function = "qup0_se6";
5340 drive-strengt 4989 drive-strength = <6>;
5341 bias-disable; 4990 bias-disable;
5342 }; 4991 };
5343 4992
5344 qup_spi7_cs: qup-spi7 4993 qup_spi7_cs: qup-spi7-cs-state {
5345 pins = "gpio1 4994 pins = "gpio13";
5346 function = "q 4995 function = "qup0_se7";
5347 drive-strengt 4996 drive-strength = <6>;
5348 bias-disable; 4997 bias-disable;
5349 }; 4998 };
5350 4999
5351 qup_spi7_data_clk: qu 5000 qup_spi7_data_clk: qup-spi7-data-clk-state {
5352 /* MISO, MOSI 5001 /* MISO, MOSI, CLK */
5353 pins = "gpio1 5002 pins = "gpio14", "gpio15", "gpio12";
5354 function = "q 5003 function = "qup0_se7";
5355 drive-strengt 5004 drive-strength = <6>;
5356 bias-disable; 5005 bias-disable;
5357 }; 5006 };
5358 5007
5359 qup_spi8_cs: qup-spi8 5008 qup_spi8_cs: qup-spi8-cs-state {
5360 pins = "gpio3 5009 pins = "gpio35";
5361 function = "q 5010 function = "qup1_se0";
5362 drive-strengt 5011 drive-strength = <6>;
5363 bias-disable; 5012 bias-disable;
5364 }; 5013 };
5365 5014
5366 qup_spi8_data_clk: qu 5015 qup_spi8_data_clk: qup-spi8-data-clk-state {
5367 /* MISO, MOSI 5016 /* MISO, MOSI, CLK */
5368 pins = "gpio3 5017 pins = "gpio32", "gpio33", "gpio34";
5369 function = "q 5018 function = "qup1_se0";
5370 drive-strengt 5019 drive-strength = <6>;
5371 bias-disable; 5020 bias-disable;
5372 }; 5021 };
5373 5022
5374 qup_spi9_cs: qup-spi9 5023 qup_spi9_cs: qup-spi9-cs-state {
5375 pins = "gpio3 5024 pins = "gpio39";
5376 function = "q 5025 function = "qup1_se1";
5377 drive-strengt 5026 drive-strength = <6>;
5378 bias-disable; 5027 bias-disable;
5379 }; 5028 };
5380 5029
5381 qup_spi9_data_clk: qu 5030 qup_spi9_data_clk: qup-spi9-data-clk-state {
5382 /* MISO, MOSI 5031 /* MISO, MOSI, CLK */
5383 pins = "gpio3 5032 pins = "gpio36", "gpio37", "gpio38";
5384 function = "q 5033 function = "qup1_se1";
5385 drive-strengt 5034 drive-strength = <6>;
5386 bias-disable; 5035 bias-disable;
5387 }; 5036 };
5388 5037
5389 qup_spi10_cs: qup-spi 5038 qup_spi10_cs: qup-spi10-cs-state {
5390 pins = "gpio4 5039 pins = "gpio43";
5391 function = "q 5040 function = "qup1_se2";
5392 drive-strengt 5041 drive-strength = <6>;
5393 bias-disable; 5042 bias-disable;
5394 }; 5043 };
5395 5044
5396 qup_spi10_data_clk: q 5045 qup_spi10_data_clk: qup-spi10-data-clk-state {
5397 /* MISO, MOSI 5046 /* MISO, MOSI, CLK */
5398 pins = "gpio4 5047 pins = "gpio40", "gpio41", "gpio42";
5399 function = "q 5048 function = "qup1_se2";
5400 drive-strengt 5049 drive-strength = <6>;
5401 bias-disable; 5050 bias-disable;
5402 }; 5051 };
5403 5052
5404 qup_spi11_cs: qup-spi 5053 qup_spi11_cs: qup-spi11-cs-state {
5405 pins = "gpio4 5054 pins = "gpio47";
5406 function = "q 5055 function = "qup1_se3";
5407 drive-strengt 5056 drive-strength = <6>;
5408 bias-disable; 5057 bias-disable;
5409 }; 5058 };
5410 5059
5411 qup_spi11_data_clk: q 5060 qup_spi11_data_clk: qup-spi11-data-clk-state {
5412 /* MISO, MOSI 5061 /* MISO, MOSI, CLK */
5413 pins = "gpio4 5062 pins = "gpio44", "gpio45", "gpio46";
5414 function = "q 5063 function = "qup1_se3";
5415 drive-strengt 5064 drive-strength = <6>;
5416 bias-disable; 5065 bias-disable;
5417 }; 5066 };
5418 5067
5419 qup_spi12_cs: qup-spi 5068 qup_spi12_cs: qup-spi12-cs-state {
5420 pins = "gpio5 5069 pins = "gpio51";
5421 function = "q 5070 function = "qup1_se4";
5422 drive-strengt 5071 drive-strength = <6>;
5423 bias-disable; 5072 bias-disable;
5424 }; 5073 };
5425 5074
5426 qup_spi12_data_clk: q 5075 qup_spi12_data_clk: qup-spi12-data-clk-state {
5427 /* MISO, MOSI 5076 /* MISO, MOSI, CLK */
5428 pins = "gpio4 5077 pins = "gpio48", "gpio49", "gpio50";
5429 function = "q 5078 function = "qup1_se4";
5430 drive-strengt 5079 drive-strength = <6>;
5431 bias-disable; 5080 bias-disable;
5432 }; 5081 };
5433 5082
5434 qup_spi13_cs: qup-spi 5083 qup_spi13_cs: qup-spi13-cs-state {
5435 pins = "gpio5 5084 pins = "gpio55";
5436 function = "q 5085 function = "qup1_se5";
5437 drive-strengt 5086 drive-strength = <6>;
5438 bias-disable; 5087 bias-disable;
5439 }; 5088 };
5440 5089
5441 qup_spi13_data_clk: q 5090 qup_spi13_data_clk: qup-spi13-data-clk-state {
5442 /* MISO, MOSI 5091 /* MISO, MOSI, CLK */
5443 pins = "gpio5 5092 pins = "gpio52", "gpio53", "gpio54";
5444 function = "q 5093 function = "qup1_se5";
5445 drive-strengt 5094 drive-strength = <6>;
5446 bias-disable; 5095 bias-disable;
5447 }; 5096 };
5448 5097
5449 qup_spi14_cs: qup-spi 5098 qup_spi14_cs: qup-spi14-cs-state {
5450 pins = "gpio5 5099 pins = "gpio59";
5451 function = "q 5100 function = "qup1_se6";
5452 drive-strengt 5101 drive-strength = <6>;
5453 bias-disable; 5102 bias-disable;
5454 }; 5103 };
5455 5104
5456 qup_spi14_data_clk: q 5105 qup_spi14_data_clk: qup-spi14-data-clk-state {
5457 /* MISO, MOSI 5106 /* MISO, MOSI, CLK */
5458 pins = "gpio5 5107 pins = "gpio56", "gpio57", "gpio58";
5459 function = "q 5108 function = "qup1_se6";
5460 drive-strengt 5109 drive-strength = <6>;
5461 bias-disable; 5110 bias-disable;
5462 }; 5111 };
5463 5112
5464 qup_spi15_cs: qup-spi 5113 qup_spi15_cs: qup-spi15-cs-state {
5465 pins = "gpio5 5114 pins = "gpio53";
5466 function = "q 5115 function = "qup1_se7";
5467 drive-strengt 5116 drive-strength = <6>;
5468 bias-disable; 5117 bias-disable;
5469 }; 5118 };
5470 5119
5471 qup_spi15_data_clk: q 5120 qup_spi15_data_clk: qup-spi15-data-clk-state {
5472 /* MISO, MOSI 5121 /* MISO, MOSI, CLK */
5473 pins = "gpio5 5122 pins = "gpio54", "gpio55", "gpio52";
5474 function = "q 5123 function = "qup1_se7";
5475 drive-strengt 5124 drive-strength = <6>;
5476 bias-disable; 5125 bias-disable;
5477 }; 5126 };
5478 5127
5479 qup_spi16_cs: qup-spi 5128 qup_spi16_cs: qup-spi16-cs-state {
5480 pins = "gpio6 5129 pins = "gpio67";
5481 function = "q 5130 function = "qup2_se0";
5482 drive-strengt 5131 drive-strength = <6>;
5483 bias-disable; 5132 bias-disable;
5484 }; 5133 };
5485 5134
5486 qup_spi16_data_clk: q 5135 qup_spi16_data_clk: qup-spi16-data-clk-state {
5487 /* MISO, MOSI 5136 /* MISO, MOSI, CLK */
5488 pins = "gpio6 5137 pins = "gpio64", "gpio65", "gpio66";
5489 function = "q 5138 function = "qup2_se0";
5490 drive-strengt 5139 drive-strength = <6>;
5491 bias-disable; 5140 bias-disable;
5492 }; 5141 };
5493 5142
5494 qup_spi17_cs: qup-spi 5143 qup_spi17_cs: qup-spi17-cs-state {
5495 pins = "gpio7 5144 pins = "gpio71";
5496 function = "q 5145 function = "qup2_se1";
5497 drive-strengt 5146 drive-strength = <6>;
5498 bias-disable; 5147 bias-disable;
5499 }; 5148 };
5500 5149
5501 qup_spi17_data_clk: q 5150 qup_spi17_data_clk: qup-spi17-data-clk-state {
5502 /* MISO, MOSI 5151 /* MISO, MOSI, CLK */
5503 pins = "gpio6 5152 pins = "gpio68", "gpio69", "gpio70";
5504 function = "q 5153 function = "qup2_se1";
5505 drive-strengt 5154 drive-strength = <6>;
5506 bias-disable; 5155 bias-disable;
5507 }; 5156 };
5508 5157
5509 qup_spi18_cs: qup-spi 5158 qup_spi18_cs: qup-spi18-cs-state {
5510 pins = "gpio7 5159 pins = "gpio75";
5511 function = "q 5160 function = "qup2_se2";
5512 drive-strengt 5161 drive-strength = <6>;
5513 bias-disable; 5162 bias-disable;
5514 }; 5163 };
5515 5164
5516 qup_spi18_data_clk: q 5165 qup_spi18_data_clk: qup-spi18-data-clk-state {
5517 /* MISO, MOSI 5166 /* MISO, MOSI, CLK */
5518 pins = "gpio7 5167 pins = "gpio72", "gpio73", "gpio74";
5519 function = "q 5168 function = "qup2_se2";
5520 drive-strengt 5169 drive-strength = <6>;
5521 bias-disable; 5170 bias-disable;
5522 }; 5171 };
5523 5172
5524 qup_spi19_cs: qup-spi 5173 qup_spi19_cs: qup-spi19-cs-state {
5525 pins = "gpio7 5174 pins = "gpio79";
5526 function = "q 5175 function = "qup2_se3";
5527 drive-strengt 5176 drive-strength = <6>;
5528 bias-disable; 5177 bias-disable;
5529 }; 5178 };
5530 5179
5531 qup_spi19_data_clk: q 5180 qup_spi19_data_clk: qup-spi19-data-clk-state {
5532 /* MISO, MOSI 5181 /* MISO, MOSI, CLK */
5533 pins = "gpio7 5182 pins = "gpio76", "gpio77", "gpio78";
5534 function = "q 5183 function = "qup2_se3";
5535 drive-strengt 5184 drive-strength = <6>;
5536 bias-disable; 5185 bias-disable;
5537 }; 5186 };
5538 5187
5539 qup_spi20_cs: qup-spi 5188 qup_spi20_cs: qup-spi20-cs-state {
5540 pins = "gpio8 5189 pins = "gpio83";
5541 function = "q 5190 function = "qup2_se4";
5542 drive-strengt 5191 drive-strength = <6>;
5543 bias-disable; 5192 bias-disable;
5544 }; 5193 };
5545 5194
5546 qup_spi20_data_clk: q 5195 qup_spi20_data_clk: qup-spi20-data-clk-state {
5547 /* MISO, MOSI 5196 /* MISO, MOSI, CLK */
5548 pins = "gpio8 5197 pins = "gpio80", "gpio81", "gpio82";
5549 function = "q 5198 function = "qup2_se4";
5550 drive-strengt 5199 drive-strength = <6>;
5551 bias-disable; 5200 bias-disable;
5552 }; 5201 };
5553 5202
5554 qup_spi21_cs: qup-spi 5203 qup_spi21_cs: qup-spi21-cs-state {
5555 pins = "gpio8 5204 pins = "gpio87";
5556 function = "q 5205 function = "qup2_se5";
5557 drive-strengt 5206 drive-strength = <6>;
5558 bias-disable; 5207 bias-disable;
5559 }; 5208 };
5560 5209
5561 qup_spi21_data_clk: q 5210 qup_spi21_data_clk: qup-spi21-data-clk-state {
5562 /* MISO, MOSI 5211 /* MISO, MOSI, CLK */
5563 pins = "gpio8 5212 pins = "gpio84", "gpio85", "gpio86";
5564 function = "q 5213 function = "qup2_se5";
5565 drive-strengt 5214 drive-strength = <6>;
5566 bias-disable; 5215 bias-disable;
5567 }; 5216 };
5568 5217
5569 qup_spi22_cs: qup-spi 5218 qup_spi22_cs: qup-spi22-cs-state {
5570 pins = "gpio9 5219 pins = "gpio91";
5571 function = "q 5220 function = "qup2_se6";
5572 drive-strengt 5221 drive-strength = <6>;
5573 bias-disable; 5222 bias-disable;
5574 }; 5223 };
5575 5224
5576 qup_spi22_data_clk: q 5225 qup_spi22_data_clk: qup-spi22-data-clk-state {
5577 /* MISO, MOSI 5226 /* MISO, MOSI, CLK */
5578 pins = "gpio8 5227 pins = "gpio88", "gpio89", "gpio90";
5579 function = "q 5228 function = "qup2_se6";
5580 drive-strengt 5229 drive-strength = <6>;
5581 bias-disable; 5230 bias-disable;
5582 }; 5231 };
5583 5232
5584 qup_spi23_cs: qup-spi 5233 qup_spi23_cs: qup-spi23-cs-state {
5585 pins = "gpio8 5234 pins = "gpio85";
5586 function = "q 5235 function = "qup2_se7";
5587 drive-strengt 5236 drive-strength = <6>;
5588 bias-disable; 5237 bias-disable;
5589 }; 5238 };
5590 5239
5591 qup_spi23_data_clk: q 5240 qup_spi23_data_clk: qup-spi23-data-clk-state {
5592 /* MISO, MOSI 5241 /* MISO, MOSI, CLK */
5593 pins = "gpio8 5242 pins = "gpio86", "gpio87", "gpio84";
5594 function = "q 5243 function = "qup2_se7";
5595 drive-strengt 5244 drive-strength = <6>;
5596 bias-disable; 5245 bias-disable;
5597 }; 5246 };
5598 5247
5599 qup_uart2_default: qu <<
5600 cts-pins { <<
5601 pins <<
5602 funct <<
5603 drive <<
5604 bias- <<
5605 }; <<
5606 <<
5607 rts-pins { <<
5608 pins <<
5609 funct <<
5610 drive <<
5611 bias- <<
5612 }; <<
5613 <<
5614 tx-pins { <<
5615 pins <<
5616 funct <<
5617 drive <<
5618 bias- <<
5619 }; <<
5620 <<
5621 rx-pins { <<
5622 pins <<
5623 funct <<
5624 drive <<
5625 bias- <<
5626 }; <<
5627 }; <<
5628 <<
5629 qup_uart21_default: q 5248 qup_uart21_default: qup-uart21-default-state {
5630 tx-pins { !! 5249 /* TX, RX */
5631 pins !! 5250 pins = "gpio86", "gpio87";
5632 funct !! 5251 function = "qup2_se5";
5633 drive !! 5252 drive-strength = <2>;
5634 bias- !! 5253 bias-disable;
5635 }; <<
5636 <<
5637 rx-pins { <<
5638 pins <<
5639 funct <<
5640 drive <<
5641 bias- <<
5642 }; <<
5643 }; 5254 };
5644 }; 5255 };
5645 5256
5646 apps_smmu: iommu@15000000 { 5257 apps_smmu: iommu@15000000 {
5647 compatible = "qcom,x1 5258 compatible = "qcom,x1e80100-smmu-500", "qcom,smmu-500", "arm,mmu-500";
5648 reg = <0 0x15000000 0 5259 reg = <0 0x15000000 0 0x100000>;
5649 5260
5650 interrupts = <GIC_SPI 5261 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
5651 <GIC_SPI 5262 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
5652 <GIC_SPI 5263 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
5653 <GIC_SPI 5264 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
5654 <GIC_SPI 5265 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
5655 <GIC_SPI 5266 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
5656 <GIC_SPI 5267 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
5657 <GIC_SPI 5268 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
5658 <GIC_SPI 5269 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
5659 <GIC_SPI 5270 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
5660 <GIC_SPI 5271 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
5661 <GIC_SPI 5272 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
5662 <GIC_SPI 5273 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
5663 <GIC_SPI 5274 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
5664 <GIC_SPI 5275 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
5665 <GIC_SPI 5276 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
5666 <GIC_SPI 5277 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
5667 <GIC_SPI 5278 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
5668 <GIC_SPI 5279 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
5669 <GIC_SPI 5280 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
5670 <GIC_SPI 5281 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
5671 <GIC_SPI 5282 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
5672 <GIC_SPI 5283 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
5673 <GIC_SPI 5284 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
5674 <GIC_SPI 5285 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
5675 <GIC_SPI 5286 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
5676 <GIC_SPI 5287 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
5677 <GIC_SPI 5288 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
5678 <GIC_SPI 5289 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
5679 <GIC_SPI 5290 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
5680 <GIC_SPI 5291 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
5681 <GIC_SPI 5292 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
5682 <GIC_SPI 5293 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
5683 <GIC_SPI 5294 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
5684 <GIC_SPI 5295 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
5685 <GIC_SPI 5296 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
5686 <GIC_SPI 5297 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
5687 <GIC_SPI 5298 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
5688 <GIC_SPI 5299 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
5689 <GIC_SPI 5300 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
5690 <GIC_SPI 5301 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
5691 <GIC_SPI 5302 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
5692 <GIC_SPI 5303 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
5693 <GIC_SPI 5304 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
5694 <GIC_SPI 5305 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
5695 <GIC_SPI 5306 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
5696 <GIC_SPI 5307 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
5697 <GIC_SPI 5308 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
5698 <GIC_SPI 5309 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
5699 <GIC_SPI 5310 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
5700 <GIC_SPI 5311 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
5701 <GIC_SPI 5312 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
5702 <GIC_SPI 5313 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
5703 <GIC_SPI 5314 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
5704 <GIC_SPI 5315 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
5705 <GIC_SPI 5316 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
5706 <GIC_SPI 5317 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
5707 <GIC_SPI 5318 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
5708 <GIC_SPI 5319 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
5709 <GIC_SPI 5320 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
5710 <GIC_SPI 5321 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
5711 <GIC_SPI 5322 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
5712 <GIC_SPI 5323 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
5713 <GIC_SPI 5324 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
5714 <GIC_SPI 5325 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
5715 <GIC_SPI 5326 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
5716 <GIC_SPI 5327 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
5717 <GIC_SPI 5328 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
5718 <GIC_SPI 5329 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
5719 <GIC_SPI 5330 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
5720 <GIC_SPI 5331 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
5721 <GIC_SPI 5332 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
5722 <GIC_SPI 5333 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
5723 <GIC_SPI 5334 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
5724 <GIC_SPI 5335 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
5725 <GIC_SPI 5336 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
5726 <GIC_SPI 5337 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
5727 <GIC_SPI 5338 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
5728 <GIC_SPI 5339 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
5729 <GIC_SPI 5340 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
5730 <GIC_SPI 5341 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
5731 <GIC_SPI 5342 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
5732 <GIC_SPI 5343 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
5733 <GIC_SPI 5344 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
5734 <GIC_SPI 5345 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
5735 <GIC_SPI 5346 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
5736 <GIC_SPI 5347 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
5737 <GIC_SPI 5348 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
5738 <GIC_SPI 5349 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
5739 <GIC_SPI 5350 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
5740 <GIC_SPI 5351 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
5741 <GIC_SPI 5352 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
5742 <GIC_SPI 5353 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
5743 <GIC_SPI 5354 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
5744 <GIC_SPI 5355 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
5745 <GIC_SPI 5356 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
5746 <GIC_SPI 5357 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>;
5747 5358
5748 #iommu-cells = <2>; 5359 #iommu-cells = <2>;
5749 #global-interrupts = 5360 #global-interrupts = <1>;
5750 }; 5361 };
5751 5362
5752 intc: interrupt-controller@17 5363 intc: interrupt-controller@17000000 {
5753 compatible = "arm,gic 5364 compatible = "arm,gic-v3";
5754 reg = <0 0x17000000 0 5365 reg = <0 0x17000000 0 0x10000>, /* GICD */
5755 <0 0x17080000 0 5366 <0 0x17080000 0 0x480000>; /* GICR * 12 */
5756 5367
5757 interrupts = <GIC_PPI 5368 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
5758 5369
5759 #interrupt-cells = <3 5370 #interrupt-cells = <3>;
5760 interrupt-controller; 5371 interrupt-controller;
5761 5372
5762 #redistributor-region 5373 #redistributor-regions = <1>;
5763 redistributor-stride 5374 redistributor-stride = <0x0 0x40000>;
5764 5375
5765 #address-cells = <2>; 5376 #address-cells = <2>;
5766 #size-cells = <2>; 5377 #size-cells = <2>;
5767 ranges; 5378 ranges;
5768 5379
5769 gic_its: msi-controll 5380 gic_its: msi-controller@17040000 {
5770 compatible = 5381 compatible = "arm,gic-v3-its";
5771 reg = <0 0x17 5382 reg = <0 0x17040000 0 0x40000>;
5772 5383
5773 msi-controlle 5384 msi-controller;
5774 #msi-cells = 5385 #msi-cells = <1>;
5775 5386
5776 status = "dis 5387 status = "disabled";
5777 }; 5388 };
5778 }; 5389 };
5779 5390
5780 apps_rsc: rsc@17500000 { 5391 apps_rsc: rsc@17500000 {
5781 compatible = "qcom,rp 5392 compatible = "qcom,rpmh-rsc";
5782 reg = <0 0x17500000 0 5393 reg = <0 0x17500000 0 0x10000>,
5783 <0 0x17510000 0 5394 <0 0x17510000 0 0x10000>,
5784 <0 0x17520000 0 5395 <0 0x17520000 0 0x10000>;
5785 reg-names = "drv-0", 5396 reg-names = "drv-0", "drv-1", "drv-2";
5786 5397
5787 interrupts = <GIC_SPI 5398 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
5788 <GIC_SPI 5399 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
5789 <GIC_SPI 5400 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
5790 qcom,tcs-offset = <0x 5401 qcom,tcs-offset = <0xd00>;
5791 qcom,drv-id = <2>; 5402 qcom,drv-id = <2>;
5792 qcom,tcs-config = <AC 5403 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
5793 <WA 5404 <WAKE_TCS 2>, <CONTROL_TCS 0>;
5794 5405
5795 label = "apps_rsc"; 5406 label = "apps_rsc";
5796 power-domains = <&SYS 5407 power-domains = <&SYSTEM_PD>;
5797 5408
5798 apps_bcm_voter: bcm-v 5409 apps_bcm_voter: bcm-voter {
5799 compatible = 5410 compatible = "qcom,bcm-voter";
5800 }; 5411 };
5801 5412
5802 rpmhcc: clock-control 5413 rpmhcc: clock-controller {
5803 compatible = 5414 compatible = "qcom,x1e80100-rpmh-clk";
5804 5415
5805 clocks = <&xo 5416 clocks = <&xo_board>;
5806 clock-names = 5417 clock-names = "xo";
5807 5418
5808 #clock-cells 5419 #clock-cells = <1>;
5809 }; 5420 };
5810 5421
5811 rpmhpd: power-control 5422 rpmhpd: power-controller {
5812 compatible = 5423 compatible = "qcom,x1e80100-rpmhpd";
5813 5424
5814 operating-poi 5425 operating-points-v2 = <&rpmhpd_opp_table>;
5815 5426
5816 #power-domain 5427 #power-domain-cells = <1>;
5817 5428
5818 rpmhpd_opp_ta 5429 rpmhpd_opp_table: opp-table {
5819 compa 5430 compatible = "operating-points-v2";
5820 5431
5821 rpmhp 5432 rpmhpd_opp_ret: opp-16 {
5822 5433 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
5823 }; 5434 };
5824 5435
5825 rpmhp 5436 rpmhpd_opp_min_svs: opp-48 {
5826 5437 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
5827 }; 5438 };
5828 5439
5829 rpmhp 5440 rpmhpd_opp_low_svs_d2: opp-52 {
5830 5441 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
5831 }; 5442 };
5832 5443
5833 rpmhp 5444 rpmhpd_opp_low_svs_d1: opp-56 {
5834 5445 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
5835 }; 5446 };
5836 5447
5837 rpmhp 5448 rpmhpd_opp_low_svs_d0: opp-60 {
5838 5449 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
5839 }; 5450 };
5840 5451
5841 rpmhp 5452 rpmhpd_opp_low_svs: opp-64 {
5842 5453 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
5843 }; 5454 };
5844 5455
5845 rpmhp 5456 rpmhpd_opp_low_svs_l1: opp-80 {
5846 5457 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
5847 }; 5458 };
5848 5459
5849 rpmhp 5460 rpmhpd_opp_svs: opp-128 {
5850 5461 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
5851 }; 5462 };
5852 5463
5853 rpmhp 5464 rpmhpd_opp_svs_l0: opp-144 {
5854 5465 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
5855 }; 5466 };
5856 5467
5857 rpmhp 5468 rpmhpd_opp_svs_l1: opp-192 {
5858 5469 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
5859 }; 5470 };
5860 5471
5861 rpmhp 5472 rpmhpd_opp_nom: opp-256 {
5862 5473 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
5863 }; 5474 };
5864 5475
5865 rpmhp 5476 rpmhpd_opp_nom_l1: opp-320 {
5866 5477 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
5867 }; 5478 };
5868 5479
5869 rpmhp 5480 rpmhpd_opp_nom_l2: opp-336 {
5870 5481 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
5871 }; 5482 };
5872 5483
5873 rpmhp 5484 rpmhpd_opp_turbo: opp-384 {
5874 5485 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
5875 }; 5486 };
5876 5487
5877 rpmhp 5488 rpmhpd_opp_turbo_l1: opp-416 {
5878 5489 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
5879 }; 5490 };
5880 }; 5491 };
5881 }; 5492 };
5882 }; 5493 };
5883 5494
5884 timer@17800000 { 5495 timer@17800000 {
5885 compatible = "arm,arm 5496 compatible = "arm,armv7-timer-mem";
5886 reg = <0 0x17800000 0 5497 reg = <0 0x17800000 0 0x1000>;
5887 5498
5888 #address-cells = <2>; 5499 #address-cells = <2>;
5889 #size-cells = <1>; 5500 #size-cells = <1>;
5890 ranges = <0 0 0 0 0x2 5501 ranges = <0 0 0 0 0x20000000>;
5891 5502
5892 frame@17801000 { 5503 frame@17801000 {
5893 reg = <0 0x17 5504 reg = <0 0x17801000 0x1000>,
5894 <0 0x17 5505 <0 0x17802000 0x1000>;
5895 5506
5896 interrupts = 5507 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
5897 5508 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
5898 5509
5899 frame-number 5510 frame-number = <0>;
5900 }; 5511 };
5901 5512
5902 frame@17803000 { 5513 frame@17803000 {
5903 reg = <0 0x17 5514 reg = <0 0x17803000 0x1000>;
5904 5515
5905 interrupts = 5516 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
5906 5517
5907 frame-number 5518 frame-number = <1>;
5908 5519
5909 status = "dis 5520 status = "disabled";
5910 }; 5521 };
5911 5522
5912 frame@17805000 { 5523 frame@17805000 {
5913 reg = <0 0x17 5524 reg = <0 0x17805000 0x1000>;
5914 5525
5915 interrupts = 5526 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
5916 5527
5917 frame-number 5528 frame-number = <2>;
5918 5529
5919 status = "dis 5530 status = "disabled";
5920 }; 5531 };
5921 5532
5922 frame@17807000 { 5533 frame@17807000 {
5923 reg = <0 0x17 5534 reg = <0 0x17807000 0x1000>;
5924 5535
5925 interrupts = 5536 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
5926 5537
5927 frame-number 5538 frame-number = <3>;
5928 5539
5929 status = "dis 5540 status = "disabled";
5930 }; 5541 };
5931 5542
5932 frame@17809000 { 5543 frame@17809000 {
5933 reg = <0 0x17 5544 reg = <0 0x17809000 0x1000>;
5934 5545
5935 interrupts = 5546 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
5936 5547
5937 frame-number 5548 frame-number = <4>;
5938 5549
5939 status = "dis 5550 status = "disabled";
5940 }; 5551 };
5941 5552
5942 frame@1780b000 { 5553 frame@1780b000 {
5943 reg = <0 0x17 5554 reg = <0 0x1780b000 0x1000>;
5944 5555
5945 interrupts = 5556 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
5946 5557
5947 frame-number 5558 frame-number = <5>;
5948 5559
5949 status = "dis 5560 status = "disabled";
5950 }; 5561 };
5951 5562
5952 frame@1780d000 { 5563 frame@1780d000 {
5953 reg = <0 0x17 5564 reg = <0 0x1780d000 0x1000>;
5954 5565
5955 interrupts = 5566 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
5956 5567
5957 frame-number 5568 frame-number = <6>;
5958 5569
5959 status = "dis 5570 status = "disabled";
5960 }; 5571 };
5961 }; 5572 };
5962 5573
5963 pmu@24091000 { 5574 pmu@24091000 {
5964 compatible = "qcom,x1 5575 compatible = "qcom,x1e80100-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
5965 reg = <0 0x24091000 0 5576 reg = <0 0x24091000 0 0x1000>;
5966 5577
5967 interrupts = <GIC_SPI 5578 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
5968 5579
5969 interconnects = <&mc_ 5580 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
5970 &mc_ 5581 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>;
5971 5582
5972 operating-points-v2 = 5583 operating-points-v2 = <&llcc_bwmon_opp_table>;
5973 5584
5974 llcc_bwmon_opp_table: 5585 llcc_bwmon_opp_table: opp-table {
5975 compatible = 5586 compatible = "operating-points-v2";
5976 5587
5977 opp-0 { 5588 opp-0 {
5978 opp-p 5589 opp-peak-kBps = <800000>;
5979 }; 5590 };
5980 5591
5981 opp-1 { 5592 opp-1 {
5982 opp-p 5593 opp-peak-kBps = <2188000>;
5983 }; 5594 };
5984 5595
5985 opp-2 { 5596 opp-2 {
5986 opp-p 5597 opp-peak-kBps = <3072000>;
5987 }; 5598 };
5988 5599
5989 opp-3 { 5600 opp-3 {
5990 opp-p 5601 opp-peak-kBps = <6220800>;
5991 }; 5602 };
5992 5603
5993 opp-4 { 5604 opp-4 {
5994 opp-p 5605 opp-peak-kBps = <6835200>;
5995 }; 5606 };
5996 5607
5997 opp-5 { 5608 opp-5 {
5998 opp-p 5609 opp-peak-kBps = <8371200>;
5999 }; 5610 };
6000 5611
6001 opp-6 { 5612 opp-6 {
6002 opp-p 5613 opp-peak-kBps = <10944000>;
6003 }; 5614 };
6004 5615
6005 opp-7 { 5616 opp-7 {
6006 opp-p 5617 opp-peak-kBps = <12748800>;
6007 }; 5618 };
6008 5619
6009 opp-8 { 5620 opp-8 {
6010 opp-p 5621 opp-peak-kBps = <14745600>;
6011 }; 5622 };
6012 5623
6013 opp-9 { 5624 opp-9 {
6014 opp-p 5625 opp-peak-kBps = <16896000>;
6015 }; 5626 };
6016 }; 5627 };
6017 }; 5628 };
6018 5629
6019 /* cluster0 */ 5630 /* cluster0 */
6020 pmu@240b3400 { 5631 pmu@240b3400 {
6021 compatible = "qcom,x1 5632 compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon";
6022 reg = <0 0x240b3400 0 5633 reg = <0 0x240b3400 0 0x600>;
6023 5634
6024 interrupts = <GIC_SPI 5635 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
6025 5636
6026 interconnects = <&gem 5637 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
6027 &gem 5638 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>;
6028 5639
6029 operating-points-v2 = 5640 operating-points-v2 = <&cpu_bwmon_opp_table>;
6030 5641
6031 cpu_bwmon_opp_table: 5642 cpu_bwmon_opp_table: opp-table {
6032 compatible = 5643 compatible = "operating-points-v2";
6033 5644
6034 opp-0 { 5645 opp-0 {
6035 opp-p 5646 opp-peak-kBps = <4800000>;
6036 }; 5647 };
6037 5648
6038 opp-1 { 5649 opp-1 {
6039 opp-p 5650 opp-peak-kBps = <7464000>;
6040 }; 5651 };
6041 5652
6042 opp-2 { 5653 opp-2 {
6043 opp-p 5654 opp-peak-kBps = <9600000>;
6044 }; 5655 };
6045 5656
6046 opp-3 { 5657 opp-3 {
6047 opp-p 5658 opp-peak-kBps = <12896000>;
6048 }; 5659 };
6049 5660
6050 opp-4 { 5661 opp-4 {
6051 opp-p 5662 opp-peak-kBps = <14928000>;
6052 }; 5663 };
6053 5664
6054 opp-5 { 5665 opp-5 {
6055 opp-p 5666 opp-peak-kBps = <17064000>;
6056 }; 5667 };
6057 }; 5668 };
6058 }; 5669 };
6059 5670
6060 /* cluster2 */ 5671 /* cluster2 */
6061 pmu@240b5400 { 5672 pmu@240b5400 {
6062 compatible = "qcom,x1 5673 compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon";
6063 reg = <0 0x240b5400 0 5674 reg = <0 0x240b5400 0 0x600>;
6064 5675
6065 interrupts = <GIC_SPI 5676 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
6066 5677
6067 interconnects = <&gem 5678 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
6068 &gem 5679 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>;
6069 5680
6070 operating-points-v2 = 5681 operating-points-v2 = <&cpu_bwmon_opp_table>;
6071 }; 5682 };
6072 5683
6073 /* cluster1 */ 5684 /* cluster1 */
6074 pmu@240b6400 { 5685 pmu@240b6400 {
6075 compatible = "qcom,x1 5686 compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon";
6076 reg = <0 0x240b6400 0 5687 reg = <0 0x240b6400 0 0x600>;
6077 5688
6078 interrupts = <GIC_SPI 5689 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
6079 5690
6080 interconnects = <&gem 5691 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
6081 &gem 5692 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>;
6082 5693
6083 operating-points-v2 = 5694 operating-points-v2 = <&cpu_bwmon_opp_table>;
6084 }; 5695 };
6085 5696
6086 system-cache-controller@25000 5697 system-cache-controller@25000000 {
6087 compatible = "qcom,x1 5698 compatible = "qcom,x1e80100-llcc";
6088 reg = <0 0x25000000 0 5699 reg = <0 0x25000000 0 0x200000>,
6089 <0 0x25200000 0 5700 <0 0x25200000 0 0x200000>,
6090 <0 0x25400000 0 5701 <0 0x25400000 0 0x200000>,
6091 <0 0x25600000 0 5702 <0 0x25600000 0 0x200000>,
6092 <0 0x25800000 0 5703 <0 0x25800000 0 0x200000>,
6093 <0 0x25a00000 0 5704 <0 0x25a00000 0 0x200000>,
6094 <0 0x25c00000 0 5705 <0 0x25c00000 0 0x200000>,
6095 <0 0x25e00000 0 5706 <0 0x25e00000 0 0x200000>,
6096 <0 0x26000000 0 5707 <0 0x26000000 0 0x200000>,
6097 <0 0x26200000 0 5708 <0 0x26200000 0 0x200000>;
6098 reg-names = "llcc0_ba 5709 reg-names = "llcc0_base",
6099 "llcc1_ba 5710 "llcc1_base",
6100 "llcc2_ba 5711 "llcc2_base",
6101 "llcc3_ba 5712 "llcc3_base",
6102 "llcc4_ba 5713 "llcc4_base",
6103 "llcc5_ba 5714 "llcc5_base",
6104 "llcc6_ba 5715 "llcc6_base",
6105 "llcc7_ba 5716 "llcc7_base",
6106 "llcc_bro 5717 "llcc_broadcast_base",
6107 "llcc_bro 5718 "llcc_broadcast_and_base";
6108 interrupts = <GIC_SPI 5719 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
6109 }; 5720 };
6110 5721
6111 remoteproc_adsp: remoteproc@3 5722 remoteproc_adsp: remoteproc@30000000 {
6112 compatible = "qcom,x1 5723 compatible = "qcom,x1e80100-adsp-pas";
6113 reg = <0 0x30000000 0 5724 reg = <0 0x30000000 0 0x100>;
6114 5725
6115 interrupts-extended = 5726 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
6116 5727 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
6117 5728 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
6118 5729 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
6119 5730 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
6120 interrupt-names = "wd 5731 interrupt-names = "wdog",
6121 "fa 5732 "fatal",
6122 "re 5733 "ready",
6123 "ha 5734 "handover",
6124 "st 5735 "stop-ack";
6125 5736
6126 clocks = <&rpmhcc RPM 5737 clocks = <&rpmhcc RPMH_CXO_CLK>;
6127 clock-names = "xo"; 5738 clock-names = "xo";
6128 5739
6129 power-domains = <&rpm 5740 power-domains = <&rpmhpd RPMHPD_LCX>,
6130 <&rpm 5741 <&rpmhpd RPMHPD_LMX>;
6131 power-domain-names = 5742 power-domain-names = "lcx",
6132 5743 "lmx";
6133 5744
6134 interconnects = <&lpa 5745 interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS
6135 &mc_ 5746 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
6136 5747
6137 memory-region = <&ads 5748 memory-region = <&adspslpi_mem>,
6138 <&q6_ 5749 <&q6_adsp_dtb_mem>;
6139 5750
6140 qcom,qmp = <&aoss_qmp 5751 qcom,qmp = <&aoss_qmp>;
6141 5752
6142 qcom,smem-states = <& 5753 qcom,smem-states = <&smp2p_adsp_out 0>;
6143 qcom,smem-state-names 5754 qcom,smem-state-names = "stop";
6144 5755
6145 status = "disabled"; 5756 status = "disabled";
6146 5757
6147 glink-edge { 5758 glink-edge {
6148 interrupts-ex 5759 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
6149 5760 IPCC_MPROC_SIGNAL_GLINK_QMP
6150 5761 IRQ_TYPE_EDGE_RISING>;
6151 mboxes = <&ip 5762 mboxes = <&ipcc IPCC_CLIENT_LPASS
6152 5763 IPCC_MPROC_SIGNAL_GLINK_QMP>;
6153 5764
6154 label = "lpas 5765 label = "lpass";
6155 qcom,remote-p 5766 qcom,remote-pid = <2>;
6156 5767
6157 fastrpc { 5768 fastrpc {
6158 compa 5769 compatible = "qcom,fastrpc";
6159 qcom, 5770 qcom,glink-channels = "fastrpcglink-apps-dsp";
6160 label 5771 label = "adsp";
6161 qcom, 5772 qcom,non-secure-domain;
6162 #addr 5773 #address-cells = <1>;
6163 #size 5774 #size-cells = <0>;
6164 5775
6165 compu 5776 compute-cb@3 {
6166 5777 compatible = "qcom,fastrpc-compute-cb";
6167 5778 reg = <3>;
6168 5779 iommus = <&apps_smmu 0x1003 0x80>,
6169 5780 <&apps_smmu 0x1063 0x0>;
6170 5781 dma-coherent;
6171 }; 5782 };
6172 5783
6173 compu 5784 compute-cb@4 {
6174 5785 compatible = "qcom,fastrpc-compute-cb";
6175 5786 reg = <4>;
6176 5787 iommus = <&apps_smmu 0x1004 0x80>,
6177 5788 <&apps_smmu 0x1064 0x0>;
6178 5789 dma-coherent;
6179 }; 5790 };
6180 5791
6181 compu 5792 compute-cb@5 {
6182 5793 compatible = "qcom,fastrpc-compute-cb";
6183 5794 reg = <5>;
6184 5795 iommus = <&apps_smmu 0x1005 0x80>,
6185 5796 <&apps_smmu 0x1065 0x0>;
6186 5797 dma-coherent;
6187 }; 5798 };
6188 5799
6189 compu 5800 compute-cb@6 {
6190 5801 compatible = "qcom,fastrpc-compute-cb";
6191 5802 reg = <6>;
6192 5803 iommus = <&apps_smmu 0x1006 0x80>,
6193 5804 <&apps_smmu 0x1066 0x0>;
6194 5805 dma-coherent;
6195 }; 5806 };
6196 5807
6197 compu 5808 compute-cb@7 {
6198 5809 compatible = "qcom,fastrpc-compute-cb";
6199 5810 reg = <7>;
6200 5811 iommus = <&apps_smmu 0x1007 0x80>,
6201 5812 <&apps_smmu 0x1067 0x0>;
6202 5813 dma-coherent;
6203 }; 5814 };
6204 }; 5815 };
6205 5816
6206 gpr { 5817 gpr {
6207 compa 5818 compatible = "qcom,gpr";
6208 qcom, 5819 qcom,glink-channels = "adsp_apps";
6209 qcom, 5820 qcom,domain = <GPR_DOMAIN_ID_ADSP>;
6210 qcom, 5821 qcom,intents = <512 20>;
6211 #addr 5822 #address-cells = <1>;
6212 #size 5823 #size-cells = <0>;
6213 5824
6214 q6apm 5825 q6apm: service@1 {
6215 5826 compatible = "qcom,q6apm";
6216 5827 reg = <GPR_APM_MODULE_IID>;
6217 5828 #sound-dai-cells = <0>;
6218 5829 qcom,protection-domain = "avs/audio",
6219 5830 "msm/adsp/audio_pd";
6220 5831
6221 5832 q6apmbedai: bedais {
6222 5833 compatible = "qcom,q6apm-lpass-dais";
6223 5834 #sound-dai-cells = <1>;
6224 5835 };
6225 5836
6226 5837 q6apmdai: dais {
6227 5838 compatible = "qcom,q6apm-dais";
6228 5839 iommus = <&apps_smmu 0x1001 0x80>,
6229 5840 <&apps_smmu 0x1061 0x0>;
6230 5841 };
6231 }; 5842 };
6232 5843
6233 q6prm 5844 q6prm: service@2 {
6234 5845 compatible = "qcom,q6prm";
6235 5846 reg = <GPR_PRM_MODULE_IID>;
6236 5847 qcom,protection-domain = "avs/audio",
6237 5848 "msm/adsp/audio_pd";
6238 5849
6239 5850 q6prmcc: clock-controller {
6240 5851 compatible = "qcom,q6prm-lpass-clocks";
6241 5852 #clock-cells = <2>;
6242 5853 };
6243 }; 5854 };
6244 }; 5855 };
6245 }; 5856 };
6246 }; 5857 };
6247 5858
6248 remoteproc_cdsp: remoteproc@3 5859 remoteproc_cdsp: remoteproc@32300000 {
6249 compatible = "qcom,x1 5860 compatible = "qcom,x1e80100-cdsp-pas";
6250 reg = <0 0x32300000 0 5861 reg = <0 0x32300000 0 0x1400000>;
6251 5862
6252 interrupts-extended = 5863 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
6253 5864 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
6254 5865 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
6255 5866 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
6256 5867 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
6257 interrupt-names = "wd 5868 interrupt-names = "wdog",
6258 "fa 5869 "fatal",
6259 "re 5870 "ready",
6260 "ha 5871 "handover",
6261 "st 5872 "stop-ack";
6262 5873
6263 clocks = <&rpmhcc RPM 5874 clocks = <&rpmhcc RPMH_CXO_CLK>;
6264 clock-names = "xo"; 5875 clock-names = "xo";
6265 5876
6266 power-domains = <&rpm 5877 power-domains = <&rpmhpd RPMHPD_CX>,
6267 <&rpm 5878 <&rpmhpd RPMHPD_MXC>,
6268 <&rpm 5879 <&rpmhpd RPMHPD_NSP>;
6269 power-domain-names = 5880 power-domain-names = "cx",
6270 5881 "mxc",
6271 5882 "nsp";
6272 5883
6273 interconnects = <&nsp 5884 interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS
6274 &mc_ 5885 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
6275 5886
6276 memory-region = <&cds 5887 memory-region = <&cdsp_mem>,
6277 <&q6_ 5888 <&q6_cdsp_dtb_mem>;
6278 5889
6279 qcom,qmp = <&aoss_qmp 5890 qcom,qmp = <&aoss_qmp>;
6280 5891
6281 qcom,smem-states = <& 5892 qcom,smem-states = <&smp2p_cdsp_out 0>;
6282 qcom,smem-state-names 5893 qcom,smem-state-names = "stop";
6283 5894
6284 status = "disabled"; 5895 status = "disabled";
6285 5896
6286 glink-edge { 5897 glink-edge {
6287 interrupts-ex 5898 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
6288 5899 IPCC_MPROC_SIGNAL_GLINK_QMP
6289 5900 IRQ_TYPE_EDGE_RISING>;
6290 mboxes = <&ip 5901 mboxes = <&ipcc IPCC_CLIENT_CDSP
6291 5902 IPCC_MPROC_SIGNAL_GLINK_QMP>;
6292 5903
6293 label = "cdsp 5904 label = "cdsp";
6294 qcom,remote-p 5905 qcom,remote-pid = <5>;
6295 5906
6296 fastrpc { 5907 fastrpc {
6297 compa 5908 compatible = "qcom,fastrpc";
6298 qcom, 5909 qcom,glink-channels = "fastrpcglink-apps-dsp";
6299 label 5910 label = "cdsp";
6300 qcom, 5911 qcom,non-secure-domain;
6301 #addr 5912 #address-cells = <1>;
6302 #size 5913 #size-cells = <0>;
6303 5914
6304 compu 5915 compute-cb@1 {
6305 5916 compatible = "qcom,fastrpc-compute-cb";
6306 5917 reg = <1>;
6307 5918 iommus = <&apps_smmu 0x0c01 0x20>;
6308 5919 dma-coherent;
6309 }; 5920 };
6310 5921
6311 compu 5922 compute-cb@2 {
6312 5923 compatible = "qcom,fastrpc-compute-cb";
6313 5924 reg = <2>;
6314 5925 iommus = <&apps_smmu 0x0c02 0x20>;
6315 5926 dma-coherent;
6316 }; 5927 };
6317 5928
6318 compu 5929 compute-cb@3 {
6319 5930 compatible = "qcom,fastrpc-compute-cb";
6320 5931 reg = <3>;
6321 5932 iommus = <&apps_smmu 0x0c03 0x20>;
6322 5933 dma-coherent;
6323 }; 5934 };
6324 5935
6325 compu 5936 compute-cb@4 {
6326 5937 compatible = "qcom,fastrpc-compute-cb";
6327 5938 reg = <4>;
6328 5939 iommus = <&apps_smmu 0x0c04 0x20>;
6329 5940 dma-coherent;
6330 }; 5941 };
6331 5942
6332 compu 5943 compute-cb@5 {
6333 5944 compatible = "qcom,fastrpc-compute-cb";
6334 5945 reg = <5>;
6335 5946 iommus = <&apps_smmu 0x0c05 0x20>;
6336 5947 dma-coherent;
6337 }; 5948 };
6338 5949
6339 compu 5950 compute-cb@6 {
6340 5951 compatible = "qcom,fastrpc-compute-cb";
6341 5952 reg = <6>;
6342 5953 iommus = <&apps_smmu 0x0c06 0x20>;
6343 5954 dma-coherent;
6344 }; 5955 };
6345 5956
6346 compu 5957 compute-cb@7 {
6347 5958 compatible = "qcom,fastrpc-compute-cb";
6348 5959 reg = <7>;
6349 5960 iommus = <&apps_smmu 0x0c07 0x20>;
6350 5961 dma-coherent;
6351 }; 5962 };
6352 5963
6353 compu 5964 compute-cb@8 {
6354 5965 compatible = "qcom,fastrpc-compute-cb";
6355 5966 reg = <8>;
6356 5967 iommus = <&apps_smmu 0x0c08 0x20>;
6357 5968 dma-coherent;
6358 }; 5969 };
6359 5970
6360 /* no 5971 /* note: compute-cb@9 is secure */
6361 5972
6362 compu 5973 compute-cb@10 {
6363 5974 compatible = "qcom,fastrpc-compute-cb";
6364 5975 reg = <10>;
6365 5976 iommus = <&apps_smmu 0x0c0c 0x20>;
6366 5977 dma-coherent;
6367 }; 5978 };
6368 5979
6369 compu 5980 compute-cb@11 {
6370 5981 compatible = "qcom,fastrpc-compute-cb";
6371 5982 reg = <11>;
6372 5983 iommus = <&apps_smmu 0x0c0d 0x20>;
6373 5984 dma-coherent;
6374 }; 5985 };
6375 5986
6376 compu 5987 compute-cb@12 {
6377 5988 compatible = "qcom,fastrpc-compute-cb";
6378 5989 reg = <12>;
6379 5990 iommus = <&apps_smmu 0x0c0e 0x20>;
6380 5991 dma-coherent;
6381 }; 5992 };
6382 5993
6383 compu 5994 compute-cb@13 {
6384 5995 compatible = "qcom,fastrpc-compute-cb";
6385 5996 reg = <13>;
6386 5997 iommus = <&apps_smmu 0x0c0f 0x20>;
6387 5998 dma-coherent;
6388 }; 5999 };
6389 }; 6000 };
6390 }; 6001 };
6391 }; 6002 };
6392 }; 6003 };
6393 6004
6394 timer { 6005 timer {
6395 compatible = "arm,armv8-timer 6006 compatible = "arm,armv8-timer";
6396 6007
6397 interrupts = <GIC_PPI 13 IRQ_ 6008 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
6398 <GIC_PPI 14 IRQ_ 6009 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
6399 <GIC_PPI 11 IRQ_ 6010 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
6400 <GIC_PPI 10 IRQ_ 6011 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
6401 }; 6012 };
6402 6013
6403 thermal-zones { 6014 thermal-zones {
6404 aoss0-thermal { 6015 aoss0-thermal {
6405 thermal-sensors = <&t 6016 thermal-sensors = <&tsens0 0>;
6406 6017
6407 trips { 6018 trips {
6408 trip-point0 { 6019 trip-point0 {
6409 tempe 6020 temperature = <90000>;
6410 hyste 6021 hysteresis = <2000>;
6411 type 6022 type = "hot";
6412 }; 6023 };
6413 6024
6414 aoss0-critica 6025 aoss0-critical {
6415 tempe 6026 temperature = <125000>;
6416 hyste 6027 hysteresis = <0>;
6417 type 6028 type = "critical";
6418 }; 6029 };
6419 }; 6030 };
6420 }; 6031 };
6421 6032
6422 cpu0-0-top-thermal { 6033 cpu0-0-top-thermal {
6423 polling-delay-passive 6034 polling-delay-passive = <250>;
6424 6035
6425 thermal-sensors = <&t 6036 thermal-sensors = <&tsens0 1>;
6426 6037
6427 trips { 6038 trips {
6428 trip-point0 { 6039 trip-point0 {
6429 tempe 6040 temperature = <90000>;
6430 hyste 6041 hysteresis = <2000>;
6431 type 6042 type = "passive";
6432 }; 6043 };
6433 6044
6434 trip-point1 { 6045 trip-point1 {
6435 tempe 6046 temperature = <95000>;
6436 hyste 6047 hysteresis = <2000>;
6437 type 6048 type = "passive";
6438 }; 6049 };
6439 6050
6440 cpu-critical 6051 cpu-critical {
6441 tempe 6052 temperature = <110000>;
6442 hyste 6053 hysteresis = <1000>;
6443 type 6054 type = "critical";
6444 }; 6055 };
6445 }; 6056 };
6446 }; 6057 };
6447 6058
6448 cpu0-0-btm-thermal { 6059 cpu0-0-btm-thermal {
6449 polling-delay-passive 6060 polling-delay-passive = <250>;
6450 6061
6451 thermal-sensors = <&t 6062 thermal-sensors = <&tsens0 2>;
6452 6063
6453 trips { 6064 trips {
6454 trip-point0 { 6065 trip-point0 {
6455 tempe 6066 temperature = <90000>;
6456 hyste 6067 hysteresis = <2000>;
6457 type 6068 type = "passive";
6458 }; 6069 };
6459 6070
6460 trip-point1 { 6071 trip-point1 {
6461 tempe 6072 temperature = <95000>;
6462 hyste 6073 hysteresis = <2000>;
6463 type 6074 type = "passive";
6464 }; 6075 };
6465 6076
6466 cpu-critical 6077 cpu-critical {
6467 tempe 6078 temperature = <110000>;
6468 hyste 6079 hysteresis = <1000>;
6469 type 6080 type = "critical";
6470 }; 6081 };
6471 }; 6082 };
6472 }; 6083 };
6473 6084
6474 cpu0-1-top-thermal { 6085 cpu0-1-top-thermal {
6475 polling-delay-passive 6086 polling-delay-passive = <250>;
6476 6087
6477 thermal-sensors = <&t 6088 thermal-sensors = <&tsens0 3>;
6478 6089
6479 trips { 6090 trips {
6480 trip-point0 { 6091 trip-point0 {
6481 tempe 6092 temperature = <90000>;
6482 hyste 6093 hysteresis = <2000>;
6483 type 6094 type = "passive";
6484 }; 6095 };
6485 6096
6486 trip-point1 { 6097 trip-point1 {
6487 tempe 6098 temperature = <95000>;
6488 hyste 6099 hysteresis = <2000>;
6489 type 6100 type = "passive";
6490 }; 6101 };
6491 6102
6492 cpu-critical 6103 cpu-critical {
6493 tempe 6104 temperature = <110000>;
6494 hyste 6105 hysteresis = <1000>;
6495 type 6106 type = "critical";
6496 }; 6107 };
6497 }; 6108 };
6498 }; 6109 };
6499 6110
6500 cpu0-1-btm-thermal { 6111 cpu0-1-btm-thermal {
6501 polling-delay-passive 6112 polling-delay-passive = <250>;
6502 6113
6503 thermal-sensors = <&t 6114 thermal-sensors = <&tsens0 4>;
6504 6115
6505 trips { 6116 trips {
6506 trip-point0 { 6117 trip-point0 {
6507 tempe 6118 temperature = <90000>;
6508 hyste 6119 hysteresis = <2000>;
6509 type 6120 type = "passive";
6510 }; 6121 };
6511 6122
6512 trip-point1 { 6123 trip-point1 {
6513 tempe 6124 temperature = <95000>;
6514 hyste 6125 hysteresis = <2000>;
6515 type 6126 type = "passive";
6516 }; 6127 };
6517 6128
6518 cpu-critical 6129 cpu-critical {
6519 tempe 6130 temperature = <110000>;
6520 hyste 6131 hysteresis = <1000>;
6521 type 6132 type = "critical";
6522 }; 6133 };
6523 }; 6134 };
6524 }; 6135 };
6525 6136
6526 cpu0-2-top-thermal { 6137 cpu0-2-top-thermal {
6527 polling-delay-passive 6138 polling-delay-passive = <250>;
6528 6139
6529 thermal-sensors = <&t 6140 thermal-sensors = <&tsens0 5>;
6530 6141
6531 trips { 6142 trips {
6532 trip-point0 { 6143 trip-point0 {
6533 tempe 6144 temperature = <90000>;
6534 hyste 6145 hysteresis = <2000>;
6535 type 6146 type = "passive";
6536 }; 6147 };
6537 6148
6538 trip-point1 { 6149 trip-point1 {
6539 tempe 6150 temperature = <95000>;
6540 hyste 6151 hysteresis = <2000>;
6541 type 6152 type = "passive";
6542 }; 6153 };
6543 6154
6544 cpu-critical 6155 cpu-critical {
6545 tempe 6156 temperature = <110000>;
6546 hyste 6157 hysteresis = <1000>;
6547 type 6158 type = "critical";
6548 }; 6159 };
6549 }; 6160 };
6550 }; 6161 };
6551 6162
6552 cpu0-2-btm-thermal { 6163 cpu0-2-btm-thermal {
6553 polling-delay-passive 6164 polling-delay-passive = <250>;
6554 6165
6555 thermal-sensors = <&t 6166 thermal-sensors = <&tsens0 6>;
6556 6167
6557 trips { 6168 trips {
6558 trip-point0 { 6169 trip-point0 {
6559 tempe 6170 temperature = <90000>;
6560 hyste 6171 hysteresis = <2000>;
6561 type 6172 type = "passive";
6562 }; 6173 };
6563 6174
6564 trip-point1 { 6175 trip-point1 {
6565 tempe 6176 temperature = <95000>;
6566 hyste 6177 hysteresis = <2000>;
6567 type 6178 type = "passive";
6568 }; 6179 };
6569 6180
6570 cpu-critical 6181 cpu-critical {
6571 tempe 6182 temperature = <110000>;
6572 hyste 6183 hysteresis = <1000>;
6573 type 6184 type = "critical";
6574 }; 6185 };
6575 }; 6186 };
6576 }; 6187 };
6577 6188
6578 cpu0-3-top-thermal { 6189 cpu0-3-top-thermal {
6579 polling-delay-passive 6190 polling-delay-passive = <250>;
6580 6191
6581 thermal-sensors = <&t 6192 thermal-sensors = <&tsens0 7>;
6582 6193
6583 trips { 6194 trips {
6584 trip-point0 { 6195 trip-point0 {
6585 tempe 6196 temperature = <90000>;
6586 hyste 6197 hysteresis = <2000>;
6587 type 6198 type = "passive";
6588 }; 6199 };
6589 6200
6590 trip-point1 { 6201 trip-point1 {
6591 tempe 6202 temperature = <95000>;
6592 hyste 6203 hysteresis = <2000>;
6593 type 6204 type = "passive";
6594 }; 6205 };
6595 6206
6596 cpu-critical 6207 cpu-critical {
6597 tempe 6208 temperature = <110000>;
6598 hyste 6209 hysteresis = <1000>;
6599 type 6210 type = "critical";
6600 }; 6211 };
6601 }; 6212 };
6602 }; 6213 };
6603 6214
6604 cpu0-3-btm-thermal { 6215 cpu0-3-btm-thermal {
6605 polling-delay-passive 6216 polling-delay-passive = <250>;
6606 6217
6607 thermal-sensors = <&t 6218 thermal-sensors = <&tsens0 8>;
6608 6219
6609 trips { 6220 trips {
6610 trip-point0 { 6221 trip-point0 {
6611 tempe 6222 temperature = <90000>;
6612 hyste 6223 hysteresis = <2000>;
6613 type 6224 type = "passive";
6614 }; 6225 };
6615 6226
6616 trip-point1 { 6227 trip-point1 {
6617 tempe 6228 temperature = <95000>;
6618 hyste 6229 hysteresis = <2000>;
6619 type 6230 type = "passive";
6620 }; 6231 };
6621 6232
6622 cpu-critical 6233 cpu-critical {
6623 tempe 6234 temperature = <110000>;
6624 hyste 6235 hysteresis = <1000>;
6625 type 6236 type = "critical";
6626 }; 6237 };
6627 }; 6238 };
6628 }; 6239 };
6629 6240
6630 cpuss0-top-thermal { 6241 cpuss0-top-thermal {
6631 thermal-sensors = <&t 6242 thermal-sensors = <&tsens0 9>;
6632 6243
6633 trips { 6244 trips {
6634 trip-point0 { 6245 trip-point0 {
6635 tempe 6246 temperature = <90000>;
6636 hyste 6247 hysteresis = <2000>;
6637 type 6248 type = "hot";
6638 }; 6249 };
6639 6250
6640 cpuss2-critic 6251 cpuss2-critical {
6641 tempe 6252 temperature = <125000>;
6642 hyste 6253 hysteresis = <0>;
6643 type 6254 type = "critical";
6644 }; 6255 };
6645 }; 6256 };
6646 }; 6257 };
6647 6258
6648 cpuss0-btm-thermal { 6259 cpuss0-btm-thermal {
6649 thermal-sensors = <&t 6260 thermal-sensors = <&tsens0 10>;
6650 6261
6651 trips { 6262 trips {
6652 trip-point0 { 6263 trip-point0 {
6653 tempe 6264 temperature = <90000>;
6654 hyste 6265 hysteresis = <2000>;
6655 type 6266 type = "hot";
6656 }; 6267 };
6657 6268
6658 cpuss2-critic 6269 cpuss2-critical {
6659 tempe 6270 temperature = <125000>;
6660 hyste 6271 hysteresis = <0>;
6661 type 6272 type = "critical";
6662 }; 6273 };
6663 }; 6274 };
6664 }; 6275 };
6665 6276
6666 mem-thermal { 6277 mem-thermal {
6667 thermal-sensors = <&t 6278 thermal-sensors = <&tsens0 11>;
6668 6279
6669 trips { 6280 trips {
6670 trip-point0 { 6281 trip-point0 {
6671 tempe 6282 temperature = <90000>;
6672 hyste 6283 hysteresis = <2000>;
6673 type 6284 type = "hot";
6674 }; 6285 };
6675 6286
6676 mem-critical 6287 mem-critical {
6677 tempe 6288 temperature = <125000>;
6678 hyste 6289 hysteresis = <0>;
6679 type 6290 type = "critical";
6680 }; 6291 };
6681 }; 6292 };
6682 }; 6293 };
6683 6294
6684 video-thermal { 6295 video-thermal {
6685 polling-delay-passive 6296 polling-delay-passive = <250>;
6686 6297
6687 thermal-sensors = <&t 6298 thermal-sensors = <&tsens0 12>;
6688 6299
6689 trips { 6300 trips {
6690 trip-point0 { 6301 trip-point0 {
6691 tempe 6302 temperature = <125000>;
6692 hyste 6303 hysteresis = <1000>;
6693 type 6304 type = "passive";
6694 }; 6305 };
6695 }; 6306 };
6696 }; 6307 };
6697 6308
6698 aoss1-thermal { 6309 aoss1-thermal {
6699 thermal-sensors = <&t 6310 thermal-sensors = <&tsens1 0>;
6700 6311
6701 trips { 6312 trips {
6702 trip-point0 { 6313 trip-point0 {
6703 tempe 6314 temperature = <90000>;
6704 hyste 6315 hysteresis = <2000>;
6705 type 6316 type = "hot";
6706 }; 6317 };
6707 6318
6708 aoss0-critica 6319 aoss0-critical {
6709 tempe 6320 temperature = <125000>;
6710 hyste 6321 hysteresis = <0>;
6711 type 6322 type = "critical";
6712 }; 6323 };
6713 }; 6324 };
6714 }; 6325 };
6715 6326
6716 cpu1-0-top-thermal { 6327 cpu1-0-top-thermal {
6717 polling-delay-passive 6328 polling-delay-passive = <250>;
6718 6329
6719 thermal-sensors = <&t 6330 thermal-sensors = <&tsens1 1>;
6720 6331
6721 trips { 6332 trips {
6722 trip-point0 { 6333 trip-point0 {
6723 tempe 6334 temperature = <90000>;
6724 hyste 6335 hysteresis = <2000>;
6725 type 6336 type = "passive";
6726 }; 6337 };
6727 6338
6728 trip-point1 { 6339 trip-point1 {
6729 tempe 6340 temperature = <95000>;
6730 hyste 6341 hysteresis = <2000>;
6731 type 6342 type = "passive";
6732 }; 6343 };
6733 6344
6734 cpu-critical 6345 cpu-critical {
6735 tempe 6346 temperature = <110000>;
6736 hyste 6347 hysteresis = <1000>;
6737 type 6348 type = "critical";
6738 }; 6349 };
6739 }; 6350 };
6740 }; 6351 };
6741 6352
6742 cpu1-0-btm-thermal { 6353 cpu1-0-btm-thermal {
6743 polling-delay-passive 6354 polling-delay-passive = <250>;
6744 6355
6745 thermal-sensors = <&t 6356 thermal-sensors = <&tsens1 2>;
6746 6357
6747 trips { 6358 trips {
6748 trip-point0 { 6359 trip-point0 {
6749 tempe 6360 temperature = <90000>;
6750 hyste 6361 hysteresis = <2000>;
6751 type 6362 type = "passive";
6752 }; 6363 };
6753 6364
6754 trip-point1 { 6365 trip-point1 {
6755 tempe 6366 temperature = <95000>;
6756 hyste 6367 hysteresis = <2000>;
6757 type 6368 type = "passive";
6758 }; 6369 };
6759 6370
6760 cpu-critical 6371 cpu-critical {
6761 tempe 6372 temperature = <110000>;
6762 hyste 6373 hysteresis = <1000>;
6763 type 6374 type = "critical";
6764 }; 6375 };
6765 }; 6376 };
6766 }; 6377 };
6767 6378
6768 cpu1-1-top-thermal { 6379 cpu1-1-top-thermal {
6769 polling-delay-passive 6380 polling-delay-passive = <250>;
6770 6381
6771 thermal-sensors = <&t 6382 thermal-sensors = <&tsens1 3>;
6772 6383
6773 trips { 6384 trips {
6774 trip-point0 { 6385 trip-point0 {
6775 tempe 6386 temperature = <90000>;
6776 hyste 6387 hysteresis = <2000>;
6777 type 6388 type = "passive";
6778 }; 6389 };
6779 6390
6780 trip-point1 { 6391 trip-point1 {
6781 tempe 6392 temperature = <95000>;
6782 hyste 6393 hysteresis = <2000>;
6783 type 6394 type = "passive";
6784 }; 6395 };
6785 6396
6786 cpu-critical 6397 cpu-critical {
6787 tempe 6398 temperature = <110000>;
6788 hyste 6399 hysteresis = <1000>;
6789 type 6400 type = "critical";
6790 }; 6401 };
6791 }; 6402 };
6792 }; 6403 };
6793 6404
6794 cpu1-1-btm-thermal { 6405 cpu1-1-btm-thermal {
6795 polling-delay-passive 6406 polling-delay-passive = <250>;
6796 6407
6797 thermal-sensors = <&t 6408 thermal-sensors = <&tsens1 4>;
6798 6409
6799 trips { 6410 trips {
6800 trip-point0 { 6411 trip-point0 {
6801 tempe 6412 temperature = <90000>;
6802 hyste 6413 hysteresis = <2000>;
6803 type 6414 type = "passive";
6804 }; 6415 };
6805 6416
6806 trip-point1 { 6417 trip-point1 {
6807 tempe 6418 temperature = <95000>;
6808 hyste 6419 hysteresis = <2000>;
6809 type 6420 type = "passive";
6810 }; 6421 };
6811 6422
6812 cpu-critical 6423 cpu-critical {
6813 tempe 6424 temperature = <110000>;
6814 hyste 6425 hysteresis = <1000>;
6815 type 6426 type = "critical";
6816 }; 6427 };
6817 }; 6428 };
6818 }; 6429 };
6819 6430
6820 cpu1-2-top-thermal { 6431 cpu1-2-top-thermal {
6821 polling-delay-passive 6432 polling-delay-passive = <250>;
6822 6433
6823 thermal-sensors = <&t 6434 thermal-sensors = <&tsens1 5>;
6824 6435
6825 trips { 6436 trips {
6826 trip-point0 { 6437 trip-point0 {
6827 tempe 6438 temperature = <90000>;
6828 hyste 6439 hysteresis = <2000>;
6829 type 6440 type = "passive";
6830 }; 6441 };
6831 6442
6832 trip-point1 { 6443 trip-point1 {
6833 tempe 6444 temperature = <95000>;
6834 hyste 6445 hysteresis = <2000>;
6835 type 6446 type = "passive";
6836 }; 6447 };
6837 6448
6838 cpu-critical 6449 cpu-critical {
6839 tempe 6450 temperature = <110000>;
6840 hyste 6451 hysteresis = <1000>;
6841 type 6452 type = "critical";
6842 }; 6453 };
6843 }; 6454 };
6844 }; 6455 };
6845 6456
6846 cpu1-2-btm-thermal { 6457 cpu1-2-btm-thermal {
6847 polling-delay-passive 6458 polling-delay-passive = <250>;
6848 6459
6849 thermal-sensors = <&t 6460 thermal-sensors = <&tsens1 6>;
6850 6461
6851 trips { 6462 trips {
6852 trip-point0 { 6463 trip-point0 {
6853 tempe 6464 temperature = <90000>;
6854 hyste 6465 hysteresis = <2000>;
6855 type 6466 type = "passive";
6856 }; 6467 };
6857 6468
6858 trip-point1 { 6469 trip-point1 {
6859 tempe 6470 temperature = <95000>;
6860 hyste 6471 hysteresis = <2000>;
6861 type 6472 type = "passive";
6862 }; 6473 };
6863 6474
6864 cpu-critical 6475 cpu-critical {
6865 tempe 6476 temperature = <110000>;
6866 hyste 6477 hysteresis = <1000>;
6867 type 6478 type = "critical";
6868 }; 6479 };
6869 }; 6480 };
6870 }; 6481 };
6871 6482
6872 cpu1-3-top-thermal { 6483 cpu1-3-top-thermal {
6873 polling-delay-passive 6484 polling-delay-passive = <250>;
6874 6485
6875 thermal-sensors = <&t 6486 thermal-sensors = <&tsens1 7>;
6876 6487
6877 trips { 6488 trips {
6878 trip-point0 { 6489 trip-point0 {
6879 tempe 6490 temperature = <90000>;
6880 hyste 6491 hysteresis = <2000>;
6881 type 6492 type = "passive";
6882 }; 6493 };
6883 6494
6884 trip-point1 { 6495 trip-point1 {
6885 tempe 6496 temperature = <95000>;
6886 hyste 6497 hysteresis = <2000>;
6887 type 6498 type = "passive";
6888 }; 6499 };
6889 6500
6890 cpu-critical 6501 cpu-critical {
6891 tempe 6502 temperature = <110000>;
6892 hyste 6503 hysteresis = <1000>;
6893 type 6504 type = "critical";
6894 }; 6505 };
6895 }; 6506 };
6896 }; 6507 };
6897 6508
6898 cpu1-3-btm-thermal { 6509 cpu1-3-btm-thermal {
6899 polling-delay-passive 6510 polling-delay-passive = <250>;
6900 6511
6901 thermal-sensors = <&t 6512 thermal-sensors = <&tsens1 8>;
6902 6513
6903 trips { 6514 trips {
6904 trip-point0 { 6515 trip-point0 {
6905 tempe 6516 temperature = <90000>;
6906 hyste 6517 hysteresis = <2000>;
6907 type 6518 type = "passive";
6908 }; 6519 };
6909 6520
6910 trip-point1 { 6521 trip-point1 {
6911 tempe 6522 temperature = <95000>;
6912 hyste 6523 hysteresis = <2000>;
6913 type 6524 type = "passive";
6914 }; 6525 };
6915 6526
6916 cpu-critical 6527 cpu-critical {
6917 tempe 6528 temperature = <110000>;
6918 hyste 6529 hysteresis = <1000>;
6919 type 6530 type = "critical";
6920 }; 6531 };
6921 }; 6532 };
6922 }; 6533 };
6923 6534
6924 cpuss1-top-thermal { 6535 cpuss1-top-thermal {
6925 thermal-sensors = <&t 6536 thermal-sensors = <&tsens1 9>;
6926 6537
6927 trips { 6538 trips {
6928 trip-point0 { 6539 trip-point0 {
6929 tempe 6540 temperature = <90000>;
6930 hyste 6541 hysteresis = <2000>;
6931 type 6542 type = "hot";
6932 }; 6543 };
6933 6544
6934 cpuss2-critic 6545 cpuss2-critical {
6935 tempe 6546 temperature = <125000>;
6936 hyste 6547 hysteresis = <0>;
6937 type 6548 type = "critical";
6938 }; 6549 };
6939 }; 6550 };
6940 }; 6551 };
6941 6552
6942 cpuss1-btm-thermal { 6553 cpuss1-btm-thermal {
6943 thermal-sensors = <&t 6554 thermal-sensors = <&tsens1 10>;
6944 6555
6945 trips { 6556 trips {
6946 trip-point0 { 6557 trip-point0 {
6947 tempe 6558 temperature = <90000>;
6948 hyste 6559 hysteresis = <2000>;
6949 type 6560 type = "hot";
6950 }; 6561 };
6951 6562
6952 cpuss2-critic 6563 cpuss2-critical {
6953 tempe 6564 temperature = <125000>;
6954 hyste 6565 hysteresis = <0>;
6955 type 6566 type = "critical";
6956 }; 6567 };
6957 }; 6568 };
6958 }; 6569 };
6959 6570
6960 aoss2-thermal { 6571 aoss2-thermal {
6961 thermal-sensors = <&t 6572 thermal-sensors = <&tsens2 0>;
6962 6573
6963 trips { 6574 trips {
6964 trip-point0 { 6575 trip-point0 {
6965 tempe 6576 temperature = <90000>;
6966 hyste 6577 hysteresis = <2000>;
6967 type 6578 type = "hot";
6968 }; 6579 };
6969 6580
6970 aoss0-critica 6581 aoss0-critical {
6971 tempe 6582 temperature = <125000>;
6972 hyste 6583 hysteresis = <0>;
6973 type 6584 type = "critical";
6974 }; 6585 };
6975 }; 6586 };
6976 }; 6587 };
6977 6588
6978 cpu2-0-top-thermal { 6589 cpu2-0-top-thermal {
6979 polling-delay-passive 6590 polling-delay-passive = <250>;
6980 6591
6981 thermal-sensors = <&t 6592 thermal-sensors = <&tsens2 1>;
6982 6593
6983 trips { 6594 trips {
6984 trip-point0 { 6595 trip-point0 {
6985 tempe 6596 temperature = <90000>;
6986 hyste 6597 hysteresis = <2000>;
6987 type 6598 type = "passive";
6988 }; 6599 };
6989 6600
6990 trip-point1 { 6601 trip-point1 {
6991 tempe 6602 temperature = <95000>;
6992 hyste 6603 hysteresis = <2000>;
6993 type 6604 type = "passive";
6994 }; 6605 };
6995 6606
6996 cpu-critical 6607 cpu-critical {
6997 tempe 6608 temperature = <110000>;
6998 hyste 6609 hysteresis = <1000>;
6999 type 6610 type = "critical";
7000 }; 6611 };
7001 }; 6612 };
7002 }; 6613 };
7003 6614
7004 cpu2-0-btm-thermal { 6615 cpu2-0-btm-thermal {
7005 polling-delay-passive 6616 polling-delay-passive = <250>;
7006 6617
7007 thermal-sensors = <&t 6618 thermal-sensors = <&tsens2 2>;
7008 6619
7009 trips { 6620 trips {
7010 trip-point0 { 6621 trip-point0 {
7011 tempe 6622 temperature = <90000>;
7012 hyste 6623 hysteresis = <2000>;
7013 type 6624 type = "passive";
7014 }; 6625 };
7015 6626
7016 trip-point1 { 6627 trip-point1 {
7017 tempe 6628 temperature = <95000>;
7018 hyste 6629 hysteresis = <2000>;
7019 type 6630 type = "passive";
7020 }; 6631 };
7021 6632
7022 cpu-critical 6633 cpu-critical {
7023 tempe 6634 temperature = <110000>;
7024 hyste 6635 hysteresis = <1000>;
7025 type 6636 type = "critical";
7026 }; 6637 };
7027 }; 6638 };
7028 }; 6639 };
7029 6640
7030 cpu2-1-top-thermal { 6641 cpu2-1-top-thermal {
7031 polling-delay-passive 6642 polling-delay-passive = <250>;
7032 6643
7033 thermal-sensors = <&t 6644 thermal-sensors = <&tsens2 3>;
7034 6645
7035 trips { 6646 trips {
7036 trip-point0 { 6647 trip-point0 {
7037 tempe 6648 temperature = <90000>;
7038 hyste 6649 hysteresis = <2000>;
7039 type 6650 type = "passive";
7040 }; 6651 };
7041 6652
7042 trip-point1 { 6653 trip-point1 {
7043 tempe 6654 temperature = <95000>;
7044 hyste 6655 hysteresis = <2000>;
7045 type 6656 type = "passive";
7046 }; 6657 };
7047 6658
7048 cpu-critical 6659 cpu-critical {
7049 tempe 6660 temperature = <110000>;
7050 hyste 6661 hysteresis = <1000>;
7051 type 6662 type = "critical";
7052 }; 6663 };
7053 }; 6664 };
7054 }; 6665 };
7055 6666
7056 cpu2-1-btm-thermal { 6667 cpu2-1-btm-thermal {
7057 polling-delay-passive 6668 polling-delay-passive = <250>;
7058 6669
7059 thermal-sensors = <&t 6670 thermal-sensors = <&tsens2 4>;
7060 6671
7061 trips { 6672 trips {
7062 trip-point0 { 6673 trip-point0 {
7063 tempe 6674 temperature = <90000>;
7064 hyste 6675 hysteresis = <2000>;
7065 type 6676 type = "passive";
7066 }; 6677 };
7067 6678
7068 trip-point1 { 6679 trip-point1 {
7069 tempe 6680 temperature = <95000>;
7070 hyste 6681 hysteresis = <2000>;
7071 type 6682 type = "passive";
7072 }; 6683 };
7073 6684
7074 cpu-critical 6685 cpu-critical {
7075 tempe 6686 temperature = <110000>;
7076 hyste 6687 hysteresis = <1000>;
7077 type 6688 type = "critical";
7078 }; 6689 };
7079 }; 6690 };
7080 }; 6691 };
7081 6692
7082 cpu2-2-top-thermal { 6693 cpu2-2-top-thermal {
7083 polling-delay-passive 6694 polling-delay-passive = <250>;
7084 6695
7085 thermal-sensors = <&t 6696 thermal-sensors = <&tsens2 5>;
7086 6697
7087 trips { 6698 trips {
7088 trip-point0 { 6699 trip-point0 {
7089 tempe 6700 temperature = <90000>;
7090 hyste 6701 hysteresis = <2000>;
7091 type 6702 type = "passive";
7092 }; 6703 };
7093 6704
7094 trip-point1 { 6705 trip-point1 {
7095 tempe 6706 temperature = <95000>;
7096 hyste 6707 hysteresis = <2000>;
7097 type 6708 type = "passive";
7098 }; 6709 };
7099 6710
7100 cpu-critical 6711 cpu-critical {
7101 tempe 6712 temperature = <110000>;
7102 hyste 6713 hysteresis = <1000>;
7103 type 6714 type = "critical";
7104 }; 6715 };
7105 }; 6716 };
7106 }; 6717 };
7107 6718
7108 cpu2-2-btm-thermal { 6719 cpu2-2-btm-thermal {
7109 polling-delay-passive 6720 polling-delay-passive = <250>;
7110 6721
7111 thermal-sensors = <&t 6722 thermal-sensors = <&tsens2 6>;
7112 6723
7113 trips { 6724 trips {
7114 trip-point0 { 6725 trip-point0 {
7115 tempe 6726 temperature = <90000>;
7116 hyste 6727 hysteresis = <2000>;
7117 type 6728 type = "passive";
7118 }; 6729 };
7119 6730
7120 trip-point1 { 6731 trip-point1 {
7121 tempe 6732 temperature = <95000>;
7122 hyste 6733 hysteresis = <2000>;
7123 type 6734 type = "passive";
7124 }; 6735 };
7125 6736
7126 cpu-critical 6737 cpu-critical {
7127 tempe 6738 temperature = <110000>;
7128 hyste 6739 hysteresis = <1000>;
7129 type 6740 type = "critical";
7130 }; 6741 };
7131 }; 6742 };
7132 }; 6743 };
7133 6744
7134 cpu2-3-top-thermal { 6745 cpu2-3-top-thermal {
7135 polling-delay-passive 6746 polling-delay-passive = <250>;
7136 6747
7137 thermal-sensors = <&t 6748 thermal-sensors = <&tsens2 7>;
7138 6749
7139 trips { 6750 trips {
7140 trip-point0 { 6751 trip-point0 {
7141 tempe 6752 temperature = <90000>;
7142 hyste 6753 hysteresis = <2000>;
7143 type 6754 type = "passive";
7144 }; 6755 };
7145 6756
7146 trip-point1 { 6757 trip-point1 {
7147 tempe 6758 temperature = <95000>;
7148 hyste 6759 hysteresis = <2000>;
7149 type 6760 type = "passive";
7150 }; 6761 };
7151 6762
7152 cpu-critical 6763 cpu-critical {
7153 tempe 6764 temperature = <110000>;
7154 hyste 6765 hysteresis = <1000>;
7155 type 6766 type = "critical";
7156 }; 6767 };
7157 }; 6768 };
7158 }; 6769 };
7159 6770
7160 cpu2-3-btm-thermal { 6771 cpu2-3-btm-thermal {
7161 polling-delay-passive 6772 polling-delay-passive = <250>;
7162 6773
7163 thermal-sensors = <&t 6774 thermal-sensors = <&tsens2 8>;
7164 6775
7165 trips { 6776 trips {
7166 trip-point0 { 6777 trip-point0 {
7167 tempe 6778 temperature = <90000>;
7168 hyste 6779 hysteresis = <2000>;
7169 type 6780 type = "passive";
7170 }; 6781 };
7171 6782
7172 trip-point1 { 6783 trip-point1 {
7173 tempe 6784 temperature = <95000>;
7174 hyste 6785 hysteresis = <2000>;
7175 type 6786 type = "passive";
7176 }; 6787 };
7177 6788
7178 cpu-critical 6789 cpu-critical {
7179 tempe 6790 temperature = <110000>;
7180 hyste 6791 hysteresis = <1000>;
7181 type 6792 type = "critical";
7182 }; 6793 };
7183 }; 6794 };
7184 }; 6795 };
7185 6796
7186 cpuss2-top-thermal { 6797 cpuss2-top-thermal {
7187 thermal-sensors = <&t 6798 thermal-sensors = <&tsens2 9>;
7188 6799
7189 trips { 6800 trips {
7190 trip-point0 { 6801 trip-point0 {
7191 tempe 6802 temperature = <90000>;
7192 hyste 6803 hysteresis = <2000>;
7193 type 6804 type = "hot";
7194 }; 6805 };
7195 6806
7196 cpuss2-critic 6807 cpuss2-critical {
7197 tempe 6808 temperature = <125000>;
7198 hyste 6809 hysteresis = <0>;
7199 type 6810 type = "critical";
7200 }; 6811 };
7201 }; 6812 };
7202 }; 6813 };
7203 6814
7204 cpuss2-btm-thermal { 6815 cpuss2-btm-thermal {
7205 thermal-sensors = <&t 6816 thermal-sensors = <&tsens2 10>;
7206 6817
7207 trips { 6818 trips {
7208 trip-point0 { 6819 trip-point0 {
7209 tempe 6820 temperature = <90000>;
7210 hyste 6821 hysteresis = <2000>;
7211 type 6822 type = "hot";
7212 }; 6823 };
7213 6824
7214 cpuss2-critic 6825 cpuss2-critical {
7215 tempe 6826 temperature = <125000>;
7216 hyste 6827 hysteresis = <0>;
7217 type 6828 type = "critical";
7218 }; 6829 };
7219 }; 6830 };
7220 }; 6831 };
7221 6832
7222 aoss3-thermal { 6833 aoss3-thermal {
7223 thermal-sensors = <&t 6834 thermal-sensors = <&tsens3 0>;
7224 6835
7225 trips { 6836 trips {
7226 trip-point0 { 6837 trip-point0 {
7227 tempe 6838 temperature = <90000>;
7228 hyste 6839 hysteresis = <2000>;
7229 type 6840 type = "hot";
7230 }; 6841 };
7231 6842
7232 aoss0-critica 6843 aoss0-critical {
7233 tempe 6844 temperature = <125000>;
7234 hyste 6845 hysteresis = <0>;
7235 type 6846 type = "critical";
7236 }; 6847 };
7237 }; 6848 };
7238 }; 6849 };
7239 6850
7240 nsp0-thermal { 6851 nsp0-thermal {
7241 thermal-sensors = <&t 6852 thermal-sensors = <&tsens3 1>;
7242 6853
7243 trips { 6854 trips {
7244 trip-point0 { 6855 trip-point0 {
7245 tempe 6856 temperature = <90000>;
7246 hyste 6857 hysteresis = <2000>;
7247 type 6858 type = "hot";
7248 }; 6859 };
7249 6860
7250 nsp0-critical 6861 nsp0-critical {
7251 tempe 6862 temperature = <125000>;
7252 hyste 6863 hysteresis = <0>;
7253 type 6864 type = "critical";
7254 }; 6865 };
7255 }; 6866 };
7256 }; 6867 };
7257 6868
7258 nsp1-thermal { 6869 nsp1-thermal {
7259 thermal-sensors = <&t 6870 thermal-sensors = <&tsens3 2>;
7260 6871
7261 trips { 6872 trips {
7262 trip-point0 { 6873 trip-point0 {
7263 tempe 6874 temperature = <90000>;
7264 hyste 6875 hysteresis = <2000>;
7265 type 6876 type = "hot";
7266 }; 6877 };
7267 6878
7268 nsp1-critical 6879 nsp1-critical {
7269 tempe 6880 temperature = <125000>;
7270 hyste 6881 hysteresis = <0>;
7271 type 6882 type = "critical";
7272 }; 6883 };
7273 }; 6884 };
7274 }; 6885 };
7275 6886
7276 nsp2-thermal { 6887 nsp2-thermal {
7277 thermal-sensors = <&t 6888 thermal-sensors = <&tsens3 3>;
7278 6889
7279 trips { 6890 trips {
7280 trip-point0 { 6891 trip-point0 {
7281 tempe 6892 temperature = <90000>;
7282 hyste 6893 hysteresis = <2000>;
7283 type 6894 type = "hot";
7284 }; 6895 };
7285 6896
7286 nsp2-critical 6897 nsp2-critical {
7287 tempe 6898 temperature = <125000>;
7288 hyste 6899 hysteresis = <0>;
7289 type 6900 type = "critical";
7290 }; 6901 };
7291 }; 6902 };
7292 }; 6903 };
7293 6904
7294 nsp3-thermal { 6905 nsp3-thermal {
7295 thermal-sensors = <&t 6906 thermal-sensors = <&tsens3 4>;
7296 6907
7297 trips { 6908 trips {
7298 trip-point0 { 6909 trip-point0 {
7299 tempe 6910 temperature = <90000>;
7300 hyste 6911 hysteresis = <2000>;
7301 type 6912 type = "hot";
7302 }; 6913 };
7303 6914
7304 nsp3-critical 6915 nsp3-critical {
7305 tempe 6916 temperature = <125000>;
7306 hyste 6917 hysteresis = <0>;
7307 type 6918 type = "critical";
7308 }; 6919 };
7309 }; 6920 };
7310 }; 6921 };
7311 6922
7312 gpuss-0-thermal { 6923 gpuss-0-thermal {
7313 polling-delay-passive 6924 polling-delay-passive = <10>;
7314 6925
7315 thermal-sensors = <&t 6926 thermal-sensors = <&tsens3 5>;
7316 6927
7317 trips { 6928 trips {
7318 trip-point0 { 6929 trip-point0 {
7319 tempe 6930 temperature = <85000>;
7320 hyste 6931 hysteresis = <1000>;
7321 type 6932 type = "passive";
7322 }; 6933 };
7323 6934
7324 trip-point1 { 6935 trip-point1 {
7325 tempe 6936 temperature = <90000>;
7326 hyste 6937 hysteresis = <1000>;
7327 type 6938 type = "hot";
7328 }; 6939 };
7329 6940
7330 trip-point2 { 6941 trip-point2 {
7331 tempe 6942 temperature = <125000>;
7332 hyste 6943 hysteresis = <1000>;
7333 type 6944 type = "critical";
7334 }; 6945 };
7335 }; 6946 };
7336 }; 6947 };
7337 6948
7338 gpuss-1-thermal { 6949 gpuss-1-thermal {
7339 polling-delay-passive 6950 polling-delay-passive = <10>;
7340 6951
7341 thermal-sensors = <&t 6952 thermal-sensors = <&tsens3 6>;
7342 6953
7343 trips { 6954 trips {
7344 trip-point0 { 6955 trip-point0 {
7345 tempe 6956 temperature = <85000>;
7346 hyste 6957 hysteresis = <1000>;
7347 type 6958 type = "passive";
7348 }; 6959 };
7349 6960
7350 trip-point1 { 6961 trip-point1 {
7351 tempe 6962 temperature = <90000>;
7352 hyste 6963 hysteresis = <1000>;
7353 type 6964 type = "hot";
7354 }; 6965 };
7355 6966
7356 trip-point2 { 6967 trip-point2 {
7357 tempe 6968 temperature = <125000>;
7358 hyste 6969 hysteresis = <1000>;
7359 type 6970 type = "critical";
7360 }; 6971 };
7361 }; 6972 };
7362 }; 6973 };
7363 6974
7364 gpuss-2-thermal { 6975 gpuss-2-thermal {
7365 polling-delay-passive 6976 polling-delay-passive = <10>;
7366 6977
7367 thermal-sensors = <&t 6978 thermal-sensors = <&tsens3 7>;
7368 6979
7369 trips { 6980 trips {
7370 trip-point0 { 6981 trip-point0 {
7371 tempe 6982 temperature = <85000>;
7372 hyste 6983 hysteresis = <1000>;
7373 type 6984 type = "passive";
7374 }; 6985 };
7375 6986
7376 trip-point1 { 6987 trip-point1 {
7377 tempe 6988 temperature = <90000>;
7378 hyste 6989 hysteresis = <1000>;
7379 type 6990 type = "hot";
7380 }; 6991 };
7381 6992
7382 trip-point2 { 6993 trip-point2 {
7383 tempe 6994 temperature = <125000>;
7384 hyste 6995 hysteresis = <1000>;
7385 type 6996 type = "critical";
7386 }; 6997 };
7387 }; 6998 };
7388 }; 6999 };
7389 7000
7390 gpuss-3-thermal { 7001 gpuss-3-thermal {
7391 polling-delay-passive 7002 polling-delay-passive = <10>;
7392 7003
7393 thermal-sensors = <&t 7004 thermal-sensors = <&tsens3 8>;
7394 7005
7395 trips { 7006 trips {
7396 trip-point0 { 7007 trip-point0 {
7397 tempe 7008 temperature = <85000>;
7398 hyste 7009 hysteresis = <1000>;
7399 type 7010 type = "passive";
7400 }; 7011 };
7401 7012
7402 trip-point1 { 7013 trip-point1 {
7403 tempe 7014 temperature = <90000>;
7404 hyste 7015 hysteresis = <1000>;
7405 type 7016 type = "hot";
7406 }; 7017 };
7407 7018
7408 trip-point2 { 7019 trip-point2 {
7409 tempe 7020 temperature = <125000>;
7410 hyste 7021 hysteresis = <1000>;
7411 type 7022 type = "critical";
7412 }; 7023 };
7413 }; 7024 };
7414 }; 7025 };
7415 7026
7416 gpuss-4-thermal { 7027 gpuss-4-thermal {
7417 polling-delay-passive 7028 polling-delay-passive = <10>;
7418 7029
7419 thermal-sensors = <&t 7030 thermal-sensors = <&tsens3 9>;
7420 7031
7421 trips { 7032 trips {
7422 trip-point0 { 7033 trip-point0 {
7423 tempe 7034 temperature = <85000>;
7424 hyste 7035 hysteresis = <1000>;
7425 type 7036 type = "passive";
7426 }; 7037 };
7427 7038
7428 trip-point1 { 7039 trip-point1 {
7429 tempe 7040 temperature = <90000>;
7430 hyste 7041 hysteresis = <1000>;
7431 type 7042 type = "hot";
7432 }; 7043 };
7433 7044
7434 trip-point2 { 7045 trip-point2 {
7435 tempe 7046 temperature = <125000>;
7436 hyste 7047 hysteresis = <1000>;
7437 type 7048 type = "critical";
7438 }; 7049 };
7439 }; 7050 };
7440 }; 7051 };
7441 7052
7442 gpuss-5-thermal { 7053 gpuss-5-thermal {
7443 polling-delay-passive 7054 polling-delay-passive = <10>;
7444 7055
7445 thermal-sensors = <&t 7056 thermal-sensors = <&tsens3 10>;
7446 7057
7447 trips { 7058 trips {
7448 trip-point0 { 7059 trip-point0 {
7449 tempe 7060 temperature = <85000>;
7450 hyste 7061 hysteresis = <1000>;
7451 type 7062 type = "passive";
7452 }; 7063 };
7453 7064
7454 trip-point1 { 7065 trip-point1 {
7455 tempe 7066 temperature = <90000>;
7456 hyste 7067 hysteresis = <1000>;
7457 type 7068 type = "hot";
7458 }; 7069 };
7459 7070
7460 trip-point2 { 7071 trip-point2 {
7461 tempe 7072 temperature = <125000>;
7462 hyste 7073 hysteresis = <1000>;
7463 type 7074 type = "critical";
7464 }; 7075 };
7465 }; 7076 };
7466 }; 7077 };
7467 7078
7468 gpuss-6-thermal { 7079 gpuss-6-thermal {
7469 polling-delay-passive 7080 polling-delay-passive = <10>;
7470 7081
7471 thermal-sensors = <&t 7082 thermal-sensors = <&tsens3 11>;
7472 7083
7473 trips { 7084 trips {
7474 trip-point0 { 7085 trip-point0 {
7475 tempe 7086 temperature = <85000>;
7476 hyste 7087 hysteresis = <1000>;
7477 type 7088 type = "passive";
7478 }; 7089 };
7479 7090
7480 trip-point1 { 7091 trip-point1 {
7481 tempe 7092 temperature = <90000>;
7482 hyste 7093 hysteresis = <1000>;
7483 type 7094 type = "hot";
7484 }; 7095 };
7485 7096
7486 trip-point2 { 7097 trip-point2 {
7487 tempe 7098 temperature = <125000>;
7488 hyste 7099 hysteresis = <1000>;
7489 type 7100 type = "critical";
7490 }; 7101 };
7491 }; 7102 };
7492 }; 7103 };
7493 7104
7494 gpuss-7-thermal { 7105 gpuss-7-thermal {
7495 polling-delay-passive 7106 polling-delay-passive = <10>;
7496 7107
7497 thermal-sensors = <&t 7108 thermal-sensors = <&tsens3 12>;
7498 7109
7499 trips { 7110 trips {
7500 trip-point0 { 7111 trip-point0 {
7501 tempe 7112 temperature = <85000>;
7502 hyste 7113 hysteresis = <1000>;
7503 type 7114 type = "passive";
7504 }; 7115 };
7505 7116
7506 trip-point1 { 7117 trip-point1 {
7507 tempe 7118 temperature = <90000>;
7508 hyste 7119 hysteresis = <1000>;
7509 type 7120 type = "hot";
7510 }; 7121 };
7511 7122
7512 trip-point2 { 7123 trip-point2 {
7513 tempe 7124 temperature = <125000>;
7514 hyste 7125 hysteresis = <1000>;
7515 type 7126 type = "critical";
7516 }; 7127 };
7517 }; 7128 };
7518 }; 7129 };
7519 7130
7520 camera0-thermal { 7131 camera0-thermal {
7521 thermal-sensors = <&t 7132 thermal-sensors = <&tsens3 13>;
7522 7133
7523 trips { 7134 trips {
7524 trip-point0 { 7135 trip-point0 {
7525 tempe 7136 temperature = <90000>;
7526 hyste 7137 hysteresis = <2000>;
7527 type 7138 type = "hot";
7528 }; 7139 };
7529 7140
7530 camera0-criti 7141 camera0-critical {
7531 tempe 7142 temperature = <115000>;
7532 hyste 7143 hysteresis = <0>;
7533 type 7144 type = "critical";
7534 }; 7145 };
7535 }; 7146 };
7536 }; 7147 };
7537 7148
7538 camera1-thermal { 7149 camera1-thermal {
7539 thermal-sensors = <&t 7150 thermal-sensors = <&tsens3 14>;
7540 7151
7541 trips { 7152 trips {
7542 trip-point0 { 7153 trip-point0 {
7543 tempe 7154 temperature = <90000>;
7544 hyste 7155 hysteresis = <2000>;
7545 type 7156 type = "hot";
7546 }; 7157 };
7547 7158
7548 camera0-criti 7159 camera0-critical {
7549 tempe 7160 temperature = <115000>;
7550 hyste 7161 hysteresis = <0>;
7551 type 7162 type = "critical";
7552 }; 7163 };
7553 }; 7164 };
7554 }; 7165 };
7555 }; 7166 };
7556 }; 7167 };
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