1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * Copyright (c) 2023 Qualcomm Innovation Cent 3 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
4 */ 4 */
5 5
6 #include <dt-bindings/clock/qcom,rpmh.h> 6 #include <dt-bindings/clock/qcom,rpmh.h>
7 #include <dt-bindings/clock/qcom,sc8280xp-lpas <<
8 #include <dt-bindings/clock/qcom,x1e80100-disp <<
9 #include <dt-bindings/clock/qcom,x1e80100-gcc. 7 #include <dt-bindings/clock/qcom,x1e80100-gcc.h>
10 #include <dt-bindings/clock/qcom,x1e80100-gpuc <<
11 #include <dt-bindings/clock/qcom,x1e80100-tcsr <<
12 #include <dt-bindings/dma/qcom-gpi.h> 8 #include <dt-bindings/dma/qcom-gpi.h>
13 #include <dt-bindings/interconnect/qcom,icc.h> 9 #include <dt-bindings/interconnect/qcom,icc.h>
14 #include <dt-bindings/interconnect/qcom,x1e801 10 #include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h>
15 #include <dt-bindings/interrupt-controller/arm 11 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/mailbox/qcom-ipcc.h> <<
17 #include <dt-bindings/phy/phy-qcom-qmp.h> <<
18 #include <dt-bindings/power/qcom,rpmhpd.h> 12 #include <dt-bindings/power/qcom,rpmhpd.h>
19 #include <dt-bindings/power/qcom-rpmpd.h> 13 #include <dt-bindings/power/qcom-rpmpd.h>
20 #include <dt-bindings/soc/qcom,gpr.h> <<
21 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 14 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
22 #include <dt-bindings/sound/qcom,q6dsp-lpass-p <<
23 15
24 / { 16 / {
25 interrupt-parent = <&intc>; 17 interrupt-parent = <&intc>;
26 18
27 #address-cells = <2>; 19 #address-cells = <2>;
28 #size-cells = <2>; 20 #size-cells = <2>;
29 21
30 chosen { }; 22 chosen { };
31 23
32 clocks { 24 clocks {
33 xo_board: xo-board { 25 xo_board: xo-board {
34 compatible = "fixed-cl 26 compatible = "fixed-clock";
35 clock-frequency = <768 27 clock-frequency = <76800000>;
36 #clock-cells = <0>; 28 #clock-cells = <0>;
37 }; 29 };
38 30
39 sleep_clk: sleep-clk { 31 sleep_clk: sleep-clk {
40 compatible = "fixed-cl 32 compatible = "fixed-clock";
41 clock-frequency = <320 33 clock-frequency = <32000>;
42 #clock-cells = <0>; 34 #clock-cells = <0>;
43 }; 35 };
44 36
45 bi_tcxo_div2: bi-tcxo-div2-clk 37 bi_tcxo_div2: bi-tcxo-div2-clk {
46 compatible = "fixed-fa 38 compatible = "fixed-factor-clock";
47 #clock-cells = <0>; 39 #clock-cells = <0>;
48 40
49 clocks = <&rpmhcc RPMH 41 clocks = <&rpmhcc RPMH_CXO_CLK>;
50 clock-mult = <1>; 42 clock-mult = <1>;
51 clock-div = <2>; 43 clock-div = <2>;
52 }; 44 };
53 45
54 bi_tcxo_ao_div2: bi-tcxo-ao-di 46 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
55 compatible = "fixed-fa 47 compatible = "fixed-factor-clock";
56 #clock-cells = <0>; 48 #clock-cells = <0>;
57 49
58 clocks = <&rpmhcc RPMH 50 clocks = <&rpmhcc RPMH_CXO_CLK_A>;
59 clock-mult = <1>; 51 clock-mult = <1>;
60 clock-div = <2>; 52 clock-div = <2>;
61 }; 53 };
62 }; 54 };
63 55
64 cpus { 56 cpus {
65 #address-cells = <2>; 57 #address-cells = <2>;
66 #size-cells = <0>; 58 #size-cells = <0>;
67 59
68 CPU0: cpu@0 { 60 CPU0: cpu@0 {
69 device_type = "cpu"; 61 device_type = "cpu";
70 compatible = "qcom,ory 62 compatible = "qcom,oryon";
71 reg = <0x0 0x0>; 63 reg = <0x0 0x0>;
72 enable-method = "psci" 64 enable-method = "psci";
73 next-level-cache = <&L 65 next-level-cache = <&L2_0>;
74 power-domains = <&CPU_ 66 power-domains = <&CPU_PD0>;
75 power-domain-names = " 67 power-domain-names = "psci";
76 cpu-idle-states = <&CL 68 cpu-idle-states = <&CLUSTER_C4>;
77 69
78 L2_0: l2-cache { 70 L2_0: l2-cache {
79 compatible = " 71 compatible = "cache";
80 cache-level = 72 cache-level = <2>;
81 cache-unified; 73 cache-unified;
82 }; 74 };
83 }; 75 };
84 76
85 CPU1: cpu@100 { 77 CPU1: cpu@100 {
86 device_type = "cpu"; 78 device_type = "cpu";
87 compatible = "qcom,ory 79 compatible = "qcom,oryon";
88 reg = <0x0 0x100>; 80 reg = <0x0 0x100>;
89 enable-method = "psci" 81 enable-method = "psci";
90 next-level-cache = <&L 82 next-level-cache = <&L2_0>;
91 power-domains = <&CPU_ 83 power-domains = <&CPU_PD1>;
92 power-domain-names = " 84 power-domain-names = "psci";
93 cpu-idle-states = <&CL 85 cpu-idle-states = <&CLUSTER_C4>;
94 }; 86 };
95 87
96 CPU2: cpu@200 { 88 CPU2: cpu@200 {
97 device_type = "cpu"; 89 device_type = "cpu";
98 compatible = "qcom,ory 90 compatible = "qcom,oryon";
99 reg = <0x0 0x200>; 91 reg = <0x0 0x200>;
100 enable-method = "psci" 92 enable-method = "psci";
101 next-level-cache = <&L 93 next-level-cache = <&L2_0>;
102 power-domains = <&CPU_ 94 power-domains = <&CPU_PD2>;
103 power-domain-names = " 95 power-domain-names = "psci";
104 cpu-idle-states = <&CL 96 cpu-idle-states = <&CLUSTER_C4>;
105 }; 97 };
106 98
107 CPU3: cpu@300 { 99 CPU3: cpu@300 {
108 device_type = "cpu"; 100 device_type = "cpu";
109 compatible = "qcom,ory 101 compatible = "qcom,oryon";
110 reg = <0x0 0x300>; 102 reg = <0x0 0x300>;
111 enable-method = "psci" 103 enable-method = "psci";
112 next-level-cache = <&L 104 next-level-cache = <&L2_0>;
113 power-domains = <&CPU_ 105 power-domains = <&CPU_PD3>;
114 power-domain-names = " 106 power-domain-names = "psci";
115 cpu-idle-states = <&CL 107 cpu-idle-states = <&CLUSTER_C4>;
116 }; 108 };
117 109
118 CPU4: cpu@10000 { 110 CPU4: cpu@10000 {
119 device_type = "cpu"; 111 device_type = "cpu";
120 compatible = "qcom,ory 112 compatible = "qcom,oryon";
121 reg = <0x0 0x10000>; 113 reg = <0x0 0x10000>;
122 enable-method = "psci" 114 enable-method = "psci";
123 next-level-cache = <&L 115 next-level-cache = <&L2_1>;
124 power-domains = <&CPU_ 116 power-domains = <&CPU_PD4>;
125 power-domain-names = " 117 power-domain-names = "psci";
126 cpu-idle-states = <&CL 118 cpu-idle-states = <&CLUSTER_C4>;
127 119
128 L2_1: l2-cache { 120 L2_1: l2-cache {
129 compatible = " 121 compatible = "cache";
130 cache-level = 122 cache-level = <2>;
131 cache-unified; 123 cache-unified;
132 }; 124 };
133 }; 125 };
134 126
135 CPU5: cpu@10100 { 127 CPU5: cpu@10100 {
136 device_type = "cpu"; 128 device_type = "cpu";
137 compatible = "qcom,ory 129 compatible = "qcom,oryon";
138 reg = <0x0 0x10100>; 130 reg = <0x0 0x10100>;
139 enable-method = "psci" 131 enable-method = "psci";
140 next-level-cache = <&L 132 next-level-cache = <&L2_1>;
141 power-domains = <&CPU_ 133 power-domains = <&CPU_PD5>;
142 power-domain-names = " 134 power-domain-names = "psci";
143 cpu-idle-states = <&CL 135 cpu-idle-states = <&CLUSTER_C4>;
144 }; 136 };
145 137
146 CPU6: cpu@10200 { 138 CPU6: cpu@10200 {
147 device_type = "cpu"; 139 device_type = "cpu";
148 compatible = "qcom,ory 140 compatible = "qcom,oryon";
149 reg = <0x0 0x10200>; 141 reg = <0x0 0x10200>;
150 enable-method = "psci" 142 enable-method = "psci";
151 next-level-cache = <&L 143 next-level-cache = <&L2_1>;
152 power-domains = <&CPU_ 144 power-domains = <&CPU_PD6>;
153 power-domain-names = " 145 power-domain-names = "psci";
154 cpu-idle-states = <&CL 146 cpu-idle-states = <&CLUSTER_C4>;
155 }; 147 };
156 148
157 CPU7: cpu@10300 { 149 CPU7: cpu@10300 {
158 device_type = "cpu"; 150 device_type = "cpu";
159 compatible = "qcom,ory 151 compatible = "qcom,oryon";
160 reg = <0x0 0x10300>; 152 reg = <0x0 0x10300>;
161 enable-method = "psci" 153 enable-method = "psci";
162 next-level-cache = <&L 154 next-level-cache = <&L2_1>;
163 power-domains = <&CPU_ 155 power-domains = <&CPU_PD7>;
164 power-domain-names = " 156 power-domain-names = "psci";
165 cpu-idle-states = <&CL 157 cpu-idle-states = <&CLUSTER_C4>;
166 }; 158 };
167 159
168 CPU8: cpu@20000 { 160 CPU8: cpu@20000 {
169 device_type = "cpu"; 161 device_type = "cpu";
170 compatible = "qcom,ory 162 compatible = "qcom,oryon";
171 reg = <0x0 0x20000>; 163 reg = <0x0 0x20000>;
172 enable-method = "psci" 164 enable-method = "psci";
173 next-level-cache = <&L 165 next-level-cache = <&L2_2>;
174 power-domains = <&CPU_ 166 power-domains = <&CPU_PD8>;
175 power-domain-names = " 167 power-domain-names = "psci";
176 cpu-idle-states = <&CL 168 cpu-idle-states = <&CLUSTER_C4>;
177 169
178 L2_2: l2-cache { 170 L2_2: l2-cache {
179 compatible = " 171 compatible = "cache";
180 cache-level = 172 cache-level = <2>;
181 cache-unified; 173 cache-unified;
182 }; 174 };
183 }; 175 };
184 176
185 CPU9: cpu@20100 { 177 CPU9: cpu@20100 {
186 device_type = "cpu"; 178 device_type = "cpu";
187 compatible = "qcom,ory 179 compatible = "qcom,oryon";
188 reg = <0x0 0x20100>; 180 reg = <0x0 0x20100>;
189 enable-method = "psci" 181 enable-method = "psci";
190 next-level-cache = <&L 182 next-level-cache = <&L2_2>;
191 power-domains = <&CPU_ 183 power-domains = <&CPU_PD9>;
192 power-domain-names = " 184 power-domain-names = "psci";
193 cpu-idle-states = <&CL 185 cpu-idle-states = <&CLUSTER_C4>;
194 }; 186 };
195 187
196 CPU10: cpu@20200 { 188 CPU10: cpu@20200 {
197 device_type = "cpu"; 189 device_type = "cpu";
198 compatible = "qcom,ory 190 compatible = "qcom,oryon";
199 reg = <0x0 0x20200>; 191 reg = <0x0 0x20200>;
200 enable-method = "psci" 192 enable-method = "psci";
201 next-level-cache = <&L 193 next-level-cache = <&L2_2>;
202 power-domains = <&CPU_ 194 power-domains = <&CPU_PD10>;
203 power-domain-names = " 195 power-domain-names = "psci";
204 cpu-idle-states = <&CL 196 cpu-idle-states = <&CLUSTER_C4>;
205 }; 197 };
206 198
207 CPU11: cpu@20300 { 199 CPU11: cpu@20300 {
208 device_type = "cpu"; 200 device_type = "cpu";
209 compatible = "qcom,ory 201 compatible = "qcom,oryon";
210 reg = <0x0 0x20300>; 202 reg = <0x0 0x20300>;
211 enable-method = "psci" 203 enable-method = "psci";
212 next-level-cache = <&L 204 next-level-cache = <&L2_2>;
213 power-domains = <&CPU_ 205 power-domains = <&CPU_PD11>;
214 power-domain-names = " 206 power-domain-names = "psci";
215 cpu-idle-states = <&CL 207 cpu-idle-states = <&CLUSTER_C4>;
216 }; 208 };
217 209
218 cpu-map { 210 cpu-map {
219 cluster0 { 211 cluster0 {
220 core0 { 212 core0 {
221 cpu = 213 cpu = <&CPU0>;
222 }; 214 };
223 215
224 core1 { 216 core1 {
225 cpu = 217 cpu = <&CPU1>;
226 }; 218 };
227 219
228 core2 { 220 core2 {
229 cpu = 221 cpu = <&CPU2>;
230 }; 222 };
231 223
232 core3 { 224 core3 {
233 cpu = 225 cpu = <&CPU3>;
234 }; 226 };
235 }; 227 };
236 228
237 cluster1 { 229 cluster1 {
238 core0 { 230 core0 {
239 cpu = 231 cpu = <&CPU4>;
240 }; 232 };
241 233
242 core1 { 234 core1 {
243 cpu = 235 cpu = <&CPU5>;
244 }; 236 };
245 237
246 core2 { 238 core2 {
247 cpu = 239 cpu = <&CPU6>;
248 }; 240 };
249 241
250 core3 { 242 core3 {
251 cpu = 243 cpu = <&CPU7>;
252 }; 244 };
253 }; 245 };
254 246
255 cluster2 { 247 cluster2 {
256 core0 { 248 core0 {
257 cpu = 249 cpu = <&CPU8>;
258 }; 250 };
259 251
260 core1 { 252 core1 {
261 cpu = 253 cpu = <&CPU9>;
262 }; 254 };
263 255
264 core2 { 256 core2 {
265 cpu = 257 cpu = <&CPU10>;
266 }; 258 };
267 259
268 core3 { 260 core3 {
269 cpu = 261 cpu = <&CPU11>;
270 }; 262 };
271 }; 263 };
272 }; 264 };
273 265
274 idle-states { 266 idle-states {
275 entry-method = "psci"; 267 entry-method = "psci";
276 268
277 CLUSTER_C4: cpu-sleep- 269 CLUSTER_C4: cpu-sleep-0 {
278 compatible = " 270 compatible = "arm,idle-state";
279 idle-state-nam 271 idle-state-name = "ret";
280 arm,psci-suspe 272 arm,psci-suspend-param = <0x00000004>;
281 entry-latency- 273 entry-latency-us = <180>;
282 exit-latency-u 274 exit-latency-us = <320>;
283 min-residency- 275 min-residency-us = <1000>;
284 }; 276 };
285 }; 277 };
286 278
287 domain-idle-states { 279 domain-idle-states {
288 CLUSTER_CL4: cluster-s 280 CLUSTER_CL4: cluster-sleep-0 {
289 compatible = " 281 compatible = "domain-idle-state";
290 idle-state-nam 282 idle-state-name = "l2-ret";
291 arm,psci-suspe 283 arm,psci-suspend-param = <0x01000044>;
292 entry-latency- 284 entry-latency-us = <350>;
293 exit-latency-u 285 exit-latency-us = <500>;
294 min-residency- 286 min-residency-us = <2500>;
295 }; 287 };
296 288
297 CLUSTER_CL5: cluster-s 289 CLUSTER_CL5: cluster-sleep-1 {
298 compatible = " 290 compatible = "domain-idle-state";
299 idle-state-nam 291 idle-state-name = "ret-pll-off";
300 arm,psci-suspe 292 arm,psci-suspend-param = <0x01000054>;
301 entry-latency- 293 entry-latency-us = <2200>;
302 exit-latency-u 294 exit-latency-us = <2500>;
303 min-residency- 295 min-residency-us = <7000>;
304 }; 296 };
305 }; 297 };
306 }; 298 };
307 299
308 firmware { 300 firmware {
309 scm: scm { 301 scm: scm {
310 compatible = "qcom,scm 302 compatible = "qcom,scm-x1e80100", "qcom,scm";
311 interconnects = <&aggr 303 interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS
312 &mc_v 304 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
313 }; 305 };
314 }; 306 };
315 307
316 clk_virt: interconnect-0 { 308 clk_virt: interconnect-0 {
317 compatible = "qcom,x1e80100-cl 309 compatible = "qcom,x1e80100-clk-virt";
318 #interconnect-cells = <2>; 310 #interconnect-cells = <2>;
319 qcom,bcm-voters = <&apps_bcm_v 311 qcom,bcm-voters = <&apps_bcm_voter>;
320 }; 312 };
321 313
322 mc_virt: interconnect-1 { 314 mc_virt: interconnect-1 {
323 compatible = "qcom,x1e80100-mc 315 compatible = "qcom,x1e80100-mc-virt";
324 #interconnect-cells = <2>; 316 #interconnect-cells = <2>;
325 qcom,bcm-voters = <&apps_bcm_v 317 qcom,bcm-voters = <&apps_bcm_voter>;
326 }; 318 };
327 319
328 memory@80000000 { 320 memory@80000000 {
329 device_type = "memory"; 321 device_type = "memory";
330 /* We expect the bootloader to 322 /* We expect the bootloader to fill in the size */
331 reg = <0 0x80000000 0 0>; 323 reg = <0 0x80000000 0 0>;
332 }; 324 };
333 325
334 pmu { 326 pmu {
335 compatible = "arm,armv8-pmuv3" 327 compatible = "arm,armv8-pmuv3";
336 interrupts = <GIC_PPI 7 IRQ_TY 328 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
337 }; 329 };
338 330
339 psci { 331 psci {
340 compatible = "arm,psci-1.0"; 332 compatible = "arm,psci-1.0";
341 method = "smc"; 333 method = "smc";
342 334
343 CPU_PD0: power-domain-cpu0 { 335 CPU_PD0: power-domain-cpu0 {
344 #power-domain-cells = 336 #power-domain-cells = <0>;
345 power-domains = <&CLUS 337 power-domains = <&CLUSTER_PD0>;
346 }; 338 };
347 339
348 CPU_PD1: power-domain-cpu1 { 340 CPU_PD1: power-domain-cpu1 {
349 #power-domain-cells = 341 #power-domain-cells = <0>;
350 power-domains = <&CLUS 342 power-domains = <&CLUSTER_PD0>;
351 }; 343 };
352 344
353 CPU_PD2: power-domain-cpu2 { 345 CPU_PD2: power-domain-cpu2 {
354 #power-domain-cells = 346 #power-domain-cells = <0>;
355 power-domains = <&CLUS 347 power-domains = <&CLUSTER_PD0>;
356 }; 348 };
357 349
358 CPU_PD3: power-domain-cpu3 { 350 CPU_PD3: power-domain-cpu3 {
359 #power-domain-cells = 351 #power-domain-cells = <0>;
360 power-domains = <&CLUS 352 power-domains = <&CLUSTER_PD0>;
361 }; 353 };
362 354
363 CPU_PD4: power-domain-cpu4 { 355 CPU_PD4: power-domain-cpu4 {
364 #power-domain-cells = 356 #power-domain-cells = <0>;
365 power-domains = <&CLUS 357 power-domains = <&CLUSTER_PD1>;
366 }; 358 };
367 359
368 CPU_PD5: power-domain-cpu5 { 360 CPU_PD5: power-domain-cpu5 {
369 #power-domain-cells = 361 #power-domain-cells = <0>;
370 power-domains = <&CLUS 362 power-domains = <&CLUSTER_PD1>;
371 }; 363 };
372 364
373 CPU_PD6: power-domain-cpu6 { 365 CPU_PD6: power-domain-cpu6 {
374 #power-domain-cells = 366 #power-domain-cells = <0>;
375 power-domains = <&CLUS 367 power-domains = <&CLUSTER_PD1>;
376 }; 368 };
377 369
378 CPU_PD7: power-domain-cpu7 { 370 CPU_PD7: power-domain-cpu7 {
379 #power-domain-cells = 371 #power-domain-cells = <0>;
380 power-domains = <&CLUS 372 power-domains = <&CLUSTER_PD1>;
381 }; 373 };
382 374
383 CPU_PD8: power-domain-cpu8 { 375 CPU_PD8: power-domain-cpu8 {
384 #power-domain-cells = 376 #power-domain-cells = <0>;
385 power-domains = <&CLUS 377 power-domains = <&CLUSTER_PD2>;
386 }; 378 };
387 379
388 CPU_PD9: power-domain-cpu9 { 380 CPU_PD9: power-domain-cpu9 {
389 #power-domain-cells = 381 #power-domain-cells = <0>;
390 power-domains = <&CLUS 382 power-domains = <&CLUSTER_PD2>;
391 }; 383 };
392 384
393 CPU_PD10: power-domain-cpu10 { 385 CPU_PD10: power-domain-cpu10 {
394 #power-domain-cells = 386 #power-domain-cells = <0>;
395 power-domains = <&CLUS 387 power-domains = <&CLUSTER_PD2>;
396 }; 388 };
397 389
398 CPU_PD11: power-domain-cpu11 { 390 CPU_PD11: power-domain-cpu11 {
399 #power-domain-cells = 391 #power-domain-cells = <0>;
400 power-domains = <&CLUS 392 power-domains = <&CLUSTER_PD2>;
401 }; 393 };
402 394
403 CLUSTER_PD0: power-domain-cpu- 395 CLUSTER_PD0: power-domain-cpu-cluster0 {
404 #power-domain-cells = 396 #power-domain-cells = <0>;
405 domain-idle-states = < 397 domain-idle-states = <&CLUSTER_CL4>, <&CLUSTER_CL5>;
406 power-domains = <&SYST <<
407 }; 398 };
408 399
409 CLUSTER_PD1: power-domain-cpu- 400 CLUSTER_PD1: power-domain-cpu-cluster1 {
410 #power-domain-cells = 401 #power-domain-cells = <0>;
411 domain-idle-states = < 402 domain-idle-states = <&CLUSTER_CL4>, <&CLUSTER_CL5>;
412 power-domains = <&SYST <<
413 }; 403 };
414 404
415 CLUSTER_PD2: power-domain-cpu- 405 CLUSTER_PD2: power-domain-cpu-cluster2 {
416 #power-domain-cells = 406 #power-domain-cells = <0>;
417 domain-idle-states = < 407 domain-idle-states = <&CLUSTER_CL4>, <&CLUSTER_CL5>;
418 power-domains = <&SYST <<
419 }; <<
420 <<
421 SYSTEM_PD: power-domain-system <<
422 #power-domain-cells = <<
423 /* TODO: system-wide i <<
424 }; 408 };
425 }; 409 };
426 410
427 reserved-memory { 411 reserved-memory {
428 #address-cells = <2>; 412 #address-cells = <2>;
429 #size-cells = <2>; 413 #size-cells = <2>;
430 ranges; 414 ranges;
431 415
432 gunyah_hyp_mem: gunyah-hyp@800 416 gunyah_hyp_mem: gunyah-hyp@80000000 {
433 reg = <0x0 0x80000000 417 reg = <0x0 0x80000000 0x0 0x800000>;
434 no-map; 418 no-map;
435 }; 419 };
436 420
437 hyp_elf_package_mem: hyp-elf-p 421 hyp_elf_package_mem: hyp-elf-package@80800000 {
438 reg = <0x0 0x80800000 422 reg = <0x0 0x80800000 0x0 0x200000>;
439 no-map; 423 no-map;
440 }; 424 };
441 425
442 ncc_mem: ncc@80a00000 { 426 ncc_mem: ncc@80a00000 {
443 reg = <0x0 0x80a00000 427 reg = <0x0 0x80a00000 0x0 0x400000>;
444 no-map; 428 no-map;
445 }; 429 };
446 430
447 cpucp_log_mem: cpucp-log@80e00 431 cpucp_log_mem: cpucp-log@80e00000 {
448 reg = <0x0 0x80e00000 432 reg = <0x0 0x80e00000 0x0 0x40000>;
449 no-map; 433 no-map;
450 }; 434 };
451 435
452 cpucp_mem: cpucp@80e40000 { 436 cpucp_mem: cpucp@80e40000 {
453 reg = <0x0 0x80e40000 437 reg = <0x0 0x80e40000 0x0 0x540000>;
454 no-map; 438 no-map;
455 }; 439 };
456 440
457 reserved-region@81380000 { 441 reserved-region@81380000 {
458 reg = <0x0 0x81380000 442 reg = <0x0 0x81380000 0x0 0x80000>;
459 no-map; 443 no-map;
460 }; 444 };
461 445
462 tags_mem: tags-region@81400000 446 tags_mem: tags-region@81400000 {
463 reg = <0x0 0x81400000 447 reg = <0x0 0x81400000 0x0 0x1a0000>;
464 no-map; 448 no-map;
465 }; 449 };
466 450
467 xbl_dtlog_mem: xbl-dtlog@81a00 451 xbl_dtlog_mem: xbl-dtlog@81a00000 {
468 reg = <0x0 0x81a00000 452 reg = <0x0 0x81a00000 0x0 0x40000>;
469 no-map; 453 no-map;
470 }; 454 };
471 455
472 xbl_ramdump_mem: xbl-ramdump@8 456 xbl_ramdump_mem: xbl-ramdump@81a40000 {
473 reg = <0x0 0x81a40000 457 reg = <0x0 0x81a40000 0x0 0x1c0000>;
474 no-map; 458 no-map;
475 }; 459 };
476 460
477 aop_image_mem: aop-image@81c00 461 aop_image_mem: aop-image@81c00000 {
478 reg = <0x0 0x81c00000 462 reg = <0x0 0x81c00000 0x0 0x60000>;
479 no-map; 463 no-map;
480 }; 464 };
481 465
482 aop_cmd_db_mem: aop-cmd-db@81c 466 aop_cmd_db_mem: aop-cmd-db@81c60000 {
483 compatible = "qcom,cmd 467 compatible = "qcom,cmd-db";
484 reg = <0x0 0x81c60000 468 reg = <0x0 0x81c60000 0x0 0x20000>;
485 no-map; 469 no-map;
486 }; 470 };
487 471
488 aop_config_mem: aop-config@81c 472 aop_config_mem: aop-config@81c80000 {
489 reg = <0x0 0x81c80000 473 reg = <0x0 0x81c80000 0x0 0x20000>;
490 no-map; 474 no-map;
491 }; 475 };
492 476
493 tme_crash_dump_mem: tme-crash- 477 tme_crash_dump_mem: tme-crash-dump@81ca0000 {
494 reg = <0x0 0x81ca0000 478 reg = <0x0 0x81ca0000 0x0 0x40000>;
495 no-map; 479 no-map;
496 }; 480 };
497 481
498 tme_log_mem: tme-log@81ce0000 482 tme_log_mem: tme-log@81ce0000 {
499 reg = <0x0 0x81ce0000 483 reg = <0x0 0x81ce0000 0x0 0x4000>;
500 no-map; 484 no-map;
501 }; 485 };
502 486
503 uefi_log_mem: uefi-log@81ce400 487 uefi_log_mem: uefi-log@81ce4000 {
504 reg = <0x0 0x81ce4000 488 reg = <0x0 0x81ce4000 0x0 0x10000>;
505 no-map; 489 no-map;
506 }; 490 };
507 491
508 secdata_apss_mem: secdata-apss 492 secdata_apss_mem: secdata-apss@81cff000 {
509 reg = <0x0 0x81cff000 493 reg = <0x0 0x81cff000 0x0 0x1000>;
510 no-map; 494 no-map;
511 }; 495 };
512 496
513 pdp_ns_shared_mem: pdp-ns-shar 497 pdp_ns_shared_mem: pdp-ns-shared@81e00000 {
514 reg = <0x0 0x81e00000 498 reg = <0x0 0x81e00000 0x0 0x100000>;
515 no-map; 499 no-map;
516 }; 500 };
517 501
518 gpu_prr_mem: gpu-prr@81f00000 502 gpu_prr_mem: gpu-prr@81f00000 {
519 reg = <0x0 0x81f00000 503 reg = <0x0 0x81f00000 0x0 0x10000>;
520 no-map; 504 no-map;
521 }; 505 };
522 506
523 tpm_control_mem: tpm-control@8 507 tpm_control_mem: tpm-control@81f10000 {
524 reg = <0x0 0x81f10000 508 reg = <0x0 0x81f10000 0x0 0x10000>;
525 no-map; 509 no-map;
526 }; 510 };
527 511
528 usb_ucsi_shared_mem: usb-ucsi- 512 usb_ucsi_shared_mem: usb-ucsi-shared@81f20000 {
529 reg = <0x0 0x81f20000 513 reg = <0x0 0x81f20000 0x0 0x10000>;
530 no-map; 514 no-map;
531 }; 515 };
532 516
533 pld_pep_mem: pld-pep@81f30000 517 pld_pep_mem: pld-pep@81f30000 {
534 reg = <0x0 0x81f30000 518 reg = <0x0 0x81f30000 0x0 0x6000>;
535 no-map; 519 no-map;
536 }; 520 };
537 521
538 pld_gmu_mem: pld-gmu@81f36000 522 pld_gmu_mem: pld-gmu@81f36000 {
539 reg = <0x0 0x81f36000 523 reg = <0x0 0x81f36000 0x0 0x1000>;
540 no-map; 524 no-map;
541 }; 525 };
542 526
543 pld_pdp_mem: pld-pdp@81f37000 527 pld_pdp_mem: pld-pdp@81f37000 {
544 reg = <0x0 0x81f37000 528 reg = <0x0 0x81f37000 0x0 0x1000>;
545 no-map; 529 no-map;
546 }; 530 };
547 531
548 tz_stat_mem: tz-stat@82700000 532 tz_stat_mem: tz-stat@82700000 {
549 reg = <0x0 0x82700000 533 reg = <0x0 0x82700000 0x0 0x100000>;
550 no-map; 534 no-map;
551 }; 535 };
552 536
553 xbl_tmp_buffer_mem: xbl-tmp-bu 537 xbl_tmp_buffer_mem: xbl-tmp-buffer@82800000 {
554 reg = <0x0 0x82800000 538 reg = <0x0 0x82800000 0x0 0xc00000>;
555 no-map; 539 no-map;
556 }; 540 };
557 541
558 adsp_rpc_remote_heap_mem: adsp 542 adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@84b00000 {
559 reg = <0x0 0x84b00000 543 reg = <0x0 0x84b00000 0x0 0x800000>;
560 no-map; 544 no-map;
561 }; 545 };
562 546
563 spu_secure_shared_memory_mem: 547 spu_secure_shared_memory_mem: spu-secure-shared-memory@85300000 {
564 reg = <0x0 0x85300000 548 reg = <0x0 0x85300000 0x0 0x80000>;
565 no-map; 549 no-map;
566 }; 550 };
567 551
568 adsp_boot_dtb_mem: adsp-boot-d 552 adsp_boot_dtb_mem: adsp-boot-dtb@866c0000 {
569 reg = <0x0 0x866c0000 553 reg = <0x0 0x866c0000 0x0 0x40000>;
570 no-map; 554 no-map;
571 }; 555 };
572 556
573 spss_region_mem: spss-region@8 557 spss_region_mem: spss-region@86700000 {
574 reg = <0x0 0x86700000 558 reg = <0x0 0x86700000 0x0 0x400000>;
575 no-map; 559 no-map;
576 }; 560 };
577 561
578 adsp_boot_mem: adsp-boot@86b00 562 adsp_boot_mem: adsp-boot@86b00000 {
579 reg = <0x0 0x86b00000 563 reg = <0x0 0x86b00000 0x0 0xc00000>;
580 no-map; 564 no-map;
581 }; 565 };
582 566
583 video_mem: video@87700000 { 567 video_mem: video@87700000 {
584 reg = <0x0 0x87700000 568 reg = <0x0 0x87700000 0x0 0x700000>;
585 no-map; 569 no-map;
586 }; 570 };
587 571
588 adspslpi_mem: adspslpi@87e0000 572 adspslpi_mem: adspslpi@87e00000 {
589 reg = <0x0 0x87e00000 573 reg = <0x0 0x87e00000 0x0 0x3a00000>;
590 no-map; 574 no-map;
591 }; 575 };
592 576
593 q6_adsp_dtb_mem: q6-adsp-dtb@8 577 q6_adsp_dtb_mem: q6-adsp-dtb@8b800000 {
594 reg = <0x0 0x8b800000 578 reg = <0x0 0x8b800000 0x0 0x80000>;
595 no-map; 579 no-map;
596 }; 580 };
597 581
598 cdsp_mem: cdsp@8b900000 { 582 cdsp_mem: cdsp@8b900000 {
599 reg = <0x0 0x8b900000 583 reg = <0x0 0x8b900000 0x0 0x2000000>;
600 no-map; 584 no-map;
601 }; 585 };
602 586
603 q6_cdsp_dtb_mem: q6-cdsp-dtb@8 587 q6_cdsp_dtb_mem: q6-cdsp-dtb@8d900000 {
604 reg = <0x0 0x8d900000 588 reg = <0x0 0x8d900000 0x0 0x80000>;
605 no-map; 589 no-map;
606 }; 590 };
607 591
608 gpu_microcode_mem: gpu-microco 592 gpu_microcode_mem: gpu-microcode@8d9fe000 {
609 reg = <0x0 0x8d9fe000 593 reg = <0x0 0x8d9fe000 0x0 0x2000>;
610 no-map; 594 no-map;
611 }; 595 };
612 596
613 cvp_mem: cvp@8da00000 { 597 cvp_mem: cvp@8da00000 {
614 reg = <0x0 0x8da00000 598 reg = <0x0 0x8da00000 0x0 0x700000>;
615 no-map; 599 no-map;
616 }; 600 };
617 601
618 camera_mem: camera@8e100000 { 602 camera_mem: camera@8e100000 {
619 reg = <0x0 0x8e100000 603 reg = <0x0 0x8e100000 0x0 0x800000>;
620 no-map; 604 no-map;
621 }; 605 };
622 606
623 av1_encoder_mem: av1-encoder@8 607 av1_encoder_mem: av1-encoder@8e900000 {
624 reg = <0x0 0x8e900000 608 reg = <0x0 0x8e900000 0x0 0x700000>;
625 no-map; 609 no-map;
626 }; 610 };
627 611
628 reserved-region@8f000000 { 612 reserved-region@8f000000 {
629 reg = <0x0 0x8f000000 613 reg = <0x0 0x8f000000 0x0 0xa00000>;
630 no-map; 614 no-map;
631 }; 615 };
632 616
633 wpss_mem: wpss@8fa00000 { 617 wpss_mem: wpss@8fa00000 {
634 reg = <0x0 0x8fa00000 618 reg = <0x0 0x8fa00000 0x0 0x1900000>;
635 no-map; 619 no-map;
636 }; 620 };
637 621
638 q6_wpss_dtb_mem: q6-wpss-dtb@9 622 q6_wpss_dtb_mem: q6-wpss-dtb@91300000 {
639 reg = <0x0 0x91300000 623 reg = <0x0 0x91300000 0x0 0x80000>;
640 no-map; 624 no-map;
641 }; 625 };
642 626
643 xbl_sc_mem: xbl-sc@d8000000 { 627 xbl_sc_mem: xbl-sc@d8000000 {
644 reg = <0x0 0xd8000000 628 reg = <0x0 0xd8000000 0x0 0x40000>;
645 no-map; 629 no-map;
646 }; 630 };
647 631
648 reserved-region@d8040000 { 632 reserved-region@d8040000 {
649 reg = <0x0 0xd8040000 633 reg = <0x0 0xd8040000 0x0 0xa0000>;
650 no-map; 634 no-map;
651 }; 635 };
652 636
653 qtee_mem: qtee@d80e0000 { 637 qtee_mem: qtee@d80e0000 {
654 reg = <0x0 0xd80e0000 638 reg = <0x0 0xd80e0000 0x0 0x520000>;
655 no-map; 639 no-map;
656 }; 640 };
657 641
658 ta_mem: ta@d8600000 { 642 ta_mem: ta@d8600000 {
659 reg = <0x0 0xd8600000 643 reg = <0x0 0xd8600000 0x0 0x8a00000>;
660 no-map; 644 no-map;
661 }; 645 };
662 646
663 tags_mem1: tags@e1000000 { 647 tags_mem1: tags@e1000000 {
664 reg = <0x0 0xe1000000 648 reg = <0x0 0xe1000000 0x0 0x26a0000>;
665 no-map; 649 no-map;
666 }; 650 };
667 651
668 llcc_lpi_mem: llcc-lpi@ff80000 652 llcc_lpi_mem: llcc-lpi@ff800000 {
669 reg = <0x0 0xff800000 653 reg = <0x0 0xff800000 0x0 0x600000>;
670 no-map; 654 no-map;
671 }; 655 };
672 656
673 smem_mem: smem@ffe00000 { 657 smem_mem: smem@ffe00000 {
674 compatible = "qcom,sme 658 compatible = "qcom,smem";
675 reg = <0x0 0xffe00000 659 reg = <0x0 0xffe00000 0x0 0x200000>;
676 hwlocks = <&tcsr_mutex 660 hwlocks = <&tcsr_mutex 3>;
677 no-map; 661 no-map;
678 }; 662 };
679 }; 663 };
680 664
681 smp2p-adsp { <<
682 compatible = "qcom,smp2p"; <<
683 <<
684 interrupts-extended = <&ipcc I <<
685 I <<
686 I <<
687 <<
688 mboxes = <&ipcc IPCC_CLIENT_LP <<
689 IPCC_MPROC_SIG <<
690 <<
691 qcom,smem = <443>, <429>; <<
692 qcom,local-pid = <0>; <<
693 qcom,remote-pid = <2>; <<
694 <<
695 smp2p_adsp_out: master-kernel <<
696 qcom,entry-name = "mas <<
697 #qcom,smem-state-cells <<
698 }; <<
699 <<
700 smp2p_adsp_in: slave-kernel { <<
701 qcom,entry-name = "sla <<
702 interrupt-controller; <<
703 #interrupt-cells = <2> <<
704 }; <<
705 }; <<
706 <<
707 smp2p-cdsp { <<
708 compatible = "qcom,smp2p"; <<
709 <<
710 interrupts-extended = <&ipcc I <<
711 I <<
712 I <<
713 <<
714 mboxes = <&ipcc IPCC_CLIENT_CD <<
715 IPCC_MPROC_SIG <<
716 <<
717 qcom,smem = <94>, <432>; <<
718 qcom,local-pid = <0>; <<
719 qcom,remote-pid = <5>; <<
720 <<
721 smp2p_cdsp_out: master-kernel <<
722 qcom,entry-name = "mas <<
723 #qcom,smem-state-cells <<
724 }; <<
725 <<
726 smp2p_cdsp_in: slave-kernel { <<
727 qcom,entry-name = "sla <<
728 interrupt-controller; <<
729 #interrupt-cells = <2> <<
730 }; <<
731 }; <<
732 <<
733 soc: soc@0 { 665 soc: soc@0 {
734 compatible = "simple-bus"; 666 compatible = "simple-bus";
735 667
736 #address-cells = <2>; 668 #address-cells = <2>;
737 #size-cells = <2>; 669 #size-cells = <2>;
738 dma-ranges = <0 0 0 0 0x10 0>; 670 dma-ranges = <0 0 0 0 0x10 0>;
739 ranges = <0 0 0 0 0x10 0>; 671 ranges = <0 0 0 0 0x10 0>;
740 672
741 gcc: clock-controller@100000 { 673 gcc: clock-controller@100000 {
742 compatible = "qcom,x1e 674 compatible = "qcom,x1e80100-gcc";
743 reg = <0 0x00100000 0 675 reg = <0 0x00100000 0 0x200000>;
744 676
745 clocks = <&bi_tcxo_div 677 clocks = <&bi_tcxo_div2>,
746 <&sleep_clk>, 678 <&sleep_clk>,
747 <0>, 679 <0>,
748 <&pcie4_phy>, <<
749 <&pcie5_phy>, <<
750 <&pcie6a_phy> <<
751 <0>, 680 <0>,
752 <&usb_1_ss0_q !! 681 <0>,
753 <&usb_1_ss1_q !! 682 <0>,
754 <&usb_1_ss2_q !! 683 <0>,
>> 684 <0>,
>> 685 <0>,
>> 686 <0>;
755 687
756 power-domains = <&rpmh 688 power-domains = <&rpmhpd RPMHPD_CX>;
757 #clock-cells = <1>; 689 #clock-cells = <1>;
758 #reset-cells = <1>; 690 #reset-cells = <1>;
759 #power-domain-cells = 691 #power-domain-cells = <1>;
760 }; 692 };
761 693
762 ipcc: mailbox@408000 { <<
763 compatible = "qcom,x1e <<
764 reg = <0 0x00408000 0 <<
765 <<
766 interrupts = <GIC_SPI <<
767 interrupt-controller; <<
768 #interrupt-cells = <3> <<
769 <<
770 #mbox-cells = <2>; <<
771 }; <<
772 <<
773 gpi_dma2: dma-controller@80000 694 gpi_dma2: dma-controller@800000 {
774 compatible = "qcom,x1e 695 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma";
775 reg = <0 0x00800000 0 696 reg = <0 0x00800000 0 0x60000>;
776 697
777 interrupts = <GIC_SPI 698 interrupts = <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>,
778 <GIC_SPI 699 <GIC_SPI 789 IRQ_TYPE_LEVEL_HIGH>,
779 <GIC_SPI 700 <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>,
780 <GIC_SPI 701 <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>,
781 <GIC_SPI 702 <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>,
782 <GIC_SPI 703 <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>,
783 <GIC_SPI 704 <GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>,
784 <GIC_SPI 705 <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>,
785 <GIC_SPI 706 <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>,
786 <GIC_SPI 707 <GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH>,
787 <GIC_SPI 708 <GIC_SPI 798 IRQ_TYPE_LEVEL_HIGH>,
788 <GIC_SPI 709 <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH>;
789 710
790 dma-channels = <12>; 711 dma-channels = <12>;
791 dma-channel-mask = <0x 712 dma-channel-mask = <0x3e>;
792 #dma-cells = <3>; 713 #dma-cells = <3>;
793 714
794 iommus = <&apps_smmu 0 715 iommus = <&apps_smmu 0x436 0x0>;
795 716
796 status = "disabled"; 717 status = "disabled";
797 }; 718 };
798 719
799 qupv3_2: geniqup@8c0000 { 720 qupv3_2: geniqup@8c0000 {
800 compatible = "qcom,gen 721 compatible = "qcom,geni-se-qup";
801 reg = <0 0x008c0000 0 722 reg = <0 0x008c0000 0 0x2000>;
802 723
803 clocks = <&gcc GCC_QUP 724 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
804 <&gcc GCC_QUP 725 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
805 clock-names = "m-ahb", 726 clock-names = "m-ahb",
806 "s-ahb"; 727 "s-ahb";
807 728
808 iommus = <&apps_smmu 0 729 iommus = <&apps_smmu 0x423 0x0>;
809 730
810 #address-cells = <2>; 731 #address-cells = <2>;
811 #size-cells = <2>; 732 #size-cells = <2>;
812 ranges; 733 ranges;
813 734
814 status = "disabled"; 735 status = "disabled";
815 736
816 i2c16: i2c@880000 { 737 i2c16: i2c@880000 {
817 compatible = " 738 compatible = "qcom,geni-i2c";
818 reg = <0 0x008 739 reg = <0 0x00880000 0 0x4000>;
819 740
820 interrupts = < 741 interrupts = <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>;
821 742
822 clocks = <&gcc 743 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
823 clock-names = 744 clock-names = "se";
824 745
825 interconnects 746 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
826 747 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
827 748 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
828 749 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
829 750 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
830 751 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
831 interconnect-n 752 interconnect-names = "qup-core",
832 753 "qup-config",
833 754 "qup-memory";
834 755
835 dmas = <&gpi_d 756 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
836 <&gpi_d 757 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
837 dma-names = "t 758 dma-names = "tx",
838 "r 759 "rx";
839 760
840 pinctrl-0 = <& 761 pinctrl-0 = <&qup_i2c16_data_clk>;
841 pinctrl-names 762 pinctrl-names = "default";
842 763
843 #address-cells 764 #address-cells = <1>;
844 #size-cells = 765 #size-cells = <0>;
845 766
846 status = "disa 767 status = "disabled";
847 }; 768 };
848 769
849 spi16: spi@880000 { 770 spi16: spi@880000 {
850 compatible = " 771 compatible = "qcom,geni-spi";
851 reg = <0 0x008 772 reg = <0 0x00880000 0 0x4000>;
852 773
853 interrupts = < 774 interrupts = <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>;
854 775
855 clocks = <&gcc 776 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
856 clock-names = 777 clock-names = "se";
857 778
858 interconnects 779 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
859 780 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
860 781 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
861 782 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
862 783 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
863 784 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
864 interconnect-n 785 interconnect-names = "qup-core",
865 786 "qup-config",
866 787 "qup-memory";
867 788
868 dmas = <&gpi_d 789 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
869 <&gpi_d 790 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
870 dma-names = "t 791 dma-names = "tx",
871 "r 792 "rx";
872 793
873 pinctrl-0 = <& 794 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>;
874 pinctrl-names 795 pinctrl-names = "default";
875 796
876 #address-cells 797 #address-cells = <1>;
877 #size-cells = 798 #size-cells = <0>;
878 799
879 status = "disa 800 status = "disabled";
880 }; 801 };
881 802
882 i2c17: i2c@884000 { 803 i2c17: i2c@884000 {
883 compatible = " 804 compatible = "qcom,geni-i2c";
884 reg = <0 0x008 805 reg = <0 0x00884000 0 0x4000>;
885 806
886 interrupts = < 807 interrupts = <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>;
887 808
888 clocks = <&gcc 809 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
889 clock-names = 810 clock-names = "se";
890 811
891 interconnects 812 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
892 813 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
893 814 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
894 815 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
895 816 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
896 817 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
897 interconnect-n 818 interconnect-names = "qup-core",
898 819 "qup-config",
899 820 "qup-memory";
900 821
901 dmas = <&gpi_d 822 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
902 <&gpi_d 823 <&gpi_dma2 1 1 QCOM_GPI_I2C>;
903 dma-names = "t 824 dma-names = "tx",
904 "r 825 "rx";
905 826
906 pinctrl-0 = <& 827 pinctrl-0 = <&qup_i2c17_data_clk>;
907 pinctrl-names 828 pinctrl-names = "default";
908 829
909 #address-cells 830 #address-cells = <1>;
910 #size-cells = 831 #size-cells = <0>;
911 832
912 status = "disa 833 status = "disabled";
913 }; 834 };
914 835
915 spi17: spi@884000 { 836 spi17: spi@884000 {
916 compatible = " 837 compatible = "qcom,geni-spi";
917 reg = <0 0x008 838 reg = <0 0x00884000 0 0x4000>;
918 839
919 interrupts = < 840 interrupts = <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>;
920 841
921 clocks = <&gcc 842 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
922 clock-names = 843 clock-names = "se";
923 844
924 interconnects 845 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
925 846 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
926 847 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
927 848 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
928 849 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
929 850 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
930 interconnect-n 851 interconnect-names = "qup-core",
931 852 "qup-config",
932 853 "qup-memory";
933 854
934 dmas = <&gpi_d 855 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
935 <&gpi_d 856 <&gpi_dma2 1 1 QCOM_GPI_SPI>;
936 dma-names = "t 857 dma-names = "tx",
937 "r 858 "rx";
938 859
939 pinctrl-0 = <& 860 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>;
940 pinctrl-names 861 pinctrl-names = "default";
941 862
942 #address-cells 863 #address-cells = <1>;
943 #size-cells = 864 #size-cells = <0>;
944 865
945 status = "disa 866 status = "disabled";
946 }; 867 };
947 868
948 i2c18: i2c@888000 { 869 i2c18: i2c@888000 {
949 compatible = " 870 compatible = "qcom,geni-i2c";
950 reg = <0 0x008 871 reg = <0 0x00888000 0 0x4000>;
951 872
952 interrupts = < 873 interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>;
953 874
954 clocks = <&gcc 875 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
955 clock-names = 876 clock-names = "se";
956 877
957 interconnects 878 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
958 879 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
959 880 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
960 881 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
961 882 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
962 883 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
963 interconnect-n 884 interconnect-names = "qup-core",
964 885 "qup-config",
965 886 "qup-memory";
966 887
967 dmas = <&gpi_d 888 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
968 <&gpi_d 889 <&gpi_dma2 1 2 QCOM_GPI_I2C>;
969 dma-names = "t 890 dma-names = "tx",
970 "r 891 "rx";
971 892
972 pinctrl-0 = <& 893 pinctrl-0 = <&qup_i2c18_data_clk>;
973 pinctrl-names 894 pinctrl-names = "default";
974 895
975 #address-cells 896 #address-cells = <1>;
976 #size-cells = 897 #size-cells = <0>;
977 898
978 status = "disa 899 status = "disabled";
979 }; 900 };
980 901
981 spi18: spi@888000 { 902 spi18: spi@888000 {
982 compatible = " 903 compatible = "qcom,geni-spi";
983 reg = <0 0x008 904 reg = <0 0x00888000 0 0x4000>;
984 905
985 interrupts = < 906 interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>;
986 907
987 clocks = <&gcc 908 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
988 clock-names = 909 clock-names = "se";
989 910
990 interconnects 911 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
991 912 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
992 913 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
993 914 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
994 915 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
995 916 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
996 interconnect-n 917 interconnect-names = "qup-core",
997 918 "qup-config",
998 919 "qup-memory";
999 920
1000 dmas = <&gpi_ 921 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
1001 <&gpi_ 922 <&gpi_dma2 1 2 QCOM_GPI_SPI>;
1002 dma-names = " 923 dma-names = "tx",
1003 " 924 "rx";
1004 925
1005 pinctrl-0 = < 926 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>;
1006 pinctrl-names 927 pinctrl-names = "default";
1007 928
1008 #address-cell 929 #address-cells = <1>;
1009 #size-cells = 930 #size-cells = <0>;
1010 931
1011 status = "dis 932 status = "disabled";
1012 }; 933 };
1013 934
1014 i2c19: i2c@88c000 { 935 i2c19: i2c@88c000 {
1015 compatible = 936 compatible = "qcom,geni-i2c";
1016 reg = <0 0x00 937 reg = <0 0x0088c000 0 0x4000>;
1017 938
1018 interrupts = 939 interrupts = <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>;
1019 940
1020 clocks = <&gc 941 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1021 clock-names = 942 clock-names = "se";
1022 943
1023 interconnects 944 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1024 945 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1025 946 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1026 947 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1027 948 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1028 949 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1029 interconnect- 950 interconnect-names = "qup-core",
1030 951 "qup-config",
1031 952 "qup-memory";
1032 953
1033 dmas = <&gpi_ 954 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
1034 <&gpi_ 955 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
1035 dma-names = " 956 dma-names = "tx",
1036 " 957 "rx";
1037 958
1038 pinctrl-0 = < 959 pinctrl-0 = <&qup_i2c19_data_clk>;
1039 pinctrl-names 960 pinctrl-names = "default";
1040 961
1041 #address-cell 962 #address-cells = <1>;
1042 #size-cells = 963 #size-cells = <0>;
1043 964
1044 status = "dis 965 status = "disabled";
1045 }; 966 };
1046 967
1047 spi19: spi@88c000 { 968 spi19: spi@88c000 {
1048 compatible = 969 compatible = "qcom,geni-spi";
1049 reg = <0 0x00 970 reg = <0 0x0088c000 0 0x4000>;
1050 971
1051 interrupts = 972 interrupts = <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>;
1052 973
1053 clocks = <&gc 974 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1054 clock-names = 975 clock-names = "se";
1055 976
1056 interconnects 977 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1057 978 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1058 979 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1059 980 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1060 981 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1061 982 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1062 interconnect- 983 interconnect-names = "qup-core",
1063 984 "qup-config",
1064 985 "qup-memory";
1065 986
1066 dmas = <&gpi_ 987 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
1067 <&gpi_ 988 <&gpi_dma2 1 3 QCOM_GPI_SPI>;
1068 dma-names = " 989 dma-names = "tx",
1069 " 990 "rx";
1070 991
1071 pinctrl-0 = < 992 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>;
1072 pinctrl-names 993 pinctrl-names = "default";
1073 994
1074 #address-cell 995 #address-cells = <1>;
1075 #size-cells = 996 #size-cells = <0>;
1076 997
1077 status = "dis 998 status = "disabled";
1078 }; 999 };
1079 1000
1080 i2c20: i2c@890000 { 1001 i2c20: i2c@890000 {
1081 compatible = 1002 compatible = "qcom,geni-i2c";
1082 reg = <0 0x00 1003 reg = <0 0x00890000 0 0x4000>;
1083 1004
1084 interrupts = 1005 interrupts = <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>;
1085 1006
1086 clocks = <&gc 1007 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1087 clock-names = 1008 clock-names = "se";
1088 1009
1089 interconnects 1010 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1090 1011 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1091 1012 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1092 1013 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1093 1014 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1094 1015 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1095 interconnect- 1016 interconnect-names = "qup-core",
1096 1017 "qup-config",
1097 1018 "qup-memory";
1098 1019
1099 dmas = <&gpi_ 1020 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1100 <&gpi_ 1021 <&gpi_dma2 1 4 QCOM_GPI_I2C>;
1101 dma-names = " 1022 dma-names = "tx",
1102 " 1023 "rx";
1103 1024
1104 pinctrl-0 = < 1025 pinctrl-0 = <&qup_i2c20_data_clk>;
1105 pinctrl-names 1026 pinctrl-names = "default";
1106 1027
1107 #address-cell 1028 #address-cells = <1>;
1108 #size-cells = 1029 #size-cells = <0>;
1109 1030
1110 status = "dis 1031 status = "disabled";
1111 }; 1032 };
1112 1033
1113 spi20: spi@890000 { 1034 spi20: spi@890000 {
1114 compatible = 1035 compatible = "qcom,geni-spi";
1115 reg = <0 0x00 1036 reg = <0 0x00890000 0 0x4000>;
1116 1037
1117 interrupts = 1038 interrupts = <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>;
1118 1039
1119 clocks = <&gc 1040 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1120 clock-names = 1041 clock-names = "se";
1121 1042
1122 interconnects 1043 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1123 1044 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1124 1045 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1125 1046 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1126 1047 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1127 1048 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1128 interconnect- 1049 interconnect-names = "qup-core",
1129 1050 "qup-config",
1130 1051 "qup-memory";
1131 1052
1132 dmas = <&gpi_ 1053 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
1133 <&gpi_ 1054 <&gpi_dma2 1 4 QCOM_GPI_SPI>;
1134 dma-names = " 1055 dma-names = "tx",
1135 " 1056 "rx";
1136 1057
1137 pinctrl-0 = < 1058 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>;
1138 pinctrl-names 1059 pinctrl-names = "default";
1139 1060
1140 #address-cell 1061 #address-cells = <1>;
1141 #size-cells = 1062 #size-cells = <0>;
1142 1063
1143 status = "dis 1064 status = "disabled";
1144 }; 1065 };
1145 1066
1146 i2c21: i2c@894000 { 1067 i2c21: i2c@894000 {
1147 compatible = 1068 compatible = "qcom,geni-i2c";
1148 reg = <0 0x00 1069 reg = <0 0x00894000 0 0x4000>;
1149 1070
1150 interrupts = 1071 interrupts = <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>;
1151 1072
1152 clocks = <&gc 1073 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1153 clock-names = 1074 clock-names = "se";
1154 1075
1155 interconnects 1076 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1156 1077 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1157 1078 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1158 1079 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1159 1080 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1160 1081 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1161 interconnect- 1082 interconnect-names = "qup-core",
1162 1083 "qup-config",
1163 1084 "qup-memory";
1164 1085
1165 dmas = <&gpi_ 1086 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1166 <&gpi_ 1087 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1167 dma-names = " 1088 dma-names = "tx",
1168 " 1089 "rx";
1169 1090
1170 pinctrl-0 = < 1091 pinctrl-0 = <&qup_i2c21_data_clk>;
1171 pinctrl-names 1092 pinctrl-names = "default";
1172 1093
1173 #address-cell 1094 #address-cells = <1>;
1174 #size-cells = 1095 #size-cells = <0>;
1175 1096
1176 status = "dis 1097 status = "disabled";
1177 }; 1098 };
1178 1099
1179 spi21: spi@894000 { 1100 spi21: spi@894000 {
1180 compatible = 1101 compatible = "qcom,geni-spi";
1181 reg = <0 0x00 1102 reg = <0 0x00894000 0 0x4000>;
1182 1103
1183 interrupts = 1104 interrupts = <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>;
1184 1105
1185 clocks = <&gc 1106 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1186 clock-names = 1107 clock-names = "se";
1187 1108
1188 interconnects 1109 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1189 1110 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1190 1111 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1191 1112 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1192 1113 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1193 1114 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1194 interconnect- 1115 interconnect-names = "qup-core",
1195 1116 "qup-config",
1196 1117 "qup-memory";
1197 1118
1198 dmas = <&gpi_ 1119 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1199 <&gpi_ 1120 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1200 dma-names = " 1121 dma-names = "tx",
1201 " 1122 "rx";
1202 1123
1203 pinctrl-0 = < 1124 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>;
1204 pinctrl-names 1125 pinctrl-names = "default";
1205 1126
1206 #address-cell 1127 #address-cells = <1>;
1207 #size-cells = 1128 #size-cells = <0>;
1208 1129
1209 status = "dis 1130 status = "disabled";
1210 }; 1131 };
1211 1132
1212 uart21: serial@894000 1133 uart21: serial@894000 {
1213 compatible = 1134 compatible = "qcom,geni-uart";
1214 reg = <0 0x00 1135 reg = <0 0x00894000 0 0x4000>;
1215 1136
1216 interrupts = 1137 interrupts = <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>;
1217 1138
1218 clocks = <&gc 1139 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1219 clock-names = 1140 clock-names = "se";
1220 1141
1221 interconnects !! 1142 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1222 1143 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1223 1144 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1224 1145 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
1225 interconnect- 1146 interconnect-names = "qup-core",
1226 1147 "qup-config";
1227 1148
1228 pinctrl-0 = < 1149 pinctrl-0 = <&qup_uart21_default>;
1229 pinctrl-names 1150 pinctrl-names = "default";
1230 1151
1231 status = "dis 1152 status = "disabled";
1232 }; 1153 };
1233 1154
1234 i2c22: i2c@898000 { 1155 i2c22: i2c@898000 {
1235 compatible = 1156 compatible = "qcom,geni-i2c";
1236 reg = <0 0x00 1157 reg = <0 0x00898000 0 0x4000>;
1237 1158
1238 interrupts = 1159 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
1239 1160
1240 clocks = <&gc 1161 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1241 clock-names = 1162 clock-names = "se";
1242 1163
1243 interconnects 1164 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1244 1165 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1245 1166 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1246 1167 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1247 1168 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1248 1169 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1249 interconnect- 1170 interconnect-names = "qup-core",
1250 1171 "qup-config",
1251 1172 "qup-memory";
1252 1173
1253 dmas = <&gpi_ 1174 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>,
1254 <&gpi_ 1175 <&gpi_dma2 1 6 QCOM_GPI_I2C>;
1255 dma-names = " 1176 dma-names = "tx",
1256 " 1177 "rx";
1257 1178
1258 pinctrl-0 = < 1179 pinctrl-0 = <&qup_i2c22_data_clk>;
1259 pinctrl-names 1180 pinctrl-names = "default";
1260 1181
1261 #address-cell 1182 #address-cells = <1>;
1262 #size-cells = 1183 #size-cells = <0>;
1263 1184
1264 status = "dis 1185 status = "disabled";
1265 }; 1186 };
1266 1187
1267 spi22: spi@898000 { 1188 spi22: spi@898000 {
1268 compatible = 1189 compatible = "qcom,geni-spi";
1269 reg = <0 0x00 1190 reg = <0 0x00898000 0 0x4000>;
1270 1191
1271 interrupts = 1192 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
1272 1193
1273 clocks = <&gc 1194 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1274 clock-names = 1195 clock-names = "se";
1275 1196
1276 interconnects 1197 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1277 1198 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1278 1199 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1279 1200 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1280 1201 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1281 1202 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1282 interconnect- 1203 interconnect-names = "qup-core",
1283 1204 "qup-config",
1284 1205 "qup-memory";
1285 1206
1286 dmas = <&gpi_ 1207 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>,
1287 <&gpi_ 1208 <&gpi_dma2 1 6 QCOM_GPI_SPI>;
1288 dma-names = " 1209 dma-names = "tx",
1289 " 1210 "rx";
1290 1211
1291 pinctrl-0 = < 1212 pinctrl-0 = <&qup_spi22_data_clk>, <&qup_spi22_cs>;
1292 pinctrl-names 1213 pinctrl-names = "default";
1293 1214
1294 #address-cell 1215 #address-cells = <1>;
1295 #size-cells = 1216 #size-cells = <0>;
1296 1217
1297 status = "dis 1218 status = "disabled";
1298 }; 1219 };
1299 1220
1300 i2c23: i2c@89c000 { 1221 i2c23: i2c@89c000 {
1301 compatible = 1222 compatible = "qcom,geni-i2c";
1302 reg = <0 0x00 1223 reg = <0 0x0089c000 0 0x4000>;
1303 1224
1304 interrupts = 1225 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
1305 1226
1306 clocks = <&gc 1227 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
1307 clock-names = 1228 clock-names = "se";
1308 1229
1309 interconnects 1230 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1310 1231 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1311 1232 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1312 1233 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1313 1234 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1314 1235 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1315 interconnect- 1236 interconnect-names = "qup-core",
1316 1237 "qup-config",
1317 1238 "qup-memory";
1318 1239
1319 dmas = <&gpi_ 1240 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>,
1320 <&gpi_ 1241 <&gpi_dma2 1 7 QCOM_GPI_I2C>;
1321 dma-names = " 1242 dma-names = "tx",
1322 " 1243 "rx";
1323 1244
1324 pinctrl-0 = < 1245 pinctrl-0 = <&qup_i2c23_data_clk>;
1325 pinctrl-names 1246 pinctrl-names = "default";
1326 1247
1327 #address-cell 1248 #address-cells = <1>;
1328 #size-cells = 1249 #size-cells = <0>;
1329 1250
1330 status = "dis 1251 status = "disabled";
1331 }; 1252 };
1332 1253
1333 spi23: spi@89c000 { 1254 spi23: spi@89c000 {
1334 compatible = 1255 compatible = "qcom,geni-spi";
1335 reg = <0 0x00 1256 reg = <0 0x0089c000 0 0x4000>;
1336 1257
1337 interrupts = 1258 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
1338 1259
1339 clocks = <&gc 1260 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
1340 clock-names = 1261 clock-names = "se";
1341 1262
1342 interconnects 1263 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1343 1264 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1344 1265 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1345 1266 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1346 1267 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1347 1268 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1348 interconnect- 1269 interconnect-names = "qup-core",
1349 1270 "qup-config",
1350 1271 "qup-memory";
1351 1272
1352 dmas = <&gpi_ 1273 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>,
1353 <&gpi_ 1274 <&gpi_dma2 1 7 QCOM_GPI_SPI>;
1354 dma-names = " 1275 dma-names = "tx",
1355 " 1276 "rx";
1356 1277
1357 pinctrl-0 = < 1278 pinctrl-0 = <&qup_spi23_data_clk>, <&qup_spi23_cs>;
1358 pinctrl-names 1279 pinctrl-names = "default";
1359 1280
1360 #address-cell 1281 #address-cells = <1>;
1361 #size-cells = 1282 #size-cells = <0>;
1362 1283
1363 status = "dis 1284 status = "disabled";
1364 }; 1285 };
1365 }; 1286 };
1366 1287
1367 gpi_dma1: dma-controller@a000 1288 gpi_dma1: dma-controller@a00000 {
1368 compatible = "qcom,x1 1289 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma";
1369 reg = <0 0x00a00000 0 1290 reg = <0 0x00a00000 0 0x60000>;
1370 1291
1371 interrupts = <GIC_SPI 1292 interrupts = <GIC_SPI 776 IRQ_TYPE_LEVEL_HIGH>,
1372 <GIC_SPI 1293 <GIC_SPI 777 IRQ_TYPE_LEVEL_HIGH>,
1373 <GIC_SPI 1294 <GIC_SPI 778 IRQ_TYPE_LEVEL_HIGH>,
1374 <GIC_SPI 1295 <GIC_SPI 779 IRQ_TYPE_LEVEL_HIGH>,
1375 <GIC_SPI 1296 <GIC_SPI 780 IRQ_TYPE_LEVEL_HIGH>,
1376 <GIC_SPI 1297 <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>,
1377 <GIC_SPI 1298 <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>,
1378 <GIC_SPI 1299 <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>,
1379 <GIC_SPI 1300 <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>,
1380 <GIC_SPI 1301 <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>,
1381 <GIC_SPI 1302 <GIC_SPI 786 IRQ_TYPE_LEVEL_HIGH>,
1382 <GIC_SPI 1303 <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>;
1383 1304
1384 dma-channels = <12>; 1305 dma-channels = <12>;
1385 dma-channel-mask = <0 1306 dma-channel-mask = <0x3e>;
1386 #dma-cells = <3>; 1307 #dma-cells = <3>;
1387 1308
1388 iommus = <&apps_smmu 1309 iommus = <&apps_smmu 0x136 0x0>;
1389 1310
1390 status = "disabled"; 1311 status = "disabled";
1391 }; 1312 };
1392 1313
1393 qupv3_1: geniqup@ac0000 { 1314 qupv3_1: geniqup@ac0000 {
1394 compatible = "qcom,ge 1315 compatible = "qcom,geni-se-qup";
1395 reg = <0 0x00ac0000 0 1316 reg = <0 0x00ac0000 0 0x2000>;
1396 1317
1397 clocks = <&gcc GCC_QU 1318 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1398 <&gcc GCC_QU 1319 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1399 clock-names = "m-ahb" 1320 clock-names = "m-ahb",
1400 "s-ahb" 1321 "s-ahb";
1401 1322
1402 iommus = <&apps_smmu 1323 iommus = <&apps_smmu 0x123 0x0>;
1403 1324
1404 #address-cells = <2>; 1325 #address-cells = <2>;
1405 #size-cells = <2>; 1326 #size-cells = <2>;
1406 ranges; 1327 ranges;
1407 1328
1408 status = "disabled"; 1329 status = "disabled";
1409 1330
1410 i2c8: i2c@a80000 { 1331 i2c8: i2c@a80000 {
1411 compatible = 1332 compatible = "qcom,geni-i2c";
1412 reg = <0 0x00 1333 reg = <0 0x00a80000 0 0x4000>;
1413 1334
1414 interrupts = 1335 interrupts = <GIC_SPI 800 IRQ_TYPE_LEVEL_HIGH>;
1415 1336
1416 clocks = <&gc 1337 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1417 clock-names = 1338 clock-names = "se";
1418 1339
1419 interconnects 1340 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1420 1341 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1421 1342 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1422 1343 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1423 1344 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1424 1345 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1425 interconnect- 1346 interconnect-names = "qup-core",
1426 1347 "qup-config",
1427 1348 "qup-memory";
1428 1349
1429 dmas = <&gpi_ 1350 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1430 <&gpi_ 1351 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1431 dma-names = " 1352 dma-names = "tx",
1432 " 1353 "rx";
1433 1354
1434 pinctrl-0 = < 1355 pinctrl-0 = <&qup_i2c8_data_clk>;
1435 pinctrl-names 1356 pinctrl-names = "default";
1436 1357
1437 #address-cell 1358 #address-cells = <1>;
1438 #size-cells = 1359 #size-cells = <0>;
1439 1360
1440 status = "dis 1361 status = "disabled";
1441 }; 1362 };
1442 1363
1443 spi8: spi@a80000 { 1364 spi8: spi@a80000 {
1444 compatible = 1365 compatible = "qcom,geni-spi";
1445 reg = <0 0x00 1366 reg = <0 0x00a80000 0 0x4000>;
1446 1367
1447 interrupts = 1368 interrupts = <GIC_SPI 800 IRQ_TYPE_LEVEL_HIGH>;
1448 1369
1449 clocks = <&gc 1370 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1450 clock-names = 1371 clock-names = "se";
1451 1372
1452 interconnects 1373 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1453 1374 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1454 1375 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1455 1376 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1456 1377 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1457 1378 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1458 interconnect- 1379 interconnect-names = "qup-core",
1459 1380 "qup-config",
1460 1381 "qup-memory";
1461 1382
1462 dmas = <&gpi_ 1383 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1463 <&gpi_ 1384 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1464 dma-names = " 1385 dma-names = "tx",
1465 " 1386 "rx";
1466 1387
1467 pinctrl-0 = < 1388 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1468 pinctrl-names 1389 pinctrl-names = "default";
1469 1390
1470 #address-cell 1391 #address-cells = <1>;
1471 #size-cells = 1392 #size-cells = <0>;
1472 1393
1473 status = "dis 1394 status = "disabled";
1474 }; 1395 };
1475 1396
1476 i2c9: i2c@a84000 { 1397 i2c9: i2c@a84000 {
1477 compatible = 1398 compatible = "qcom,geni-i2c";
1478 reg = <0 0x00 1399 reg = <0 0x00a84000 0 0x4000>;
1479 1400
1480 interrupts = 1401 interrupts = <GIC_SPI 801 IRQ_TYPE_LEVEL_HIGH>;
1481 1402
1482 clocks = <&gc 1403 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1483 clock-names = 1404 clock-names = "se";
1484 1405
1485 interconnects 1406 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1486 1407 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1487 1408 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1488 1409 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1489 1410 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1490 1411 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1491 interconnect- 1412 interconnect-names = "qup-core",
1492 1413 "qup-config",
1493 1414 "qup-memory";
1494 1415
1495 dmas = <&gpi_ 1416 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1496 <&gpi_ 1417 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1497 dma-names = " 1418 dma-names = "tx",
1498 " 1419 "rx";
1499 1420
1500 pinctrl-0 = < 1421 pinctrl-0 = <&qup_i2c9_data_clk>;
1501 pinctrl-names 1422 pinctrl-names = "default";
1502 1423
1503 #address-cell 1424 #address-cells = <1>;
1504 #size-cells = 1425 #size-cells = <0>;
1505 1426
1506 status = "dis 1427 status = "disabled";
1507 }; 1428 };
1508 1429
1509 spi9: spi@a84000 { 1430 spi9: spi@a84000 {
1510 compatible = 1431 compatible = "qcom,geni-spi";
1511 reg = <0 0x00 1432 reg = <0 0x00a84000 0 0x4000>;
1512 1433
1513 interrupts = 1434 interrupts = <GIC_SPI 801 IRQ_TYPE_LEVEL_HIGH>;
1514 1435
1515 clocks = <&gc 1436 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1516 clock-names = 1437 clock-names = "se";
1517 1438
1518 interconnects 1439 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1519 1440 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1520 1441 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1521 1442 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1522 1443 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1523 1444 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1524 interconnect- 1445 interconnect-names = "qup-core",
1525 1446 "qup-config",
1526 1447 "qup-memory";
1527 1448
1528 dmas = <&gpi_ 1449 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1529 <&gpi_ 1450 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1530 dma-names = " 1451 dma-names = "tx",
1531 " 1452 "rx";
1532 1453
1533 pinctrl-0 = < 1454 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1534 pinctrl-names 1455 pinctrl-names = "default";
1535 1456
1536 #address-cell 1457 #address-cells = <1>;
1537 #size-cells = 1458 #size-cells = <0>;
1538 1459
1539 status = "dis 1460 status = "disabled";
1540 }; 1461 };
1541 1462
1542 i2c10: i2c@a88000 { 1463 i2c10: i2c@a88000 {
1543 compatible = 1464 compatible = "qcom,geni-i2c";
1544 reg = <0 0x00 1465 reg = <0 0x00a88000 0 0x4000>;
1545 1466
1546 interrupts = 1467 interrupts = <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>;
1547 1468
1548 clocks = <&gc 1469 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1549 clock-names = 1470 clock-names = "se";
1550 1471
1551 interconnects 1472 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1552 1473 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1553 1474 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1554 1475 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1555 1476 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1556 1477 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1557 interconnect- 1478 interconnect-names = "qup-core",
1558 1479 "qup-config",
1559 1480 "qup-memory";
1560 1481
1561 dmas = <&gpi_ 1482 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1562 <&gpi_ 1483 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1563 dma-names = " 1484 dma-names = "tx",
1564 " 1485 "rx";
1565 1486
1566 pinctrl-0 = < 1487 pinctrl-0 = <&qup_i2c10_data_clk>;
1567 pinctrl-names 1488 pinctrl-names = "default";
1568 1489
1569 #address-cell 1490 #address-cells = <1>;
1570 #size-cells = 1491 #size-cells = <0>;
1571 1492
1572 status = "dis 1493 status = "disabled";
1573 }; 1494 };
1574 1495
1575 spi10: spi@a88000 { 1496 spi10: spi@a88000 {
1576 compatible = 1497 compatible = "qcom,geni-spi";
1577 reg = <0 0x00 1498 reg = <0 0x00a88000 0 0x4000>;
1578 1499
1579 interrupts = 1500 interrupts = <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>;
1580 1501
1581 clocks = <&gc 1502 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1582 clock-names = 1503 clock-names = "se";
1583 1504
1584 interconnects 1505 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1585 1506 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1586 1507 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1587 1508 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1588 1509 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1589 1510 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1590 interconnect- 1511 interconnect-names = "qup-core",
1591 1512 "qup-config",
1592 1513 "qup-memory";
1593 1514
1594 dmas = <&gpi_ 1515 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1595 <&gpi_ 1516 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1596 dma-names = " 1517 dma-names = "tx",
1597 " 1518 "rx";
1598 1519
1599 pinctrl-0 = < 1520 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1600 pinctrl-names 1521 pinctrl-names = "default";
1601 1522
1602 #address-cell 1523 #address-cells = <1>;
1603 #size-cells = 1524 #size-cells = <0>;
1604 1525
1605 status = "dis 1526 status = "disabled";
1606 }; 1527 };
1607 1528
1608 i2c11: i2c@a8c000 { 1529 i2c11: i2c@a8c000 {
1609 compatible = 1530 compatible = "qcom,geni-i2c";
1610 reg = <0 0x00 1531 reg = <0 0x00a8c000 0 0x4000>;
1611 1532
1612 interrupts = 1533 interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>;
1613 1534
1614 clocks = <&gc 1535 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1615 clock-names = 1536 clock-names = "se";
1616 1537
1617 interconnects 1538 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1618 1539 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1619 1540 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1620 1541 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1621 1542 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1622 1543 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1623 interconnect- 1544 interconnect-names = "qup-core",
1624 1545 "qup-config",
1625 1546 "qup-memory";
1626 1547
1627 dmas = <&gpi_ 1548 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1628 <&gpi_ 1549 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1629 dma-names = " 1550 dma-names = "tx",
1630 " 1551 "rx";
1631 1552
1632 pinctrl-0 = < 1553 pinctrl-0 = <&qup_i2c11_data_clk>;
1633 pinctrl-names 1554 pinctrl-names = "default";
1634 1555
1635 #address-cell 1556 #address-cells = <1>;
1636 #size-cells = 1557 #size-cells = <0>;
1637 1558
1638 status = "dis 1559 status = "disabled";
1639 }; 1560 };
1640 1561
1641 spi11: spi@a8c000 { 1562 spi11: spi@a8c000 {
1642 compatible = 1563 compatible = "qcom,geni-spi";
1643 reg = <0 0x00 1564 reg = <0 0x00a8c000 0 0x4000>;
1644 1565
1645 interrupts = 1566 interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>;
1646 1567
1647 clocks = <&gc 1568 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1648 clock-names = 1569 clock-names = "se";
1649 1570
1650 interconnects 1571 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1651 1572 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1652 1573 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1653 1574 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1654 1575 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1655 1576 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1656 interconnect- 1577 interconnect-names = "qup-core",
1657 1578 "qup-config",
1658 1579 "qup-memory";
1659 1580
1660 dmas = <&gpi_ 1581 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1661 <&gpi_ 1582 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1662 dma-names = " 1583 dma-names = "tx",
1663 " 1584 "rx";
1664 1585
1665 pinctrl-0 = < 1586 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1666 pinctrl-names 1587 pinctrl-names = "default";
1667 1588
1668 #address-cell 1589 #address-cells = <1>;
1669 #size-cells = 1590 #size-cells = <0>;
1670 1591
1671 status = "dis 1592 status = "disabled";
1672 }; 1593 };
1673 1594
1674 i2c12: i2c@a90000 { 1595 i2c12: i2c@a90000 {
1675 compatible = 1596 compatible = "qcom,geni-i2c";
1676 reg = <0 0x00 1597 reg = <0 0x00a90000 0 0x4000>;
1677 1598
1678 interrupts = 1599 interrupts = <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>;
1679 1600
1680 clocks = <&gc 1601 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1681 clock-names = 1602 clock-names = "se";
1682 1603
1683 interconnects 1604 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1684 1605 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1685 1606 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1686 1607 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1687 1608 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1688 1609 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1689 interconnect- 1610 interconnect-names = "qup-core",
1690 1611 "qup-config",
1691 1612 "qup-memory";
1692 1613
1693 dmas = <&gpi_ 1614 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1694 <&gpi_ 1615 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1695 dma-names = " 1616 dma-names = "tx",
1696 " 1617 "rx";
1697 1618
1698 pinctrl-0 = < 1619 pinctrl-0 = <&qup_i2c12_data_clk>;
1699 pinctrl-names 1620 pinctrl-names = "default";
1700 1621
1701 #address-cell 1622 #address-cells = <1>;
1702 #size-cells = 1623 #size-cells = <0>;
1703 1624
1704 status = "dis 1625 status = "disabled";
1705 }; 1626 };
1706 1627
1707 spi12: spi@a90000 { 1628 spi12: spi@a90000 {
1708 compatible = 1629 compatible = "qcom,geni-spi";
1709 reg = <0 0x00 1630 reg = <0 0x00a90000 0 0x4000>;
1710 1631
1711 interrupts = 1632 interrupts = <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>;
1712 1633
1713 clocks = <&gc 1634 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1714 clock-names = 1635 clock-names = "se";
1715 1636
1716 interconnects 1637 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1717 1638 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1718 1639 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1719 1640 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1720 1641 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1721 1642 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1722 interconnect- 1643 interconnect-names = "qup-core",
1723 1644 "qup-config",
1724 1645 "qup-memory";
1725 1646
1726 dmas = <&gpi_ 1647 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1727 <&gpi_ 1648 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1728 dma-names = " 1649 dma-names = "tx",
1729 " 1650 "rx";
1730 1651
1731 pinctrl-0 = < 1652 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1732 pinctrl-names 1653 pinctrl-names = "default";
1733 1654
1734 #address-cell 1655 #address-cells = <1>;
1735 #size-cells = 1656 #size-cells = <0>;
1736 1657
1737 status = "dis 1658 status = "disabled";
1738 }; 1659 };
1739 1660
1740 i2c13: i2c@a94000 { 1661 i2c13: i2c@a94000 {
1741 compatible = 1662 compatible = "qcom,geni-i2c";
1742 reg = <0 0x00 1663 reg = <0 0x00a94000 0 0x4000>;
1743 1664
1744 interrupts = 1665 interrupts = <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>;
1745 1666
1746 clocks = <&gc 1667 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1747 clock-names = 1668 clock-names = "se";
1748 1669
1749 interconnects 1670 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1750 1671 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1751 1672 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1752 1673 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1753 1674 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1754 1675 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1755 interconnect- 1676 interconnect-names = "qup-core",
1756 1677 "qup-config",
1757 1678 "qup-memory";
1758 1679
1759 dmas = <&gpi_ 1680 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1760 <&gpi_ 1681 <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1761 dma-names = " 1682 dma-names = "tx",
1762 " 1683 "rx";
1763 1684
1764 pinctrl-0 = < 1685 pinctrl-0 = <&qup_i2c13_data_clk>;
1765 pinctrl-names 1686 pinctrl-names = "default";
1766 1687
1767 #address-cell 1688 #address-cells = <1>;
1768 #size-cells = 1689 #size-cells = <0>;
1769 1690
1770 status = "dis 1691 status = "disabled";
1771 }; 1692 };
1772 1693
1773 spi13: spi@a94000 { 1694 spi13: spi@a94000 {
1774 compatible = 1695 compatible = "qcom,geni-spi";
1775 reg = <0 0x00 1696 reg = <0 0x00a94000 0 0x4000>;
1776 1697
1777 interrupts = 1698 interrupts = <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>;
1778 1699
1779 clocks = <&gc 1700 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1780 clock-names = 1701 clock-names = "se";
1781 1702
1782 interconnects 1703 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1783 1704 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1784 1705 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1785 1706 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1786 1707 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1787 1708 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1788 interconnect- 1709 interconnect-names = "qup-core",
1789 1710 "qup-config",
1790 1711 "qup-memory";
1791 1712
1792 dmas = <&gpi_ 1713 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1793 <&gpi_ 1714 <&gpi_dma1 1 5 QCOM_GPI_SPI>;
1794 dma-names = " 1715 dma-names = "tx",
1795 " 1716 "rx";
1796 1717
1797 pinctrl-0 = < 1718 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1798 pinctrl-names 1719 pinctrl-names = "default";
1799 1720
1800 #address-cell 1721 #address-cells = <1>;
1801 #size-cells = 1722 #size-cells = <0>;
1802 1723
1803 status = "dis 1724 status = "disabled";
1804 }; 1725 };
1805 1726
1806 i2c14: i2c@a98000 { 1727 i2c14: i2c@a98000 {
1807 compatible = 1728 compatible = "qcom,geni-i2c";
1808 reg = <0 0x00 1729 reg = <0 0x00a98000 0 0x4000>;
1809 1730
1810 interrupts = 1731 interrupts = <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>;
1811 1732
1812 clocks = <&gc 1733 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1813 clock-names = 1734 clock-names = "se";
1814 1735
1815 interconnects 1736 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1816 1737 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1817 1738 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1818 1739 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1819 1740 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1820 1741 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1821 interconnect- 1742 interconnect-names = "qup-core",
1822 1743 "qup-config",
1823 1744 "qup-memory";
1824 1745
1825 dmas = <&gpi_ 1746 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
1826 <&gpi_ 1747 <&gpi_dma1 1 6 QCOM_GPI_I2C>;
1827 dma-names = " 1748 dma-names = "tx",
1828 " 1749 "rx";
1829 1750
1830 pinctrl-0 = < 1751 pinctrl-0 = <&qup_i2c14_data_clk>;
1831 pinctrl-names 1752 pinctrl-names = "default";
1832 1753
1833 #address-cell 1754 #address-cells = <1>;
1834 #size-cells = 1755 #size-cells = <0>;
1835 1756
1836 status = "dis 1757 status = "disabled";
1837 }; 1758 };
1838 1759
1839 spi14: spi@a98000 { 1760 spi14: spi@a98000 {
1840 compatible = 1761 compatible = "qcom,geni-spi";
1841 reg = <0 0x00 1762 reg = <0 0x00a98000 0 0x4000>;
1842 1763
1843 interrupts = 1764 interrupts = <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>;
1844 1765
1845 clocks = <&gc 1766 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1846 clock-names = 1767 clock-names = "se";
1847 1768
1848 interconnects 1769 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1849 1770 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1850 1771 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1851 1772 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1852 1773 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1853 1774 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1854 interconnect- 1775 interconnect-names = "qup-core",
1855 1776 "qup-config",
1856 1777 "qup-memory";
1857 1778
1858 dmas = <&gpi_ 1779 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
1859 <&gpi_ 1780 <&gpi_dma1 1 6 QCOM_GPI_SPI>;
1860 dma-names = " 1781 dma-names = "tx",
1861 " 1782 "rx";
1862 1783
1863 pinctrl-0 = < 1784 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
1864 pinctrl-names 1785 pinctrl-names = "default";
1865 1786
1866 #address-cell 1787 #address-cells = <1>;
1867 #size-cells = 1788 #size-cells = <0>;
1868 1789
1869 status = "dis 1790 status = "disabled";
1870 }; 1791 };
1871 1792
1872 i2c15: i2c@a9c000 { 1793 i2c15: i2c@a9c000 {
1873 compatible = 1794 compatible = "qcom,geni-i2c";
1874 reg = <0 0x00 1795 reg = <0 0x00a9c000 0 0x4000>;
1875 1796
1876 interrupts = 1797 interrupts = <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>;
1877 1798
1878 clocks = <&gc 1799 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1879 clock-names = 1800 clock-names = "se";
1880 1801
1881 interconnects 1802 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1882 1803 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1883 1804 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1884 1805 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1885 1806 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1886 1807 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1887 interconnect- 1808 interconnect-names = "qup-core",
1888 1809 "qup-config",
1889 1810 "qup-memory";
1890 1811
1891 dmas = <&gpi_ 1812 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
1892 <&gpi_ 1813 <&gpi_dma1 1 7 QCOM_GPI_I2C>;
1893 dma-names = " 1814 dma-names = "tx",
1894 " 1815 "rx";
1895 1816
1896 pinctrl-0 = < 1817 pinctrl-0 = <&qup_i2c15_data_clk>;
1897 pinctrl-names 1818 pinctrl-names = "default";
1898 1819
1899 #address-cell 1820 #address-cells = <1>;
1900 #size-cells = 1821 #size-cells = <0>;
1901 1822
1902 status = "dis 1823 status = "disabled";
1903 }; 1824 };
1904 1825
1905 spi15: spi@a9c000 { 1826 spi15: spi@a9c000 {
1906 compatible = 1827 compatible = "qcom,geni-spi";
1907 reg = <0 0x00 1828 reg = <0 0x00a9c000 0 0x4000>;
1908 1829
1909 interrupts = 1830 interrupts = <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>;
1910 1831
1911 clocks = <&gc 1832 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1912 clock-names = 1833 clock-names = "se";
1913 1834
1914 interconnects 1835 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1915 1836 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1916 1837 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1917 1838 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1918 1839 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1919 1840 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1920 interconnect- 1841 interconnect-names = "qup-core",
1921 1842 "qup-config",
1922 1843 "qup-memory";
1923 1844
1924 dmas = <&gpi_ 1845 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>,
1925 <&gpi_ 1846 <&gpi_dma1 1 7 QCOM_GPI_SPI>;
1926 dma-names = " 1847 dma-names = "tx",
1927 " 1848 "rx";
1928 1849
1929 pinctrl-0 = < 1850 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
1930 pinctrl-names 1851 pinctrl-names = "default";
1931 1852
1932 #address-cell 1853 #address-cells = <1>;
1933 #size-cells = 1854 #size-cells = <0>;
1934 1855
1935 status = "dis 1856 status = "disabled";
1936 }; 1857 };
1937 }; 1858 };
1938 1859
1939 gpi_dma0: dma-controller@b000 1860 gpi_dma0: dma-controller@b00000 {
1940 compatible = "qcom,x1 1861 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma";
1941 reg = <0 0x00b00000 0 1862 reg = <0 0x00b00000 0 0x60000>;
1942 1863
1943 interrupts = <GIC_SPI 1864 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
1944 <GIC_SPI 1865 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
1945 <GIC_SPI 1866 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
1946 <GIC_SPI 1867 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
1947 <GIC_SPI 1868 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
1948 <GIC_SPI 1869 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
1949 <GIC_SPI 1870 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
1950 <GIC_SPI 1871 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
1951 <GIC_SPI 1872 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
1952 <GIC_SPI 1873 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
1953 <GIC_SPI 1874 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
1954 <GIC_SPI 1875 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
1955 1876
1956 dma-channels = <12>; 1877 dma-channels = <12>;
1957 dma-channel-mask = <0 1878 dma-channel-mask = <0x3e>;
1958 #dma-cells = <3>; 1879 #dma-cells = <3>;
1959 1880
1960 iommus = <&apps_smmu 1881 iommus = <&apps_smmu 0x456 0x0>;
1961 1882
1962 status = "disabled"; 1883 status = "disabled";
1963 }; 1884 };
1964 1885
1965 qupv3_0: geniqup@bc0000 { 1886 qupv3_0: geniqup@bc0000 {
1966 compatible = "qcom,ge 1887 compatible = "qcom,geni-se-qup";
1967 reg = <0 0x00bc0000 0 1888 reg = <0 0x00bc0000 0 0x2000>;
1968 1889
1969 clocks = <&gcc GCC_QU 1890 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1970 <&gcc GCC_QU 1891 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1971 clock-names = "m-ahb" 1892 clock-names = "m-ahb",
1972 "s-ahb" 1893 "s-ahb";
1973 1894
1974 iommus = <&apps_smmu 1895 iommus = <&apps_smmu 0x443 0x0>;
1975 #address-cells = <2>; 1896 #address-cells = <2>;
1976 #size-cells = <2>; 1897 #size-cells = <2>;
1977 ranges; 1898 ranges;
1978 1899
1979 status = "disabled"; 1900 status = "disabled";
1980 1901
1981 i2c0: i2c@b80000 { 1902 i2c0: i2c@b80000 {
1982 compatible = 1903 compatible = "qcom,geni-i2c";
1983 reg = <0 0x00 !! 1904 reg = <0 0xb80000 0 0x4000>;
1984 1905
1985 interrupts = 1906 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1986 1907
1987 clocks = <&gc 1908 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1988 clock-names = 1909 clock-names = "se";
1989 1910
1990 interconnects 1911 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1991 1912 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1992 1913 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1993 1914 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
1994 1915 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
1995 1916 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1996 interconnect- 1917 interconnect-names = "qup-core",
1997 1918 "qup-config",
1998 1919 "qup-memory";
1999 1920
2000 dmas = <&gpi_ 1921 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
2001 <&gpi_ 1922 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
2002 dma-names = " 1923 dma-names = "tx",
2003 " 1924 "rx";
2004 1925
2005 pinctrl-0 = < 1926 pinctrl-0 = <&qup_i2c0_data_clk>;
2006 pinctrl-names 1927 pinctrl-names = "default";
2007 1928
2008 #address-cell 1929 #address-cells = <1>;
2009 #size-cells = 1930 #size-cells = <0>;
2010 1931
2011 status = "dis 1932 status = "disabled";
2012 }; 1933 };
2013 1934
2014 spi0: spi@b80000 { 1935 spi0: spi@b80000 {
2015 compatible = 1936 compatible = "qcom,geni-spi";
2016 reg = <0 0x00 1937 reg = <0 0x00b80000 0 0x4000>;
2017 1938
2018 interrupts = 1939 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
2019 1940
2020 clocks = <&gc 1941 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
2021 clock-names = 1942 clock-names = "se";
2022 1943
2023 interconnects 1944 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2024 1945 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2025 1946 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2026 1947 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2027 1948 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2028 1949 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2029 interconnect- 1950 interconnect-names = "qup-core",
2030 1951 "qup-config",
2031 1952 "qup-memory";
2032 1953
2033 dmas = <&gpi_ 1954 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
2034 <&gpi_ 1955 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
2035 dma-names = " 1956 dma-names = "tx",
2036 " 1957 "rx";
2037 1958
2038 pinctrl-0 = < 1959 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
2039 pinctrl-names 1960 pinctrl-names = "default";
2040 1961
2041 #address-cell 1962 #address-cells = <1>;
2042 #size-cells = 1963 #size-cells = <0>;
2043 1964
2044 status = "dis 1965 status = "disabled";
2045 }; 1966 };
2046 1967
2047 i2c1: i2c@b84000 { 1968 i2c1: i2c@b84000 {
2048 compatible = 1969 compatible = "qcom,geni-i2c";
2049 reg = <0 0x00 1970 reg = <0 0x00b84000 0 0x4000>;
2050 1971
2051 interrupts = 1972 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
2052 1973
2053 clocks = <&gc 1974 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
2054 clock-names = 1975 clock-names = "se";
2055 1976
2056 interconnects 1977 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2057 1978 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2058 1979 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2059 1980 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2060 1981 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2061 1982 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2062 interconnect- 1983 interconnect-names = "qup-core",
2063 1984 "qup-config",
2064 1985 "qup-memory";
2065 1986
2066 dmas = <&gpi_ 1987 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
2067 <&gpi_ 1988 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
2068 dma-names = " 1989 dma-names = "tx",
2069 " 1990 "rx";
2070 1991
2071 pinctrl-0 = < 1992 pinctrl-0 = <&qup_i2c1_data_clk>;
2072 pinctrl-names 1993 pinctrl-names = "default";
2073 1994
2074 #address-cell 1995 #address-cells = <1>;
2075 #size-cells = 1996 #size-cells = <0>;
2076 1997
2077 status = "dis 1998 status = "disabled";
2078 }; 1999 };
2079 2000
2080 spi1: spi@b84000 { 2001 spi1: spi@b84000 {
2081 compatible = 2002 compatible = "qcom,geni-spi";
2082 reg = <0 0x00 2003 reg = <0 0x00b84000 0 0x4000>;
2083 2004
2084 interrupts = 2005 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
2085 2006
2086 clocks = <&gc 2007 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
2087 clock-names = 2008 clock-names = "se";
2088 2009
2089 interconnects 2010 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2090 2011 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2091 2012 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2092 2013 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2093 2014 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2094 2015 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2095 interconnect- 2016 interconnect-names = "qup-core",
2096 2017 "qup-config",
2097 2018 "qup-memory";
2098 2019
2099 dmas = <&gpi_ 2020 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
2100 <&gpi_ 2021 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
2101 dma-names = " 2022 dma-names = "tx",
2102 " 2023 "rx";
2103 2024
2104 pinctrl-0 = < 2025 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
2105 pinctrl-names 2026 pinctrl-names = "default";
2106 2027
2107 #address-cell 2028 #address-cells = <1>;
2108 #size-cells = 2029 #size-cells = <0>;
2109 2030
2110 status = "dis 2031 status = "disabled";
2111 }; 2032 };
2112 2033
2113 i2c2: i2c@b88000 { 2034 i2c2: i2c@b88000 {
2114 compatible = 2035 compatible = "qcom,geni-i2c";
2115 reg = <0 0x00 2036 reg = <0 0x00b88000 0 0x4000>;
2116 2037
2117 interrupts = 2038 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
2118 2039
2119 clocks = <&gc 2040 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
2120 clock-names = 2041 clock-names = "se";
2121 2042
2122 interconnects 2043 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2123 2044 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2124 2045 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2125 2046 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2126 2047 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2127 2048 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2128 interconnect- 2049 interconnect-names = "qup-core",
2129 2050 "qup-config",
2130 2051 "qup-memory";
2131 2052
2132 dmas = <&gpi_ 2053 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
2133 <&gpi_ 2054 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
2134 dma-names = " 2055 dma-names = "tx",
2135 " 2056 "rx";
2136 2057
2137 pinctrl-0 = < 2058 pinctrl-0 = <&qup_i2c2_data_clk>;
2138 pinctrl-names 2059 pinctrl-names = "default";
2139 2060
2140 #address-cell 2061 #address-cells = <1>;
2141 #size-cells = 2062 #size-cells = <0>;
2142 2063
2143 status = "dis 2064 status = "disabled";
2144 }; 2065 };
2145 2066
2146 uart2: serial@b88000 <<
2147 compatible = <<
2148 reg = <0 0x00 <<
2149 <<
2150 interrupts = <<
2151 <<
2152 clocks = <&gc <<
2153 clock-names = <<
2154 <<
2155 interconnects <<
2156 <<
2157 <<
2158 <<
2159 interconnect- <<
2160 <<
2161 <<
2162 pinctrl-0 = < <<
2163 pinctrl-names <<
2164 <<
2165 status = "dis <<
2166 }; <<
2167 <<
2168 spi2: spi@b88000 { 2067 spi2: spi@b88000 {
2169 compatible = 2068 compatible = "qcom,geni-spi";
2170 reg = <0 0x00 !! 2069 reg = <0 0xb88000 0 0x4000>;
2171 2070
2172 interrupts = 2071 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
2173 2072
2174 clocks = <&gc 2073 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
2175 clock-names = 2074 clock-names = "se";
2176 2075
2177 interconnects 2076 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2178 2077 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2179 2078 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2180 2079 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2181 2080 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2182 2081 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2183 interconnect- 2082 interconnect-names = "qup-core",
2184 2083 "qup-config",
2185 2084 "qup-memory";
2186 2085
2187 dmas = <&gpi_ 2086 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
2188 <&gpi_ 2087 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
2189 dma-names = " 2088 dma-names = "tx",
2190 " 2089 "rx";
2191 2090
2192 pinctrl-0 = < 2091 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
2193 pinctrl-names 2092 pinctrl-names = "default";
2194 2093
2195 #address-cell 2094 #address-cells = <1>;
2196 #size-cells = 2095 #size-cells = <0>;
2197 2096
2198 status = "dis 2097 status = "disabled";
2199 }; 2098 };
2200 2099
2201 i2c3: i2c@b8c000 { 2100 i2c3: i2c@b8c000 {
2202 compatible = 2101 compatible = "qcom,geni-i2c";
2203 reg = <0 0x00 2102 reg = <0 0x00b8c000 0 0x4000>;
2204 2103
2205 interrupts = 2104 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
2206 2105
2207 clocks = <&gc 2106 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
2208 clock-names = 2107 clock-names = "se";
2209 2108
2210 interconnects 2109 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2211 2110 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2212 2111 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2213 2112 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2214 2113 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2215 2114 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2216 interconnect- 2115 interconnect-names = "qup-core",
2217 2116 "qup-config",
2218 2117 "qup-memory";
2219 2118
2220 dmas = <&gpi_ 2119 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
2221 <&gpi_ 2120 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
2222 dma-names = " 2121 dma-names = "tx",
2223 " 2122 "rx";
2224 2123
2225 pinctrl-0 = < 2124 pinctrl-0 = <&qup_i2c3_data_clk>;
2226 pinctrl-names 2125 pinctrl-names = "default";
2227 2126
2228 #address-cell 2127 #address-cells = <1>;
2229 #size-cells = 2128 #size-cells = <0>;
2230 2129
2231 status = "dis 2130 status = "disabled";
2232 }; 2131 };
2233 2132
2234 spi3: spi@b8c000 { 2133 spi3: spi@b8c000 {
2235 compatible = 2134 compatible = "qcom,geni-spi";
2236 reg = <0 0x00 2135 reg = <0 0x00b8c000 0 0x4000>;
2237 2136
2238 interrupts = 2137 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
2239 2138
2240 clocks = <&gc 2139 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
2241 clock-names = 2140 clock-names = "se";
2242 2141
2243 interconnects 2142 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2244 2143 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2245 2144 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2246 2145 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2247 2146 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2248 2147 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2249 interconnect- 2148 interconnect-names = "qup-core",
2250 2149 "qup-config",
2251 2150 "qup-memory";
2252 2151
2253 dmas = <&gpi_ 2152 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
2254 <&gpi_ 2153 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
2255 dma-names = " 2154 dma-names = "tx",
2256 " 2155 "rx";
2257 2156
2258 pinctrl-0 = < 2157 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
2259 pinctrl-names 2158 pinctrl-names = "default";
2260 2159
2261 #address-cell 2160 #address-cells = <1>;
2262 #size-cells = 2161 #size-cells = <0>;
2263 2162
2264 status = "dis 2163 status = "disabled";
2265 }; 2164 };
2266 2165
2267 i2c4: i2c@b90000 { 2166 i2c4: i2c@b90000 {
2268 compatible = 2167 compatible = "qcom,geni-i2c";
2269 reg = <0 0x00 !! 2168 reg = <0 0xb90000 0 0x4000>;
2270 2169
2271 interrupts = 2170 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
2272 2171
2273 clocks = <&gc 2172 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
2274 clock-names = 2173 clock-names = "se";
2275 2174
2276 interconnects 2175 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2277 2176 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2278 2177 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2279 2178 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2280 2179 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2281 2180 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2282 interconnect- 2181 interconnect-names = "qup-core",
2283 2182 "qup-config",
2284 2183 "qup-memory";
2285 2184
2286 dmas = <&gpi_ 2185 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
2287 <&gpi_ 2186 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
2288 dma-names = " 2187 dma-names = "tx",
2289 " 2188 "rx";
2290 2189
2291 pinctrl-0 = < 2190 pinctrl-0 = <&qup_i2c4_data_clk>;
2292 pinctrl-names 2191 pinctrl-names = "default";
2293 2192
2294 #address-cell 2193 #address-cells = <1>;
2295 #size-cells = 2194 #size-cells = <0>;
2296 2195
2297 status = "dis 2196 status = "disabled";
2298 }; 2197 };
2299 2198
2300 spi4: spi@b90000 { 2199 spi4: spi@b90000 {
2301 compatible = 2200 compatible = "qcom,geni-spi";
2302 reg = <0 0x00 2201 reg = <0 0x00b90000 0 0x4000>;
2303 2202
2304 interrupts = 2203 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
2305 2204
2306 clocks = <&gc 2205 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
2307 clock-names = 2206 clock-names = "se";
2308 2207
2309 interconnects 2208 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2310 2209 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2311 2210 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2312 2211 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2313 2212 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2314 2213 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2315 interconnect- 2214 interconnect-names = "qup-core",
2316 2215 "qup-config",
2317 2216 "qup-memory";
2318 2217
2319 dmas = <&gpi_ 2218 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
2320 <&gpi_ 2219 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
2321 dma-names = " 2220 dma-names = "tx",
2322 " 2221 "rx";
2323 2222
2324 pinctrl-0 = < 2223 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
2325 pinctrl-names 2224 pinctrl-names = "default";
2326 2225
2327 #address-cell 2226 #address-cells = <1>;
2328 #size-cells = 2227 #size-cells = <0>;
2329 2228
2330 status = "dis 2229 status = "disabled";
2331 }; 2230 };
2332 2231
2333 i2c5: i2c@b94000 { 2232 i2c5: i2c@b94000 {
2334 compatible = 2233 compatible = "qcom,geni-i2c";
2335 reg = <0 0x00 2234 reg = <0 0x00b94000 0 0x4000>;
2336 2235
2337 interrupts = 2236 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
2338 2237
2339 clocks = <&gc 2238 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
2340 clock-names = 2239 clock-names = "se";
2341 2240
2342 interconnects 2241 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2343 2242 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2344 2243 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2345 2244 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2346 2245 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2347 2246 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2348 interconnect- 2247 interconnect-names = "qup-core",
2349 2248 "qup-config",
2350 2249 "qup-memory";
2351 2250
2352 dmas = <&gpi_ 2251 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
2353 <&gpi_ 2252 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
2354 dma-names = " 2253 dma-names = "tx",
2355 " 2254 "rx";
2356 2255
2357 pinctrl-0 = < 2256 pinctrl-0 = <&qup_i2c5_data_clk>;
2358 pinctrl-names 2257 pinctrl-names = "default";
2359 2258
2360 #address-cell 2259 #address-cells = <1>;
2361 #size-cells = 2260 #size-cells = <0>;
2362 2261
2363 status = "dis 2262 status = "disabled";
2364 }; 2263 };
2365 2264
2366 spi5: spi@b94000 { 2265 spi5: spi@b94000 {
2367 compatible = 2266 compatible = "qcom,geni-spi";
2368 reg = <0 0x00 2267 reg = <0 0x00b94000 0 0x4000>;
2369 2268
2370 interrupts = 2269 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
2371 2270
2372 clocks = <&gc 2271 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
2373 clock-names = 2272 clock-names = "se";
2374 2273
2375 interconnects 2274 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2376 2275 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2377 2276 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2378 2277 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2379 2278 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2380 2279 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2381 interconnect- 2280 interconnect-names = "qup-core",
2382 2281 "qup-config",
2383 2282 "qup-memory";
2384 2283
2385 dmas = <&gpi_ 2284 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
2386 <&gpi_ 2285 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
2387 dma-names = " 2286 dma-names = "tx",
2388 " 2287 "rx";
2389 2288
2390 pinctrl-0 = < 2289 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
2391 pinctrl-names 2290 pinctrl-names = "default";
2392 2291
2393 #address-cell 2292 #address-cells = <1>;
2394 #size-cells = 2293 #size-cells = <0>;
2395 2294
2396 status = "dis 2295 status = "disabled";
2397 }; 2296 };
2398 2297
2399 i2c6: i2c@b98000 { 2298 i2c6: i2c@b98000 {
2400 compatible = 2299 compatible = "qcom,geni-i2c";
2401 reg = <0 0x00 2300 reg = <0 0x00b98000 0 0x4000>;
2402 2301
2403 interrupts = 2302 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
2404 2303
2405 clocks = <&gc 2304 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
2406 clock-names = 2305 clock-names = "se";
2407 2306
2408 interconnects 2307 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2409 2308 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2410 2309 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2411 2310 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2412 2311 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2413 2312 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2414 interconnect- 2313 interconnect-names = "qup-core",
2415 2314 "qup-config",
2416 2315 "qup-memory";
2417 2316
2418 dmas = <&gpi_ 2317 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
2419 <&gpi_ 2318 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
2420 dma-names = " 2319 dma-names = "tx",
2421 " 2320 "rx";
2422 2321
2423 pinctrl-0 = < 2322 pinctrl-0 = <&qup_i2c6_data_clk>;
2424 pinctrl-names 2323 pinctrl-names = "default";
2425 2324
2426 #address-cell 2325 #address-cells = <1>;
2427 #size-cells = 2326 #size-cells = <0>;
2428 2327
2429 status = "dis 2328 status = "disabled";
2430 }; 2329 };
2431 2330
2432 spi6: spi@b98000 { 2331 spi6: spi@b98000 {
2433 compatible = 2332 compatible = "qcom,geni-spi";
2434 reg = <0 0x00 2333 reg = <0 0x00b98000 0 0x4000>;
2435 2334
2436 interrupts = 2335 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
2437 2336
2438 clocks = <&gc 2337 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
2439 clock-names = 2338 clock-names = "se";
2440 2339
2441 interconnects 2340 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2442 2341 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2443 2342 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2444 2343 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2445 2344 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2446 2345 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2447 interconnect- 2346 interconnect-names = "qup-core",
2448 2347 "qup-config",
2449 2348 "qup-memory";
2450 2349
2451 dmas = <&gpi_ 2350 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
2452 <&gpi_ 2351 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
2453 dma-names = " 2352 dma-names = "tx",
2454 " 2353 "rx";
2455 2354
2456 pinctrl-0 = < 2355 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
2457 pinctrl-names 2356 pinctrl-names = "default";
2458 2357
2459 #address-cell 2358 #address-cells = <1>;
2460 #size-cells = 2359 #size-cells = <0>;
2461 2360
2462 status = "dis 2361 status = "disabled";
2463 }; 2362 };
2464 2363
2465 i2c7: i2c@b9c000 { 2364 i2c7: i2c@b9c000 {
2466 compatible = 2365 compatible = "qcom,geni-i2c";
2467 reg = <0 0x00 2366 reg = <0 0x00b9c000 0 0x4000>;
2468 2367
2469 interrupts = 2368 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
2470 2369
2471 clocks = <&gc 2370 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
2472 clock-names = 2371 clock-names = "se";
2473 2372
2474 interconnects 2373 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2475 2374 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2476 2375 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2477 2376 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2478 2377 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2479 2378 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2480 interconnect- 2379 interconnect-names = "qup-core",
2481 2380 "qup-config",
2482 2381 "qup-memory";
2483 2382
2484 dmas = <&gpi_ 2383 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
2485 <&gpi_ 2384 <&gpi_dma0 1 7 QCOM_GPI_I2C>;
2486 dma-names = " 2385 dma-names = "tx",
2487 " 2386 "rx";
2488 2387
2489 pinctrl-0 = < 2388 pinctrl-0 = <&qup_i2c7_data_clk>;
2490 pinctrl-names 2389 pinctrl-names = "default";
2491 2390
2492 #address-cell 2391 #address-cells = <1>;
2493 #size-cells = 2392 #size-cells = <0>;
2494 2393
2495 status = "dis 2394 status = "disabled";
2496 }; 2395 };
2497 2396
2498 spi7: spi@b9c000 { 2397 spi7: spi@b9c000 {
2499 compatible = 2398 compatible = "qcom,geni-spi";
2500 reg = <0 0x00 2399 reg = <0 0x00b9c000 0 0x4000>;
2501 2400
2502 interrupts = 2401 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
2503 2402
2504 clocks = <&gc 2403 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
2505 clock-names = 2404 clock-names = "se";
2506 2405
2507 interconnects 2406 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2508 2407 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2509 2408 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2510 2409 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2511 2410 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2512 2411 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2513 interconnect- 2412 interconnect-names = "qup-core",
2514 2413 "qup-config",
2515 2414 "qup-memory";
2516 2415
2517 dmas = <&gpi_ 2416 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
2518 <&gpi_ 2417 <&gpi_dma0 1 7 QCOM_GPI_SPI>;
2519 dma-names = " 2418 dma-names = "tx",
2520 " 2419 "rx";
2521 2420
2522 pinctrl-0 = < 2421 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
2523 pinctrl-names 2422 pinctrl-names = "default";
2524 2423
2525 #address-cell 2424 #address-cells = <1>;
2526 #size-cells = 2425 #size-cells = <0>;
2527 2426
2528 status = "dis 2427 status = "disabled";
2529 }; 2428 };
2530 }; 2429 };
2531 2430
2532 tsens0: thermal-sensor@c27100 <<
2533 compatible = "qcom,x1 <<
2534 reg = <0 0x0c271000 0 <<
2535 <0 0x0c222000 0 <<
2536 <<
2537 interrupts-extended = <<
2538 <<
2539 interrupt-names = "up <<
2540 "cr <<
2541 <<
2542 #qcom,sensors = <16>; <<
2543 <<
2544 #thermal-sensor-cells <<
2545 }; <<
2546 <<
2547 tsens1: thermal-sensor@c27200 <<
2548 compatible = "qcom,x1 <<
2549 reg = <0 0x0c272000 0 <<
2550 <0 0x0c223000 0 <<
2551 <<
2552 interrupts-extended = <<
2553 <<
2554 interrupt-names = "up <<
2555 "cr <<
2556 <<
2557 #qcom,sensors = <16>; <<
2558 <<
2559 #thermal-sensor-cells <<
2560 }; <<
2561 <<
2562 tsens2: thermal-sensor@c27300 <<
2563 compatible = "qcom,x1 <<
2564 reg = <0 0x0c273000 0 <<
2565 <0 0x0c224000 0 <<
2566 <<
2567 interrupts-extended = <<
2568 <<
2569 interrupt-names = "up <<
2570 "cr <<
2571 <<
2572 #qcom,sensors = <16>; <<
2573 <<
2574 #thermal-sensor-cells <<
2575 }; <<
2576 <<
2577 tsens3: thermal-sensor@c27400 <<
2578 compatible = "qcom,x1 <<
2579 reg = <0 0x0c274000 0 <<
2580 <0 0x0c225000 0 <<
2581 <<
2582 interrupts-extended = <<
2583 <<
2584 interrupt-names = "up <<
2585 "cr <<
2586 <<
2587 #qcom,sensors = <16>; <<
2588 <<
2589 #thermal-sensor-cells <<
2590 }; <<
2591 <<
2592 usb_1_ss0_hsphy: phy@fd3000 { <<
2593 compatible = "qcom,x1 <<
2594 "qcom,sm <<
2595 reg = <0 0x00fd3000 0 <<
2596 #phy-cells = <0>; <<
2597 <<
2598 clocks = <&tcsr TCSR_ <<
2599 clock-names = "ref"; <<
2600 <<
2601 resets = <&gcc GCC_QU <<
2602 <<
2603 status = "disabled"; <<
2604 }; <<
2605 <<
2606 usb_1_ss0_qmpphy: phy@fd5000 <<
2607 compatible = "qcom,x1 <<
2608 reg = <0 0x00fd5000 0 <<
2609 <<
2610 clocks = <&gcc GCC_US <<
2611 <&rpmhcc RPM <<
2612 <&gcc GCC_US <<
2613 <&gcc GCC_US <<
2614 clock-names = "aux", <<
2615 "ref", <<
2616 "com_au <<
2617 "usb3_p <<
2618 <<
2619 power-domains = <&gcc <<
2620 <<
2621 resets = <&gcc GCC_US <<
2622 <&gcc GCC_US <<
2623 reset-names = "phy", <<
2624 "common <<
2625 <<
2626 #clock-cells = <1>; <<
2627 #phy-cells = <1>; <<
2628 <<
2629 orientation-switch; <<
2630 <<
2631 status = "disabled"; <<
2632 <<
2633 ports { <<
2634 #address-cell <<
2635 #size-cells = <<
2636 <<
2637 port@0 { <<
2638 reg = <<
2639 <<
2640 usb_1 <<
2641 }; <<
2642 }; <<
2643 <<
2644 port@1 { <<
2645 reg = <<
2646 <<
2647 usb_1 <<
2648 <<
2649 }; <<
2650 }; <<
2651 <<
2652 port@2 { <<
2653 reg = <<
2654 <<
2655 usb_1 <<
2656 <<
2657 }; <<
2658 }; <<
2659 }; <<
2660 }; <<
2661 <<
2662 usb_1_ss1_hsphy: phy@fd9000 { <<
2663 compatible = "qcom,x1 <<
2664 "qcom,sm <<
2665 reg = <0 0x00fd9000 0 <<
2666 #phy-cells = <0>; <<
2667 <<
2668 clocks = <&tcsr TCSR_ <<
2669 clock-names = "ref"; <<
2670 <<
2671 resets = <&gcc GCC_QU <<
2672 <<
2673 status = "disabled"; <<
2674 }; <<
2675 <<
2676 usb_1_ss1_qmpphy: phy@fda000 <<
2677 compatible = "qcom,x1 <<
2678 reg = <0 0x00fda000 0 <<
2679 <<
2680 clocks = <&gcc GCC_US <<
2681 <&rpmhcc RPM <<
2682 <&gcc GCC_US <<
2683 <&gcc GCC_US <<
2684 clock-names = "aux", <<
2685 "ref", <<
2686 "com_au <<
2687 "usb3_p <<
2688 <<
2689 power-domains = <&gcc <<
2690 <<
2691 resets = <&gcc GCC_US <<
2692 <&gcc GCC_US <<
2693 reset-names = "phy", <<
2694 "common <<
2695 <<
2696 #clock-cells = <1>; <<
2697 #phy-cells = <1>; <<
2698 <<
2699 orientation-switch; <<
2700 <<
2701 status = "disabled"; <<
2702 <<
2703 ports { <<
2704 #address-cell <<
2705 #size-cells = <<
2706 <<
2707 port@0 { <<
2708 reg = <<
2709 <<
2710 usb_1 <<
2711 }; <<
2712 }; <<
2713 <<
2714 port@1 { <<
2715 reg = <<
2716 <<
2717 usb_1 <<
2718 <<
2719 }; <<
2720 }; <<
2721 <<
2722 port@2 { <<
2723 reg = <<
2724 <<
2725 usb_1 <<
2726 <<
2727 }; <<
2728 }; <<
2729 }; <<
2730 }; <<
2731 <<
2732 usb_1_ss2_hsphy: phy@fde000 { <<
2733 compatible = "qcom,x1 <<
2734 "qcom,sm <<
2735 reg = <0 0x00fde000 0 <<
2736 #phy-cells = <0>; <<
2737 <<
2738 clocks = <&tcsr TCSR_ <<
2739 clock-names = "ref"; <<
2740 <<
2741 resets = <&gcc GCC_QU <<
2742 <<
2743 status = "disabled"; <<
2744 }; <<
2745 <<
2746 usb_1_ss2_qmpphy: phy@fdf000 <<
2747 compatible = "qcom,x1 <<
2748 reg = <0 0x00fdf000 0 <<
2749 <<
2750 clocks = <&gcc GCC_US <<
2751 <&rpmhcc RPM <<
2752 <&gcc GCC_US <<
2753 <&gcc GCC_US <<
2754 clock-names = "aux", <<
2755 "ref", <<
2756 "com_au <<
2757 "usb3_p <<
2758 <<
2759 power-domains = <&gcc <<
2760 <<
2761 resets = <&gcc GCC_US <<
2762 <&gcc GCC_US <<
2763 reset-names = "phy", <<
2764 "common <<
2765 <<
2766 #clock-cells = <1>; <<
2767 #phy-cells = <1>; <<
2768 <<
2769 orientation-switch; <<
2770 <<
2771 status = "disabled"; <<
2772 <<
2773 ports { <<
2774 #address-cell <<
2775 #size-cells = <<
2776 <<
2777 port@0 { <<
2778 reg = <<
2779 <<
2780 usb_1 <<
2781 }; <<
2782 }; <<
2783 <<
2784 port@1 { <<
2785 reg = <<
2786 <<
2787 usb_1 <<
2788 <<
2789 }; <<
2790 }; <<
2791 <<
2792 port@2 { <<
2793 reg = <<
2794 <<
2795 usb_1 <<
2796 <<
2797 }; <<
2798 }; <<
2799 }; <<
2800 }; <<
2801 <<
2802 cnoc_main: interconnect@15000 2431 cnoc_main: interconnect@1500000 {
2803 compatible = "qcom,x1 2432 compatible = "qcom,x1e80100-cnoc-main";
2804 reg = <0 0x01500000 0 !! 2433 reg = <0 0x1500000 0 0x14400>;
2805 2434
2806 qcom,bcm-voters = <&a 2435 qcom,bcm-voters = <&apps_bcm_voter>;
2807 2436
2808 #interconnect-cells = 2437 #interconnect-cells = <2>;
2809 }; 2438 };
2810 2439
2811 config_noc: interconnect@1600 2440 config_noc: interconnect@1600000 {
2812 compatible = "qcom,x1 2441 compatible = "qcom,x1e80100-cnoc-cfg";
2813 reg = <0 0x01600000 0 !! 2442 reg = <0 0x1600000 0 0x6600>;
2814 2443
2815 qcom,bcm-voters = <&a 2444 qcom,bcm-voters = <&apps_bcm_voter>;
2816 2445
2817 #interconnect-cells = 2446 #interconnect-cells = <2>;
2818 }; 2447 };
2819 2448
2820 system_noc: interconnect@1680 2449 system_noc: interconnect@1680000 {
2821 compatible = "qcom,x1 2450 compatible = "qcom,x1e80100-system-noc";
2822 reg = <0 0x01680000 0 !! 2451 reg = <0 0x1680000 0 0x1c080>;
2823 2452
2824 qcom,bcm-voters = <&a 2453 qcom,bcm-voters = <&apps_bcm_voter>;
2825 2454
2826 #interconnect-cells = 2455 #interconnect-cells = <2>;
2827 }; 2456 };
2828 2457
2829 pcie_south_anoc: interconnect 2458 pcie_south_anoc: interconnect@16c0000 {
2830 compatible = "qcom,x1 2459 compatible = "qcom,x1e80100-pcie-south-anoc";
2831 reg = <0 0x016c0000 0 !! 2460 reg = <0 0x16c0000 0 0xd080>;
2832 2461
2833 qcom,bcm-voters = <&a 2462 qcom,bcm-voters = <&apps_bcm_voter>;
2834 2463
2835 #interconnect-cells = 2464 #interconnect-cells = <2>;
2836 }; 2465 };
2837 2466
2838 pcie_center_anoc: interconnec 2467 pcie_center_anoc: interconnect@16d0000 {
2839 compatible = "qcom,x1 2468 compatible = "qcom,x1e80100-pcie-center-anoc";
2840 reg = <0 0x016d0000 0 !! 2469 reg = <0 0x16d0000 0 0x7000>;
2841 2470
2842 qcom,bcm-voters = <&a 2471 qcom,bcm-voters = <&apps_bcm_voter>;
2843 2472
2844 #interconnect-cells = 2473 #interconnect-cells = <2>;
2845 }; 2474 };
2846 2475
2847 aggre1_noc: interconnect@16e0 2476 aggre1_noc: interconnect@16e0000 {
2848 compatible = "qcom,x1 2477 compatible = "qcom,x1e80100-aggre1-noc";
2849 reg = <0 0x016e0000 0 !! 2478 reg = <0 0x16E0000 0 0x14400>;
2850 2479
2851 qcom,bcm-voters = <&a 2480 qcom,bcm-voters = <&apps_bcm_voter>;
2852 2481
2853 #interconnect-cells = 2482 #interconnect-cells = <2>;
2854 }; 2483 };
2855 2484
2856 aggre2_noc: interconnect@1700 2485 aggre2_noc: interconnect@1700000 {
2857 compatible = "qcom,x1 2486 compatible = "qcom,x1e80100-aggre2-noc";
2858 reg = <0 0x01700000 0 !! 2487 reg = <0 0x1700000 0 0x1c400>;
2859 2488
2860 qcom,bcm-voters = <&a 2489 qcom,bcm-voters = <&apps_bcm_voter>;
2861 2490
2862 #interconnect-cells = 2491 #interconnect-cells = <2>;
2863 }; 2492 };
2864 2493
2865 pcie_north_anoc: interconnect 2494 pcie_north_anoc: interconnect@1740000 {
2866 compatible = "qcom,x1 2495 compatible = "qcom,x1e80100-pcie-north-anoc";
2867 reg = <0 0x01740000 0 !! 2496 reg = <0 0x1740000 0 0x9080>;
2868 2497
2869 qcom,bcm-voters = <&a 2498 qcom,bcm-voters = <&apps_bcm_voter>;
2870 2499
2871 #interconnect-cells = 2500 #interconnect-cells = <2>;
2872 }; 2501 };
2873 2502
2874 usb_center_anoc: interconnect 2503 usb_center_anoc: interconnect@1750000 {
2875 compatible = "qcom,x1 2504 compatible = "qcom,x1e80100-usb-center-anoc";
2876 reg = <0 0x01750000 0 !! 2505 reg = <0 0x1750000 0 0x8800>;
2877 2506
2878 qcom,bcm-voters = <&a 2507 qcom,bcm-voters = <&apps_bcm_voter>;
2879 2508
2880 #interconnect-cells = 2509 #interconnect-cells = <2>;
2881 }; 2510 };
2882 2511
2883 usb_north_anoc: interconnect@ 2512 usb_north_anoc: interconnect@1760000 {
2884 compatible = "qcom,x1 2513 compatible = "qcom,x1e80100-usb-north-anoc";
2885 reg = <0 0x01760000 0 !! 2514 reg = <0 0x1760000 0 0x7080>;
2886 2515
2887 qcom,bcm-voters = <&a 2516 qcom,bcm-voters = <&apps_bcm_voter>;
2888 2517
2889 #interconnect-cells = 2518 #interconnect-cells = <2>;
2890 }; 2519 };
2891 2520
2892 usb_south_anoc: interconnect@ 2521 usb_south_anoc: interconnect@1770000 {
2893 compatible = "qcom,x1 2522 compatible = "qcom,x1e80100-usb-south-anoc";
2894 reg = <0 0x01770000 0 !! 2523 reg = <0 0x1770000 0 0xf080>;
2895 2524
2896 qcom,bcm-voters = <&a 2525 qcom,bcm-voters = <&apps_bcm_voter>;
2897 2526
2898 #interconnect-cells = 2527 #interconnect-cells = <2>;
2899 }; 2528 };
2900 2529
2901 mmss_noc: interconnect@178000 2530 mmss_noc: interconnect@1780000 {
2902 compatible = "qcom,x1 2531 compatible = "qcom,x1e80100-mmss-noc";
2903 reg = <0 0x01780000 0 !! 2532 reg = <0 0x1780000 0 0x5B800>;
2904 2533
2905 qcom,bcm-voters = <&a 2534 qcom,bcm-voters = <&apps_bcm_voter>;
2906 2535
2907 #interconnect-cells = 2536 #interconnect-cells = <2>;
2908 }; 2537 };
2909 2538
2910 pcie6a: pci@1bf8000 { <<
2911 device_type = "pci"; <<
2912 compatible = "qcom,pc <<
2913 reg = <0 0x01bf8000 0 <<
2914 <0 0x70000000 0 <<
2915 <0 0x70000f40 0 <<
2916 <0 0x70001000 0 <<
2917 <0 0x70100000 0 <<
2918 <0 0x01bfb000 0 <<
2919 reg-names = "parf", <<
2920 "dbi", <<
2921 "elbi", <<
2922 "atu", <<
2923 "config", <<
2924 "mhi"; <<
2925 #address-cells = <3>; <<
2926 #size-cells = <2>; <<
2927 ranges = <0x01000000 <<
2928 <0x02000000 <<
2929 bus-range = <0x00 0xf <<
2930 <<
2931 dma-coherent; <<
2932 <<
2933 linux,pci-domain = <6 <<
2934 num-lanes = <4>; <<
2935 <<
2936 interrupts = <GIC_SPI <<
2937 <GIC_SPI <<
2938 <GIC_SPI <<
2939 <GIC_SPI <<
2940 <GIC_SPI <<
2941 <GIC_SPI <<
2942 <GIC_SPI <<
2943 <GIC_SPI <<
2944 interrupt-names = "ms <<
2945 "ms <<
2946 "ms <<
2947 "ms <<
2948 "ms <<
2949 "ms <<
2950 "ms <<
2951 "ms <<
2952 <<
2953 #interrupt-cells = <1 <<
2954 interrupt-map-mask = <<
2955 interrupt-map = <0 0 <<
2956 <0 0 <<
2957 <0 0 <<
2958 <0 0 <<
2959 <<
2960 clocks = <&gcc GCC_PC <<
2961 <&gcc GCC_PC <<
2962 <&gcc GCC_PC <<
2963 <&gcc GCC_PC <<
2964 <&gcc GCC_PC <<
2965 <&gcc GCC_CF <<
2966 <&gcc GCC_CN <<
2967 clock-names = "aux", <<
2968 "cfg", <<
2969 "bus_ma <<
2970 "bus_sl <<
2971 "slave_ <<
2972 "noc_ag <<
2973 "cnoc_s <<
2974 <<
2975 assigned-clocks = <&g <<
2976 assigned-clock-rates <<
2977 <<
2978 interconnects = <&pci <<
2979 &mc_ <<
2980 <&gem <<
2981 &cno <<
2982 interconnect-names = <<
2983 <<
2984 <<
2985 resets = <&gcc GCC_PC <<
2986 <&gcc GCC_PC <<
2987 reset-names = "pci", <<
2988 "link_d <<
2989 <<
2990 power-domains = <&gcc <<
2991 required-opps = <&rpm <<
2992 <<
2993 phys = <&pcie6a_phy>; <<
2994 phy-names = "pciephy" <<
2995 <<
2996 status = "disabled"; <<
2997 }; <<
2998 <<
2999 pcie6a_phy: phy@1bfc000 { <<
3000 compatible = "qcom,x1 <<
3001 reg = <0 0x01bfc000 0 <<
3002 <0 0x01bfe000 0 <<
3003 <<
3004 clocks = <&gcc GCC_PC <<
3005 <&gcc GCC_PC <<
3006 <&tcsr TCSR_ <<
3007 <&gcc GCC_PC <<
3008 <&gcc GCC_PC <<
3009 <&gcc GCC_PC <<
3010 clock-names = "aux", <<
3011 "cfg_ah <<
3012 "ref", <<
3013 "rchng" <<
3014 "pipe", <<
3015 "pipedi <<
3016 <<
3017 resets = <&gcc GCC_PC <<
3018 <&gcc GCC_PC <<
3019 reset-names = "phy", <<
3020 "phy_no <<
3021 <<
3022 assigned-clocks = <&g <<
3023 assigned-clock-rates <<
3024 <<
3025 power-domains = <&gcc <<
3026 <<
3027 qcom,4ln-config-sel = <<
3028 <<
3029 #clock-cells = <0>; <<
3030 clock-output-names = <<
3031 <<
3032 #phy-cells = <0>; <<
3033 <<
3034 status = "disabled"; <<
3035 }; <<
3036 <<
3037 pcie5: pci@1c00000 { <<
3038 device_type = "pci"; <<
3039 compatible = "qcom,pc <<
3040 reg = <0 0x01c00000 0 <<
3041 <0 0x7e000000 0 <<
3042 <0 0x7e000f40 0 <<
3043 <0 0x7e001000 0 <<
3044 <0 0x7e100000 0 <<
3045 <0 0x01c03000 0 <<
3046 reg-names = "parf", <<
3047 "dbi", <<
3048 "elbi", <<
3049 "atu", <<
3050 "config", <<
3051 "mhi"; <<
3052 #address-cells = <3>; <<
3053 #size-cells = <2>; <<
3054 ranges = <0x01000000 <<
3055 <0x02000000 <<
3056 bus-range = <0x00 0xf <<
3057 <<
3058 dma-coherent; <<
3059 <<
3060 linux,pci-domain = <5 <<
3061 num-lanes = <2>; <<
3062 <<
3063 interrupts = <GIC_SPI <<
3064 <GIC_SPI <<
3065 <GIC_SPI <<
3066 <GIC_SPI <<
3067 <GIC_SPI <<
3068 <GIC_SPI <<
3069 <GIC_SPI <<
3070 <GIC_SPI <<
3071 interrupt-names = "ms <<
3072 "ms <<
3073 "ms <<
3074 "ms <<
3075 "ms <<
3076 "ms <<
3077 "ms <<
3078 "ms <<
3079 <<
3080 #interrupt-cells = <1 <<
3081 interrupt-map-mask = <<
3082 interrupt-map = <0 0 <<
3083 <0 0 <<
3084 <0 0 <<
3085 <0 0 <<
3086 <<
3087 clocks = <&gcc GCC_PC <<
3088 <&gcc GCC_PC <<
3089 <&gcc GCC_PC <<
3090 <&gcc GCC_PC <<
3091 <&gcc GCC_PC <<
3092 <&gcc GCC_CF <<
3093 <&gcc GCC_CN <<
3094 clock-names = "aux", <<
3095 "cfg", <<
3096 "bus_ma <<
3097 "bus_sl <<
3098 "slave_ <<
3099 "noc_ag <<
3100 "cnoc_s <<
3101 <<
3102 assigned-clocks = <&g <<
3103 assigned-clock-rates <<
3104 <<
3105 interconnects = <&pci <<
3106 &mc_ <<
3107 <&gem <<
3108 &cno <<
3109 interconnect-names = <<
3110 <<
3111 <<
3112 resets = <&gcc GCC_PC <<
3113 <&gcc GCC_PC <<
3114 reset-names = "pci", <<
3115 "link_d <<
3116 <<
3117 power-domains = <&gcc <<
3118 required-opps = <&rpm <<
3119 <<
3120 phys = <&pcie5_phy>; <<
3121 phy-names = "pciephy" <<
3122 <<
3123 status = "disabled"; <<
3124 }; <<
3125 <<
3126 pcie5_phy: phy@1c06000 { <<
3127 compatible = "qcom,x1 <<
3128 reg = <0 0x01c06000 0 <<
3129 <<
3130 clocks = <&gcc GCC_PC <<
3131 <&gcc GCC_PC <<
3132 <&tcsr TCSR_ <<
3133 <&gcc GCC_PC <<
3134 <&gcc GCC_PC <<
3135 <&gcc GCC_PC <<
3136 clock-names = "aux", <<
3137 "cfg_ah <<
3138 "ref", <<
3139 "rchng" <<
3140 "pipe", <<
3141 "pipedi <<
3142 <<
3143 resets = <&gcc GCC_PC <<
3144 reset-names = "phy"; <<
3145 <<
3146 assigned-clocks = <&g <<
3147 assigned-clock-rates <<
3148 <<
3149 power-domains = <&gcc <<
3150 <<
3151 #clock-cells = <0>; <<
3152 clock-output-names = <<
3153 <<
3154 #phy-cells = <0>; <<
3155 <<
3156 status = "disabled"; <<
3157 }; <<
3158 <<
3159 pcie4: pci@1c08000 { <<
3160 device_type = "pci"; <<
3161 compatible = "qcom,pc <<
3162 reg = <0 0x01c08000 0 <<
3163 <0 0x7c000000 0 <<
3164 <0 0x7c000f40 0 <<
3165 <0 0x7c001000 0 <<
3166 <0 0x7c100000 0 <<
3167 <0 0x01c0b000 0 <<
3168 reg-names = "parf", <<
3169 "dbi", <<
3170 "elbi", <<
3171 "atu", <<
3172 "config", <<
3173 "mhi"; <<
3174 #address-cells = <3>; <<
3175 #size-cells = <2>; <<
3176 ranges = <0x01000000 <<
3177 <0x02000000 <<
3178 bus-range = <0x00 0xf <<
3179 <<
3180 dma-coherent; <<
3181 <<
3182 linux,pci-domain = <4 <<
3183 num-lanes = <2>; <<
3184 <<
3185 interrupts = <GIC_SPI <<
3186 <GIC_SPI <<
3187 <GIC_SPI <<
3188 <GIC_SPI <<
3189 <GIC_SPI <<
3190 <GIC_SPI <<
3191 <GIC_SPI <<
3192 <GIC_SPI <<
3193 interrupt-names = "ms <<
3194 "ms <<
3195 "ms <<
3196 "ms <<
3197 "ms <<
3198 "ms <<
3199 "ms <<
3200 "ms <<
3201 <<
3202 #interrupt-cells = <1 <<
3203 interrupt-map-mask = <<
3204 interrupt-map = <0 0 <<
3205 <0 0 <<
3206 <0 0 <<
3207 <0 0 <<
3208 <<
3209 clocks = <&gcc GCC_PC <<
3210 <&gcc GCC_PC <<
3211 <&gcc GCC_PC <<
3212 <&gcc GCC_PC <<
3213 <&gcc GCC_PC <<
3214 <&gcc GCC_CF <<
3215 <&gcc GCC_CN <<
3216 clock-names = "aux", <<
3217 "cfg", <<
3218 "bus_ma <<
3219 "bus_sl <<
3220 "slave_ <<
3221 "noc_ag <<
3222 "cnoc_s <<
3223 <<
3224 assigned-clocks = <&g <<
3225 assigned-clock-rates <<
3226 <<
3227 interconnects = <&pci <<
3228 &mc_ <<
3229 <&gem <<
3230 &cno <<
3231 interconnect-names = <<
3232 <<
3233 <<
3234 resets = <&gcc GCC_PC <<
3235 <&gcc GCC_PC <<
3236 reset-names = "pci", <<
3237 "link_d <<
3238 <<
3239 power-domains = <&gcc <<
3240 required-opps = <&rpm <<
3241 <<
3242 phys = <&pcie4_phy>; <<
3243 phy-names = "pciephy" <<
3244 <<
3245 status = "disabled"; <<
3246 <<
3247 pcie4_port0: pcie@0 { <<
3248 device_type = <<
3249 reg = <0x0 0x <<
3250 bus-range = < <<
3251 <<
3252 #address-cell <<
3253 #size-cells = <<
3254 ranges; <<
3255 }; <<
3256 }; <<
3257 <<
3258 pcie4_phy: phy@1c0e000 { <<
3259 compatible = "qcom,x1 <<
3260 reg = <0 0x01c0e000 0 <<
3261 <<
3262 clocks = <&gcc GCC_PC <<
3263 <&gcc GCC_PC <<
3264 <&tcsr TCSR_ <<
3265 <&gcc GCC_PC <<
3266 <&gcc GCC_PC <<
3267 <&gcc GCC_PC <<
3268 clock-names = "aux", <<
3269 "cfg_ah <<
3270 "ref", <<
3271 "rchng" <<
3272 "pipe", <<
3273 "pipedi <<
3274 <<
3275 resets = <&gcc GCC_PC <<
3276 reset-names = "phy"; <<
3277 <<
3278 assigned-clocks = <&g <<
3279 assigned-clock-rates <<
3280 <<
3281 power-domains = <&gcc <<
3282 <<
3283 #clock-cells = <0>; <<
3284 clock-output-names = <<
3285 <<
3286 #phy-cells = <0>; <<
3287 <<
3288 status = "disabled"; <<
3289 }; <<
3290 <<
3291 tcsr_mutex: hwlock@1f40000 { 2539 tcsr_mutex: hwlock@1f40000 {
3292 compatible = "qcom,tc 2540 compatible = "qcom,tcsr-mutex";
3293 reg = <0 0x01f40000 0 2541 reg = <0 0x01f40000 0 0x20000>;
3294 #hwlock-cells = <1>; 2542 #hwlock-cells = <1>;
3295 }; 2543 };
3296 2544
3297 tcsr: clock-controller@1fc000 <<
3298 compatible = "qcom,x1 <<
3299 reg = <0 0x01fc0000 0 <<
3300 clocks = <&rpmhcc RPM <<
3301 #clock-cells = <1>; <<
3302 #reset-cells = <1>; <<
3303 }; <<
3304 <<
3305 gpu: gpu@3d00000 { <<
3306 compatible = "qcom,ad <<
3307 reg = <0x0 0x03d00000 <<
3308 <0x0 0x03d9e000 <<
3309 <0x0 0x03d61000 <<
3310 <<
3311 reg-names = "kgsl_3d0 <<
3312 "cx_mem", <<
3313 "cx_dbgc" <<
3314 <<
3315 interrupts = <GIC_SPI <<
3316 <<
3317 iommus = <&adreno_smm <<
3318 <&adreno_smm <<
3319 <<
3320 operating-points-v2 = <<
3321 <<
3322 qcom,gmu = <&gmu>; <<
3323 #cooling-cells = <2>; <<
3324 <<
3325 interconnects = <&gem <<
3326 interconnect-names = <<
3327 <<
3328 status = "disabled"; <<
3329 <<
3330 zap-shader { <<
3331 memory-region <<
3332 }; <<
3333 <<
3334 gpu_opp_table: opp-ta <<
3335 compatible = <<
3336 <<
3337 opp-110000000 <<
3338 opp-h <<
3339 opp-l <<
3340 opp-p <<
3341 }; <<
3342 <<
3343 opp-100000000 <<
3344 opp-h <<
3345 opp-l <<
3346 opp-p <<
3347 }; <<
3348 <<
3349 opp-925000000 <<
3350 opp-h <<
3351 opp-l <<
3352 opp-p <<
3353 }; <<
3354 <<
3355 opp-800000000 <<
3356 opp-h <<
3357 opp-l <<
3358 opp-p <<
3359 }; <<
3360 <<
3361 opp-744000000 <<
3362 opp-h <<
3363 opp-l <<
3364 opp-p <<
3365 }; <<
3366 <<
3367 opp-687000000 <<
3368 opp-h <<
3369 opp-l <<
3370 opp-p <<
3371 }; <<
3372 <<
3373 opp-550000000 <<
3374 opp-h <<
3375 opp-l <<
3376 opp-p <<
3377 }; <<
3378 <<
3379 opp-390000000 <<
3380 opp-h <<
3381 opp-l <<
3382 opp-p <<
3383 }; <<
3384 <<
3385 opp-300000000 <<
3386 opp-h <<
3387 opp-l <<
3388 opp-p <<
3389 }; <<
3390 }; <<
3391 }; <<
3392 <<
3393 gmu: gmu@3d6a000 { <<
3394 compatible = "qcom,ad <<
3395 reg = <0x0 0x03d6a000 <<
3396 <0x0 0x03d50000 <<
3397 <0x0 0x0b280000 <<
3398 reg-names = "gmu", " <<
3399 <<
3400 interrupts = <GIC_SPI <<
3401 <GIC_SPI <<
3402 interrupt-names = "hf <<
3403 <<
3404 clocks = <&gpucc GPU_ <<
3405 <&gpucc GPU_ <<
3406 <&gpucc GPU_ <<
3407 <&gcc GCC_DD <<
3408 <&gcc GCC_GP <<
3409 <&gpucc GPU_ <<
3410 <&gpucc GPU_ <<
3411 clock-names = "ahb", <<
3412 "gmu", <<
3413 "cxo", <<
3414 "axi", <<
3415 "memnoc <<
3416 "hub", <<
3417 "demet" <<
3418 <<
3419 power-domains = <&gpu <<
3420 <&gpu <<
3421 power-domain-names = <<
3422 <<
3423 <<
3424 iommus = <&adreno_smm <<
3425 <<
3426 qcom,qmp = <&aoss_qmp <<
3427 <<
3428 operating-points-v2 = <<
3429 <<
3430 gmu_opp_table: opp-ta <<
3431 compatible = <<
3432 <<
3433 opp-550000000 <<
3434 opp-h <<
3435 opp-l <<
3436 }; <<
3437 <<
3438 opp-220000000 <<
3439 opp-h <<
3440 opp-l <<
3441 }; <<
3442 }; <<
3443 }; <<
3444 <<
3445 gpucc: clock-controller@3d900 <<
3446 compatible = "qcom,x1 <<
3447 reg = <0 0x03d90000 0 <<
3448 clocks = <&bi_tcxo_di <<
3449 <&gcc GCC_GP <<
3450 <&gcc GCC_GP <<
3451 #clock-cells = <1>; <<
3452 #reset-cells = <1>; <<
3453 #power-domain-cells = <<
3454 }; <<
3455 <<
3456 adreno_smmu: iommu@3da0000 { <<
3457 compatible = "qcom,x1 <<
3458 "qcom,sm <<
3459 reg = <0x0 0x03da0000 <<
3460 #iommu-cells = <2>; <<
3461 #global-interrupts = <<
3462 interrupts = <GIC_SPI <<
3463 <GIC_SPI <<
3464 <GIC_SPI <<
3465 <GIC_SPI <<
3466 <GIC_SPI <<
3467 <GIC_SPI <<
3468 <GIC_SPI <<
3469 <GIC_SPI <<
3470 <GIC_SPI <<
3471 <GIC_SPI <<
3472 <GIC_SPI <<
3473 <GIC_SPI <<
3474 <GIC_SPI <<
3475 <GIC_SPI <<
3476 <GIC_SPI <<
3477 <GIC_SPI <<
3478 <GIC_SPI <<
3479 <GIC_SPI <<
3480 <GIC_SPI <<
3481 <GIC_SPI <<
3482 <GIC_SPI <<
3483 <GIC_SPI <<
3484 <GIC_SPI <<
3485 <GIC_SPI <<
3486 <GIC_SPI <<
3487 <GIC_SPI <<
3488 clocks = <&gpucc GPU_ <<
3489 <&gcc GCC_GP <<
3490 <&gcc GCC_GP <<
3491 <&gpucc GPU_ <<
3492 clock-names = "hlos", <<
3493 "bus", <<
3494 "iface" <<
3495 "ahb"; <<
3496 power-domains = <&gpu <<
3497 dma-coherent; <<
3498 }; <<
3499 <<
3500 gem_noc: interconnect@2640000 2545 gem_noc: interconnect@26400000 {
3501 compatible = "qcom,x1 2546 compatible = "qcom,x1e80100-gem-noc";
3502 reg = <0 0x26400000 0 2547 reg = <0 0x26400000 0 0x311200>;
3503 2548
3504 qcom,bcm-voters = <&a 2549 qcom,bcm-voters = <&apps_bcm_voter>;
3505 2550
3506 #interconnect-cells = 2551 #interconnect-cells = <2>;
3507 }; 2552 };
3508 2553
3509 nsp_noc: interconnect@320c000 2554 nsp_noc: interconnect@320c0000 {
3510 compatible = "qcom,x1 2555 compatible = "qcom,x1e80100-nsp-noc";
3511 reg = <0 0x320C0000 0 !! 2556 reg = <0 0x320C0000 0 0xE080>;
3512 2557
3513 qcom,bcm-voters = <&a 2558 qcom,bcm-voters = <&apps_bcm_voter>;
3514 2559
3515 #interconnect-cells = 2560 #interconnect-cells = <2>;
3516 }; 2561 };
3517 2562
3518 lpass_wsa2macro: codec@6aa000 <<
3519 compatible = "qcom,x1 <<
3520 reg = <0 0x06aa0000 0 <<
3521 clocks = <&q6prmcc LP <<
3522 <&q6prmcc LP <<
3523 <&q6prmcc LP <<
3524 <&lpass_vama <<
3525 clock-names = "mclk", <<
3526 "macro" <<
3527 "dcodec <<
3528 "fsgen" <<
3529 <<
3530 #clock-cells = <0>; <<
3531 clock-output-names = <<
3532 #sound-dai-cells = <1 <<
3533 sound-name-prefix = " <<
3534 }; <<
3535 <<
3536 swr3: soundwire@6ab0000 { <<
3537 compatible = "qcom,so <<
3538 reg = <0 0x06ab0000 0 <<
3539 clocks = <&lpass_wsa2 <<
3540 clock-names = "iface" <<
3541 interrupts = <GIC_SPI <<
3542 label = "WSA2"; <<
3543 <<
3544 pinctrl-0 = <&wsa2_sw <<
3545 pinctrl-names = "defa <<
3546 resets = <&lpass_audi <<
3547 reset-names = "swr_au <<
3548 <<
3549 qcom,din-ports = <4>; <<
3550 qcom,dout-ports = <9> <<
3551 <<
3552 qcom,ports-sinterval <<
3553 qcom,ports-offset1 = <<
3554 qcom,ports-offset2 = <<
3555 qcom,ports-hstart = <<
3556 qcom,ports-hstop = <<
3557 qcom,ports-word-lengt <<
3558 qcom,ports-block-pack <<
3559 qcom,ports-block-grou <<
3560 qcom,ports-lane-contr <<
3561 <<
3562 #address-cells = <2>; <<
3563 #size-cells = <0>; <<
3564 #sound-dai-cells = <1 <<
3565 status = "disabled"; <<
3566 }; <<
3567 <<
3568 lpass_rxmacro: codec@6ac0000 <<
3569 compatible = "qcom,x1 <<
3570 reg = <0 0x06ac0000 0 <<
3571 clocks = <&q6prmcc LP <<
3572 <&q6prmcc LP <<
3573 <&q6prmcc LP <<
3574 <&lpass_vama <<
3575 clock-names = "mclk", <<
3576 "macro" <<
3577 "dcodec <<
3578 "fsgen" <<
3579 <<
3580 #clock-cells = <0>; <<
3581 clock-output-names = <<
3582 #sound-dai-cells = <1 <<
3583 }; <<
3584 <<
3585 swr1: soundwire@6ad0000 { <<
3586 compatible = "qcom,so <<
3587 reg = <0 0x06ad0000 0 <<
3588 clocks = <&lpass_rxma <<
3589 clock-names = "iface" <<
3590 interrupts = <GIC_SPI <<
3591 label = "RX"; <<
3592 <<
3593 pinctrl-0 = <&rx_swr_ <<
3594 pinctrl-names = "defa <<
3595 <<
3596 resets = <&lpass_audi <<
3597 reset-names = "swr_au <<
3598 qcom,din-ports = <1>; <<
3599 qcom,dout-ports = <11 <<
3600 <<
3601 qcom,ports-sinterval <<
3602 qcom,ports-offset1 = <<
3603 qcom,ports-offset2 = <<
3604 qcom,ports-hstart = <<
3605 qcom,ports-hstop = <<
3606 qcom,ports-word-lengt <<
3607 qcom,ports-block-pack <<
3608 qcom,ports-block-grou <<
3609 qcom,ports-lane-contr <<
3610 <<
3611 #address-cells = <2>; <<
3612 #size-cells = <0>; <<
3613 #sound-dai-cells = <1 <<
3614 status = "disabled"; <<
3615 }; <<
3616 <<
3617 lpass_txmacro: codec@6ae0000 <<
3618 compatible = "qcom,x1 <<
3619 reg = <0 0x06ae0000 0 <<
3620 clocks = <&q6prmcc LP <<
3621 <&q6prmcc LP <<
3622 <&q6prmcc LP <<
3623 <&lpass_vama <<
3624 clock-names = "mclk", <<
3625 "macro" <<
3626 "dcodec <<
3627 "fsgen" <<
3628 <<
3629 #clock-cells = <0>; <<
3630 clock-output-names = <<
3631 #sound-dai-cells = <1 <<
3632 }; <<
3633 <<
3634 lpass_wsamacro: codec@6b00000 <<
3635 compatible = "qcom,x1 <<
3636 reg = <0 0x06b00000 0 <<
3637 clocks = <&q6prmcc LP <<
3638 <&q6prmcc LP <<
3639 <&q6prmcc LP <<
3640 <&lpass_vama <<
3641 clock-names = "mclk", <<
3642 "macro" <<
3643 "dcodec <<
3644 "fsgen" <<
3645 <<
3646 #clock-cells = <0>; <<
3647 clock-output-names = <<
3648 #sound-dai-cells = <1 <<
3649 sound-name-prefix = " <<
3650 }; <<
3651 <<
3652 swr0: soundwire@6b10000 { <<
3653 compatible = "qcom,so <<
3654 reg = <0 0x06b10000 0 <<
3655 clocks = <&lpass_wsam <<
3656 clock-names = "iface" <<
3657 interrupts = <GIC_SPI <<
3658 label = "WSA"; <<
3659 <<
3660 pinctrl-0 = <&wsa_swr <<
3661 pinctrl-names = "defa <<
3662 resets = <&lpass_audi <<
3663 reset-names = "swr_au <<
3664 <<
3665 qcom,din-ports = <4>; <<
3666 qcom,dout-ports = <9> <<
3667 <<
3668 qcom,ports-sinterval <<
3669 qcom,ports-offset1 = <<
3670 qcom,ports-offset2 = <<
3671 qcom,ports-hstart = <<
3672 qcom,ports-hstop = <<
3673 qcom,ports-word-lengt <<
3674 qcom,ports-block-pack <<
3675 qcom,ports-block-grou <<
3676 qcom,ports-lane-contr <<
3677 <<
3678 #address-cells = <2>; <<
3679 #size-cells = <0>; <<
3680 #sound-dai-cells = <1 <<
3681 status = "disabled"; <<
3682 }; <<
3683 <<
3684 lpass_audiocc: clock-controll <<
3685 compatible = "qcom,x1 <<
3686 reg = <0 0x06b6c000 0 <<
3687 #clock-cells = <1>; <<
3688 #reset-cells = <1>; <<
3689 }; <<
3690 <<
3691 swr2: soundwire@6d30000 { <<
3692 compatible = "qcom,so <<
3693 reg = <0 0x06d30000 0 <<
3694 clocks = <&lpass_txma <<
3695 clock-names = "iface" <<
3696 interrupts = <GIC_SPI <<
3697 <GIC_SPI <<
3698 interrupt-names = "co <<
3699 label = "TX"; <<
3700 resets = <&lpasscc LP <<
3701 reset-names = "swr_au <<
3702 <<
3703 pinctrl-0 = <&tx_swr_ <<
3704 pinctrl-names = "defa <<
3705 <<
3706 qcom,din-ports = <4>; <<
3707 qcom,dout-ports = <1> <<
3708 <<
3709 qcom,ports-sinterval- <<
3710 qcom,ports-offset1 = <<
3711 qcom,ports-offset2 = <<
3712 qcom,ports-hstart = <<
3713 qcom,ports-hstop = <<
3714 qcom,ports-word-lengt <<
3715 qcom,ports-block-pack <<
3716 qcom,ports-block-grou <<
3717 qcom,ports-lane-contr <<
3718 <<
3719 #address-cells = <2>; <<
3720 #size-cells = <0>; <<
3721 #sound-dai-cells = <1 <<
3722 status = "disabled"; <<
3723 }; <<
3724 <<
3725 lpass_vamacro: codec@6d44000 <<
3726 compatible = "qcom,x1 <<
3727 reg = <0 0x06d44000 0 <<
3728 clocks = <&q6prmcc LP <<
3729 <&q6prmcc LP <<
3730 <&q6prmcc LP <<
3731 clock-names = "mclk", <<
3732 "macro" <<
3733 "dcodec <<
3734 <<
3735 #clock-cells = <0>; <<
3736 clock-output-names = <<
3737 #sound-dai-cells = <1 <<
3738 }; <<
3739 <<
3740 lpass_tlmm: pinctrl@6e80000 { <<
3741 compatible = "qcom,x1 <<
3742 reg = <0 0x06e80000 0 <<
3743 <0 0x07250000 0 <<
3744 <<
3745 clocks = <&q6prmcc LP <<
3746 <&q6prmcc LP <<
3747 clock-names = "core", <<
3748 <<
3749 gpio-controller; <<
3750 #gpio-cells = <2>; <<
3751 gpio-ranges = <&lpass <<
3752 <<
3753 tx_swr_active: tx-swr <<
3754 clk-pins { <<
3755 pins <<
3756 funct <<
3757 drive <<
3758 slew- <<
3759 bias- <<
3760 }; <<
3761 <<
3762 data-pins { <<
3763 pins <<
3764 funct <<
3765 drive <<
3766 slew- <<
3767 bias- <<
3768 }; <<
3769 }; <<
3770 <<
3771 rx_swr_active: rx-swr <<
3772 clk-pins { <<
3773 pins <<
3774 funct <<
3775 drive <<
3776 slew- <<
3777 bias- <<
3778 }; <<
3779 <<
3780 data-pins { <<
3781 pins <<
3782 funct <<
3783 drive <<
3784 slew- <<
3785 bias- <<
3786 }; <<
3787 }; <<
3788 <<
3789 dmic01_default: dmic0 <<
3790 clk-pins { <<
3791 pins <<
3792 funct <<
3793 drive <<
3794 outpu <<
3795 }; <<
3796 <<
3797 data-pins { <<
3798 pins <<
3799 funct <<
3800 drive <<
3801 input <<
3802 }; <<
3803 }; <<
3804 <<
3805 dmic23_default: dmic2 <<
3806 clk-pins { <<
3807 pins <<
3808 funct <<
3809 drive <<
3810 outpu <<
3811 }; <<
3812 <<
3813 data-pins { <<
3814 pins <<
3815 funct <<
3816 drive <<
3817 input <<
3818 }; <<
3819 }; <<
3820 <<
3821 wsa_swr_active: wsa-s <<
3822 clk-pins { <<
3823 pins <<
3824 funct <<
3825 drive <<
3826 slew- <<
3827 bias- <<
3828 }; <<
3829 <<
3830 data-pins { <<
3831 pins <<
3832 funct <<
3833 drive <<
3834 slew- <<
3835 bias- <<
3836 }; <<
3837 }; <<
3838 <<
3839 wsa2_swr_active: wsa2 <<
3840 clk-pins { <<
3841 pins <<
3842 funct <<
3843 drive <<
3844 slew- <<
3845 bias- <<
3846 }; <<
3847 <<
3848 data-pins { <<
3849 pins <<
3850 funct <<
3851 drive <<
3852 slew- <<
3853 bias- <<
3854 }; <<
3855 }; <<
3856 }; <<
3857 <<
3858 lpasscc: clock-controller@6ea <<
3859 compatible = "qcom,x1 <<
3860 reg = <0 0x06ea0000 0 <<
3861 #clock-cells = <1>; <<
3862 #reset-cells = <1>; <<
3863 }; <<
3864 <<
3865 lpass_ag_noc: interconnect@7e 2563 lpass_ag_noc: interconnect@7e40000 {
3866 compatible = "qcom,x1 2564 compatible = "qcom,x1e80100-lpass-ag-noc";
3867 reg = <0 0x07e40000 0 !! 2565 reg = <0 0x7e40000 0 0xE080>;
3868 2566
3869 qcom,bcm-voters = <&a 2567 qcom,bcm-voters = <&apps_bcm_voter>;
3870 2568
3871 #interconnect-cells = 2569 #interconnect-cells = <2>;
3872 }; 2570 };
3873 2571
3874 lpass_lpiaon_noc: interconnec 2572 lpass_lpiaon_noc: interconnect@7400000 {
3875 compatible = "qcom,x1 2573 compatible = "qcom,x1e80100-lpass-lpiaon-noc";
3876 reg = <0 0x07400000 0 !! 2574 reg = <0 0x7400000 0 0x19080>;
3877 2575
3878 qcom,bcm-voters = <&a 2576 qcom,bcm-voters = <&apps_bcm_voter>;
3879 2577
3880 #interconnect-cells = 2578 #interconnect-cells = <2>;
3881 }; 2579 };
3882 2580
3883 lpass_lpicx_noc: interconnect 2581 lpass_lpicx_noc: interconnect@7430000 {
3884 compatible = "qcom,x1 2582 compatible = "qcom,x1e80100-lpass-lpicx-noc";
3885 reg = <0 0x07430000 0 !! 2583 reg = <0 0x7430000 0 0x3A200>;
3886 2584
3887 qcom,bcm-voters = <&a 2585 qcom,bcm-voters = <&apps_bcm_voter>;
3888 2586
3889 #interconnect-cells = 2587 #interconnect-cells = <2>;
3890 }; 2588 };
3891 2589
3892 usb_2_hsphy: phy@88e0000 { <<
3893 compatible = "qcom,x1 <<
3894 "qcom,sm <<
3895 reg = <0 0x088e0000 0 <<
3896 #phy-cells = <0>; <<
3897 <<
3898 clocks = <&tcsr TCSR_ <<
3899 clock-names = "ref"; <<
3900 <<
3901 resets = <&gcc GCC_QU <<
3902 <<
3903 status = "disabled"; <<
3904 }; <<
3905 <<
3906 usb_mp_hsphy0: phy@88e1000 { <<
3907 compatible = "qcom,x1 <<
3908 "qcom,sm <<
3909 reg = <0 0x088e1000 0 <<
3910 #phy-cells = <0>; <<
3911 <<
3912 clocks = <&tcsr TCSR_ <<
3913 clock-names = "ref"; <<
3914 <<
3915 resets = <&gcc GCC_QU <<
3916 <<
3917 status = "disabled"; <<
3918 }; <<
3919 <<
3920 usb_mp_hsphy1: phy@88e2000 { <<
3921 compatible = "qcom,x1 <<
3922 "qcom,sm <<
3923 reg = <0 0x088e2000 0 <<
3924 #phy-cells = <0>; <<
3925 <<
3926 clocks = <&tcsr TCSR_ <<
3927 clock-names = "ref"; <<
3928 <<
3929 resets = <&gcc GCC_QU <<
3930 <<
3931 status = "disabled"; <<
3932 }; <<
3933 <<
3934 usb_mp_qmpphy0: phy@88e3000 { <<
3935 compatible = "qcom,x1 <<
3936 reg = <0 0x088e3000 0 <<
3937 <<
3938 clocks = <&gcc GCC_US <<
3939 <&rpmhcc RPM <<
3940 <&gcc GCC_US <<
3941 <&gcc GCC_US <<
3942 clock-names = "aux", <<
3943 "ref", <<
3944 "com_au <<
3945 "pipe"; <<
3946 <<
3947 resets = <&gcc GCC_US <<
3948 <&gcc GCC_US <<
3949 reset-names = "phy", <<
3950 "phy_ph <<
3951 <<
3952 power-domains = <&gcc <<
3953 <<
3954 #clock-cells = <0>; <<
3955 clock-output-names = <<
3956 <<
3957 #phy-cells = <0>; <<
3958 <<
3959 status = "disabled"; <<
3960 }; <<
3961 <<
3962 usb_mp_qmpphy1: phy@88e5000 { <<
3963 compatible = "qcom,x1 <<
3964 reg = <0 0x088e5000 0 <<
3965 <<
3966 clocks = <&gcc GCC_US <<
3967 <&rpmhcc RPM <<
3968 <&gcc GCC_US <<
3969 <&gcc GCC_US <<
3970 clock-names = "aux", <<
3971 "ref", <<
3972 "com_au <<
3973 "pipe"; <<
3974 <<
3975 resets = <&gcc GCC_US <<
3976 <&gcc GCC_US <<
3977 reset-names = "phy", <<
3978 "phy_ph <<
3979 <<
3980 power-domains = <&gcc <<
3981 <<
3982 #clock-cells = <0>; <<
3983 clock-output-names = <<
3984 <<
3985 #phy-cells = <0>; <<
3986 <<
3987 status = "disabled"; <<
3988 }; <<
3989 <<
3990 usb_1_ss2: usb@a0f8800 { <<
3991 compatible = "qcom,x1 <<
3992 reg = <0 0x0a0f8800 0 <<
3993 <<
3994 clocks = <&gcc GCC_CF <<
3995 <&gcc GCC_US <<
3996 <&gcc GCC_AG <<
3997 <&gcc GCC_US <<
3998 <&gcc GCC_US <<
3999 <&gcc GCC_AG <<
4000 <&gcc GCC_AG <<
4001 <&gcc GCC_AG <<
4002 <&gcc GCC_SY <<
4003 clock-names = "cfg_no <<
4004 "core", <<
4005 "iface" <<
4006 "sleep" <<
4007 "mock_u <<
4008 "noc_ag <<
4009 "noc_ag <<
4010 "noc_ag <<
4011 "noc_sy <<
4012 <<
4013 assigned-clocks = <&g <<
4014 <&g <<
4015 assigned-clock-rates <<
4016 <<
4017 <<
4018 interrupts-extended = <<
4019 <<
4020 <<
4021 <<
4022 interrupt-names = "pw <<
4023 "dp <<
4024 "dm <<
4025 "ss <<
4026 <<
4027 power-domains = <&gcc <<
4028 required-opps = <&rpm <<
4029 <<
4030 resets = <&gcc GCC_US <<
4031 <<
4032 interconnects = <&usb <<
4033 &mc_ <<
4034 <&gem <<
4035 &con <<
4036 interconnect-names = <<
4037 <<
4038 <<
4039 wakeup-source; <<
4040 <<
4041 #address-cells = <2>; <<
4042 #size-cells = <2>; <<
4043 ranges; <<
4044 <<
4045 status = "disabled"; <<
4046 <<
4047 usb_1_ss2_dwc3: usb@a <<
4048 compatible = <<
4049 reg = <0 0x0a <<
4050 <<
4051 interrupts = <<
4052 <<
4053 iommus = <&ap <<
4054 <<
4055 phys = <&usb_ <<
4056 <&usb_ <<
4057 phy-names = " <<
4058 " <<
4059 <<
4060 snps,dis_u2_s <<
4061 snps,dis_enbl <<
4062 snps,usb3_lpm <<
4063 <<
4064 dma-coherent; <<
4065 <<
4066 ports { <<
4067 #addr <<
4068 #size <<
4069 <<
4070 port@ <<
4071 <<
4072 <<
4073 <<
4074 <<
4075 }; <<
4076 <<
4077 port@ <<
4078 <<
4079 <<
4080 <<
4081 <<
4082 <<
4083 }; <<
4084 }; <<
4085 }; <<
4086 }; <<
4087 <<
4088 usb_2: usb@a2f8800 { <<
4089 compatible = "qcom,x1 <<
4090 reg = <0 0x0a2f8800 0 <<
4091 #address-cells = <2>; <<
4092 #size-cells = <2>; <<
4093 ranges; <<
4094 <<
4095 clocks = <&gcc GCC_CF <<
4096 <&gcc GCC_US <<
4097 <&gcc GCC_AG <<
4098 <&gcc GCC_US <<
4099 <&gcc GCC_US <<
4100 <&gcc GCC_AG <<
4101 <&gcc GCC_AG <<
4102 <&gcc GCC_AG <<
4103 <&gcc GCC_SY <<
4104 clock-names = "cfg_no <<
4105 "core", <<
4106 "iface" <<
4107 "sleep" <<
4108 "mock_u <<
4109 "noc_ag <<
4110 "noc_ag <<
4111 "noc_ag <<
4112 "noc_sy <<
4113 <<
4114 assigned-clocks = <&g <<
4115 <&g <<
4116 assigned-clock-rates <<
4117 <<
4118 interrupts-extended = <<
4119 <<
4120 <<
4121 interrupt-names = "pw <<
4122 "dp <<
4123 "dm <<
4124 <<
4125 power-domains = <&gcc <<
4126 required-opps = <&rpm <<
4127 <<
4128 resets = <&gcc GCC_US <<
4129 <<
4130 interconnects = <&usb <<
4131 &mc_ <<
4132 <&gem <<
4133 &con <<
4134 interconnect-names = <<
4135 <<
4136 <<
4137 wakeup-source; <<
4138 <<
4139 status = "disabled"; <<
4140 <<
4141 usb_2_dwc3: usb@a2000 <<
4142 compatible = <<
4143 reg = <0 0x0a <<
4144 interrupts = <<
4145 iommus = <&ap <<
4146 phys = <&usb_ <<
4147 phy-names = " <<
4148 maximum-speed <<
4149 <<
4150 ports { <<
4151 #addr <<
4152 #size <<
4153 <<
4154 port@ <<
4155 <<
4156 <<
4157 <<
4158 <<
4159 }; <<
4160 }; <<
4161 }; <<
4162 }; <<
4163 <<
4164 usb_mp: usb@a4f8800 { <<
4165 compatible = "qcom,x1 <<
4166 reg = <0 0x0a4f8800 0 <<
4167 <<
4168 clocks = <&gcc GCC_CF <<
4169 <&gcc GCC_US <<
4170 <&gcc GCC_AG <<
4171 <&gcc GCC_US <<
4172 <&gcc GCC_US <<
4173 <&gcc GCC_AG <<
4174 <&gcc GCC_AG <<
4175 <&gcc GCC_AG <<
4176 <&gcc GCC_SY <<
4177 clock-names = "cfg_no <<
4178 "core", <<
4179 "iface" <<
4180 "sleep" <<
4181 "mock_u <<
4182 "noc_ag <<
4183 "noc_ag <<
4184 "noc_ag <<
4185 "noc_sy <<
4186 <<
4187 assigned-clocks = <&g <<
4188 <&g <<
4189 assigned-clock-rates <<
4190 <<
4191 <<
4192 interrupts-extended = <<
4193 <<
4194 <<
4195 <<
4196 <<
4197 <<
4198 <<
4199 <<
4200 <<
4201 <<
4202 interrupt-names = "pw <<
4203 "hs <<
4204 "dp <<
4205 "dp <<
4206 "ss <<
4207 <<
4208 power-domains = <&gcc <<
4209 required-opps = <&rpm <<
4210 <<
4211 resets = <&gcc GCC_US <<
4212 <<
4213 interconnects = <&usb <<
4214 &mc_ <<
4215 <&gem <<
4216 &con <<
4217 interconnect-names = <<
4218 <<
4219 <<
4220 wakeup-source; <<
4221 <<
4222 #address-cells = <2>; <<
4223 #size-cells = <2>; <<
4224 ranges; <<
4225 <<
4226 status = "disabled"; <<
4227 <<
4228 usb_mp_dwc3: usb@a400 <<
4229 compatible = <<
4230 reg = <0 0x0a <<
4231 <<
4232 interrupts = <<
4233 <<
4234 iommus = <&ap <<
4235 <<
4236 phys = <&usb_ <<
4237 <&usb_ <<
4238 phy-names = " <<
4239 " <<
4240 dr_mode = "ho <<
4241 <<
4242 snps,dis_u2_s <<
4243 snps,dis_enbl <<
4244 snps,usb3_lpm <<
4245 <<
4246 dma-coherent; <<
4247 }; <<
4248 }; <<
4249 <<
4250 usb_1_ss0: usb@a6f8800 { <<
4251 compatible = "qcom,x1 <<
4252 reg = <0 0x0a6f8800 0 <<
4253 <<
4254 clocks = <&gcc GCC_CF <<
4255 <&gcc GCC_US <<
4256 <&gcc GCC_AG <<
4257 <&gcc GCC_US <<
4258 <&gcc GCC_US <<
4259 <&gcc GCC_AG <<
4260 <&gcc GCC_CF <<
4261 <&gcc GCC_CF <<
4262 <&gcc GCC_SY <<
4263 clock-names = "cfg_no <<
4264 "core", <<
4265 "iface" <<
4266 "sleep" <<
4267 "mock_u <<
4268 "noc_ag <<
4269 "noc_ag <<
4270 "noc_ag <<
4271 "noc_sy <<
4272 <<
4273 assigned-clocks = <&g <<
4274 <&g <<
4275 assigned-clock-rates <<
4276 <<
4277 <<
4278 interrupts-extended = <<
4279 <<
4280 <<
4281 <<
4282 interrupt-names = "pw <<
4283 "dp <<
4284 "dm <<
4285 "ss <<
4286 <<
4287 power-domains = <&gcc <<
4288 required-opps = <&rpm <<
4289 <<
4290 resets = <&gcc GCC_US <<
4291 <<
4292 wakeup-source; <<
4293 <<
4294 #address-cells = <2>; <<
4295 #size-cells = <2>; <<
4296 ranges; <<
4297 <<
4298 status = "disabled"; <<
4299 <<
4300 usb_1_ss0_dwc3: usb@a <<
4301 compatible = <<
4302 reg = <0 0x0a <<
4303 <<
4304 interrupts = <<
4305 <<
4306 iommus = <&ap <<
4307 <<
4308 phys = <&usb_ <<
4309 <&usb_ <<
4310 phy-names = " <<
4311 " <<
4312 <<
4313 snps,dis_u2_s <<
4314 snps,dis_enbl <<
4315 snps,usb3_lpm <<
4316 <<
4317 dma-coherent; <<
4318 <<
4319 ports { <<
4320 #addr <<
4321 #size <<
4322 <<
4323 port@ <<
4324 <<
4325 <<
4326 <<
4327 <<
4328 }; <<
4329 <<
4330 port@ <<
4331 <<
4332 <<
4333 <<
4334 <<
4335 <<
4336 }; <<
4337 }; <<
4338 }; <<
4339 }; <<
4340 <<
4341 usb_1_ss1: usb@a8f8800 { <<
4342 compatible = "qcom,x1 <<
4343 reg = <0 0x0a8f8800 0 <<
4344 <<
4345 clocks = <&gcc GCC_CF <<
4346 <&gcc GCC_US <<
4347 <&gcc GCC_AG <<
4348 <&gcc GCC_US <<
4349 <&gcc GCC_US <<
4350 <&gcc GCC_AG <<
4351 <&gcc GCC_AG <<
4352 <&gcc GCC_AG <<
4353 <&gcc GCC_SY <<
4354 clock-names = "cfg_no <<
4355 "core", <<
4356 "iface" <<
4357 "sleep" <<
4358 "mock_u <<
4359 "noc_ag <<
4360 "noc_ag <<
4361 "noc_ag <<
4362 "noc_sy <<
4363 <<
4364 assigned-clocks = <&g <<
4365 <&g <<
4366 assigned-clock-rates <<
4367 <<
4368 <<
4369 interrupts-extended = <<
4370 <<
4371 <<
4372 <<
4373 interrupt-names = "pw <<
4374 "dp <<
4375 "dm <<
4376 "ss <<
4377 <<
4378 power-domains = <&gcc <<
4379 required-opps = <&rpm <<
4380 <<
4381 resets = <&gcc GCC_US <<
4382 <<
4383 interconnects = <&usb <<
4384 &mc_ <<
4385 <&gem <<
4386 &con <<
4387 interconnect-names = <<
4388 <<
4389 <<
4390 wakeup-source; <<
4391 <<
4392 #address-cells = <2>; <<
4393 #size-cells = <2>; <<
4394 ranges; <<
4395 <<
4396 status = "disabled"; <<
4397 <<
4398 usb_1_ss1_dwc3: usb@a <<
4399 compatible = <<
4400 reg = <0 0x0a <<
4401 <<
4402 interrupts = <<
4403 <<
4404 iommus = <&ap <<
4405 <<
4406 phys = <&usb_ <<
4407 <&usb_ <<
4408 phy-names = " <<
4409 " <<
4410 <<
4411 snps,dis_u2_s <<
4412 snps,dis_enbl <<
4413 snps,usb3_lpm <<
4414 <<
4415 dma-coherent; <<
4416 <<
4417 ports { <<
4418 #addr <<
4419 #size <<
4420 <<
4421 port@ <<
4422 <<
4423 <<
4424 <<
4425 <<
4426 }; <<
4427 <<
4428 port@ <<
4429 <<
4430 <<
4431 <<
4432 <<
4433 <<
4434 }; <<
4435 }; <<
4436 }; <<
4437 }; <<
4438 <<
4439 mdss: display-subsystem@ae000 <<
4440 compatible = "qcom,x1 <<
4441 reg = <0 0x0ae00000 0 <<
4442 reg-names = "mdss"; <<
4443 <<
4444 interrupts = <GIC_SPI <<
4445 <<
4446 clocks = <&dispcc DIS <<
4447 <&gcc GCC_DI <<
4448 <&dispcc DIS <<
4449 <<
4450 resets = <&dispcc DIS <<
4451 <<
4452 interconnects = <&mms <<
4453 &gem <<
4454 <&mc_ <<
4455 &mc_ <<
4456 <&gem <<
4457 &con <<
4458 interconnect-names = <<
4459 <<
4460 <<
4461 <<
4462 power-domains = <&dis <<
4463 <<
4464 iommus = <&apps_smmu <<
4465 <<
4466 interrupt-controller; <<
4467 #interrupt-cells = <1 <<
4468 <<
4469 #address-cells = <2>; <<
4470 #size-cells = <2>; <<
4471 ranges; <<
4472 <<
4473 status = "disabled"; <<
4474 <<
4475 mdss_mdp: display-con <<
4476 compatible = <<
4477 reg = <0 0x0a <<
4478 <0 0x0a <<
4479 reg-names = " <<
4480 " <<
4481 <<
4482 interrupts-ex <<
4483 <<
4484 clocks = <&gc <<
4485 <&di <<
4486 <&di <<
4487 <&di <<
4488 <&di <<
4489 clock-names = <<
4490 <<
4491 <<
4492 <<
4493 <<
4494 <<
4495 operating-poi <<
4496 <<
4497 power-domains <<
4498 <<
4499 ports { <<
4500 #addr <<
4501 #size <<
4502 <<
4503 port@ <<
4504 <<
4505 <<
4506 <<
4507 <<
4508 <<
4509 }; <<
4510 <<
4511 port@ <<
4512 <<
4513 <<
4514 <<
4515 <<
4516 <<
4517 }; <<
4518 <<
4519 port@ <<
4520 <<
4521 <<
4522 <<
4523 <<
4524 <<
4525 }; <<
4526 <<
4527 port@ <<
4528 <<
4529 <<
4530 <<
4531 <<
4532 <<
4533 }; <<
4534 }; <<
4535 <<
4536 mdp_opp_table <<
4537 compa <<
4538 <<
4539 opp-2 <<
4540 <<
4541 <<
4542 }; <<
4543 <<
4544 opp-3 <<
4545 <<
4546 <<
4547 }; <<
4548 <<
4549 opp-3 <<
4550 <<
4551 <<
4552 }; <<
4553 <<
4554 opp-5 <<
4555 <<
4556 <<
4557 }; <<
4558 <<
4559 opp-5 <<
4560 <<
4561 <<
4562 }; <<
4563 }; <<
4564 }; <<
4565 <<
4566 mdss_dp0: displayport <<
4567 compatible = <<
4568 reg = <0 0x0a <<
4569 <0 0x0a <<
4570 <0 0x0a <<
4571 <0 0x0a <<
4572 <0 0x0a <<
4573 <<
4574 interrupts-ex <<
4575 <<
4576 clocks = <&di <<
4577 <&di <<
4578 <&di <<
4579 <&di <<
4580 <&di <<
4581 clock-names = <<
4582 <<
4583 <<
4584 <<
4585 <<
4586 <<
4587 assigned-cloc <<
4588 <<
4589 assigned-cloc <<
4590 <<
4591 <<
4592 operating-poi <<
4593 <<
4594 power-domains <<
4595 <<
4596 phys = <&usb_ <<
4597 phy-names = " <<
4598 <<
4599 #sound-dai-ce <<
4600 <<
4601 status = "dis <<
4602 <<
4603 ports { <<
4604 #addr <<
4605 #size <<
4606 <<
4607 port@ <<
4608 <<
4609 <<
4610 <<
4611 <<
4612 <<
4613 }; <<
4614 <<
4615 port@ <<
4616 <<
4617 <<
4618 <<
4619 <<
4620 <<
4621 }; <<
4622 }; <<
4623 <<
4624 mdss_dp0_opp_ <<
4625 compa <<
4626 <<
4627 opp-1 <<
4628 <<
4629 <<
4630 }; <<
4631 <<
4632 opp-2 <<
4633 <<
4634 <<
4635 }; <<
4636 <<
4637 opp-5 <<
4638 <<
4639 <<
4640 }; <<
4641 <<
4642 opp-8 <<
4643 <<
4644 <<
4645 }; <<
4646 }; <<
4647 }; <<
4648 <<
4649 mdss_dp1: displayport <<
4650 compatible = <<
4651 reg = <0 0x0a <<
4652 <0 0x0a <<
4653 <0 0x0a <<
4654 <0 0x0a <<
4655 <0 0x0a <<
4656 <<
4657 interrupts-ex <<
4658 <<
4659 clocks = <&di <<
4660 <&di <<
4661 <&di <<
4662 <&di <<
4663 <&di <<
4664 clock-names = <<
4665 <<
4666 <<
4667 <<
4668 <<
4669 <<
4670 assigned-cloc <<
4671 <<
4672 assigned-cloc <<
4673 <<
4674 <<
4675 operating-poi <<
4676 <<
4677 power-domains <<
4678 <<
4679 phys = <&usb_ <<
4680 phy-names = " <<
4681 <<
4682 #sound-dai-ce <<
4683 <<
4684 status = "dis <<
4685 <<
4686 ports { <<
4687 #addr <<
4688 #size <<
4689 <<
4690 port@ <<
4691 <<
4692 <<
4693 <<
4694 <<
4695 <<
4696 }; <<
4697 <<
4698 port@ <<
4699 <<
4700 <<
4701 <<
4702 <<
4703 <<
4704 }; <<
4705 }; <<
4706 <<
4707 mdss_dp1_opp_ <<
4708 compa <<
4709 <<
4710 opp-1 <<
4711 <<
4712 <<
4713 }; <<
4714 <<
4715 opp-2 <<
4716 <<
4717 <<
4718 }; <<
4719 <<
4720 opp-5 <<
4721 <<
4722 <<
4723 }; <<
4724 <<
4725 opp-8 <<
4726 <<
4727 <<
4728 }; <<
4729 }; <<
4730 }; <<
4731 <<
4732 mdss_dp2: displayport <<
4733 compatible = <<
4734 reg = <0 0x0a <<
4735 <0 0x0a <<
4736 <0 0x0a <<
4737 <0 0x0a <<
4738 <0 0x0a <<
4739 <<
4740 interrupts-ex <<
4741 <<
4742 clocks = <&di <<
4743 <&di <<
4744 <&di <<
4745 <&di <<
4746 <&di <<
4747 clock-names = <<
4748 <<
4749 <<
4750 <<
4751 <<
4752 <<
4753 assigned-cloc <<
4754 <<
4755 assigned-cloc <<
4756 <<
4757 <<
4758 operating-poi <<
4759 <<
4760 power-domains <<
4761 <<
4762 phys = <&usb_ <<
4763 phy-names = " <<
4764 <<
4765 #sound-dai-ce <<
4766 <<
4767 status = "dis <<
4768 <<
4769 ports { <<
4770 #addr <<
4771 #size <<
4772 <<
4773 port@ <<
4774 <<
4775 <<
4776 <<
4777 <<
4778 }; <<
4779 <<
4780 port@ <<
4781 <<
4782 <<
4783 <<
4784 <<
4785 <<
4786 }; <<
4787 }; <<
4788 <<
4789 mdss_dp2_opp_ <<
4790 compa <<
4791 <<
4792 opp-1 <<
4793 <<
4794 <<
4795 }; <<
4796 <<
4797 opp-2 <<
4798 <<
4799 <<
4800 }; <<
4801 <<
4802 opp-5 <<
4803 <<
4804 <<
4805 }; <<
4806 <<
4807 opp-8 <<
4808 <<
4809 <<
4810 }; <<
4811 }; <<
4812 }; <<
4813 <<
4814 mdss_dp3: displayport <<
4815 compatible = <<
4816 reg = <0 0x0a <<
4817 <0 0x0a <<
4818 <0 0x0a <<
4819 <0 0x0a <<
4820 <0 0x0a <<
4821 <<
4822 interrupts-ex <<
4823 <<
4824 clocks = <&di <<
4825 <&di <<
4826 <&di <<
4827 <&di <<
4828 <&di <<
4829 clock-names = <<
4830 <<
4831 <<
4832 <<
4833 <<
4834 <<
4835 assigned-cloc <<
4836 <<
4837 assigned-cloc <<
4838 <<
4839 <<
4840 operating-poi <<
4841 <<
4842 power-domains <<
4843 <<
4844 phys = <&mdss <<
4845 phy-names = " <<
4846 <<
4847 #sound-dai-ce <<
4848 <<
4849 status = "dis <<
4850 <<
4851 ports { <<
4852 #addr <<
4853 #size <<
4854 <<
4855 port@ <<
4856 <<
4857 <<
4858 <<
4859 <<
4860 <<
4861 }; <<
4862 <<
4863 port@ <<
4864 <<
4865 }; <<
4866 }; <<
4867 <<
4868 mdss_dp3_opp_ <<
4869 compa <<
4870 <<
4871 opp-1 <<
4872 <<
4873 <<
4874 }; <<
4875 <<
4876 opp-2 <<
4877 <<
4878 <<
4879 }; <<
4880 <<
4881 opp-5 <<
4882 <<
4883 <<
4884 }; <<
4885 <<
4886 opp-8 <<
4887 <<
4888 <<
4889 }; <<
4890 }; <<
4891 }; <<
4892 <<
4893 }; <<
4894 <<
4895 mdss_dp2_phy: phy@aec2a00 { <<
4896 compatible = "qcom,x1 <<
4897 reg = <0 0x0aec2a00 0 <<
4898 <0 0x0aec2200 0 <<
4899 <0 0x0aec2600 0 <<
4900 <0 0x0aec2000 0 <<
4901 <<
4902 clocks = <&dispcc DIS <<
4903 <&dispcc DIS <<
4904 clock-names = "aux", <<
4905 "cfg_ah <<
4906 <<
4907 power-domains = <&rpm <<
4908 <<
4909 #clock-cells = <1>; <<
4910 #phy-cells = <0>; <<
4911 <<
4912 status = "disabled"; <<
4913 }; <<
4914 <<
4915 mdss_dp3_phy: phy@aec5a00 { <<
4916 compatible = "qcom,x1 <<
4917 reg = <0 0x0aec5a00 0 <<
4918 <0 0x0aec5200 0 <<
4919 <0 0x0aec5600 0 <<
4920 <0 0x0aec5000 0 <<
4921 <<
4922 clocks = <&dispcc DIS <<
4923 <&dispcc DIS <<
4924 clock-names = "aux", <<
4925 "cfg_ah <<
4926 <<
4927 power-domains = <&rpm <<
4928 <<
4929 #clock-cells = <1>; <<
4930 #phy-cells = <0>; <<
4931 <<
4932 status = "disabled"; <<
4933 }; <<
4934 <<
4935 dispcc: clock-controller@af00 <<
4936 compatible = "qcom,x1 <<
4937 reg = <0 0x0af00000 0 <<
4938 clocks = <&bi_tcxo_di <<
4939 <&bi_tcxo_ao <<
4940 <&gcc GCC_DI <<
4941 <&sleep_clk> <<
4942 <0>, /* dsi0 <<
4943 <0>, <<
4944 <0>, /* dsi1 <<
4945 <0>, <<
4946 <&usb_1_ss0_ <<
4947 <&usb_1_ss0_ <<
4948 <&usb_1_ss1_ <<
4949 <&usb_1_ss1_ <<
4950 <&usb_1_ss2_ <<
4951 <&usb_1_ss2_ <<
4952 <&mdss_dp3_p <<
4953 <&mdss_dp3_p <<
4954 power-domains = <&rpm <<
4955 required-opps = <&rpm <<
4956 #clock-cells = <1>; <<
4957 #reset-cells = <1>; <<
4958 #power-domain-cells = <<
4959 }; <<
4960 <<
4961 pdc: interrupt-controller@b22 2590 pdc: interrupt-controller@b220000 {
4962 compatible = "qcom,x1 2591 compatible = "qcom,x1e80100-pdc", "qcom,pdc";
4963 reg = <0 0x0b220000 0 2592 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
4964 2593
4965 qcom,pdc-ranges = <0 2594 qcom,pdc-ranges = <0 480 42>, <42 251 5>,
4966 <47 2595 <47 522 52>, <99 609 32>,
4967 <13 2596 <131 717 12>, <143 816 19>;
4968 #interrupt-cells = <2 2597 #interrupt-cells = <2>;
4969 interrupt-parent = <& 2598 interrupt-parent = <&intc>;
4970 interrupt-controller; 2599 interrupt-controller;
4971 }; 2600 };
4972 2601
4973 aoss_qmp: power-management@c3 <<
4974 compatible = "qcom,x1 <<
4975 reg = <0 0x0c300000 0 <<
4976 interrupt-parent = <& <<
4977 interrupts-extended = <<
4978 <<
4979 mboxes = <&ipcc IPCC_ <<
4980 <<
4981 #clock-cells = <0>; <<
4982 }; <<
4983 <<
4984 sram@c3f0000 { <<
4985 compatible = "qcom,rp <<
4986 reg = <0 0x0c3f0000 0 <<
4987 }; <<
4988 <<
4989 spmi: arbiter@c400000 { <<
4990 compatible = "qcom,x1 <<
4991 reg = <0 0x0c400000 0 <<
4992 <0 0x0c500000 0 <<
4993 <0 0x0c440000 0 <<
4994 reg-names = "core", " <<
4995 <<
4996 qcom,ee = <0>; <<
4997 qcom,channel = <0>; <<
4998 <<
4999 #address-cells = <2>; <<
5000 #size-cells = <2>; <<
5001 ranges; <<
5002 <<
5003 spmi_bus0: spmi@c42d0 <<
5004 reg = <0 0x0c <<
5005 <0 0x0c <<
5006 reg-names = " <<
5007 <<
5008 interrupt-nam <<
5009 interrupts-ex <<
5010 interrupt-con <<
5011 #interrupt-ce <<
5012 <<
5013 #address-cell <<
5014 #size-cells = <<
5015 }; <<
5016 <<
5017 spmi_bus1: spmi@c4320 <<
5018 reg = <0 0x0c <<
5019 <0 0x0c <<
5020 reg-names = " <<
5021 <<
5022 interrupt-nam <<
5023 interrupts-ex <<
5024 interrupt-con <<
5025 #interrupt-ce <<
5026 <<
5027 #address-cell <<
5028 #size-cells = <<
5029 }; <<
5030 }; <<
5031 <<
5032 tlmm: pinctrl@f100000 { 2602 tlmm: pinctrl@f100000 {
5033 compatible = "qcom,x1 2603 compatible = "qcom,x1e80100-tlmm";
5034 reg = <0 0x0f100000 0 2604 reg = <0 0x0f100000 0 0xf00000>;
5035 2605
5036 interrupts = <GIC_SPI 2606 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
5037 2607
5038 gpio-controller; 2608 gpio-controller;
5039 #gpio-cells = <2>; 2609 #gpio-cells = <2>;
5040 2610
5041 interrupt-controller; 2611 interrupt-controller;
5042 #interrupt-cells = <2 2612 #interrupt-cells = <2>;
5043 2613
5044 gpio-ranges = <&tlmm 2614 gpio-ranges = <&tlmm 0 0 239>;
5045 wakeup-parent = <&pdc 2615 wakeup-parent = <&pdc>;
5046 2616
5047 qup_i2c0_data_clk: qu 2617 qup_i2c0_data_clk: qup-i2c0-data-clk-state {
5048 /* SDA, SCL * 2618 /* SDA, SCL */
5049 pins = "gpio0 2619 pins = "gpio0", "gpio1";
5050 function = "q 2620 function = "qup0_se0";
5051 drive-strengt 2621 drive-strength = <2>;
5052 bias-pull-up 2622 bias-pull-up = <2200>;
5053 }; 2623 };
5054 2624
5055 qup_i2c1_data_clk: qu 2625 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
5056 /* SDA, SCL * 2626 /* SDA, SCL */
5057 pins = "gpio4 2627 pins = "gpio4", "gpio5";
5058 function = "q 2628 function = "qup0_se1";
5059 drive-strengt 2629 drive-strength = <2>;
5060 bias-pull-up 2630 bias-pull-up = <2200>;
5061 }; 2631 };
5062 2632
5063 qup_i2c2_data_clk: qu 2633 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
5064 /* SDA, SCL * 2634 /* SDA, SCL */
5065 pins = "gpio8 2635 pins = "gpio8", "gpio9";
5066 function = "q 2636 function = "qup0_se2";
5067 drive-strengt 2637 drive-strength = <2>;
5068 bias-pull-up 2638 bias-pull-up = <2200>;
5069 }; 2639 };
5070 2640
5071 qup_i2c3_data_clk: qu 2641 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
5072 /* SDA, SCL * 2642 /* SDA, SCL */
5073 pins = "gpio1 2643 pins = "gpio12", "gpio13";
5074 function = "q 2644 function = "qup0_se3";
5075 drive-strengt 2645 drive-strength = <2>;
5076 bias-pull-up 2646 bias-pull-up = <2200>;
5077 }; 2647 };
5078 2648
5079 qup_i2c4_data_clk: qu 2649 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
5080 /* SDA, SCL * 2650 /* SDA, SCL */
5081 pins = "gpio1 2651 pins = "gpio16", "gpio17";
5082 function = "q 2652 function = "qup0_se4";
5083 drive-strengt 2653 drive-strength = <2>;
5084 bias-pull-up 2654 bias-pull-up = <2200>;
5085 }; 2655 };
5086 2656
5087 qup_i2c5_data_clk: qu 2657 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
5088 /* SDA, SCL * 2658 /* SDA, SCL */
5089 pins = "gpio2 2659 pins = "gpio20", "gpio21";
5090 function = "q 2660 function = "qup0_se5";
5091 drive-strengt 2661 drive-strength = <2>;
5092 bias-pull-up 2662 bias-pull-up = <2200>;
5093 }; 2663 };
5094 2664
5095 qup_i2c6_data_clk: qu 2665 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
5096 /* SDA, SCL * 2666 /* SDA, SCL */
5097 pins = "gpio2 2667 pins = "gpio24", "gpio25";
5098 function = "q 2668 function = "qup0_se6";
5099 drive-strengt 2669 drive-strength = <2>;
5100 bias-pull-up 2670 bias-pull-up = <2200>;
5101 }; 2671 };
5102 2672
5103 qup_i2c7_data_clk: qu 2673 qup_i2c7_data_clk: qup-i2c7-data-clk-state {
5104 /* SDA, SCL * 2674 /* SDA, SCL */
5105 pins = "gpio1 2675 pins = "gpio14", "gpio15";
5106 function = "q 2676 function = "qup0_se7";
5107 drive-strengt 2677 drive-strength = <2>;
5108 bias-pull-up 2678 bias-pull-up = <2200>;
5109 }; 2679 };
5110 2680
5111 qup_i2c8_data_clk: qu 2681 qup_i2c8_data_clk: qup-i2c8-data-clk-state {
5112 /* SDA, SCL * 2682 /* SDA, SCL */
5113 pins = "gpio3 2683 pins = "gpio32", "gpio33";
5114 function = "q 2684 function = "qup1_se0";
5115 drive-strengt 2685 drive-strength = <2>;
5116 bias-pull-up 2686 bias-pull-up = <2200>;
5117 }; 2687 };
5118 2688
5119 qup_i2c9_data_clk: qu 2689 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
5120 /* SDA, SCL * 2690 /* SDA, SCL */
5121 pins = "gpio3 2691 pins = "gpio36", "gpio37";
5122 function = "q 2692 function = "qup1_se1";
5123 drive-strengt 2693 drive-strength = <2>;
5124 bias-pull-up 2694 bias-pull-up = <2200>;
5125 }; 2695 };
5126 2696
5127 qup_i2c10_data_clk: q 2697 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
5128 /* SDA, SCL * 2698 /* SDA, SCL */
5129 pins = "gpio4 2699 pins = "gpio40", "gpio41";
5130 function = "q 2700 function = "qup1_se2";
5131 drive-strengt 2701 drive-strength = <2>;
5132 bias-pull-up 2702 bias-pull-up = <2200>;
5133 }; 2703 };
5134 2704
5135 qup_i2c11_data_clk: q 2705 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
5136 /* SDA, SCL * 2706 /* SDA, SCL */
5137 pins = "gpio4 2707 pins = "gpio44", "gpio45";
5138 function = "q 2708 function = "qup1_se3";
5139 drive-strengt 2709 drive-strength = <2>;
5140 bias-pull-up 2710 bias-pull-up = <2200>;
5141 }; 2711 };
5142 2712
5143 qup_i2c12_data_clk: q 2713 qup_i2c12_data_clk: qup-i2c12-data-clk-state {
5144 /* SDA, SCL * 2714 /* SDA, SCL */
5145 pins = "gpio4 2715 pins = "gpio48", "gpio49";
5146 function = "q 2716 function = "qup1_se4";
5147 drive-strengt 2717 drive-strength = <2>;
5148 bias-pull-up 2718 bias-pull-up = <2200>;
5149 }; 2719 };
5150 2720
5151 qup_i2c13_data_clk: q 2721 qup_i2c13_data_clk: qup-i2c13-data-clk-state {
5152 /* SDA, SCL * 2722 /* SDA, SCL */
5153 pins = "gpio5 2723 pins = "gpio52", "gpio53";
5154 function = "q 2724 function = "qup1_se5";
5155 drive-strengt 2725 drive-strength = <2>;
5156 bias-pull-up 2726 bias-pull-up = <2200>;
5157 }; 2727 };
5158 2728
5159 qup_i2c14_data_clk: q 2729 qup_i2c14_data_clk: qup-i2c14-data-clk-state {
5160 /* SDA, SCL * 2730 /* SDA, SCL */
5161 pins = "gpio5 2731 pins = "gpio56", "gpio57";
5162 function = "q 2732 function = "qup1_se6";
5163 drive-strengt 2733 drive-strength = <2>;
5164 bias-pull-up 2734 bias-pull-up = <2200>;
5165 }; 2735 };
5166 2736
5167 qup_i2c15_data_clk: q 2737 qup_i2c15_data_clk: qup-i2c15-data-clk-state {
5168 /* SDA, SCL * 2738 /* SDA, SCL */
5169 pins = "gpio5 2739 pins = "gpio54", "gpio55";
5170 function = "q 2740 function = "qup1_se7";
5171 drive-strengt 2741 drive-strength = <2>;
5172 bias-pull-up 2742 bias-pull-up = <2200>;
5173 }; 2743 };
5174 2744
5175 qup_i2c16_data_clk: q 2745 qup_i2c16_data_clk: qup-i2c16-data-clk-state {
5176 /* SDA, SCL * 2746 /* SDA, SCL */
5177 pins = "gpio6 2747 pins = "gpio64", "gpio65";
5178 function = "q 2748 function = "qup2_se0";
5179 drive-strengt 2749 drive-strength = <2>;
5180 bias-pull-up 2750 bias-pull-up = <2200>;
5181 }; 2751 };
5182 2752
5183 qup_i2c17_data_clk: q 2753 qup_i2c17_data_clk: qup-i2c17-data-clk-state {
5184 /* SDA, SCL * 2754 /* SDA, SCL */
5185 pins = "gpio6 2755 pins = "gpio68", "gpio69";
5186 function = "q 2756 function = "qup2_se1";
5187 drive-strengt 2757 drive-strength = <2>;
5188 bias-pull-up 2758 bias-pull-up = <2200>;
5189 }; 2759 };
5190 2760
5191 qup_i2c18_data_clk: q 2761 qup_i2c18_data_clk: qup-i2c18-data-clk-state {
5192 /* SDA, SCL * 2762 /* SDA, SCL */
5193 pins = "gpio7 2763 pins = "gpio72", "gpio73";
5194 function = "q 2764 function = "qup2_se2";
5195 drive-strengt 2765 drive-strength = <2>;
5196 bias-pull-up 2766 bias-pull-up = <2200>;
5197 }; 2767 };
5198 2768
5199 qup_i2c19_data_clk: q 2769 qup_i2c19_data_clk: qup-i2c19-data-clk-state {
5200 /* SDA, SCL * 2770 /* SDA, SCL */
5201 pins = "gpio7 2771 pins = "gpio76", "gpio77";
5202 function = "q 2772 function = "qup2_se3";
5203 drive-strengt 2773 drive-strength = <2>;
5204 bias-pull-up 2774 bias-pull-up = <2200>;
5205 }; 2775 };
5206 2776
5207 qup_i2c20_data_clk: q 2777 qup_i2c20_data_clk: qup-i2c20-data-clk-state {
5208 /* SDA, SCL * 2778 /* SDA, SCL */
5209 pins = "gpio8 2779 pins = "gpio80", "gpio81";
5210 function = "q 2780 function = "qup2_se4";
5211 drive-strengt 2781 drive-strength = <2>;
5212 bias-pull-up 2782 bias-pull-up = <2200>;
5213 }; 2783 };
5214 2784
5215 qup_i2c21_data_clk: q 2785 qup_i2c21_data_clk: qup-i2c21-data-clk-state {
5216 /* SDA, SCL * 2786 /* SDA, SCL */
5217 pins = "gpio8 2787 pins = "gpio84", "gpio85";
5218 function = "q 2788 function = "qup2_se5";
5219 drive-strengt 2789 drive-strength = <2>;
5220 bias-pull-up 2790 bias-pull-up = <2200>;
5221 }; 2791 };
5222 2792
5223 qup_i2c22_data_clk: q 2793 qup_i2c22_data_clk: qup-i2c22-data-clk-state {
5224 /* SDA, SCL * 2794 /* SDA, SCL */
5225 pins = "gpio8 2795 pins = "gpio88", "gpio89";
5226 function = "q 2796 function = "qup2_se6";
5227 drive-strengt 2797 drive-strength = <2>;
5228 bias-pull-up 2798 bias-pull-up = <2200>;
5229 }; 2799 };
5230 2800
5231 qup_i2c23_data_clk: q 2801 qup_i2c23_data_clk: qup-i2c23-data-clk-state {
5232 /* SDA, SCL * 2802 /* SDA, SCL */
5233 pins = "gpio8 2803 pins = "gpio86", "gpio87";
5234 function = "q 2804 function = "qup2_se7";
5235 drive-strengt 2805 drive-strength = <2>;
5236 bias-pull-up 2806 bias-pull-up = <2200>;
5237 }; 2807 };
5238 2808
5239 qup_spi0_cs: qup-spi0 2809 qup_spi0_cs: qup-spi0-cs-state {
5240 pins = "gpio3 2810 pins = "gpio3";
5241 function = "q 2811 function = "qup0_se0";
5242 drive-strengt 2812 drive-strength = <6>;
5243 bias-disable; 2813 bias-disable;
5244 }; 2814 };
5245 2815
5246 qup_spi0_data_clk: qu 2816 qup_spi0_data_clk: qup-spi0-data-clk-state {
5247 /* MISO, MOSI 2817 /* MISO, MOSI, CLK */
5248 pins = "gpio0 2818 pins = "gpio0", "gpio1", "gpio2";
5249 function = "q 2819 function = "qup0_se0";
5250 drive-strengt 2820 drive-strength = <6>;
5251 bias-disable; 2821 bias-disable;
5252 }; 2822 };
5253 2823
5254 qup_spi1_cs: qup-spi1 2824 qup_spi1_cs: qup-spi1-cs-state {
5255 pins = "gpio7 2825 pins = "gpio7";
5256 function = "q 2826 function = "qup0_se1";
5257 drive-strengt 2827 drive-strength = <6>;
5258 bias-disable; 2828 bias-disable;
5259 }; 2829 };
5260 2830
5261 qup_spi1_data_clk: qu 2831 qup_spi1_data_clk: qup-spi1-data-clk-state {
5262 /* MISO, MOSI 2832 /* MISO, MOSI, CLK */
5263 pins = "gpio4 2833 pins = "gpio4", "gpio5", "gpio6";
5264 function = "q 2834 function = "qup0_se1";
5265 drive-strengt 2835 drive-strength = <6>;
5266 bias-disable; 2836 bias-disable;
5267 }; 2837 };
5268 2838
5269 qup_spi2_cs: qup-spi2 2839 qup_spi2_cs: qup-spi2-cs-state {
5270 pins = "gpio1 2840 pins = "gpio11";
5271 function = "q 2841 function = "qup0_se2";
5272 drive-strengt 2842 drive-strength = <6>;
5273 bias-disable; 2843 bias-disable;
5274 }; 2844 };
5275 2845
5276 qup_spi2_data_clk: qu 2846 qup_spi2_data_clk: qup-spi2-data-clk-state {
5277 /* MISO, MOSI 2847 /* MISO, MOSI, CLK */
5278 pins = "gpio8 2848 pins = "gpio8", "gpio9", "gpio10";
5279 function = "q 2849 function = "qup0_se2";
5280 drive-strengt 2850 drive-strength = <6>;
5281 bias-disable; 2851 bias-disable;
5282 }; 2852 };
5283 2853
5284 qup_spi3_cs: qup-spi3 2854 qup_spi3_cs: qup-spi3-cs-state {
5285 pins = "gpio1 2855 pins = "gpio15";
5286 function = "q 2856 function = "qup0_se3";
5287 drive-strengt 2857 drive-strength = <6>;
5288 bias-disable; 2858 bias-disable;
5289 }; 2859 };
5290 2860
5291 qup_spi3_data_clk: qu 2861 qup_spi3_data_clk: qup-spi3-data-clk-state {
5292 /* MISO, MOSI 2862 /* MISO, MOSI, CLK */
5293 pins = "gpio1 2863 pins = "gpio12", "gpio13", "gpio14";
5294 function = "q 2864 function = "qup0_se3";
5295 drive-strengt 2865 drive-strength = <6>;
5296 bias-disable; 2866 bias-disable;
5297 }; 2867 };
5298 2868
5299 qup_spi4_cs: qup-spi4 2869 qup_spi4_cs: qup-spi4-cs-state {
5300 pins = "gpio1 2870 pins = "gpio19";
5301 function = "q 2871 function = "qup0_se4";
5302 drive-strengt 2872 drive-strength = <6>;
5303 bias-disable; 2873 bias-disable;
5304 }; 2874 };
5305 2875
5306 qup_spi4_data_clk: qu 2876 qup_spi4_data_clk: qup-spi4-data-clk-state {
5307 /* MISO, MOSI 2877 /* MISO, MOSI, CLK */
5308 pins = "gpio1 2878 pins = "gpio16", "gpio17", "gpio18";
5309 function = "q 2879 function = "qup0_se4";
5310 drive-strengt 2880 drive-strength = <6>;
5311 bias-disable; 2881 bias-disable;
5312 }; 2882 };
5313 2883
5314 qup_spi5_cs: qup-spi5 2884 qup_spi5_cs: qup-spi5-cs-state {
5315 pins = "gpio2 2885 pins = "gpio23";
5316 function = "q 2886 function = "qup0_se5";
5317 drive-strengt 2887 drive-strength = <6>;
5318 bias-disable; 2888 bias-disable;
5319 }; 2889 };
5320 2890
5321 qup_spi5_data_clk: qu 2891 qup_spi5_data_clk: qup-spi5-data-clk-state {
5322 /* MISO, MOSI 2892 /* MISO, MOSI, CLK */
5323 pins = "gpio2 2893 pins = "gpio20", "gpio21", "gpio22";
5324 function = "q 2894 function = "qup0_se5";
5325 drive-strengt 2895 drive-strength = <6>;
5326 bias-disable; 2896 bias-disable;
5327 }; 2897 };
5328 2898
5329 qup_spi6_cs: qup-spi6 2899 qup_spi6_cs: qup-spi6-cs-state {
5330 pins = "gpio2 2900 pins = "gpio27";
5331 function = "q 2901 function = "qup0_se6";
5332 drive-strengt 2902 drive-strength = <6>;
5333 bias-disable; 2903 bias-disable;
5334 }; 2904 };
5335 2905
5336 qup_spi6_data_clk: qu 2906 qup_spi6_data_clk: qup-spi6-data-clk-state {
5337 /* MISO, MOSI 2907 /* MISO, MOSI, CLK */
5338 pins = "gpio2 2908 pins = "gpio24", "gpio25", "gpio26";
5339 function = "q 2909 function = "qup0_se6";
5340 drive-strengt 2910 drive-strength = <6>;
5341 bias-disable; 2911 bias-disable;
5342 }; 2912 };
5343 2913
5344 qup_spi7_cs: qup-spi7 2914 qup_spi7_cs: qup-spi7-cs-state {
5345 pins = "gpio1 2915 pins = "gpio13";
5346 function = "q 2916 function = "qup0_se7";
5347 drive-strengt 2917 drive-strength = <6>;
5348 bias-disable; 2918 bias-disable;
5349 }; 2919 };
5350 2920
5351 qup_spi7_data_clk: qu 2921 qup_spi7_data_clk: qup-spi7-data-clk-state {
5352 /* MISO, MOSI 2922 /* MISO, MOSI, CLK */
5353 pins = "gpio1 2923 pins = "gpio14", "gpio15", "gpio12";
5354 function = "q 2924 function = "qup0_se7";
5355 drive-strengt 2925 drive-strength = <6>;
5356 bias-disable; 2926 bias-disable;
5357 }; 2927 };
5358 2928
5359 qup_spi8_cs: qup-spi8 2929 qup_spi8_cs: qup-spi8-cs-state {
5360 pins = "gpio3 2930 pins = "gpio35";
5361 function = "q 2931 function = "qup1_se0";
5362 drive-strengt 2932 drive-strength = <6>;
5363 bias-disable; 2933 bias-disable;
5364 }; 2934 };
5365 2935
5366 qup_spi8_data_clk: qu 2936 qup_spi8_data_clk: qup-spi8-data-clk-state {
5367 /* MISO, MOSI 2937 /* MISO, MOSI, CLK */
5368 pins = "gpio3 2938 pins = "gpio32", "gpio33", "gpio34";
5369 function = "q 2939 function = "qup1_se0";
5370 drive-strengt 2940 drive-strength = <6>;
5371 bias-disable; 2941 bias-disable;
5372 }; 2942 };
5373 2943
5374 qup_spi9_cs: qup-spi9 2944 qup_spi9_cs: qup-spi9-cs-state {
5375 pins = "gpio3 2945 pins = "gpio39";
5376 function = "q 2946 function = "qup1_se1";
5377 drive-strengt 2947 drive-strength = <6>;
5378 bias-disable; 2948 bias-disable;
5379 }; 2949 };
5380 2950
5381 qup_spi9_data_clk: qu 2951 qup_spi9_data_clk: qup-spi9-data-clk-state {
5382 /* MISO, MOSI 2952 /* MISO, MOSI, CLK */
5383 pins = "gpio3 2953 pins = "gpio36", "gpio37", "gpio38";
5384 function = "q 2954 function = "qup1_se1";
5385 drive-strengt 2955 drive-strength = <6>;
5386 bias-disable; 2956 bias-disable;
5387 }; 2957 };
5388 2958
5389 qup_spi10_cs: qup-spi 2959 qup_spi10_cs: qup-spi10-cs-state {
5390 pins = "gpio4 2960 pins = "gpio43";
5391 function = "q 2961 function = "qup1_se2";
5392 drive-strengt 2962 drive-strength = <6>;
5393 bias-disable; 2963 bias-disable;
5394 }; 2964 };
5395 2965
5396 qup_spi10_data_clk: q 2966 qup_spi10_data_clk: qup-spi10-data-clk-state {
5397 /* MISO, MOSI 2967 /* MISO, MOSI, CLK */
5398 pins = "gpio4 2968 pins = "gpio40", "gpio41", "gpio42";
5399 function = "q 2969 function = "qup1_se2";
5400 drive-strengt 2970 drive-strength = <6>;
5401 bias-disable; 2971 bias-disable;
5402 }; 2972 };
5403 2973
5404 qup_spi11_cs: qup-spi 2974 qup_spi11_cs: qup-spi11-cs-state {
5405 pins = "gpio4 2975 pins = "gpio47";
5406 function = "q 2976 function = "qup1_se3";
5407 drive-strengt 2977 drive-strength = <6>;
5408 bias-disable; 2978 bias-disable;
5409 }; 2979 };
5410 2980
5411 qup_spi11_data_clk: q 2981 qup_spi11_data_clk: qup-spi11-data-clk-state {
5412 /* MISO, MOSI 2982 /* MISO, MOSI, CLK */
5413 pins = "gpio4 2983 pins = "gpio44", "gpio45", "gpio46";
5414 function = "q 2984 function = "qup1_se3";
5415 drive-strengt 2985 drive-strength = <6>;
5416 bias-disable; 2986 bias-disable;
5417 }; 2987 };
5418 2988
5419 qup_spi12_cs: qup-spi 2989 qup_spi12_cs: qup-spi12-cs-state {
5420 pins = "gpio5 2990 pins = "gpio51";
5421 function = "q 2991 function = "qup1_se4";
5422 drive-strengt 2992 drive-strength = <6>;
5423 bias-disable; 2993 bias-disable;
5424 }; 2994 };
5425 2995
5426 qup_spi12_data_clk: q 2996 qup_spi12_data_clk: qup-spi12-data-clk-state {
5427 /* MISO, MOSI 2997 /* MISO, MOSI, CLK */
5428 pins = "gpio4 2998 pins = "gpio48", "gpio49", "gpio50";
5429 function = "q 2999 function = "qup1_se4";
5430 drive-strengt 3000 drive-strength = <6>;
5431 bias-disable; 3001 bias-disable;
5432 }; 3002 };
5433 3003
5434 qup_spi13_cs: qup-spi 3004 qup_spi13_cs: qup-spi13-cs-state {
5435 pins = "gpio5 3005 pins = "gpio55";
5436 function = "q 3006 function = "qup1_se5";
5437 drive-strengt 3007 drive-strength = <6>;
5438 bias-disable; 3008 bias-disable;
5439 }; 3009 };
5440 3010
5441 qup_spi13_data_clk: q 3011 qup_spi13_data_clk: qup-spi13-data-clk-state {
5442 /* MISO, MOSI 3012 /* MISO, MOSI, CLK */
5443 pins = "gpio5 3013 pins = "gpio52", "gpio53", "gpio54";
5444 function = "q 3014 function = "qup1_se5";
5445 drive-strengt 3015 drive-strength = <6>;
5446 bias-disable; 3016 bias-disable;
5447 }; 3017 };
5448 3018
5449 qup_spi14_cs: qup-spi 3019 qup_spi14_cs: qup-spi14-cs-state {
5450 pins = "gpio5 3020 pins = "gpio59";
5451 function = "q 3021 function = "qup1_se6";
5452 drive-strengt 3022 drive-strength = <6>;
5453 bias-disable; 3023 bias-disable;
5454 }; 3024 };
5455 3025
5456 qup_spi14_data_clk: q 3026 qup_spi14_data_clk: qup-spi14-data-clk-state {
5457 /* MISO, MOSI 3027 /* MISO, MOSI, CLK */
5458 pins = "gpio5 3028 pins = "gpio56", "gpio57", "gpio58";
5459 function = "q 3029 function = "qup1_se6";
5460 drive-strengt 3030 drive-strength = <6>;
5461 bias-disable; 3031 bias-disable;
5462 }; 3032 };
5463 3033
5464 qup_spi15_cs: qup-spi 3034 qup_spi15_cs: qup-spi15-cs-state {
5465 pins = "gpio5 3035 pins = "gpio53";
5466 function = "q 3036 function = "qup1_se7";
5467 drive-strengt 3037 drive-strength = <6>;
5468 bias-disable; 3038 bias-disable;
5469 }; 3039 };
5470 3040
5471 qup_spi15_data_clk: q 3041 qup_spi15_data_clk: qup-spi15-data-clk-state {
5472 /* MISO, MOSI 3042 /* MISO, MOSI, CLK */
5473 pins = "gpio5 3043 pins = "gpio54", "gpio55", "gpio52";
5474 function = "q 3044 function = "qup1_se7";
5475 drive-strengt 3045 drive-strength = <6>;
5476 bias-disable; 3046 bias-disable;
5477 }; 3047 };
5478 3048
5479 qup_spi16_cs: qup-spi 3049 qup_spi16_cs: qup-spi16-cs-state {
5480 pins = "gpio6 3050 pins = "gpio67";
5481 function = "q 3051 function = "qup2_se0";
5482 drive-strengt 3052 drive-strength = <6>;
5483 bias-disable; 3053 bias-disable;
5484 }; 3054 };
5485 3055
5486 qup_spi16_data_clk: q 3056 qup_spi16_data_clk: qup-spi16-data-clk-state {
5487 /* MISO, MOSI 3057 /* MISO, MOSI, CLK */
5488 pins = "gpio6 3058 pins = "gpio64", "gpio65", "gpio66";
5489 function = "q 3059 function = "qup2_se0";
5490 drive-strengt 3060 drive-strength = <6>;
5491 bias-disable; 3061 bias-disable;
5492 }; 3062 };
5493 3063
5494 qup_spi17_cs: qup-spi 3064 qup_spi17_cs: qup-spi17-cs-state {
5495 pins = "gpio7 3065 pins = "gpio71";
5496 function = "q 3066 function = "qup2_se1";
5497 drive-strengt 3067 drive-strength = <6>;
5498 bias-disable; 3068 bias-disable;
5499 }; 3069 };
5500 3070
5501 qup_spi17_data_clk: q 3071 qup_spi17_data_clk: qup-spi17-data-clk-state {
5502 /* MISO, MOSI 3072 /* MISO, MOSI, CLK */
5503 pins = "gpio6 3073 pins = "gpio68", "gpio69", "gpio70";
5504 function = "q 3074 function = "qup2_se1";
5505 drive-strengt 3075 drive-strength = <6>;
5506 bias-disable; 3076 bias-disable;
5507 }; 3077 };
5508 3078
5509 qup_spi18_cs: qup-spi 3079 qup_spi18_cs: qup-spi18-cs-state {
5510 pins = "gpio7 3080 pins = "gpio75";
5511 function = "q 3081 function = "qup2_se2";
5512 drive-strengt 3082 drive-strength = <6>;
5513 bias-disable; 3083 bias-disable;
5514 }; 3084 };
5515 3085
5516 qup_spi18_data_clk: q 3086 qup_spi18_data_clk: qup-spi18-data-clk-state {
5517 /* MISO, MOSI 3087 /* MISO, MOSI, CLK */
5518 pins = "gpio7 3088 pins = "gpio72", "gpio73", "gpio74";
5519 function = "q 3089 function = "qup2_se2";
5520 drive-strengt 3090 drive-strength = <6>;
5521 bias-disable; 3091 bias-disable;
5522 }; 3092 };
5523 3093
5524 qup_spi19_cs: qup-spi 3094 qup_spi19_cs: qup-spi19-cs-state {
5525 pins = "gpio7 3095 pins = "gpio79";
5526 function = "q 3096 function = "qup2_se3";
5527 drive-strengt 3097 drive-strength = <6>;
5528 bias-disable; 3098 bias-disable;
5529 }; 3099 };
5530 3100
5531 qup_spi19_data_clk: q 3101 qup_spi19_data_clk: qup-spi19-data-clk-state {
5532 /* MISO, MOSI 3102 /* MISO, MOSI, CLK */
5533 pins = "gpio7 3103 pins = "gpio76", "gpio77", "gpio78";
5534 function = "q 3104 function = "qup2_se3";
5535 drive-strengt 3105 drive-strength = <6>;
5536 bias-disable; 3106 bias-disable;
5537 }; 3107 };
5538 3108
5539 qup_spi20_cs: qup-spi 3109 qup_spi20_cs: qup-spi20-cs-state {
5540 pins = "gpio8 3110 pins = "gpio83";
5541 function = "q 3111 function = "qup2_se4";
5542 drive-strengt 3112 drive-strength = <6>;
5543 bias-disable; 3113 bias-disable;
5544 }; 3114 };
5545 3115
5546 qup_spi20_data_clk: q 3116 qup_spi20_data_clk: qup-spi20-data-clk-state {
5547 /* MISO, MOSI 3117 /* MISO, MOSI, CLK */
5548 pins = "gpio8 3118 pins = "gpio80", "gpio81", "gpio82";
5549 function = "q 3119 function = "qup2_se4";
5550 drive-strengt 3120 drive-strength = <6>;
5551 bias-disable; 3121 bias-disable;
5552 }; 3122 };
5553 3123
5554 qup_spi21_cs: qup-spi 3124 qup_spi21_cs: qup-spi21-cs-state {
5555 pins = "gpio8 3125 pins = "gpio87";
5556 function = "q 3126 function = "qup2_se5";
5557 drive-strengt 3127 drive-strength = <6>;
5558 bias-disable; 3128 bias-disable;
5559 }; 3129 };
5560 3130
5561 qup_spi21_data_clk: q 3131 qup_spi21_data_clk: qup-spi21-data-clk-state {
5562 /* MISO, MOSI 3132 /* MISO, MOSI, CLK */
5563 pins = "gpio8 3133 pins = "gpio84", "gpio85", "gpio86";
5564 function = "q 3134 function = "qup2_se5";
5565 drive-strengt 3135 drive-strength = <6>;
5566 bias-disable; 3136 bias-disable;
5567 }; 3137 };
5568 3138
5569 qup_spi22_cs: qup-spi 3139 qup_spi22_cs: qup-spi22-cs-state {
5570 pins = "gpio9 3140 pins = "gpio91";
5571 function = "q 3141 function = "qup2_se6";
5572 drive-strengt 3142 drive-strength = <6>;
5573 bias-disable; 3143 bias-disable;
5574 }; 3144 };
5575 3145
5576 qup_spi22_data_clk: q 3146 qup_spi22_data_clk: qup-spi22-data-clk-state {
5577 /* MISO, MOSI 3147 /* MISO, MOSI, CLK */
5578 pins = "gpio8 3148 pins = "gpio88", "gpio89", "gpio90";
5579 function = "q 3149 function = "qup2_se6";
5580 drive-strengt 3150 drive-strength = <6>;
5581 bias-disable; 3151 bias-disable;
5582 }; 3152 };
5583 3153
5584 qup_spi23_cs: qup-spi 3154 qup_spi23_cs: qup-spi23-cs-state {
5585 pins = "gpio8 3155 pins = "gpio85";
5586 function = "q 3156 function = "qup2_se7";
5587 drive-strengt 3157 drive-strength = <6>;
5588 bias-disable; 3158 bias-disable;
5589 }; 3159 };
5590 3160
5591 qup_spi23_data_clk: q 3161 qup_spi23_data_clk: qup-spi23-data-clk-state {
5592 /* MISO, MOSI 3162 /* MISO, MOSI, CLK */
5593 pins = "gpio8 3163 pins = "gpio86", "gpio87", "gpio84";
5594 function = "q 3164 function = "qup2_se7";
5595 drive-strengt 3165 drive-strength = <6>;
5596 bias-disable; 3166 bias-disable;
5597 }; 3167 };
5598 3168
5599 qup_uart2_default: qu <<
5600 cts-pins { <<
5601 pins <<
5602 funct <<
5603 drive <<
5604 bias- <<
5605 }; <<
5606 <<
5607 rts-pins { <<
5608 pins <<
5609 funct <<
5610 drive <<
5611 bias- <<
5612 }; <<
5613 <<
5614 tx-pins { <<
5615 pins <<
5616 funct <<
5617 drive <<
5618 bias- <<
5619 }; <<
5620 <<
5621 rx-pins { <<
5622 pins <<
5623 funct <<
5624 drive <<
5625 bias- <<
5626 }; <<
5627 }; <<
5628 <<
5629 qup_uart21_default: q 3169 qup_uart21_default: qup-uart21-default-state {
5630 tx-pins { !! 3170 /* TX, RX */
5631 pins !! 3171 pins = "gpio86", "gpio87";
5632 funct !! 3172 function = "qup2_se5";
5633 drive !! 3173 drive-strength= <2>;
5634 bias- !! 3174 bias-disable;
5635 }; <<
5636 <<
5637 rx-pins { <<
5638 pins <<
5639 funct <<
5640 drive <<
5641 bias- <<
5642 }; <<
5643 }; 3175 };
5644 }; 3176 };
5645 3177
5646 apps_smmu: iommu@15000000 { 3178 apps_smmu: iommu@15000000 {
5647 compatible = "qcom,x1 3179 compatible = "qcom,x1e80100-smmu-500", "qcom,smmu-500", "arm,mmu-500";
5648 reg = <0 0x15000000 0 3180 reg = <0 0x15000000 0 0x100000>;
5649 3181
5650 interrupts = <GIC_SPI 3182 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
5651 <GIC_SPI 3183 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
5652 <GIC_SPI 3184 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
5653 <GIC_SPI 3185 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
5654 <GIC_SPI 3186 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
5655 <GIC_SPI 3187 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
5656 <GIC_SPI 3188 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
5657 <GIC_SPI 3189 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
5658 <GIC_SPI 3190 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
5659 <GIC_SPI 3191 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
5660 <GIC_SPI 3192 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
5661 <GIC_SPI 3193 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
5662 <GIC_SPI 3194 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
5663 <GIC_SPI 3195 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
5664 <GIC_SPI 3196 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
5665 <GIC_SPI 3197 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
5666 <GIC_SPI 3198 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
5667 <GIC_SPI 3199 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
5668 <GIC_SPI 3200 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
5669 <GIC_SPI 3201 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
5670 <GIC_SPI 3202 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
5671 <GIC_SPI 3203 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
5672 <GIC_SPI 3204 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
5673 <GIC_SPI 3205 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
5674 <GIC_SPI 3206 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
5675 <GIC_SPI 3207 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
5676 <GIC_SPI 3208 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
5677 <GIC_SPI 3209 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
5678 <GIC_SPI 3210 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
5679 <GIC_SPI 3211 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
5680 <GIC_SPI 3212 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
5681 <GIC_SPI 3213 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
5682 <GIC_SPI 3214 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
5683 <GIC_SPI 3215 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
5684 <GIC_SPI 3216 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
5685 <GIC_SPI 3217 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
5686 <GIC_SPI 3218 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
5687 <GIC_SPI 3219 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
5688 <GIC_SPI 3220 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
5689 <GIC_SPI 3221 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
5690 <GIC_SPI 3222 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
5691 <GIC_SPI 3223 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
5692 <GIC_SPI 3224 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
5693 <GIC_SPI 3225 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
5694 <GIC_SPI 3226 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
5695 <GIC_SPI 3227 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
5696 <GIC_SPI 3228 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
5697 <GIC_SPI 3229 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
5698 <GIC_SPI 3230 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
5699 <GIC_SPI 3231 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
5700 <GIC_SPI 3232 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
5701 <GIC_SPI 3233 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
5702 <GIC_SPI 3234 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
5703 <GIC_SPI 3235 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
5704 <GIC_SPI 3236 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
5705 <GIC_SPI 3237 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
5706 <GIC_SPI 3238 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
5707 <GIC_SPI 3239 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
5708 <GIC_SPI 3240 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
5709 <GIC_SPI 3241 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
5710 <GIC_SPI 3242 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
5711 <GIC_SPI 3243 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
5712 <GIC_SPI 3244 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
5713 <GIC_SPI 3245 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
5714 <GIC_SPI 3246 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
5715 <GIC_SPI 3247 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
5716 <GIC_SPI 3248 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
5717 <GIC_SPI 3249 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
5718 <GIC_SPI 3250 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
5719 <GIC_SPI 3251 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
5720 <GIC_SPI 3252 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
5721 <GIC_SPI 3253 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
5722 <GIC_SPI 3254 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
5723 <GIC_SPI 3255 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
5724 <GIC_SPI 3256 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
5725 <GIC_SPI 3257 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
5726 <GIC_SPI 3258 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
5727 <GIC_SPI 3259 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
5728 <GIC_SPI 3260 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
5729 <GIC_SPI 3261 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
5730 <GIC_SPI 3262 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
5731 <GIC_SPI 3263 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
5732 <GIC_SPI 3264 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
5733 <GIC_SPI 3265 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
5734 <GIC_SPI 3266 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
5735 <GIC_SPI 3267 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
5736 <GIC_SPI 3268 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
5737 <GIC_SPI 3269 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
5738 <GIC_SPI 3270 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
5739 <GIC_SPI 3271 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
5740 <GIC_SPI 3272 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
5741 <GIC_SPI 3273 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
5742 <GIC_SPI 3274 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
5743 <GIC_SPI 3275 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
5744 <GIC_SPI 3276 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
5745 <GIC_SPI 3277 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
5746 <GIC_SPI 3278 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>;
5747 3279
5748 #iommu-cells = <2>; 3280 #iommu-cells = <2>;
5749 #global-interrupts = 3281 #global-interrupts = <1>;
5750 }; 3282 };
5751 3283
5752 intc: interrupt-controller@17 3284 intc: interrupt-controller@17000000 {
5753 compatible = "arm,gic 3285 compatible = "arm,gic-v3";
5754 reg = <0 0x17000000 0 3286 reg = <0 0x17000000 0 0x10000>, /* GICD */
5755 <0 0x17080000 0 3287 <0 0x17080000 0 0x480000>; /* GICR * 12 */
5756 3288
5757 interrupts = <GIC_PPI 3289 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
5758 3290
5759 #interrupt-cells = <3 3291 #interrupt-cells = <3>;
5760 interrupt-controller; 3292 interrupt-controller;
5761 3293
5762 #redistributor-region 3294 #redistributor-regions = <1>;
5763 redistributor-stride 3295 redistributor-stride = <0x0 0x40000>;
5764 3296
5765 #address-cells = <2>; 3297 #address-cells = <2>;
5766 #size-cells = <2>; 3298 #size-cells = <2>;
5767 ranges; 3299 ranges;
5768 3300
5769 gic_its: msi-controll 3301 gic_its: msi-controller@17040000 {
5770 compatible = 3302 compatible = "arm,gic-v3-its";
5771 reg = <0 0x17 3303 reg = <0 0x17040000 0 0x40000>;
5772 3304
5773 msi-controlle 3305 msi-controller;
5774 #msi-cells = 3306 #msi-cells = <1>;
5775 3307
5776 status = "dis 3308 status = "disabled";
5777 }; 3309 };
5778 }; 3310 };
5779 3311
5780 apps_rsc: rsc@17500000 { 3312 apps_rsc: rsc@17500000 {
5781 compatible = "qcom,rp 3313 compatible = "qcom,rpmh-rsc";
5782 reg = <0 0x17500000 0 3314 reg = <0 0x17500000 0 0x10000>,
5783 <0 0x17510000 0 3315 <0 0x17510000 0 0x10000>,
5784 <0 0x17520000 0 3316 <0 0x17520000 0 0x10000>;
5785 reg-names = "drv-0", 3317 reg-names = "drv-0", "drv-1", "drv-2";
5786 3318
5787 interrupts = <GIC_SPI 3319 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
5788 <GIC_SPI 3320 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
5789 <GIC_SPI 3321 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
5790 qcom,tcs-offset = <0x 3322 qcom,tcs-offset = <0xd00>;
5791 qcom,drv-id = <2>; 3323 qcom,drv-id = <2>;
5792 qcom,tcs-config = <AC 3324 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
5793 <WA 3325 <WAKE_TCS 2>, <CONTROL_TCS 0>;
5794 3326
5795 label = "apps_rsc"; 3327 label = "apps_rsc";
5796 power-domains = <&SYS <<
5797 3328
5798 apps_bcm_voter: bcm-v 3329 apps_bcm_voter: bcm-voter {
5799 compatible = 3330 compatible = "qcom,bcm-voter";
5800 }; 3331 };
5801 3332
5802 rpmhcc: clock-control 3333 rpmhcc: clock-controller {
5803 compatible = 3334 compatible = "qcom,x1e80100-rpmh-clk";
5804 3335
5805 clocks = <&xo 3336 clocks = <&xo_board>;
5806 clock-names = 3337 clock-names = "xo";
5807 3338
5808 #clock-cells 3339 #clock-cells = <1>;
5809 }; 3340 };
5810 3341
5811 rpmhpd: power-control 3342 rpmhpd: power-controller {
5812 compatible = 3343 compatible = "qcom,x1e80100-rpmhpd";
5813 3344
5814 operating-poi 3345 operating-points-v2 = <&rpmhpd_opp_table>;
5815 3346
5816 #power-domain 3347 #power-domain-cells = <1>;
5817 3348
5818 rpmhpd_opp_ta 3349 rpmhpd_opp_table: opp-table {
5819 compa 3350 compatible = "operating-points-v2";
5820 3351
5821 rpmhp 3352 rpmhpd_opp_ret: opp-16 {
5822 3353 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
5823 }; 3354 };
5824 3355
5825 rpmhp 3356 rpmhpd_opp_min_svs: opp-48 {
5826 3357 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
5827 }; 3358 };
5828 3359
5829 rpmhp 3360 rpmhpd_opp_low_svs_d2: opp-52 {
5830 3361 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
5831 }; 3362 };
5832 3363
5833 rpmhp 3364 rpmhpd_opp_low_svs_d1: opp-56 {
5834 3365 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
5835 }; 3366 };
5836 3367
5837 rpmhp 3368 rpmhpd_opp_low_svs_d0: opp-60 {
5838 3369 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
5839 }; 3370 };
5840 3371
5841 rpmhp 3372 rpmhpd_opp_low_svs: opp-64 {
5842 3373 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
5843 }; 3374 };
5844 3375
5845 rpmhp 3376 rpmhpd_opp_low_svs_l1: opp-80 {
5846 3377 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
5847 }; 3378 };
5848 3379
5849 rpmhp 3380 rpmhpd_opp_svs: opp-128 {
5850 3381 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
5851 }; 3382 };
5852 3383
5853 rpmhp 3384 rpmhpd_opp_svs_l0: opp-144 {
5854 3385 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
5855 }; 3386 };
5856 3387
5857 rpmhp 3388 rpmhpd_opp_svs_l1: opp-192 {
5858 3389 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
5859 }; 3390 };
5860 3391
5861 rpmhp 3392 rpmhpd_opp_nom: opp-256 {
5862 3393 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
5863 }; 3394 };
5864 3395
5865 rpmhp 3396 rpmhpd_opp_nom_l1: opp-320 {
5866 3397 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
5867 }; 3398 };
5868 3399
5869 rpmhp 3400 rpmhpd_opp_nom_l2: opp-336 {
5870 3401 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
5871 }; 3402 };
5872 3403
5873 rpmhp 3404 rpmhpd_opp_turbo: opp-384 {
5874 3405 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
5875 }; 3406 };
5876 3407
5877 rpmhp 3408 rpmhpd_opp_turbo_l1: opp-416 {
5878 3409 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
5879 }; 3410 };
5880 }; 3411 };
5881 }; 3412 };
5882 }; 3413 };
5883 3414
5884 timer@17800000 { 3415 timer@17800000 {
5885 compatible = "arm,arm 3416 compatible = "arm,armv7-timer-mem";
5886 reg = <0 0x17800000 0 3417 reg = <0 0x17800000 0 0x1000>;
5887 3418
5888 #address-cells = <2>; 3419 #address-cells = <2>;
5889 #size-cells = <1>; 3420 #size-cells = <1>;
5890 ranges = <0 0 0 0 0x2 3421 ranges = <0 0 0 0 0x20000000>;
5891 3422
5892 frame@17801000 { 3423 frame@17801000 {
5893 reg = <0 0x17 3424 reg = <0 0x17801000 0x1000>,
5894 <0 0x17 3425 <0 0x17802000 0x1000>;
5895 3426
5896 interrupts = 3427 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
5897 3428 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
5898 3429
5899 frame-number 3430 frame-number = <0>;
5900 }; 3431 };
5901 3432
5902 frame@17803000 { 3433 frame@17803000 {
5903 reg = <0 0x17 3434 reg = <0 0x17803000 0x1000>;
5904 3435
5905 interrupts = 3436 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
5906 3437
5907 frame-number 3438 frame-number = <1>;
5908 3439
5909 status = "dis 3440 status = "disabled";
5910 }; 3441 };
5911 3442
5912 frame@17805000 { 3443 frame@17805000 {
5913 reg = <0 0x17 3444 reg = <0 0x17805000 0x1000>;
5914 3445
5915 interrupts = 3446 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
5916 3447
5917 frame-number 3448 frame-number = <2>;
5918 3449
5919 status = "dis 3450 status = "disabled";
5920 }; 3451 };
5921 3452
5922 frame@17807000 { 3453 frame@17807000 {
5923 reg = <0 0x17 3454 reg = <0 0x17807000 0x1000>;
5924 3455
5925 interrupts = 3456 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
5926 3457
5927 frame-number 3458 frame-number = <3>;
5928 3459
5929 status = "dis 3460 status = "disabled";
5930 }; 3461 };
5931 3462
5932 frame@17809000 { 3463 frame@17809000 {
5933 reg = <0 0x17 3464 reg = <0 0x17809000 0x1000>;
5934 3465
5935 interrupts = 3466 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
5936 3467
5937 frame-number 3468 frame-number = <4>;
5938 3469
5939 status = "dis 3470 status = "disabled";
5940 }; 3471 };
5941 3472
5942 frame@1780b000 { 3473 frame@1780b000 {
5943 reg = <0 0x17 3474 reg = <0 0x1780b000 0x1000>;
5944 3475
5945 interrupts = 3476 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
5946 3477
5947 frame-number 3478 frame-number = <5>;
5948 3479
5949 status = "dis 3480 status = "disabled";
5950 }; 3481 };
5951 3482
5952 frame@1780d000 { 3483 frame@1780d000 {
5953 reg = <0 0x17 3484 reg = <0 0x1780d000 0x1000>;
5954 3485
5955 interrupts = 3486 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
5956 3487
5957 frame-number 3488 frame-number = <6>;
5958 3489
5959 status = "dis 3490 status = "disabled";
5960 }; 3491 };
5961 }; 3492 };
5962 3493
5963 pmu@24091000 { <<
5964 compatible = "qcom,x1 <<
5965 reg = <0 0x24091000 0 <<
5966 <<
5967 interrupts = <GIC_SPI <<
5968 <<
5969 interconnects = <&mc_ <<
5970 &mc_ <<
5971 <<
5972 operating-points-v2 = <<
5973 <<
5974 llcc_bwmon_opp_table: <<
5975 compatible = <<
5976 <<
5977 opp-0 { <<
5978 opp-p <<
5979 }; <<
5980 <<
5981 opp-1 { <<
5982 opp-p <<
5983 }; <<
5984 <<
5985 opp-2 { <<
5986 opp-p <<
5987 }; <<
5988 <<
5989 opp-3 { <<
5990 opp-p <<
5991 }; <<
5992 <<
5993 opp-4 { <<
5994 opp-p <<
5995 }; <<
5996 <<
5997 opp-5 { <<
5998 opp-p <<
5999 }; <<
6000 <<
6001 opp-6 { <<
6002 opp-p <<
6003 }; <<
6004 <<
6005 opp-7 { <<
6006 opp-p <<
6007 }; <<
6008 <<
6009 opp-8 { <<
6010 opp-p <<
6011 }; <<
6012 <<
6013 opp-9 { <<
6014 opp-p <<
6015 }; <<
6016 }; <<
6017 }; <<
6018 <<
6019 /* cluster0 */ <<
6020 pmu@240b3400 { <<
6021 compatible = "qcom,x1 <<
6022 reg = <0 0x240b3400 0 <<
6023 <<
6024 interrupts = <GIC_SPI <<
6025 <<
6026 interconnects = <&gem <<
6027 &gem <<
6028 <<
6029 operating-points-v2 = <<
6030 <<
6031 cpu_bwmon_opp_table: <<
6032 compatible = <<
6033 <<
6034 opp-0 { <<
6035 opp-p <<
6036 }; <<
6037 <<
6038 opp-1 { <<
6039 opp-p <<
6040 }; <<
6041 <<
6042 opp-2 { <<
6043 opp-p <<
6044 }; <<
6045 <<
6046 opp-3 { <<
6047 opp-p <<
6048 }; <<
6049 <<
6050 opp-4 { <<
6051 opp-p <<
6052 }; <<
6053 <<
6054 opp-5 { <<
6055 opp-p <<
6056 }; <<
6057 }; <<
6058 }; <<
6059 <<
6060 /* cluster2 */ <<
6061 pmu@240b5400 { <<
6062 compatible = "qcom,x1 <<
6063 reg = <0 0x240b5400 0 <<
6064 <<
6065 interrupts = <GIC_SPI <<
6066 <<
6067 interconnects = <&gem <<
6068 &gem <<
6069 <<
6070 operating-points-v2 = <<
6071 }; <<
6072 <<
6073 /* cluster1 */ <<
6074 pmu@240b6400 { <<
6075 compatible = "qcom,x1 <<
6076 reg = <0 0x240b6400 0 <<
6077 <<
6078 interrupts = <GIC_SPI <<
6079 <<
6080 interconnects = <&gem <<
6081 &gem <<
6082 <<
6083 operating-points-v2 = <<
6084 }; <<
6085 <<
6086 system-cache-controller@25000 3494 system-cache-controller@25000000 {
6087 compatible = "qcom,x1 3495 compatible = "qcom,x1e80100-llcc";
6088 reg = <0 0x25000000 0 3496 reg = <0 0x25000000 0 0x200000>,
6089 <0 0x25200000 0 3497 <0 0x25200000 0 0x200000>,
6090 <0 0x25400000 0 3498 <0 0x25400000 0 0x200000>,
6091 <0 0x25600000 0 3499 <0 0x25600000 0 0x200000>,
6092 <0 0x25800000 0 3500 <0 0x25800000 0 0x200000>,
6093 <0 0x25a00000 0 3501 <0 0x25a00000 0 0x200000>,
6094 <0 0x25c00000 0 3502 <0 0x25c00000 0 0x200000>,
6095 <0 0x25e00000 0 3503 <0 0x25e00000 0 0x200000>,
6096 <0 0x26000000 0 !! 3504 <0 0x26000000 0 0x200000>;
6097 <0 0x26200000 0 <<
6098 reg-names = "llcc0_ba 3505 reg-names = "llcc0_base",
6099 "llcc1_ba 3506 "llcc1_base",
6100 "llcc2_ba 3507 "llcc2_base",
6101 "llcc3_ba 3508 "llcc3_base",
6102 "llcc4_ba 3509 "llcc4_base",
6103 "llcc5_ba 3510 "llcc5_base",
6104 "llcc6_ba 3511 "llcc6_base",
6105 "llcc7_ba 3512 "llcc7_base",
6106 "llcc_bro !! 3513 "llcc_broadcast_base";
6107 "llcc_bro <<
6108 interrupts = <GIC_SPI 3514 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
6109 }; 3515 };
6110 <<
6111 remoteproc_adsp: remoteproc@3 <<
6112 compatible = "qcom,x1 <<
6113 reg = <0 0x30000000 0 <<
6114 <<
6115 interrupts-extended = <<
6116 <<
6117 <<
6118 <<
6119 <<
6120 interrupt-names = "wd <<
6121 "fa <<
6122 "re <<
6123 "ha <<
6124 "st <<
6125 <<
6126 clocks = <&rpmhcc RPM <<
6127 clock-names = "xo"; <<
6128 <<
6129 power-domains = <&rpm <<
6130 <&rpm <<
6131 power-domain-names = <<
6132 <<
6133 <<
6134 interconnects = <&lpa <<
6135 &mc_ <<
6136 <<
6137 memory-region = <&ads <<
6138 <&q6_ <<
6139 <<
6140 qcom,qmp = <&aoss_qmp <<
6141 <<
6142 qcom,smem-states = <& <<
6143 qcom,smem-state-names <<
6144 <<
6145 status = "disabled"; <<
6146 <<
6147 glink-edge { <<
6148 interrupts-ex <<
6149 <<
6150 <<
6151 mboxes = <&ip <<
6152 <<
6153 <<
6154 label = "lpas <<
6155 qcom,remote-p <<
6156 <<
6157 fastrpc { <<
6158 compa <<
6159 qcom, <<
6160 label <<
6161 qcom, <<
6162 #addr <<
6163 #size <<
6164 <<
6165 compu <<
6166 <<
6167 <<
6168 <<
6169 <<
6170 <<
6171 }; <<
6172 <<
6173 compu <<
6174 <<
6175 <<
6176 <<
6177 <<
6178 <<
6179 }; <<
6180 <<
6181 compu <<
6182 <<
6183 <<
6184 <<
6185 <<
6186 <<
6187 }; <<
6188 <<
6189 compu <<
6190 <<
6191 <<
6192 <<
6193 <<
6194 <<
6195 }; <<
6196 <<
6197 compu <<
6198 <<
6199 <<
6200 <<
6201 <<
6202 <<
6203 }; <<
6204 }; <<
6205 <<
6206 gpr { <<
6207 compa <<
6208 qcom, <<
6209 qcom, <<
6210 qcom, <<
6211 #addr <<
6212 #size <<
6213 <<
6214 q6apm <<
6215 <<
6216 <<
6217 <<
6218 <<
6219 <<
6220 <<
6221 <<
6222 <<
6223 <<
6224 <<
6225 <<
6226 <<
6227 <<
6228 <<
6229 <<
6230 <<
6231 }; <<
6232 <<
6233 q6prm <<
6234 <<
6235 <<
6236 <<
6237 <<
6238 <<
6239 <<
6240 <<
6241 <<
6242 <<
6243 }; <<
6244 }; <<
6245 }; <<
6246 }; <<
6247 <<
6248 remoteproc_cdsp: remoteproc@3 <<
6249 compatible = "qcom,x1 <<
6250 reg = <0 0x32300000 0 <<
6251 <<
6252 interrupts-extended = <<
6253 <<
6254 <<
6255 <<
6256 <<
6257 interrupt-names = "wd <<
6258 "fa <<
6259 "re <<
6260 "ha <<
6261 "st <<
6262 <<
6263 clocks = <&rpmhcc RPM <<
6264 clock-names = "xo"; <<
6265 <<
6266 power-domains = <&rpm <<
6267 <&rpm <<
6268 <&rpm <<
6269 power-domain-names = <<
6270 <<
6271 <<
6272 <<
6273 interconnects = <&nsp <<
6274 &mc_ <<
6275 <<
6276 memory-region = <&cds <<
6277 <&q6_ <<
6278 <<
6279 qcom,qmp = <&aoss_qmp <<
6280 <<
6281 qcom,smem-states = <& <<
6282 qcom,smem-state-names <<
6283 <<
6284 status = "disabled"; <<
6285 <<
6286 glink-edge { <<
6287 interrupts-ex <<
6288 <<
6289 <<
6290 mboxes = <&ip <<
6291 <<
6292 <<
6293 label = "cdsp <<
6294 qcom,remote-p <<
6295 <<
6296 fastrpc { <<
6297 compa <<
6298 qcom, <<
6299 label <<
6300 qcom, <<
6301 #addr <<
6302 #size <<
6303 <<
6304 compu <<
6305 <<
6306 <<
6307 <<
6308 <<
6309 }; <<
6310 <<
6311 compu <<
6312 <<
6313 <<
6314 <<
6315 <<
6316 }; <<
6317 <<
6318 compu <<
6319 <<
6320 <<
6321 <<
6322 <<
6323 }; <<
6324 <<
6325 compu <<
6326 <<
6327 <<
6328 <<
6329 <<
6330 }; <<
6331 <<
6332 compu <<
6333 <<
6334 <<
6335 <<
6336 <<
6337 }; <<
6338 <<
6339 compu <<
6340 <<
6341 <<
6342 <<
6343 <<
6344 }; <<
6345 <<
6346 compu <<
6347 <<
6348 <<
6349 <<
6350 <<
6351 }; <<
6352 <<
6353 compu <<
6354 <<
6355 <<
6356 <<
6357 <<
6358 }; <<
6359 <<
6360 /* no <<
6361 <<
6362 compu <<
6363 <<
6364 <<
6365 <<
6366 <<
6367 }; <<
6368 <<
6369 compu <<
6370 <<
6371 <<
6372 <<
6373 <<
6374 }; <<
6375 <<
6376 compu <<
6377 <<
6378 <<
6379 <<
6380 <<
6381 }; <<
6382 <<
6383 compu <<
6384 <<
6385 <<
6386 <<
6387 <<
6388 }; <<
6389 }; <<
6390 }; <<
6391 }; <<
6392 }; 3516 };
6393 3517
6394 timer { 3518 timer {
6395 compatible = "arm,armv8-timer 3519 compatible = "arm,armv8-timer";
6396 3520
6397 interrupts = <GIC_PPI 13 IRQ_ 3521 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
6398 <GIC_PPI 14 IRQ_ 3522 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
6399 <GIC_PPI 11 IRQ_ 3523 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
6400 <GIC_PPI 10 IRQ_ 3524 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
6401 }; <<
6402 <<
6403 thermal-zones { <<
6404 aoss0-thermal { <<
6405 thermal-sensors = <&t <<
6406 <<
6407 trips { <<
6408 trip-point0 { <<
6409 tempe <<
6410 hyste <<
6411 type <<
6412 }; <<
6413 <<
6414 aoss0-critica <<
6415 tempe <<
6416 hyste <<
6417 type <<
6418 }; <<
6419 }; <<
6420 }; <<
6421 <<
6422 cpu0-0-top-thermal { <<
6423 polling-delay-passive <<
6424 <<
6425 thermal-sensors = <&t <<
6426 <<
6427 trips { <<
6428 trip-point0 { <<
6429 tempe <<
6430 hyste <<
6431 type <<
6432 }; <<
6433 <<
6434 trip-point1 { <<
6435 tempe <<
6436 hyste <<
6437 type <<
6438 }; <<
6439 <<
6440 cpu-critical <<
6441 tempe <<
6442 hyste <<
6443 type <<
6444 }; <<
6445 }; <<
6446 }; <<
6447 <<
6448 cpu0-0-btm-thermal { <<
6449 polling-delay-passive <<
6450 <<
6451 thermal-sensors = <&t <<
6452 <<
6453 trips { <<
6454 trip-point0 { <<
6455 tempe <<
6456 hyste <<
6457 type <<
6458 }; <<
6459 <<
6460 trip-point1 { <<
6461 tempe <<
6462 hyste <<
6463 type <<
6464 }; <<
6465 <<
6466 cpu-critical <<
6467 tempe <<
6468 hyste <<
6469 type <<
6470 }; <<
6471 }; <<
6472 }; <<
6473 <<
6474 cpu0-1-top-thermal { <<
6475 polling-delay-passive <<
6476 <<
6477 thermal-sensors = <&t <<
6478 <<
6479 trips { <<
6480 trip-point0 { <<
6481 tempe <<
6482 hyste <<
6483 type <<
6484 }; <<
6485 <<
6486 trip-point1 { <<
6487 tempe <<
6488 hyste <<
6489 type <<
6490 }; <<
6491 <<
6492 cpu-critical <<
6493 tempe <<
6494 hyste <<
6495 type <<
6496 }; <<
6497 }; <<
6498 }; <<
6499 <<
6500 cpu0-1-btm-thermal { <<
6501 polling-delay-passive <<
6502 <<
6503 thermal-sensors = <&t <<
6504 <<
6505 trips { <<
6506 trip-point0 { <<
6507 tempe <<
6508 hyste <<
6509 type <<
6510 }; <<
6511 <<
6512 trip-point1 { <<
6513 tempe <<
6514 hyste <<
6515 type <<
6516 }; <<
6517 <<
6518 cpu-critical <<
6519 tempe <<
6520 hyste <<
6521 type <<
6522 }; <<
6523 }; <<
6524 }; <<
6525 <<
6526 cpu0-2-top-thermal { <<
6527 polling-delay-passive <<
6528 <<
6529 thermal-sensors = <&t <<
6530 <<
6531 trips { <<
6532 trip-point0 { <<
6533 tempe <<
6534 hyste <<
6535 type <<
6536 }; <<
6537 <<
6538 trip-point1 { <<
6539 tempe <<
6540 hyste <<
6541 type <<
6542 }; <<
6543 <<
6544 cpu-critical <<
6545 tempe <<
6546 hyste <<
6547 type <<
6548 }; <<
6549 }; <<
6550 }; <<
6551 <<
6552 cpu0-2-btm-thermal { <<
6553 polling-delay-passive <<
6554 <<
6555 thermal-sensors = <&t <<
6556 <<
6557 trips { <<
6558 trip-point0 { <<
6559 tempe <<
6560 hyste <<
6561 type <<
6562 }; <<
6563 <<
6564 trip-point1 { <<
6565 tempe <<
6566 hyste <<
6567 type <<
6568 }; <<
6569 <<
6570 cpu-critical <<
6571 tempe <<
6572 hyste <<
6573 type <<
6574 }; <<
6575 }; <<
6576 }; <<
6577 <<
6578 cpu0-3-top-thermal { <<
6579 polling-delay-passive <<
6580 <<
6581 thermal-sensors = <&t <<
6582 <<
6583 trips { <<
6584 trip-point0 { <<
6585 tempe <<
6586 hyste <<
6587 type <<
6588 }; <<
6589 <<
6590 trip-point1 { <<
6591 tempe <<
6592 hyste <<
6593 type <<
6594 }; <<
6595 <<
6596 cpu-critical <<
6597 tempe <<
6598 hyste <<
6599 type <<
6600 }; <<
6601 }; <<
6602 }; <<
6603 <<
6604 cpu0-3-btm-thermal { <<
6605 polling-delay-passive <<
6606 <<
6607 thermal-sensors = <&t <<
6608 <<
6609 trips { <<
6610 trip-point0 { <<
6611 tempe <<
6612 hyste <<
6613 type <<
6614 }; <<
6615 <<
6616 trip-point1 { <<
6617 tempe <<
6618 hyste <<
6619 type <<
6620 }; <<
6621 <<
6622 cpu-critical <<
6623 tempe <<
6624 hyste <<
6625 type <<
6626 }; <<
6627 }; <<
6628 }; <<
6629 <<
6630 cpuss0-top-thermal { <<
6631 thermal-sensors = <&t <<
6632 <<
6633 trips { <<
6634 trip-point0 { <<
6635 tempe <<
6636 hyste <<
6637 type <<
6638 }; <<
6639 <<
6640 cpuss2-critic <<
6641 tempe <<
6642 hyste <<
6643 type <<
6644 }; <<
6645 }; <<
6646 }; <<
6647 <<
6648 cpuss0-btm-thermal { <<
6649 thermal-sensors = <&t <<
6650 <<
6651 trips { <<
6652 trip-point0 { <<
6653 tempe <<
6654 hyste <<
6655 type <<
6656 }; <<
6657 <<
6658 cpuss2-critic <<
6659 tempe <<
6660 hyste <<
6661 type <<
6662 }; <<
6663 }; <<
6664 }; <<
6665 <<
6666 mem-thermal { <<
6667 thermal-sensors = <&t <<
6668 <<
6669 trips { <<
6670 trip-point0 { <<
6671 tempe <<
6672 hyste <<
6673 type <<
6674 }; <<
6675 <<
6676 mem-critical <<
6677 tempe <<
6678 hyste <<
6679 type <<
6680 }; <<
6681 }; <<
6682 }; <<
6683 <<
6684 video-thermal { <<
6685 polling-delay-passive <<
6686 <<
6687 thermal-sensors = <&t <<
6688 <<
6689 trips { <<
6690 trip-point0 { <<
6691 tempe <<
6692 hyste <<
6693 type <<
6694 }; <<
6695 }; <<
6696 }; <<
6697 <<
6698 aoss1-thermal { <<
6699 thermal-sensors = <&t <<
6700 <<
6701 trips { <<
6702 trip-point0 { <<
6703 tempe <<
6704 hyste <<
6705 type <<
6706 }; <<
6707 <<
6708 aoss0-critica <<
6709 tempe <<
6710 hyste <<
6711 type <<
6712 }; <<
6713 }; <<
6714 }; <<
6715 <<
6716 cpu1-0-top-thermal { <<
6717 polling-delay-passive <<
6718 <<
6719 thermal-sensors = <&t <<
6720 <<
6721 trips { <<
6722 trip-point0 { <<
6723 tempe <<
6724 hyste <<
6725 type <<
6726 }; <<
6727 <<
6728 trip-point1 { <<
6729 tempe <<
6730 hyste <<
6731 type <<
6732 }; <<
6733 <<
6734 cpu-critical <<
6735 tempe <<
6736 hyste <<
6737 type <<
6738 }; <<
6739 }; <<
6740 }; <<
6741 <<
6742 cpu1-0-btm-thermal { <<
6743 polling-delay-passive <<
6744 <<
6745 thermal-sensors = <&t <<
6746 <<
6747 trips { <<
6748 trip-point0 { <<
6749 tempe <<
6750 hyste <<
6751 type <<
6752 }; <<
6753 <<
6754 trip-point1 { <<
6755 tempe <<
6756 hyste <<
6757 type <<
6758 }; <<
6759 <<
6760 cpu-critical <<
6761 tempe <<
6762 hyste <<
6763 type <<
6764 }; <<
6765 }; <<
6766 }; <<
6767 <<
6768 cpu1-1-top-thermal { <<
6769 polling-delay-passive <<
6770 <<
6771 thermal-sensors = <&t <<
6772 <<
6773 trips { <<
6774 trip-point0 { <<
6775 tempe <<
6776 hyste <<
6777 type <<
6778 }; <<
6779 <<
6780 trip-point1 { <<
6781 tempe <<
6782 hyste <<
6783 type <<
6784 }; <<
6785 <<
6786 cpu-critical <<
6787 tempe <<
6788 hyste <<
6789 type <<
6790 }; <<
6791 }; <<
6792 }; <<
6793 <<
6794 cpu1-1-btm-thermal { <<
6795 polling-delay-passive <<
6796 <<
6797 thermal-sensors = <&t <<
6798 <<
6799 trips { <<
6800 trip-point0 { <<
6801 tempe <<
6802 hyste <<
6803 type <<
6804 }; <<
6805 <<
6806 trip-point1 { <<
6807 tempe <<
6808 hyste <<
6809 type <<
6810 }; <<
6811 <<
6812 cpu-critical <<
6813 tempe <<
6814 hyste <<
6815 type <<
6816 }; <<
6817 }; <<
6818 }; <<
6819 <<
6820 cpu1-2-top-thermal { <<
6821 polling-delay-passive <<
6822 <<
6823 thermal-sensors = <&t <<
6824 <<
6825 trips { <<
6826 trip-point0 { <<
6827 tempe <<
6828 hyste <<
6829 type <<
6830 }; <<
6831 <<
6832 trip-point1 { <<
6833 tempe <<
6834 hyste <<
6835 type <<
6836 }; <<
6837 <<
6838 cpu-critical <<
6839 tempe <<
6840 hyste <<
6841 type <<
6842 }; <<
6843 }; <<
6844 }; <<
6845 <<
6846 cpu1-2-btm-thermal { <<
6847 polling-delay-passive <<
6848 <<
6849 thermal-sensors = <&t <<
6850 <<
6851 trips { <<
6852 trip-point0 { <<
6853 tempe <<
6854 hyste <<
6855 type <<
6856 }; <<
6857 <<
6858 trip-point1 { <<
6859 tempe <<
6860 hyste <<
6861 type <<
6862 }; <<
6863 <<
6864 cpu-critical <<
6865 tempe <<
6866 hyste <<
6867 type <<
6868 }; <<
6869 }; <<
6870 }; <<
6871 <<
6872 cpu1-3-top-thermal { <<
6873 polling-delay-passive <<
6874 <<
6875 thermal-sensors = <&t <<
6876 <<
6877 trips { <<
6878 trip-point0 { <<
6879 tempe <<
6880 hyste <<
6881 type <<
6882 }; <<
6883 <<
6884 trip-point1 { <<
6885 tempe <<
6886 hyste <<
6887 type <<
6888 }; <<
6889 <<
6890 cpu-critical <<
6891 tempe <<
6892 hyste <<
6893 type <<
6894 }; <<
6895 }; <<
6896 }; <<
6897 <<
6898 cpu1-3-btm-thermal { <<
6899 polling-delay-passive <<
6900 <<
6901 thermal-sensors = <&t <<
6902 <<
6903 trips { <<
6904 trip-point0 { <<
6905 tempe <<
6906 hyste <<
6907 type <<
6908 }; <<
6909 <<
6910 trip-point1 { <<
6911 tempe <<
6912 hyste <<
6913 type <<
6914 }; <<
6915 <<
6916 cpu-critical <<
6917 tempe <<
6918 hyste <<
6919 type <<
6920 }; <<
6921 }; <<
6922 }; <<
6923 <<
6924 cpuss1-top-thermal { <<
6925 thermal-sensors = <&t <<
6926 <<
6927 trips { <<
6928 trip-point0 { <<
6929 tempe <<
6930 hyste <<
6931 type <<
6932 }; <<
6933 <<
6934 cpuss2-critic <<
6935 tempe <<
6936 hyste <<
6937 type <<
6938 }; <<
6939 }; <<
6940 }; <<
6941 <<
6942 cpuss1-btm-thermal { <<
6943 thermal-sensors = <&t <<
6944 <<
6945 trips { <<
6946 trip-point0 { <<
6947 tempe <<
6948 hyste <<
6949 type <<
6950 }; <<
6951 <<
6952 cpuss2-critic <<
6953 tempe <<
6954 hyste <<
6955 type <<
6956 }; <<
6957 }; <<
6958 }; <<
6959 <<
6960 aoss2-thermal { <<
6961 thermal-sensors = <&t <<
6962 <<
6963 trips { <<
6964 trip-point0 { <<
6965 tempe <<
6966 hyste <<
6967 type <<
6968 }; <<
6969 <<
6970 aoss0-critica <<
6971 tempe <<
6972 hyste <<
6973 type <<
6974 }; <<
6975 }; <<
6976 }; <<
6977 <<
6978 cpu2-0-top-thermal { <<
6979 polling-delay-passive <<
6980 <<
6981 thermal-sensors = <&t <<
6982 <<
6983 trips { <<
6984 trip-point0 { <<
6985 tempe <<
6986 hyste <<
6987 type <<
6988 }; <<
6989 <<
6990 trip-point1 { <<
6991 tempe <<
6992 hyste <<
6993 type <<
6994 }; <<
6995 <<
6996 cpu-critical <<
6997 tempe <<
6998 hyste <<
6999 type <<
7000 }; <<
7001 }; <<
7002 }; <<
7003 <<
7004 cpu2-0-btm-thermal { <<
7005 polling-delay-passive <<
7006 <<
7007 thermal-sensors = <&t <<
7008 <<
7009 trips { <<
7010 trip-point0 { <<
7011 tempe <<
7012 hyste <<
7013 type <<
7014 }; <<
7015 <<
7016 trip-point1 { <<
7017 tempe <<
7018 hyste <<
7019 type <<
7020 }; <<
7021 <<
7022 cpu-critical <<
7023 tempe <<
7024 hyste <<
7025 type <<
7026 }; <<
7027 }; <<
7028 }; <<
7029 <<
7030 cpu2-1-top-thermal { <<
7031 polling-delay-passive <<
7032 <<
7033 thermal-sensors = <&t <<
7034 <<
7035 trips { <<
7036 trip-point0 { <<
7037 tempe <<
7038 hyste <<
7039 type <<
7040 }; <<
7041 <<
7042 trip-point1 { <<
7043 tempe <<
7044 hyste <<
7045 type <<
7046 }; <<
7047 <<
7048 cpu-critical <<
7049 tempe <<
7050 hyste <<
7051 type <<
7052 }; <<
7053 }; <<
7054 }; <<
7055 <<
7056 cpu2-1-btm-thermal { <<
7057 polling-delay-passive <<
7058 <<
7059 thermal-sensors = <&t <<
7060 <<
7061 trips { <<
7062 trip-point0 { <<
7063 tempe <<
7064 hyste <<
7065 type <<
7066 }; <<
7067 <<
7068 trip-point1 { <<
7069 tempe <<
7070 hyste <<
7071 type <<
7072 }; <<
7073 <<
7074 cpu-critical <<
7075 tempe <<
7076 hyste <<
7077 type <<
7078 }; <<
7079 }; <<
7080 }; <<
7081 <<
7082 cpu2-2-top-thermal { <<
7083 polling-delay-passive <<
7084 <<
7085 thermal-sensors = <&t <<
7086 <<
7087 trips { <<
7088 trip-point0 { <<
7089 tempe <<
7090 hyste <<
7091 type <<
7092 }; <<
7093 <<
7094 trip-point1 { <<
7095 tempe <<
7096 hyste <<
7097 type <<
7098 }; <<
7099 <<
7100 cpu-critical <<
7101 tempe <<
7102 hyste <<
7103 type <<
7104 }; <<
7105 }; <<
7106 }; <<
7107 <<
7108 cpu2-2-btm-thermal { <<
7109 polling-delay-passive <<
7110 <<
7111 thermal-sensors = <&t <<
7112 <<
7113 trips { <<
7114 trip-point0 { <<
7115 tempe <<
7116 hyste <<
7117 type <<
7118 }; <<
7119 <<
7120 trip-point1 { <<
7121 tempe <<
7122 hyste <<
7123 type <<
7124 }; <<
7125 <<
7126 cpu-critical <<
7127 tempe <<
7128 hyste <<
7129 type <<
7130 }; <<
7131 }; <<
7132 }; <<
7133 <<
7134 cpu2-3-top-thermal { <<
7135 polling-delay-passive <<
7136 <<
7137 thermal-sensors = <&t <<
7138 <<
7139 trips { <<
7140 trip-point0 { <<
7141 tempe <<
7142 hyste <<
7143 type <<
7144 }; <<
7145 <<
7146 trip-point1 { <<
7147 tempe <<
7148 hyste <<
7149 type <<
7150 }; <<
7151 <<
7152 cpu-critical <<
7153 tempe <<
7154 hyste <<
7155 type <<
7156 }; <<
7157 }; <<
7158 }; <<
7159 <<
7160 cpu2-3-btm-thermal { <<
7161 polling-delay-passive <<
7162 <<
7163 thermal-sensors = <&t <<
7164 <<
7165 trips { <<
7166 trip-point0 { <<
7167 tempe <<
7168 hyste <<
7169 type <<
7170 }; <<
7171 <<
7172 trip-point1 { <<
7173 tempe <<
7174 hyste <<
7175 type <<
7176 }; <<
7177 <<
7178 cpu-critical <<
7179 tempe <<
7180 hyste <<
7181 type <<
7182 }; <<
7183 }; <<
7184 }; <<
7185 <<
7186 cpuss2-top-thermal { <<
7187 thermal-sensors = <&t <<
7188 <<
7189 trips { <<
7190 trip-point0 { <<
7191 tempe <<
7192 hyste <<
7193 type <<
7194 }; <<
7195 <<
7196 cpuss2-critic <<
7197 tempe <<
7198 hyste <<
7199 type <<
7200 }; <<
7201 }; <<
7202 }; <<
7203 <<
7204 cpuss2-btm-thermal { <<
7205 thermal-sensors = <&t <<
7206 <<
7207 trips { <<
7208 trip-point0 { <<
7209 tempe <<
7210 hyste <<
7211 type <<
7212 }; <<
7213 <<
7214 cpuss2-critic <<
7215 tempe <<
7216 hyste <<
7217 type <<
7218 }; <<
7219 }; <<
7220 }; <<
7221 <<
7222 aoss3-thermal { <<
7223 thermal-sensors = <&t <<
7224 <<
7225 trips { <<
7226 trip-point0 { <<
7227 tempe <<
7228 hyste <<
7229 type <<
7230 }; <<
7231 <<
7232 aoss0-critica <<
7233 tempe <<
7234 hyste <<
7235 type <<
7236 }; <<
7237 }; <<
7238 }; <<
7239 <<
7240 nsp0-thermal { <<
7241 thermal-sensors = <&t <<
7242 <<
7243 trips { <<
7244 trip-point0 { <<
7245 tempe <<
7246 hyste <<
7247 type <<
7248 }; <<
7249 <<
7250 nsp0-critical <<
7251 tempe <<
7252 hyste <<
7253 type <<
7254 }; <<
7255 }; <<
7256 }; <<
7257 <<
7258 nsp1-thermal { <<
7259 thermal-sensors = <&t <<
7260 <<
7261 trips { <<
7262 trip-point0 { <<
7263 tempe <<
7264 hyste <<
7265 type <<
7266 }; <<
7267 <<
7268 nsp1-critical <<
7269 tempe <<
7270 hyste <<
7271 type <<
7272 }; <<
7273 }; <<
7274 }; <<
7275 <<
7276 nsp2-thermal { <<
7277 thermal-sensors = <&t <<
7278 <<
7279 trips { <<
7280 trip-point0 { <<
7281 tempe <<
7282 hyste <<
7283 type <<
7284 }; <<
7285 <<
7286 nsp2-critical <<
7287 tempe <<
7288 hyste <<
7289 type <<
7290 }; <<
7291 }; <<
7292 }; <<
7293 <<
7294 nsp3-thermal { <<
7295 thermal-sensors = <&t <<
7296 <<
7297 trips { <<
7298 trip-point0 { <<
7299 tempe <<
7300 hyste <<
7301 type <<
7302 }; <<
7303 <<
7304 nsp3-critical <<
7305 tempe <<
7306 hyste <<
7307 type <<
7308 }; <<
7309 }; <<
7310 }; <<
7311 <<
7312 gpuss-0-thermal { <<
7313 polling-delay-passive <<
7314 <<
7315 thermal-sensors = <&t <<
7316 <<
7317 trips { <<
7318 trip-point0 { <<
7319 tempe <<
7320 hyste <<
7321 type <<
7322 }; <<
7323 <<
7324 trip-point1 { <<
7325 tempe <<
7326 hyste <<
7327 type <<
7328 }; <<
7329 <<
7330 trip-point2 { <<
7331 tempe <<
7332 hyste <<
7333 type <<
7334 }; <<
7335 }; <<
7336 }; <<
7337 <<
7338 gpuss-1-thermal { <<
7339 polling-delay-passive <<
7340 <<
7341 thermal-sensors = <&t <<
7342 <<
7343 trips { <<
7344 trip-point0 { <<
7345 tempe <<
7346 hyste <<
7347 type <<
7348 }; <<
7349 <<
7350 trip-point1 { <<
7351 tempe <<
7352 hyste <<
7353 type <<
7354 }; <<
7355 <<
7356 trip-point2 { <<
7357 tempe <<
7358 hyste <<
7359 type <<
7360 }; <<
7361 }; <<
7362 }; <<
7363 <<
7364 gpuss-2-thermal { <<
7365 polling-delay-passive <<
7366 <<
7367 thermal-sensors = <&t <<
7368 <<
7369 trips { <<
7370 trip-point0 { <<
7371 tempe <<
7372 hyste <<
7373 type <<
7374 }; <<
7375 <<
7376 trip-point1 { <<
7377 tempe <<
7378 hyste <<
7379 type <<
7380 }; <<
7381 <<
7382 trip-point2 { <<
7383 tempe <<
7384 hyste <<
7385 type <<
7386 }; <<
7387 }; <<
7388 }; <<
7389 <<
7390 gpuss-3-thermal { <<
7391 polling-delay-passive <<
7392 <<
7393 thermal-sensors = <&t <<
7394 <<
7395 trips { <<
7396 trip-point0 { <<
7397 tempe <<
7398 hyste <<
7399 type <<
7400 }; <<
7401 <<
7402 trip-point1 { <<
7403 tempe <<
7404 hyste <<
7405 type <<
7406 }; <<
7407 <<
7408 trip-point2 { <<
7409 tempe <<
7410 hyste <<
7411 type <<
7412 }; <<
7413 }; <<
7414 }; <<
7415 <<
7416 gpuss-4-thermal { <<
7417 polling-delay-passive <<
7418 <<
7419 thermal-sensors = <&t <<
7420 <<
7421 trips { <<
7422 trip-point0 { <<
7423 tempe <<
7424 hyste <<
7425 type <<
7426 }; <<
7427 <<
7428 trip-point1 { <<
7429 tempe <<
7430 hyste <<
7431 type <<
7432 }; <<
7433 <<
7434 trip-point2 { <<
7435 tempe <<
7436 hyste <<
7437 type <<
7438 }; <<
7439 }; <<
7440 }; <<
7441 <<
7442 gpuss-5-thermal { <<
7443 polling-delay-passive <<
7444 <<
7445 thermal-sensors = <&t <<
7446 <<
7447 trips { <<
7448 trip-point0 { <<
7449 tempe <<
7450 hyste <<
7451 type <<
7452 }; <<
7453 <<
7454 trip-point1 { <<
7455 tempe <<
7456 hyste <<
7457 type <<
7458 }; <<
7459 <<
7460 trip-point2 { <<
7461 tempe <<
7462 hyste <<
7463 type <<
7464 }; <<
7465 }; <<
7466 }; <<
7467 <<
7468 gpuss-6-thermal { <<
7469 polling-delay-passive <<
7470 <<
7471 thermal-sensors = <&t <<
7472 <<
7473 trips { <<
7474 trip-point0 { <<
7475 tempe <<
7476 hyste <<
7477 type <<
7478 }; <<
7479 <<
7480 trip-point1 { <<
7481 tempe <<
7482 hyste <<
7483 type <<
7484 }; <<
7485 <<
7486 trip-point2 { <<
7487 tempe <<
7488 hyste <<
7489 type <<
7490 }; <<
7491 }; <<
7492 }; <<
7493 <<
7494 gpuss-7-thermal { <<
7495 polling-delay-passive <<
7496 <<
7497 thermal-sensors = <&t <<
7498 <<
7499 trips { <<
7500 trip-point0 { <<
7501 tempe <<
7502 hyste <<
7503 type <<
7504 }; <<
7505 <<
7506 trip-point1 { <<
7507 tempe <<
7508 hyste <<
7509 type <<
7510 }; <<
7511 <<
7512 trip-point2 { <<
7513 tempe <<
7514 hyste <<
7515 type <<
7516 }; <<
7517 }; <<
7518 }; <<
7519 <<
7520 camera0-thermal { <<
7521 thermal-sensors = <&t <<
7522 <<
7523 trips { <<
7524 trip-point0 { <<
7525 tempe <<
7526 hyste <<
7527 type <<
7528 }; <<
7529 <<
7530 camera0-criti <<
7531 tempe <<
7532 hyste <<
7533 type <<
7534 }; <<
7535 }; <<
7536 }; <<
7537 <<
7538 camera1-thermal { <<
7539 thermal-sensors = <&t <<
7540 <<
7541 trips { <<
7542 trip-point0 { <<
7543 tempe <<
7544 hyste <<
7545 type <<
7546 }; <<
7547 <<
7548 camera0-criti <<
7549 tempe <<
7550 hyste <<
7551 type <<
7552 }; <<
7553 }; <<
7554 }; <<
7555 }; 3525 };
7556 }; 3526 };
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