1 // SPDX-License-Identifier: BSD-3-Clause
2 /*
3 * Copyright (c) 2023 Qualcomm Innovation Cent
4 */
5
6 #include <dt-bindings/clock/qcom,rpmh.h>
7 #include <dt-bindings/clock/qcom,sc8280xp-lpas
8 #include <dt-bindings/clock/qcom,x1e80100-disp
9 #include <dt-bindings/clock/qcom,x1e80100-gcc.
10 #include <dt-bindings/clock/qcom,x1e80100-gpuc
11 #include <dt-bindings/clock/qcom,x1e80100-tcsr
12 #include <dt-bindings/dma/qcom-gpi.h>
13 #include <dt-bindings/interconnect/qcom,icc.h>
14 #include <dt-bindings/interconnect/qcom,x1e801
15 #include <dt-bindings/interrupt-controller/arm
16 #include <dt-bindings/mailbox/qcom-ipcc.h>
17 #include <dt-bindings/phy/phy-qcom-qmp.h>
18 #include <dt-bindings/power/qcom,rpmhpd.h>
19 #include <dt-bindings/power/qcom-rpmpd.h>
20 #include <dt-bindings/soc/qcom,gpr.h>
21 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
22 #include <dt-bindings/sound/qcom,q6dsp-lpass-p
23
24 / {
25 interrupt-parent = <&intc>;
26
27 #address-cells = <2>;
28 #size-cells = <2>;
29
30 chosen { };
31
32 clocks {
33 xo_board: xo-board {
34 compatible = "fixed-cl
35 clock-frequency = <768
36 #clock-cells = <0>;
37 };
38
39 sleep_clk: sleep-clk {
40 compatible = "fixed-cl
41 clock-frequency = <320
42 #clock-cells = <0>;
43 };
44
45 bi_tcxo_div2: bi-tcxo-div2-clk
46 compatible = "fixed-fa
47 #clock-cells = <0>;
48
49 clocks = <&rpmhcc RPMH
50 clock-mult = <1>;
51 clock-div = <2>;
52 };
53
54 bi_tcxo_ao_div2: bi-tcxo-ao-di
55 compatible = "fixed-fa
56 #clock-cells = <0>;
57
58 clocks = <&rpmhcc RPMH
59 clock-mult = <1>;
60 clock-div = <2>;
61 };
62 };
63
64 cpus {
65 #address-cells = <2>;
66 #size-cells = <0>;
67
68 CPU0: cpu@0 {
69 device_type = "cpu";
70 compatible = "qcom,ory
71 reg = <0x0 0x0>;
72 enable-method = "psci"
73 next-level-cache = <&L
74 power-domains = <&CPU_
75 power-domain-names = "
76 cpu-idle-states = <&CL
77
78 L2_0: l2-cache {
79 compatible = "
80 cache-level =
81 cache-unified;
82 };
83 };
84
85 CPU1: cpu@100 {
86 device_type = "cpu";
87 compatible = "qcom,ory
88 reg = <0x0 0x100>;
89 enable-method = "psci"
90 next-level-cache = <&L
91 power-domains = <&CPU_
92 power-domain-names = "
93 cpu-idle-states = <&CL
94 };
95
96 CPU2: cpu@200 {
97 device_type = "cpu";
98 compatible = "qcom,ory
99 reg = <0x0 0x200>;
100 enable-method = "psci"
101 next-level-cache = <&L
102 power-domains = <&CPU_
103 power-domain-names = "
104 cpu-idle-states = <&CL
105 };
106
107 CPU3: cpu@300 {
108 device_type = "cpu";
109 compatible = "qcom,ory
110 reg = <0x0 0x300>;
111 enable-method = "psci"
112 next-level-cache = <&L
113 power-domains = <&CPU_
114 power-domain-names = "
115 cpu-idle-states = <&CL
116 };
117
118 CPU4: cpu@10000 {
119 device_type = "cpu";
120 compatible = "qcom,ory
121 reg = <0x0 0x10000>;
122 enable-method = "psci"
123 next-level-cache = <&L
124 power-domains = <&CPU_
125 power-domain-names = "
126 cpu-idle-states = <&CL
127
128 L2_1: l2-cache {
129 compatible = "
130 cache-level =
131 cache-unified;
132 };
133 };
134
135 CPU5: cpu@10100 {
136 device_type = "cpu";
137 compatible = "qcom,ory
138 reg = <0x0 0x10100>;
139 enable-method = "psci"
140 next-level-cache = <&L
141 power-domains = <&CPU_
142 power-domain-names = "
143 cpu-idle-states = <&CL
144 };
145
146 CPU6: cpu@10200 {
147 device_type = "cpu";
148 compatible = "qcom,ory
149 reg = <0x0 0x10200>;
150 enable-method = "psci"
151 next-level-cache = <&L
152 power-domains = <&CPU_
153 power-domain-names = "
154 cpu-idle-states = <&CL
155 };
156
157 CPU7: cpu@10300 {
158 device_type = "cpu";
159 compatible = "qcom,ory
160 reg = <0x0 0x10300>;
161 enable-method = "psci"
162 next-level-cache = <&L
163 power-domains = <&CPU_
164 power-domain-names = "
165 cpu-idle-states = <&CL
166 };
167
168 CPU8: cpu@20000 {
169 device_type = "cpu";
170 compatible = "qcom,ory
171 reg = <0x0 0x20000>;
172 enable-method = "psci"
173 next-level-cache = <&L
174 power-domains = <&CPU_
175 power-domain-names = "
176 cpu-idle-states = <&CL
177
178 L2_2: l2-cache {
179 compatible = "
180 cache-level =
181 cache-unified;
182 };
183 };
184
185 CPU9: cpu@20100 {
186 device_type = "cpu";
187 compatible = "qcom,ory
188 reg = <0x0 0x20100>;
189 enable-method = "psci"
190 next-level-cache = <&L
191 power-domains = <&CPU_
192 power-domain-names = "
193 cpu-idle-states = <&CL
194 };
195
196 CPU10: cpu@20200 {
197 device_type = "cpu";
198 compatible = "qcom,ory
199 reg = <0x0 0x20200>;
200 enable-method = "psci"
201 next-level-cache = <&L
202 power-domains = <&CPU_
203 power-domain-names = "
204 cpu-idle-states = <&CL
205 };
206
207 CPU11: cpu@20300 {
208 device_type = "cpu";
209 compatible = "qcom,ory
210 reg = <0x0 0x20300>;
211 enable-method = "psci"
212 next-level-cache = <&L
213 power-domains = <&CPU_
214 power-domain-names = "
215 cpu-idle-states = <&CL
216 };
217
218 cpu-map {
219 cluster0 {
220 core0 {
221 cpu =
222 };
223
224 core1 {
225 cpu =
226 };
227
228 core2 {
229 cpu =
230 };
231
232 core3 {
233 cpu =
234 };
235 };
236
237 cluster1 {
238 core0 {
239 cpu =
240 };
241
242 core1 {
243 cpu =
244 };
245
246 core2 {
247 cpu =
248 };
249
250 core3 {
251 cpu =
252 };
253 };
254
255 cluster2 {
256 core0 {
257 cpu =
258 };
259
260 core1 {
261 cpu =
262 };
263
264 core2 {
265 cpu =
266 };
267
268 core3 {
269 cpu =
270 };
271 };
272 };
273
274 idle-states {
275 entry-method = "psci";
276
277 CLUSTER_C4: cpu-sleep-
278 compatible = "
279 idle-state-nam
280 arm,psci-suspe
281 entry-latency-
282 exit-latency-u
283 min-residency-
284 };
285 };
286
287 domain-idle-states {
288 CLUSTER_CL4: cluster-s
289 compatible = "
290 idle-state-nam
291 arm,psci-suspe
292 entry-latency-
293 exit-latency-u
294 min-residency-
295 };
296
297 CLUSTER_CL5: cluster-s
298 compatible = "
299 idle-state-nam
300 arm,psci-suspe
301 entry-latency-
302 exit-latency-u
303 min-residency-
304 };
305 };
306 };
307
308 firmware {
309 scm: scm {
310 compatible = "qcom,scm
311 interconnects = <&aggr
312 &mc_v
313 };
314 };
315
316 clk_virt: interconnect-0 {
317 compatible = "qcom,x1e80100-cl
318 #interconnect-cells = <2>;
319 qcom,bcm-voters = <&apps_bcm_v
320 };
321
322 mc_virt: interconnect-1 {
323 compatible = "qcom,x1e80100-mc
324 #interconnect-cells = <2>;
325 qcom,bcm-voters = <&apps_bcm_v
326 };
327
328 memory@80000000 {
329 device_type = "memory";
330 /* We expect the bootloader to
331 reg = <0 0x80000000 0 0>;
332 };
333
334 pmu {
335 compatible = "arm,armv8-pmuv3"
336 interrupts = <GIC_PPI 7 IRQ_TY
337 };
338
339 psci {
340 compatible = "arm,psci-1.0";
341 method = "smc";
342
343 CPU_PD0: power-domain-cpu0 {
344 #power-domain-cells =
345 power-domains = <&CLUS
346 };
347
348 CPU_PD1: power-domain-cpu1 {
349 #power-domain-cells =
350 power-domains = <&CLUS
351 };
352
353 CPU_PD2: power-domain-cpu2 {
354 #power-domain-cells =
355 power-domains = <&CLUS
356 };
357
358 CPU_PD3: power-domain-cpu3 {
359 #power-domain-cells =
360 power-domains = <&CLUS
361 };
362
363 CPU_PD4: power-domain-cpu4 {
364 #power-domain-cells =
365 power-domains = <&CLUS
366 };
367
368 CPU_PD5: power-domain-cpu5 {
369 #power-domain-cells =
370 power-domains = <&CLUS
371 };
372
373 CPU_PD6: power-domain-cpu6 {
374 #power-domain-cells =
375 power-domains = <&CLUS
376 };
377
378 CPU_PD7: power-domain-cpu7 {
379 #power-domain-cells =
380 power-domains = <&CLUS
381 };
382
383 CPU_PD8: power-domain-cpu8 {
384 #power-domain-cells =
385 power-domains = <&CLUS
386 };
387
388 CPU_PD9: power-domain-cpu9 {
389 #power-domain-cells =
390 power-domains = <&CLUS
391 };
392
393 CPU_PD10: power-domain-cpu10 {
394 #power-domain-cells =
395 power-domains = <&CLUS
396 };
397
398 CPU_PD11: power-domain-cpu11 {
399 #power-domain-cells =
400 power-domains = <&CLUS
401 };
402
403 CLUSTER_PD0: power-domain-cpu-
404 #power-domain-cells =
405 domain-idle-states = <
406 power-domains = <&SYST
407 };
408
409 CLUSTER_PD1: power-domain-cpu-
410 #power-domain-cells =
411 domain-idle-states = <
412 power-domains = <&SYST
413 };
414
415 CLUSTER_PD2: power-domain-cpu-
416 #power-domain-cells =
417 domain-idle-states = <
418 power-domains = <&SYST
419 };
420
421 SYSTEM_PD: power-domain-system
422 #power-domain-cells =
423 /* TODO: system-wide i
424 };
425 };
426
427 reserved-memory {
428 #address-cells = <2>;
429 #size-cells = <2>;
430 ranges;
431
432 gunyah_hyp_mem: gunyah-hyp@800
433 reg = <0x0 0x80000000
434 no-map;
435 };
436
437 hyp_elf_package_mem: hyp-elf-p
438 reg = <0x0 0x80800000
439 no-map;
440 };
441
442 ncc_mem: ncc@80a00000 {
443 reg = <0x0 0x80a00000
444 no-map;
445 };
446
447 cpucp_log_mem: cpucp-log@80e00
448 reg = <0x0 0x80e00000
449 no-map;
450 };
451
452 cpucp_mem: cpucp@80e40000 {
453 reg = <0x0 0x80e40000
454 no-map;
455 };
456
457 reserved-region@81380000 {
458 reg = <0x0 0x81380000
459 no-map;
460 };
461
462 tags_mem: tags-region@81400000
463 reg = <0x0 0x81400000
464 no-map;
465 };
466
467 xbl_dtlog_mem: xbl-dtlog@81a00
468 reg = <0x0 0x81a00000
469 no-map;
470 };
471
472 xbl_ramdump_mem: xbl-ramdump@8
473 reg = <0x0 0x81a40000
474 no-map;
475 };
476
477 aop_image_mem: aop-image@81c00
478 reg = <0x0 0x81c00000
479 no-map;
480 };
481
482 aop_cmd_db_mem: aop-cmd-db@81c
483 compatible = "qcom,cmd
484 reg = <0x0 0x81c60000
485 no-map;
486 };
487
488 aop_config_mem: aop-config@81c
489 reg = <0x0 0x81c80000
490 no-map;
491 };
492
493 tme_crash_dump_mem: tme-crash-
494 reg = <0x0 0x81ca0000
495 no-map;
496 };
497
498 tme_log_mem: tme-log@81ce0000
499 reg = <0x0 0x81ce0000
500 no-map;
501 };
502
503 uefi_log_mem: uefi-log@81ce400
504 reg = <0x0 0x81ce4000
505 no-map;
506 };
507
508 secdata_apss_mem: secdata-apss
509 reg = <0x0 0x81cff000
510 no-map;
511 };
512
513 pdp_ns_shared_mem: pdp-ns-shar
514 reg = <0x0 0x81e00000
515 no-map;
516 };
517
518 gpu_prr_mem: gpu-prr@81f00000
519 reg = <0x0 0x81f00000
520 no-map;
521 };
522
523 tpm_control_mem: tpm-control@8
524 reg = <0x0 0x81f10000
525 no-map;
526 };
527
528 usb_ucsi_shared_mem: usb-ucsi-
529 reg = <0x0 0x81f20000
530 no-map;
531 };
532
533 pld_pep_mem: pld-pep@81f30000
534 reg = <0x0 0x81f30000
535 no-map;
536 };
537
538 pld_gmu_mem: pld-gmu@81f36000
539 reg = <0x0 0x81f36000
540 no-map;
541 };
542
543 pld_pdp_mem: pld-pdp@81f37000
544 reg = <0x0 0x81f37000
545 no-map;
546 };
547
548 tz_stat_mem: tz-stat@82700000
549 reg = <0x0 0x82700000
550 no-map;
551 };
552
553 xbl_tmp_buffer_mem: xbl-tmp-bu
554 reg = <0x0 0x82800000
555 no-map;
556 };
557
558 adsp_rpc_remote_heap_mem: adsp
559 reg = <0x0 0x84b00000
560 no-map;
561 };
562
563 spu_secure_shared_memory_mem:
564 reg = <0x0 0x85300000
565 no-map;
566 };
567
568 adsp_boot_dtb_mem: adsp-boot-d
569 reg = <0x0 0x866c0000
570 no-map;
571 };
572
573 spss_region_mem: spss-region@8
574 reg = <0x0 0x86700000
575 no-map;
576 };
577
578 adsp_boot_mem: adsp-boot@86b00
579 reg = <0x0 0x86b00000
580 no-map;
581 };
582
583 video_mem: video@87700000 {
584 reg = <0x0 0x87700000
585 no-map;
586 };
587
588 adspslpi_mem: adspslpi@87e0000
589 reg = <0x0 0x87e00000
590 no-map;
591 };
592
593 q6_adsp_dtb_mem: q6-adsp-dtb@8
594 reg = <0x0 0x8b800000
595 no-map;
596 };
597
598 cdsp_mem: cdsp@8b900000 {
599 reg = <0x0 0x8b900000
600 no-map;
601 };
602
603 q6_cdsp_dtb_mem: q6-cdsp-dtb@8
604 reg = <0x0 0x8d900000
605 no-map;
606 };
607
608 gpu_microcode_mem: gpu-microco
609 reg = <0x0 0x8d9fe000
610 no-map;
611 };
612
613 cvp_mem: cvp@8da00000 {
614 reg = <0x0 0x8da00000
615 no-map;
616 };
617
618 camera_mem: camera@8e100000 {
619 reg = <0x0 0x8e100000
620 no-map;
621 };
622
623 av1_encoder_mem: av1-encoder@8
624 reg = <0x0 0x8e900000
625 no-map;
626 };
627
628 reserved-region@8f000000 {
629 reg = <0x0 0x8f000000
630 no-map;
631 };
632
633 wpss_mem: wpss@8fa00000 {
634 reg = <0x0 0x8fa00000
635 no-map;
636 };
637
638 q6_wpss_dtb_mem: q6-wpss-dtb@9
639 reg = <0x0 0x91300000
640 no-map;
641 };
642
643 xbl_sc_mem: xbl-sc@d8000000 {
644 reg = <0x0 0xd8000000
645 no-map;
646 };
647
648 reserved-region@d8040000 {
649 reg = <0x0 0xd8040000
650 no-map;
651 };
652
653 qtee_mem: qtee@d80e0000 {
654 reg = <0x0 0xd80e0000
655 no-map;
656 };
657
658 ta_mem: ta@d8600000 {
659 reg = <0x0 0xd8600000
660 no-map;
661 };
662
663 tags_mem1: tags@e1000000 {
664 reg = <0x0 0xe1000000
665 no-map;
666 };
667
668 llcc_lpi_mem: llcc-lpi@ff80000
669 reg = <0x0 0xff800000
670 no-map;
671 };
672
673 smem_mem: smem@ffe00000 {
674 compatible = "qcom,sme
675 reg = <0x0 0xffe00000
676 hwlocks = <&tcsr_mutex
677 no-map;
678 };
679 };
680
681 smp2p-adsp {
682 compatible = "qcom,smp2p";
683
684 interrupts-extended = <&ipcc I
685 I
686 I
687
688 mboxes = <&ipcc IPCC_CLIENT_LP
689 IPCC_MPROC_SIG
690
691 qcom,smem = <443>, <429>;
692 qcom,local-pid = <0>;
693 qcom,remote-pid = <2>;
694
695 smp2p_adsp_out: master-kernel
696 qcom,entry-name = "mas
697 #qcom,smem-state-cells
698 };
699
700 smp2p_adsp_in: slave-kernel {
701 qcom,entry-name = "sla
702 interrupt-controller;
703 #interrupt-cells = <2>
704 };
705 };
706
707 smp2p-cdsp {
708 compatible = "qcom,smp2p";
709
710 interrupts-extended = <&ipcc I
711 I
712 I
713
714 mboxes = <&ipcc IPCC_CLIENT_CD
715 IPCC_MPROC_SIG
716
717 qcom,smem = <94>, <432>;
718 qcom,local-pid = <0>;
719 qcom,remote-pid = <5>;
720
721 smp2p_cdsp_out: master-kernel
722 qcom,entry-name = "mas
723 #qcom,smem-state-cells
724 };
725
726 smp2p_cdsp_in: slave-kernel {
727 qcom,entry-name = "sla
728 interrupt-controller;
729 #interrupt-cells = <2>
730 };
731 };
732
733 soc: soc@0 {
734 compatible = "simple-bus";
735
736 #address-cells = <2>;
737 #size-cells = <2>;
738 dma-ranges = <0 0 0 0 0x10 0>;
739 ranges = <0 0 0 0 0x10 0>;
740
741 gcc: clock-controller@100000 {
742 compatible = "qcom,x1e
743 reg = <0 0x00100000 0
744
745 clocks = <&bi_tcxo_div
746 <&sleep_clk>,
747 <0>,
748 <&pcie4_phy>,
749 <&pcie5_phy>,
750 <&pcie6a_phy>
751 <0>,
752 <&usb_1_ss0_q
753 <&usb_1_ss1_q
754 <&usb_1_ss2_q
755
756 power-domains = <&rpmh
757 #clock-cells = <1>;
758 #reset-cells = <1>;
759 #power-domain-cells =
760 };
761
762 ipcc: mailbox@408000 {
763 compatible = "qcom,x1e
764 reg = <0 0x00408000 0
765
766 interrupts = <GIC_SPI
767 interrupt-controller;
768 #interrupt-cells = <3>
769
770 #mbox-cells = <2>;
771 };
772
773 gpi_dma2: dma-controller@80000
774 compatible = "qcom,x1e
775 reg = <0 0x00800000 0
776
777 interrupts = <GIC_SPI
778 <GIC_SPI
779 <GIC_SPI
780 <GIC_SPI
781 <GIC_SPI
782 <GIC_SPI
783 <GIC_SPI
784 <GIC_SPI
785 <GIC_SPI
786 <GIC_SPI
787 <GIC_SPI
788 <GIC_SPI
789
790 dma-channels = <12>;
791 dma-channel-mask = <0x
792 #dma-cells = <3>;
793
794 iommus = <&apps_smmu 0
795
796 status = "disabled";
797 };
798
799 qupv3_2: geniqup@8c0000 {
800 compatible = "qcom,gen
801 reg = <0 0x008c0000 0
802
803 clocks = <&gcc GCC_QUP
804 <&gcc GCC_QUP
805 clock-names = "m-ahb",
806 "s-ahb";
807
808 iommus = <&apps_smmu 0
809
810 #address-cells = <2>;
811 #size-cells = <2>;
812 ranges;
813
814 status = "disabled";
815
816 i2c16: i2c@880000 {
817 compatible = "
818 reg = <0 0x008
819
820 interrupts = <
821
822 clocks = <&gcc
823 clock-names =
824
825 interconnects
826
827
828
829
830
831 interconnect-n
832
833
834
835 dmas = <&gpi_d
836 <&gpi_d
837 dma-names = "t
838 "r
839
840 pinctrl-0 = <&
841 pinctrl-names
842
843 #address-cells
844 #size-cells =
845
846 status = "disa
847 };
848
849 spi16: spi@880000 {
850 compatible = "
851 reg = <0 0x008
852
853 interrupts = <
854
855 clocks = <&gcc
856 clock-names =
857
858 interconnects
859
860
861
862
863
864 interconnect-n
865
866
867
868 dmas = <&gpi_d
869 <&gpi_d
870 dma-names = "t
871 "r
872
873 pinctrl-0 = <&
874 pinctrl-names
875
876 #address-cells
877 #size-cells =
878
879 status = "disa
880 };
881
882 i2c17: i2c@884000 {
883 compatible = "
884 reg = <0 0x008
885
886 interrupts = <
887
888 clocks = <&gcc
889 clock-names =
890
891 interconnects
892
893
894
895
896
897 interconnect-n
898
899
900
901 dmas = <&gpi_d
902 <&gpi_d
903 dma-names = "t
904 "r
905
906 pinctrl-0 = <&
907 pinctrl-names
908
909 #address-cells
910 #size-cells =
911
912 status = "disa
913 };
914
915 spi17: spi@884000 {
916 compatible = "
917 reg = <0 0x008
918
919 interrupts = <
920
921 clocks = <&gcc
922 clock-names =
923
924 interconnects
925
926
927
928
929
930 interconnect-n
931
932
933
934 dmas = <&gpi_d
935 <&gpi_d
936 dma-names = "t
937 "r
938
939 pinctrl-0 = <&
940 pinctrl-names
941
942 #address-cells
943 #size-cells =
944
945 status = "disa
946 };
947
948 i2c18: i2c@888000 {
949 compatible = "
950 reg = <0 0x008
951
952 interrupts = <
953
954 clocks = <&gcc
955 clock-names =
956
957 interconnects
958
959
960
961
962
963 interconnect-n
964
965
966
967 dmas = <&gpi_d
968 <&gpi_d
969 dma-names = "t
970 "r
971
972 pinctrl-0 = <&
973 pinctrl-names
974
975 #address-cells
976 #size-cells =
977
978 status = "disa
979 };
980
981 spi18: spi@888000 {
982 compatible = "
983 reg = <0 0x008
984
985 interrupts = <
986
987 clocks = <&gcc
988 clock-names =
989
990 interconnects
991
992
993
994
995
996 interconnect-n
997
998
999
1000 dmas = <&gpi_
1001 <&gpi_
1002 dma-names = "
1003 "
1004
1005 pinctrl-0 = <
1006 pinctrl-names
1007
1008 #address-cell
1009 #size-cells =
1010
1011 status = "dis
1012 };
1013
1014 i2c19: i2c@88c000 {
1015 compatible =
1016 reg = <0 0x00
1017
1018 interrupts =
1019
1020 clocks = <&gc
1021 clock-names =
1022
1023 interconnects
1024
1025
1026
1027
1028
1029 interconnect-
1030
1031
1032
1033 dmas = <&gpi_
1034 <&gpi_
1035 dma-names = "
1036 "
1037
1038 pinctrl-0 = <
1039 pinctrl-names
1040
1041 #address-cell
1042 #size-cells =
1043
1044 status = "dis
1045 };
1046
1047 spi19: spi@88c000 {
1048 compatible =
1049 reg = <0 0x00
1050
1051 interrupts =
1052
1053 clocks = <&gc
1054 clock-names =
1055
1056 interconnects
1057
1058
1059
1060
1061
1062 interconnect-
1063
1064
1065
1066 dmas = <&gpi_
1067 <&gpi_
1068 dma-names = "
1069 "
1070
1071 pinctrl-0 = <
1072 pinctrl-names
1073
1074 #address-cell
1075 #size-cells =
1076
1077 status = "dis
1078 };
1079
1080 i2c20: i2c@890000 {
1081 compatible =
1082 reg = <0 0x00
1083
1084 interrupts =
1085
1086 clocks = <&gc
1087 clock-names =
1088
1089 interconnects
1090
1091
1092
1093
1094
1095 interconnect-
1096
1097
1098
1099 dmas = <&gpi_
1100 <&gpi_
1101 dma-names = "
1102 "
1103
1104 pinctrl-0 = <
1105 pinctrl-names
1106
1107 #address-cell
1108 #size-cells =
1109
1110 status = "dis
1111 };
1112
1113 spi20: spi@890000 {
1114 compatible =
1115 reg = <0 0x00
1116
1117 interrupts =
1118
1119 clocks = <&gc
1120 clock-names =
1121
1122 interconnects
1123
1124
1125
1126
1127
1128 interconnect-
1129
1130
1131
1132 dmas = <&gpi_
1133 <&gpi_
1134 dma-names = "
1135 "
1136
1137 pinctrl-0 = <
1138 pinctrl-names
1139
1140 #address-cell
1141 #size-cells =
1142
1143 status = "dis
1144 };
1145
1146 i2c21: i2c@894000 {
1147 compatible =
1148 reg = <0 0x00
1149
1150 interrupts =
1151
1152 clocks = <&gc
1153 clock-names =
1154
1155 interconnects
1156
1157
1158
1159
1160
1161 interconnect-
1162
1163
1164
1165 dmas = <&gpi_
1166 <&gpi_
1167 dma-names = "
1168 "
1169
1170 pinctrl-0 = <
1171 pinctrl-names
1172
1173 #address-cell
1174 #size-cells =
1175
1176 status = "dis
1177 };
1178
1179 spi21: spi@894000 {
1180 compatible =
1181 reg = <0 0x00
1182
1183 interrupts =
1184
1185 clocks = <&gc
1186 clock-names =
1187
1188 interconnects
1189
1190
1191
1192
1193
1194 interconnect-
1195
1196
1197
1198 dmas = <&gpi_
1199 <&gpi_
1200 dma-names = "
1201 "
1202
1203 pinctrl-0 = <
1204 pinctrl-names
1205
1206 #address-cell
1207 #size-cells =
1208
1209 status = "dis
1210 };
1211
1212 uart21: serial@894000
1213 compatible =
1214 reg = <0 0x00
1215
1216 interrupts =
1217
1218 clocks = <&gc
1219 clock-names =
1220
1221 interconnects
1222
1223
1224
1225 interconnect-
1226
1227
1228 pinctrl-0 = <
1229 pinctrl-names
1230
1231 status = "dis
1232 };
1233
1234 i2c22: i2c@898000 {
1235 compatible =
1236 reg = <0 0x00
1237
1238 interrupts =
1239
1240 clocks = <&gc
1241 clock-names =
1242
1243 interconnects
1244
1245
1246
1247
1248
1249 interconnect-
1250
1251
1252
1253 dmas = <&gpi_
1254 <&gpi_
1255 dma-names = "
1256 "
1257
1258 pinctrl-0 = <
1259 pinctrl-names
1260
1261 #address-cell
1262 #size-cells =
1263
1264 status = "dis
1265 };
1266
1267 spi22: spi@898000 {
1268 compatible =
1269 reg = <0 0x00
1270
1271 interrupts =
1272
1273 clocks = <&gc
1274 clock-names =
1275
1276 interconnects
1277
1278
1279
1280
1281
1282 interconnect-
1283
1284
1285
1286 dmas = <&gpi_
1287 <&gpi_
1288 dma-names = "
1289 "
1290
1291 pinctrl-0 = <
1292 pinctrl-names
1293
1294 #address-cell
1295 #size-cells =
1296
1297 status = "dis
1298 };
1299
1300 i2c23: i2c@89c000 {
1301 compatible =
1302 reg = <0 0x00
1303
1304 interrupts =
1305
1306 clocks = <&gc
1307 clock-names =
1308
1309 interconnects
1310
1311
1312
1313
1314
1315 interconnect-
1316
1317
1318
1319 dmas = <&gpi_
1320 <&gpi_
1321 dma-names = "
1322 "
1323
1324 pinctrl-0 = <
1325 pinctrl-names
1326
1327 #address-cell
1328 #size-cells =
1329
1330 status = "dis
1331 };
1332
1333 spi23: spi@89c000 {
1334 compatible =
1335 reg = <0 0x00
1336
1337 interrupts =
1338
1339 clocks = <&gc
1340 clock-names =
1341
1342 interconnects
1343
1344
1345
1346
1347
1348 interconnect-
1349
1350
1351
1352 dmas = <&gpi_
1353 <&gpi_
1354 dma-names = "
1355 "
1356
1357 pinctrl-0 = <
1358 pinctrl-names
1359
1360 #address-cell
1361 #size-cells =
1362
1363 status = "dis
1364 };
1365 };
1366
1367 gpi_dma1: dma-controller@a000
1368 compatible = "qcom,x1
1369 reg = <0 0x00a00000 0
1370
1371 interrupts = <GIC_SPI
1372 <GIC_SPI
1373 <GIC_SPI
1374 <GIC_SPI
1375 <GIC_SPI
1376 <GIC_SPI
1377 <GIC_SPI
1378 <GIC_SPI
1379 <GIC_SPI
1380 <GIC_SPI
1381 <GIC_SPI
1382 <GIC_SPI
1383
1384 dma-channels = <12>;
1385 dma-channel-mask = <0
1386 #dma-cells = <3>;
1387
1388 iommus = <&apps_smmu
1389
1390 status = "disabled";
1391 };
1392
1393 qupv3_1: geniqup@ac0000 {
1394 compatible = "qcom,ge
1395 reg = <0 0x00ac0000 0
1396
1397 clocks = <&gcc GCC_QU
1398 <&gcc GCC_QU
1399 clock-names = "m-ahb"
1400 "s-ahb"
1401
1402 iommus = <&apps_smmu
1403
1404 #address-cells = <2>;
1405 #size-cells = <2>;
1406 ranges;
1407
1408 status = "disabled";
1409
1410 i2c8: i2c@a80000 {
1411 compatible =
1412 reg = <0 0x00
1413
1414 interrupts =
1415
1416 clocks = <&gc
1417 clock-names =
1418
1419 interconnects
1420
1421
1422
1423
1424
1425 interconnect-
1426
1427
1428
1429 dmas = <&gpi_
1430 <&gpi_
1431 dma-names = "
1432 "
1433
1434 pinctrl-0 = <
1435 pinctrl-names
1436
1437 #address-cell
1438 #size-cells =
1439
1440 status = "dis
1441 };
1442
1443 spi8: spi@a80000 {
1444 compatible =
1445 reg = <0 0x00
1446
1447 interrupts =
1448
1449 clocks = <&gc
1450 clock-names =
1451
1452 interconnects
1453
1454
1455
1456
1457
1458 interconnect-
1459
1460
1461
1462 dmas = <&gpi_
1463 <&gpi_
1464 dma-names = "
1465 "
1466
1467 pinctrl-0 = <
1468 pinctrl-names
1469
1470 #address-cell
1471 #size-cells =
1472
1473 status = "dis
1474 };
1475
1476 i2c9: i2c@a84000 {
1477 compatible =
1478 reg = <0 0x00
1479
1480 interrupts =
1481
1482 clocks = <&gc
1483 clock-names =
1484
1485 interconnects
1486
1487
1488
1489
1490
1491 interconnect-
1492
1493
1494
1495 dmas = <&gpi_
1496 <&gpi_
1497 dma-names = "
1498 "
1499
1500 pinctrl-0 = <
1501 pinctrl-names
1502
1503 #address-cell
1504 #size-cells =
1505
1506 status = "dis
1507 };
1508
1509 spi9: spi@a84000 {
1510 compatible =
1511 reg = <0 0x00
1512
1513 interrupts =
1514
1515 clocks = <&gc
1516 clock-names =
1517
1518 interconnects
1519
1520
1521
1522
1523
1524 interconnect-
1525
1526
1527
1528 dmas = <&gpi_
1529 <&gpi_
1530 dma-names = "
1531 "
1532
1533 pinctrl-0 = <
1534 pinctrl-names
1535
1536 #address-cell
1537 #size-cells =
1538
1539 status = "dis
1540 };
1541
1542 i2c10: i2c@a88000 {
1543 compatible =
1544 reg = <0 0x00
1545
1546 interrupts =
1547
1548 clocks = <&gc
1549 clock-names =
1550
1551 interconnects
1552
1553
1554
1555
1556
1557 interconnect-
1558
1559
1560
1561 dmas = <&gpi_
1562 <&gpi_
1563 dma-names = "
1564 "
1565
1566 pinctrl-0 = <
1567 pinctrl-names
1568
1569 #address-cell
1570 #size-cells =
1571
1572 status = "dis
1573 };
1574
1575 spi10: spi@a88000 {
1576 compatible =
1577 reg = <0 0x00
1578
1579 interrupts =
1580
1581 clocks = <&gc
1582 clock-names =
1583
1584 interconnects
1585
1586
1587
1588
1589
1590 interconnect-
1591
1592
1593
1594 dmas = <&gpi_
1595 <&gpi_
1596 dma-names = "
1597 "
1598
1599 pinctrl-0 = <
1600 pinctrl-names
1601
1602 #address-cell
1603 #size-cells =
1604
1605 status = "dis
1606 };
1607
1608 i2c11: i2c@a8c000 {
1609 compatible =
1610 reg = <0 0x00
1611
1612 interrupts =
1613
1614 clocks = <&gc
1615 clock-names =
1616
1617 interconnects
1618
1619
1620
1621
1622
1623 interconnect-
1624
1625
1626
1627 dmas = <&gpi_
1628 <&gpi_
1629 dma-names = "
1630 "
1631
1632 pinctrl-0 = <
1633 pinctrl-names
1634
1635 #address-cell
1636 #size-cells =
1637
1638 status = "dis
1639 };
1640
1641 spi11: spi@a8c000 {
1642 compatible =
1643 reg = <0 0x00
1644
1645 interrupts =
1646
1647 clocks = <&gc
1648 clock-names =
1649
1650 interconnects
1651
1652
1653
1654
1655
1656 interconnect-
1657
1658
1659
1660 dmas = <&gpi_
1661 <&gpi_
1662 dma-names = "
1663 "
1664
1665 pinctrl-0 = <
1666 pinctrl-names
1667
1668 #address-cell
1669 #size-cells =
1670
1671 status = "dis
1672 };
1673
1674 i2c12: i2c@a90000 {
1675 compatible =
1676 reg = <0 0x00
1677
1678 interrupts =
1679
1680 clocks = <&gc
1681 clock-names =
1682
1683 interconnects
1684
1685
1686
1687
1688
1689 interconnect-
1690
1691
1692
1693 dmas = <&gpi_
1694 <&gpi_
1695 dma-names = "
1696 "
1697
1698 pinctrl-0 = <
1699 pinctrl-names
1700
1701 #address-cell
1702 #size-cells =
1703
1704 status = "dis
1705 };
1706
1707 spi12: spi@a90000 {
1708 compatible =
1709 reg = <0 0x00
1710
1711 interrupts =
1712
1713 clocks = <&gc
1714 clock-names =
1715
1716 interconnects
1717
1718
1719
1720
1721
1722 interconnect-
1723
1724
1725
1726 dmas = <&gpi_
1727 <&gpi_
1728 dma-names = "
1729 "
1730
1731 pinctrl-0 = <
1732 pinctrl-names
1733
1734 #address-cell
1735 #size-cells =
1736
1737 status = "dis
1738 };
1739
1740 i2c13: i2c@a94000 {
1741 compatible =
1742 reg = <0 0x00
1743
1744 interrupts =
1745
1746 clocks = <&gc
1747 clock-names =
1748
1749 interconnects
1750
1751
1752
1753
1754
1755 interconnect-
1756
1757
1758
1759 dmas = <&gpi_
1760 <&gpi_
1761 dma-names = "
1762 "
1763
1764 pinctrl-0 = <
1765 pinctrl-names
1766
1767 #address-cell
1768 #size-cells =
1769
1770 status = "dis
1771 };
1772
1773 spi13: spi@a94000 {
1774 compatible =
1775 reg = <0 0x00
1776
1777 interrupts =
1778
1779 clocks = <&gc
1780 clock-names =
1781
1782 interconnects
1783
1784
1785
1786
1787
1788 interconnect-
1789
1790
1791
1792 dmas = <&gpi_
1793 <&gpi_
1794 dma-names = "
1795 "
1796
1797 pinctrl-0 = <
1798 pinctrl-names
1799
1800 #address-cell
1801 #size-cells =
1802
1803 status = "dis
1804 };
1805
1806 i2c14: i2c@a98000 {
1807 compatible =
1808 reg = <0 0x00
1809
1810 interrupts =
1811
1812 clocks = <&gc
1813 clock-names =
1814
1815 interconnects
1816
1817
1818
1819
1820
1821 interconnect-
1822
1823
1824
1825 dmas = <&gpi_
1826 <&gpi_
1827 dma-names = "
1828 "
1829
1830 pinctrl-0 = <
1831 pinctrl-names
1832
1833 #address-cell
1834 #size-cells =
1835
1836 status = "dis
1837 };
1838
1839 spi14: spi@a98000 {
1840 compatible =
1841 reg = <0 0x00
1842
1843 interrupts =
1844
1845 clocks = <&gc
1846 clock-names =
1847
1848 interconnects
1849
1850
1851
1852
1853
1854 interconnect-
1855
1856
1857
1858 dmas = <&gpi_
1859 <&gpi_
1860 dma-names = "
1861 "
1862
1863 pinctrl-0 = <
1864 pinctrl-names
1865
1866 #address-cell
1867 #size-cells =
1868
1869 status = "dis
1870 };
1871
1872 i2c15: i2c@a9c000 {
1873 compatible =
1874 reg = <0 0x00
1875
1876 interrupts =
1877
1878 clocks = <&gc
1879 clock-names =
1880
1881 interconnects
1882
1883
1884
1885
1886
1887 interconnect-
1888
1889
1890
1891 dmas = <&gpi_
1892 <&gpi_
1893 dma-names = "
1894 "
1895
1896 pinctrl-0 = <
1897 pinctrl-names
1898
1899 #address-cell
1900 #size-cells =
1901
1902 status = "dis
1903 };
1904
1905 spi15: spi@a9c000 {
1906 compatible =
1907 reg = <0 0x00
1908
1909 interrupts =
1910
1911 clocks = <&gc
1912 clock-names =
1913
1914 interconnects
1915
1916
1917
1918
1919
1920 interconnect-
1921
1922
1923
1924 dmas = <&gpi_
1925 <&gpi_
1926 dma-names = "
1927 "
1928
1929 pinctrl-0 = <
1930 pinctrl-names
1931
1932 #address-cell
1933 #size-cells =
1934
1935 status = "dis
1936 };
1937 };
1938
1939 gpi_dma0: dma-controller@b000
1940 compatible = "qcom,x1
1941 reg = <0 0x00b00000 0
1942
1943 interrupts = <GIC_SPI
1944 <GIC_SPI
1945 <GIC_SPI
1946 <GIC_SPI
1947 <GIC_SPI
1948 <GIC_SPI
1949 <GIC_SPI
1950 <GIC_SPI
1951 <GIC_SPI
1952 <GIC_SPI
1953 <GIC_SPI
1954 <GIC_SPI
1955
1956 dma-channels = <12>;
1957 dma-channel-mask = <0
1958 #dma-cells = <3>;
1959
1960 iommus = <&apps_smmu
1961
1962 status = "disabled";
1963 };
1964
1965 qupv3_0: geniqup@bc0000 {
1966 compatible = "qcom,ge
1967 reg = <0 0x00bc0000 0
1968
1969 clocks = <&gcc GCC_QU
1970 <&gcc GCC_QU
1971 clock-names = "m-ahb"
1972 "s-ahb"
1973
1974 iommus = <&apps_smmu
1975 #address-cells = <2>;
1976 #size-cells = <2>;
1977 ranges;
1978
1979 status = "disabled";
1980
1981 i2c0: i2c@b80000 {
1982 compatible =
1983 reg = <0 0x00
1984
1985 interrupts =
1986
1987 clocks = <&gc
1988 clock-names =
1989
1990 interconnects
1991
1992
1993
1994
1995
1996 interconnect-
1997
1998
1999
2000 dmas = <&gpi_
2001 <&gpi_
2002 dma-names = "
2003 "
2004
2005 pinctrl-0 = <
2006 pinctrl-names
2007
2008 #address-cell
2009 #size-cells =
2010
2011 status = "dis
2012 };
2013
2014 spi0: spi@b80000 {
2015 compatible =
2016 reg = <0 0x00
2017
2018 interrupts =
2019
2020 clocks = <&gc
2021 clock-names =
2022
2023 interconnects
2024
2025
2026
2027
2028
2029 interconnect-
2030
2031
2032
2033 dmas = <&gpi_
2034 <&gpi_
2035 dma-names = "
2036 "
2037
2038 pinctrl-0 = <
2039 pinctrl-names
2040
2041 #address-cell
2042 #size-cells =
2043
2044 status = "dis
2045 };
2046
2047 i2c1: i2c@b84000 {
2048 compatible =
2049 reg = <0 0x00
2050
2051 interrupts =
2052
2053 clocks = <&gc
2054 clock-names =
2055
2056 interconnects
2057
2058
2059
2060
2061
2062 interconnect-
2063
2064
2065
2066 dmas = <&gpi_
2067 <&gpi_
2068 dma-names = "
2069 "
2070
2071 pinctrl-0 = <
2072 pinctrl-names
2073
2074 #address-cell
2075 #size-cells =
2076
2077 status = "dis
2078 };
2079
2080 spi1: spi@b84000 {
2081 compatible =
2082 reg = <0 0x00
2083
2084 interrupts =
2085
2086 clocks = <&gc
2087 clock-names =
2088
2089 interconnects
2090
2091
2092
2093
2094
2095 interconnect-
2096
2097
2098
2099 dmas = <&gpi_
2100 <&gpi_
2101 dma-names = "
2102 "
2103
2104 pinctrl-0 = <
2105 pinctrl-names
2106
2107 #address-cell
2108 #size-cells =
2109
2110 status = "dis
2111 };
2112
2113 i2c2: i2c@b88000 {
2114 compatible =
2115 reg = <0 0x00
2116
2117 interrupts =
2118
2119 clocks = <&gc
2120 clock-names =
2121
2122 interconnects
2123
2124
2125
2126
2127
2128 interconnect-
2129
2130
2131
2132 dmas = <&gpi_
2133 <&gpi_
2134 dma-names = "
2135 "
2136
2137 pinctrl-0 = <
2138 pinctrl-names
2139
2140 #address-cell
2141 #size-cells =
2142
2143 status = "dis
2144 };
2145
2146 uart2: serial@b88000
2147 compatible =
2148 reg = <0 0x00
2149
2150 interrupts =
2151
2152 clocks = <&gc
2153 clock-names =
2154
2155 interconnects
2156
2157
2158
2159 interconnect-
2160
2161
2162 pinctrl-0 = <
2163 pinctrl-names
2164
2165 status = "dis
2166 };
2167
2168 spi2: spi@b88000 {
2169 compatible =
2170 reg = <0 0x00
2171
2172 interrupts =
2173
2174 clocks = <&gc
2175 clock-names =
2176
2177 interconnects
2178
2179
2180
2181
2182
2183 interconnect-
2184
2185
2186
2187 dmas = <&gpi_
2188 <&gpi_
2189 dma-names = "
2190 "
2191
2192 pinctrl-0 = <
2193 pinctrl-names
2194
2195 #address-cell
2196 #size-cells =
2197
2198 status = "dis
2199 };
2200
2201 i2c3: i2c@b8c000 {
2202 compatible =
2203 reg = <0 0x00
2204
2205 interrupts =
2206
2207 clocks = <&gc
2208 clock-names =
2209
2210 interconnects
2211
2212
2213
2214
2215
2216 interconnect-
2217
2218
2219
2220 dmas = <&gpi_
2221 <&gpi_
2222 dma-names = "
2223 "
2224
2225 pinctrl-0 = <
2226 pinctrl-names
2227
2228 #address-cell
2229 #size-cells =
2230
2231 status = "dis
2232 };
2233
2234 spi3: spi@b8c000 {
2235 compatible =
2236 reg = <0 0x00
2237
2238 interrupts =
2239
2240 clocks = <&gc
2241 clock-names =
2242
2243 interconnects
2244
2245
2246
2247
2248
2249 interconnect-
2250
2251
2252
2253 dmas = <&gpi_
2254 <&gpi_
2255 dma-names = "
2256 "
2257
2258 pinctrl-0 = <
2259 pinctrl-names
2260
2261 #address-cell
2262 #size-cells =
2263
2264 status = "dis
2265 };
2266
2267 i2c4: i2c@b90000 {
2268 compatible =
2269 reg = <0 0x00
2270
2271 interrupts =
2272
2273 clocks = <&gc
2274 clock-names =
2275
2276 interconnects
2277
2278
2279
2280
2281
2282 interconnect-
2283
2284
2285
2286 dmas = <&gpi_
2287 <&gpi_
2288 dma-names = "
2289 "
2290
2291 pinctrl-0 = <
2292 pinctrl-names
2293
2294 #address-cell
2295 #size-cells =
2296
2297 status = "dis
2298 };
2299
2300 spi4: spi@b90000 {
2301 compatible =
2302 reg = <0 0x00
2303
2304 interrupts =
2305
2306 clocks = <&gc
2307 clock-names =
2308
2309 interconnects
2310
2311
2312
2313
2314
2315 interconnect-
2316
2317
2318
2319 dmas = <&gpi_
2320 <&gpi_
2321 dma-names = "
2322 "
2323
2324 pinctrl-0 = <
2325 pinctrl-names
2326
2327 #address-cell
2328 #size-cells =
2329
2330 status = "dis
2331 };
2332
2333 i2c5: i2c@b94000 {
2334 compatible =
2335 reg = <0 0x00
2336
2337 interrupts =
2338
2339 clocks = <&gc
2340 clock-names =
2341
2342 interconnects
2343
2344
2345
2346
2347
2348 interconnect-
2349
2350
2351
2352 dmas = <&gpi_
2353 <&gpi_
2354 dma-names = "
2355 "
2356
2357 pinctrl-0 = <
2358 pinctrl-names
2359
2360 #address-cell
2361 #size-cells =
2362
2363 status = "dis
2364 };
2365
2366 spi5: spi@b94000 {
2367 compatible =
2368 reg = <0 0x00
2369
2370 interrupts =
2371
2372 clocks = <&gc
2373 clock-names =
2374
2375 interconnects
2376
2377
2378
2379
2380
2381 interconnect-
2382
2383
2384
2385 dmas = <&gpi_
2386 <&gpi_
2387 dma-names = "
2388 "
2389
2390 pinctrl-0 = <
2391 pinctrl-names
2392
2393 #address-cell
2394 #size-cells =
2395
2396 status = "dis
2397 };
2398
2399 i2c6: i2c@b98000 {
2400 compatible =
2401 reg = <0 0x00
2402
2403 interrupts =
2404
2405 clocks = <&gc
2406 clock-names =
2407
2408 interconnects
2409
2410
2411
2412
2413
2414 interconnect-
2415
2416
2417
2418 dmas = <&gpi_
2419 <&gpi_
2420 dma-names = "
2421 "
2422
2423 pinctrl-0 = <
2424 pinctrl-names
2425
2426 #address-cell
2427 #size-cells =
2428
2429 status = "dis
2430 };
2431
2432 spi6: spi@b98000 {
2433 compatible =
2434 reg = <0 0x00
2435
2436 interrupts =
2437
2438 clocks = <&gc
2439 clock-names =
2440
2441 interconnects
2442
2443
2444
2445
2446
2447 interconnect-
2448
2449
2450
2451 dmas = <&gpi_
2452 <&gpi_
2453 dma-names = "
2454 "
2455
2456 pinctrl-0 = <
2457 pinctrl-names
2458
2459 #address-cell
2460 #size-cells =
2461
2462 status = "dis
2463 };
2464
2465 i2c7: i2c@b9c000 {
2466 compatible =
2467 reg = <0 0x00
2468
2469 interrupts =
2470
2471 clocks = <&gc
2472 clock-names =
2473
2474 interconnects
2475
2476
2477
2478
2479
2480 interconnect-
2481
2482
2483
2484 dmas = <&gpi_
2485 <&gpi_
2486 dma-names = "
2487 "
2488
2489 pinctrl-0 = <
2490 pinctrl-names
2491
2492 #address-cell
2493 #size-cells =
2494
2495 status = "dis
2496 };
2497
2498 spi7: spi@b9c000 {
2499 compatible =
2500 reg = <0 0x00
2501
2502 interrupts =
2503
2504 clocks = <&gc
2505 clock-names =
2506
2507 interconnects
2508
2509
2510
2511
2512
2513 interconnect-
2514
2515
2516
2517 dmas = <&gpi_
2518 <&gpi_
2519 dma-names = "
2520 "
2521
2522 pinctrl-0 = <
2523 pinctrl-names
2524
2525 #address-cell
2526 #size-cells =
2527
2528 status = "dis
2529 };
2530 };
2531
2532 tsens0: thermal-sensor@c27100
2533 compatible = "qcom,x1
2534 reg = <0 0x0c271000 0
2535 <0 0x0c222000 0
2536
2537 interrupts-extended =
2538
2539 interrupt-names = "up
2540 "cr
2541
2542 #qcom,sensors = <16>;
2543
2544 #thermal-sensor-cells
2545 };
2546
2547 tsens1: thermal-sensor@c27200
2548 compatible = "qcom,x1
2549 reg = <0 0x0c272000 0
2550 <0 0x0c223000 0
2551
2552 interrupts-extended =
2553
2554 interrupt-names = "up
2555 "cr
2556
2557 #qcom,sensors = <16>;
2558
2559 #thermal-sensor-cells
2560 };
2561
2562 tsens2: thermal-sensor@c27300
2563 compatible = "qcom,x1
2564 reg = <0 0x0c273000 0
2565 <0 0x0c224000 0
2566
2567 interrupts-extended =
2568
2569 interrupt-names = "up
2570 "cr
2571
2572 #qcom,sensors = <16>;
2573
2574 #thermal-sensor-cells
2575 };
2576
2577 tsens3: thermal-sensor@c27400
2578 compatible = "qcom,x1
2579 reg = <0 0x0c274000 0
2580 <0 0x0c225000 0
2581
2582 interrupts-extended =
2583
2584 interrupt-names = "up
2585 "cr
2586
2587 #qcom,sensors = <16>;
2588
2589 #thermal-sensor-cells
2590 };
2591
2592 usb_1_ss0_hsphy: phy@fd3000 {
2593 compatible = "qcom,x1
2594 "qcom,sm
2595 reg = <0 0x00fd3000 0
2596 #phy-cells = <0>;
2597
2598 clocks = <&tcsr TCSR_
2599 clock-names = "ref";
2600
2601 resets = <&gcc GCC_QU
2602
2603 status = "disabled";
2604 };
2605
2606 usb_1_ss0_qmpphy: phy@fd5000
2607 compatible = "qcom,x1
2608 reg = <0 0x00fd5000 0
2609
2610 clocks = <&gcc GCC_US
2611 <&rpmhcc RPM
2612 <&gcc GCC_US
2613 <&gcc GCC_US
2614 clock-names = "aux",
2615 "ref",
2616 "com_au
2617 "usb3_p
2618
2619 power-domains = <&gcc
2620
2621 resets = <&gcc GCC_US
2622 <&gcc GCC_US
2623 reset-names = "phy",
2624 "common
2625
2626 #clock-cells = <1>;
2627 #phy-cells = <1>;
2628
2629 orientation-switch;
2630
2631 status = "disabled";
2632
2633 ports {
2634 #address-cell
2635 #size-cells =
2636
2637 port@0 {
2638 reg =
2639
2640 usb_1
2641 };
2642 };
2643
2644 port@1 {
2645 reg =
2646
2647 usb_1
2648
2649 };
2650 };
2651
2652 port@2 {
2653 reg =
2654
2655 usb_1
2656
2657 };
2658 };
2659 };
2660 };
2661
2662 usb_1_ss1_hsphy: phy@fd9000 {
2663 compatible = "qcom,x1
2664 "qcom,sm
2665 reg = <0 0x00fd9000 0
2666 #phy-cells = <0>;
2667
2668 clocks = <&tcsr TCSR_
2669 clock-names = "ref";
2670
2671 resets = <&gcc GCC_QU
2672
2673 status = "disabled";
2674 };
2675
2676 usb_1_ss1_qmpphy: phy@fda000
2677 compatible = "qcom,x1
2678 reg = <0 0x00fda000 0
2679
2680 clocks = <&gcc GCC_US
2681 <&rpmhcc RPM
2682 <&gcc GCC_US
2683 <&gcc GCC_US
2684 clock-names = "aux",
2685 "ref",
2686 "com_au
2687 "usb3_p
2688
2689 power-domains = <&gcc
2690
2691 resets = <&gcc GCC_US
2692 <&gcc GCC_US
2693 reset-names = "phy",
2694 "common
2695
2696 #clock-cells = <1>;
2697 #phy-cells = <1>;
2698
2699 orientation-switch;
2700
2701 status = "disabled";
2702
2703 ports {
2704 #address-cell
2705 #size-cells =
2706
2707 port@0 {
2708 reg =
2709
2710 usb_1
2711 };
2712 };
2713
2714 port@1 {
2715 reg =
2716
2717 usb_1
2718
2719 };
2720 };
2721
2722 port@2 {
2723 reg =
2724
2725 usb_1
2726
2727 };
2728 };
2729 };
2730 };
2731
2732 usb_1_ss2_hsphy: phy@fde000 {
2733 compatible = "qcom,x1
2734 "qcom,sm
2735 reg = <0 0x00fde000 0
2736 #phy-cells = <0>;
2737
2738 clocks = <&tcsr TCSR_
2739 clock-names = "ref";
2740
2741 resets = <&gcc GCC_QU
2742
2743 status = "disabled";
2744 };
2745
2746 usb_1_ss2_qmpphy: phy@fdf000
2747 compatible = "qcom,x1
2748 reg = <0 0x00fdf000 0
2749
2750 clocks = <&gcc GCC_US
2751 <&rpmhcc RPM
2752 <&gcc GCC_US
2753 <&gcc GCC_US
2754 clock-names = "aux",
2755 "ref",
2756 "com_au
2757 "usb3_p
2758
2759 power-domains = <&gcc
2760
2761 resets = <&gcc GCC_US
2762 <&gcc GCC_US
2763 reset-names = "phy",
2764 "common
2765
2766 #clock-cells = <1>;
2767 #phy-cells = <1>;
2768
2769 orientation-switch;
2770
2771 status = "disabled";
2772
2773 ports {
2774 #address-cell
2775 #size-cells =
2776
2777 port@0 {
2778 reg =
2779
2780 usb_1
2781 };
2782 };
2783
2784 port@1 {
2785 reg =
2786
2787 usb_1
2788
2789 };
2790 };
2791
2792 port@2 {
2793 reg =
2794
2795 usb_1
2796
2797 };
2798 };
2799 };
2800 };
2801
2802 cnoc_main: interconnect@15000
2803 compatible = "qcom,x1
2804 reg = <0 0x01500000 0
2805
2806 qcom,bcm-voters = <&a
2807
2808 #interconnect-cells =
2809 };
2810
2811 config_noc: interconnect@1600
2812 compatible = "qcom,x1
2813 reg = <0 0x01600000 0
2814
2815 qcom,bcm-voters = <&a
2816
2817 #interconnect-cells =
2818 };
2819
2820 system_noc: interconnect@1680
2821 compatible = "qcom,x1
2822 reg = <0 0x01680000 0
2823
2824 qcom,bcm-voters = <&a
2825
2826 #interconnect-cells =
2827 };
2828
2829 pcie_south_anoc: interconnect
2830 compatible = "qcom,x1
2831 reg = <0 0x016c0000 0
2832
2833 qcom,bcm-voters = <&a
2834
2835 #interconnect-cells =
2836 };
2837
2838 pcie_center_anoc: interconnec
2839 compatible = "qcom,x1
2840 reg = <0 0x016d0000 0
2841
2842 qcom,bcm-voters = <&a
2843
2844 #interconnect-cells =
2845 };
2846
2847 aggre1_noc: interconnect@16e0
2848 compatible = "qcom,x1
2849 reg = <0 0x016e0000 0
2850
2851 qcom,bcm-voters = <&a
2852
2853 #interconnect-cells =
2854 };
2855
2856 aggre2_noc: interconnect@1700
2857 compatible = "qcom,x1
2858 reg = <0 0x01700000 0
2859
2860 qcom,bcm-voters = <&a
2861
2862 #interconnect-cells =
2863 };
2864
2865 pcie_north_anoc: interconnect
2866 compatible = "qcom,x1
2867 reg = <0 0x01740000 0
2868
2869 qcom,bcm-voters = <&a
2870
2871 #interconnect-cells =
2872 };
2873
2874 usb_center_anoc: interconnect
2875 compatible = "qcom,x1
2876 reg = <0 0x01750000 0
2877
2878 qcom,bcm-voters = <&a
2879
2880 #interconnect-cells =
2881 };
2882
2883 usb_north_anoc: interconnect@
2884 compatible = "qcom,x1
2885 reg = <0 0x01760000 0
2886
2887 qcom,bcm-voters = <&a
2888
2889 #interconnect-cells =
2890 };
2891
2892 usb_south_anoc: interconnect@
2893 compatible = "qcom,x1
2894 reg = <0 0x01770000 0
2895
2896 qcom,bcm-voters = <&a
2897
2898 #interconnect-cells =
2899 };
2900
2901 mmss_noc: interconnect@178000
2902 compatible = "qcom,x1
2903 reg = <0 0x01780000 0
2904
2905 qcom,bcm-voters = <&a
2906
2907 #interconnect-cells =
2908 };
2909
2910 pcie6a: pci@1bf8000 {
2911 device_type = "pci";
2912 compatible = "qcom,pc
2913 reg = <0 0x01bf8000 0
2914 <0 0x70000000 0
2915 <0 0x70000f40 0
2916 <0 0x70001000 0
2917 <0 0x70100000 0
2918 <0 0x01bfb000 0
2919 reg-names = "parf",
2920 "dbi",
2921 "elbi",
2922 "atu",
2923 "config",
2924 "mhi";
2925 #address-cells = <3>;
2926 #size-cells = <2>;
2927 ranges = <0x01000000
2928 <0x02000000
2929 bus-range = <0x00 0xf
2930
2931 dma-coherent;
2932
2933 linux,pci-domain = <6
2934 num-lanes = <4>;
2935
2936 interrupts = <GIC_SPI
2937 <GIC_SPI
2938 <GIC_SPI
2939 <GIC_SPI
2940 <GIC_SPI
2941 <GIC_SPI
2942 <GIC_SPI
2943 <GIC_SPI
2944 interrupt-names = "ms
2945 "ms
2946 "ms
2947 "ms
2948 "ms
2949 "ms
2950 "ms
2951 "ms
2952
2953 #interrupt-cells = <1
2954 interrupt-map-mask =
2955 interrupt-map = <0 0
2956 <0 0
2957 <0 0
2958 <0 0
2959
2960 clocks = <&gcc GCC_PC
2961 <&gcc GCC_PC
2962 <&gcc GCC_PC
2963 <&gcc GCC_PC
2964 <&gcc GCC_PC
2965 <&gcc GCC_CF
2966 <&gcc GCC_CN
2967 clock-names = "aux",
2968 "cfg",
2969 "bus_ma
2970 "bus_sl
2971 "slave_
2972 "noc_ag
2973 "cnoc_s
2974
2975 assigned-clocks = <&g
2976 assigned-clock-rates
2977
2978 interconnects = <&pci
2979 &mc_
2980 <&gem
2981 &cno
2982 interconnect-names =
2983
2984
2985 resets = <&gcc GCC_PC
2986 <&gcc GCC_PC
2987 reset-names = "pci",
2988 "link_d
2989
2990 power-domains = <&gcc
2991 required-opps = <&rpm
2992
2993 phys = <&pcie6a_phy>;
2994 phy-names = "pciephy"
2995
2996 status = "disabled";
2997 };
2998
2999 pcie6a_phy: phy@1bfc000 {
3000 compatible = "qcom,x1
3001 reg = <0 0x01bfc000 0
3002 <0 0x01bfe000 0
3003
3004 clocks = <&gcc GCC_PC
3005 <&gcc GCC_PC
3006 <&tcsr TCSR_
3007 <&gcc GCC_PC
3008 <&gcc GCC_PC
3009 <&gcc GCC_PC
3010 clock-names = "aux",
3011 "cfg_ah
3012 "ref",
3013 "rchng"
3014 "pipe",
3015 "pipedi
3016
3017 resets = <&gcc GCC_PC
3018 <&gcc GCC_PC
3019 reset-names = "phy",
3020 "phy_no
3021
3022 assigned-clocks = <&g
3023 assigned-clock-rates
3024
3025 power-domains = <&gcc
3026
3027 qcom,4ln-config-sel =
3028
3029 #clock-cells = <0>;
3030 clock-output-names =
3031
3032 #phy-cells = <0>;
3033
3034 status = "disabled";
3035 };
3036
3037 pcie5: pci@1c00000 {
3038 device_type = "pci";
3039 compatible = "qcom,pc
3040 reg = <0 0x01c00000 0
3041 <0 0x7e000000 0
3042 <0 0x7e000f40 0
3043 <0 0x7e001000 0
3044 <0 0x7e100000 0
3045 <0 0x01c03000 0
3046 reg-names = "parf",
3047 "dbi",
3048 "elbi",
3049 "atu",
3050 "config",
3051 "mhi";
3052 #address-cells = <3>;
3053 #size-cells = <2>;
3054 ranges = <0x01000000
3055 <0x02000000
3056 bus-range = <0x00 0xf
3057
3058 dma-coherent;
3059
3060 linux,pci-domain = <5
3061 num-lanes = <2>;
3062
3063 interrupts = <GIC_SPI
3064 <GIC_SPI
3065 <GIC_SPI
3066 <GIC_SPI
3067 <GIC_SPI
3068 <GIC_SPI
3069 <GIC_SPI
3070 <GIC_SPI
3071 interrupt-names = "ms
3072 "ms
3073 "ms
3074 "ms
3075 "ms
3076 "ms
3077 "ms
3078 "ms
3079
3080 #interrupt-cells = <1
3081 interrupt-map-mask =
3082 interrupt-map = <0 0
3083 <0 0
3084 <0 0
3085 <0 0
3086
3087 clocks = <&gcc GCC_PC
3088 <&gcc GCC_PC
3089 <&gcc GCC_PC
3090 <&gcc GCC_PC
3091 <&gcc GCC_PC
3092 <&gcc GCC_CF
3093 <&gcc GCC_CN
3094 clock-names = "aux",
3095 "cfg",
3096 "bus_ma
3097 "bus_sl
3098 "slave_
3099 "noc_ag
3100 "cnoc_s
3101
3102 assigned-clocks = <&g
3103 assigned-clock-rates
3104
3105 interconnects = <&pci
3106 &mc_
3107 <&gem
3108 &cno
3109 interconnect-names =
3110
3111
3112 resets = <&gcc GCC_PC
3113 <&gcc GCC_PC
3114 reset-names = "pci",
3115 "link_d
3116
3117 power-domains = <&gcc
3118 required-opps = <&rpm
3119
3120 phys = <&pcie5_phy>;
3121 phy-names = "pciephy"
3122
3123 status = "disabled";
3124 };
3125
3126 pcie5_phy: phy@1c06000 {
3127 compatible = "qcom,x1
3128 reg = <0 0x01c06000 0
3129
3130 clocks = <&gcc GCC_PC
3131 <&gcc GCC_PC
3132 <&tcsr TCSR_
3133 <&gcc GCC_PC
3134 <&gcc GCC_PC
3135 <&gcc GCC_PC
3136 clock-names = "aux",
3137 "cfg_ah
3138 "ref",
3139 "rchng"
3140 "pipe",
3141 "pipedi
3142
3143 resets = <&gcc GCC_PC
3144 reset-names = "phy";
3145
3146 assigned-clocks = <&g
3147 assigned-clock-rates
3148
3149 power-domains = <&gcc
3150
3151 #clock-cells = <0>;
3152 clock-output-names =
3153
3154 #phy-cells = <0>;
3155
3156 status = "disabled";
3157 };
3158
3159 pcie4: pci@1c08000 {
3160 device_type = "pci";
3161 compatible = "qcom,pc
3162 reg = <0 0x01c08000 0
3163 <0 0x7c000000 0
3164 <0 0x7c000f40 0
3165 <0 0x7c001000 0
3166 <0 0x7c100000 0
3167 <0 0x01c0b000 0
3168 reg-names = "parf",
3169 "dbi",
3170 "elbi",
3171 "atu",
3172 "config",
3173 "mhi";
3174 #address-cells = <3>;
3175 #size-cells = <2>;
3176 ranges = <0x01000000
3177 <0x02000000
3178 bus-range = <0x00 0xf
3179
3180 dma-coherent;
3181
3182 linux,pci-domain = <4
3183 num-lanes = <2>;
3184
3185 interrupts = <GIC_SPI
3186 <GIC_SPI
3187 <GIC_SPI
3188 <GIC_SPI
3189 <GIC_SPI
3190 <GIC_SPI
3191 <GIC_SPI
3192 <GIC_SPI
3193 interrupt-names = "ms
3194 "ms
3195 "ms
3196 "ms
3197 "ms
3198 "ms
3199 "ms
3200 "ms
3201
3202 #interrupt-cells = <1
3203 interrupt-map-mask =
3204 interrupt-map = <0 0
3205 <0 0
3206 <0 0
3207 <0 0
3208
3209 clocks = <&gcc GCC_PC
3210 <&gcc GCC_PC
3211 <&gcc GCC_PC
3212 <&gcc GCC_PC
3213 <&gcc GCC_PC
3214 <&gcc GCC_CF
3215 <&gcc GCC_CN
3216 clock-names = "aux",
3217 "cfg",
3218 "bus_ma
3219 "bus_sl
3220 "slave_
3221 "noc_ag
3222 "cnoc_s
3223
3224 assigned-clocks = <&g
3225 assigned-clock-rates
3226
3227 interconnects = <&pci
3228 &mc_
3229 <&gem
3230 &cno
3231 interconnect-names =
3232
3233
3234 resets = <&gcc GCC_PC
3235 <&gcc GCC_PC
3236 reset-names = "pci",
3237 "link_d
3238
3239 power-domains = <&gcc
3240 required-opps = <&rpm
3241
3242 phys = <&pcie4_phy>;
3243 phy-names = "pciephy"
3244
3245 status = "disabled";
3246
3247 pcie4_port0: pcie@0 {
3248 device_type =
3249 reg = <0x0 0x
3250 bus-range = <
3251
3252 #address-cell
3253 #size-cells =
3254 ranges;
3255 };
3256 };
3257
3258 pcie4_phy: phy@1c0e000 {
3259 compatible = "qcom,x1
3260 reg = <0 0x01c0e000 0
3261
3262 clocks = <&gcc GCC_PC
3263 <&gcc GCC_PC
3264 <&tcsr TCSR_
3265 <&gcc GCC_PC
3266 <&gcc GCC_PC
3267 <&gcc GCC_PC
3268 clock-names = "aux",
3269 "cfg_ah
3270 "ref",
3271 "rchng"
3272 "pipe",
3273 "pipedi
3274
3275 resets = <&gcc GCC_PC
3276 reset-names = "phy";
3277
3278 assigned-clocks = <&g
3279 assigned-clock-rates
3280
3281 power-domains = <&gcc
3282
3283 #clock-cells = <0>;
3284 clock-output-names =
3285
3286 #phy-cells = <0>;
3287
3288 status = "disabled";
3289 };
3290
3291 tcsr_mutex: hwlock@1f40000 {
3292 compatible = "qcom,tc
3293 reg = <0 0x01f40000 0
3294 #hwlock-cells = <1>;
3295 };
3296
3297 tcsr: clock-controller@1fc000
3298 compatible = "qcom,x1
3299 reg = <0 0x01fc0000 0
3300 clocks = <&rpmhcc RPM
3301 #clock-cells = <1>;
3302 #reset-cells = <1>;
3303 };
3304
3305 gpu: gpu@3d00000 {
3306 compatible = "qcom,ad
3307 reg = <0x0 0x03d00000
3308 <0x0 0x03d9e000
3309 <0x0 0x03d61000
3310
3311 reg-names = "kgsl_3d0
3312 "cx_mem",
3313 "cx_dbgc"
3314
3315 interrupts = <GIC_SPI
3316
3317 iommus = <&adreno_smm
3318 <&adreno_smm
3319
3320 operating-points-v2 =
3321
3322 qcom,gmu = <&gmu>;
3323 #cooling-cells = <2>;
3324
3325 interconnects = <&gem
3326 interconnect-names =
3327
3328 status = "disabled";
3329
3330 zap-shader {
3331 memory-region
3332 };
3333
3334 gpu_opp_table: opp-ta
3335 compatible =
3336
3337 opp-110000000
3338 opp-h
3339 opp-l
3340 opp-p
3341 };
3342
3343 opp-100000000
3344 opp-h
3345 opp-l
3346 opp-p
3347 };
3348
3349 opp-925000000
3350 opp-h
3351 opp-l
3352 opp-p
3353 };
3354
3355 opp-800000000
3356 opp-h
3357 opp-l
3358 opp-p
3359 };
3360
3361 opp-744000000
3362 opp-h
3363 opp-l
3364 opp-p
3365 };
3366
3367 opp-687000000
3368 opp-h
3369 opp-l
3370 opp-p
3371 };
3372
3373 opp-550000000
3374 opp-h
3375 opp-l
3376 opp-p
3377 };
3378
3379 opp-390000000
3380 opp-h
3381 opp-l
3382 opp-p
3383 };
3384
3385 opp-300000000
3386 opp-h
3387 opp-l
3388 opp-p
3389 };
3390 };
3391 };
3392
3393 gmu: gmu@3d6a000 {
3394 compatible = "qcom,ad
3395 reg = <0x0 0x03d6a000
3396 <0x0 0x03d50000
3397 <0x0 0x0b280000
3398 reg-names = "gmu", "
3399
3400 interrupts = <GIC_SPI
3401 <GIC_SPI
3402 interrupt-names = "hf
3403
3404 clocks = <&gpucc GPU_
3405 <&gpucc GPU_
3406 <&gpucc GPU_
3407 <&gcc GCC_DD
3408 <&gcc GCC_GP
3409 <&gpucc GPU_
3410 <&gpucc GPU_
3411 clock-names = "ahb",
3412 "gmu",
3413 "cxo",
3414 "axi",
3415 "memnoc
3416 "hub",
3417 "demet"
3418
3419 power-domains = <&gpu
3420 <&gpu
3421 power-domain-names =
3422
3423
3424 iommus = <&adreno_smm
3425
3426 qcom,qmp = <&aoss_qmp
3427
3428 operating-points-v2 =
3429
3430 gmu_opp_table: opp-ta
3431 compatible =
3432
3433 opp-550000000
3434 opp-h
3435 opp-l
3436 };
3437
3438 opp-220000000
3439 opp-h
3440 opp-l
3441 };
3442 };
3443 };
3444
3445 gpucc: clock-controller@3d900
3446 compatible = "qcom,x1
3447 reg = <0 0x03d90000 0
3448 clocks = <&bi_tcxo_di
3449 <&gcc GCC_GP
3450 <&gcc GCC_GP
3451 #clock-cells = <1>;
3452 #reset-cells = <1>;
3453 #power-domain-cells =
3454 };
3455
3456 adreno_smmu: iommu@3da0000 {
3457 compatible = "qcom,x1
3458 "qcom,sm
3459 reg = <0x0 0x03da0000
3460 #iommu-cells = <2>;
3461 #global-interrupts =
3462 interrupts = <GIC_SPI
3463 <GIC_SPI
3464 <GIC_SPI
3465 <GIC_SPI
3466 <GIC_SPI
3467 <GIC_SPI
3468 <GIC_SPI
3469 <GIC_SPI
3470 <GIC_SPI
3471 <GIC_SPI
3472 <GIC_SPI
3473 <GIC_SPI
3474 <GIC_SPI
3475 <GIC_SPI
3476 <GIC_SPI
3477 <GIC_SPI
3478 <GIC_SPI
3479 <GIC_SPI
3480 <GIC_SPI
3481 <GIC_SPI
3482 <GIC_SPI
3483 <GIC_SPI
3484 <GIC_SPI
3485 <GIC_SPI
3486 <GIC_SPI
3487 <GIC_SPI
3488 clocks = <&gpucc GPU_
3489 <&gcc GCC_GP
3490 <&gcc GCC_GP
3491 <&gpucc GPU_
3492 clock-names = "hlos",
3493 "bus",
3494 "iface"
3495 "ahb";
3496 power-domains = <&gpu
3497 dma-coherent;
3498 };
3499
3500 gem_noc: interconnect@2640000
3501 compatible = "qcom,x1
3502 reg = <0 0x26400000 0
3503
3504 qcom,bcm-voters = <&a
3505
3506 #interconnect-cells =
3507 };
3508
3509 nsp_noc: interconnect@320c000
3510 compatible = "qcom,x1
3511 reg = <0 0x320C0000 0
3512
3513 qcom,bcm-voters = <&a
3514
3515 #interconnect-cells =
3516 };
3517
3518 lpass_wsa2macro: codec@6aa000
3519 compatible = "qcom,x1
3520 reg = <0 0x06aa0000 0
3521 clocks = <&q6prmcc LP
3522 <&q6prmcc LP
3523 <&q6prmcc LP
3524 <&lpass_vama
3525 clock-names = "mclk",
3526 "macro"
3527 "dcodec
3528 "fsgen"
3529
3530 #clock-cells = <0>;
3531 clock-output-names =
3532 #sound-dai-cells = <1
3533 sound-name-prefix = "
3534 };
3535
3536 swr3: soundwire@6ab0000 {
3537 compatible = "qcom,so
3538 reg = <0 0x06ab0000 0
3539 clocks = <&lpass_wsa2
3540 clock-names = "iface"
3541 interrupts = <GIC_SPI
3542 label = "WSA2";
3543
3544 pinctrl-0 = <&wsa2_sw
3545 pinctrl-names = "defa
3546 resets = <&lpass_audi
3547 reset-names = "swr_au
3548
3549 qcom,din-ports = <4>;
3550 qcom,dout-ports = <9>
3551
3552 qcom,ports-sinterval
3553 qcom,ports-offset1 =
3554 qcom,ports-offset2 =
3555 qcom,ports-hstart =
3556 qcom,ports-hstop =
3557 qcom,ports-word-lengt
3558 qcom,ports-block-pack
3559 qcom,ports-block-grou
3560 qcom,ports-lane-contr
3561
3562 #address-cells = <2>;
3563 #size-cells = <0>;
3564 #sound-dai-cells = <1
3565 status = "disabled";
3566 };
3567
3568 lpass_rxmacro: codec@6ac0000
3569 compatible = "qcom,x1
3570 reg = <0 0x06ac0000 0
3571 clocks = <&q6prmcc LP
3572 <&q6prmcc LP
3573 <&q6prmcc LP
3574 <&lpass_vama
3575 clock-names = "mclk",
3576 "macro"
3577 "dcodec
3578 "fsgen"
3579
3580 #clock-cells = <0>;
3581 clock-output-names =
3582 #sound-dai-cells = <1
3583 };
3584
3585 swr1: soundwire@6ad0000 {
3586 compatible = "qcom,so
3587 reg = <0 0x06ad0000 0
3588 clocks = <&lpass_rxma
3589 clock-names = "iface"
3590 interrupts = <GIC_SPI
3591 label = "RX";
3592
3593 pinctrl-0 = <&rx_swr_
3594 pinctrl-names = "defa
3595
3596 resets = <&lpass_audi
3597 reset-names = "swr_au
3598 qcom,din-ports = <1>;
3599 qcom,dout-ports = <11
3600
3601 qcom,ports-sinterval
3602 qcom,ports-offset1 =
3603 qcom,ports-offset2 =
3604 qcom,ports-hstart =
3605 qcom,ports-hstop =
3606 qcom,ports-word-lengt
3607 qcom,ports-block-pack
3608 qcom,ports-block-grou
3609 qcom,ports-lane-contr
3610
3611 #address-cells = <2>;
3612 #size-cells = <0>;
3613 #sound-dai-cells = <1
3614 status = "disabled";
3615 };
3616
3617 lpass_txmacro: codec@6ae0000
3618 compatible = "qcom,x1
3619 reg = <0 0x06ae0000 0
3620 clocks = <&q6prmcc LP
3621 <&q6prmcc LP
3622 <&q6prmcc LP
3623 <&lpass_vama
3624 clock-names = "mclk",
3625 "macro"
3626 "dcodec
3627 "fsgen"
3628
3629 #clock-cells = <0>;
3630 clock-output-names =
3631 #sound-dai-cells = <1
3632 };
3633
3634 lpass_wsamacro: codec@6b00000
3635 compatible = "qcom,x1
3636 reg = <0 0x06b00000 0
3637 clocks = <&q6prmcc LP
3638 <&q6prmcc LP
3639 <&q6prmcc LP
3640 <&lpass_vama
3641 clock-names = "mclk",
3642 "macro"
3643 "dcodec
3644 "fsgen"
3645
3646 #clock-cells = <0>;
3647 clock-output-names =
3648 #sound-dai-cells = <1
3649 sound-name-prefix = "
3650 };
3651
3652 swr0: soundwire@6b10000 {
3653 compatible = "qcom,so
3654 reg = <0 0x06b10000 0
3655 clocks = <&lpass_wsam
3656 clock-names = "iface"
3657 interrupts = <GIC_SPI
3658 label = "WSA";
3659
3660 pinctrl-0 = <&wsa_swr
3661 pinctrl-names = "defa
3662 resets = <&lpass_audi
3663 reset-names = "swr_au
3664
3665 qcom,din-ports = <4>;
3666 qcom,dout-ports = <9>
3667
3668 qcom,ports-sinterval
3669 qcom,ports-offset1 =
3670 qcom,ports-offset2 =
3671 qcom,ports-hstart =
3672 qcom,ports-hstop =
3673 qcom,ports-word-lengt
3674 qcom,ports-block-pack
3675 qcom,ports-block-grou
3676 qcom,ports-lane-contr
3677
3678 #address-cells = <2>;
3679 #size-cells = <0>;
3680 #sound-dai-cells = <1
3681 status = "disabled";
3682 };
3683
3684 lpass_audiocc: clock-controll
3685 compatible = "qcom,x1
3686 reg = <0 0x06b6c000 0
3687 #clock-cells = <1>;
3688 #reset-cells = <1>;
3689 };
3690
3691 swr2: soundwire@6d30000 {
3692 compatible = "qcom,so
3693 reg = <0 0x06d30000 0
3694 clocks = <&lpass_txma
3695 clock-names = "iface"
3696 interrupts = <GIC_SPI
3697 <GIC_SPI
3698 interrupt-names = "co
3699 label = "TX";
3700 resets = <&lpasscc LP
3701 reset-names = "swr_au
3702
3703 pinctrl-0 = <&tx_swr_
3704 pinctrl-names = "defa
3705
3706 qcom,din-ports = <4>;
3707 qcom,dout-ports = <1>
3708
3709 qcom,ports-sinterval-
3710 qcom,ports-offset1 =
3711 qcom,ports-offset2 =
3712 qcom,ports-hstart =
3713 qcom,ports-hstop =
3714 qcom,ports-word-lengt
3715 qcom,ports-block-pack
3716 qcom,ports-block-grou
3717 qcom,ports-lane-contr
3718
3719 #address-cells = <2>;
3720 #size-cells = <0>;
3721 #sound-dai-cells = <1
3722 status = "disabled";
3723 };
3724
3725 lpass_vamacro: codec@6d44000
3726 compatible = "qcom,x1
3727 reg = <0 0x06d44000 0
3728 clocks = <&q6prmcc LP
3729 <&q6prmcc LP
3730 <&q6prmcc LP
3731 clock-names = "mclk",
3732 "macro"
3733 "dcodec
3734
3735 #clock-cells = <0>;
3736 clock-output-names =
3737 #sound-dai-cells = <1
3738 };
3739
3740 lpass_tlmm: pinctrl@6e80000 {
3741 compatible = "qcom,x1
3742 reg = <0 0x06e80000 0
3743 <0 0x07250000 0
3744
3745 clocks = <&q6prmcc LP
3746 <&q6prmcc LP
3747 clock-names = "core",
3748
3749 gpio-controller;
3750 #gpio-cells = <2>;
3751 gpio-ranges = <&lpass
3752
3753 tx_swr_active: tx-swr
3754 clk-pins {
3755 pins
3756 funct
3757 drive
3758 slew-
3759 bias-
3760 };
3761
3762 data-pins {
3763 pins
3764 funct
3765 drive
3766 slew-
3767 bias-
3768 };
3769 };
3770
3771 rx_swr_active: rx-swr
3772 clk-pins {
3773 pins
3774 funct
3775 drive
3776 slew-
3777 bias-
3778 };
3779
3780 data-pins {
3781 pins
3782 funct
3783 drive
3784 slew-
3785 bias-
3786 };
3787 };
3788
3789 dmic01_default: dmic0
3790 clk-pins {
3791 pins
3792 funct
3793 drive
3794 outpu
3795 };
3796
3797 data-pins {
3798 pins
3799 funct
3800 drive
3801 input
3802 };
3803 };
3804
3805 dmic23_default: dmic2
3806 clk-pins {
3807 pins
3808 funct
3809 drive
3810 outpu
3811 };
3812
3813 data-pins {
3814 pins
3815 funct
3816 drive
3817 input
3818 };
3819 };
3820
3821 wsa_swr_active: wsa-s
3822 clk-pins {
3823 pins
3824 funct
3825 drive
3826 slew-
3827 bias-
3828 };
3829
3830 data-pins {
3831 pins
3832 funct
3833 drive
3834 slew-
3835 bias-
3836 };
3837 };
3838
3839 wsa2_swr_active: wsa2
3840 clk-pins {
3841 pins
3842 funct
3843 drive
3844 slew-
3845 bias-
3846 };
3847
3848 data-pins {
3849 pins
3850 funct
3851 drive
3852 slew-
3853 bias-
3854 };
3855 };
3856 };
3857
3858 lpasscc: clock-controller@6ea
3859 compatible = "qcom,x1
3860 reg = <0 0x06ea0000 0
3861 #clock-cells = <1>;
3862 #reset-cells = <1>;
3863 };
3864
3865 lpass_ag_noc: interconnect@7e
3866 compatible = "qcom,x1
3867 reg = <0 0x07e40000 0
3868
3869 qcom,bcm-voters = <&a
3870
3871 #interconnect-cells =
3872 };
3873
3874 lpass_lpiaon_noc: interconnec
3875 compatible = "qcom,x1
3876 reg = <0 0x07400000 0
3877
3878 qcom,bcm-voters = <&a
3879
3880 #interconnect-cells =
3881 };
3882
3883 lpass_lpicx_noc: interconnect
3884 compatible = "qcom,x1
3885 reg = <0 0x07430000 0
3886
3887 qcom,bcm-voters = <&a
3888
3889 #interconnect-cells =
3890 };
3891
3892 usb_2_hsphy: phy@88e0000 {
3893 compatible = "qcom,x1
3894 "qcom,sm
3895 reg = <0 0x088e0000 0
3896 #phy-cells = <0>;
3897
3898 clocks = <&tcsr TCSR_
3899 clock-names = "ref";
3900
3901 resets = <&gcc GCC_QU
3902
3903 status = "disabled";
3904 };
3905
3906 usb_mp_hsphy0: phy@88e1000 {
3907 compatible = "qcom,x1
3908 "qcom,sm
3909 reg = <0 0x088e1000 0
3910 #phy-cells = <0>;
3911
3912 clocks = <&tcsr TCSR_
3913 clock-names = "ref";
3914
3915 resets = <&gcc GCC_QU
3916
3917 status = "disabled";
3918 };
3919
3920 usb_mp_hsphy1: phy@88e2000 {
3921 compatible = "qcom,x1
3922 "qcom,sm
3923 reg = <0 0x088e2000 0
3924 #phy-cells = <0>;
3925
3926 clocks = <&tcsr TCSR_
3927 clock-names = "ref";
3928
3929 resets = <&gcc GCC_QU
3930
3931 status = "disabled";
3932 };
3933
3934 usb_mp_qmpphy0: phy@88e3000 {
3935 compatible = "qcom,x1
3936 reg = <0 0x088e3000 0
3937
3938 clocks = <&gcc GCC_US
3939 <&rpmhcc RPM
3940 <&gcc GCC_US
3941 <&gcc GCC_US
3942 clock-names = "aux",
3943 "ref",
3944 "com_au
3945 "pipe";
3946
3947 resets = <&gcc GCC_US
3948 <&gcc GCC_US
3949 reset-names = "phy",
3950 "phy_ph
3951
3952 power-domains = <&gcc
3953
3954 #clock-cells = <0>;
3955 clock-output-names =
3956
3957 #phy-cells = <0>;
3958
3959 status = "disabled";
3960 };
3961
3962 usb_mp_qmpphy1: phy@88e5000 {
3963 compatible = "qcom,x1
3964 reg = <0 0x088e5000 0
3965
3966 clocks = <&gcc GCC_US
3967 <&rpmhcc RPM
3968 <&gcc GCC_US
3969 <&gcc GCC_US
3970 clock-names = "aux",
3971 "ref",
3972 "com_au
3973 "pipe";
3974
3975 resets = <&gcc GCC_US
3976 <&gcc GCC_US
3977 reset-names = "phy",
3978 "phy_ph
3979
3980 power-domains = <&gcc
3981
3982 #clock-cells = <0>;
3983 clock-output-names =
3984
3985 #phy-cells = <0>;
3986
3987 status = "disabled";
3988 };
3989
3990 usb_1_ss2: usb@a0f8800 {
3991 compatible = "qcom,x1
3992 reg = <0 0x0a0f8800 0
3993
3994 clocks = <&gcc GCC_CF
3995 <&gcc GCC_US
3996 <&gcc GCC_AG
3997 <&gcc GCC_US
3998 <&gcc GCC_US
3999 <&gcc GCC_AG
4000 <&gcc GCC_AG
4001 <&gcc GCC_AG
4002 <&gcc GCC_SY
4003 clock-names = "cfg_no
4004 "core",
4005 "iface"
4006 "sleep"
4007 "mock_u
4008 "noc_ag
4009 "noc_ag
4010 "noc_ag
4011 "noc_sy
4012
4013 assigned-clocks = <&g
4014 <&g
4015 assigned-clock-rates
4016
4017
4018 interrupts-extended =
4019
4020
4021
4022 interrupt-names = "pw
4023 "dp
4024 "dm
4025 "ss
4026
4027 power-domains = <&gcc
4028 required-opps = <&rpm
4029
4030 resets = <&gcc GCC_US
4031
4032 interconnects = <&usb
4033 &mc_
4034 <&gem
4035 &con
4036 interconnect-names =
4037
4038
4039 wakeup-source;
4040
4041 #address-cells = <2>;
4042 #size-cells = <2>;
4043 ranges;
4044
4045 status = "disabled";
4046
4047 usb_1_ss2_dwc3: usb@a
4048 compatible =
4049 reg = <0 0x0a
4050
4051 interrupts =
4052
4053 iommus = <&ap
4054
4055 phys = <&usb_
4056 <&usb_
4057 phy-names = "
4058 "
4059
4060 snps,dis_u2_s
4061 snps,dis_enbl
4062 snps,usb3_lpm
4063
4064 dma-coherent;
4065
4066 ports {
4067 #addr
4068 #size
4069
4070 port@
4071
4072
4073
4074
4075 };
4076
4077 port@
4078
4079
4080
4081
4082
4083 };
4084 };
4085 };
4086 };
4087
4088 usb_2: usb@a2f8800 {
4089 compatible = "qcom,x1
4090 reg = <0 0x0a2f8800 0
4091 #address-cells = <2>;
4092 #size-cells = <2>;
4093 ranges;
4094
4095 clocks = <&gcc GCC_CF
4096 <&gcc GCC_US
4097 <&gcc GCC_AG
4098 <&gcc GCC_US
4099 <&gcc GCC_US
4100 <&gcc GCC_AG
4101 <&gcc GCC_AG
4102 <&gcc GCC_AG
4103 <&gcc GCC_SY
4104 clock-names = "cfg_no
4105 "core",
4106 "iface"
4107 "sleep"
4108 "mock_u
4109 "noc_ag
4110 "noc_ag
4111 "noc_ag
4112 "noc_sy
4113
4114 assigned-clocks = <&g
4115 <&g
4116 assigned-clock-rates
4117
4118 interrupts-extended =
4119
4120
4121 interrupt-names = "pw
4122 "dp
4123 "dm
4124
4125 power-domains = <&gcc
4126 required-opps = <&rpm
4127
4128 resets = <&gcc GCC_US
4129
4130 interconnects = <&usb
4131 &mc_
4132 <&gem
4133 &con
4134 interconnect-names =
4135
4136
4137 wakeup-source;
4138
4139 status = "disabled";
4140
4141 usb_2_dwc3: usb@a2000
4142 compatible =
4143 reg = <0 0x0a
4144 interrupts =
4145 iommus = <&ap
4146 phys = <&usb_
4147 phy-names = "
4148 maximum-speed
4149
4150 ports {
4151 #addr
4152 #size
4153
4154 port@
4155
4156
4157
4158
4159 };
4160 };
4161 };
4162 };
4163
4164 usb_mp: usb@a4f8800 {
4165 compatible = "qcom,x1
4166 reg = <0 0x0a4f8800 0
4167
4168 clocks = <&gcc GCC_CF
4169 <&gcc GCC_US
4170 <&gcc GCC_AG
4171 <&gcc GCC_US
4172 <&gcc GCC_US
4173 <&gcc GCC_AG
4174 <&gcc GCC_AG
4175 <&gcc GCC_AG
4176 <&gcc GCC_SY
4177 clock-names = "cfg_no
4178 "core",
4179 "iface"
4180 "sleep"
4181 "mock_u
4182 "noc_ag
4183 "noc_ag
4184 "noc_ag
4185 "noc_sy
4186
4187 assigned-clocks = <&g
4188 <&g
4189 assigned-clock-rates
4190
4191
4192 interrupts-extended =
4193
4194
4195
4196
4197
4198
4199
4200
4201
4202 interrupt-names = "pw
4203 "hs
4204 "dp
4205 "dp
4206 "ss
4207
4208 power-domains = <&gcc
4209 required-opps = <&rpm
4210
4211 resets = <&gcc GCC_US
4212
4213 interconnects = <&usb
4214 &mc_
4215 <&gem
4216 &con
4217 interconnect-names =
4218
4219
4220 wakeup-source;
4221
4222 #address-cells = <2>;
4223 #size-cells = <2>;
4224 ranges;
4225
4226 status = "disabled";
4227
4228 usb_mp_dwc3: usb@a400
4229 compatible =
4230 reg = <0 0x0a
4231
4232 interrupts =
4233
4234 iommus = <&ap
4235
4236 phys = <&usb_
4237 <&usb_
4238 phy-names = "
4239 "
4240 dr_mode = "ho
4241
4242 snps,dis_u2_s
4243 snps,dis_enbl
4244 snps,usb3_lpm
4245
4246 dma-coherent;
4247 };
4248 };
4249
4250 usb_1_ss0: usb@a6f8800 {
4251 compatible = "qcom,x1
4252 reg = <0 0x0a6f8800 0
4253
4254 clocks = <&gcc GCC_CF
4255 <&gcc GCC_US
4256 <&gcc GCC_AG
4257 <&gcc GCC_US
4258 <&gcc GCC_US
4259 <&gcc GCC_AG
4260 <&gcc GCC_CF
4261 <&gcc GCC_CF
4262 <&gcc GCC_SY
4263 clock-names = "cfg_no
4264 "core",
4265 "iface"
4266 "sleep"
4267 "mock_u
4268 "noc_ag
4269 "noc_ag
4270 "noc_ag
4271 "noc_sy
4272
4273 assigned-clocks = <&g
4274 <&g
4275 assigned-clock-rates
4276
4277
4278 interrupts-extended =
4279
4280
4281
4282 interrupt-names = "pw
4283 "dp
4284 "dm
4285 "ss
4286
4287 power-domains = <&gcc
4288 required-opps = <&rpm
4289
4290 resets = <&gcc GCC_US
4291
4292 wakeup-source;
4293
4294 #address-cells = <2>;
4295 #size-cells = <2>;
4296 ranges;
4297
4298 status = "disabled";
4299
4300 usb_1_ss0_dwc3: usb@a
4301 compatible =
4302 reg = <0 0x0a
4303
4304 interrupts =
4305
4306 iommus = <&ap
4307
4308 phys = <&usb_
4309 <&usb_
4310 phy-names = "
4311 "
4312
4313 snps,dis_u2_s
4314 snps,dis_enbl
4315 snps,usb3_lpm
4316
4317 dma-coherent;
4318
4319 ports {
4320 #addr
4321 #size
4322
4323 port@
4324
4325
4326
4327
4328 };
4329
4330 port@
4331
4332
4333
4334
4335
4336 };
4337 };
4338 };
4339 };
4340
4341 usb_1_ss1: usb@a8f8800 {
4342 compatible = "qcom,x1
4343 reg = <0 0x0a8f8800 0
4344
4345 clocks = <&gcc GCC_CF
4346 <&gcc GCC_US
4347 <&gcc GCC_AG
4348 <&gcc GCC_US
4349 <&gcc GCC_US
4350 <&gcc GCC_AG
4351 <&gcc GCC_AG
4352 <&gcc GCC_AG
4353 <&gcc GCC_SY
4354 clock-names = "cfg_no
4355 "core",
4356 "iface"
4357 "sleep"
4358 "mock_u
4359 "noc_ag
4360 "noc_ag
4361 "noc_ag
4362 "noc_sy
4363
4364 assigned-clocks = <&g
4365 <&g
4366 assigned-clock-rates
4367
4368
4369 interrupts-extended =
4370
4371
4372
4373 interrupt-names = "pw
4374 "dp
4375 "dm
4376 "ss
4377
4378 power-domains = <&gcc
4379 required-opps = <&rpm
4380
4381 resets = <&gcc GCC_US
4382
4383 interconnects = <&usb
4384 &mc_
4385 <&gem
4386 &con
4387 interconnect-names =
4388
4389
4390 wakeup-source;
4391
4392 #address-cells = <2>;
4393 #size-cells = <2>;
4394 ranges;
4395
4396 status = "disabled";
4397
4398 usb_1_ss1_dwc3: usb@a
4399 compatible =
4400 reg = <0 0x0a
4401
4402 interrupts =
4403
4404 iommus = <&ap
4405
4406 phys = <&usb_
4407 <&usb_
4408 phy-names = "
4409 "
4410
4411 snps,dis_u2_s
4412 snps,dis_enbl
4413 snps,usb3_lpm
4414
4415 dma-coherent;
4416
4417 ports {
4418 #addr
4419 #size
4420
4421 port@
4422
4423
4424
4425
4426 };
4427
4428 port@
4429
4430
4431
4432
4433
4434 };
4435 };
4436 };
4437 };
4438
4439 mdss: display-subsystem@ae000
4440 compatible = "qcom,x1
4441 reg = <0 0x0ae00000 0
4442 reg-names = "mdss";
4443
4444 interrupts = <GIC_SPI
4445
4446 clocks = <&dispcc DIS
4447 <&gcc GCC_DI
4448 <&dispcc DIS
4449
4450 resets = <&dispcc DIS
4451
4452 interconnects = <&mms
4453 &gem
4454 <&mc_
4455 &mc_
4456 <&gem
4457 &con
4458 interconnect-names =
4459
4460
4461
4462 power-domains = <&dis
4463
4464 iommus = <&apps_smmu
4465
4466 interrupt-controller;
4467 #interrupt-cells = <1
4468
4469 #address-cells = <2>;
4470 #size-cells = <2>;
4471 ranges;
4472
4473 status = "disabled";
4474
4475 mdss_mdp: display-con
4476 compatible =
4477 reg = <0 0x0a
4478 <0 0x0a
4479 reg-names = "
4480 "
4481
4482 interrupts-ex
4483
4484 clocks = <&gc
4485 <&di
4486 <&di
4487 <&di
4488 <&di
4489 clock-names =
4490
4491
4492
4493
4494
4495 operating-poi
4496
4497 power-domains
4498
4499 ports {
4500 #addr
4501 #size
4502
4503 port@
4504
4505
4506
4507
4508
4509 };
4510
4511 port@
4512
4513
4514
4515
4516
4517 };
4518
4519 port@
4520
4521
4522
4523
4524
4525 };
4526
4527 port@
4528
4529
4530
4531
4532
4533 };
4534 };
4535
4536 mdp_opp_table
4537 compa
4538
4539 opp-2
4540
4541
4542 };
4543
4544 opp-3
4545
4546
4547 };
4548
4549 opp-3
4550
4551
4552 };
4553
4554 opp-5
4555
4556
4557 };
4558
4559 opp-5
4560
4561
4562 };
4563 };
4564 };
4565
4566 mdss_dp0: displayport
4567 compatible =
4568 reg = <0 0x0a
4569 <0 0x0a
4570 <0 0x0a
4571 <0 0x0a
4572 <0 0x0a
4573
4574 interrupts-ex
4575
4576 clocks = <&di
4577 <&di
4578 <&di
4579 <&di
4580 <&di
4581 clock-names =
4582
4583
4584
4585
4586
4587 assigned-cloc
4588
4589 assigned-cloc
4590
4591
4592 operating-poi
4593
4594 power-domains
4595
4596 phys = <&usb_
4597 phy-names = "
4598
4599 #sound-dai-ce
4600
4601 status = "dis
4602
4603 ports {
4604 #addr
4605 #size
4606
4607 port@
4608
4609
4610
4611
4612
4613 };
4614
4615 port@
4616
4617
4618
4619
4620
4621 };
4622 };
4623
4624 mdss_dp0_opp_
4625 compa
4626
4627 opp-1
4628
4629
4630 };
4631
4632 opp-2
4633
4634
4635 };
4636
4637 opp-5
4638
4639
4640 };
4641
4642 opp-8
4643
4644
4645 };
4646 };
4647 };
4648
4649 mdss_dp1: displayport
4650 compatible =
4651 reg = <0 0x0a
4652 <0 0x0a
4653 <0 0x0a
4654 <0 0x0a
4655 <0 0x0a
4656
4657 interrupts-ex
4658
4659 clocks = <&di
4660 <&di
4661 <&di
4662 <&di
4663 <&di
4664 clock-names =
4665
4666
4667
4668
4669
4670 assigned-cloc
4671
4672 assigned-cloc
4673
4674
4675 operating-poi
4676
4677 power-domains
4678
4679 phys = <&usb_
4680 phy-names = "
4681
4682 #sound-dai-ce
4683
4684 status = "dis
4685
4686 ports {
4687 #addr
4688 #size
4689
4690 port@
4691
4692
4693
4694
4695
4696 };
4697
4698 port@
4699
4700
4701
4702
4703
4704 };
4705 };
4706
4707 mdss_dp1_opp_
4708 compa
4709
4710 opp-1
4711
4712
4713 };
4714
4715 opp-2
4716
4717
4718 };
4719
4720 opp-5
4721
4722
4723 };
4724
4725 opp-8
4726
4727
4728 };
4729 };
4730 };
4731
4732 mdss_dp2: displayport
4733 compatible =
4734 reg = <0 0x0a
4735 <0 0x0a
4736 <0 0x0a
4737 <0 0x0a
4738 <0 0x0a
4739
4740 interrupts-ex
4741
4742 clocks = <&di
4743 <&di
4744 <&di
4745 <&di
4746 <&di
4747 clock-names =
4748
4749
4750
4751
4752
4753 assigned-cloc
4754
4755 assigned-cloc
4756
4757
4758 operating-poi
4759
4760 power-domains
4761
4762 phys = <&usb_
4763 phy-names = "
4764
4765 #sound-dai-ce
4766
4767 status = "dis
4768
4769 ports {
4770 #addr
4771 #size
4772
4773 port@
4774
4775
4776
4777
4778 };
4779
4780 port@
4781
4782
4783
4784
4785
4786 };
4787 };
4788
4789 mdss_dp2_opp_
4790 compa
4791
4792 opp-1
4793
4794
4795 };
4796
4797 opp-2
4798
4799
4800 };
4801
4802 opp-5
4803
4804
4805 };
4806
4807 opp-8
4808
4809
4810 };
4811 };
4812 };
4813
4814 mdss_dp3: displayport
4815 compatible =
4816 reg = <0 0x0a
4817 <0 0x0a
4818 <0 0x0a
4819 <0 0x0a
4820 <0 0x0a
4821
4822 interrupts-ex
4823
4824 clocks = <&di
4825 <&di
4826 <&di
4827 <&di
4828 <&di
4829 clock-names =
4830
4831
4832
4833
4834
4835 assigned-cloc
4836
4837 assigned-cloc
4838
4839
4840 operating-poi
4841
4842 power-domains
4843
4844 phys = <&mdss
4845 phy-names = "
4846
4847 #sound-dai-ce
4848
4849 status = "dis
4850
4851 ports {
4852 #addr
4853 #size
4854
4855 port@
4856
4857
4858
4859
4860
4861 };
4862
4863 port@
4864
4865 };
4866 };
4867
4868 mdss_dp3_opp_
4869 compa
4870
4871 opp-1
4872
4873
4874 };
4875
4876 opp-2
4877
4878
4879 };
4880
4881 opp-5
4882
4883
4884 };
4885
4886 opp-8
4887
4888
4889 };
4890 };
4891 };
4892
4893 };
4894
4895 mdss_dp2_phy: phy@aec2a00 {
4896 compatible = "qcom,x1
4897 reg = <0 0x0aec2a00 0
4898 <0 0x0aec2200 0
4899 <0 0x0aec2600 0
4900 <0 0x0aec2000 0
4901
4902 clocks = <&dispcc DIS
4903 <&dispcc DIS
4904 clock-names = "aux",
4905 "cfg_ah
4906
4907 power-domains = <&rpm
4908
4909 #clock-cells = <1>;
4910 #phy-cells = <0>;
4911
4912 status = "disabled";
4913 };
4914
4915 mdss_dp3_phy: phy@aec5a00 {
4916 compatible = "qcom,x1
4917 reg = <0 0x0aec5a00 0
4918 <0 0x0aec5200 0
4919 <0 0x0aec5600 0
4920 <0 0x0aec5000 0
4921
4922 clocks = <&dispcc DIS
4923 <&dispcc DIS
4924 clock-names = "aux",
4925 "cfg_ah
4926
4927 power-domains = <&rpm
4928
4929 #clock-cells = <1>;
4930 #phy-cells = <0>;
4931
4932 status = "disabled";
4933 };
4934
4935 dispcc: clock-controller@af00
4936 compatible = "qcom,x1
4937 reg = <0 0x0af00000 0
4938 clocks = <&bi_tcxo_di
4939 <&bi_tcxo_ao
4940 <&gcc GCC_DI
4941 <&sleep_clk>
4942 <0>, /* dsi0
4943 <0>,
4944 <0>, /* dsi1
4945 <0>,
4946 <&usb_1_ss0_
4947 <&usb_1_ss0_
4948 <&usb_1_ss1_
4949 <&usb_1_ss1_
4950 <&usb_1_ss2_
4951 <&usb_1_ss2_
4952 <&mdss_dp3_p
4953 <&mdss_dp3_p
4954 power-domains = <&rpm
4955 required-opps = <&rpm
4956 #clock-cells = <1>;
4957 #reset-cells = <1>;
4958 #power-domain-cells =
4959 };
4960
4961 pdc: interrupt-controller@b22
4962 compatible = "qcom,x1
4963 reg = <0 0x0b220000 0
4964
4965 qcom,pdc-ranges = <0
4966 <47
4967 <13
4968 #interrupt-cells = <2
4969 interrupt-parent = <&
4970 interrupt-controller;
4971 };
4972
4973 aoss_qmp: power-management@c3
4974 compatible = "qcom,x1
4975 reg = <0 0x0c300000 0
4976 interrupt-parent = <&
4977 interrupts-extended =
4978
4979 mboxes = <&ipcc IPCC_
4980
4981 #clock-cells = <0>;
4982 };
4983
4984 sram@c3f0000 {
4985 compatible = "qcom,rp
4986 reg = <0 0x0c3f0000 0
4987 };
4988
4989 spmi: arbiter@c400000 {
4990 compatible = "qcom,x1
4991 reg = <0 0x0c400000 0
4992 <0 0x0c500000 0
4993 <0 0x0c440000 0
4994 reg-names = "core", "
4995
4996 qcom,ee = <0>;
4997 qcom,channel = <0>;
4998
4999 #address-cells = <2>;
5000 #size-cells = <2>;
5001 ranges;
5002
5003 spmi_bus0: spmi@c42d0
5004 reg = <0 0x0c
5005 <0 0x0c
5006 reg-names = "
5007
5008 interrupt-nam
5009 interrupts-ex
5010 interrupt-con
5011 #interrupt-ce
5012
5013 #address-cell
5014 #size-cells =
5015 };
5016
5017 spmi_bus1: spmi@c4320
5018 reg = <0 0x0c
5019 <0 0x0c
5020 reg-names = "
5021
5022 interrupt-nam
5023 interrupts-ex
5024 interrupt-con
5025 #interrupt-ce
5026
5027 #address-cell
5028 #size-cells =
5029 };
5030 };
5031
5032 tlmm: pinctrl@f100000 {
5033 compatible = "qcom,x1
5034 reg = <0 0x0f100000 0
5035
5036 interrupts = <GIC_SPI
5037
5038 gpio-controller;
5039 #gpio-cells = <2>;
5040
5041 interrupt-controller;
5042 #interrupt-cells = <2
5043
5044 gpio-ranges = <&tlmm
5045 wakeup-parent = <&pdc
5046
5047 qup_i2c0_data_clk: qu
5048 /* SDA, SCL *
5049 pins = "gpio0
5050 function = "q
5051 drive-strengt
5052 bias-pull-up
5053 };
5054
5055 qup_i2c1_data_clk: qu
5056 /* SDA, SCL *
5057 pins = "gpio4
5058 function = "q
5059 drive-strengt
5060 bias-pull-up
5061 };
5062
5063 qup_i2c2_data_clk: qu
5064 /* SDA, SCL *
5065 pins = "gpio8
5066 function = "q
5067 drive-strengt
5068 bias-pull-up
5069 };
5070
5071 qup_i2c3_data_clk: qu
5072 /* SDA, SCL *
5073 pins = "gpio1
5074 function = "q
5075 drive-strengt
5076 bias-pull-up
5077 };
5078
5079 qup_i2c4_data_clk: qu
5080 /* SDA, SCL *
5081 pins = "gpio1
5082 function = "q
5083 drive-strengt
5084 bias-pull-up
5085 };
5086
5087 qup_i2c5_data_clk: qu
5088 /* SDA, SCL *
5089 pins = "gpio2
5090 function = "q
5091 drive-strengt
5092 bias-pull-up
5093 };
5094
5095 qup_i2c6_data_clk: qu
5096 /* SDA, SCL *
5097 pins = "gpio2
5098 function = "q
5099 drive-strengt
5100 bias-pull-up
5101 };
5102
5103 qup_i2c7_data_clk: qu
5104 /* SDA, SCL *
5105 pins = "gpio1
5106 function = "q
5107 drive-strengt
5108 bias-pull-up
5109 };
5110
5111 qup_i2c8_data_clk: qu
5112 /* SDA, SCL *
5113 pins = "gpio3
5114 function = "q
5115 drive-strengt
5116 bias-pull-up
5117 };
5118
5119 qup_i2c9_data_clk: qu
5120 /* SDA, SCL *
5121 pins = "gpio3
5122 function = "q
5123 drive-strengt
5124 bias-pull-up
5125 };
5126
5127 qup_i2c10_data_clk: q
5128 /* SDA, SCL *
5129 pins = "gpio4
5130 function = "q
5131 drive-strengt
5132 bias-pull-up
5133 };
5134
5135 qup_i2c11_data_clk: q
5136 /* SDA, SCL *
5137 pins = "gpio4
5138 function = "q
5139 drive-strengt
5140 bias-pull-up
5141 };
5142
5143 qup_i2c12_data_clk: q
5144 /* SDA, SCL *
5145 pins = "gpio4
5146 function = "q
5147 drive-strengt
5148 bias-pull-up
5149 };
5150
5151 qup_i2c13_data_clk: q
5152 /* SDA, SCL *
5153 pins = "gpio5
5154 function = "q
5155 drive-strengt
5156 bias-pull-up
5157 };
5158
5159 qup_i2c14_data_clk: q
5160 /* SDA, SCL *
5161 pins = "gpio5
5162 function = "q
5163 drive-strengt
5164 bias-pull-up
5165 };
5166
5167 qup_i2c15_data_clk: q
5168 /* SDA, SCL *
5169 pins = "gpio5
5170 function = "q
5171 drive-strengt
5172 bias-pull-up
5173 };
5174
5175 qup_i2c16_data_clk: q
5176 /* SDA, SCL *
5177 pins = "gpio6
5178 function = "q
5179 drive-strengt
5180 bias-pull-up
5181 };
5182
5183 qup_i2c17_data_clk: q
5184 /* SDA, SCL *
5185 pins = "gpio6
5186 function = "q
5187 drive-strengt
5188 bias-pull-up
5189 };
5190
5191 qup_i2c18_data_clk: q
5192 /* SDA, SCL *
5193 pins = "gpio7
5194 function = "q
5195 drive-strengt
5196 bias-pull-up
5197 };
5198
5199 qup_i2c19_data_clk: q
5200 /* SDA, SCL *
5201 pins = "gpio7
5202 function = "q
5203 drive-strengt
5204 bias-pull-up
5205 };
5206
5207 qup_i2c20_data_clk: q
5208 /* SDA, SCL *
5209 pins = "gpio8
5210 function = "q
5211 drive-strengt
5212 bias-pull-up
5213 };
5214
5215 qup_i2c21_data_clk: q
5216 /* SDA, SCL *
5217 pins = "gpio8
5218 function = "q
5219 drive-strengt
5220 bias-pull-up
5221 };
5222
5223 qup_i2c22_data_clk: q
5224 /* SDA, SCL *
5225 pins = "gpio8
5226 function = "q
5227 drive-strengt
5228 bias-pull-up
5229 };
5230
5231 qup_i2c23_data_clk: q
5232 /* SDA, SCL *
5233 pins = "gpio8
5234 function = "q
5235 drive-strengt
5236 bias-pull-up
5237 };
5238
5239 qup_spi0_cs: qup-spi0
5240 pins = "gpio3
5241 function = "q
5242 drive-strengt
5243 bias-disable;
5244 };
5245
5246 qup_spi0_data_clk: qu
5247 /* MISO, MOSI
5248 pins = "gpio0
5249 function = "q
5250 drive-strengt
5251 bias-disable;
5252 };
5253
5254 qup_spi1_cs: qup-spi1
5255 pins = "gpio7
5256 function = "q
5257 drive-strengt
5258 bias-disable;
5259 };
5260
5261 qup_spi1_data_clk: qu
5262 /* MISO, MOSI
5263 pins = "gpio4
5264 function = "q
5265 drive-strengt
5266 bias-disable;
5267 };
5268
5269 qup_spi2_cs: qup-spi2
5270 pins = "gpio1
5271 function = "q
5272 drive-strengt
5273 bias-disable;
5274 };
5275
5276 qup_spi2_data_clk: qu
5277 /* MISO, MOSI
5278 pins = "gpio8
5279 function = "q
5280 drive-strengt
5281 bias-disable;
5282 };
5283
5284 qup_spi3_cs: qup-spi3
5285 pins = "gpio1
5286 function = "q
5287 drive-strengt
5288 bias-disable;
5289 };
5290
5291 qup_spi3_data_clk: qu
5292 /* MISO, MOSI
5293 pins = "gpio1
5294 function = "q
5295 drive-strengt
5296 bias-disable;
5297 };
5298
5299 qup_spi4_cs: qup-spi4
5300 pins = "gpio1
5301 function = "q
5302 drive-strengt
5303 bias-disable;
5304 };
5305
5306 qup_spi4_data_clk: qu
5307 /* MISO, MOSI
5308 pins = "gpio1
5309 function = "q
5310 drive-strengt
5311 bias-disable;
5312 };
5313
5314 qup_spi5_cs: qup-spi5
5315 pins = "gpio2
5316 function = "q
5317 drive-strengt
5318 bias-disable;
5319 };
5320
5321 qup_spi5_data_clk: qu
5322 /* MISO, MOSI
5323 pins = "gpio2
5324 function = "q
5325 drive-strengt
5326 bias-disable;
5327 };
5328
5329 qup_spi6_cs: qup-spi6
5330 pins = "gpio2
5331 function = "q
5332 drive-strengt
5333 bias-disable;
5334 };
5335
5336 qup_spi6_data_clk: qu
5337 /* MISO, MOSI
5338 pins = "gpio2
5339 function = "q
5340 drive-strengt
5341 bias-disable;
5342 };
5343
5344 qup_spi7_cs: qup-spi7
5345 pins = "gpio1
5346 function = "q
5347 drive-strengt
5348 bias-disable;
5349 };
5350
5351 qup_spi7_data_clk: qu
5352 /* MISO, MOSI
5353 pins = "gpio1
5354 function = "q
5355 drive-strengt
5356 bias-disable;
5357 };
5358
5359 qup_spi8_cs: qup-spi8
5360 pins = "gpio3
5361 function = "q
5362 drive-strengt
5363 bias-disable;
5364 };
5365
5366 qup_spi8_data_clk: qu
5367 /* MISO, MOSI
5368 pins = "gpio3
5369 function = "q
5370 drive-strengt
5371 bias-disable;
5372 };
5373
5374 qup_spi9_cs: qup-spi9
5375 pins = "gpio3
5376 function = "q
5377 drive-strengt
5378 bias-disable;
5379 };
5380
5381 qup_spi9_data_clk: qu
5382 /* MISO, MOSI
5383 pins = "gpio3
5384 function = "q
5385 drive-strengt
5386 bias-disable;
5387 };
5388
5389 qup_spi10_cs: qup-spi
5390 pins = "gpio4
5391 function = "q
5392 drive-strengt
5393 bias-disable;
5394 };
5395
5396 qup_spi10_data_clk: q
5397 /* MISO, MOSI
5398 pins = "gpio4
5399 function = "q
5400 drive-strengt
5401 bias-disable;
5402 };
5403
5404 qup_spi11_cs: qup-spi
5405 pins = "gpio4
5406 function = "q
5407 drive-strengt
5408 bias-disable;
5409 };
5410
5411 qup_spi11_data_clk: q
5412 /* MISO, MOSI
5413 pins = "gpio4
5414 function = "q
5415 drive-strengt
5416 bias-disable;
5417 };
5418
5419 qup_spi12_cs: qup-spi
5420 pins = "gpio5
5421 function = "q
5422 drive-strengt
5423 bias-disable;
5424 };
5425
5426 qup_spi12_data_clk: q
5427 /* MISO, MOSI
5428 pins = "gpio4
5429 function = "q
5430 drive-strengt
5431 bias-disable;
5432 };
5433
5434 qup_spi13_cs: qup-spi
5435 pins = "gpio5
5436 function = "q
5437 drive-strengt
5438 bias-disable;
5439 };
5440
5441 qup_spi13_data_clk: q
5442 /* MISO, MOSI
5443 pins = "gpio5
5444 function = "q
5445 drive-strengt
5446 bias-disable;
5447 };
5448
5449 qup_spi14_cs: qup-spi
5450 pins = "gpio5
5451 function = "q
5452 drive-strengt
5453 bias-disable;
5454 };
5455
5456 qup_spi14_data_clk: q
5457 /* MISO, MOSI
5458 pins = "gpio5
5459 function = "q
5460 drive-strengt
5461 bias-disable;
5462 };
5463
5464 qup_spi15_cs: qup-spi
5465 pins = "gpio5
5466 function = "q
5467 drive-strengt
5468 bias-disable;
5469 };
5470
5471 qup_spi15_data_clk: q
5472 /* MISO, MOSI
5473 pins = "gpio5
5474 function = "q
5475 drive-strengt
5476 bias-disable;
5477 };
5478
5479 qup_spi16_cs: qup-spi
5480 pins = "gpio6
5481 function = "q
5482 drive-strengt
5483 bias-disable;
5484 };
5485
5486 qup_spi16_data_clk: q
5487 /* MISO, MOSI
5488 pins = "gpio6
5489 function = "q
5490 drive-strengt
5491 bias-disable;
5492 };
5493
5494 qup_spi17_cs: qup-spi
5495 pins = "gpio7
5496 function = "q
5497 drive-strengt
5498 bias-disable;
5499 };
5500
5501 qup_spi17_data_clk: q
5502 /* MISO, MOSI
5503 pins = "gpio6
5504 function = "q
5505 drive-strengt
5506 bias-disable;
5507 };
5508
5509 qup_spi18_cs: qup-spi
5510 pins = "gpio7
5511 function = "q
5512 drive-strengt
5513 bias-disable;
5514 };
5515
5516 qup_spi18_data_clk: q
5517 /* MISO, MOSI
5518 pins = "gpio7
5519 function = "q
5520 drive-strengt
5521 bias-disable;
5522 };
5523
5524 qup_spi19_cs: qup-spi
5525 pins = "gpio7
5526 function = "q
5527 drive-strengt
5528 bias-disable;
5529 };
5530
5531 qup_spi19_data_clk: q
5532 /* MISO, MOSI
5533 pins = "gpio7
5534 function = "q
5535 drive-strengt
5536 bias-disable;
5537 };
5538
5539 qup_spi20_cs: qup-spi
5540 pins = "gpio8
5541 function = "q
5542 drive-strengt
5543 bias-disable;
5544 };
5545
5546 qup_spi20_data_clk: q
5547 /* MISO, MOSI
5548 pins = "gpio8
5549 function = "q
5550 drive-strengt
5551 bias-disable;
5552 };
5553
5554 qup_spi21_cs: qup-spi
5555 pins = "gpio8
5556 function = "q
5557 drive-strengt
5558 bias-disable;
5559 };
5560
5561 qup_spi21_data_clk: q
5562 /* MISO, MOSI
5563 pins = "gpio8
5564 function = "q
5565 drive-strengt
5566 bias-disable;
5567 };
5568
5569 qup_spi22_cs: qup-spi
5570 pins = "gpio9
5571 function = "q
5572 drive-strengt
5573 bias-disable;
5574 };
5575
5576 qup_spi22_data_clk: q
5577 /* MISO, MOSI
5578 pins = "gpio8
5579 function = "q
5580 drive-strengt
5581 bias-disable;
5582 };
5583
5584 qup_spi23_cs: qup-spi
5585 pins = "gpio8
5586 function = "q
5587 drive-strengt
5588 bias-disable;
5589 };
5590
5591 qup_spi23_data_clk: q
5592 /* MISO, MOSI
5593 pins = "gpio8
5594 function = "q
5595 drive-strengt
5596 bias-disable;
5597 };
5598
5599 qup_uart2_default: qu
5600 cts-pins {
5601 pins
5602 funct
5603 drive
5604 bias-
5605 };
5606
5607 rts-pins {
5608 pins
5609 funct
5610 drive
5611 bias-
5612 };
5613
5614 tx-pins {
5615 pins
5616 funct
5617 drive
5618 bias-
5619 };
5620
5621 rx-pins {
5622 pins
5623 funct
5624 drive
5625 bias-
5626 };
5627 };
5628
5629 qup_uart21_default: q
5630 tx-pins {
5631 pins
5632 funct
5633 drive
5634 bias-
5635 };
5636
5637 rx-pins {
5638 pins
5639 funct
5640 drive
5641 bias-
5642 };
5643 };
5644 };
5645
5646 apps_smmu: iommu@15000000 {
5647 compatible = "qcom,x1
5648 reg = <0 0x15000000 0
5649
5650 interrupts = <GIC_SPI
5651 <GIC_SPI
5652 <GIC_SPI
5653 <GIC_SPI
5654 <GIC_SPI
5655 <GIC_SPI
5656 <GIC_SPI
5657 <GIC_SPI
5658 <GIC_SPI
5659 <GIC_SPI
5660 <GIC_SPI
5661 <GIC_SPI
5662 <GIC_SPI
5663 <GIC_SPI
5664 <GIC_SPI
5665 <GIC_SPI
5666 <GIC_SPI
5667 <GIC_SPI
5668 <GIC_SPI
5669 <GIC_SPI
5670 <GIC_SPI
5671 <GIC_SPI
5672 <GIC_SPI
5673 <GIC_SPI
5674 <GIC_SPI
5675 <GIC_SPI
5676 <GIC_SPI
5677 <GIC_SPI
5678 <GIC_SPI
5679 <GIC_SPI
5680 <GIC_SPI
5681 <GIC_SPI
5682 <GIC_SPI
5683 <GIC_SPI
5684 <GIC_SPI
5685 <GIC_SPI
5686 <GIC_SPI
5687 <GIC_SPI
5688 <GIC_SPI
5689 <GIC_SPI
5690 <GIC_SPI
5691 <GIC_SPI
5692 <GIC_SPI
5693 <GIC_SPI
5694 <GIC_SPI
5695 <GIC_SPI
5696 <GIC_SPI
5697 <GIC_SPI
5698 <GIC_SPI
5699 <GIC_SPI
5700 <GIC_SPI
5701 <GIC_SPI
5702 <GIC_SPI
5703 <GIC_SPI
5704 <GIC_SPI
5705 <GIC_SPI
5706 <GIC_SPI
5707 <GIC_SPI
5708 <GIC_SPI
5709 <GIC_SPI
5710 <GIC_SPI
5711 <GIC_SPI
5712 <GIC_SPI
5713 <GIC_SPI
5714 <GIC_SPI
5715 <GIC_SPI
5716 <GIC_SPI
5717 <GIC_SPI
5718 <GIC_SPI
5719 <GIC_SPI
5720 <GIC_SPI
5721 <GIC_SPI
5722 <GIC_SPI
5723 <GIC_SPI
5724 <GIC_SPI
5725 <GIC_SPI
5726 <GIC_SPI
5727 <GIC_SPI
5728 <GIC_SPI
5729 <GIC_SPI
5730 <GIC_SPI
5731 <GIC_SPI
5732 <GIC_SPI
5733 <GIC_SPI
5734 <GIC_SPI
5735 <GIC_SPI
5736 <GIC_SPI
5737 <GIC_SPI
5738 <GIC_SPI
5739 <GIC_SPI
5740 <GIC_SPI
5741 <GIC_SPI
5742 <GIC_SPI
5743 <GIC_SPI
5744 <GIC_SPI
5745 <GIC_SPI
5746 <GIC_SPI
5747
5748 #iommu-cells = <2>;
5749 #global-interrupts =
5750 };
5751
5752 intc: interrupt-controller@17
5753 compatible = "arm,gic
5754 reg = <0 0x17000000 0
5755 <0 0x17080000 0
5756
5757 interrupts = <GIC_PPI
5758
5759 #interrupt-cells = <3
5760 interrupt-controller;
5761
5762 #redistributor-region
5763 redistributor-stride
5764
5765 #address-cells = <2>;
5766 #size-cells = <2>;
5767 ranges;
5768
5769 gic_its: msi-controll
5770 compatible =
5771 reg = <0 0x17
5772
5773 msi-controlle
5774 #msi-cells =
5775
5776 status = "dis
5777 };
5778 };
5779
5780 apps_rsc: rsc@17500000 {
5781 compatible = "qcom,rp
5782 reg = <0 0x17500000 0
5783 <0 0x17510000 0
5784 <0 0x17520000 0
5785 reg-names = "drv-0",
5786
5787 interrupts = <GIC_SPI
5788 <GIC_SPI
5789 <GIC_SPI
5790 qcom,tcs-offset = <0x
5791 qcom,drv-id = <2>;
5792 qcom,tcs-config = <AC
5793 <WA
5794
5795 label = "apps_rsc";
5796 power-domains = <&SYS
5797
5798 apps_bcm_voter: bcm-v
5799 compatible =
5800 };
5801
5802 rpmhcc: clock-control
5803 compatible =
5804
5805 clocks = <&xo
5806 clock-names =
5807
5808 #clock-cells
5809 };
5810
5811 rpmhpd: power-control
5812 compatible =
5813
5814 operating-poi
5815
5816 #power-domain
5817
5818 rpmhpd_opp_ta
5819 compa
5820
5821 rpmhp
5822
5823 };
5824
5825 rpmhp
5826
5827 };
5828
5829 rpmhp
5830
5831 };
5832
5833 rpmhp
5834
5835 };
5836
5837 rpmhp
5838
5839 };
5840
5841 rpmhp
5842
5843 };
5844
5845 rpmhp
5846
5847 };
5848
5849 rpmhp
5850
5851 };
5852
5853 rpmhp
5854
5855 };
5856
5857 rpmhp
5858
5859 };
5860
5861 rpmhp
5862
5863 };
5864
5865 rpmhp
5866
5867 };
5868
5869 rpmhp
5870
5871 };
5872
5873 rpmhp
5874
5875 };
5876
5877 rpmhp
5878
5879 };
5880 };
5881 };
5882 };
5883
5884 timer@17800000 {
5885 compatible = "arm,arm
5886 reg = <0 0x17800000 0
5887
5888 #address-cells = <2>;
5889 #size-cells = <1>;
5890 ranges = <0 0 0 0 0x2
5891
5892 frame@17801000 {
5893 reg = <0 0x17
5894 <0 0x17
5895
5896 interrupts =
5897
5898
5899 frame-number
5900 };
5901
5902 frame@17803000 {
5903 reg = <0 0x17
5904
5905 interrupts =
5906
5907 frame-number
5908
5909 status = "dis
5910 };
5911
5912 frame@17805000 {
5913 reg = <0 0x17
5914
5915 interrupts =
5916
5917 frame-number
5918
5919 status = "dis
5920 };
5921
5922 frame@17807000 {
5923 reg = <0 0x17
5924
5925 interrupts =
5926
5927 frame-number
5928
5929 status = "dis
5930 };
5931
5932 frame@17809000 {
5933 reg = <0 0x17
5934
5935 interrupts =
5936
5937 frame-number
5938
5939 status = "dis
5940 };
5941
5942 frame@1780b000 {
5943 reg = <0 0x17
5944
5945 interrupts =
5946
5947 frame-number
5948
5949 status = "dis
5950 };
5951
5952 frame@1780d000 {
5953 reg = <0 0x17
5954
5955 interrupts =
5956
5957 frame-number
5958
5959 status = "dis
5960 };
5961 };
5962
5963 pmu@24091000 {
5964 compatible = "qcom,x1
5965 reg = <0 0x24091000 0
5966
5967 interrupts = <GIC_SPI
5968
5969 interconnects = <&mc_
5970 &mc_
5971
5972 operating-points-v2 =
5973
5974 llcc_bwmon_opp_table:
5975 compatible =
5976
5977 opp-0 {
5978 opp-p
5979 };
5980
5981 opp-1 {
5982 opp-p
5983 };
5984
5985 opp-2 {
5986 opp-p
5987 };
5988
5989 opp-3 {
5990 opp-p
5991 };
5992
5993 opp-4 {
5994 opp-p
5995 };
5996
5997 opp-5 {
5998 opp-p
5999 };
6000
6001 opp-6 {
6002 opp-p
6003 };
6004
6005 opp-7 {
6006 opp-p
6007 };
6008
6009 opp-8 {
6010 opp-p
6011 };
6012
6013 opp-9 {
6014 opp-p
6015 };
6016 };
6017 };
6018
6019 /* cluster0 */
6020 pmu@240b3400 {
6021 compatible = "qcom,x1
6022 reg = <0 0x240b3400 0
6023
6024 interrupts = <GIC_SPI
6025
6026 interconnects = <&gem
6027 &gem
6028
6029 operating-points-v2 =
6030
6031 cpu_bwmon_opp_table:
6032 compatible =
6033
6034 opp-0 {
6035 opp-p
6036 };
6037
6038 opp-1 {
6039 opp-p
6040 };
6041
6042 opp-2 {
6043 opp-p
6044 };
6045
6046 opp-3 {
6047 opp-p
6048 };
6049
6050 opp-4 {
6051 opp-p
6052 };
6053
6054 opp-5 {
6055 opp-p
6056 };
6057 };
6058 };
6059
6060 /* cluster2 */
6061 pmu@240b5400 {
6062 compatible = "qcom,x1
6063 reg = <0 0x240b5400 0
6064
6065 interrupts = <GIC_SPI
6066
6067 interconnects = <&gem
6068 &gem
6069
6070 operating-points-v2 =
6071 };
6072
6073 /* cluster1 */
6074 pmu@240b6400 {
6075 compatible = "qcom,x1
6076 reg = <0 0x240b6400 0
6077
6078 interrupts = <GIC_SPI
6079
6080 interconnects = <&gem
6081 &gem
6082
6083 operating-points-v2 =
6084 };
6085
6086 system-cache-controller@25000
6087 compatible = "qcom,x1
6088 reg = <0 0x25000000 0
6089 <0 0x25200000 0
6090 <0 0x25400000 0
6091 <0 0x25600000 0
6092 <0 0x25800000 0
6093 <0 0x25a00000 0
6094 <0 0x25c00000 0
6095 <0 0x25e00000 0
6096 <0 0x26000000 0
6097 <0 0x26200000 0
6098 reg-names = "llcc0_ba
6099 "llcc1_ba
6100 "llcc2_ba
6101 "llcc3_ba
6102 "llcc4_ba
6103 "llcc5_ba
6104 "llcc6_ba
6105 "llcc7_ba
6106 "llcc_bro
6107 "llcc_bro
6108 interrupts = <GIC_SPI
6109 };
6110
6111 remoteproc_adsp: remoteproc@3
6112 compatible = "qcom,x1
6113 reg = <0 0x30000000 0
6114
6115 interrupts-extended =
6116
6117
6118
6119
6120 interrupt-names = "wd
6121 "fa
6122 "re
6123 "ha
6124 "st
6125
6126 clocks = <&rpmhcc RPM
6127 clock-names = "xo";
6128
6129 power-domains = <&rpm
6130 <&rpm
6131 power-domain-names =
6132
6133
6134 interconnects = <&lpa
6135 &mc_
6136
6137 memory-region = <&ads
6138 <&q6_
6139
6140 qcom,qmp = <&aoss_qmp
6141
6142 qcom,smem-states = <&
6143 qcom,smem-state-names
6144
6145 status = "disabled";
6146
6147 glink-edge {
6148 interrupts-ex
6149
6150
6151 mboxes = <&ip
6152
6153
6154 label = "lpas
6155 qcom,remote-p
6156
6157 fastrpc {
6158 compa
6159 qcom,
6160 label
6161 qcom,
6162 #addr
6163 #size
6164
6165 compu
6166
6167
6168
6169
6170
6171 };
6172
6173 compu
6174
6175
6176
6177
6178
6179 };
6180
6181 compu
6182
6183
6184
6185
6186
6187 };
6188
6189 compu
6190
6191
6192
6193
6194
6195 };
6196
6197 compu
6198
6199
6200
6201
6202
6203 };
6204 };
6205
6206 gpr {
6207 compa
6208 qcom,
6209 qcom,
6210 qcom,
6211 #addr
6212 #size
6213
6214 q6apm
6215
6216
6217
6218
6219
6220
6221
6222
6223
6224
6225
6226
6227
6228
6229
6230
6231 };
6232
6233 q6prm
6234
6235
6236
6237
6238
6239
6240
6241
6242
6243 };
6244 };
6245 };
6246 };
6247
6248 remoteproc_cdsp: remoteproc@3
6249 compatible = "qcom,x1
6250 reg = <0 0x32300000 0
6251
6252 interrupts-extended =
6253
6254
6255
6256
6257 interrupt-names = "wd
6258 "fa
6259 "re
6260 "ha
6261 "st
6262
6263 clocks = <&rpmhcc RPM
6264 clock-names = "xo";
6265
6266 power-domains = <&rpm
6267 <&rpm
6268 <&rpm
6269 power-domain-names =
6270
6271
6272
6273 interconnects = <&nsp
6274 &mc_
6275
6276 memory-region = <&cds
6277 <&q6_
6278
6279 qcom,qmp = <&aoss_qmp
6280
6281 qcom,smem-states = <&
6282 qcom,smem-state-names
6283
6284 status = "disabled";
6285
6286 glink-edge {
6287 interrupts-ex
6288
6289
6290 mboxes = <&ip
6291
6292
6293 label = "cdsp
6294 qcom,remote-p
6295
6296 fastrpc {
6297 compa
6298 qcom,
6299 label
6300 qcom,
6301 #addr
6302 #size
6303
6304 compu
6305
6306
6307
6308
6309 };
6310
6311 compu
6312
6313
6314
6315
6316 };
6317
6318 compu
6319
6320
6321
6322
6323 };
6324
6325 compu
6326
6327
6328
6329
6330 };
6331
6332 compu
6333
6334
6335
6336
6337 };
6338
6339 compu
6340
6341
6342
6343
6344 };
6345
6346 compu
6347
6348
6349
6350
6351 };
6352
6353 compu
6354
6355
6356
6357
6358 };
6359
6360 /* no
6361
6362 compu
6363
6364
6365
6366
6367 };
6368
6369 compu
6370
6371
6372
6373
6374 };
6375
6376 compu
6377
6378
6379
6380
6381 };
6382
6383 compu
6384
6385
6386
6387
6388 };
6389 };
6390 };
6391 };
6392 };
6393
6394 timer {
6395 compatible = "arm,armv8-timer
6396
6397 interrupts = <GIC_PPI 13 IRQ_
6398 <GIC_PPI 14 IRQ_
6399 <GIC_PPI 11 IRQ_
6400 <GIC_PPI 10 IRQ_
6401 };
6402
6403 thermal-zones {
6404 aoss0-thermal {
6405 thermal-sensors = <&t
6406
6407 trips {
6408 trip-point0 {
6409 tempe
6410 hyste
6411 type
6412 };
6413
6414 aoss0-critica
6415 tempe
6416 hyste
6417 type
6418 };
6419 };
6420 };
6421
6422 cpu0-0-top-thermal {
6423 polling-delay-passive
6424
6425 thermal-sensors = <&t
6426
6427 trips {
6428 trip-point0 {
6429 tempe
6430 hyste
6431 type
6432 };
6433
6434 trip-point1 {
6435 tempe
6436 hyste
6437 type
6438 };
6439
6440 cpu-critical
6441 tempe
6442 hyste
6443 type
6444 };
6445 };
6446 };
6447
6448 cpu0-0-btm-thermal {
6449 polling-delay-passive
6450
6451 thermal-sensors = <&t
6452
6453 trips {
6454 trip-point0 {
6455 tempe
6456 hyste
6457 type
6458 };
6459
6460 trip-point1 {
6461 tempe
6462 hyste
6463 type
6464 };
6465
6466 cpu-critical
6467 tempe
6468 hyste
6469 type
6470 };
6471 };
6472 };
6473
6474 cpu0-1-top-thermal {
6475 polling-delay-passive
6476
6477 thermal-sensors = <&t
6478
6479 trips {
6480 trip-point0 {
6481 tempe
6482 hyste
6483 type
6484 };
6485
6486 trip-point1 {
6487 tempe
6488 hyste
6489 type
6490 };
6491
6492 cpu-critical
6493 tempe
6494 hyste
6495 type
6496 };
6497 };
6498 };
6499
6500 cpu0-1-btm-thermal {
6501 polling-delay-passive
6502
6503 thermal-sensors = <&t
6504
6505 trips {
6506 trip-point0 {
6507 tempe
6508 hyste
6509 type
6510 };
6511
6512 trip-point1 {
6513 tempe
6514 hyste
6515 type
6516 };
6517
6518 cpu-critical
6519 tempe
6520 hyste
6521 type
6522 };
6523 };
6524 };
6525
6526 cpu0-2-top-thermal {
6527 polling-delay-passive
6528
6529 thermal-sensors = <&t
6530
6531 trips {
6532 trip-point0 {
6533 tempe
6534 hyste
6535 type
6536 };
6537
6538 trip-point1 {
6539 tempe
6540 hyste
6541 type
6542 };
6543
6544 cpu-critical
6545 tempe
6546 hyste
6547 type
6548 };
6549 };
6550 };
6551
6552 cpu0-2-btm-thermal {
6553 polling-delay-passive
6554
6555 thermal-sensors = <&t
6556
6557 trips {
6558 trip-point0 {
6559 tempe
6560 hyste
6561 type
6562 };
6563
6564 trip-point1 {
6565 tempe
6566 hyste
6567 type
6568 };
6569
6570 cpu-critical
6571 tempe
6572 hyste
6573 type
6574 };
6575 };
6576 };
6577
6578 cpu0-3-top-thermal {
6579 polling-delay-passive
6580
6581 thermal-sensors = <&t
6582
6583 trips {
6584 trip-point0 {
6585 tempe
6586 hyste
6587 type
6588 };
6589
6590 trip-point1 {
6591 tempe
6592 hyste
6593 type
6594 };
6595
6596 cpu-critical
6597 tempe
6598 hyste
6599 type
6600 };
6601 };
6602 };
6603
6604 cpu0-3-btm-thermal {
6605 polling-delay-passive
6606
6607 thermal-sensors = <&t
6608
6609 trips {
6610 trip-point0 {
6611 tempe
6612 hyste
6613 type
6614 };
6615
6616 trip-point1 {
6617 tempe
6618 hyste
6619 type
6620 };
6621
6622 cpu-critical
6623 tempe
6624 hyste
6625 type
6626 };
6627 };
6628 };
6629
6630 cpuss0-top-thermal {
6631 thermal-sensors = <&t
6632
6633 trips {
6634 trip-point0 {
6635 tempe
6636 hyste
6637 type
6638 };
6639
6640 cpuss2-critic
6641 tempe
6642 hyste
6643 type
6644 };
6645 };
6646 };
6647
6648 cpuss0-btm-thermal {
6649 thermal-sensors = <&t
6650
6651 trips {
6652 trip-point0 {
6653 tempe
6654 hyste
6655 type
6656 };
6657
6658 cpuss2-critic
6659 tempe
6660 hyste
6661 type
6662 };
6663 };
6664 };
6665
6666 mem-thermal {
6667 thermal-sensors = <&t
6668
6669 trips {
6670 trip-point0 {
6671 tempe
6672 hyste
6673 type
6674 };
6675
6676 mem-critical
6677 tempe
6678 hyste
6679 type
6680 };
6681 };
6682 };
6683
6684 video-thermal {
6685 polling-delay-passive
6686
6687 thermal-sensors = <&t
6688
6689 trips {
6690 trip-point0 {
6691 tempe
6692 hyste
6693 type
6694 };
6695 };
6696 };
6697
6698 aoss1-thermal {
6699 thermal-sensors = <&t
6700
6701 trips {
6702 trip-point0 {
6703 tempe
6704 hyste
6705 type
6706 };
6707
6708 aoss0-critica
6709 tempe
6710 hyste
6711 type
6712 };
6713 };
6714 };
6715
6716 cpu1-0-top-thermal {
6717 polling-delay-passive
6718
6719 thermal-sensors = <&t
6720
6721 trips {
6722 trip-point0 {
6723 tempe
6724 hyste
6725 type
6726 };
6727
6728 trip-point1 {
6729 tempe
6730 hyste
6731 type
6732 };
6733
6734 cpu-critical
6735 tempe
6736 hyste
6737 type
6738 };
6739 };
6740 };
6741
6742 cpu1-0-btm-thermal {
6743 polling-delay-passive
6744
6745 thermal-sensors = <&t
6746
6747 trips {
6748 trip-point0 {
6749 tempe
6750 hyste
6751 type
6752 };
6753
6754 trip-point1 {
6755 tempe
6756 hyste
6757 type
6758 };
6759
6760 cpu-critical
6761 tempe
6762 hyste
6763 type
6764 };
6765 };
6766 };
6767
6768 cpu1-1-top-thermal {
6769 polling-delay-passive
6770
6771 thermal-sensors = <&t
6772
6773 trips {
6774 trip-point0 {
6775 tempe
6776 hyste
6777 type
6778 };
6779
6780 trip-point1 {
6781 tempe
6782 hyste
6783 type
6784 };
6785
6786 cpu-critical
6787 tempe
6788 hyste
6789 type
6790 };
6791 };
6792 };
6793
6794 cpu1-1-btm-thermal {
6795 polling-delay-passive
6796
6797 thermal-sensors = <&t
6798
6799 trips {
6800 trip-point0 {
6801 tempe
6802 hyste
6803 type
6804 };
6805
6806 trip-point1 {
6807 tempe
6808 hyste
6809 type
6810 };
6811
6812 cpu-critical
6813 tempe
6814 hyste
6815 type
6816 };
6817 };
6818 };
6819
6820 cpu1-2-top-thermal {
6821 polling-delay-passive
6822
6823 thermal-sensors = <&t
6824
6825 trips {
6826 trip-point0 {
6827 tempe
6828 hyste
6829 type
6830 };
6831
6832 trip-point1 {
6833 tempe
6834 hyste
6835 type
6836 };
6837
6838 cpu-critical
6839 tempe
6840 hyste
6841 type
6842 };
6843 };
6844 };
6845
6846 cpu1-2-btm-thermal {
6847 polling-delay-passive
6848
6849 thermal-sensors = <&t
6850
6851 trips {
6852 trip-point0 {
6853 tempe
6854 hyste
6855 type
6856 };
6857
6858 trip-point1 {
6859 tempe
6860 hyste
6861 type
6862 };
6863
6864 cpu-critical
6865 tempe
6866 hyste
6867 type
6868 };
6869 };
6870 };
6871
6872 cpu1-3-top-thermal {
6873 polling-delay-passive
6874
6875 thermal-sensors = <&t
6876
6877 trips {
6878 trip-point0 {
6879 tempe
6880 hyste
6881 type
6882 };
6883
6884 trip-point1 {
6885 tempe
6886 hyste
6887 type
6888 };
6889
6890 cpu-critical
6891 tempe
6892 hyste
6893 type
6894 };
6895 };
6896 };
6897
6898 cpu1-3-btm-thermal {
6899 polling-delay-passive
6900
6901 thermal-sensors = <&t
6902
6903 trips {
6904 trip-point0 {
6905 tempe
6906 hyste
6907 type
6908 };
6909
6910 trip-point1 {
6911 tempe
6912 hyste
6913 type
6914 };
6915
6916 cpu-critical
6917 tempe
6918 hyste
6919 type
6920 };
6921 };
6922 };
6923
6924 cpuss1-top-thermal {
6925 thermal-sensors = <&t
6926
6927 trips {
6928 trip-point0 {
6929 tempe
6930 hyste
6931 type
6932 };
6933
6934 cpuss2-critic
6935 tempe
6936 hyste
6937 type
6938 };
6939 };
6940 };
6941
6942 cpuss1-btm-thermal {
6943 thermal-sensors = <&t
6944
6945 trips {
6946 trip-point0 {
6947 tempe
6948 hyste
6949 type
6950 };
6951
6952 cpuss2-critic
6953 tempe
6954 hyste
6955 type
6956 };
6957 };
6958 };
6959
6960 aoss2-thermal {
6961 thermal-sensors = <&t
6962
6963 trips {
6964 trip-point0 {
6965 tempe
6966 hyste
6967 type
6968 };
6969
6970 aoss0-critica
6971 tempe
6972 hyste
6973 type
6974 };
6975 };
6976 };
6977
6978 cpu2-0-top-thermal {
6979 polling-delay-passive
6980
6981 thermal-sensors = <&t
6982
6983 trips {
6984 trip-point0 {
6985 tempe
6986 hyste
6987 type
6988 };
6989
6990 trip-point1 {
6991 tempe
6992 hyste
6993 type
6994 };
6995
6996 cpu-critical
6997 tempe
6998 hyste
6999 type
7000 };
7001 };
7002 };
7003
7004 cpu2-0-btm-thermal {
7005 polling-delay-passive
7006
7007 thermal-sensors = <&t
7008
7009 trips {
7010 trip-point0 {
7011 tempe
7012 hyste
7013 type
7014 };
7015
7016 trip-point1 {
7017 tempe
7018 hyste
7019 type
7020 };
7021
7022 cpu-critical
7023 tempe
7024 hyste
7025 type
7026 };
7027 };
7028 };
7029
7030 cpu2-1-top-thermal {
7031 polling-delay-passive
7032
7033 thermal-sensors = <&t
7034
7035 trips {
7036 trip-point0 {
7037 tempe
7038 hyste
7039 type
7040 };
7041
7042 trip-point1 {
7043 tempe
7044 hyste
7045 type
7046 };
7047
7048 cpu-critical
7049 tempe
7050 hyste
7051 type
7052 };
7053 };
7054 };
7055
7056 cpu2-1-btm-thermal {
7057 polling-delay-passive
7058
7059 thermal-sensors = <&t
7060
7061 trips {
7062 trip-point0 {
7063 tempe
7064 hyste
7065 type
7066 };
7067
7068 trip-point1 {
7069 tempe
7070 hyste
7071 type
7072 };
7073
7074 cpu-critical
7075 tempe
7076 hyste
7077 type
7078 };
7079 };
7080 };
7081
7082 cpu2-2-top-thermal {
7083 polling-delay-passive
7084
7085 thermal-sensors = <&t
7086
7087 trips {
7088 trip-point0 {
7089 tempe
7090 hyste
7091 type
7092 };
7093
7094 trip-point1 {
7095 tempe
7096 hyste
7097 type
7098 };
7099
7100 cpu-critical
7101 tempe
7102 hyste
7103 type
7104 };
7105 };
7106 };
7107
7108 cpu2-2-btm-thermal {
7109 polling-delay-passive
7110
7111 thermal-sensors = <&t
7112
7113 trips {
7114 trip-point0 {
7115 tempe
7116 hyste
7117 type
7118 };
7119
7120 trip-point1 {
7121 tempe
7122 hyste
7123 type
7124 };
7125
7126 cpu-critical
7127 tempe
7128 hyste
7129 type
7130 };
7131 };
7132 };
7133
7134 cpu2-3-top-thermal {
7135 polling-delay-passive
7136
7137 thermal-sensors = <&t
7138
7139 trips {
7140 trip-point0 {
7141 tempe
7142 hyste
7143 type
7144 };
7145
7146 trip-point1 {
7147 tempe
7148 hyste
7149 type
7150 };
7151
7152 cpu-critical
7153 tempe
7154 hyste
7155 type
7156 };
7157 };
7158 };
7159
7160 cpu2-3-btm-thermal {
7161 polling-delay-passive
7162
7163 thermal-sensors = <&t
7164
7165 trips {
7166 trip-point0 {
7167 tempe
7168 hyste
7169 type
7170 };
7171
7172 trip-point1 {
7173 tempe
7174 hyste
7175 type
7176 };
7177
7178 cpu-critical
7179 tempe
7180 hyste
7181 type
7182 };
7183 };
7184 };
7185
7186 cpuss2-top-thermal {
7187 thermal-sensors = <&t
7188
7189 trips {
7190 trip-point0 {
7191 tempe
7192 hyste
7193 type
7194 };
7195
7196 cpuss2-critic
7197 tempe
7198 hyste
7199 type
7200 };
7201 };
7202 };
7203
7204 cpuss2-btm-thermal {
7205 thermal-sensors = <&t
7206
7207 trips {
7208 trip-point0 {
7209 tempe
7210 hyste
7211 type
7212 };
7213
7214 cpuss2-critic
7215 tempe
7216 hyste
7217 type
7218 };
7219 };
7220 };
7221
7222 aoss3-thermal {
7223 thermal-sensors = <&t
7224
7225 trips {
7226 trip-point0 {
7227 tempe
7228 hyste
7229 type
7230 };
7231
7232 aoss0-critica
7233 tempe
7234 hyste
7235 type
7236 };
7237 };
7238 };
7239
7240 nsp0-thermal {
7241 thermal-sensors = <&t
7242
7243 trips {
7244 trip-point0 {
7245 tempe
7246 hyste
7247 type
7248 };
7249
7250 nsp0-critical
7251 tempe
7252 hyste
7253 type
7254 };
7255 };
7256 };
7257
7258 nsp1-thermal {
7259 thermal-sensors = <&t
7260
7261 trips {
7262 trip-point0 {
7263 tempe
7264 hyste
7265 type
7266 };
7267
7268 nsp1-critical
7269 tempe
7270 hyste
7271 type
7272 };
7273 };
7274 };
7275
7276 nsp2-thermal {
7277 thermal-sensors = <&t
7278
7279 trips {
7280 trip-point0 {
7281 tempe
7282 hyste
7283 type
7284 };
7285
7286 nsp2-critical
7287 tempe
7288 hyste
7289 type
7290 };
7291 };
7292 };
7293
7294 nsp3-thermal {
7295 thermal-sensors = <&t
7296
7297 trips {
7298 trip-point0 {
7299 tempe
7300 hyste
7301 type
7302 };
7303
7304 nsp3-critical
7305 tempe
7306 hyste
7307 type
7308 };
7309 };
7310 };
7311
7312 gpuss-0-thermal {
7313 polling-delay-passive
7314
7315 thermal-sensors = <&t
7316
7317 trips {
7318 trip-point0 {
7319 tempe
7320 hyste
7321 type
7322 };
7323
7324 trip-point1 {
7325 tempe
7326 hyste
7327 type
7328 };
7329
7330 trip-point2 {
7331 tempe
7332 hyste
7333 type
7334 };
7335 };
7336 };
7337
7338 gpuss-1-thermal {
7339 polling-delay-passive
7340
7341 thermal-sensors = <&t
7342
7343 trips {
7344 trip-point0 {
7345 tempe
7346 hyste
7347 type
7348 };
7349
7350 trip-point1 {
7351 tempe
7352 hyste
7353 type
7354 };
7355
7356 trip-point2 {
7357 tempe
7358 hyste
7359 type
7360 };
7361 };
7362 };
7363
7364 gpuss-2-thermal {
7365 polling-delay-passive
7366
7367 thermal-sensors = <&t
7368
7369 trips {
7370 trip-point0 {
7371 tempe
7372 hyste
7373 type
7374 };
7375
7376 trip-point1 {
7377 tempe
7378 hyste
7379 type
7380 };
7381
7382 trip-point2 {
7383 tempe
7384 hyste
7385 type
7386 };
7387 };
7388 };
7389
7390 gpuss-3-thermal {
7391 polling-delay-passive
7392
7393 thermal-sensors = <&t
7394
7395 trips {
7396 trip-point0 {
7397 tempe
7398 hyste
7399 type
7400 };
7401
7402 trip-point1 {
7403 tempe
7404 hyste
7405 type
7406 };
7407
7408 trip-point2 {
7409 tempe
7410 hyste
7411 type
7412 };
7413 };
7414 };
7415
7416 gpuss-4-thermal {
7417 polling-delay-passive
7418
7419 thermal-sensors = <&t
7420
7421 trips {
7422 trip-point0 {
7423 tempe
7424 hyste
7425 type
7426 };
7427
7428 trip-point1 {
7429 tempe
7430 hyste
7431 type
7432 };
7433
7434 trip-point2 {
7435 tempe
7436 hyste
7437 type
7438 };
7439 };
7440 };
7441
7442 gpuss-5-thermal {
7443 polling-delay-passive
7444
7445 thermal-sensors = <&t
7446
7447 trips {
7448 trip-point0 {
7449 tempe
7450 hyste
7451 type
7452 };
7453
7454 trip-point1 {
7455 tempe
7456 hyste
7457 type
7458 };
7459
7460 trip-point2 {
7461 tempe
7462 hyste
7463 type
7464 };
7465 };
7466 };
7467
7468 gpuss-6-thermal {
7469 polling-delay-passive
7470
7471 thermal-sensors = <&t
7472
7473 trips {
7474 trip-point0 {
7475 tempe
7476 hyste
7477 type
7478 };
7479
7480 trip-point1 {
7481 tempe
7482 hyste
7483 type
7484 };
7485
7486 trip-point2 {
7487 tempe
7488 hyste
7489 type
7490 };
7491 };
7492 };
7493
7494 gpuss-7-thermal {
7495 polling-delay-passive
7496
7497 thermal-sensors = <&t
7498
7499 trips {
7500 trip-point0 {
7501 tempe
7502 hyste
7503 type
7504 };
7505
7506 trip-point1 {
7507 tempe
7508 hyste
7509 type
7510 };
7511
7512 trip-point2 {
7513 tempe
7514 hyste
7515 type
7516 };
7517 };
7518 };
7519
7520 camera0-thermal {
7521 thermal-sensors = <&t
7522
7523 trips {
7524 trip-point0 {
7525 tempe
7526 hyste
7527 type
7528 };
7529
7530 camera0-criti
7531 tempe
7532 hyste
7533 type
7534 };
7535 };
7536 };
7537
7538 camera1-thermal {
7539 thermal-sensors = <&t
7540
7541 trips {
7542 trip-point0 {
7543 tempe
7544 hyste
7545 type
7546 };
7547
7548 camera0-criti
7549 tempe
7550 hyste
7551 type
7552 };
7553 };
7554 };
7555 };
7556 };
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