1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * Copyright (c) 2023 Qualcomm Innovation Cent 3 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
4 */ 4 */
5 5
6 #include <dt-bindings/clock/qcom,rpmh.h> 6 #include <dt-bindings/clock/qcom,rpmh.h>
7 #include <dt-bindings/clock/qcom,sc8280xp-lpas 7 #include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
8 #include <dt-bindings/clock/qcom,x1e80100-disp 8 #include <dt-bindings/clock/qcom,x1e80100-dispcc.h>
9 #include <dt-bindings/clock/qcom,x1e80100-gcc. 9 #include <dt-bindings/clock/qcom,x1e80100-gcc.h>
10 #include <dt-bindings/clock/qcom,x1e80100-gpuc 10 #include <dt-bindings/clock/qcom,x1e80100-gpucc.h>
11 #include <dt-bindings/clock/qcom,x1e80100-tcsr 11 #include <dt-bindings/clock/qcom,x1e80100-tcsr.h>
12 #include <dt-bindings/dma/qcom-gpi.h> 12 #include <dt-bindings/dma/qcom-gpi.h>
13 #include <dt-bindings/interconnect/qcom,icc.h> 13 #include <dt-bindings/interconnect/qcom,icc.h>
14 #include <dt-bindings/interconnect/qcom,x1e801 14 #include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h>
15 #include <dt-bindings/interrupt-controller/arm 15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/mailbox/qcom-ipcc.h> 16 #include <dt-bindings/mailbox/qcom-ipcc.h>
17 #include <dt-bindings/phy/phy-qcom-qmp.h> 17 #include <dt-bindings/phy/phy-qcom-qmp.h>
18 #include <dt-bindings/power/qcom,rpmhpd.h> 18 #include <dt-bindings/power/qcom,rpmhpd.h>
19 #include <dt-bindings/power/qcom-rpmpd.h> 19 #include <dt-bindings/power/qcom-rpmpd.h>
20 #include <dt-bindings/soc/qcom,gpr.h> 20 #include <dt-bindings/soc/qcom,gpr.h>
21 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 21 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
22 #include <dt-bindings/sound/qcom,q6dsp-lpass-p 22 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
23 23
24 / { 24 / {
25 interrupt-parent = <&intc>; 25 interrupt-parent = <&intc>;
26 26
27 #address-cells = <2>; 27 #address-cells = <2>;
28 #size-cells = <2>; 28 #size-cells = <2>;
29 29
30 chosen { }; 30 chosen { };
31 31
32 clocks { 32 clocks {
33 xo_board: xo-board { 33 xo_board: xo-board {
34 compatible = "fixed-cl 34 compatible = "fixed-clock";
35 clock-frequency = <768 35 clock-frequency = <76800000>;
36 #clock-cells = <0>; 36 #clock-cells = <0>;
37 }; 37 };
38 38
39 sleep_clk: sleep-clk { 39 sleep_clk: sleep-clk {
40 compatible = "fixed-cl 40 compatible = "fixed-clock";
41 clock-frequency = <320 41 clock-frequency = <32000>;
42 #clock-cells = <0>; 42 #clock-cells = <0>;
43 }; 43 };
44 44
45 bi_tcxo_div2: bi-tcxo-div2-clk 45 bi_tcxo_div2: bi-tcxo-div2-clk {
46 compatible = "fixed-fa 46 compatible = "fixed-factor-clock";
47 #clock-cells = <0>; 47 #clock-cells = <0>;
48 48
49 clocks = <&rpmhcc RPMH 49 clocks = <&rpmhcc RPMH_CXO_CLK>;
50 clock-mult = <1>; 50 clock-mult = <1>;
51 clock-div = <2>; 51 clock-div = <2>;
52 }; 52 };
53 53
54 bi_tcxo_ao_div2: bi-tcxo-ao-di 54 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
55 compatible = "fixed-fa 55 compatible = "fixed-factor-clock";
56 #clock-cells = <0>; 56 #clock-cells = <0>;
57 57
58 clocks = <&rpmhcc RPMH 58 clocks = <&rpmhcc RPMH_CXO_CLK_A>;
59 clock-mult = <1>; 59 clock-mult = <1>;
60 clock-div = <2>; 60 clock-div = <2>;
61 }; 61 };
62 }; 62 };
63 63
64 cpus { 64 cpus {
65 #address-cells = <2>; 65 #address-cells = <2>;
66 #size-cells = <0>; 66 #size-cells = <0>;
67 67
68 CPU0: cpu@0 { 68 CPU0: cpu@0 {
69 device_type = "cpu"; 69 device_type = "cpu";
70 compatible = "qcom,ory 70 compatible = "qcom,oryon";
71 reg = <0x0 0x0>; 71 reg = <0x0 0x0>;
72 enable-method = "psci" 72 enable-method = "psci";
73 next-level-cache = <&L 73 next-level-cache = <&L2_0>;
74 power-domains = <&CPU_ 74 power-domains = <&CPU_PD0>;
75 power-domain-names = " 75 power-domain-names = "psci";
76 cpu-idle-states = <&CL 76 cpu-idle-states = <&CLUSTER_C4>;
77 77
78 L2_0: l2-cache { 78 L2_0: l2-cache {
79 compatible = " 79 compatible = "cache";
80 cache-level = 80 cache-level = <2>;
81 cache-unified; 81 cache-unified;
82 }; 82 };
83 }; 83 };
84 84
85 CPU1: cpu@100 { 85 CPU1: cpu@100 {
86 device_type = "cpu"; 86 device_type = "cpu";
87 compatible = "qcom,ory 87 compatible = "qcom,oryon";
88 reg = <0x0 0x100>; 88 reg = <0x0 0x100>;
89 enable-method = "psci" 89 enable-method = "psci";
90 next-level-cache = <&L 90 next-level-cache = <&L2_0>;
91 power-domains = <&CPU_ 91 power-domains = <&CPU_PD1>;
92 power-domain-names = " 92 power-domain-names = "psci";
93 cpu-idle-states = <&CL 93 cpu-idle-states = <&CLUSTER_C4>;
94 }; 94 };
95 95
96 CPU2: cpu@200 { 96 CPU2: cpu@200 {
97 device_type = "cpu"; 97 device_type = "cpu";
98 compatible = "qcom,ory 98 compatible = "qcom,oryon";
99 reg = <0x0 0x200>; 99 reg = <0x0 0x200>;
100 enable-method = "psci" 100 enable-method = "psci";
101 next-level-cache = <&L 101 next-level-cache = <&L2_0>;
102 power-domains = <&CPU_ 102 power-domains = <&CPU_PD2>;
103 power-domain-names = " 103 power-domain-names = "psci";
104 cpu-idle-states = <&CL 104 cpu-idle-states = <&CLUSTER_C4>;
105 }; 105 };
106 106
107 CPU3: cpu@300 { 107 CPU3: cpu@300 {
108 device_type = "cpu"; 108 device_type = "cpu";
109 compatible = "qcom,ory 109 compatible = "qcom,oryon";
110 reg = <0x0 0x300>; 110 reg = <0x0 0x300>;
111 enable-method = "psci" 111 enable-method = "psci";
112 next-level-cache = <&L 112 next-level-cache = <&L2_0>;
113 power-domains = <&CPU_ 113 power-domains = <&CPU_PD3>;
114 power-domain-names = " 114 power-domain-names = "psci";
115 cpu-idle-states = <&CL 115 cpu-idle-states = <&CLUSTER_C4>;
116 }; 116 };
117 117
118 CPU4: cpu@10000 { 118 CPU4: cpu@10000 {
119 device_type = "cpu"; 119 device_type = "cpu";
120 compatible = "qcom,ory 120 compatible = "qcom,oryon";
121 reg = <0x0 0x10000>; 121 reg = <0x0 0x10000>;
122 enable-method = "psci" 122 enable-method = "psci";
123 next-level-cache = <&L 123 next-level-cache = <&L2_1>;
124 power-domains = <&CPU_ 124 power-domains = <&CPU_PD4>;
125 power-domain-names = " 125 power-domain-names = "psci";
126 cpu-idle-states = <&CL 126 cpu-idle-states = <&CLUSTER_C4>;
127 127
128 L2_1: l2-cache { 128 L2_1: l2-cache {
129 compatible = " 129 compatible = "cache";
130 cache-level = 130 cache-level = <2>;
131 cache-unified; 131 cache-unified;
132 }; 132 };
133 }; 133 };
134 134
135 CPU5: cpu@10100 { 135 CPU5: cpu@10100 {
136 device_type = "cpu"; 136 device_type = "cpu";
137 compatible = "qcom,ory 137 compatible = "qcom,oryon";
138 reg = <0x0 0x10100>; 138 reg = <0x0 0x10100>;
139 enable-method = "psci" 139 enable-method = "psci";
140 next-level-cache = <&L 140 next-level-cache = <&L2_1>;
141 power-domains = <&CPU_ 141 power-domains = <&CPU_PD5>;
142 power-domain-names = " 142 power-domain-names = "psci";
143 cpu-idle-states = <&CL 143 cpu-idle-states = <&CLUSTER_C4>;
144 }; 144 };
145 145
146 CPU6: cpu@10200 { 146 CPU6: cpu@10200 {
147 device_type = "cpu"; 147 device_type = "cpu";
148 compatible = "qcom,ory 148 compatible = "qcom,oryon";
149 reg = <0x0 0x10200>; 149 reg = <0x0 0x10200>;
150 enable-method = "psci" 150 enable-method = "psci";
151 next-level-cache = <&L 151 next-level-cache = <&L2_1>;
152 power-domains = <&CPU_ 152 power-domains = <&CPU_PD6>;
153 power-domain-names = " 153 power-domain-names = "psci";
154 cpu-idle-states = <&CL 154 cpu-idle-states = <&CLUSTER_C4>;
155 }; 155 };
156 156
157 CPU7: cpu@10300 { 157 CPU7: cpu@10300 {
158 device_type = "cpu"; 158 device_type = "cpu";
159 compatible = "qcom,ory 159 compatible = "qcom,oryon";
160 reg = <0x0 0x10300>; 160 reg = <0x0 0x10300>;
161 enable-method = "psci" 161 enable-method = "psci";
162 next-level-cache = <&L 162 next-level-cache = <&L2_1>;
163 power-domains = <&CPU_ 163 power-domains = <&CPU_PD7>;
164 power-domain-names = " 164 power-domain-names = "psci";
165 cpu-idle-states = <&CL 165 cpu-idle-states = <&CLUSTER_C4>;
166 }; 166 };
167 167
168 CPU8: cpu@20000 { 168 CPU8: cpu@20000 {
169 device_type = "cpu"; 169 device_type = "cpu";
170 compatible = "qcom,ory 170 compatible = "qcom,oryon";
171 reg = <0x0 0x20000>; 171 reg = <0x0 0x20000>;
172 enable-method = "psci" 172 enable-method = "psci";
173 next-level-cache = <&L 173 next-level-cache = <&L2_2>;
174 power-domains = <&CPU_ 174 power-domains = <&CPU_PD8>;
175 power-domain-names = " 175 power-domain-names = "psci";
176 cpu-idle-states = <&CL 176 cpu-idle-states = <&CLUSTER_C4>;
177 177
178 L2_2: l2-cache { 178 L2_2: l2-cache {
179 compatible = " 179 compatible = "cache";
180 cache-level = 180 cache-level = <2>;
181 cache-unified; 181 cache-unified;
182 }; 182 };
183 }; 183 };
184 184
185 CPU9: cpu@20100 { 185 CPU9: cpu@20100 {
186 device_type = "cpu"; 186 device_type = "cpu";
187 compatible = "qcom,ory 187 compatible = "qcom,oryon";
188 reg = <0x0 0x20100>; 188 reg = <0x0 0x20100>;
189 enable-method = "psci" 189 enable-method = "psci";
190 next-level-cache = <&L 190 next-level-cache = <&L2_2>;
191 power-domains = <&CPU_ 191 power-domains = <&CPU_PD9>;
192 power-domain-names = " 192 power-domain-names = "psci";
193 cpu-idle-states = <&CL 193 cpu-idle-states = <&CLUSTER_C4>;
194 }; 194 };
195 195
196 CPU10: cpu@20200 { 196 CPU10: cpu@20200 {
197 device_type = "cpu"; 197 device_type = "cpu";
198 compatible = "qcom,ory 198 compatible = "qcom,oryon";
199 reg = <0x0 0x20200>; 199 reg = <0x0 0x20200>;
200 enable-method = "psci" 200 enable-method = "psci";
201 next-level-cache = <&L 201 next-level-cache = <&L2_2>;
202 power-domains = <&CPU_ 202 power-domains = <&CPU_PD10>;
203 power-domain-names = " 203 power-domain-names = "psci";
204 cpu-idle-states = <&CL 204 cpu-idle-states = <&CLUSTER_C4>;
205 }; 205 };
206 206
207 CPU11: cpu@20300 { 207 CPU11: cpu@20300 {
208 device_type = "cpu"; 208 device_type = "cpu";
209 compatible = "qcom,ory 209 compatible = "qcom,oryon";
210 reg = <0x0 0x20300>; 210 reg = <0x0 0x20300>;
211 enable-method = "psci" 211 enable-method = "psci";
212 next-level-cache = <&L 212 next-level-cache = <&L2_2>;
213 power-domains = <&CPU_ 213 power-domains = <&CPU_PD11>;
214 power-domain-names = " 214 power-domain-names = "psci";
215 cpu-idle-states = <&CL 215 cpu-idle-states = <&CLUSTER_C4>;
216 }; 216 };
217 217
218 cpu-map { 218 cpu-map {
219 cluster0 { 219 cluster0 {
220 core0 { 220 core0 {
221 cpu = 221 cpu = <&CPU0>;
222 }; 222 };
223 223
224 core1 { 224 core1 {
225 cpu = 225 cpu = <&CPU1>;
226 }; 226 };
227 227
228 core2 { 228 core2 {
229 cpu = 229 cpu = <&CPU2>;
230 }; 230 };
231 231
232 core3 { 232 core3 {
233 cpu = 233 cpu = <&CPU3>;
234 }; 234 };
235 }; 235 };
236 236
237 cluster1 { 237 cluster1 {
238 core0 { 238 core0 {
239 cpu = 239 cpu = <&CPU4>;
240 }; 240 };
241 241
242 core1 { 242 core1 {
243 cpu = 243 cpu = <&CPU5>;
244 }; 244 };
245 245
246 core2 { 246 core2 {
247 cpu = 247 cpu = <&CPU6>;
248 }; 248 };
249 249
250 core3 { 250 core3 {
251 cpu = 251 cpu = <&CPU7>;
252 }; 252 };
253 }; 253 };
254 254
255 cluster2 { 255 cluster2 {
256 core0 { 256 core0 {
257 cpu = 257 cpu = <&CPU8>;
258 }; 258 };
259 259
260 core1 { 260 core1 {
261 cpu = 261 cpu = <&CPU9>;
262 }; 262 };
263 263
264 core2 { 264 core2 {
265 cpu = 265 cpu = <&CPU10>;
266 }; 266 };
267 267
268 core3 { 268 core3 {
269 cpu = 269 cpu = <&CPU11>;
270 }; 270 };
271 }; 271 };
272 }; 272 };
273 273
274 idle-states { 274 idle-states {
275 entry-method = "psci"; 275 entry-method = "psci";
276 276
277 CLUSTER_C4: cpu-sleep- 277 CLUSTER_C4: cpu-sleep-0 {
278 compatible = " 278 compatible = "arm,idle-state";
279 idle-state-nam 279 idle-state-name = "ret";
280 arm,psci-suspe 280 arm,psci-suspend-param = <0x00000004>;
281 entry-latency- 281 entry-latency-us = <180>;
282 exit-latency-u 282 exit-latency-us = <320>;
283 min-residency- 283 min-residency-us = <1000>;
284 }; 284 };
285 }; 285 };
286 286
287 domain-idle-states { 287 domain-idle-states {
288 CLUSTER_CL4: cluster-s 288 CLUSTER_CL4: cluster-sleep-0 {
289 compatible = " 289 compatible = "domain-idle-state";
290 idle-state-nam 290 idle-state-name = "l2-ret";
291 arm,psci-suspe 291 arm,psci-suspend-param = <0x01000044>;
292 entry-latency- 292 entry-latency-us = <350>;
293 exit-latency-u 293 exit-latency-us = <500>;
294 min-residency- 294 min-residency-us = <2500>;
295 }; 295 };
296 296
297 CLUSTER_CL5: cluster-s 297 CLUSTER_CL5: cluster-sleep-1 {
298 compatible = " 298 compatible = "domain-idle-state";
299 idle-state-nam 299 idle-state-name = "ret-pll-off";
300 arm,psci-suspe 300 arm,psci-suspend-param = <0x01000054>;
301 entry-latency- 301 entry-latency-us = <2200>;
302 exit-latency-u 302 exit-latency-us = <2500>;
303 min-residency- 303 min-residency-us = <7000>;
304 }; 304 };
305 }; 305 };
306 }; 306 };
307 307
308 firmware { 308 firmware {
309 scm: scm { 309 scm: scm {
310 compatible = "qcom,scm 310 compatible = "qcom,scm-x1e80100", "qcom,scm";
311 interconnects = <&aggr 311 interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS
312 &mc_v 312 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
313 }; 313 };
314 }; 314 };
315 315
316 clk_virt: interconnect-0 { 316 clk_virt: interconnect-0 {
317 compatible = "qcom,x1e80100-cl 317 compatible = "qcom,x1e80100-clk-virt";
318 #interconnect-cells = <2>; 318 #interconnect-cells = <2>;
319 qcom,bcm-voters = <&apps_bcm_v 319 qcom,bcm-voters = <&apps_bcm_voter>;
320 }; 320 };
321 321
322 mc_virt: interconnect-1 { 322 mc_virt: interconnect-1 {
323 compatible = "qcom,x1e80100-mc 323 compatible = "qcom,x1e80100-mc-virt";
324 #interconnect-cells = <2>; 324 #interconnect-cells = <2>;
325 qcom,bcm-voters = <&apps_bcm_v 325 qcom,bcm-voters = <&apps_bcm_voter>;
326 }; 326 };
327 327
328 memory@80000000 { 328 memory@80000000 {
329 device_type = "memory"; 329 device_type = "memory";
330 /* We expect the bootloader to 330 /* We expect the bootloader to fill in the size */
331 reg = <0 0x80000000 0 0>; 331 reg = <0 0x80000000 0 0>;
332 }; 332 };
333 333
334 pmu { 334 pmu {
335 compatible = "arm,armv8-pmuv3" 335 compatible = "arm,armv8-pmuv3";
336 interrupts = <GIC_PPI 7 IRQ_TY 336 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
337 }; 337 };
338 338
339 psci { 339 psci {
340 compatible = "arm,psci-1.0"; 340 compatible = "arm,psci-1.0";
341 method = "smc"; 341 method = "smc";
342 342
343 CPU_PD0: power-domain-cpu0 { 343 CPU_PD0: power-domain-cpu0 {
344 #power-domain-cells = 344 #power-domain-cells = <0>;
345 power-domains = <&CLUS 345 power-domains = <&CLUSTER_PD0>;
346 }; 346 };
347 347
348 CPU_PD1: power-domain-cpu1 { 348 CPU_PD1: power-domain-cpu1 {
349 #power-domain-cells = 349 #power-domain-cells = <0>;
350 power-domains = <&CLUS 350 power-domains = <&CLUSTER_PD0>;
351 }; 351 };
352 352
353 CPU_PD2: power-domain-cpu2 { 353 CPU_PD2: power-domain-cpu2 {
354 #power-domain-cells = 354 #power-domain-cells = <0>;
355 power-domains = <&CLUS 355 power-domains = <&CLUSTER_PD0>;
356 }; 356 };
357 357
358 CPU_PD3: power-domain-cpu3 { 358 CPU_PD3: power-domain-cpu3 {
359 #power-domain-cells = 359 #power-domain-cells = <0>;
360 power-domains = <&CLUS 360 power-domains = <&CLUSTER_PD0>;
361 }; 361 };
362 362
363 CPU_PD4: power-domain-cpu4 { 363 CPU_PD4: power-domain-cpu4 {
364 #power-domain-cells = 364 #power-domain-cells = <0>;
365 power-domains = <&CLUS 365 power-domains = <&CLUSTER_PD1>;
366 }; 366 };
367 367
368 CPU_PD5: power-domain-cpu5 { 368 CPU_PD5: power-domain-cpu5 {
369 #power-domain-cells = 369 #power-domain-cells = <0>;
370 power-domains = <&CLUS 370 power-domains = <&CLUSTER_PD1>;
371 }; 371 };
372 372
373 CPU_PD6: power-domain-cpu6 { 373 CPU_PD6: power-domain-cpu6 {
374 #power-domain-cells = 374 #power-domain-cells = <0>;
375 power-domains = <&CLUS 375 power-domains = <&CLUSTER_PD1>;
376 }; 376 };
377 377
378 CPU_PD7: power-domain-cpu7 { 378 CPU_PD7: power-domain-cpu7 {
379 #power-domain-cells = 379 #power-domain-cells = <0>;
380 power-domains = <&CLUS 380 power-domains = <&CLUSTER_PD1>;
381 }; 381 };
382 382
383 CPU_PD8: power-domain-cpu8 { 383 CPU_PD8: power-domain-cpu8 {
384 #power-domain-cells = 384 #power-domain-cells = <0>;
385 power-domains = <&CLUS 385 power-domains = <&CLUSTER_PD2>;
386 }; 386 };
387 387
388 CPU_PD9: power-domain-cpu9 { 388 CPU_PD9: power-domain-cpu9 {
389 #power-domain-cells = 389 #power-domain-cells = <0>;
390 power-domains = <&CLUS 390 power-domains = <&CLUSTER_PD2>;
391 }; 391 };
392 392
393 CPU_PD10: power-domain-cpu10 { 393 CPU_PD10: power-domain-cpu10 {
394 #power-domain-cells = 394 #power-domain-cells = <0>;
395 power-domains = <&CLUS 395 power-domains = <&CLUSTER_PD2>;
396 }; 396 };
397 397
398 CPU_PD11: power-domain-cpu11 { 398 CPU_PD11: power-domain-cpu11 {
399 #power-domain-cells = 399 #power-domain-cells = <0>;
400 power-domains = <&CLUS 400 power-domains = <&CLUSTER_PD2>;
401 }; 401 };
402 402
403 CLUSTER_PD0: power-domain-cpu- 403 CLUSTER_PD0: power-domain-cpu-cluster0 {
404 #power-domain-cells = 404 #power-domain-cells = <0>;
405 domain-idle-states = < 405 domain-idle-states = <&CLUSTER_CL4>, <&CLUSTER_CL5>;
406 power-domains = <&SYST 406 power-domains = <&SYSTEM_PD>;
407 }; 407 };
408 408
409 CLUSTER_PD1: power-domain-cpu- 409 CLUSTER_PD1: power-domain-cpu-cluster1 {
410 #power-domain-cells = 410 #power-domain-cells = <0>;
411 domain-idle-states = < 411 domain-idle-states = <&CLUSTER_CL4>, <&CLUSTER_CL5>;
412 power-domains = <&SYST 412 power-domains = <&SYSTEM_PD>;
413 }; 413 };
414 414
415 CLUSTER_PD2: power-domain-cpu- 415 CLUSTER_PD2: power-domain-cpu-cluster2 {
416 #power-domain-cells = 416 #power-domain-cells = <0>;
417 domain-idle-states = < 417 domain-idle-states = <&CLUSTER_CL4>, <&CLUSTER_CL5>;
418 power-domains = <&SYST 418 power-domains = <&SYSTEM_PD>;
419 }; 419 };
420 420
421 SYSTEM_PD: power-domain-system 421 SYSTEM_PD: power-domain-system {
422 #power-domain-cells = 422 #power-domain-cells = <0>;
423 /* TODO: system-wide i 423 /* TODO: system-wide idle states */
424 }; 424 };
425 }; 425 };
426 426
427 reserved-memory { 427 reserved-memory {
428 #address-cells = <2>; 428 #address-cells = <2>;
429 #size-cells = <2>; 429 #size-cells = <2>;
430 ranges; 430 ranges;
431 431
432 gunyah_hyp_mem: gunyah-hyp@800 432 gunyah_hyp_mem: gunyah-hyp@80000000 {
433 reg = <0x0 0x80000000 433 reg = <0x0 0x80000000 0x0 0x800000>;
434 no-map; 434 no-map;
435 }; 435 };
436 436
437 hyp_elf_package_mem: hyp-elf-p 437 hyp_elf_package_mem: hyp-elf-package@80800000 {
438 reg = <0x0 0x80800000 438 reg = <0x0 0x80800000 0x0 0x200000>;
439 no-map; 439 no-map;
440 }; 440 };
441 441
442 ncc_mem: ncc@80a00000 { 442 ncc_mem: ncc@80a00000 {
443 reg = <0x0 0x80a00000 443 reg = <0x0 0x80a00000 0x0 0x400000>;
444 no-map; 444 no-map;
445 }; 445 };
446 446
447 cpucp_log_mem: cpucp-log@80e00 447 cpucp_log_mem: cpucp-log@80e00000 {
448 reg = <0x0 0x80e00000 448 reg = <0x0 0x80e00000 0x0 0x40000>;
449 no-map; 449 no-map;
450 }; 450 };
451 451
452 cpucp_mem: cpucp@80e40000 { 452 cpucp_mem: cpucp@80e40000 {
453 reg = <0x0 0x80e40000 453 reg = <0x0 0x80e40000 0x0 0x540000>;
454 no-map; 454 no-map;
455 }; 455 };
456 456
457 reserved-region@81380000 { 457 reserved-region@81380000 {
458 reg = <0x0 0x81380000 458 reg = <0x0 0x81380000 0x0 0x80000>;
459 no-map; 459 no-map;
460 }; 460 };
461 461
462 tags_mem: tags-region@81400000 462 tags_mem: tags-region@81400000 {
463 reg = <0x0 0x81400000 463 reg = <0x0 0x81400000 0x0 0x1a0000>;
464 no-map; 464 no-map;
465 }; 465 };
466 466
467 xbl_dtlog_mem: xbl-dtlog@81a00 467 xbl_dtlog_mem: xbl-dtlog@81a00000 {
468 reg = <0x0 0x81a00000 468 reg = <0x0 0x81a00000 0x0 0x40000>;
469 no-map; 469 no-map;
470 }; 470 };
471 471
472 xbl_ramdump_mem: xbl-ramdump@8 472 xbl_ramdump_mem: xbl-ramdump@81a40000 {
473 reg = <0x0 0x81a40000 473 reg = <0x0 0x81a40000 0x0 0x1c0000>;
474 no-map; 474 no-map;
475 }; 475 };
476 476
477 aop_image_mem: aop-image@81c00 477 aop_image_mem: aop-image@81c00000 {
478 reg = <0x0 0x81c00000 478 reg = <0x0 0x81c00000 0x0 0x60000>;
479 no-map; 479 no-map;
480 }; 480 };
481 481
482 aop_cmd_db_mem: aop-cmd-db@81c 482 aop_cmd_db_mem: aop-cmd-db@81c60000 {
483 compatible = "qcom,cmd 483 compatible = "qcom,cmd-db";
484 reg = <0x0 0x81c60000 484 reg = <0x0 0x81c60000 0x0 0x20000>;
485 no-map; 485 no-map;
486 }; 486 };
487 487
488 aop_config_mem: aop-config@81c 488 aop_config_mem: aop-config@81c80000 {
489 reg = <0x0 0x81c80000 489 reg = <0x0 0x81c80000 0x0 0x20000>;
490 no-map; 490 no-map;
491 }; 491 };
492 492
493 tme_crash_dump_mem: tme-crash- 493 tme_crash_dump_mem: tme-crash-dump@81ca0000 {
494 reg = <0x0 0x81ca0000 494 reg = <0x0 0x81ca0000 0x0 0x40000>;
495 no-map; 495 no-map;
496 }; 496 };
497 497
498 tme_log_mem: tme-log@81ce0000 498 tme_log_mem: tme-log@81ce0000 {
499 reg = <0x0 0x81ce0000 499 reg = <0x0 0x81ce0000 0x0 0x4000>;
500 no-map; 500 no-map;
501 }; 501 };
502 502
503 uefi_log_mem: uefi-log@81ce400 503 uefi_log_mem: uefi-log@81ce4000 {
504 reg = <0x0 0x81ce4000 504 reg = <0x0 0x81ce4000 0x0 0x10000>;
505 no-map; 505 no-map;
506 }; 506 };
507 507
508 secdata_apss_mem: secdata-apss 508 secdata_apss_mem: secdata-apss@81cff000 {
509 reg = <0x0 0x81cff000 509 reg = <0x0 0x81cff000 0x0 0x1000>;
510 no-map; 510 no-map;
511 }; 511 };
512 512
513 pdp_ns_shared_mem: pdp-ns-shar 513 pdp_ns_shared_mem: pdp-ns-shared@81e00000 {
514 reg = <0x0 0x81e00000 514 reg = <0x0 0x81e00000 0x0 0x100000>;
515 no-map; 515 no-map;
516 }; 516 };
517 517
518 gpu_prr_mem: gpu-prr@81f00000 518 gpu_prr_mem: gpu-prr@81f00000 {
519 reg = <0x0 0x81f00000 519 reg = <0x0 0x81f00000 0x0 0x10000>;
520 no-map; 520 no-map;
521 }; 521 };
522 522
523 tpm_control_mem: tpm-control@8 523 tpm_control_mem: tpm-control@81f10000 {
524 reg = <0x0 0x81f10000 524 reg = <0x0 0x81f10000 0x0 0x10000>;
525 no-map; 525 no-map;
526 }; 526 };
527 527
528 usb_ucsi_shared_mem: usb-ucsi- 528 usb_ucsi_shared_mem: usb-ucsi-shared@81f20000 {
529 reg = <0x0 0x81f20000 529 reg = <0x0 0x81f20000 0x0 0x10000>;
530 no-map; 530 no-map;
531 }; 531 };
532 532
533 pld_pep_mem: pld-pep@81f30000 533 pld_pep_mem: pld-pep@81f30000 {
534 reg = <0x0 0x81f30000 534 reg = <0x0 0x81f30000 0x0 0x6000>;
535 no-map; 535 no-map;
536 }; 536 };
537 537
538 pld_gmu_mem: pld-gmu@81f36000 538 pld_gmu_mem: pld-gmu@81f36000 {
539 reg = <0x0 0x81f36000 539 reg = <0x0 0x81f36000 0x0 0x1000>;
540 no-map; 540 no-map;
541 }; 541 };
542 542
543 pld_pdp_mem: pld-pdp@81f37000 543 pld_pdp_mem: pld-pdp@81f37000 {
544 reg = <0x0 0x81f37000 544 reg = <0x0 0x81f37000 0x0 0x1000>;
545 no-map; 545 no-map;
546 }; 546 };
547 547
548 tz_stat_mem: tz-stat@82700000 548 tz_stat_mem: tz-stat@82700000 {
549 reg = <0x0 0x82700000 549 reg = <0x0 0x82700000 0x0 0x100000>;
550 no-map; 550 no-map;
551 }; 551 };
552 552
553 xbl_tmp_buffer_mem: xbl-tmp-bu 553 xbl_tmp_buffer_mem: xbl-tmp-buffer@82800000 {
554 reg = <0x0 0x82800000 554 reg = <0x0 0x82800000 0x0 0xc00000>;
555 no-map; 555 no-map;
556 }; 556 };
557 557
558 adsp_rpc_remote_heap_mem: adsp 558 adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@84b00000 {
559 reg = <0x0 0x84b00000 559 reg = <0x0 0x84b00000 0x0 0x800000>;
560 no-map; 560 no-map;
561 }; 561 };
562 562
563 spu_secure_shared_memory_mem: 563 spu_secure_shared_memory_mem: spu-secure-shared-memory@85300000 {
564 reg = <0x0 0x85300000 564 reg = <0x0 0x85300000 0x0 0x80000>;
565 no-map; 565 no-map;
566 }; 566 };
567 567
568 adsp_boot_dtb_mem: adsp-boot-d 568 adsp_boot_dtb_mem: adsp-boot-dtb@866c0000 {
569 reg = <0x0 0x866c0000 569 reg = <0x0 0x866c0000 0x0 0x40000>;
570 no-map; 570 no-map;
571 }; 571 };
572 572
573 spss_region_mem: spss-region@8 573 spss_region_mem: spss-region@86700000 {
574 reg = <0x0 0x86700000 574 reg = <0x0 0x86700000 0x0 0x400000>;
575 no-map; 575 no-map;
576 }; 576 };
577 577
578 adsp_boot_mem: adsp-boot@86b00 578 adsp_boot_mem: adsp-boot@86b00000 {
579 reg = <0x0 0x86b00000 579 reg = <0x0 0x86b00000 0x0 0xc00000>;
580 no-map; 580 no-map;
581 }; 581 };
582 582
583 video_mem: video@87700000 { 583 video_mem: video@87700000 {
584 reg = <0x0 0x87700000 584 reg = <0x0 0x87700000 0x0 0x700000>;
585 no-map; 585 no-map;
586 }; 586 };
587 587
588 adspslpi_mem: adspslpi@87e0000 588 adspslpi_mem: adspslpi@87e00000 {
589 reg = <0x0 0x87e00000 589 reg = <0x0 0x87e00000 0x0 0x3a00000>;
590 no-map; 590 no-map;
591 }; 591 };
592 592
593 q6_adsp_dtb_mem: q6-adsp-dtb@8 593 q6_adsp_dtb_mem: q6-adsp-dtb@8b800000 {
594 reg = <0x0 0x8b800000 594 reg = <0x0 0x8b800000 0x0 0x80000>;
595 no-map; 595 no-map;
596 }; 596 };
597 597
598 cdsp_mem: cdsp@8b900000 { 598 cdsp_mem: cdsp@8b900000 {
599 reg = <0x0 0x8b900000 599 reg = <0x0 0x8b900000 0x0 0x2000000>;
600 no-map; 600 no-map;
601 }; 601 };
602 602
603 q6_cdsp_dtb_mem: q6-cdsp-dtb@8 603 q6_cdsp_dtb_mem: q6-cdsp-dtb@8d900000 {
604 reg = <0x0 0x8d900000 604 reg = <0x0 0x8d900000 0x0 0x80000>;
605 no-map; 605 no-map;
606 }; 606 };
607 607
608 gpu_microcode_mem: gpu-microco 608 gpu_microcode_mem: gpu-microcode@8d9fe000 {
609 reg = <0x0 0x8d9fe000 609 reg = <0x0 0x8d9fe000 0x0 0x2000>;
610 no-map; 610 no-map;
611 }; 611 };
612 612
613 cvp_mem: cvp@8da00000 { 613 cvp_mem: cvp@8da00000 {
614 reg = <0x0 0x8da00000 614 reg = <0x0 0x8da00000 0x0 0x700000>;
615 no-map; 615 no-map;
616 }; 616 };
617 617
618 camera_mem: camera@8e100000 { 618 camera_mem: camera@8e100000 {
619 reg = <0x0 0x8e100000 619 reg = <0x0 0x8e100000 0x0 0x800000>;
620 no-map; 620 no-map;
621 }; 621 };
622 622
623 av1_encoder_mem: av1-encoder@8 623 av1_encoder_mem: av1-encoder@8e900000 {
624 reg = <0x0 0x8e900000 624 reg = <0x0 0x8e900000 0x0 0x700000>;
625 no-map; 625 no-map;
626 }; 626 };
627 627
628 reserved-region@8f000000 { 628 reserved-region@8f000000 {
629 reg = <0x0 0x8f000000 629 reg = <0x0 0x8f000000 0x0 0xa00000>;
630 no-map; 630 no-map;
631 }; 631 };
632 632
633 wpss_mem: wpss@8fa00000 { 633 wpss_mem: wpss@8fa00000 {
634 reg = <0x0 0x8fa00000 634 reg = <0x0 0x8fa00000 0x0 0x1900000>;
635 no-map; 635 no-map;
636 }; 636 };
637 637
638 q6_wpss_dtb_mem: q6-wpss-dtb@9 638 q6_wpss_dtb_mem: q6-wpss-dtb@91300000 {
639 reg = <0x0 0x91300000 639 reg = <0x0 0x91300000 0x0 0x80000>;
640 no-map; 640 no-map;
641 }; 641 };
642 642
643 xbl_sc_mem: xbl-sc@d8000000 { 643 xbl_sc_mem: xbl-sc@d8000000 {
644 reg = <0x0 0xd8000000 644 reg = <0x0 0xd8000000 0x0 0x40000>;
645 no-map; 645 no-map;
646 }; 646 };
647 647
648 reserved-region@d8040000 { 648 reserved-region@d8040000 {
649 reg = <0x0 0xd8040000 649 reg = <0x0 0xd8040000 0x0 0xa0000>;
650 no-map; 650 no-map;
651 }; 651 };
652 652
653 qtee_mem: qtee@d80e0000 { 653 qtee_mem: qtee@d80e0000 {
654 reg = <0x0 0xd80e0000 654 reg = <0x0 0xd80e0000 0x0 0x520000>;
655 no-map; 655 no-map;
656 }; 656 };
657 657
658 ta_mem: ta@d8600000 { 658 ta_mem: ta@d8600000 {
659 reg = <0x0 0xd8600000 659 reg = <0x0 0xd8600000 0x0 0x8a00000>;
660 no-map; 660 no-map;
661 }; 661 };
662 662
663 tags_mem1: tags@e1000000 { 663 tags_mem1: tags@e1000000 {
664 reg = <0x0 0xe1000000 664 reg = <0x0 0xe1000000 0x0 0x26a0000>;
665 no-map; 665 no-map;
666 }; 666 };
667 667
668 llcc_lpi_mem: llcc-lpi@ff80000 668 llcc_lpi_mem: llcc-lpi@ff800000 {
669 reg = <0x0 0xff800000 669 reg = <0x0 0xff800000 0x0 0x600000>;
670 no-map; 670 no-map;
671 }; 671 };
672 672
673 smem_mem: smem@ffe00000 { 673 smem_mem: smem@ffe00000 {
674 compatible = "qcom,sme 674 compatible = "qcom,smem";
675 reg = <0x0 0xffe00000 675 reg = <0x0 0xffe00000 0x0 0x200000>;
676 hwlocks = <&tcsr_mutex 676 hwlocks = <&tcsr_mutex 3>;
677 no-map; 677 no-map;
678 }; 678 };
679 }; 679 };
680 680
681 smp2p-adsp { 681 smp2p-adsp {
682 compatible = "qcom,smp2p"; 682 compatible = "qcom,smp2p";
683 683
684 interrupts-extended = <&ipcc I 684 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
685 I 685 IPCC_MPROC_SIGNAL_SMP2P
686 I 686 IRQ_TYPE_EDGE_RISING>;
687 687
688 mboxes = <&ipcc IPCC_CLIENT_LP 688 mboxes = <&ipcc IPCC_CLIENT_LPASS
689 IPCC_MPROC_SIG 689 IPCC_MPROC_SIGNAL_SMP2P>;
690 690
691 qcom,smem = <443>, <429>; 691 qcom,smem = <443>, <429>;
692 qcom,local-pid = <0>; 692 qcom,local-pid = <0>;
693 qcom,remote-pid = <2>; 693 qcom,remote-pid = <2>;
694 694
695 smp2p_adsp_out: master-kernel 695 smp2p_adsp_out: master-kernel {
696 qcom,entry-name = "mas 696 qcom,entry-name = "master-kernel";
697 #qcom,smem-state-cells 697 #qcom,smem-state-cells = <1>;
698 }; 698 };
699 699
700 smp2p_adsp_in: slave-kernel { 700 smp2p_adsp_in: slave-kernel {
701 qcom,entry-name = "sla 701 qcom,entry-name = "slave-kernel";
702 interrupt-controller; 702 interrupt-controller;
703 #interrupt-cells = <2> 703 #interrupt-cells = <2>;
704 }; 704 };
705 }; 705 };
706 706
707 smp2p-cdsp { 707 smp2p-cdsp {
708 compatible = "qcom,smp2p"; 708 compatible = "qcom,smp2p";
709 709
710 interrupts-extended = <&ipcc I 710 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
711 I 711 IPCC_MPROC_SIGNAL_SMP2P
712 I 712 IRQ_TYPE_EDGE_RISING>;
713 713
714 mboxes = <&ipcc IPCC_CLIENT_CD 714 mboxes = <&ipcc IPCC_CLIENT_CDSP
715 IPCC_MPROC_SIG 715 IPCC_MPROC_SIGNAL_SMP2P>;
716 716
717 qcom,smem = <94>, <432>; 717 qcom,smem = <94>, <432>;
718 qcom,local-pid = <0>; 718 qcom,local-pid = <0>;
719 qcom,remote-pid = <5>; 719 qcom,remote-pid = <5>;
720 720
721 smp2p_cdsp_out: master-kernel 721 smp2p_cdsp_out: master-kernel {
722 qcom,entry-name = "mas 722 qcom,entry-name = "master-kernel";
723 #qcom,smem-state-cells 723 #qcom,smem-state-cells = <1>;
724 }; 724 };
725 725
726 smp2p_cdsp_in: slave-kernel { 726 smp2p_cdsp_in: slave-kernel {
727 qcom,entry-name = "sla 727 qcom,entry-name = "slave-kernel";
728 interrupt-controller; 728 interrupt-controller;
729 #interrupt-cells = <2> 729 #interrupt-cells = <2>;
730 }; 730 };
731 }; 731 };
732 732
733 soc: soc@0 { 733 soc: soc@0 {
734 compatible = "simple-bus"; 734 compatible = "simple-bus";
735 735
736 #address-cells = <2>; 736 #address-cells = <2>;
737 #size-cells = <2>; 737 #size-cells = <2>;
738 dma-ranges = <0 0 0 0 0x10 0>; 738 dma-ranges = <0 0 0 0 0x10 0>;
739 ranges = <0 0 0 0 0x10 0>; 739 ranges = <0 0 0 0 0x10 0>;
740 740
741 gcc: clock-controller@100000 { 741 gcc: clock-controller@100000 {
742 compatible = "qcom,x1e 742 compatible = "qcom,x1e80100-gcc";
743 reg = <0 0x00100000 0 743 reg = <0 0x00100000 0 0x200000>;
744 744
745 clocks = <&bi_tcxo_div 745 clocks = <&bi_tcxo_div2>,
746 <&sleep_clk>, 746 <&sleep_clk>,
747 <0>, 747 <0>,
748 <&pcie4_phy>, 748 <&pcie4_phy>,
749 <&pcie5_phy>, 749 <&pcie5_phy>,
750 <&pcie6a_phy> 750 <&pcie6a_phy>,
751 <0>, 751 <0>,
752 <&usb_1_ss0_q 752 <&usb_1_ss0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
753 <&usb_1_ss1_q 753 <&usb_1_ss1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
754 <&usb_1_ss2_q 754 <&usb_1_ss2_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
755 755
756 power-domains = <&rpmh 756 power-domains = <&rpmhpd RPMHPD_CX>;
757 #clock-cells = <1>; 757 #clock-cells = <1>;
758 #reset-cells = <1>; 758 #reset-cells = <1>;
759 #power-domain-cells = 759 #power-domain-cells = <1>;
760 }; 760 };
761 761
762 ipcc: mailbox@408000 { 762 ipcc: mailbox@408000 {
763 compatible = "qcom,x1e 763 compatible = "qcom,x1e80100-ipcc", "qcom,ipcc";
764 reg = <0 0x00408000 0 764 reg = <0 0x00408000 0 0x1000>;
765 765
766 interrupts = <GIC_SPI 766 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
767 interrupt-controller; 767 interrupt-controller;
768 #interrupt-cells = <3> 768 #interrupt-cells = <3>;
769 769
770 #mbox-cells = <2>; 770 #mbox-cells = <2>;
771 }; 771 };
772 772
773 gpi_dma2: dma-controller@80000 773 gpi_dma2: dma-controller@800000 {
774 compatible = "qcom,x1e 774 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma";
775 reg = <0 0x00800000 0 775 reg = <0 0x00800000 0 0x60000>;
776 776
777 interrupts = <GIC_SPI 777 interrupts = <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>,
778 <GIC_SPI 778 <GIC_SPI 789 IRQ_TYPE_LEVEL_HIGH>,
779 <GIC_SPI 779 <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>,
780 <GIC_SPI 780 <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>,
781 <GIC_SPI 781 <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>,
782 <GIC_SPI 782 <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>,
783 <GIC_SPI 783 <GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>,
784 <GIC_SPI 784 <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>,
785 <GIC_SPI 785 <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>,
786 <GIC_SPI 786 <GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH>,
787 <GIC_SPI 787 <GIC_SPI 798 IRQ_TYPE_LEVEL_HIGH>,
788 <GIC_SPI 788 <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH>;
789 789
790 dma-channels = <12>; 790 dma-channels = <12>;
791 dma-channel-mask = <0x 791 dma-channel-mask = <0x3e>;
792 #dma-cells = <3>; 792 #dma-cells = <3>;
793 793
794 iommus = <&apps_smmu 0 794 iommus = <&apps_smmu 0x436 0x0>;
795 795
796 status = "disabled"; 796 status = "disabled";
797 }; 797 };
798 798
799 qupv3_2: geniqup@8c0000 { 799 qupv3_2: geniqup@8c0000 {
800 compatible = "qcom,gen 800 compatible = "qcom,geni-se-qup";
801 reg = <0 0x008c0000 0 801 reg = <0 0x008c0000 0 0x2000>;
802 802
803 clocks = <&gcc GCC_QUP 803 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
804 <&gcc GCC_QUP 804 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
805 clock-names = "m-ahb", 805 clock-names = "m-ahb",
806 "s-ahb"; 806 "s-ahb";
807 807
808 iommus = <&apps_smmu 0 808 iommus = <&apps_smmu 0x423 0x0>;
809 809
810 #address-cells = <2>; 810 #address-cells = <2>;
811 #size-cells = <2>; 811 #size-cells = <2>;
812 ranges; 812 ranges;
813 813
814 status = "disabled"; 814 status = "disabled";
815 815
816 i2c16: i2c@880000 { 816 i2c16: i2c@880000 {
817 compatible = " 817 compatible = "qcom,geni-i2c";
818 reg = <0 0x008 818 reg = <0 0x00880000 0 0x4000>;
819 819
820 interrupts = < 820 interrupts = <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>;
821 821
822 clocks = <&gcc 822 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
823 clock-names = 823 clock-names = "se";
824 824
825 interconnects 825 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
826 826 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
827 827 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
828 828 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
829 829 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
830 830 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
831 interconnect-n 831 interconnect-names = "qup-core",
832 832 "qup-config",
833 833 "qup-memory";
834 834
835 dmas = <&gpi_d 835 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
836 <&gpi_d 836 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
837 dma-names = "t 837 dma-names = "tx",
838 "r 838 "rx";
839 839
840 pinctrl-0 = <& 840 pinctrl-0 = <&qup_i2c16_data_clk>;
841 pinctrl-names 841 pinctrl-names = "default";
842 842
843 #address-cells 843 #address-cells = <1>;
844 #size-cells = 844 #size-cells = <0>;
845 845
846 status = "disa 846 status = "disabled";
847 }; 847 };
848 848
849 spi16: spi@880000 { 849 spi16: spi@880000 {
850 compatible = " 850 compatible = "qcom,geni-spi";
851 reg = <0 0x008 851 reg = <0 0x00880000 0 0x4000>;
852 852
853 interrupts = < 853 interrupts = <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>;
854 854
855 clocks = <&gcc 855 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
856 clock-names = 856 clock-names = "se";
857 857
858 interconnects 858 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
859 859 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
860 860 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
861 861 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
862 862 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
863 863 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
864 interconnect-n 864 interconnect-names = "qup-core",
865 865 "qup-config",
866 866 "qup-memory";
867 867
868 dmas = <&gpi_d 868 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
869 <&gpi_d 869 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
870 dma-names = "t 870 dma-names = "tx",
871 "r 871 "rx";
872 872
873 pinctrl-0 = <& 873 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>;
874 pinctrl-names 874 pinctrl-names = "default";
875 875
876 #address-cells 876 #address-cells = <1>;
877 #size-cells = 877 #size-cells = <0>;
878 878
879 status = "disa 879 status = "disabled";
880 }; 880 };
881 881
882 i2c17: i2c@884000 { 882 i2c17: i2c@884000 {
883 compatible = " 883 compatible = "qcom,geni-i2c";
884 reg = <0 0x008 884 reg = <0 0x00884000 0 0x4000>;
885 885
886 interrupts = < 886 interrupts = <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>;
887 887
888 clocks = <&gcc 888 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
889 clock-names = 889 clock-names = "se";
890 890
891 interconnects 891 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
892 892 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
893 893 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
894 894 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
895 895 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
896 896 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
897 interconnect-n 897 interconnect-names = "qup-core",
898 898 "qup-config",
899 899 "qup-memory";
900 900
901 dmas = <&gpi_d 901 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
902 <&gpi_d 902 <&gpi_dma2 1 1 QCOM_GPI_I2C>;
903 dma-names = "t 903 dma-names = "tx",
904 "r 904 "rx";
905 905
906 pinctrl-0 = <& 906 pinctrl-0 = <&qup_i2c17_data_clk>;
907 pinctrl-names 907 pinctrl-names = "default";
908 908
909 #address-cells 909 #address-cells = <1>;
910 #size-cells = 910 #size-cells = <0>;
911 911
912 status = "disa 912 status = "disabled";
913 }; 913 };
914 914
915 spi17: spi@884000 { 915 spi17: spi@884000 {
916 compatible = " 916 compatible = "qcom,geni-spi";
917 reg = <0 0x008 917 reg = <0 0x00884000 0 0x4000>;
918 918
919 interrupts = < 919 interrupts = <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>;
920 920
921 clocks = <&gcc 921 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
922 clock-names = 922 clock-names = "se";
923 923
924 interconnects 924 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
925 925 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
926 926 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
927 927 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
928 928 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
929 929 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
930 interconnect-n 930 interconnect-names = "qup-core",
931 931 "qup-config",
932 932 "qup-memory";
933 933
934 dmas = <&gpi_d 934 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
935 <&gpi_d 935 <&gpi_dma2 1 1 QCOM_GPI_SPI>;
936 dma-names = "t 936 dma-names = "tx",
937 "r 937 "rx";
938 938
939 pinctrl-0 = <& 939 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>;
940 pinctrl-names 940 pinctrl-names = "default";
941 941
942 #address-cells 942 #address-cells = <1>;
943 #size-cells = 943 #size-cells = <0>;
944 944
945 status = "disa 945 status = "disabled";
946 }; 946 };
947 947
948 i2c18: i2c@888000 { 948 i2c18: i2c@888000 {
949 compatible = " 949 compatible = "qcom,geni-i2c";
950 reg = <0 0x008 950 reg = <0 0x00888000 0 0x4000>;
951 951
952 interrupts = < 952 interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>;
953 953
954 clocks = <&gcc 954 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
955 clock-names = 955 clock-names = "se";
956 956
957 interconnects 957 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
958 958 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
959 959 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
960 960 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
961 961 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
962 962 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
963 interconnect-n 963 interconnect-names = "qup-core",
964 964 "qup-config",
965 965 "qup-memory";
966 966
967 dmas = <&gpi_d 967 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
968 <&gpi_d 968 <&gpi_dma2 1 2 QCOM_GPI_I2C>;
969 dma-names = "t 969 dma-names = "tx",
970 "r 970 "rx";
971 971
972 pinctrl-0 = <& 972 pinctrl-0 = <&qup_i2c18_data_clk>;
973 pinctrl-names 973 pinctrl-names = "default";
974 974
975 #address-cells 975 #address-cells = <1>;
976 #size-cells = 976 #size-cells = <0>;
977 977
978 status = "disa 978 status = "disabled";
979 }; 979 };
980 980
981 spi18: spi@888000 { 981 spi18: spi@888000 {
982 compatible = " 982 compatible = "qcom,geni-spi";
983 reg = <0 0x008 983 reg = <0 0x00888000 0 0x4000>;
984 984
985 interrupts = < 985 interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>;
986 986
987 clocks = <&gcc 987 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
988 clock-names = 988 clock-names = "se";
989 989
990 interconnects 990 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
991 991 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
992 992 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
993 993 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
994 994 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
995 995 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
996 interconnect-n 996 interconnect-names = "qup-core",
997 997 "qup-config",
998 998 "qup-memory";
999 999
1000 dmas = <&gpi_ 1000 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
1001 <&gpi_ 1001 <&gpi_dma2 1 2 QCOM_GPI_SPI>;
1002 dma-names = " 1002 dma-names = "tx",
1003 " 1003 "rx";
1004 1004
1005 pinctrl-0 = < 1005 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>;
1006 pinctrl-names 1006 pinctrl-names = "default";
1007 1007
1008 #address-cell 1008 #address-cells = <1>;
1009 #size-cells = 1009 #size-cells = <0>;
1010 1010
1011 status = "dis 1011 status = "disabled";
1012 }; 1012 };
1013 1013
1014 i2c19: i2c@88c000 { 1014 i2c19: i2c@88c000 {
1015 compatible = 1015 compatible = "qcom,geni-i2c";
1016 reg = <0 0x00 1016 reg = <0 0x0088c000 0 0x4000>;
1017 1017
1018 interrupts = 1018 interrupts = <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>;
1019 1019
1020 clocks = <&gc 1020 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1021 clock-names = 1021 clock-names = "se";
1022 1022
1023 interconnects 1023 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1024 1024 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1025 1025 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1026 1026 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1027 1027 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1028 1028 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1029 interconnect- 1029 interconnect-names = "qup-core",
1030 1030 "qup-config",
1031 1031 "qup-memory";
1032 1032
1033 dmas = <&gpi_ 1033 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
1034 <&gpi_ 1034 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
1035 dma-names = " 1035 dma-names = "tx",
1036 " 1036 "rx";
1037 1037
1038 pinctrl-0 = < 1038 pinctrl-0 = <&qup_i2c19_data_clk>;
1039 pinctrl-names 1039 pinctrl-names = "default";
1040 1040
1041 #address-cell 1041 #address-cells = <1>;
1042 #size-cells = 1042 #size-cells = <0>;
1043 1043
1044 status = "dis 1044 status = "disabled";
1045 }; 1045 };
1046 1046
1047 spi19: spi@88c000 { 1047 spi19: spi@88c000 {
1048 compatible = 1048 compatible = "qcom,geni-spi";
1049 reg = <0 0x00 1049 reg = <0 0x0088c000 0 0x4000>;
1050 1050
1051 interrupts = 1051 interrupts = <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>;
1052 1052
1053 clocks = <&gc 1053 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1054 clock-names = 1054 clock-names = "se";
1055 1055
1056 interconnects 1056 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1057 1057 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1058 1058 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1059 1059 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1060 1060 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1061 1061 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1062 interconnect- 1062 interconnect-names = "qup-core",
1063 1063 "qup-config",
1064 1064 "qup-memory";
1065 1065
1066 dmas = <&gpi_ 1066 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
1067 <&gpi_ 1067 <&gpi_dma2 1 3 QCOM_GPI_SPI>;
1068 dma-names = " 1068 dma-names = "tx",
1069 " 1069 "rx";
1070 1070
1071 pinctrl-0 = < 1071 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>;
1072 pinctrl-names 1072 pinctrl-names = "default";
1073 1073
1074 #address-cell 1074 #address-cells = <1>;
1075 #size-cells = 1075 #size-cells = <0>;
1076 1076
1077 status = "dis 1077 status = "disabled";
1078 }; 1078 };
1079 1079
1080 i2c20: i2c@890000 { 1080 i2c20: i2c@890000 {
1081 compatible = 1081 compatible = "qcom,geni-i2c";
1082 reg = <0 0x00 1082 reg = <0 0x00890000 0 0x4000>;
1083 1083
1084 interrupts = 1084 interrupts = <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>;
1085 1085
1086 clocks = <&gc 1086 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1087 clock-names = 1087 clock-names = "se";
1088 1088
1089 interconnects 1089 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1090 1090 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1091 1091 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1092 1092 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1093 1093 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1094 1094 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1095 interconnect- 1095 interconnect-names = "qup-core",
1096 1096 "qup-config",
1097 1097 "qup-memory";
1098 1098
1099 dmas = <&gpi_ 1099 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1100 <&gpi_ 1100 <&gpi_dma2 1 4 QCOM_GPI_I2C>;
1101 dma-names = " 1101 dma-names = "tx",
1102 " 1102 "rx";
1103 1103
1104 pinctrl-0 = < 1104 pinctrl-0 = <&qup_i2c20_data_clk>;
1105 pinctrl-names 1105 pinctrl-names = "default";
1106 1106
1107 #address-cell 1107 #address-cells = <1>;
1108 #size-cells = 1108 #size-cells = <0>;
1109 1109
1110 status = "dis 1110 status = "disabled";
1111 }; 1111 };
1112 1112
1113 spi20: spi@890000 { 1113 spi20: spi@890000 {
1114 compatible = 1114 compatible = "qcom,geni-spi";
1115 reg = <0 0x00 1115 reg = <0 0x00890000 0 0x4000>;
1116 1116
1117 interrupts = 1117 interrupts = <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>;
1118 1118
1119 clocks = <&gc 1119 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1120 clock-names = 1120 clock-names = "se";
1121 1121
1122 interconnects 1122 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1123 1123 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1124 1124 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1125 1125 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1126 1126 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1127 1127 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1128 interconnect- 1128 interconnect-names = "qup-core",
1129 1129 "qup-config",
1130 1130 "qup-memory";
1131 1131
1132 dmas = <&gpi_ 1132 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
1133 <&gpi_ 1133 <&gpi_dma2 1 4 QCOM_GPI_SPI>;
1134 dma-names = " 1134 dma-names = "tx",
1135 " 1135 "rx";
1136 1136
1137 pinctrl-0 = < 1137 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>;
1138 pinctrl-names 1138 pinctrl-names = "default";
1139 1139
1140 #address-cell 1140 #address-cells = <1>;
1141 #size-cells = 1141 #size-cells = <0>;
1142 1142
1143 status = "dis 1143 status = "disabled";
1144 }; 1144 };
1145 1145
1146 i2c21: i2c@894000 { 1146 i2c21: i2c@894000 {
1147 compatible = 1147 compatible = "qcom,geni-i2c";
1148 reg = <0 0x00 1148 reg = <0 0x00894000 0 0x4000>;
1149 1149
1150 interrupts = 1150 interrupts = <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>;
1151 1151
1152 clocks = <&gc 1152 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1153 clock-names = 1153 clock-names = "se";
1154 1154
1155 interconnects 1155 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1156 1156 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1157 1157 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1158 1158 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1159 1159 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1160 1160 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1161 interconnect- 1161 interconnect-names = "qup-core",
1162 1162 "qup-config",
1163 1163 "qup-memory";
1164 1164
1165 dmas = <&gpi_ 1165 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1166 <&gpi_ 1166 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1167 dma-names = " 1167 dma-names = "tx",
1168 " 1168 "rx";
1169 1169
1170 pinctrl-0 = < 1170 pinctrl-0 = <&qup_i2c21_data_clk>;
1171 pinctrl-names 1171 pinctrl-names = "default";
1172 1172
1173 #address-cell 1173 #address-cells = <1>;
1174 #size-cells = 1174 #size-cells = <0>;
1175 1175
1176 status = "dis 1176 status = "disabled";
1177 }; 1177 };
1178 1178
1179 spi21: spi@894000 { 1179 spi21: spi@894000 {
1180 compatible = 1180 compatible = "qcom,geni-spi";
1181 reg = <0 0x00 1181 reg = <0 0x00894000 0 0x4000>;
1182 1182
1183 interrupts = 1183 interrupts = <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>;
1184 1184
1185 clocks = <&gc 1185 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1186 clock-names = 1186 clock-names = "se";
1187 1187
1188 interconnects 1188 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1189 1189 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1190 1190 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1191 1191 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1192 1192 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1193 1193 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1194 interconnect- 1194 interconnect-names = "qup-core",
1195 1195 "qup-config",
1196 1196 "qup-memory";
1197 1197
1198 dmas = <&gpi_ 1198 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1199 <&gpi_ 1199 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1200 dma-names = " 1200 dma-names = "tx",
1201 " 1201 "rx";
1202 1202
1203 pinctrl-0 = < 1203 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>;
1204 pinctrl-names 1204 pinctrl-names = "default";
1205 1205
1206 #address-cell 1206 #address-cells = <1>;
1207 #size-cells = 1207 #size-cells = <0>;
1208 1208
1209 status = "dis 1209 status = "disabled";
1210 }; 1210 };
1211 1211
1212 uart21: serial@894000 1212 uart21: serial@894000 {
1213 compatible = 1213 compatible = "qcom,geni-uart";
1214 reg = <0 0x00 1214 reg = <0 0x00894000 0 0x4000>;
1215 1215
1216 interrupts = 1216 interrupts = <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>;
1217 1217
1218 clocks = <&gc 1218 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1219 clock-names = 1219 clock-names = "se";
1220 1220
1221 interconnects 1221 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1222 1222 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1223 1223 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1224 1224 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
1225 interconnect- 1225 interconnect-names = "qup-core",
1226 1226 "qup-config";
1227 1227
1228 pinctrl-0 = < 1228 pinctrl-0 = <&qup_uart21_default>;
1229 pinctrl-names 1229 pinctrl-names = "default";
1230 1230
1231 status = "dis 1231 status = "disabled";
1232 }; 1232 };
1233 1233
1234 i2c22: i2c@898000 { 1234 i2c22: i2c@898000 {
1235 compatible = 1235 compatible = "qcom,geni-i2c";
1236 reg = <0 0x00 1236 reg = <0 0x00898000 0 0x4000>;
1237 1237
1238 interrupts = 1238 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
1239 1239
1240 clocks = <&gc 1240 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1241 clock-names = 1241 clock-names = "se";
1242 1242
1243 interconnects 1243 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1244 1244 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1245 1245 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1246 1246 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1247 1247 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1248 1248 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1249 interconnect- 1249 interconnect-names = "qup-core",
1250 1250 "qup-config",
1251 1251 "qup-memory";
1252 1252
1253 dmas = <&gpi_ 1253 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>,
1254 <&gpi_ 1254 <&gpi_dma2 1 6 QCOM_GPI_I2C>;
1255 dma-names = " 1255 dma-names = "tx",
1256 " 1256 "rx";
1257 1257
1258 pinctrl-0 = < 1258 pinctrl-0 = <&qup_i2c22_data_clk>;
1259 pinctrl-names 1259 pinctrl-names = "default";
1260 1260
1261 #address-cell 1261 #address-cells = <1>;
1262 #size-cells = 1262 #size-cells = <0>;
1263 1263
1264 status = "dis 1264 status = "disabled";
1265 }; 1265 };
1266 1266
1267 spi22: spi@898000 { 1267 spi22: spi@898000 {
1268 compatible = 1268 compatible = "qcom,geni-spi";
1269 reg = <0 0x00 1269 reg = <0 0x00898000 0 0x4000>;
1270 1270
1271 interrupts = 1271 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
1272 1272
1273 clocks = <&gc 1273 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1274 clock-names = 1274 clock-names = "se";
1275 1275
1276 interconnects 1276 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1277 1277 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1278 1278 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1279 1279 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1280 1280 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1281 1281 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1282 interconnect- 1282 interconnect-names = "qup-core",
1283 1283 "qup-config",
1284 1284 "qup-memory";
1285 1285
1286 dmas = <&gpi_ 1286 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>,
1287 <&gpi_ 1287 <&gpi_dma2 1 6 QCOM_GPI_SPI>;
1288 dma-names = " 1288 dma-names = "tx",
1289 " 1289 "rx";
1290 1290
1291 pinctrl-0 = < 1291 pinctrl-0 = <&qup_spi22_data_clk>, <&qup_spi22_cs>;
1292 pinctrl-names 1292 pinctrl-names = "default";
1293 1293
1294 #address-cell 1294 #address-cells = <1>;
1295 #size-cells = 1295 #size-cells = <0>;
1296 1296
1297 status = "dis 1297 status = "disabled";
1298 }; 1298 };
1299 1299
1300 i2c23: i2c@89c000 { 1300 i2c23: i2c@89c000 {
1301 compatible = 1301 compatible = "qcom,geni-i2c";
1302 reg = <0 0x00 1302 reg = <0 0x0089c000 0 0x4000>;
1303 1303
1304 interrupts = 1304 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
1305 1305
1306 clocks = <&gc 1306 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
1307 clock-names = 1307 clock-names = "se";
1308 1308
1309 interconnects 1309 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1310 1310 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1311 1311 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1312 1312 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1313 1313 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1314 1314 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1315 interconnect- 1315 interconnect-names = "qup-core",
1316 1316 "qup-config",
1317 1317 "qup-memory";
1318 1318
1319 dmas = <&gpi_ 1319 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>,
1320 <&gpi_ 1320 <&gpi_dma2 1 7 QCOM_GPI_I2C>;
1321 dma-names = " 1321 dma-names = "tx",
1322 " 1322 "rx";
1323 1323
1324 pinctrl-0 = < 1324 pinctrl-0 = <&qup_i2c23_data_clk>;
1325 pinctrl-names 1325 pinctrl-names = "default";
1326 1326
1327 #address-cell 1327 #address-cells = <1>;
1328 #size-cells = 1328 #size-cells = <0>;
1329 1329
1330 status = "dis 1330 status = "disabled";
1331 }; 1331 };
1332 1332
1333 spi23: spi@89c000 { 1333 spi23: spi@89c000 {
1334 compatible = 1334 compatible = "qcom,geni-spi";
1335 reg = <0 0x00 1335 reg = <0 0x0089c000 0 0x4000>;
1336 1336
1337 interrupts = 1337 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
1338 1338
1339 clocks = <&gc 1339 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
1340 clock-names = 1340 clock-names = "se";
1341 1341
1342 interconnects 1342 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1343 1343 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1344 1344 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1345 1345 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
1346 1346 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1347 1347 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1348 interconnect- 1348 interconnect-names = "qup-core",
1349 1349 "qup-config",
1350 1350 "qup-memory";
1351 1351
1352 dmas = <&gpi_ 1352 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>,
1353 <&gpi_ 1353 <&gpi_dma2 1 7 QCOM_GPI_SPI>;
1354 dma-names = " 1354 dma-names = "tx",
1355 " 1355 "rx";
1356 1356
1357 pinctrl-0 = < 1357 pinctrl-0 = <&qup_spi23_data_clk>, <&qup_spi23_cs>;
1358 pinctrl-names 1358 pinctrl-names = "default";
1359 1359
1360 #address-cell 1360 #address-cells = <1>;
1361 #size-cells = 1361 #size-cells = <0>;
1362 1362
1363 status = "dis 1363 status = "disabled";
1364 }; 1364 };
1365 }; 1365 };
1366 1366
1367 gpi_dma1: dma-controller@a000 1367 gpi_dma1: dma-controller@a00000 {
1368 compatible = "qcom,x1 1368 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma";
1369 reg = <0 0x00a00000 0 1369 reg = <0 0x00a00000 0 0x60000>;
1370 1370
1371 interrupts = <GIC_SPI 1371 interrupts = <GIC_SPI 776 IRQ_TYPE_LEVEL_HIGH>,
1372 <GIC_SPI 1372 <GIC_SPI 777 IRQ_TYPE_LEVEL_HIGH>,
1373 <GIC_SPI 1373 <GIC_SPI 778 IRQ_TYPE_LEVEL_HIGH>,
1374 <GIC_SPI 1374 <GIC_SPI 779 IRQ_TYPE_LEVEL_HIGH>,
1375 <GIC_SPI 1375 <GIC_SPI 780 IRQ_TYPE_LEVEL_HIGH>,
1376 <GIC_SPI 1376 <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>,
1377 <GIC_SPI 1377 <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>,
1378 <GIC_SPI 1378 <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>,
1379 <GIC_SPI 1379 <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>,
1380 <GIC_SPI 1380 <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>,
1381 <GIC_SPI 1381 <GIC_SPI 786 IRQ_TYPE_LEVEL_HIGH>,
1382 <GIC_SPI 1382 <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>;
1383 1383
1384 dma-channels = <12>; 1384 dma-channels = <12>;
1385 dma-channel-mask = <0 1385 dma-channel-mask = <0x3e>;
1386 #dma-cells = <3>; 1386 #dma-cells = <3>;
1387 1387
1388 iommus = <&apps_smmu 1388 iommus = <&apps_smmu 0x136 0x0>;
1389 1389
1390 status = "disabled"; 1390 status = "disabled";
1391 }; 1391 };
1392 1392
1393 qupv3_1: geniqup@ac0000 { 1393 qupv3_1: geniqup@ac0000 {
1394 compatible = "qcom,ge 1394 compatible = "qcom,geni-se-qup";
1395 reg = <0 0x00ac0000 0 1395 reg = <0 0x00ac0000 0 0x2000>;
1396 1396
1397 clocks = <&gcc GCC_QU 1397 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1398 <&gcc GCC_QU 1398 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1399 clock-names = "m-ahb" 1399 clock-names = "m-ahb",
1400 "s-ahb" 1400 "s-ahb";
1401 1401
1402 iommus = <&apps_smmu 1402 iommus = <&apps_smmu 0x123 0x0>;
1403 1403
1404 #address-cells = <2>; 1404 #address-cells = <2>;
1405 #size-cells = <2>; 1405 #size-cells = <2>;
1406 ranges; 1406 ranges;
1407 1407
1408 status = "disabled"; 1408 status = "disabled";
1409 1409
1410 i2c8: i2c@a80000 { 1410 i2c8: i2c@a80000 {
1411 compatible = 1411 compatible = "qcom,geni-i2c";
1412 reg = <0 0x00 1412 reg = <0 0x00a80000 0 0x4000>;
1413 1413
1414 interrupts = 1414 interrupts = <GIC_SPI 800 IRQ_TYPE_LEVEL_HIGH>;
1415 1415
1416 clocks = <&gc 1416 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1417 clock-names = 1417 clock-names = "se";
1418 1418
1419 interconnects 1419 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1420 1420 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1421 1421 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1422 1422 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1423 1423 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1424 1424 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1425 interconnect- 1425 interconnect-names = "qup-core",
1426 1426 "qup-config",
1427 1427 "qup-memory";
1428 1428
1429 dmas = <&gpi_ 1429 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1430 <&gpi_ 1430 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1431 dma-names = " 1431 dma-names = "tx",
1432 " 1432 "rx";
1433 1433
1434 pinctrl-0 = < 1434 pinctrl-0 = <&qup_i2c8_data_clk>;
1435 pinctrl-names 1435 pinctrl-names = "default";
1436 1436
1437 #address-cell 1437 #address-cells = <1>;
1438 #size-cells = 1438 #size-cells = <0>;
1439 1439
1440 status = "dis 1440 status = "disabled";
1441 }; 1441 };
1442 1442
1443 spi8: spi@a80000 { 1443 spi8: spi@a80000 {
1444 compatible = 1444 compatible = "qcom,geni-spi";
1445 reg = <0 0x00 1445 reg = <0 0x00a80000 0 0x4000>;
1446 1446
1447 interrupts = 1447 interrupts = <GIC_SPI 800 IRQ_TYPE_LEVEL_HIGH>;
1448 1448
1449 clocks = <&gc 1449 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1450 clock-names = 1450 clock-names = "se";
1451 1451
1452 interconnects 1452 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1453 1453 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1454 1454 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1455 1455 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1456 1456 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1457 1457 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1458 interconnect- 1458 interconnect-names = "qup-core",
1459 1459 "qup-config",
1460 1460 "qup-memory";
1461 1461
1462 dmas = <&gpi_ 1462 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1463 <&gpi_ 1463 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1464 dma-names = " 1464 dma-names = "tx",
1465 " 1465 "rx";
1466 1466
1467 pinctrl-0 = < 1467 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1468 pinctrl-names 1468 pinctrl-names = "default";
1469 1469
1470 #address-cell 1470 #address-cells = <1>;
1471 #size-cells = 1471 #size-cells = <0>;
1472 1472
1473 status = "dis 1473 status = "disabled";
1474 }; 1474 };
1475 1475
1476 i2c9: i2c@a84000 { 1476 i2c9: i2c@a84000 {
1477 compatible = 1477 compatible = "qcom,geni-i2c";
1478 reg = <0 0x00 1478 reg = <0 0x00a84000 0 0x4000>;
1479 1479
1480 interrupts = 1480 interrupts = <GIC_SPI 801 IRQ_TYPE_LEVEL_HIGH>;
1481 1481
1482 clocks = <&gc 1482 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1483 clock-names = 1483 clock-names = "se";
1484 1484
1485 interconnects 1485 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1486 1486 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1487 1487 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1488 1488 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1489 1489 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1490 1490 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1491 interconnect- 1491 interconnect-names = "qup-core",
1492 1492 "qup-config",
1493 1493 "qup-memory";
1494 1494
1495 dmas = <&gpi_ 1495 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1496 <&gpi_ 1496 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1497 dma-names = " 1497 dma-names = "tx",
1498 " 1498 "rx";
1499 1499
1500 pinctrl-0 = < 1500 pinctrl-0 = <&qup_i2c9_data_clk>;
1501 pinctrl-names 1501 pinctrl-names = "default";
1502 1502
1503 #address-cell 1503 #address-cells = <1>;
1504 #size-cells = 1504 #size-cells = <0>;
1505 1505
1506 status = "dis 1506 status = "disabled";
1507 }; 1507 };
1508 1508
1509 spi9: spi@a84000 { 1509 spi9: spi@a84000 {
1510 compatible = 1510 compatible = "qcom,geni-spi";
1511 reg = <0 0x00 1511 reg = <0 0x00a84000 0 0x4000>;
1512 1512
1513 interrupts = 1513 interrupts = <GIC_SPI 801 IRQ_TYPE_LEVEL_HIGH>;
1514 1514
1515 clocks = <&gc 1515 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1516 clock-names = 1516 clock-names = "se";
1517 1517
1518 interconnects 1518 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1519 1519 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1520 1520 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1521 1521 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1522 1522 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1523 1523 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1524 interconnect- 1524 interconnect-names = "qup-core",
1525 1525 "qup-config",
1526 1526 "qup-memory";
1527 1527
1528 dmas = <&gpi_ 1528 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1529 <&gpi_ 1529 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1530 dma-names = " 1530 dma-names = "tx",
1531 " 1531 "rx";
1532 1532
1533 pinctrl-0 = < 1533 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1534 pinctrl-names 1534 pinctrl-names = "default";
1535 1535
1536 #address-cell 1536 #address-cells = <1>;
1537 #size-cells = 1537 #size-cells = <0>;
1538 1538
1539 status = "dis 1539 status = "disabled";
1540 }; 1540 };
1541 1541
1542 i2c10: i2c@a88000 { 1542 i2c10: i2c@a88000 {
1543 compatible = 1543 compatible = "qcom,geni-i2c";
1544 reg = <0 0x00 1544 reg = <0 0x00a88000 0 0x4000>;
1545 1545
1546 interrupts = 1546 interrupts = <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>;
1547 1547
1548 clocks = <&gc 1548 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1549 clock-names = 1549 clock-names = "se";
1550 1550
1551 interconnects 1551 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1552 1552 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1553 1553 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1554 1554 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1555 1555 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1556 1556 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1557 interconnect- 1557 interconnect-names = "qup-core",
1558 1558 "qup-config",
1559 1559 "qup-memory";
1560 1560
1561 dmas = <&gpi_ 1561 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1562 <&gpi_ 1562 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1563 dma-names = " 1563 dma-names = "tx",
1564 " 1564 "rx";
1565 1565
1566 pinctrl-0 = < 1566 pinctrl-0 = <&qup_i2c10_data_clk>;
1567 pinctrl-names 1567 pinctrl-names = "default";
1568 1568
1569 #address-cell 1569 #address-cells = <1>;
1570 #size-cells = 1570 #size-cells = <0>;
1571 1571
1572 status = "dis 1572 status = "disabled";
1573 }; 1573 };
1574 1574
1575 spi10: spi@a88000 { 1575 spi10: spi@a88000 {
1576 compatible = 1576 compatible = "qcom,geni-spi";
1577 reg = <0 0x00 1577 reg = <0 0x00a88000 0 0x4000>;
1578 1578
1579 interrupts = 1579 interrupts = <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>;
1580 1580
1581 clocks = <&gc 1581 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1582 clock-names = 1582 clock-names = "se";
1583 1583
1584 interconnects 1584 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1585 1585 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1586 1586 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1587 1587 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1588 1588 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1589 1589 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1590 interconnect- 1590 interconnect-names = "qup-core",
1591 1591 "qup-config",
1592 1592 "qup-memory";
1593 1593
1594 dmas = <&gpi_ 1594 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1595 <&gpi_ 1595 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1596 dma-names = " 1596 dma-names = "tx",
1597 " 1597 "rx";
1598 1598
1599 pinctrl-0 = < 1599 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1600 pinctrl-names 1600 pinctrl-names = "default";
1601 1601
1602 #address-cell 1602 #address-cells = <1>;
1603 #size-cells = 1603 #size-cells = <0>;
1604 1604
1605 status = "dis 1605 status = "disabled";
1606 }; 1606 };
1607 1607
1608 i2c11: i2c@a8c000 { 1608 i2c11: i2c@a8c000 {
1609 compatible = 1609 compatible = "qcom,geni-i2c";
1610 reg = <0 0x00 1610 reg = <0 0x00a8c000 0 0x4000>;
1611 1611
1612 interrupts = 1612 interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>;
1613 1613
1614 clocks = <&gc 1614 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1615 clock-names = 1615 clock-names = "se";
1616 1616
1617 interconnects 1617 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1618 1618 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1619 1619 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1620 1620 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1621 1621 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1622 1622 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1623 interconnect- 1623 interconnect-names = "qup-core",
1624 1624 "qup-config",
1625 1625 "qup-memory";
1626 1626
1627 dmas = <&gpi_ 1627 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1628 <&gpi_ 1628 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1629 dma-names = " 1629 dma-names = "tx",
1630 " 1630 "rx";
1631 1631
1632 pinctrl-0 = < 1632 pinctrl-0 = <&qup_i2c11_data_clk>;
1633 pinctrl-names 1633 pinctrl-names = "default";
1634 1634
1635 #address-cell 1635 #address-cells = <1>;
1636 #size-cells = 1636 #size-cells = <0>;
1637 1637
1638 status = "dis 1638 status = "disabled";
1639 }; 1639 };
1640 1640
1641 spi11: spi@a8c000 { 1641 spi11: spi@a8c000 {
1642 compatible = 1642 compatible = "qcom,geni-spi";
1643 reg = <0 0x00 1643 reg = <0 0x00a8c000 0 0x4000>;
1644 1644
1645 interrupts = 1645 interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>;
1646 1646
1647 clocks = <&gc 1647 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1648 clock-names = 1648 clock-names = "se";
1649 1649
1650 interconnects 1650 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1651 1651 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1652 1652 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1653 1653 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1654 1654 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1655 1655 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1656 interconnect- 1656 interconnect-names = "qup-core",
1657 1657 "qup-config",
1658 1658 "qup-memory";
1659 1659
1660 dmas = <&gpi_ 1660 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1661 <&gpi_ 1661 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1662 dma-names = " 1662 dma-names = "tx",
1663 " 1663 "rx";
1664 1664
1665 pinctrl-0 = < 1665 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1666 pinctrl-names 1666 pinctrl-names = "default";
1667 1667
1668 #address-cell 1668 #address-cells = <1>;
1669 #size-cells = 1669 #size-cells = <0>;
1670 1670
1671 status = "dis 1671 status = "disabled";
1672 }; 1672 };
1673 1673
1674 i2c12: i2c@a90000 { 1674 i2c12: i2c@a90000 {
1675 compatible = 1675 compatible = "qcom,geni-i2c";
1676 reg = <0 0x00 1676 reg = <0 0x00a90000 0 0x4000>;
1677 1677
1678 interrupts = 1678 interrupts = <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>;
1679 1679
1680 clocks = <&gc 1680 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1681 clock-names = 1681 clock-names = "se";
1682 1682
1683 interconnects 1683 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1684 1684 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1685 1685 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1686 1686 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1687 1687 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1688 1688 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1689 interconnect- 1689 interconnect-names = "qup-core",
1690 1690 "qup-config",
1691 1691 "qup-memory";
1692 1692
1693 dmas = <&gpi_ 1693 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1694 <&gpi_ 1694 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1695 dma-names = " 1695 dma-names = "tx",
1696 " 1696 "rx";
1697 1697
1698 pinctrl-0 = < 1698 pinctrl-0 = <&qup_i2c12_data_clk>;
1699 pinctrl-names 1699 pinctrl-names = "default";
1700 1700
1701 #address-cell 1701 #address-cells = <1>;
1702 #size-cells = 1702 #size-cells = <0>;
1703 1703
1704 status = "dis 1704 status = "disabled";
1705 }; 1705 };
1706 1706
1707 spi12: spi@a90000 { 1707 spi12: spi@a90000 {
1708 compatible = 1708 compatible = "qcom,geni-spi";
1709 reg = <0 0x00 1709 reg = <0 0x00a90000 0 0x4000>;
1710 1710
1711 interrupts = 1711 interrupts = <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>;
1712 1712
1713 clocks = <&gc 1713 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1714 clock-names = 1714 clock-names = "se";
1715 1715
1716 interconnects 1716 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1717 1717 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1718 1718 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1719 1719 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1720 1720 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1721 1721 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1722 interconnect- 1722 interconnect-names = "qup-core",
1723 1723 "qup-config",
1724 1724 "qup-memory";
1725 1725
1726 dmas = <&gpi_ 1726 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1727 <&gpi_ 1727 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1728 dma-names = " 1728 dma-names = "tx",
1729 " 1729 "rx";
1730 1730
1731 pinctrl-0 = < 1731 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1732 pinctrl-names 1732 pinctrl-names = "default";
1733 1733
1734 #address-cell 1734 #address-cells = <1>;
1735 #size-cells = 1735 #size-cells = <0>;
1736 1736
1737 status = "dis 1737 status = "disabled";
1738 }; 1738 };
1739 1739
1740 i2c13: i2c@a94000 { 1740 i2c13: i2c@a94000 {
1741 compatible = 1741 compatible = "qcom,geni-i2c";
1742 reg = <0 0x00 1742 reg = <0 0x00a94000 0 0x4000>;
1743 1743
1744 interrupts = 1744 interrupts = <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>;
1745 1745
1746 clocks = <&gc 1746 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1747 clock-names = 1747 clock-names = "se";
1748 1748
1749 interconnects 1749 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1750 1750 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1751 1751 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1752 1752 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1753 1753 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1754 1754 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1755 interconnect- 1755 interconnect-names = "qup-core",
1756 1756 "qup-config",
1757 1757 "qup-memory";
1758 1758
1759 dmas = <&gpi_ 1759 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1760 <&gpi_ 1760 <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1761 dma-names = " 1761 dma-names = "tx",
1762 " 1762 "rx";
1763 1763
1764 pinctrl-0 = < 1764 pinctrl-0 = <&qup_i2c13_data_clk>;
1765 pinctrl-names 1765 pinctrl-names = "default";
1766 1766
1767 #address-cell 1767 #address-cells = <1>;
1768 #size-cells = 1768 #size-cells = <0>;
1769 1769
1770 status = "dis 1770 status = "disabled";
1771 }; 1771 };
1772 1772
1773 spi13: spi@a94000 { 1773 spi13: spi@a94000 {
1774 compatible = 1774 compatible = "qcom,geni-spi";
1775 reg = <0 0x00 1775 reg = <0 0x00a94000 0 0x4000>;
1776 1776
1777 interrupts = 1777 interrupts = <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>;
1778 1778
1779 clocks = <&gc 1779 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1780 clock-names = 1780 clock-names = "se";
1781 1781
1782 interconnects 1782 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1783 1783 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1784 1784 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1785 1785 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1786 1786 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1787 1787 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1788 interconnect- 1788 interconnect-names = "qup-core",
1789 1789 "qup-config",
1790 1790 "qup-memory";
1791 1791
1792 dmas = <&gpi_ 1792 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1793 <&gpi_ 1793 <&gpi_dma1 1 5 QCOM_GPI_SPI>;
1794 dma-names = " 1794 dma-names = "tx",
1795 " 1795 "rx";
1796 1796
1797 pinctrl-0 = < 1797 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1798 pinctrl-names 1798 pinctrl-names = "default";
1799 1799
1800 #address-cell 1800 #address-cells = <1>;
1801 #size-cells = 1801 #size-cells = <0>;
1802 1802
1803 status = "dis 1803 status = "disabled";
1804 }; 1804 };
1805 1805
1806 i2c14: i2c@a98000 { 1806 i2c14: i2c@a98000 {
1807 compatible = 1807 compatible = "qcom,geni-i2c";
1808 reg = <0 0x00 1808 reg = <0 0x00a98000 0 0x4000>;
1809 1809
1810 interrupts = 1810 interrupts = <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>;
1811 1811
1812 clocks = <&gc 1812 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1813 clock-names = 1813 clock-names = "se";
1814 1814
1815 interconnects 1815 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1816 1816 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1817 1817 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1818 1818 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1819 1819 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1820 1820 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1821 interconnect- 1821 interconnect-names = "qup-core",
1822 1822 "qup-config",
1823 1823 "qup-memory";
1824 1824
1825 dmas = <&gpi_ 1825 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
1826 <&gpi_ 1826 <&gpi_dma1 1 6 QCOM_GPI_I2C>;
1827 dma-names = " 1827 dma-names = "tx",
1828 " 1828 "rx";
1829 1829
1830 pinctrl-0 = < 1830 pinctrl-0 = <&qup_i2c14_data_clk>;
1831 pinctrl-names 1831 pinctrl-names = "default";
1832 1832
1833 #address-cell 1833 #address-cells = <1>;
1834 #size-cells = 1834 #size-cells = <0>;
1835 1835
1836 status = "dis 1836 status = "disabled";
1837 }; 1837 };
1838 1838
1839 spi14: spi@a98000 { 1839 spi14: spi@a98000 {
1840 compatible = 1840 compatible = "qcom,geni-spi";
1841 reg = <0 0x00 1841 reg = <0 0x00a98000 0 0x4000>;
1842 1842
1843 interrupts = 1843 interrupts = <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>;
1844 1844
1845 clocks = <&gc 1845 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1846 clock-names = 1846 clock-names = "se";
1847 1847
1848 interconnects 1848 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1849 1849 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1850 1850 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1851 1851 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1852 1852 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1853 1853 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1854 interconnect- 1854 interconnect-names = "qup-core",
1855 1855 "qup-config",
1856 1856 "qup-memory";
1857 1857
1858 dmas = <&gpi_ 1858 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
1859 <&gpi_ 1859 <&gpi_dma1 1 6 QCOM_GPI_SPI>;
1860 dma-names = " 1860 dma-names = "tx",
1861 " 1861 "rx";
1862 1862
1863 pinctrl-0 = < 1863 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
1864 pinctrl-names 1864 pinctrl-names = "default";
1865 1865
1866 #address-cell 1866 #address-cells = <1>;
1867 #size-cells = 1867 #size-cells = <0>;
1868 1868
1869 status = "dis 1869 status = "disabled";
1870 }; 1870 };
1871 1871
1872 i2c15: i2c@a9c000 { 1872 i2c15: i2c@a9c000 {
1873 compatible = 1873 compatible = "qcom,geni-i2c";
1874 reg = <0 0x00 1874 reg = <0 0x00a9c000 0 0x4000>;
1875 1875
1876 interrupts = 1876 interrupts = <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>;
1877 1877
1878 clocks = <&gc 1878 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1879 clock-names = 1879 clock-names = "se";
1880 1880
1881 interconnects 1881 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1882 1882 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1883 1883 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1884 1884 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1885 1885 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1886 1886 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1887 interconnect- 1887 interconnect-names = "qup-core",
1888 1888 "qup-config",
1889 1889 "qup-memory";
1890 1890
1891 dmas = <&gpi_ 1891 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
1892 <&gpi_ 1892 <&gpi_dma1 1 7 QCOM_GPI_I2C>;
1893 dma-names = " 1893 dma-names = "tx",
1894 " 1894 "rx";
1895 1895
1896 pinctrl-0 = < 1896 pinctrl-0 = <&qup_i2c15_data_clk>;
1897 pinctrl-names 1897 pinctrl-names = "default";
1898 1898
1899 #address-cell 1899 #address-cells = <1>;
1900 #size-cells = 1900 #size-cells = <0>;
1901 1901
1902 status = "dis 1902 status = "disabled";
1903 }; 1903 };
1904 1904
1905 spi15: spi@a9c000 { 1905 spi15: spi@a9c000 {
1906 compatible = 1906 compatible = "qcom,geni-spi";
1907 reg = <0 0x00 1907 reg = <0 0x00a9c000 0 0x4000>;
1908 1908
1909 interrupts = 1909 interrupts = <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>;
1910 1910
1911 clocks = <&gc 1911 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1912 clock-names = 1912 clock-names = "se";
1913 1913
1914 interconnects 1914 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1915 1915 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1916 1916 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1917 1917 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1918 1918 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1919 1919 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1920 interconnect- 1920 interconnect-names = "qup-core",
1921 1921 "qup-config",
1922 1922 "qup-memory";
1923 1923
1924 dmas = <&gpi_ 1924 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>,
1925 <&gpi_ 1925 <&gpi_dma1 1 7 QCOM_GPI_SPI>;
1926 dma-names = " 1926 dma-names = "tx",
1927 " 1927 "rx";
1928 1928
1929 pinctrl-0 = < 1929 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
1930 pinctrl-names 1930 pinctrl-names = "default";
1931 1931
1932 #address-cell 1932 #address-cells = <1>;
1933 #size-cells = 1933 #size-cells = <0>;
1934 1934
1935 status = "dis 1935 status = "disabled";
1936 }; 1936 };
1937 }; 1937 };
1938 1938
1939 gpi_dma0: dma-controller@b000 1939 gpi_dma0: dma-controller@b00000 {
1940 compatible = "qcom,x1 1940 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma";
1941 reg = <0 0x00b00000 0 1941 reg = <0 0x00b00000 0 0x60000>;
1942 1942
1943 interrupts = <GIC_SPI 1943 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
1944 <GIC_SPI 1944 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
1945 <GIC_SPI 1945 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
1946 <GIC_SPI 1946 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
1947 <GIC_SPI 1947 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
1948 <GIC_SPI 1948 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
1949 <GIC_SPI 1949 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
1950 <GIC_SPI 1950 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
1951 <GIC_SPI 1951 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
1952 <GIC_SPI 1952 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
1953 <GIC_SPI 1953 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
1954 <GIC_SPI 1954 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
1955 1955
1956 dma-channels = <12>; 1956 dma-channels = <12>;
1957 dma-channel-mask = <0 1957 dma-channel-mask = <0x3e>;
1958 #dma-cells = <3>; 1958 #dma-cells = <3>;
1959 1959
1960 iommus = <&apps_smmu 1960 iommus = <&apps_smmu 0x456 0x0>;
1961 1961
1962 status = "disabled"; 1962 status = "disabled";
1963 }; 1963 };
1964 1964
1965 qupv3_0: geniqup@bc0000 { 1965 qupv3_0: geniqup@bc0000 {
1966 compatible = "qcom,ge 1966 compatible = "qcom,geni-se-qup";
1967 reg = <0 0x00bc0000 0 1967 reg = <0 0x00bc0000 0 0x2000>;
1968 1968
1969 clocks = <&gcc GCC_QU 1969 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1970 <&gcc GCC_QU 1970 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1971 clock-names = "m-ahb" 1971 clock-names = "m-ahb",
1972 "s-ahb" 1972 "s-ahb";
1973 1973
1974 iommus = <&apps_smmu 1974 iommus = <&apps_smmu 0x443 0x0>;
1975 #address-cells = <2>; 1975 #address-cells = <2>;
1976 #size-cells = <2>; 1976 #size-cells = <2>;
1977 ranges; 1977 ranges;
1978 1978
1979 status = "disabled"; 1979 status = "disabled";
1980 1980
1981 i2c0: i2c@b80000 { 1981 i2c0: i2c@b80000 {
1982 compatible = 1982 compatible = "qcom,geni-i2c";
1983 reg = <0 0x00 1983 reg = <0 0x00b80000 0 0x4000>;
1984 1984
1985 interrupts = 1985 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1986 1986
1987 clocks = <&gc 1987 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1988 clock-names = 1988 clock-names = "se";
1989 1989
1990 interconnects 1990 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1991 1991 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1992 1992 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1993 1993 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
1994 1994 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
1995 1995 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1996 interconnect- 1996 interconnect-names = "qup-core",
1997 1997 "qup-config",
1998 1998 "qup-memory";
1999 1999
2000 dmas = <&gpi_ 2000 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
2001 <&gpi_ 2001 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
2002 dma-names = " 2002 dma-names = "tx",
2003 " 2003 "rx";
2004 2004
2005 pinctrl-0 = < 2005 pinctrl-0 = <&qup_i2c0_data_clk>;
2006 pinctrl-names 2006 pinctrl-names = "default";
2007 2007
2008 #address-cell 2008 #address-cells = <1>;
2009 #size-cells = 2009 #size-cells = <0>;
2010 2010
2011 status = "dis 2011 status = "disabled";
2012 }; 2012 };
2013 2013
2014 spi0: spi@b80000 { 2014 spi0: spi@b80000 {
2015 compatible = 2015 compatible = "qcom,geni-spi";
2016 reg = <0 0x00 2016 reg = <0 0x00b80000 0 0x4000>;
2017 2017
2018 interrupts = 2018 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
2019 2019
2020 clocks = <&gc 2020 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
2021 clock-names = 2021 clock-names = "se";
2022 2022
2023 interconnects 2023 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2024 2024 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2025 2025 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2026 2026 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2027 2027 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2028 2028 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2029 interconnect- 2029 interconnect-names = "qup-core",
2030 2030 "qup-config",
2031 2031 "qup-memory";
2032 2032
2033 dmas = <&gpi_ 2033 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
2034 <&gpi_ 2034 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
2035 dma-names = " 2035 dma-names = "tx",
2036 " 2036 "rx";
2037 2037
2038 pinctrl-0 = < 2038 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
2039 pinctrl-names 2039 pinctrl-names = "default";
2040 2040
2041 #address-cell 2041 #address-cells = <1>;
2042 #size-cells = 2042 #size-cells = <0>;
2043 2043
2044 status = "dis 2044 status = "disabled";
2045 }; 2045 };
2046 2046
2047 i2c1: i2c@b84000 { 2047 i2c1: i2c@b84000 {
2048 compatible = 2048 compatible = "qcom,geni-i2c";
2049 reg = <0 0x00 2049 reg = <0 0x00b84000 0 0x4000>;
2050 2050
2051 interrupts = 2051 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
2052 2052
2053 clocks = <&gc 2053 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
2054 clock-names = 2054 clock-names = "se";
2055 2055
2056 interconnects 2056 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2057 2057 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2058 2058 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2059 2059 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2060 2060 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2061 2061 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2062 interconnect- 2062 interconnect-names = "qup-core",
2063 2063 "qup-config",
2064 2064 "qup-memory";
2065 2065
2066 dmas = <&gpi_ 2066 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
2067 <&gpi_ 2067 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
2068 dma-names = " 2068 dma-names = "tx",
2069 " 2069 "rx";
2070 2070
2071 pinctrl-0 = < 2071 pinctrl-0 = <&qup_i2c1_data_clk>;
2072 pinctrl-names 2072 pinctrl-names = "default";
2073 2073
2074 #address-cell 2074 #address-cells = <1>;
2075 #size-cells = 2075 #size-cells = <0>;
2076 2076
2077 status = "dis 2077 status = "disabled";
2078 }; 2078 };
2079 2079
2080 spi1: spi@b84000 { 2080 spi1: spi@b84000 {
2081 compatible = 2081 compatible = "qcom,geni-spi";
2082 reg = <0 0x00 2082 reg = <0 0x00b84000 0 0x4000>;
2083 2083
2084 interrupts = 2084 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
2085 2085
2086 clocks = <&gc 2086 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
2087 clock-names = 2087 clock-names = "se";
2088 2088
2089 interconnects 2089 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2090 2090 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2091 2091 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2092 2092 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2093 2093 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2094 2094 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2095 interconnect- 2095 interconnect-names = "qup-core",
2096 2096 "qup-config",
2097 2097 "qup-memory";
2098 2098
2099 dmas = <&gpi_ 2099 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
2100 <&gpi_ 2100 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
2101 dma-names = " 2101 dma-names = "tx",
2102 " 2102 "rx";
2103 2103
2104 pinctrl-0 = < 2104 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
2105 pinctrl-names 2105 pinctrl-names = "default";
2106 2106
2107 #address-cell 2107 #address-cells = <1>;
2108 #size-cells = 2108 #size-cells = <0>;
2109 2109
2110 status = "dis 2110 status = "disabled";
2111 }; 2111 };
2112 2112
2113 i2c2: i2c@b88000 { 2113 i2c2: i2c@b88000 {
2114 compatible = 2114 compatible = "qcom,geni-i2c";
2115 reg = <0 0x00 2115 reg = <0 0x00b88000 0 0x4000>;
2116 2116
2117 interrupts = 2117 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
2118 2118
2119 clocks = <&gc 2119 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
2120 clock-names = 2120 clock-names = "se";
2121 2121
2122 interconnects 2122 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2123 2123 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2124 2124 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2125 2125 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2126 2126 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2127 2127 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2128 interconnect- 2128 interconnect-names = "qup-core",
2129 2129 "qup-config",
2130 2130 "qup-memory";
2131 2131
2132 dmas = <&gpi_ 2132 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
2133 <&gpi_ 2133 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
2134 dma-names = " 2134 dma-names = "tx",
2135 " 2135 "rx";
2136 2136
2137 pinctrl-0 = < 2137 pinctrl-0 = <&qup_i2c2_data_clk>;
2138 pinctrl-names 2138 pinctrl-names = "default";
2139 2139
2140 #address-cell 2140 #address-cells = <1>;
2141 #size-cells = 2141 #size-cells = <0>;
2142 2142
2143 status = "dis 2143 status = "disabled";
2144 }; 2144 };
2145 2145
2146 uart2: serial@b88000 2146 uart2: serial@b88000 {
2147 compatible = 2147 compatible = "qcom,geni-uart";
2148 reg = <0 0x00 2148 reg = <0 0x00b88000 0 0x4000>;
2149 2149
2150 interrupts = 2150 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
2151 2151
2152 clocks = <&gc 2152 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
2153 clock-names = 2153 clock-names = "se";
2154 2154
2155 interconnects 2155 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2156 2156 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2157 2157 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2158 2158 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
2159 interconnect- 2159 interconnect-names = "qup-core",
2160 2160 "qup-config";
2161 2161
2162 pinctrl-0 = < 2162 pinctrl-0 = <&qup_uart2_default>;
2163 pinctrl-names 2163 pinctrl-names = "default";
2164 2164
2165 status = "dis 2165 status = "disabled";
2166 }; 2166 };
2167 2167
2168 spi2: spi@b88000 { 2168 spi2: spi@b88000 {
2169 compatible = 2169 compatible = "qcom,geni-spi";
2170 reg = <0 0x00 2170 reg = <0 0x00b88000 0 0x4000>;
2171 2171
2172 interrupts = 2172 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
2173 2173
2174 clocks = <&gc 2174 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
2175 clock-names = 2175 clock-names = "se";
2176 2176
2177 interconnects 2177 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2178 2178 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2179 2179 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2180 2180 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2181 2181 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2182 2182 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2183 interconnect- 2183 interconnect-names = "qup-core",
2184 2184 "qup-config",
2185 2185 "qup-memory";
2186 2186
2187 dmas = <&gpi_ 2187 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
2188 <&gpi_ 2188 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
2189 dma-names = " 2189 dma-names = "tx",
2190 " 2190 "rx";
2191 2191
2192 pinctrl-0 = < 2192 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
2193 pinctrl-names 2193 pinctrl-names = "default";
2194 2194
2195 #address-cell 2195 #address-cells = <1>;
2196 #size-cells = 2196 #size-cells = <0>;
2197 2197
2198 status = "dis 2198 status = "disabled";
2199 }; 2199 };
2200 2200
2201 i2c3: i2c@b8c000 { 2201 i2c3: i2c@b8c000 {
2202 compatible = 2202 compatible = "qcom,geni-i2c";
2203 reg = <0 0x00 2203 reg = <0 0x00b8c000 0 0x4000>;
2204 2204
2205 interrupts = 2205 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
2206 2206
2207 clocks = <&gc 2207 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
2208 clock-names = 2208 clock-names = "se";
2209 2209
2210 interconnects 2210 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2211 2211 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2212 2212 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2213 2213 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2214 2214 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2215 2215 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2216 interconnect- 2216 interconnect-names = "qup-core",
2217 2217 "qup-config",
2218 2218 "qup-memory";
2219 2219
2220 dmas = <&gpi_ 2220 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
2221 <&gpi_ 2221 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
2222 dma-names = " 2222 dma-names = "tx",
2223 " 2223 "rx";
2224 2224
2225 pinctrl-0 = < 2225 pinctrl-0 = <&qup_i2c3_data_clk>;
2226 pinctrl-names 2226 pinctrl-names = "default";
2227 2227
2228 #address-cell 2228 #address-cells = <1>;
2229 #size-cells = 2229 #size-cells = <0>;
2230 2230
2231 status = "dis 2231 status = "disabled";
2232 }; 2232 };
2233 2233
2234 spi3: spi@b8c000 { 2234 spi3: spi@b8c000 {
2235 compatible = 2235 compatible = "qcom,geni-spi";
2236 reg = <0 0x00 2236 reg = <0 0x00b8c000 0 0x4000>;
2237 2237
2238 interrupts = 2238 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
2239 2239
2240 clocks = <&gc 2240 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
2241 clock-names = 2241 clock-names = "se";
2242 2242
2243 interconnects 2243 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2244 2244 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2245 2245 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2246 2246 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2247 2247 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2248 2248 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2249 interconnect- 2249 interconnect-names = "qup-core",
2250 2250 "qup-config",
2251 2251 "qup-memory";
2252 2252
2253 dmas = <&gpi_ 2253 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
2254 <&gpi_ 2254 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
2255 dma-names = " 2255 dma-names = "tx",
2256 " 2256 "rx";
2257 2257
2258 pinctrl-0 = < 2258 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
2259 pinctrl-names 2259 pinctrl-names = "default";
2260 2260
2261 #address-cell 2261 #address-cells = <1>;
2262 #size-cells = 2262 #size-cells = <0>;
2263 2263
2264 status = "dis 2264 status = "disabled";
2265 }; 2265 };
2266 2266
2267 i2c4: i2c@b90000 { 2267 i2c4: i2c@b90000 {
2268 compatible = 2268 compatible = "qcom,geni-i2c";
2269 reg = <0 0x00 2269 reg = <0 0x00b90000 0 0x4000>;
2270 2270
2271 interrupts = 2271 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
2272 2272
2273 clocks = <&gc 2273 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
2274 clock-names = 2274 clock-names = "se";
2275 2275
2276 interconnects 2276 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2277 2277 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2278 2278 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2279 2279 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2280 2280 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2281 2281 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2282 interconnect- 2282 interconnect-names = "qup-core",
2283 2283 "qup-config",
2284 2284 "qup-memory";
2285 2285
2286 dmas = <&gpi_ 2286 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
2287 <&gpi_ 2287 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
2288 dma-names = " 2288 dma-names = "tx",
2289 " 2289 "rx";
2290 2290
2291 pinctrl-0 = < 2291 pinctrl-0 = <&qup_i2c4_data_clk>;
2292 pinctrl-names 2292 pinctrl-names = "default";
2293 2293
2294 #address-cell 2294 #address-cells = <1>;
2295 #size-cells = 2295 #size-cells = <0>;
2296 2296
2297 status = "dis 2297 status = "disabled";
2298 }; 2298 };
2299 2299
2300 spi4: spi@b90000 { 2300 spi4: spi@b90000 {
2301 compatible = 2301 compatible = "qcom,geni-spi";
2302 reg = <0 0x00 2302 reg = <0 0x00b90000 0 0x4000>;
2303 2303
2304 interrupts = 2304 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
2305 2305
2306 clocks = <&gc 2306 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
2307 clock-names = 2307 clock-names = "se";
2308 2308
2309 interconnects 2309 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2310 2310 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2311 2311 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2312 2312 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2313 2313 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2314 2314 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2315 interconnect- 2315 interconnect-names = "qup-core",
2316 2316 "qup-config",
2317 2317 "qup-memory";
2318 2318
2319 dmas = <&gpi_ 2319 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
2320 <&gpi_ 2320 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
2321 dma-names = " 2321 dma-names = "tx",
2322 " 2322 "rx";
2323 2323
2324 pinctrl-0 = < 2324 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
2325 pinctrl-names 2325 pinctrl-names = "default";
2326 2326
2327 #address-cell 2327 #address-cells = <1>;
2328 #size-cells = 2328 #size-cells = <0>;
2329 2329
2330 status = "dis 2330 status = "disabled";
2331 }; 2331 };
2332 2332
2333 i2c5: i2c@b94000 { 2333 i2c5: i2c@b94000 {
2334 compatible = 2334 compatible = "qcom,geni-i2c";
2335 reg = <0 0x00 2335 reg = <0 0x00b94000 0 0x4000>;
2336 2336
2337 interrupts = 2337 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
2338 2338
2339 clocks = <&gc 2339 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
2340 clock-names = 2340 clock-names = "se";
2341 2341
2342 interconnects 2342 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2343 2343 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2344 2344 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2345 2345 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2346 2346 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2347 2347 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2348 interconnect- 2348 interconnect-names = "qup-core",
2349 2349 "qup-config",
2350 2350 "qup-memory";
2351 2351
2352 dmas = <&gpi_ 2352 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
2353 <&gpi_ 2353 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
2354 dma-names = " 2354 dma-names = "tx",
2355 " 2355 "rx";
2356 2356
2357 pinctrl-0 = < 2357 pinctrl-0 = <&qup_i2c5_data_clk>;
2358 pinctrl-names 2358 pinctrl-names = "default";
2359 2359
2360 #address-cell 2360 #address-cells = <1>;
2361 #size-cells = 2361 #size-cells = <0>;
2362 2362
2363 status = "dis 2363 status = "disabled";
2364 }; 2364 };
2365 2365
2366 spi5: spi@b94000 { 2366 spi5: spi@b94000 {
2367 compatible = 2367 compatible = "qcom,geni-spi";
2368 reg = <0 0x00 2368 reg = <0 0x00b94000 0 0x4000>;
2369 2369
2370 interrupts = 2370 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
2371 2371
2372 clocks = <&gc 2372 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
2373 clock-names = 2373 clock-names = "se";
2374 2374
2375 interconnects 2375 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2376 2376 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2377 2377 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2378 2378 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2379 2379 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2380 2380 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2381 interconnect- 2381 interconnect-names = "qup-core",
2382 2382 "qup-config",
2383 2383 "qup-memory";
2384 2384
2385 dmas = <&gpi_ 2385 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
2386 <&gpi_ 2386 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
2387 dma-names = " 2387 dma-names = "tx",
2388 " 2388 "rx";
2389 2389
2390 pinctrl-0 = < 2390 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
2391 pinctrl-names 2391 pinctrl-names = "default";
2392 2392
2393 #address-cell 2393 #address-cells = <1>;
2394 #size-cells = 2394 #size-cells = <0>;
2395 2395
2396 status = "dis 2396 status = "disabled";
2397 }; 2397 };
2398 2398
2399 i2c6: i2c@b98000 { 2399 i2c6: i2c@b98000 {
2400 compatible = 2400 compatible = "qcom,geni-i2c";
2401 reg = <0 0x00 2401 reg = <0 0x00b98000 0 0x4000>;
2402 2402
2403 interrupts = 2403 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
2404 2404
2405 clocks = <&gc 2405 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
2406 clock-names = 2406 clock-names = "se";
2407 2407
2408 interconnects 2408 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2409 2409 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2410 2410 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2411 2411 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2412 2412 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2413 2413 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2414 interconnect- 2414 interconnect-names = "qup-core",
2415 2415 "qup-config",
2416 2416 "qup-memory";
2417 2417
2418 dmas = <&gpi_ 2418 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
2419 <&gpi_ 2419 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
2420 dma-names = " 2420 dma-names = "tx",
2421 " 2421 "rx";
2422 2422
2423 pinctrl-0 = < 2423 pinctrl-0 = <&qup_i2c6_data_clk>;
2424 pinctrl-names 2424 pinctrl-names = "default";
2425 2425
2426 #address-cell 2426 #address-cells = <1>;
2427 #size-cells = 2427 #size-cells = <0>;
2428 2428
2429 status = "dis 2429 status = "disabled";
2430 }; 2430 };
2431 2431
2432 spi6: spi@b98000 { 2432 spi6: spi@b98000 {
2433 compatible = 2433 compatible = "qcom,geni-spi";
2434 reg = <0 0x00 2434 reg = <0 0x00b98000 0 0x4000>;
2435 2435
2436 interrupts = 2436 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
2437 2437
2438 clocks = <&gc 2438 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
2439 clock-names = 2439 clock-names = "se";
2440 2440
2441 interconnects 2441 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2442 2442 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2443 2443 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2444 2444 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2445 2445 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2446 2446 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2447 interconnect- 2447 interconnect-names = "qup-core",
2448 2448 "qup-config",
2449 2449 "qup-memory";
2450 2450
2451 dmas = <&gpi_ 2451 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
2452 <&gpi_ 2452 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
2453 dma-names = " 2453 dma-names = "tx",
2454 " 2454 "rx";
2455 2455
2456 pinctrl-0 = < 2456 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
2457 pinctrl-names 2457 pinctrl-names = "default";
2458 2458
2459 #address-cell 2459 #address-cells = <1>;
2460 #size-cells = 2460 #size-cells = <0>;
2461 2461
2462 status = "dis 2462 status = "disabled";
2463 }; 2463 };
2464 2464
2465 i2c7: i2c@b9c000 { 2465 i2c7: i2c@b9c000 {
2466 compatible = 2466 compatible = "qcom,geni-i2c";
2467 reg = <0 0x00 2467 reg = <0 0x00b9c000 0 0x4000>;
2468 2468
2469 interrupts = 2469 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
2470 2470
2471 clocks = <&gc 2471 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
2472 clock-names = 2472 clock-names = "se";
2473 2473
2474 interconnects 2474 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2475 2475 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2476 2476 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2477 2477 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2478 2478 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2479 2479 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2480 interconnect- 2480 interconnect-names = "qup-core",
2481 2481 "qup-config",
2482 2482 "qup-memory";
2483 2483
2484 dmas = <&gpi_ 2484 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
2485 <&gpi_ 2485 <&gpi_dma0 1 7 QCOM_GPI_I2C>;
2486 dma-names = " 2486 dma-names = "tx",
2487 " 2487 "rx";
2488 2488
2489 pinctrl-0 = < 2489 pinctrl-0 = <&qup_i2c7_data_clk>;
2490 pinctrl-names 2490 pinctrl-names = "default";
2491 2491
2492 #address-cell 2492 #address-cells = <1>;
2493 #size-cells = 2493 #size-cells = <0>;
2494 2494
2495 status = "dis 2495 status = "disabled";
2496 }; 2496 };
2497 2497
2498 spi7: spi@b9c000 { 2498 spi7: spi@b9c000 {
2499 compatible = 2499 compatible = "qcom,geni-spi";
2500 reg = <0 0x00 2500 reg = <0 0x00b9c000 0 0x4000>;
2501 2501
2502 interrupts = 2502 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
2503 2503
2504 clocks = <&gc 2504 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
2505 clock-names = 2505 clock-names = "se";
2506 2506
2507 interconnects 2507 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2508 2508 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2509 2509 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2510 2510 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
2511 2511 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2512 2512 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2513 interconnect- 2513 interconnect-names = "qup-core",
2514 2514 "qup-config",
2515 2515 "qup-memory";
2516 2516
2517 dmas = <&gpi_ 2517 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
2518 <&gpi_ 2518 <&gpi_dma0 1 7 QCOM_GPI_SPI>;
2519 dma-names = " 2519 dma-names = "tx",
2520 " 2520 "rx";
2521 2521
2522 pinctrl-0 = < 2522 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
2523 pinctrl-names 2523 pinctrl-names = "default";
2524 2524
2525 #address-cell 2525 #address-cells = <1>;
2526 #size-cells = 2526 #size-cells = <0>;
2527 2527
2528 status = "dis 2528 status = "disabled";
2529 }; 2529 };
2530 }; 2530 };
2531 2531
2532 tsens0: thermal-sensor@c27100 2532 tsens0: thermal-sensor@c271000 {
2533 compatible = "qcom,x1 2533 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2";
2534 reg = <0 0x0c271000 0 2534 reg = <0 0x0c271000 0 0x1000>,
2535 <0 0x0c222000 0 2535 <0 0x0c222000 0 0x1000>;
2536 2536
2537 interrupts-extended = 2537 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
2538 2538 <&intc GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>;
2539 interrupt-names = "up 2539 interrupt-names = "uplow",
2540 "cr 2540 "critical";
2541 2541
2542 #qcom,sensors = <16>; 2542 #qcom,sensors = <16>;
2543 2543
2544 #thermal-sensor-cells 2544 #thermal-sensor-cells = <1>;
2545 }; 2545 };
2546 2546
2547 tsens1: thermal-sensor@c27200 2547 tsens1: thermal-sensor@c272000 {
2548 compatible = "qcom,x1 2548 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2";
2549 reg = <0 0x0c272000 0 2549 reg = <0 0x0c272000 0 0x1000>,
2550 <0 0x0c223000 0 2550 <0 0x0c223000 0 0x1000>;
2551 2551
2552 interrupts-extended = 2552 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
2553 2553 <&intc GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>;
2554 interrupt-names = "up 2554 interrupt-names = "uplow",
2555 "cr 2555 "critical";
2556 2556
2557 #qcom,sensors = <16>; 2557 #qcom,sensors = <16>;
2558 2558
2559 #thermal-sensor-cells 2559 #thermal-sensor-cells = <1>;
2560 }; 2560 };
2561 2561
2562 tsens2: thermal-sensor@c27300 2562 tsens2: thermal-sensor@c273000 {
2563 compatible = "qcom,x1 2563 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2";
2564 reg = <0 0x0c273000 0 2564 reg = <0 0x0c273000 0 0x1000>,
2565 <0 0x0c224000 0 2565 <0 0x0c224000 0 0x1000>;
2566 2566
2567 interrupts-extended = 2567 interrupts-extended = <&pdc 28 IRQ_TYPE_LEVEL_HIGH>,
2568 2568 <&intc GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH>;
2569 interrupt-names = "up 2569 interrupt-names = "uplow",
2570 "cr 2570 "critical";
2571 2571
2572 #qcom,sensors = <16>; 2572 #qcom,sensors = <16>;
2573 2573
2574 #thermal-sensor-cells 2574 #thermal-sensor-cells = <1>;
2575 }; 2575 };
2576 2576
2577 tsens3: thermal-sensor@c27400 2577 tsens3: thermal-sensor@c274000 {
2578 compatible = "qcom,x1 2578 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2";
2579 reg = <0 0x0c274000 0 2579 reg = <0 0x0c274000 0 0x1000>,
2580 <0 0x0c225000 0 2580 <0 0x0c225000 0 0x1000>;
2581 2581
2582 interrupts-extended = 2582 interrupts-extended = <&pdc 29 IRQ_TYPE_LEVEL_HIGH>,
2583 2583 <&intc GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>;
2584 interrupt-names = "up 2584 interrupt-names = "uplow",
2585 "cr 2585 "critical";
2586 2586
2587 #qcom,sensors = <16>; 2587 #qcom,sensors = <16>;
2588 2588
2589 #thermal-sensor-cells 2589 #thermal-sensor-cells = <1>;
2590 }; 2590 };
2591 2591
2592 usb_1_ss0_hsphy: phy@fd3000 { 2592 usb_1_ss0_hsphy: phy@fd3000 {
2593 compatible = "qcom,x1 2593 compatible = "qcom,x1e80100-snps-eusb2-phy",
2594 "qcom,sm 2594 "qcom,sm8550-snps-eusb2-phy";
2595 reg = <0 0x00fd3000 0 2595 reg = <0 0x00fd3000 0 0x154>;
2596 #phy-cells = <0>; 2596 #phy-cells = <0>;
2597 2597
2598 clocks = <&tcsr TCSR_ 2598 clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>;
2599 clock-names = "ref"; 2599 clock-names = "ref";
2600 2600
2601 resets = <&gcc GCC_QU 2601 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2602 2602
2603 status = "disabled"; 2603 status = "disabled";
2604 }; 2604 };
2605 2605
2606 usb_1_ss0_qmpphy: phy@fd5000 2606 usb_1_ss0_qmpphy: phy@fd5000 {
2607 compatible = "qcom,x1 2607 compatible = "qcom,x1e80100-qmp-usb3-dp-phy";
2608 reg = <0 0x00fd5000 0 2608 reg = <0 0x00fd5000 0 0x4000>;
2609 2609
2610 clocks = <&gcc GCC_US 2610 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2611 <&rpmhcc RPM 2611 <&rpmhcc RPMH_CXO_CLK>,
2612 <&gcc GCC_US 2612 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
2613 <&gcc GCC_US 2613 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2614 clock-names = "aux", 2614 clock-names = "aux",
2615 "ref", 2615 "ref",
2616 "com_au 2616 "com_aux",
2617 "usb3_p 2617 "usb3_pipe";
2618 2618
2619 power-domains = <&gcc 2619 power-domains = <&gcc GCC_USB_0_PHY_GDSC>;
2620 2620
2621 resets = <&gcc GCC_US 2621 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
2622 <&gcc GCC_US 2622 <&gcc GCC_USB4_0_DP0_PHY_PRIM_BCR>;
2623 reset-names = "phy", 2623 reset-names = "phy",
2624 "common 2624 "common";
2625 2625
2626 #clock-cells = <1>; 2626 #clock-cells = <1>;
2627 #phy-cells = <1>; 2627 #phy-cells = <1>;
2628 2628
2629 orientation-switch; 2629 orientation-switch;
2630 2630
2631 status = "disabled"; 2631 status = "disabled";
2632 2632
2633 ports { 2633 ports {
2634 #address-cell 2634 #address-cells = <1>;
2635 #size-cells = 2635 #size-cells = <0>;
2636 2636
2637 port@0 { 2637 port@0 {
2638 reg = 2638 reg = <0>;
2639 2639
2640 usb_1 2640 usb_1_ss0_qmpphy_out: endpoint {
2641 }; 2641 };
2642 }; 2642 };
2643 2643
2644 port@1 { 2644 port@1 {
2645 reg = 2645 reg = <1>;
2646 2646
2647 usb_1 2647 usb_1_ss0_qmpphy_usb_ss_in: endpoint {
2648 2648 remote-endpoint = <&usb_1_ss0_dwc3_ss>;
2649 }; 2649 };
2650 }; 2650 };
2651 2651
2652 port@2 { 2652 port@2 {
2653 reg = 2653 reg = <2>;
2654 2654
2655 usb_1 2655 usb_1_ss0_qmpphy_dp_in: endpoint {
2656 2656 remote-endpoint = <&mdss_dp0_out>;
2657 }; 2657 };
2658 }; 2658 };
2659 }; 2659 };
2660 }; 2660 };
2661 2661
2662 usb_1_ss1_hsphy: phy@fd9000 { 2662 usb_1_ss1_hsphy: phy@fd9000 {
2663 compatible = "qcom,x1 2663 compatible = "qcom,x1e80100-snps-eusb2-phy",
2664 "qcom,sm 2664 "qcom,sm8550-snps-eusb2-phy";
2665 reg = <0 0x00fd9000 0 2665 reg = <0 0x00fd9000 0 0x154>;
2666 #phy-cells = <0>; 2666 #phy-cells = <0>;
2667 2667
2668 clocks = <&tcsr TCSR_ 2668 clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>;
2669 clock-names = "ref"; 2669 clock-names = "ref";
2670 2670
2671 resets = <&gcc GCC_QU 2671 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
2672 2672
2673 status = "disabled"; 2673 status = "disabled";
2674 }; 2674 };
2675 2675
2676 usb_1_ss1_qmpphy: phy@fda000 2676 usb_1_ss1_qmpphy: phy@fda000 {
2677 compatible = "qcom,x1 2677 compatible = "qcom,x1e80100-qmp-usb3-dp-phy";
2678 reg = <0 0x00fda000 0 2678 reg = <0 0x00fda000 0 0x4000>;
2679 2679
2680 clocks = <&gcc GCC_US 2680 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
2681 <&rpmhcc RPM 2681 <&rpmhcc RPMH_CXO_CLK>,
2682 <&gcc GCC_US 2682 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
2683 <&gcc GCC_US 2683 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
2684 clock-names = "aux", 2684 clock-names = "aux",
2685 "ref", 2685 "ref",
2686 "com_au 2686 "com_aux",
2687 "usb3_p 2687 "usb3_pipe";
2688 2688
2689 power-domains = <&gcc 2689 power-domains = <&gcc GCC_USB_1_PHY_GDSC>;
2690 2690
2691 resets = <&gcc GCC_US 2691 resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
2692 <&gcc GCC_US 2692 <&gcc GCC_USB4_1_DP0_PHY_SEC_BCR>;
2693 reset-names = "phy", 2693 reset-names = "phy",
2694 "common 2694 "common";
2695 2695
2696 #clock-cells = <1>; 2696 #clock-cells = <1>;
2697 #phy-cells = <1>; 2697 #phy-cells = <1>;
2698 2698
2699 orientation-switch; 2699 orientation-switch;
2700 2700
2701 status = "disabled"; 2701 status = "disabled";
2702 2702
2703 ports { 2703 ports {
2704 #address-cell 2704 #address-cells = <1>;
2705 #size-cells = 2705 #size-cells = <0>;
2706 2706
2707 port@0 { 2707 port@0 {
2708 reg = 2708 reg = <0>;
2709 2709
2710 usb_1 2710 usb_1_ss1_qmpphy_out: endpoint {
2711 }; 2711 };
2712 }; 2712 };
2713 2713
2714 port@1 { 2714 port@1 {
2715 reg = 2715 reg = <1>;
2716 2716
2717 usb_1 2717 usb_1_ss1_qmpphy_usb_ss_in: endpoint {
2718 2718 remote-endpoint = <&usb_1_ss1_dwc3_ss>;
2719 }; 2719 };
2720 }; 2720 };
2721 2721
2722 port@2 { 2722 port@2 {
2723 reg = 2723 reg = <2>;
2724 2724
2725 usb_1 2725 usb_1_ss1_qmpphy_dp_in: endpoint {
2726 2726 remote-endpoint = <&mdss_dp1_out>;
2727 }; 2727 };
2728 }; 2728 };
2729 }; 2729 };
2730 }; 2730 };
2731 2731
2732 usb_1_ss2_hsphy: phy@fde000 { 2732 usb_1_ss2_hsphy: phy@fde000 {
2733 compatible = "qcom,x1 2733 compatible = "qcom,x1e80100-snps-eusb2-phy",
2734 "qcom,sm 2734 "qcom,sm8550-snps-eusb2-phy";
2735 reg = <0 0x00fde000 0 2735 reg = <0 0x00fde000 0 0x154>;
2736 #phy-cells = <0>; 2736 #phy-cells = <0>;
2737 2737
2738 clocks = <&tcsr TCSR_ 2738 clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>;
2739 clock-names = "ref"; 2739 clock-names = "ref";
2740 2740
2741 resets = <&gcc GCC_QU 2741 resets = <&gcc GCC_QUSB2PHY_TERT_BCR>;
2742 2742
2743 status = "disabled"; 2743 status = "disabled";
2744 }; 2744 };
2745 2745
2746 usb_1_ss2_qmpphy: phy@fdf000 2746 usb_1_ss2_qmpphy: phy@fdf000 {
2747 compatible = "qcom,x1 2747 compatible = "qcom,x1e80100-qmp-usb3-dp-phy";
2748 reg = <0 0x00fdf000 0 2748 reg = <0 0x00fdf000 0 0x4000>;
2749 2749
2750 clocks = <&gcc GCC_US 2750 clocks = <&gcc GCC_USB3_TERT_PHY_AUX_CLK>,
2751 <&rpmhcc RPM 2751 <&rpmhcc RPMH_CXO_CLK>,
2752 <&gcc GCC_US 2752 <&gcc GCC_USB3_TERT_PHY_COM_AUX_CLK>,
2753 <&gcc GCC_US 2753 <&gcc GCC_USB3_TERT_PHY_PIPE_CLK>;
2754 clock-names = "aux", 2754 clock-names = "aux",
2755 "ref", 2755 "ref",
2756 "com_au 2756 "com_aux",
2757 "usb3_p 2757 "usb3_pipe";
2758 2758
2759 power-domains = <&gcc 2759 power-domains = <&gcc GCC_USB_2_PHY_GDSC>;
2760 2760
2761 resets = <&gcc GCC_US 2761 resets = <&gcc GCC_USB3_PHY_TERT_BCR>,
2762 <&gcc GCC_US 2762 <&gcc GCC_USB4_2_DP0_PHY_TERT_BCR>;
2763 reset-names = "phy", 2763 reset-names = "phy",
2764 "common 2764 "common";
2765 2765
2766 #clock-cells = <1>; 2766 #clock-cells = <1>;
2767 #phy-cells = <1>; 2767 #phy-cells = <1>;
2768 2768
2769 orientation-switch; 2769 orientation-switch;
2770 2770
2771 status = "disabled"; 2771 status = "disabled";
2772 2772
2773 ports { 2773 ports {
2774 #address-cell 2774 #address-cells = <1>;
2775 #size-cells = 2775 #size-cells = <0>;
2776 2776
2777 port@0 { 2777 port@0 {
2778 reg = 2778 reg = <0>;
2779 2779
2780 usb_1 2780 usb_1_ss2_qmpphy_out: endpoint {
2781 }; 2781 };
2782 }; 2782 };
2783 2783
2784 port@1 { 2784 port@1 {
2785 reg = 2785 reg = <1>;
2786 2786
2787 usb_1 2787 usb_1_ss2_qmpphy_usb_ss_in: endpoint {
2788 2788 remote-endpoint = <&usb_1_ss2_dwc3_ss>;
2789 }; 2789 };
2790 }; 2790 };
2791 2791
2792 port@2 { 2792 port@2 {
2793 reg = 2793 reg = <2>;
2794 2794
2795 usb_1 2795 usb_1_ss2_qmpphy_dp_in: endpoint {
2796 2796 remote-endpoint = <&mdss_dp2_out>;
2797 }; 2797 };
2798 }; 2798 };
2799 }; 2799 };
2800 }; 2800 };
2801 2801
2802 cnoc_main: interconnect@15000 2802 cnoc_main: interconnect@1500000 {
2803 compatible = "qcom,x1 2803 compatible = "qcom,x1e80100-cnoc-main";
2804 reg = <0 0x01500000 0 2804 reg = <0 0x01500000 0 0x14400>;
2805 2805
2806 qcom,bcm-voters = <&a 2806 qcom,bcm-voters = <&apps_bcm_voter>;
2807 2807
2808 #interconnect-cells = 2808 #interconnect-cells = <2>;
2809 }; 2809 };
2810 2810
2811 config_noc: interconnect@1600 2811 config_noc: interconnect@1600000 {
2812 compatible = "qcom,x1 2812 compatible = "qcom,x1e80100-cnoc-cfg";
2813 reg = <0 0x01600000 0 2813 reg = <0 0x01600000 0 0x6600>;
2814 2814
2815 qcom,bcm-voters = <&a 2815 qcom,bcm-voters = <&apps_bcm_voter>;
2816 2816
2817 #interconnect-cells = 2817 #interconnect-cells = <2>;
2818 }; 2818 };
2819 2819
2820 system_noc: interconnect@1680 2820 system_noc: interconnect@1680000 {
2821 compatible = "qcom,x1 2821 compatible = "qcom,x1e80100-system-noc";
2822 reg = <0 0x01680000 0 2822 reg = <0 0x01680000 0 0x1c080>;
2823 2823
2824 qcom,bcm-voters = <&a 2824 qcom,bcm-voters = <&apps_bcm_voter>;
2825 2825
2826 #interconnect-cells = 2826 #interconnect-cells = <2>;
2827 }; 2827 };
2828 2828
2829 pcie_south_anoc: interconnect 2829 pcie_south_anoc: interconnect@16c0000 {
2830 compatible = "qcom,x1 2830 compatible = "qcom,x1e80100-pcie-south-anoc";
2831 reg = <0 0x016c0000 0 2831 reg = <0 0x016c0000 0 0xd080>;
2832 2832
2833 qcom,bcm-voters = <&a 2833 qcom,bcm-voters = <&apps_bcm_voter>;
2834 2834
2835 #interconnect-cells = 2835 #interconnect-cells = <2>;
2836 }; 2836 };
2837 2837
2838 pcie_center_anoc: interconnec 2838 pcie_center_anoc: interconnect@16d0000 {
2839 compatible = "qcom,x1 2839 compatible = "qcom,x1e80100-pcie-center-anoc";
2840 reg = <0 0x016d0000 0 2840 reg = <0 0x016d0000 0 0x7000>;
2841 2841
2842 qcom,bcm-voters = <&a 2842 qcom,bcm-voters = <&apps_bcm_voter>;
2843 2843
2844 #interconnect-cells = 2844 #interconnect-cells = <2>;
2845 }; 2845 };
2846 2846
2847 aggre1_noc: interconnect@16e0 2847 aggre1_noc: interconnect@16e0000 {
2848 compatible = "qcom,x1 2848 compatible = "qcom,x1e80100-aggre1-noc";
2849 reg = <0 0x016e0000 0 2849 reg = <0 0x016e0000 0 0x14400>;
2850 2850
2851 qcom,bcm-voters = <&a 2851 qcom,bcm-voters = <&apps_bcm_voter>;
2852 2852
2853 #interconnect-cells = 2853 #interconnect-cells = <2>;
2854 }; 2854 };
2855 2855
2856 aggre2_noc: interconnect@1700 2856 aggre2_noc: interconnect@1700000 {
2857 compatible = "qcom,x1 2857 compatible = "qcom,x1e80100-aggre2-noc";
2858 reg = <0 0x01700000 0 2858 reg = <0 0x01700000 0 0x1c400>;
2859 2859
2860 qcom,bcm-voters = <&a 2860 qcom,bcm-voters = <&apps_bcm_voter>;
2861 2861
2862 #interconnect-cells = 2862 #interconnect-cells = <2>;
2863 }; 2863 };
2864 2864
2865 pcie_north_anoc: interconnect 2865 pcie_north_anoc: interconnect@1740000 {
2866 compatible = "qcom,x1 2866 compatible = "qcom,x1e80100-pcie-north-anoc";
2867 reg = <0 0x01740000 0 2867 reg = <0 0x01740000 0 0x9080>;
2868 2868
2869 qcom,bcm-voters = <&a 2869 qcom,bcm-voters = <&apps_bcm_voter>;
2870 2870
2871 #interconnect-cells = 2871 #interconnect-cells = <2>;
2872 }; 2872 };
2873 2873
2874 usb_center_anoc: interconnect 2874 usb_center_anoc: interconnect@1750000 {
2875 compatible = "qcom,x1 2875 compatible = "qcom,x1e80100-usb-center-anoc";
2876 reg = <0 0x01750000 0 2876 reg = <0 0x01750000 0 0x8800>;
2877 2877
2878 qcom,bcm-voters = <&a 2878 qcom,bcm-voters = <&apps_bcm_voter>;
2879 2879
2880 #interconnect-cells = 2880 #interconnect-cells = <2>;
2881 }; 2881 };
2882 2882
2883 usb_north_anoc: interconnect@ 2883 usb_north_anoc: interconnect@1760000 {
2884 compatible = "qcom,x1 2884 compatible = "qcom,x1e80100-usb-north-anoc";
2885 reg = <0 0x01760000 0 2885 reg = <0 0x01760000 0 0x7080>;
2886 2886
2887 qcom,bcm-voters = <&a 2887 qcom,bcm-voters = <&apps_bcm_voter>;
2888 2888
2889 #interconnect-cells = 2889 #interconnect-cells = <2>;
2890 }; 2890 };
2891 2891
2892 usb_south_anoc: interconnect@ 2892 usb_south_anoc: interconnect@1770000 {
2893 compatible = "qcom,x1 2893 compatible = "qcom,x1e80100-usb-south-anoc";
2894 reg = <0 0x01770000 0 2894 reg = <0 0x01770000 0 0xf080>;
2895 2895
2896 qcom,bcm-voters = <&a 2896 qcom,bcm-voters = <&apps_bcm_voter>;
2897 2897
2898 #interconnect-cells = 2898 #interconnect-cells = <2>;
2899 }; 2899 };
2900 2900
2901 mmss_noc: interconnect@178000 2901 mmss_noc: interconnect@1780000 {
2902 compatible = "qcom,x1 2902 compatible = "qcom,x1e80100-mmss-noc";
2903 reg = <0 0x01780000 0 2903 reg = <0 0x01780000 0 0x5B800>;
2904 2904
2905 qcom,bcm-voters = <&a 2905 qcom,bcm-voters = <&apps_bcm_voter>;
2906 2906
2907 #interconnect-cells = 2907 #interconnect-cells = <2>;
2908 }; 2908 };
2909 2909
2910 pcie6a: pci@1bf8000 { 2910 pcie6a: pci@1bf8000 {
2911 device_type = "pci"; 2911 device_type = "pci";
2912 compatible = "qcom,pc 2912 compatible = "qcom,pcie-x1e80100";
2913 reg = <0 0x01bf8000 0 2913 reg = <0 0x01bf8000 0 0x3000>,
2914 <0 0x70000000 0 2914 <0 0x70000000 0 0xf20>,
2915 <0 0x70000f40 0 2915 <0 0x70000f40 0 0xa8>,
2916 <0 0x70001000 0 2916 <0 0x70001000 0 0x1000>,
2917 <0 0x70100000 0 2917 <0 0x70100000 0 0x100000>,
2918 <0 0x01bfb000 0 2918 <0 0x01bfb000 0 0x1000>;
2919 reg-names = "parf", 2919 reg-names = "parf",
2920 "dbi", 2920 "dbi",
2921 "elbi", 2921 "elbi",
2922 "atu", 2922 "atu",
2923 "config", 2923 "config",
2924 "mhi"; 2924 "mhi";
2925 #address-cells = <3>; 2925 #address-cells = <3>;
2926 #size-cells = <2>; 2926 #size-cells = <2>;
2927 ranges = <0x01000000 2927 ranges = <0x01000000 0x0 0x00000000 0x0 0x70200000 0x0 0x100000>,
2928 <0x02000000 2928 <0x02000000 0x0 0x70300000 0x0 0x70300000 0x0 0x1d00000>;
2929 bus-range = <0x00 0xf 2929 bus-range = <0x00 0xff>;
2930 2930
2931 dma-coherent; 2931 dma-coherent;
2932 2932
2933 linux,pci-domain = <6 2933 linux,pci-domain = <6>;
2934 num-lanes = <4>; 2934 num-lanes = <4>;
2935 2935
2936 interrupts = <GIC_SPI 2936 interrupts = <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,
2937 <GIC_SPI 2937 <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>,
2938 <GIC_SPI 2938 <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>,
2939 <GIC_SPI 2939 <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>,
2940 <GIC_SPI 2940 <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>,
2941 <GIC_SPI 2941 <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>,
2942 <GIC_SPI 2942 <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>,
2943 <GIC_SPI 2943 <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>;
2944 interrupt-names = "ms 2944 interrupt-names = "msi0",
2945 "ms 2945 "msi1",
2946 "ms 2946 "msi2",
2947 "ms 2947 "msi3",
2948 "ms 2948 "msi4",
2949 "ms 2949 "msi5",
2950 "ms 2950 "msi6",
2951 "ms 2951 "msi7";
2952 2952
2953 #interrupt-cells = <1 2953 #interrupt-cells = <1>;
2954 interrupt-map-mask = 2954 interrupt-map-mask = <0 0 0 0x7>;
2955 interrupt-map = <0 0 2955 interrupt-map = <0 0 0 1 &intc 0 0 0 843 IRQ_TYPE_LEVEL_HIGH>,
2956 <0 0 2956 <0 0 0 2 &intc 0 0 0 844 IRQ_TYPE_LEVEL_HIGH>,
2957 <0 0 2957 <0 0 0 3 &intc 0 0 0 845 IRQ_TYPE_LEVEL_HIGH>,
2958 <0 0 2958 <0 0 0 4 &intc 0 0 0 772 IRQ_TYPE_LEVEL_HIGH>;
2959 2959
2960 clocks = <&gcc GCC_PC 2960 clocks = <&gcc GCC_PCIE_6A_AUX_CLK>,
2961 <&gcc GCC_PC 2961 <&gcc GCC_PCIE_6A_CFG_AHB_CLK>,
2962 <&gcc GCC_PC 2962 <&gcc GCC_PCIE_6A_MSTR_AXI_CLK>,
2963 <&gcc GCC_PC 2963 <&gcc GCC_PCIE_6A_SLV_AXI_CLK>,
2964 <&gcc GCC_PC 2964 <&gcc GCC_PCIE_6A_SLV_Q2A_AXI_CLK>,
2965 <&gcc GCC_CF 2965 <&gcc GCC_CFG_NOC_PCIE_ANOC_SOUTH_AHB_CLK>,
2966 <&gcc GCC_CN 2966 <&gcc GCC_CNOC_PCIE_SOUTH_SF_AXI_CLK>;
2967 clock-names = "aux", 2967 clock-names = "aux",
2968 "cfg", 2968 "cfg",
2969 "bus_ma 2969 "bus_master",
2970 "bus_sl 2970 "bus_slave",
2971 "slave_ 2971 "slave_q2a",
2972 "noc_ag 2972 "noc_aggr",
2973 "cnoc_s 2973 "cnoc_sf_axi";
2974 2974
2975 assigned-clocks = <&g 2975 assigned-clocks = <&gcc GCC_PCIE_6A_AUX_CLK>;
2976 assigned-clock-rates 2976 assigned-clock-rates = <19200000>;
2977 2977
2978 interconnects = <&pci 2978 interconnects = <&pcie_south_anoc MASTER_PCIE_6A QCOM_ICC_TAG_ALWAYS
2979 &mc_ 2979 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
2980 <&gem 2980 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2981 &cno 2981 &cnoc_main SLAVE_PCIE_6A QCOM_ICC_TAG_ALWAYS>;
2982 interconnect-names = 2982 interconnect-names = "pcie-mem",
2983 2983 "cpu-pcie";
2984 2984
2985 resets = <&gcc GCC_PC 2985 resets = <&gcc GCC_PCIE_6A_BCR>,
2986 <&gcc GCC_PC 2986 <&gcc GCC_PCIE_6A_LINK_DOWN_BCR>;
2987 reset-names = "pci", 2987 reset-names = "pci",
2988 "link_d 2988 "link_down";
2989 2989
2990 power-domains = <&gcc 2990 power-domains = <&gcc GCC_PCIE_6A_GDSC>;
2991 required-opps = <&rpm 2991 required-opps = <&rpmhpd_opp_nom>;
2992 2992
2993 phys = <&pcie6a_phy>; 2993 phys = <&pcie6a_phy>;
2994 phy-names = "pciephy" 2994 phy-names = "pciephy";
2995 2995
2996 status = "disabled"; 2996 status = "disabled";
2997 }; 2997 };
2998 2998
2999 pcie6a_phy: phy@1bfc000 { 2999 pcie6a_phy: phy@1bfc000 {
3000 compatible = "qcom,x1 3000 compatible = "qcom,x1e80100-qmp-gen4x4-pcie-phy";
3001 reg = <0 0x01bfc000 0 3001 reg = <0 0x01bfc000 0 0x2000>,
3002 <0 0x01bfe000 0 3002 <0 0x01bfe000 0 0x2000>;
3003 3003
3004 clocks = <&gcc GCC_PC 3004 clocks = <&gcc GCC_PCIE_6A_PHY_AUX_CLK>,
3005 <&gcc GCC_PC 3005 <&gcc GCC_PCIE_6A_CFG_AHB_CLK>,
3006 <&tcsr TCSR_ 3006 <&tcsr TCSR_PCIE_4L_CLKREF_EN>,
3007 <&gcc GCC_PC 3007 <&gcc GCC_PCIE_6A_PHY_RCHNG_CLK>,
3008 <&gcc GCC_PC 3008 <&gcc GCC_PCIE_6A_PIPE_CLK>,
3009 <&gcc GCC_PC 3009 <&gcc GCC_PCIE_6A_PIPEDIV2_CLK>;
3010 clock-names = "aux", 3010 clock-names = "aux",
3011 "cfg_ah 3011 "cfg_ahb",
3012 "ref", 3012 "ref",
3013 "rchng" 3013 "rchng",
3014 "pipe", 3014 "pipe",
3015 "pipedi 3015 "pipediv2";
3016 3016
3017 resets = <&gcc GCC_PC 3017 resets = <&gcc GCC_PCIE_6A_PHY_BCR>,
3018 <&gcc GCC_PC 3018 <&gcc GCC_PCIE_6A_NOCSR_COM_PHY_BCR>;
3019 reset-names = "phy", 3019 reset-names = "phy",
3020 "phy_no 3020 "phy_nocsr";
3021 3021
3022 assigned-clocks = <&g 3022 assigned-clocks = <&gcc GCC_PCIE_6A_PHY_RCHNG_CLK>;
3023 assigned-clock-rates 3023 assigned-clock-rates = <100000000>;
3024 3024
3025 power-domains = <&gcc 3025 power-domains = <&gcc GCC_PCIE_6_PHY_GDSC>;
3026 3026
3027 qcom,4ln-config-sel = 3027 qcom,4ln-config-sel = <&tcsr 0x1a000 0>;
3028 3028
3029 #clock-cells = <0>; 3029 #clock-cells = <0>;
3030 clock-output-names = 3030 clock-output-names = "pcie6a_pipe_clk";
3031 3031
3032 #phy-cells = <0>; 3032 #phy-cells = <0>;
3033 3033
3034 status = "disabled"; 3034 status = "disabled";
3035 }; 3035 };
3036 3036
3037 pcie5: pci@1c00000 { 3037 pcie5: pci@1c00000 {
3038 device_type = "pci"; 3038 device_type = "pci";
3039 compatible = "qcom,pc 3039 compatible = "qcom,pcie-x1e80100";
3040 reg = <0 0x01c00000 0 3040 reg = <0 0x01c00000 0 0x3000>,
3041 <0 0x7e000000 0 3041 <0 0x7e000000 0 0xf1d>,
3042 <0 0x7e000f40 0 3042 <0 0x7e000f40 0 0xa8>,
3043 <0 0x7e001000 0 3043 <0 0x7e001000 0 0x1000>,
3044 <0 0x7e100000 0 3044 <0 0x7e100000 0 0x100000>,
3045 <0 0x01c03000 0 3045 <0 0x01c03000 0 0x1000>;
3046 reg-names = "parf", 3046 reg-names = "parf",
3047 "dbi", 3047 "dbi",
3048 "elbi", 3048 "elbi",
3049 "atu", 3049 "atu",
3050 "config", 3050 "config",
3051 "mhi"; 3051 "mhi";
3052 #address-cells = <3>; 3052 #address-cells = <3>;
3053 #size-cells = <2>; 3053 #size-cells = <2>;
3054 ranges = <0x01000000 3054 ranges = <0x01000000 0x0 0x00000000 0x0 0x7e200000 0x0 0x100000>,
3055 <0x02000000 3055 <0x02000000 0x0 0x7e300000 0x0 0x7e300000 0x0 0x1d00000>;
3056 bus-range = <0x00 0xf 3056 bus-range = <0x00 0xff>;
3057 3057
3058 dma-coherent; 3058 dma-coherent;
3059 3059
3060 linux,pci-domain = <5 3060 linux,pci-domain = <5>;
3061 num-lanes = <2>; 3061 num-lanes = <2>;
3062 3062
3063 interrupts = <GIC_SPI 3063 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
3064 <GIC_SPI 3064 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
3065 <GIC_SPI 3065 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
3066 <GIC_SPI 3066 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
3067 <GIC_SPI 3067 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
3068 <GIC_SPI 3068 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
3069 <GIC_SPI 3069 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
3070 <GIC_SPI 3070 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
3071 interrupt-names = "ms 3071 interrupt-names = "msi0",
3072 "ms 3072 "msi1",
3073 "ms 3073 "msi2",
3074 "ms 3074 "msi3",
3075 "ms 3075 "msi4",
3076 "ms 3076 "msi5",
3077 "ms 3077 "msi6",
3078 "ms 3078 "msi7";
3079 3079
3080 #interrupt-cells = <1 3080 #interrupt-cells = <1>;
3081 interrupt-map-mask = 3081 interrupt-map-mask = <0 0 0 0x7>;
3082 interrupt-map = <0 0 3082 interrupt-map = <0 0 0 1 &intc 0 0 0 70 IRQ_TYPE_LEVEL_HIGH>,
3083 <0 0 3083 <0 0 0 2 &intc 0 0 0 71 IRQ_TYPE_LEVEL_HIGH>,
3084 <0 0 3084 <0 0 0 3 &intc 0 0 0 72 IRQ_TYPE_LEVEL_HIGH>,
3085 <0 0 3085 <0 0 0 4 &intc 0 0 0 73 IRQ_TYPE_LEVEL_HIGH>;
3086 3086
3087 clocks = <&gcc GCC_PC 3087 clocks = <&gcc GCC_PCIE_5_AUX_CLK>,
3088 <&gcc GCC_PC 3088 <&gcc GCC_PCIE_5_CFG_AHB_CLK>,
3089 <&gcc GCC_PC 3089 <&gcc GCC_PCIE_5_MSTR_AXI_CLK>,
3090 <&gcc GCC_PC 3090 <&gcc GCC_PCIE_5_SLV_AXI_CLK>,
3091 <&gcc GCC_PC 3091 <&gcc GCC_PCIE_5_SLV_Q2A_AXI_CLK>,
3092 <&gcc GCC_CF 3092 <&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>,
3093 <&gcc GCC_CN 3093 <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>;
3094 clock-names = "aux", 3094 clock-names = "aux",
3095 "cfg", 3095 "cfg",
3096 "bus_ma 3096 "bus_master",
3097 "bus_sl 3097 "bus_slave",
3098 "slave_ 3098 "slave_q2a",
3099 "noc_ag 3099 "noc_aggr",
3100 "cnoc_s 3100 "cnoc_sf_axi";
3101 3101
3102 assigned-clocks = <&g 3102 assigned-clocks = <&gcc GCC_PCIE_5_AUX_CLK>;
3103 assigned-clock-rates 3103 assigned-clock-rates = <19200000>;
3104 3104
3105 interconnects = <&pci 3105 interconnects = <&pcie_north_anoc MASTER_PCIE_5 QCOM_ICC_TAG_ALWAYS
3106 &mc_ 3106 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
3107 <&gem 3107 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
3108 &cno 3108 &cnoc_main SLAVE_PCIE_5 QCOM_ICC_TAG_ALWAYS>;
3109 interconnect-names = 3109 interconnect-names = "pcie-mem",
3110 3110 "cpu-pcie";
3111 3111
3112 resets = <&gcc GCC_PC 3112 resets = <&gcc GCC_PCIE_5_BCR>,
3113 <&gcc GCC_PC 3113 <&gcc GCC_PCIE_5_LINK_DOWN_BCR>;
3114 reset-names = "pci", 3114 reset-names = "pci",
3115 "link_d 3115 "link_down";
3116 3116
3117 power-domains = <&gcc 3117 power-domains = <&gcc GCC_PCIE_5_GDSC>;
3118 required-opps = <&rpm 3118 required-opps = <&rpmhpd_opp_nom>;
3119 3119
3120 phys = <&pcie5_phy>; 3120 phys = <&pcie5_phy>;
3121 phy-names = "pciephy" 3121 phy-names = "pciephy";
3122 3122
3123 status = "disabled"; 3123 status = "disabled";
3124 }; 3124 };
3125 3125
3126 pcie5_phy: phy@1c06000 { 3126 pcie5_phy: phy@1c06000 {
3127 compatible = "qcom,x1 3127 compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy";
3128 reg = <0 0x01c06000 0 3128 reg = <0 0x01c06000 0 0x2000>;
3129 3129
3130 clocks = <&gcc GCC_PC 3130 clocks = <&gcc GCC_PCIE_5_AUX_CLK>,
3131 <&gcc GCC_PC 3131 <&gcc GCC_PCIE_5_CFG_AHB_CLK>,
3132 <&tcsr TCSR_ 3132 <&tcsr TCSR_PCIE_2L_5_CLKREF_EN>,
3133 <&gcc GCC_PC 3133 <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>,
3134 <&gcc GCC_PC 3134 <&gcc GCC_PCIE_5_PIPE_CLK>,
3135 <&gcc GCC_PC 3135 <&gcc GCC_PCIE_5_PIPEDIV2_CLK>;
3136 clock-names = "aux", 3136 clock-names = "aux",
3137 "cfg_ah 3137 "cfg_ahb",
3138 "ref", 3138 "ref",
3139 "rchng" 3139 "rchng",
3140 "pipe", 3140 "pipe",
3141 "pipedi 3141 "pipediv2";
3142 3142
3143 resets = <&gcc GCC_PC 3143 resets = <&gcc GCC_PCIE_5_PHY_BCR>;
3144 reset-names = "phy"; 3144 reset-names = "phy";
3145 3145
3146 assigned-clocks = <&g 3146 assigned-clocks = <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>;
3147 assigned-clock-rates 3147 assigned-clock-rates = <100000000>;
3148 3148
3149 power-domains = <&gcc 3149 power-domains = <&gcc GCC_PCIE_5_PHY_GDSC>;
3150 3150
3151 #clock-cells = <0>; 3151 #clock-cells = <0>;
3152 clock-output-names = 3152 clock-output-names = "pcie5_pipe_clk";
3153 3153
3154 #phy-cells = <0>; 3154 #phy-cells = <0>;
3155 3155
3156 status = "disabled"; 3156 status = "disabled";
3157 }; 3157 };
3158 3158
3159 pcie4: pci@1c08000 { 3159 pcie4: pci@1c08000 {
3160 device_type = "pci"; 3160 device_type = "pci";
3161 compatible = "qcom,pc 3161 compatible = "qcom,pcie-x1e80100";
3162 reg = <0 0x01c08000 0 3162 reg = <0 0x01c08000 0 0x3000>,
3163 <0 0x7c000000 0 3163 <0 0x7c000000 0 0xf1d>,
3164 <0 0x7c000f40 0 3164 <0 0x7c000f40 0 0xa8>,
3165 <0 0x7c001000 0 3165 <0 0x7c001000 0 0x1000>,
3166 <0 0x7c100000 0 3166 <0 0x7c100000 0 0x100000>,
3167 <0 0x01c0b000 0 3167 <0 0x01c0b000 0 0x1000>;
3168 reg-names = "parf", 3168 reg-names = "parf",
3169 "dbi", 3169 "dbi",
3170 "elbi", 3170 "elbi",
3171 "atu", 3171 "atu",
3172 "config", 3172 "config",
3173 "mhi"; 3173 "mhi";
3174 #address-cells = <3>; 3174 #address-cells = <3>;
3175 #size-cells = <2>; 3175 #size-cells = <2>;
3176 ranges = <0x01000000 3176 ranges = <0x01000000 0x0 0x00000000 0x0 0x7c200000 0x0 0x100000>,
3177 <0x02000000 3177 <0x02000000 0x0 0x7c300000 0x0 0x7c300000 0x0 0x1d00000>;
3178 bus-range = <0x00 0xf 3178 bus-range = <0x00 0xff>;
3179 3179
3180 dma-coherent; 3180 dma-coherent;
3181 3181
3182 linux,pci-domain = <4 3182 linux,pci-domain = <4>;
3183 num-lanes = <2>; 3183 num-lanes = <2>;
3184 3184
3185 interrupts = <GIC_SPI 3185 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
3186 <GIC_SPI 3186 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
3187 <GIC_SPI 3187 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
3188 <GIC_SPI 3188 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
3189 <GIC_SPI 3189 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
3190 <GIC_SPI 3190 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
3191 <GIC_SPI 3191 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
3192 <GIC_SPI 3192 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
3193 interrupt-names = "ms 3193 interrupt-names = "msi0",
3194 "ms 3194 "msi1",
3195 "ms 3195 "msi2",
3196 "ms 3196 "msi3",
3197 "ms 3197 "msi4",
3198 "ms 3198 "msi5",
3199 "ms 3199 "msi6",
3200 "ms 3200 "msi7";
3201 3201
3202 #interrupt-cells = <1 3202 #interrupt-cells = <1>;
3203 interrupt-map-mask = 3203 interrupt-map-mask = <0 0 0 0x7>;
3204 interrupt-map = <0 0 3204 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>,
3205 <0 0 3205 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>,
3206 <0 0 3206 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>,
3207 <0 0 3207 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>;
3208 3208
3209 clocks = <&gcc GCC_PC 3209 clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
3210 <&gcc GCC_PC 3210 <&gcc GCC_PCIE_4_CFG_AHB_CLK>,
3211 <&gcc GCC_PC 3211 <&gcc GCC_PCIE_4_MSTR_AXI_CLK>,
3212 <&gcc GCC_PC 3212 <&gcc GCC_PCIE_4_SLV_AXI_CLK>,
3213 <&gcc GCC_PC 3213 <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>,
3214 <&gcc GCC_CF 3214 <&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>,
3215 <&gcc GCC_CN 3215 <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>;
3216 clock-names = "aux", 3216 clock-names = "aux",
3217 "cfg", 3217 "cfg",
3218 "bus_ma 3218 "bus_master",
3219 "bus_sl 3219 "bus_slave",
3220 "slave_ 3220 "slave_q2a",
3221 "noc_ag 3221 "noc_aggr",
3222 "cnoc_s 3222 "cnoc_sf_axi";
3223 3223
3224 assigned-clocks = <&g 3224 assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>;
3225 assigned-clock-rates 3225 assigned-clock-rates = <19200000>;
3226 3226
3227 interconnects = <&pci 3227 interconnects = <&pcie_north_anoc MASTER_PCIE_4 QCOM_ICC_TAG_ALWAYS
3228 &mc_ 3228 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
3229 <&gem 3229 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
3230 &cno 3230 &cnoc_main SLAVE_PCIE_4 QCOM_ICC_TAG_ALWAYS>;
3231 interconnect-names = 3231 interconnect-names = "pcie-mem",
3232 3232 "cpu-pcie";
3233 3233
3234 resets = <&gcc GCC_PC 3234 resets = <&gcc GCC_PCIE_4_BCR>,
3235 <&gcc GCC_PC 3235 <&gcc GCC_PCIE_4_LINK_DOWN_BCR>;
3236 reset-names = "pci", 3236 reset-names = "pci",
3237 "link_d 3237 "link_down";
3238 3238
3239 power-domains = <&gcc 3239 power-domains = <&gcc GCC_PCIE_4_GDSC>;
3240 required-opps = <&rpm 3240 required-opps = <&rpmhpd_opp_nom>;
3241 3241
3242 phys = <&pcie4_phy>; 3242 phys = <&pcie4_phy>;
3243 phy-names = "pciephy" 3243 phy-names = "pciephy";
3244 3244
3245 status = "disabled"; 3245 status = "disabled";
3246 3246
3247 pcie4_port0: pcie@0 { 3247 pcie4_port0: pcie@0 {
3248 device_type = 3248 device_type = "pci";
3249 reg = <0x0 0x 3249 reg = <0x0 0x0 0x0 0x0 0x0>;
3250 bus-range = < 3250 bus-range = <0x01 0xff>;
3251 3251
3252 #address-cell 3252 #address-cells = <3>;
3253 #size-cells = 3253 #size-cells = <2>;
3254 ranges; 3254 ranges;
3255 }; 3255 };
3256 }; 3256 };
3257 3257
3258 pcie4_phy: phy@1c0e000 { 3258 pcie4_phy: phy@1c0e000 {
3259 compatible = "qcom,x1 3259 compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy";
3260 reg = <0 0x01c0e000 0 3260 reg = <0 0x01c0e000 0 0x2000>;
3261 3261
3262 clocks = <&gcc GCC_PC 3262 clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
3263 <&gcc GCC_PC 3263 <&gcc GCC_PCIE_4_CFG_AHB_CLK>,
3264 <&tcsr TCSR_ 3264 <&tcsr TCSR_PCIE_2L_4_CLKREF_EN>,
3265 <&gcc GCC_PC 3265 <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>,
3266 <&gcc GCC_PC 3266 <&gcc GCC_PCIE_4_PIPE_CLK>,
3267 <&gcc GCC_PC 3267 <&gcc GCC_PCIE_4_PIPEDIV2_CLK>;
3268 clock-names = "aux", 3268 clock-names = "aux",
3269 "cfg_ah 3269 "cfg_ahb",
3270 "ref", 3270 "ref",
3271 "rchng" 3271 "rchng",
3272 "pipe", 3272 "pipe",
3273 "pipedi 3273 "pipediv2";
3274 3274
3275 resets = <&gcc GCC_PC 3275 resets = <&gcc GCC_PCIE_4_PHY_BCR>;
3276 reset-names = "phy"; 3276 reset-names = "phy";
3277 3277
3278 assigned-clocks = <&g 3278 assigned-clocks = <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>;
3279 assigned-clock-rates 3279 assigned-clock-rates = <100000000>;
3280 3280
3281 power-domains = <&gcc 3281 power-domains = <&gcc GCC_PCIE_4_PHY_GDSC>;
3282 3282
3283 #clock-cells = <0>; 3283 #clock-cells = <0>;
3284 clock-output-names = 3284 clock-output-names = "pcie4_pipe_clk";
3285 3285
3286 #phy-cells = <0>; 3286 #phy-cells = <0>;
3287 3287
3288 status = "disabled"; 3288 status = "disabled";
3289 }; 3289 };
3290 3290
3291 tcsr_mutex: hwlock@1f40000 { 3291 tcsr_mutex: hwlock@1f40000 {
3292 compatible = "qcom,tc 3292 compatible = "qcom,tcsr-mutex";
3293 reg = <0 0x01f40000 0 3293 reg = <0 0x01f40000 0 0x20000>;
3294 #hwlock-cells = <1>; 3294 #hwlock-cells = <1>;
3295 }; 3295 };
3296 3296
3297 tcsr: clock-controller@1fc000 3297 tcsr: clock-controller@1fc0000 {
3298 compatible = "qcom,x1 3298 compatible = "qcom,x1e80100-tcsr", "syscon";
3299 reg = <0 0x01fc0000 0 3299 reg = <0 0x01fc0000 0 0x30000>;
3300 clocks = <&rpmhcc RPM 3300 clocks = <&rpmhcc RPMH_CXO_CLK>;
3301 #clock-cells = <1>; 3301 #clock-cells = <1>;
3302 #reset-cells = <1>; 3302 #reset-cells = <1>;
3303 }; 3303 };
3304 3304
3305 gpu: gpu@3d00000 { 3305 gpu: gpu@3d00000 {
3306 compatible = "qcom,ad 3306 compatible = "qcom,adreno-43050c01", "qcom,adreno";
3307 reg = <0x0 0x03d00000 3307 reg = <0x0 0x03d00000 0x0 0x40000>,
3308 <0x0 0x03d9e000 3308 <0x0 0x03d9e000 0x0 0x1000>,
3309 <0x0 0x03d61000 3309 <0x0 0x03d61000 0x0 0x800>;
3310 3310
3311 reg-names = "kgsl_3d0 3311 reg-names = "kgsl_3d0_reg_memory",
3312 "cx_mem", 3312 "cx_mem",
3313 "cx_dbgc" 3313 "cx_dbgc";
3314 3314
3315 interrupts = <GIC_SPI 3315 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
3316 3316
3317 iommus = <&adreno_smm 3317 iommus = <&adreno_smmu 0 0x0>,
3318 <&adreno_smm 3318 <&adreno_smmu 1 0x0>;
3319 3319
3320 operating-points-v2 = 3320 operating-points-v2 = <&gpu_opp_table>;
3321 3321
3322 qcom,gmu = <&gmu>; 3322 qcom,gmu = <&gmu>;
3323 #cooling-cells = <2>; 3323 #cooling-cells = <2>;
3324 3324
3325 interconnects = <&gem 3325 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
3326 interconnect-names = 3326 interconnect-names = "gfx-mem";
3327 3327
3328 status = "disabled"; 3328 status = "disabled";
3329 3329
3330 zap-shader { 3330 zap-shader {
3331 memory-region 3331 memory-region = <&gpu_microcode_mem>;
3332 }; 3332 };
3333 3333
3334 gpu_opp_table: opp-ta 3334 gpu_opp_table: opp-table {
3335 compatible = 3335 compatible = "operating-points-v2";
3336 3336
3337 opp-110000000 3337 opp-1100000000 {
3338 opp-h 3338 opp-hz = /bits/ 64 <1100000000>;
3339 opp-l 3339 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3340 opp-p 3340 opp-peak-kBps = <16500000>;
3341 }; 3341 };
3342 3342
3343 opp-100000000 3343 opp-1000000000 {
3344 opp-h 3344 opp-hz = /bits/ 64 <1000000000>;
3345 opp-l 3345 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3346 opp-p 3346 opp-peak-kBps = <14398438>;
3347 }; 3347 };
3348 3348
3349 opp-925000000 3349 opp-925000000 {
3350 opp-h 3350 opp-hz = /bits/ 64 <925000000>;
3351 opp-l 3351 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3352 opp-p 3352 opp-peak-kBps = <14398438>;
3353 }; 3353 };
3354 3354
3355 opp-800000000 3355 opp-800000000 {
3356 opp-h 3356 opp-hz = /bits/ 64 <800000000>;
3357 opp-l 3357 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3358 opp-p 3358 opp-peak-kBps = <12449219>;
3359 }; 3359 };
3360 3360
3361 opp-744000000 3361 opp-744000000 {
3362 opp-h 3362 opp-hz = /bits/ 64 <744000000>;
3363 opp-l 3363 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
3364 opp-p 3364 opp-peak-kBps = <10687500>;
3365 }; 3365 };
3366 3366
3367 opp-687000000 3367 opp-687000000 {
3368 opp-h 3368 opp-hz = /bits/ 64 <687000000>;
3369 opp-l 3369 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3370 opp-p 3370 opp-peak-kBps = <8171875>;
3371 }; 3371 };
3372 3372
3373 opp-550000000 3373 opp-550000000 {
3374 opp-h 3374 opp-hz = /bits/ 64 <550000000>;
3375 opp-l 3375 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3376 opp-p 3376 opp-peak-kBps = <6074219>;
3377 }; 3377 };
3378 3378
3379 opp-390000000 3379 opp-390000000 {
3380 opp-h 3380 opp-hz = /bits/ 64 <390000000>;
3381 opp-l 3381 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3382 opp-p 3382 opp-peak-kBps = <3000000>;
3383 }; 3383 };
3384 3384
3385 opp-300000000 3385 opp-300000000 {
3386 opp-h 3386 opp-hz = /bits/ 64 <300000000>;
3387 opp-l 3387 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
3388 opp-p 3388 opp-peak-kBps = <2136719>;
3389 }; 3389 };
3390 }; 3390 };
3391 }; 3391 };
3392 3392
3393 gmu: gmu@3d6a000 { 3393 gmu: gmu@3d6a000 {
3394 compatible = "qcom,ad 3394 compatible = "qcom,adreno-gmu-x185.1", "qcom,adreno-gmu";
3395 reg = <0x0 0x03d6a000 3395 reg = <0x0 0x03d6a000 0x0 0x35000>,
3396 <0x0 0x03d50000 3396 <0x0 0x03d50000 0x0 0x10000>,
3397 <0x0 0x0b280000 3397 <0x0 0x0b280000 0x0 0x10000>;
3398 reg-names = "gmu", " 3398 reg-names = "gmu", "rscc", "gmu_pdc";
3399 3399
3400 interrupts = <GIC_SPI 3400 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
3401 <GIC_SPI 3401 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
3402 interrupt-names = "hf 3402 interrupt-names = "hfi", "gmu";
3403 3403
3404 clocks = <&gpucc GPU_ 3404 clocks = <&gpucc GPU_CC_AHB_CLK>,
3405 <&gpucc GPU_ 3405 <&gpucc GPU_CC_CX_GMU_CLK>,
3406 <&gpucc GPU_ 3406 <&gpucc GPU_CC_CXO_CLK>,
3407 <&gcc GCC_DD 3407 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
3408 <&gcc GCC_GP 3408 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
3409 <&gpucc GPU_ 3409 <&gpucc GPU_CC_HUB_CX_INT_CLK>,
3410 <&gpucc GPU_ 3410 <&gpucc GPU_CC_DEMET_CLK>;
3411 clock-names = "ahb", 3411 clock-names = "ahb",
3412 "gmu", 3412 "gmu",
3413 "cxo", 3413 "cxo",
3414 "axi", 3414 "axi",
3415 "memnoc 3415 "memnoc",
3416 "hub", 3416 "hub",
3417 "demet" 3417 "demet";
3418 3418
3419 power-domains = <&gpu 3419 power-domains = <&gpucc GPU_CX_GDSC>,
3420 <&gpu 3420 <&gpucc GPU_GX_GDSC>;
3421 power-domain-names = 3421 power-domain-names = "cx",
3422 3422 "gx";
3423 3423
3424 iommus = <&adreno_smm 3424 iommus = <&adreno_smmu 5 0x0>;
3425 3425
3426 qcom,qmp = <&aoss_qmp 3426 qcom,qmp = <&aoss_qmp>;
3427 3427
3428 operating-points-v2 = 3428 operating-points-v2 = <&gmu_opp_table>;
3429 3429
3430 gmu_opp_table: opp-ta 3430 gmu_opp_table: opp-table {
3431 compatible = 3431 compatible = "operating-points-v2";
3432 3432
3433 opp-550000000 3433 opp-550000000 {
3434 opp-h 3434 opp-hz = /bits/ 64 <550000000>;
3435 opp-l 3435 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3436 }; 3436 };
3437 3437
3438 opp-220000000 3438 opp-220000000 {
3439 opp-h 3439 opp-hz = /bits/ 64 <220000000>;
3440 opp-l 3440 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3441 }; 3441 };
3442 }; 3442 };
3443 }; 3443 };
3444 3444
3445 gpucc: clock-controller@3d900 3445 gpucc: clock-controller@3d90000 {
3446 compatible = "qcom,x1 3446 compatible = "qcom,x1e80100-gpucc";
3447 reg = <0 0x03d90000 0 3447 reg = <0 0x03d90000 0 0xa000>;
3448 clocks = <&bi_tcxo_di 3448 clocks = <&bi_tcxo_div2>,
3449 <&gcc GCC_GP 3449 <&gcc GCC_GPU_GPLL0_CPH_CLK_SRC>,
3450 <&gcc GCC_GP 3450 <&gcc GCC_GPU_GPLL0_DIV_CPH_CLK_SRC>;
3451 #clock-cells = <1>; 3451 #clock-cells = <1>;
3452 #reset-cells = <1>; 3452 #reset-cells = <1>;
3453 #power-domain-cells = 3453 #power-domain-cells = <1>;
3454 }; 3454 };
3455 3455
3456 adreno_smmu: iommu@3da0000 { 3456 adreno_smmu: iommu@3da0000 {
3457 compatible = "qcom,x1 3457 compatible = "qcom,x1e80100-smmu-500", "qcom,adreno-smmu",
3458 "qcom,sm 3458 "qcom,smmu-500", "arm,mmu-500";
3459 reg = <0x0 0x03da0000 3459 reg = <0x0 0x03da0000 0x0 0x40000>;
3460 #iommu-cells = <2>; 3460 #iommu-cells = <2>;
3461 #global-interrupts = 3461 #global-interrupts = <1>;
3462 interrupts = <GIC_SPI 3462 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
3463 <GIC_SPI 3463 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
3464 <GIC_SPI 3464 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
3465 <GIC_SPI 3465 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
3466 <GIC_SPI 3466 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
3467 <GIC_SPI 3467 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
3468 <GIC_SPI 3468 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
3469 <GIC_SPI 3469 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
3470 <GIC_SPI 3470 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
3471 <GIC_SPI 3471 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
3472 <GIC_SPI 3472 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
3473 <GIC_SPI 3473 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>,
3474 <GIC_SPI 3474 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
3475 <GIC_SPI 3475 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
3476 <GIC_SPI 3476 <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>,
3477 <GIC_SPI 3477 <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>,
3478 <GIC_SPI 3478 <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
3479 <GIC_SPI 3479 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>,
3480 <GIC_SPI 3480 <GIC_SPI 660 IRQ_TYPE_LEVEL_HIGH>,
3481 <GIC_SPI 3481 <GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH>,
3482 <GIC_SPI 3482 <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>,
3483 <GIC_SPI 3483 <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>,
3484 <GIC_SPI 3484 <GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH>,
3485 <GIC_SPI 3485 <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>,
3486 <GIC_SPI 3486 <GIC_SPI 670 IRQ_TYPE_LEVEL_HIGH>,
3487 <GIC_SPI 3487 <GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH>;
3488 clocks = <&gpucc GPU_ 3488 clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
3489 <&gcc GCC_GP 3489 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
3490 <&gcc GCC_GP 3490 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
3491 <&gpucc GPU_ 3491 <&gpucc GPU_CC_AHB_CLK>;
3492 clock-names = "hlos", 3492 clock-names = "hlos",
3493 "bus", 3493 "bus",
3494 "iface" 3494 "iface",
3495 "ahb"; 3495 "ahb";
3496 power-domains = <&gpu 3496 power-domains = <&gpucc GPU_CX_GDSC>;
3497 dma-coherent; 3497 dma-coherent;
3498 }; 3498 };
3499 3499
3500 gem_noc: interconnect@2640000 3500 gem_noc: interconnect@26400000 {
3501 compatible = "qcom,x1 3501 compatible = "qcom,x1e80100-gem-noc";
3502 reg = <0 0x26400000 0 3502 reg = <0 0x26400000 0 0x311200>;
3503 3503
3504 qcom,bcm-voters = <&a 3504 qcom,bcm-voters = <&apps_bcm_voter>;
3505 3505
3506 #interconnect-cells = 3506 #interconnect-cells = <2>;
3507 }; 3507 };
3508 3508
3509 nsp_noc: interconnect@320c000 3509 nsp_noc: interconnect@320c0000 {
3510 compatible = "qcom,x1 3510 compatible = "qcom,x1e80100-nsp-noc";
3511 reg = <0 0x320C0000 0 3511 reg = <0 0x320C0000 0 0xe080>;
3512 3512
3513 qcom,bcm-voters = <&a 3513 qcom,bcm-voters = <&apps_bcm_voter>;
3514 3514
3515 #interconnect-cells = 3515 #interconnect-cells = <2>;
3516 }; 3516 };
3517 3517
3518 lpass_wsa2macro: codec@6aa000 3518 lpass_wsa2macro: codec@6aa0000 {
3519 compatible = "qcom,x1 3519 compatible = "qcom,x1e80100-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro";
3520 reg = <0 0x06aa0000 0 3520 reg = <0 0x06aa0000 0 0x1000>;
3521 clocks = <&q6prmcc LP 3521 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3522 <&q6prmcc LP 3522 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3523 <&q6prmcc LP 3523 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3524 <&lpass_vama 3524 <&lpass_vamacro>;
3525 clock-names = "mclk", 3525 clock-names = "mclk",
3526 "macro" 3526 "macro",
3527 "dcodec 3527 "dcodec",
3528 "fsgen" 3528 "fsgen";
3529 3529
3530 #clock-cells = <0>; 3530 #clock-cells = <0>;
3531 clock-output-names = 3531 clock-output-names = "wsa2-mclk";
3532 #sound-dai-cells = <1 3532 #sound-dai-cells = <1>;
3533 sound-name-prefix = " 3533 sound-name-prefix = "WSA2";
3534 }; 3534 };
3535 3535
3536 swr3: soundwire@6ab0000 { 3536 swr3: soundwire@6ab0000 {
3537 compatible = "qcom,so 3537 compatible = "qcom,soundwire-v2.0.0";
3538 reg = <0 0x06ab0000 0 3538 reg = <0 0x06ab0000 0 0x10000>;
3539 clocks = <&lpass_wsa2 3539 clocks = <&lpass_wsa2macro>;
3540 clock-names = "iface" 3540 clock-names = "iface";
3541 interrupts = <GIC_SPI 3541 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
3542 label = "WSA2"; 3542 label = "WSA2";
3543 3543
3544 pinctrl-0 = <&wsa2_sw 3544 pinctrl-0 = <&wsa2_swr_active>;
3545 pinctrl-names = "defa 3545 pinctrl-names = "default";
3546 resets = <&lpass_audi 3546 resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA2_CGCR>;
3547 reset-names = "swr_au 3547 reset-names = "swr_audio_cgcr";
3548 3548
3549 qcom,din-ports = <4>; 3549 qcom,din-ports = <4>;
3550 qcom,dout-ports = <9> 3550 qcom,dout-ports = <9>;
3551 3551
3552 qcom,ports-sinterval 3552 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0x0f 0x0f 0xff 0x31f>;
3553 qcom,ports-offset1 = 3553 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
3554 qcom,ports-offset2 = 3554 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3555 qcom,ports-hstart = 3555 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
3556 qcom,ports-hstop = 3556 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
3557 qcom,ports-word-lengt 3557 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>;
3558 qcom,ports-block-pack 3558 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>;
3559 qcom,ports-block-grou 3559 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3560 qcom,ports-lane-contr 3560 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3561 3561
3562 #address-cells = <2>; 3562 #address-cells = <2>;
3563 #size-cells = <0>; 3563 #size-cells = <0>;
3564 #sound-dai-cells = <1 3564 #sound-dai-cells = <1>;
3565 status = "disabled"; 3565 status = "disabled";
3566 }; 3566 };
3567 3567
3568 lpass_rxmacro: codec@6ac0000 3568 lpass_rxmacro: codec@6ac0000 {
3569 compatible = "qcom,x1 3569 compatible = "qcom,x1e80100-lpass-rx-macro", "qcom,sm8550-lpass-rx-macro";
3570 reg = <0 0x06ac0000 0 3570 reg = <0 0x06ac0000 0 0x1000>;
3571 clocks = <&q6prmcc LP 3571 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3572 <&q6prmcc LP 3572 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3573 <&q6prmcc LP 3573 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3574 <&lpass_vama 3574 <&lpass_vamacro>;
3575 clock-names = "mclk", 3575 clock-names = "mclk",
3576 "macro" 3576 "macro",
3577 "dcodec 3577 "dcodec",
3578 "fsgen" 3578 "fsgen";
3579 3579
3580 #clock-cells = <0>; 3580 #clock-cells = <0>;
3581 clock-output-names = 3581 clock-output-names = "mclk";
3582 #sound-dai-cells = <1 3582 #sound-dai-cells = <1>;
3583 }; 3583 };
3584 3584
3585 swr1: soundwire@6ad0000 { 3585 swr1: soundwire@6ad0000 {
3586 compatible = "qcom,so 3586 compatible = "qcom,soundwire-v2.0.0";
3587 reg = <0 0x06ad0000 0 3587 reg = <0 0x06ad0000 0 0x10000>;
3588 clocks = <&lpass_rxma 3588 clocks = <&lpass_rxmacro>;
3589 clock-names = "iface" 3589 clock-names = "iface";
3590 interrupts = <GIC_SPI 3590 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
3591 label = "RX"; 3591 label = "RX";
3592 3592
3593 pinctrl-0 = <&rx_swr_ 3593 pinctrl-0 = <&rx_swr_active>;
3594 pinctrl-names = "defa 3594 pinctrl-names = "default";
3595 3595
3596 resets = <&lpass_audi 3596 resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>;
3597 reset-names = "swr_au 3597 reset-names = "swr_audio_cgcr";
3598 qcom,din-ports = <1>; 3598 qcom,din-ports = <1>;
3599 qcom,dout-ports = <11 3599 qcom,dout-ports = <11>;
3600 3600
3601 qcom,ports-sinterval 3601 qcom,ports-sinterval = /bits/ 16 <0x03 0x1f 0x1f 0x07 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3602 qcom,ports-offset1 = 3602 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3603 qcom,ports-offset2 = 3603 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3604 qcom,ports-hstart = 3604 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3605 qcom,ports-hstop = 3605 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3606 qcom,ports-word-lengt 3606 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3607 qcom,ports-block-pack 3607 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3608 qcom,ports-block-grou 3608 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3609 qcom,ports-lane-contr 3609 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3610 3610
3611 #address-cells = <2>; 3611 #address-cells = <2>;
3612 #size-cells = <0>; 3612 #size-cells = <0>;
3613 #sound-dai-cells = <1 3613 #sound-dai-cells = <1>;
3614 status = "disabled"; 3614 status = "disabled";
3615 }; 3615 };
3616 3616
3617 lpass_txmacro: codec@6ae0000 3617 lpass_txmacro: codec@6ae0000 {
3618 compatible = "qcom,x1 3618 compatible = "qcom,x1e80100-lpass-tx-macro", "qcom,sm8550-lpass-tx-macro";
3619 reg = <0 0x06ae0000 0 3619 reg = <0 0x06ae0000 0 0x1000>;
3620 clocks = <&q6prmcc LP 3620 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3621 <&q6prmcc LP 3621 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3622 <&q6prmcc LP 3622 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3623 <&lpass_vama 3623 <&lpass_vamacro>;
3624 clock-names = "mclk", 3624 clock-names = "mclk",
3625 "macro" 3625 "macro",
3626 "dcodec 3626 "dcodec",
3627 "fsgen" 3627 "fsgen";
3628 3628
3629 #clock-cells = <0>; 3629 #clock-cells = <0>;
3630 clock-output-names = 3630 clock-output-names = "mclk";
3631 #sound-dai-cells = <1 3631 #sound-dai-cells = <1>;
3632 }; 3632 };
3633 3633
3634 lpass_wsamacro: codec@6b00000 3634 lpass_wsamacro: codec@6b00000 {
3635 compatible = "qcom,x1 3635 compatible = "qcom,x1e80100-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro";
3636 reg = <0 0x06b00000 0 3636 reg = <0 0x06b00000 0 0x1000>;
3637 clocks = <&q6prmcc LP 3637 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3638 <&q6prmcc LP 3638 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3639 <&q6prmcc LP 3639 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3640 <&lpass_vama 3640 <&lpass_vamacro>;
3641 clock-names = "mclk", 3641 clock-names = "mclk",
3642 "macro" 3642 "macro",
3643 "dcodec 3643 "dcodec",
3644 "fsgen" 3644 "fsgen";
3645 3645
3646 #clock-cells = <0>; 3646 #clock-cells = <0>;
3647 clock-output-names = 3647 clock-output-names = "mclk";
3648 #sound-dai-cells = <1 3648 #sound-dai-cells = <1>;
3649 sound-name-prefix = " 3649 sound-name-prefix = "WSA";
3650 }; 3650 };
3651 3651
3652 swr0: soundwire@6b10000 { 3652 swr0: soundwire@6b10000 {
3653 compatible = "qcom,so 3653 compatible = "qcom,soundwire-v2.0.0";
3654 reg = <0 0x06b10000 0 3654 reg = <0 0x06b10000 0 0x10000>;
3655 clocks = <&lpass_wsam 3655 clocks = <&lpass_wsamacro>;
3656 clock-names = "iface" 3656 clock-names = "iface";
3657 interrupts = <GIC_SPI 3657 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
3658 label = "WSA"; 3658 label = "WSA";
3659 3659
3660 pinctrl-0 = <&wsa_swr 3660 pinctrl-0 = <&wsa_swr_active>;
3661 pinctrl-names = "defa 3661 pinctrl-names = "default";
3662 resets = <&lpass_audi 3662 resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA_CGCR>;
3663 reset-names = "swr_au 3663 reset-names = "swr_audio_cgcr";
3664 3664
3665 qcom,din-ports = <4>; 3665 qcom,din-ports = <4>;
3666 qcom,dout-ports = <9> 3666 qcom,dout-ports = <9>;
3667 3667
3668 qcom,ports-sinterval 3668 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0x0f 0x0f 0xff 0x31f>;
3669 qcom,ports-offset1 = 3669 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
3670 qcom,ports-offset2 = 3670 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3671 qcom,ports-hstart = 3671 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
3672 qcom,ports-hstop = 3672 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
3673 qcom,ports-word-lengt 3673 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>;
3674 qcom,ports-block-pack 3674 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>;
3675 qcom,ports-block-grou 3675 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3676 qcom,ports-lane-contr 3676 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3677 3677
3678 #address-cells = <2>; 3678 #address-cells = <2>;
3679 #size-cells = <0>; 3679 #size-cells = <0>;
3680 #sound-dai-cells = <1 3680 #sound-dai-cells = <1>;
3681 status = "disabled"; 3681 status = "disabled";
3682 }; 3682 };
3683 3683
3684 lpass_audiocc: clock-controll 3684 lpass_audiocc: clock-controller@6b6c000 {
3685 compatible = "qcom,x1 3685 compatible = "qcom,x1e80100-lpassaudiocc", "qcom,sc8280xp-lpassaudiocc";
3686 reg = <0 0x06b6c000 0 3686 reg = <0 0x06b6c000 0 0x1000>;
3687 #clock-cells = <1>; 3687 #clock-cells = <1>;
3688 #reset-cells = <1>; 3688 #reset-cells = <1>;
3689 }; 3689 };
3690 3690
3691 swr2: soundwire@6d30000 { 3691 swr2: soundwire@6d30000 {
3692 compatible = "qcom,so 3692 compatible = "qcom,soundwire-v2.0.0";
3693 reg = <0 0x06d30000 0 3693 reg = <0 0x06d30000 0 0x10000>;
3694 clocks = <&lpass_txma 3694 clocks = <&lpass_txmacro>;
3695 clock-names = "iface" 3695 clock-names = "iface";
3696 interrupts = <GIC_SPI 3696 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
3697 <GIC_SPI 3697 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>;
3698 interrupt-names = "co 3698 interrupt-names = "core", "wakeup";
3699 label = "TX"; 3699 label = "TX";
3700 resets = <&lpasscc LP 3700 resets = <&lpasscc LPASS_AUDIO_SWR_TX_CGCR>;
3701 reset-names = "swr_au 3701 reset-names = "swr_audio_cgcr";
3702 3702
3703 pinctrl-0 = <&tx_swr_ 3703 pinctrl-0 = <&tx_swr_active>;
3704 pinctrl-names = "defa 3704 pinctrl-names = "default";
3705 3705
3706 qcom,din-ports = <4>; 3706 qcom,din-ports = <4>;
3707 qcom,dout-ports = <1> 3707 qcom,dout-ports = <1>;
3708 3708
3709 qcom,ports-sinterval- 3709 qcom,ports-sinterval-low = /bits/ 8 <0x00 0x01 0x03 0x03 0x00>;
3710 qcom,ports-offset1 = 3710 qcom,ports-offset1 = /bits/ 8 <0x00 0x01 0x02 0x00 0x00>;
3711 qcom,ports-offset2 = 3711 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00 0xff>;
3712 qcom,ports-hstart = 3712 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
3713 qcom,ports-hstop = 3713 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
3714 qcom,ports-word-lengt 3714 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
3715 qcom,ports-block-pack 3715 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
3716 qcom,ports-block-grou 3716 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
3717 qcom,ports-lane-contr 3717 qcom,ports-lane-control = /bits/ 8 <0xff 0x00 0x00 0x01 0xff>;
3718 3718
3719 #address-cells = <2>; 3719 #address-cells = <2>;
3720 #size-cells = <0>; 3720 #size-cells = <0>;
3721 #sound-dai-cells = <1 3721 #sound-dai-cells = <1>;
3722 status = "disabled"; 3722 status = "disabled";
3723 }; 3723 };
3724 3724
3725 lpass_vamacro: codec@6d44000 3725 lpass_vamacro: codec@6d44000 {
3726 compatible = "qcom,x1 3726 compatible = "qcom,x1e80100-lpass-va-macro", "qcom,sm8550-lpass-va-macro";
3727 reg = <0 0x06d44000 0 3727 reg = <0 0x06d44000 0 0x1000>;
3728 clocks = <&q6prmcc LP 3728 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3729 <&q6prmcc LP 3729 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3730 <&q6prmcc LP 3730 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
3731 clock-names = "mclk", 3731 clock-names = "mclk",
3732 "macro" 3732 "macro",
3733 "dcodec 3733 "dcodec";
3734 3734
3735 #clock-cells = <0>; 3735 #clock-cells = <0>;
3736 clock-output-names = 3736 clock-output-names = "fsgen";
3737 #sound-dai-cells = <1 3737 #sound-dai-cells = <1>;
3738 }; 3738 };
3739 3739
3740 lpass_tlmm: pinctrl@6e80000 { 3740 lpass_tlmm: pinctrl@6e80000 {
3741 compatible = "qcom,x1 3741 compatible = "qcom,x1e80100-lpass-lpi-pinctrl", "qcom,sm8550-lpass-lpi-pinctrl";
3742 reg = <0 0x06e80000 0 3742 reg = <0 0x06e80000 0 0x20000>,
3743 <0 0x07250000 0 3743 <0 0x07250000 0 0x10000>;
3744 3744
3745 clocks = <&q6prmcc LP 3745 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3746 <&q6prmcc LP 3746 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
3747 clock-names = "core", 3747 clock-names = "core", "audio";
3748 3748
3749 gpio-controller; 3749 gpio-controller;
3750 #gpio-cells = <2>; 3750 #gpio-cells = <2>;
3751 gpio-ranges = <&lpass 3751 gpio-ranges = <&lpass_tlmm 0 0 23>;
3752 3752
3753 tx_swr_active: tx-swr 3753 tx_swr_active: tx-swr-active-state {
3754 clk-pins { 3754 clk-pins {
3755 pins 3755 pins = "gpio0";
3756 funct 3756 function = "swr_tx_clk";
3757 drive 3757 drive-strength = <2>;
3758 slew- 3758 slew-rate = <1>;
3759 bias- 3759 bias-disable;
3760 }; 3760 };
3761 3761
3762 data-pins { 3762 data-pins {
3763 pins 3763 pins = "gpio1", "gpio2";
3764 funct 3764 function = "swr_tx_data";
3765 drive 3765 drive-strength = <2>;
3766 slew- 3766 slew-rate = <1>;
3767 bias- 3767 bias-bus-hold;
3768 }; 3768 };
3769 }; 3769 };
3770 3770
3771 rx_swr_active: rx-swr 3771 rx_swr_active: rx-swr-active-state {
3772 clk-pins { 3772 clk-pins {
3773 pins 3773 pins = "gpio3";
3774 funct 3774 function = "swr_rx_clk";
3775 drive 3775 drive-strength = <2>;
3776 slew- 3776 slew-rate = <1>;
3777 bias- 3777 bias-disable;
3778 }; 3778 };
3779 3779
3780 data-pins { 3780 data-pins {
3781 pins 3781 pins = "gpio4", "gpio5";
3782 funct 3782 function = "swr_rx_data";
3783 drive 3783 drive-strength = <2>;
3784 slew- 3784 slew-rate = <1>;
3785 bias- 3785 bias-bus-hold;
3786 }; 3786 };
3787 }; 3787 };
3788 3788
3789 dmic01_default: dmic0 3789 dmic01_default: dmic01-default-state {
3790 clk-pins { 3790 clk-pins {
3791 pins 3791 pins = "gpio6";
3792 funct 3792 function = "dmic1_clk";
3793 drive 3793 drive-strength = <8>;
3794 outpu 3794 output-high;
3795 }; 3795 };
3796 3796
3797 data-pins { 3797 data-pins {
3798 pins 3798 pins = "gpio7";
3799 funct 3799 function = "dmic1_data";
3800 drive 3800 drive-strength = <8>;
3801 input 3801 input-enable;
3802 }; 3802 };
3803 }; 3803 };
3804 3804
3805 dmic23_default: dmic2 3805 dmic23_default: dmic23-default-state {
3806 clk-pins { 3806 clk-pins {
3807 pins 3807 pins = "gpio8";
3808 funct 3808 function = "dmic2_clk";
3809 drive 3809 drive-strength = <8>;
3810 outpu 3810 output-high;
3811 }; 3811 };
3812 3812
3813 data-pins { 3813 data-pins {
3814 pins 3814 pins = "gpio9";
3815 funct 3815 function = "dmic2_data";
3816 drive 3816 drive-strength = <8>;
3817 input 3817 input-enable;
3818 }; 3818 };
3819 }; 3819 };
3820 3820
3821 wsa_swr_active: wsa-s 3821 wsa_swr_active: wsa-swr-active-state {
3822 clk-pins { 3822 clk-pins {
3823 pins 3823 pins = "gpio10";
3824 funct 3824 function = "wsa_swr_clk";
3825 drive 3825 drive-strength = <2>;
3826 slew- 3826 slew-rate = <1>;
3827 bias- 3827 bias-disable;
3828 }; 3828 };
3829 3829
3830 data-pins { 3830 data-pins {
3831 pins 3831 pins = "gpio11";
3832 funct 3832 function = "wsa_swr_data";
3833 drive 3833 drive-strength = <2>;
3834 slew- 3834 slew-rate = <1>;
3835 bias- 3835 bias-bus-hold;
3836 }; 3836 };
3837 }; 3837 };
3838 3838
3839 wsa2_swr_active: wsa2 3839 wsa2_swr_active: wsa2-swr-active-state {
3840 clk-pins { 3840 clk-pins {
3841 pins 3841 pins = "gpio15";
3842 funct 3842 function = "wsa2_swr_clk";
3843 drive 3843 drive-strength = <2>;
3844 slew- 3844 slew-rate = <1>;
3845 bias- 3845 bias-disable;
3846 }; 3846 };
3847 3847
3848 data-pins { 3848 data-pins {
3849 pins 3849 pins = "gpio16";
3850 funct 3850 function = "wsa2_swr_data";
3851 drive 3851 drive-strength = <2>;
3852 slew- 3852 slew-rate = <1>;
3853 bias- 3853 bias-bus-hold;
3854 }; 3854 };
3855 }; 3855 };
3856 }; 3856 };
3857 3857
3858 lpasscc: clock-controller@6ea 3858 lpasscc: clock-controller@6ea0000 {
3859 compatible = "qcom,x1 3859 compatible = "qcom,x1e80100-lpasscc", "qcom,sc8280xp-lpasscc";
3860 reg = <0 0x06ea0000 0 3860 reg = <0 0x06ea0000 0 0x12000>;
3861 #clock-cells = <1>; 3861 #clock-cells = <1>;
3862 #reset-cells = <1>; 3862 #reset-cells = <1>;
3863 }; 3863 };
3864 3864
3865 lpass_ag_noc: interconnect@7e 3865 lpass_ag_noc: interconnect@7e40000 {
3866 compatible = "qcom,x1 3866 compatible = "qcom,x1e80100-lpass-ag-noc";
3867 reg = <0 0x07e40000 0 3867 reg = <0 0x07e40000 0 0xe080>;
3868 3868
3869 qcom,bcm-voters = <&a 3869 qcom,bcm-voters = <&apps_bcm_voter>;
3870 3870
3871 #interconnect-cells = 3871 #interconnect-cells = <2>;
3872 }; 3872 };
3873 3873
3874 lpass_lpiaon_noc: interconnec 3874 lpass_lpiaon_noc: interconnect@7400000 {
3875 compatible = "qcom,x1 3875 compatible = "qcom,x1e80100-lpass-lpiaon-noc";
3876 reg = <0 0x07400000 0 3876 reg = <0 0x07400000 0 0x19080>;
3877 3877
3878 qcom,bcm-voters = <&a 3878 qcom,bcm-voters = <&apps_bcm_voter>;
3879 3879
3880 #interconnect-cells = 3880 #interconnect-cells = <2>;
3881 }; 3881 };
3882 3882
3883 lpass_lpicx_noc: interconnect 3883 lpass_lpicx_noc: interconnect@7430000 {
3884 compatible = "qcom,x1 3884 compatible = "qcom,x1e80100-lpass-lpicx-noc";
3885 reg = <0 0x07430000 0 3885 reg = <0 0x07430000 0 0x3A200>;
3886 3886
3887 qcom,bcm-voters = <&a 3887 qcom,bcm-voters = <&apps_bcm_voter>;
3888 3888
3889 #interconnect-cells = 3889 #interconnect-cells = <2>;
3890 }; 3890 };
3891 3891
3892 usb_2_hsphy: phy@88e0000 { 3892 usb_2_hsphy: phy@88e0000 {
3893 compatible = "qcom,x1 3893 compatible = "qcom,x1e80100-snps-eusb2-phy",
3894 "qcom,sm 3894 "qcom,sm8550-snps-eusb2-phy";
3895 reg = <0 0x088e0000 0 3895 reg = <0 0x088e0000 0 0x154>;
3896 #phy-cells = <0>; 3896 #phy-cells = <0>;
3897 3897
3898 clocks = <&tcsr TCSR_ 3898 clocks = <&tcsr TCSR_USB2_2_CLKREF_EN>;
3899 clock-names = "ref"; 3899 clock-names = "ref";
3900 3900
3901 resets = <&gcc GCC_QU 3901 resets = <&gcc GCC_QUSB2PHY_USB20_HS_BCR>;
3902 3902
3903 status = "disabled"; 3903 status = "disabled";
3904 }; 3904 };
3905 3905
3906 usb_mp_hsphy0: phy@88e1000 { 3906 usb_mp_hsphy0: phy@88e1000 {
3907 compatible = "qcom,x1 3907 compatible = "qcom,x1e80100-snps-eusb2-phy",
3908 "qcom,sm 3908 "qcom,sm8550-snps-eusb2-phy";
3909 reg = <0 0x088e1000 0 3909 reg = <0 0x088e1000 0 0x154>;
3910 #phy-cells = <0>; 3910 #phy-cells = <0>;
3911 3911
3912 clocks = <&tcsr TCSR_ 3912 clocks = <&tcsr TCSR_USB3_MP0_CLKREF_EN>;
3913 clock-names = "ref"; 3913 clock-names = "ref";
3914 3914
3915 resets = <&gcc GCC_QU 3915 resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>;
3916 3916
3917 status = "disabled"; 3917 status = "disabled";
3918 }; 3918 };
3919 3919
3920 usb_mp_hsphy1: phy@88e2000 { 3920 usb_mp_hsphy1: phy@88e2000 {
3921 compatible = "qcom,x1 3921 compatible = "qcom,x1e80100-snps-eusb2-phy",
3922 "qcom,sm 3922 "qcom,sm8550-snps-eusb2-phy";
3923 reg = <0 0x088e2000 0 3923 reg = <0 0x088e2000 0 0x154>;
3924 #phy-cells = <0>; 3924 #phy-cells = <0>;
3925 3925
3926 clocks = <&tcsr TCSR_ 3926 clocks = <&tcsr TCSR_USB3_MP1_CLKREF_EN>;
3927 clock-names = "ref"; 3927 clock-names = "ref";
3928 3928
3929 resets = <&gcc GCC_QU 3929 resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>;
3930 3930
3931 status = "disabled"; 3931 status = "disabled";
3932 }; 3932 };
3933 3933
3934 usb_mp_qmpphy0: phy@88e3000 { 3934 usb_mp_qmpphy0: phy@88e3000 {
3935 compatible = "qcom,x1 3935 compatible = "qcom,x1e80100-qmp-usb3-uni-phy";
3936 reg = <0 0x088e3000 0 3936 reg = <0 0x088e3000 0 0x2000>;
3937 3937
3938 clocks = <&gcc GCC_US 3938 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
3939 <&rpmhcc RPM 3939 <&rpmhcc RPMH_CXO_CLK>,
3940 <&gcc GCC_US 3940 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
3941 <&gcc GCC_US 3941 <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>;
3942 clock-names = "aux", 3942 clock-names = "aux",
3943 "ref", 3943 "ref",
3944 "com_au 3944 "com_aux",
3945 "pipe"; 3945 "pipe";
3946 3946
3947 resets = <&gcc GCC_US 3947 resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>,
3948 <&gcc GCC_US 3948 <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>;
3949 reset-names = "phy", 3949 reset-names = "phy",
3950 "phy_ph 3950 "phy_phy";
3951 3951
3952 power-domains = <&gcc 3952 power-domains = <&gcc GCC_USB3_MP_SS0_PHY_GDSC>;
3953 3953
3954 #clock-cells = <0>; 3954 #clock-cells = <0>;
3955 clock-output-names = 3955 clock-output-names = "usb_mp_phy0_pipe_clk";
3956 3956
3957 #phy-cells = <0>; 3957 #phy-cells = <0>;
3958 3958
3959 status = "disabled"; 3959 status = "disabled";
3960 }; 3960 };
3961 3961
3962 usb_mp_qmpphy1: phy@88e5000 { 3962 usb_mp_qmpphy1: phy@88e5000 {
3963 compatible = "qcom,x1 3963 compatible = "qcom,x1e80100-qmp-usb3-uni-phy";
3964 reg = <0 0x088e5000 0 3964 reg = <0 0x088e5000 0 0x2000>;
3965 3965
3966 clocks = <&gcc GCC_US 3966 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
3967 <&rpmhcc RPM 3967 <&rpmhcc RPMH_CXO_CLK>,
3968 <&gcc GCC_US 3968 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
3969 <&gcc GCC_US 3969 <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>;
3970 clock-names = "aux", 3970 clock-names = "aux",
3971 "ref", 3971 "ref",
3972 "com_au 3972 "com_aux",
3973 "pipe"; 3973 "pipe";
3974 3974
3975 resets = <&gcc GCC_US 3975 resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>,
3976 <&gcc GCC_US 3976 <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>;
3977 reset-names = "phy", 3977 reset-names = "phy",
3978 "phy_ph 3978 "phy_phy";
3979 3979
3980 power-domains = <&gcc 3980 power-domains = <&gcc GCC_USB3_MP_SS1_PHY_GDSC>;
3981 3981
3982 #clock-cells = <0>; 3982 #clock-cells = <0>;
3983 clock-output-names = 3983 clock-output-names = "usb_mp_phy1_pipe_clk";
3984 3984
3985 #phy-cells = <0>; 3985 #phy-cells = <0>;
3986 3986
3987 status = "disabled"; 3987 status = "disabled";
3988 }; 3988 };
3989 3989
3990 usb_1_ss2: usb@a0f8800 { 3990 usb_1_ss2: usb@a0f8800 {
3991 compatible = "qcom,x1 3991 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3";
3992 reg = <0 0x0a0f8800 0 3992 reg = <0 0x0a0f8800 0 0x400>;
3993 3993
3994 clocks = <&gcc GCC_CF 3994 clocks = <&gcc GCC_CFG_NOC_USB3_TERT_AXI_CLK>,
3995 <&gcc GCC_US 3995 <&gcc GCC_USB30_TERT_MASTER_CLK>,
3996 <&gcc GCC_AG 3996 <&gcc GCC_AGGRE_USB3_TERT_AXI_CLK>,
3997 <&gcc GCC_US 3997 <&gcc GCC_USB30_TERT_SLEEP_CLK>,
3998 <&gcc GCC_US 3998 <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>,
3999 <&gcc GCC_AG 3999 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
4000 <&gcc GCC_AG 4000 <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>,
4001 <&gcc GCC_AG 4001 <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>,
4002 <&gcc GCC_SY 4002 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
4003 clock-names = "cfg_no 4003 clock-names = "cfg_noc",
4004 "core", 4004 "core",
4005 "iface" 4005 "iface",
4006 "sleep" 4006 "sleep",
4007 "mock_u 4007 "mock_utmi",
4008 "noc_ag 4008 "noc_aggr",
4009 "noc_ag 4009 "noc_aggr_north",
4010 "noc_ag 4010 "noc_aggr_south",
4011 "noc_sy 4011 "noc_sys";
4012 4012
4013 assigned-clocks = <&g 4013 assigned-clocks = <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>,
4014 <&g 4014 <&gcc GCC_USB30_TERT_MASTER_CLK>;
4015 assigned-clock-rates 4015 assigned-clock-rates = <19200000>,
4016 4016 <200000000>;
4017 4017
4018 interrupts-extended = 4018 interrupts-extended = <&intc GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
4019 4019 <&pdc 58 IRQ_TYPE_EDGE_BOTH>,
4020 4020 <&pdc 57 IRQ_TYPE_EDGE_BOTH>,
4021 4021 <&pdc 10 IRQ_TYPE_LEVEL_HIGH>;
4022 interrupt-names = "pw 4022 interrupt-names = "pwr_event",
4023 "dp 4023 "dp_hs_phy_irq",
4024 "dm 4024 "dm_hs_phy_irq",
4025 "ss 4025 "ss_phy_irq";
4026 4026
4027 power-domains = <&gcc 4027 power-domains = <&gcc GCC_USB30_TERT_GDSC>;
4028 required-opps = <&rpm 4028 required-opps = <&rpmhpd_opp_nom>;
4029 4029
4030 resets = <&gcc GCC_US 4030 resets = <&gcc GCC_USB30_TERT_BCR>;
4031 4031
4032 interconnects = <&usb 4032 interconnects = <&usb_south_anoc MASTER_USB3_2 QCOM_ICC_TAG_ALWAYS
4033 &mc_ 4033 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
4034 <&gem 4034 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
4035 &con 4035 &config_noc SLAVE_USB3_2 QCOM_ICC_TAG_ALWAYS>;
4036 interconnect-names = 4036 interconnect-names = "usb-ddr",
4037 4037 "apps-usb";
4038 4038
4039 wakeup-source; 4039 wakeup-source;
4040 4040
4041 #address-cells = <2>; 4041 #address-cells = <2>;
4042 #size-cells = <2>; 4042 #size-cells = <2>;
4043 ranges; 4043 ranges;
4044 4044
4045 status = "disabled"; 4045 status = "disabled";
4046 4046
4047 usb_1_ss2_dwc3: usb@a 4047 usb_1_ss2_dwc3: usb@a000000 {
4048 compatible = 4048 compatible = "snps,dwc3";
4049 reg = <0 0x0a 4049 reg = <0 0x0a000000 0 0xcd00>;
4050 4050
4051 interrupts = 4051 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
4052 4052
4053 iommus = <&ap 4053 iommus = <&apps_smmu 0x14a0 0x0>;
4054 4054
4055 phys = <&usb_ 4055 phys = <&usb_1_ss2_hsphy>,
4056 <&usb_ 4056 <&usb_1_ss2_qmpphy QMP_USB43DP_USB3_PHY>;
4057 phy-names = " 4057 phy-names = "usb2-phy",
4058 " 4058 "usb3-phy";
4059 4059
4060 snps,dis_u2_s 4060 snps,dis_u2_susphy_quirk;
4061 snps,dis_enbl 4061 snps,dis_enblslpm_quirk;
4062 snps,usb3_lpm 4062 snps,usb3_lpm_capable;
4063 4063
4064 dma-coherent; 4064 dma-coherent;
4065 4065
4066 ports { 4066 ports {
4067 #addr 4067 #address-cells = <1>;
4068 #size 4068 #size-cells = <0>;
4069 4069
4070 port@ 4070 port@0 {
4071 4071 reg = <0>;
4072 4072
4073 4073 usb_1_ss2_dwc3_hs: endpoint {
4074 4074 };
4075 }; 4075 };
4076 4076
4077 port@ 4077 port@1 {
4078 4078 reg = <1>;
4079 4079
4080 4080 usb_1_ss2_dwc3_ss: endpoint {
4081 4081 remote-endpoint = <&usb_1_ss2_qmpphy_usb_ss_in>;
4082 4082 };
4083 }; 4083 };
4084 }; 4084 };
4085 }; 4085 };
4086 }; 4086 };
4087 4087
4088 usb_2: usb@a2f8800 { 4088 usb_2: usb@a2f8800 {
4089 compatible = "qcom,x1 4089 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3";
4090 reg = <0 0x0a2f8800 0 4090 reg = <0 0x0a2f8800 0 0x400>;
4091 #address-cells = <2>; 4091 #address-cells = <2>;
4092 #size-cells = <2>; 4092 #size-cells = <2>;
4093 ranges; 4093 ranges;
4094 4094
4095 clocks = <&gcc GCC_CF 4095 clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>,
4096 <&gcc GCC_US 4096 <&gcc GCC_USB20_MASTER_CLK>,
4097 <&gcc GCC_AG 4097 <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>,
4098 <&gcc GCC_US 4098 <&gcc GCC_USB20_SLEEP_CLK>,
4099 <&gcc GCC_US 4099 <&gcc GCC_USB20_MOCK_UTMI_CLK>,
4100 <&gcc GCC_AG 4100 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
4101 <&gcc GCC_AG 4101 <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>,
4102 <&gcc GCC_AG 4102 <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>,
4103 <&gcc GCC_SY 4103 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
4104 clock-names = "cfg_no 4104 clock-names = "cfg_noc",
4105 "core", 4105 "core",
4106 "iface" 4106 "iface",
4107 "sleep" 4107 "sleep",
4108 "mock_u 4108 "mock_utmi",
4109 "noc_ag 4109 "noc_aggr",
4110 "noc_ag 4110 "noc_aggr_north",
4111 "noc_ag 4111 "noc_aggr_south",
4112 "noc_sy 4112 "noc_sys";
4113 4113
4114 assigned-clocks = <&g 4114 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
4115 <&g 4115 <&gcc GCC_USB20_MASTER_CLK>;
4116 assigned-clock-rates 4116 assigned-clock-rates = <19200000>, <200000000>;
4117 4117
4118 interrupts-extended = 4118 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
4119 4119 <&pdc 50 IRQ_TYPE_EDGE_BOTH>,
4120 4120 <&pdc 49 IRQ_TYPE_EDGE_BOTH>;
4121 interrupt-names = "pw 4121 interrupt-names = "pwr_event",
4122 "dp 4122 "dp_hs_phy_irq",
4123 "dm 4123 "dm_hs_phy_irq";
4124 4124
4125 power-domains = <&gcc 4125 power-domains = <&gcc GCC_USB20_PRIM_GDSC>;
4126 required-opps = <&rpm 4126 required-opps = <&rpmhpd_opp_nom>;
4127 4127
4128 resets = <&gcc GCC_US 4128 resets = <&gcc GCC_USB20_PRIM_BCR>;
4129 4129
4130 interconnects = <&usb 4130 interconnects = <&usb_north_anoc MASTER_USB2 QCOM_ICC_TAG_ALWAYS
4131 &mc_ 4131 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
4132 <&gem 4132 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
4133 &con 4133 &config_noc SLAVE_USB2 QCOM_ICC_TAG_ALWAYS>;
4134 interconnect-names = 4134 interconnect-names = "usb-ddr",
4135 4135 "apps-usb";
4136 4136
4137 wakeup-source; 4137 wakeup-source;
4138 4138
4139 status = "disabled"; 4139 status = "disabled";
4140 4140
4141 usb_2_dwc3: usb@a2000 4141 usb_2_dwc3: usb@a200000 {
4142 compatible = 4142 compatible = "snps,dwc3";
4143 reg = <0 0x0a 4143 reg = <0 0x0a200000 0 0xcd00>;
4144 interrupts = 4144 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
4145 iommus = <&ap 4145 iommus = <&apps_smmu 0x14e0 0x0>;
4146 phys = <&usb_ 4146 phys = <&usb_2_hsphy>;
4147 phy-names = " 4147 phy-names = "usb2-phy";
4148 maximum-speed 4148 maximum-speed = "high-speed";
4149 4149
4150 ports { 4150 ports {
4151 #addr 4151 #address-cells = <1>;
4152 #size 4152 #size-cells = <0>;
4153 4153
4154 port@ 4154 port@0 {
4155 4155 reg = <0>;
4156 4156
4157 4157 usb_2_dwc3_hs: endpoint {
4158 4158 };
4159 }; 4159 };
4160 }; 4160 };
4161 }; 4161 };
4162 }; 4162 };
4163 4163
4164 usb_mp: usb@a4f8800 { 4164 usb_mp: usb@a4f8800 {
4165 compatible = "qcom,x1 4165 compatible = "qcom,x1e80100-dwc3-mp", "qcom,dwc3";
4166 reg = <0 0x0a4f8800 0 4166 reg = <0 0x0a4f8800 0 0x400>;
4167 4167
4168 clocks = <&gcc GCC_CF 4168 clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>,
4169 <&gcc GCC_US 4169 <&gcc GCC_USB30_MP_MASTER_CLK>,
4170 <&gcc GCC_AG 4170 <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>,
4171 <&gcc GCC_US 4171 <&gcc GCC_USB30_MP_SLEEP_CLK>,
4172 <&gcc GCC_US 4172 <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
4173 <&gcc GCC_AG 4173 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
4174 <&gcc GCC_AG 4174 <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>,
4175 <&gcc GCC_AG 4175 <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>,
4176 <&gcc GCC_SY 4176 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
4177 clock-names = "cfg_no 4177 clock-names = "cfg_noc",
4178 "core", 4178 "core",
4179 "iface" 4179 "iface",
4180 "sleep" 4180 "sleep",
4181 "mock_u 4181 "mock_utmi",
4182 "noc_ag 4182 "noc_aggr",
4183 "noc_ag 4183 "noc_aggr_north",
4184 "noc_ag 4184 "noc_aggr_south",
4185 "noc_sy 4185 "noc_sys";
4186 4186
4187 assigned-clocks = <&g 4187 assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
4188 <&g 4188 <&gcc GCC_USB30_MP_MASTER_CLK>;
4189 assigned-clock-rates 4189 assigned-clock-rates = <19200000>,
4190 4190 <200000000>;
4191 4191
4192 interrupts-extended = 4192 interrupts-extended = <&intc GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
4193 4193 <&intc GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
4194 4194 <&intc GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
4195 4195 <&intc GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
4196 4196 <&pdc 52 IRQ_TYPE_EDGE_BOTH>,
4197 4197 <&pdc 51 IRQ_TYPE_EDGE_BOTH>,
4198 4198 <&pdc 54 IRQ_TYPE_EDGE_BOTH>,
4199 4199 <&pdc 53 IRQ_TYPE_EDGE_BOTH>,
4200 4200 <&pdc 55 IRQ_TYPE_LEVEL_HIGH>,
4201 4201 <&pdc 56 IRQ_TYPE_LEVEL_HIGH>;
4202 interrupt-names = "pw 4202 interrupt-names = "pwr_event_1", "pwr_event_2",
4203 "hs 4203 "hs_phy_1", "hs_phy_2",
4204 "dp 4204 "dp_hs_phy_1", "dm_hs_phy_1",
4205 "dp 4205 "dp_hs_phy_2", "dm_hs_phy_2",
4206 "ss 4206 "ss_phy_1", "ss_phy_2";
4207 4207
4208 power-domains = <&gcc 4208 power-domains = <&gcc GCC_USB30_MP_GDSC>;
4209 required-opps = <&rpm 4209 required-opps = <&rpmhpd_opp_nom>;
4210 4210
4211 resets = <&gcc GCC_US 4211 resets = <&gcc GCC_USB30_MP_BCR>;
4212 4212
4213 interconnects = <&usb 4213 interconnects = <&usb_north_anoc MASTER_USB3_MP QCOM_ICC_TAG_ALWAYS
4214 &mc_ 4214 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
4215 <&gem 4215 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
4216 &con 4216 &config_noc SLAVE_USB3_MP QCOM_ICC_TAG_ALWAYS>;
4217 interconnect-names = 4217 interconnect-names = "usb-ddr",
4218 4218 "apps-usb";
4219 4219
4220 wakeup-source; 4220 wakeup-source;
4221 4221
4222 #address-cells = <2>; 4222 #address-cells = <2>;
4223 #size-cells = <2>; 4223 #size-cells = <2>;
4224 ranges; 4224 ranges;
4225 4225
4226 status = "disabled"; 4226 status = "disabled";
4227 4227
4228 usb_mp_dwc3: usb@a400 4228 usb_mp_dwc3: usb@a400000 {
4229 compatible = 4229 compatible = "snps,dwc3";
4230 reg = <0 0x0a 4230 reg = <0 0x0a400000 0 0xcd00>;
4231 4231
4232 interrupts = 4232 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
4233 4233
4234 iommus = <&ap 4234 iommus = <&apps_smmu 0x1400 0x0>;
4235 4235
4236 phys = <&usb_ 4236 phys = <&usb_mp_hsphy0>, <&usb_mp_qmpphy0>,
4237 <&usb_ 4237 <&usb_mp_hsphy1>, <&usb_mp_qmpphy1>;
4238 phy-names = " 4238 phy-names = "usb2-0", "usb3-0",
4239 " 4239 "usb2-1", "usb3-1";
4240 dr_mode = "ho 4240 dr_mode = "host";
4241 4241
4242 snps,dis_u2_s 4242 snps,dis_u2_susphy_quirk;
4243 snps,dis_enbl 4243 snps,dis_enblslpm_quirk;
4244 snps,usb3_lpm 4244 snps,usb3_lpm_capable;
4245 4245
4246 dma-coherent; 4246 dma-coherent;
4247 }; 4247 };
4248 }; 4248 };
4249 4249
4250 usb_1_ss0: usb@a6f8800 { 4250 usb_1_ss0: usb@a6f8800 {
4251 compatible = "qcom,x1 4251 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3";
4252 reg = <0 0x0a6f8800 0 4252 reg = <0 0x0a6f8800 0 0x400>;
4253 4253
4254 clocks = <&gcc GCC_CF 4254 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
4255 <&gcc GCC_US 4255 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
4256 <&gcc GCC_AG 4256 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
4257 <&gcc GCC_US 4257 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
4258 <&gcc GCC_US 4258 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4259 <&gcc GCC_AG 4259 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
4260 <&gcc GCC_CF 4260 <&gcc GCC_CFG_NOC_USB_ANOC_NORTH_AHB_CLK>,
4261 <&gcc GCC_CF 4261 <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>,
4262 <&gcc GCC_SY 4262 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
4263 clock-names = "cfg_no 4263 clock-names = "cfg_noc",
4264 "core", 4264 "core",
4265 "iface" 4265 "iface",
4266 "sleep" 4266 "sleep",
4267 "mock_u 4267 "mock_utmi",
4268 "noc_ag 4268 "noc_aggr",
4269 "noc_ag 4269 "noc_aggr_north",
4270 "noc_ag 4270 "noc_aggr_south",
4271 "noc_sy 4271 "noc_sys";
4272 4272
4273 assigned-clocks = <&g 4273 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4274 <&g 4274 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
4275 assigned-clock-rates 4275 assigned-clock-rates = <19200000>,
4276 4276 <200000000>;
4277 4277
4278 interrupts-extended = 4278 interrupts-extended = <&intc GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>,
4279 4279 <&pdc 61 IRQ_TYPE_EDGE_BOTH>,
4280 4280 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
4281 4281 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
4282 interrupt-names = "pw 4282 interrupt-names = "pwr_event",
4283 "dp 4283 "dp_hs_phy_irq",
4284 "dm 4284 "dm_hs_phy_irq",
4285 "ss 4285 "ss_phy_irq";
4286 4286
4287 power-domains = <&gcc 4287 power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
4288 required-opps = <&rpm 4288 required-opps = <&rpmhpd_opp_nom>;
4289 4289
4290 resets = <&gcc GCC_US 4290 resets = <&gcc GCC_USB30_PRIM_BCR>;
4291 4291
4292 wakeup-source; 4292 wakeup-source;
4293 4293
4294 #address-cells = <2>; 4294 #address-cells = <2>;
4295 #size-cells = <2>; 4295 #size-cells = <2>;
4296 ranges; 4296 ranges;
4297 4297
4298 status = "disabled"; 4298 status = "disabled";
4299 4299
4300 usb_1_ss0_dwc3: usb@a 4300 usb_1_ss0_dwc3: usb@a600000 {
4301 compatible = 4301 compatible = "snps,dwc3";
4302 reg = <0 0x0a 4302 reg = <0 0x0a600000 0 0xcd00>;
4303 4303
4304 interrupts = 4304 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
4305 4305
4306 iommus = <&ap 4306 iommus = <&apps_smmu 0x1420 0x0>;
4307 4307
4308 phys = <&usb_ 4308 phys = <&usb_1_ss0_hsphy>,
4309 <&usb_ 4309 <&usb_1_ss0_qmpphy QMP_USB43DP_USB3_PHY>;
4310 phy-names = " 4310 phy-names = "usb2-phy",
4311 " 4311 "usb3-phy";
4312 4312
4313 snps,dis_u2_s 4313 snps,dis_u2_susphy_quirk;
4314 snps,dis_enbl 4314 snps,dis_enblslpm_quirk;
4315 snps,usb3_lpm 4315 snps,usb3_lpm_capable;
4316 4316
4317 dma-coherent; 4317 dma-coherent;
4318 4318
4319 ports { 4319 ports {
4320 #addr 4320 #address-cells = <1>;
4321 #size 4321 #size-cells = <0>;
4322 4322
4323 port@ 4323 port@0 {
4324 4324 reg = <0>;
4325 4325
4326 4326 usb_1_ss0_dwc3_hs: endpoint {
4327 4327 };
4328 }; 4328 };
4329 4329
4330 port@ 4330 port@1 {
4331 4331 reg = <1>;
4332 4332
4333 4333 usb_1_ss0_dwc3_ss: endpoint {
4334 4334 remote-endpoint = <&usb_1_ss0_qmpphy_usb_ss_in>;
4335 4335 };
4336 }; 4336 };
4337 }; 4337 };
4338 }; 4338 };
4339 }; 4339 };
4340 4340
4341 usb_1_ss1: usb@a8f8800 { 4341 usb_1_ss1: usb@a8f8800 {
4342 compatible = "qcom,x1 4342 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3";
4343 reg = <0 0x0a8f8800 0 4343 reg = <0 0x0a8f8800 0 0x400>;
4344 4344
4345 clocks = <&gcc GCC_CF 4345 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
4346 <&gcc GCC_US 4346 <&gcc GCC_USB30_SEC_MASTER_CLK>,
4347 <&gcc GCC_AG 4347 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
4348 <&gcc GCC_US 4348 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
4349 <&gcc GCC_US 4349 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4350 <&gcc GCC_AG 4350 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
4351 <&gcc GCC_AG 4351 <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>,
4352 <&gcc GCC_AG 4352 <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>,
4353 <&gcc GCC_SY 4353 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
4354 clock-names = "cfg_no 4354 clock-names = "cfg_noc",
4355 "core", 4355 "core",
4356 "iface" 4356 "iface",
4357 "sleep" 4357 "sleep",
4358 "mock_u 4358 "mock_utmi",
4359 "noc_ag 4359 "noc_aggr",
4360 "noc_ag 4360 "noc_aggr_north",
4361 "noc_ag 4361 "noc_aggr_south",
4362 "noc_sy 4362 "noc_sys";
4363 4363
4364 assigned-clocks = <&g 4364 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4365 <&g 4365 <&gcc GCC_USB30_SEC_MASTER_CLK>;
4366 assigned-clock-rates 4366 assigned-clock-rates = <19200000>,
4367 4367 <200000000>;
4368 4368
4369 interrupts-extended = 4369 interrupts-extended = <&intc GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>,
4370 4370 <&pdc 60 IRQ_TYPE_EDGE_BOTH>,
4371 4371 <&pdc 11 IRQ_TYPE_EDGE_BOTH>,
4372 4372 <&pdc 47 IRQ_TYPE_LEVEL_HIGH>;
4373 interrupt-names = "pw 4373 interrupt-names = "pwr_event",
4374 "dp 4374 "dp_hs_phy_irq",
4375 "dm 4375 "dm_hs_phy_irq",
4376 "ss 4376 "ss_phy_irq";
4377 4377
4378 power-domains = <&gcc 4378 power-domains = <&gcc GCC_USB30_SEC_GDSC>;
4379 required-opps = <&rpm 4379 required-opps = <&rpmhpd_opp_nom>;
4380 4380
4381 resets = <&gcc GCC_US 4381 resets = <&gcc GCC_USB30_SEC_BCR>;
4382 4382
4383 interconnects = <&usb 4383 interconnects = <&usb_south_anoc MASTER_USB3_1 QCOM_ICC_TAG_ALWAYS
4384 &mc_ 4384 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
4385 <&gem 4385 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
4386 &con 4386 &config_noc SLAVE_USB3_1 QCOM_ICC_TAG_ALWAYS>;
4387 interconnect-names = 4387 interconnect-names = "usb-ddr",
4388 4388 "apps-usb";
4389 4389
4390 wakeup-source; 4390 wakeup-source;
4391 4391
4392 #address-cells = <2>; 4392 #address-cells = <2>;
4393 #size-cells = <2>; 4393 #size-cells = <2>;
4394 ranges; 4394 ranges;
4395 4395
4396 status = "disabled"; 4396 status = "disabled";
4397 4397
4398 usb_1_ss1_dwc3: usb@a 4398 usb_1_ss1_dwc3: usb@a800000 {
4399 compatible = 4399 compatible = "snps,dwc3";
4400 reg = <0 0x0a 4400 reg = <0 0x0a800000 0 0xcd00>;
4401 4401
4402 interrupts = 4402 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
4403 4403
4404 iommus = <&ap 4404 iommus = <&apps_smmu 0x1460 0x0>;
4405 4405
4406 phys = <&usb_ 4406 phys = <&usb_1_ss1_hsphy>,
4407 <&usb_ 4407 <&usb_1_ss1_qmpphy QMP_USB43DP_USB3_PHY>;
4408 phy-names = " 4408 phy-names = "usb2-phy",
4409 " 4409 "usb3-phy";
4410 4410
4411 snps,dis_u2_s 4411 snps,dis_u2_susphy_quirk;
4412 snps,dis_enbl 4412 snps,dis_enblslpm_quirk;
4413 snps,usb3_lpm 4413 snps,usb3_lpm_capable;
4414 4414
4415 dma-coherent; 4415 dma-coherent;
4416 4416
4417 ports { 4417 ports {
4418 #addr 4418 #address-cells = <1>;
4419 #size 4419 #size-cells = <0>;
4420 4420
4421 port@ 4421 port@0 {
4422 4422 reg = <0>;
4423 4423
4424 4424 usb_1_ss1_dwc3_hs: endpoint {
4425 4425 };
4426 }; 4426 };
4427 4427
4428 port@ 4428 port@1 {
4429 4429 reg = <1>;
4430 4430
4431 4431 usb_1_ss1_dwc3_ss: endpoint {
4432 4432 remote-endpoint = <&usb_1_ss1_qmpphy_usb_ss_in>;
4433 4433 };
4434 }; 4434 };
4435 }; 4435 };
4436 }; 4436 };
4437 }; 4437 };
4438 4438
4439 mdss: display-subsystem@ae000 4439 mdss: display-subsystem@ae00000 {
4440 compatible = "qcom,x1 4440 compatible = "qcom,x1e80100-mdss";
4441 reg = <0 0x0ae00000 0 4441 reg = <0 0x0ae00000 0 0x1000>;
4442 reg-names = "mdss"; 4442 reg-names = "mdss";
4443 4443
4444 interrupts = <GIC_SPI 4444 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
4445 4445
4446 clocks = <&dispcc DIS 4446 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4447 <&gcc GCC_DI 4447 <&gcc GCC_DISP_HF_AXI_CLK>,
4448 <&dispcc DIS 4448 <&dispcc DISP_CC_MDSS_MDP_CLK>;
4449 4449
4450 resets = <&dispcc DIS 4450 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
4451 4451
4452 interconnects = <&mms 4452 interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS
4453 &gem 4453 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
4454 <&mc_ 4454 <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS
4455 &mc_ 4455 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
4456 <&gem 4456 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
4457 &con 4457 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
4458 interconnect-names = 4458 interconnect-names = "mdp0-mem",
4459 4459 "mdp1-mem",
4460 4460 "cpu-cfg";
4461 4461
4462 power-domains = <&dis 4462 power-domains = <&dispcc MDSS_GDSC>;
4463 4463
4464 iommus = <&apps_smmu 4464 iommus = <&apps_smmu 0x1c00 0x2>;
4465 4465
4466 interrupt-controller; 4466 interrupt-controller;
4467 #interrupt-cells = <1 4467 #interrupt-cells = <1>;
4468 4468
4469 #address-cells = <2>; 4469 #address-cells = <2>;
4470 #size-cells = <2>; 4470 #size-cells = <2>;
4471 ranges; 4471 ranges;
4472 4472
4473 status = "disabled"; 4473 status = "disabled";
4474 4474
4475 mdss_mdp: display-con 4475 mdss_mdp: display-controller@ae01000 {
4476 compatible = 4476 compatible = "qcom,x1e80100-dpu";
4477 reg = <0 0x0a 4477 reg = <0 0x0ae01000 0 0x8f000>,
4478 <0 0x0a 4478 <0 0x0aeb0000 0 0x2008>;
4479 reg-names = " 4479 reg-names = "mdp",
4480 " 4480 "vbif";
4481 4481
4482 interrupts-ex 4482 interrupts-extended = <&mdss 0>;
4483 4483
4484 clocks = <&gc 4484 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
4485 <&di 4485 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4486 <&di 4486 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
4487 <&di 4487 <&dispcc DISP_CC_MDSS_MDP_CLK>,
4488 <&di 4488 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4489 clock-names = 4489 clock-names = "nrt_bus",
4490 4490 "iface",
4491 4491 "lut",
4492 4492 "core",
4493 4493 "vsync";
4494 4494
4495 operating-poi 4495 operating-points-v2 = <&mdp_opp_table>;
4496 4496
4497 power-domains 4497 power-domains = <&rpmhpd RPMHPD_MMCX>;
4498 4498
4499 ports { 4499 ports {
4500 #addr 4500 #address-cells = <1>;
4501 #size 4501 #size-cells = <0>;
4502 4502
4503 port@ 4503 port@0 {
4504 4504 reg = <0>;
4505 4505
4506 4506 mdss_intf0_out: endpoint {
4507 4507 remote-endpoint = <&mdss_dp0_in>;
4508 4508 };
4509 }; 4509 };
4510 4510
4511 port@ 4511 port@4 {
4512 4512 reg = <4>;
4513 4513
4514 4514 mdss_intf4_out: endpoint {
4515 4515 remote-endpoint = <&mdss_dp1_in>;
4516 4516 };
4517 }; 4517 };
4518 4518
4519 port@ 4519 port@5 {
4520 4520 reg = <5>;
4521 4521
4522 4522 mdss_intf5_out: endpoint {
4523 4523 remote-endpoint = <&mdss_dp3_in>;
4524 4524 };
4525 }; 4525 };
4526 4526
4527 port@ 4527 port@6 {
4528 4528 reg = <6>;
4529 4529
4530 4530 mdss_intf6_out: endpoint {
4531 4531 remote-endpoint = <&mdss_dp2_in>;
4532 4532 };
4533 }; 4533 };
4534 }; 4534 };
4535 4535
4536 mdp_opp_table 4536 mdp_opp_table: opp-table {
4537 compa 4537 compatible = "operating-points-v2";
4538 4538
4539 opp-2 4539 opp-200000000 {
4540 4540 opp-hz = /bits/ 64 <200000000>;
4541 4541 required-opps = <&rpmhpd_opp_low_svs>;
4542 }; 4542 };
4543 4543
4544 opp-3 4544 opp-325000000 {
4545 4545 opp-hz = /bits/ 64 <325000000>;
4546 4546 required-opps = <&rpmhpd_opp_svs>;
4547 }; 4547 };
4548 4548
4549 opp-3 4549 opp-375000000 {
4550 4550 opp-hz = /bits/ 64 <375000000>;
4551 4551 required-opps = <&rpmhpd_opp_svs_l1>;
4552 }; 4552 };
4553 4553
4554 opp-5 4554 opp-514000000 {
4555 4555 opp-hz = /bits/ 64 <514000000>;
4556 4556 required-opps = <&rpmhpd_opp_nom>;
4557 }; 4557 };
4558 4558
4559 opp-5 4559 opp-575000000 {
4560 4560 opp-hz = /bits/ 64 <575000000>;
4561 4561 required-opps = <&rpmhpd_opp_nom_l1>;
4562 }; 4562 };
4563 }; 4563 };
4564 }; 4564 };
4565 4565
4566 mdss_dp0: displayport 4566 mdss_dp0: displayport-controller@ae90000 {
4567 compatible = 4567 compatible = "qcom,x1e80100-dp";
4568 reg = <0 0x0a 4568 reg = <0 0x0ae90000 0 0x200>,
4569 <0 0x0a 4569 <0 0x0ae90200 0 0x200>,
4570 <0 0x0a 4570 <0 0x0ae90400 0 0x600>,
4571 <0 0x0a 4571 <0 0x0ae91000 0 0x400>,
4572 <0 0x0a 4572 <0 0x0ae91400 0 0x400>;
4573 4573
4574 interrupts-ex 4574 interrupts-extended = <&mdss 12>;
4575 4575
4576 clocks = <&di 4576 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4577 <&di 4577 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
4578 <&di 4578 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
4579 <&di 4579 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
4580 <&di 4580 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
4581 clock-names = 4581 clock-names = "core_iface",
4582 4582 "core_aux",
4583 4583 "ctrl_link",
4584 4584 "ctrl_link_iface",
4585 4585 "stream_pixel";
4586 4586
4587 assigned-cloc 4587 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
4588 4588 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
4589 assigned-cloc 4589 assigned-clock-parents = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4590 4590 <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
4591 4591
4592 operating-poi 4592 operating-points-v2 = <&mdss_dp0_opp_table>;
4593 4593
4594 power-domains 4594 power-domains = <&rpmhpd RPMHPD_MMCX>;
4595 4595
4596 phys = <&usb_ 4596 phys = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_PHY>;
4597 phy-names = " 4597 phy-names = "dp";
4598 4598
4599 #sound-dai-ce 4599 #sound-dai-cells = <0>;
4600 4600
4601 status = "dis 4601 status = "disabled";
4602 4602
4603 ports { 4603 ports {
4604 #addr 4604 #address-cells = <1>;
4605 #size 4605 #size-cells = <0>;
4606 4606
4607 port@ 4607 port@0 {
4608 4608 reg = <0>;
4609 4609
4610 4610 mdss_dp0_in: endpoint {
4611 4611 remote-endpoint = <&mdss_intf0_out>;
4612 4612 };
4613 }; 4613 };
4614 4614
4615 port@ 4615 port@1 {
4616 4616 reg = <1>;
4617 4617
4618 4618 mdss_dp0_out: endpoint {
4619 4619 remote-endpoint = <&usb_1_ss0_qmpphy_dp_in>;
4620 4620 };
4621 }; 4621 };
4622 }; 4622 };
4623 4623
4624 mdss_dp0_opp_ 4624 mdss_dp0_opp_table: opp-table {
4625 compa 4625 compatible = "operating-points-v2";
4626 4626
4627 opp-1 4627 opp-160000000 {
4628 4628 opp-hz = /bits/ 64 <160000000>;
4629 4629 required-opps = <&rpmhpd_opp_low_svs>;
4630 }; 4630 };
4631 4631
4632 opp-2 4632 opp-270000000 {
4633 4633 opp-hz = /bits/ 64 <270000000>;
4634 4634 required-opps = <&rpmhpd_opp_svs>;
4635 }; 4635 };
4636 4636
4637 opp-5 4637 opp-540000000 {
4638 4638 opp-hz = /bits/ 64 <540000000>;
4639 4639 required-opps = <&rpmhpd_opp_svs_l1>;
4640 }; 4640 };
4641 4641
4642 opp-8 4642 opp-810000000 {
4643 4643 opp-hz = /bits/ 64 <810000000>;
4644 4644 required-opps = <&rpmhpd_opp_nom>;
4645 }; 4645 };
4646 }; 4646 };
4647 }; 4647 };
4648 4648
4649 mdss_dp1: displayport 4649 mdss_dp1: displayport-controller@ae98000 {
4650 compatible = 4650 compatible = "qcom,x1e80100-dp";
4651 reg = <0 0x0a 4651 reg = <0 0x0ae98000 0 0x200>,
4652 <0 0x0a 4652 <0 0x0ae98200 0 0x200>,
4653 <0 0x0a 4653 <0 0x0ae98400 0 0x600>,
4654 <0 0x0a 4654 <0 0x0ae99000 0 0x400>,
4655 <0 0x0a 4655 <0 0x0ae99400 0 0x400>;
4656 4656
4657 interrupts-ex 4657 interrupts-extended = <&mdss 13>;
4658 4658
4659 clocks = <&di 4659 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4660 <&di 4660 <&dispcc DISP_CC_MDSS_DPTX1_AUX_CLK>,
4661 <&di 4661 <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK>,
4662 <&di 4662 <&dispcc DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
4663 <&di 4663 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK>;
4664 clock-names = 4664 clock-names = "core_iface",
4665 4665 "core_aux",
4666 4666 "ctrl_link",
4667 4667 "ctrl_link_iface",
4668 4668 "stream_pixel";
4669 4669
4670 assigned-cloc 4670 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
4671 4671 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>;
4672 assigned-cloc 4672 assigned-clock-parents = <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4673 4673 <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
4674 4674
4675 operating-poi 4675 operating-points-v2 = <&mdss_dp1_opp_table>;
4676 4676
4677 power-domains 4677 power-domains = <&rpmhpd RPMHPD_MMCX>;
4678 4678
4679 phys = <&usb_ 4679 phys = <&usb_1_ss1_qmpphy QMP_USB43DP_DP_PHY>;
4680 phy-names = " 4680 phy-names = "dp";
4681 4681
4682 #sound-dai-ce 4682 #sound-dai-cells = <0>;
4683 4683
4684 status = "dis 4684 status = "disabled";
4685 4685
4686 ports { 4686 ports {
4687 #addr 4687 #address-cells = <1>;
4688 #size 4688 #size-cells = <0>;
4689 4689
4690 port@ 4690 port@0 {
4691 4691 reg = <0>;
4692 4692
4693 4693 mdss_dp1_in: endpoint {
4694 4694 remote-endpoint = <&mdss_intf4_out>;
4695 4695 };
4696 }; 4696 };
4697 4697
4698 port@ 4698 port@1 {
4699 4699 reg = <1>;
4700 4700
4701 4701 mdss_dp1_out: endpoint {
4702 4702 remote-endpoint = <&usb_1_ss1_qmpphy_dp_in>;
4703 4703 };
4704 }; 4704 };
4705 }; 4705 };
4706 4706
4707 mdss_dp1_opp_ 4707 mdss_dp1_opp_table: opp-table {
4708 compa 4708 compatible = "operating-points-v2";
4709 4709
4710 opp-1 4710 opp-160000000 {
4711 4711 opp-hz = /bits/ 64 <160000000>;
4712 4712 required-opps = <&rpmhpd_opp_low_svs>;
4713 }; 4713 };
4714 4714
4715 opp-2 4715 opp-270000000 {
4716 4716 opp-hz = /bits/ 64 <270000000>;
4717 4717 required-opps = <&rpmhpd_opp_svs>;
4718 }; 4718 };
4719 4719
4720 opp-5 4720 opp-540000000 {
4721 4721 opp-hz = /bits/ 64 <540000000>;
4722 4722 required-opps = <&rpmhpd_opp_svs_l1>;
4723 }; 4723 };
4724 4724
4725 opp-8 4725 opp-810000000 {
4726 4726 opp-hz = /bits/ 64 <810000000>;
4727 4727 required-opps = <&rpmhpd_opp_nom>;
4728 }; 4728 };
4729 }; 4729 };
4730 }; 4730 };
4731 4731
4732 mdss_dp2: displayport 4732 mdss_dp2: displayport-controller@ae9a000 {
4733 compatible = 4733 compatible = "qcom,x1e80100-dp";
4734 reg = <0 0x0a 4734 reg = <0 0x0ae9a000 0 0x200>,
4735 <0 0x0a 4735 <0 0x0ae9a200 0 0x200>,
4736 <0 0x0a 4736 <0 0x0ae9a400 0 0x600>,
4737 <0 0x0a 4737 <0 0x0ae9b000 0 0x400>,
4738 <0 0x0a 4738 <0 0x0ae9b400 0 0x400>;
4739 4739
4740 interrupts-ex 4740 interrupts-extended = <&mdss 14>;
4741 4741
4742 clocks = <&di 4742 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4743 <&di 4743 <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>,
4744 <&di 4744 <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK>,
4745 <&di 4745 <&dispcc DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>,
4746 <&di 4746 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK>;
4747 clock-names = 4747 clock-names = "core_iface",
4748 4748 "core_aux",
4749 4749 "ctrl_link",
4750 4750 "ctrl_link_iface",
4751 4751 "stream_pixel";
4752 4752
4753 assigned-cloc 4753 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
4754 4754 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>;
4755 assigned-cloc 4755 assigned-clock-parents = <&usb_1_ss2_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4756 4756 <&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
4757 4757
4758 operating-poi 4758 operating-points-v2 = <&mdss_dp2_opp_table>;
4759 4759
4760 power-domains 4760 power-domains = <&rpmhpd RPMHPD_MMCX>;
4761 4761
4762 phys = <&usb_ 4762 phys = <&usb_1_ss2_qmpphy QMP_USB43DP_DP_PHY>;
4763 phy-names = " 4763 phy-names = "dp";
4764 4764
4765 #sound-dai-ce 4765 #sound-dai-cells = <0>;
4766 4766
4767 status = "dis 4767 status = "disabled";
4768 4768
4769 ports { 4769 ports {
4770 #addr 4770 #address-cells = <1>;
4771 #size 4771 #size-cells = <0>;
4772 4772
4773 port@ 4773 port@0 {
4774 4774 reg = <0>;
4775 4775 mdss_dp2_in: endpoint {
4776 4776 remote-endpoint = <&mdss_intf6_out>;
4777 4777 };
4778 }; 4778 };
4779 4779
4780 port@ 4780 port@1 {
4781 4781 reg = <1>;
4782 4782
4783 4783 mdss_dp2_out: endpoint {
4784 4784 remote-endpoint = <&usb_1_ss2_qmpphy_dp_in>;
4785 4785 };
4786 }; 4786 };
4787 }; 4787 };
4788 4788
4789 mdss_dp2_opp_ 4789 mdss_dp2_opp_table: opp-table {
4790 compa 4790 compatible = "operating-points-v2";
4791 4791
4792 opp-1 4792 opp-160000000 {
4793 4793 opp-hz = /bits/ 64 <160000000>;
4794 4794 required-opps = <&rpmhpd_opp_low_svs>;
4795 }; 4795 };
4796 4796
4797 opp-2 4797 opp-270000000 {
4798 4798 opp-hz = /bits/ 64 <270000000>;
4799 4799 required-opps = <&rpmhpd_opp_svs>;
4800 }; 4800 };
4801 4801
4802 opp-5 4802 opp-540000000 {
4803 4803 opp-hz = /bits/ 64 <540000000>;
4804 4804 required-opps = <&rpmhpd_opp_svs_l1>;
4805 }; 4805 };
4806 4806
4807 opp-8 4807 opp-810000000 {
4808 4808 opp-hz = /bits/ 64 <810000000>;
4809 4809 required-opps = <&rpmhpd_opp_nom>;
4810 }; 4810 };
4811 }; 4811 };
4812 }; 4812 };
4813 4813
4814 mdss_dp3: displayport 4814 mdss_dp3: displayport-controller@aea0000 {
4815 compatible = 4815 compatible = "qcom,x1e80100-dp";
4816 reg = <0 0x0a 4816 reg = <0 0x0aea0000 0 0x200>,
4817 <0 0x0a 4817 <0 0x0aea0200 0 0x200>,
4818 <0 0x0a 4818 <0 0x0aea0400 0 0x600>,
4819 <0 0x0a 4819 <0 0x0aea1000 0 0x400>,
4820 <0 0x0a 4820 <0 0x0aea1400 0 0x400>;
4821 4821
4822 interrupts-ex 4822 interrupts-extended = <&mdss 15>;
4823 4823
4824 clocks = <&di 4824 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4825 <&di 4825 <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>,
4826 <&di 4826 <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK>,
4827 <&di 4827 <&dispcc DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>,
4828 <&di 4828 <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK>;
4829 clock-names = 4829 clock-names = "core_iface",
4830 4830 "core_aux",
4831 4831 "ctrl_link",
4832 4832 "ctrl_link_iface",
4833 4833 "stream_pixel";
4834 4834
4835 assigned-cloc 4835 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>,
4836 4836 <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>;
4837 assigned-cloc 4837 assigned-clock-parents = <&mdss_dp3_phy 0>,
4838 4838 <&mdss_dp3_phy 1>;
4839 4839
4840 operating-poi 4840 operating-points-v2 = <&mdss_dp3_opp_table>;
4841 4841
4842 power-domains 4842 power-domains = <&rpmhpd RPMHPD_MMCX>;
4843 4843
4844 phys = <&mdss 4844 phys = <&mdss_dp3_phy>;
4845 phy-names = " 4845 phy-names = "dp";
4846 4846
4847 #sound-dai-ce 4847 #sound-dai-cells = <0>;
4848 4848
4849 status = "dis 4849 status = "disabled";
4850 4850
4851 ports { 4851 ports {
4852 #addr 4852 #address-cells = <1>;
4853 #size 4853 #size-cells = <0>;
4854 4854
4855 port@ 4855 port@0 {
4856 4856 reg = <0>;
4857 4857
4858 4858 mdss_dp3_in: endpoint {
4859 4859 remote-endpoint = <&mdss_intf5_out>;
4860 4860 };
4861 }; 4861 };
4862 4862
4863 port@ 4863 port@1 {
4864 4864 reg = <1>;
4865 }; 4865 };
4866 }; 4866 };
4867 4867
4868 mdss_dp3_opp_ 4868 mdss_dp3_opp_table: opp-table {
4869 compa 4869 compatible = "operating-points-v2";
4870 4870
4871 opp-1 4871 opp-160000000 {
4872 4872 opp-hz = /bits/ 64 <160000000>;
4873 4873 required-opps = <&rpmhpd_opp_low_svs>;
4874 }; 4874 };
4875 4875
4876 opp-2 4876 opp-270000000 {
4877 4877 opp-hz = /bits/ 64 <270000000>;
4878 4878 required-opps = <&rpmhpd_opp_svs>;
4879 }; 4879 };
4880 4880
4881 opp-5 4881 opp-540000000 {
4882 4882 opp-hz = /bits/ 64 <540000000>;
4883 4883 required-opps = <&rpmhpd_opp_svs_l1>;
4884 }; 4884 };
4885 4885
4886 opp-8 4886 opp-810000000 {
4887 4887 opp-hz = /bits/ 64 <810000000>;
4888 4888 required-opps = <&rpmhpd_opp_nom>;
4889 }; 4889 };
4890 }; 4890 };
4891 }; 4891 };
4892 4892
4893 }; 4893 };
4894 4894
4895 mdss_dp2_phy: phy@aec2a00 { 4895 mdss_dp2_phy: phy@aec2a00 {
4896 compatible = "qcom,x1 4896 compatible = "qcom,x1e80100-dp-phy";
4897 reg = <0 0x0aec2a00 0 4897 reg = <0 0x0aec2a00 0 0x19c>,
4898 <0 0x0aec2200 0 4898 <0 0x0aec2200 0 0xec>,
4899 <0 0x0aec2600 0 4899 <0 0x0aec2600 0 0xec>,
4900 <0 0x0aec2000 0 4900 <0 0x0aec2000 0 0x1c8>;
4901 4901
4902 clocks = <&dispcc DIS 4902 clocks = <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>,
4903 <&dispcc DIS 4903 <&dispcc DISP_CC_MDSS_AHB_CLK>;
4904 clock-names = "aux", 4904 clock-names = "aux",
4905 "cfg_ah 4905 "cfg_ahb";
4906 4906
4907 power-domains = <&rpm 4907 power-domains = <&rpmhpd RPMHPD_MX>;
4908 4908
4909 #clock-cells = <1>; 4909 #clock-cells = <1>;
4910 #phy-cells = <0>; 4910 #phy-cells = <0>;
4911 4911
4912 status = "disabled"; 4912 status = "disabled";
4913 }; 4913 };
4914 4914
4915 mdss_dp3_phy: phy@aec5a00 { 4915 mdss_dp3_phy: phy@aec5a00 {
4916 compatible = "qcom,x1 4916 compatible = "qcom,x1e80100-dp-phy";
4917 reg = <0 0x0aec5a00 0 4917 reg = <0 0x0aec5a00 0 0x19c>,
4918 <0 0x0aec5200 0 4918 <0 0x0aec5200 0 0xec>,
4919 <0 0x0aec5600 0 4919 <0 0x0aec5600 0 0xec>,
4920 <0 0x0aec5000 0 4920 <0 0x0aec5000 0 0x1c8>;
4921 4921
4922 clocks = <&dispcc DIS 4922 clocks = <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>,
4923 <&dispcc DIS 4923 <&dispcc DISP_CC_MDSS_AHB_CLK>;
4924 clock-names = "aux", 4924 clock-names = "aux",
4925 "cfg_ah 4925 "cfg_ahb";
4926 4926
4927 power-domains = <&rpm 4927 power-domains = <&rpmhpd RPMHPD_MX>;
4928 4928
4929 #clock-cells = <1>; 4929 #clock-cells = <1>;
4930 #phy-cells = <0>; 4930 #phy-cells = <0>;
4931 4931
4932 status = "disabled"; 4932 status = "disabled";
4933 }; 4933 };
4934 4934
4935 dispcc: clock-controller@af00 4935 dispcc: clock-controller@af00000 {
4936 compatible = "qcom,x1 4936 compatible = "qcom,x1e80100-dispcc";
4937 reg = <0 0x0af00000 0 4937 reg = <0 0x0af00000 0 0x20000>;
4938 clocks = <&bi_tcxo_di 4938 clocks = <&bi_tcxo_div2>,
4939 <&bi_tcxo_ao 4939 <&bi_tcxo_ao_div2>,
4940 <&gcc GCC_DI 4940 <&gcc GCC_DISP_AHB_CLK>,
4941 <&sleep_clk> 4941 <&sleep_clk>,
4942 <0>, /* dsi0 4942 <0>, /* dsi0 */
4943 <0>, 4943 <0>,
4944 <0>, /* dsi1 4944 <0>, /* dsi1 */
4945 <0>, 4945 <0>,
4946 <&usb_1_ss0_ 4946 <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp0 */
4947 <&usb_1_ss0_ 4947 <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
4948 <&usb_1_ss1_ 4948 <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp1 */
4949 <&usb_1_ss1_ 4949 <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
4950 <&usb_1_ss2_ 4950 <&usb_1_ss2_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp2 */
4951 <&usb_1_ss2_ 4951 <&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
4952 <&mdss_dp3_p 4952 <&mdss_dp3_phy 0>, /* dp3 */
4953 <&mdss_dp3_p 4953 <&mdss_dp3_phy 1>;
4954 power-domains = <&rpm 4954 power-domains = <&rpmhpd RPMHPD_MMCX>;
4955 required-opps = <&rpm 4955 required-opps = <&rpmhpd_opp_low_svs>;
4956 #clock-cells = <1>; 4956 #clock-cells = <1>;
4957 #reset-cells = <1>; 4957 #reset-cells = <1>;
4958 #power-domain-cells = 4958 #power-domain-cells = <1>;
4959 }; 4959 };
4960 4960
4961 pdc: interrupt-controller@b22 4961 pdc: interrupt-controller@b220000 {
4962 compatible = "qcom,x1 4962 compatible = "qcom,x1e80100-pdc", "qcom,pdc";
4963 reg = <0 0x0b220000 0 4963 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
4964 4964
4965 qcom,pdc-ranges = <0 4965 qcom,pdc-ranges = <0 480 42>, <42 251 5>,
4966 <47 4966 <47 522 52>, <99 609 32>,
4967 <13 4967 <131 717 12>, <143 816 19>;
4968 #interrupt-cells = <2 4968 #interrupt-cells = <2>;
4969 interrupt-parent = <& 4969 interrupt-parent = <&intc>;
4970 interrupt-controller; 4970 interrupt-controller;
4971 }; 4971 };
4972 4972
4973 aoss_qmp: power-management@c3 4973 aoss_qmp: power-management@c300000 {
4974 compatible = "qcom,x1 4974 compatible = "qcom,x1e80100-aoss-qmp", "qcom,aoss-qmp";
4975 reg = <0 0x0c300000 0 4975 reg = <0 0x0c300000 0 0x400>;
4976 interrupt-parent = <& 4976 interrupt-parent = <&ipcc>;
4977 interrupts-extended = 4977 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
4978 4978 IRQ_TYPE_EDGE_RISING>;
4979 mboxes = <&ipcc IPCC_ 4979 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
4980 4980
4981 #clock-cells = <0>; 4981 #clock-cells = <0>;
4982 }; 4982 };
4983 4983
4984 sram@c3f0000 { 4984 sram@c3f0000 {
4985 compatible = "qcom,rp 4985 compatible = "qcom,rpmh-stats";
4986 reg = <0 0x0c3f0000 0 4986 reg = <0 0x0c3f0000 0 0x400>;
4987 }; 4987 };
4988 4988
4989 spmi: arbiter@c400000 { 4989 spmi: arbiter@c400000 {
4990 compatible = "qcom,x1 4990 compatible = "qcom,x1e80100-spmi-pmic-arb";
4991 reg = <0 0x0c400000 0 4991 reg = <0 0x0c400000 0 0x3000>,
4992 <0 0x0c500000 0 4992 <0 0x0c500000 0 0x400000>,
4993 <0 0x0c440000 0 4993 <0 0x0c440000 0 0x80000>;
4994 reg-names = "core", " 4994 reg-names = "core", "chnls", "obsrvr";
4995 4995
4996 qcom,ee = <0>; 4996 qcom,ee = <0>;
4997 qcom,channel = <0>; 4997 qcom,channel = <0>;
4998 4998
4999 #address-cells = <2>; 4999 #address-cells = <2>;
5000 #size-cells = <2>; 5000 #size-cells = <2>;
5001 ranges; 5001 ranges;
5002 5002
5003 spmi_bus0: spmi@c42d0 5003 spmi_bus0: spmi@c42d000 {
5004 reg = <0 0x0c 5004 reg = <0 0x0c42d000 0 0x4000>,
5005 <0 0x0c 5005 <0 0x0c4c0000 0 0x10000>;
5006 reg-names = " 5006 reg-names = "cnfg", "intr";
5007 5007
5008 interrupt-nam 5008 interrupt-names = "periph_irq";
5009 interrupts-ex 5009 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
5010 interrupt-con 5010 interrupt-controller;
5011 #interrupt-ce 5011 #interrupt-cells = <4>;
5012 5012
5013 #address-cell 5013 #address-cells = <2>;
5014 #size-cells = 5014 #size-cells = <0>;
5015 }; 5015 };
5016 5016
5017 spmi_bus1: spmi@c4320 5017 spmi_bus1: spmi@c432000 {
5018 reg = <0 0x0c 5018 reg = <0 0x0c432000 0 0x4000>,
5019 <0 0x0c 5019 <0 0x0c4d0000 0 0x10000>;
5020 reg-names = " 5020 reg-names = "cnfg", "intr";
5021 5021
5022 interrupt-nam 5022 interrupt-names = "periph_irq";
5023 interrupts-ex 5023 interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>;
5024 interrupt-con 5024 interrupt-controller;
5025 #interrupt-ce 5025 #interrupt-cells = <4>;
5026 5026
5027 #address-cell 5027 #address-cells = <2>;
5028 #size-cells = 5028 #size-cells = <0>;
5029 }; 5029 };
5030 }; 5030 };
5031 5031
5032 tlmm: pinctrl@f100000 { 5032 tlmm: pinctrl@f100000 {
5033 compatible = "qcom,x1 5033 compatible = "qcom,x1e80100-tlmm";
5034 reg = <0 0x0f100000 0 5034 reg = <0 0x0f100000 0 0xf00000>;
5035 5035
5036 interrupts = <GIC_SPI 5036 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
5037 5037
5038 gpio-controller; 5038 gpio-controller;
5039 #gpio-cells = <2>; 5039 #gpio-cells = <2>;
5040 5040
5041 interrupt-controller; 5041 interrupt-controller;
5042 #interrupt-cells = <2 5042 #interrupt-cells = <2>;
5043 5043
5044 gpio-ranges = <&tlmm 5044 gpio-ranges = <&tlmm 0 0 239>;
5045 wakeup-parent = <&pdc 5045 wakeup-parent = <&pdc>;
5046 5046
5047 qup_i2c0_data_clk: qu 5047 qup_i2c0_data_clk: qup-i2c0-data-clk-state {
5048 /* SDA, SCL * 5048 /* SDA, SCL */
5049 pins = "gpio0 5049 pins = "gpio0", "gpio1";
5050 function = "q 5050 function = "qup0_se0";
5051 drive-strengt 5051 drive-strength = <2>;
5052 bias-pull-up 5052 bias-pull-up = <2200>;
5053 }; 5053 };
5054 5054
5055 qup_i2c1_data_clk: qu 5055 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
5056 /* SDA, SCL * 5056 /* SDA, SCL */
5057 pins = "gpio4 5057 pins = "gpio4", "gpio5";
5058 function = "q 5058 function = "qup0_se1";
5059 drive-strengt 5059 drive-strength = <2>;
5060 bias-pull-up 5060 bias-pull-up = <2200>;
5061 }; 5061 };
5062 5062
5063 qup_i2c2_data_clk: qu 5063 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
5064 /* SDA, SCL * 5064 /* SDA, SCL */
5065 pins = "gpio8 5065 pins = "gpio8", "gpio9";
5066 function = "q 5066 function = "qup0_se2";
5067 drive-strengt 5067 drive-strength = <2>;
5068 bias-pull-up 5068 bias-pull-up = <2200>;
5069 }; 5069 };
5070 5070
5071 qup_i2c3_data_clk: qu 5071 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
5072 /* SDA, SCL * 5072 /* SDA, SCL */
5073 pins = "gpio1 5073 pins = "gpio12", "gpio13";
5074 function = "q 5074 function = "qup0_se3";
5075 drive-strengt 5075 drive-strength = <2>;
5076 bias-pull-up 5076 bias-pull-up = <2200>;
5077 }; 5077 };
5078 5078
5079 qup_i2c4_data_clk: qu 5079 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
5080 /* SDA, SCL * 5080 /* SDA, SCL */
5081 pins = "gpio1 5081 pins = "gpio16", "gpio17";
5082 function = "q 5082 function = "qup0_se4";
5083 drive-strengt 5083 drive-strength = <2>;
5084 bias-pull-up 5084 bias-pull-up = <2200>;
5085 }; 5085 };
5086 5086
5087 qup_i2c5_data_clk: qu 5087 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
5088 /* SDA, SCL * 5088 /* SDA, SCL */
5089 pins = "gpio2 5089 pins = "gpio20", "gpio21";
5090 function = "q 5090 function = "qup0_se5";
5091 drive-strengt 5091 drive-strength = <2>;
5092 bias-pull-up 5092 bias-pull-up = <2200>;
5093 }; 5093 };
5094 5094
5095 qup_i2c6_data_clk: qu 5095 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
5096 /* SDA, SCL * 5096 /* SDA, SCL */
5097 pins = "gpio2 5097 pins = "gpio24", "gpio25";
5098 function = "q 5098 function = "qup0_se6";
5099 drive-strengt 5099 drive-strength = <2>;
5100 bias-pull-up 5100 bias-pull-up = <2200>;
5101 }; 5101 };
5102 5102
5103 qup_i2c7_data_clk: qu 5103 qup_i2c7_data_clk: qup-i2c7-data-clk-state {
5104 /* SDA, SCL * 5104 /* SDA, SCL */
5105 pins = "gpio1 5105 pins = "gpio14", "gpio15";
5106 function = "q 5106 function = "qup0_se7";
5107 drive-strengt 5107 drive-strength = <2>;
5108 bias-pull-up 5108 bias-pull-up = <2200>;
5109 }; 5109 };
5110 5110
5111 qup_i2c8_data_clk: qu 5111 qup_i2c8_data_clk: qup-i2c8-data-clk-state {
5112 /* SDA, SCL * 5112 /* SDA, SCL */
5113 pins = "gpio3 5113 pins = "gpio32", "gpio33";
5114 function = "q 5114 function = "qup1_se0";
5115 drive-strengt 5115 drive-strength = <2>;
5116 bias-pull-up 5116 bias-pull-up = <2200>;
5117 }; 5117 };
5118 5118
5119 qup_i2c9_data_clk: qu 5119 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
5120 /* SDA, SCL * 5120 /* SDA, SCL */
5121 pins = "gpio3 5121 pins = "gpio36", "gpio37";
5122 function = "q 5122 function = "qup1_se1";
5123 drive-strengt 5123 drive-strength = <2>;
5124 bias-pull-up 5124 bias-pull-up = <2200>;
5125 }; 5125 };
5126 5126
5127 qup_i2c10_data_clk: q 5127 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
5128 /* SDA, SCL * 5128 /* SDA, SCL */
5129 pins = "gpio4 5129 pins = "gpio40", "gpio41";
5130 function = "q 5130 function = "qup1_se2";
5131 drive-strengt 5131 drive-strength = <2>;
5132 bias-pull-up 5132 bias-pull-up = <2200>;
5133 }; 5133 };
5134 5134
5135 qup_i2c11_data_clk: q 5135 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
5136 /* SDA, SCL * 5136 /* SDA, SCL */
5137 pins = "gpio4 5137 pins = "gpio44", "gpio45";
5138 function = "q 5138 function = "qup1_se3";
5139 drive-strengt 5139 drive-strength = <2>;
5140 bias-pull-up 5140 bias-pull-up = <2200>;
5141 }; 5141 };
5142 5142
5143 qup_i2c12_data_clk: q 5143 qup_i2c12_data_clk: qup-i2c12-data-clk-state {
5144 /* SDA, SCL * 5144 /* SDA, SCL */
5145 pins = "gpio4 5145 pins = "gpio48", "gpio49";
5146 function = "q 5146 function = "qup1_se4";
5147 drive-strengt 5147 drive-strength = <2>;
5148 bias-pull-up 5148 bias-pull-up = <2200>;
5149 }; 5149 };
5150 5150
5151 qup_i2c13_data_clk: q 5151 qup_i2c13_data_clk: qup-i2c13-data-clk-state {
5152 /* SDA, SCL * 5152 /* SDA, SCL */
5153 pins = "gpio5 5153 pins = "gpio52", "gpio53";
5154 function = "q 5154 function = "qup1_se5";
5155 drive-strengt 5155 drive-strength = <2>;
5156 bias-pull-up 5156 bias-pull-up = <2200>;
5157 }; 5157 };
5158 5158
5159 qup_i2c14_data_clk: q 5159 qup_i2c14_data_clk: qup-i2c14-data-clk-state {
5160 /* SDA, SCL * 5160 /* SDA, SCL */
5161 pins = "gpio5 5161 pins = "gpio56", "gpio57";
5162 function = "q 5162 function = "qup1_se6";
5163 drive-strengt 5163 drive-strength = <2>;
5164 bias-pull-up 5164 bias-pull-up = <2200>;
5165 }; 5165 };
5166 5166
5167 qup_i2c15_data_clk: q 5167 qup_i2c15_data_clk: qup-i2c15-data-clk-state {
5168 /* SDA, SCL * 5168 /* SDA, SCL */
5169 pins = "gpio5 5169 pins = "gpio54", "gpio55";
5170 function = "q 5170 function = "qup1_se7";
5171 drive-strengt 5171 drive-strength = <2>;
5172 bias-pull-up 5172 bias-pull-up = <2200>;
5173 }; 5173 };
5174 5174
5175 qup_i2c16_data_clk: q 5175 qup_i2c16_data_clk: qup-i2c16-data-clk-state {
5176 /* SDA, SCL * 5176 /* SDA, SCL */
5177 pins = "gpio6 5177 pins = "gpio64", "gpio65";
5178 function = "q 5178 function = "qup2_se0";
5179 drive-strengt 5179 drive-strength = <2>;
5180 bias-pull-up 5180 bias-pull-up = <2200>;
5181 }; 5181 };
5182 5182
5183 qup_i2c17_data_clk: q 5183 qup_i2c17_data_clk: qup-i2c17-data-clk-state {
5184 /* SDA, SCL * 5184 /* SDA, SCL */
5185 pins = "gpio6 5185 pins = "gpio68", "gpio69";
5186 function = "q 5186 function = "qup2_se1";
5187 drive-strengt 5187 drive-strength = <2>;
5188 bias-pull-up 5188 bias-pull-up = <2200>;
5189 }; 5189 };
5190 5190
5191 qup_i2c18_data_clk: q 5191 qup_i2c18_data_clk: qup-i2c18-data-clk-state {
5192 /* SDA, SCL * 5192 /* SDA, SCL */
5193 pins = "gpio7 5193 pins = "gpio72", "gpio73";
5194 function = "q 5194 function = "qup2_se2";
5195 drive-strengt 5195 drive-strength = <2>;
5196 bias-pull-up 5196 bias-pull-up = <2200>;
5197 }; 5197 };
5198 5198
5199 qup_i2c19_data_clk: q 5199 qup_i2c19_data_clk: qup-i2c19-data-clk-state {
5200 /* SDA, SCL * 5200 /* SDA, SCL */
5201 pins = "gpio7 5201 pins = "gpio76", "gpio77";
5202 function = "q 5202 function = "qup2_se3";
5203 drive-strengt 5203 drive-strength = <2>;
5204 bias-pull-up 5204 bias-pull-up = <2200>;
5205 }; 5205 };
5206 5206
5207 qup_i2c20_data_clk: q 5207 qup_i2c20_data_clk: qup-i2c20-data-clk-state {
5208 /* SDA, SCL * 5208 /* SDA, SCL */
5209 pins = "gpio8 5209 pins = "gpio80", "gpio81";
5210 function = "q 5210 function = "qup2_se4";
5211 drive-strengt 5211 drive-strength = <2>;
5212 bias-pull-up 5212 bias-pull-up = <2200>;
5213 }; 5213 };
5214 5214
5215 qup_i2c21_data_clk: q 5215 qup_i2c21_data_clk: qup-i2c21-data-clk-state {
5216 /* SDA, SCL * 5216 /* SDA, SCL */
5217 pins = "gpio8 5217 pins = "gpio84", "gpio85";
5218 function = "q 5218 function = "qup2_se5";
5219 drive-strengt 5219 drive-strength = <2>;
5220 bias-pull-up 5220 bias-pull-up = <2200>;
5221 }; 5221 };
5222 5222
5223 qup_i2c22_data_clk: q 5223 qup_i2c22_data_clk: qup-i2c22-data-clk-state {
5224 /* SDA, SCL * 5224 /* SDA, SCL */
5225 pins = "gpio8 5225 pins = "gpio88", "gpio89";
5226 function = "q 5226 function = "qup2_se6";
5227 drive-strengt 5227 drive-strength = <2>;
5228 bias-pull-up 5228 bias-pull-up = <2200>;
5229 }; 5229 };
5230 5230
5231 qup_i2c23_data_clk: q 5231 qup_i2c23_data_clk: qup-i2c23-data-clk-state {
5232 /* SDA, SCL * 5232 /* SDA, SCL */
5233 pins = "gpio8 5233 pins = "gpio86", "gpio87";
5234 function = "q 5234 function = "qup2_se7";
5235 drive-strengt 5235 drive-strength = <2>;
5236 bias-pull-up 5236 bias-pull-up = <2200>;
5237 }; 5237 };
5238 5238
5239 qup_spi0_cs: qup-spi0 5239 qup_spi0_cs: qup-spi0-cs-state {
5240 pins = "gpio3 5240 pins = "gpio3";
5241 function = "q 5241 function = "qup0_se0";
5242 drive-strengt 5242 drive-strength = <6>;
5243 bias-disable; 5243 bias-disable;
5244 }; 5244 };
5245 5245
5246 qup_spi0_data_clk: qu 5246 qup_spi0_data_clk: qup-spi0-data-clk-state {
5247 /* MISO, MOSI 5247 /* MISO, MOSI, CLK */
5248 pins = "gpio0 5248 pins = "gpio0", "gpio1", "gpio2";
5249 function = "q 5249 function = "qup0_se0";
5250 drive-strengt 5250 drive-strength = <6>;
5251 bias-disable; 5251 bias-disable;
5252 }; 5252 };
5253 5253
5254 qup_spi1_cs: qup-spi1 5254 qup_spi1_cs: qup-spi1-cs-state {
5255 pins = "gpio7 5255 pins = "gpio7";
5256 function = "q 5256 function = "qup0_se1";
5257 drive-strengt 5257 drive-strength = <6>;
5258 bias-disable; 5258 bias-disable;
5259 }; 5259 };
5260 5260
5261 qup_spi1_data_clk: qu 5261 qup_spi1_data_clk: qup-spi1-data-clk-state {
5262 /* MISO, MOSI 5262 /* MISO, MOSI, CLK */
5263 pins = "gpio4 5263 pins = "gpio4", "gpio5", "gpio6";
5264 function = "q 5264 function = "qup0_se1";
5265 drive-strengt 5265 drive-strength = <6>;
5266 bias-disable; 5266 bias-disable;
5267 }; 5267 };
5268 5268
5269 qup_spi2_cs: qup-spi2 5269 qup_spi2_cs: qup-spi2-cs-state {
5270 pins = "gpio1 5270 pins = "gpio11";
5271 function = "q 5271 function = "qup0_se2";
5272 drive-strengt 5272 drive-strength = <6>;
5273 bias-disable; 5273 bias-disable;
5274 }; 5274 };
5275 5275
5276 qup_spi2_data_clk: qu 5276 qup_spi2_data_clk: qup-spi2-data-clk-state {
5277 /* MISO, MOSI 5277 /* MISO, MOSI, CLK */
5278 pins = "gpio8 5278 pins = "gpio8", "gpio9", "gpio10";
5279 function = "q 5279 function = "qup0_se2";
5280 drive-strengt 5280 drive-strength = <6>;
5281 bias-disable; 5281 bias-disable;
5282 }; 5282 };
5283 5283
5284 qup_spi3_cs: qup-spi3 5284 qup_spi3_cs: qup-spi3-cs-state {
5285 pins = "gpio1 5285 pins = "gpio15";
5286 function = "q 5286 function = "qup0_se3";
5287 drive-strengt 5287 drive-strength = <6>;
5288 bias-disable; 5288 bias-disable;
5289 }; 5289 };
5290 5290
5291 qup_spi3_data_clk: qu 5291 qup_spi3_data_clk: qup-spi3-data-clk-state {
5292 /* MISO, MOSI 5292 /* MISO, MOSI, CLK */
5293 pins = "gpio1 5293 pins = "gpio12", "gpio13", "gpio14";
5294 function = "q 5294 function = "qup0_se3";
5295 drive-strengt 5295 drive-strength = <6>;
5296 bias-disable; 5296 bias-disable;
5297 }; 5297 };
5298 5298
5299 qup_spi4_cs: qup-spi4 5299 qup_spi4_cs: qup-spi4-cs-state {
5300 pins = "gpio1 5300 pins = "gpio19";
5301 function = "q 5301 function = "qup0_se4";
5302 drive-strengt 5302 drive-strength = <6>;
5303 bias-disable; 5303 bias-disable;
5304 }; 5304 };
5305 5305
5306 qup_spi4_data_clk: qu 5306 qup_spi4_data_clk: qup-spi4-data-clk-state {
5307 /* MISO, MOSI 5307 /* MISO, MOSI, CLK */
5308 pins = "gpio1 5308 pins = "gpio16", "gpio17", "gpio18";
5309 function = "q 5309 function = "qup0_se4";
5310 drive-strengt 5310 drive-strength = <6>;
5311 bias-disable; 5311 bias-disable;
5312 }; 5312 };
5313 5313
5314 qup_spi5_cs: qup-spi5 5314 qup_spi5_cs: qup-spi5-cs-state {
5315 pins = "gpio2 5315 pins = "gpio23";
5316 function = "q 5316 function = "qup0_se5";
5317 drive-strengt 5317 drive-strength = <6>;
5318 bias-disable; 5318 bias-disable;
5319 }; 5319 };
5320 5320
5321 qup_spi5_data_clk: qu 5321 qup_spi5_data_clk: qup-spi5-data-clk-state {
5322 /* MISO, MOSI 5322 /* MISO, MOSI, CLK */
5323 pins = "gpio2 5323 pins = "gpio20", "gpio21", "gpio22";
5324 function = "q 5324 function = "qup0_se5";
5325 drive-strengt 5325 drive-strength = <6>;
5326 bias-disable; 5326 bias-disable;
5327 }; 5327 };
5328 5328
5329 qup_spi6_cs: qup-spi6 5329 qup_spi6_cs: qup-spi6-cs-state {
5330 pins = "gpio2 5330 pins = "gpio27";
5331 function = "q 5331 function = "qup0_se6";
5332 drive-strengt 5332 drive-strength = <6>;
5333 bias-disable; 5333 bias-disable;
5334 }; 5334 };
5335 5335
5336 qup_spi6_data_clk: qu 5336 qup_spi6_data_clk: qup-spi6-data-clk-state {
5337 /* MISO, MOSI 5337 /* MISO, MOSI, CLK */
5338 pins = "gpio2 5338 pins = "gpio24", "gpio25", "gpio26";
5339 function = "q 5339 function = "qup0_se6";
5340 drive-strengt 5340 drive-strength = <6>;
5341 bias-disable; 5341 bias-disable;
5342 }; 5342 };
5343 5343
5344 qup_spi7_cs: qup-spi7 5344 qup_spi7_cs: qup-spi7-cs-state {
5345 pins = "gpio1 5345 pins = "gpio13";
5346 function = "q 5346 function = "qup0_se7";
5347 drive-strengt 5347 drive-strength = <6>;
5348 bias-disable; 5348 bias-disable;
5349 }; 5349 };
5350 5350
5351 qup_spi7_data_clk: qu 5351 qup_spi7_data_clk: qup-spi7-data-clk-state {
5352 /* MISO, MOSI 5352 /* MISO, MOSI, CLK */
5353 pins = "gpio1 5353 pins = "gpio14", "gpio15", "gpio12";
5354 function = "q 5354 function = "qup0_se7";
5355 drive-strengt 5355 drive-strength = <6>;
5356 bias-disable; 5356 bias-disable;
5357 }; 5357 };
5358 5358
5359 qup_spi8_cs: qup-spi8 5359 qup_spi8_cs: qup-spi8-cs-state {
5360 pins = "gpio3 5360 pins = "gpio35";
5361 function = "q 5361 function = "qup1_se0";
5362 drive-strengt 5362 drive-strength = <6>;
5363 bias-disable; 5363 bias-disable;
5364 }; 5364 };
5365 5365
5366 qup_spi8_data_clk: qu 5366 qup_spi8_data_clk: qup-spi8-data-clk-state {
5367 /* MISO, MOSI 5367 /* MISO, MOSI, CLK */
5368 pins = "gpio3 5368 pins = "gpio32", "gpio33", "gpio34";
5369 function = "q 5369 function = "qup1_se0";
5370 drive-strengt 5370 drive-strength = <6>;
5371 bias-disable; 5371 bias-disable;
5372 }; 5372 };
5373 5373
5374 qup_spi9_cs: qup-spi9 5374 qup_spi9_cs: qup-spi9-cs-state {
5375 pins = "gpio3 5375 pins = "gpio39";
5376 function = "q 5376 function = "qup1_se1";
5377 drive-strengt 5377 drive-strength = <6>;
5378 bias-disable; 5378 bias-disable;
5379 }; 5379 };
5380 5380
5381 qup_spi9_data_clk: qu 5381 qup_spi9_data_clk: qup-spi9-data-clk-state {
5382 /* MISO, MOSI 5382 /* MISO, MOSI, CLK */
5383 pins = "gpio3 5383 pins = "gpio36", "gpio37", "gpio38";
5384 function = "q 5384 function = "qup1_se1";
5385 drive-strengt 5385 drive-strength = <6>;
5386 bias-disable; 5386 bias-disable;
5387 }; 5387 };
5388 5388
5389 qup_spi10_cs: qup-spi 5389 qup_spi10_cs: qup-spi10-cs-state {
5390 pins = "gpio4 5390 pins = "gpio43";
5391 function = "q 5391 function = "qup1_se2";
5392 drive-strengt 5392 drive-strength = <6>;
5393 bias-disable; 5393 bias-disable;
5394 }; 5394 };
5395 5395
5396 qup_spi10_data_clk: q 5396 qup_spi10_data_clk: qup-spi10-data-clk-state {
5397 /* MISO, MOSI 5397 /* MISO, MOSI, CLK */
5398 pins = "gpio4 5398 pins = "gpio40", "gpio41", "gpio42";
5399 function = "q 5399 function = "qup1_se2";
5400 drive-strengt 5400 drive-strength = <6>;
5401 bias-disable; 5401 bias-disable;
5402 }; 5402 };
5403 5403
5404 qup_spi11_cs: qup-spi 5404 qup_spi11_cs: qup-spi11-cs-state {
5405 pins = "gpio4 5405 pins = "gpio47";
5406 function = "q 5406 function = "qup1_se3";
5407 drive-strengt 5407 drive-strength = <6>;
5408 bias-disable; 5408 bias-disable;
5409 }; 5409 };
5410 5410
5411 qup_spi11_data_clk: q 5411 qup_spi11_data_clk: qup-spi11-data-clk-state {
5412 /* MISO, MOSI 5412 /* MISO, MOSI, CLK */
5413 pins = "gpio4 5413 pins = "gpio44", "gpio45", "gpio46";
5414 function = "q 5414 function = "qup1_se3";
5415 drive-strengt 5415 drive-strength = <6>;
5416 bias-disable; 5416 bias-disable;
5417 }; 5417 };
5418 5418
5419 qup_spi12_cs: qup-spi 5419 qup_spi12_cs: qup-spi12-cs-state {
5420 pins = "gpio5 5420 pins = "gpio51";
5421 function = "q 5421 function = "qup1_se4";
5422 drive-strengt 5422 drive-strength = <6>;
5423 bias-disable; 5423 bias-disable;
5424 }; 5424 };
5425 5425
5426 qup_spi12_data_clk: q 5426 qup_spi12_data_clk: qup-spi12-data-clk-state {
5427 /* MISO, MOSI 5427 /* MISO, MOSI, CLK */
5428 pins = "gpio4 5428 pins = "gpio48", "gpio49", "gpio50";
5429 function = "q 5429 function = "qup1_se4";
5430 drive-strengt 5430 drive-strength = <6>;
5431 bias-disable; 5431 bias-disable;
5432 }; 5432 };
5433 5433
5434 qup_spi13_cs: qup-spi 5434 qup_spi13_cs: qup-spi13-cs-state {
5435 pins = "gpio5 5435 pins = "gpio55";
5436 function = "q 5436 function = "qup1_se5";
5437 drive-strengt 5437 drive-strength = <6>;
5438 bias-disable; 5438 bias-disable;
5439 }; 5439 };
5440 5440
5441 qup_spi13_data_clk: q 5441 qup_spi13_data_clk: qup-spi13-data-clk-state {
5442 /* MISO, MOSI 5442 /* MISO, MOSI, CLK */
5443 pins = "gpio5 5443 pins = "gpio52", "gpio53", "gpio54";
5444 function = "q 5444 function = "qup1_se5";
5445 drive-strengt 5445 drive-strength = <6>;
5446 bias-disable; 5446 bias-disable;
5447 }; 5447 };
5448 5448
5449 qup_spi14_cs: qup-spi 5449 qup_spi14_cs: qup-spi14-cs-state {
5450 pins = "gpio5 5450 pins = "gpio59";
5451 function = "q 5451 function = "qup1_se6";
5452 drive-strengt 5452 drive-strength = <6>;
5453 bias-disable; 5453 bias-disable;
5454 }; 5454 };
5455 5455
5456 qup_spi14_data_clk: q 5456 qup_spi14_data_clk: qup-spi14-data-clk-state {
5457 /* MISO, MOSI 5457 /* MISO, MOSI, CLK */
5458 pins = "gpio5 5458 pins = "gpio56", "gpio57", "gpio58";
5459 function = "q 5459 function = "qup1_se6";
5460 drive-strengt 5460 drive-strength = <6>;
5461 bias-disable; 5461 bias-disable;
5462 }; 5462 };
5463 5463
5464 qup_spi15_cs: qup-spi 5464 qup_spi15_cs: qup-spi15-cs-state {
5465 pins = "gpio5 5465 pins = "gpio53";
5466 function = "q 5466 function = "qup1_se7";
5467 drive-strengt 5467 drive-strength = <6>;
5468 bias-disable; 5468 bias-disable;
5469 }; 5469 };
5470 5470
5471 qup_spi15_data_clk: q 5471 qup_spi15_data_clk: qup-spi15-data-clk-state {
5472 /* MISO, MOSI 5472 /* MISO, MOSI, CLK */
5473 pins = "gpio5 5473 pins = "gpio54", "gpio55", "gpio52";
5474 function = "q 5474 function = "qup1_se7";
5475 drive-strengt 5475 drive-strength = <6>;
5476 bias-disable; 5476 bias-disable;
5477 }; 5477 };
5478 5478
5479 qup_spi16_cs: qup-spi 5479 qup_spi16_cs: qup-spi16-cs-state {
5480 pins = "gpio6 5480 pins = "gpio67";
5481 function = "q 5481 function = "qup2_se0";
5482 drive-strengt 5482 drive-strength = <6>;
5483 bias-disable; 5483 bias-disable;
5484 }; 5484 };
5485 5485
5486 qup_spi16_data_clk: q 5486 qup_spi16_data_clk: qup-spi16-data-clk-state {
5487 /* MISO, MOSI 5487 /* MISO, MOSI, CLK */
5488 pins = "gpio6 5488 pins = "gpio64", "gpio65", "gpio66";
5489 function = "q 5489 function = "qup2_se0";
5490 drive-strengt 5490 drive-strength = <6>;
5491 bias-disable; 5491 bias-disable;
5492 }; 5492 };
5493 5493
5494 qup_spi17_cs: qup-spi 5494 qup_spi17_cs: qup-spi17-cs-state {
5495 pins = "gpio7 5495 pins = "gpio71";
5496 function = "q 5496 function = "qup2_se1";
5497 drive-strengt 5497 drive-strength = <6>;
5498 bias-disable; 5498 bias-disable;
5499 }; 5499 };
5500 5500
5501 qup_spi17_data_clk: q 5501 qup_spi17_data_clk: qup-spi17-data-clk-state {
5502 /* MISO, MOSI 5502 /* MISO, MOSI, CLK */
5503 pins = "gpio6 5503 pins = "gpio68", "gpio69", "gpio70";
5504 function = "q 5504 function = "qup2_se1";
5505 drive-strengt 5505 drive-strength = <6>;
5506 bias-disable; 5506 bias-disable;
5507 }; 5507 };
5508 5508
5509 qup_spi18_cs: qup-spi 5509 qup_spi18_cs: qup-spi18-cs-state {
5510 pins = "gpio7 5510 pins = "gpio75";
5511 function = "q 5511 function = "qup2_se2";
5512 drive-strengt 5512 drive-strength = <6>;
5513 bias-disable; 5513 bias-disable;
5514 }; 5514 };
5515 5515
5516 qup_spi18_data_clk: q 5516 qup_spi18_data_clk: qup-spi18-data-clk-state {
5517 /* MISO, MOSI 5517 /* MISO, MOSI, CLK */
5518 pins = "gpio7 5518 pins = "gpio72", "gpio73", "gpio74";
5519 function = "q 5519 function = "qup2_se2";
5520 drive-strengt 5520 drive-strength = <6>;
5521 bias-disable; 5521 bias-disable;
5522 }; 5522 };
5523 5523
5524 qup_spi19_cs: qup-spi 5524 qup_spi19_cs: qup-spi19-cs-state {
5525 pins = "gpio7 5525 pins = "gpio79";
5526 function = "q 5526 function = "qup2_se3";
5527 drive-strengt 5527 drive-strength = <6>;
5528 bias-disable; 5528 bias-disable;
5529 }; 5529 };
5530 5530
5531 qup_spi19_data_clk: q 5531 qup_spi19_data_clk: qup-spi19-data-clk-state {
5532 /* MISO, MOSI 5532 /* MISO, MOSI, CLK */
5533 pins = "gpio7 5533 pins = "gpio76", "gpio77", "gpio78";
5534 function = "q 5534 function = "qup2_se3";
5535 drive-strengt 5535 drive-strength = <6>;
5536 bias-disable; 5536 bias-disable;
5537 }; 5537 };
5538 5538
5539 qup_spi20_cs: qup-spi 5539 qup_spi20_cs: qup-spi20-cs-state {
5540 pins = "gpio8 5540 pins = "gpio83";
5541 function = "q 5541 function = "qup2_se4";
5542 drive-strengt 5542 drive-strength = <6>;
5543 bias-disable; 5543 bias-disable;
5544 }; 5544 };
5545 5545
5546 qup_spi20_data_clk: q 5546 qup_spi20_data_clk: qup-spi20-data-clk-state {
5547 /* MISO, MOSI 5547 /* MISO, MOSI, CLK */
5548 pins = "gpio8 5548 pins = "gpio80", "gpio81", "gpio82";
5549 function = "q 5549 function = "qup2_se4";
5550 drive-strengt 5550 drive-strength = <6>;
5551 bias-disable; 5551 bias-disable;
5552 }; 5552 };
5553 5553
5554 qup_spi21_cs: qup-spi 5554 qup_spi21_cs: qup-spi21-cs-state {
5555 pins = "gpio8 5555 pins = "gpio87";
5556 function = "q 5556 function = "qup2_se5";
5557 drive-strengt 5557 drive-strength = <6>;
5558 bias-disable; 5558 bias-disable;
5559 }; 5559 };
5560 5560
5561 qup_spi21_data_clk: q 5561 qup_spi21_data_clk: qup-spi21-data-clk-state {
5562 /* MISO, MOSI 5562 /* MISO, MOSI, CLK */
5563 pins = "gpio8 5563 pins = "gpio84", "gpio85", "gpio86";
5564 function = "q 5564 function = "qup2_se5";
5565 drive-strengt 5565 drive-strength = <6>;
5566 bias-disable; 5566 bias-disable;
5567 }; 5567 };
5568 5568
5569 qup_spi22_cs: qup-spi 5569 qup_spi22_cs: qup-spi22-cs-state {
5570 pins = "gpio9 5570 pins = "gpio91";
5571 function = "q 5571 function = "qup2_se6";
5572 drive-strengt 5572 drive-strength = <6>;
5573 bias-disable; 5573 bias-disable;
5574 }; 5574 };
5575 5575
5576 qup_spi22_data_clk: q 5576 qup_spi22_data_clk: qup-spi22-data-clk-state {
5577 /* MISO, MOSI 5577 /* MISO, MOSI, CLK */
5578 pins = "gpio8 5578 pins = "gpio88", "gpio89", "gpio90";
5579 function = "q 5579 function = "qup2_se6";
5580 drive-strengt 5580 drive-strength = <6>;
5581 bias-disable; 5581 bias-disable;
5582 }; 5582 };
5583 5583
5584 qup_spi23_cs: qup-spi 5584 qup_spi23_cs: qup-spi23-cs-state {
5585 pins = "gpio8 5585 pins = "gpio85";
5586 function = "q 5586 function = "qup2_se7";
5587 drive-strengt 5587 drive-strength = <6>;
5588 bias-disable; 5588 bias-disable;
5589 }; 5589 };
5590 5590
5591 qup_spi23_data_clk: q 5591 qup_spi23_data_clk: qup-spi23-data-clk-state {
5592 /* MISO, MOSI 5592 /* MISO, MOSI, CLK */
5593 pins = "gpio8 5593 pins = "gpio86", "gpio87", "gpio84";
5594 function = "q 5594 function = "qup2_se7";
5595 drive-strengt 5595 drive-strength = <6>;
5596 bias-disable; 5596 bias-disable;
5597 }; 5597 };
5598 5598
5599 qup_uart2_default: qu 5599 qup_uart2_default: qup-uart2-default-state {
5600 cts-pins { 5600 cts-pins {
5601 pins 5601 pins = "gpio8";
5602 funct 5602 function = "qup0_se2";
5603 drive 5603 drive-strength = <2>;
5604 bias- 5604 bias-disable;
5605 }; 5605 };
5606 5606
5607 rts-pins { 5607 rts-pins {
5608 pins 5608 pins = "gpio9";
5609 funct 5609 function = "qup0_se2";
5610 drive 5610 drive-strength = <2>;
5611 bias- 5611 bias-disable;
5612 }; 5612 };
5613 5613
5614 tx-pins { 5614 tx-pins {
5615 pins 5615 pins = "gpio10";
5616 funct 5616 function = "qup0_se2";
5617 drive 5617 drive-strength = <2>;
5618 bias- 5618 bias-disable;
5619 }; 5619 };
5620 5620
5621 rx-pins { 5621 rx-pins {
5622 pins 5622 pins = "gpio11";
5623 funct 5623 function = "qup0_se2";
5624 drive 5624 drive-strength = <2>;
5625 bias- 5625 bias-disable;
5626 }; 5626 };
5627 }; 5627 };
5628 5628
5629 qup_uart21_default: q 5629 qup_uart21_default: qup-uart21-default-state {
5630 tx-pins { 5630 tx-pins {
5631 pins 5631 pins = "gpio86";
5632 funct 5632 function = "qup2_se5";
5633 drive 5633 drive-strength = <2>;
5634 bias- 5634 bias-disable;
5635 }; 5635 };
5636 5636
5637 rx-pins { 5637 rx-pins {
5638 pins 5638 pins = "gpio87";
5639 funct 5639 function = "qup2_se5";
5640 drive 5640 drive-strength = <2>;
5641 bias- 5641 bias-disable;
5642 }; 5642 };
5643 }; 5643 };
5644 }; 5644 };
5645 5645
5646 apps_smmu: iommu@15000000 { 5646 apps_smmu: iommu@15000000 {
5647 compatible = "qcom,x1 5647 compatible = "qcom,x1e80100-smmu-500", "qcom,smmu-500", "arm,mmu-500";
5648 reg = <0 0x15000000 0 5648 reg = <0 0x15000000 0 0x100000>;
5649 5649
5650 interrupts = <GIC_SPI 5650 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
5651 <GIC_SPI 5651 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
5652 <GIC_SPI 5652 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
5653 <GIC_SPI 5653 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
5654 <GIC_SPI 5654 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
5655 <GIC_SPI 5655 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
5656 <GIC_SPI 5656 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
5657 <GIC_SPI 5657 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
5658 <GIC_SPI 5658 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
5659 <GIC_SPI 5659 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
5660 <GIC_SPI 5660 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
5661 <GIC_SPI 5661 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
5662 <GIC_SPI 5662 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
5663 <GIC_SPI 5663 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
5664 <GIC_SPI 5664 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
5665 <GIC_SPI 5665 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
5666 <GIC_SPI 5666 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
5667 <GIC_SPI 5667 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
5668 <GIC_SPI 5668 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
5669 <GIC_SPI 5669 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
5670 <GIC_SPI 5670 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
5671 <GIC_SPI 5671 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
5672 <GIC_SPI 5672 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
5673 <GIC_SPI 5673 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
5674 <GIC_SPI 5674 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
5675 <GIC_SPI 5675 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
5676 <GIC_SPI 5676 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
5677 <GIC_SPI 5677 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
5678 <GIC_SPI 5678 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
5679 <GIC_SPI 5679 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
5680 <GIC_SPI 5680 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
5681 <GIC_SPI 5681 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
5682 <GIC_SPI 5682 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
5683 <GIC_SPI 5683 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
5684 <GIC_SPI 5684 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
5685 <GIC_SPI 5685 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
5686 <GIC_SPI 5686 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
5687 <GIC_SPI 5687 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
5688 <GIC_SPI 5688 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
5689 <GIC_SPI 5689 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
5690 <GIC_SPI 5690 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
5691 <GIC_SPI 5691 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
5692 <GIC_SPI 5692 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
5693 <GIC_SPI 5693 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
5694 <GIC_SPI 5694 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
5695 <GIC_SPI 5695 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
5696 <GIC_SPI 5696 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
5697 <GIC_SPI 5697 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
5698 <GIC_SPI 5698 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
5699 <GIC_SPI 5699 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
5700 <GIC_SPI 5700 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
5701 <GIC_SPI 5701 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
5702 <GIC_SPI 5702 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
5703 <GIC_SPI 5703 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
5704 <GIC_SPI 5704 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
5705 <GIC_SPI 5705 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
5706 <GIC_SPI 5706 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
5707 <GIC_SPI 5707 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
5708 <GIC_SPI 5708 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
5709 <GIC_SPI 5709 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
5710 <GIC_SPI 5710 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
5711 <GIC_SPI 5711 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
5712 <GIC_SPI 5712 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
5713 <GIC_SPI 5713 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
5714 <GIC_SPI 5714 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
5715 <GIC_SPI 5715 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
5716 <GIC_SPI 5716 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
5717 <GIC_SPI 5717 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
5718 <GIC_SPI 5718 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
5719 <GIC_SPI 5719 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
5720 <GIC_SPI 5720 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
5721 <GIC_SPI 5721 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
5722 <GIC_SPI 5722 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
5723 <GIC_SPI 5723 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
5724 <GIC_SPI 5724 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
5725 <GIC_SPI 5725 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
5726 <GIC_SPI 5726 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
5727 <GIC_SPI 5727 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
5728 <GIC_SPI 5728 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
5729 <GIC_SPI 5729 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
5730 <GIC_SPI 5730 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
5731 <GIC_SPI 5731 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
5732 <GIC_SPI 5732 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
5733 <GIC_SPI 5733 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
5734 <GIC_SPI 5734 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
5735 <GIC_SPI 5735 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
5736 <GIC_SPI 5736 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
5737 <GIC_SPI 5737 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
5738 <GIC_SPI 5738 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
5739 <GIC_SPI 5739 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
5740 <GIC_SPI 5740 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
5741 <GIC_SPI 5741 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
5742 <GIC_SPI 5742 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
5743 <GIC_SPI 5743 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
5744 <GIC_SPI 5744 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
5745 <GIC_SPI 5745 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
5746 <GIC_SPI 5746 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>;
5747 5747
5748 #iommu-cells = <2>; 5748 #iommu-cells = <2>;
5749 #global-interrupts = 5749 #global-interrupts = <1>;
5750 }; 5750 };
5751 5751
5752 intc: interrupt-controller@17 5752 intc: interrupt-controller@17000000 {
5753 compatible = "arm,gic 5753 compatible = "arm,gic-v3";
5754 reg = <0 0x17000000 0 5754 reg = <0 0x17000000 0 0x10000>, /* GICD */
5755 <0 0x17080000 0 5755 <0 0x17080000 0 0x480000>; /* GICR * 12 */
5756 5756
5757 interrupts = <GIC_PPI 5757 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
5758 5758
5759 #interrupt-cells = <3 5759 #interrupt-cells = <3>;
5760 interrupt-controller; 5760 interrupt-controller;
5761 5761
5762 #redistributor-region 5762 #redistributor-regions = <1>;
5763 redistributor-stride 5763 redistributor-stride = <0x0 0x40000>;
5764 5764
5765 #address-cells = <2>; 5765 #address-cells = <2>;
5766 #size-cells = <2>; 5766 #size-cells = <2>;
5767 ranges; 5767 ranges;
5768 5768
5769 gic_its: msi-controll 5769 gic_its: msi-controller@17040000 {
5770 compatible = 5770 compatible = "arm,gic-v3-its";
5771 reg = <0 0x17 5771 reg = <0 0x17040000 0 0x40000>;
5772 5772
5773 msi-controlle 5773 msi-controller;
5774 #msi-cells = 5774 #msi-cells = <1>;
5775 5775
5776 status = "dis 5776 status = "disabled";
5777 }; 5777 };
5778 }; 5778 };
5779 5779
5780 apps_rsc: rsc@17500000 { 5780 apps_rsc: rsc@17500000 {
5781 compatible = "qcom,rp 5781 compatible = "qcom,rpmh-rsc";
5782 reg = <0 0x17500000 0 5782 reg = <0 0x17500000 0 0x10000>,
5783 <0 0x17510000 0 5783 <0 0x17510000 0 0x10000>,
5784 <0 0x17520000 0 5784 <0 0x17520000 0 0x10000>;
5785 reg-names = "drv-0", 5785 reg-names = "drv-0", "drv-1", "drv-2";
5786 5786
5787 interrupts = <GIC_SPI 5787 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
5788 <GIC_SPI 5788 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
5789 <GIC_SPI 5789 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
5790 qcom,tcs-offset = <0x 5790 qcom,tcs-offset = <0xd00>;
5791 qcom,drv-id = <2>; 5791 qcom,drv-id = <2>;
5792 qcom,tcs-config = <AC 5792 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
5793 <WA 5793 <WAKE_TCS 2>, <CONTROL_TCS 0>;
5794 5794
5795 label = "apps_rsc"; 5795 label = "apps_rsc";
5796 power-domains = <&SYS 5796 power-domains = <&SYSTEM_PD>;
5797 5797
5798 apps_bcm_voter: bcm-v 5798 apps_bcm_voter: bcm-voter {
5799 compatible = 5799 compatible = "qcom,bcm-voter";
5800 }; 5800 };
5801 5801
5802 rpmhcc: clock-control 5802 rpmhcc: clock-controller {
5803 compatible = 5803 compatible = "qcom,x1e80100-rpmh-clk";
5804 5804
5805 clocks = <&xo 5805 clocks = <&xo_board>;
5806 clock-names = 5806 clock-names = "xo";
5807 5807
5808 #clock-cells 5808 #clock-cells = <1>;
5809 }; 5809 };
5810 5810
5811 rpmhpd: power-control 5811 rpmhpd: power-controller {
5812 compatible = 5812 compatible = "qcom,x1e80100-rpmhpd";
5813 5813
5814 operating-poi 5814 operating-points-v2 = <&rpmhpd_opp_table>;
5815 5815
5816 #power-domain 5816 #power-domain-cells = <1>;
5817 5817
5818 rpmhpd_opp_ta 5818 rpmhpd_opp_table: opp-table {
5819 compa 5819 compatible = "operating-points-v2";
5820 5820
5821 rpmhp 5821 rpmhpd_opp_ret: opp-16 {
5822 5822 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
5823 }; 5823 };
5824 5824
5825 rpmhp 5825 rpmhpd_opp_min_svs: opp-48 {
5826 5826 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
5827 }; 5827 };
5828 5828
5829 rpmhp 5829 rpmhpd_opp_low_svs_d2: opp-52 {
5830 5830 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
5831 }; 5831 };
5832 5832
5833 rpmhp 5833 rpmhpd_opp_low_svs_d1: opp-56 {
5834 5834 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
5835 }; 5835 };
5836 5836
5837 rpmhp 5837 rpmhpd_opp_low_svs_d0: opp-60 {
5838 5838 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
5839 }; 5839 };
5840 5840
5841 rpmhp 5841 rpmhpd_opp_low_svs: opp-64 {
5842 5842 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
5843 }; 5843 };
5844 5844
5845 rpmhp 5845 rpmhpd_opp_low_svs_l1: opp-80 {
5846 5846 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
5847 }; 5847 };
5848 5848
5849 rpmhp 5849 rpmhpd_opp_svs: opp-128 {
5850 5850 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
5851 }; 5851 };
5852 5852
5853 rpmhp 5853 rpmhpd_opp_svs_l0: opp-144 {
5854 5854 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
5855 }; 5855 };
5856 5856
5857 rpmhp 5857 rpmhpd_opp_svs_l1: opp-192 {
5858 5858 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
5859 }; 5859 };
5860 5860
5861 rpmhp 5861 rpmhpd_opp_nom: opp-256 {
5862 5862 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
5863 }; 5863 };
5864 5864
5865 rpmhp 5865 rpmhpd_opp_nom_l1: opp-320 {
5866 5866 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
5867 }; 5867 };
5868 5868
5869 rpmhp 5869 rpmhpd_opp_nom_l2: opp-336 {
5870 5870 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
5871 }; 5871 };
5872 5872
5873 rpmhp 5873 rpmhpd_opp_turbo: opp-384 {
5874 5874 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
5875 }; 5875 };
5876 5876
5877 rpmhp 5877 rpmhpd_opp_turbo_l1: opp-416 {
5878 5878 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
5879 }; 5879 };
5880 }; 5880 };
5881 }; 5881 };
5882 }; 5882 };
5883 5883
5884 timer@17800000 { 5884 timer@17800000 {
5885 compatible = "arm,arm 5885 compatible = "arm,armv7-timer-mem";
5886 reg = <0 0x17800000 0 5886 reg = <0 0x17800000 0 0x1000>;
5887 5887
5888 #address-cells = <2>; 5888 #address-cells = <2>;
5889 #size-cells = <1>; 5889 #size-cells = <1>;
5890 ranges = <0 0 0 0 0x2 5890 ranges = <0 0 0 0 0x20000000>;
5891 5891
5892 frame@17801000 { 5892 frame@17801000 {
5893 reg = <0 0x17 5893 reg = <0 0x17801000 0x1000>,
5894 <0 0x17 5894 <0 0x17802000 0x1000>;
5895 5895
5896 interrupts = 5896 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
5897 5897 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
5898 5898
5899 frame-number 5899 frame-number = <0>;
5900 }; 5900 };
5901 5901
5902 frame@17803000 { 5902 frame@17803000 {
5903 reg = <0 0x17 5903 reg = <0 0x17803000 0x1000>;
5904 5904
5905 interrupts = 5905 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
5906 5906
5907 frame-number 5907 frame-number = <1>;
5908 5908
5909 status = "dis 5909 status = "disabled";
5910 }; 5910 };
5911 5911
5912 frame@17805000 { 5912 frame@17805000 {
5913 reg = <0 0x17 5913 reg = <0 0x17805000 0x1000>;
5914 5914
5915 interrupts = 5915 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
5916 5916
5917 frame-number 5917 frame-number = <2>;
5918 5918
5919 status = "dis 5919 status = "disabled";
5920 }; 5920 };
5921 5921
5922 frame@17807000 { 5922 frame@17807000 {
5923 reg = <0 0x17 5923 reg = <0 0x17807000 0x1000>;
5924 5924
5925 interrupts = 5925 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
5926 5926
5927 frame-number 5927 frame-number = <3>;
5928 5928
5929 status = "dis 5929 status = "disabled";
5930 }; 5930 };
5931 5931
5932 frame@17809000 { 5932 frame@17809000 {
5933 reg = <0 0x17 5933 reg = <0 0x17809000 0x1000>;
5934 5934
5935 interrupts = 5935 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
5936 5936
5937 frame-number 5937 frame-number = <4>;
5938 5938
5939 status = "dis 5939 status = "disabled";
5940 }; 5940 };
5941 5941
5942 frame@1780b000 { 5942 frame@1780b000 {
5943 reg = <0 0x17 5943 reg = <0 0x1780b000 0x1000>;
5944 5944
5945 interrupts = 5945 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
5946 5946
5947 frame-number 5947 frame-number = <5>;
5948 5948
5949 status = "dis 5949 status = "disabled";
5950 }; 5950 };
5951 5951
5952 frame@1780d000 { 5952 frame@1780d000 {
5953 reg = <0 0x17 5953 reg = <0 0x1780d000 0x1000>;
5954 5954
5955 interrupts = 5955 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
5956 5956
5957 frame-number 5957 frame-number = <6>;
5958 5958
5959 status = "dis 5959 status = "disabled";
5960 }; 5960 };
5961 }; 5961 };
5962 5962
5963 pmu@24091000 { 5963 pmu@24091000 {
5964 compatible = "qcom,x1 5964 compatible = "qcom,x1e80100-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
5965 reg = <0 0x24091000 0 5965 reg = <0 0x24091000 0 0x1000>;
5966 5966
5967 interrupts = <GIC_SPI 5967 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
5968 5968
5969 interconnects = <&mc_ 5969 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
5970 &mc_ 5970 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>;
5971 5971
5972 operating-points-v2 = 5972 operating-points-v2 = <&llcc_bwmon_opp_table>;
5973 5973
5974 llcc_bwmon_opp_table: 5974 llcc_bwmon_opp_table: opp-table {
5975 compatible = 5975 compatible = "operating-points-v2";
5976 5976
5977 opp-0 { 5977 opp-0 {
5978 opp-p 5978 opp-peak-kBps = <800000>;
5979 }; 5979 };
5980 5980
5981 opp-1 { 5981 opp-1 {
5982 opp-p 5982 opp-peak-kBps = <2188000>;
5983 }; 5983 };
5984 5984
5985 opp-2 { 5985 opp-2 {
5986 opp-p 5986 opp-peak-kBps = <3072000>;
5987 }; 5987 };
5988 5988
5989 opp-3 { 5989 opp-3 {
5990 opp-p 5990 opp-peak-kBps = <6220800>;
5991 }; 5991 };
5992 5992
5993 opp-4 { 5993 opp-4 {
5994 opp-p 5994 opp-peak-kBps = <6835200>;
5995 }; 5995 };
5996 5996
5997 opp-5 { 5997 opp-5 {
5998 opp-p 5998 opp-peak-kBps = <8371200>;
5999 }; 5999 };
6000 6000
6001 opp-6 { 6001 opp-6 {
6002 opp-p 6002 opp-peak-kBps = <10944000>;
6003 }; 6003 };
6004 6004
6005 opp-7 { 6005 opp-7 {
6006 opp-p 6006 opp-peak-kBps = <12748800>;
6007 }; 6007 };
6008 6008
6009 opp-8 { 6009 opp-8 {
6010 opp-p 6010 opp-peak-kBps = <14745600>;
6011 }; 6011 };
6012 6012
6013 opp-9 { 6013 opp-9 {
6014 opp-p 6014 opp-peak-kBps = <16896000>;
6015 }; 6015 };
6016 }; 6016 };
6017 }; 6017 };
6018 6018
6019 /* cluster0 */ 6019 /* cluster0 */
6020 pmu@240b3400 { 6020 pmu@240b3400 {
6021 compatible = "qcom,x1 6021 compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon";
6022 reg = <0 0x240b3400 0 6022 reg = <0 0x240b3400 0 0x600>;
6023 6023
6024 interrupts = <GIC_SPI 6024 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
6025 6025
6026 interconnects = <&gem 6026 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
6027 &gem 6027 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>;
6028 6028
6029 operating-points-v2 = 6029 operating-points-v2 = <&cpu_bwmon_opp_table>;
6030 6030
6031 cpu_bwmon_opp_table: 6031 cpu_bwmon_opp_table: opp-table {
6032 compatible = 6032 compatible = "operating-points-v2";
6033 6033
6034 opp-0 { 6034 opp-0 {
6035 opp-p 6035 opp-peak-kBps = <4800000>;
6036 }; 6036 };
6037 6037
6038 opp-1 { 6038 opp-1 {
6039 opp-p 6039 opp-peak-kBps = <7464000>;
6040 }; 6040 };
6041 6041
6042 opp-2 { 6042 opp-2 {
6043 opp-p 6043 opp-peak-kBps = <9600000>;
6044 }; 6044 };
6045 6045
6046 opp-3 { 6046 opp-3 {
6047 opp-p 6047 opp-peak-kBps = <12896000>;
6048 }; 6048 };
6049 6049
6050 opp-4 { 6050 opp-4 {
6051 opp-p 6051 opp-peak-kBps = <14928000>;
6052 }; 6052 };
6053 6053
6054 opp-5 { 6054 opp-5 {
6055 opp-p 6055 opp-peak-kBps = <17064000>;
6056 }; 6056 };
6057 }; 6057 };
6058 }; 6058 };
6059 6059
6060 /* cluster2 */ 6060 /* cluster2 */
6061 pmu@240b5400 { 6061 pmu@240b5400 {
6062 compatible = "qcom,x1 6062 compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon";
6063 reg = <0 0x240b5400 0 6063 reg = <0 0x240b5400 0 0x600>;
6064 6064
6065 interrupts = <GIC_SPI 6065 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
6066 6066
6067 interconnects = <&gem 6067 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
6068 &gem 6068 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>;
6069 6069
6070 operating-points-v2 = 6070 operating-points-v2 = <&cpu_bwmon_opp_table>;
6071 }; 6071 };
6072 6072
6073 /* cluster1 */ 6073 /* cluster1 */
6074 pmu@240b6400 { 6074 pmu@240b6400 {
6075 compatible = "qcom,x1 6075 compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon";
6076 reg = <0 0x240b6400 0 6076 reg = <0 0x240b6400 0 0x600>;
6077 6077
6078 interrupts = <GIC_SPI 6078 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
6079 6079
6080 interconnects = <&gem 6080 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
6081 &gem 6081 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>;
6082 6082
6083 operating-points-v2 = 6083 operating-points-v2 = <&cpu_bwmon_opp_table>;
6084 }; 6084 };
6085 6085
6086 system-cache-controller@25000 6086 system-cache-controller@25000000 {
6087 compatible = "qcom,x1 6087 compatible = "qcom,x1e80100-llcc";
6088 reg = <0 0x25000000 0 6088 reg = <0 0x25000000 0 0x200000>,
6089 <0 0x25200000 0 6089 <0 0x25200000 0 0x200000>,
6090 <0 0x25400000 0 6090 <0 0x25400000 0 0x200000>,
6091 <0 0x25600000 0 6091 <0 0x25600000 0 0x200000>,
6092 <0 0x25800000 0 6092 <0 0x25800000 0 0x200000>,
6093 <0 0x25a00000 0 6093 <0 0x25a00000 0 0x200000>,
6094 <0 0x25c00000 0 6094 <0 0x25c00000 0 0x200000>,
6095 <0 0x25e00000 0 6095 <0 0x25e00000 0 0x200000>,
6096 <0 0x26000000 0 6096 <0 0x26000000 0 0x200000>,
6097 <0 0x26200000 0 6097 <0 0x26200000 0 0x200000>;
6098 reg-names = "llcc0_ba 6098 reg-names = "llcc0_base",
6099 "llcc1_ba 6099 "llcc1_base",
6100 "llcc2_ba 6100 "llcc2_base",
6101 "llcc3_ba 6101 "llcc3_base",
6102 "llcc4_ba 6102 "llcc4_base",
6103 "llcc5_ba 6103 "llcc5_base",
6104 "llcc6_ba 6104 "llcc6_base",
6105 "llcc7_ba 6105 "llcc7_base",
6106 "llcc_bro 6106 "llcc_broadcast_base",
6107 "llcc_bro 6107 "llcc_broadcast_and_base";
6108 interrupts = <GIC_SPI 6108 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
6109 }; 6109 };
6110 6110
6111 remoteproc_adsp: remoteproc@3 6111 remoteproc_adsp: remoteproc@30000000 {
6112 compatible = "qcom,x1 6112 compatible = "qcom,x1e80100-adsp-pas";
6113 reg = <0 0x30000000 0 6113 reg = <0 0x30000000 0 0x100>;
6114 6114
6115 interrupts-extended = 6115 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
6116 6116 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
6117 6117 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
6118 6118 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
6119 6119 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
6120 interrupt-names = "wd 6120 interrupt-names = "wdog",
6121 "fa 6121 "fatal",
6122 "re 6122 "ready",
6123 "ha 6123 "handover",
6124 "st 6124 "stop-ack";
6125 6125
6126 clocks = <&rpmhcc RPM 6126 clocks = <&rpmhcc RPMH_CXO_CLK>;
6127 clock-names = "xo"; 6127 clock-names = "xo";
6128 6128
6129 power-domains = <&rpm 6129 power-domains = <&rpmhpd RPMHPD_LCX>,
6130 <&rpm 6130 <&rpmhpd RPMHPD_LMX>;
6131 power-domain-names = 6131 power-domain-names = "lcx",
6132 6132 "lmx";
6133 6133
6134 interconnects = <&lpa 6134 interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS
6135 &mc_ 6135 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
6136 6136
6137 memory-region = <&ads 6137 memory-region = <&adspslpi_mem>,
6138 <&q6_ 6138 <&q6_adsp_dtb_mem>;
6139 6139
6140 qcom,qmp = <&aoss_qmp 6140 qcom,qmp = <&aoss_qmp>;
6141 6141
6142 qcom,smem-states = <& 6142 qcom,smem-states = <&smp2p_adsp_out 0>;
6143 qcom,smem-state-names 6143 qcom,smem-state-names = "stop";
6144 6144
6145 status = "disabled"; 6145 status = "disabled";
6146 6146
6147 glink-edge { 6147 glink-edge {
6148 interrupts-ex 6148 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
6149 6149 IPCC_MPROC_SIGNAL_GLINK_QMP
6150 6150 IRQ_TYPE_EDGE_RISING>;
6151 mboxes = <&ip 6151 mboxes = <&ipcc IPCC_CLIENT_LPASS
6152 6152 IPCC_MPROC_SIGNAL_GLINK_QMP>;
6153 6153
6154 label = "lpas 6154 label = "lpass";
6155 qcom,remote-p 6155 qcom,remote-pid = <2>;
6156 6156
6157 fastrpc { 6157 fastrpc {
6158 compa 6158 compatible = "qcom,fastrpc";
6159 qcom, 6159 qcom,glink-channels = "fastrpcglink-apps-dsp";
6160 label 6160 label = "adsp";
6161 qcom, 6161 qcom,non-secure-domain;
6162 #addr 6162 #address-cells = <1>;
6163 #size 6163 #size-cells = <0>;
6164 6164
6165 compu 6165 compute-cb@3 {
6166 6166 compatible = "qcom,fastrpc-compute-cb";
6167 6167 reg = <3>;
6168 6168 iommus = <&apps_smmu 0x1003 0x80>,
6169 6169 <&apps_smmu 0x1063 0x0>;
6170 6170 dma-coherent;
6171 }; 6171 };
6172 6172
6173 compu 6173 compute-cb@4 {
6174 6174 compatible = "qcom,fastrpc-compute-cb";
6175 6175 reg = <4>;
6176 6176 iommus = <&apps_smmu 0x1004 0x80>,
6177 6177 <&apps_smmu 0x1064 0x0>;
6178 6178 dma-coherent;
6179 }; 6179 };
6180 6180
6181 compu 6181 compute-cb@5 {
6182 6182 compatible = "qcom,fastrpc-compute-cb";
6183 6183 reg = <5>;
6184 6184 iommus = <&apps_smmu 0x1005 0x80>,
6185 6185 <&apps_smmu 0x1065 0x0>;
6186 6186 dma-coherent;
6187 }; 6187 };
6188 6188
6189 compu 6189 compute-cb@6 {
6190 6190 compatible = "qcom,fastrpc-compute-cb";
6191 6191 reg = <6>;
6192 6192 iommus = <&apps_smmu 0x1006 0x80>,
6193 6193 <&apps_smmu 0x1066 0x0>;
6194 6194 dma-coherent;
6195 }; 6195 };
6196 6196
6197 compu 6197 compute-cb@7 {
6198 6198 compatible = "qcom,fastrpc-compute-cb";
6199 6199 reg = <7>;
6200 6200 iommus = <&apps_smmu 0x1007 0x80>,
6201 6201 <&apps_smmu 0x1067 0x0>;
6202 6202 dma-coherent;
6203 }; 6203 };
6204 }; 6204 };
6205 6205
6206 gpr { 6206 gpr {
6207 compa 6207 compatible = "qcom,gpr";
6208 qcom, 6208 qcom,glink-channels = "adsp_apps";
6209 qcom, 6209 qcom,domain = <GPR_DOMAIN_ID_ADSP>;
6210 qcom, 6210 qcom,intents = <512 20>;
6211 #addr 6211 #address-cells = <1>;
6212 #size 6212 #size-cells = <0>;
6213 6213
6214 q6apm 6214 q6apm: service@1 {
6215 6215 compatible = "qcom,q6apm";
6216 6216 reg = <GPR_APM_MODULE_IID>;
6217 6217 #sound-dai-cells = <0>;
6218 6218 qcom,protection-domain = "avs/audio",
6219 6219 "msm/adsp/audio_pd";
6220 6220
6221 6221 q6apmbedai: bedais {
6222 6222 compatible = "qcom,q6apm-lpass-dais";
6223 6223 #sound-dai-cells = <1>;
6224 6224 };
6225 6225
6226 6226 q6apmdai: dais {
6227 6227 compatible = "qcom,q6apm-dais";
6228 6228 iommus = <&apps_smmu 0x1001 0x80>,
6229 6229 <&apps_smmu 0x1061 0x0>;
6230 6230 };
6231 }; 6231 };
6232 6232
6233 q6prm 6233 q6prm: service@2 {
6234 6234 compatible = "qcom,q6prm";
6235 6235 reg = <GPR_PRM_MODULE_IID>;
6236 6236 qcom,protection-domain = "avs/audio",
6237 6237 "msm/adsp/audio_pd";
6238 6238
6239 6239 q6prmcc: clock-controller {
6240 6240 compatible = "qcom,q6prm-lpass-clocks";
6241 6241 #clock-cells = <2>;
6242 6242 };
6243 }; 6243 };
6244 }; 6244 };
6245 }; 6245 };
6246 }; 6246 };
6247 6247
6248 remoteproc_cdsp: remoteproc@3 6248 remoteproc_cdsp: remoteproc@32300000 {
6249 compatible = "qcom,x1 6249 compatible = "qcom,x1e80100-cdsp-pas";
6250 reg = <0 0x32300000 0 6250 reg = <0 0x32300000 0 0x1400000>;
6251 6251
6252 interrupts-extended = 6252 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
6253 6253 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
6254 6254 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
6255 6255 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
6256 6256 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
6257 interrupt-names = "wd 6257 interrupt-names = "wdog",
6258 "fa 6258 "fatal",
6259 "re 6259 "ready",
6260 "ha 6260 "handover",
6261 "st 6261 "stop-ack";
6262 6262
6263 clocks = <&rpmhcc RPM 6263 clocks = <&rpmhcc RPMH_CXO_CLK>;
6264 clock-names = "xo"; 6264 clock-names = "xo";
6265 6265
6266 power-domains = <&rpm 6266 power-domains = <&rpmhpd RPMHPD_CX>,
6267 <&rpm 6267 <&rpmhpd RPMHPD_MXC>,
6268 <&rpm 6268 <&rpmhpd RPMHPD_NSP>;
6269 power-domain-names = 6269 power-domain-names = "cx",
6270 6270 "mxc",
6271 6271 "nsp";
6272 6272
6273 interconnects = <&nsp 6273 interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS
6274 &mc_ 6274 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
6275 6275
6276 memory-region = <&cds 6276 memory-region = <&cdsp_mem>,
6277 <&q6_ 6277 <&q6_cdsp_dtb_mem>;
6278 6278
6279 qcom,qmp = <&aoss_qmp 6279 qcom,qmp = <&aoss_qmp>;
6280 6280
6281 qcom,smem-states = <& 6281 qcom,smem-states = <&smp2p_cdsp_out 0>;
6282 qcom,smem-state-names 6282 qcom,smem-state-names = "stop";
6283 6283
6284 status = "disabled"; 6284 status = "disabled";
6285 6285
6286 glink-edge { 6286 glink-edge {
6287 interrupts-ex 6287 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
6288 6288 IPCC_MPROC_SIGNAL_GLINK_QMP
6289 6289 IRQ_TYPE_EDGE_RISING>;
6290 mboxes = <&ip 6290 mboxes = <&ipcc IPCC_CLIENT_CDSP
6291 6291 IPCC_MPROC_SIGNAL_GLINK_QMP>;
6292 6292
6293 label = "cdsp 6293 label = "cdsp";
6294 qcom,remote-p 6294 qcom,remote-pid = <5>;
6295 6295
6296 fastrpc { 6296 fastrpc {
6297 compa 6297 compatible = "qcom,fastrpc";
6298 qcom, 6298 qcom,glink-channels = "fastrpcglink-apps-dsp";
6299 label 6299 label = "cdsp";
6300 qcom, 6300 qcom,non-secure-domain;
6301 #addr 6301 #address-cells = <1>;
6302 #size 6302 #size-cells = <0>;
6303 6303
6304 compu 6304 compute-cb@1 {
6305 6305 compatible = "qcom,fastrpc-compute-cb";
6306 6306 reg = <1>;
6307 6307 iommus = <&apps_smmu 0x0c01 0x20>;
6308 6308 dma-coherent;
6309 }; 6309 };
6310 6310
6311 compu 6311 compute-cb@2 {
6312 6312 compatible = "qcom,fastrpc-compute-cb";
6313 6313 reg = <2>;
6314 6314 iommus = <&apps_smmu 0x0c02 0x20>;
6315 6315 dma-coherent;
6316 }; 6316 };
6317 6317
6318 compu 6318 compute-cb@3 {
6319 6319 compatible = "qcom,fastrpc-compute-cb";
6320 6320 reg = <3>;
6321 6321 iommus = <&apps_smmu 0x0c03 0x20>;
6322 6322 dma-coherent;
6323 }; 6323 };
6324 6324
6325 compu 6325 compute-cb@4 {
6326 6326 compatible = "qcom,fastrpc-compute-cb";
6327 6327 reg = <4>;
6328 6328 iommus = <&apps_smmu 0x0c04 0x20>;
6329 6329 dma-coherent;
6330 }; 6330 };
6331 6331
6332 compu 6332 compute-cb@5 {
6333 6333 compatible = "qcom,fastrpc-compute-cb";
6334 6334 reg = <5>;
6335 6335 iommus = <&apps_smmu 0x0c05 0x20>;
6336 6336 dma-coherent;
6337 }; 6337 };
6338 6338
6339 compu 6339 compute-cb@6 {
6340 6340 compatible = "qcom,fastrpc-compute-cb";
6341 6341 reg = <6>;
6342 6342 iommus = <&apps_smmu 0x0c06 0x20>;
6343 6343 dma-coherent;
6344 }; 6344 };
6345 6345
6346 compu 6346 compute-cb@7 {
6347 6347 compatible = "qcom,fastrpc-compute-cb";
6348 6348 reg = <7>;
6349 6349 iommus = <&apps_smmu 0x0c07 0x20>;
6350 6350 dma-coherent;
6351 }; 6351 };
6352 6352
6353 compu 6353 compute-cb@8 {
6354 6354 compatible = "qcom,fastrpc-compute-cb";
6355 6355 reg = <8>;
6356 6356 iommus = <&apps_smmu 0x0c08 0x20>;
6357 6357 dma-coherent;
6358 }; 6358 };
6359 6359
6360 /* no 6360 /* note: compute-cb@9 is secure */
6361 6361
6362 compu 6362 compute-cb@10 {
6363 6363 compatible = "qcom,fastrpc-compute-cb";
6364 6364 reg = <10>;
6365 6365 iommus = <&apps_smmu 0x0c0c 0x20>;
6366 6366 dma-coherent;
6367 }; 6367 };
6368 6368
6369 compu 6369 compute-cb@11 {
6370 6370 compatible = "qcom,fastrpc-compute-cb";
6371 6371 reg = <11>;
6372 6372 iommus = <&apps_smmu 0x0c0d 0x20>;
6373 6373 dma-coherent;
6374 }; 6374 };
6375 6375
6376 compu 6376 compute-cb@12 {
6377 6377 compatible = "qcom,fastrpc-compute-cb";
6378 6378 reg = <12>;
6379 6379 iommus = <&apps_smmu 0x0c0e 0x20>;
6380 6380 dma-coherent;
6381 }; 6381 };
6382 6382
6383 compu 6383 compute-cb@13 {
6384 6384 compatible = "qcom,fastrpc-compute-cb";
6385 6385 reg = <13>;
6386 6386 iommus = <&apps_smmu 0x0c0f 0x20>;
6387 6387 dma-coherent;
6388 }; 6388 };
6389 }; 6389 };
6390 }; 6390 };
6391 }; 6391 };
6392 }; 6392 };
6393 6393
6394 timer { 6394 timer {
6395 compatible = "arm,armv8-timer 6395 compatible = "arm,armv8-timer";
6396 6396
6397 interrupts = <GIC_PPI 13 IRQ_ 6397 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
6398 <GIC_PPI 14 IRQ_ 6398 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
6399 <GIC_PPI 11 IRQ_ 6399 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
6400 <GIC_PPI 10 IRQ_ 6400 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
6401 }; 6401 };
6402 6402
6403 thermal-zones { 6403 thermal-zones {
6404 aoss0-thermal { 6404 aoss0-thermal {
6405 thermal-sensors = <&t 6405 thermal-sensors = <&tsens0 0>;
6406 6406
6407 trips { 6407 trips {
6408 trip-point0 { 6408 trip-point0 {
6409 tempe 6409 temperature = <90000>;
6410 hyste 6410 hysteresis = <2000>;
6411 type 6411 type = "hot";
6412 }; 6412 };
6413 6413
6414 aoss0-critica 6414 aoss0-critical {
6415 tempe 6415 temperature = <125000>;
6416 hyste 6416 hysteresis = <0>;
6417 type 6417 type = "critical";
6418 }; 6418 };
6419 }; 6419 };
6420 }; 6420 };
6421 6421
6422 cpu0-0-top-thermal { 6422 cpu0-0-top-thermal {
6423 polling-delay-passive 6423 polling-delay-passive = <250>;
6424 6424
6425 thermal-sensors = <&t 6425 thermal-sensors = <&tsens0 1>;
6426 6426
6427 trips { 6427 trips {
6428 trip-point0 { 6428 trip-point0 {
6429 tempe 6429 temperature = <90000>;
6430 hyste 6430 hysteresis = <2000>;
6431 type 6431 type = "passive";
6432 }; 6432 };
6433 6433
6434 trip-point1 { 6434 trip-point1 {
6435 tempe 6435 temperature = <95000>;
6436 hyste 6436 hysteresis = <2000>;
6437 type 6437 type = "passive";
6438 }; 6438 };
6439 6439
6440 cpu-critical 6440 cpu-critical {
6441 tempe 6441 temperature = <110000>;
6442 hyste 6442 hysteresis = <1000>;
6443 type 6443 type = "critical";
6444 }; 6444 };
6445 }; 6445 };
6446 }; 6446 };
6447 6447
6448 cpu0-0-btm-thermal { 6448 cpu0-0-btm-thermal {
6449 polling-delay-passive 6449 polling-delay-passive = <250>;
6450 6450
6451 thermal-sensors = <&t 6451 thermal-sensors = <&tsens0 2>;
6452 6452
6453 trips { 6453 trips {
6454 trip-point0 { 6454 trip-point0 {
6455 tempe 6455 temperature = <90000>;
6456 hyste 6456 hysteresis = <2000>;
6457 type 6457 type = "passive";
6458 }; 6458 };
6459 6459
6460 trip-point1 { 6460 trip-point1 {
6461 tempe 6461 temperature = <95000>;
6462 hyste 6462 hysteresis = <2000>;
6463 type 6463 type = "passive";
6464 }; 6464 };
6465 6465
6466 cpu-critical 6466 cpu-critical {
6467 tempe 6467 temperature = <110000>;
6468 hyste 6468 hysteresis = <1000>;
6469 type 6469 type = "critical";
6470 }; 6470 };
6471 }; 6471 };
6472 }; 6472 };
6473 6473
6474 cpu0-1-top-thermal { 6474 cpu0-1-top-thermal {
6475 polling-delay-passive 6475 polling-delay-passive = <250>;
6476 6476
6477 thermal-sensors = <&t 6477 thermal-sensors = <&tsens0 3>;
6478 6478
6479 trips { 6479 trips {
6480 trip-point0 { 6480 trip-point0 {
6481 tempe 6481 temperature = <90000>;
6482 hyste 6482 hysteresis = <2000>;
6483 type 6483 type = "passive";
6484 }; 6484 };
6485 6485
6486 trip-point1 { 6486 trip-point1 {
6487 tempe 6487 temperature = <95000>;
6488 hyste 6488 hysteresis = <2000>;
6489 type 6489 type = "passive";
6490 }; 6490 };
6491 6491
6492 cpu-critical 6492 cpu-critical {
6493 tempe 6493 temperature = <110000>;
6494 hyste 6494 hysteresis = <1000>;
6495 type 6495 type = "critical";
6496 }; 6496 };
6497 }; 6497 };
6498 }; 6498 };
6499 6499
6500 cpu0-1-btm-thermal { 6500 cpu0-1-btm-thermal {
6501 polling-delay-passive 6501 polling-delay-passive = <250>;
6502 6502
6503 thermal-sensors = <&t 6503 thermal-sensors = <&tsens0 4>;
6504 6504
6505 trips { 6505 trips {
6506 trip-point0 { 6506 trip-point0 {
6507 tempe 6507 temperature = <90000>;
6508 hyste 6508 hysteresis = <2000>;
6509 type 6509 type = "passive";
6510 }; 6510 };
6511 6511
6512 trip-point1 { 6512 trip-point1 {
6513 tempe 6513 temperature = <95000>;
6514 hyste 6514 hysteresis = <2000>;
6515 type 6515 type = "passive";
6516 }; 6516 };
6517 6517
6518 cpu-critical 6518 cpu-critical {
6519 tempe 6519 temperature = <110000>;
6520 hyste 6520 hysteresis = <1000>;
6521 type 6521 type = "critical";
6522 }; 6522 };
6523 }; 6523 };
6524 }; 6524 };
6525 6525
6526 cpu0-2-top-thermal { 6526 cpu0-2-top-thermal {
6527 polling-delay-passive 6527 polling-delay-passive = <250>;
6528 6528
6529 thermal-sensors = <&t 6529 thermal-sensors = <&tsens0 5>;
6530 6530
6531 trips { 6531 trips {
6532 trip-point0 { 6532 trip-point0 {
6533 tempe 6533 temperature = <90000>;
6534 hyste 6534 hysteresis = <2000>;
6535 type 6535 type = "passive";
6536 }; 6536 };
6537 6537
6538 trip-point1 { 6538 trip-point1 {
6539 tempe 6539 temperature = <95000>;
6540 hyste 6540 hysteresis = <2000>;
6541 type 6541 type = "passive";
6542 }; 6542 };
6543 6543
6544 cpu-critical 6544 cpu-critical {
6545 tempe 6545 temperature = <110000>;
6546 hyste 6546 hysteresis = <1000>;
6547 type 6547 type = "critical";
6548 }; 6548 };
6549 }; 6549 };
6550 }; 6550 };
6551 6551
6552 cpu0-2-btm-thermal { 6552 cpu0-2-btm-thermal {
6553 polling-delay-passive 6553 polling-delay-passive = <250>;
6554 6554
6555 thermal-sensors = <&t 6555 thermal-sensors = <&tsens0 6>;
6556 6556
6557 trips { 6557 trips {
6558 trip-point0 { 6558 trip-point0 {
6559 tempe 6559 temperature = <90000>;
6560 hyste 6560 hysteresis = <2000>;
6561 type 6561 type = "passive";
6562 }; 6562 };
6563 6563
6564 trip-point1 { 6564 trip-point1 {
6565 tempe 6565 temperature = <95000>;
6566 hyste 6566 hysteresis = <2000>;
6567 type 6567 type = "passive";
6568 }; 6568 };
6569 6569
6570 cpu-critical 6570 cpu-critical {
6571 tempe 6571 temperature = <110000>;
6572 hyste 6572 hysteresis = <1000>;
6573 type 6573 type = "critical";
6574 }; 6574 };
6575 }; 6575 };
6576 }; 6576 };
6577 6577
6578 cpu0-3-top-thermal { 6578 cpu0-3-top-thermal {
6579 polling-delay-passive 6579 polling-delay-passive = <250>;
6580 6580
6581 thermal-sensors = <&t 6581 thermal-sensors = <&tsens0 7>;
6582 6582
6583 trips { 6583 trips {
6584 trip-point0 { 6584 trip-point0 {
6585 tempe 6585 temperature = <90000>;
6586 hyste 6586 hysteresis = <2000>;
6587 type 6587 type = "passive";
6588 }; 6588 };
6589 6589
6590 trip-point1 { 6590 trip-point1 {
6591 tempe 6591 temperature = <95000>;
6592 hyste 6592 hysteresis = <2000>;
6593 type 6593 type = "passive";
6594 }; 6594 };
6595 6595
6596 cpu-critical 6596 cpu-critical {
6597 tempe 6597 temperature = <110000>;
6598 hyste 6598 hysteresis = <1000>;
6599 type 6599 type = "critical";
6600 }; 6600 };
6601 }; 6601 };
6602 }; 6602 };
6603 6603
6604 cpu0-3-btm-thermal { 6604 cpu0-3-btm-thermal {
6605 polling-delay-passive 6605 polling-delay-passive = <250>;
6606 6606
6607 thermal-sensors = <&t 6607 thermal-sensors = <&tsens0 8>;
6608 6608
6609 trips { 6609 trips {
6610 trip-point0 { 6610 trip-point0 {
6611 tempe 6611 temperature = <90000>;
6612 hyste 6612 hysteresis = <2000>;
6613 type 6613 type = "passive";
6614 }; 6614 };
6615 6615
6616 trip-point1 { 6616 trip-point1 {
6617 tempe 6617 temperature = <95000>;
6618 hyste 6618 hysteresis = <2000>;
6619 type 6619 type = "passive";
6620 }; 6620 };
6621 6621
6622 cpu-critical 6622 cpu-critical {
6623 tempe 6623 temperature = <110000>;
6624 hyste 6624 hysteresis = <1000>;
6625 type 6625 type = "critical";
6626 }; 6626 };
6627 }; 6627 };
6628 }; 6628 };
6629 6629
6630 cpuss0-top-thermal { 6630 cpuss0-top-thermal {
6631 thermal-sensors = <&t 6631 thermal-sensors = <&tsens0 9>;
6632 6632
6633 trips { 6633 trips {
6634 trip-point0 { 6634 trip-point0 {
6635 tempe 6635 temperature = <90000>;
6636 hyste 6636 hysteresis = <2000>;
6637 type 6637 type = "hot";
6638 }; 6638 };
6639 6639
6640 cpuss2-critic 6640 cpuss2-critical {
6641 tempe 6641 temperature = <125000>;
6642 hyste 6642 hysteresis = <0>;
6643 type 6643 type = "critical";
6644 }; 6644 };
6645 }; 6645 };
6646 }; 6646 };
6647 6647
6648 cpuss0-btm-thermal { 6648 cpuss0-btm-thermal {
6649 thermal-sensors = <&t 6649 thermal-sensors = <&tsens0 10>;
6650 6650
6651 trips { 6651 trips {
6652 trip-point0 { 6652 trip-point0 {
6653 tempe 6653 temperature = <90000>;
6654 hyste 6654 hysteresis = <2000>;
6655 type 6655 type = "hot";
6656 }; 6656 };
6657 6657
6658 cpuss2-critic 6658 cpuss2-critical {
6659 tempe 6659 temperature = <125000>;
6660 hyste 6660 hysteresis = <0>;
6661 type 6661 type = "critical";
6662 }; 6662 };
6663 }; 6663 };
6664 }; 6664 };
6665 6665
6666 mem-thermal { 6666 mem-thermal {
6667 thermal-sensors = <&t 6667 thermal-sensors = <&tsens0 11>;
6668 6668
6669 trips { 6669 trips {
6670 trip-point0 { 6670 trip-point0 {
6671 tempe 6671 temperature = <90000>;
6672 hyste 6672 hysteresis = <2000>;
6673 type 6673 type = "hot";
6674 }; 6674 };
6675 6675
6676 mem-critical 6676 mem-critical {
6677 tempe 6677 temperature = <125000>;
6678 hyste 6678 hysteresis = <0>;
6679 type 6679 type = "critical";
6680 }; 6680 };
6681 }; 6681 };
6682 }; 6682 };
6683 6683
6684 video-thermal { 6684 video-thermal {
6685 polling-delay-passive 6685 polling-delay-passive = <250>;
6686 6686
6687 thermal-sensors = <&t 6687 thermal-sensors = <&tsens0 12>;
6688 6688
6689 trips { 6689 trips {
6690 trip-point0 { 6690 trip-point0 {
6691 tempe 6691 temperature = <125000>;
6692 hyste 6692 hysteresis = <1000>;
6693 type 6693 type = "passive";
6694 }; 6694 };
6695 }; 6695 };
6696 }; 6696 };
6697 6697
6698 aoss1-thermal { 6698 aoss1-thermal {
6699 thermal-sensors = <&t 6699 thermal-sensors = <&tsens1 0>;
6700 6700
6701 trips { 6701 trips {
6702 trip-point0 { 6702 trip-point0 {
6703 tempe 6703 temperature = <90000>;
6704 hyste 6704 hysteresis = <2000>;
6705 type 6705 type = "hot";
6706 }; 6706 };
6707 6707
6708 aoss0-critica 6708 aoss0-critical {
6709 tempe 6709 temperature = <125000>;
6710 hyste 6710 hysteresis = <0>;
6711 type 6711 type = "critical";
6712 }; 6712 };
6713 }; 6713 };
6714 }; 6714 };
6715 6715
6716 cpu1-0-top-thermal { 6716 cpu1-0-top-thermal {
6717 polling-delay-passive 6717 polling-delay-passive = <250>;
6718 6718
6719 thermal-sensors = <&t 6719 thermal-sensors = <&tsens1 1>;
6720 6720
6721 trips { 6721 trips {
6722 trip-point0 { 6722 trip-point0 {
6723 tempe 6723 temperature = <90000>;
6724 hyste 6724 hysteresis = <2000>;
6725 type 6725 type = "passive";
6726 }; 6726 };
6727 6727
6728 trip-point1 { 6728 trip-point1 {
6729 tempe 6729 temperature = <95000>;
6730 hyste 6730 hysteresis = <2000>;
6731 type 6731 type = "passive";
6732 }; 6732 };
6733 6733
6734 cpu-critical 6734 cpu-critical {
6735 tempe 6735 temperature = <110000>;
6736 hyste 6736 hysteresis = <1000>;
6737 type 6737 type = "critical";
6738 }; 6738 };
6739 }; 6739 };
6740 }; 6740 };
6741 6741
6742 cpu1-0-btm-thermal { 6742 cpu1-0-btm-thermal {
6743 polling-delay-passive 6743 polling-delay-passive = <250>;
6744 6744
6745 thermal-sensors = <&t 6745 thermal-sensors = <&tsens1 2>;
6746 6746
6747 trips { 6747 trips {
6748 trip-point0 { 6748 trip-point0 {
6749 tempe 6749 temperature = <90000>;
6750 hyste 6750 hysteresis = <2000>;
6751 type 6751 type = "passive";
6752 }; 6752 };
6753 6753
6754 trip-point1 { 6754 trip-point1 {
6755 tempe 6755 temperature = <95000>;
6756 hyste 6756 hysteresis = <2000>;
6757 type 6757 type = "passive";
6758 }; 6758 };
6759 6759
6760 cpu-critical 6760 cpu-critical {
6761 tempe 6761 temperature = <110000>;
6762 hyste 6762 hysteresis = <1000>;
6763 type 6763 type = "critical";
6764 }; 6764 };
6765 }; 6765 };
6766 }; 6766 };
6767 6767
6768 cpu1-1-top-thermal { 6768 cpu1-1-top-thermal {
6769 polling-delay-passive 6769 polling-delay-passive = <250>;
6770 6770
6771 thermal-sensors = <&t 6771 thermal-sensors = <&tsens1 3>;
6772 6772
6773 trips { 6773 trips {
6774 trip-point0 { 6774 trip-point0 {
6775 tempe 6775 temperature = <90000>;
6776 hyste 6776 hysteresis = <2000>;
6777 type 6777 type = "passive";
6778 }; 6778 };
6779 6779
6780 trip-point1 { 6780 trip-point1 {
6781 tempe 6781 temperature = <95000>;
6782 hyste 6782 hysteresis = <2000>;
6783 type 6783 type = "passive";
6784 }; 6784 };
6785 6785
6786 cpu-critical 6786 cpu-critical {
6787 tempe 6787 temperature = <110000>;
6788 hyste 6788 hysteresis = <1000>;
6789 type 6789 type = "critical";
6790 }; 6790 };
6791 }; 6791 };
6792 }; 6792 };
6793 6793
6794 cpu1-1-btm-thermal { 6794 cpu1-1-btm-thermal {
6795 polling-delay-passive 6795 polling-delay-passive = <250>;
6796 6796
6797 thermal-sensors = <&t 6797 thermal-sensors = <&tsens1 4>;
6798 6798
6799 trips { 6799 trips {
6800 trip-point0 { 6800 trip-point0 {
6801 tempe 6801 temperature = <90000>;
6802 hyste 6802 hysteresis = <2000>;
6803 type 6803 type = "passive";
6804 }; 6804 };
6805 6805
6806 trip-point1 { 6806 trip-point1 {
6807 tempe 6807 temperature = <95000>;
6808 hyste 6808 hysteresis = <2000>;
6809 type 6809 type = "passive";
6810 }; 6810 };
6811 6811
6812 cpu-critical 6812 cpu-critical {
6813 tempe 6813 temperature = <110000>;
6814 hyste 6814 hysteresis = <1000>;
6815 type 6815 type = "critical";
6816 }; 6816 };
6817 }; 6817 };
6818 }; 6818 };
6819 6819
6820 cpu1-2-top-thermal { 6820 cpu1-2-top-thermal {
6821 polling-delay-passive 6821 polling-delay-passive = <250>;
6822 6822
6823 thermal-sensors = <&t 6823 thermal-sensors = <&tsens1 5>;
6824 6824
6825 trips { 6825 trips {
6826 trip-point0 { 6826 trip-point0 {
6827 tempe 6827 temperature = <90000>;
6828 hyste 6828 hysteresis = <2000>;
6829 type 6829 type = "passive";
6830 }; 6830 };
6831 6831
6832 trip-point1 { 6832 trip-point1 {
6833 tempe 6833 temperature = <95000>;
6834 hyste 6834 hysteresis = <2000>;
6835 type 6835 type = "passive";
6836 }; 6836 };
6837 6837
6838 cpu-critical 6838 cpu-critical {
6839 tempe 6839 temperature = <110000>;
6840 hyste 6840 hysteresis = <1000>;
6841 type 6841 type = "critical";
6842 }; 6842 };
6843 }; 6843 };
6844 }; 6844 };
6845 6845
6846 cpu1-2-btm-thermal { 6846 cpu1-2-btm-thermal {
6847 polling-delay-passive 6847 polling-delay-passive = <250>;
6848 6848
6849 thermal-sensors = <&t 6849 thermal-sensors = <&tsens1 6>;
6850 6850
6851 trips { 6851 trips {
6852 trip-point0 { 6852 trip-point0 {
6853 tempe 6853 temperature = <90000>;
6854 hyste 6854 hysteresis = <2000>;
6855 type 6855 type = "passive";
6856 }; 6856 };
6857 6857
6858 trip-point1 { 6858 trip-point1 {
6859 tempe 6859 temperature = <95000>;
6860 hyste 6860 hysteresis = <2000>;
6861 type 6861 type = "passive";
6862 }; 6862 };
6863 6863
6864 cpu-critical 6864 cpu-critical {
6865 tempe 6865 temperature = <110000>;
6866 hyste 6866 hysteresis = <1000>;
6867 type 6867 type = "critical";
6868 }; 6868 };
6869 }; 6869 };
6870 }; 6870 };
6871 6871
6872 cpu1-3-top-thermal { 6872 cpu1-3-top-thermal {
6873 polling-delay-passive 6873 polling-delay-passive = <250>;
6874 6874
6875 thermal-sensors = <&t 6875 thermal-sensors = <&tsens1 7>;
6876 6876
6877 trips { 6877 trips {
6878 trip-point0 { 6878 trip-point0 {
6879 tempe 6879 temperature = <90000>;
6880 hyste 6880 hysteresis = <2000>;
6881 type 6881 type = "passive";
6882 }; 6882 };
6883 6883
6884 trip-point1 { 6884 trip-point1 {
6885 tempe 6885 temperature = <95000>;
6886 hyste 6886 hysteresis = <2000>;
6887 type 6887 type = "passive";
6888 }; 6888 };
6889 6889
6890 cpu-critical 6890 cpu-critical {
6891 tempe 6891 temperature = <110000>;
6892 hyste 6892 hysteresis = <1000>;
6893 type 6893 type = "critical";
6894 }; 6894 };
6895 }; 6895 };
6896 }; 6896 };
6897 6897
6898 cpu1-3-btm-thermal { 6898 cpu1-3-btm-thermal {
6899 polling-delay-passive 6899 polling-delay-passive = <250>;
6900 6900
6901 thermal-sensors = <&t 6901 thermal-sensors = <&tsens1 8>;
6902 6902
6903 trips { 6903 trips {
6904 trip-point0 { 6904 trip-point0 {
6905 tempe 6905 temperature = <90000>;
6906 hyste 6906 hysteresis = <2000>;
6907 type 6907 type = "passive";
6908 }; 6908 };
6909 6909
6910 trip-point1 { 6910 trip-point1 {
6911 tempe 6911 temperature = <95000>;
6912 hyste 6912 hysteresis = <2000>;
6913 type 6913 type = "passive";
6914 }; 6914 };
6915 6915
6916 cpu-critical 6916 cpu-critical {
6917 tempe 6917 temperature = <110000>;
6918 hyste 6918 hysteresis = <1000>;
6919 type 6919 type = "critical";
6920 }; 6920 };
6921 }; 6921 };
6922 }; 6922 };
6923 6923
6924 cpuss1-top-thermal { 6924 cpuss1-top-thermal {
6925 thermal-sensors = <&t 6925 thermal-sensors = <&tsens1 9>;
6926 6926
6927 trips { 6927 trips {
6928 trip-point0 { 6928 trip-point0 {
6929 tempe 6929 temperature = <90000>;
6930 hyste 6930 hysteresis = <2000>;
6931 type 6931 type = "hot";
6932 }; 6932 };
6933 6933
6934 cpuss2-critic 6934 cpuss2-critical {
6935 tempe 6935 temperature = <125000>;
6936 hyste 6936 hysteresis = <0>;
6937 type 6937 type = "critical";
6938 }; 6938 };
6939 }; 6939 };
6940 }; 6940 };
6941 6941
6942 cpuss1-btm-thermal { 6942 cpuss1-btm-thermal {
6943 thermal-sensors = <&t 6943 thermal-sensors = <&tsens1 10>;
6944 6944
6945 trips { 6945 trips {
6946 trip-point0 { 6946 trip-point0 {
6947 tempe 6947 temperature = <90000>;
6948 hyste 6948 hysteresis = <2000>;
6949 type 6949 type = "hot";
6950 }; 6950 };
6951 6951
6952 cpuss2-critic 6952 cpuss2-critical {
6953 tempe 6953 temperature = <125000>;
6954 hyste 6954 hysteresis = <0>;
6955 type 6955 type = "critical";
6956 }; 6956 };
6957 }; 6957 };
6958 }; 6958 };
6959 6959
6960 aoss2-thermal { 6960 aoss2-thermal {
6961 thermal-sensors = <&t 6961 thermal-sensors = <&tsens2 0>;
6962 6962
6963 trips { 6963 trips {
6964 trip-point0 { 6964 trip-point0 {
6965 tempe 6965 temperature = <90000>;
6966 hyste 6966 hysteresis = <2000>;
6967 type 6967 type = "hot";
6968 }; 6968 };
6969 6969
6970 aoss0-critica 6970 aoss0-critical {
6971 tempe 6971 temperature = <125000>;
6972 hyste 6972 hysteresis = <0>;
6973 type 6973 type = "critical";
6974 }; 6974 };
6975 }; 6975 };
6976 }; 6976 };
6977 6977
6978 cpu2-0-top-thermal { 6978 cpu2-0-top-thermal {
6979 polling-delay-passive 6979 polling-delay-passive = <250>;
6980 6980
6981 thermal-sensors = <&t 6981 thermal-sensors = <&tsens2 1>;
6982 6982
6983 trips { 6983 trips {
6984 trip-point0 { 6984 trip-point0 {
6985 tempe 6985 temperature = <90000>;
6986 hyste 6986 hysteresis = <2000>;
6987 type 6987 type = "passive";
6988 }; 6988 };
6989 6989
6990 trip-point1 { 6990 trip-point1 {
6991 tempe 6991 temperature = <95000>;
6992 hyste 6992 hysteresis = <2000>;
6993 type 6993 type = "passive";
6994 }; 6994 };
6995 6995
6996 cpu-critical 6996 cpu-critical {
6997 tempe 6997 temperature = <110000>;
6998 hyste 6998 hysteresis = <1000>;
6999 type 6999 type = "critical";
7000 }; 7000 };
7001 }; 7001 };
7002 }; 7002 };
7003 7003
7004 cpu2-0-btm-thermal { 7004 cpu2-0-btm-thermal {
7005 polling-delay-passive 7005 polling-delay-passive = <250>;
7006 7006
7007 thermal-sensors = <&t 7007 thermal-sensors = <&tsens2 2>;
7008 7008
7009 trips { 7009 trips {
7010 trip-point0 { 7010 trip-point0 {
7011 tempe 7011 temperature = <90000>;
7012 hyste 7012 hysteresis = <2000>;
7013 type 7013 type = "passive";
7014 }; 7014 };
7015 7015
7016 trip-point1 { 7016 trip-point1 {
7017 tempe 7017 temperature = <95000>;
7018 hyste 7018 hysteresis = <2000>;
7019 type 7019 type = "passive";
7020 }; 7020 };
7021 7021
7022 cpu-critical 7022 cpu-critical {
7023 tempe 7023 temperature = <110000>;
7024 hyste 7024 hysteresis = <1000>;
7025 type 7025 type = "critical";
7026 }; 7026 };
7027 }; 7027 };
7028 }; 7028 };
7029 7029
7030 cpu2-1-top-thermal { 7030 cpu2-1-top-thermal {
7031 polling-delay-passive 7031 polling-delay-passive = <250>;
7032 7032
7033 thermal-sensors = <&t 7033 thermal-sensors = <&tsens2 3>;
7034 7034
7035 trips { 7035 trips {
7036 trip-point0 { 7036 trip-point0 {
7037 tempe 7037 temperature = <90000>;
7038 hyste 7038 hysteresis = <2000>;
7039 type 7039 type = "passive";
7040 }; 7040 };
7041 7041
7042 trip-point1 { 7042 trip-point1 {
7043 tempe 7043 temperature = <95000>;
7044 hyste 7044 hysteresis = <2000>;
7045 type 7045 type = "passive";
7046 }; 7046 };
7047 7047
7048 cpu-critical 7048 cpu-critical {
7049 tempe 7049 temperature = <110000>;
7050 hyste 7050 hysteresis = <1000>;
7051 type 7051 type = "critical";
7052 }; 7052 };
7053 }; 7053 };
7054 }; 7054 };
7055 7055
7056 cpu2-1-btm-thermal { 7056 cpu2-1-btm-thermal {
7057 polling-delay-passive 7057 polling-delay-passive = <250>;
7058 7058
7059 thermal-sensors = <&t 7059 thermal-sensors = <&tsens2 4>;
7060 7060
7061 trips { 7061 trips {
7062 trip-point0 { 7062 trip-point0 {
7063 tempe 7063 temperature = <90000>;
7064 hyste 7064 hysteresis = <2000>;
7065 type 7065 type = "passive";
7066 }; 7066 };
7067 7067
7068 trip-point1 { 7068 trip-point1 {
7069 tempe 7069 temperature = <95000>;
7070 hyste 7070 hysteresis = <2000>;
7071 type 7071 type = "passive";
7072 }; 7072 };
7073 7073
7074 cpu-critical 7074 cpu-critical {
7075 tempe 7075 temperature = <110000>;
7076 hyste 7076 hysteresis = <1000>;
7077 type 7077 type = "critical";
7078 }; 7078 };
7079 }; 7079 };
7080 }; 7080 };
7081 7081
7082 cpu2-2-top-thermal { 7082 cpu2-2-top-thermal {
7083 polling-delay-passive 7083 polling-delay-passive = <250>;
7084 7084
7085 thermal-sensors = <&t 7085 thermal-sensors = <&tsens2 5>;
7086 7086
7087 trips { 7087 trips {
7088 trip-point0 { 7088 trip-point0 {
7089 tempe 7089 temperature = <90000>;
7090 hyste 7090 hysteresis = <2000>;
7091 type 7091 type = "passive";
7092 }; 7092 };
7093 7093
7094 trip-point1 { 7094 trip-point1 {
7095 tempe 7095 temperature = <95000>;
7096 hyste 7096 hysteresis = <2000>;
7097 type 7097 type = "passive";
7098 }; 7098 };
7099 7099
7100 cpu-critical 7100 cpu-critical {
7101 tempe 7101 temperature = <110000>;
7102 hyste 7102 hysteresis = <1000>;
7103 type 7103 type = "critical";
7104 }; 7104 };
7105 }; 7105 };
7106 }; 7106 };
7107 7107
7108 cpu2-2-btm-thermal { 7108 cpu2-2-btm-thermal {
7109 polling-delay-passive 7109 polling-delay-passive = <250>;
7110 7110
7111 thermal-sensors = <&t 7111 thermal-sensors = <&tsens2 6>;
7112 7112
7113 trips { 7113 trips {
7114 trip-point0 { 7114 trip-point0 {
7115 tempe 7115 temperature = <90000>;
7116 hyste 7116 hysteresis = <2000>;
7117 type 7117 type = "passive";
7118 }; 7118 };
7119 7119
7120 trip-point1 { 7120 trip-point1 {
7121 tempe 7121 temperature = <95000>;
7122 hyste 7122 hysteresis = <2000>;
7123 type 7123 type = "passive";
7124 }; 7124 };
7125 7125
7126 cpu-critical 7126 cpu-critical {
7127 tempe 7127 temperature = <110000>;
7128 hyste 7128 hysteresis = <1000>;
7129 type 7129 type = "critical";
7130 }; 7130 };
7131 }; 7131 };
7132 }; 7132 };
7133 7133
7134 cpu2-3-top-thermal { 7134 cpu2-3-top-thermal {
7135 polling-delay-passive 7135 polling-delay-passive = <250>;
7136 7136
7137 thermal-sensors = <&t 7137 thermal-sensors = <&tsens2 7>;
7138 7138
7139 trips { 7139 trips {
7140 trip-point0 { 7140 trip-point0 {
7141 tempe 7141 temperature = <90000>;
7142 hyste 7142 hysteresis = <2000>;
7143 type 7143 type = "passive";
7144 }; 7144 };
7145 7145
7146 trip-point1 { 7146 trip-point1 {
7147 tempe 7147 temperature = <95000>;
7148 hyste 7148 hysteresis = <2000>;
7149 type 7149 type = "passive";
7150 }; 7150 };
7151 7151
7152 cpu-critical 7152 cpu-critical {
7153 tempe 7153 temperature = <110000>;
7154 hyste 7154 hysteresis = <1000>;
7155 type 7155 type = "critical";
7156 }; 7156 };
7157 }; 7157 };
7158 }; 7158 };
7159 7159
7160 cpu2-3-btm-thermal { 7160 cpu2-3-btm-thermal {
7161 polling-delay-passive 7161 polling-delay-passive = <250>;
7162 7162
7163 thermal-sensors = <&t 7163 thermal-sensors = <&tsens2 8>;
7164 7164
7165 trips { 7165 trips {
7166 trip-point0 { 7166 trip-point0 {
7167 tempe 7167 temperature = <90000>;
7168 hyste 7168 hysteresis = <2000>;
7169 type 7169 type = "passive";
7170 }; 7170 };
7171 7171
7172 trip-point1 { 7172 trip-point1 {
7173 tempe 7173 temperature = <95000>;
7174 hyste 7174 hysteresis = <2000>;
7175 type 7175 type = "passive";
7176 }; 7176 };
7177 7177
7178 cpu-critical 7178 cpu-critical {
7179 tempe 7179 temperature = <110000>;
7180 hyste 7180 hysteresis = <1000>;
7181 type 7181 type = "critical";
7182 }; 7182 };
7183 }; 7183 };
7184 }; 7184 };
7185 7185
7186 cpuss2-top-thermal { 7186 cpuss2-top-thermal {
7187 thermal-sensors = <&t 7187 thermal-sensors = <&tsens2 9>;
7188 7188
7189 trips { 7189 trips {
7190 trip-point0 { 7190 trip-point0 {
7191 tempe 7191 temperature = <90000>;
7192 hyste 7192 hysteresis = <2000>;
7193 type 7193 type = "hot";
7194 }; 7194 };
7195 7195
7196 cpuss2-critic 7196 cpuss2-critical {
7197 tempe 7197 temperature = <125000>;
7198 hyste 7198 hysteresis = <0>;
7199 type 7199 type = "critical";
7200 }; 7200 };
7201 }; 7201 };
7202 }; 7202 };
7203 7203
7204 cpuss2-btm-thermal { 7204 cpuss2-btm-thermal {
7205 thermal-sensors = <&t 7205 thermal-sensors = <&tsens2 10>;
7206 7206
7207 trips { 7207 trips {
7208 trip-point0 { 7208 trip-point0 {
7209 tempe 7209 temperature = <90000>;
7210 hyste 7210 hysteresis = <2000>;
7211 type 7211 type = "hot";
7212 }; 7212 };
7213 7213
7214 cpuss2-critic 7214 cpuss2-critical {
7215 tempe 7215 temperature = <125000>;
7216 hyste 7216 hysteresis = <0>;
7217 type 7217 type = "critical";
7218 }; 7218 };
7219 }; 7219 };
7220 }; 7220 };
7221 7221
7222 aoss3-thermal { 7222 aoss3-thermal {
7223 thermal-sensors = <&t 7223 thermal-sensors = <&tsens3 0>;
7224 7224
7225 trips { 7225 trips {
7226 trip-point0 { 7226 trip-point0 {
7227 tempe 7227 temperature = <90000>;
7228 hyste 7228 hysteresis = <2000>;
7229 type 7229 type = "hot";
7230 }; 7230 };
7231 7231
7232 aoss0-critica 7232 aoss0-critical {
7233 tempe 7233 temperature = <125000>;
7234 hyste 7234 hysteresis = <0>;
7235 type 7235 type = "critical";
7236 }; 7236 };
7237 }; 7237 };
7238 }; 7238 };
7239 7239
7240 nsp0-thermal { 7240 nsp0-thermal {
7241 thermal-sensors = <&t 7241 thermal-sensors = <&tsens3 1>;
7242 7242
7243 trips { 7243 trips {
7244 trip-point0 { 7244 trip-point0 {
7245 tempe 7245 temperature = <90000>;
7246 hyste 7246 hysteresis = <2000>;
7247 type 7247 type = "hot";
7248 }; 7248 };
7249 7249
7250 nsp0-critical 7250 nsp0-critical {
7251 tempe 7251 temperature = <125000>;
7252 hyste 7252 hysteresis = <0>;
7253 type 7253 type = "critical";
7254 }; 7254 };
7255 }; 7255 };
7256 }; 7256 };
7257 7257
7258 nsp1-thermal { 7258 nsp1-thermal {
7259 thermal-sensors = <&t 7259 thermal-sensors = <&tsens3 2>;
7260 7260
7261 trips { 7261 trips {
7262 trip-point0 { 7262 trip-point0 {
7263 tempe 7263 temperature = <90000>;
7264 hyste 7264 hysteresis = <2000>;
7265 type 7265 type = "hot";
7266 }; 7266 };
7267 7267
7268 nsp1-critical 7268 nsp1-critical {
7269 tempe 7269 temperature = <125000>;
7270 hyste 7270 hysteresis = <0>;
7271 type 7271 type = "critical";
7272 }; 7272 };
7273 }; 7273 };
7274 }; 7274 };
7275 7275
7276 nsp2-thermal { 7276 nsp2-thermal {
7277 thermal-sensors = <&t 7277 thermal-sensors = <&tsens3 3>;
7278 7278
7279 trips { 7279 trips {
7280 trip-point0 { 7280 trip-point0 {
7281 tempe 7281 temperature = <90000>;
7282 hyste 7282 hysteresis = <2000>;
7283 type 7283 type = "hot";
7284 }; 7284 };
7285 7285
7286 nsp2-critical 7286 nsp2-critical {
7287 tempe 7287 temperature = <125000>;
7288 hyste 7288 hysteresis = <0>;
7289 type 7289 type = "critical";
7290 }; 7290 };
7291 }; 7291 };
7292 }; 7292 };
7293 7293
7294 nsp3-thermal { 7294 nsp3-thermal {
7295 thermal-sensors = <&t 7295 thermal-sensors = <&tsens3 4>;
7296 7296
7297 trips { 7297 trips {
7298 trip-point0 { 7298 trip-point0 {
7299 tempe 7299 temperature = <90000>;
7300 hyste 7300 hysteresis = <2000>;
7301 type 7301 type = "hot";
7302 }; 7302 };
7303 7303
7304 nsp3-critical 7304 nsp3-critical {
7305 tempe 7305 temperature = <125000>;
7306 hyste 7306 hysteresis = <0>;
7307 type 7307 type = "critical";
7308 }; 7308 };
7309 }; 7309 };
7310 }; 7310 };
7311 7311
7312 gpuss-0-thermal { 7312 gpuss-0-thermal {
7313 polling-delay-passive 7313 polling-delay-passive = <10>;
7314 7314
7315 thermal-sensors = <&t 7315 thermal-sensors = <&tsens3 5>;
7316 7316
7317 trips { 7317 trips {
7318 trip-point0 { 7318 trip-point0 {
7319 tempe 7319 temperature = <85000>;
7320 hyste 7320 hysteresis = <1000>;
7321 type 7321 type = "passive";
7322 }; 7322 };
7323 7323
7324 trip-point1 { 7324 trip-point1 {
7325 tempe 7325 temperature = <90000>;
7326 hyste 7326 hysteresis = <1000>;
7327 type 7327 type = "hot";
7328 }; 7328 };
7329 7329
7330 trip-point2 { 7330 trip-point2 {
7331 tempe 7331 temperature = <125000>;
7332 hyste 7332 hysteresis = <1000>;
7333 type 7333 type = "critical";
7334 }; 7334 };
7335 }; 7335 };
7336 }; 7336 };
7337 7337
7338 gpuss-1-thermal { 7338 gpuss-1-thermal {
7339 polling-delay-passive 7339 polling-delay-passive = <10>;
7340 7340
7341 thermal-sensors = <&t 7341 thermal-sensors = <&tsens3 6>;
7342 7342
7343 trips { 7343 trips {
7344 trip-point0 { 7344 trip-point0 {
7345 tempe 7345 temperature = <85000>;
7346 hyste 7346 hysteresis = <1000>;
7347 type 7347 type = "passive";
7348 }; 7348 };
7349 7349
7350 trip-point1 { 7350 trip-point1 {
7351 tempe 7351 temperature = <90000>;
7352 hyste 7352 hysteresis = <1000>;
7353 type 7353 type = "hot";
7354 }; 7354 };
7355 7355
7356 trip-point2 { 7356 trip-point2 {
7357 tempe 7357 temperature = <125000>;
7358 hyste 7358 hysteresis = <1000>;
7359 type 7359 type = "critical";
7360 }; 7360 };
7361 }; 7361 };
7362 }; 7362 };
7363 7363
7364 gpuss-2-thermal { 7364 gpuss-2-thermal {
7365 polling-delay-passive 7365 polling-delay-passive = <10>;
7366 7366
7367 thermal-sensors = <&t 7367 thermal-sensors = <&tsens3 7>;
7368 7368
7369 trips { 7369 trips {
7370 trip-point0 { 7370 trip-point0 {
7371 tempe 7371 temperature = <85000>;
7372 hyste 7372 hysteresis = <1000>;
7373 type 7373 type = "passive";
7374 }; 7374 };
7375 7375
7376 trip-point1 { 7376 trip-point1 {
7377 tempe 7377 temperature = <90000>;
7378 hyste 7378 hysteresis = <1000>;
7379 type 7379 type = "hot";
7380 }; 7380 };
7381 7381
7382 trip-point2 { 7382 trip-point2 {
7383 tempe 7383 temperature = <125000>;
7384 hyste 7384 hysteresis = <1000>;
7385 type 7385 type = "critical";
7386 }; 7386 };
7387 }; 7387 };
7388 }; 7388 };
7389 7389
7390 gpuss-3-thermal { 7390 gpuss-3-thermal {
7391 polling-delay-passive 7391 polling-delay-passive = <10>;
7392 7392
7393 thermal-sensors = <&t 7393 thermal-sensors = <&tsens3 8>;
7394 7394
7395 trips { 7395 trips {
7396 trip-point0 { 7396 trip-point0 {
7397 tempe 7397 temperature = <85000>;
7398 hyste 7398 hysteresis = <1000>;
7399 type 7399 type = "passive";
7400 }; 7400 };
7401 7401
7402 trip-point1 { 7402 trip-point1 {
7403 tempe 7403 temperature = <90000>;
7404 hyste 7404 hysteresis = <1000>;
7405 type 7405 type = "hot";
7406 }; 7406 };
7407 7407
7408 trip-point2 { 7408 trip-point2 {
7409 tempe 7409 temperature = <125000>;
7410 hyste 7410 hysteresis = <1000>;
7411 type 7411 type = "critical";
7412 }; 7412 };
7413 }; 7413 };
7414 }; 7414 };
7415 7415
7416 gpuss-4-thermal { 7416 gpuss-4-thermal {
7417 polling-delay-passive 7417 polling-delay-passive = <10>;
7418 7418
7419 thermal-sensors = <&t 7419 thermal-sensors = <&tsens3 9>;
7420 7420
7421 trips { 7421 trips {
7422 trip-point0 { 7422 trip-point0 {
7423 tempe 7423 temperature = <85000>;
7424 hyste 7424 hysteresis = <1000>;
7425 type 7425 type = "passive";
7426 }; 7426 };
7427 7427
7428 trip-point1 { 7428 trip-point1 {
7429 tempe 7429 temperature = <90000>;
7430 hyste 7430 hysteresis = <1000>;
7431 type 7431 type = "hot";
7432 }; 7432 };
7433 7433
7434 trip-point2 { 7434 trip-point2 {
7435 tempe 7435 temperature = <125000>;
7436 hyste 7436 hysteresis = <1000>;
7437 type 7437 type = "critical";
7438 }; 7438 };
7439 }; 7439 };
7440 }; 7440 };
7441 7441
7442 gpuss-5-thermal { 7442 gpuss-5-thermal {
7443 polling-delay-passive 7443 polling-delay-passive = <10>;
7444 7444
7445 thermal-sensors = <&t 7445 thermal-sensors = <&tsens3 10>;
7446 7446
7447 trips { 7447 trips {
7448 trip-point0 { 7448 trip-point0 {
7449 tempe 7449 temperature = <85000>;
7450 hyste 7450 hysteresis = <1000>;
7451 type 7451 type = "passive";
7452 }; 7452 };
7453 7453
7454 trip-point1 { 7454 trip-point1 {
7455 tempe 7455 temperature = <90000>;
7456 hyste 7456 hysteresis = <1000>;
7457 type 7457 type = "hot";
7458 }; 7458 };
7459 7459
7460 trip-point2 { 7460 trip-point2 {
7461 tempe 7461 temperature = <125000>;
7462 hyste 7462 hysteresis = <1000>;
7463 type 7463 type = "critical";
7464 }; 7464 };
7465 }; 7465 };
7466 }; 7466 };
7467 7467
7468 gpuss-6-thermal { 7468 gpuss-6-thermal {
7469 polling-delay-passive 7469 polling-delay-passive = <10>;
7470 7470
7471 thermal-sensors = <&t 7471 thermal-sensors = <&tsens3 11>;
7472 7472
7473 trips { 7473 trips {
7474 trip-point0 { 7474 trip-point0 {
7475 tempe 7475 temperature = <85000>;
7476 hyste 7476 hysteresis = <1000>;
7477 type 7477 type = "passive";
7478 }; 7478 };
7479 7479
7480 trip-point1 { 7480 trip-point1 {
7481 tempe 7481 temperature = <90000>;
7482 hyste 7482 hysteresis = <1000>;
7483 type 7483 type = "hot";
7484 }; 7484 };
7485 7485
7486 trip-point2 { 7486 trip-point2 {
7487 tempe 7487 temperature = <125000>;
7488 hyste 7488 hysteresis = <1000>;
7489 type 7489 type = "critical";
7490 }; 7490 };
7491 }; 7491 };
7492 }; 7492 };
7493 7493
7494 gpuss-7-thermal { 7494 gpuss-7-thermal {
7495 polling-delay-passive 7495 polling-delay-passive = <10>;
7496 7496
7497 thermal-sensors = <&t 7497 thermal-sensors = <&tsens3 12>;
7498 7498
7499 trips { 7499 trips {
7500 trip-point0 { 7500 trip-point0 {
7501 tempe 7501 temperature = <85000>;
7502 hyste 7502 hysteresis = <1000>;
7503 type 7503 type = "passive";
7504 }; 7504 };
7505 7505
7506 trip-point1 { 7506 trip-point1 {
7507 tempe 7507 temperature = <90000>;
7508 hyste 7508 hysteresis = <1000>;
7509 type 7509 type = "hot";
7510 }; 7510 };
7511 7511
7512 trip-point2 { 7512 trip-point2 {
7513 tempe 7513 temperature = <125000>;
7514 hyste 7514 hysteresis = <1000>;
7515 type 7515 type = "critical";
7516 }; 7516 };
7517 }; 7517 };
7518 }; 7518 };
7519 7519
7520 camera0-thermal { 7520 camera0-thermal {
7521 thermal-sensors = <&t 7521 thermal-sensors = <&tsens3 13>;
7522 7522
7523 trips { 7523 trips {
7524 trip-point0 { 7524 trip-point0 {
7525 tempe 7525 temperature = <90000>;
7526 hyste 7526 hysteresis = <2000>;
7527 type 7527 type = "hot";
7528 }; 7528 };
7529 7529
7530 camera0-criti 7530 camera0-critical {
7531 tempe 7531 temperature = <115000>;
7532 hyste 7532 hysteresis = <0>;
7533 type 7533 type = "critical";
7534 }; 7534 };
7535 }; 7535 };
7536 }; 7536 };
7537 7537
7538 camera1-thermal { 7538 camera1-thermal {
7539 thermal-sensors = <&t 7539 thermal-sensors = <&tsens3 14>;
7540 7540
7541 trips { 7541 trips {
7542 trip-point0 { 7542 trip-point0 {
7543 tempe 7543 temperature = <90000>;
7544 hyste 7544 hysteresis = <2000>;
7545 type 7545 type = "hot";
7546 }; 7546 };
7547 7547
7548 camera0-criti 7548 camera0-critical {
7549 tempe 7549 temperature = <115000>;
7550 hyste 7550 hysteresis = <0>;
7551 type 7551 type = "critical";
7552 }; 7552 };
7553 }; 7553 };
7554 }; 7554 };
7555 }; 7555 };
7556 }; 7556 };
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