1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * Copyright 2020, Compass Electronics Group, 3 * Copyright 2020, Compass Electronics Group, LLC
4 */ 4 */
5 5
6 #include <dt-bindings/gpio/gpio.h> 6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/clock/versaclock.h> !! 7 #include <dt-bindings/clk/versaclock.h>
8 8
9 / { 9 / {
10 memory@48000000 { 10 memory@48000000 {
11 device_type = "memory"; 11 device_type = "memory";
12 /* first 128MB is reserved for 12 /* first 128MB is reserved for secure area. */
13 reg = <0x0 0x48000000 0x0 0x78 13 reg = <0x0 0x48000000 0x0 0x78000000>;
14 }; 14 };
15 15
16 osc_32k: osc_32k { 16 osc_32k: osc_32k {
17 compatible = "fixed-clock"; 17 compatible = "fixed-clock";
18 #clock-cells = <0>; 18 #clock-cells = <0>;
19 clock-frequency = <32768>; 19 clock-frequency = <32768>;
20 clock-output-names = "osc_32k" 20 clock-output-names = "osc_32k";
21 }; 21 };
22 22
23 reg_1p8v: regulator-1p8v { !! 23 reg_1p8v: regulator0 {
24 compatible = "regulator-fixed" 24 compatible = "regulator-fixed";
25 regulator-name = "fixed-1.8V"; 25 regulator-name = "fixed-1.8V";
26 regulator-min-microvolt = <180 26 regulator-min-microvolt = <1800000>;
27 regulator-max-microvolt = <180 27 regulator-max-microvolt = <1800000>;
28 regulator-boot-on; 28 regulator-boot-on;
29 regulator-always-on; 29 regulator-always-on;
30 }; 30 };
31 31
32 reg_3p3v: regulator-3p3v { !! 32 reg_3p3v: regulator1 {
33 compatible = "regulator-fixed" 33 compatible = "regulator-fixed";
34 regulator-name = "fixed-3.3V"; 34 regulator-name = "fixed-3.3V";
35 regulator-min-microvolt = <330 35 regulator-min-microvolt = <3300000>;
36 regulator-max-microvolt = <330 36 regulator-max-microvolt = <3300000>;
37 regulator-boot-on; 37 regulator-boot-on;
38 regulator-always-on; 38 regulator-always-on;
39 }; 39 };
40 40
41 wlan_pwrseq: wlan_pwrseq { 41 wlan_pwrseq: wlan_pwrseq {
42 compatible = "mmc-pwrseq-simpl 42 compatible = "mmc-pwrseq-simple";
43 reset-gpios = <&pca9654 1 GPIO 43 reset-gpios = <&pca9654 1 GPIO_ACTIVE_LOW>;
44 clocks = <&osc_32k>; 44 clocks = <&osc_32k>;
45 clock-names = "ext_clock"; 45 clock-names = "ext_clock";
46 post-power-on-delay-ms = <80>; 46 post-power-on-delay-ms = <80>;
47 }; 47 };
48 }; 48 };
49 49
50 &avb { 50 &avb {
51 pinctrl-0 = <&avb_pins>; 51 pinctrl-0 = <&avb_pins>;
52 pinctrl-names = "default"; 52 pinctrl-names = "default";
53 phy-mode = "rgmii-rxid"; 53 phy-mode = "rgmii-rxid";
54 phy-handle = <&phy0>; 54 phy-handle = <&phy0>;
55 rx-internal-delay-ps = <1800>; 55 rx-internal-delay-ps = <1800>;
56 tx-internal-delay-ps = <2000>; 56 tx-internal-delay-ps = <2000>;
57 clocks = <&cpg CPG_MOD 812>, <&versacl 57 clocks = <&cpg CPG_MOD 812>, <&versaclock5 4>;
58 clock-names = "fck", "refclk"; 58 clock-names = "fck", "refclk";
59 status = "okay"; 59 status = "okay";
60 60
61 phy0: ethernet-phy@0 { 61 phy0: ethernet-phy@0 {
62 compatible = "ethernet-phy-id0 <<
63 "ethernet-phy-iee <<
64 reg = <0>; 62 reg = <0>;
65 interrupt-parent = <&gpio2>; 63 interrupt-parent = <&gpio2>;
66 interrupts = <11 IRQ_TYPE_LEVE 64 interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
67 reset-gpios = <&gpio2 10 GPIO_ 65 reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
68 }; 66 };
69 }; 67 };
70 68
71 &extal_clk { 69 &extal_clk {
72 clock-frequency = <16666666>; 70 clock-frequency = <16666666>;
73 }; 71 };
74 72
75 &extalr_clk { 73 &extalr_clk {
76 clock-frequency = <32768>; 74 clock-frequency = <32768>;
77 }; 75 };
78 76
79 &gpio6 { 77 &gpio6 {
80 usb-hub-reset-hog { !! 78 usb_hub_reset {
81 gpio-hog; 79 gpio-hog;
82 gpios = <10 GPIO_ACTIVE_HIGH>; 80 gpios = <10 GPIO_ACTIVE_HIGH>;
83 output-high; 81 output-high;
84 line-name = "usb-hub-reset"; 82 line-name = "usb-hub-reset";
85 }; 83 };
86 }; 84 };
87 85
88 &hscif0 { 86 &hscif0 {
89 pinctrl-0 = <&hscif0_pins>; 87 pinctrl-0 = <&hscif0_pins>;
90 pinctrl-names = "default"; 88 pinctrl-names = "default";
91 uart-has-rtscts; 89 uart-has-rtscts;
92 status = "okay"; 90 status = "okay";
93 91
94 bluetooth { 92 bluetooth {
95 compatible = "brcm,bcm43438-bt 93 compatible = "brcm,bcm43438-bt";
96 shutdown-gpios = <&pca9654 2 G 94 shutdown-gpios = <&pca9654 2 GPIO_ACTIVE_HIGH>;
97 host-wakeup-gpios = <&gpio1 28 95 host-wakeup-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
98 device-wakeup-gpios = <&pca965 96 device-wakeup-gpios = <&pca9654 5 GPIO_ACTIVE_HIGH>;
99 clocks = <&osc_32k>; 97 clocks = <&osc_32k>;
100 clock-names = "extclk"; 98 clock-names = "extclk";
101 max-speed = <4000000>; 99 max-speed = <4000000>;
102 }; 100 };
103 }; 101 };
104 102
105 &hscif2 { 103 &hscif2 {
106 status = "okay"; 104 status = "okay";
107 pinctrl-0 = <&hscif2_pins>; 105 pinctrl-0 = <&hscif2_pins>;
108 pinctrl-names = "default"; 106 pinctrl-names = "default";
109 }; 107 };
110 108
111 &i2c4 { 109 &i2c4 {
112 status = "okay"; 110 status = "okay";
113 clock-frequency = <100000>; 111 clock-frequency = <100000>;
114 112
115 pca9654: gpio@20 { 113 pca9654: gpio@20 {
116 compatible = "onnn,pca9654"; 114 compatible = "onnn,pca9654";
117 reg = <0x20>; 115 reg = <0x20>;
118 gpio-controller; 116 gpio-controller;
119 #gpio-cells = <2>; 117 #gpio-cells = <2>;
120 gpio-line-names = 118 gpio-line-names =
121 "i2c4_20_0", 119 "i2c4_20_0",
122 "wl_reg_on", 120 "wl_reg_on",
123 "bt_reg_on", 121 "bt_reg_on",
124 "i2c4_20_3", 122 "i2c4_20_3",
125 "i2c4_20_4", 123 "i2c4_20_4",
126 "bt_dev_wake", 124 "bt_dev_wake",
127 "i2c4_20_6", 125 "i2c4_20_6",
128 "i2c4_20_7"; 126 "i2c4_20_7";
129 }; 127 };
130 128
131 pca9654_lte: gpio@21 { 129 pca9654_lte: gpio@21 {
132 compatible = "onnn,pca9654"; 130 compatible = "onnn,pca9654";
133 reg = <0x21>; 131 reg = <0x21>;
134 interrupt-parent = <&gpio5>; 132 interrupt-parent = <&gpio5>;
135 interrupts = <25 IRQ_TYPE_EDGE 133 interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
136 interrupt-controller; 134 interrupt-controller;
137 #interrupt-cells = <2>; 135 #interrupt-cells = <2>;
138 gpio-controller; 136 gpio-controller;
139 #gpio-cells = <2>; 137 #gpio-cells = <2>;
140 gpio-line-names = 138 gpio-line-names =
141 "i2c4_21_0", 139 "i2c4_21_0",
142 "zoe_pwr_on", 140 "zoe_pwr_on",
143 "zoe_extint", 141 "zoe_extint",
144 "zoe_reset_n", 142 "zoe_reset_n",
145 "sara_reset", 143 "sara_reset",
146 "i2c4_21_5", 144 "i2c4_21_5",
147 "sara_pwr_off", 145 "sara_pwr_off",
148 "sara_networking_statu 146 "sara_networking_status";
149 }; 147 };
150 148
151 eeprom@50 { 149 eeprom@50 {
152 compatible = "microchip,24c64" 150 compatible = "microchip,24c64", "atmel,24c64";
153 pagesize = <32>; 151 pagesize = <32>;
154 read-only; /* Manufacturi 152 read-only; /* Manufacturing EEPROM programmed at factory */
155 reg = <0x50>; 153 reg = <0x50>;
156 }; 154 };
157 155
158 rtc@51 { 156 rtc@51 {
159 compatible = "nxp,pcf85263"; 157 compatible = "nxp,pcf85263";
160 reg = <0x51>; 158 reg = <0x51>;
161 }; 159 };
162 160
163 versaclock5: versaclock_som@6a { 161 versaclock5: versaclock_som@6a {
164 compatible = "idt,5p49v6965"; 162 compatible = "idt,5p49v6965";
165 reg = <0x6a>; 163 reg = <0x6a>;
166 #clock-cells = <1>; 164 #clock-cells = <1>;
167 clocks = <&x304_clk>; 165 clocks = <&x304_clk>;
168 clock-names = "xin"; 166 clock-names = "xin";
169 /* du_dotclkin0, du_dotclkin2, 167 /* du_dotclkin0, du_dotclkin2, usb_extal, avb_txcrefclk */
170 assigned-clocks = <&versaclock 168 assigned-clocks = <&versaclock5 1>,
171 <&versacloc 169 <&versaclock5 2>,
172 <&versacloc 170 <&versaclock5 3>,
173 <&versacloc 171 <&versaclock5 4>;
174 172
175 assigned-clock-rates = <333333 173 assigned-clock-rates = <33333333>, <33333333>, <50000000>, <125000000>;
176 174
177 OUT1 { 175 OUT1 {
178 idt,mode = <VC5_CMOS>; 176 idt,mode = <VC5_CMOS>;
179 idt,voltage-microvolt 177 idt,voltage-microvolt = <1800000>;
180 idt,slew-percent = <10 178 idt,slew-percent = <100>;
181 }; 179 };
182 180
183 OUT2 { 181 OUT2 {
184 idt,mode = <VC5_CMOS>; 182 idt,mode = <VC5_CMOS>;
185 idt,voltage-microvolt 183 idt,voltage-microvolt = <1800000>;
186 idt,slew-percent = <10 184 idt,slew-percent = <100>;
187 }; 185 };
188 186
189 OUT3 { 187 OUT3 {
190 idt,mode = <VC5_CMOS>; 188 idt,mode = <VC5_CMOS>;
191 idt,voltage-microvolt 189 idt,voltage-microvolt = <1800000>;
192 idt,slew-percent = <10 190 idt,slew-percent = <100>;
193 }; 191 };
194 192
195 OUT4 { 193 OUT4 {
196 idt,mode = <VC5_CMOS>; 194 idt,mode = <VC5_CMOS>;
197 idt,voltage-microvolt 195 idt,voltage-microvolt = <3300000>;
198 idt,slew-percent = <10 196 idt,slew-percent = <100>;
199 }; 197 };
200 }; 198 };
201 }; 199 };
202 200
203 &pfc { 201 &pfc {
204 pinctrl-0 = <&scif_clk_pins>; 202 pinctrl-0 = <&scif_clk_pins>;
205 pinctrl-names = "default"; 203 pinctrl-names = "default";
206 204
207 avb_pins: avb { 205 avb_pins: avb {
208 mux { 206 mux {
209 groups = "avb_link", " 207 groups = "avb_link", "avb_mdio", "avb_mii";
210 function = "avb"; 208 function = "avb";
211 }; 209 };
212 210
213 pins_mdio { 211 pins_mdio {
214 groups = "avb_mdio"; 212 groups = "avb_mdio";
215 drive-strength = <24>; 213 drive-strength = <24>;
216 }; 214 };
217 215
218 pins_mii_tx { 216 pins_mii_tx {
219 pins = "PIN_AVB_TX_CTL 217 pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0",
220 "PIN_AVB_TD1", 218 "PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3";
221 drive-strength = <12>; 219 drive-strength = <12>;
222 }; 220 };
223 }; 221 };
224 222
225 scif2_pins: scif2 { 223 scif2_pins: scif2 {
226 groups = "scif2_data_a"; 224 groups = "scif2_data_a";
227 function = "scif2"; 225 function = "scif2";
228 }; 226 };
229 227
230 hscif0_pins: hscif0 { 228 hscif0_pins: hscif0 {
231 groups = "hscif0_data", "hscif 229 groups = "hscif0_data", "hscif0_ctrl";
232 function = "hscif0"; 230 function = "hscif0";
233 }; 231 };
234 232
235 hscif1_pins: hscif1 { 233 hscif1_pins: hscif1 {
236 groups = "hscif1_data_a", "hsc 234 groups = "hscif1_data_a", "hscif1_ctrl_a";
237 function = "hscif1"; 235 function = "hscif1";
238 }; 236 };
239 237
240 hscif2_pins: hscif2 { 238 hscif2_pins: hscif2 {
241 groups = "hscif2_data_a"; 239 groups = "hscif2_data_a";
242 function = "hscif2"; 240 function = "hscif2";
243 }; 241 };
244 242
245 scif0_pins: scif0 { 243 scif0_pins: scif0 {
246 groups = "scif0_data"; 244 groups = "scif0_data";
247 function = "scif0"; 245 function = "scif0";
248 }; 246 };
249 247
250 scif5_pins: scif5 { 248 scif5_pins: scif5 {
251 groups = "scif5_data_a"; 249 groups = "scif5_data_a";
252 function = "scif5"; 250 function = "scif5";
253 }; 251 };
254 252
255 scif_clk_pins: scif_clk { 253 scif_clk_pins: scif_clk {
256 groups = "scif_clk_a"; 254 groups = "scif_clk_a";
257 function = "scif_clk"; 255 function = "scif_clk";
258 }; 256 };
259 257
260 i2c0_pins: i2c0 { 258 i2c0_pins: i2c0 {
261 groups = "i2c0"; 259 groups = "i2c0";
262 function = "i2c0"; 260 function = "i2c0";
263 }; 261 };
264 262
265 sdhi2_pins: sd2 { 263 sdhi2_pins: sd2 {
266 groups = "sdhi2_data4", "sdhi2 264 groups = "sdhi2_data4", "sdhi2_ctrl";
267 function = "sdhi2"; 265 function = "sdhi2";
268 power-source = <1800>; 266 power-source = <1800>;
269 }; 267 };
270 268
271 sdhi3_pins: sd3 { 269 sdhi3_pins: sd3 {
272 groups = "sdhi3_data8", "sdhi3 270 groups = "sdhi3_data8", "sdhi3_ctrl", "sdhi3_ds";
273 function = "sdhi3"; 271 function = "sdhi3";
274 power-source = <1800>; 272 power-source = <1800>;
275 }; 273 };
276 }; 274 };
277 275
278 &scif_clk { 276 &scif_clk {
279 clock-frequency = <14745600>; 277 clock-frequency = <14745600>;
280 }; 278 };
281 279
282 &scif2 { 280 &scif2 {
283 pinctrl-0 = <&scif2_pins>; 281 pinctrl-0 = <&scif2_pins>;
284 pinctrl-names = "default"; 282 pinctrl-names = "default";
285 status = "okay"; 283 status = "okay";
286 }; 284 };
287 285
288 &sdhi2 { 286 &sdhi2 {
289 pinctrl-names = "default"; 287 pinctrl-names = "default";
290 pinctrl-0 = <&sdhi2_pins>; 288 pinctrl-0 = <&sdhi2_pins>;
291 bus-width = <4>; 289 bus-width = <4>;
292 vmmc-supply = <®_3p3v>; 290 vmmc-supply = <®_3p3v>;
293 vqmmc-supply = <®_1p8v>; 291 vqmmc-supply = <®_1p8v>;
294 non-removable; 292 non-removable;
295 cap-power-off-card; 293 cap-power-off-card;
>> 294 pm-ignore-notify;
296 keep-power-in-suspend; 295 keep-power-in-suspend;
297 mmc-pwrseq = <&wlan_pwrseq>; 296 mmc-pwrseq = <&wlan_pwrseq>;
298 status = "okay"; 297 status = "okay";
299 #address-cells = <1>; 298 #address-cells = <1>;
300 #size-cells = <0>; 299 #size-cells = <0>;
301 300
302 brcmf: bcrmf@1 { 301 brcmf: bcrmf@1 {
303 reg = <1>; 302 reg = <1>;
304 compatible = "brcm,bcm4329-fma 303 compatible = "brcm,bcm4329-fmac";
305 interrupt-parent = <&gpio1>; 304 interrupt-parent = <&gpio1>;
306 interrupts = <27 IRQ_TYPE_LEVE 305 interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
307 interrupt-names = "host-wake"; 306 interrupt-names = "host-wake";
308 }; 307 };
309 }; 308 };
310 309
311 &sdhi3 { 310 &sdhi3 {
312 pinctrl-0 = <&sdhi3_pins>; 311 pinctrl-0 = <&sdhi3_pins>;
313 pinctrl-1 = <&sdhi3_pins>; 312 pinctrl-1 = <&sdhi3_pins>;
314 pinctrl-names = "default", "state_uhs" 313 pinctrl-names = "default", "state_uhs";
315 vmmc-supply = <®_3p3v>; 314 vmmc-supply = <®_3p3v>;
316 vqmmc-supply = <®_1p8v>; 315 vqmmc-supply = <®_1p8v>;
317 bus-width = <8>; 316 bus-width = <8>;
318 mmc-hs200-1_8v; 317 mmc-hs200-1_8v;
319 no-sd; 318 no-sd;
320 no-sdio; 319 no-sdio;
321 non-removable; 320 non-removable;
322 fixed-emmc-driver-type = <1>; 321 fixed-emmc-driver-type = <1>;
323 status = "okay"; 322 status = "okay";
324 }; 323 };
325 324
326 &usb2_clksel { 325 &usb2_clksel {
327 clocks = <&cpg CPG_MOD 703>, <&cpg CPG 326 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>,
328 <&versaclock5 3>, <&usb3s0_c 327 <&versaclock5 3>, <&usb3s0_clk>;
329 status = "okay"; 328 status = "okay";
330 }; 329 };
331 330
332 &usb3s0_clk { 331 &usb3s0_clk {
333 clock-frequency = <100000000>; 332 clock-frequency = <100000000>;
334 }; 333 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.