1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * Device Tree Source for the Draak board 3 * Device Tree Source for the Draak board
4 * 4 *
5 * Copyright (C) 2016-2018 Renesas Electronics 5 * Copyright (C) 2016-2018 Renesas Electronics Corp.
6 * Copyright (C) 2017 Glider bvba 6 * Copyright (C) 2017 Glider bvba
7 */ 7 */
8 8
9 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h> 10 #include <dt-bindings/input/input.h>
11 11
12 / { 12 / {
13 model = "Renesas Draak board"; 13 model = "Renesas Draak board";
14 compatible = "renesas,draak"; 14 compatible = "renesas,draak";
15 15
16 aliases { 16 aliases {
17 serial0 = &scif2; 17 serial0 = &scif2;
18 ethernet0 = &avb; 18 ethernet0 = &avb;
19 }; 19 };
20 20
21 audio_clkout: audio-clkout { 21 audio_clkout: audio-clkout {
22 /* 22 /*
23 * This is same as <&rcar_soun 23 * This is same as <&rcar_sound 0>
24 * but needed to avoid cs2000/ 24 * but needed to avoid cs2000/rcar_sound probe dead-lock
25 */ 25 */
26 compatible = "fixed-clock"; 26 compatible = "fixed-clock";
27 #clock-cells = <0>; 27 #clock-cells = <0>;
28 clock-frequency = <12288000>; 28 clock-frequency = <12288000>;
29 }; 29 };
30 30
31 backlight: backlight { 31 backlight: backlight {
32 compatible = "pwm-backlight"; 32 compatible = "pwm-backlight";
33 pwms = <&pwm1 0 50000>; 33 pwms = <&pwm1 0 50000>;
34 34
35 brightness-levels = <512 511 5 35 brightness-levels = <512 511 505 494 473 440 392 327 241 133 0>;
36 default-brightness-level = <10 36 default-brightness-level = <10>;
37 37
38 power-supply = <®_12p0v>; 38 power-supply = <®_12p0v>;
39 enable-gpios = <&gpio4 0 GPIO_ 39 enable-gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>;
40 }; 40 };
41 41
42 chosen { 42 chosen {
43 bootargs = "ignore_loglevel rw 43 bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
44 stdout-path = "serial0:115200n 44 stdout-path = "serial0:115200n8";
45 }; 45 };
46 46
47 composite-in { 47 composite-in {
48 compatible = "composite-video- 48 compatible = "composite-video-connector";
49 49
50 port { 50 port {
51 composite_con_in: endp 51 composite_con_in: endpoint {
52 remote-endpoin 52 remote-endpoint = <&adv7180_in>;
53 }; 53 };
54 }; 54 };
55 }; 55 };
56 56
57 hdmi-in { 57 hdmi-in {
58 compatible = "hdmi-connector"; 58 compatible = "hdmi-connector";
59 type = "a"; 59 type = "a";
60 60
61 port { 61 port {
62 hdmi_con_in: endpoint 62 hdmi_con_in: endpoint {
63 remote-endpoin 63 remote-endpoint = <&adv7612_in>;
64 }; 64 };
65 }; 65 };
66 }; 66 };
67 67
68 hdmi-out { 68 hdmi-out {
69 compatible = "hdmi-connector"; 69 compatible = "hdmi-connector";
70 type = "a"; 70 type = "a";
71 71
72 port { 72 port {
73 hdmi_con_out: endpoint 73 hdmi_con_out: endpoint {
74 remote-endpoin 74 remote-endpoint = <&adv7511_out>;
75 }; 75 };
76 }; 76 };
77 }; 77 };
78 78
79 keys { 79 keys {
80 compatible = "gpio-keys"; 80 compatible = "gpio-keys";
81 81
82 pinctrl-0 = <&keys_pins>; 82 pinctrl-0 = <&keys_pins>;
83 pinctrl-names = "default"; 83 pinctrl-names = "default";
84 84
85 key-1 { 85 key-1 {
86 gpios = <&gpio4 12 GPI 86 gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
87 linux,code = <KEY_1>; 87 linux,code = <KEY_1>;
88 label = "SW56-1"; 88 label = "SW56-1";
89 wakeup-source; 89 wakeup-source;
90 debounce-interval = <2 90 debounce-interval = <20>;
91 }; 91 };
92 key-2 { 92 key-2 {
93 gpios = <&gpio4 13 GPI 93 gpios = <&gpio4 13 GPIO_ACTIVE_LOW>;
94 linux,code = <KEY_2>; 94 linux,code = <KEY_2>;
95 label = "SW56-2"; 95 label = "SW56-2";
96 wakeup-source; 96 wakeup-source;
97 debounce-interval = <2 97 debounce-interval = <20>;
98 }; 98 };
99 key-3 { 99 key-3 {
100 gpios = <&gpio4 14 GPI 100 gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;
101 linux,code = <KEY_3>; 101 linux,code = <KEY_3>;
102 label = "SW56-3"; 102 label = "SW56-3";
103 wakeup-source; 103 wakeup-source;
104 debounce-interval = <2 104 debounce-interval = <20>;
105 }; 105 };
106 key-4 { 106 key-4 {
107 gpios = <&gpio4 15 GPI 107 gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
108 linux,code = <KEY_4>; 108 linux,code = <KEY_4>;
109 label = "SW56-4"; 109 label = "SW56-4";
110 wakeup-source; 110 wakeup-source;
111 debounce-interval = <2 111 debounce-interval = <20>;
112 }; 112 };
113 }; 113 };
114 114
115 lvds-decoder { 115 lvds-decoder {
116 compatible = "thine,thc63lvd10 116 compatible = "thine,thc63lvd1024";
117 vcc-supply = <®_3p3v>; 117 vcc-supply = <®_3p3v>;
118 118
119 ports { 119 ports {
120 #address-cells = <1>; 120 #address-cells = <1>;
121 #size-cells = <0>; 121 #size-cells = <0>;
122 122
123 port@0 { 123 port@0 {
124 reg = <0>; 124 reg = <0>;
125 thc63lvd1024_i 125 thc63lvd1024_in: endpoint {
126 remote 126 remote-endpoint = <&lvds0_out>;
127 }; 127 };
128 }; 128 };
129 129
130 port@2 { 130 port@2 {
131 reg = <2>; 131 reg = <2>;
132 thc63lvd1024_o 132 thc63lvd1024_out: endpoint {
133 remote 133 remote-endpoint = <&adv7511_in>;
134 }; 134 };
135 }; 135 };
136 }; 136 };
137 }; 137 };
138 138
139 memory@48000000 { 139 memory@48000000 {
140 device_type = "memory"; 140 device_type = "memory";
141 /* first 128MB is reserved for 141 /* first 128MB is reserved for secure area. */
142 reg = <0x0 0x48000000 0x0 0x18 142 reg = <0x0 0x48000000 0x0 0x18000000>;
143 }; 143 };
144 144
145 reg_1p8v: regulator-1p8v { 145 reg_1p8v: regulator-1p8v {
146 compatible = "regulator-fixed" 146 compatible = "regulator-fixed";
147 regulator-name = "fixed-1.8V"; 147 regulator-name = "fixed-1.8V";
148 regulator-min-microvolt = <180 148 regulator-min-microvolt = <1800000>;
149 regulator-max-microvolt = <180 149 regulator-max-microvolt = <1800000>;
150 regulator-boot-on; 150 regulator-boot-on;
151 regulator-always-on; 151 regulator-always-on;
152 }; 152 };
153 153
154 reg_3p3v: regulator-3p3v { 154 reg_3p3v: regulator-3p3v {
155 compatible = "regulator-fixed" 155 compatible = "regulator-fixed";
156 regulator-name = "fixed-3.3V"; 156 regulator-name = "fixed-3.3V";
157 regulator-min-microvolt = <330 157 regulator-min-microvolt = <3300000>;
158 regulator-max-microvolt = <330 158 regulator-max-microvolt = <3300000>;
159 regulator-boot-on; 159 regulator-boot-on;
160 regulator-always-on; 160 regulator-always-on;
161 }; 161 };
162 162
163 reg_12p0v: regulator-12p0v { 163 reg_12p0v: regulator-12p0v {
164 compatible = "regulator-fixed" 164 compatible = "regulator-fixed";
165 regulator-name = "D12.0V"; 165 regulator-name = "D12.0V";
166 regulator-min-microvolt = <120 166 regulator-min-microvolt = <12000000>;
167 regulator-max-microvolt = <120 167 regulator-max-microvolt = <12000000>;
168 regulator-boot-on; 168 regulator-boot-on;
169 regulator-always-on; 169 regulator-always-on;
170 }; 170 };
171 171
172 sound_card: sound { 172 sound_card: sound {
173 compatible = "audio-graph-card 173 compatible = "audio-graph-card";
174 174
175 dais = <&rsnd_port0 /* ak4 175 dais = <&rsnd_port0 /* ak4613 */
176 /* HDMI is not yet sup 176 /* HDMI is not yet supported */
177 >; 177 >;
178 }; 178 };
179 179
180 vga { 180 vga {
181 compatible = "vga-connector"; 181 compatible = "vga-connector";
182 182
183 port { 183 port {
184 vga_in: endpoint { 184 vga_in: endpoint {
185 remote-endpoin 185 remote-endpoint = <&adv7123_out>;
186 }; 186 };
187 }; 187 };
188 }; 188 };
189 189
190 vga-encoder { 190 vga-encoder {
191 compatible = "adi,adv7123"; 191 compatible = "adi,adv7123";
192 192
193 ports { 193 ports {
194 #address-cells = <1>; 194 #address-cells = <1>;
195 #size-cells = <0>; 195 #size-cells = <0>;
196 196
197 port@0 { 197 port@0 {
198 reg = <0>; 198 reg = <0>;
199 adv7123_in: en 199 adv7123_in: endpoint {
200 remote 200 remote-endpoint = <&du_out_rgb>;
201 }; 201 };
202 }; 202 };
203 port@1 { 203 port@1 {
204 reg = <1>; 204 reg = <1>;
205 adv7123_out: e 205 adv7123_out: endpoint {
206 remote 206 remote-endpoint = <&vga_in>;
207 }; 207 };
208 }; 208 };
209 }; 209 };
210 }; 210 };
211 211
212 x12_clk: x12 { 212 x12_clk: x12 {
213 compatible = "fixed-clock"; 213 compatible = "fixed-clock";
214 #clock-cells = <0>; 214 #clock-cells = <0>;
215 clock-frequency = <74250000>; 215 clock-frequency = <74250000>;
216 }; 216 };
217 217
218 x19_clk: x19 { 218 x19_clk: x19 {
219 compatible = "fixed-clock"; 219 compatible = "fixed-clock";
220 #clock-cells = <0>; 220 #clock-cells = <0>;
221 clock-frequency = <24576000>; 221 clock-frequency = <24576000>;
222 }; 222 };
223 }; 223 };
224 224
225 &audio_clk_b { 225 &audio_clk_b {
226 /* 226 /*
227 * X11 is connected to VI4_FIELD/SCIF_ 227 * X11 is connected to VI4_FIELD/SCIF_CLK/AUDIO_CLKB,
228 * and R-Car Sound uses AUDIO_CLKB. 228 * and R-Car Sound uses AUDIO_CLKB.
229 * Note is that schematic indicates VI 229 * Note is that schematic indicates VI4_FIELD conection only
230 * not AUDIO_CLKB at SoC page. 230 * not AUDIO_CLKB at SoC page.
231 * And this VI4_FIELD/SCIF_CLK/AUDIO_C 231 * And this VI4_FIELD/SCIF_CLK/AUDIO_CLKB is connected to SW60.
232 * SW60 should be 1-2. 232 * SW60 should be 1-2.
233 */ 233 */
234 234
235 clock-frequency = <22579200>; 235 clock-frequency = <22579200>;
236 }; 236 };
237 237
238 &avb { 238 &avb {
239 pinctrl-0 = <&avb0_pins>; 239 pinctrl-0 = <&avb0_pins>;
240 pinctrl-names = "default"; 240 pinctrl-names = "default";
241 renesas,no-ether-link; 241 renesas,no-ether-link;
242 phy-handle = <&phy0>; 242 phy-handle = <&phy0>;
243 status = "okay"; 243 status = "okay";
244 244
245 phy0: ethernet-phy@0 { 245 phy0: ethernet-phy@0 {
246 compatible = "ethernet-phy-id0 246 compatible = "ethernet-phy-id0022.1622",
247 "ethernet-phy-iee 247 "ethernet-phy-ieee802.3-c22";
248 rxc-skew-ps = <1500>; 248 rxc-skew-ps = <1500>;
249 reg = <0>; 249 reg = <0>;
250 interrupt-parent = <&gpio5>; 250 interrupt-parent = <&gpio5>;
251 interrupts = <19 IRQ_TYPE_LEVE 251 interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
252 reset-gpios = <&gpio5 18 GPIO_ 252 reset-gpios = <&gpio5 18 GPIO_ACTIVE_LOW>;
253 /* 253 /*
254 * TX clock internal delay mod 254 * TX clock internal delay mode is required for reliable
255 * 1Gbps communication using t 255 * 1Gbps communication using the KSZ9031RNX phy present on
256 * the Draak board, however, T 256 * the Draak board, however, TX clock internal delay mode
257 * isn't supported on R-Car D3 257 * isn't supported on R-Car D3(e). Thus, limit speed to
258 * 100Mbps for reliable commun 258 * 100Mbps for reliable communication.
259 */ 259 */
260 max-speed = <100>; 260 max-speed = <100>;
261 }; 261 };
262 }; 262 };
263 263
264 &can0 { 264 &can0 {
265 pinctrl-0 = <&can0_pins>; 265 pinctrl-0 = <&can0_pins>;
266 pinctrl-names = "default"; 266 pinctrl-names = "default";
267 status = "okay"; 267 status = "okay";
268 }; 268 };
269 269
270 &can1 { 270 &can1 {
271 pinctrl-0 = <&can1_pins>; 271 pinctrl-0 = <&can1_pins>;
272 pinctrl-names = "default"; 272 pinctrl-names = "default";
273 status = "okay"; 273 status = "okay";
274 }; 274 };
275 275
276 &du { 276 &du {
277 pinctrl-0 = <&du_pins>; 277 pinctrl-0 = <&du_pins>;
278 pinctrl-names = "default"; 278 pinctrl-names = "default";
279 status = "okay"; 279 status = "okay";
280 280
281 clocks = <&cpg CPG_MOD 724>, 281 clocks = <&cpg CPG_MOD 724>,
282 <&cpg CPG_MOD 723>, 282 <&cpg CPG_MOD 723>,
283 <&x12_clk>; 283 <&x12_clk>;
284 clock-names = "du.0", "du.1", "dclkin. 284 clock-names = "du.0", "du.1", "dclkin.0";
285 285
286 ports { 286 ports {
287 port@0 { 287 port@0 {
288 du_out_rgb: endpoint { 288 du_out_rgb: endpoint {
289 remote-endpoin 289 remote-endpoint = <&adv7123_in>;
290 }; 290 };
291 }; 291 };
292 }; 292 };
293 }; 293 };
294 294
295 &ehci0 { 295 &ehci0 {
296 dr_mode = "host"; 296 dr_mode = "host";
297 status = "okay"; 297 status = "okay";
298 }; 298 };
299 299
300 &extal_clk { 300 &extal_clk {
301 clock-frequency = <48000000>; 301 clock-frequency = <48000000>;
302 }; 302 };
303 303
304 &hsusb { 304 &hsusb {
305 dr_mode = "host"; 305 dr_mode = "host";
306 status = "okay"; 306 status = "okay";
307 }; 307 };
308 308
309 &i2c0 { 309 &i2c0 {
310 pinctrl-0 = <&i2c0_pins>; 310 pinctrl-0 = <&i2c0_pins>;
311 pinctrl-names = "default"; 311 pinctrl-names = "default";
312 status = "okay"; 312 status = "okay";
313 313
314 ak4613: codec@10 { 314 ak4613: codec@10 {
315 compatible = "asahi-kasei,ak46 315 compatible = "asahi-kasei,ak4613";
316 #sound-dai-cells = <0>; 316 #sound-dai-cells = <0>;
317 reg = <0x10>; 317 reg = <0x10>;
318 clocks = <&rcar_sound 0>; /* a 318 clocks = <&rcar_sound 0>; /* audio_clkout */
319 319
320 asahi-kasei,in1-single-end; 320 asahi-kasei,in1-single-end;
321 asahi-kasei,in2-single-end; 321 asahi-kasei,in2-single-end;
322 asahi-kasei,out1-single-end; 322 asahi-kasei,out1-single-end;
323 asahi-kasei,out2-single-end; 323 asahi-kasei,out2-single-end;
324 asahi-kasei,out3-single-end; 324 asahi-kasei,out3-single-end;
325 asahi-kasei,out4-single-end; 325 asahi-kasei,out4-single-end;
326 asahi-kasei,out5-single-end; 326 asahi-kasei,out5-single-end;
327 asahi-kasei,out6-single-end; 327 asahi-kasei,out6-single-end;
328 328
329 port { 329 port {
330 ak4613_endpoint: endpo 330 ak4613_endpoint: endpoint {
331 remote-endpoin 331 remote-endpoint = <&rsnd_for_ak4613>;
332 }; 332 };
333 }; 333 };
334 }; 334 };
335 335
336 composite-in@20 { 336 composite-in@20 {
337 compatible = "adi,adv7180cp"; 337 compatible = "adi,adv7180cp";
338 reg = <0x20>; 338 reg = <0x20>;
339 339
340 ports { 340 ports {
341 #address-cells = <1>; 341 #address-cells = <1>;
342 #size-cells = <0>; 342 #size-cells = <0>;
343 343
344 port@0 { 344 port@0 {
345 reg = <0>; 345 reg = <0>;
346 adv7180_in: en 346 adv7180_in: endpoint {
347 remote 347 remote-endpoint = <&composite_con_in>;
348 }; 348 };
349 }; 349 };
350 350
351 port@3 { 351 port@3 {
352 reg = <3>; 352 reg = <3>;
353 353
354 /* 354 /*
355 * The VIN4 vi 355 * The VIN4 video input path is shared between
356 * CVBS and HD 356 * CVBS and HDMI inputs through SW[49-53]
357 * switches. 357 * switches.
358 * 358 *
359 * HDMI is the !! 359 * CVBS is the default selection, link it to
360 * not connect !! 360 * VIN4 here.
361 */ 361 */
>> 362 adv7180_out: endpoint {
>> 363 remote-endpoint = <&vin4_in>;
>> 364 };
362 }; 365 };
363 }; 366 };
364 367
365 }; 368 };
366 369
367 hdmi-encoder@39 { 370 hdmi-encoder@39 {
368 compatible = "adi,adv7511w"; 371 compatible = "adi,adv7511w";
369 reg = <0x39>, <0x3f>, <0x3c>, 372 reg = <0x39>, <0x3f>, <0x3c>, <0x38>;
370 reg-names = "main", "edid", "c 373 reg-names = "main", "edid", "cec", "packet";
371 interrupt-parent = <&gpio1>; 374 interrupt-parent = <&gpio1>;
372 interrupts = <28 IRQ_TYPE_LEVE 375 interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
373 376
374 avdd-supply = <®_1p8v>; <<
375 dvdd-supply = <®_1p8v>; <<
376 pvdd-supply = <®_1p8v>; <<
377 dvdd-3v-supply = <®_3p3v>; <<
378 bgvdd-supply = <®_1p8v>; <<
379 <<
380 adi,input-depth = <8>; 377 adi,input-depth = <8>;
381 adi,input-colorspace = "rgb"; 378 adi,input-colorspace = "rgb";
382 adi,input-clock = "1x"; 379 adi,input-clock = "1x";
383 380
384 ports { 381 ports {
385 #address-cells = <1>; 382 #address-cells = <1>;
386 #size-cells = <0>; 383 #size-cells = <0>;
387 384
388 port@0 { 385 port@0 {
389 reg = <0>; 386 reg = <0>;
390 adv7511_in: en 387 adv7511_in: endpoint {
391 remote 388 remote-endpoint = <&thc63lvd1024_out>;
392 }; 389 };
393 }; 390 };
394 391
395 port@1 { 392 port@1 {
396 reg = <1>; 393 reg = <1>;
397 adv7511_out: e 394 adv7511_out: endpoint {
398 remote 395 remote-endpoint = <&hdmi_con_out>;
399 }; 396 };
400 }; 397 };
401 }; 398 };
402 }; 399 };
403 400
404 hdmi-decoder@4c { 401 hdmi-decoder@4c {
405 compatible = "adi,adv7612"; 402 compatible = "adi,adv7612";
406 reg = <0x4c>; 403 reg = <0x4c>;
407 default-input = <0>; 404 default-input = <0>;
408 405
409 ports { 406 ports {
410 #address-cells = <1>; 407 #address-cells = <1>;
411 #size-cells = <0>; 408 #size-cells = <0>;
412 409
413 port@0 { 410 port@0 {
414 reg = <0>; 411 reg = <0>;
415 412
416 adv7612_in: en 413 adv7612_in: endpoint {
417 remote 414 remote-endpoint = <&hdmi_con_in>;
418 }; 415 };
419 }; 416 };
420 417
421 port@2 { 418 port@2 {
422 reg = <2>; 419 reg = <2>;
423 420
424 /* 421 /*
425 * The VIN4 vi 422 * The VIN4 video input path is shared between
426 * CVBS and HD 423 * CVBS and HDMI inputs through SW[49-53]
427 * switches. 424 * switches.
428 * 425 *
429 * HDMI is the !! 426 * CVBS is the default selection, leave HDMI
430 * VIN4 here. !! 427 * not connected here.
431 */ 428 */
432 adv7612_out: e 429 adv7612_out: endpoint {
433 remote !! 430 pclk-sample = <0>;
>> 431 hsync-active = <0>;
>> 432 vsync-active = <0>;
434 }; 433 };
435 }; 434 };
436 }; 435 };
437 }; 436 };
438 437
439 cs2000: clk-multiplier@4f { 438 cs2000: clk-multiplier@4f {
440 #clock-cells = <0>; 439 #clock-cells = <0>;
441 compatible = "cirrus,cs2000-cp 440 compatible = "cirrus,cs2000-cp";
442 reg = <0x4f>; 441 reg = <0x4f>;
443 clocks = <&audio_clkout>, <&x1 442 clocks = <&audio_clkout>, <&x19_clk>; /* audio_clkout_1, x19 */
444 clock-names = "clk_in", "ref_c 443 clock-names = "clk_in", "ref_clk";
445 444
446 assigned-clocks = <&cs2000>; 445 assigned-clocks = <&cs2000>;
447 assigned-clock-rates = <245760 446 assigned-clock-rates = <24576000>; /* 1/1 divide */
448 }; 447 };
449 448
450 eeprom@50 { 449 eeprom@50 {
451 compatible = "rohm,br24t01", " 450 compatible = "rohm,br24t01", "atmel,24c01";
452 reg = <0x50>; 451 reg = <0x50>;
453 pagesize = <8>; 452 pagesize = <8>;
454 }; 453 };
455 }; 454 };
456 455
457 &i2c1 { 456 &i2c1 {
458 pinctrl-0 = <&i2c1_pins>; 457 pinctrl-0 = <&i2c1_pins>;
459 pinctrl-names = "default"; 458 pinctrl-names = "default";
460 status = "okay"; 459 status = "okay";
461 }; 460 };
462 461
463 &lvds0 { 462 &lvds0 {
464 status = "okay"; 463 status = "okay";
465 464
466 clocks = <&cpg CPG_MOD 727>, 465 clocks = <&cpg CPG_MOD 727>,
467 <&x12_clk>, 466 <&x12_clk>,
468 <&extal_clk>; 467 <&extal_clk>;
469 clock-names = "fck", "dclkin.0", "exta 468 clock-names = "fck", "dclkin.0", "extal";
470 469
471 ports { 470 ports {
472 port@1 { 471 port@1 {
473 lvds0_out: endpoint { 472 lvds0_out: endpoint {
474 remote-endpoin 473 remote-endpoint = <&thc63lvd1024_in>;
475 }; 474 };
476 }; 475 };
477 }; 476 };
478 }; 477 };
479 478
480 &lvds1 { 479 &lvds1 {
481 /* 480 /*
482 * Even though the LVDS1 output is not 481 * Even though the LVDS1 output is not connected, the encoder must be
483 * enabled to supply a pixel clock to 482 * enabled to supply a pixel clock to the DU for the DPAD output when
484 * LVDS0 is in use. 483 * LVDS0 is in use.
485 */ 484 */
486 status = "okay"; 485 status = "okay";
487 486
488 clocks = <&cpg CPG_MOD 727>, 487 clocks = <&cpg CPG_MOD 727>,
489 <&x12_clk>, 488 <&x12_clk>,
490 <&extal_clk>; 489 <&extal_clk>;
491 clock-names = "fck", "dclkin.0", "exta 490 clock-names = "fck", "dclkin.0", "extal";
492 }; 491 };
493 492
494 &ohci0 { 493 &ohci0 {
495 dr_mode = "host"; 494 dr_mode = "host";
496 status = "okay"; 495 status = "okay";
497 }; 496 };
498 497
499 &pfc { 498 &pfc {
500 avb0_pins: avb { 499 avb0_pins: avb {
501 groups = "avb0_link", "avb0_md 500 groups = "avb0_link", "avb0_mdio", "avb0_mii";
502 function = "avb0"; 501 function = "avb0";
503 }; 502 };
504 503
505 can0_pins: can0 { 504 can0_pins: can0 {
506 groups = "can0_data_a"; 505 groups = "can0_data_a";
507 function = "can0"; 506 function = "can0";
508 }; 507 };
509 508
510 can1_pins: can1 { 509 can1_pins: can1 {
511 groups = "can1_data_a"; 510 groups = "can1_data_a";
512 function = "can1"; 511 function = "can1";
513 }; 512 };
514 513
515 du_pins: du { 514 du_pins: du {
516 groups = "du_rgb888", "du_sync 515 groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
517 function = "du"; 516 function = "du";
518 }; 517 };
519 518
520 i2c0_pins: i2c0 { 519 i2c0_pins: i2c0 {
521 groups = "i2c0"; 520 groups = "i2c0";
522 function = "i2c0"; 521 function = "i2c0";
523 }; 522 };
524 523
525 i2c1_pins: i2c1 { 524 i2c1_pins: i2c1 {
526 groups = "i2c1"; 525 groups = "i2c1";
527 function = "i2c1"; 526 function = "i2c1";
528 }; 527 };
529 528
530 keys_pins: keys { 529 keys_pins: keys {
531 pins = "GP_4_12", "GP_4_13", " 530 pins = "GP_4_12", "GP_4_13", "GP_4_14", "GP_4_15";
532 bias-pull-up; 531 bias-pull-up;
533 }; 532 };
534 533
535 pwm0_pins: pwm0 { 534 pwm0_pins: pwm0 {
536 groups = "pwm0_c"; 535 groups = "pwm0_c";
537 function = "pwm0"; 536 function = "pwm0";
538 }; 537 };
539 538
540 pwm1_pins: pwm1 { 539 pwm1_pins: pwm1 {
541 groups = "pwm1_c"; 540 groups = "pwm1_c";
542 function = "pwm1"; 541 function = "pwm1";
543 }; 542 };
544 543
545 rpc_pins: rpc { 544 rpc_pins: rpc {
546 groups = "rpc_clk2", "rpc_ctrl 545 groups = "rpc_clk2", "rpc_ctrl", "rpc_data", "rpc_reset",
547 "rpc_int"; 546 "rpc_int";
548 function = "rpc"; 547 function = "rpc";
549 }; 548 };
550 549
551 scif2_pins: scif2 { 550 scif2_pins: scif2 {
552 groups = "scif2_data"; 551 groups = "scif2_data";
553 function = "scif2"; 552 function = "scif2";
554 }; 553 };
555 554
556 sdhi2_pins: sd2 { 555 sdhi2_pins: sd2 {
557 groups = "mmc_data8", "mmc_ctr 556 groups = "mmc_data8", "mmc_ctrl";
558 function = "mmc"; 557 function = "mmc";
559 power-source = <1800>; 558 power-source = <1800>;
560 }; 559 };
561 560
562 sdhi2_pins_uhs: sd2_uhs { 561 sdhi2_pins_uhs: sd2_uhs {
563 groups = "mmc_data8", "mmc_ctr 562 groups = "mmc_data8", "mmc_ctrl";
564 function = "mmc"; 563 function = "mmc";
565 power-source = <1800>; 564 power-source = <1800>;
566 }; 565 };
567 566
568 sound_pins: sound { 567 sound_pins: sound {
569 groups = "ssi34_ctrl", "ssi3_d 568 groups = "ssi34_ctrl", "ssi3_data", "ssi4_data_a";
570 function = "ssi"; 569 function = "ssi";
571 }; 570 };
572 571
573 sound_clk_pins: sound-clk { 572 sound_clk_pins: sound-clk {
574 groups = "audio_clk_a", "audio 573 groups = "audio_clk_a", "audio_clk_b",
575 "audio_clkout", "audi 574 "audio_clkout", "audio_clkout1";
576 function = "audio_clk"; 575 function = "audio_clk";
577 }; 576 };
578 577
579 usb0_pins: usb0 { 578 usb0_pins: usb0 {
580 groups = "usb0"; 579 groups = "usb0";
581 function = "usb0"; 580 function = "usb0";
582 }; 581 };
583 582
584 vin4_pins: vin4 { !! 583 vin4_pins_cvbs: vin4 {
585 groups = "vin4_data24", "vin4_ !! 584 groups = "vin4_data8", "vin4_sync", "vin4_clk";
586 function = "vin4"; 585 function = "vin4";
587 }; 586 };
588 }; 587 };
589 588
590 &pwm0 { 589 &pwm0 {
591 pinctrl-0 = <&pwm0_pins>; 590 pinctrl-0 = <&pwm0_pins>;
592 pinctrl-names = "default"; 591 pinctrl-names = "default";
593 592
594 status = "okay"; 593 status = "okay";
595 }; 594 };
596 595
597 &pwm1 { 596 &pwm1 {
598 pinctrl-0 = <&pwm1_pins>; 597 pinctrl-0 = <&pwm1_pins>;
599 pinctrl-names = "default"; 598 pinctrl-names = "default";
600 599
601 status = "okay"; 600 status = "okay";
602 }; 601 };
603 602
604 &rcar_sound { 603 &rcar_sound {
605 pinctrl-0 = <&sound_pins>, <&sound_clk 604 pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
606 pinctrl-names = "default"; 605 pinctrl-names = "default";
607 606
608 /* Single DAI */ 607 /* Single DAI */
609 #sound-dai-cells = <0>; 608 #sound-dai-cells = <0>;
610 609
611 /* audio_clkout0/1 */ 610 /* audio_clkout0/1 */
612 #clock-cells = <1>; 611 #clock-cells = <1>;
613 clock-frequency = <12288000 11289600>; 612 clock-frequency = <12288000 11289600>;
614 613
615 status = "okay"; 614 status = "okay";
616 615
617 clocks = <&cpg CPG_MOD 1005>, 616 clocks = <&cpg CPG_MOD 1005>,
618 <&cpg CPG_MOD 1011>, <&cpg CP 617 <&cpg CPG_MOD 1011>, <&cpg CPG_MOD 1012>,
619 <&cpg CPG_MOD 1025>, <&cpg CP 618 <&cpg CPG_MOD 1025>, <&cpg CPG_MOD 1026>,
620 <&cpg CPG_MOD 1020>, <&cpg CP 619 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
621 <&cpg CPG_MOD 1020>, <&cpg CP 620 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
622 <&cpg CPG_MOD 1019>, <&cpg CP 621 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
623 <&cs2000>, <&audio_clk_b>, 622 <&cs2000>, <&audio_clk_b>,
624 <&cpg CPG_CORE R8A77995_CLK_Z 623 <&cpg CPG_CORE R8A77995_CLK_ZA2>;
625 624
626 ports { 625 ports {
627 rsnd_port0: port { 626 rsnd_port0: port {
628 rsnd_for_ak4613: endpo 627 rsnd_for_ak4613: endpoint {
629 remote-endpoin 628 remote-endpoint = <&ak4613_endpoint>;
630 dai-format = " 629 dai-format = "left_j";
631 bitclock-maste 630 bitclock-master = <&rsnd_for_ak4613>;
632 frame-master = 631 frame-master = <&rsnd_for_ak4613>;
633 playback = <&s 632 playback = <&ssi3>, <&src5>, <&dvc0>;
634 capture = <&ss 633 capture = <&ssi4>, <&src6>, <&dvc1>;
635 }; 634 };
636 }; 635 };
637 }; 636 };
638 }; 637 };
639 638
640 &rpc { 639 &rpc {
641 pinctrl-0 = <&rpc_pins>; 640 pinctrl-0 = <&rpc_pins>;
642 pinctrl-names = "default"; 641 pinctrl-names = "default";
643 642
644 /* Left disabled. To be enabled by fi 643 /* Left disabled. To be enabled by firmware when unlocked. */
645 644
646 flash@0 { 645 flash@0 {
647 compatible = "cypress,hyperfla 646 compatible = "cypress,hyperflash", "cfi-flash";
648 reg = <0>; 647 reg = <0>;
649 648
650 partitions { 649 partitions {
651 compatible = "fixed-pa 650 compatible = "fixed-partitions";
652 #address-cells = <1>; 651 #address-cells = <1>;
653 #size-cells = <1>; 652 #size-cells = <1>;
654 653
655 bootparam@0 { 654 bootparam@0 {
656 reg = <0x00000 655 reg = <0x00000000 0x040000>;
657 read-only; 656 read-only;
658 }; 657 };
659 bl2@40000 { 658 bl2@40000 {
660 reg = <0x00040 659 reg = <0x00040000 0x140000>;
661 read-only; 660 read-only;
662 }; 661 };
663 cert_header_sa6@180000 662 cert_header_sa6@180000 {
664 reg = <0x00180 663 reg = <0x00180000 0x040000>;
665 read-only; 664 read-only;
666 }; 665 };
667 bl31@1c0000 { 666 bl31@1c0000 {
668 reg = <0x001c0 667 reg = <0x001c0000 0x040000>;
669 read-only; 668 read-only;
670 }; 669 };
671 tee@200000 { 670 tee@200000 {
672 reg = <0x00200 671 reg = <0x00200000 0x440000>;
673 read-only; 672 read-only;
674 }; 673 };
675 uboot@640000 { 674 uboot@640000 {
676 reg = <0x00640 675 reg = <0x00640000 0x100000>;
677 read-only; 676 read-only;
678 }; 677 };
679 dtb@740000 { 678 dtb@740000 {
680 reg = <0x00740 679 reg = <0x00740000 0x080000>;
681 }; 680 };
682 kernel@7c0000 { 681 kernel@7c0000 {
683 reg = <0x007c0 682 reg = <0x007c0000 0x1400000>;
684 }; 683 };
685 user@1bc0000 { 684 user@1bc0000 {
686 reg = <0x01bc0 685 reg = <0x01bc0000 0x2440000>;
687 }; 686 };
688 }; 687 };
689 }; 688 };
690 }; 689 };
691 690
692 &rwdt { 691 &rwdt {
693 timeout-sec = <60>; 692 timeout-sec = <60>;
694 status = "okay"; 693 status = "okay";
695 }; 694 };
696 695
697 &scif2 { 696 &scif2 {
698 pinctrl-0 = <&scif2_pins>; 697 pinctrl-0 = <&scif2_pins>;
699 pinctrl-names = "default"; 698 pinctrl-names = "default";
700 699
701 status = "okay"; 700 status = "okay";
702 }; 701 };
703 702
704 &sdhi2 { 703 &sdhi2 {
705 /* used for on-board eMMC */ 704 /* used for on-board eMMC */
706 pinctrl-0 = <&sdhi2_pins>; 705 pinctrl-0 = <&sdhi2_pins>;
707 pinctrl-1 = <&sdhi2_pins_uhs>; 706 pinctrl-1 = <&sdhi2_pins_uhs>;
708 pinctrl-names = "default", "state_uhs" 707 pinctrl-names = "default", "state_uhs";
709 708
710 vmmc-supply = <®_3p3v>; 709 vmmc-supply = <®_3p3v>;
711 vqmmc-supply = <®_1p8v>; 710 vqmmc-supply = <®_1p8v>;
712 bus-width = <8>; 711 bus-width = <8>;
713 mmc-hs200-1_8v; 712 mmc-hs200-1_8v;
714 no-sd; 713 no-sd;
715 no-sdio; 714 no-sdio;
716 non-removable; 715 non-removable;
717 status = "okay"; 716 status = "okay";
718 }; 717 };
719 718
720 &ssi4 { 719 &ssi4 {
721 shared-pin; 720 shared-pin;
722 }; 721 };
723 722
724 &usb2_phy0 { 723 &usb2_phy0 {
725 pinctrl-0 = <&usb0_pins>; 724 pinctrl-0 = <&usb0_pins>;
726 pinctrl-names = "default"; 725 pinctrl-names = "default";
727 726
728 renesas,no-otg-pins; 727 renesas,no-otg-pins;
729 status = "okay"; 728 status = "okay";
730 }; 729 };
731 730
732 &vin4 { 731 &vin4 {
733 pinctrl-0 = <&vin4_pins>; !! 732 pinctrl-0 = <&vin4_pins_cvbs>;
734 pinctrl-names = "default"; 733 pinctrl-names = "default";
735 734
736 status = "okay"; 735 status = "okay";
737 736
738 ports { 737 ports {
739 port { 738 port {
740 vin4_in: endpoint { 739 vin4_in: endpoint {
741 pclk-sample = !! 740 remote-endpoint = <&adv7180_out>;
742 hsync-active = <<
743 vsync-active = <<
744 remote-endpoin <<
745 }; 741 };
746 }; 742 };
747 }; 743 };
748 }; 744 };
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