1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * Device Tree Source for the Ebisu/Ebisu-4D b !! 3 * Device Tree Source for the Ebisu board
4 * 4 *
5 * Copyright (C) 2018 Renesas Electronics Corp 5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */ 6 */
7 7
8 #include <dt-bindings/gpio/gpio.h> 8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h> 9 #include <dt-bindings/input/input.h>
10 10
11 / { 11 / {
12 model = "Renesas Ebisu board"; 12 model = "Renesas Ebisu board";
13 compatible = "renesas,ebisu"; 13 compatible = "renesas,ebisu";
14 14
15 aliases { 15 aliases {
16 i2c0 = &i2c0; <<
17 i2c1 = &i2c1; <<
18 i2c2 = &i2c2; <<
19 i2c3 = &i2c3; <<
20 i2c4 = &i2c4; <<
21 i2c5 = &i2c5; <<
22 i2c6 = &i2c6; <<
23 i2c7 = &i2c7; <<
24 serial0 = &scif2; 16 serial0 = &scif2;
25 ethernet0 = &avb; 17 ethernet0 = &avb;
26 mmc0 = &sdhi3; 18 mmc0 = &sdhi3;
27 mmc1 = &sdhi0; 19 mmc1 = &sdhi0;
28 mmc2 = &sdhi1; 20 mmc2 = &sdhi1;
29 }; 21 };
30 22
31 chosen { 23 chosen {
32 bootargs = "ignore_loglevel rw 24 bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
33 stdout-path = "serial0:115200n 25 stdout-path = "serial0:115200n8";
34 }; 26 };
35 27
36 audio_clkout: audio-clkout { 28 audio_clkout: audio-clkout {
37 /* 29 /*
38 * This is same as <&rcar_soun 30 * This is same as <&rcar_sound 0>
39 * but needed to avoid cs2000/ 31 * but needed to avoid cs2000/rcar_sound probe dead-lock
40 */ 32 */
41 compatible = "fixed-clock"; 33 compatible = "fixed-clock";
42 #clock-cells = <0>; 34 #clock-cells = <0>;
43 clock-frequency = <11289600>; 35 clock-frequency = <11289600>;
44 }; 36 };
45 37
46 backlight: backlight { 38 backlight: backlight {
47 compatible = "pwm-backlight"; 39 compatible = "pwm-backlight";
48 pwms = <&pwm3 0 50000>; 40 pwms = <&pwm3 0 50000>;
49 41
50 brightness-levels = <512 511 5 42 brightness-levels = <512 511 505 494 473 440 392 327 241 133 0>;
51 default-brightness-level = <10 43 default-brightness-level = <10>;
52 44
53 power-supply = <®_12p0v>; 45 power-supply = <®_12p0v>;
54 }; 46 };
55 47
56 cvbs-in { 48 cvbs-in {
57 compatible = "composite-video- 49 compatible = "composite-video-connector";
58 label = "CVBS IN"; 50 label = "CVBS IN";
59 51
60 port { 52 port {
61 cvbs_con: endpoint { 53 cvbs_con: endpoint {
62 remote-endpoin 54 remote-endpoint = <&adv7482_ain7>;
63 }; 55 };
64 }; 56 };
65 }; 57 };
66 58
67 hdmi-in { 59 hdmi-in {
68 compatible = "hdmi-connector"; 60 compatible = "hdmi-connector";
69 label = "HDMI IN"; 61 label = "HDMI IN";
70 type = "a"; 62 type = "a";
71 63
72 port { 64 port {
73 hdmi_in_con: endpoint 65 hdmi_in_con: endpoint {
74 remote-endpoin 66 remote-endpoint = <&adv7482_hdmi>;
75 }; 67 };
76 }; 68 };
77 }; 69 };
78 70
79 hdmi-out { 71 hdmi-out {
80 compatible = "hdmi-connector"; 72 compatible = "hdmi-connector";
81 type = "a"; 73 type = "a";
82 74
83 port { 75 port {
84 hdmi_con_out: endpoint 76 hdmi_con_out: endpoint {
85 remote-endpoin 77 remote-endpoint = <&adv7511_out>;
86 }; 78 };
87 }; 79 };
88 }; 80 };
89 81
90 keys { 82 keys {
91 compatible = "gpio-keys"; 83 compatible = "gpio-keys";
92 84
93 pinctrl-0 = <&keys_pins>; 85 pinctrl-0 = <&keys_pins>;
94 pinctrl-names = "default"; 86 pinctrl-names = "default";
95 87
96 key-1 { 88 key-1 {
97 gpios = <&gpio5 10 GPI 89 gpios = <&gpio5 10 GPIO_ACTIVE_LOW>;
98 linux,code = <KEY_1>; 90 linux,code = <KEY_1>;
99 label = "SW4-1"; 91 label = "SW4-1";
100 wakeup-source; 92 wakeup-source;
101 debounce-interval = <2 93 debounce-interval = <20>;
102 }; 94 };
103 key-2 { 95 key-2 {
104 gpios = <&gpio5 11 GPI 96 gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
105 linux,code = <KEY_2>; 97 linux,code = <KEY_2>;
106 label = "SW4-2"; 98 label = "SW4-2";
107 wakeup-source; 99 wakeup-source;
108 debounce-interval = <2 100 debounce-interval = <20>;
109 }; 101 };
110 key-3 { 102 key-3 {
111 gpios = <&gpio5 12 GPI 103 gpios = <&gpio5 12 GPIO_ACTIVE_LOW>;
112 linux,code = <KEY_3>; 104 linux,code = <KEY_3>;
113 label = "SW4-3"; 105 label = "SW4-3";
114 wakeup-source; 106 wakeup-source;
115 debounce-interval = <2 107 debounce-interval = <20>;
116 }; 108 };
117 key-4 { 109 key-4 {
118 gpios = <&gpio5 13 GPI 110 gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
119 linux,code = <KEY_4>; 111 linux,code = <KEY_4>;
120 label = "SW4-4"; 112 label = "SW4-4";
121 wakeup-source; 113 wakeup-source;
122 debounce-interval = <2 114 debounce-interval = <20>;
123 }; 115 };
124 }; 116 };
125 117
126 lvds-decoder { 118 lvds-decoder {
127 compatible = "thine,thc63lvd10 119 compatible = "thine,thc63lvd1024";
128 vcc-supply = <®_3p3v>; 120 vcc-supply = <®_3p3v>;
129 121
130 ports { 122 ports {
131 #address-cells = <1>; 123 #address-cells = <1>;
132 #size-cells = <0>; 124 #size-cells = <0>;
133 125
134 port@0 { 126 port@0 {
135 reg = <0>; 127 reg = <0>;
136 thc63lvd1024_i 128 thc63lvd1024_in: endpoint {
137 remote 129 remote-endpoint = <&lvds0_out>;
138 }; 130 };
139 }; 131 };
140 132
141 port@2 { 133 port@2 {
142 reg = <2>; 134 reg = <2>;
143 thc63lvd1024_o 135 thc63lvd1024_out: endpoint {
144 remote 136 remote-endpoint = <&adv7511_in>;
145 }; 137 };
146 }; 138 };
147 }; 139 };
148 }; 140 };
149 141
150 memory@48000000 { 142 memory@48000000 {
151 device_type = "memory"; 143 device_type = "memory";
152 /* first 128MB is reserved for 144 /* first 128MB is reserved for secure area. */
153 reg = <0x0 0x48000000 0x0 0x38 145 reg = <0x0 0x48000000 0x0 0x38000000>;
154 }; 146 };
155 147
156 reg_1p8v: regulator-1p8v { !! 148 reg_1p8v: regulator0 {
157 compatible = "regulator-fixed" 149 compatible = "regulator-fixed";
158 regulator-name = "fixed-1.8V"; 150 regulator-name = "fixed-1.8V";
159 regulator-min-microvolt = <180 151 regulator-min-microvolt = <1800000>;
160 regulator-max-microvolt = <180 152 regulator-max-microvolt = <1800000>;
161 regulator-boot-on; 153 regulator-boot-on;
162 regulator-always-on; 154 regulator-always-on;
163 }; 155 };
164 156
165 reg_3p3v: regulator-3p3v { !! 157 reg_3p3v: regulator1 {
166 compatible = "regulator-fixed" 158 compatible = "regulator-fixed";
167 regulator-name = "fixed-3.3V"; 159 regulator-name = "fixed-3.3V";
168 regulator-min-microvolt = <330 160 regulator-min-microvolt = <3300000>;
169 regulator-max-microvolt = <330 161 regulator-max-microvolt = <3300000>;
170 regulator-boot-on; 162 regulator-boot-on;
171 regulator-always-on; 163 regulator-always-on;
172 }; 164 };
173 165
174 reg_12p0v: regulator-12p0v { !! 166 reg_12p0v: regulator2 {
175 compatible = "regulator-fixed" 167 compatible = "regulator-fixed";
176 regulator-name = "D12.0V"; 168 regulator-name = "D12.0V";
177 regulator-min-microvolt = <120 169 regulator-min-microvolt = <12000000>;
178 regulator-max-microvolt = <120 170 regulator-max-microvolt = <12000000>;
179 regulator-boot-on; 171 regulator-boot-on;
180 regulator-always-on; 172 regulator-always-on;
181 }; 173 };
182 174
183 rsnd_ak4613: sound { 175 rsnd_ak4613: sound {
184 compatible = "simple-audio-car 176 compatible = "simple-audio-card";
185 177
186 simple-audio-card,name = "rsnd 178 simple-audio-card,name = "rsnd-ak4613";
187 simple-audio-card,format = "le 179 simple-audio-card,format = "left_j";
188 simple-audio-card,bitclock-mas 180 simple-audio-card,bitclock-master = <&sndcpu>;
189 simple-audio-card,frame-master 181 simple-audio-card,frame-master = <&sndcpu>;
190 182
191 sndcodec: simple-audio-card,co 183 sndcodec: simple-audio-card,codec {
192 sound-dai = <&ak4613>; 184 sound-dai = <&ak4613>;
193 }; 185 };
194 186
195 sndcpu: simple-audio-card,cpu 187 sndcpu: simple-audio-card,cpu {
196 sound-dai = <&rcar_sou 188 sound-dai = <&rcar_sound>;
197 }; 189 };
198 }; 190 };
199 191
200 vbus0_usb2: regulator-vbus0-usb2 { 192 vbus0_usb2: regulator-vbus0-usb2 {
201 compatible = "regulator-fixed" 193 compatible = "regulator-fixed";
202 194
203 regulator-name = "USB20_VBUS_C 195 regulator-name = "USB20_VBUS_CN";
204 regulator-min-microvolt = <500 196 regulator-min-microvolt = <5000000>;
205 regulator-max-microvolt = <500 197 regulator-max-microvolt = <5000000>;
206 198
207 gpio = <&gpio6 4 GPIO_ACTIVE_H 199 gpio = <&gpio6 4 GPIO_ACTIVE_HIGH>;
208 enable-active-high; 200 enable-active-high;
209 }; 201 };
210 202
211 vcc_sdhi0: regulator-vcc-sdhi0 { 203 vcc_sdhi0: regulator-vcc-sdhi0 {
212 compatible = "regulator-fixed" 204 compatible = "regulator-fixed";
213 205
214 regulator-name = "SDHI0 Vcc"; 206 regulator-name = "SDHI0 Vcc";
215 regulator-min-microvolt = <330 207 regulator-min-microvolt = <3300000>;
216 regulator-max-microvolt = <330 208 regulator-max-microvolt = <3300000>;
217 209
218 gpio = <&gpio5 17 GPIO_ACTIVE_ 210 gpio = <&gpio5 17 GPIO_ACTIVE_HIGH>;
219 enable-active-high; 211 enable-active-high;
220 }; 212 };
221 213
222 vccq_sdhi0: regulator-vccq-sdhi0 { 214 vccq_sdhi0: regulator-vccq-sdhi0 {
223 compatible = "regulator-gpio"; 215 compatible = "regulator-gpio";
224 216
225 regulator-name = "SDHI0 VccQ"; 217 regulator-name = "SDHI0 VccQ";
226 regulator-min-microvolt = <180 218 regulator-min-microvolt = <1800000>;
227 regulator-max-microvolt = <330 219 regulator-max-microvolt = <3300000>;
228 220
229 gpios = <&gpio5 18 GPIO_ACTIVE 221 gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
230 gpios-states = <1>; 222 gpios-states = <1>;
231 states = <3300000 1>, <1800000 223 states = <3300000 1>, <1800000 0>;
232 }; 224 };
233 225
234 vcc_sdhi1: regulator-vcc-sdhi1 { 226 vcc_sdhi1: regulator-vcc-sdhi1 {
235 compatible = "regulator-fixed" 227 compatible = "regulator-fixed";
236 228
237 regulator-name = "SDHI1 Vcc"; 229 regulator-name = "SDHI1 Vcc";
238 regulator-min-microvolt = <330 230 regulator-min-microvolt = <3300000>;
239 regulator-max-microvolt = <330 231 regulator-max-microvolt = <3300000>;
240 232
241 gpio = <&gpio0 4 GPIO_ACTIVE_H 233 gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>;
242 enable-active-high; 234 enable-active-high;
243 }; 235 };
244 236
245 vccq_sdhi1: regulator-vccq-sdhi1 { 237 vccq_sdhi1: regulator-vccq-sdhi1 {
246 compatible = "regulator-gpio"; 238 compatible = "regulator-gpio";
247 239
248 regulator-name = "SDHI1 VccQ"; 240 regulator-name = "SDHI1 VccQ";
249 regulator-min-microvolt = <180 241 regulator-min-microvolt = <1800000>;
250 regulator-max-microvolt = <330 242 regulator-max-microvolt = <3300000>;
251 243
252 gpios = <&gpio3 15 GPIO_ACTIVE 244 gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
253 gpios-states = <1>; 245 gpios-states = <1>;
254 states = <3300000 1>, <1800000 246 states = <3300000 1>, <1800000 0>;
255 }; 247 };
256 248
257 vga { 249 vga {
258 compatible = "vga-connector"; 250 compatible = "vga-connector";
259 251
260 port { 252 port {
261 vga_in: endpoint { 253 vga_in: endpoint {
262 remote-endpoin 254 remote-endpoint = <&adv7123_out>;
263 }; 255 };
264 }; 256 };
265 }; 257 };
266 258
267 vga-encoder { 259 vga-encoder {
268 compatible = "adi,adv7123"; 260 compatible = "adi,adv7123";
269 261
270 ports { 262 ports {
271 #address-cells = <1>; 263 #address-cells = <1>;
272 #size-cells = <0>; 264 #size-cells = <0>;
273 265
274 port@0 { 266 port@0 {
275 reg = <0>; 267 reg = <0>;
276 adv7123_in: en 268 adv7123_in: endpoint {
277 remote 269 remote-endpoint = <&du_out_rgb>;
278 }; 270 };
279 }; 271 };
280 port@1 { 272 port@1 {
281 reg = <1>; 273 reg = <1>;
282 adv7123_out: e 274 adv7123_out: endpoint {
283 remote 275 remote-endpoint = <&vga_in>;
284 }; 276 };
285 }; 277 };
286 }; 278 };
287 }; 279 };
288 280
289 x12_clk: x12 { 281 x12_clk: x12 {
290 compatible = "fixed-clock"; 282 compatible = "fixed-clock";
291 #clock-cells = <0>; 283 #clock-cells = <0>;
292 clock-frequency = <24576000>; 284 clock-frequency = <24576000>;
293 }; 285 };
294 286
295 x13_clk: x13 { 287 x13_clk: x13 {
296 compatible = "fixed-clock"; 288 compatible = "fixed-clock";
297 #clock-cells = <0>; 289 #clock-cells = <0>;
298 clock-frequency = <74250000>; 290 clock-frequency = <74250000>;
299 }; 291 };
300 }; 292 };
301 293
302 &audio_clk_a { 294 &audio_clk_a {
303 clock-frequency = <22579200>; 295 clock-frequency = <22579200>;
304 }; 296 };
305 297
306 &avb { 298 &avb {
307 pinctrl-0 = <&avb_pins>; 299 pinctrl-0 = <&avb_pins>;
308 pinctrl-names = "default"; 300 pinctrl-names = "default";
309 phy-handle = <&phy0>; 301 phy-handle = <&phy0>;
310 status = "okay"; 302 status = "okay";
311 303
312 phy0: ethernet-phy@0 { 304 phy0: ethernet-phy@0 {
313 compatible = "ethernet-phy-id0 305 compatible = "ethernet-phy-id0022.1622",
314 "ethernet-phy-iee 306 "ethernet-phy-ieee802.3-c22";
315 rxc-skew-ps = <1500>; 307 rxc-skew-ps = <1500>;
316 reg = <0>; 308 reg = <0>;
317 interrupt-parent = <&gpio2>; 309 interrupt-parent = <&gpio2>;
318 interrupts = <21 IRQ_TYPE_LEVE 310 interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
319 reset-gpios = <&gpio1 20 GPIO_ 311 reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
320 /* 312 /*
321 * TX clock internal delay mod 313 * TX clock internal delay mode is required for reliable
322 * 1Gbps communication using t 314 * 1Gbps communication using the KSZ9031RNX phy present on
323 * the Ebisu board, however, T 315 * the Ebisu board, however, TX clock internal delay mode
324 * isn't supported on R-Car E3 316 * isn't supported on R-Car E3(e). Thus, limit speed to
325 * 100Mbps for reliable commun 317 * 100Mbps for reliable communication.
326 */ 318 */
327 max-speed = <100>; 319 max-speed = <100>;
328 }; 320 };
329 }; 321 };
330 322
331 &canfd { 323 &canfd {
332 pinctrl-0 = <&canfd0_pins>; 324 pinctrl-0 = <&canfd0_pins>;
333 pinctrl-names = "default"; 325 pinctrl-names = "default";
334 status = "okay"; 326 status = "okay";
335 327
336 channel0 { 328 channel0 {
337 status = "okay"; 329 status = "okay";
338 }; 330 };
339 }; 331 };
340 332
341 &csi40 { 333 &csi40 {
342 status = "okay"; 334 status = "okay";
343 335
344 ports { 336 ports {
345 port@0 { 337 port@0 {
346 csi40_in: endpoint { 338 csi40_in: endpoint {
347 clock-lanes = 339 clock-lanes = <0>;
348 data-lanes = < 340 data-lanes = <1 2>;
349 remote-endpoin 341 remote-endpoint = <&adv7482_txa>;
350 }; 342 };
351 }; 343 };
352 }; 344 };
353 }; 345 };
354 346
355 &du { 347 &du {
356 pinctrl-0 = <&du_pins>; 348 pinctrl-0 = <&du_pins>;
357 pinctrl-names = "default"; 349 pinctrl-names = "default";
358 status = "okay"; 350 status = "okay";
359 351
360 clocks = <&cpg CPG_MOD 724>, 352 clocks = <&cpg CPG_MOD 724>,
361 <&cpg CPG_MOD 723>, 353 <&cpg CPG_MOD 723>,
362 <&x13_clk>; 354 <&x13_clk>;
363 clock-names = "du.0", "du.1", "dclkin. 355 clock-names = "du.0", "du.1", "dclkin.0";
364 356
365 ports { 357 ports {
366 port@0 { 358 port@0 {
367 du_out_rgb: endpoint { 359 du_out_rgb: endpoint {
368 remote-endpoin 360 remote-endpoint = <&adv7123_in>;
369 }; 361 };
370 }; 362 };
371 }; 363 };
372 }; 364 };
373 365
374 &ehci0 { 366 &ehci0 {
375 dr_mode = "otg"; 367 dr_mode = "otg";
376 status = "okay"; 368 status = "okay";
377 }; 369 };
378 370
379 &extal_clk { 371 &extal_clk {
380 clock-frequency = <48000000>; 372 clock-frequency = <48000000>;
381 }; 373 };
382 374
383 &hsusb { 375 &hsusb {
384 dr_mode = "otg"; 376 dr_mode = "otg";
385 status = "okay"; 377 status = "okay";
386 }; 378 };
387 379
388 &i2c0 { 380 &i2c0 {
389 status = "okay"; 381 status = "okay";
390 382
391 io_expander: gpio@20 { 383 io_expander: gpio@20 {
392 compatible = "onnn,pca9654"; 384 compatible = "onnn,pca9654";
393 reg = <0x20>; 385 reg = <0x20>;
394 gpio-controller; 386 gpio-controller;
395 #gpio-cells = <2>; 387 #gpio-cells = <2>;
396 interrupt-parent = <&gpio2>; 388 interrupt-parent = <&gpio2>;
397 interrupts = <22 IRQ_TYPE_LEVE 389 interrupts = <22 IRQ_TYPE_LEVEL_LOW>;
398 }; 390 };
399 391
400 hdmi-encoder@39 { 392 hdmi-encoder@39 {
401 compatible = "adi,adv7511w"; 393 compatible = "adi,adv7511w";
402 reg = <0x39>; 394 reg = <0x39>;
403 interrupt-parent = <&gpio1>; 395 interrupt-parent = <&gpio1>;
404 interrupts = <1 IRQ_TYPE_LEVEL 396 interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
405 397
406 avdd-supply = <®_1p8v>; <<
407 dvdd-supply = <®_1p8v>; <<
408 pvdd-supply = <®_1p8v>; <<
409 dvdd-3v-supply = <®_3p3v>; <<
410 bgvdd-supply = <®_1p8v>; <<
411 <<
412 adi,input-depth = <8>; 398 adi,input-depth = <8>;
413 adi,input-colorspace = "rgb"; 399 adi,input-colorspace = "rgb";
414 adi,input-clock = "1x"; 400 adi,input-clock = "1x";
415 401
416 ports { 402 ports {
417 #address-cells = <1>; 403 #address-cells = <1>;
418 #size-cells = <0>; 404 #size-cells = <0>;
419 405
420 port@0 { 406 port@0 {
421 reg = <0>; 407 reg = <0>;
422 adv7511_in: en 408 adv7511_in: endpoint {
423 remote 409 remote-endpoint = <&thc63lvd1024_out>;
424 }; 410 };
425 }; 411 };
426 412
427 port@1 { 413 port@1 {
428 reg = <1>; 414 reg = <1>;
429 adv7511_out: e 415 adv7511_out: endpoint {
430 remote 416 remote-endpoint = <&hdmi_con_out>;
431 }; 417 };
432 }; 418 };
433 }; 419 };
434 }; 420 };
435 421
436 video-receiver@70 { 422 video-receiver@70 {
437 compatible = "adi,adv7482"; 423 compatible = "adi,adv7482";
438 reg = <0x70>; 424 reg = <0x70>;
439 425
440 interrupt-parent = <&gpio0>; 426 interrupt-parent = <&gpio0>;
441 interrupt-names = "intrq1", "i 427 interrupt-names = "intrq1", "intrq2";
442 interrupts = <7 IRQ_TYPE_LEVEL 428 interrupts = <7 IRQ_TYPE_LEVEL_LOW>,
443 <17 IRQ_TYPE_LEVE 429 <17 IRQ_TYPE_LEVEL_LOW>;
444 430
445 ports { 431 ports {
446 #address-cells = <1>; 432 #address-cells = <1>;
447 #size-cells = <0>; 433 #size-cells = <0>;
448 434
449 port@7 { 435 port@7 {
450 reg = <7>; 436 reg = <7>;
451 437
452 adv7482_ain7: 438 adv7482_ain7: endpoint {
453 remote 439 remote-endpoint = <&cvbs_con>;
454 }; 440 };
455 }; 441 };
456 442
457 port@8 { 443 port@8 {
458 reg = <8>; 444 reg = <8>;
459 445
460 adv7482_hdmi: 446 adv7482_hdmi: endpoint {
461 remote 447 remote-endpoint = <&hdmi_in_con>;
462 }; 448 };
463 }; 449 };
464 450
465 port@a { 451 port@a {
466 reg = <10>; 452 reg = <10>;
467 453
468 adv7482_txa: e 454 adv7482_txa: endpoint {
469 clock- 455 clock-lanes = <0>;
470 data-l 456 data-lanes = <1 2>;
471 remote 457 remote-endpoint = <&csi40_in>;
472 }; 458 };
473 }; 459 };
474 }; 460 };
475 }; 461 };
476 }; 462 };
477 463
478 &i2c3 { 464 &i2c3 {
479 status = "okay"; 465 status = "okay";
480 466
481 ak4613: codec@10 { 467 ak4613: codec@10 {
482 compatible = "asahi-kasei,ak46 468 compatible = "asahi-kasei,ak4613";
483 #sound-dai-cells = <0>; 469 #sound-dai-cells = <0>;
484 reg = <0x10>; 470 reg = <0x10>;
485 clocks = <&rcar_sound 3>; 471 clocks = <&rcar_sound 3>;
486 472
487 asahi-kasei,in1-single-end; 473 asahi-kasei,in1-single-end;
488 asahi-kasei,in2-single-end; 474 asahi-kasei,in2-single-end;
489 asahi-kasei,out1-single-end; 475 asahi-kasei,out1-single-end;
490 asahi-kasei,out2-single-end; 476 asahi-kasei,out2-single-end;
491 asahi-kasei,out3-single-end; 477 asahi-kasei,out3-single-end;
492 asahi-kasei,out4-single-end; 478 asahi-kasei,out4-single-end;
493 asahi-kasei,out5-single-end; 479 asahi-kasei,out5-single-end;
494 asahi-kasei,out6-single-end; 480 asahi-kasei,out6-single-end;
495 }; 481 };
496 482
497 cs2000: clk-multiplier@4f { 483 cs2000: clk-multiplier@4f {
498 #clock-cells = <0>; 484 #clock-cells = <0>;
499 compatible = "cirrus,cs2000-cp 485 compatible = "cirrus,cs2000-cp";
500 reg = <0x4f>; 486 reg = <0x4f>;
501 clocks = <&audio_clkout>, <&x1 487 clocks = <&audio_clkout>, <&x12_clk>;
502 clock-names = "clk_in", "ref_c 488 clock-names = "clk_in", "ref_clk";
503 489
504 assigned-clocks = <&cs2000>; 490 assigned-clocks = <&cs2000>;
505 assigned-clock-rates = <245760 491 assigned-clock-rates = <24576000>; /* 1/1 divide */
506 }; 492 };
507 }; 493 };
508 494
509 &i2c_dvfs { 495 &i2c_dvfs {
510 status = "okay"; 496 status = "okay";
511 497
512 clock-frequency = <400000>; 498 clock-frequency = <400000>;
513 499
514 pmic: pmic@30 { 500 pmic: pmic@30 {
515 pinctrl-0 = <&irq0_pins>; 501 pinctrl-0 = <&irq0_pins>;
516 pinctrl-names = "default"; 502 pinctrl-names = "default";
517 503
518 compatible = "rohm,bd9571mwv"; 504 compatible = "rohm,bd9571mwv";
519 reg = <0x30>; 505 reg = <0x30>;
520 interrupt-parent = <&intc_ex>; 506 interrupt-parent = <&intc_ex>;
521 interrupts = <0 IRQ_TYPE_LEVEL 507 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
522 interrupt-controller; 508 interrupt-controller;
523 #interrupt-cells = <2>; 509 #interrupt-cells = <2>;
524 gpio-controller; 510 gpio-controller;
525 #gpio-cells = <2>; 511 #gpio-cells = <2>;
526 rohm,ddr-backup-power = <0x1>; 512 rohm,ddr-backup-power = <0x1>;
527 rohm,rstbmode-level; 513 rohm,rstbmode-level;
528 }; 514 };
529 515
530 eeprom@50 { 516 eeprom@50 {
531 compatible = "rohm,br24t01", " 517 compatible = "rohm,br24t01", "atmel,24c01";
532 reg = <0x50>; 518 reg = <0x50>;
533 pagesize = <8>; 519 pagesize = <8>;
534 }; 520 };
535 }; 521 };
536 522
537 &lvds0 { 523 &lvds0 {
538 status = "okay"; 524 status = "okay";
539 525
540 clocks = <&cpg CPG_MOD 727>, 526 clocks = <&cpg CPG_MOD 727>,
541 <&x13_clk>, 527 <&x13_clk>,
542 <&extal_clk>; 528 <&extal_clk>;
543 clock-names = "fck", "dclkin.0", "exta 529 clock-names = "fck", "dclkin.0", "extal";
544 530
545 ports { 531 ports {
546 port@1 { 532 port@1 {
547 lvds0_out: endpoint { 533 lvds0_out: endpoint {
548 remote-endpoin 534 remote-endpoint = <&thc63lvd1024_in>;
549 }; 535 };
550 }; 536 };
551 }; 537 };
552 }; 538 };
553 539
554 &lvds1 { 540 &lvds1 {
555 /* 541 /*
556 * Even though the LVDS1 output is not 542 * Even though the LVDS1 output is not connected, the encoder must be
557 * enabled to supply a pixel clock to 543 * enabled to supply a pixel clock to the DU for the DPAD output when
558 * LVDS0 is in use. 544 * LVDS0 is in use.
559 */ 545 */
560 status = "okay"; 546 status = "okay";
561 547
562 clocks = <&cpg CPG_MOD 727>, 548 clocks = <&cpg CPG_MOD 727>,
563 <&x13_clk>, 549 <&x13_clk>,
564 <&extal_clk>; 550 <&extal_clk>;
565 clock-names = "fck", "dclkin.0", "exta 551 clock-names = "fck", "dclkin.0", "extal";
566 }; 552 };
567 553
568 &ohci0 { 554 &ohci0 {
569 dr_mode = "otg"; 555 dr_mode = "otg";
570 status = "okay"; 556 status = "okay";
571 }; 557 };
572 558
573 &pcie_bus_clk { 559 &pcie_bus_clk {
574 clock-frequency = <100000000>; 560 clock-frequency = <100000000>;
575 }; 561 };
576 562
577 &pciec0 { 563 &pciec0 {
578 status = "okay"; 564 status = "okay";
579 }; 565 };
580 566
581 &pfc { 567 &pfc {
582 avb_pins: avb { 568 avb_pins: avb {
583 groups = "avb_link", "avb_mii" 569 groups = "avb_link", "avb_mii";
584 function = "avb"; 570 function = "avb";
585 }; 571 };
586 572
587 canfd0_pins: canfd0 { 573 canfd0_pins: canfd0 {
588 groups = "canfd0_data"; 574 groups = "canfd0_data";
589 function = "canfd0"; 575 function = "canfd0";
590 }; 576 };
591 577
592 du_pins: du { 578 du_pins: du {
593 groups = "du_rgb888", "du_sync 579 groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
594 function = "du"; 580 function = "du";
595 }; 581 };
596 582
597 irq0_pins: irq0 { 583 irq0_pins: irq0 {
598 groups = "intc_ex_irq0"; 584 groups = "intc_ex_irq0";
599 function = "intc_ex"; 585 function = "intc_ex";
600 }; 586 };
601 587
602 keys_pins: keys { 588 keys_pins: keys {
603 pins = "GP_5_10", "GP_5_11", " 589 pins = "GP_5_10", "GP_5_11", "GP_5_12", "GP_5_13";
604 bias-pull-up; 590 bias-pull-up;
605 }; 591 };
606 592
607 pwm3_pins: pwm3 { 593 pwm3_pins: pwm3 {
608 groups = "pwm3_b"; 594 groups = "pwm3_b";
609 function = "pwm3"; 595 function = "pwm3";
610 }; 596 };
611 597
612 pwm5_pins: pwm5 { 598 pwm5_pins: pwm5 {
613 groups = "pwm5_a"; 599 groups = "pwm5_a";
614 function = "pwm5"; 600 function = "pwm5";
615 }; 601 };
616 602
617 rpc_pins: rpc { 603 rpc_pins: rpc {
618 groups = "rpc_clk2", "rpc_ctrl 604 groups = "rpc_clk2", "rpc_ctrl", "rpc_data", "rpc_reset",
619 "rpc_int"; 605 "rpc_int";
620 function = "rpc"; 606 function = "rpc";
621 }; 607 };
622 608
623 scif2_pins: scif2 { 609 scif2_pins: scif2 {
624 groups = "scif2_data_a"; 610 groups = "scif2_data_a";
625 function = "scif2"; 611 function = "scif2";
626 }; 612 };
627 613
628 sdhi0_pins: sd0 { 614 sdhi0_pins: sd0 {
629 groups = "sdhi0_data4", "sdhi0 615 groups = "sdhi0_data4", "sdhi0_ctrl";
630 function = "sdhi0"; 616 function = "sdhi0";
631 power-source = <3300>; 617 power-source = <3300>;
632 }; 618 };
633 619
634 sdhi0_pins_uhs: sd0_uhs { 620 sdhi0_pins_uhs: sd0_uhs {
635 groups = "sdhi0_data4", "sdhi0 621 groups = "sdhi0_data4", "sdhi0_ctrl";
636 function = "sdhi0"; 622 function = "sdhi0";
637 power-source = <1800>; 623 power-source = <1800>;
638 }; 624 };
639 625
640 sdhi1_pins: sd1 { 626 sdhi1_pins: sd1 {
641 groups = "sdhi1_data4", "sdhi1 627 groups = "sdhi1_data4", "sdhi1_ctrl";
642 function = "sdhi1"; 628 function = "sdhi1";
643 power-source = <3300>; 629 power-source = <3300>;
644 }; 630 };
645 631
646 sdhi1_pins_uhs: sd1_uhs { 632 sdhi1_pins_uhs: sd1_uhs {
647 groups = "sdhi1_data4", "sdhi1 633 groups = "sdhi1_data4", "sdhi1_ctrl";
648 function = "sdhi1"; 634 function = "sdhi1";
649 power-source = <1800>; 635 power-source = <1800>;
650 }; 636 };
651 637
652 sdhi3_pins: sd3 { 638 sdhi3_pins: sd3 {
653 groups = "sdhi3_data8", "sdhi3 639 groups = "sdhi3_data8", "sdhi3_ctrl", "sdhi3_ds";
654 function = "sdhi3"; 640 function = "sdhi3";
655 power-source = <1800>; 641 power-source = <1800>;
656 }; 642 };
657 643
658 sound_clk_pins: sound_clk { 644 sound_clk_pins: sound_clk {
659 groups = "audio_clk_a", "audio 645 groups = "audio_clk_a", "audio_clk_b_a", "audio_clk_c_a",
660 "audio_clkout_a", "au 646 "audio_clkout_a", "audio_clkout1_a";
661 function = "audio_clk"; 647 function = "audio_clk";
662 }; 648 };
663 649
664 sound_pins: sound { 650 sound_pins: sound {
665 groups = "ssi01239_ctrl", "ssi 651 groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data";
666 function = "ssi"; 652 function = "ssi";
667 }; 653 };
668 654
669 usb0_pins: usb { 655 usb0_pins: usb {
670 groups = "usb0_b", "usb0_id"; 656 groups = "usb0_b", "usb0_id";
671 function = "usb0"; 657 function = "usb0";
672 }; 658 };
673 659
674 usb30_pins: usb30 { 660 usb30_pins: usb30 {
675 groups = "usb30"; 661 groups = "usb30";
676 function = "usb30"; 662 function = "usb30";
677 }; 663 };
678 }; 664 };
679 665
680 &pwm3 { 666 &pwm3 {
681 pinctrl-0 = <&pwm3_pins>; 667 pinctrl-0 = <&pwm3_pins>;
682 pinctrl-names = "default"; 668 pinctrl-names = "default";
683 669
684 status = "okay"; 670 status = "okay";
685 }; 671 };
686 672
687 &pwm5 { 673 &pwm5 {
688 pinctrl-0 = <&pwm5_pins>; 674 pinctrl-0 = <&pwm5_pins>;
689 pinctrl-names = "default"; 675 pinctrl-names = "default";
690 676
691 status = "okay"; 677 status = "okay";
692 }; 678 };
693 679
694 &rcar_sound { 680 &rcar_sound {
695 pinctrl-0 = <&sound_pins>, <&sound_clk 681 pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
696 pinctrl-names = "default"; 682 pinctrl-names = "default";
697 683
698 /* Single DAI */ 684 /* Single DAI */
699 #sound-dai-cells = <0>; 685 #sound-dai-cells = <0>;
700 686
701 /* audio_clkout0/1/2/3 */ 687 /* audio_clkout0/1/2/3 */
702 #clock-cells = <1>; 688 #clock-cells = <1>;
703 clock-frequency = <12288000 11289600>; 689 clock-frequency = <12288000 11289600>;
704 690
705 status = "okay"; 691 status = "okay";
706 692
707 /* update <audio_clk_b> to <cs2000> */ 693 /* update <audio_clk_b> to <cs2000> */
708 clocks = <&cpg CPG_MOD 1005>, 694 clocks = <&cpg CPG_MOD 1005>,
709 <&cpg CPG_MOD 1006>, <&cpg CP 695 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
710 <&cpg CPG_MOD 1008>, <&cpg CP 696 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
711 <&cpg CPG_MOD 1010>, <&cpg CP 697 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
712 <&cpg CPG_MOD 1012>, <&cpg CP 698 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
713 <&cpg CPG_MOD 1014>, <&cpg CP 699 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
714 <&cpg CPG_MOD 1022>, <&cpg CP 700 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
715 <&cpg CPG_MOD 1024>, <&cpg CP 701 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
716 <&cpg CPG_MOD 1026>, <&cpg CP 702 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
717 <&cpg CPG_MOD 1028>, <&cpg CP 703 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
718 <&cpg CPG_MOD 1030>, <&cpg CP 704 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
719 <&cpg CPG_MOD 1020>, <&cpg CP 705 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
720 <&cpg CPG_MOD 1020>, <&cpg CP 706 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
721 <&cpg CPG_MOD 1019>, <&cpg CP 707 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
722 <&audio_clk_a>, <&cs2000>, <& 708 <&audio_clk_a>, <&cs2000>, <&audio_clk_c>,
723 <&cpg CPG_CORE R8A77990_CLK_Z 709 <&cpg CPG_CORE R8A77990_CLK_ZA2>;
724 710
725 rcar_sound,dai { 711 rcar_sound,dai {
726 dai0 { 712 dai0 {
727 playback = <&ssi0>, <& 713 playback = <&ssi0>, <&src0>, <&dvc0>;
728 capture = <&ssi1>, <&s !! 714 capture = <&ssi1>, <&src1>, <&dvc1>;
729 }; 715 };
730 }; 716 };
731 717
732 }; 718 };
733 719
734 &rpc { 720 &rpc {
735 pinctrl-0 = <&rpc_pins>; 721 pinctrl-0 = <&rpc_pins>;
736 pinctrl-names = "default"; 722 pinctrl-names = "default";
737 723
738 /* Left disabled. To be enabled by fi 724 /* Left disabled. To be enabled by firmware when unlocked. */
739 725
740 flash@0 { 726 flash@0 {
741 compatible = "cypress,hyperfla 727 compatible = "cypress,hyperflash", "cfi-flash";
742 reg = <0>; 728 reg = <0>;
743 729
744 partitions { 730 partitions {
745 compatible = "fixed-pa 731 compatible = "fixed-partitions";
746 #address-cells = <1>; 732 #address-cells = <1>;
747 #size-cells = <1>; 733 #size-cells = <1>;
748 734
749 bootparam@0 { 735 bootparam@0 {
750 reg = <0x00000 736 reg = <0x00000000 0x040000>;
751 read-only; 737 read-only;
752 }; 738 };
753 bl2@40000 { 739 bl2@40000 {
754 reg = <0x00040 740 reg = <0x00040000 0x140000>;
755 read-only; 741 read-only;
756 }; 742 };
757 cert_header_sa6@180000 743 cert_header_sa6@180000 {
758 reg = <0x00180 744 reg = <0x00180000 0x040000>;
759 read-only; 745 read-only;
760 }; 746 };
761 bl31@1c0000 { 747 bl31@1c0000 {
762 reg = <0x001c0 748 reg = <0x001c0000 0x040000>;
763 read-only; 749 read-only;
764 }; 750 };
765 tee@200000 { 751 tee@200000 {
766 reg = <0x00200 752 reg = <0x00200000 0x440000>;
767 read-only; 753 read-only;
768 }; 754 };
769 uboot@640000 { 755 uboot@640000 {
770 reg = <0x00640 756 reg = <0x00640000 0x100000>;
771 read-only; 757 read-only;
772 }; 758 };
773 dtb@740000 { 759 dtb@740000 {
774 reg = <0x00740 760 reg = <0x00740000 0x080000>;
775 }; 761 };
776 kernel@7c0000 { 762 kernel@7c0000 {
777 reg = <0x007c0 763 reg = <0x007c0000 0x1400000>;
778 }; 764 };
779 user@1bc0000 { 765 user@1bc0000 {
780 reg = <0x01bc0 766 reg = <0x01bc0000 0x2440000>;
781 }; 767 };
782 }; 768 };
783 }; 769 };
784 }; 770 };
785 771
786 &rwdt { 772 &rwdt {
787 timeout-sec = <60>; 773 timeout-sec = <60>;
788 status = "okay"; 774 status = "okay";
789 }; 775 };
790 776
791 &scif2 { 777 &scif2 {
792 pinctrl-0 = <&scif2_pins>; 778 pinctrl-0 = <&scif2_pins>;
793 pinctrl-names = "default"; 779 pinctrl-names = "default";
794 780
795 status = "okay"; 781 status = "okay";
796 }; 782 };
797 783
798 &sdhi0 { 784 &sdhi0 {
799 pinctrl-0 = <&sdhi0_pins>; 785 pinctrl-0 = <&sdhi0_pins>;
800 pinctrl-1 = <&sdhi0_pins_uhs>; 786 pinctrl-1 = <&sdhi0_pins_uhs>;
801 pinctrl-names = "default", "state_uhs" 787 pinctrl-names = "default", "state_uhs";
802 788
803 vmmc-supply = <&vcc_sdhi0>; 789 vmmc-supply = <&vcc_sdhi0>;
804 vqmmc-supply = <&vccq_sdhi0>; 790 vqmmc-supply = <&vccq_sdhi0>;
805 cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW> 791 cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
806 wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH 792 wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
807 bus-width = <4>; 793 bus-width = <4>;
808 sd-uhs-sdr50; 794 sd-uhs-sdr50;
809 sd-uhs-sdr104; 795 sd-uhs-sdr104;
810 status = "okay"; 796 status = "okay";
811 }; 797 };
812 798
813 &sdhi1 { 799 &sdhi1 {
814 pinctrl-0 = <&sdhi1_pins>; 800 pinctrl-0 = <&sdhi1_pins>;
815 pinctrl-1 = <&sdhi1_pins_uhs>; 801 pinctrl-1 = <&sdhi1_pins_uhs>;
816 pinctrl-names = "default", "state_uhs" 802 pinctrl-names = "default", "state_uhs";
817 803
818 vmmc-supply = <&vcc_sdhi1>; 804 vmmc-supply = <&vcc_sdhi1>;
819 vqmmc-supply = <&vccq_sdhi1>; 805 vqmmc-supply = <&vccq_sdhi1>;
820 cd-gpios = <&gpio3 14 GPIO_ACTIVE_LOW> 806 cd-gpios = <&gpio3 14 GPIO_ACTIVE_LOW>;
821 bus-width = <4>; 807 bus-width = <4>;
822 sd-uhs-sdr50; 808 sd-uhs-sdr50;
823 sd-uhs-sdr104; 809 sd-uhs-sdr104;
824 status = "okay"; 810 status = "okay";
825 }; 811 };
826 812
827 &sdhi3 { 813 &sdhi3 {
828 /* used for on-board 8bit eMMC */ 814 /* used for on-board 8bit eMMC */
829 pinctrl-0 = <&sdhi3_pins>; 815 pinctrl-0 = <&sdhi3_pins>;
830 pinctrl-1 = <&sdhi3_pins>; 816 pinctrl-1 = <&sdhi3_pins>;
831 pinctrl-names = "default", "state_uhs" 817 pinctrl-names = "default", "state_uhs";
832 818
833 vmmc-supply = <®_3p3v>; 819 vmmc-supply = <®_3p3v>;
834 vqmmc-supply = <®_1p8v>; 820 vqmmc-supply = <®_1p8v>;
835 mmc-hs200-1_8v; 821 mmc-hs200-1_8v;
836 mmc-hs400-1_8v; 822 mmc-hs400-1_8v;
837 bus-width = <8>; 823 bus-width = <8>;
838 no-sd; 824 no-sd;
839 no-sdio; 825 no-sdio;
840 non-removable; 826 non-removable;
841 full-pwr-cycle-in-suspend; 827 full-pwr-cycle-in-suspend;
842 status = "okay"; 828 status = "okay";
843 }; 829 };
844 830
845 &ssi1 { 831 &ssi1 {
846 shared-pin; 832 shared-pin;
847 }; 833 };
848 834
849 &usb2_phy0 { 835 &usb2_phy0 {
850 pinctrl-0 = <&usb0_pins>; 836 pinctrl-0 = <&usb0_pins>;
851 pinctrl-names = "default"; 837 pinctrl-names = "default";
852 838
853 vbus-supply = <&vbus0_usb2>; 839 vbus-supply = <&vbus0_usb2>;
854 status = "okay"; 840 status = "okay";
855 }; 841 };
856 842
857 &usb3_peri0 { 843 &usb3_peri0 {
858 companion = <&xhci0>; 844 companion = <&xhci0>;
859 status = "okay"; 845 status = "okay";
860 }; 846 };
861 847
862 &vin4 { 848 &vin4 {
863 status = "okay"; 849 status = "okay";
864 }; 850 };
865 851
866 &vin5 { 852 &vin5 {
867 status = "okay"; 853 status = "okay";
868 }; 854 };
869 855
870 &xhci0 { 856 &xhci0 {
871 pinctrl-0 = <&usb30_pins>; 857 pinctrl-0 = <&usb30_pins>;
872 pinctrl-names = "default"; 858 pinctrl-names = "default";
873 859
874 status = "okay"; 860 status = "okay";
875 }; 861 };
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