1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * Device Tree Source for the Ebisu/Ebisu-4D b !! 3 * Device Tree Source for the Ebisu board
4 * 4 *
5 * Copyright (C) 2018 Renesas Electronics Corp 5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */ 6 */
7 7
8 #include <dt-bindings/gpio/gpio.h> 8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h> 9 #include <dt-bindings/input/input.h>
10 10
11 / { 11 / {
12 model = "Renesas Ebisu board"; 12 model = "Renesas Ebisu board";
13 compatible = "renesas,ebisu"; 13 compatible = "renesas,ebisu";
14 14
15 aliases { 15 aliases {
16 i2c0 = &i2c0; 16 i2c0 = &i2c0;
17 i2c1 = &i2c1; 17 i2c1 = &i2c1;
18 i2c2 = &i2c2; 18 i2c2 = &i2c2;
19 i2c3 = &i2c3; 19 i2c3 = &i2c3;
20 i2c4 = &i2c4; 20 i2c4 = &i2c4;
21 i2c5 = &i2c5; 21 i2c5 = &i2c5;
22 i2c6 = &i2c6; 22 i2c6 = &i2c6;
23 i2c7 = &i2c7; 23 i2c7 = &i2c7;
24 serial0 = &scif2; 24 serial0 = &scif2;
25 ethernet0 = &avb; 25 ethernet0 = &avb;
26 mmc0 = &sdhi3; 26 mmc0 = &sdhi3;
27 mmc1 = &sdhi0; 27 mmc1 = &sdhi0;
28 mmc2 = &sdhi1; 28 mmc2 = &sdhi1;
29 }; 29 };
30 30
31 chosen { 31 chosen {
32 bootargs = "ignore_loglevel rw 32 bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
33 stdout-path = "serial0:115200n 33 stdout-path = "serial0:115200n8";
34 }; 34 };
35 35
36 audio_clkout: audio-clkout { 36 audio_clkout: audio-clkout {
37 /* 37 /*
38 * This is same as <&rcar_soun 38 * This is same as <&rcar_sound 0>
39 * but needed to avoid cs2000/ 39 * but needed to avoid cs2000/rcar_sound probe dead-lock
40 */ 40 */
41 compatible = "fixed-clock"; 41 compatible = "fixed-clock";
42 #clock-cells = <0>; 42 #clock-cells = <0>;
43 clock-frequency = <11289600>; 43 clock-frequency = <11289600>;
44 }; 44 };
45 45
46 backlight: backlight { 46 backlight: backlight {
47 compatible = "pwm-backlight"; 47 compatible = "pwm-backlight";
48 pwms = <&pwm3 0 50000>; 48 pwms = <&pwm3 0 50000>;
49 49
50 brightness-levels = <512 511 5 50 brightness-levels = <512 511 505 494 473 440 392 327 241 133 0>;
51 default-brightness-level = <10 51 default-brightness-level = <10>;
52 52
53 power-supply = <®_12p0v>; 53 power-supply = <®_12p0v>;
54 }; 54 };
55 55
56 cvbs-in { 56 cvbs-in {
57 compatible = "composite-video- 57 compatible = "composite-video-connector";
58 label = "CVBS IN"; 58 label = "CVBS IN";
59 59
60 port { 60 port {
61 cvbs_con: endpoint { 61 cvbs_con: endpoint {
62 remote-endpoin 62 remote-endpoint = <&adv7482_ain7>;
63 }; 63 };
64 }; 64 };
65 }; 65 };
66 66
67 hdmi-in { 67 hdmi-in {
68 compatible = "hdmi-connector"; 68 compatible = "hdmi-connector";
69 label = "HDMI IN"; 69 label = "HDMI IN";
70 type = "a"; 70 type = "a";
71 71
72 port { 72 port {
73 hdmi_in_con: endpoint 73 hdmi_in_con: endpoint {
74 remote-endpoin 74 remote-endpoint = <&adv7482_hdmi>;
75 }; 75 };
76 }; 76 };
77 }; 77 };
78 78
79 hdmi-out { 79 hdmi-out {
80 compatible = "hdmi-connector"; 80 compatible = "hdmi-connector";
81 type = "a"; 81 type = "a";
82 82
83 port { 83 port {
84 hdmi_con_out: endpoint 84 hdmi_con_out: endpoint {
85 remote-endpoin 85 remote-endpoint = <&adv7511_out>;
86 }; 86 };
87 }; 87 };
88 }; 88 };
89 89
90 keys { 90 keys {
91 compatible = "gpio-keys"; 91 compatible = "gpio-keys";
92 92
93 pinctrl-0 = <&keys_pins>; 93 pinctrl-0 = <&keys_pins>;
94 pinctrl-names = "default"; 94 pinctrl-names = "default";
95 95
96 key-1 { 96 key-1 {
97 gpios = <&gpio5 10 GPI 97 gpios = <&gpio5 10 GPIO_ACTIVE_LOW>;
98 linux,code = <KEY_1>; 98 linux,code = <KEY_1>;
99 label = "SW4-1"; 99 label = "SW4-1";
100 wakeup-source; 100 wakeup-source;
101 debounce-interval = <2 101 debounce-interval = <20>;
102 }; 102 };
103 key-2 { 103 key-2 {
104 gpios = <&gpio5 11 GPI 104 gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
105 linux,code = <KEY_2>; 105 linux,code = <KEY_2>;
106 label = "SW4-2"; 106 label = "SW4-2";
107 wakeup-source; 107 wakeup-source;
108 debounce-interval = <2 108 debounce-interval = <20>;
109 }; 109 };
110 key-3 { 110 key-3 {
111 gpios = <&gpio5 12 GPI 111 gpios = <&gpio5 12 GPIO_ACTIVE_LOW>;
112 linux,code = <KEY_3>; 112 linux,code = <KEY_3>;
113 label = "SW4-3"; 113 label = "SW4-3";
114 wakeup-source; 114 wakeup-source;
115 debounce-interval = <2 115 debounce-interval = <20>;
116 }; 116 };
117 key-4 { 117 key-4 {
118 gpios = <&gpio5 13 GPI 118 gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
119 linux,code = <KEY_4>; 119 linux,code = <KEY_4>;
120 label = "SW4-4"; 120 label = "SW4-4";
121 wakeup-source; 121 wakeup-source;
122 debounce-interval = <2 122 debounce-interval = <20>;
123 }; 123 };
124 }; 124 };
125 125
126 lvds-decoder { 126 lvds-decoder {
127 compatible = "thine,thc63lvd10 127 compatible = "thine,thc63lvd1024";
128 vcc-supply = <®_3p3v>; 128 vcc-supply = <®_3p3v>;
129 129
130 ports { 130 ports {
131 #address-cells = <1>; 131 #address-cells = <1>;
132 #size-cells = <0>; 132 #size-cells = <0>;
133 133
134 port@0 { 134 port@0 {
135 reg = <0>; 135 reg = <0>;
136 thc63lvd1024_i 136 thc63lvd1024_in: endpoint {
137 remote 137 remote-endpoint = <&lvds0_out>;
138 }; 138 };
139 }; 139 };
140 140
141 port@2 { 141 port@2 {
142 reg = <2>; 142 reg = <2>;
143 thc63lvd1024_o 143 thc63lvd1024_out: endpoint {
144 remote 144 remote-endpoint = <&adv7511_in>;
145 }; 145 };
146 }; 146 };
147 }; 147 };
148 }; 148 };
149 149
150 memory@48000000 { 150 memory@48000000 {
151 device_type = "memory"; 151 device_type = "memory";
152 /* first 128MB is reserved for 152 /* first 128MB is reserved for secure area. */
153 reg = <0x0 0x48000000 0x0 0x38 153 reg = <0x0 0x48000000 0x0 0x38000000>;
154 }; 154 };
155 155
156 reg_1p8v: regulator-1p8v { 156 reg_1p8v: regulator-1p8v {
157 compatible = "regulator-fixed" 157 compatible = "regulator-fixed";
158 regulator-name = "fixed-1.8V"; 158 regulator-name = "fixed-1.8V";
159 regulator-min-microvolt = <180 159 regulator-min-microvolt = <1800000>;
160 regulator-max-microvolt = <180 160 regulator-max-microvolt = <1800000>;
161 regulator-boot-on; 161 regulator-boot-on;
162 regulator-always-on; 162 regulator-always-on;
163 }; 163 };
164 164
165 reg_3p3v: regulator-3p3v { 165 reg_3p3v: regulator-3p3v {
166 compatible = "regulator-fixed" 166 compatible = "regulator-fixed";
167 regulator-name = "fixed-3.3V"; 167 regulator-name = "fixed-3.3V";
168 regulator-min-microvolt = <330 168 regulator-min-microvolt = <3300000>;
169 regulator-max-microvolt = <330 169 regulator-max-microvolt = <3300000>;
170 regulator-boot-on; 170 regulator-boot-on;
171 regulator-always-on; 171 regulator-always-on;
172 }; 172 };
173 173
174 reg_12p0v: regulator-12p0v { 174 reg_12p0v: regulator-12p0v {
175 compatible = "regulator-fixed" 175 compatible = "regulator-fixed";
176 regulator-name = "D12.0V"; 176 regulator-name = "D12.0V";
177 regulator-min-microvolt = <120 177 regulator-min-microvolt = <12000000>;
178 regulator-max-microvolt = <120 178 regulator-max-microvolt = <12000000>;
179 regulator-boot-on; 179 regulator-boot-on;
180 regulator-always-on; 180 regulator-always-on;
181 }; 181 };
182 182
183 rsnd_ak4613: sound { 183 rsnd_ak4613: sound {
184 compatible = "simple-audio-car 184 compatible = "simple-audio-card";
185 185
186 simple-audio-card,name = "rsnd 186 simple-audio-card,name = "rsnd-ak4613";
187 simple-audio-card,format = "le 187 simple-audio-card,format = "left_j";
188 simple-audio-card,bitclock-mas 188 simple-audio-card,bitclock-master = <&sndcpu>;
189 simple-audio-card,frame-master 189 simple-audio-card,frame-master = <&sndcpu>;
190 190
191 sndcodec: simple-audio-card,co 191 sndcodec: simple-audio-card,codec {
192 sound-dai = <&ak4613>; 192 sound-dai = <&ak4613>;
193 }; 193 };
194 194
195 sndcpu: simple-audio-card,cpu 195 sndcpu: simple-audio-card,cpu {
196 sound-dai = <&rcar_sou 196 sound-dai = <&rcar_sound>;
197 }; 197 };
198 }; 198 };
199 199
200 vbus0_usb2: regulator-vbus0-usb2 { 200 vbus0_usb2: regulator-vbus0-usb2 {
201 compatible = "regulator-fixed" 201 compatible = "regulator-fixed";
202 202
203 regulator-name = "USB20_VBUS_C 203 regulator-name = "USB20_VBUS_CN";
204 regulator-min-microvolt = <500 204 regulator-min-microvolt = <5000000>;
205 regulator-max-microvolt = <500 205 regulator-max-microvolt = <5000000>;
206 206
207 gpio = <&gpio6 4 GPIO_ACTIVE_H 207 gpio = <&gpio6 4 GPIO_ACTIVE_HIGH>;
208 enable-active-high; 208 enable-active-high;
209 }; 209 };
210 210
211 vcc_sdhi0: regulator-vcc-sdhi0 { 211 vcc_sdhi0: regulator-vcc-sdhi0 {
212 compatible = "regulator-fixed" 212 compatible = "regulator-fixed";
213 213
214 regulator-name = "SDHI0 Vcc"; 214 regulator-name = "SDHI0 Vcc";
215 regulator-min-microvolt = <330 215 regulator-min-microvolt = <3300000>;
216 regulator-max-microvolt = <330 216 regulator-max-microvolt = <3300000>;
217 217
218 gpio = <&gpio5 17 GPIO_ACTIVE_ 218 gpio = <&gpio5 17 GPIO_ACTIVE_HIGH>;
219 enable-active-high; 219 enable-active-high;
220 }; 220 };
221 221
222 vccq_sdhi0: regulator-vccq-sdhi0 { 222 vccq_sdhi0: regulator-vccq-sdhi0 {
223 compatible = "regulator-gpio"; 223 compatible = "regulator-gpio";
224 224
225 regulator-name = "SDHI0 VccQ"; 225 regulator-name = "SDHI0 VccQ";
226 regulator-min-microvolt = <180 226 regulator-min-microvolt = <1800000>;
227 regulator-max-microvolt = <330 227 regulator-max-microvolt = <3300000>;
228 228
229 gpios = <&gpio5 18 GPIO_ACTIVE 229 gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
230 gpios-states = <1>; 230 gpios-states = <1>;
231 states = <3300000 1>, <1800000 231 states = <3300000 1>, <1800000 0>;
232 }; 232 };
233 233
234 vcc_sdhi1: regulator-vcc-sdhi1 { 234 vcc_sdhi1: regulator-vcc-sdhi1 {
235 compatible = "regulator-fixed" 235 compatible = "regulator-fixed";
236 236
237 regulator-name = "SDHI1 Vcc"; 237 regulator-name = "SDHI1 Vcc";
238 regulator-min-microvolt = <330 238 regulator-min-microvolt = <3300000>;
239 regulator-max-microvolt = <330 239 regulator-max-microvolt = <3300000>;
240 240
241 gpio = <&gpio0 4 GPIO_ACTIVE_H 241 gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>;
242 enable-active-high; 242 enable-active-high;
243 }; 243 };
244 244
245 vccq_sdhi1: regulator-vccq-sdhi1 { 245 vccq_sdhi1: regulator-vccq-sdhi1 {
246 compatible = "regulator-gpio"; 246 compatible = "regulator-gpio";
247 247
248 regulator-name = "SDHI1 VccQ"; 248 regulator-name = "SDHI1 VccQ";
249 regulator-min-microvolt = <180 249 regulator-min-microvolt = <1800000>;
250 regulator-max-microvolt = <330 250 regulator-max-microvolt = <3300000>;
251 251
252 gpios = <&gpio3 15 GPIO_ACTIVE 252 gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
253 gpios-states = <1>; 253 gpios-states = <1>;
254 states = <3300000 1>, <1800000 254 states = <3300000 1>, <1800000 0>;
255 }; 255 };
256 256
257 vga { 257 vga {
258 compatible = "vga-connector"; 258 compatible = "vga-connector";
259 259
260 port { 260 port {
261 vga_in: endpoint { 261 vga_in: endpoint {
262 remote-endpoin 262 remote-endpoint = <&adv7123_out>;
263 }; 263 };
264 }; 264 };
265 }; 265 };
266 266
267 vga-encoder { 267 vga-encoder {
268 compatible = "adi,adv7123"; 268 compatible = "adi,adv7123";
269 269
270 ports { 270 ports {
271 #address-cells = <1>; 271 #address-cells = <1>;
272 #size-cells = <0>; 272 #size-cells = <0>;
273 273
274 port@0 { 274 port@0 {
275 reg = <0>; 275 reg = <0>;
276 adv7123_in: en 276 adv7123_in: endpoint {
277 remote 277 remote-endpoint = <&du_out_rgb>;
278 }; 278 };
279 }; 279 };
280 port@1 { 280 port@1 {
281 reg = <1>; 281 reg = <1>;
282 adv7123_out: e 282 adv7123_out: endpoint {
283 remote 283 remote-endpoint = <&vga_in>;
284 }; 284 };
285 }; 285 };
286 }; 286 };
287 }; 287 };
288 288
289 x12_clk: x12 { 289 x12_clk: x12 {
290 compatible = "fixed-clock"; 290 compatible = "fixed-clock";
291 #clock-cells = <0>; 291 #clock-cells = <0>;
292 clock-frequency = <24576000>; 292 clock-frequency = <24576000>;
293 }; 293 };
294 294
295 x13_clk: x13 { 295 x13_clk: x13 {
296 compatible = "fixed-clock"; 296 compatible = "fixed-clock";
297 #clock-cells = <0>; 297 #clock-cells = <0>;
298 clock-frequency = <74250000>; 298 clock-frequency = <74250000>;
299 }; 299 };
300 }; 300 };
301 301
302 &audio_clk_a { 302 &audio_clk_a {
303 clock-frequency = <22579200>; 303 clock-frequency = <22579200>;
304 }; 304 };
305 305
306 &avb { 306 &avb {
307 pinctrl-0 = <&avb_pins>; 307 pinctrl-0 = <&avb_pins>;
308 pinctrl-names = "default"; 308 pinctrl-names = "default";
309 phy-handle = <&phy0>; 309 phy-handle = <&phy0>;
310 status = "okay"; 310 status = "okay";
311 311
312 phy0: ethernet-phy@0 { 312 phy0: ethernet-phy@0 {
313 compatible = "ethernet-phy-id0 313 compatible = "ethernet-phy-id0022.1622",
314 "ethernet-phy-iee 314 "ethernet-phy-ieee802.3-c22";
315 rxc-skew-ps = <1500>; 315 rxc-skew-ps = <1500>;
316 reg = <0>; 316 reg = <0>;
317 interrupt-parent = <&gpio2>; 317 interrupt-parent = <&gpio2>;
318 interrupts = <21 IRQ_TYPE_LEVE 318 interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
319 reset-gpios = <&gpio1 20 GPIO_ 319 reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
320 /* 320 /*
321 * TX clock internal delay mod 321 * TX clock internal delay mode is required for reliable
322 * 1Gbps communication using t 322 * 1Gbps communication using the KSZ9031RNX phy present on
323 * the Ebisu board, however, T 323 * the Ebisu board, however, TX clock internal delay mode
324 * isn't supported on R-Car E3 324 * isn't supported on R-Car E3(e). Thus, limit speed to
325 * 100Mbps for reliable commun 325 * 100Mbps for reliable communication.
326 */ 326 */
327 max-speed = <100>; 327 max-speed = <100>;
328 }; 328 };
329 }; 329 };
330 330
331 &canfd { 331 &canfd {
332 pinctrl-0 = <&canfd0_pins>; 332 pinctrl-0 = <&canfd0_pins>;
333 pinctrl-names = "default"; 333 pinctrl-names = "default";
334 status = "okay"; 334 status = "okay";
335 335
336 channel0 { 336 channel0 {
337 status = "okay"; 337 status = "okay";
338 }; 338 };
339 }; 339 };
340 340
341 &csi40 { 341 &csi40 {
342 status = "okay"; 342 status = "okay";
343 343
344 ports { 344 ports {
345 port@0 { 345 port@0 {
346 csi40_in: endpoint { 346 csi40_in: endpoint {
347 clock-lanes = 347 clock-lanes = <0>;
348 data-lanes = < 348 data-lanes = <1 2>;
349 remote-endpoin 349 remote-endpoint = <&adv7482_txa>;
350 }; 350 };
351 }; 351 };
352 }; 352 };
353 }; 353 };
354 354
355 &du { 355 &du {
356 pinctrl-0 = <&du_pins>; 356 pinctrl-0 = <&du_pins>;
357 pinctrl-names = "default"; 357 pinctrl-names = "default";
358 status = "okay"; 358 status = "okay";
359 359
360 clocks = <&cpg CPG_MOD 724>, 360 clocks = <&cpg CPG_MOD 724>,
361 <&cpg CPG_MOD 723>, 361 <&cpg CPG_MOD 723>,
362 <&x13_clk>; 362 <&x13_clk>;
363 clock-names = "du.0", "du.1", "dclkin. 363 clock-names = "du.0", "du.1", "dclkin.0";
364 364
365 ports { 365 ports {
366 port@0 { 366 port@0 {
367 du_out_rgb: endpoint { 367 du_out_rgb: endpoint {
368 remote-endpoin 368 remote-endpoint = <&adv7123_in>;
369 }; 369 };
370 }; 370 };
371 }; 371 };
372 }; 372 };
373 373
374 &ehci0 { 374 &ehci0 {
375 dr_mode = "otg"; 375 dr_mode = "otg";
376 status = "okay"; 376 status = "okay";
377 }; 377 };
378 378
379 &extal_clk { 379 &extal_clk {
380 clock-frequency = <48000000>; 380 clock-frequency = <48000000>;
381 }; 381 };
382 382
383 &hsusb { 383 &hsusb {
384 dr_mode = "otg"; 384 dr_mode = "otg";
385 status = "okay"; 385 status = "okay";
386 }; 386 };
387 387
388 &i2c0 { 388 &i2c0 {
389 status = "okay"; 389 status = "okay";
390 390
391 io_expander: gpio@20 { 391 io_expander: gpio@20 {
392 compatible = "onnn,pca9654"; 392 compatible = "onnn,pca9654";
393 reg = <0x20>; 393 reg = <0x20>;
394 gpio-controller; 394 gpio-controller;
395 #gpio-cells = <2>; 395 #gpio-cells = <2>;
396 interrupt-parent = <&gpio2>; 396 interrupt-parent = <&gpio2>;
397 interrupts = <22 IRQ_TYPE_LEVE 397 interrupts = <22 IRQ_TYPE_LEVEL_LOW>;
398 }; 398 };
399 399
400 hdmi-encoder@39 { 400 hdmi-encoder@39 {
401 compatible = "adi,adv7511w"; 401 compatible = "adi,adv7511w";
402 reg = <0x39>; 402 reg = <0x39>;
403 interrupt-parent = <&gpio1>; 403 interrupt-parent = <&gpio1>;
404 interrupts = <1 IRQ_TYPE_LEVEL 404 interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
405 <<
406 avdd-supply = <®_1p8v>; <<
407 dvdd-supply = <®_1p8v>; <<
408 pvdd-supply = <®_1p8v>; <<
409 dvdd-3v-supply = <®_3p3v>; <<
410 bgvdd-supply = <®_1p8v>; <<
411 405
412 adi,input-depth = <8>; 406 adi,input-depth = <8>;
413 adi,input-colorspace = "rgb"; 407 adi,input-colorspace = "rgb";
414 adi,input-clock = "1x"; 408 adi,input-clock = "1x";
415 409
416 ports { 410 ports {
417 #address-cells = <1>; 411 #address-cells = <1>;
418 #size-cells = <0>; 412 #size-cells = <0>;
419 413
420 port@0 { 414 port@0 {
421 reg = <0>; 415 reg = <0>;
422 adv7511_in: en 416 adv7511_in: endpoint {
423 remote 417 remote-endpoint = <&thc63lvd1024_out>;
424 }; 418 };
425 }; 419 };
426 420
427 port@1 { 421 port@1 {
428 reg = <1>; 422 reg = <1>;
429 adv7511_out: e 423 adv7511_out: endpoint {
430 remote 424 remote-endpoint = <&hdmi_con_out>;
431 }; 425 };
432 }; 426 };
433 }; 427 };
434 }; 428 };
435 429
436 video-receiver@70 { 430 video-receiver@70 {
437 compatible = "adi,adv7482"; 431 compatible = "adi,adv7482";
438 reg = <0x70>; 432 reg = <0x70>;
439 433
440 interrupt-parent = <&gpio0>; 434 interrupt-parent = <&gpio0>;
441 interrupt-names = "intrq1", "i 435 interrupt-names = "intrq1", "intrq2";
442 interrupts = <7 IRQ_TYPE_LEVEL 436 interrupts = <7 IRQ_TYPE_LEVEL_LOW>,
443 <17 IRQ_TYPE_LEVE 437 <17 IRQ_TYPE_LEVEL_LOW>;
444 438
445 ports { 439 ports {
446 #address-cells = <1>; 440 #address-cells = <1>;
447 #size-cells = <0>; 441 #size-cells = <0>;
448 442
449 port@7 { 443 port@7 {
450 reg = <7>; 444 reg = <7>;
451 445
452 adv7482_ain7: 446 adv7482_ain7: endpoint {
453 remote 447 remote-endpoint = <&cvbs_con>;
454 }; 448 };
455 }; 449 };
456 450
457 port@8 { 451 port@8 {
458 reg = <8>; 452 reg = <8>;
459 453
460 adv7482_hdmi: 454 adv7482_hdmi: endpoint {
461 remote 455 remote-endpoint = <&hdmi_in_con>;
462 }; 456 };
463 }; 457 };
464 458
465 port@a { 459 port@a {
466 reg = <10>; 460 reg = <10>;
467 461
468 adv7482_txa: e 462 adv7482_txa: endpoint {
469 clock- 463 clock-lanes = <0>;
470 data-l 464 data-lanes = <1 2>;
471 remote 465 remote-endpoint = <&csi40_in>;
472 }; 466 };
473 }; 467 };
474 }; 468 };
475 }; 469 };
476 }; 470 };
477 471
478 &i2c3 { 472 &i2c3 {
479 status = "okay"; 473 status = "okay";
480 474
481 ak4613: codec@10 { 475 ak4613: codec@10 {
482 compatible = "asahi-kasei,ak46 476 compatible = "asahi-kasei,ak4613";
483 #sound-dai-cells = <0>; 477 #sound-dai-cells = <0>;
484 reg = <0x10>; 478 reg = <0x10>;
485 clocks = <&rcar_sound 3>; 479 clocks = <&rcar_sound 3>;
486 480
487 asahi-kasei,in1-single-end; 481 asahi-kasei,in1-single-end;
488 asahi-kasei,in2-single-end; 482 asahi-kasei,in2-single-end;
489 asahi-kasei,out1-single-end; 483 asahi-kasei,out1-single-end;
490 asahi-kasei,out2-single-end; 484 asahi-kasei,out2-single-end;
491 asahi-kasei,out3-single-end; 485 asahi-kasei,out3-single-end;
492 asahi-kasei,out4-single-end; 486 asahi-kasei,out4-single-end;
493 asahi-kasei,out5-single-end; 487 asahi-kasei,out5-single-end;
494 asahi-kasei,out6-single-end; 488 asahi-kasei,out6-single-end;
495 }; 489 };
496 490
497 cs2000: clk-multiplier@4f { 491 cs2000: clk-multiplier@4f {
498 #clock-cells = <0>; 492 #clock-cells = <0>;
499 compatible = "cirrus,cs2000-cp 493 compatible = "cirrus,cs2000-cp";
500 reg = <0x4f>; 494 reg = <0x4f>;
501 clocks = <&audio_clkout>, <&x1 495 clocks = <&audio_clkout>, <&x12_clk>;
502 clock-names = "clk_in", "ref_c 496 clock-names = "clk_in", "ref_clk";
503 497
504 assigned-clocks = <&cs2000>; 498 assigned-clocks = <&cs2000>;
505 assigned-clock-rates = <245760 499 assigned-clock-rates = <24576000>; /* 1/1 divide */
506 }; 500 };
507 }; 501 };
508 502
509 &i2c_dvfs { 503 &i2c_dvfs {
510 status = "okay"; 504 status = "okay";
511 505
512 clock-frequency = <400000>; 506 clock-frequency = <400000>;
513 507
514 pmic: pmic@30 { 508 pmic: pmic@30 {
515 pinctrl-0 = <&irq0_pins>; 509 pinctrl-0 = <&irq0_pins>;
516 pinctrl-names = "default"; 510 pinctrl-names = "default";
517 511
518 compatible = "rohm,bd9571mwv"; 512 compatible = "rohm,bd9571mwv";
519 reg = <0x30>; 513 reg = <0x30>;
520 interrupt-parent = <&intc_ex>; 514 interrupt-parent = <&intc_ex>;
521 interrupts = <0 IRQ_TYPE_LEVEL 515 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
522 interrupt-controller; 516 interrupt-controller;
523 #interrupt-cells = <2>; 517 #interrupt-cells = <2>;
524 gpio-controller; 518 gpio-controller;
525 #gpio-cells = <2>; 519 #gpio-cells = <2>;
526 rohm,ddr-backup-power = <0x1>; 520 rohm,ddr-backup-power = <0x1>;
527 rohm,rstbmode-level; 521 rohm,rstbmode-level;
528 }; 522 };
529 523
530 eeprom@50 { 524 eeprom@50 {
531 compatible = "rohm,br24t01", " 525 compatible = "rohm,br24t01", "atmel,24c01";
532 reg = <0x50>; 526 reg = <0x50>;
533 pagesize = <8>; 527 pagesize = <8>;
534 }; 528 };
535 }; 529 };
536 530
537 &lvds0 { 531 &lvds0 {
538 status = "okay"; 532 status = "okay";
539 533
540 clocks = <&cpg CPG_MOD 727>, 534 clocks = <&cpg CPG_MOD 727>,
541 <&x13_clk>, 535 <&x13_clk>,
542 <&extal_clk>; 536 <&extal_clk>;
543 clock-names = "fck", "dclkin.0", "exta 537 clock-names = "fck", "dclkin.0", "extal";
544 538
545 ports { 539 ports {
546 port@1 { 540 port@1 {
547 lvds0_out: endpoint { 541 lvds0_out: endpoint {
548 remote-endpoin 542 remote-endpoint = <&thc63lvd1024_in>;
549 }; 543 };
550 }; 544 };
551 }; 545 };
552 }; 546 };
553 547
554 &lvds1 { 548 &lvds1 {
555 /* 549 /*
556 * Even though the LVDS1 output is not 550 * Even though the LVDS1 output is not connected, the encoder must be
557 * enabled to supply a pixel clock to 551 * enabled to supply a pixel clock to the DU for the DPAD output when
558 * LVDS0 is in use. 552 * LVDS0 is in use.
559 */ 553 */
560 status = "okay"; 554 status = "okay";
561 555
562 clocks = <&cpg CPG_MOD 727>, 556 clocks = <&cpg CPG_MOD 727>,
563 <&x13_clk>, 557 <&x13_clk>,
564 <&extal_clk>; 558 <&extal_clk>;
565 clock-names = "fck", "dclkin.0", "exta 559 clock-names = "fck", "dclkin.0", "extal";
566 }; 560 };
567 561
568 &ohci0 { 562 &ohci0 {
569 dr_mode = "otg"; 563 dr_mode = "otg";
570 status = "okay"; 564 status = "okay";
571 }; 565 };
572 566
573 &pcie_bus_clk { 567 &pcie_bus_clk {
574 clock-frequency = <100000000>; 568 clock-frequency = <100000000>;
575 }; 569 };
576 570
577 &pciec0 { 571 &pciec0 {
578 status = "okay"; 572 status = "okay";
579 }; 573 };
580 574
581 &pfc { 575 &pfc {
582 avb_pins: avb { 576 avb_pins: avb {
583 groups = "avb_link", "avb_mii" 577 groups = "avb_link", "avb_mii";
584 function = "avb"; 578 function = "avb";
585 }; 579 };
586 580
587 canfd0_pins: canfd0 { 581 canfd0_pins: canfd0 {
588 groups = "canfd0_data"; 582 groups = "canfd0_data";
589 function = "canfd0"; 583 function = "canfd0";
590 }; 584 };
591 585
592 du_pins: du { 586 du_pins: du {
593 groups = "du_rgb888", "du_sync 587 groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
594 function = "du"; 588 function = "du";
595 }; 589 };
596 590
597 irq0_pins: irq0 { 591 irq0_pins: irq0 {
598 groups = "intc_ex_irq0"; 592 groups = "intc_ex_irq0";
599 function = "intc_ex"; 593 function = "intc_ex";
600 }; 594 };
601 595
602 keys_pins: keys { 596 keys_pins: keys {
603 pins = "GP_5_10", "GP_5_11", " 597 pins = "GP_5_10", "GP_5_11", "GP_5_12", "GP_5_13";
604 bias-pull-up; 598 bias-pull-up;
605 }; 599 };
606 600
607 pwm3_pins: pwm3 { 601 pwm3_pins: pwm3 {
608 groups = "pwm3_b"; 602 groups = "pwm3_b";
609 function = "pwm3"; 603 function = "pwm3";
610 }; 604 };
611 605
612 pwm5_pins: pwm5 { 606 pwm5_pins: pwm5 {
613 groups = "pwm5_a"; 607 groups = "pwm5_a";
614 function = "pwm5"; 608 function = "pwm5";
615 }; 609 };
616 610
617 rpc_pins: rpc { 611 rpc_pins: rpc {
618 groups = "rpc_clk2", "rpc_ctrl 612 groups = "rpc_clk2", "rpc_ctrl", "rpc_data", "rpc_reset",
619 "rpc_int"; 613 "rpc_int";
620 function = "rpc"; 614 function = "rpc";
621 }; 615 };
622 616
623 scif2_pins: scif2 { 617 scif2_pins: scif2 {
624 groups = "scif2_data_a"; 618 groups = "scif2_data_a";
625 function = "scif2"; 619 function = "scif2";
626 }; 620 };
627 621
628 sdhi0_pins: sd0 { 622 sdhi0_pins: sd0 {
629 groups = "sdhi0_data4", "sdhi0 623 groups = "sdhi0_data4", "sdhi0_ctrl";
630 function = "sdhi0"; 624 function = "sdhi0";
631 power-source = <3300>; 625 power-source = <3300>;
632 }; 626 };
633 627
634 sdhi0_pins_uhs: sd0_uhs { 628 sdhi0_pins_uhs: sd0_uhs {
635 groups = "sdhi0_data4", "sdhi0 629 groups = "sdhi0_data4", "sdhi0_ctrl";
636 function = "sdhi0"; 630 function = "sdhi0";
637 power-source = <1800>; 631 power-source = <1800>;
638 }; 632 };
639 633
640 sdhi1_pins: sd1 { 634 sdhi1_pins: sd1 {
641 groups = "sdhi1_data4", "sdhi1 635 groups = "sdhi1_data4", "sdhi1_ctrl";
642 function = "sdhi1"; 636 function = "sdhi1";
643 power-source = <3300>; 637 power-source = <3300>;
644 }; 638 };
645 639
646 sdhi1_pins_uhs: sd1_uhs { 640 sdhi1_pins_uhs: sd1_uhs {
647 groups = "sdhi1_data4", "sdhi1 641 groups = "sdhi1_data4", "sdhi1_ctrl";
648 function = "sdhi1"; 642 function = "sdhi1";
649 power-source = <1800>; 643 power-source = <1800>;
650 }; 644 };
651 645
652 sdhi3_pins: sd3 { 646 sdhi3_pins: sd3 {
653 groups = "sdhi3_data8", "sdhi3 647 groups = "sdhi3_data8", "sdhi3_ctrl", "sdhi3_ds";
654 function = "sdhi3"; 648 function = "sdhi3";
655 power-source = <1800>; 649 power-source = <1800>;
656 }; 650 };
657 651
658 sound_clk_pins: sound_clk { 652 sound_clk_pins: sound_clk {
659 groups = "audio_clk_a", "audio 653 groups = "audio_clk_a", "audio_clk_b_a", "audio_clk_c_a",
660 "audio_clkout_a", "au 654 "audio_clkout_a", "audio_clkout1_a";
661 function = "audio_clk"; 655 function = "audio_clk";
662 }; 656 };
663 657
664 sound_pins: sound { 658 sound_pins: sound {
665 groups = "ssi01239_ctrl", "ssi 659 groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data";
666 function = "ssi"; 660 function = "ssi";
667 }; 661 };
668 662
669 usb0_pins: usb { 663 usb0_pins: usb {
670 groups = "usb0_b", "usb0_id"; 664 groups = "usb0_b", "usb0_id";
671 function = "usb0"; 665 function = "usb0";
672 }; 666 };
673 667
674 usb30_pins: usb30 { 668 usb30_pins: usb30 {
675 groups = "usb30"; 669 groups = "usb30";
676 function = "usb30"; 670 function = "usb30";
677 }; 671 };
678 }; 672 };
679 673
680 &pwm3 { 674 &pwm3 {
681 pinctrl-0 = <&pwm3_pins>; 675 pinctrl-0 = <&pwm3_pins>;
682 pinctrl-names = "default"; 676 pinctrl-names = "default";
683 677
684 status = "okay"; 678 status = "okay";
685 }; 679 };
686 680
687 &pwm5 { 681 &pwm5 {
688 pinctrl-0 = <&pwm5_pins>; 682 pinctrl-0 = <&pwm5_pins>;
689 pinctrl-names = "default"; 683 pinctrl-names = "default";
690 684
691 status = "okay"; 685 status = "okay";
692 }; 686 };
693 687
694 &rcar_sound { 688 &rcar_sound {
695 pinctrl-0 = <&sound_pins>, <&sound_clk 689 pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
696 pinctrl-names = "default"; 690 pinctrl-names = "default";
697 691
698 /* Single DAI */ 692 /* Single DAI */
699 #sound-dai-cells = <0>; 693 #sound-dai-cells = <0>;
700 694
701 /* audio_clkout0/1/2/3 */ 695 /* audio_clkout0/1/2/3 */
702 #clock-cells = <1>; 696 #clock-cells = <1>;
703 clock-frequency = <12288000 11289600>; 697 clock-frequency = <12288000 11289600>;
704 698
705 status = "okay"; 699 status = "okay";
706 700
707 /* update <audio_clk_b> to <cs2000> */ 701 /* update <audio_clk_b> to <cs2000> */
708 clocks = <&cpg CPG_MOD 1005>, 702 clocks = <&cpg CPG_MOD 1005>,
709 <&cpg CPG_MOD 1006>, <&cpg CP 703 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
710 <&cpg CPG_MOD 1008>, <&cpg CP 704 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
711 <&cpg CPG_MOD 1010>, <&cpg CP 705 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
712 <&cpg CPG_MOD 1012>, <&cpg CP 706 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
713 <&cpg CPG_MOD 1014>, <&cpg CP 707 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
714 <&cpg CPG_MOD 1022>, <&cpg CP 708 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
715 <&cpg CPG_MOD 1024>, <&cpg CP 709 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
716 <&cpg CPG_MOD 1026>, <&cpg CP 710 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
717 <&cpg CPG_MOD 1028>, <&cpg CP 711 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
718 <&cpg CPG_MOD 1030>, <&cpg CP 712 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
719 <&cpg CPG_MOD 1020>, <&cpg CP 713 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
720 <&cpg CPG_MOD 1020>, <&cpg CP 714 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
721 <&cpg CPG_MOD 1019>, <&cpg CP 715 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
722 <&audio_clk_a>, <&cs2000>, <& 716 <&audio_clk_a>, <&cs2000>, <&audio_clk_c>,
723 <&cpg CPG_CORE R8A77990_CLK_Z 717 <&cpg CPG_CORE R8A77990_CLK_ZA2>;
724 718
725 rcar_sound,dai { 719 rcar_sound,dai {
726 dai0 { 720 dai0 {
727 playback = <&ssi0>, <& 721 playback = <&ssi0>, <&src0>, <&dvc0>;
728 capture = <&ssi1>, <&s 722 capture = <&ssi1>, <&src1>, <&dvc1>;
729 }; 723 };
730 }; 724 };
731 725
732 }; 726 };
733 727
734 &rpc { 728 &rpc {
735 pinctrl-0 = <&rpc_pins>; 729 pinctrl-0 = <&rpc_pins>;
736 pinctrl-names = "default"; 730 pinctrl-names = "default";
737 731
738 /* Left disabled. To be enabled by fi 732 /* Left disabled. To be enabled by firmware when unlocked. */
739 733
740 flash@0 { 734 flash@0 {
741 compatible = "cypress,hyperfla 735 compatible = "cypress,hyperflash", "cfi-flash";
742 reg = <0>; 736 reg = <0>;
743 737
744 partitions { 738 partitions {
745 compatible = "fixed-pa 739 compatible = "fixed-partitions";
746 #address-cells = <1>; 740 #address-cells = <1>;
747 #size-cells = <1>; 741 #size-cells = <1>;
748 742
749 bootparam@0 { 743 bootparam@0 {
750 reg = <0x00000 744 reg = <0x00000000 0x040000>;
751 read-only; 745 read-only;
752 }; 746 };
753 bl2@40000 { 747 bl2@40000 {
754 reg = <0x00040 748 reg = <0x00040000 0x140000>;
755 read-only; 749 read-only;
756 }; 750 };
757 cert_header_sa6@180000 751 cert_header_sa6@180000 {
758 reg = <0x00180 752 reg = <0x00180000 0x040000>;
759 read-only; 753 read-only;
760 }; 754 };
761 bl31@1c0000 { 755 bl31@1c0000 {
762 reg = <0x001c0 756 reg = <0x001c0000 0x040000>;
763 read-only; 757 read-only;
764 }; 758 };
765 tee@200000 { 759 tee@200000 {
766 reg = <0x00200 760 reg = <0x00200000 0x440000>;
767 read-only; 761 read-only;
768 }; 762 };
769 uboot@640000 { 763 uboot@640000 {
770 reg = <0x00640 764 reg = <0x00640000 0x100000>;
771 read-only; 765 read-only;
772 }; 766 };
773 dtb@740000 { 767 dtb@740000 {
774 reg = <0x00740 768 reg = <0x00740000 0x080000>;
775 }; 769 };
776 kernel@7c0000 { 770 kernel@7c0000 {
777 reg = <0x007c0 771 reg = <0x007c0000 0x1400000>;
778 }; 772 };
779 user@1bc0000 { 773 user@1bc0000 {
780 reg = <0x01bc0 774 reg = <0x01bc0000 0x2440000>;
781 }; 775 };
782 }; 776 };
783 }; 777 };
784 }; 778 };
785 779
786 &rwdt { 780 &rwdt {
787 timeout-sec = <60>; 781 timeout-sec = <60>;
788 status = "okay"; 782 status = "okay";
789 }; 783 };
790 784
791 &scif2 { 785 &scif2 {
792 pinctrl-0 = <&scif2_pins>; 786 pinctrl-0 = <&scif2_pins>;
793 pinctrl-names = "default"; 787 pinctrl-names = "default";
794 788
795 status = "okay"; 789 status = "okay";
796 }; 790 };
797 791
798 &sdhi0 { 792 &sdhi0 {
799 pinctrl-0 = <&sdhi0_pins>; 793 pinctrl-0 = <&sdhi0_pins>;
800 pinctrl-1 = <&sdhi0_pins_uhs>; 794 pinctrl-1 = <&sdhi0_pins_uhs>;
801 pinctrl-names = "default", "state_uhs" 795 pinctrl-names = "default", "state_uhs";
802 796
803 vmmc-supply = <&vcc_sdhi0>; 797 vmmc-supply = <&vcc_sdhi0>;
804 vqmmc-supply = <&vccq_sdhi0>; 798 vqmmc-supply = <&vccq_sdhi0>;
805 cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW> 799 cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
806 wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH 800 wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
807 bus-width = <4>; 801 bus-width = <4>;
808 sd-uhs-sdr50; 802 sd-uhs-sdr50;
809 sd-uhs-sdr104; 803 sd-uhs-sdr104;
810 status = "okay"; 804 status = "okay";
811 }; 805 };
812 806
813 &sdhi1 { 807 &sdhi1 {
814 pinctrl-0 = <&sdhi1_pins>; 808 pinctrl-0 = <&sdhi1_pins>;
815 pinctrl-1 = <&sdhi1_pins_uhs>; 809 pinctrl-1 = <&sdhi1_pins_uhs>;
816 pinctrl-names = "default", "state_uhs" 810 pinctrl-names = "default", "state_uhs";
817 811
818 vmmc-supply = <&vcc_sdhi1>; 812 vmmc-supply = <&vcc_sdhi1>;
819 vqmmc-supply = <&vccq_sdhi1>; 813 vqmmc-supply = <&vccq_sdhi1>;
820 cd-gpios = <&gpio3 14 GPIO_ACTIVE_LOW> 814 cd-gpios = <&gpio3 14 GPIO_ACTIVE_LOW>;
821 bus-width = <4>; 815 bus-width = <4>;
822 sd-uhs-sdr50; 816 sd-uhs-sdr50;
823 sd-uhs-sdr104; 817 sd-uhs-sdr104;
824 status = "okay"; 818 status = "okay";
825 }; 819 };
826 820
827 &sdhi3 { 821 &sdhi3 {
828 /* used for on-board 8bit eMMC */ 822 /* used for on-board 8bit eMMC */
829 pinctrl-0 = <&sdhi3_pins>; 823 pinctrl-0 = <&sdhi3_pins>;
830 pinctrl-1 = <&sdhi3_pins>; 824 pinctrl-1 = <&sdhi3_pins>;
831 pinctrl-names = "default", "state_uhs" 825 pinctrl-names = "default", "state_uhs";
832 826
833 vmmc-supply = <®_3p3v>; 827 vmmc-supply = <®_3p3v>;
834 vqmmc-supply = <®_1p8v>; 828 vqmmc-supply = <®_1p8v>;
835 mmc-hs200-1_8v; 829 mmc-hs200-1_8v;
836 mmc-hs400-1_8v; 830 mmc-hs400-1_8v;
837 bus-width = <8>; 831 bus-width = <8>;
838 no-sd; 832 no-sd;
839 no-sdio; 833 no-sdio;
840 non-removable; 834 non-removable;
841 full-pwr-cycle-in-suspend; 835 full-pwr-cycle-in-suspend;
842 status = "okay"; 836 status = "okay";
843 }; 837 };
844 838
845 &ssi1 { 839 &ssi1 {
846 shared-pin; 840 shared-pin;
847 }; 841 };
848 842
849 &usb2_phy0 { 843 &usb2_phy0 {
850 pinctrl-0 = <&usb0_pins>; 844 pinctrl-0 = <&usb0_pins>;
851 pinctrl-names = "default"; 845 pinctrl-names = "default";
852 846
853 vbus-supply = <&vbus0_usb2>; 847 vbus-supply = <&vbus0_usb2>;
854 status = "okay"; 848 status = "okay";
855 }; 849 };
856 850
857 &usb3_peri0 { 851 &usb3_peri0 {
858 companion = <&xhci0>; 852 companion = <&xhci0>;
859 status = "okay"; 853 status = "okay";
860 }; 854 };
861 855
862 &vin4 { 856 &vin4 {
863 status = "okay"; 857 status = "okay";
864 }; 858 };
865 859
866 &vin5 { 860 &vin5 {
867 status = "okay"; 861 status = "okay";
868 }; 862 };
869 863
870 &xhci0 { 864 &xhci0 {
871 pinctrl-0 = <&usb30_pins>; 865 pinctrl-0 = <&usb30_pins>;
872 pinctrl-names = "default"; 866 pinctrl-names = "default";
873 867
874 status = "okay"; 868 status = "okay";
875 }; 869 };
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