1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * Device Tree Source for the Silicon Linux RZ 3 * Device Tree Source for the Silicon Linux RZ/G2E evaluation kit (EK874),
4 * connected to an Advantech IDK-2121WR 21.5" 4 * connected to an Advantech IDK-2121WR 21.5" LVDS panel
5 * 5 *
6 * Copyright (C) 2019 Renesas Electronics Corp 6 * Copyright (C) 2019 Renesas Electronics Corp.
7 */ 7 */
8 8
9 #include "r8a774c0-ek874.dts" 9 #include "r8a774c0-ek874.dts"
10 10
11 / { 11 / {
12 backlight: backlight { 12 backlight: backlight {
13 compatible = "pwm-backlight"; 13 compatible = "pwm-backlight";
14 pwms = <&pwm5 0 50000>; 14 pwms = <&pwm5 0 50000>;
15 15
16 brightness-levels = <0 4 8 16 16 brightness-levels = <0 4 8 16 32 64 128 255>;
17 default-brightness-level = <6> 17 default-brightness-level = <6>;
18 18
19 power-supply = <®_12p0v>; 19 power-supply = <®_12p0v>;
20 enable-gpios = <&gpio6 12 GPIO 20 enable-gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>;
21 }; 21 };
22 22
23 panel-lvds { 23 panel-lvds {
24 compatible = "advantech,idk-21 24 compatible = "advantech,idk-2121wr", "panel-lvds";
25 25
26 width-mm = <476>; 26 width-mm = <476>;
27 height-mm = <268>; 27 height-mm = <268>;
28 28
29 data-mapping = "vesa-24"; 29 data-mapping = "vesa-24";
30 30
31 panel-timing { 31 panel-timing {
32 clock-frequency = <148 32 clock-frequency = <148500000>;
33 hactive = <1920>; 33 hactive = <1920>;
34 vactive = <1080>; 34 vactive = <1080>;
35 hsync-len = <44>; 35 hsync-len = <44>;
36 hfront-porch = <88>; 36 hfront-porch = <88>;
37 hback-porch = <148>; 37 hback-porch = <148>;
38 vfront-porch = <4>; 38 vfront-porch = <4>;
39 vback-porch = <36>; 39 vback-porch = <36>;
40 vsync-len = <5>; 40 vsync-len = <5>;
41 }; 41 };
42 42
43 ports { 43 ports {
44 #address-cells = <1>; 44 #address-cells = <1>;
45 #size-cells = <0>; 45 #size-cells = <0>;
46 46
47 port@0 { 47 port@0 {
48 reg = <0>; 48 reg = <0>;
49 dual-lvds-odd- 49 dual-lvds-odd-pixels;
50 panel_in0: end 50 panel_in0: endpoint {
51 remote 51 remote-endpoint = <&lvds0_out>;
52 }; 52 };
53 }; 53 };
54 54
55 port@1 { 55 port@1 {
56 reg = <1>; 56 reg = <1>;
57 dual-lvds-even 57 dual-lvds-even-pixels;
58 panel_in1: end 58 panel_in1: endpoint {
59 remote 59 remote-endpoint = <&lvds1_out>;
60 }; 60 };
61 }; 61 };
62 }; 62 };
63 }; 63 };
64 }; 64 };
65 65
66 &gpio0 { 66 &gpio0 {
67 /* 67 /*
68 * When GP0_17 is low LVDS[01] are con 68 * When GP0_17 is low LVDS[01] are connected to the LVDS connector
69 * When GP0_17 is high LVDS[01] are co 69 * When GP0_17 is high LVDS[01] are connected to the LT8918L
70 */ 70 */
71 lvds-connector-en-hog { !! 71 lvds-connector-en-gpio{
72 gpio-hog; 72 gpio-hog;
73 gpios = <17 GPIO_ACTIVE_HIGH>; 73 gpios = <17 GPIO_ACTIVE_HIGH>;
74 output-low; 74 output-low;
75 line-name = "lvds-connector-en 75 line-name = "lvds-connector-en-gpio";
76 }; 76 };
77 }; 77 };
78 78
79 &lvds0 { 79 &lvds0 {
80 ports { 80 ports {
81 port@1 { 81 port@1 {
82 lvds0_out: endpoint { 82 lvds0_out: endpoint {
83 remote-endpoin 83 remote-endpoint = <&panel_in0>;
84 }; 84 };
85 }; 85 };
86 }; 86 };
87 }; 87 };
88 88
89 &lvds1 { 89 &lvds1 {
90 status = "okay"; 90 status = "okay";
91 91
92 clocks = <&cpg CPG_MOD 727>, <&x13_clk 92 clocks = <&cpg CPG_MOD 727>, <&x13_clk>, <&extal_clk>;
93 clock-names = "fck", "dclkin.0", "exta 93 clock-names = "fck", "dclkin.0", "extal";
94 94
95 ports { 95 ports {
96 port@1 { 96 port@1 {
97 lvds1_out: endpoint { 97 lvds1_out: endpoint {
98 remote-endpoin 98 remote-endpoint = <&panel_in1>;
99 }; 99 };
100 }; 100 };
101 }; 101 };
102 }; 102 };
103 103
104 &pfc { 104 &pfc {
105 pwm5_pins: pwm5 { 105 pwm5_pins: pwm5 {
106 groups = "pwm5_a"; 106 groups = "pwm5_a";
107 function = "pwm5"; 107 function = "pwm5";
108 }; 108 };
109 }; 109 };
110 110
111 &pwm5 { 111 &pwm5 {
112 pinctrl-0 = <&pwm5_pins>; 112 pinctrl-0 = <&pwm5_pins>;
113 pinctrl-names = "default"; 113 pinctrl-names = "default";
114 114
115 status = "okay"; 115 status = "okay";
116 }; 116 };
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