1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * Device Tree Source for the RZ/G2E (R8A774C0 3 * Device Tree Source for the RZ/G2E (R8A774C0) SoC
4 * 4 *
5 * Copyright (C) 2018-2019 Renesas Electronics 5 * Copyright (C) 2018-2019 Renesas Electronics Corp.
6 */ 6 */
7 7
8 #include <dt-bindings/clock/r8a774c0-cpg-mssr. 8 #include <dt-bindings/clock/r8a774c0-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm 9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a774c0-sysc.h> 10 #include <dt-bindings/power/r8a774c0-sysc.h>
11 11
12 / { 12 / {
13 compatible = "renesas,r8a774c0"; 13 compatible = "renesas,r8a774c0";
14 #address-cells = <2>; 14 #address-cells = <2>;
15 #size-cells = <2>; 15 #size-cells = <2>;
16 16
17 /* 17 /*
18 * The external audio clocks are confi 18 * The external audio clocks are configured as 0 Hz fixed frequency
19 * clocks by default. 19 * clocks by default.
20 * Boards that provide audio clocks sh 20 * Boards that provide audio clocks should override them.
21 */ 21 */
22 audio_clk_a: audio_clk_a { 22 audio_clk_a: audio_clk_a {
23 compatible = "fixed-clock"; 23 compatible = "fixed-clock";
24 #clock-cells = <0>; 24 #clock-cells = <0>;
25 clock-frequency = <0>; 25 clock-frequency = <0>;
26 }; 26 };
27 27
28 audio_clk_b: audio_clk_b { 28 audio_clk_b: audio_clk_b {
29 compatible = "fixed-clock"; 29 compatible = "fixed-clock";
30 #clock-cells = <0>; 30 #clock-cells = <0>;
31 clock-frequency = <0>; 31 clock-frequency = <0>;
32 }; 32 };
33 33
34 audio_clk_c: audio_clk_c { 34 audio_clk_c: audio_clk_c {
35 compatible = "fixed-clock"; 35 compatible = "fixed-clock";
36 #clock-cells = <0>; 36 #clock-cells = <0>;
37 clock-frequency = <0>; 37 clock-frequency = <0>;
38 }; 38 };
39 39
40 /* External CAN clock - to be overridd 40 /* External CAN clock - to be overridden by boards that provide it */
41 can_clk: can { 41 can_clk: can {
42 compatible = "fixed-clock"; 42 compatible = "fixed-clock";
43 #clock-cells = <0>; 43 #clock-cells = <0>;
44 clock-frequency = <0>; 44 clock-frequency = <0>;
45 }; 45 };
46 46
47 cluster1_opp: opp-table-1 { 47 cluster1_opp: opp-table-1 {
48 compatible = "operating-points 48 compatible = "operating-points-v2";
49 opp-shared; 49 opp-shared;
50 opp-800000000 { 50 opp-800000000 {
51 opp-hz = /bits/ 64 <80 51 opp-hz = /bits/ 64 <800000000>;
52 clock-latency-ns = <30 52 clock-latency-ns = <300000>;
53 }; 53 };
54 opp-1000000000 { 54 opp-1000000000 {
55 opp-hz = /bits/ 64 <10 55 opp-hz = /bits/ 64 <1000000000>;
56 clock-latency-ns = <30 56 clock-latency-ns = <300000>;
57 }; 57 };
58 opp-1200000000 { 58 opp-1200000000 {
59 opp-hz = /bits/ 64 <12 59 opp-hz = /bits/ 64 <1200000000>;
60 clock-latency-ns = <30 60 clock-latency-ns = <300000>;
61 opp-suspend; 61 opp-suspend;
62 }; 62 };
63 }; 63 };
64 64
65 cpus { 65 cpus {
66 #address-cells = <1>; 66 #address-cells = <1>;
67 #size-cells = <0>; 67 #size-cells = <0>;
68 68
69 a53_0: cpu@0 { 69 a53_0: cpu@0 {
70 compatible = "arm,cort 70 compatible = "arm,cortex-a53";
71 reg = <0>; 71 reg = <0>;
72 device_type = "cpu"; 72 device_type = "cpu";
73 #cooling-cells = <2>; 73 #cooling-cells = <2>;
74 power-domains = <&sysc 74 power-domains = <&sysc R8A774C0_PD_CA53_CPU0>;
75 next-level-cache = <&L 75 next-level-cache = <&L2_CA53>;
76 enable-method = "psci" 76 enable-method = "psci";
77 dynamic-power-coeffici 77 dynamic-power-coefficient = <277>;
78 clocks = <&cpg CPG_COR 78 clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>;
79 operating-points-v2 = 79 operating-points-v2 = <&cluster1_opp>;
80 }; 80 };
81 81
82 a53_1: cpu@1 { 82 a53_1: cpu@1 {
83 compatible = "arm,cort 83 compatible = "arm,cortex-a53";
84 reg = <1>; 84 reg = <1>;
85 device_type = "cpu"; 85 device_type = "cpu";
86 power-domains = <&sysc 86 power-domains = <&sysc R8A774C0_PD_CA53_CPU1>;
87 next-level-cache = <&L 87 next-level-cache = <&L2_CA53>;
88 enable-method = "psci" 88 enable-method = "psci";
89 clocks = <&cpg CPG_COR 89 clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>;
90 operating-points-v2 = 90 operating-points-v2 = <&cluster1_opp>;
91 }; 91 };
92 92
93 L2_CA53: cache-controller-0 { 93 L2_CA53: cache-controller-0 {
94 compatible = "cache"; 94 compatible = "cache";
95 power-domains = <&sysc 95 power-domains = <&sysc R8A774C0_PD_CA53_SCU>;
96 cache-unified; 96 cache-unified;
97 cache-level = <2>; 97 cache-level = <2>;
98 }; 98 };
99 }; 99 };
100 100
101 extal_clk: extal { 101 extal_clk: extal {
102 compatible = "fixed-clock"; 102 compatible = "fixed-clock";
103 #clock-cells = <0>; 103 #clock-cells = <0>;
104 /* This value must be overridd 104 /* This value must be overridden by the board */
105 clock-frequency = <0>; 105 clock-frequency = <0>;
106 }; 106 };
107 107
108 /* External PCIe clock - can be overri 108 /* External PCIe clock - can be overridden by the board */
109 pcie_bus_clk: pcie_bus { 109 pcie_bus_clk: pcie_bus {
110 compatible = "fixed-clock"; 110 compatible = "fixed-clock";
111 #clock-cells = <0>; 111 #clock-cells = <0>;
112 clock-frequency = <0>; 112 clock-frequency = <0>;
113 }; 113 };
114 114
115 pmu_a53 { 115 pmu_a53 {
116 compatible = "arm,cortex-a53-p 116 compatible = "arm,cortex-a53-pmu";
117 interrupts-extended = <&gic GI 117 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
118 <&gic GI 118 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
119 interrupt-affinity = <&a53_0>, 119 interrupt-affinity = <&a53_0>, <&a53_1>;
120 }; 120 };
121 121
122 psci { 122 psci {
123 compatible = "arm,psci-1.0", " 123 compatible = "arm,psci-1.0", "arm,psci-0.2";
124 method = "smc"; 124 method = "smc";
125 }; 125 };
126 126
127 /* External SCIF clock - to be overrid 127 /* External SCIF clock - to be overridden by boards that provide it */
128 scif_clk: scif { 128 scif_clk: scif {
129 compatible = "fixed-clock"; 129 compatible = "fixed-clock";
130 #clock-cells = <0>; 130 #clock-cells = <0>;
131 clock-frequency = <0>; 131 clock-frequency = <0>;
132 }; 132 };
133 133
134 soc: soc { 134 soc: soc {
135 compatible = "simple-bus"; 135 compatible = "simple-bus";
136 interrupt-parent = <&gic>; 136 interrupt-parent = <&gic>;
137 #address-cells = <2>; 137 #address-cells = <2>;
138 #size-cells = <2>; 138 #size-cells = <2>;
139 ranges; 139 ranges;
140 140
141 rwdt: watchdog@e6020000 { 141 rwdt: watchdog@e6020000 {
142 compatible = "renesas, 142 compatible = "renesas,r8a774c0-wdt",
143 "renesas, 143 "renesas,rcar-gen3-wdt";
144 reg = <0 0xe6020000 0 144 reg = <0 0xe6020000 0 0x0c>;
145 interrupts = <GIC_SPI 145 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
146 clocks = <&cpg CPG_MOD 146 clocks = <&cpg CPG_MOD 402>;
147 power-domains = <&sysc 147 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
148 resets = <&cpg 402>; 148 resets = <&cpg 402>;
149 status = "disabled"; 149 status = "disabled";
150 }; 150 };
151 151
152 gpio0: gpio@e6050000 { 152 gpio0: gpio@e6050000 {
153 compatible = "renesas, 153 compatible = "renesas,gpio-r8a774c0",
154 "renesas, 154 "renesas,rcar-gen3-gpio";
155 reg = <0 0xe6050000 0 155 reg = <0 0xe6050000 0 0x50>;
156 interrupts = <GIC_SPI 156 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
157 #gpio-cells = <2>; 157 #gpio-cells = <2>;
158 gpio-controller; 158 gpio-controller;
159 gpio-ranges = <&pfc 0 159 gpio-ranges = <&pfc 0 0 18>;
160 #interrupt-cells = <2> 160 #interrupt-cells = <2>;
161 interrupt-controller; 161 interrupt-controller;
162 clocks = <&cpg CPG_MOD 162 clocks = <&cpg CPG_MOD 912>;
163 power-domains = <&sysc 163 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
164 resets = <&cpg 912>; 164 resets = <&cpg 912>;
165 }; 165 };
166 166
167 gpio1: gpio@e6051000 { 167 gpio1: gpio@e6051000 {
168 compatible = "renesas, 168 compatible = "renesas,gpio-r8a774c0",
169 "renesas, 169 "renesas,rcar-gen3-gpio";
170 reg = <0 0xe6051000 0 170 reg = <0 0xe6051000 0 0x50>;
171 interrupts = <GIC_SPI 171 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
172 #gpio-cells = <2>; 172 #gpio-cells = <2>;
173 gpio-controller; 173 gpio-controller;
174 gpio-ranges = <&pfc 0 174 gpio-ranges = <&pfc 0 32 23>;
175 #interrupt-cells = <2> 175 #interrupt-cells = <2>;
176 interrupt-controller; 176 interrupt-controller;
177 clocks = <&cpg CPG_MOD 177 clocks = <&cpg CPG_MOD 911>;
178 power-domains = <&sysc 178 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
179 resets = <&cpg 911>; 179 resets = <&cpg 911>;
180 }; 180 };
181 181
182 gpio2: gpio@e6052000 { 182 gpio2: gpio@e6052000 {
183 compatible = "renesas, 183 compatible = "renesas,gpio-r8a774c0",
184 "renesas, 184 "renesas,rcar-gen3-gpio";
185 reg = <0 0xe6052000 0 185 reg = <0 0xe6052000 0 0x50>;
186 interrupts = <GIC_SPI 186 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
187 #gpio-cells = <2>; 187 #gpio-cells = <2>;
188 gpio-controller; 188 gpio-controller;
189 gpio-ranges = <&pfc 0 189 gpio-ranges = <&pfc 0 64 26>;
190 #interrupt-cells = <2> 190 #interrupt-cells = <2>;
191 interrupt-controller; 191 interrupt-controller;
192 clocks = <&cpg CPG_MOD 192 clocks = <&cpg CPG_MOD 910>;
193 power-domains = <&sysc 193 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
194 resets = <&cpg 910>; 194 resets = <&cpg 910>;
195 }; 195 };
196 196
197 gpio3: gpio@e6053000 { 197 gpio3: gpio@e6053000 {
198 compatible = "renesas, 198 compatible = "renesas,gpio-r8a774c0",
199 "renesas, 199 "renesas,rcar-gen3-gpio";
200 reg = <0 0xe6053000 0 200 reg = <0 0xe6053000 0 0x50>;
201 interrupts = <GIC_SPI 201 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
202 #gpio-cells = <2>; 202 #gpio-cells = <2>;
203 gpio-controller; 203 gpio-controller;
204 gpio-ranges = <&pfc 0 204 gpio-ranges = <&pfc 0 96 16>;
205 #interrupt-cells = <2> 205 #interrupt-cells = <2>;
206 interrupt-controller; 206 interrupt-controller;
207 clocks = <&cpg CPG_MOD 207 clocks = <&cpg CPG_MOD 909>;
208 power-domains = <&sysc 208 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
209 resets = <&cpg 909>; 209 resets = <&cpg 909>;
210 }; 210 };
211 211
212 gpio4: gpio@e6054000 { 212 gpio4: gpio@e6054000 {
213 compatible = "renesas, 213 compatible = "renesas,gpio-r8a774c0",
214 "renesas, 214 "renesas,rcar-gen3-gpio";
215 reg = <0 0xe6054000 0 215 reg = <0 0xe6054000 0 0x50>;
216 interrupts = <GIC_SPI 216 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
217 #gpio-cells = <2>; 217 #gpio-cells = <2>;
218 gpio-controller; 218 gpio-controller;
219 gpio-ranges = <&pfc 0 219 gpio-ranges = <&pfc 0 128 11>;
220 #interrupt-cells = <2> 220 #interrupt-cells = <2>;
221 interrupt-controller; 221 interrupt-controller;
222 clocks = <&cpg CPG_MOD 222 clocks = <&cpg CPG_MOD 908>;
223 power-domains = <&sysc 223 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
224 resets = <&cpg 908>; 224 resets = <&cpg 908>;
225 }; 225 };
226 226
227 gpio5: gpio@e6055000 { 227 gpio5: gpio@e6055000 {
228 compatible = "renesas, 228 compatible = "renesas,gpio-r8a774c0",
229 "renesas, 229 "renesas,rcar-gen3-gpio";
230 reg = <0 0xe6055000 0 230 reg = <0 0xe6055000 0 0x50>;
231 interrupts = <GIC_SPI 231 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
232 #gpio-cells = <2>; 232 #gpio-cells = <2>;
233 gpio-controller; 233 gpio-controller;
234 gpio-ranges = <&pfc 0 234 gpio-ranges = <&pfc 0 160 20>;
235 #interrupt-cells = <2> 235 #interrupt-cells = <2>;
236 interrupt-controller; 236 interrupt-controller;
237 clocks = <&cpg CPG_MOD 237 clocks = <&cpg CPG_MOD 907>;
238 power-domains = <&sysc 238 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
239 resets = <&cpg 907>; 239 resets = <&cpg 907>;
240 }; 240 };
241 241
242 gpio6: gpio@e6055400 { 242 gpio6: gpio@e6055400 {
243 compatible = "renesas, 243 compatible = "renesas,gpio-r8a774c0",
244 "renesas, 244 "renesas,rcar-gen3-gpio";
245 reg = <0 0xe6055400 0 245 reg = <0 0xe6055400 0 0x50>;
246 interrupts = <GIC_SPI 246 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
247 #gpio-cells = <2>; 247 #gpio-cells = <2>;
248 gpio-controller; 248 gpio-controller;
249 gpio-ranges = <&pfc 0 249 gpio-ranges = <&pfc 0 192 18>;
250 #interrupt-cells = <2> 250 #interrupt-cells = <2>;
251 interrupt-controller; 251 interrupt-controller;
252 clocks = <&cpg CPG_MOD 252 clocks = <&cpg CPG_MOD 906>;
253 power-domains = <&sysc 253 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
254 resets = <&cpg 906>; 254 resets = <&cpg 906>;
255 }; 255 };
256 256
257 pfc: pinctrl@e6060000 { 257 pfc: pinctrl@e6060000 {
258 compatible = "renesas, 258 compatible = "renesas,pfc-r8a774c0";
259 reg = <0 0xe6060000 0 259 reg = <0 0xe6060000 0 0x508>;
260 }; 260 };
261 261
262 cmt0: timer@e60f0000 { 262 cmt0: timer@e60f0000 {
263 compatible = "renesas, 263 compatible = "renesas,r8a774c0-cmt0",
264 "renesas, 264 "renesas,rcar-gen3-cmt0";
265 reg = <0 0xe60f0000 0 265 reg = <0 0xe60f0000 0 0x1004>;
266 interrupts = <GIC_SPI 266 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
267 <GIC_SPI 267 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
268 clocks = <&cpg CPG_MOD 268 clocks = <&cpg CPG_MOD 303>;
269 clock-names = "fck"; 269 clock-names = "fck";
270 power-domains = <&sysc 270 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
271 resets = <&cpg 303>; 271 resets = <&cpg 303>;
272 status = "disabled"; 272 status = "disabled";
273 }; 273 };
274 274
275 cmt1: timer@e6130000 { 275 cmt1: timer@e6130000 {
276 compatible = "renesas, 276 compatible = "renesas,r8a774c0-cmt1",
277 "renesas, 277 "renesas,rcar-gen3-cmt1";
278 reg = <0 0xe6130000 0 278 reg = <0 0xe6130000 0 0x1004>;
279 interrupts = <GIC_SPI 279 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
280 <GIC_SPI 280 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
281 <GIC_SPI 281 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
282 <GIC_SPI 282 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
283 <GIC_SPI 283 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
284 <GIC_SPI 284 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
285 <GIC_SPI 285 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
286 <GIC_SPI 286 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
287 clocks = <&cpg CPG_MOD 287 clocks = <&cpg CPG_MOD 302>;
288 clock-names = "fck"; 288 clock-names = "fck";
289 power-domains = <&sysc 289 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
290 resets = <&cpg 302>; 290 resets = <&cpg 302>;
291 status = "disabled"; 291 status = "disabled";
292 }; 292 };
293 293
294 cmt2: timer@e6140000 { 294 cmt2: timer@e6140000 {
295 compatible = "renesas, 295 compatible = "renesas,r8a774c0-cmt1",
296 "renesas, 296 "renesas,rcar-gen3-cmt1";
297 reg = <0 0xe6140000 0 297 reg = <0 0xe6140000 0 0x1004>;
298 interrupts = <GIC_SPI 298 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
299 <GIC_SPI 299 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
300 <GIC_SPI 300 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
301 <GIC_SPI 301 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
302 <GIC_SPI 302 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
303 <GIC_SPI 303 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
304 <GIC_SPI 304 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
305 <GIC_SPI 305 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
306 clocks = <&cpg CPG_MOD 306 clocks = <&cpg CPG_MOD 301>;
307 clock-names = "fck"; 307 clock-names = "fck";
308 power-domains = <&sysc 308 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
309 resets = <&cpg 301>; 309 resets = <&cpg 301>;
310 status = "disabled"; 310 status = "disabled";
311 }; 311 };
312 312
313 cmt3: timer@e6148000 { 313 cmt3: timer@e6148000 {
314 compatible = "renesas, 314 compatible = "renesas,r8a774c0-cmt1",
315 "renesas, 315 "renesas,rcar-gen3-cmt1";
316 reg = <0 0xe6148000 0 316 reg = <0 0xe6148000 0 0x1004>;
317 interrupts = <GIC_SPI 317 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
318 <GIC_SPI 318 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
319 <GIC_SPI 319 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
320 <GIC_SPI 320 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
321 <GIC_SPI 321 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
322 <GIC_SPI 322 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
323 <GIC_SPI 323 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
324 <GIC_SPI 324 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
325 clocks = <&cpg CPG_MOD 325 clocks = <&cpg CPG_MOD 300>;
326 clock-names = "fck"; 326 clock-names = "fck";
327 power-domains = <&sysc 327 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
328 resets = <&cpg 300>; 328 resets = <&cpg 300>;
329 status = "disabled"; 329 status = "disabled";
330 }; 330 };
331 331
332 cpg: clock-controller@e6150000 332 cpg: clock-controller@e6150000 {
333 compatible = "renesas, 333 compatible = "renesas,r8a774c0-cpg-mssr";
334 reg = <0 0xe6150000 0 334 reg = <0 0xe6150000 0 0x1000>;
335 clocks = <&extal_clk>; 335 clocks = <&extal_clk>;
336 clock-names = "extal"; 336 clock-names = "extal";
337 #clock-cells = <2>; 337 #clock-cells = <2>;
338 #power-domain-cells = 338 #power-domain-cells = <0>;
339 #reset-cells = <1>; 339 #reset-cells = <1>;
340 }; 340 };
341 341
342 rst: reset-controller@e6160000 342 rst: reset-controller@e6160000 {
343 compatible = "renesas, 343 compatible = "renesas,r8a774c0-rst";
344 reg = <0 0xe6160000 0 344 reg = <0 0xe6160000 0 0x0200>;
345 }; 345 };
346 346
347 sysc: system-controller@e61800 347 sysc: system-controller@e6180000 {
348 compatible = "renesas, 348 compatible = "renesas,r8a774c0-sysc";
349 reg = <0 0xe6180000 0 349 reg = <0 0xe6180000 0 0x0400>;
350 #power-domain-cells = 350 #power-domain-cells = <1>;
351 }; 351 };
352 352
353 thermal: thermal@e6190000 { 353 thermal: thermal@e6190000 {
354 compatible = "renesas, 354 compatible = "renesas,thermal-r8a774c0";
355 reg = <0 0xe6190000 0 355 reg = <0 0xe6190000 0 0x10>, <0 0xe6190100 0 0x38>;
356 interrupts = <GIC_SPI 356 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
357 <GIC_SPI 357 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
358 <GIC_SPI 358 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
359 clocks = <&cpg CPG_MOD 359 clocks = <&cpg CPG_MOD 522>;
360 power-domains = <&sysc 360 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
361 resets = <&cpg 522>; 361 resets = <&cpg 522>;
362 #thermal-sensor-cells 362 #thermal-sensor-cells = <0>;
363 }; 363 };
364 364
365 intc_ex: interrupt-controller@ 365 intc_ex: interrupt-controller@e61c0000 {
366 compatible = "renesas, 366 compatible = "renesas,intc-ex-r8a774c0", "renesas,irqc";
367 #interrupt-cells = <2> 367 #interrupt-cells = <2>;
368 interrupt-controller; 368 interrupt-controller;
369 reg = <0 0xe61c0000 0 369 reg = <0 0xe61c0000 0 0x200>;
370 interrupts = <GIC_SPI 370 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
371 <GIC_SPI 371 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
372 <GIC_SPI 372 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
373 <GIC_SPI 373 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
374 <GIC_SPI 374 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
375 <GIC_SPI 375 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
376 clocks = <&cpg CPG_MOD 376 clocks = <&cpg CPG_MOD 407>;
377 power-domains = <&sysc 377 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
378 resets = <&cpg 407>; 378 resets = <&cpg 407>;
379 }; 379 };
380 380
381 tmu0: timer@e61e0000 { 381 tmu0: timer@e61e0000 {
382 compatible = "renesas, 382 compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
383 reg = <0 0xe61e0000 0 383 reg = <0 0xe61e0000 0 0x30>;
384 interrupts = <GIC_SPI 384 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
385 <GIC_SPI 385 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
386 <GIC_SPI 386 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
387 interrupt-names = "tun 387 interrupt-names = "tuni0", "tuni1", "tuni2";
388 clocks = <&cpg CPG_MOD 388 clocks = <&cpg CPG_MOD 125>;
389 clock-names = "fck"; 389 clock-names = "fck";
390 power-domains = <&sysc 390 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
391 resets = <&cpg 125>; 391 resets = <&cpg 125>;
392 status = "disabled"; 392 status = "disabled";
393 }; 393 };
394 394
395 tmu1: timer@e6fc0000 { 395 tmu1: timer@e6fc0000 {
396 compatible = "renesas, 396 compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
397 reg = <0 0xe6fc0000 0 397 reg = <0 0xe6fc0000 0 0x30>;
398 interrupts = <GIC_SPI 398 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
399 <GIC_SPI 399 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
400 <GIC_SPI 400 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
401 <GIC_SPI 401 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
402 interrupt-names = "tun 402 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
403 clocks = <&cpg CPG_MOD 403 clocks = <&cpg CPG_MOD 124>;
404 clock-names = "fck"; 404 clock-names = "fck";
405 power-domains = <&sysc 405 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
406 resets = <&cpg 124>; 406 resets = <&cpg 124>;
407 status = "disabled"; 407 status = "disabled";
408 }; 408 };
409 409
410 tmu2: timer@e6fd0000 { 410 tmu2: timer@e6fd0000 {
411 compatible = "renesas, 411 compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
412 reg = <0 0xe6fd0000 0 412 reg = <0 0xe6fd0000 0 0x30>;
413 interrupts = <GIC_SPI 413 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
414 <GIC_SPI 414 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
415 <GIC_SPI 415 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
416 <GIC_SPI 416 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
417 interrupt-names = "tun 417 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
418 clocks = <&cpg CPG_MOD 418 clocks = <&cpg CPG_MOD 123>;
419 clock-names = "fck"; 419 clock-names = "fck";
420 power-domains = <&sysc 420 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
421 resets = <&cpg 123>; 421 resets = <&cpg 123>;
422 status = "disabled"; 422 status = "disabled";
423 }; 423 };
424 424
425 tmu3: timer@e6fe0000 { 425 tmu3: timer@e6fe0000 {
426 compatible = "renesas, 426 compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
427 reg = <0 0xe6fe0000 0 427 reg = <0 0xe6fe0000 0 0x30>;
428 interrupts = <GIC_SPI 428 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
429 <GIC_SPI 429 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
430 <GIC_SPI 430 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
431 interrupt-names = "tun 431 interrupt-names = "tuni0", "tuni1", "tuni2";
432 clocks = <&cpg CPG_MOD 432 clocks = <&cpg CPG_MOD 122>;
433 clock-names = "fck"; 433 clock-names = "fck";
434 power-domains = <&sysc 434 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
435 resets = <&cpg 122>; 435 resets = <&cpg 122>;
436 status = "disabled"; 436 status = "disabled";
437 }; 437 };
438 438
439 tmu4: timer@ffc00000 { 439 tmu4: timer@ffc00000 {
440 compatible = "renesas, 440 compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
441 reg = <0 0xffc00000 0 441 reg = <0 0xffc00000 0 0x30>;
442 interrupts = <GIC_SPI 442 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
443 <GIC_SPI 443 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
444 <GIC_SPI 444 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
445 interrupt-names = "tun 445 interrupt-names = "tuni0", "tuni1", "tuni2";
446 clocks = <&cpg CPG_MOD 446 clocks = <&cpg CPG_MOD 121>;
447 clock-names = "fck"; 447 clock-names = "fck";
448 power-domains = <&sysc 448 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
449 resets = <&cpg 121>; 449 resets = <&cpg 121>;
450 status = "disabled"; 450 status = "disabled";
451 }; 451 };
452 452
453 i2c0: i2c@e6500000 { 453 i2c0: i2c@e6500000 {
454 #address-cells = <1>; 454 #address-cells = <1>;
455 #size-cells = <0>; 455 #size-cells = <0>;
456 compatible = "renesas, 456 compatible = "renesas,i2c-r8a774c0",
457 "renesas, 457 "renesas,rcar-gen3-i2c";
458 reg = <0 0xe6500000 0 458 reg = <0 0xe6500000 0 0x40>;
459 interrupts = <GIC_SPI 459 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
460 clocks = <&cpg CPG_MOD 460 clocks = <&cpg CPG_MOD 931>;
461 power-domains = <&sysc 461 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
462 resets = <&cpg 931>; 462 resets = <&cpg 931>;
463 dmas = <&dmac1 0x91>, 463 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
464 <&dmac2 0x91>, 464 <&dmac2 0x91>, <&dmac2 0x90>;
465 dma-names = "tx", "rx" 465 dma-names = "tx", "rx", "tx", "rx";
466 i2c-scl-internal-delay 466 i2c-scl-internal-delay-ns = <110>;
467 status = "disabled"; 467 status = "disabled";
468 }; 468 };
469 469
470 i2c1: i2c@e6508000 { 470 i2c1: i2c@e6508000 {
471 #address-cells = <1>; 471 #address-cells = <1>;
472 #size-cells = <0>; 472 #size-cells = <0>;
473 compatible = "renesas, 473 compatible = "renesas,i2c-r8a774c0",
474 "renesas, 474 "renesas,rcar-gen3-i2c";
475 reg = <0 0xe6508000 0 475 reg = <0 0xe6508000 0 0x40>;
476 interrupts = <GIC_SPI 476 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
477 clocks = <&cpg CPG_MOD 477 clocks = <&cpg CPG_MOD 930>;
478 power-domains = <&sysc 478 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
479 resets = <&cpg 930>; 479 resets = <&cpg 930>;
480 dmas = <&dmac1 0x93>, 480 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
481 <&dmac2 0x93>, 481 <&dmac2 0x93>, <&dmac2 0x92>;
482 dma-names = "tx", "rx" 482 dma-names = "tx", "rx", "tx", "rx";
483 i2c-scl-internal-delay 483 i2c-scl-internal-delay-ns = <6>;
484 status = "disabled"; 484 status = "disabled";
485 }; 485 };
486 486
487 i2c2: i2c@e6510000 { 487 i2c2: i2c@e6510000 {
488 #address-cells = <1>; 488 #address-cells = <1>;
489 #size-cells = <0>; 489 #size-cells = <0>;
490 compatible = "renesas, 490 compatible = "renesas,i2c-r8a774c0",
491 "renesas, 491 "renesas,rcar-gen3-i2c";
492 reg = <0 0xe6510000 0 492 reg = <0 0xe6510000 0 0x40>;
493 interrupts = <GIC_SPI 493 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
494 clocks = <&cpg CPG_MOD 494 clocks = <&cpg CPG_MOD 929>;
495 power-domains = <&sysc 495 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
496 resets = <&cpg 929>; 496 resets = <&cpg 929>;
497 dmas = <&dmac1 0x95>, 497 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
498 <&dmac2 0x95>, 498 <&dmac2 0x95>, <&dmac2 0x94>;
499 dma-names = "tx", "rx" 499 dma-names = "tx", "rx", "tx", "rx";
500 i2c-scl-internal-delay 500 i2c-scl-internal-delay-ns = <6>;
501 status = "disabled"; 501 status = "disabled";
502 }; 502 };
503 503
504 i2c3: i2c@e66d0000 { 504 i2c3: i2c@e66d0000 {
505 #address-cells = <1>; 505 #address-cells = <1>;
506 #size-cells = <0>; 506 #size-cells = <0>;
507 compatible = "renesas, 507 compatible = "renesas,i2c-r8a774c0",
508 "renesas, 508 "renesas,rcar-gen3-i2c";
509 reg = <0 0xe66d0000 0 509 reg = <0 0xe66d0000 0 0x40>;
510 interrupts = <GIC_SPI 510 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
511 clocks = <&cpg CPG_MOD 511 clocks = <&cpg CPG_MOD 928>;
512 power-domains = <&sysc 512 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
513 resets = <&cpg 928>; 513 resets = <&cpg 928>;
514 dmas = <&dmac0 0x97>, 514 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
515 dma-names = "tx", "rx" 515 dma-names = "tx", "rx";
516 i2c-scl-internal-delay 516 i2c-scl-internal-delay-ns = <110>;
517 status = "disabled"; 517 status = "disabled";
518 }; 518 };
519 519
520 i2c4: i2c@e66d8000 { 520 i2c4: i2c@e66d8000 {
521 #address-cells = <1>; 521 #address-cells = <1>;
522 #size-cells = <0>; 522 #size-cells = <0>;
523 compatible = "renesas, 523 compatible = "renesas,i2c-r8a774c0",
524 "renesas, 524 "renesas,rcar-gen3-i2c";
525 reg = <0 0xe66d8000 0 525 reg = <0 0xe66d8000 0 0x40>;
526 interrupts = <GIC_SPI 526 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
527 clocks = <&cpg CPG_MOD 527 clocks = <&cpg CPG_MOD 927>;
528 power-domains = <&sysc 528 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
529 resets = <&cpg 927>; 529 resets = <&cpg 927>;
530 dmas = <&dmac0 0x99>, 530 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
531 dma-names = "tx", "rx" 531 dma-names = "tx", "rx";
532 i2c-scl-internal-delay 532 i2c-scl-internal-delay-ns = <6>;
533 status = "disabled"; 533 status = "disabled";
534 }; 534 };
535 535
536 i2c5: i2c@e66e0000 { 536 i2c5: i2c@e66e0000 {
537 #address-cells = <1>; 537 #address-cells = <1>;
538 #size-cells = <0>; 538 #size-cells = <0>;
539 compatible = "renesas, 539 compatible = "renesas,i2c-r8a774c0",
540 "renesas, 540 "renesas,rcar-gen3-i2c";
541 reg = <0 0xe66e0000 0 541 reg = <0 0xe66e0000 0 0x40>;
542 interrupts = <GIC_SPI 542 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
543 clocks = <&cpg CPG_MOD 543 clocks = <&cpg CPG_MOD 919>;
544 power-domains = <&sysc 544 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
545 resets = <&cpg 919>; 545 resets = <&cpg 919>;
546 dmas = <&dmac0 0x9b>, 546 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
547 dma-names = "tx", "rx" 547 dma-names = "tx", "rx";
548 i2c-scl-internal-delay 548 i2c-scl-internal-delay-ns = <6>;
549 status = "disabled"; 549 status = "disabled";
550 }; 550 };
551 551
552 i2c6: i2c@e66e8000 { 552 i2c6: i2c@e66e8000 {
553 #address-cells = <1>; 553 #address-cells = <1>;
554 #size-cells = <0>; 554 #size-cells = <0>;
555 compatible = "renesas, 555 compatible = "renesas,i2c-r8a774c0",
556 "renesas, 556 "renesas,rcar-gen3-i2c";
557 reg = <0 0xe66e8000 0 557 reg = <0 0xe66e8000 0 0x40>;
558 interrupts = <GIC_SPI 558 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
559 clocks = <&cpg CPG_MOD 559 clocks = <&cpg CPG_MOD 918>;
560 power-domains = <&sysc 560 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
561 resets = <&cpg 918>; 561 resets = <&cpg 918>;
562 dmas = <&dmac0 0x9d>, 562 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
563 dma-names = "tx", "rx" 563 dma-names = "tx", "rx";
564 i2c-scl-internal-delay 564 i2c-scl-internal-delay-ns = <6>;
565 status = "disabled"; 565 status = "disabled";
566 }; 566 };
567 567
568 i2c7: i2c@e6690000 { 568 i2c7: i2c@e6690000 {
569 #address-cells = <1>; 569 #address-cells = <1>;
570 #size-cells = <0>; 570 #size-cells = <0>;
571 compatible = "renesas, 571 compatible = "renesas,i2c-r8a774c0",
572 "renesas, 572 "renesas,rcar-gen3-i2c";
573 reg = <0 0xe6690000 0 573 reg = <0 0xe6690000 0 0x40>;
574 interrupts = <GIC_SPI 574 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
575 clocks = <&cpg CPG_MOD 575 clocks = <&cpg CPG_MOD 1003>;
576 power-domains = <&sysc 576 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
577 resets = <&cpg 1003>; 577 resets = <&cpg 1003>;
578 i2c-scl-internal-delay 578 i2c-scl-internal-delay-ns = <6>;
579 status = "disabled"; 579 status = "disabled";
580 }; 580 };
581 581
582 iic_pmic: i2c@e60b0000 { 582 iic_pmic: i2c@e60b0000 {
583 #address-cells = <1>; 583 #address-cells = <1>;
584 #size-cells = <0>; 584 #size-cells = <0>;
585 compatible = "renesas, 585 compatible = "renesas,iic-r8a774c0",
586 "renesas, 586 "renesas,rcar-gen3-iic",
587 "renesas, 587 "renesas,rmobile-iic";
588 reg = <0 0xe60b0000 0 588 reg = <0 0xe60b0000 0 0x425>;
589 interrupts = <GIC_SPI 589 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
590 clocks = <&cpg CPG_MOD 590 clocks = <&cpg CPG_MOD 926>;
591 power-domains = <&sysc 591 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
592 resets = <&cpg 926>; 592 resets = <&cpg 926>;
593 dmas = <&dmac0 0x11>, 593 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
594 dma-names = "tx", "rx" 594 dma-names = "tx", "rx";
595 status = "disabled"; 595 status = "disabled";
596 }; 596 };
597 597
598 hscif0: serial@e6540000 { 598 hscif0: serial@e6540000 {
599 compatible = "renesas, 599 compatible = "renesas,hscif-r8a774c0",
600 "renesas, 600 "renesas,rcar-gen3-hscif",
601 "renesas, 601 "renesas,hscif";
602 reg = <0 0xe6540000 0 602 reg = <0 0xe6540000 0 0x60>;
603 interrupts = <GIC_SPI 603 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
604 clocks = <&cpg CPG_MOD 604 clocks = <&cpg CPG_MOD 520>,
605 <&cpg CPG_COR 605 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
606 <&scif_clk>; 606 <&scif_clk>;
607 clock-names = "fck", " 607 clock-names = "fck", "brg_int", "scif_clk";
608 dmas = <&dmac1 0x31>, 608 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
609 <&dmac2 0x31>, 609 <&dmac2 0x31>, <&dmac2 0x30>;
610 dma-names = "tx", "rx" 610 dma-names = "tx", "rx", "tx", "rx";
611 power-domains = <&sysc 611 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
612 resets = <&cpg 520>; 612 resets = <&cpg 520>;
613 status = "disabled"; 613 status = "disabled";
614 }; 614 };
615 615
616 hscif1: serial@e6550000 { 616 hscif1: serial@e6550000 {
617 compatible = "renesas, 617 compatible = "renesas,hscif-r8a774c0",
618 "renesas, 618 "renesas,rcar-gen3-hscif",
619 "renesas, 619 "renesas,hscif";
620 reg = <0 0xe6550000 0 620 reg = <0 0xe6550000 0 0x60>;
621 interrupts = <GIC_SPI 621 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
622 clocks = <&cpg CPG_MOD 622 clocks = <&cpg CPG_MOD 519>,
623 <&cpg CPG_COR 623 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
624 <&scif_clk>; 624 <&scif_clk>;
625 clock-names = "fck", " 625 clock-names = "fck", "brg_int", "scif_clk";
626 dmas = <&dmac1 0x33>, 626 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
627 <&dmac2 0x33>, 627 <&dmac2 0x33>, <&dmac2 0x32>;
628 dma-names = "tx", "rx" 628 dma-names = "tx", "rx", "tx", "rx";
629 power-domains = <&sysc 629 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
630 resets = <&cpg 519>; 630 resets = <&cpg 519>;
631 status = "disabled"; 631 status = "disabled";
632 }; 632 };
633 633
634 hscif2: serial@e6560000 { 634 hscif2: serial@e6560000 {
635 compatible = "renesas, 635 compatible = "renesas,hscif-r8a774c0",
636 "renesas, 636 "renesas,rcar-gen3-hscif",
637 "renesas, 637 "renesas,hscif";
638 reg = <0 0xe6560000 0 638 reg = <0 0xe6560000 0 0x60>;
639 interrupts = <GIC_SPI 639 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
640 clocks = <&cpg CPG_MOD 640 clocks = <&cpg CPG_MOD 518>,
641 <&cpg CPG_COR 641 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
642 <&scif_clk>; 642 <&scif_clk>;
643 clock-names = "fck", " 643 clock-names = "fck", "brg_int", "scif_clk";
644 dmas = <&dmac1 0x35>, 644 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
645 <&dmac2 0x35>, 645 <&dmac2 0x35>, <&dmac2 0x34>;
646 dma-names = "tx", "rx" 646 dma-names = "tx", "rx", "tx", "rx";
647 power-domains = <&sysc 647 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
648 resets = <&cpg 518>; 648 resets = <&cpg 518>;
649 status = "disabled"; 649 status = "disabled";
650 }; 650 };
651 651
652 hscif3: serial@e66a0000 { 652 hscif3: serial@e66a0000 {
653 compatible = "renesas, 653 compatible = "renesas,hscif-r8a774c0",
654 "renesas, 654 "renesas,rcar-gen3-hscif",
655 "renesas, 655 "renesas,hscif";
656 reg = <0 0xe66a0000 0 656 reg = <0 0xe66a0000 0 0x60>;
657 interrupts = <GIC_SPI 657 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
658 clocks = <&cpg CPG_MOD 658 clocks = <&cpg CPG_MOD 517>,
659 <&cpg CPG_COR 659 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
660 <&scif_clk>; 660 <&scif_clk>;
661 clock-names = "fck", " 661 clock-names = "fck", "brg_int", "scif_clk";
662 dmas = <&dmac0 0x37>, 662 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
663 dma-names = "tx", "rx" 663 dma-names = "tx", "rx";
664 power-domains = <&sysc 664 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
665 resets = <&cpg 517>; 665 resets = <&cpg 517>;
666 status = "disabled"; 666 status = "disabled";
667 }; 667 };
668 668
669 hscif4: serial@e66b0000 { 669 hscif4: serial@e66b0000 {
670 compatible = "renesas, 670 compatible = "renesas,hscif-r8a774c0",
671 "renesas, 671 "renesas,rcar-gen3-hscif",
672 "renesas, 672 "renesas,hscif";
673 reg = <0 0xe66b0000 0 673 reg = <0 0xe66b0000 0 0x60>;
674 interrupts = <GIC_SPI 674 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
675 clocks = <&cpg CPG_MOD 675 clocks = <&cpg CPG_MOD 516>,
676 <&cpg CPG_COR 676 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
677 <&scif_clk>; 677 <&scif_clk>;
678 clock-names = "fck", " 678 clock-names = "fck", "brg_int", "scif_clk";
679 dmas = <&dmac0 0x39>, 679 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
680 dma-names = "tx", "rx" 680 dma-names = "tx", "rx";
681 power-domains = <&sysc 681 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
682 resets = <&cpg 516>; 682 resets = <&cpg 516>;
683 status = "disabled"; 683 status = "disabled";
684 }; 684 };
685 685
686 hsusb: usb@e6590000 { 686 hsusb: usb@e6590000 {
687 compatible = "renesas, 687 compatible = "renesas,usbhs-r8a774c0",
688 "renesas, 688 "renesas,rcar-gen3-usbhs";
689 reg = <0 0xe6590000 0 689 reg = <0 0xe6590000 0 0x200>;
690 interrupts = <GIC_SPI 690 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
691 clocks = <&cpg CPG_MOD 691 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
692 dmas = <&usb_dmac0 0>, 692 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
693 <&usb_dmac1 0>, 693 <&usb_dmac1 0>, <&usb_dmac1 1>;
694 dma-names = "ch0", "ch 694 dma-names = "ch0", "ch1", "ch2", "ch3";
695 renesas,buswait = <11> 695 renesas,buswait = <11>;
696 phys = <&usb2_phy0 3>; 696 phys = <&usb2_phy0 3>;
697 phy-names = "usb"; 697 phy-names = "usb";
698 power-domains = <&sysc 698 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
699 resets = <&cpg 704>, < 699 resets = <&cpg 704>, <&cpg 703>;
700 status = "disabled"; 700 status = "disabled";
701 }; 701 };
702 702
703 usb_dmac0: dma-controller@e65a 703 usb_dmac0: dma-controller@e65a0000 {
704 compatible = "renesas, 704 compatible = "renesas,r8a774c0-usb-dmac",
705 "renesas, 705 "renesas,usb-dmac";
706 reg = <0 0xe65a0000 0 706 reg = <0 0xe65a0000 0 0x100>;
707 interrupts = <GIC_SPI 707 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
708 <GIC_SPI 708 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
709 interrupt-names = "ch0 709 interrupt-names = "ch0", "ch1";
710 clocks = <&cpg CPG_MOD 710 clocks = <&cpg CPG_MOD 330>;
711 power-domains = <&sysc 711 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
712 resets = <&cpg 330>; 712 resets = <&cpg 330>;
713 #dma-cells = <1>; 713 #dma-cells = <1>;
714 dma-channels = <2>; 714 dma-channels = <2>;
715 }; 715 };
716 716
717 usb_dmac1: dma-controller@e65b 717 usb_dmac1: dma-controller@e65b0000 {
718 compatible = "renesas, 718 compatible = "renesas,r8a774c0-usb-dmac",
719 "renesas, 719 "renesas,usb-dmac";
720 reg = <0 0xe65b0000 0 720 reg = <0 0xe65b0000 0 0x100>;
721 interrupts = <GIC_SPI 721 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
722 <GIC_SPI 722 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
723 interrupt-names = "ch0 723 interrupt-names = "ch0", "ch1";
724 clocks = <&cpg CPG_MOD 724 clocks = <&cpg CPG_MOD 331>;
725 power-domains = <&sysc 725 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
726 resets = <&cpg 331>; 726 resets = <&cpg 331>;
727 #dma-cells = <1>; 727 #dma-cells = <1>;
728 dma-channels = <2>; 728 dma-channels = <2>;
729 }; 729 };
730 730
731 dmac0: dma-controller@e6700000 731 dmac0: dma-controller@e6700000 {
732 compatible = "renesas, 732 compatible = "renesas,dmac-r8a774c0",
733 "renesas, 733 "renesas,rcar-dmac";
734 reg = <0 0xe6700000 0 734 reg = <0 0xe6700000 0 0x10000>;
735 interrupts = <GIC_SPI 735 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
736 <GIC_SPI 736 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
737 <GIC_SPI 737 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
738 <GIC_SPI 738 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
739 <GIC_SPI 739 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
740 <GIC_SPI 740 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
741 <GIC_SPI 741 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
742 <GIC_SPI 742 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
743 <GIC_SPI 743 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
744 <GIC_SPI 744 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
745 <GIC_SPI 745 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
746 <GIC_SPI 746 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
747 <GIC_SPI 747 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
748 <GIC_SPI 748 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
749 <GIC_SPI 749 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
750 <GIC_SPI 750 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
751 <GIC_SPI 751 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
752 interrupt-names = "err 752 interrupt-names = "error",
753 "ch0", 753 "ch0", "ch1", "ch2", "ch3",
754 "ch4", 754 "ch4", "ch5", "ch6", "ch7",
755 "ch8", 755 "ch8", "ch9", "ch10", "ch11",
756 "ch12" 756 "ch12", "ch13", "ch14", "ch15";
757 clocks = <&cpg CPG_MOD 757 clocks = <&cpg CPG_MOD 219>;
758 clock-names = "fck"; 758 clock-names = "fck";
759 power-domains = <&sysc 759 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
760 resets = <&cpg 219>; 760 resets = <&cpg 219>;
761 #dma-cells = <1>; 761 #dma-cells = <1>;
762 dma-channels = <16>; 762 dma-channels = <16>;
763 iommus = <&ipmmu_ds0 0 763 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
764 <&ipmmu_ds0 2>, 764 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
765 <&ipmmu_ds0 4>, 765 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
766 <&ipmmu_ds0 6>, 766 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
767 <&ipmmu_ds0 8>, 767 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
768 <&ipmmu_ds0 10> 768 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
769 <&ipmmu_ds0 12> 769 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
770 <&ipmmu_ds0 14> 770 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
771 }; 771 };
772 772
773 dmac1: dma-controller@e7300000 773 dmac1: dma-controller@e7300000 {
774 compatible = "renesas, 774 compatible = "renesas,dmac-r8a774c0",
775 "renesas, 775 "renesas,rcar-dmac";
776 reg = <0 0xe7300000 0 776 reg = <0 0xe7300000 0 0x10000>;
777 interrupts = <GIC_SPI 777 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
778 <GIC_SPI 778 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
779 <GIC_SPI 779 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
780 <GIC_SPI 780 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
781 <GIC_SPI 781 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
782 <GIC_SPI 782 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
783 <GIC_SPI 783 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
784 <GIC_SPI 784 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
785 <GIC_SPI 785 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
786 <GIC_SPI 786 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
787 <GIC_SPI 787 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
788 <GIC_SPI 788 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
789 <GIC_SPI 789 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
790 <GIC_SPI 790 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
791 <GIC_SPI 791 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
792 <GIC_SPI 792 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
793 <GIC_SPI 793 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
794 interrupt-names = "err 794 interrupt-names = "error",
795 "ch0", 795 "ch0", "ch1", "ch2", "ch3",
796 "ch4", 796 "ch4", "ch5", "ch6", "ch7",
797 "ch8", 797 "ch8", "ch9", "ch10", "ch11",
798 "ch12" 798 "ch12", "ch13", "ch14", "ch15";
799 clocks = <&cpg CPG_MOD 799 clocks = <&cpg CPG_MOD 218>;
800 clock-names = "fck"; 800 clock-names = "fck";
801 power-domains = <&sysc 801 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
802 resets = <&cpg 218>; 802 resets = <&cpg 218>;
803 #dma-cells = <1>; 803 #dma-cells = <1>;
804 dma-channels = <16>; 804 dma-channels = <16>;
805 iommus = <&ipmmu_ds1 0 805 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
806 <&ipmmu_ds1 2>, 806 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
807 <&ipmmu_ds1 4>, 807 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
808 <&ipmmu_ds1 6>, 808 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
809 <&ipmmu_ds1 8>, 809 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
810 <&ipmmu_ds1 10> 810 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
811 <&ipmmu_ds1 12> 811 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
812 <&ipmmu_ds1 14> 812 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
813 }; 813 };
814 814
815 dmac2: dma-controller@e7310000 815 dmac2: dma-controller@e7310000 {
816 compatible = "renesas, 816 compatible = "renesas,dmac-r8a774c0",
817 "renesas, 817 "renesas,rcar-dmac";
818 reg = <0 0xe7310000 0 818 reg = <0 0xe7310000 0 0x10000>;
819 interrupts = <GIC_SPI 819 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
820 <GIC_SPI 820 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
821 <GIC_SPI 821 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
822 <GIC_SPI 822 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
823 <GIC_SPI 823 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
824 <GIC_SPI 824 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
825 <GIC_SPI 825 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
826 <GIC_SPI 826 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
827 <GIC_SPI 827 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
828 <GIC_SPI 828 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
829 <GIC_SPI 829 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
830 <GIC_SPI 830 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
831 <GIC_SPI 831 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
832 <GIC_SPI 832 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
833 <GIC_SPI 833 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
834 <GIC_SPI 834 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
835 <GIC_SPI 835 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
836 interrupt-names = "err 836 interrupt-names = "error",
837 "ch0", 837 "ch0", "ch1", "ch2", "ch3",
838 "ch4", 838 "ch4", "ch5", "ch6", "ch7",
839 "ch8", 839 "ch8", "ch9", "ch10", "ch11",
840 "ch12" 840 "ch12", "ch13", "ch14", "ch15";
841 clocks = <&cpg CPG_MOD 841 clocks = <&cpg CPG_MOD 217>;
842 clock-names = "fck"; 842 clock-names = "fck";
843 power-domains = <&sysc 843 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
844 resets = <&cpg 217>; 844 resets = <&cpg 217>;
845 #dma-cells = <1>; 845 #dma-cells = <1>;
846 dma-channels = <16>; 846 dma-channels = <16>;
847 iommus = <&ipmmu_ds1 1 847 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
848 <&ipmmu_ds1 18> 848 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
849 <&ipmmu_ds1 20> 849 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
850 <&ipmmu_ds1 22> 850 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
851 <&ipmmu_ds1 24> 851 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
852 <&ipmmu_ds1 26> 852 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
853 <&ipmmu_ds1 28> 853 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
854 <&ipmmu_ds1 30> 854 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
855 }; 855 };
856 856
857 ipmmu_ds0: iommu@e6740000 { 857 ipmmu_ds0: iommu@e6740000 {
858 compatible = "renesas, 858 compatible = "renesas,ipmmu-r8a774c0";
859 reg = <0 0xe6740000 0 859 reg = <0 0xe6740000 0 0x1000>;
860 renesas,ipmmu-main = < 860 renesas,ipmmu-main = <&ipmmu_mm 0>;
861 power-domains = <&sysc 861 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
862 #iommu-cells = <1>; 862 #iommu-cells = <1>;
863 }; 863 };
864 864
865 ipmmu_ds1: iommu@e7740000 { 865 ipmmu_ds1: iommu@e7740000 {
866 compatible = "renesas, 866 compatible = "renesas,ipmmu-r8a774c0";
867 reg = <0 0xe7740000 0 867 reg = <0 0xe7740000 0 0x1000>;
868 renesas,ipmmu-main = < 868 renesas,ipmmu-main = <&ipmmu_mm 1>;
869 power-domains = <&sysc 869 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
870 #iommu-cells = <1>; 870 #iommu-cells = <1>;
871 }; 871 };
872 872
873 ipmmu_hc: iommu@e6570000 { 873 ipmmu_hc: iommu@e6570000 {
874 compatible = "renesas, 874 compatible = "renesas,ipmmu-r8a774c0";
875 reg = <0 0xe6570000 0 875 reg = <0 0xe6570000 0 0x1000>;
876 renesas,ipmmu-main = < 876 renesas,ipmmu-main = <&ipmmu_mm 2>;
877 power-domains = <&sysc 877 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
878 #iommu-cells = <1>; 878 #iommu-cells = <1>;
879 }; 879 };
880 880
881 ipmmu_mm: iommu@e67b0000 { 881 ipmmu_mm: iommu@e67b0000 {
882 compatible = "renesas, 882 compatible = "renesas,ipmmu-r8a774c0";
883 reg = <0 0xe67b0000 0 883 reg = <0 0xe67b0000 0 0x1000>;
884 interrupts = <GIC_SPI 884 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
885 <GIC_SPI 885 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
886 power-domains = <&sysc 886 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
887 #iommu-cells = <1>; 887 #iommu-cells = <1>;
888 }; 888 };
889 889
890 ipmmu_mp: iommu@ec670000 { 890 ipmmu_mp: iommu@ec670000 {
891 compatible = "renesas, 891 compatible = "renesas,ipmmu-r8a774c0";
892 reg = <0 0xec670000 0 892 reg = <0 0xec670000 0 0x1000>;
893 renesas,ipmmu-main = < 893 renesas,ipmmu-main = <&ipmmu_mm 4>;
894 power-domains = <&sysc 894 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
895 #iommu-cells = <1>; 895 #iommu-cells = <1>;
896 }; 896 };
897 897
898 ipmmu_pv0: iommu@fd800000 { 898 ipmmu_pv0: iommu@fd800000 {
899 compatible = "renesas, 899 compatible = "renesas,ipmmu-r8a774c0";
900 reg = <0 0xfd800000 0 900 reg = <0 0xfd800000 0 0x1000>;
901 renesas,ipmmu-main = < 901 renesas,ipmmu-main = <&ipmmu_mm 6>;
902 power-domains = <&sysc 902 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
903 #iommu-cells = <1>; 903 #iommu-cells = <1>;
904 }; 904 };
905 905
906 ipmmu_vc0: iommu@fe6b0000 { 906 ipmmu_vc0: iommu@fe6b0000 {
907 compatible = "renesas, 907 compatible = "renesas,ipmmu-r8a774c0";
908 reg = <0 0xfe6b0000 0 908 reg = <0 0xfe6b0000 0 0x1000>;
909 renesas,ipmmu-main = < 909 renesas,ipmmu-main = <&ipmmu_mm 12>;
910 power-domains = <&sysc 910 power-domains = <&sysc R8A774C0_PD_A3VC>;
911 #iommu-cells = <1>; 911 #iommu-cells = <1>;
912 }; 912 };
913 913
914 ipmmu_vi0: iommu@febd0000 { 914 ipmmu_vi0: iommu@febd0000 {
915 compatible = "renesas, 915 compatible = "renesas,ipmmu-r8a774c0";
916 reg = <0 0xfebd0000 0 916 reg = <0 0xfebd0000 0 0x1000>;
917 renesas,ipmmu-main = < 917 renesas,ipmmu-main = <&ipmmu_mm 14>;
918 power-domains = <&sysc 918 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
919 #iommu-cells = <1>; 919 #iommu-cells = <1>;
920 }; 920 };
921 921
922 ipmmu_vp0: iommu@fe990000 { 922 ipmmu_vp0: iommu@fe990000 {
923 compatible = "renesas, 923 compatible = "renesas,ipmmu-r8a774c0";
924 reg = <0 0xfe990000 0 924 reg = <0 0xfe990000 0 0x1000>;
925 renesas,ipmmu-main = < 925 renesas,ipmmu-main = <&ipmmu_mm 16>;
926 power-domains = <&sysc 926 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
927 #iommu-cells = <1>; 927 #iommu-cells = <1>;
928 }; 928 };
929 929
930 avb: ethernet@e6800000 { 930 avb: ethernet@e6800000 {
931 compatible = "renesas, 931 compatible = "renesas,etheravb-r8a774c0",
932 "renesas, 932 "renesas,etheravb-rcar-gen3";
933 reg = <0 0xe6800000 0 933 reg = <0 0xe6800000 0 0x800>;
934 interrupts = <GIC_SPI 934 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
935 <GIC_SPI 935 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
936 <GIC_SPI 936 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
937 <GIC_SPI 937 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
938 <GIC_SPI 938 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
939 <GIC_SPI 939 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
940 <GIC_SPI 940 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
941 <GIC_SPI 941 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
942 <GIC_SPI 942 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
943 <GIC_SPI 943 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
944 <GIC_SPI 944 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
945 <GIC_SPI 945 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
946 <GIC_SPI 946 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
947 <GIC_SPI 947 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
948 <GIC_SPI 948 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
949 <GIC_SPI 949 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
950 <GIC_SPI 950 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
951 <GIC_SPI 951 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
952 <GIC_SPI 952 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
953 <GIC_SPI 953 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
954 <GIC_SPI 954 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
955 <GIC_SPI 955 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
956 <GIC_SPI 956 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
957 <GIC_SPI 957 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
958 <GIC_SPI 958 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
959 interrupt-names = "ch0 959 interrupt-names = "ch0", "ch1", "ch2", "ch3",
960 "ch4 960 "ch4", "ch5", "ch6", "ch7",
961 "ch8 961 "ch8", "ch9", "ch10", "ch11",
962 "ch1 962 "ch12", "ch13", "ch14", "ch15",
963 "ch1 963 "ch16", "ch17", "ch18", "ch19",
964 "ch2 964 "ch20", "ch21", "ch22", "ch23",
965 "ch2 965 "ch24";
966 clocks = <&cpg CPG_MOD 966 clocks = <&cpg CPG_MOD 812>;
967 clock-names = "fck"; 967 clock-names = "fck";
968 power-domains = <&sysc 968 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
969 resets = <&cpg 812>; 969 resets = <&cpg 812>;
970 phy-mode = "rgmii"; 970 phy-mode = "rgmii";
971 rx-internal-delay-ps = 971 rx-internal-delay-ps = <0>;
972 iommus = <&ipmmu_ds0 1 972 iommus = <&ipmmu_ds0 16>;
973 #address-cells = <1>; 973 #address-cells = <1>;
974 #size-cells = <0>; 974 #size-cells = <0>;
975 status = "disabled"; 975 status = "disabled";
976 }; 976 };
977 977
978 can0: can@e6c30000 { 978 can0: can@e6c30000 {
979 compatible = "renesas, 979 compatible = "renesas,can-r8a774c0",
980 "renesas, 980 "renesas,rcar-gen3-can";
981 reg = <0 0xe6c30000 0 981 reg = <0 0xe6c30000 0 0x1000>;
982 interrupts = <GIC_SPI 982 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
983 clocks = <&cpg CPG_MOD 983 clocks = <&cpg CPG_MOD 916>,
984 <&cpg CPG_COR 984 <&cpg CPG_CORE R8A774C0_CLK_CANFD>,
985 <&can_clk>; 985 <&can_clk>;
986 clock-names = "clkp1", 986 clock-names = "clkp1", "clkp2", "can_clk";
987 assigned-clocks = <&cp 987 assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>;
988 assigned-clock-rates = 988 assigned-clock-rates = <40000000>;
989 power-domains = <&sysc 989 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
990 resets = <&cpg 916>; 990 resets = <&cpg 916>;
991 status = "disabled"; 991 status = "disabled";
992 }; 992 };
993 993
994 can1: can@e6c38000 { 994 can1: can@e6c38000 {
995 compatible = "renesas, 995 compatible = "renesas,can-r8a774c0",
996 "renesas, 996 "renesas,rcar-gen3-can";
997 reg = <0 0xe6c38000 0 997 reg = <0 0xe6c38000 0 0x1000>;
998 interrupts = <GIC_SPI 998 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
999 clocks = <&cpg CPG_MOD 999 clocks = <&cpg CPG_MOD 915>,
1000 <&cpg CPG_CO 1000 <&cpg CPG_CORE R8A774C0_CLK_CANFD>,
1001 <&can_clk>; 1001 <&can_clk>;
1002 clock-names = "clkp1" 1002 clock-names = "clkp1", "clkp2", "can_clk";
1003 assigned-clocks = <&c 1003 assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>;
1004 assigned-clock-rates 1004 assigned-clock-rates = <40000000>;
1005 power-domains = <&sys 1005 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1006 resets = <&cpg 915>; 1006 resets = <&cpg 915>;
1007 status = "disabled"; 1007 status = "disabled";
1008 }; 1008 };
1009 1009
1010 canfd: can@e66c0000 { 1010 canfd: can@e66c0000 {
1011 compatible = "renesas 1011 compatible = "renesas,r8a774c0-canfd",
1012 "renesas 1012 "renesas,rcar-gen3-canfd";
1013 reg = <0 0xe66c0000 0 1013 reg = <0 0xe66c0000 0 0x8000>;
1014 interrupts = <GIC_SPI 1014 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
1015 <GIC_SPI 1015 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1016 interrupt-names = "ch 1016 interrupt-names = "ch_int", "g_int";
1017 clocks = <&cpg CPG_MO 1017 clocks = <&cpg CPG_MOD 914>,
1018 <&cpg CPG_CO 1018 <&cpg CPG_CORE R8A774C0_CLK_CANFD>,
1019 <&can_clk>; 1019 <&can_clk>;
1020 clock-names = "fck", 1020 clock-names = "fck", "canfd", "can_clk";
1021 assigned-clocks = <&c 1021 assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>;
1022 assigned-clock-rates 1022 assigned-clock-rates = <40000000>;
1023 power-domains = <&sys 1023 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1024 resets = <&cpg 914>; 1024 resets = <&cpg 914>;
1025 status = "disabled"; 1025 status = "disabled";
1026 1026
1027 channel0 { 1027 channel0 {
1028 status = "dis 1028 status = "disabled";
1029 }; 1029 };
1030 1030
1031 channel1 { 1031 channel1 {
1032 status = "dis 1032 status = "disabled";
1033 }; 1033 };
1034 }; 1034 };
1035 1035
1036 pwm0: pwm@e6e30000 { 1036 pwm0: pwm@e6e30000 {
1037 compatible = "renesas 1037 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1038 reg = <0 0xe6e30000 0 1038 reg = <0 0xe6e30000 0 0x8>;
1039 clocks = <&cpg CPG_MO 1039 clocks = <&cpg CPG_MOD 523>;
1040 power-domains = <&sys 1040 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1041 resets = <&cpg 523>; 1041 resets = <&cpg 523>;
1042 #pwm-cells = <2>; 1042 #pwm-cells = <2>;
1043 status = "disabled"; 1043 status = "disabled";
1044 }; 1044 };
1045 1045
1046 pwm1: pwm@e6e31000 { 1046 pwm1: pwm@e6e31000 {
1047 compatible = "renesas 1047 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1048 reg = <0 0xe6e31000 0 1048 reg = <0 0xe6e31000 0 0x8>;
1049 clocks = <&cpg CPG_MO 1049 clocks = <&cpg CPG_MOD 523>;
1050 power-domains = <&sys 1050 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1051 resets = <&cpg 523>; 1051 resets = <&cpg 523>;
1052 #pwm-cells = <2>; 1052 #pwm-cells = <2>;
1053 status = "disabled"; 1053 status = "disabled";
1054 }; 1054 };
1055 1055
1056 pwm2: pwm@e6e32000 { 1056 pwm2: pwm@e6e32000 {
1057 compatible = "renesas 1057 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1058 reg = <0 0xe6e32000 0 1058 reg = <0 0xe6e32000 0 0x8>;
1059 clocks = <&cpg CPG_MO 1059 clocks = <&cpg CPG_MOD 523>;
1060 power-domains = <&sys 1060 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1061 resets = <&cpg 523>; 1061 resets = <&cpg 523>;
1062 #pwm-cells = <2>; 1062 #pwm-cells = <2>;
1063 status = "disabled"; 1063 status = "disabled";
1064 }; 1064 };
1065 1065
1066 pwm3: pwm@e6e33000 { 1066 pwm3: pwm@e6e33000 {
1067 compatible = "renesas 1067 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1068 reg = <0 0xe6e33000 0 1068 reg = <0 0xe6e33000 0 0x8>;
1069 clocks = <&cpg CPG_MO 1069 clocks = <&cpg CPG_MOD 523>;
1070 power-domains = <&sys 1070 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1071 resets = <&cpg 523>; 1071 resets = <&cpg 523>;
1072 #pwm-cells = <2>; 1072 #pwm-cells = <2>;
1073 status = "disabled"; 1073 status = "disabled";
1074 }; 1074 };
1075 1075
1076 pwm4: pwm@e6e34000 { 1076 pwm4: pwm@e6e34000 {
1077 compatible = "renesas 1077 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1078 reg = <0 0xe6e34000 0 1078 reg = <0 0xe6e34000 0 0x8>;
1079 clocks = <&cpg CPG_MO 1079 clocks = <&cpg CPG_MOD 523>;
1080 power-domains = <&sys 1080 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1081 resets = <&cpg 523>; 1081 resets = <&cpg 523>;
1082 #pwm-cells = <2>; 1082 #pwm-cells = <2>;
1083 status = "disabled"; 1083 status = "disabled";
1084 }; 1084 };
1085 1085
1086 pwm5: pwm@e6e35000 { 1086 pwm5: pwm@e6e35000 {
1087 compatible = "renesas 1087 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1088 reg = <0 0xe6e35000 0 1088 reg = <0 0xe6e35000 0 0x8>;
1089 clocks = <&cpg CPG_MO 1089 clocks = <&cpg CPG_MOD 523>;
1090 power-domains = <&sys 1090 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1091 resets = <&cpg 523>; 1091 resets = <&cpg 523>;
1092 #pwm-cells = <2>; 1092 #pwm-cells = <2>;
1093 status = "disabled"; 1093 status = "disabled";
1094 }; 1094 };
1095 1095
1096 pwm6: pwm@e6e36000 { 1096 pwm6: pwm@e6e36000 {
1097 compatible = "renesas 1097 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1098 reg = <0 0xe6e36000 0 1098 reg = <0 0xe6e36000 0 0x8>;
1099 clocks = <&cpg CPG_MO 1099 clocks = <&cpg CPG_MOD 523>;
1100 power-domains = <&sys 1100 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1101 resets = <&cpg 523>; 1101 resets = <&cpg 523>;
1102 #pwm-cells = <2>; 1102 #pwm-cells = <2>;
1103 status = "disabled"; 1103 status = "disabled";
1104 }; 1104 };
1105 1105
1106 scif0: serial@e6e60000 { 1106 scif0: serial@e6e60000 {
1107 compatible = "renesas 1107 compatible = "renesas,scif-r8a774c0",
1108 "renesas 1108 "renesas,rcar-gen3-scif", "renesas,scif";
1109 reg = <0 0xe6e60000 0 1109 reg = <0 0xe6e60000 0 64>;
1110 interrupts = <GIC_SPI 1110 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
1111 clocks = <&cpg CPG_MO 1111 clocks = <&cpg CPG_MOD 207>,
1112 <&cpg CPG_CO 1112 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
1113 <&scif_clk>; 1113 <&scif_clk>;
1114 clock-names = "fck", 1114 clock-names = "fck", "brg_int", "scif_clk";
1115 dmas = <&dmac1 0x51>, 1115 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1116 <&dmac2 0x51>, 1116 <&dmac2 0x51>, <&dmac2 0x50>;
1117 dma-names = "tx", "rx 1117 dma-names = "tx", "rx", "tx", "rx";
1118 power-domains = <&sys 1118 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1119 resets = <&cpg 207>; 1119 resets = <&cpg 207>;
1120 status = "disabled"; 1120 status = "disabled";
1121 }; 1121 };
1122 1122
1123 scif1: serial@e6e68000 { 1123 scif1: serial@e6e68000 {
1124 compatible = "renesas 1124 compatible = "renesas,scif-r8a774c0",
1125 "renesas 1125 "renesas,rcar-gen3-scif", "renesas,scif";
1126 reg = <0 0xe6e68000 0 1126 reg = <0 0xe6e68000 0 64>;
1127 interrupts = <GIC_SPI 1127 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
1128 clocks = <&cpg CPG_MO 1128 clocks = <&cpg CPG_MOD 206>,
1129 <&cpg CPG_CO 1129 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
1130 <&scif_clk>; 1130 <&scif_clk>;
1131 clock-names = "fck", 1131 clock-names = "fck", "brg_int", "scif_clk";
1132 dmas = <&dmac1 0x53>, 1132 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1133 <&dmac2 0x53>, 1133 <&dmac2 0x53>, <&dmac2 0x52>;
1134 dma-names = "tx", "rx 1134 dma-names = "tx", "rx", "tx", "rx";
1135 power-domains = <&sys 1135 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1136 resets = <&cpg 206>; 1136 resets = <&cpg 206>;
1137 status = "disabled"; 1137 status = "disabled";
1138 }; 1138 };
1139 1139
1140 scif2: serial@e6e88000 { 1140 scif2: serial@e6e88000 {
1141 compatible = "renesas 1141 compatible = "renesas,scif-r8a774c0",
1142 "renesas 1142 "renesas,rcar-gen3-scif", "renesas,scif";
1143 reg = <0 0xe6e88000 0 1143 reg = <0 0xe6e88000 0 64>;
1144 interrupts = <GIC_SPI 1144 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
1145 clocks = <&cpg CPG_MO 1145 clocks = <&cpg CPG_MOD 310>,
1146 <&cpg CPG_CO 1146 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
1147 <&scif_clk>; 1147 <&scif_clk>;
1148 clock-names = "fck", 1148 clock-names = "fck", "brg_int", "scif_clk";
1149 dmas = <&dmac1 0x13>, 1149 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1150 <&dmac2 0x13>, 1150 <&dmac2 0x13>, <&dmac2 0x12>;
1151 dma-names = "tx", "rx 1151 dma-names = "tx", "rx", "tx", "rx";
1152 power-domains = <&sys 1152 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1153 resets = <&cpg 310>; 1153 resets = <&cpg 310>;
1154 status = "disabled"; 1154 status = "disabled";
1155 }; 1155 };
1156 1156
1157 scif3: serial@e6c50000 { 1157 scif3: serial@e6c50000 {
1158 compatible = "renesas 1158 compatible = "renesas,scif-r8a774c0",
1159 "renesas 1159 "renesas,rcar-gen3-scif", "renesas,scif";
1160 reg = <0 0xe6c50000 0 1160 reg = <0 0xe6c50000 0 64>;
1161 interrupts = <GIC_SPI 1161 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1162 clocks = <&cpg CPG_MO 1162 clocks = <&cpg CPG_MOD 204>,
1163 <&cpg CPG_CO 1163 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
1164 <&scif_clk>; 1164 <&scif_clk>;
1165 clock-names = "fck", 1165 clock-names = "fck", "brg_int", "scif_clk";
1166 dmas = <&dmac0 0x57>, 1166 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1167 dma-names = "tx", "rx 1167 dma-names = "tx", "rx";
1168 power-domains = <&sys 1168 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1169 resets = <&cpg 204>; 1169 resets = <&cpg 204>;
1170 status = "disabled"; 1170 status = "disabled";
1171 }; 1171 };
1172 1172
1173 scif4: serial@e6c40000 { 1173 scif4: serial@e6c40000 {
1174 compatible = "renesas 1174 compatible = "renesas,scif-r8a774c0",
1175 "renesas 1175 "renesas,rcar-gen3-scif", "renesas,scif";
1176 reg = <0 0xe6c40000 0 1176 reg = <0 0xe6c40000 0 64>;
1177 interrupts = <GIC_SPI 1177 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1178 clocks = <&cpg CPG_MO 1178 clocks = <&cpg CPG_MOD 203>,
1179 <&cpg CPG_CO 1179 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
1180 <&scif_clk>; 1180 <&scif_clk>;
1181 clock-names = "fck", 1181 clock-names = "fck", "brg_int", "scif_clk";
1182 dmas = <&dmac0 0x59>, 1182 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1183 dma-names = "tx", "rx 1183 dma-names = "tx", "rx";
1184 power-domains = <&sys 1184 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1185 resets = <&cpg 203>; 1185 resets = <&cpg 203>;
1186 status = "disabled"; 1186 status = "disabled";
1187 }; 1187 };
1188 1188
1189 scif5: serial@e6f30000 { 1189 scif5: serial@e6f30000 {
1190 compatible = "renesas 1190 compatible = "renesas,scif-r8a774c0",
1191 "renesas 1191 "renesas,rcar-gen3-scif", "renesas,scif";
1192 reg = <0 0xe6f30000 0 1192 reg = <0 0xe6f30000 0 64>;
1193 interrupts = <GIC_SPI 1193 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1194 clocks = <&cpg CPG_MO 1194 clocks = <&cpg CPG_MOD 202>,
1195 <&cpg CPG_CO 1195 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
1196 <&scif_clk>; 1196 <&scif_clk>;
1197 clock-names = "fck", 1197 clock-names = "fck", "brg_int", "scif_clk";
1198 dmas = <&dmac0 0x5b>, 1198 dmas = <&dmac0 0x5b>, <&dmac0 0x5a>;
1199 dma-names = "tx", "rx 1199 dma-names = "tx", "rx";
1200 power-domains = <&sys 1200 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1201 resets = <&cpg 202>; 1201 resets = <&cpg 202>;
1202 status = "disabled"; 1202 status = "disabled";
1203 }; 1203 };
1204 1204
1205 msiof0: spi@e6e90000 { 1205 msiof0: spi@e6e90000 {
1206 compatible = "renesas 1206 compatible = "renesas,msiof-r8a774c0",
1207 "renesas 1207 "renesas,rcar-gen3-msiof";
1208 reg = <0 0xe6e90000 0 1208 reg = <0 0xe6e90000 0 0x0064>;
1209 interrupts = <GIC_SPI 1209 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1210 clocks = <&cpg CPG_MO 1210 clocks = <&cpg CPG_MOD 211>;
1211 dmas = <&dmac1 0x41>, 1211 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1212 <&dmac2 0x41>, 1212 <&dmac2 0x41>, <&dmac2 0x40>;
1213 dma-names = "tx", "rx 1213 dma-names = "tx", "rx", "tx", "rx";
1214 power-domains = <&sys 1214 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1215 resets = <&cpg 211>; 1215 resets = <&cpg 211>;
1216 #address-cells = <1>; 1216 #address-cells = <1>;
1217 #size-cells = <0>; 1217 #size-cells = <0>;
1218 status = "disabled"; 1218 status = "disabled";
1219 }; 1219 };
1220 1220
1221 msiof1: spi@e6ea0000 { 1221 msiof1: spi@e6ea0000 {
1222 compatible = "renesas 1222 compatible = "renesas,msiof-r8a774c0",
1223 "renesas 1223 "renesas,rcar-gen3-msiof";
1224 reg = <0 0xe6ea0000 0 1224 reg = <0 0xe6ea0000 0 0x0064>;
1225 interrupts = <GIC_SPI 1225 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1226 clocks = <&cpg CPG_MO 1226 clocks = <&cpg CPG_MOD 210>;
1227 dmas = <&dmac0 0x43>, 1227 dmas = <&dmac0 0x43>, <&dmac0 0x42>;
1228 dma-names = "tx", "rx 1228 dma-names = "tx", "rx";
1229 power-domains = <&sys 1229 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1230 resets = <&cpg 210>; 1230 resets = <&cpg 210>;
1231 #address-cells = <1>; 1231 #address-cells = <1>;
1232 #size-cells = <0>; 1232 #size-cells = <0>;
1233 status = "disabled"; 1233 status = "disabled";
1234 }; 1234 };
1235 1235
1236 msiof2: spi@e6c00000 { 1236 msiof2: spi@e6c00000 {
1237 compatible = "renesas 1237 compatible = "renesas,msiof-r8a774c0",
1238 "renesas 1238 "renesas,rcar-gen3-msiof";
1239 reg = <0 0xe6c00000 0 1239 reg = <0 0xe6c00000 0 0x0064>;
1240 interrupts = <GIC_SPI 1240 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1241 clocks = <&cpg CPG_MO 1241 clocks = <&cpg CPG_MOD 209>;
1242 dmas = <&dmac0 0x45>, 1242 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1243 dma-names = "tx", "rx 1243 dma-names = "tx", "rx";
1244 power-domains = <&sys 1244 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1245 resets = <&cpg 209>; 1245 resets = <&cpg 209>;
1246 #address-cells = <1>; 1246 #address-cells = <1>;
1247 #size-cells = <0>; 1247 #size-cells = <0>;
1248 status = "disabled"; 1248 status = "disabled";
1249 }; 1249 };
1250 1250
1251 msiof3: spi@e6c10000 { 1251 msiof3: spi@e6c10000 {
1252 compatible = "renesas 1252 compatible = "renesas,msiof-r8a774c0",
1253 "renesas 1253 "renesas,rcar-gen3-msiof";
1254 reg = <0 0xe6c10000 0 1254 reg = <0 0xe6c10000 0 0x0064>;
1255 interrupts = <GIC_SPI 1255 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1256 clocks = <&cpg CPG_MO 1256 clocks = <&cpg CPG_MOD 208>;
1257 dmas = <&dmac0 0x47>, 1257 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1258 dma-names = "tx", "rx 1258 dma-names = "tx", "rx";
1259 power-domains = <&sys 1259 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1260 resets = <&cpg 208>; 1260 resets = <&cpg 208>;
1261 #address-cells = <1>; 1261 #address-cells = <1>;
1262 #size-cells = <0>; 1262 #size-cells = <0>;
1263 status = "disabled"; 1263 status = "disabled";
1264 }; 1264 };
1265 1265
1266 vin4: video@e6ef4000 { 1266 vin4: video@e6ef4000 {
1267 compatible = "renesas 1267 compatible = "renesas,vin-r8a774c0";
1268 reg = <0 0xe6ef4000 0 1268 reg = <0 0xe6ef4000 0 0x1000>;
1269 interrupts = <GIC_SPI 1269 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
1270 clocks = <&cpg CPG_MO 1270 clocks = <&cpg CPG_MOD 807>;
1271 power-domains = <&sys 1271 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1272 resets = <&cpg 807>; 1272 resets = <&cpg 807>;
1273 renesas,id = <4>; 1273 renesas,id = <4>;
1274 status = "disabled"; 1274 status = "disabled";
1275 1275
1276 ports { 1276 ports {
1277 #address-cell 1277 #address-cells = <1>;
1278 #size-cells = 1278 #size-cells = <0>;
1279 1279
1280 port@1 { 1280 port@1 {
1281 #addr 1281 #address-cells = <1>;
1282 #size 1282 #size-cells = <0>;
1283 1283
1284 reg = 1284 reg = <1>;
1285 1285
1286 vin4c 1286 vin4csi40: endpoint@2 {
1287 1287 reg = <2>;
1288 1288 remote-endpoint = <&csi40vin4>;
1289 }; 1289 };
1290 }; 1290 };
1291 }; 1291 };
1292 }; 1292 };
1293 1293
1294 vin5: video@e6ef5000 { 1294 vin5: video@e6ef5000 {
1295 compatible = "renesas 1295 compatible = "renesas,vin-r8a774c0";
1296 reg = <0 0xe6ef5000 0 1296 reg = <0 0xe6ef5000 0 0x1000>;
1297 interrupts = <GIC_SPI 1297 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
1298 clocks = <&cpg CPG_MO 1298 clocks = <&cpg CPG_MOD 806>;
1299 power-domains = <&sys 1299 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1300 resets = <&cpg 806>; 1300 resets = <&cpg 806>;
1301 renesas,id = <5>; 1301 renesas,id = <5>;
1302 status = "disabled"; 1302 status = "disabled";
1303 1303
1304 ports { 1304 ports {
1305 #address-cell 1305 #address-cells = <1>;
1306 #size-cells = 1306 #size-cells = <0>;
1307 1307
1308 port@1 { 1308 port@1 {
1309 #addr 1309 #address-cells = <1>;
1310 #size 1310 #size-cells = <0>;
1311 1311
1312 reg = 1312 reg = <1>;
1313 1313
1314 vin5c 1314 vin5csi40: endpoint@2 {
1315 1315 reg = <2>;
1316 1316 remote-endpoint = <&csi40vin5>;
1317 }; 1317 };
1318 }; 1318 };
1319 }; 1319 };
1320 }; 1320 };
1321 1321
1322 rcar_sound: sound@ec500000 { 1322 rcar_sound: sound@ec500000 {
1323 /* 1323 /*
1324 * #sound-dai-cells i 1324 * #sound-dai-cells is required if simple-card
1325 * 1325 *
1326 * Single DAI : #soun 1326 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1327 * Multi DAI : #soun 1327 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1328 */ 1328 */
1329 /* 1329 /*
1330 * #clock-cells is re 1330 * #clock-cells is required for audio_clkout0/1/2/3
1331 * 1331 *
1332 * clkout : #cl 1332 * clkout : #clock-cells = <0>; <&rcar_sound>;
1333 * clkout0/1/2/3: #cl 1333 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
1334 */ 1334 */
1335 compatible = "renesas 1335 compatible = "renesas,rcar_sound-r8a774c0",
1336 "renesas 1336 "renesas,rcar_sound-gen3";
1337 reg = <0 0xec500000 0 1337 reg = <0 0xec500000 0 0x1000>, /* SCU */
1338 <0 0xec5a0000 0 1338 <0 0xec5a0000 0 0x100>, /* ADG */
1339 <0 0xec540000 0 1339 <0 0xec540000 0 0x1000>, /* SSIU */
1340 <0 0xec541000 0 1340 <0 0xec541000 0 0x280>, /* SSI */
1341 <0 0xec760000 0 1341 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
1342 reg-names = "scu", "a 1342 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1343 1343
1344 clocks = <&cpg CPG_MO 1344 clocks = <&cpg CPG_MOD 1005>,
1345 <&cpg CPG_MO 1345 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
1346 <&cpg CPG_MO 1346 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
1347 <&cpg CPG_MO 1347 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
1348 <&cpg CPG_MO 1348 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
1349 <&cpg CPG_MO 1349 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
1350 <&cpg CPG_MO 1350 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
1351 <&cpg CPG_MO 1351 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
1352 <&cpg CPG_MO 1352 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
1353 <&cpg CPG_MO 1353 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
1354 <&cpg CPG_MO 1354 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
1355 <&cpg CPG_MO 1355 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1356 <&cpg CPG_MO 1356 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1357 <&cpg CPG_MO 1357 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
1358 <&audio_clk_ 1358 <&audio_clk_a>, <&audio_clk_b>,
1359 <&audio_clk_ 1359 <&audio_clk_c>,
1360 <&cpg CPG_MO 1360 <&cpg CPG_MOD 922>;
1361 clock-names = "ssi-al 1361 clock-names = "ssi-all",
1362 "ssi.9" 1362 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1363 "ssi.5" 1363 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1364 "ssi.1" 1364 "ssi.1", "ssi.0",
1365 "src.9" 1365 "src.9", "src.8", "src.7", "src.6",
1366 "src.5" 1366 "src.5", "src.4", "src.3", "src.2",
1367 "src.1" 1367 "src.1", "src.0",
1368 "mix.1" 1368 "mix.1", "mix.0",
1369 "ctu.1" 1369 "ctu.1", "ctu.0",
1370 "dvc.0" 1370 "dvc.0", "dvc.1",
1371 "clk_a" 1371 "clk_a", "clk_b", "clk_c", "clk_i";
1372 power-domains = <&sys 1372 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1373 resets = <&cpg 1005>, 1373 resets = <&cpg 1005>,
1374 <&cpg 1006>, 1374 <&cpg 1006>, <&cpg 1007>,
1375 <&cpg 1008>, 1375 <&cpg 1008>, <&cpg 1009>,
1376 <&cpg 1010>, 1376 <&cpg 1010>, <&cpg 1011>,
1377 <&cpg 1012>, 1377 <&cpg 1012>, <&cpg 1013>,
1378 <&cpg 1014>, 1378 <&cpg 1014>, <&cpg 1015>;
1379 reset-names = "ssi-al 1379 reset-names = "ssi-all",
1380 "ssi.9" 1380 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1381 "ssi.5" 1381 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1382 "ssi.1" 1382 "ssi.1", "ssi.0";
1383 status = "disabled"; 1383 status = "disabled";
1384 1384
1385 rcar_sound,ctu { 1385 rcar_sound,ctu {
1386 ctu00: ctu-0 1386 ctu00: ctu-0 { };
1387 ctu01: ctu-1 1387 ctu01: ctu-1 { };
1388 ctu02: ctu-2 1388 ctu02: ctu-2 { };
1389 ctu03: ctu-3 1389 ctu03: ctu-3 { };
1390 ctu10: ctu-4 1390 ctu10: ctu-4 { };
1391 ctu11: ctu-5 1391 ctu11: ctu-5 { };
1392 ctu12: ctu-6 1392 ctu12: ctu-6 { };
1393 ctu13: ctu-7 1393 ctu13: ctu-7 { };
1394 }; 1394 };
1395 1395
1396 rcar_sound,dvc { 1396 rcar_sound,dvc {
1397 dvc0: dvc-0 { 1397 dvc0: dvc-0 {
1398 dmas 1398 dmas = <&audma0 0xbc>;
1399 dma-n 1399 dma-names = "tx";
1400 }; 1400 };
1401 dvc1: dvc-1 { 1401 dvc1: dvc-1 {
1402 dmas 1402 dmas = <&audma0 0xbe>;
1403 dma-n 1403 dma-names = "tx";
1404 }; 1404 };
1405 }; 1405 };
1406 1406
1407 rcar_sound,mix { 1407 rcar_sound,mix {
1408 mix0: mix-0 { 1408 mix0: mix-0 { };
1409 mix1: mix-1 { 1409 mix1: mix-1 { };
1410 }; 1410 };
1411 1411
1412 rcar_sound,src { 1412 rcar_sound,src {
1413 src0: src-0 { 1413 src0: src-0 {
1414 inter 1414 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1415 dmas 1415 dmas = <&audma0 0x85>, <&audma0 0x9a>;
1416 dma-n 1416 dma-names = "rx", "tx";
1417 }; 1417 };
1418 src1: src-1 { 1418 src1: src-1 {
1419 inter 1419 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1420 dmas 1420 dmas = <&audma0 0x87>, <&audma0 0x9c>;
1421 dma-n 1421 dma-names = "rx", "tx";
1422 }; 1422 };
1423 src2: src-2 { 1423 src2: src-2 {
1424 inter 1424 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1425 dmas 1425 dmas = <&audma0 0x89>, <&audma0 0x9e>;
1426 dma-n 1426 dma-names = "rx", "tx";
1427 }; 1427 };
1428 src3: src-3 { 1428 src3: src-3 {
1429 inter 1429 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1430 dmas 1430 dmas = <&audma0 0x8b>, <&audma0 0xa0>;
1431 dma-n 1431 dma-names = "rx", "tx";
1432 }; 1432 };
1433 src4: src-4 { 1433 src4: src-4 {
1434 inter 1434 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1435 dmas 1435 dmas = <&audma0 0x8d>, <&audma0 0xb0>;
1436 dma-n 1436 dma-names = "rx", "tx";
1437 }; 1437 };
1438 src5: src-5 { 1438 src5: src-5 {
1439 inter 1439 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1440 dmas 1440 dmas = <&audma0 0x8f>, <&audma0 0xb2>;
1441 dma-n 1441 dma-names = "rx", "tx";
1442 }; 1442 };
1443 src6: src-6 { 1443 src6: src-6 {
1444 inter 1444 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1445 dmas 1445 dmas = <&audma0 0x91>, <&audma0 0xb4>;
1446 dma-n 1446 dma-names = "rx", "tx";
1447 }; 1447 };
1448 src7: src-7 { 1448 src7: src-7 {
1449 inter 1449 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1450 dmas 1450 dmas = <&audma0 0x93>, <&audma0 0xb6>;
1451 dma-n 1451 dma-names = "rx", "tx";
1452 }; 1452 };
1453 src8: src-8 { 1453 src8: src-8 {
1454 inter 1454 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1455 dmas 1455 dmas = <&audma0 0x95>, <&audma0 0xb8>;
1456 dma-n 1456 dma-names = "rx", "tx";
1457 }; 1457 };
1458 src9: src-9 { 1458 src9: src-9 {
1459 inter 1459 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
1460 dmas 1460 dmas = <&audma0 0x97>, <&audma0 0xba>;
1461 dma-n 1461 dma-names = "rx", "tx";
1462 }; 1462 };
1463 }; 1463 };
1464 1464
1465 rcar_sound,ssi { 1465 rcar_sound,ssi {
1466 ssi0: ssi-0 { 1466 ssi0: ssi-0 {
1467 inter 1467 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
1468 dmas 1468 dmas = <&audma0 0x01>, <&audma0 0x02>,
1469 1469 <&audma0 0x15>, <&audma0 0x16>;
1470 dma-n 1470 dma-names = "rx", "tx", "rxu", "txu";
1471 }; 1471 };
1472 ssi1: ssi-1 { 1472 ssi1: ssi-1 {
1473 inter 1473 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
1474 dmas 1474 dmas = <&audma0 0x03>, <&audma0 0x04>,
1475 1475 <&audma0 0x49>, <&audma0 0x4a>;
1476 dma-n 1476 dma-names = "rx", "tx", "rxu", "txu";
1477 }; 1477 };
1478 ssi2: ssi-2 { 1478 ssi2: ssi-2 {
1479 inter 1479 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
1480 dmas 1480 dmas = <&audma0 0x05>, <&audma0 0x06>,
1481 1481 <&audma0 0x63>, <&audma0 0x64>;
1482 dma-n 1482 dma-names = "rx", "tx", "rxu", "txu";
1483 }; 1483 };
1484 ssi3: ssi-3 { 1484 ssi3: ssi-3 {
1485 inter 1485 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1486 dmas 1486 dmas = <&audma0 0x07>, <&audma0 0x08>,
1487 1487 <&audma0 0x6f>, <&audma0 0x70>;
1488 dma-n 1488 dma-names = "rx", "tx", "rxu", "txu";
1489 }; 1489 };
1490 ssi4: ssi-4 { 1490 ssi4: ssi-4 {
1491 inter 1491 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1492 dmas 1492 dmas = <&audma0 0x09>, <&audma0 0x0a>,
1493 1493 <&audma0 0x71>, <&audma0 0x72>;
1494 dma-n 1494 dma-names = "rx", "tx", "rxu", "txu";
1495 }; 1495 };
1496 ssi5: ssi-5 { 1496 ssi5: ssi-5 {
1497 inter 1497 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1498 dmas 1498 dmas = <&audma0 0x0b>, <&audma0 0x0c>,
1499 1499 <&audma0 0x73>, <&audma0 0x74>;
1500 dma-n 1500 dma-names = "rx", "tx", "rxu", "txu";
1501 }; 1501 };
1502 ssi6: ssi-6 { 1502 ssi6: ssi-6 {
1503 inter 1503 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
1504 dmas 1504 dmas = <&audma0 0x0d>, <&audma0 0x0e>,
1505 1505 <&audma0 0x75>, <&audma0 0x76>;
1506 dma-n 1506 dma-names = "rx", "tx", "rxu", "txu";
1507 }; 1507 };
1508 ssi7: ssi-7 { 1508 ssi7: ssi-7 {
1509 inter 1509 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
1510 dmas 1510 dmas = <&audma0 0x0f>, <&audma0 0x10>,
1511 1511 <&audma0 0x79>, <&audma0 0x7a>;
1512 dma-n 1512 dma-names = "rx", "tx", "rxu", "txu";
1513 }; 1513 };
1514 ssi8: ssi-8 { 1514 ssi8: ssi-8 {
1515 inter 1515 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
1516 dmas 1516 dmas = <&audma0 0x11>, <&audma0 0x12>,
1517 1517 <&audma0 0x7b>, <&audma0 0x7c>;
1518 dma-n 1518 dma-names = "rx", "tx", "rxu", "txu";
1519 }; 1519 };
1520 ssi9: ssi-9 { 1520 ssi9: ssi-9 {
1521 inter 1521 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
1522 dmas 1522 dmas = <&audma0 0x13>, <&audma0 0x14>,
1523 1523 <&audma0 0x7d>, <&audma0 0x7e>;
1524 dma-n 1524 dma-names = "rx", "tx", "rxu", "txu";
1525 }; 1525 };
1526 }; 1526 };
1527 }; 1527 };
1528 1528
1529 audma0: dma-controller@ec7000 1529 audma0: dma-controller@ec700000 {
1530 compatible = "renesas 1530 compatible = "renesas,dmac-r8a774c0",
1531 "renesas 1531 "renesas,rcar-dmac";
1532 reg = <0 0xec700000 0 1532 reg = <0 0xec700000 0 0x10000>;
1533 interrupts = <GIC_SPI 1533 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
1534 <GIC_SPI 1534 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
1535 <GIC_SPI 1535 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
1536 <GIC_SPI 1536 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
1537 <GIC_SPI 1537 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
1538 <GIC_SPI 1538 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
1539 <GIC_SPI 1539 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
1540 <GIC_SPI 1540 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
1541 <GIC_SPI 1541 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
1542 <GIC_SPI 1542 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
1543 <GIC_SPI 1543 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1544 <GIC_SPI 1544 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
1545 <GIC_SPI 1545 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
1546 <GIC_SPI 1546 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
1547 <GIC_SPI 1547 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
1548 <GIC_SPI 1548 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1549 <GIC_SPI 1549 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
1550 interrupt-names = "er 1550 interrupt-names = "error",
1551 "ch0" 1551 "ch0", "ch1", "ch2", "ch3",
1552 "ch4" 1552 "ch4", "ch5", "ch6", "ch7",
1553 "ch8" 1553 "ch8", "ch9", "ch10", "ch11",
1554 "ch12 1554 "ch12", "ch13", "ch14", "ch15";
1555 clocks = <&cpg CPG_MO 1555 clocks = <&cpg CPG_MOD 502>;
1556 clock-names = "fck"; 1556 clock-names = "fck";
1557 power-domains = <&sys 1557 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1558 resets = <&cpg 502>; 1558 resets = <&cpg 502>;
1559 #dma-cells = <1>; 1559 #dma-cells = <1>;
1560 dma-channels = <16>; 1560 dma-channels = <16>;
1561 iommus = <&ipmmu_mp 0 1561 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
1562 <&ipmmu_mp 2 1562 <&ipmmu_mp 2>, <&ipmmu_mp 3>,
1563 <&ipmmu_mp 4 1563 <&ipmmu_mp 4>, <&ipmmu_mp 5>,
1564 <&ipmmu_mp 6 1564 <&ipmmu_mp 6>, <&ipmmu_mp 7>,
1565 <&ipmmu_mp 8 1565 <&ipmmu_mp 8>, <&ipmmu_mp 9>,
1566 <&ipmmu_mp 1 1566 <&ipmmu_mp 10>, <&ipmmu_mp 11>,
1567 <&ipmmu_mp 1 1567 <&ipmmu_mp 12>, <&ipmmu_mp 13>,
1568 <&ipmmu_mp 1 1568 <&ipmmu_mp 14>, <&ipmmu_mp 15>;
1569 }; 1569 };
1570 1570
1571 xhci0: usb@ee000000 { 1571 xhci0: usb@ee000000 {
1572 compatible = "renesas 1572 compatible = "renesas,xhci-r8a774c0",
1573 "renesas 1573 "renesas,rcar-gen3-xhci";
1574 reg = <0 0xee000000 0 1574 reg = <0 0xee000000 0 0xc00>;
1575 interrupts = <GIC_SPI 1575 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1576 clocks = <&cpg CPG_MO 1576 clocks = <&cpg CPG_MOD 328>;
1577 power-domains = <&sys 1577 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1578 resets = <&cpg 328>; 1578 resets = <&cpg 328>;
1579 status = "disabled"; 1579 status = "disabled";
1580 }; 1580 };
1581 1581
1582 usb3_peri0: usb@ee020000 { 1582 usb3_peri0: usb@ee020000 {
1583 compatible = "renesas 1583 compatible = "renesas,r8a774c0-usb3-peri",
1584 "renesas 1584 "renesas,rcar-gen3-usb3-peri";
1585 reg = <0 0xee020000 0 1585 reg = <0 0xee020000 0 0x400>;
1586 interrupts = <GIC_SPI 1586 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1587 clocks = <&cpg CPG_MO 1587 clocks = <&cpg CPG_MOD 328>;
1588 power-domains = <&sys 1588 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1589 resets = <&cpg 328>; 1589 resets = <&cpg 328>;
1590 status = "disabled"; 1590 status = "disabled";
1591 }; 1591 };
1592 1592
1593 ohci0: usb@ee080000 { 1593 ohci0: usb@ee080000 {
1594 compatible = "generic 1594 compatible = "generic-ohci";
1595 reg = <0 0xee080000 0 1595 reg = <0 0xee080000 0 0x100>;
1596 interrupts = <GIC_SPI 1596 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1597 clocks = <&cpg CPG_MO 1597 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
1598 phys = <&usb2_phy0 1> 1598 phys = <&usb2_phy0 1>;
1599 phy-names = "usb"; 1599 phy-names = "usb";
1600 power-domains = <&sys 1600 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1601 resets = <&cpg 703>, 1601 resets = <&cpg 703>, <&cpg 704>;
1602 status = "disabled"; 1602 status = "disabled";
1603 }; 1603 };
1604 1604
1605 ehci0: usb@ee080100 { 1605 ehci0: usb@ee080100 {
1606 compatible = "generic 1606 compatible = "generic-ehci";
1607 reg = <0 0xee080100 0 1607 reg = <0 0xee080100 0 0x100>;
1608 interrupts = <GIC_SPI 1608 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1609 clocks = <&cpg CPG_MO 1609 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
1610 phys = <&usb2_phy0 2> 1610 phys = <&usb2_phy0 2>;
1611 phy-names = "usb"; 1611 phy-names = "usb";
1612 companion = <&ohci0>; 1612 companion = <&ohci0>;
1613 power-domains = <&sys 1613 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1614 resets = <&cpg 703>, 1614 resets = <&cpg 703>, <&cpg 704>;
1615 status = "disabled"; 1615 status = "disabled";
1616 }; 1616 };
1617 1617
1618 usb2_phy0: usb-phy@ee080200 { 1618 usb2_phy0: usb-phy@ee080200 {
1619 compatible = "renesas 1619 compatible = "renesas,usb2-phy-r8a774c0",
1620 "renesas 1620 "renesas,rcar-gen3-usb2-phy";
1621 reg = <0 0xee080200 0 1621 reg = <0 0xee080200 0 0x700>;
1622 interrupts = <GIC_SPI 1622 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1623 clocks = <&cpg CPG_MO 1623 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
1624 power-domains = <&sys 1624 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1625 resets = <&cpg 703>, 1625 resets = <&cpg 703>, <&cpg 704>;
1626 #phy-cells = <1>; 1626 #phy-cells = <1>;
1627 status = "disabled"; 1627 status = "disabled";
1628 }; 1628 };
1629 1629
1630 sdhi0: mmc@ee100000 { 1630 sdhi0: mmc@ee100000 {
1631 compatible = "renesas 1631 compatible = "renesas,sdhi-r8a774c0",
1632 "renesas 1632 "renesas,rcar-gen3-sdhi";
1633 reg = <0 0xee100000 0 1633 reg = <0 0xee100000 0 0x2000>;
1634 interrupts = <GIC_SPI 1634 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
1635 clocks = <&cpg CPG_MO 1635 clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A774C0_CLK_SD0H>;
1636 clock-names = "core", 1636 clock-names = "core", "clkh";
1637 max-frequency = <2000 1637 max-frequency = <200000000>;
1638 power-domains = <&sys 1638 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1639 resets = <&cpg 314>; 1639 resets = <&cpg 314>;
1640 iommus = <&ipmmu_ds1 1640 iommus = <&ipmmu_ds1 32>;
1641 status = "disabled"; 1641 status = "disabled";
1642 }; 1642 };
1643 1643
1644 sdhi1: mmc@ee120000 { 1644 sdhi1: mmc@ee120000 {
1645 compatible = "renesas 1645 compatible = "renesas,sdhi-r8a774c0",
1646 "renesas 1646 "renesas,rcar-gen3-sdhi";
1647 reg = <0 0xee120000 0 1647 reg = <0 0xee120000 0 0x2000>;
1648 interrupts = <GIC_SPI 1648 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
1649 clocks = <&cpg CPG_MO 1649 clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A774C0_CLK_SD1H>;
1650 clock-names = "core", 1650 clock-names = "core", "clkh";
1651 max-frequency = <2000 1651 max-frequency = <200000000>;
1652 power-domains = <&sys 1652 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1653 resets = <&cpg 313>; 1653 resets = <&cpg 313>;
1654 iommus = <&ipmmu_ds1 1654 iommus = <&ipmmu_ds1 33>;
1655 status = "disabled"; 1655 status = "disabled";
1656 }; 1656 };
1657 1657
1658 sdhi3: mmc@ee160000 { 1658 sdhi3: mmc@ee160000 {
1659 compatible = "renesas 1659 compatible = "renesas,sdhi-r8a774c0",
1660 "renesas 1660 "renesas,rcar-gen3-sdhi";
1661 reg = <0 0xee160000 0 1661 reg = <0 0xee160000 0 0x2000>;
1662 interrupts = <GIC_SPI 1662 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
1663 clocks = <&cpg CPG_MO 1663 clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A774C0_CLK_SD3H>;
1664 clock-names = "core", 1664 clock-names = "core", "clkh";
1665 max-frequency = <2000 1665 max-frequency = <200000000>;
1666 power-domains = <&sys 1666 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1667 resets = <&cpg 311>; 1667 resets = <&cpg 311>;
1668 iommus = <&ipmmu_ds1 1668 iommus = <&ipmmu_ds1 35>;
1669 status = "disabled"; 1669 status = "disabled";
1670 }; 1670 };
1671 1671
1672 rpc: spi@ee200000 { 1672 rpc: spi@ee200000 {
1673 compatible = "renesas 1673 compatible = "renesas,r8a774c0-rpc-if",
1674 "renesas 1674 "renesas,rcar-gen3-rpc-if";
1675 reg = <0 0xee200000 0 1675 reg = <0 0xee200000 0 0x200>,
1676 <0 0x08000000 0 1676 <0 0x08000000 0 0x4000000>,
1677 <0 0xee208000 0 1677 <0 0xee208000 0 0x100>;
1678 reg-names = "regs", " 1678 reg-names = "regs", "dirmap", "wbuf";
1679 interrupts = <GIC_SPI 1679 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
1680 clocks = <&cpg CPG_MO 1680 clocks = <&cpg CPG_MOD 917>;
1681 power-domains = <&sys 1681 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1682 resets = <&cpg 917>; 1682 resets = <&cpg 917>;
1683 #address-cells = <1>; 1683 #address-cells = <1>;
1684 #size-cells = <0>; 1684 #size-cells = <0>;
1685 status = "disabled"; 1685 status = "disabled";
1686 }; 1686 };
1687 1687
1688 gic: interrupt-controller@f10 1688 gic: interrupt-controller@f1010000 {
1689 compatible = "arm,gic 1689 compatible = "arm,gic-400";
1690 #interrupt-cells = <3 1690 #interrupt-cells = <3>;
1691 #address-cells = <0>; 1691 #address-cells = <0>;
1692 interrupt-controller; 1692 interrupt-controller;
1693 reg = <0x0 0xf1010000 1693 reg = <0x0 0xf1010000 0 0x1000>,
1694 <0x0 0xf1020000 1694 <0x0 0xf1020000 0 0x20000>,
1695 <0x0 0xf1040000 1695 <0x0 0xf1040000 0 0x20000>,
1696 <0x0 0xf1060000 1696 <0x0 0xf1060000 0 0x20000>;
1697 interrupts = <GIC_PPI 1697 interrupts = <GIC_PPI 9
1698 (GIC_ 1698 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
1699 clocks = <&cpg CPG_MO 1699 clocks = <&cpg CPG_MOD 408>;
1700 clock-names = "clk"; 1700 clock-names = "clk";
1701 power-domains = <&sys 1701 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1702 resets = <&cpg 408>; 1702 resets = <&cpg 408>;
1703 }; 1703 };
1704 1704
1705 pciec0: pcie@fe000000 { 1705 pciec0: pcie@fe000000 {
1706 compatible = "renesas 1706 compatible = "renesas,pcie-r8a774c0",
1707 "renesas 1707 "renesas,pcie-rcar-gen3";
1708 reg = <0 0xfe000000 0 1708 reg = <0 0xfe000000 0 0x80000>;
1709 #address-cells = <3>; 1709 #address-cells = <3>;
1710 #size-cells = <2>; 1710 #size-cells = <2>;
1711 bus-range = <0x00 0xf 1711 bus-range = <0x00 0xff>;
1712 device_type = "pci"; 1712 device_type = "pci";
1713 ranges = <0x01000000 1713 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
1714 <0x02000000 1714 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
1715 <0x02000000 1715 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
1716 <0x42000000 1716 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1717 /* Map all possible D 1717 /* Map all possible DDR/IOMMU as inbound ranges */
1718 dma-ranges = <0x42000 1718 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
1719 interrupts = <GIC_SPI 1719 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1720 <GIC_SPI 1720 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1721 <GIC_SPI 1721 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1722 #interrupt-cells = <1 1722 #interrupt-cells = <1>;
1723 interrupt-map-mask = 1723 interrupt-map-mask = <0 0 0 0>;
1724 interrupt-map = <0 0 1724 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1725 clocks = <&cpg CPG_MO 1725 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
1726 clock-names = "pcie", 1726 clock-names = "pcie", "pcie_bus";
1727 power-domains = <&sys 1727 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1728 resets = <&cpg 319>; 1728 resets = <&cpg 319>;
1729 iommu-map = <0 &ipmmu 1729 iommu-map = <0 &ipmmu_hc 0 1>;
1730 iommu-map-mask = <0>; 1730 iommu-map-mask = <0>;
1731 status = "disabled"; 1731 status = "disabled";
1732 }; 1732 };
1733 1733
1734 pciec0_ep: pcie-ep@fe000000 { 1734 pciec0_ep: pcie-ep@fe000000 {
1735 compatible = "renesas 1735 compatible = "renesas,r8a774c0-pcie-ep",
1736 "renesas 1736 "renesas,rcar-gen3-pcie-ep";
1737 reg = <0x0 0xfe000000 1737 reg = <0x0 0xfe000000 0 0x80000>,
1738 <0x0 0xfe100000 1738 <0x0 0xfe100000 0 0x100000>,
1739 <0x0 0xfe200000 1739 <0x0 0xfe200000 0 0x200000>,
1740 <0x0 0x30000000 1740 <0x0 0x30000000 0 0x8000000>,
1741 <0x0 0x38000000 1741 <0x0 0x38000000 0 0x8000000>;
1742 reg-names = "apb-base 1742 reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
1743 interrupts = <GIC_SPI 1743 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1744 <GIC_SPI 1744 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1745 <GIC_SPI 1745 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1746 clocks = <&cpg CPG_MO 1746 clocks = <&cpg CPG_MOD 319>;
1747 clock-names = "pcie"; 1747 clock-names = "pcie";
1748 resets = <&cpg 319>; 1748 resets = <&cpg 319>;
1749 power-domains = <&sys 1749 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1750 status = "disabled"; 1750 status = "disabled";
1751 }; 1751 };
1752 1752
1753 vspb0: vsp@fe960000 { 1753 vspb0: vsp@fe960000 {
1754 compatible = "renesas 1754 compatible = "renesas,vsp2";
1755 reg = <0 0xfe960000 0 1755 reg = <0 0xfe960000 0 0x8000>;
1756 interrupts = <GIC_SPI 1756 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
1757 clocks = <&cpg CPG_MO 1757 clocks = <&cpg CPG_MOD 626>;
1758 power-domains = <&sys 1758 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1759 resets = <&cpg 626>; 1759 resets = <&cpg 626>;
1760 renesas,fcp = <&fcpvb 1760 renesas,fcp = <&fcpvb0>;
1761 }; 1761 };
1762 1762
1763 vspd0: vsp@fea20000 { 1763 vspd0: vsp@fea20000 {
1764 compatible = "renesas 1764 compatible = "renesas,vsp2";
1765 reg = <0 0xfea20000 0 1765 reg = <0 0xfea20000 0 0x7000>;
1766 interrupts = <GIC_SPI 1766 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
1767 clocks = <&cpg CPG_MO 1767 clocks = <&cpg CPG_MOD 623>;
1768 power-domains = <&sys 1768 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1769 resets = <&cpg 623>; 1769 resets = <&cpg 623>;
1770 renesas,fcp = <&fcpvd 1770 renesas,fcp = <&fcpvd0>;
1771 }; 1771 };
1772 1772
1773 vspd1: vsp@fea28000 { 1773 vspd1: vsp@fea28000 {
1774 compatible = "renesas 1774 compatible = "renesas,vsp2";
1775 reg = <0 0xfea28000 0 1775 reg = <0 0xfea28000 0 0x7000>;
1776 interrupts = <GIC_SPI 1776 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
1777 clocks = <&cpg CPG_MO 1777 clocks = <&cpg CPG_MOD 622>;
1778 power-domains = <&sys 1778 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1779 resets = <&cpg 622>; 1779 resets = <&cpg 622>;
1780 renesas,fcp = <&fcpvd 1780 renesas,fcp = <&fcpvd1>;
1781 }; 1781 };
1782 1782
1783 vspi0: vsp@fe9a0000 { 1783 vspi0: vsp@fe9a0000 {
1784 compatible = "renesas 1784 compatible = "renesas,vsp2";
1785 reg = <0 0xfe9a0000 0 1785 reg = <0 0xfe9a0000 0 0x8000>;
1786 interrupts = <GIC_SPI 1786 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
1787 clocks = <&cpg CPG_MO 1787 clocks = <&cpg CPG_MOD 631>;
1788 power-domains = <&sys 1788 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1789 resets = <&cpg 631>; 1789 resets = <&cpg 631>;
1790 renesas,fcp = <&fcpvi 1790 renesas,fcp = <&fcpvi0>;
1791 }; 1791 };
1792 1792
1793 fcpvb0: fcp@fe96f000 { 1793 fcpvb0: fcp@fe96f000 {
1794 compatible = "renesas 1794 compatible = "renesas,fcpv";
1795 reg = <0 0xfe96f000 0 1795 reg = <0 0xfe96f000 0 0x200>;
1796 clocks = <&cpg CPG_MO 1796 clocks = <&cpg CPG_MOD 607>;
1797 power-domains = <&sys 1797 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1798 resets = <&cpg 607>; 1798 resets = <&cpg 607>;
1799 iommus = <&ipmmu_vp0 1799 iommus = <&ipmmu_vp0 5>;
1800 }; 1800 };
1801 1801
1802 fcpvd0: fcp@fea27000 { 1802 fcpvd0: fcp@fea27000 {
1803 compatible = "renesas 1803 compatible = "renesas,fcpv";
1804 reg = <0 0xfea27000 0 1804 reg = <0 0xfea27000 0 0x200>;
1805 clocks = <&cpg CPG_MO 1805 clocks = <&cpg CPG_MOD 603>;
1806 power-domains = <&sys 1806 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1807 resets = <&cpg 603>; 1807 resets = <&cpg 603>;
1808 iommus = <&ipmmu_vi0 1808 iommus = <&ipmmu_vi0 8>;
1809 }; 1809 };
1810 1810
1811 fcpvd1: fcp@fea2f000 { 1811 fcpvd1: fcp@fea2f000 {
1812 compatible = "renesas 1812 compatible = "renesas,fcpv";
1813 reg = <0 0xfea2f000 0 1813 reg = <0 0xfea2f000 0 0x200>;
1814 clocks = <&cpg CPG_MO 1814 clocks = <&cpg CPG_MOD 602>;
1815 power-domains = <&sys 1815 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1816 resets = <&cpg 602>; 1816 resets = <&cpg 602>;
1817 iommus = <&ipmmu_vi0 1817 iommus = <&ipmmu_vi0 9>;
1818 }; 1818 };
1819 1819
1820 fcpvi0: fcp@fe9af000 { 1820 fcpvi0: fcp@fe9af000 {
1821 compatible = "renesas 1821 compatible = "renesas,fcpv";
1822 reg = <0 0xfe9af000 0 1822 reg = <0 0xfe9af000 0 0x200>;
1823 clocks = <&cpg CPG_MO 1823 clocks = <&cpg CPG_MOD 611>;
1824 power-domains = <&sys 1824 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1825 resets = <&cpg 611>; 1825 resets = <&cpg 611>;
1826 iommus = <&ipmmu_vp0 1826 iommus = <&ipmmu_vp0 8>;
1827 }; 1827 };
1828 1828
1829 csi40: csi2@feaa0000 { 1829 csi40: csi2@feaa0000 {
1830 compatible = "renesas 1830 compatible = "renesas,r8a774c0-csi2";
1831 reg = <0 0xfeaa0000 0 1831 reg = <0 0xfeaa0000 0 0x10000>;
1832 interrupts = <GIC_SPI 1832 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
1833 clocks = <&cpg CPG_MO 1833 clocks = <&cpg CPG_MOD 716>;
1834 power-domains = <&sys 1834 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1835 resets = <&cpg 716>; 1835 resets = <&cpg 716>;
1836 status = "disabled"; 1836 status = "disabled";
1837 1837
1838 ports { 1838 ports {
1839 #address-cell 1839 #address-cells = <1>;
1840 #size-cells = 1840 #size-cells = <0>;
1841 1841
1842 port@0 { 1842 port@0 {
1843 reg = 1843 reg = <0>;
1844 }; 1844 };
1845 1845
1846 port@1 { 1846 port@1 {
1847 #addr 1847 #address-cells = <1>;
1848 #size 1848 #size-cells = <0>;
1849 1849
1850 reg = 1850 reg = <1>;
1851 1851
1852 csi40 1852 csi40vin4: endpoint@0 {
1853 1853 reg = <0>;
1854 1854 remote-endpoint = <&vin4csi40>;
1855 }; 1855 };
1856 csi40 1856 csi40vin5: endpoint@1 {
1857 1857 reg = <1>;
1858 1858 remote-endpoint = <&vin5csi40>;
1859 }; 1859 };
1860 }; 1860 };
1861 }; 1861 };
1862 }; 1862 };
1863 1863
1864 du: display@feb00000 { 1864 du: display@feb00000 {
1865 compatible = "renesas 1865 compatible = "renesas,du-r8a774c0";
1866 reg = <0 0xfeb00000 0 1866 reg = <0 0xfeb00000 0 0x40000>;
1867 interrupts = <GIC_SPI 1867 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
1868 <GIC_SPI 1868 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
1869 clocks = <&cpg CPG_MO 1869 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
1870 clock-names = "du.0", 1870 clock-names = "du.0", "du.1";
1871 resets = <&cpg 724>; 1871 resets = <&cpg 724>;
1872 reset-names = "du.0"; 1872 reset-names = "du.0";
1873 renesas,vsps = <&vspd 1873 renesas,vsps = <&vspd0 0>, <&vspd1 0>;
1874 1874
1875 status = "disabled"; 1875 status = "disabled";
1876 1876
1877 ports { 1877 ports {
1878 #address-cell 1878 #address-cells = <1>;
1879 #size-cells = 1879 #size-cells = <0>;
1880 1880
1881 port@0 { 1881 port@0 {
1882 reg = 1882 reg = <0>;
1883 }; 1883 };
1884 1884
1885 port@1 { 1885 port@1 {
1886 reg = 1886 reg = <1>;
1887 du_ou 1887 du_out_lvds0: endpoint {
1888 1888 remote-endpoint = <&lvds0_in>;
1889 }; 1889 };
1890 }; 1890 };
1891 1891
1892 port@2 { 1892 port@2 {
1893 reg = 1893 reg = <2>;
1894 du_ou 1894 du_out_lvds1: endpoint {
1895 1895 remote-endpoint = <&lvds1_in>;
1896 }; 1896 };
1897 }; 1897 };
1898 }; 1898 };
1899 }; 1899 };
1900 1900
1901 lvds0: lvds-encoder@feb90000 1901 lvds0: lvds-encoder@feb90000 {
1902 compatible = "renesas 1902 compatible = "renesas,r8a774c0-lvds";
1903 reg = <0 0xfeb90000 0 1903 reg = <0 0xfeb90000 0 0x20>;
1904 clocks = <&cpg CPG_MO 1904 clocks = <&cpg CPG_MOD 727>;
1905 power-domains = <&sys 1905 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1906 resets = <&cpg 727>; 1906 resets = <&cpg 727>;
1907 status = "disabled"; 1907 status = "disabled";
1908 1908
1909 renesas,companion = < 1909 renesas,companion = <&lvds1>;
1910 1910
1911 ports { 1911 ports {
1912 #address-cell 1912 #address-cells = <1>;
1913 #size-cells = 1913 #size-cells = <0>;
1914 1914
1915 port@0 { 1915 port@0 {
1916 reg = 1916 reg = <0>;
1917 lvds0 1917 lvds0_in: endpoint {
1918 1918 remote-endpoint = <&du_out_lvds0>;
1919 }; 1919 };
1920 }; 1920 };
1921 1921
1922 port@1 { 1922 port@1 {
1923 reg = 1923 reg = <1>;
1924 }; 1924 };
1925 }; 1925 };
1926 }; 1926 };
1927 1927
1928 lvds1: lvds-encoder@feb90100 1928 lvds1: lvds-encoder@feb90100 {
1929 compatible = "renesas 1929 compatible = "renesas,r8a774c0-lvds";
1930 reg = <0 0xfeb90100 0 1930 reg = <0 0xfeb90100 0 0x20>;
1931 clocks = <&cpg CPG_MO 1931 clocks = <&cpg CPG_MOD 727>;
1932 power-domains = <&sys 1932 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1933 resets = <&cpg 726>; 1933 resets = <&cpg 726>;
1934 status = "disabled"; 1934 status = "disabled";
1935 1935
1936 ports { 1936 ports {
1937 #address-cell 1937 #address-cells = <1>;
1938 #size-cells = 1938 #size-cells = <0>;
1939 1939
1940 port@0 { 1940 port@0 {
1941 reg = 1941 reg = <0>;
1942 lvds1 1942 lvds1_in: endpoint {
1943 1943 remote-endpoint = <&du_out_lvds1>;
1944 }; 1944 };
1945 }; 1945 };
1946 1946
1947 port@1 { 1947 port@1 {
1948 reg = 1948 reg = <1>;
1949 }; 1949 };
1950 }; 1950 };
1951 }; 1951 };
1952 1952
1953 prr: chipid@fff00044 { 1953 prr: chipid@fff00044 {
1954 compatible = "renesas 1954 compatible = "renesas,prr";
1955 reg = <0 0xfff00044 0 1955 reg = <0 0xfff00044 0 4>;
1956 }; 1956 };
1957 }; 1957 };
1958 1958
1959 thermal-zones { 1959 thermal-zones {
1960 cpu-thermal { 1960 cpu-thermal {
1961 polling-delay-passive 1961 polling-delay-passive = <250>;
1962 polling-delay = <0>; 1962 polling-delay = <0>;
1963 thermal-sensors = <&t 1963 thermal-sensors = <&thermal>;
1964 sustainable-power = < 1964 sustainable-power = <717>;
1965 1965
1966 cooling-maps { 1966 cooling-maps {
1967 map0 { 1967 map0 {
1968 trip 1968 trip = <&target>;
1969 cooli 1969 cooling-device = <&a53_0 0 2>;
1970 contr 1970 contribution = <1024>;
1971 }; 1971 };
1972 }; 1972 };
1973 1973
1974 trips { 1974 trips {
1975 sensor1_crit: 1975 sensor1_crit: sensor1-crit {
1976 tempe 1976 temperature = <120000>;
1977 hyste 1977 hysteresis = <2000>;
1978 type 1978 type = "critical";
1979 }; 1979 };
1980 1980
1981 target: trip- 1981 target: trip-point1 {
1982 tempe 1982 temperature = <100000>;
1983 hyste 1983 hysteresis = <2000>;
1984 type 1984 type = "passive";
1985 }; 1985 };
1986 }; 1986 };
1987 }; 1987 };
1988 }; 1988 };
1989 1989
1990 timer { 1990 timer {
1991 compatible = "arm,armv8-timer 1991 compatible = "arm,armv8-timer";
1992 interrupts-extended = <&gic G 1992 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1993 <&gic G 1993 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1994 <&gic G 1994 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1995 <&gic G 1995 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
1996 interrupt-names = "sec-phys", 1996 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys";
1997 }; 1997 };
1998 1998
1999 /* External USB clocks - can be overr 1999 /* External USB clocks - can be overridden by the board */
2000 usb3s0_clk: usb3s0 { 2000 usb3s0_clk: usb3s0 {
2001 compatible = "fixed-clock"; 2001 compatible = "fixed-clock";
2002 #clock-cells = <0>; 2002 #clock-cells = <0>;
2003 clock-frequency = <0>; 2003 clock-frequency = <0>;
2004 }; 2004 };
2005 2005
2006 usb_extal_clk: usb_extal { 2006 usb_extal_clk: usb_extal {
2007 compatible = "fixed-clock"; 2007 compatible = "fixed-clock";
2008 #clock-cells = <0>; 2008 #clock-cells = <0>;
2009 clock-frequency = <0>; 2009 clock-frequency = <0>;
2010 }; 2010 };
2011 }; 2011 };
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