1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * Device Tree Source for the RZ/G2E (R8A774C0 3 * Device Tree Source for the RZ/G2E (R8A774C0) SoC
4 * 4 *
5 * Copyright (C) 2018-2019 Renesas Electronics 5 * Copyright (C) 2018-2019 Renesas Electronics Corp.
6 */ 6 */
7 7
8 #include <dt-bindings/clock/r8a774c0-cpg-mssr. 8 #include <dt-bindings/clock/r8a774c0-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm 9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a774c0-sysc.h> 10 #include <dt-bindings/power/r8a774c0-sysc.h>
11 11
12 / { 12 / {
13 compatible = "renesas,r8a774c0"; 13 compatible = "renesas,r8a774c0";
14 #address-cells = <2>; 14 #address-cells = <2>;
15 #size-cells = <2>; 15 #size-cells = <2>;
16 16
17 /* 17 /*
18 * The external audio clocks are confi 18 * The external audio clocks are configured as 0 Hz fixed frequency
19 * clocks by default. 19 * clocks by default.
20 * Boards that provide audio clocks sh 20 * Boards that provide audio clocks should override them.
21 */ 21 */
22 audio_clk_a: audio_clk_a { 22 audio_clk_a: audio_clk_a {
23 compatible = "fixed-clock"; 23 compatible = "fixed-clock";
24 #clock-cells = <0>; 24 #clock-cells = <0>;
25 clock-frequency = <0>; 25 clock-frequency = <0>;
26 }; 26 };
27 27
28 audio_clk_b: audio_clk_b { 28 audio_clk_b: audio_clk_b {
29 compatible = "fixed-clock"; 29 compatible = "fixed-clock";
30 #clock-cells = <0>; 30 #clock-cells = <0>;
31 clock-frequency = <0>; 31 clock-frequency = <0>;
32 }; 32 };
33 33
34 audio_clk_c: audio_clk_c { 34 audio_clk_c: audio_clk_c {
35 compatible = "fixed-clock"; 35 compatible = "fixed-clock";
36 #clock-cells = <0>; 36 #clock-cells = <0>;
37 clock-frequency = <0>; 37 clock-frequency = <0>;
38 }; 38 };
39 39
40 /* External CAN clock - to be overridd 40 /* External CAN clock - to be overridden by boards that provide it */
41 can_clk: can { 41 can_clk: can {
42 compatible = "fixed-clock"; 42 compatible = "fixed-clock";
43 #clock-cells = <0>; 43 #clock-cells = <0>;
44 clock-frequency = <0>; 44 clock-frequency = <0>;
45 }; 45 };
46 46
47 cluster1_opp: opp-table-1 { !! 47 cluster1_opp: opp_table10 {
48 compatible = "operating-points 48 compatible = "operating-points-v2";
49 opp-shared; 49 opp-shared;
50 opp-800000000 { 50 opp-800000000 {
51 opp-hz = /bits/ 64 <80 51 opp-hz = /bits/ 64 <800000000>;
>> 52 opp-microvolt = <820000>;
52 clock-latency-ns = <30 53 clock-latency-ns = <300000>;
53 }; 54 };
54 opp-1000000000 { 55 opp-1000000000 {
55 opp-hz = /bits/ 64 <10 56 opp-hz = /bits/ 64 <1000000000>;
>> 57 opp-microvolt = <820000>;
56 clock-latency-ns = <30 58 clock-latency-ns = <300000>;
57 }; 59 };
58 opp-1200000000 { 60 opp-1200000000 {
59 opp-hz = /bits/ 64 <12 61 opp-hz = /bits/ 64 <1200000000>;
>> 62 opp-microvolt = <820000>;
60 clock-latency-ns = <30 63 clock-latency-ns = <300000>;
61 opp-suspend; 64 opp-suspend;
62 }; 65 };
63 }; 66 };
64 67
65 cpus { 68 cpus {
66 #address-cells = <1>; 69 #address-cells = <1>;
67 #size-cells = <0>; 70 #size-cells = <0>;
68 71
69 a53_0: cpu@0 { 72 a53_0: cpu@0 {
70 compatible = "arm,cort 73 compatible = "arm,cortex-a53";
71 reg = <0>; 74 reg = <0>;
72 device_type = "cpu"; 75 device_type = "cpu";
73 #cooling-cells = <2>; 76 #cooling-cells = <2>;
74 power-domains = <&sysc 77 power-domains = <&sysc R8A774C0_PD_CA53_CPU0>;
75 next-level-cache = <&L 78 next-level-cache = <&L2_CA53>;
76 enable-method = "psci" 79 enable-method = "psci";
77 dynamic-power-coeffici 80 dynamic-power-coefficient = <277>;
78 clocks = <&cpg CPG_COR 81 clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>;
79 operating-points-v2 = 82 operating-points-v2 = <&cluster1_opp>;
80 }; 83 };
81 84
82 a53_1: cpu@1 { 85 a53_1: cpu@1 {
83 compatible = "arm,cort 86 compatible = "arm,cortex-a53";
84 reg = <1>; 87 reg = <1>;
85 device_type = "cpu"; 88 device_type = "cpu";
86 power-domains = <&sysc 89 power-domains = <&sysc R8A774C0_PD_CA53_CPU1>;
87 next-level-cache = <&L 90 next-level-cache = <&L2_CA53>;
88 enable-method = "psci" 91 enable-method = "psci";
89 clocks = <&cpg CPG_COR 92 clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>;
90 operating-points-v2 = 93 operating-points-v2 = <&cluster1_opp>;
91 }; 94 };
92 95
93 L2_CA53: cache-controller-0 { 96 L2_CA53: cache-controller-0 {
94 compatible = "cache"; 97 compatible = "cache";
95 power-domains = <&sysc 98 power-domains = <&sysc R8A774C0_PD_CA53_SCU>;
96 cache-unified; 99 cache-unified;
97 cache-level = <2>; 100 cache-level = <2>;
98 }; 101 };
99 }; 102 };
100 103
101 extal_clk: extal { 104 extal_clk: extal {
102 compatible = "fixed-clock"; 105 compatible = "fixed-clock";
103 #clock-cells = <0>; 106 #clock-cells = <0>;
104 /* This value must be overridd 107 /* This value must be overridden by the board */
105 clock-frequency = <0>; 108 clock-frequency = <0>;
106 }; 109 };
107 110
108 /* External PCIe clock - can be overri 111 /* External PCIe clock - can be overridden by the board */
109 pcie_bus_clk: pcie_bus { 112 pcie_bus_clk: pcie_bus {
110 compatible = "fixed-clock"; 113 compatible = "fixed-clock";
111 #clock-cells = <0>; 114 #clock-cells = <0>;
112 clock-frequency = <0>; 115 clock-frequency = <0>;
113 }; 116 };
114 117
115 pmu_a53 { 118 pmu_a53 {
116 compatible = "arm,cortex-a53-p 119 compatible = "arm,cortex-a53-pmu";
117 interrupts-extended = <&gic GI 120 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
118 <&gic GI 121 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
119 interrupt-affinity = <&a53_0>, 122 interrupt-affinity = <&a53_0>, <&a53_1>;
120 }; 123 };
121 124
122 psci { 125 psci {
123 compatible = "arm,psci-1.0", " 126 compatible = "arm,psci-1.0", "arm,psci-0.2";
124 method = "smc"; 127 method = "smc";
125 }; 128 };
126 129
127 /* External SCIF clock - to be overrid 130 /* External SCIF clock - to be overridden by boards that provide it */
128 scif_clk: scif { 131 scif_clk: scif {
129 compatible = "fixed-clock"; 132 compatible = "fixed-clock";
130 #clock-cells = <0>; 133 #clock-cells = <0>;
131 clock-frequency = <0>; 134 clock-frequency = <0>;
132 }; 135 };
133 136
134 soc: soc { 137 soc: soc {
135 compatible = "simple-bus"; 138 compatible = "simple-bus";
136 interrupt-parent = <&gic>; 139 interrupt-parent = <&gic>;
137 #address-cells = <2>; 140 #address-cells = <2>;
138 #size-cells = <2>; 141 #size-cells = <2>;
139 ranges; 142 ranges;
140 143
141 rwdt: watchdog@e6020000 { 144 rwdt: watchdog@e6020000 {
142 compatible = "renesas, 145 compatible = "renesas,r8a774c0-wdt",
143 "renesas, 146 "renesas,rcar-gen3-wdt";
144 reg = <0 0xe6020000 0 147 reg = <0 0xe6020000 0 0x0c>;
145 interrupts = <GIC_SPI <<
146 clocks = <&cpg CPG_MOD 148 clocks = <&cpg CPG_MOD 402>;
147 power-domains = <&sysc 149 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
148 resets = <&cpg 402>; 150 resets = <&cpg 402>;
149 status = "disabled"; 151 status = "disabled";
150 }; 152 };
151 153
152 gpio0: gpio@e6050000 { 154 gpio0: gpio@e6050000 {
153 compatible = "renesas, 155 compatible = "renesas,gpio-r8a774c0",
154 "renesas, 156 "renesas,rcar-gen3-gpio";
155 reg = <0 0xe6050000 0 157 reg = <0 0xe6050000 0 0x50>;
156 interrupts = <GIC_SPI 158 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
157 #gpio-cells = <2>; 159 #gpio-cells = <2>;
158 gpio-controller; 160 gpio-controller;
159 gpio-ranges = <&pfc 0 161 gpio-ranges = <&pfc 0 0 18>;
160 #interrupt-cells = <2> 162 #interrupt-cells = <2>;
161 interrupt-controller; 163 interrupt-controller;
162 clocks = <&cpg CPG_MOD 164 clocks = <&cpg CPG_MOD 912>;
163 power-domains = <&sysc 165 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
164 resets = <&cpg 912>; 166 resets = <&cpg 912>;
165 }; 167 };
166 168
167 gpio1: gpio@e6051000 { 169 gpio1: gpio@e6051000 {
168 compatible = "renesas, 170 compatible = "renesas,gpio-r8a774c0",
169 "renesas, 171 "renesas,rcar-gen3-gpio";
170 reg = <0 0xe6051000 0 172 reg = <0 0xe6051000 0 0x50>;
171 interrupts = <GIC_SPI 173 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
172 #gpio-cells = <2>; 174 #gpio-cells = <2>;
173 gpio-controller; 175 gpio-controller;
174 gpio-ranges = <&pfc 0 176 gpio-ranges = <&pfc 0 32 23>;
175 #interrupt-cells = <2> 177 #interrupt-cells = <2>;
176 interrupt-controller; 178 interrupt-controller;
177 clocks = <&cpg CPG_MOD 179 clocks = <&cpg CPG_MOD 911>;
178 power-domains = <&sysc 180 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
179 resets = <&cpg 911>; 181 resets = <&cpg 911>;
180 }; 182 };
181 183
182 gpio2: gpio@e6052000 { 184 gpio2: gpio@e6052000 {
183 compatible = "renesas, 185 compatible = "renesas,gpio-r8a774c0",
184 "renesas, 186 "renesas,rcar-gen3-gpio";
185 reg = <0 0xe6052000 0 187 reg = <0 0xe6052000 0 0x50>;
186 interrupts = <GIC_SPI 188 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
187 #gpio-cells = <2>; 189 #gpio-cells = <2>;
188 gpio-controller; 190 gpio-controller;
189 gpio-ranges = <&pfc 0 191 gpio-ranges = <&pfc 0 64 26>;
190 #interrupt-cells = <2> 192 #interrupt-cells = <2>;
191 interrupt-controller; 193 interrupt-controller;
192 clocks = <&cpg CPG_MOD 194 clocks = <&cpg CPG_MOD 910>;
193 power-domains = <&sysc 195 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
194 resets = <&cpg 910>; 196 resets = <&cpg 910>;
195 }; 197 };
196 198
197 gpio3: gpio@e6053000 { 199 gpio3: gpio@e6053000 {
198 compatible = "renesas, 200 compatible = "renesas,gpio-r8a774c0",
199 "renesas, 201 "renesas,rcar-gen3-gpio";
200 reg = <0 0xe6053000 0 202 reg = <0 0xe6053000 0 0x50>;
201 interrupts = <GIC_SPI 203 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
202 #gpio-cells = <2>; 204 #gpio-cells = <2>;
203 gpio-controller; 205 gpio-controller;
204 gpio-ranges = <&pfc 0 206 gpio-ranges = <&pfc 0 96 16>;
205 #interrupt-cells = <2> 207 #interrupt-cells = <2>;
206 interrupt-controller; 208 interrupt-controller;
207 clocks = <&cpg CPG_MOD 209 clocks = <&cpg CPG_MOD 909>;
208 power-domains = <&sysc 210 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
209 resets = <&cpg 909>; 211 resets = <&cpg 909>;
210 }; 212 };
211 213
212 gpio4: gpio@e6054000 { 214 gpio4: gpio@e6054000 {
213 compatible = "renesas, 215 compatible = "renesas,gpio-r8a774c0",
214 "renesas, 216 "renesas,rcar-gen3-gpio";
215 reg = <0 0xe6054000 0 217 reg = <0 0xe6054000 0 0x50>;
216 interrupts = <GIC_SPI 218 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
217 #gpio-cells = <2>; 219 #gpio-cells = <2>;
218 gpio-controller; 220 gpio-controller;
219 gpio-ranges = <&pfc 0 221 gpio-ranges = <&pfc 0 128 11>;
220 #interrupt-cells = <2> 222 #interrupt-cells = <2>;
221 interrupt-controller; 223 interrupt-controller;
222 clocks = <&cpg CPG_MOD 224 clocks = <&cpg CPG_MOD 908>;
223 power-domains = <&sysc 225 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
224 resets = <&cpg 908>; 226 resets = <&cpg 908>;
225 }; 227 };
226 228
227 gpio5: gpio@e6055000 { 229 gpio5: gpio@e6055000 {
228 compatible = "renesas, 230 compatible = "renesas,gpio-r8a774c0",
229 "renesas, 231 "renesas,rcar-gen3-gpio";
230 reg = <0 0xe6055000 0 232 reg = <0 0xe6055000 0 0x50>;
231 interrupts = <GIC_SPI 233 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
232 #gpio-cells = <2>; 234 #gpio-cells = <2>;
233 gpio-controller; 235 gpio-controller;
234 gpio-ranges = <&pfc 0 236 gpio-ranges = <&pfc 0 160 20>;
235 #interrupt-cells = <2> 237 #interrupt-cells = <2>;
236 interrupt-controller; 238 interrupt-controller;
237 clocks = <&cpg CPG_MOD 239 clocks = <&cpg CPG_MOD 907>;
238 power-domains = <&sysc 240 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
239 resets = <&cpg 907>; 241 resets = <&cpg 907>;
240 }; 242 };
241 243
242 gpio6: gpio@e6055400 { 244 gpio6: gpio@e6055400 {
243 compatible = "renesas, 245 compatible = "renesas,gpio-r8a774c0",
244 "renesas, 246 "renesas,rcar-gen3-gpio";
245 reg = <0 0xe6055400 0 247 reg = <0 0xe6055400 0 0x50>;
246 interrupts = <GIC_SPI 248 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
247 #gpio-cells = <2>; 249 #gpio-cells = <2>;
248 gpio-controller; 250 gpio-controller;
249 gpio-ranges = <&pfc 0 251 gpio-ranges = <&pfc 0 192 18>;
250 #interrupt-cells = <2> 252 #interrupt-cells = <2>;
251 interrupt-controller; 253 interrupt-controller;
252 clocks = <&cpg CPG_MOD 254 clocks = <&cpg CPG_MOD 906>;
253 power-domains = <&sysc 255 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
254 resets = <&cpg 906>; 256 resets = <&cpg 906>;
255 }; 257 };
256 258
257 pfc: pinctrl@e6060000 { 259 pfc: pinctrl@e6060000 {
258 compatible = "renesas, 260 compatible = "renesas,pfc-r8a774c0";
259 reg = <0 0xe6060000 0 261 reg = <0 0xe6060000 0 0x508>;
260 }; 262 };
261 263
262 cmt0: timer@e60f0000 { 264 cmt0: timer@e60f0000 {
263 compatible = "renesas, 265 compatible = "renesas,r8a774c0-cmt0",
264 "renesas, 266 "renesas,rcar-gen3-cmt0";
265 reg = <0 0xe60f0000 0 267 reg = <0 0xe60f0000 0 0x1004>;
266 interrupts = <GIC_SPI 268 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
267 <GIC_SPI 269 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
268 clocks = <&cpg CPG_MOD 270 clocks = <&cpg CPG_MOD 303>;
269 clock-names = "fck"; 271 clock-names = "fck";
270 power-domains = <&sysc 272 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
271 resets = <&cpg 303>; 273 resets = <&cpg 303>;
272 status = "disabled"; 274 status = "disabled";
273 }; 275 };
274 276
275 cmt1: timer@e6130000 { 277 cmt1: timer@e6130000 {
276 compatible = "renesas, 278 compatible = "renesas,r8a774c0-cmt1",
277 "renesas, 279 "renesas,rcar-gen3-cmt1";
278 reg = <0 0xe6130000 0 280 reg = <0 0xe6130000 0 0x1004>;
279 interrupts = <GIC_SPI 281 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
280 <GIC_SPI 282 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
281 <GIC_SPI 283 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
282 <GIC_SPI 284 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
283 <GIC_SPI 285 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
284 <GIC_SPI 286 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
285 <GIC_SPI 287 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
286 <GIC_SPI 288 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
287 clocks = <&cpg CPG_MOD 289 clocks = <&cpg CPG_MOD 302>;
288 clock-names = "fck"; 290 clock-names = "fck";
289 power-domains = <&sysc 291 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
290 resets = <&cpg 302>; 292 resets = <&cpg 302>;
291 status = "disabled"; 293 status = "disabled";
292 }; 294 };
293 295
294 cmt2: timer@e6140000 { 296 cmt2: timer@e6140000 {
295 compatible = "renesas, 297 compatible = "renesas,r8a774c0-cmt1",
296 "renesas, 298 "renesas,rcar-gen3-cmt1";
297 reg = <0 0xe6140000 0 299 reg = <0 0xe6140000 0 0x1004>;
298 interrupts = <GIC_SPI 300 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
299 <GIC_SPI 301 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
300 <GIC_SPI 302 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
301 <GIC_SPI 303 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
302 <GIC_SPI 304 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
303 <GIC_SPI 305 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
304 <GIC_SPI 306 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
305 <GIC_SPI 307 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
306 clocks = <&cpg CPG_MOD 308 clocks = <&cpg CPG_MOD 301>;
307 clock-names = "fck"; 309 clock-names = "fck";
308 power-domains = <&sysc 310 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
309 resets = <&cpg 301>; 311 resets = <&cpg 301>;
310 status = "disabled"; 312 status = "disabled";
311 }; 313 };
312 314
313 cmt3: timer@e6148000 { 315 cmt3: timer@e6148000 {
314 compatible = "renesas, 316 compatible = "renesas,r8a774c0-cmt1",
315 "renesas, 317 "renesas,rcar-gen3-cmt1";
316 reg = <0 0xe6148000 0 318 reg = <0 0xe6148000 0 0x1004>;
317 interrupts = <GIC_SPI 319 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
318 <GIC_SPI 320 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
319 <GIC_SPI 321 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
320 <GIC_SPI 322 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
321 <GIC_SPI 323 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
322 <GIC_SPI 324 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
323 <GIC_SPI 325 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
324 <GIC_SPI 326 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
325 clocks = <&cpg CPG_MOD 327 clocks = <&cpg CPG_MOD 300>;
326 clock-names = "fck"; 328 clock-names = "fck";
327 power-domains = <&sysc 329 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
328 resets = <&cpg 300>; 330 resets = <&cpg 300>;
329 status = "disabled"; 331 status = "disabled";
330 }; 332 };
331 333
332 cpg: clock-controller@e6150000 334 cpg: clock-controller@e6150000 {
333 compatible = "renesas, 335 compatible = "renesas,r8a774c0-cpg-mssr";
334 reg = <0 0xe6150000 0 336 reg = <0 0xe6150000 0 0x1000>;
335 clocks = <&extal_clk>; 337 clocks = <&extal_clk>;
336 clock-names = "extal"; 338 clock-names = "extal";
337 #clock-cells = <2>; 339 #clock-cells = <2>;
338 #power-domain-cells = 340 #power-domain-cells = <0>;
339 #reset-cells = <1>; 341 #reset-cells = <1>;
340 }; 342 };
341 343
342 rst: reset-controller@e6160000 344 rst: reset-controller@e6160000 {
343 compatible = "renesas, 345 compatible = "renesas,r8a774c0-rst";
344 reg = <0 0xe6160000 0 346 reg = <0 0xe6160000 0 0x0200>;
345 }; 347 };
346 348
347 sysc: system-controller@e61800 349 sysc: system-controller@e6180000 {
348 compatible = "renesas, 350 compatible = "renesas,r8a774c0-sysc";
349 reg = <0 0xe6180000 0 351 reg = <0 0xe6180000 0 0x0400>;
350 #power-domain-cells = 352 #power-domain-cells = <1>;
351 }; 353 };
352 354
353 thermal: thermal@e6190000 { 355 thermal: thermal@e6190000 {
354 compatible = "renesas, 356 compatible = "renesas,thermal-r8a774c0";
355 reg = <0 0xe6190000 0 357 reg = <0 0xe6190000 0 0x10>, <0 0xe6190100 0 0x38>;
356 interrupts = <GIC_SPI 358 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
357 <GIC_SPI 359 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
358 <GIC_SPI 360 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
359 clocks = <&cpg CPG_MOD 361 clocks = <&cpg CPG_MOD 522>;
360 power-domains = <&sysc 362 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
361 resets = <&cpg 522>; 363 resets = <&cpg 522>;
362 #thermal-sensor-cells 364 #thermal-sensor-cells = <0>;
363 }; 365 };
364 366
365 intc_ex: interrupt-controller@ 367 intc_ex: interrupt-controller@e61c0000 {
366 compatible = "renesas, 368 compatible = "renesas,intc-ex-r8a774c0", "renesas,irqc";
367 #interrupt-cells = <2> 369 #interrupt-cells = <2>;
368 interrupt-controller; 370 interrupt-controller;
369 reg = <0 0xe61c0000 0 371 reg = <0 0xe61c0000 0 0x200>;
370 interrupts = <GIC_SPI 372 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
371 <GIC_SPI 373 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
372 <GIC_SPI 374 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
373 <GIC_SPI 375 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
374 <GIC_SPI 376 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
375 <GIC_SPI 377 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
376 clocks = <&cpg CPG_MOD 378 clocks = <&cpg CPG_MOD 407>;
377 power-domains = <&sysc 379 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
378 resets = <&cpg 407>; 380 resets = <&cpg 407>;
379 }; 381 };
380 382
381 tmu0: timer@e61e0000 { 383 tmu0: timer@e61e0000 {
382 compatible = "renesas, 384 compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
383 reg = <0 0xe61e0000 0 385 reg = <0 0xe61e0000 0 0x30>;
384 interrupts = <GIC_SPI 386 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
385 <GIC_SPI 387 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
386 <GIC_SPI 388 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
387 interrupt-names = "tun <<
388 clocks = <&cpg CPG_MOD 389 clocks = <&cpg CPG_MOD 125>;
389 clock-names = "fck"; 390 clock-names = "fck";
390 power-domains = <&sysc 391 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
391 resets = <&cpg 125>; 392 resets = <&cpg 125>;
392 status = "disabled"; 393 status = "disabled";
393 }; 394 };
394 395
395 tmu1: timer@e6fc0000 { 396 tmu1: timer@e6fc0000 {
396 compatible = "renesas, 397 compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
397 reg = <0 0xe6fc0000 0 398 reg = <0 0xe6fc0000 0 0x30>;
398 interrupts = <GIC_SPI 399 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
399 <GIC_SPI 400 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
400 <GIC_SPI !! 401 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
401 <GIC_SPI <<
402 interrupt-names = "tun <<
403 clocks = <&cpg CPG_MOD 402 clocks = <&cpg CPG_MOD 124>;
404 clock-names = "fck"; 403 clock-names = "fck";
405 power-domains = <&sysc 404 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
406 resets = <&cpg 124>; 405 resets = <&cpg 124>;
407 status = "disabled"; 406 status = "disabled";
408 }; 407 };
409 408
410 tmu2: timer@e6fd0000 { 409 tmu2: timer@e6fd0000 {
411 compatible = "renesas, 410 compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
412 reg = <0 0xe6fd0000 0 411 reg = <0 0xe6fd0000 0 0x30>;
413 interrupts = <GIC_SPI 412 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
414 <GIC_SPI 413 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
415 <GIC_SPI !! 414 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
416 <GIC_SPI <<
417 interrupt-names = "tun <<
418 clocks = <&cpg CPG_MOD 415 clocks = <&cpg CPG_MOD 123>;
419 clock-names = "fck"; 416 clock-names = "fck";
420 power-domains = <&sysc 417 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
421 resets = <&cpg 123>; 418 resets = <&cpg 123>;
422 status = "disabled"; 419 status = "disabled";
423 }; 420 };
424 421
425 tmu3: timer@e6fe0000 { 422 tmu3: timer@e6fe0000 {
426 compatible = "renesas, 423 compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
427 reg = <0 0xe6fe0000 0 424 reg = <0 0xe6fe0000 0 0x30>;
428 interrupts = <GIC_SPI 425 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
429 <GIC_SPI 426 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
430 <GIC_SPI 427 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
431 interrupt-names = "tun <<
432 clocks = <&cpg CPG_MOD 428 clocks = <&cpg CPG_MOD 122>;
433 clock-names = "fck"; 429 clock-names = "fck";
434 power-domains = <&sysc 430 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
435 resets = <&cpg 122>; 431 resets = <&cpg 122>;
436 status = "disabled"; 432 status = "disabled";
437 }; 433 };
438 434
439 tmu4: timer@ffc00000 { 435 tmu4: timer@ffc00000 {
440 compatible = "renesas, 436 compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
441 reg = <0 0xffc00000 0 437 reg = <0 0xffc00000 0 0x30>;
442 interrupts = <GIC_SPI 438 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
443 <GIC_SPI 439 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
444 <GIC_SPI 440 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
445 interrupt-names = "tun <<
446 clocks = <&cpg CPG_MOD 441 clocks = <&cpg CPG_MOD 121>;
447 clock-names = "fck"; 442 clock-names = "fck";
448 power-domains = <&sysc 443 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
449 resets = <&cpg 121>; 444 resets = <&cpg 121>;
450 status = "disabled"; 445 status = "disabled";
451 }; 446 };
452 447
453 i2c0: i2c@e6500000 { 448 i2c0: i2c@e6500000 {
454 #address-cells = <1>; 449 #address-cells = <1>;
455 #size-cells = <0>; 450 #size-cells = <0>;
456 compatible = "renesas, 451 compatible = "renesas,i2c-r8a774c0",
457 "renesas, 452 "renesas,rcar-gen3-i2c";
458 reg = <0 0xe6500000 0 453 reg = <0 0xe6500000 0 0x40>;
459 interrupts = <GIC_SPI 454 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
460 clocks = <&cpg CPG_MOD 455 clocks = <&cpg CPG_MOD 931>;
461 power-domains = <&sysc 456 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
462 resets = <&cpg 931>; 457 resets = <&cpg 931>;
463 dmas = <&dmac1 0x91>, 458 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
464 <&dmac2 0x91>, 459 <&dmac2 0x91>, <&dmac2 0x90>;
465 dma-names = "tx", "rx" 460 dma-names = "tx", "rx", "tx", "rx";
466 i2c-scl-internal-delay 461 i2c-scl-internal-delay-ns = <110>;
467 status = "disabled"; 462 status = "disabled";
468 }; 463 };
469 464
470 i2c1: i2c@e6508000 { 465 i2c1: i2c@e6508000 {
471 #address-cells = <1>; 466 #address-cells = <1>;
472 #size-cells = <0>; 467 #size-cells = <0>;
473 compatible = "renesas, 468 compatible = "renesas,i2c-r8a774c0",
474 "renesas, 469 "renesas,rcar-gen3-i2c";
475 reg = <0 0xe6508000 0 470 reg = <0 0xe6508000 0 0x40>;
476 interrupts = <GIC_SPI 471 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
477 clocks = <&cpg CPG_MOD 472 clocks = <&cpg CPG_MOD 930>;
478 power-domains = <&sysc 473 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
479 resets = <&cpg 930>; 474 resets = <&cpg 930>;
480 dmas = <&dmac1 0x93>, 475 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
481 <&dmac2 0x93>, 476 <&dmac2 0x93>, <&dmac2 0x92>;
482 dma-names = "tx", "rx" 477 dma-names = "tx", "rx", "tx", "rx";
483 i2c-scl-internal-delay 478 i2c-scl-internal-delay-ns = <6>;
484 status = "disabled"; 479 status = "disabled";
485 }; 480 };
486 481
487 i2c2: i2c@e6510000 { 482 i2c2: i2c@e6510000 {
488 #address-cells = <1>; 483 #address-cells = <1>;
489 #size-cells = <0>; 484 #size-cells = <0>;
490 compatible = "renesas, 485 compatible = "renesas,i2c-r8a774c0",
491 "renesas, 486 "renesas,rcar-gen3-i2c";
492 reg = <0 0xe6510000 0 487 reg = <0 0xe6510000 0 0x40>;
493 interrupts = <GIC_SPI 488 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
494 clocks = <&cpg CPG_MOD 489 clocks = <&cpg CPG_MOD 929>;
495 power-domains = <&sysc 490 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
496 resets = <&cpg 929>; 491 resets = <&cpg 929>;
497 dmas = <&dmac1 0x95>, 492 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
498 <&dmac2 0x95>, 493 <&dmac2 0x95>, <&dmac2 0x94>;
499 dma-names = "tx", "rx" 494 dma-names = "tx", "rx", "tx", "rx";
500 i2c-scl-internal-delay 495 i2c-scl-internal-delay-ns = <6>;
501 status = "disabled"; 496 status = "disabled";
502 }; 497 };
503 498
504 i2c3: i2c@e66d0000 { 499 i2c3: i2c@e66d0000 {
505 #address-cells = <1>; 500 #address-cells = <1>;
506 #size-cells = <0>; 501 #size-cells = <0>;
507 compatible = "renesas, 502 compatible = "renesas,i2c-r8a774c0",
508 "renesas, 503 "renesas,rcar-gen3-i2c";
509 reg = <0 0xe66d0000 0 504 reg = <0 0xe66d0000 0 0x40>;
510 interrupts = <GIC_SPI 505 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
511 clocks = <&cpg CPG_MOD 506 clocks = <&cpg CPG_MOD 928>;
512 power-domains = <&sysc 507 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
513 resets = <&cpg 928>; 508 resets = <&cpg 928>;
514 dmas = <&dmac0 0x97>, 509 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
515 dma-names = "tx", "rx" 510 dma-names = "tx", "rx";
516 i2c-scl-internal-delay 511 i2c-scl-internal-delay-ns = <110>;
517 status = "disabled"; 512 status = "disabled";
518 }; 513 };
519 514
520 i2c4: i2c@e66d8000 { 515 i2c4: i2c@e66d8000 {
521 #address-cells = <1>; 516 #address-cells = <1>;
522 #size-cells = <0>; 517 #size-cells = <0>;
523 compatible = "renesas, 518 compatible = "renesas,i2c-r8a774c0",
524 "renesas, 519 "renesas,rcar-gen3-i2c";
525 reg = <0 0xe66d8000 0 520 reg = <0 0xe66d8000 0 0x40>;
526 interrupts = <GIC_SPI 521 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
527 clocks = <&cpg CPG_MOD 522 clocks = <&cpg CPG_MOD 927>;
528 power-domains = <&sysc 523 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
529 resets = <&cpg 927>; 524 resets = <&cpg 927>;
530 dmas = <&dmac0 0x99>, 525 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
531 dma-names = "tx", "rx" 526 dma-names = "tx", "rx";
532 i2c-scl-internal-delay 527 i2c-scl-internal-delay-ns = <6>;
533 status = "disabled"; 528 status = "disabled";
534 }; 529 };
535 530
536 i2c5: i2c@e66e0000 { 531 i2c5: i2c@e66e0000 {
537 #address-cells = <1>; 532 #address-cells = <1>;
538 #size-cells = <0>; 533 #size-cells = <0>;
539 compatible = "renesas, 534 compatible = "renesas,i2c-r8a774c0",
540 "renesas, 535 "renesas,rcar-gen3-i2c";
541 reg = <0 0xe66e0000 0 536 reg = <0 0xe66e0000 0 0x40>;
542 interrupts = <GIC_SPI 537 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
543 clocks = <&cpg CPG_MOD 538 clocks = <&cpg CPG_MOD 919>;
544 power-domains = <&sysc 539 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
545 resets = <&cpg 919>; 540 resets = <&cpg 919>;
546 dmas = <&dmac0 0x9b>, 541 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
547 dma-names = "tx", "rx" 542 dma-names = "tx", "rx";
548 i2c-scl-internal-delay 543 i2c-scl-internal-delay-ns = <6>;
549 status = "disabled"; 544 status = "disabled";
550 }; 545 };
551 546
552 i2c6: i2c@e66e8000 { 547 i2c6: i2c@e66e8000 {
553 #address-cells = <1>; 548 #address-cells = <1>;
554 #size-cells = <0>; 549 #size-cells = <0>;
555 compatible = "renesas, 550 compatible = "renesas,i2c-r8a774c0",
556 "renesas, 551 "renesas,rcar-gen3-i2c";
557 reg = <0 0xe66e8000 0 552 reg = <0 0xe66e8000 0 0x40>;
558 interrupts = <GIC_SPI 553 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
559 clocks = <&cpg CPG_MOD 554 clocks = <&cpg CPG_MOD 918>;
560 power-domains = <&sysc 555 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
561 resets = <&cpg 918>; 556 resets = <&cpg 918>;
562 dmas = <&dmac0 0x9d>, 557 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
563 dma-names = "tx", "rx" 558 dma-names = "tx", "rx";
564 i2c-scl-internal-delay 559 i2c-scl-internal-delay-ns = <6>;
565 status = "disabled"; 560 status = "disabled";
566 }; 561 };
567 562
568 i2c7: i2c@e6690000 { 563 i2c7: i2c@e6690000 {
569 #address-cells = <1>; 564 #address-cells = <1>;
570 #size-cells = <0>; 565 #size-cells = <0>;
571 compatible = "renesas, 566 compatible = "renesas,i2c-r8a774c0",
572 "renesas, 567 "renesas,rcar-gen3-i2c";
573 reg = <0 0xe6690000 0 568 reg = <0 0xe6690000 0 0x40>;
574 interrupts = <GIC_SPI 569 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
575 clocks = <&cpg CPG_MOD 570 clocks = <&cpg CPG_MOD 1003>;
576 power-domains = <&sysc 571 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
577 resets = <&cpg 1003>; 572 resets = <&cpg 1003>;
578 i2c-scl-internal-delay 573 i2c-scl-internal-delay-ns = <6>;
579 status = "disabled"; 574 status = "disabled";
580 }; 575 };
581 576
582 iic_pmic: i2c@e60b0000 { 577 iic_pmic: i2c@e60b0000 {
583 #address-cells = <1>; 578 #address-cells = <1>;
584 #size-cells = <0>; 579 #size-cells = <0>;
585 compatible = "renesas, 580 compatible = "renesas,iic-r8a774c0",
586 "renesas, 581 "renesas,rcar-gen3-iic",
587 "renesas, 582 "renesas,rmobile-iic";
588 reg = <0 0xe60b0000 0 583 reg = <0 0xe60b0000 0 0x425>;
589 interrupts = <GIC_SPI 584 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
590 clocks = <&cpg CPG_MOD 585 clocks = <&cpg CPG_MOD 926>;
591 power-domains = <&sysc 586 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
592 resets = <&cpg 926>; 587 resets = <&cpg 926>;
593 dmas = <&dmac0 0x11>, 588 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
594 dma-names = "tx", "rx" 589 dma-names = "tx", "rx";
595 status = "disabled"; 590 status = "disabled";
596 }; 591 };
597 592
598 hscif0: serial@e6540000 { 593 hscif0: serial@e6540000 {
599 compatible = "renesas, 594 compatible = "renesas,hscif-r8a774c0",
600 "renesas, 595 "renesas,rcar-gen3-hscif",
601 "renesas, 596 "renesas,hscif";
602 reg = <0 0xe6540000 0 597 reg = <0 0xe6540000 0 0x60>;
603 interrupts = <GIC_SPI 598 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
604 clocks = <&cpg CPG_MOD 599 clocks = <&cpg CPG_MOD 520>,
605 <&cpg CPG_COR 600 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
606 <&scif_clk>; 601 <&scif_clk>;
607 clock-names = "fck", " 602 clock-names = "fck", "brg_int", "scif_clk";
608 dmas = <&dmac1 0x31>, 603 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
609 <&dmac2 0x31>, 604 <&dmac2 0x31>, <&dmac2 0x30>;
610 dma-names = "tx", "rx" 605 dma-names = "tx", "rx", "tx", "rx";
611 power-domains = <&sysc 606 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
612 resets = <&cpg 520>; 607 resets = <&cpg 520>;
613 status = "disabled"; 608 status = "disabled";
614 }; 609 };
615 610
616 hscif1: serial@e6550000 { 611 hscif1: serial@e6550000 {
617 compatible = "renesas, 612 compatible = "renesas,hscif-r8a774c0",
618 "renesas, 613 "renesas,rcar-gen3-hscif",
619 "renesas, 614 "renesas,hscif";
620 reg = <0 0xe6550000 0 615 reg = <0 0xe6550000 0 0x60>;
621 interrupts = <GIC_SPI 616 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
622 clocks = <&cpg CPG_MOD 617 clocks = <&cpg CPG_MOD 519>,
623 <&cpg CPG_COR 618 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
624 <&scif_clk>; 619 <&scif_clk>;
625 clock-names = "fck", " 620 clock-names = "fck", "brg_int", "scif_clk";
626 dmas = <&dmac1 0x33>, 621 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
627 <&dmac2 0x33>, 622 <&dmac2 0x33>, <&dmac2 0x32>;
628 dma-names = "tx", "rx" 623 dma-names = "tx", "rx", "tx", "rx";
629 power-domains = <&sysc 624 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
630 resets = <&cpg 519>; 625 resets = <&cpg 519>;
631 status = "disabled"; 626 status = "disabled";
632 }; 627 };
633 628
634 hscif2: serial@e6560000 { 629 hscif2: serial@e6560000 {
635 compatible = "renesas, 630 compatible = "renesas,hscif-r8a774c0",
636 "renesas, 631 "renesas,rcar-gen3-hscif",
637 "renesas, 632 "renesas,hscif";
638 reg = <0 0xe6560000 0 633 reg = <0 0xe6560000 0 0x60>;
639 interrupts = <GIC_SPI 634 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
640 clocks = <&cpg CPG_MOD 635 clocks = <&cpg CPG_MOD 518>,
641 <&cpg CPG_COR 636 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
642 <&scif_clk>; 637 <&scif_clk>;
643 clock-names = "fck", " 638 clock-names = "fck", "brg_int", "scif_clk";
644 dmas = <&dmac1 0x35>, 639 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
645 <&dmac2 0x35>, 640 <&dmac2 0x35>, <&dmac2 0x34>;
646 dma-names = "tx", "rx" 641 dma-names = "tx", "rx", "tx", "rx";
647 power-domains = <&sysc 642 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
648 resets = <&cpg 518>; 643 resets = <&cpg 518>;
649 status = "disabled"; 644 status = "disabled";
650 }; 645 };
651 646
652 hscif3: serial@e66a0000 { 647 hscif3: serial@e66a0000 {
653 compatible = "renesas, 648 compatible = "renesas,hscif-r8a774c0",
654 "renesas, 649 "renesas,rcar-gen3-hscif",
655 "renesas, 650 "renesas,hscif";
656 reg = <0 0xe66a0000 0 651 reg = <0 0xe66a0000 0 0x60>;
657 interrupts = <GIC_SPI 652 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
658 clocks = <&cpg CPG_MOD 653 clocks = <&cpg CPG_MOD 517>,
659 <&cpg CPG_COR 654 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
660 <&scif_clk>; 655 <&scif_clk>;
661 clock-names = "fck", " 656 clock-names = "fck", "brg_int", "scif_clk";
662 dmas = <&dmac0 0x37>, 657 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
663 dma-names = "tx", "rx" 658 dma-names = "tx", "rx";
664 power-domains = <&sysc 659 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
665 resets = <&cpg 517>; 660 resets = <&cpg 517>;
666 status = "disabled"; 661 status = "disabled";
667 }; 662 };
668 663
669 hscif4: serial@e66b0000 { 664 hscif4: serial@e66b0000 {
670 compatible = "renesas, 665 compatible = "renesas,hscif-r8a774c0",
671 "renesas, 666 "renesas,rcar-gen3-hscif",
672 "renesas, 667 "renesas,hscif";
673 reg = <0 0xe66b0000 0 668 reg = <0 0xe66b0000 0 0x60>;
674 interrupts = <GIC_SPI 669 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
675 clocks = <&cpg CPG_MOD 670 clocks = <&cpg CPG_MOD 516>,
676 <&cpg CPG_COR 671 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
677 <&scif_clk>; 672 <&scif_clk>;
678 clock-names = "fck", " 673 clock-names = "fck", "brg_int", "scif_clk";
679 dmas = <&dmac0 0x39>, 674 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
680 dma-names = "tx", "rx" 675 dma-names = "tx", "rx";
681 power-domains = <&sysc 676 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
682 resets = <&cpg 516>; 677 resets = <&cpg 516>;
683 status = "disabled"; 678 status = "disabled";
684 }; 679 };
685 680
686 hsusb: usb@e6590000 { 681 hsusb: usb@e6590000 {
687 compatible = "renesas, 682 compatible = "renesas,usbhs-r8a774c0",
688 "renesas, 683 "renesas,rcar-gen3-usbhs";
689 reg = <0 0xe6590000 0 684 reg = <0 0xe6590000 0 0x200>;
690 interrupts = <GIC_SPI 685 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
691 clocks = <&cpg CPG_MOD 686 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
692 dmas = <&usb_dmac0 0>, 687 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
693 <&usb_dmac1 0>, 688 <&usb_dmac1 0>, <&usb_dmac1 1>;
694 dma-names = "ch0", "ch 689 dma-names = "ch0", "ch1", "ch2", "ch3";
695 renesas,buswait = <11> 690 renesas,buswait = <11>;
696 phys = <&usb2_phy0 3>; 691 phys = <&usb2_phy0 3>;
697 phy-names = "usb"; 692 phy-names = "usb";
698 power-domains = <&sysc 693 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
699 resets = <&cpg 704>, < 694 resets = <&cpg 704>, <&cpg 703>;
700 status = "disabled"; 695 status = "disabled";
701 }; 696 };
702 697
703 usb_dmac0: dma-controller@e65a 698 usb_dmac0: dma-controller@e65a0000 {
704 compatible = "renesas, 699 compatible = "renesas,r8a774c0-usb-dmac",
705 "renesas, 700 "renesas,usb-dmac";
706 reg = <0 0xe65a0000 0 701 reg = <0 0xe65a0000 0 0x100>;
707 interrupts = <GIC_SPI 702 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
708 <GIC_SPI 703 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
709 interrupt-names = "ch0 704 interrupt-names = "ch0", "ch1";
710 clocks = <&cpg CPG_MOD 705 clocks = <&cpg CPG_MOD 330>;
711 power-domains = <&sysc 706 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
712 resets = <&cpg 330>; 707 resets = <&cpg 330>;
713 #dma-cells = <1>; 708 #dma-cells = <1>;
714 dma-channels = <2>; 709 dma-channels = <2>;
715 }; 710 };
716 711
717 usb_dmac1: dma-controller@e65b 712 usb_dmac1: dma-controller@e65b0000 {
718 compatible = "renesas, 713 compatible = "renesas,r8a774c0-usb-dmac",
719 "renesas, 714 "renesas,usb-dmac";
720 reg = <0 0xe65b0000 0 715 reg = <0 0xe65b0000 0 0x100>;
721 interrupts = <GIC_SPI 716 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
722 <GIC_SPI 717 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
723 interrupt-names = "ch0 718 interrupt-names = "ch0", "ch1";
724 clocks = <&cpg CPG_MOD 719 clocks = <&cpg CPG_MOD 331>;
725 power-domains = <&sysc 720 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
726 resets = <&cpg 331>; 721 resets = <&cpg 331>;
727 #dma-cells = <1>; 722 #dma-cells = <1>;
728 dma-channels = <2>; 723 dma-channels = <2>;
729 }; 724 };
730 725
731 dmac0: dma-controller@e6700000 726 dmac0: dma-controller@e6700000 {
732 compatible = "renesas, 727 compatible = "renesas,dmac-r8a774c0",
733 "renesas, 728 "renesas,rcar-dmac";
734 reg = <0 0xe6700000 0 729 reg = <0 0xe6700000 0 0x10000>;
735 interrupts = <GIC_SPI 730 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
736 <GIC_SPI 731 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
737 <GIC_SPI 732 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
738 <GIC_SPI 733 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
739 <GIC_SPI 734 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
740 <GIC_SPI 735 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
741 <GIC_SPI 736 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
742 <GIC_SPI 737 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
743 <GIC_SPI 738 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
744 <GIC_SPI 739 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
745 <GIC_SPI 740 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
746 <GIC_SPI 741 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
747 <GIC_SPI 742 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
748 <GIC_SPI 743 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
749 <GIC_SPI 744 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
750 <GIC_SPI 745 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
751 <GIC_SPI 746 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
752 interrupt-names = "err 747 interrupt-names = "error",
753 "ch0", 748 "ch0", "ch1", "ch2", "ch3",
754 "ch4", 749 "ch4", "ch5", "ch6", "ch7",
755 "ch8", 750 "ch8", "ch9", "ch10", "ch11",
756 "ch12" 751 "ch12", "ch13", "ch14", "ch15";
757 clocks = <&cpg CPG_MOD 752 clocks = <&cpg CPG_MOD 219>;
758 clock-names = "fck"; 753 clock-names = "fck";
759 power-domains = <&sysc 754 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
760 resets = <&cpg 219>; 755 resets = <&cpg 219>;
761 #dma-cells = <1>; 756 #dma-cells = <1>;
762 dma-channels = <16>; 757 dma-channels = <16>;
763 iommus = <&ipmmu_ds0 0 758 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
764 <&ipmmu_ds0 2>, 759 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
765 <&ipmmu_ds0 4>, 760 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
766 <&ipmmu_ds0 6>, 761 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
767 <&ipmmu_ds0 8>, 762 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
768 <&ipmmu_ds0 10> 763 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
769 <&ipmmu_ds0 12> 764 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
770 <&ipmmu_ds0 14> 765 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
771 }; 766 };
772 767
773 dmac1: dma-controller@e7300000 768 dmac1: dma-controller@e7300000 {
774 compatible = "renesas, 769 compatible = "renesas,dmac-r8a774c0",
775 "renesas, 770 "renesas,rcar-dmac";
776 reg = <0 0xe7300000 0 771 reg = <0 0xe7300000 0 0x10000>;
777 interrupts = <GIC_SPI 772 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
778 <GIC_SPI 773 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
779 <GIC_SPI 774 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
780 <GIC_SPI 775 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
781 <GIC_SPI 776 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
782 <GIC_SPI 777 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
783 <GIC_SPI 778 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
784 <GIC_SPI 779 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
785 <GIC_SPI 780 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
786 <GIC_SPI 781 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
787 <GIC_SPI 782 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
788 <GIC_SPI 783 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
789 <GIC_SPI 784 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
790 <GIC_SPI 785 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
791 <GIC_SPI 786 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
792 <GIC_SPI 787 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
793 <GIC_SPI 788 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
794 interrupt-names = "err 789 interrupt-names = "error",
795 "ch0", 790 "ch0", "ch1", "ch2", "ch3",
796 "ch4", 791 "ch4", "ch5", "ch6", "ch7",
797 "ch8", 792 "ch8", "ch9", "ch10", "ch11",
798 "ch12" 793 "ch12", "ch13", "ch14", "ch15";
799 clocks = <&cpg CPG_MOD 794 clocks = <&cpg CPG_MOD 218>;
800 clock-names = "fck"; 795 clock-names = "fck";
801 power-domains = <&sysc 796 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
802 resets = <&cpg 218>; 797 resets = <&cpg 218>;
803 #dma-cells = <1>; 798 #dma-cells = <1>;
804 dma-channels = <16>; 799 dma-channels = <16>;
805 iommus = <&ipmmu_ds1 0 800 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
806 <&ipmmu_ds1 2>, 801 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
807 <&ipmmu_ds1 4>, 802 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
808 <&ipmmu_ds1 6>, 803 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
809 <&ipmmu_ds1 8>, 804 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
810 <&ipmmu_ds1 10> 805 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
811 <&ipmmu_ds1 12> 806 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
812 <&ipmmu_ds1 14> 807 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
813 }; 808 };
814 809
815 dmac2: dma-controller@e7310000 810 dmac2: dma-controller@e7310000 {
816 compatible = "renesas, 811 compatible = "renesas,dmac-r8a774c0",
817 "renesas, 812 "renesas,rcar-dmac";
818 reg = <0 0xe7310000 0 813 reg = <0 0xe7310000 0 0x10000>;
819 interrupts = <GIC_SPI 814 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
820 <GIC_SPI 815 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
821 <GIC_SPI 816 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
822 <GIC_SPI 817 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
823 <GIC_SPI 818 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
824 <GIC_SPI 819 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
825 <GIC_SPI 820 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
826 <GIC_SPI 821 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
827 <GIC_SPI 822 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
828 <GIC_SPI 823 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
829 <GIC_SPI 824 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
830 <GIC_SPI 825 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
831 <GIC_SPI 826 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
832 <GIC_SPI 827 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
833 <GIC_SPI 828 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
834 <GIC_SPI 829 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
835 <GIC_SPI 830 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
836 interrupt-names = "err 831 interrupt-names = "error",
837 "ch0", 832 "ch0", "ch1", "ch2", "ch3",
838 "ch4", 833 "ch4", "ch5", "ch6", "ch7",
839 "ch8", 834 "ch8", "ch9", "ch10", "ch11",
840 "ch12" 835 "ch12", "ch13", "ch14", "ch15";
841 clocks = <&cpg CPG_MOD 836 clocks = <&cpg CPG_MOD 217>;
842 clock-names = "fck"; 837 clock-names = "fck";
843 power-domains = <&sysc 838 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
844 resets = <&cpg 217>; 839 resets = <&cpg 217>;
845 #dma-cells = <1>; 840 #dma-cells = <1>;
846 dma-channels = <16>; 841 dma-channels = <16>;
847 iommus = <&ipmmu_ds1 1 842 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
848 <&ipmmu_ds1 18> 843 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
849 <&ipmmu_ds1 20> 844 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
850 <&ipmmu_ds1 22> 845 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
851 <&ipmmu_ds1 24> 846 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
852 <&ipmmu_ds1 26> 847 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
853 <&ipmmu_ds1 28> 848 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
854 <&ipmmu_ds1 30> 849 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
855 }; 850 };
856 851
857 ipmmu_ds0: iommu@e6740000 { 852 ipmmu_ds0: iommu@e6740000 {
858 compatible = "renesas, 853 compatible = "renesas,ipmmu-r8a774c0";
859 reg = <0 0xe6740000 0 854 reg = <0 0xe6740000 0 0x1000>;
860 renesas,ipmmu-main = < 855 renesas,ipmmu-main = <&ipmmu_mm 0>;
861 power-domains = <&sysc 856 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
862 #iommu-cells = <1>; 857 #iommu-cells = <1>;
863 }; 858 };
864 859
865 ipmmu_ds1: iommu@e7740000 { 860 ipmmu_ds1: iommu@e7740000 {
866 compatible = "renesas, 861 compatible = "renesas,ipmmu-r8a774c0";
867 reg = <0 0xe7740000 0 862 reg = <0 0xe7740000 0 0x1000>;
868 renesas,ipmmu-main = < 863 renesas,ipmmu-main = <&ipmmu_mm 1>;
869 power-domains = <&sysc 864 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
870 #iommu-cells = <1>; 865 #iommu-cells = <1>;
871 }; 866 };
872 867
873 ipmmu_hc: iommu@e6570000 { 868 ipmmu_hc: iommu@e6570000 {
874 compatible = "renesas, 869 compatible = "renesas,ipmmu-r8a774c0";
875 reg = <0 0xe6570000 0 870 reg = <0 0xe6570000 0 0x1000>;
876 renesas,ipmmu-main = < 871 renesas,ipmmu-main = <&ipmmu_mm 2>;
877 power-domains = <&sysc 872 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
878 #iommu-cells = <1>; 873 #iommu-cells = <1>;
879 }; 874 };
880 875
881 ipmmu_mm: iommu@e67b0000 { 876 ipmmu_mm: iommu@e67b0000 {
882 compatible = "renesas, 877 compatible = "renesas,ipmmu-r8a774c0";
883 reg = <0 0xe67b0000 0 878 reg = <0 0xe67b0000 0 0x1000>;
884 interrupts = <GIC_SPI 879 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
885 <GIC_SPI 880 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
886 power-domains = <&sysc 881 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
887 #iommu-cells = <1>; 882 #iommu-cells = <1>;
888 }; 883 };
889 884
890 ipmmu_mp: iommu@ec670000 { 885 ipmmu_mp: iommu@ec670000 {
891 compatible = "renesas, 886 compatible = "renesas,ipmmu-r8a774c0";
892 reg = <0 0xec670000 0 887 reg = <0 0xec670000 0 0x1000>;
893 renesas,ipmmu-main = < 888 renesas,ipmmu-main = <&ipmmu_mm 4>;
894 power-domains = <&sysc 889 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
895 #iommu-cells = <1>; 890 #iommu-cells = <1>;
896 }; 891 };
897 892
898 ipmmu_pv0: iommu@fd800000 { 893 ipmmu_pv0: iommu@fd800000 {
899 compatible = "renesas, 894 compatible = "renesas,ipmmu-r8a774c0";
900 reg = <0 0xfd800000 0 895 reg = <0 0xfd800000 0 0x1000>;
901 renesas,ipmmu-main = < 896 renesas,ipmmu-main = <&ipmmu_mm 6>;
902 power-domains = <&sysc 897 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
903 #iommu-cells = <1>; 898 #iommu-cells = <1>;
904 }; 899 };
905 900
906 ipmmu_vc0: iommu@fe6b0000 { 901 ipmmu_vc0: iommu@fe6b0000 {
907 compatible = "renesas, 902 compatible = "renesas,ipmmu-r8a774c0";
908 reg = <0 0xfe6b0000 0 903 reg = <0 0xfe6b0000 0 0x1000>;
909 renesas,ipmmu-main = < 904 renesas,ipmmu-main = <&ipmmu_mm 12>;
910 power-domains = <&sysc 905 power-domains = <&sysc R8A774C0_PD_A3VC>;
911 #iommu-cells = <1>; 906 #iommu-cells = <1>;
912 }; 907 };
913 908
914 ipmmu_vi0: iommu@febd0000 { 909 ipmmu_vi0: iommu@febd0000 {
915 compatible = "renesas, 910 compatible = "renesas,ipmmu-r8a774c0";
916 reg = <0 0xfebd0000 0 911 reg = <0 0xfebd0000 0 0x1000>;
917 renesas,ipmmu-main = < 912 renesas,ipmmu-main = <&ipmmu_mm 14>;
918 power-domains = <&sysc 913 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
919 #iommu-cells = <1>; 914 #iommu-cells = <1>;
920 }; 915 };
921 916
922 ipmmu_vp0: iommu@fe990000 { 917 ipmmu_vp0: iommu@fe990000 {
923 compatible = "renesas, 918 compatible = "renesas,ipmmu-r8a774c0";
924 reg = <0 0xfe990000 0 919 reg = <0 0xfe990000 0 0x1000>;
925 renesas,ipmmu-main = < 920 renesas,ipmmu-main = <&ipmmu_mm 16>;
926 power-domains = <&sysc 921 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
927 #iommu-cells = <1>; 922 #iommu-cells = <1>;
928 }; 923 };
929 924
930 avb: ethernet@e6800000 { 925 avb: ethernet@e6800000 {
931 compatible = "renesas, 926 compatible = "renesas,etheravb-r8a774c0",
932 "renesas, 927 "renesas,etheravb-rcar-gen3";
933 reg = <0 0xe6800000 0 928 reg = <0 0xe6800000 0 0x800>;
934 interrupts = <GIC_SPI 929 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
935 <GIC_SPI 930 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
936 <GIC_SPI 931 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
937 <GIC_SPI 932 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
938 <GIC_SPI 933 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
939 <GIC_SPI 934 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
940 <GIC_SPI 935 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
941 <GIC_SPI 936 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
942 <GIC_SPI 937 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
943 <GIC_SPI 938 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
944 <GIC_SPI 939 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
945 <GIC_SPI 940 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
946 <GIC_SPI 941 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
947 <GIC_SPI 942 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
948 <GIC_SPI 943 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
949 <GIC_SPI 944 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
950 <GIC_SPI 945 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
951 <GIC_SPI 946 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
952 <GIC_SPI 947 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
953 <GIC_SPI 948 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
954 <GIC_SPI 949 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
955 <GIC_SPI 950 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
956 <GIC_SPI 951 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
957 <GIC_SPI 952 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
958 <GIC_SPI 953 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
959 interrupt-names = "ch0 954 interrupt-names = "ch0", "ch1", "ch2", "ch3",
960 "ch4 955 "ch4", "ch5", "ch6", "ch7",
961 "ch8 956 "ch8", "ch9", "ch10", "ch11",
962 "ch1 957 "ch12", "ch13", "ch14", "ch15",
963 "ch1 958 "ch16", "ch17", "ch18", "ch19",
964 "ch2 959 "ch20", "ch21", "ch22", "ch23",
965 "ch2 960 "ch24";
966 clocks = <&cpg CPG_MOD 961 clocks = <&cpg CPG_MOD 812>;
967 clock-names = "fck"; 962 clock-names = "fck";
968 power-domains = <&sysc 963 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
969 resets = <&cpg 812>; 964 resets = <&cpg 812>;
970 phy-mode = "rgmii"; 965 phy-mode = "rgmii";
971 rx-internal-delay-ps = 966 rx-internal-delay-ps = <0>;
972 iommus = <&ipmmu_ds0 1 967 iommus = <&ipmmu_ds0 16>;
973 #address-cells = <1>; 968 #address-cells = <1>;
974 #size-cells = <0>; 969 #size-cells = <0>;
975 status = "disabled"; 970 status = "disabled";
976 }; 971 };
977 972
978 can0: can@e6c30000 { 973 can0: can@e6c30000 {
979 compatible = "renesas, 974 compatible = "renesas,can-r8a774c0",
980 "renesas, 975 "renesas,rcar-gen3-can";
981 reg = <0 0xe6c30000 0 976 reg = <0 0xe6c30000 0 0x1000>;
982 interrupts = <GIC_SPI 977 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
983 clocks = <&cpg CPG_MOD 978 clocks = <&cpg CPG_MOD 916>,
984 <&cpg CPG_COR 979 <&cpg CPG_CORE R8A774C0_CLK_CANFD>,
985 <&can_clk>; 980 <&can_clk>;
986 clock-names = "clkp1", 981 clock-names = "clkp1", "clkp2", "can_clk";
987 assigned-clocks = <&cp 982 assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>;
988 assigned-clock-rates = 983 assigned-clock-rates = <40000000>;
989 power-domains = <&sysc 984 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
990 resets = <&cpg 916>; 985 resets = <&cpg 916>;
991 status = "disabled"; 986 status = "disabled";
992 }; 987 };
993 988
994 can1: can@e6c38000 { 989 can1: can@e6c38000 {
995 compatible = "renesas, 990 compatible = "renesas,can-r8a774c0",
996 "renesas, 991 "renesas,rcar-gen3-can";
997 reg = <0 0xe6c38000 0 992 reg = <0 0xe6c38000 0 0x1000>;
998 interrupts = <GIC_SPI 993 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
999 clocks = <&cpg CPG_MOD 994 clocks = <&cpg CPG_MOD 915>,
1000 <&cpg CPG_CO 995 <&cpg CPG_CORE R8A774C0_CLK_CANFD>,
1001 <&can_clk>; 996 <&can_clk>;
1002 clock-names = "clkp1" 997 clock-names = "clkp1", "clkp2", "can_clk";
1003 assigned-clocks = <&c 998 assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>;
1004 assigned-clock-rates 999 assigned-clock-rates = <40000000>;
1005 power-domains = <&sys 1000 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1006 resets = <&cpg 915>; 1001 resets = <&cpg 915>;
1007 status = "disabled"; 1002 status = "disabled";
1008 }; 1003 };
1009 1004
1010 canfd: can@e66c0000 { 1005 canfd: can@e66c0000 {
1011 compatible = "renesas 1006 compatible = "renesas,r8a774c0-canfd",
1012 "renesas 1007 "renesas,rcar-gen3-canfd";
1013 reg = <0 0xe66c0000 0 1008 reg = <0 0xe66c0000 0 0x8000>;
1014 interrupts = <GIC_SPI 1009 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
1015 <GIC_SPI 1010 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1016 interrupt-names = "ch <<
1017 clocks = <&cpg CPG_MO 1011 clocks = <&cpg CPG_MOD 914>,
1018 <&cpg CPG_CO 1012 <&cpg CPG_CORE R8A774C0_CLK_CANFD>,
1019 <&can_clk>; 1013 <&can_clk>;
1020 clock-names = "fck", 1014 clock-names = "fck", "canfd", "can_clk";
1021 assigned-clocks = <&c 1015 assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>;
1022 assigned-clock-rates 1016 assigned-clock-rates = <40000000>;
1023 power-domains = <&sys 1017 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1024 resets = <&cpg 914>; 1018 resets = <&cpg 914>;
1025 status = "disabled"; 1019 status = "disabled";
1026 1020
1027 channel0 { 1021 channel0 {
1028 status = "dis 1022 status = "disabled";
1029 }; 1023 };
1030 1024
1031 channel1 { 1025 channel1 {
1032 status = "dis 1026 status = "disabled";
1033 }; 1027 };
1034 }; 1028 };
1035 1029
1036 pwm0: pwm@e6e30000 { 1030 pwm0: pwm@e6e30000 {
1037 compatible = "renesas 1031 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1038 reg = <0 0xe6e30000 0 1032 reg = <0 0xe6e30000 0 0x8>;
1039 clocks = <&cpg CPG_MO 1033 clocks = <&cpg CPG_MOD 523>;
1040 power-domains = <&sys 1034 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1041 resets = <&cpg 523>; 1035 resets = <&cpg 523>;
1042 #pwm-cells = <2>; 1036 #pwm-cells = <2>;
1043 status = "disabled"; 1037 status = "disabled";
1044 }; 1038 };
1045 1039
1046 pwm1: pwm@e6e31000 { 1040 pwm1: pwm@e6e31000 {
1047 compatible = "renesas 1041 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1048 reg = <0 0xe6e31000 0 1042 reg = <0 0xe6e31000 0 0x8>;
1049 clocks = <&cpg CPG_MO 1043 clocks = <&cpg CPG_MOD 523>;
1050 power-domains = <&sys 1044 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1051 resets = <&cpg 523>; 1045 resets = <&cpg 523>;
1052 #pwm-cells = <2>; 1046 #pwm-cells = <2>;
1053 status = "disabled"; 1047 status = "disabled";
1054 }; 1048 };
1055 1049
1056 pwm2: pwm@e6e32000 { 1050 pwm2: pwm@e6e32000 {
1057 compatible = "renesas 1051 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1058 reg = <0 0xe6e32000 0 1052 reg = <0 0xe6e32000 0 0x8>;
1059 clocks = <&cpg CPG_MO 1053 clocks = <&cpg CPG_MOD 523>;
1060 power-domains = <&sys 1054 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1061 resets = <&cpg 523>; 1055 resets = <&cpg 523>;
1062 #pwm-cells = <2>; 1056 #pwm-cells = <2>;
1063 status = "disabled"; 1057 status = "disabled";
1064 }; 1058 };
1065 1059
1066 pwm3: pwm@e6e33000 { 1060 pwm3: pwm@e6e33000 {
1067 compatible = "renesas 1061 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1068 reg = <0 0xe6e33000 0 1062 reg = <0 0xe6e33000 0 0x8>;
1069 clocks = <&cpg CPG_MO 1063 clocks = <&cpg CPG_MOD 523>;
1070 power-domains = <&sys 1064 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1071 resets = <&cpg 523>; 1065 resets = <&cpg 523>;
1072 #pwm-cells = <2>; 1066 #pwm-cells = <2>;
1073 status = "disabled"; 1067 status = "disabled";
1074 }; 1068 };
1075 1069
1076 pwm4: pwm@e6e34000 { 1070 pwm4: pwm@e6e34000 {
1077 compatible = "renesas 1071 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1078 reg = <0 0xe6e34000 0 1072 reg = <0 0xe6e34000 0 0x8>;
1079 clocks = <&cpg CPG_MO 1073 clocks = <&cpg CPG_MOD 523>;
1080 power-domains = <&sys 1074 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1081 resets = <&cpg 523>; 1075 resets = <&cpg 523>;
1082 #pwm-cells = <2>; 1076 #pwm-cells = <2>;
1083 status = "disabled"; 1077 status = "disabled";
1084 }; 1078 };
1085 1079
1086 pwm5: pwm@e6e35000 { 1080 pwm5: pwm@e6e35000 {
1087 compatible = "renesas 1081 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1088 reg = <0 0xe6e35000 0 1082 reg = <0 0xe6e35000 0 0x8>;
1089 clocks = <&cpg CPG_MO 1083 clocks = <&cpg CPG_MOD 523>;
1090 power-domains = <&sys 1084 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1091 resets = <&cpg 523>; 1085 resets = <&cpg 523>;
1092 #pwm-cells = <2>; 1086 #pwm-cells = <2>;
1093 status = "disabled"; 1087 status = "disabled";
1094 }; 1088 };
1095 1089
1096 pwm6: pwm@e6e36000 { 1090 pwm6: pwm@e6e36000 {
1097 compatible = "renesas 1091 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1098 reg = <0 0xe6e36000 0 1092 reg = <0 0xe6e36000 0 0x8>;
1099 clocks = <&cpg CPG_MO 1093 clocks = <&cpg CPG_MOD 523>;
1100 power-domains = <&sys 1094 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1101 resets = <&cpg 523>; 1095 resets = <&cpg 523>;
1102 #pwm-cells = <2>; 1096 #pwm-cells = <2>;
1103 status = "disabled"; 1097 status = "disabled";
1104 }; 1098 };
1105 1099
1106 scif0: serial@e6e60000 { 1100 scif0: serial@e6e60000 {
1107 compatible = "renesas 1101 compatible = "renesas,scif-r8a774c0",
1108 "renesas 1102 "renesas,rcar-gen3-scif", "renesas,scif";
1109 reg = <0 0xe6e60000 0 1103 reg = <0 0xe6e60000 0 64>;
1110 interrupts = <GIC_SPI 1104 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
1111 clocks = <&cpg CPG_MO 1105 clocks = <&cpg CPG_MOD 207>,
1112 <&cpg CPG_CO 1106 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
1113 <&scif_clk>; 1107 <&scif_clk>;
1114 clock-names = "fck", 1108 clock-names = "fck", "brg_int", "scif_clk";
1115 dmas = <&dmac1 0x51>, 1109 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1116 <&dmac2 0x51>, 1110 <&dmac2 0x51>, <&dmac2 0x50>;
1117 dma-names = "tx", "rx 1111 dma-names = "tx", "rx", "tx", "rx";
1118 power-domains = <&sys 1112 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1119 resets = <&cpg 207>; 1113 resets = <&cpg 207>;
1120 status = "disabled"; 1114 status = "disabled";
1121 }; 1115 };
1122 1116
1123 scif1: serial@e6e68000 { 1117 scif1: serial@e6e68000 {
1124 compatible = "renesas 1118 compatible = "renesas,scif-r8a774c0",
1125 "renesas 1119 "renesas,rcar-gen3-scif", "renesas,scif";
1126 reg = <0 0xe6e68000 0 1120 reg = <0 0xe6e68000 0 64>;
1127 interrupts = <GIC_SPI 1121 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
1128 clocks = <&cpg CPG_MO 1122 clocks = <&cpg CPG_MOD 206>,
1129 <&cpg CPG_CO 1123 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
1130 <&scif_clk>; 1124 <&scif_clk>;
1131 clock-names = "fck", 1125 clock-names = "fck", "brg_int", "scif_clk";
1132 dmas = <&dmac1 0x53>, 1126 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1133 <&dmac2 0x53>, 1127 <&dmac2 0x53>, <&dmac2 0x52>;
1134 dma-names = "tx", "rx 1128 dma-names = "tx", "rx", "tx", "rx";
1135 power-domains = <&sys 1129 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1136 resets = <&cpg 206>; 1130 resets = <&cpg 206>;
1137 status = "disabled"; 1131 status = "disabled";
1138 }; 1132 };
1139 1133
1140 scif2: serial@e6e88000 { 1134 scif2: serial@e6e88000 {
1141 compatible = "renesas 1135 compatible = "renesas,scif-r8a774c0",
1142 "renesas 1136 "renesas,rcar-gen3-scif", "renesas,scif";
1143 reg = <0 0xe6e88000 0 1137 reg = <0 0xe6e88000 0 64>;
1144 interrupts = <GIC_SPI 1138 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
1145 clocks = <&cpg CPG_MO 1139 clocks = <&cpg CPG_MOD 310>,
1146 <&cpg CPG_CO 1140 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
1147 <&scif_clk>; 1141 <&scif_clk>;
1148 clock-names = "fck", 1142 clock-names = "fck", "brg_int", "scif_clk";
1149 dmas = <&dmac1 0x13>, 1143 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1150 <&dmac2 0x13>, 1144 <&dmac2 0x13>, <&dmac2 0x12>;
1151 dma-names = "tx", "rx 1145 dma-names = "tx", "rx", "tx", "rx";
1152 power-domains = <&sys 1146 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1153 resets = <&cpg 310>; 1147 resets = <&cpg 310>;
1154 status = "disabled"; 1148 status = "disabled";
1155 }; 1149 };
1156 1150
1157 scif3: serial@e6c50000 { 1151 scif3: serial@e6c50000 {
1158 compatible = "renesas 1152 compatible = "renesas,scif-r8a774c0",
1159 "renesas 1153 "renesas,rcar-gen3-scif", "renesas,scif";
1160 reg = <0 0xe6c50000 0 1154 reg = <0 0xe6c50000 0 64>;
1161 interrupts = <GIC_SPI 1155 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1162 clocks = <&cpg CPG_MO 1156 clocks = <&cpg CPG_MOD 204>,
1163 <&cpg CPG_CO 1157 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
1164 <&scif_clk>; 1158 <&scif_clk>;
1165 clock-names = "fck", 1159 clock-names = "fck", "brg_int", "scif_clk";
1166 dmas = <&dmac0 0x57>, 1160 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1167 dma-names = "tx", "rx 1161 dma-names = "tx", "rx";
1168 power-domains = <&sys 1162 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1169 resets = <&cpg 204>; 1163 resets = <&cpg 204>;
1170 status = "disabled"; 1164 status = "disabled";
1171 }; 1165 };
1172 1166
1173 scif4: serial@e6c40000 { 1167 scif4: serial@e6c40000 {
1174 compatible = "renesas 1168 compatible = "renesas,scif-r8a774c0",
1175 "renesas 1169 "renesas,rcar-gen3-scif", "renesas,scif";
1176 reg = <0 0xe6c40000 0 1170 reg = <0 0xe6c40000 0 64>;
1177 interrupts = <GIC_SPI 1171 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1178 clocks = <&cpg CPG_MO 1172 clocks = <&cpg CPG_MOD 203>,
1179 <&cpg CPG_CO 1173 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
1180 <&scif_clk>; 1174 <&scif_clk>;
1181 clock-names = "fck", 1175 clock-names = "fck", "brg_int", "scif_clk";
1182 dmas = <&dmac0 0x59>, 1176 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1183 dma-names = "tx", "rx 1177 dma-names = "tx", "rx";
1184 power-domains = <&sys 1178 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1185 resets = <&cpg 203>; 1179 resets = <&cpg 203>;
1186 status = "disabled"; 1180 status = "disabled";
1187 }; 1181 };
1188 1182
1189 scif5: serial@e6f30000 { 1183 scif5: serial@e6f30000 {
1190 compatible = "renesas 1184 compatible = "renesas,scif-r8a774c0",
1191 "renesas 1185 "renesas,rcar-gen3-scif", "renesas,scif";
1192 reg = <0 0xe6f30000 0 1186 reg = <0 0xe6f30000 0 64>;
1193 interrupts = <GIC_SPI 1187 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1194 clocks = <&cpg CPG_MO 1188 clocks = <&cpg CPG_MOD 202>,
1195 <&cpg CPG_CO 1189 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
1196 <&scif_clk>; 1190 <&scif_clk>;
1197 clock-names = "fck", 1191 clock-names = "fck", "brg_int", "scif_clk";
1198 dmas = <&dmac0 0x5b>, 1192 dmas = <&dmac0 0x5b>, <&dmac0 0x5a>;
1199 dma-names = "tx", "rx 1193 dma-names = "tx", "rx";
1200 power-domains = <&sys 1194 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1201 resets = <&cpg 202>; 1195 resets = <&cpg 202>;
1202 status = "disabled"; 1196 status = "disabled";
1203 }; 1197 };
1204 1198
1205 msiof0: spi@e6e90000 { 1199 msiof0: spi@e6e90000 {
1206 compatible = "renesas 1200 compatible = "renesas,msiof-r8a774c0",
1207 "renesas 1201 "renesas,rcar-gen3-msiof";
1208 reg = <0 0xe6e90000 0 1202 reg = <0 0xe6e90000 0 0x0064>;
1209 interrupts = <GIC_SPI 1203 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1210 clocks = <&cpg CPG_MO 1204 clocks = <&cpg CPG_MOD 211>;
1211 dmas = <&dmac1 0x41>, 1205 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1212 <&dmac2 0x41>, 1206 <&dmac2 0x41>, <&dmac2 0x40>;
1213 dma-names = "tx", "rx 1207 dma-names = "tx", "rx", "tx", "rx";
1214 power-domains = <&sys 1208 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1215 resets = <&cpg 211>; 1209 resets = <&cpg 211>;
1216 #address-cells = <1>; 1210 #address-cells = <1>;
1217 #size-cells = <0>; 1211 #size-cells = <0>;
1218 status = "disabled"; 1212 status = "disabled";
1219 }; 1213 };
1220 1214
1221 msiof1: spi@e6ea0000 { 1215 msiof1: spi@e6ea0000 {
1222 compatible = "renesas 1216 compatible = "renesas,msiof-r8a774c0",
1223 "renesas 1217 "renesas,rcar-gen3-msiof";
1224 reg = <0 0xe6ea0000 0 1218 reg = <0 0xe6ea0000 0 0x0064>;
1225 interrupts = <GIC_SPI 1219 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1226 clocks = <&cpg CPG_MO 1220 clocks = <&cpg CPG_MOD 210>;
1227 dmas = <&dmac0 0x43>, 1221 dmas = <&dmac0 0x43>, <&dmac0 0x42>;
1228 dma-names = "tx", "rx 1222 dma-names = "tx", "rx";
1229 power-domains = <&sys 1223 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1230 resets = <&cpg 210>; 1224 resets = <&cpg 210>;
1231 #address-cells = <1>; 1225 #address-cells = <1>;
1232 #size-cells = <0>; 1226 #size-cells = <0>;
1233 status = "disabled"; 1227 status = "disabled";
1234 }; 1228 };
1235 1229
1236 msiof2: spi@e6c00000 { 1230 msiof2: spi@e6c00000 {
1237 compatible = "renesas 1231 compatible = "renesas,msiof-r8a774c0",
1238 "renesas 1232 "renesas,rcar-gen3-msiof";
1239 reg = <0 0xe6c00000 0 1233 reg = <0 0xe6c00000 0 0x0064>;
1240 interrupts = <GIC_SPI 1234 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1241 clocks = <&cpg CPG_MO 1235 clocks = <&cpg CPG_MOD 209>;
1242 dmas = <&dmac0 0x45>, 1236 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1243 dma-names = "tx", "rx 1237 dma-names = "tx", "rx";
1244 power-domains = <&sys 1238 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1245 resets = <&cpg 209>; 1239 resets = <&cpg 209>;
1246 #address-cells = <1>; 1240 #address-cells = <1>;
1247 #size-cells = <0>; 1241 #size-cells = <0>;
1248 status = "disabled"; 1242 status = "disabled";
1249 }; 1243 };
1250 1244
1251 msiof3: spi@e6c10000 { 1245 msiof3: spi@e6c10000 {
1252 compatible = "renesas 1246 compatible = "renesas,msiof-r8a774c0",
1253 "renesas 1247 "renesas,rcar-gen3-msiof";
1254 reg = <0 0xe6c10000 0 1248 reg = <0 0xe6c10000 0 0x0064>;
1255 interrupts = <GIC_SPI 1249 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1256 clocks = <&cpg CPG_MO 1250 clocks = <&cpg CPG_MOD 208>;
1257 dmas = <&dmac0 0x47>, 1251 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1258 dma-names = "tx", "rx 1252 dma-names = "tx", "rx";
1259 power-domains = <&sys 1253 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1260 resets = <&cpg 208>; 1254 resets = <&cpg 208>;
1261 #address-cells = <1>; 1255 #address-cells = <1>;
1262 #size-cells = <0>; 1256 #size-cells = <0>;
1263 status = "disabled"; 1257 status = "disabled";
1264 }; 1258 };
1265 1259
1266 vin4: video@e6ef4000 { 1260 vin4: video@e6ef4000 {
1267 compatible = "renesas 1261 compatible = "renesas,vin-r8a774c0";
1268 reg = <0 0xe6ef4000 0 1262 reg = <0 0xe6ef4000 0 0x1000>;
1269 interrupts = <GIC_SPI 1263 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
1270 clocks = <&cpg CPG_MO 1264 clocks = <&cpg CPG_MOD 807>;
1271 power-domains = <&sys 1265 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1272 resets = <&cpg 807>; 1266 resets = <&cpg 807>;
1273 renesas,id = <4>; 1267 renesas,id = <4>;
1274 status = "disabled"; 1268 status = "disabled";
1275 1269
1276 ports { 1270 ports {
1277 #address-cell 1271 #address-cells = <1>;
1278 #size-cells = 1272 #size-cells = <0>;
1279 1273
1280 port@1 { 1274 port@1 {
1281 #addr 1275 #address-cells = <1>;
1282 #size 1276 #size-cells = <0>;
1283 1277
1284 reg = 1278 reg = <1>;
1285 1279
1286 vin4c 1280 vin4csi40: endpoint@2 {
1287 1281 reg = <2>;
1288 !! 1282 remote-endpoint= <&csi40vin4>;
1289 }; 1283 };
1290 }; 1284 };
1291 }; 1285 };
1292 }; 1286 };
1293 1287
1294 vin5: video@e6ef5000 { 1288 vin5: video@e6ef5000 {
1295 compatible = "renesas 1289 compatible = "renesas,vin-r8a774c0";
1296 reg = <0 0xe6ef5000 0 1290 reg = <0 0xe6ef5000 0 0x1000>;
1297 interrupts = <GIC_SPI 1291 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
1298 clocks = <&cpg CPG_MO 1292 clocks = <&cpg CPG_MOD 806>;
1299 power-domains = <&sys 1293 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1300 resets = <&cpg 806>; 1294 resets = <&cpg 806>;
1301 renesas,id = <5>; 1295 renesas,id = <5>;
1302 status = "disabled"; 1296 status = "disabled";
1303 1297
1304 ports { 1298 ports {
1305 #address-cell 1299 #address-cells = <1>;
1306 #size-cells = 1300 #size-cells = <0>;
1307 1301
1308 port@1 { 1302 port@1 {
1309 #addr 1303 #address-cells = <1>;
1310 #size 1304 #size-cells = <0>;
1311 1305
1312 reg = 1306 reg = <1>;
1313 1307
1314 vin5c 1308 vin5csi40: endpoint@2 {
1315 1309 reg = <2>;
1316 !! 1310 remote-endpoint= <&csi40vin5>;
1317 }; 1311 };
1318 }; 1312 };
1319 }; 1313 };
1320 }; 1314 };
1321 1315
1322 rcar_sound: sound@ec500000 { 1316 rcar_sound: sound@ec500000 {
1323 /* 1317 /*
1324 * #sound-dai-cells i !! 1318 * #sound-dai-cells is required
1325 * 1319 *
1326 * Single DAI : #soun 1320 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1327 * Multi DAI : #soun 1321 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1328 */ 1322 */
1329 /* 1323 /*
1330 * #clock-cells is re 1324 * #clock-cells is required for audio_clkout0/1/2/3
1331 * 1325 *
1332 * clkout : #cl 1326 * clkout : #clock-cells = <0>; <&rcar_sound>;
1333 * clkout0/1/2/3: #cl 1327 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
1334 */ 1328 */
1335 compatible = "renesas 1329 compatible = "renesas,rcar_sound-r8a774c0",
1336 "renesas 1330 "renesas,rcar_sound-gen3";
1337 reg = <0 0xec500000 0 !! 1331 reg = <0 0xec500000 0 0x1000>, /* SCU */
1338 <0 0xec5a0000 0 !! 1332 <0 0xec5a0000 0 0x100>, /* ADG */
1339 <0 0xec540000 0 !! 1333 <0 0xec540000 0 0x1000>, /* SSIU */
1340 <0 0xec541000 0 !! 1334 <0 0xec541000 0 0x280>, /* SSI */
1341 <0 0xec760000 0 !! 1335 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
1342 reg-names = "scu", "a 1336 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1343 1337
1344 clocks = <&cpg CPG_MO 1338 clocks = <&cpg CPG_MOD 1005>,
1345 <&cpg CPG_MO 1339 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
1346 <&cpg CPG_MO 1340 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
1347 <&cpg CPG_MO 1341 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
1348 <&cpg CPG_MO 1342 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
1349 <&cpg CPG_MO 1343 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
1350 <&cpg CPG_MO 1344 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
1351 <&cpg CPG_MO 1345 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
1352 <&cpg CPG_MO 1346 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
1353 <&cpg CPG_MO 1347 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
1354 <&cpg CPG_MO 1348 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
1355 <&cpg CPG_MO 1349 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1356 <&cpg CPG_MO 1350 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1357 <&cpg CPG_MO 1351 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
1358 <&audio_clk_ 1352 <&audio_clk_a>, <&audio_clk_b>,
1359 <&audio_clk_ 1353 <&audio_clk_c>,
1360 <&cpg CPG_MO !! 1354 <&cpg CPG_CORE R8A774C0_CLK_ZA2>;
1361 clock-names = "ssi-al 1355 clock-names = "ssi-all",
1362 "ssi.9" 1356 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1363 "ssi.5" 1357 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1364 "ssi.1" 1358 "ssi.1", "ssi.0",
1365 "src.9" 1359 "src.9", "src.8", "src.7", "src.6",
1366 "src.5" 1360 "src.5", "src.4", "src.3", "src.2",
1367 "src.1" 1361 "src.1", "src.0",
1368 "mix.1" 1362 "mix.1", "mix.0",
1369 "ctu.1" 1363 "ctu.1", "ctu.0",
1370 "dvc.0" 1364 "dvc.0", "dvc.1",
1371 "clk_a" 1365 "clk_a", "clk_b", "clk_c", "clk_i";
1372 power-domains = <&sys 1366 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1373 resets = <&cpg 1005>, 1367 resets = <&cpg 1005>,
1374 <&cpg 1006>, 1368 <&cpg 1006>, <&cpg 1007>,
1375 <&cpg 1008>, 1369 <&cpg 1008>, <&cpg 1009>,
1376 <&cpg 1010>, 1370 <&cpg 1010>, <&cpg 1011>,
1377 <&cpg 1012>, 1371 <&cpg 1012>, <&cpg 1013>,
1378 <&cpg 1014>, 1372 <&cpg 1014>, <&cpg 1015>;
1379 reset-names = "ssi-al 1373 reset-names = "ssi-all",
1380 "ssi.9" 1374 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1381 "ssi.5" 1375 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1382 "ssi.1" 1376 "ssi.1", "ssi.0";
1383 status = "disabled"; 1377 status = "disabled";
1384 1378
1385 rcar_sound,ctu { 1379 rcar_sound,ctu {
1386 ctu00: ctu-0 1380 ctu00: ctu-0 { };
1387 ctu01: ctu-1 1381 ctu01: ctu-1 { };
1388 ctu02: ctu-2 1382 ctu02: ctu-2 { };
1389 ctu03: ctu-3 1383 ctu03: ctu-3 { };
1390 ctu10: ctu-4 1384 ctu10: ctu-4 { };
1391 ctu11: ctu-5 1385 ctu11: ctu-5 { };
1392 ctu12: ctu-6 1386 ctu12: ctu-6 { };
1393 ctu13: ctu-7 1387 ctu13: ctu-7 { };
1394 }; 1388 };
1395 1389
1396 rcar_sound,dvc { 1390 rcar_sound,dvc {
1397 dvc0: dvc-0 { 1391 dvc0: dvc-0 {
1398 dmas 1392 dmas = <&audma0 0xbc>;
1399 dma-n 1393 dma-names = "tx";
1400 }; 1394 };
1401 dvc1: dvc-1 { 1395 dvc1: dvc-1 {
1402 dmas 1396 dmas = <&audma0 0xbe>;
1403 dma-n 1397 dma-names = "tx";
1404 }; 1398 };
1405 }; 1399 };
1406 1400
1407 rcar_sound,mix { 1401 rcar_sound,mix {
1408 mix0: mix-0 { 1402 mix0: mix-0 { };
1409 mix1: mix-1 { 1403 mix1: mix-1 { };
1410 }; 1404 };
1411 1405
1412 rcar_sound,src { 1406 rcar_sound,src {
1413 src0: src-0 { 1407 src0: src-0 {
1414 inter 1408 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1415 dmas 1409 dmas = <&audma0 0x85>, <&audma0 0x9a>;
1416 dma-n 1410 dma-names = "rx", "tx";
1417 }; 1411 };
1418 src1: src-1 { 1412 src1: src-1 {
1419 inter 1413 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1420 dmas 1414 dmas = <&audma0 0x87>, <&audma0 0x9c>;
1421 dma-n 1415 dma-names = "rx", "tx";
1422 }; 1416 };
1423 src2: src-2 { 1417 src2: src-2 {
1424 inter 1418 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1425 dmas 1419 dmas = <&audma0 0x89>, <&audma0 0x9e>;
1426 dma-n 1420 dma-names = "rx", "tx";
1427 }; 1421 };
1428 src3: src-3 { 1422 src3: src-3 {
1429 inter 1423 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1430 dmas 1424 dmas = <&audma0 0x8b>, <&audma0 0xa0>;
1431 dma-n 1425 dma-names = "rx", "tx";
1432 }; 1426 };
1433 src4: src-4 { 1427 src4: src-4 {
1434 inter 1428 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1435 dmas 1429 dmas = <&audma0 0x8d>, <&audma0 0xb0>;
1436 dma-n 1430 dma-names = "rx", "tx";
1437 }; 1431 };
1438 src5: src-5 { 1432 src5: src-5 {
1439 inter 1433 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1440 dmas 1434 dmas = <&audma0 0x8f>, <&audma0 0xb2>;
1441 dma-n 1435 dma-names = "rx", "tx";
1442 }; 1436 };
1443 src6: src-6 { 1437 src6: src-6 {
1444 inter 1438 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1445 dmas 1439 dmas = <&audma0 0x91>, <&audma0 0xb4>;
1446 dma-n 1440 dma-names = "rx", "tx";
1447 }; 1441 };
1448 src7: src-7 { 1442 src7: src-7 {
1449 inter 1443 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1450 dmas 1444 dmas = <&audma0 0x93>, <&audma0 0xb6>;
1451 dma-n 1445 dma-names = "rx", "tx";
1452 }; 1446 };
1453 src8: src-8 { 1447 src8: src-8 {
1454 inter 1448 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1455 dmas 1449 dmas = <&audma0 0x95>, <&audma0 0xb8>;
1456 dma-n 1450 dma-names = "rx", "tx";
1457 }; 1451 };
1458 src9: src-9 { 1452 src9: src-9 {
1459 inter 1453 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
1460 dmas 1454 dmas = <&audma0 0x97>, <&audma0 0xba>;
1461 dma-n 1455 dma-names = "rx", "tx";
1462 }; 1456 };
1463 }; 1457 };
1464 1458
1465 rcar_sound,ssi { 1459 rcar_sound,ssi {
1466 ssi0: ssi-0 { 1460 ssi0: ssi-0 {
1467 inter 1461 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
1468 dmas 1462 dmas = <&audma0 0x01>, <&audma0 0x02>,
1469 1463 <&audma0 0x15>, <&audma0 0x16>;
1470 dma-n 1464 dma-names = "rx", "tx", "rxu", "txu";
1471 }; 1465 };
1472 ssi1: ssi-1 { 1466 ssi1: ssi-1 {
1473 inter 1467 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
1474 dmas 1468 dmas = <&audma0 0x03>, <&audma0 0x04>,
1475 1469 <&audma0 0x49>, <&audma0 0x4a>;
1476 dma-n 1470 dma-names = "rx", "tx", "rxu", "txu";
1477 }; 1471 };
1478 ssi2: ssi-2 { 1472 ssi2: ssi-2 {
1479 inter 1473 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
1480 dmas 1474 dmas = <&audma0 0x05>, <&audma0 0x06>,
1481 1475 <&audma0 0x63>, <&audma0 0x64>;
1482 dma-n 1476 dma-names = "rx", "tx", "rxu", "txu";
1483 }; 1477 };
1484 ssi3: ssi-3 { 1478 ssi3: ssi-3 {
1485 inter 1479 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1486 dmas 1480 dmas = <&audma0 0x07>, <&audma0 0x08>,
1487 1481 <&audma0 0x6f>, <&audma0 0x70>;
1488 dma-n 1482 dma-names = "rx", "tx", "rxu", "txu";
1489 }; 1483 };
1490 ssi4: ssi-4 { 1484 ssi4: ssi-4 {
1491 inter 1485 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1492 dmas 1486 dmas = <&audma0 0x09>, <&audma0 0x0a>,
1493 1487 <&audma0 0x71>, <&audma0 0x72>;
1494 dma-n 1488 dma-names = "rx", "tx", "rxu", "txu";
1495 }; 1489 };
1496 ssi5: ssi-5 { 1490 ssi5: ssi-5 {
1497 inter 1491 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1498 dmas 1492 dmas = <&audma0 0x0b>, <&audma0 0x0c>,
1499 1493 <&audma0 0x73>, <&audma0 0x74>;
1500 dma-n 1494 dma-names = "rx", "tx", "rxu", "txu";
1501 }; 1495 };
1502 ssi6: ssi-6 { 1496 ssi6: ssi-6 {
1503 inter 1497 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
1504 dmas 1498 dmas = <&audma0 0x0d>, <&audma0 0x0e>,
1505 1499 <&audma0 0x75>, <&audma0 0x76>;
1506 dma-n 1500 dma-names = "rx", "tx", "rxu", "txu";
1507 }; 1501 };
1508 ssi7: ssi-7 { 1502 ssi7: ssi-7 {
1509 inter 1503 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
1510 dmas 1504 dmas = <&audma0 0x0f>, <&audma0 0x10>,
1511 1505 <&audma0 0x79>, <&audma0 0x7a>;
1512 dma-n 1506 dma-names = "rx", "tx", "rxu", "txu";
1513 }; 1507 };
1514 ssi8: ssi-8 { 1508 ssi8: ssi-8 {
1515 inter 1509 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
1516 dmas 1510 dmas = <&audma0 0x11>, <&audma0 0x12>,
1517 1511 <&audma0 0x7b>, <&audma0 0x7c>;
1518 dma-n 1512 dma-names = "rx", "tx", "rxu", "txu";
1519 }; 1513 };
1520 ssi9: ssi-9 { 1514 ssi9: ssi-9 {
1521 inter 1515 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
1522 dmas 1516 dmas = <&audma0 0x13>, <&audma0 0x14>,
1523 1517 <&audma0 0x7d>, <&audma0 0x7e>;
1524 dma-n 1518 dma-names = "rx", "tx", "rxu", "txu";
1525 }; 1519 };
1526 }; 1520 };
1527 }; 1521 };
1528 1522
1529 audma0: dma-controller@ec7000 1523 audma0: dma-controller@ec700000 {
1530 compatible = "renesas 1524 compatible = "renesas,dmac-r8a774c0",
1531 "renesas 1525 "renesas,rcar-dmac";
1532 reg = <0 0xec700000 0 1526 reg = <0 0xec700000 0 0x10000>;
1533 interrupts = <GIC_SPI 1527 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
1534 <GIC_SPI 1528 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
1535 <GIC_SPI 1529 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
1536 <GIC_SPI 1530 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
1537 <GIC_SPI 1531 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
1538 <GIC_SPI 1532 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
1539 <GIC_SPI 1533 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
1540 <GIC_SPI 1534 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
1541 <GIC_SPI 1535 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
1542 <GIC_SPI 1536 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
1543 <GIC_SPI 1537 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1544 <GIC_SPI 1538 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
1545 <GIC_SPI 1539 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
1546 <GIC_SPI 1540 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
1547 <GIC_SPI 1541 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
1548 <GIC_SPI 1542 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1549 <GIC_SPI 1543 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
1550 interrupt-names = "er 1544 interrupt-names = "error",
1551 "ch0" 1545 "ch0", "ch1", "ch2", "ch3",
1552 "ch4" 1546 "ch4", "ch5", "ch6", "ch7",
1553 "ch8" 1547 "ch8", "ch9", "ch10", "ch11",
1554 "ch12 1548 "ch12", "ch13", "ch14", "ch15";
1555 clocks = <&cpg CPG_MO 1549 clocks = <&cpg CPG_MOD 502>;
1556 clock-names = "fck"; 1550 clock-names = "fck";
1557 power-domains = <&sys 1551 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1558 resets = <&cpg 502>; 1552 resets = <&cpg 502>;
1559 #dma-cells = <1>; 1553 #dma-cells = <1>;
1560 dma-channels = <16>; 1554 dma-channels = <16>;
1561 iommus = <&ipmmu_mp 0 1555 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
1562 <&ipmmu_mp 2 1556 <&ipmmu_mp 2>, <&ipmmu_mp 3>,
1563 <&ipmmu_mp 4 1557 <&ipmmu_mp 4>, <&ipmmu_mp 5>,
1564 <&ipmmu_mp 6 1558 <&ipmmu_mp 6>, <&ipmmu_mp 7>,
1565 <&ipmmu_mp 8 1559 <&ipmmu_mp 8>, <&ipmmu_mp 9>,
1566 <&ipmmu_mp 1 1560 <&ipmmu_mp 10>, <&ipmmu_mp 11>,
1567 <&ipmmu_mp 1 1561 <&ipmmu_mp 12>, <&ipmmu_mp 13>,
1568 <&ipmmu_mp 1 1562 <&ipmmu_mp 14>, <&ipmmu_mp 15>;
1569 }; 1563 };
1570 1564
1571 xhci0: usb@ee000000 { 1565 xhci0: usb@ee000000 {
1572 compatible = "renesas 1566 compatible = "renesas,xhci-r8a774c0",
1573 "renesas 1567 "renesas,rcar-gen3-xhci";
1574 reg = <0 0xee000000 0 1568 reg = <0 0xee000000 0 0xc00>;
1575 interrupts = <GIC_SPI 1569 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1576 clocks = <&cpg CPG_MO 1570 clocks = <&cpg CPG_MOD 328>;
1577 power-domains = <&sys 1571 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1578 resets = <&cpg 328>; 1572 resets = <&cpg 328>;
1579 status = "disabled"; 1573 status = "disabled";
1580 }; 1574 };
1581 1575
1582 usb3_peri0: usb@ee020000 { 1576 usb3_peri0: usb@ee020000 {
1583 compatible = "renesas 1577 compatible = "renesas,r8a774c0-usb3-peri",
1584 "renesas 1578 "renesas,rcar-gen3-usb3-peri";
1585 reg = <0 0xee020000 0 1579 reg = <0 0xee020000 0 0x400>;
1586 interrupts = <GIC_SPI 1580 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1587 clocks = <&cpg CPG_MO 1581 clocks = <&cpg CPG_MOD 328>;
1588 power-domains = <&sys 1582 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1589 resets = <&cpg 328>; 1583 resets = <&cpg 328>;
1590 status = "disabled"; 1584 status = "disabled";
1591 }; 1585 };
1592 1586
1593 ohci0: usb@ee080000 { 1587 ohci0: usb@ee080000 {
1594 compatible = "generic 1588 compatible = "generic-ohci";
1595 reg = <0 0xee080000 0 1589 reg = <0 0xee080000 0 0x100>;
1596 interrupts = <GIC_SPI 1590 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1597 clocks = <&cpg CPG_MO 1591 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
1598 phys = <&usb2_phy0 1> 1592 phys = <&usb2_phy0 1>;
1599 phy-names = "usb"; 1593 phy-names = "usb";
1600 power-domains = <&sys 1594 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1601 resets = <&cpg 703>, 1595 resets = <&cpg 703>, <&cpg 704>;
1602 status = "disabled"; 1596 status = "disabled";
1603 }; 1597 };
1604 1598
1605 ehci0: usb@ee080100 { 1599 ehci0: usb@ee080100 {
1606 compatible = "generic 1600 compatible = "generic-ehci";
1607 reg = <0 0xee080100 0 1601 reg = <0 0xee080100 0 0x100>;
1608 interrupts = <GIC_SPI 1602 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1609 clocks = <&cpg CPG_MO 1603 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
1610 phys = <&usb2_phy0 2> 1604 phys = <&usb2_phy0 2>;
1611 phy-names = "usb"; 1605 phy-names = "usb";
1612 companion = <&ohci0>; 1606 companion = <&ohci0>;
1613 power-domains = <&sys 1607 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1614 resets = <&cpg 703>, 1608 resets = <&cpg 703>, <&cpg 704>;
1615 status = "disabled"; 1609 status = "disabled";
1616 }; 1610 };
1617 1611
1618 usb2_phy0: usb-phy@ee080200 { 1612 usb2_phy0: usb-phy@ee080200 {
1619 compatible = "renesas 1613 compatible = "renesas,usb2-phy-r8a774c0",
1620 "renesas 1614 "renesas,rcar-gen3-usb2-phy";
1621 reg = <0 0xee080200 0 1615 reg = <0 0xee080200 0 0x700>;
1622 interrupts = <GIC_SPI 1616 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1623 clocks = <&cpg CPG_MO 1617 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
1624 power-domains = <&sys 1618 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1625 resets = <&cpg 703>, 1619 resets = <&cpg 703>, <&cpg 704>;
1626 #phy-cells = <1>; 1620 #phy-cells = <1>;
1627 status = "disabled"; 1621 status = "disabled";
1628 }; 1622 };
1629 1623
1630 sdhi0: mmc@ee100000 { 1624 sdhi0: mmc@ee100000 {
1631 compatible = "renesas 1625 compatible = "renesas,sdhi-r8a774c0",
1632 "renesas 1626 "renesas,rcar-gen3-sdhi";
1633 reg = <0 0xee100000 0 1627 reg = <0 0xee100000 0 0x2000>;
1634 interrupts = <GIC_SPI 1628 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
1635 clocks = <&cpg CPG_MO !! 1629 clocks = <&cpg CPG_MOD 314>;
1636 clock-names = "core", <<
1637 max-frequency = <2000 1630 max-frequency = <200000000>;
1638 power-domains = <&sys 1631 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1639 resets = <&cpg 314>; 1632 resets = <&cpg 314>;
1640 iommus = <&ipmmu_ds1 <<
1641 status = "disabled"; 1633 status = "disabled";
1642 }; 1634 };
1643 1635
1644 sdhi1: mmc@ee120000 { 1636 sdhi1: mmc@ee120000 {
1645 compatible = "renesas 1637 compatible = "renesas,sdhi-r8a774c0",
1646 "renesas 1638 "renesas,rcar-gen3-sdhi";
1647 reg = <0 0xee120000 0 1639 reg = <0 0xee120000 0 0x2000>;
1648 interrupts = <GIC_SPI 1640 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
1649 clocks = <&cpg CPG_MO !! 1641 clocks = <&cpg CPG_MOD 313>;
1650 clock-names = "core", <<
1651 max-frequency = <2000 1642 max-frequency = <200000000>;
1652 power-domains = <&sys 1643 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1653 resets = <&cpg 313>; 1644 resets = <&cpg 313>;
1654 iommus = <&ipmmu_ds1 <<
1655 status = "disabled"; 1645 status = "disabled";
1656 }; 1646 };
1657 1647
1658 sdhi3: mmc@ee160000 { 1648 sdhi3: mmc@ee160000 {
1659 compatible = "renesas 1649 compatible = "renesas,sdhi-r8a774c0",
1660 "renesas 1650 "renesas,rcar-gen3-sdhi";
1661 reg = <0 0xee160000 0 1651 reg = <0 0xee160000 0 0x2000>;
1662 interrupts = <GIC_SPI 1652 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
1663 clocks = <&cpg CPG_MO !! 1653 clocks = <&cpg CPG_MOD 311>;
1664 clock-names = "core", <<
1665 max-frequency = <2000 1654 max-frequency = <200000000>;
1666 power-domains = <&sys 1655 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1667 resets = <&cpg 311>; 1656 resets = <&cpg 311>;
1668 iommus = <&ipmmu_ds1 <<
1669 status = "disabled"; 1657 status = "disabled";
1670 }; 1658 };
1671 1659
1672 rpc: spi@ee200000 { 1660 rpc: spi@ee200000 {
1673 compatible = "renesas 1661 compatible = "renesas,r8a774c0-rpc-if",
1674 "renesas 1662 "renesas,rcar-gen3-rpc-if";
1675 reg = <0 0xee200000 0 1663 reg = <0 0xee200000 0 0x200>,
1676 <0 0x08000000 0 1664 <0 0x08000000 0 0x4000000>,
1677 <0 0xee208000 0 1665 <0 0xee208000 0 0x100>;
1678 reg-names = "regs", " 1666 reg-names = "regs", "dirmap", "wbuf";
1679 interrupts = <GIC_SPI 1667 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
1680 clocks = <&cpg CPG_MO 1668 clocks = <&cpg CPG_MOD 917>;
>> 1669 clock-names = "rpc";
1681 power-domains = <&sys 1670 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1682 resets = <&cpg 917>; 1671 resets = <&cpg 917>;
1683 #address-cells = <1>; 1672 #address-cells = <1>;
1684 #size-cells = <0>; 1673 #size-cells = <0>;
1685 status = "disabled"; 1674 status = "disabled";
1686 }; 1675 };
1687 1676
1688 gic: interrupt-controller@f10 1677 gic: interrupt-controller@f1010000 {
1689 compatible = "arm,gic 1678 compatible = "arm,gic-400";
1690 #interrupt-cells = <3 1679 #interrupt-cells = <3>;
1691 #address-cells = <0>; 1680 #address-cells = <0>;
1692 interrupt-controller; 1681 interrupt-controller;
1693 reg = <0x0 0xf1010000 1682 reg = <0x0 0xf1010000 0 0x1000>,
1694 <0x0 0xf1020000 1683 <0x0 0xf1020000 0 0x20000>,
1695 <0x0 0xf1040000 1684 <0x0 0xf1040000 0 0x20000>,
1696 <0x0 0xf1060000 1685 <0x0 0xf1060000 0 0x20000>;
1697 interrupts = <GIC_PPI 1686 interrupts = <GIC_PPI 9
1698 (GIC_ 1687 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
1699 clocks = <&cpg CPG_MO 1688 clocks = <&cpg CPG_MOD 408>;
1700 clock-names = "clk"; 1689 clock-names = "clk";
1701 power-domains = <&sys 1690 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1702 resets = <&cpg 408>; 1691 resets = <&cpg 408>;
1703 }; 1692 };
1704 1693
1705 pciec0: pcie@fe000000 { 1694 pciec0: pcie@fe000000 {
1706 compatible = "renesas 1695 compatible = "renesas,pcie-r8a774c0",
1707 "renesas 1696 "renesas,pcie-rcar-gen3";
1708 reg = <0 0xfe000000 0 1697 reg = <0 0xfe000000 0 0x80000>;
1709 #address-cells = <3>; 1698 #address-cells = <3>;
1710 #size-cells = <2>; 1699 #size-cells = <2>;
1711 bus-range = <0x00 0xf 1700 bus-range = <0x00 0xff>;
1712 device_type = "pci"; 1701 device_type = "pci";
1713 ranges = <0x01000000 1702 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
1714 <0x02000000 1703 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
1715 <0x02000000 1704 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
1716 <0x42000000 1705 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1717 /* Map all possible D !! 1706 /* Map all possible DDR as inbound ranges */
1718 dma-ranges = <0x42000 !! 1707 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;
1719 interrupts = <GIC_SPI 1708 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1720 <GIC_SPI 1709 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1721 <GIC_SPI 1710 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1722 #interrupt-cells = <1 1711 #interrupt-cells = <1>;
1723 interrupt-map-mask = 1712 interrupt-map-mask = <0 0 0 0>;
1724 interrupt-map = <0 0 1713 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1725 clocks = <&cpg CPG_MO 1714 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
1726 clock-names = "pcie", 1715 clock-names = "pcie", "pcie_bus";
1727 power-domains = <&sys 1716 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1728 resets = <&cpg 319>; 1717 resets = <&cpg 319>;
1729 iommu-map = <0 &ipmmu <<
1730 iommu-map-mask = <0>; <<
1731 status = "disabled"; 1718 status = "disabled";
1732 }; 1719 };
1733 1720
1734 pciec0_ep: pcie-ep@fe000000 { 1721 pciec0_ep: pcie-ep@fe000000 {
1735 compatible = "renesas 1722 compatible = "renesas,r8a774c0-pcie-ep",
1736 "renesas 1723 "renesas,rcar-gen3-pcie-ep";
1737 reg = <0x0 0xfe000000 1724 reg = <0x0 0xfe000000 0 0x80000>,
1738 <0x0 0xfe100000 1725 <0x0 0xfe100000 0 0x100000>,
1739 <0x0 0xfe200000 1726 <0x0 0xfe200000 0 0x200000>,
1740 <0x0 0x30000000 1727 <0x0 0x30000000 0 0x8000000>,
1741 <0x0 0x38000000 1728 <0x0 0x38000000 0 0x8000000>;
1742 reg-names = "apb-base 1729 reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
1743 interrupts = <GIC_SPI 1730 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1744 <GIC_SPI 1731 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1745 <GIC_SPI 1732 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1746 clocks = <&cpg CPG_MO 1733 clocks = <&cpg CPG_MOD 319>;
1747 clock-names = "pcie"; 1734 clock-names = "pcie";
1748 resets = <&cpg 319>; 1735 resets = <&cpg 319>;
1749 power-domains = <&sys 1736 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1750 status = "disabled"; 1737 status = "disabled";
1751 }; 1738 };
1752 1739
1753 vspb0: vsp@fe960000 { 1740 vspb0: vsp@fe960000 {
1754 compatible = "renesas 1741 compatible = "renesas,vsp2";
1755 reg = <0 0xfe960000 0 1742 reg = <0 0xfe960000 0 0x8000>;
1756 interrupts = <GIC_SPI 1743 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
1757 clocks = <&cpg CPG_MO 1744 clocks = <&cpg CPG_MOD 626>;
1758 power-domains = <&sys 1745 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1759 resets = <&cpg 626>; 1746 resets = <&cpg 626>;
1760 renesas,fcp = <&fcpvb 1747 renesas,fcp = <&fcpvb0>;
1761 }; 1748 };
1762 1749
1763 vspd0: vsp@fea20000 { 1750 vspd0: vsp@fea20000 {
1764 compatible = "renesas 1751 compatible = "renesas,vsp2";
1765 reg = <0 0xfea20000 0 1752 reg = <0 0xfea20000 0 0x7000>;
1766 interrupts = <GIC_SPI 1753 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
1767 clocks = <&cpg CPG_MO 1754 clocks = <&cpg CPG_MOD 623>;
1768 power-domains = <&sys 1755 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1769 resets = <&cpg 623>; 1756 resets = <&cpg 623>;
1770 renesas,fcp = <&fcpvd 1757 renesas,fcp = <&fcpvd0>;
1771 }; 1758 };
1772 1759
1773 vspd1: vsp@fea28000 { 1760 vspd1: vsp@fea28000 {
1774 compatible = "renesas 1761 compatible = "renesas,vsp2";
1775 reg = <0 0xfea28000 0 1762 reg = <0 0xfea28000 0 0x7000>;
1776 interrupts = <GIC_SPI 1763 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
1777 clocks = <&cpg CPG_MO 1764 clocks = <&cpg CPG_MOD 622>;
1778 power-domains = <&sys 1765 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1779 resets = <&cpg 622>; 1766 resets = <&cpg 622>;
1780 renesas,fcp = <&fcpvd 1767 renesas,fcp = <&fcpvd1>;
1781 }; 1768 };
1782 1769
1783 vspi0: vsp@fe9a0000 { 1770 vspi0: vsp@fe9a0000 {
1784 compatible = "renesas 1771 compatible = "renesas,vsp2";
1785 reg = <0 0xfe9a0000 0 1772 reg = <0 0xfe9a0000 0 0x8000>;
1786 interrupts = <GIC_SPI 1773 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
1787 clocks = <&cpg CPG_MO 1774 clocks = <&cpg CPG_MOD 631>;
1788 power-domains = <&sys 1775 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1789 resets = <&cpg 631>; 1776 resets = <&cpg 631>;
1790 renesas,fcp = <&fcpvi 1777 renesas,fcp = <&fcpvi0>;
1791 }; 1778 };
1792 1779
1793 fcpvb0: fcp@fe96f000 { 1780 fcpvb0: fcp@fe96f000 {
1794 compatible = "renesas 1781 compatible = "renesas,fcpv";
1795 reg = <0 0xfe96f000 0 1782 reg = <0 0xfe96f000 0 0x200>;
1796 clocks = <&cpg CPG_MO 1783 clocks = <&cpg CPG_MOD 607>;
1797 power-domains = <&sys 1784 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1798 resets = <&cpg 607>; 1785 resets = <&cpg 607>;
1799 iommus = <&ipmmu_vp0 1786 iommus = <&ipmmu_vp0 5>;
1800 }; 1787 };
1801 1788
1802 fcpvd0: fcp@fea27000 { 1789 fcpvd0: fcp@fea27000 {
1803 compatible = "renesas 1790 compatible = "renesas,fcpv";
1804 reg = <0 0xfea27000 0 1791 reg = <0 0xfea27000 0 0x200>;
1805 clocks = <&cpg CPG_MO 1792 clocks = <&cpg CPG_MOD 603>;
1806 power-domains = <&sys 1793 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1807 resets = <&cpg 603>; 1794 resets = <&cpg 603>;
1808 iommus = <&ipmmu_vi0 1795 iommus = <&ipmmu_vi0 8>;
1809 }; 1796 };
1810 1797
1811 fcpvd1: fcp@fea2f000 { 1798 fcpvd1: fcp@fea2f000 {
1812 compatible = "renesas 1799 compatible = "renesas,fcpv";
1813 reg = <0 0xfea2f000 0 1800 reg = <0 0xfea2f000 0 0x200>;
1814 clocks = <&cpg CPG_MO 1801 clocks = <&cpg CPG_MOD 602>;
1815 power-domains = <&sys 1802 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1816 resets = <&cpg 602>; 1803 resets = <&cpg 602>;
1817 iommus = <&ipmmu_vi0 1804 iommus = <&ipmmu_vi0 9>;
1818 }; 1805 };
1819 1806
1820 fcpvi0: fcp@fe9af000 { 1807 fcpvi0: fcp@fe9af000 {
1821 compatible = "renesas 1808 compatible = "renesas,fcpv";
1822 reg = <0 0xfe9af000 0 1809 reg = <0 0xfe9af000 0 0x200>;
1823 clocks = <&cpg CPG_MO 1810 clocks = <&cpg CPG_MOD 611>;
1824 power-domains = <&sys 1811 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1825 resets = <&cpg 611>; 1812 resets = <&cpg 611>;
1826 iommus = <&ipmmu_vp0 1813 iommus = <&ipmmu_vp0 8>;
1827 }; 1814 };
1828 1815
1829 csi40: csi2@feaa0000 { 1816 csi40: csi2@feaa0000 {
1830 compatible = "renesas 1817 compatible = "renesas,r8a774c0-csi2";
1831 reg = <0 0xfeaa0000 0 1818 reg = <0 0xfeaa0000 0 0x10000>;
1832 interrupts = <GIC_SPI 1819 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
1833 clocks = <&cpg CPG_MO 1820 clocks = <&cpg CPG_MOD 716>;
1834 power-domains = <&sys 1821 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1835 resets = <&cpg 716>; 1822 resets = <&cpg 716>;
1836 status = "disabled"; 1823 status = "disabled";
1837 1824
1838 ports { 1825 ports {
1839 #address-cell 1826 #address-cells = <1>;
1840 #size-cells = 1827 #size-cells = <0>;
1841 1828
1842 port@0 { 1829 port@0 {
1843 reg = 1830 reg = <0>;
1844 }; 1831 };
1845 1832
1846 port@1 { 1833 port@1 {
1847 #addr 1834 #address-cells = <1>;
1848 #size 1835 #size-cells = <0>;
1849 1836
1850 reg = 1837 reg = <1>;
1851 1838
1852 csi40 1839 csi40vin4: endpoint@0 {
1853 1840 reg = <0>;
1854 1841 remote-endpoint = <&vin4csi40>;
1855 }; 1842 };
1856 csi40 1843 csi40vin5: endpoint@1 {
1857 1844 reg = <1>;
1858 1845 remote-endpoint = <&vin5csi40>;
1859 }; 1846 };
1860 }; 1847 };
1861 }; 1848 };
1862 }; 1849 };
1863 1850
1864 du: display@feb00000 { 1851 du: display@feb00000 {
1865 compatible = "renesas 1852 compatible = "renesas,du-r8a774c0";
1866 reg = <0 0xfeb00000 0 1853 reg = <0 0xfeb00000 0 0x40000>;
1867 interrupts = <GIC_SPI 1854 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
1868 <GIC_SPI 1855 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
1869 clocks = <&cpg CPG_MO 1856 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
1870 clock-names = "du.0", 1857 clock-names = "du.0", "du.1";
1871 resets = <&cpg 724>; 1858 resets = <&cpg 724>;
1872 reset-names = "du.0"; 1859 reset-names = "du.0";
1873 renesas,vsps = <&vspd 1860 renesas,vsps = <&vspd0 0>, <&vspd1 0>;
1874 1861
1875 status = "disabled"; 1862 status = "disabled";
1876 1863
1877 ports { 1864 ports {
1878 #address-cell 1865 #address-cells = <1>;
1879 #size-cells = 1866 #size-cells = <0>;
1880 1867
1881 port@0 { 1868 port@0 {
1882 reg = 1869 reg = <0>;
>> 1870 du_out_rgb: endpoint {
>> 1871 };
1883 }; 1872 };
1884 1873
1885 port@1 { 1874 port@1 {
1886 reg = 1875 reg = <1>;
1887 du_ou 1876 du_out_lvds0: endpoint {
1888 1877 remote-endpoint = <&lvds0_in>;
1889 }; 1878 };
1890 }; 1879 };
1891 1880
1892 port@2 { 1881 port@2 {
1893 reg = 1882 reg = <2>;
1894 du_ou 1883 du_out_lvds1: endpoint {
1895 1884 remote-endpoint = <&lvds1_in>;
1896 }; 1885 };
1897 }; 1886 };
1898 }; 1887 };
1899 }; 1888 };
1900 1889
1901 lvds0: lvds-encoder@feb90000 1890 lvds0: lvds-encoder@feb90000 {
1902 compatible = "renesas 1891 compatible = "renesas,r8a774c0-lvds";
1903 reg = <0 0xfeb90000 0 1892 reg = <0 0xfeb90000 0 0x20>;
1904 clocks = <&cpg CPG_MO 1893 clocks = <&cpg CPG_MOD 727>;
1905 power-domains = <&sys 1894 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1906 resets = <&cpg 727>; 1895 resets = <&cpg 727>;
1907 status = "disabled"; 1896 status = "disabled";
1908 1897
1909 renesas,companion = < 1898 renesas,companion = <&lvds1>;
1910 1899
1911 ports { 1900 ports {
1912 #address-cell 1901 #address-cells = <1>;
1913 #size-cells = 1902 #size-cells = <0>;
1914 1903
1915 port@0 { 1904 port@0 {
1916 reg = 1905 reg = <0>;
1917 lvds0 1906 lvds0_in: endpoint {
1918 1907 remote-endpoint = <&du_out_lvds0>;
1919 }; 1908 };
1920 }; 1909 };
1921 1910
1922 port@1 { 1911 port@1 {
1923 reg = 1912 reg = <1>;
>> 1913 lvds0_out: endpoint {
>> 1914 };
1924 }; 1915 };
1925 }; 1916 };
1926 }; 1917 };
1927 1918
1928 lvds1: lvds-encoder@feb90100 1919 lvds1: lvds-encoder@feb90100 {
1929 compatible = "renesas 1920 compatible = "renesas,r8a774c0-lvds";
1930 reg = <0 0xfeb90100 0 1921 reg = <0 0xfeb90100 0 0x20>;
1931 clocks = <&cpg CPG_MO 1922 clocks = <&cpg CPG_MOD 727>;
1932 power-domains = <&sys 1923 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1933 resets = <&cpg 726>; 1924 resets = <&cpg 726>;
1934 status = "disabled"; 1925 status = "disabled";
1935 1926
1936 ports { 1927 ports {
1937 #address-cell 1928 #address-cells = <1>;
1938 #size-cells = 1929 #size-cells = <0>;
1939 1930
1940 port@0 { 1931 port@0 {
1941 reg = 1932 reg = <0>;
1942 lvds1 1933 lvds1_in: endpoint {
1943 1934 remote-endpoint = <&du_out_lvds1>;
1944 }; 1935 };
1945 }; 1936 };
1946 1937
1947 port@1 { 1938 port@1 {
1948 reg = 1939 reg = <1>;
>> 1940 lvds1_out: endpoint {
>> 1941 };
1949 }; 1942 };
1950 }; 1943 };
1951 }; 1944 };
1952 1945
1953 prr: chipid@fff00044 { 1946 prr: chipid@fff00044 {
1954 compatible = "renesas 1947 compatible = "renesas,prr";
1955 reg = <0 0xfff00044 0 1948 reg = <0 0xfff00044 0 4>;
1956 }; 1949 };
1957 }; 1950 };
1958 1951
1959 thermal-zones { 1952 thermal-zones {
1960 cpu-thermal { 1953 cpu-thermal {
1961 polling-delay-passive 1954 polling-delay-passive = <250>;
1962 polling-delay = <0>; 1955 polling-delay = <0>;
1963 thermal-sensors = <&t !! 1956 thermal-sensors = <&thermal 0>;
1964 sustainable-power = < 1957 sustainable-power = <717>;
1965 1958
1966 cooling-maps { 1959 cooling-maps {
1967 map0 { 1960 map0 {
1968 trip 1961 trip = <&target>;
1969 cooli 1962 cooling-device = <&a53_0 0 2>;
1970 contr 1963 contribution = <1024>;
1971 }; 1964 };
1972 }; 1965 };
1973 1966
1974 trips { 1967 trips {
1975 sensor1_crit: 1968 sensor1_crit: sensor1-crit {
1976 tempe 1969 temperature = <120000>;
1977 hyste 1970 hysteresis = <2000>;
1978 type 1971 type = "critical";
1979 }; 1972 };
1980 1973
1981 target: trip- 1974 target: trip-point1 {
1982 tempe 1975 temperature = <100000>;
1983 hyste 1976 hysteresis = <2000>;
1984 type 1977 type = "passive";
1985 }; 1978 };
1986 }; 1979 };
1987 }; 1980 };
1988 }; 1981 };
1989 1982
1990 timer { 1983 timer {
1991 compatible = "arm,armv8-timer 1984 compatible = "arm,armv8-timer";
1992 interrupts-extended = <&gic G 1985 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1993 <&gic G 1986 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1994 <&gic G 1987 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1995 <&gic G 1988 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
1996 interrupt-names = "sec-phys", <<
1997 }; 1989 };
1998 1990
1999 /* External USB clocks - can be overr 1991 /* External USB clocks - can be overridden by the board */
2000 usb3s0_clk: usb3s0 { 1992 usb3s0_clk: usb3s0 {
2001 compatible = "fixed-clock"; 1993 compatible = "fixed-clock";
2002 #clock-cells = <0>; 1994 #clock-cells = <0>;
2003 clock-frequency = <0>; 1995 clock-frequency = <0>;
2004 }; 1996 };
2005 1997
2006 usb_extal_clk: usb_extal { 1998 usb_extal_clk: usb_extal {
2007 compatible = "fixed-clock"; 1999 compatible = "fixed-clock";
2008 #clock-cells = <0>; 2000 #clock-cells = <0>;
2009 clock-frequency = <0>; 2001 clock-frequency = <0>;
2010 }; 2002 };
2011 }; 2003 };
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