1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * Device Tree Source for the RZ/G2E (R8A774C0 3 * Device Tree Source for the RZ/G2E (R8A774C0) SoC
4 * 4 *
5 * Copyright (C) 2018-2019 Renesas Electronics 5 * Copyright (C) 2018-2019 Renesas Electronics Corp.
6 */ 6 */
7 7
8 #include <dt-bindings/clock/r8a774c0-cpg-mssr. 8 #include <dt-bindings/clock/r8a774c0-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm 9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a774c0-sysc.h> 10 #include <dt-bindings/power/r8a774c0-sysc.h>
11 11
12 / { 12 / {
13 compatible = "renesas,r8a774c0"; 13 compatible = "renesas,r8a774c0";
14 #address-cells = <2>; 14 #address-cells = <2>;
15 #size-cells = <2>; 15 #size-cells = <2>;
16 16
17 /* 17 /*
18 * The external audio clocks are confi 18 * The external audio clocks are configured as 0 Hz fixed frequency
19 * clocks by default. 19 * clocks by default.
20 * Boards that provide audio clocks sh 20 * Boards that provide audio clocks should override them.
21 */ 21 */
22 audio_clk_a: audio_clk_a { 22 audio_clk_a: audio_clk_a {
23 compatible = "fixed-clock"; 23 compatible = "fixed-clock";
24 #clock-cells = <0>; 24 #clock-cells = <0>;
25 clock-frequency = <0>; 25 clock-frequency = <0>;
26 }; 26 };
27 27
28 audio_clk_b: audio_clk_b { 28 audio_clk_b: audio_clk_b {
29 compatible = "fixed-clock"; 29 compatible = "fixed-clock";
30 #clock-cells = <0>; 30 #clock-cells = <0>;
31 clock-frequency = <0>; 31 clock-frequency = <0>;
32 }; 32 };
33 33
34 audio_clk_c: audio_clk_c { 34 audio_clk_c: audio_clk_c {
35 compatible = "fixed-clock"; 35 compatible = "fixed-clock";
36 #clock-cells = <0>; 36 #clock-cells = <0>;
37 clock-frequency = <0>; 37 clock-frequency = <0>;
38 }; 38 };
39 39
40 /* External CAN clock - to be overridd 40 /* External CAN clock - to be overridden by boards that provide it */
41 can_clk: can { 41 can_clk: can {
42 compatible = "fixed-clock"; 42 compatible = "fixed-clock";
43 #clock-cells = <0>; 43 #clock-cells = <0>;
44 clock-frequency = <0>; 44 clock-frequency = <0>;
45 }; 45 };
46 46
47 cluster1_opp: opp-table-1 { !! 47 cluster1_opp: opp_table10 {
48 compatible = "operating-points 48 compatible = "operating-points-v2";
49 opp-shared; 49 opp-shared;
50 opp-800000000 { 50 opp-800000000 {
51 opp-hz = /bits/ 64 <80 51 opp-hz = /bits/ 64 <800000000>;
52 clock-latency-ns = <30 52 clock-latency-ns = <300000>;
53 }; 53 };
54 opp-1000000000 { 54 opp-1000000000 {
55 opp-hz = /bits/ 64 <10 55 opp-hz = /bits/ 64 <1000000000>;
56 clock-latency-ns = <30 56 clock-latency-ns = <300000>;
57 }; 57 };
58 opp-1200000000 { 58 opp-1200000000 {
59 opp-hz = /bits/ 64 <12 59 opp-hz = /bits/ 64 <1200000000>;
60 clock-latency-ns = <30 60 clock-latency-ns = <300000>;
61 opp-suspend; 61 opp-suspend;
62 }; 62 };
63 }; 63 };
64 64
65 cpus { 65 cpus {
66 #address-cells = <1>; 66 #address-cells = <1>;
67 #size-cells = <0>; 67 #size-cells = <0>;
68 68
69 a53_0: cpu@0 { 69 a53_0: cpu@0 {
70 compatible = "arm,cort 70 compatible = "arm,cortex-a53";
71 reg = <0>; 71 reg = <0>;
72 device_type = "cpu"; 72 device_type = "cpu";
73 #cooling-cells = <2>; <<
74 power-domains = <&sysc 73 power-domains = <&sysc R8A774C0_PD_CA53_CPU0>;
75 next-level-cache = <&L 74 next-level-cache = <&L2_CA53>;
76 enable-method = "psci" 75 enable-method = "psci";
77 dynamic-power-coeffici <<
78 clocks = <&cpg CPG_COR 76 clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>;
79 operating-points-v2 = 77 operating-points-v2 = <&cluster1_opp>;
80 }; 78 };
81 79
82 a53_1: cpu@1 { 80 a53_1: cpu@1 {
83 compatible = "arm,cort 81 compatible = "arm,cortex-a53";
84 reg = <1>; 82 reg = <1>;
85 device_type = "cpu"; 83 device_type = "cpu";
86 power-domains = <&sysc 84 power-domains = <&sysc R8A774C0_PD_CA53_CPU1>;
87 next-level-cache = <&L 85 next-level-cache = <&L2_CA53>;
88 enable-method = "psci" 86 enable-method = "psci";
89 clocks = <&cpg CPG_COR 87 clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>;
90 operating-points-v2 = 88 operating-points-v2 = <&cluster1_opp>;
91 }; 89 };
92 90
93 L2_CA53: cache-controller-0 { 91 L2_CA53: cache-controller-0 {
94 compatible = "cache"; 92 compatible = "cache";
95 power-domains = <&sysc 93 power-domains = <&sysc R8A774C0_PD_CA53_SCU>;
96 cache-unified; 94 cache-unified;
97 cache-level = <2>; 95 cache-level = <2>;
98 }; 96 };
99 }; 97 };
100 98
101 extal_clk: extal { 99 extal_clk: extal {
102 compatible = "fixed-clock"; 100 compatible = "fixed-clock";
103 #clock-cells = <0>; 101 #clock-cells = <0>;
104 /* This value must be overridd 102 /* This value must be overridden by the board */
105 clock-frequency = <0>; 103 clock-frequency = <0>;
106 }; 104 };
107 105
108 /* External PCIe clock - can be overri 106 /* External PCIe clock - can be overridden by the board */
109 pcie_bus_clk: pcie_bus { 107 pcie_bus_clk: pcie_bus {
110 compatible = "fixed-clock"; 108 compatible = "fixed-clock";
111 #clock-cells = <0>; 109 #clock-cells = <0>;
112 clock-frequency = <0>; 110 clock-frequency = <0>;
113 }; 111 };
114 112
115 pmu_a53 { 113 pmu_a53 {
116 compatible = "arm,cortex-a53-p 114 compatible = "arm,cortex-a53-pmu";
117 interrupts-extended = <&gic GI 115 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
118 <&gic GI 116 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
119 interrupt-affinity = <&a53_0>, 117 interrupt-affinity = <&a53_0>, <&a53_1>;
120 }; 118 };
121 119
122 psci { 120 psci {
123 compatible = "arm,psci-1.0", " 121 compatible = "arm,psci-1.0", "arm,psci-0.2";
124 method = "smc"; 122 method = "smc";
125 }; 123 };
126 124
127 /* External SCIF clock - to be overrid 125 /* External SCIF clock - to be overridden by boards that provide it */
128 scif_clk: scif { 126 scif_clk: scif {
129 compatible = "fixed-clock"; 127 compatible = "fixed-clock";
130 #clock-cells = <0>; 128 #clock-cells = <0>;
131 clock-frequency = <0>; 129 clock-frequency = <0>;
132 }; 130 };
133 131
134 soc: soc { 132 soc: soc {
135 compatible = "simple-bus"; 133 compatible = "simple-bus";
136 interrupt-parent = <&gic>; 134 interrupt-parent = <&gic>;
137 #address-cells = <2>; 135 #address-cells = <2>;
138 #size-cells = <2>; 136 #size-cells = <2>;
139 ranges; 137 ranges;
140 138
141 rwdt: watchdog@e6020000 { 139 rwdt: watchdog@e6020000 {
142 compatible = "renesas, 140 compatible = "renesas,r8a774c0-wdt",
143 "renesas, 141 "renesas,rcar-gen3-wdt";
144 reg = <0 0xe6020000 0 142 reg = <0 0xe6020000 0 0x0c>;
145 interrupts = <GIC_SPI <<
146 clocks = <&cpg CPG_MOD 143 clocks = <&cpg CPG_MOD 402>;
147 power-domains = <&sysc 144 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
148 resets = <&cpg 402>; 145 resets = <&cpg 402>;
149 status = "disabled"; 146 status = "disabled";
150 }; 147 };
151 148
152 gpio0: gpio@e6050000 { 149 gpio0: gpio@e6050000 {
153 compatible = "renesas, 150 compatible = "renesas,gpio-r8a774c0",
154 "renesas, 151 "renesas,rcar-gen3-gpio";
155 reg = <0 0xe6050000 0 152 reg = <0 0xe6050000 0 0x50>;
156 interrupts = <GIC_SPI 153 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
157 #gpio-cells = <2>; 154 #gpio-cells = <2>;
158 gpio-controller; 155 gpio-controller;
159 gpio-ranges = <&pfc 0 156 gpio-ranges = <&pfc 0 0 18>;
160 #interrupt-cells = <2> 157 #interrupt-cells = <2>;
161 interrupt-controller; 158 interrupt-controller;
162 clocks = <&cpg CPG_MOD 159 clocks = <&cpg CPG_MOD 912>;
163 power-domains = <&sysc 160 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
164 resets = <&cpg 912>; 161 resets = <&cpg 912>;
165 }; 162 };
166 163
167 gpio1: gpio@e6051000 { 164 gpio1: gpio@e6051000 {
168 compatible = "renesas, 165 compatible = "renesas,gpio-r8a774c0",
169 "renesas, 166 "renesas,rcar-gen3-gpio";
170 reg = <0 0xe6051000 0 167 reg = <0 0xe6051000 0 0x50>;
171 interrupts = <GIC_SPI 168 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
172 #gpio-cells = <2>; 169 #gpio-cells = <2>;
173 gpio-controller; 170 gpio-controller;
174 gpio-ranges = <&pfc 0 171 gpio-ranges = <&pfc 0 32 23>;
175 #interrupt-cells = <2> 172 #interrupt-cells = <2>;
176 interrupt-controller; 173 interrupt-controller;
177 clocks = <&cpg CPG_MOD 174 clocks = <&cpg CPG_MOD 911>;
178 power-domains = <&sysc 175 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
179 resets = <&cpg 911>; 176 resets = <&cpg 911>;
180 }; 177 };
181 178
182 gpio2: gpio@e6052000 { 179 gpio2: gpio@e6052000 {
183 compatible = "renesas, 180 compatible = "renesas,gpio-r8a774c0",
184 "renesas, 181 "renesas,rcar-gen3-gpio";
185 reg = <0 0xe6052000 0 182 reg = <0 0xe6052000 0 0x50>;
186 interrupts = <GIC_SPI 183 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
187 #gpio-cells = <2>; 184 #gpio-cells = <2>;
188 gpio-controller; 185 gpio-controller;
189 gpio-ranges = <&pfc 0 186 gpio-ranges = <&pfc 0 64 26>;
190 #interrupt-cells = <2> 187 #interrupt-cells = <2>;
191 interrupt-controller; 188 interrupt-controller;
192 clocks = <&cpg CPG_MOD 189 clocks = <&cpg CPG_MOD 910>;
193 power-domains = <&sysc 190 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
194 resets = <&cpg 910>; 191 resets = <&cpg 910>;
195 }; 192 };
196 193
197 gpio3: gpio@e6053000 { 194 gpio3: gpio@e6053000 {
198 compatible = "renesas, 195 compatible = "renesas,gpio-r8a774c0",
199 "renesas, 196 "renesas,rcar-gen3-gpio";
200 reg = <0 0xe6053000 0 197 reg = <0 0xe6053000 0 0x50>;
201 interrupts = <GIC_SPI 198 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
202 #gpio-cells = <2>; 199 #gpio-cells = <2>;
203 gpio-controller; 200 gpio-controller;
204 gpio-ranges = <&pfc 0 201 gpio-ranges = <&pfc 0 96 16>;
205 #interrupt-cells = <2> 202 #interrupt-cells = <2>;
206 interrupt-controller; 203 interrupt-controller;
207 clocks = <&cpg CPG_MOD 204 clocks = <&cpg CPG_MOD 909>;
208 power-domains = <&sysc 205 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
209 resets = <&cpg 909>; 206 resets = <&cpg 909>;
210 }; 207 };
211 208
212 gpio4: gpio@e6054000 { 209 gpio4: gpio@e6054000 {
213 compatible = "renesas, 210 compatible = "renesas,gpio-r8a774c0",
214 "renesas, 211 "renesas,rcar-gen3-gpio";
215 reg = <0 0xe6054000 0 212 reg = <0 0xe6054000 0 0x50>;
216 interrupts = <GIC_SPI 213 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
217 #gpio-cells = <2>; 214 #gpio-cells = <2>;
218 gpio-controller; 215 gpio-controller;
219 gpio-ranges = <&pfc 0 216 gpio-ranges = <&pfc 0 128 11>;
220 #interrupt-cells = <2> 217 #interrupt-cells = <2>;
221 interrupt-controller; 218 interrupt-controller;
222 clocks = <&cpg CPG_MOD 219 clocks = <&cpg CPG_MOD 908>;
223 power-domains = <&sysc 220 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
224 resets = <&cpg 908>; 221 resets = <&cpg 908>;
225 }; 222 };
226 223
227 gpio5: gpio@e6055000 { 224 gpio5: gpio@e6055000 {
228 compatible = "renesas, 225 compatible = "renesas,gpio-r8a774c0",
229 "renesas, 226 "renesas,rcar-gen3-gpio";
230 reg = <0 0xe6055000 0 227 reg = <0 0xe6055000 0 0x50>;
231 interrupts = <GIC_SPI 228 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
232 #gpio-cells = <2>; 229 #gpio-cells = <2>;
233 gpio-controller; 230 gpio-controller;
234 gpio-ranges = <&pfc 0 231 gpio-ranges = <&pfc 0 160 20>;
235 #interrupt-cells = <2> 232 #interrupt-cells = <2>;
236 interrupt-controller; 233 interrupt-controller;
237 clocks = <&cpg CPG_MOD 234 clocks = <&cpg CPG_MOD 907>;
238 power-domains = <&sysc 235 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
239 resets = <&cpg 907>; 236 resets = <&cpg 907>;
240 }; 237 };
241 238
242 gpio6: gpio@e6055400 { 239 gpio6: gpio@e6055400 {
243 compatible = "renesas, 240 compatible = "renesas,gpio-r8a774c0",
244 "renesas, 241 "renesas,rcar-gen3-gpio";
245 reg = <0 0xe6055400 0 242 reg = <0 0xe6055400 0 0x50>;
246 interrupts = <GIC_SPI 243 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
247 #gpio-cells = <2>; 244 #gpio-cells = <2>;
248 gpio-controller; 245 gpio-controller;
249 gpio-ranges = <&pfc 0 246 gpio-ranges = <&pfc 0 192 18>;
250 #interrupt-cells = <2> 247 #interrupt-cells = <2>;
251 interrupt-controller; 248 interrupt-controller;
252 clocks = <&cpg CPG_MOD 249 clocks = <&cpg CPG_MOD 906>;
253 power-domains = <&sysc 250 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
254 resets = <&cpg 906>; 251 resets = <&cpg 906>;
255 }; 252 };
256 253
257 pfc: pinctrl@e6060000 { !! 254 pfc: pin-controller@e6060000 {
258 compatible = "renesas, 255 compatible = "renesas,pfc-r8a774c0";
259 reg = <0 0xe6060000 0 256 reg = <0 0xe6060000 0 0x508>;
260 }; 257 };
261 258
262 cmt0: timer@e60f0000 { 259 cmt0: timer@e60f0000 {
263 compatible = "renesas, 260 compatible = "renesas,r8a774c0-cmt0",
264 "renesas, 261 "renesas,rcar-gen3-cmt0";
265 reg = <0 0xe60f0000 0 262 reg = <0 0xe60f0000 0 0x1004>;
266 interrupts = <GIC_SPI 263 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
267 <GIC_SPI 264 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
268 clocks = <&cpg CPG_MOD 265 clocks = <&cpg CPG_MOD 303>;
269 clock-names = "fck"; 266 clock-names = "fck";
270 power-domains = <&sysc 267 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
271 resets = <&cpg 303>; 268 resets = <&cpg 303>;
272 status = "disabled"; 269 status = "disabled";
273 }; 270 };
274 271
275 cmt1: timer@e6130000 { 272 cmt1: timer@e6130000 {
276 compatible = "renesas, 273 compatible = "renesas,r8a774c0-cmt1",
277 "renesas, 274 "renesas,rcar-gen3-cmt1";
278 reg = <0 0xe6130000 0 275 reg = <0 0xe6130000 0 0x1004>;
279 interrupts = <GIC_SPI 276 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
280 <GIC_SPI 277 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
281 <GIC_SPI 278 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
282 <GIC_SPI 279 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
283 <GIC_SPI 280 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
284 <GIC_SPI 281 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
285 <GIC_SPI 282 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
286 <GIC_SPI 283 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
287 clocks = <&cpg CPG_MOD 284 clocks = <&cpg CPG_MOD 302>;
288 clock-names = "fck"; 285 clock-names = "fck";
289 power-domains = <&sysc 286 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
290 resets = <&cpg 302>; 287 resets = <&cpg 302>;
291 status = "disabled"; 288 status = "disabled";
292 }; 289 };
293 290
294 cmt2: timer@e6140000 { 291 cmt2: timer@e6140000 {
295 compatible = "renesas, 292 compatible = "renesas,r8a774c0-cmt1",
296 "renesas, 293 "renesas,rcar-gen3-cmt1";
297 reg = <0 0xe6140000 0 294 reg = <0 0xe6140000 0 0x1004>;
298 interrupts = <GIC_SPI 295 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
299 <GIC_SPI 296 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
300 <GIC_SPI 297 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
301 <GIC_SPI 298 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
302 <GIC_SPI 299 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
303 <GIC_SPI 300 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
304 <GIC_SPI 301 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
305 <GIC_SPI 302 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
306 clocks = <&cpg CPG_MOD 303 clocks = <&cpg CPG_MOD 301>;
307 clock-names = "fck"; 304 clock-names = "fck";
308 power-domains = <&sysc 305 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
309 resets = <&cpg 301>; 306 resets = <&cpg 301>;
310 status = "disabled"; 307 status = "disabled";
311 }; 308 };
312 309
313 cmt3: timer@e6148000 { 310 cmt3: timer@e6148000 {
314 compatible = "renesas, 311 compatible = "renesas,r8a774c0-cmt1",
315 "renesas, 312 "renesas,rcar-gen3-cmt1";
316 reg = <0 0xe6148000 0 313 reg = <0 0xe6148000 0 0x1004>;
317 interrupts = <GIC_SPI 314 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
318 <GIC_SPI 315 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
319 <GIC_SPI 316 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
320 <GIC_SPI 317 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
321 <GIC_SPI 318 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
322 <GIC_SPI 319 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
323 <GIC_SPI 320 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
324 <GIC_SPI 321 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
325 clocks = <&cpg CPG_MOD 322 clocks = <&cpg CPG_MOD 300>;
326 clock-names = "fck"; 323 clock-names = "fck";
327 power-domains = <&sysc 324 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
328 resets = <&cpg 300>; 325 resets = <&cpg 300>;
329 status = "disabled"; 326 status = "disabled";
330 }; 327 };
331 328
332 cpg: clock-controller@e6150000 329 cpg: clock-controller@e6150000 {
333 compatible = "renesas, 330 compatible = "renesas,r8a774c0-cpg-mssr";
334 reg = <0 0xe6150000 0 331 reg = <0 0xe6150000 0 0x1000>;
335 clocks = <&extal_clk>; 332 clocks = <&extal_clk>;
336 clock-names = "extal"; 333 clock-names = "extal";
337 #clock-cells = <2>; 334 #clock-cells = <2>;
338 #power-domain-cells = 335 #power-domain-cells = <0>;
339 #reset-cells = <1>; 336 #reset-cells = <1>;
340 }; 337 };
341 338
342 rst: reset-controller@e6160000 339 rst: reset-controller@e6160000 {
343 compatible = "renesas, 340 compatible = "renesas,r8a774c0-rst";
344 reg = <0 0xe6160000 0 341 reg = <0 0xe6160000 0 0x0200>;
345 }; 342 };
346 343
347 sysc: system-controller@e61800 344 sysc: system-controller@e6180000 {
348 compatible = "renesas, 345 compatible = "renesas,r8a774c0-sysc";
349 reg = <0 0xe6180000 0 346 reg = <0 0xe6180000 0 0x0400>;
350 #power-domain-cells = 347 #power-domain-cells = <1>;
351 }; 348 };
352 349
353 thermal: thermal@e6190000 { 350 thermal: thermal@e6190000 {
354 compatible = "renesas, 351 compatible = "renesas,thermal-r8a774c0";
355 reg = <0 0xe6190000 0 352 reg = <0 0xe6190000 0 0x10>, <0 0xe6190100 0 0x38>;
356 interrupts = <GIC_SPI 353 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
357 <GIC_SPI 354 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
358 <GIC_SPI 355 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
359 clocks = <&cpg CPG_MOD 356 clocks = <&cpg CPG_MOD 522>;
360 power-domains = <&sysc 357 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
361 resets = <&cpg 522>; 358 resets = <&cpg 522>;
362 #thermal-sensor-cells 359 #thermal-sensor-cells = <0>;
363 }; 360 };
364 361
365 intc_ex: interrupt-controller@ 362 intc_ex: interrupt-controller@e61c0000 {
366 compatible = "renesas, 363 compatible = "renesas,intc-ex-r8a774c0", "renesas,irqc";
367 #interrupt-cells = <2> 364 #interrupt-cells = <2>;
368 interrupt-controller; 365 interrupt-controller;
369 reg = <0 0xe61c0000 0 366 reg = <0 0xe61c0000 0 0x200>;
370 interrupts = <GIC_SPI !! 367 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
371 <GIC_SPI !! 368 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
372 <GIC_SPI !! 369 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
373 <GIC_SPI !! 370 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
374 <GIC_SPI !! 371 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
375 <GIC_SPI !! 372 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
376 clocks = <&cpg CPG_MOD 373 clocks = <&cpg CPG_MOD 407>;
377 power-domains = <&sysc 374 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
378 resets = <&cpg 407>; 375 resets = <&cpg 407>;
379 }; 376 };
380 377
381 tmu0: timer@e61e0000 { 378 tmu0: timer@e61e0000 {
382 compatible = "renesas, 379 compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
383 reg = <0 0xe61e0000 0 380 reg = <0 0xe61e0000 0 0x30>;
384 interrupts = <GIC_SPI 381 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
385 <GIC_SPI 382 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
386 <GIC_SPI 383 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
387 interrupt-names = "tun <<
388 clocks = <&cpg CPG_MOD 384 clocks = <&cpg CPG_MOD 125>;
389 clock-names = "fck"; 385 clock-names = "fck";
390 power-domains = <&sysc 386 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
391 resets = <&cpg 125>; 387 resets = <&cpg 125>;
392 status = "disabled"; 388 status = "disabled";
393 }; 389 };
394 390
395 tmu1: timer@e6fc0000 { 391 tmu1: timer@e6fc0000 {
396 compatible = "renesas, 392 compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
397 reg = <0 0xe6fc0000 0 393 reg = <0 0xe6fc0000 0 0x30>;
398 interrupts = <GIC_SPI 394 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
399 <GIC_SPI 395 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
400 <GIC_SPI !! 396 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
401 <GIC_SPI <<
402 interrupt-names = "tun <<
403 clocks = <&cpg CPG_MOD 397 clocks = <&cpg CPG_MOD 124>;
404 clock-names = "fck"; 398 clock-names = "fck";
405 power-domains = <&sysc 399 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
406 resets = <&cpg 124>; 400 resets = <&cpg 124>;
407 status = "disabled"; 401 status = "disabled";
408 }; 402 };
409 403
410 tmu2: timer@e6fd0000 { 404 tmu2: timer@e6fd0000 {
411 compatible = "renesas, 405 compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
412 reg = <0 0xe6fd0000 0 406 reg = <0 0xe6fd0000 0 0x30>;
413 interrupts = <GIC_SPI 407 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
414 <GIC_SPI 408 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
415 <GIC_SPI !! 409 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
416 <GIC_SPI <<
417 interrupt-names = "tun <<
418 clocks = <&cpg CPG_MOD 410 clocks = <&cpg CPG_MOD 123>;
419 clock-names = "fck"; 411 clock-names = "fck";
420 power-domains = <&sysc 412 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
421 resets = <&cpg 123>; 413 resets = <&cpg 123>;
422 status = "disabled"; 414 status = "disabled";
423 }; 415 };
424 416
425 tmu3: timer@e6fe0000 { 417 tmu3: timer@e6fe0000 {
426 compatible = "renesas, 418 compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
427 reg = <0 0xe6fe0000 0 419 reg = <0 0xe6fe0000 0 0x30>;
428 interrupts = <GIC_SPI 420 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
429 <GIC_SPI 421 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
430 <GIC_SPI 422 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
431 interrupt-names = "tun <<
432 clocks = <&cpg CPG_MOD 423 clocks = <&cpg CPG_MOD 122>;
433 clock-names = "fck"; 424 clock-names = "fck";
434 power-domains = <&sysc 425 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
435 resets = <&cpg 122>; 426 resets = <&cpg 122>;
436 status = "disabled"; 427 status = "disabled";
437 }; 428 };
438 429
439 tmu4: timer@ffc00000 { 430 tmu4: timer@ffc00000 {
440 compatible = "renesas, 431 compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
441 reg = <0 0xffc00000 0 432 reg = <0 0xffc00000 0 0x30>;
442 interrupts = <GIC_SPI 433 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
443 <GIC_SPI 434 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
444 <GIC_SPI 435 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
445 interrupt-names = "tun <<
446 clocks = <&cpg CPG_MOD 436 clocks = <&cpg CPG_MOD 121>;
447 clock-names = "fck"; 437 clock-names = "fck";
448 power-domains = <&sysc 438 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
449 resets = <&cpg 121>; 439 resets = <&cpg 121>;
450 status = "disabled"; 440 status = "disabled";
451 }; 441 };
452 442
453 i2c0: i2c@e6500000 { 443 i2c0: i2c@e6500000 {
454 #address-cells = <1>; 444 #address-cells = <1>;
455 #size-cells = <0>; 445 #size-cells = <0>;
456 compatible = "renesas, 446 compatible = "renesas,i2c-r8a774c0",
457 "renesas, 447 "renesas,rcar-gen3-i2c";
458 reg = <0 0xe6500000 0 448 reg = <0 0xe6500000 0 0x40>;
459 interrupts = <GIC_SPI 449 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
460 clocks = <&cpg CPG_MOD 450 clocks = <&cpg CPG_MOD 931>;
461 power-domains = <&sysc 451 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
462 resets = <&cpg 931>; 452 resets = <&cpg 931>;
463 dmas = <&dmac1 0x91>, 453 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
464 <&dmac2 0x91>, 454 <&dmac2 0x91>, <&dmac2 0x90>;
465 dma-names = "tx", "rx" 455 dma-names = "tx", "rx", "tx", "rx";
466 i2c-scl-internal-delay 456 i2c-scl-internal-delay-ns = <110>;
467 status = "disabled"; 457 status = "disabled";
468 }; 458 };
469 459
470 i2c1: i2c@e6508000 { 460 i2c1: i2c@e6508000 {
471 #address-cells = <1>; 461 #address-cells = <1>;
472 #size-cells = <0>; 462 #size-cells = <0>;
473 compatible = "renesas, 463 compatible = "renesas,i2c-r8a774c0",
474 "renesas, 464 "renesas,rcar-gen3-i2c";
475 reg = <0 0xe6508000 0 465 reg = <0 0xe6508000 0 0x40>;
476 interrupts = <GIC_SPI 466 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
477 clocks = <&cpg CPG_MOD 467 clocks = <&cpg CPG_MOD 930>;
478 power-domains = <&sysc 468 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
479 resets = <&cpg 930>; 469 resets = <&cpg 930>;
480 dmas = <&dmac1 0x93>, 470 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
481 <&dmac2 0x93>, 471 <&dmac2 0x93>, <&dmac2 0x92>;
482 dma-names = "tx", "rx" 472 dma-names = "tx", "rx", "tx", "rx";
483 i2c-scl-internal-delay 473 i2c-scl-internal-delay-ns = <6>;
484 status = "disabled"; 474 status = "disabled";
485 }; 475 };
486 476
487 i2c2: i2c@e6510000 { 477 i2c2: i2c@e6510000 {
488 #address-cells = <1>; 478 #address-cells = <1>;
489 #size-cells = <0>; 479 #size-cells = <0>;
490 compatible = "renesas, 480 compatible = "renesas,i2c-r8a774c0",
491 "renesas, 481 "renesas,rcar-gen3-i2c";
492 reg = <0 0xe6510000 0 482 reg = <0 0xe6510000 0 0x40>;
493 interrupts = <GIC_SPI 483 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
494 clocks = <&cpg CPG_MOD 484 clocks = <&cpg CPG_MOD 929>;
495 power-domains = <&sysc 485 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
496 resets = <&cpg 929>; 486 resets = <&cpg 929>;
497 dmas = <&dmac1 0x95>, 487 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
498 <&dmac2 0x95>, 488 <&dmac2 0x95>, <&dmac2 0x94>;
499 dma-names = "tx", "rx" 489 dma-names = "tx", "rx", "tx", "rx";
500 i2c-scl-internal-delay 490 i2c-scl-internal-delay-ns = <6>;
501 status = "disabled"; 491 status = "disabled";
502 }; 492 };
503 493
504 i2c3: i2c@e66d0000 { 494 i2c3: i2c@e66d0000 {
505 #address-cells = <1>; 495 #address-cells = <1>;
506 #size-cells = <0>; 496 #size-cells = <0>;
507 compatible = "renesas, 497 compatible = "renesas,i2c-r8a774c0",
508 "renesas, 498 "renesas,rcar-gen3-i2c";
509 reg = <0 0xe66d0000 0 499 reg = <0 0xe66d0000 0 0x40>;
510 interrupts = <GIC_SPI 500 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
511 clocks = <&cpg CPG_MOD 501 clocks = <&cpg CPG_MOD 928>;
512 power-domains = <&sysc 502 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
513 resets = <&cpg 928>; 503 resets = <&cpg 928>;
514 dmas = <&dmac0 0x97>, 504 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
515 dma-names = "tx", "rx" 505 dma-names = "tx", "rx";
516 i2c-scl-internal-delay 506 i2c-scl-internal-delay-ns = <110>;
517 status = "disabled"; 507 status = "disabled";
518 }; 508 };
519 509
520 i2c4: i2c@e66d8000 { 510 i2c4: i2c@e66d8000 {
521 #address-cells = <1>; 511 #address-cells = <1>;
522 #size-cells = <0>; 512 #size-cells = <0>;
523 compatible = "renesas, 513 compatible = "renesas,i2c-r8a774c0",
524 "renesas, 514 "renesas,rcar-gen3-i2c";
525 reg = <0 0xe66d8000 0 515 reg = <0 0xe66d8000 0 0x40>;
526 interrupts = <GIC_SPI 516 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
527 clocks = <&cpg CPG_MOD 517 clocks = <&cpg CPG_MOD 927>;
528 power-domains = <&sysc 518 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
529 resets = <&cpg 927>; 519 resets = <&cpg 927>;
530 dmas = <&dmac0 0x99>, 520 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
531 dma-names = "tx", "rx" 521 dma-names = "tx", "rx";
532 i2c-scl-internal-delay 522 i2c-scl-internal-delay-ns = <6>;
533 status = "disabled"; 523 status = "disabled";
534 }; 524 };
535 525
536 i2c5: i2c@e66e0000 { 526 i2c5: i2c@e66e0000 {
537 #address-cells = <1>; 527 #address-cells = <1>;
538 #size-cells = <0>; 528 #size-cells = <0>;
539 compatible = "renesas, 529 compatible = "renesas,i2c-r8a774c0",
540 "renesas, 530 "renesas,rcar-gen3-i2c";
541 reg = <0 0xe66e0000 0 531 reg = <0 0xe66e0000 0 0x40>;
542 interrupts = <GIC_SPI 532 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
543 clocks = <&cpg CPG_MOD 533 clocks = <&cpg CPG_MOD 919>;
544 power-domains = <&sysc 534 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
545 resets = <&cpg 919>; 535 resets = <&cpg 919>;
546 dmas = <&dmac0 0x9b>, 536 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
547 dma-names = "tx", "rx" 537 dma-names = "tx", "rx";
548 i2c-scl-internal-delay 538 i2c-scl-internal-delay-ns = <6>;
549 status = "disabled"; 539 status = "disabled";
550 }; 540 };
551 541
552 i2c6: i2c@e66e8000 { 542 i2c6: i2c@e66e8000 {
553 #address-cells = <1>; 543 #address-cells = <1>;
554 #size-cells = <0>; 544 #size-cells = <0>;
555 compatible = "renesas, 545 compatible = "renesas,i2c-r8a774c0",
556 "renesas, 546 "renesas,rcar-gen3-i2c";
557 reg = <0 0xe66e8000 0 547 reg = <0 0xe66e8000 0 0x40>;
558 interrupts = <GIC_SPI 548 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
559 clocks = <&cpg CPG_MOD 549 clocks = <&cpg CPG_MOD 918>;
560 power-domains = <&sysc 550 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
561 resets = <&cpg 918>; 551 resets = <&cpg 918>;
562 dmas = <&dmac0 0x9d>, 552 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
563 dma-names = "tx", "rx" 553 dma-names = "tx", "rx";
564 i2c-scl-internal-delay 554 i2c-scl-internal-delay-ns = <6>;
565 status = "disabled"; 555 status = "disabled";
566 }; 556 };
567 557
568 i2c7: i2c@e6690000 { 558 i2c7: i2c@e6690000 {
569 #address-cells = <1>; 559 #address-cells = <1>;
570 #size-cells = <0>; 560 #size-cells = <0>;
571 compatible = "renesas, 561 compatible = "renesas,i2c-r8a774c0",
572 "renesas, 562 "renesas,rcar-gen3-i2c";
573 reg = <0 0xe6690000 0 563 reg = <0 0xe6690000 0 0x40>;
574 interrupts = <GIC_SPI 564 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
575 clocks = <&cpg CPG_MOD 565 clocks = <&cpg CPG_MOD 1003>;
576 power-domains = <&sysc 566 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
577 resets = <&cpg 1003>; 567 resets = <&cpg 1003>;
578 i2c-scl-internal-delay 568 i2c-scl-internal-delay-ns = <6>;
579 status = "disabled"; 569 status = "disabled";
580 }; 570 };
581 571
582 iic_pmic: i2c@e60b0000 { !! 572 i2c_dvfs: i2c@e60b0000 {
583 #address-cells = <1>; 573 #address-cells = <1>;
584 #size-cells = <0>; 574 #size-cells = <0>;
585 compatible = "renesas, !! 575 compatible = "renesas,iic-r8a774c0";
586 "renesas, !! 576 reg = <0 0xe60b0000 0 0x15>;
587 "renesas, <<
588 reg = <0 0xe60b0000 0 <<
589 interrupts = <GIC_SPI 577 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
590 clocks = <&cpg CPG_MOD 578 clocks = <&cpg CPG_MOD 926>;
591 power-domains = <&sysc 579 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
592 resets = <&cpg 926>; 580 resets = <&cpg 926>;
593 dmas = <&dmac0 0x11>, 581 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
594 dma-names = "tx", "rx" 582 dma-names = "tx", "rx";
595 status = "disabled"; 583 status = "disabled";
596 }; 584 };
597 585
598 hscif0: serial@e6540000 { 586 hscif0: serial@e6540000 {
599 compatible = "renesas, 587 compatible = "renesas,hscif-r8a774c0",
600 "renesas, 588 "renesas,rcar-gen3-hscif",
601 "renesas, 589 "renesas,hscif";
602 reg = <0 0xe6540000 0 590 reg = <0 0xe6540000 0 0x60>;
603 interrupts = <GIC_SPI 591 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
604 clocks = <&cpg CPG_MOD 592 clocks = <&cpg CPG_MOD 520>,
605 <&cpg CPG_COR 593 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
606 <&scif_clk>; 594 <&scif_clk>;
607 clock-names = "fck", " 595 clock-names = "fck", "brg_int", "scif_clk";
608 dmas = <&dmac1 0x31>, 596 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
609 <&dmac2 0x31>, 597 <&dmac2 0x31>, <&dmac2 0x30>;
610 dma-names = "tx", "rx" 598 dma-names = "tx", "rx", "tx", "rx";
611 power-domains = <&sysc 599 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
612 resets = <&cpg 520>; 600 resets = <&cpg 520>;
613 status = "disabled"; 601 status = "disabled";
614 }; 602 };
615 603
616 hscif1: serial@e6550000 { 604 hscif1: serial@e6550000 {
617 compatible = "renesas, 605 compatible = "renesas,hscif-r8a774c0",
618 "renesas, 606 "renesas,rcar-gen3-hscif",
619 "renesas, 607 "renesas,hscif";
620 reg = <0 0xe6550000 0 608 reg = <0 0xe6550000 0 0x60>;
621 interrupts = <GIC_SPI 609 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
622 clocks = <&cpg CPG_MOD 610 clocks = <&cpg CPG_MOD 519>,
623 <&cpg CPG_COR 611 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
624 <&scif_clk>; 612 <&scif_clk>;
625 clock-names = "fck", " 613 clock-names = "fck", "brg_int", "scif_clk";
626 dmas = <&dmac1 0x33>, 614 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
627 <&dmac2 0x33>, 615 <&dmac2 0x33>, <&dmac2 0x32>;
628 dma-names = "tx", "rx" 616 dma-names = "tx", "rx", "tx", "rx";
629 power-domains = <&sysc 617 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
630 resets = <&cpg 519>; 618 resets = <&cpg 519>;
631 status = "disabled"; 619 status = "disabled";
632 }; 620 };
633 621
634 hscif2: serial@e6560000 { 622 hscif2: serial@e6560000 {
635 compatible = "renesas, 623 compatible = "renesas,hscif-r8a774c0",
636 "renesas, 624 "renesas,rcar-gen3-hscif",
637 "renesas, 625 "renesas,hscif";
638 reg = <0 0xe6560000 0 626 reg = <0 0xe6560000 0 0x60>;
639 interrupts = <GIC_SPI 627 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
640 clocks = <&cpg CPG_MOD 628 clocks = <&cpg CPG_MOD 518>,
641 <&cpg CPG_COR 629 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
642 <&scif_clk>; 630 <&scif_clk>;
643 clock-names = "fck", " 631 clock-names = "fck", "brg_int", "scif_clk";
644 dmas = <&dmac1 0x35>, 632 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
645 <&dmac2 0x35>, 633 <&dmac2 0x35>, <&dmac2 0x34>;
646 dma-names = "tx", "rx" 634 dma-names = "tx", "rx", "tx", "rx";
647 power-domains = <&sysc 635 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
648 resets = <&cpg 518>; 636 resets = <&cpg 518>;
649 status = "disabled"; 637 status = "disabled";
650 }; 638 };
651 639
652 hscif3: serial@e66a0000 { 640 hscif3: serial@e66a0000 {
653 compatible = "renesas, 641 compatible = "renesas,hscif-r8a774c0",
654 "renesas, 642 "renesas,rcar-gen3-hscif",
655 "renesas, 643 "renesas,hscif";
656 reg = <0 0xe66a0000 0 644 reg = <0 0xe66a0000 0 0x60>;
657 interrupts = <GIC_SPI 645 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
658 clocks = <&cpg CPG_MOD 646 clocks = <&cpg CPG_MOD 517>,
659 <&cpg CPG_COR 647 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
660 <&scif_clk>; 648 <&scif_clk>;
661 clock-names = "fck", " 649 clock-names = "fck", "brg_int", "scif_clk";
662 dmas = <&dmac0 0x37>, 650 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
663 dma-names = "tx", "rx" 651 dma-names = "tx", "rx";
664 power-domains = <&sysc 652 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
665 resets = <&cpg 517>; 653 resets = <&cpg 517>;
666 status = "disabled"; 654 status = "disabled";
667 }; 655 };
668 656
669 hscif4: serial@e66b0000 { 657 hscif4: serial@e66b0000 {
670 compatible = "renesas, 658 compatible = "renesas,hscif-r8a774c0",
671 "renesas, 659 "renesas,rcar-gen3-hscif",
672 "renesas, 660 "renesas,hscif";
673 reg = <0 0xe66b0000 0 661 reg = <0 0xe66b0000 0 0x60>;
674 interrupts = <GIC_SPI 662 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
675 clocks = <&cpg CPG_MOD 663 clocks = <&cpg CPG_MOD 516>,
676 <&cpg CPG_COR 664 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
677 <&scif_clk>; 665 <&scif_clk>;
678 clock-names = "fck", " 666 clock-names = "fck", "brg_int", "scif_clk";
679 dmas = <&dmac0 0x39>, 667 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
680 dma-names = "tx", "rx" 668 dma-names = "tx", "rx";
681 power-domains = <&sysc 669 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
682 resets = <&cpg 516>; 670 resets = <&cpg 516>;
683 status = "disabled"; 671 status = "disabled";
684 }; 672 };
685 673
686 hsusb: usb@e6590000 { 674 hsusb: usb@e6590000 {
687 compatible = "renesas, 675 compatible = "renesas,usbhs-r8a774c0",
688 "renesas, 676 "renesas,rcar-gen3-usbhs";
689 reg = <0 0xe6590000 0 677 reg = <0 0xe6590000 0 0x200>;
690 interrupts = <GIC_SPI 678 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
691 clocks = <&cpg CPG_MOD 679 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
692 dmas = <&usb_dmac0 0>, 680 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
693 <&usb_dmac1 0>, 681 <&usb_dmac1 0>, <&usb_dmac1 1>;
694 dma-names = "ch0", "ch 682 dma-names = "ch0", "ch1", "ch2", "ch3";
695 renesas,buswait = <11> 683 renesas,buswait = <11>;
696 phys = <&usb2_phy0 3>; 684 phys = <&usb2_phy0 3>;
697 phy-names = "usb"; 685 phy-names = "usb";
698 power-domains = <&sysc 686 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
699 resets = <&cpg 704>, < 687 resets = <&cpg 704>, <&cpg 703>;
700 status = "disabled"; 688 status = "disabled";
701 }; 689 };
702 690
703 usb_dmac0: dma-controller@e65a 691 usb_dmac0: dma-controller@e65a0000 {
704 compatible = "renesas, 692 compatible = "renesas,r8a774c0-usb-dmac",
705 "renesas, 693 "renesas,usb-dmac";
706 reg = <0 0xe65a0000 0 694 reg = <0 0xe65a0000 0 0x100>;
707 interrupts = <GIC_SPI !! 695 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
708 <GIC_SPI !! 696 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
709 interrupt-names = "ch0 697 interrupt-names = "ch0", "ch1";
710 clocks = <&cpg CPG_MOD 698 clocks = <&cpg CPG_MOD 330>;
711 power-domains = <&sysc 699 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
712 resets = <&cpg 330>; 700 resets = <&cpg 330>;
713 #dma-cells = <1>; 701 #dma-cells = <1>;
714 dma-channels = <2>; 702 dma-channels = <2>;
715 }; 703 };
716 704
717 usb_dmac1: dma-controller@e65b 705 usb_dmac1: dma-controller@e65b0000 {
718 compatible = "renesas, 706 compatible = "renesas,r8a774c0-usb-dmac",
719 "renesas, 707 "renesas,usb-dmac";
720 reg = <0 0xe65b0000 0 708 reg = <0 0xe65b0000 0 0x100>;
721 interrupts = <GIC_SPI !! 709 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
722 <GIC_SPI !! 710 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
723 interrupt-names = "ch0 711 interrupt-names = "ch0", "ch1";
724 clocks = <&cpg CPG_MOD 712 clocks = <&cpg CPG_MOD 331>;
725 power-domains = <&sysc 713 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
726 resets = <&cpg 331>; 714 resets = <&cpg 331>;
727 #dma-cells = <1>; 715 #dma-cells = <1>;
728 dma-channels = <2>; 716 dma-channels = <2>;
729 }; 717 };
730 718
731 dmac0: dma-controller@e6700000 719 dmac0: dma-controller@e6700000 {
732 compatible = "renesas, 720 compatible = "renesas,dmac-r8a774c0",
733 "renesas, 721 "renesas,rcar-dmac";
734 reg = <0 0xe6700000 0 722 reg = <0 0xe6700000 0 0x10000>;
735 interrupts = <GIC_SPI !! 723 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH
736 <GIC_SPI !! 724 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
737 <GIC_SPI !! 725 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
738 <GIC_SPI !! 726 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
739 <GIC_SPI !! 727 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
740 <GIC_SPI !! 728 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
741 <GIC_SPI !! 729 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
742 <GIC_SPI !! 730 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
743 <GIC_SPI !! 731 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
744 <GIC_SPI !! 732 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
745 <GIC_SPI !! 733 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
746 <GIC_SPI !! 734 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
747 <GIC_SPI !! 735 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
748 <GIC_SPI !! 736 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
749 <GIC_SPI !! 737 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
750 <GIC_SPI !! 738 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH
751 <GIC_SPI !! 739 GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
752 interrupt-names = "err 740 interrupt-names = "error",
753 "ch0", 741 "ch0", "ch1", "ch2", "ch3",
754 "ch4", 742 "ch4", "ch5", "ch6", "ch7",
755 "ch8", 743 "ch8", "ch9", "ch10", "ch11",
756 "ch12" 744 "ch12", "ch13", "ch14", "ch15";
757 clocks = <&cpg CPG_MOD 745 clocks = <&cpg CPG_MOD 219>;
758 clock-names = "fck"; 746 clock-names = "fck";
759 power-domains = <&sysc 747 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
760 resets = <&cpg 219>; 748 resets = <&cpg 219>;
761 #dma-cells = <1>; 749 #dma-cells = <1>;
762 dma-channels = <16>; 750 dma-channels = <16>;
763 iommus = <&ipmmu_ds0 0 751 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
764 <&ipmmu_ds0 2>, 752 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
765 <&ipmmu_ds0 4>, 753 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
766 <&ipmmu_ds0 6>, 754 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
767 <&ipmmu_ds0 8>, 755 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
768 <&ipmmu_ds0 10> 756 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
769 <&ipmmu_ds0 12> 757 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
770 <&ipmmu_ds0 14> 758 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
771 }; 759 };
772 760
773 dmac1: dma-controller@e7300000 761 dmac1: dma-controller@e7300000 {
774 compatible = "renesas, 762 compatible = "renesas,dmac-r8a774c0",
775 "renesas, 763 "renesas,rcar-dmac";
776 reg = <0 0xe7300000 0 764 reg = <0 0xe7300000 0 0x10000>;
777 interrupts = <GIC_SPI !! 765 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
778 <GIC_SPI !! 766 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
779 <GIC_SPI !! 767 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
780 <GIC_SPI !! 768 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
781 <GIC_SPI !! 769 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
782 <GIC_SPI !! 770 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
783 <GIC_SPI !! 771 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
784 <GIC_SPI !! 772 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
785 <GIC_SPI !! 773 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
786 <GIC_SPI !! 774 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
787 <GIC_SPI !! 775 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
788 <GIC_SPI !! 776 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
789 <GIC_SPI !! 777 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
790 <GIC_SPI !! 778 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
791 <GIC_SPI !! 779 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
792 <GIC_SPI !! 780 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
793 <GIC_SPI !! 781 GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
794 interrupt-names = "err 782 interrupt-names = "error",
795 "ch0", 783 "ch0", "ch1", "ch2", "ch3",
796 "ch4", 784 "ch4", "ch5", "ch6", "ch7",
797 "ch8", 785 "ch8", "ch9", "ch10", "ch11",
798 "ch12" 786 "ch12", "ch13", "ch14", "ch15";
799 clocks = <&cpg CPG_MOD 787 clocks = <&cpg CPG_MOD 218>;
800 clock-names = "fck"; 788 clock-names = "fck";
801 power-domains = <&sysc 789 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
802 resets = <&cpg 218>; 790 resets = <&cpg 218>;
803 #dma-cells = <1>; 791 #dma-cells = <1>;
804 dma-channels = <16>; 792 dma-channels = <16>;
805 iommus = <&ipmmu_ds1 0 793 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
806 <&ipmmu_ds1 2>, 794 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
807 <&ipmmu_ds1 4>, 795 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
808 <&ipmmu_ds1 6>, 796 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
809 <&ipmmu_ds1 8>, 797 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
810 <&ipmmu_ds1 10> 798 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
811 <&ipmmu_ds1 12> 799 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
812 <&ipmmu_ds1 14> 800 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
813 }; 801 };
814 802
815 dmac2: dma-controller@e7310000 803 dmac2: dma-controller@e7310000 {
816 compatible = "renesas, 804 compatible = "renesas,dmac-r8a774c0",
817 "renesas, 805 "renesas,rcar-dmac";
818 reg = <0 0xe7310000 0 806 reg = <0 0xe7310000 0 0x10000>;
819 interrupts = <GIC_SPI !! 807 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH
820 <GIC_SPI !! 808 GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH
821 <GIC_SPI !! 809 GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH
822 <GIC_SPI !! 810 GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH
823 <GIC_SPI !! 811 GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH
824 <GIC_SPI !! 812 GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH
825 <GIC_SPI !! 813 GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH
826 <GIC_SPI !! 814 GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH
827 <GIC_SPI !! 815 GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH
828 <GIC_SPI !! 816 GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH
829 <GIC_SPI !! 817 GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH
830 <GIC_SPI !! 818 GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH
831 <GIC_SPI !! 819 GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH
832 <GIC_SPI !! 820 GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH
833 <GIC_SPI !! 821 GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH
834 <GIC_SPI !! 822 GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH
835 <GIC_SPI !! 823 GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
836 interrupt-names = "err 824 interrupt-names = "error",
837 "ch0", 825 "ch0", "ch1", "ch2", "ch3",
838 "ch4", 826 "ch4", "ch5", "ch6", "ch7",
839 "ch8", 827 "ch8", "ch9", "ch10", "ch11",
840 "ch12" 828 "ch12", "ch13", "ch14", "ch15";
841 clocks = <&cpg CPG_MOD 829 clocks = <&cpg CPG_MOD 217>;
842 clock-names = "fck"; 830 clock-names = "fck";
843 power-domains = <&sysc 831 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
844 resets = <&cpg 217>; 832 resets = <&cpg 217>;
845 #dma-cells = <1>; 833 #dma-cells = <1>;
846 dma-channels = <16>; 834 dma-channels = <16>;
847 iommus = <&ipmmu_ds1 1 835 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
848 <&ipmmu_ds1 18> 836 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
849 <&ipmmu_ds1 20> 837 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
850 <&ipmmu_ds1 22> 838 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
851 <&ipmmu_ds1 24> 839 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
852 <&ipmmu_ds1 26> 840 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
853 <&ipmmu_ds1 28> 841 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
854 <&ipmmu_ds1 30> 842 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
855 }; 843 };
856 844
857 ipmmu_ds0: iommu@e6740000 { !! 845 ipmmu_ds0: mmu@e6740000 {
858 compatible = "renesas, 846 compatible = "renesas,ipmmu-r8a774c0";
859 reg = <0 0xe6740000 0 847 reg = <0 0xe6740000 0 0x1000>;
860 renesas,ipmmu-main = < 848 renesas,ipmmu-main = <&ipmmu_mm 0>;
861 power-domains = <&sysc 849 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
862 #iommu-cells = <1>; 850 #iommu-cells = <1>;
863 }; 851 };
864 852
865 ipmmu_ds1: iommu@e7740000 { !! 853 ipmmu_ds1: mmu@e7740000 {
866 compatible = "renesas, 854 compatible = "renesas,ipmmu-r8a774c0";
867 reg = <0 0xe7740000 0 855 reg = <0 0xe7740000 0 0x1000>;
868 renesas,ipmmu-main = < 856 renesas,ipmmu-main = <&ipmmu_mm 1>;
869 power-domains = <&sysc 857 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
870 #iommu-cells = <1>; 858 #iommu-cells = <1>;
871 }; 859 };
872 860
873 ipmmu_hc: iommu@e6570000 { !! 861 ipmmu_hc: mmu@e6570000 {
874 compatible = "renesas, 862 compatible = "renesas,ipmmu-r8a774c0";
875 reg = <0 0xe6570000 0 863 reg = <0 0xe6570000 0 0x1000>;
876 renesas,ipmmu-main = < 864 renesas,ipmmu-main = <&ipmmu_mm 2>;
877 power-domains = <&sysc 865 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
878 #iommu-cells = <1>; 866 #iommu-cells = <1>;
879 }; 867 };
880 868
881 ipmmu_mm: iommu@e67b0000 { !! 869 ipmmu_mm: mmu@e67b0000 {
882 compatible = "renesas, 870 compatible = "renesas,ipmmu-r8a774c0";
883 reg = <0 0xe67b0000 0 871 reg = <0 0xe67b0000 0 0x1000>;
884 interrupts = <GIC_SPI 872 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
885 <GIC_SPI 873 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
886 power-domains = <&sysc 874 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
887 #iommu-cells = <1>; 875 #iommu-cells = <1>;
888 }; 876 };
889 877
890 ipmmu_mp: iommu@ec670000 { !! 878 ipmmu_mp: mmu@ec670000 {
891 compatible = "renesas, 879 compatible = "renesas,ipmmu-r8a774c0";
892 reg = <0 0xec670000 0 880 reg = <0 0xec670000 0 0x1000>;
893 renesas,ipmmu-main = < 881 renesas,ipmmu-main = <&ipmmu_mm 4>;
894 power-domains = <&sysc 882 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
895 #iommu-cells = <1>; 883 #iommu-cells = <1>;
896 }; 884 };
897 885
898 ipmmu_pv0: iommu@fd800000 { !! 886 ipmmu_pv0: mmu@fd800000 {
899 compatible = "renesas, 887 compatible = "renesas,ipmmu-r8a774c0";
900 reg = <0 0xfd800000 0 888 reg = <0 0xfd800000 0 0x1000>;
901 renesas,ipmmu-main = < 889 renesas,ipmmu-main = <&ipmmu_mm 6>;
902 power-domains = <&sysc 890 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
903 #iommu-cells = <1>; 891 #iommu-cells = <1>;
904 }; 892 };
905 893
906 ipmmu_vc0: iommu@fe6b0000 { !! 894 ipmmu_vc0: mmu@fe6b0000 {
907 compatible = "renesas, 895 compatible = "renesas,ipmmu-r8a774c0";
908 reg = <0 0xfe6b0000 0 896 reg = <0 0xfe6b0000 0 0x1000>;
909 renesas,ipmmu-main = < 897 renesas,ipmmu-main = <&ipmmu_mm 12>;
910 power-domains = <&sysc 898 power-domains = <&sysc R8A774C0_PD_A3VC>;
911 #iommu-cells = <1>; 899 #iommu-cells = <1>;
912 }; 900 };
913 901
914 ipmmu_vi0: iommu@febd0000 { !! 902 ipmmu_vi0: mmu@febd0000 {
915 compatible = "renesas, 903 compatible = "renesas,ipmmu-r8a774c0";
916 reg = <0 0xfebd0000 0 904 reg = <0 0xfebd0000 0 0x1000>;
917 renesas,ipmmu-main = < 905 renesas,ipmmu-main = <&ipmmu_mm 14>;
918 power-domains = <&sysc 906 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
919 #iommu-cells = <1>; 907 #iommu-cells = <1>;
920 }; 908 };
921 909
922 ipmmu_vp0: iommu@fe990000 { !! 910 ipmmu_vp0: mmu@fe990000 {
923 compatible = "renesas, 911 compatible = "renesas,ipmmu-r8a774c0";
924 reg = <0 0xfe990000 0 912 reg = <0 0xfe990000 0 0x1000>;
925 renesas,ipmmu-main = < 913 renesas,ipmmu-main = <&ipmmu_mm 16>;
926 power-domains = <&sysc 914 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
927 #iommu-cells = <1>; 915 #iommu-cells = <1>;
928 }; 916 };
929 917
930 avb: ethernet@e6800000 { 918 avb: ethernet@e6800000 {
931 compatible = "renesas, 919 compatible = "renesas,etheravb-r8a774c0",
932 "renesas, 920 "renesas,etheravb-rcar-gen3";
933 reg = <0 0xe6800000 0 921 reg = <0 0xe6800000 0 0x800>;
934 interrupts = <GIC_SPI 922 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
935 <GIC_SPI 923 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
936 <GIC_SPI 924 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
937 <GIC_SPI 925 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
938 <GIC_SPI 926 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
939 <GIC_SPI 927 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
940 <GIC_SPI 928 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
941 <GIC_SPI 929 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
942 <GIC_SPI 930 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
943 <GIC_SPI 931 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
944 <GIC_SPI 932 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
945 <GIC_SPI 933 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
946 <GIC_SPI 934 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
947 <GIC_SPI 935 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
948 <GIC_SPI 936 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
949 <GIC_SPI 937 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
950 <GIC_SPI 938 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
951 <GIC_SPI 939 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
952 <GIC_SPI 940 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
953 <GIC_SPI 941 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
954 <GIC_SPI 942 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
955 <GIC_SPI 943 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
956 <GIC_SPI 944 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
957 <GIC_SPI 945 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
958 <GIC_SPI 946 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
959 interrupt-names = "ch0 947 interrupt-names = "ch0", "ch1", "ch2", "ch3",
960 "ch4 948 "ch4", "ch5", "ch6", "ch7",
961 "ch8 949 "ch8", "ch9", "ch10", "ch11",
962 "ch1 950 "ch12", "ch13", "ch14", "ch15",
963 "ch1 951 "ch16", "ch17", "ch18", "ch19",
964 "ch2 952 "ch20", "ch21", "ch22", "ch23",
965 "ch2 953 "ch24";
966 clocks = <&cpg CPG_MOD 954 clocks = <&cpg CPG_MOD 812>;
967 clock-names = "fck"; <<
968 power-domains = <&sysc 955 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
969 resets = <&cpg 812>; 956 resets = <&cpg 812>;
970 phy-mode = "rgmii"; 957 phy-mode = "rgmii";
971 rx-internal-delay-ps = <<
972 iommus = <&ipmmu_ds0 1 958 iommus = <&ipmmu_ds0 16>;
973 #address-cells = <1>; 959 #address-cells = <1>;
974 #size-cells = <0>; 960 #size-cells = <0>;
975 status = "disabled"; 961 status = "disabled";
976 }; 962 };
977 963
978 can0: can@e6c30000 { 964 can0: can@e6c30000 {
979 compatible = "renesas, 965 compatible = "renesas,can-r8a774c0",
980 "renesas, 966 "renesas,rcar-gen3-can";
981 reg = <0 0xe6c30000 0 967 reg = <0 0xe6c30000 0 0x1000>;
982 interrupts = <GIC_SPI 968 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
983 clocks = <&cpg CPG_MOD 969 clocks = <&cpg CPG_MOD 916>,
984 <&cpg CPG_COR 970 <&cpg CPG_CORE R8A774C0_CLK_CANFD>,
985 <&can_clk>; 971 <&can_clk>;
986 clock-names = "clkp1", 972 clock-names = "clkp1", "clkp2", "can_clk";
987 assigned-clocks = <&cp 973 assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>;
988 assigned-clock-rates = 974 assigned-clock-rates = <40000000>;
989 power-domains = <&sysc 975 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
990 resets = <&cpg 916>; 976 resets = <&cpg 916>;
991 status = "disabled"; 977 status = "disabled";
992 }; 978 };
993 979
994 can1: can@e6c38000 { 980 can1: can@e6c38000 {
995 compatible = "renesas, 981 compatible = "renesas,can-r8a774c0",
996 "renesas, 982 "renesas,rcar-gen3-can";
997 reg = <0 0xe6c38000 0 983 reg = <0 0xe6c38000 0 0x1000>;
998 interrupts = <GIC_SPI 984 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
999 clocks = <&cpg CPG_MOD 985 clocks = <&cpg CPG_MOD 915>,
1000 <&cpg CPG_CO 986 <&cpg CPG_CORE R8A774C0_CLK_CANFD>,
1001 <&can_clk>; 987 <&can_clk>;
1002 clock-names = "clkp1" 988 clock-names = "clkp1", "clkp2", "can_clk";
1003 assigned-clocks = <&c 989 assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>;
1004 assigned-clock-rates 990 assigned-clock-rates = <40000000>;
1005 power-domains = <&sys 991 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1006 resets = <&cpg 915>; 992 resets = <&cpg 915>;
1007 status = "disabled"; 993 status = "disabled";
1008 }; 994 };
1009 995
1010 canfd: can@e66c0000 { 996 canfd: can@e66c0000 {
1011 compatible = "renesas 997 compatible = "renesas,r8a774c0-canfd",
1012 "renesas 998 "renesas,rcar-gen3-canfd";
1013 reg = <0 0xe66c0000 0 999 reg = <0 0xe66c0000 0 0x8000>;
1014 interrupts = <GIC_SPI 1000 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
1015 <GIC_SPI 1001 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1016 interrupt-names = "ch <<
1017 clocks = <&cpg CPG_MO 1002 clocks = <&cpg CPG_MOD 914>,
1018 <&cpg CPG_CO 1003 <&cpg CPG_CORE R8A774C0_CLK_CANFD>,
1019 <&can_clk>; 1004 <&can_clk>;
1020 clock-names = "fck", 1005 clock-names = "fck", "canfd", "can_clk";
1021 assigned-clocks = <&c 1006 assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>;
1022 assigned-clock-rates 1007 assigned-clock-rates = <40000000>;
1023 power-domains = <&sys 1008 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1024 resets = <&cpg 914>; 1009 resets = <&cpg 914>;
1025 status = "disabled"; 1010 status = "disabled";
1026 1011
1027 channel0 { 1012 channel0 {
1028 status = "dis 1013 status = "disabled";
1029 }; 1014 };
1030 1015
1031 channel1 { 1016 channel1 {
1032 status = "dis 1017 status = "disabled";
1033 }; 1018 };
1034 }; 1019 };
1035 1020
1036 pwm0: pwm@e6e30000 { 1021 pwm0: pwm@e6e30000 {
1037 compatible = "renesas 1022 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1038 reg = <0 0xe6e30000 0 1023 reg = <0 0xe6e30000 0 0x8>;
1039 clocks = <&cpg CPG_MO 1024 clocks = <&cpg CPG_MOD 523>;
1040 power-domains = <&sys 1025 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1041 resets = <&cpg 523>; 1026 resets = <&cpg 523>;
1042 #pwm-cells = <2>; 1027 #pwm-cells = <2>;
1043 status = "disabled"; 1028 status = "disabled";
1044 }; 1029 };
1045 1030
1046 pwm1: pwm@e6e31000 { 1031 pwm1: pwm@e6e31000 {
1047 compatible = "renesas 1032 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1048 reg = <0 0xe6e31000 0 1033 reg = <0 0xe6e31000 0 0x8>;
1049 clocks = <&cpg CPG_MO 1034 clocks = <&cpg CPG_MOD 523>;
1050 power-domains = <&sys 1035 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1051 resets = <&cpg 523>; 1036 resets = <&cpg 523>;
1052 #pwm-cells = <2>; 1037 #pwm-cells = <2>;
1053 status = "disabled"; 1038 status = "disabled";
1054 }; 1039 };
1055 1040
1056 pwm2: pwm@e6e32000 { 1041 pwm2: pwm@e6e32000 {
1057 compatible = "renesas 1042 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1058 reg = <0 0xe6e32000 0 1043 reg = <0 0xe6e32000 0 0x8>;
1059 clocks = <&cpg CPG_MO 1044 clocks = <&cpg CPG_MOD 523>;
1060 power-domains = <&sys 1045 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1061 resets = <&cpg 523>; 1046 resets = <&cpg 523>;
1062 #pwm-cells = <2>; 1047 #pwm-cells = <2>;
1063 status = "disabled"; 1048 status = "disabled";
1064 }; 1049 };
1065 1050
1066 pwm3: pwm@e6e33000 { 1051 pwm3: pwm@e6e33000 {
1067 compatible = "renesas 1052 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1068 reg = <0 0xe6e33000 0 1053 reg = <0 0xe6e33000 0 0x8>;
1069 clocks = <&cpg CPG_MO 1054 clocks = <&cpg CPG_MOD 523>;
1070 power-domains = <&sys 1055 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1071 resets = <&cpg 523>; 1056 resets = <&cpg 523>;
1072 #pwm-cells = <2>; 1057 #pwm-cells = <2>;
1073 status = "disabled"; 1058 status = "disabled";
1074 }; 1059 };
1075 1060
1076 pwm4: pwm@e6e34000 { 1061 pwm4: pwm@e6e34000 {
1077 compatible = "renesas 1062 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1078 reg = <0 0xe6e34000 0 1063 reg = <0 0xe6e34000 0 0x8>;
1079 clocks = <&cpg CPG_MO 1064 clocks = <&cpg CPG_MOD 523>;
1080 power-domains = <&sys 1065 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1081 resets = <&cpg 523>; 1066 resets = <&cpg 523>;
1082 #pwm-cells = <2>; 1067 #pwm-cells = <2>;
1083 status = "disabled"; 1068 status = "disabled";
1084 }; 1069 };
1085 1070
1086 pwm5: pwm@e6e35000 { 1071 pwm5: pwm@e6e35000 {
1087 compatible = "renesas 1072 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1088 reg = <0 0xe6e35000 0 1073 reg = <0 0xe6e35000 0 0x8>;
1089 clocks = <&cpg CPG_MO 1074 clocks = <&cpg CPG_MOD 523>;
1090 power-domains = <&sys 1075 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1091 resets = <&cpg 523>; 1076 resets = <&cpg 523>;
1092 #pwm-cells = <2>; 1077 #pwm-cells = <2>;
1093 status = "disabled"; 1078 status = "disabled";
1094 }; 1079 };
1095 1080
1096 pwm6: pwm@e6e36000 { 1081 pwm6: pwm@e6e36000 {
1097 compatible = "renesas 1082 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1098 reg = <0 0xe6e36000 0 1083 reg = <0 0xe6e36000 0 0x8>;
1099 clocks = <&cpg CPG_MO 1084 clocks = <&cpg CPG_MOD 523>;
1100 power-domains = <&sys 1085 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1101 resets = <&cpg 523>; 1086 resets = <&cpg 523>;
1102 #pwm-cells = <2>; 1087 #pwm-cells = <2>;
1103 status = "disabled"; 1088 status = "disabled";
1104 }; 1089 };
1105 1090
1106 scif0: serial@e6e60000 { 1091 scif0: serial@e6e60000 {
1107 compatible = "renesas 1092 compatible = "renesas,scif-r8a774c0",
1108 "renesas 1093 "renesas,rcar-gen3-scif", "renesas,scif";
1109 reg = <0 0xe6e60000 0 1094 reg = <0 0xe6e60000 0 64>;
1110 interrupts = <GIC_SPI 1095 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
1111 clocks = <&cpg CPG_MO 1096 clocks = <&cpg CPG_MOD 207>,
1112 <&cpg CPG_CO 1097 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
1113 <&scif_clk>; 1098 <&scif_clk>;
1114 clock-names = "fck", 1099 clock-names = "fck", "brg_int", "scif_clk";
1115 dmas = <&dmac1 0x51>, 1100 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1116 <&dmac2 0x51>, 1101 <&dmac2 0x51>, <&dmac2 0x50>;
1117 dma-names = "tx", "rx 1102 dma-names = "tx", "rx", "tx", "rx";
1118 power-domains = <&sys 1103 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1119 resets = <&cpg 207>; 1104 resets = <&cpg 207>;
1120 status = "disabled"; 1105 status = "disabled";
1121 }; 1106 };
1122 1107
1123 scif1: serial@e6e68000 { 1108 scif1: serial@e6e68000 {
1124 compatible = "renesas 1109 compatible = "renesas,scif-r8a774c0",
1125 "renesas 1110 "renesas,rcar-gen3-scif", "renesas,scif";
1126 reg = <0 0xe6e68000 0 1111 reg = <0 0xe6e68000 0 64>;
1127 interrupts = <GIC_SPI 1112 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
1128 clocks = <&cpg CPG_MO 1113 clocks = <&cpg CPG_MOD 206>,
1129 <&cpg CPG_CO 1114 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
1130 <&scif_clk>; 1115 <&scif_clk>;
1131 clock-names = "fck", 1116 clock-names = "fck", "brg_int", "scif_clk";
1132 dmas = <&dmac1 0x53>, 1117 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1133 <&dmac2 0x53>, 1118 <&dmac2 0x53>, <&dmac2 0x52>;
1134 dma-names = "tx", "rx 1119 dma-names = "tx", "rx", "tx", "rx";
1135 power-domains = <&sys 1120 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1136 resets = <&cpg 206>; 1121 resets = <&cpg 206>;
1137 status = "disabled"; 1122 status = "disabled";
1138 }; 1123 };
1139 1124
1140 scif2: serial@e6e88000 { 1125 scif2: serial@e6e88000 {
1141 compatible = "renesas 1126 compatible = "renesas,scif-r8a774c0",
1142 "renesas 1127 "renesas,rcar-gen3-scif", "renesas,scif";
1143 reg = <0 0xe6e88000 0 1128 reg = <0 0xe6e88000 0 64>;
1144 interrupts = <GIC_SPI 1129 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
1145 clocks = <&cpg CPG_MO 1130 clocks = <&cpg CPG_MOD 310>,
1146 <&cpg CPG_CO 1131 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
1147 <&scif_clk>; 1132 <&scif_clk>;
1148 clock-names = "fck", 1133 clock-names = "fck", "brg_int", "scif_clk";
1149 dmas = <&dmac1 0x13>, 1134 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1150 <&dmac2 0x13>, 1135 <&dmac2 0x13>, <&dmac2 0x12>;
1151 dma-names = "tx", "rx 1136 dma-names = "tx", "rx", "tx", "rx";
1152 power-domains = <&sys 1137 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1153 resets = <&cpg 310>; 1138 resets = <&cpg 310>;
1154 status = "disabled"; 1139 status = "disabled";
1155 }; 1140 };
1156 1141
1157 scif3: serial@e6c50000 { 1142 scif3: serial@e6c50000 {
1158 compatible = "renesas 1143 compatible = "renesas,scif-r8a774c0",
1159 "renesas 1144 "renesas,rcar-gen3-scif", "renesas,scif";
1160 reg = <0 0xe6c50000 0 1145 reg = <0 0xe6c50000 0 64>;
1161 interrupts = <GIC_SPI 1146 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1162 clocks = <&cpg CPG_MO 1147 clocks = <&cpg CPG_MOD 204>,
1163 <&cpg CPG_CO 1148 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
1164 <&scif_clk>; 1149 <&scif_clk>;
1165 clock-names = "fck", 1150 clock-names = "fck", "brg_int", "scif_clk";
1166 dmas = <&dmac0 0x57>, 1151 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1167 dma-names = "tx", "rx 1152 dma-names = "tx", "rx";
1168 power-domains = <&sys 1153 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1169 resets = <&cpg 204>; 1154 resets = <&cpg 204>;
1170 status = "disabled"; 1155 status = "disabled";
1171 }; 1156 };
1172 1157
1173 scif4: serial@e6c40000 { 1158 scif4: serial@e6c40000 {
1174 compatible = "renesas 1159 compatible = "renesas,scif-r8a774c0",
1175 "renesas 1160 "renesas,rcar-gen3-scif", "renesas,scif";
1176 reg = <0 0xe6c40000 0 1161 reg = <0 0xe6c40000 0 64>;
1177 interrupts = <GIC_SPI 1162 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1178 clocks = <&cpg CPG_MO 1163 clocks = <&cpg CPG_MOD 203>,
1179 <&cpg CPG_CO 1164 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
1180 <&scif_clk>; 1165 <&scif_clk>;
1181 clock-names = "fck", 1166 clock-names = "fck", "brg_int", "scif_clk";
1182 dmas = <&dmac0 0x59>, 1167 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1183 dma-names = "tx", "rx 1168 dma-names = "tx", "rx";
1184 power-domains = <&sys 1169 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1185 resets = <&cpg 203>; 1170 resets = <&cpg 203>;
1186 status = "disabled"; 1171 status = "disabled";
1187 }; 1172 };
1188 1173
1189 scif5: serial@e6f30000 { 1174 scif5: serial@e6f30000 {
1190 compatible = "renesas 1175 compatible = "renesas,scif-r8a774c0",
1191 "renesas 1176 "renesas,rcar-gen3-scif", "renesas,scif";
1192 reg = <0 0xe6f30000 0 1177 reg = <0 0xe6f30000 0 64>;
1193 interrupts = <GIC_SPI 1178 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1194 clocks = <&cpg CPG_MO 1179 clocks = <&cpg CPG_MOD 202>,
1195 <&cpg CPG_CO 1180 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
1196 <&scif_clk>; 1181 <&scif_clk>;
1197 clock-names = "fck", 1182 clock-names = "fck", "brg_int", "scif_clk";
1198 dmas = <&dmac0 0x5b>, 1183 dmas = <&dmac0 0x5b>, <&dmac0 0x5a>;
1199 dma-names = "tx", "rx 1184 dma-names = "tx", "rx";
1200 power-domains = <&sys 1185 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1201 resets = <&cpg 202>; 1186 resets = <&cpg 202>;
1202 status = "disabled"; 1187 status = "disabled";
1203 }; 1188 };
1204 1189
1205 msiof0: spi@e6e90000 { 1190 msiof0: spi@e6e90000 {
1206 compatible = "renesas 1191 compatible = "renesas,msiof-r8a774c0",
1207 "renesas 1192 "renesas,rcar-gen3-msiof";
1208 reg = <0 0xe6e90000 0 1193 reg = <0 0xe6e90000 0 0x0064>;
1209 interrupts = <GIC_SPI 1194 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1210 clocks = <&cpg CPG_MO 1195 clocks = <&cpg CPG_MOD 211>;
1211 dmas = <&dmac1 0x41>, 1196 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1212 <&dmac2 0x41>, 1197 <&dmac2 0x41>, <&dmac2 0x40>;
1213 dma-names = "tx", "rx 1198 dma-names = "tx", "rx", "tx", "rx";
1214 power-domains = <&sys 1199 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1215 resets = <&cpg 211>; 1200 resets = <&cpg 211>;
1216 #address-cells = <1>; 1201 #address-cells = <1>;
1217 #size-cells = <0>; 1202 #size-cells = <0>;
1218 status = "disabled"; 1203 status = "disabled";
1219 }; 1204 };
1220 1205
1221 msiof1: spi@e6ea0000 { 1206 msiof1: spi@e6ea0000 {
1222 compatible = "renesas 1207 compatible = "renesas,msiof-r8a774c0",
1223 "renesas 1208 "renesas,rcar-gen3-msiof";
1224 reg = <0 0xe6ea0000 0 1209 reg = <0 0xe6ea0000 0 0x0064>;
1225 interrupts = <GIC_SPI 1210 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1226 clocks = <&cpg CPG_MO 1211 clocks = <&cpg CPG_MOD 210>;
1227 dmas = <&dmac0 0x43>, 1212 dmas = <&dmac0 0x43>, <&dmac0 0x42>;
1228 dma-names = "tx", "rx 1213 dma-names = "tx", "rx";
1229 power-domains = <&sys 1214 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1230 resets = <&cpg 210>; 1215 resets = <&cpg 210>;
1231 #address-cells = <1>; 1216 #address-cells = <1>;
1232 #size-cells = <0>; 1217 #size-cells = <0>;
1233 status = "disabled"; 1218 status = "disabled";
1234 }; 1219 };
1235 1220
1236 msiof2: spi@e6c00000 { 1221 msiof2: spi@e6c00000 {
1237 compatible = "renesas 1222 compatible = "renesas,msiof-r8a774c0",
1238 "renesas 1223 "renesas,rcar-gen3-msiof";
1239 reg = <0 0xe6c00000 0 1224 reg = <0 0xe6c00000 0 0x0064>;
1240 interrupts = <GIC_SPI 1225 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1241 clocks = <&cpg CPG_MO 1226 clocks = <&cpg CPG_MOD 209>;
1242 dmas = <&dmac0 0x45>, 1227 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1243 dma-names = "tx", "rx 1228 dma-names = "tx", "rx";
1244 power-domains = <&sys 1229 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1245 resets = <&cpg 209>; 1230 resets = <&cpg 209>;
1246 #address-cells = <1>; 1231 #address-cells = <1>;
1247 #size-cells = <0>; 1232 #size-cells = <0>;
1248 status = "disabled"; 1233 status = "disabled";
1249 }; 1234 };
1250 1235
1251 msiof3: spi@e6c10000 { 1236 msiof3: spi@e6c10000 {
1252 compatible = "renesas 1237 compatible = "renesas,msiof-r8a774c0",
1253 "renesas 1238 "renesas,rcar-gen3-msiof";
1254 reg = <0 0xe6c10000 0 1239 reg = <0 0xe6c10000 0 0x0064>;
1255 interrupts = <GIC_SPI 1240 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1256 clocks = <&cpg CPG_MO 1241 clocks = <&cpg CPG_MOD 208>;
1257 dmas = <&dmac0 0x47>, 1242 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1258 dma-names = "tx", "rx 1243 dma-names = "tx", "rx";
1259 power-domains = <&sys 1244 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1260 resets = <&cpg 208>; 1245 resets = <&cpg 208>;
1261 #address-cells = <1>; 1246 #address-cells = <1>;
1262 #size-cells = <0>; 1247 #size-cells = <0>;
1263 status = "disabled"; 1248 status = "disabled";
1264 }; 1249 };
1265 1250
1266 vin4: video@e6ef4000 { 1251 vin4: video@e6ef4000 {
1267 compatible = "renesas 1252 compatible = "renesas,vin-r8a774c0";
1268 reg = <0 0xe6ef4000 0 1253 reg = <0 0xe6ef4000 0 0x1000>;
1269 interrupts = <GIC_SPI 1254 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
1270 clocks = <&cpg CPG_MO 1255 clocks = <&cpg CPG_MOD 807>;
1271 power-domains = <&sys 1256 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1272 resets = <&cpg 807>; 1257 resets = <&cpg 807>;
1273 renesas,id = <4>; 1258 renesas,id = <4>;
1274 status = "disabled"; 1259 status = "disabled";
1275 1260
1276 ports { 1261 ports {
1277 #address-cell 1262 #address-cells = <1>;
1278 #size-cells = 1263 #size-cells = <0>;
1279 1264
1280 port@1 { 1265 port@1 {
1281 #addr 1266 #address-cells = <1>;
1282 #size 1267 #size-cells = <0>;
1283 1268
1284 reg = 1269 reg = <1>;
1285 1270
1286 vin4c 1271 vin4csi40: endpoint@2 {
1287 1272 reg = <2>;
1288 !! 1273 remote-endpoint= <&csi40vin4>;
1289 }; 1274 };
1290 }; 1275 };
1291 }; 1276 };
1292 }; 1277 };
1293 1278
1294 vin5: video@e6ef5000 { 1279 vin5: video@e6ef5000 {
1295 compatible = "renesas 1280 compatible = "renesas,vin-r8a774c0";
1296 reg = <0 0xe6ef5000 0 1281 reg = <0 0xe6ef5000 0 0x1000>;
1297 interrupts = <GIC_SPI 1282 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
1298 clocks = <&cpg CPG_MO 1283 clocks = <&cpg CPG_MOD 806>;
1299 power-domains = <&sys 1284 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1300 resets = <&cpg 806>; 1285 resets = <&cpg 806>;
1301 renesas,id = <5>; 1286 renesas,id = <5>;
1302 status = "disabled"; 1287 status = "disabled";
1303 1288
1304 ports { 1289 ports {
1305 #address-cell 1290 #address-cells = <1>;
1306 #size-cells = 1291 #size-cells = <0>;
1307 1292
1308 port@1 { 1293 port@1 {
1309 #addr 1294 #address-cells = <1>;
1310 #size 1295 #size-cells = <0>;
1311 1296
1312 reg = 1297 reg = <1>;
1313 1298
1314 vin5c 1299 vin5csi40: endpoint@2 {
1315 1300 reg = <2>;
1316 !! 1301 remote-endpoint= <&csi40vin5>;
1317 }; 1302 };
1318 }; 1303 };
1319 }; 1304 };
1320 }; 1305 };
1321 1306
1322 rcar_sound: sound@ec500000 { 1307 rcar_sound: sound@ec500000 {
1323 /* 1308 /*
1324 * #sound-dai-cells i !! 1309 * #sound-dai-cells is required
1325 * 1310 *
1326 * Single DAI : #soun 1311 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1327 * Multi DAI : #soun 1312 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1328 */ 1313 */
1329 /* 1314 /*
1330 * #clock-cells is re 1315 * #clock-cells is required for audio_clkout0/1/2/3
1331 * 1316 *
1332 * clkout : #cl 1317 * clkout : #clock-cells = <0>; <&rcar_sound>;
1333 * clkout0/1/2/3: #cl 1318 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
1334 */ 1319 */
1335 compatible = "renesas 1320 compatible = "renesas,rcar_sound-r8a774c0",
1336 "renesas 1321 "renesas,rcar_sound-gen3";
1337 reg = <0 0xec500000 0 !! 1322 reg = <0 0xec500000 0 0x1000>, /* SCU */
1338 <0 0xec5a0000 0 !! 1323 <0 0xec5a0000 0 0x100>, /* ADG */
1339 <0 0xec540000 0 !! 1324 <0 0xec540000 0 0x1000>, /* SSIU */
1340 <0 0xec541000 0 !! 1325 <0 0xec541000 0 0x280>, /* SSI */
1341 <0 0xec760000 0 !! 1326 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
1342 reg-names = "scu", "a 1327 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1343 1328
1344 clocks = <&cpg CPG_MO 1329 clocks = <&cpg CPG_MOD 1005>,
1345 <&cpg CPG_MO 1330 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
1346 <&cpg CPG_MO 1331 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
1347 <&cpg CPG_MO 1332 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
1348 <&cpg CPG_MO 1333 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
1349 <&cpg CPG_MO 1334 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
1350 <&cpg CPG_MO 1335 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
1351 <&cpg CPG_MO 1336 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
1352 <&cpg CPG_MO 1337 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
1353 <&cpg CPG_MO 1338 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
1354 <&cpg CPG_MO 1339 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
1355 <&cpg CPG_MO 1340 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1356 <&cpg CPG_MO 1341 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1357 <&cpg CPG_MO 1342 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
1358 <&audio_clk_ 1343 <&audio_clk_a>, <&audio_clk_b>,
1359 <&audio_clk_ 1344 <&audio_clk_c>,
1360 <&cpg CPG_MO !! 1345 <&cpg CPG_CORE R8A774C0_CLK_ZA2>;
1361 clock-names = "ssi-al 1346 clock-names = "ssi-all",
1362 "ssi.9" 1347 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1363 "ssi.5" 1348 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1364 "ssi.1" 1349 "ssi.1", "ssi.0",
1365 "src.9" 1350 "src.9", "src.8", "src.7", "src.6",
1366 "src.5" 1351 "src.5", "src.4", "src.3", "src.2",
1367 "src.1" 1352 "src.1", "src.0",
1368 "mix.1" 1353 "mix.1", "mix.0",
1369 "ctu.1" 1354 "ctu.1", "ctu.0",
1370 "dvc.0" 1355 "dvc.0", "dvc.1",
1371 "clk_a" 1356 "clk_a", "clk_b", "clk_c", "clk_i";
1372 power-domains = <&sys 1357 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1373 resets = <&cpg 1005>, 1358 resets = <&cpg 1005>,
1374 <&cpg 1006>, 1359 <&cpg 1006>, <&cpg 1007>,
1375 <&cpg 1008>, 1360 <&cpg 1008>, <&cpg 1009>,
1376 <&cpg 1010>, 1361 <&cpg 1010>, <&cpg 1011>,
1377 <&cpg 1012>, 1362 <&cpg 1012>, <&cpg 1013>,
1378 <&cpg 1014>, 1363 <&cpg 1014>, <&cpg 1015>;
1379 reset-names = "ssi-al 1364 reset-names = "ssi-all",
1380 "ssi.9" 1365 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1381 "ssi.5" 1366 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1382 "ssi.1" 1367 "ssi.1", "ssi.0";
1383 status = "disabled"; 1368 status = "disabled";
1384 1369
1385 rcar_sound,ctu { 1370 rcar_sound,ctu {
1386 ctu00: ctu-0 1371 ctu00: ctu-0 { };
1387 ctu01: ctu-1 1372 ctu01: ctu-1 { };
1388 ctu02: ctu-2 1373 ctu02: ctu-2 { };
1389 ctu03: ctu-3 1374 ctu03: ctu-3 { };
1390 ctu10: ctu-4 1375 ctu10: ctu-4 { };
1391 ctu11: ctu-5 1376 ctu11: ctu-5 { };
1392 ctu12: ctu-6 1377 ctu12: ctu-6 { };
1393 ctu13: ctu-7 1378 ctu13: ctu-7 { };
1394 }; 1379 };
1395 1380
1396 rcar_sound,dvc { 1381 rcar_sound,dvc {
1397 dvc0: dvc-0 { 1382 dvc0: dvc-0 {
1398 dmas 1383 dmas = <&audma0 0xbc>;
1399 dma-n 1384 dma-names = "tx";
1400 }; 1385 };
1401 dvc1: dvc-1 { 1386 dvc1: dvc-1 {
1402 dmas 1387 dmas = <&audma0 0xbe>;
1403 dma-n 1388 dma-names = "tx";
1404 }; 1389 };
1405 }; 1390 };
1406 1391
1407 rcar_sound,mix { 1392 rcar_sound,mix {
1408 mix0: mix-0 { 1393 mix0: mix-0 { };
1409 mix1: mix-1 { 1394 mix1: mix-1 { };
1410 }; 1395 };
1411 1396
1412 rcar_sound,src { 1397 rcar_sound,src {
1413 src0: src-0 { 1398 src0: src-0 {
1414 inter 1399 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1415 dmas 1400 dmas = <&audma0 0x85>, <&audma0 0x9a>;
1416 dma-n 1401 dma-names = "rx", "tx";
1417 }; 1402 };
1418 src1: src-1 { 1403 src1: src-1 {
1419 inter 1404 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1420 dmas 1405 dmas = <&audma0 0x87>, <&audma0 0x9c>;
1421 dma-n 1406 dma-names = "rx", "tx";
1422 }; 1407 };
1423 src2: src-2 { 1408 src2: src-2 {
1424 inter 1409 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1425 dmas 1410 dmas = <&audma0 0x89>, <&audma0 0x9e>;
1426 dma-n 1411 dma-names = "rx", "tx";
1427 }; 1412 };
1428 src3: src-3 { 1413 src3: src-3 {
1429 inter 1414 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1430 dmas 1415 dmas = <&audma0 0x8b>, <&audma0 0xa0>;
1431 dma-n 1416 dma-names = "rx", "tx";
1432 }; 1417 };
1433 src4: src-4 { 1418 src4: src-4 {
1434 inter 1419 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1435 dmas 1420 dmas = <&audma0 0x8d>, <&audma0 0xb0>;
1436 dma-n 1421 dma-names = "rx", "tx";
1437 }; 1422 };
1438 src5: src-5 { 1423 src5: src-5 {
1439 inter 1424 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1440 dmas 1425 dmas = <&audma0 0x8f>, <&audma0 0xb2>;
1441 dma-n 1426 dma-names = "rx", "tx";
1442 }; 1427 };
1443 src6: src-6 { 1428 src6: src-6 {
1444 inter 1429 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1445 dmas 1430 dmas = <&audma0 0x91>, <&audma0 0xb4>;
1446 dma-n 1431 dma-names = "rx", "tx";
1447 }; 1432 };
1448 src7: src-7 { 1433 src7: src-7 {
1449 inter 1434 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1450 dmas 1435 dmas = <&audma0 0x93>, <&audma0 0xb6>;
1451 dma-n 1436 dma-names = "rx", "tx";
1452 }; 1437 };
1453 src8: src-8 { 1438 src8: src-8 {
1454 inter 1439 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1455 dmas 1440 dmas = <&audma0 0x95>, <&audma0 0xb8>;
1456 dma-n 1441 dma-names = "rx", "tx";
1457 }; 1442 };
1458 src9: src-9 { 1443 src9: src-9 {
1459 inter 1444 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
1460 dmas 1445 dmas = <&audma0 0x97>, <&audma0 0xba>;
1461 dma-n 1446 dma-names = "rx", "tx";
1462 }; 1447 };
1463 }; 1448 };
1464 1449
1465 rcar_sound,ssi { 1450 rcar_sound,ssi {
1466 ssi0: ssi-0 { 1451 ssi0: ssi-0 {
1467 inter 1452 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
1468 dmas 1453 dmas = <&audma0 0x01>, <&audma0 0x02>,
1469 1454 <&audma0 0x15>, <&audma0 0x16>;
1470 dma-n 1455 dma-names = "rx", "tx", "rxu", "txu";
1471 }; 1456 };
1472 ssi1: ssi-1 { 1457 ssi1: ssi-1 {
1473 inter 1458 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
1474 dmas 1459 dmas = <&audma0 0x03>, <&audma0 0x04>,
1475 1460 <&audma0 0x49>, <&audma0 0x4a>;
1476 dma-n 1461 dma-names = "rx", "tx", "rxu", "txu";
1477 }; 1462 };
1478 ssi2: ssi-2 { 1463 ssi2: ssi-2 {
1479 inter 1464 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
1480 dmas 1465 dmas = <&audma0 0x05>, <&audma0 0x06>,
1481 1466 <&audma0 0x63>, <&audma0 0x64>;
1482 dma-n 1467 dma-names = "rx", "tx", "rxu", "txu";
1483 }; 1468 };
1484 ssi3: ssi-3 { 1469 ssi3: ssi-3 {
1485 inter 1470 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1486 dmas 1471 dmas = <&audma0 0x07>, <&audma0 0x08>,
1487 1472 <&audma0 0x6f>, <&audma0 0x70>;
1488 dma-n 1473 dma-names = "rx", "tx", "rxu", "txu";
1489 }; 1474 };
1490 ssi4: ssi-4 { 1475 ssi4: ssi-4 {
1491 inter 1476 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1492 dmas 1477 dmas = <&audma0 0x09>, <&audma0 0x0a>,
1493 1478 <&audma0 0x71>, <&audma0 0x72>;
1494 dma-n 1479 dma-names = "rx", "tx", "rxu", "txu";
1495 }; 1480 };
1496 ssi5: ssi-5 { 1481 ssi5: ssi-5 {
1497 inter 1482 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1498 dmas 1483 dmas = <&audma0 0x0b>, <&audma0 0x0c>,
1499 1484 <&audma0 0x73>, <&audma0 0x74>;
1500 dma-n 1485 dma-names = "rx", "tx", "rxu", "txu";
1501 }; 1486 };
1502 ssi6: ssi-6 { 1487 ssi6: ssi-6 {
1503 inter 1488 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
1504 dmas 1489 dmas = <&audma0 0x0d>, <&audma0 0x0e>,
1505 1490 <&audma0 0x75>, <&audma0 0x76>;
1506 dma-n 1491 dma-names = "rx", "tx", "rxu", "txu";
1507 }; 1492 };
1508 ssi7: ssi-7 { 1493 ssi7: ssi-7 {
1509 inter 1494 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
1510 dmas 1495 dmas = <&audma0 0x0f>, <&audma0 0x10>,
1511 1496 <&audma0 0x79>, <&audma0 0x7a>;
1512 dma-n 1497 dma-names = "rx", "tx", "rxu", "txu";
1513 }; 1498 };
1514 ssi8: ssi-8 { 1499 ssi8: ssi-8 {
1515 inter 1500 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
1516 dmas 1501 dmas = <&audma0 0x11>, <&audma0 0x12>,
1517 1502 <&audma0 0x7b>, <&audma0 0x7c>;
1518 dma-n 1503 dma-names = "rx", "tx", "rxu", "txu";
1519 }; 1504 };
1520 ssi9: ssi-9 { 1505 ssi9: ssi-9 {
1521 inter 1506 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
1522 dmas 1507 dmas = <&audma0 0x13>, <&audma0 0x14>,
1523 1508 <&audma0 0x7d>, <&audma0 0x7e>;
1524 dma-n 1509 dma-names = "rx", "tx", "rxu", "txu";
1525 }; 1510 };
1526 }; 1511 };
1527 }; 1512 };
1528 1513
1529 audma0: dma-controller@ec7000 1514 audma0: dma-controller@ec700000 {
1530 compatible = "renesas 1515 compatible = "renesas,dmac-r8a774c0",
1531 "renesas 1516 "renesas,rcar-dmac";
1532 reg = <0 0xec700000 0 1517 reg = <0 0xec700000 0 0x10000>;
1533 interrupts = <GIC_SPI !! 1518 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH
1534 <GIC_SPI !! 1519 GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
1535 <GIC_SPI !! 1520 GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
1536 <GIC_SPI !! 1521 GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
1537 <GIC_SPI !! 1522 GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
1538 <GIC_SPI !! 1523 GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
1539 <GIC_SPI !! 1524 GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
1540 <GIC_SPI !! 1525 GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
1541 <GIC_SPI !! 1526 GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
1542 <GIC_SPI !! 1527 GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
1543 <GIC_SPI !! 1528 GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
1544 <GIC_SPI !! 1529 GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
1545 <GIC_SPI !! 1530 GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
1546 <GIC_SPI !! 1531 GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH
1547 <GIC_SPI !! 1532 GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
1548 <GIC_SPI !! 1533 GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
1549 <GIC_SPI !! 1534 GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
1550 interrupt-names = "er 1535 interrupt-names = "error",
1551 "ch0" 1536 "ch0", "ch1", "ch2", "ch3",
1552 "ch4" 1537 "ch4", "ch5", "ch6", "ch7",
1553 "ch8" 1538 "ch8", "ch9", "ch10", "ch11",
1554 "ch12 1539 "ch12", "ch13", "ch14", "ch15";
1555 clocks = <&cpg CPG_MO 1540 clocks = <&cpg CPG_MOD 502>;
1556 clock-names = "fck"; 1541 clock-names = "fck";
1557 power-domains = <&sys 1542 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1558 resets = <&cpg 502>; 1543 resets = <&cpg 502>;
1559 #dma-cells = <1>; 1544 #dma-cells = <1>;
1560 dma-channels = <16>; 1545 dma-channels = <16>;
1561 iommus = <&ipmmu_mp 0 1546 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
1562 <&ipmmu_mp 2 1547 <&ipmmu_mp 2>, <&ipmmu_mp 3>,
1563 <&ipmmu_mp 4 1548 <&ipmmu_mp 4>, <&ipmmu_mp 5>,
1564 <&ipmmu_mp 6 1549 <&ipmmu_mp 6>, <&ipmmu_mp 7>,
1565 <&ipmmu_mp 8 1550 <&ipmmu_mp 8>, <&ipmmu_mp 9>,
1566 <&ipmmu_mp 1 1551 <&ipmmu_mp 10>, <&ipmmu_mp 11>,
1567 <&ipmmu_mp 1 1552 <&ipmmu_mp 12>, <&ipmmu_mp 13>,
1568 <&ipmmu_mp 1 1553 <&ipmmu_mp 14>, <&ipmmu_mp 15>;
1569 }; 1554 };
1570 1555
1571 xhci0: usb@ee000000 { 1556 xhci0: usb@ee000000 {
1572 compatible = "renesas 1557 compatible = "renesas,xhci-r8a774c0",
1573 "renesas 1558 "renesas,rcar-gen3-xhci";
1574 reg = <0 0xee000000 0 1559 reg = <0 0xee000000 0 0xc00>;
1575 interrupts = <GIC_SPI 1560 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1576 clocks = <&cpg CPG_MO 1561 clocks = <&cpg CPG_MOD 328>;
1577 power-domains = <&sys 1562 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1578 resets = <&cpg 328>; 1563 resets = <&cpg 328>;
1579 status = "disabled"; 1564 status = "disabled";
1580 }; 1565 };
1581 1566
1582 usb3_peri0: usb@ee020000 { 1567 usb3_peri0: usb@ee020000 {
1583 compatible = "renesas 1568 compatible = "renesas,r8a774c0-usb3-peri",
1584 "renesas 1569 "renesas,rcar-gen3-usb3-peri";
1585 reg = <0 0xee020000 0 1570 reg = <0 0xee020000 0 0x400>;
1586 interrupts = <GIC_SPI 1571 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1587 clocks = <&cpg CPG_MO 1572 clocks = <&cpg CPG_MOD 328>;
1588 power-domains = <&sys 1573 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1589 resets = <&cpg 328>; 1574 resets = <&cpg 328>;
1590 status = "disabled"; 1575 status = "disabled";
1591 }; 1576 };
1592 1577
1593 ohci0: usb@ee080000 { 1578 ohci0: usb@ee080000 {
1594 compatible = "generic 1579 compatible = "generic-ohci";
1595 reg = <0 0xee080000 0 1580 reg = <0 0xee080000 0 0x100>;
1596 interrupts = <GIC_SPI 1581 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1597 clocks = <&cpg CPG_MO 1582 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
1598 phys = <&usb2_phy0 1> 1583 phys = <&usb2_phy0 1>;
1599 phy-names = "usb"; 1584 phy-names = "usb";
1600 power-domains = <&sys 1585 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1601 resets = <&cpg 703>, 1586 resets = <&cpg 703>, <&cpg 704>;
1602 status = "disabled"; 1587 status = "disabled";
1603 }; 1588 };
1604 1589
1605 ehci0: usb@ee080100 { 1590 ehci0: usb@ee080100 {
1606 compatible = "generic 1591 compatible = "generic-ehci";
1607 reg = <0 0xee080100 0 1592 reg = <0 0xee080100 0 0x100>;
1608 interrupts = <GIC_SPI 1593 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1609 clocks = <&cpg CPG_MO 1594 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
1610 phys = <&usb2_phy0 2> 1595 phys = <&usb2_phy0 2>;
1611 phy-names = "usb"; 1596 phy-names = "usb";
1612 companion = <&ohci0>; 1597 companion = <&ohci0>;
1613 power-domains = <&sys 1598 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1614 resets = <&cpg 703>, 1599 resets = <&cpg 703>, <&cpg 704>;
1615 status = "disabled"; 1600 status = "disabled";
1616 }; 1601 };
1617 1602
1618 usb2_phy0: usb-phy@ee080200 { 1603 usb2_phy0: usb-phy@ee080200 {
1619 compatible = "renesas 1604 compatible = "renesas,usb2-phy-r8a774c0",
1620 "renesas 1605 "renesas,rcar-gen3-usb2-phy";
1621 reg = <0 0xee080200 0 1606 reg = <0 0xee080200 0 0x700>;
1622 interrupts = <GIC_SPI 1607 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1623 clocks = <&cpg CPG_MO 1608 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
1624 power-domains = <&sys 1609 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1625 resets = <&cpg 703>, 1610 resets = <&cpg 703>, <&cpg 704>;
1626 #phy-cells = <1>; 1611 #phy-cells = <1>;
1627 status = "disabled"; 1612 status = "disabled";
1628 }; 1613 };
1629 1614
1630 sdhi0: mmc@ee100000 { !! 1615 sdhi0: sd@ee100000 {
1631 compatible = "renesas 1616 compatible = "renesas,sdhi-r8a774c0",
1632 "renesas 1617 "renesas,rcar-gen3-sdhi";
1633 reg = <0 0xee100000 0 1618 reg = <0 0xee100000 0 0x2000>;
1634 interrupts = <GIC_SPI 1619 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
1635 clocks = <&cpg CPG_MO !! 1620 clocks = <&cpg CPG_MOD 314>;
1636 clock-names = "core", <<
1637 max-frequency = <2000 1621 max-frequency = <200000000>;
1638 power-domains = <&sys 1622 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1639 resets = <&cpg 314>; 1623 resets = <&cpg 314>;
1640 iommus = <&ipmmu_ds1 <<
1641 status = "disabled"; 1624 status = "disabled";
1642 }; 1625 };
1643 1626
1644 sdhi1: mmc@ee120000 { !! 1627 sdhi1: sd@ee120000 {
1645 compatible = "renesas 1628 compatible = "renesas,sdhi-r8a774c0",
1646 "renesas 1629 "renesas,rcar-gen3-sdhi";
1647 reg = <0 0xee120000 0 1630 reg = <0 0xee120000 0 0x2000>;
1648 interrupts = <GIC_SPI 1631 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
1649 clocks = <&cpg CPG_MO !! 1632 clocks = <&cpg CPG_MOD 313>;
1650 clock-names = "core", <<
1651 max-frequency = <2000 1633 max-frequency = <200000000>;
1652 power-domains = <&sys 1634 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1653 resets = <&cpg 313>; 1635 resets = <&cpg 313>;
1654 iommus = <&ipmmu_ds1 <<
1655 status = "disabled"; 1636 status = "disabled";
1656 }; 1637 };
1657 1638
1658 sdhi3: mmc@ee160000 { !! 1639 sdhi3: sd@ee160000 {
1659 compatible = "renesas 1640 compatible = "renesas,sdhi-r8a774c0",
1660 "renesas 1641 "renesas,rcar-gen3-sdhi";
1661 reg = <0 0xee160000 0 1642 reg = <0 0xee160000 0 0x2000>;
1662 interrupts = <GIC_SPI 1643 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
1663 clocks = <&cpg CPG_MO !! 1644 clocks = <&cpg CPG_MOD 311>;
1664 clock-names = "core", <<
1665 max-frequency = <2000 1645 max-frequency = <200000000>;
1666 power-domains = <&sys 1646 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1667 resets = <&cpg 311>; 1647 resets = <&cpg 311>;
1668 iommus = <&ipmmu_ds1 <<
1669 status = "disabled"; <<
1670 }; <<
1671 <<
1672 rpc: spi@ee200000 { <<
1673 compatible = "renesas <<
1674 "renesas <<
1675 reg = <0 0xee200000 0 <<
1676 <0 0x08000000 0 <<
1677 <0 0xee208000 0 <<
1678 reg-names = "regs", " <<
1679 interrupts = <GIC_SPI <<
1680 clocks = <&cpg CPG_MO <<
1681 power-domains = <&sys <<
1682 resets = <&cpg 917>; <<
1683 #address-cells = <1>; <<
1684 #size-cells = <0>; <<
1685 status = "disabled"; 1648 status = "disabled";
1686 }; 1649 };
1687 1650
1688 gic: interrupt-controller@f10 1651 gic: interrupt-controller@f1010000 {
1689 compatible = "arm,gic 1652 compatible = "arm,gic-400";
1690 #interrupt-cells = <3 1653 #interrupt-cells = <3>;
1691 #address-cells = <0>; 1654 #address-cells = <0>;
1692 interrupt-controller; 1655 interrupt-controller;
1693 reg = <0x0 0xf1010000 1656 reg = <0x0 0xf1010000 0 0x1000>,
1694 <0x0 0xf1020000 1657 <0x0 0xf1020000 0 0x20000>,
1695 <0x0 0xf1040000 1658 <0x0 0xf1040000 0 0x20000>,
1696 <0x0 0xf1060000 1659 <0x0 0xf1060000 0 0x20000>;
1697 interrupts = <GIC_PPI 1660 interrupts = <GIC_PPI 9
1698 (GIC_ 1661 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
1699 clocks = <&cpg CPG_MO 1662 clocks = <&cpg CPG_MOD 408>;
1700 clock-names = "clk"; 1663 clock-names = "clk";
1701 power-domains = <&sys 1664 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1702 resets = <&cpg 408>; 1665 resets = <&cpg 408>;
1703 }; 1666 };
1704 1667
1705 pciec0: pcie@fe000000 { 1668 pciec0: pcie@fe000000 {
1706 compatible = "renesas 1669 compatible = "renesas,pcie-r8a774c0",
1707 "renesas 1670 "renesas,pcie-rcar-gen3";
1708 reg = <0 0xfe000000 0 1671 reg = <0 0xfe000000 0 0x80000>;
1709 #address-cells = <3>; 1672 #address-cells = <3>;
1710 #size-cells = <2>; 1673 #size-cells = <2>;
1711 bus-range = <0x00 0xf 1674 bus-range = <0x00 0xff>;
1712 device_type = "pci"; 1675 device_type = "pci";
1713 ranges = <0x01000000 !! 1676 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
1714 <0x02000000 !! 1677 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
1715 <0x02000000 !! 1678 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
1716 <0x42000000 !! 1679 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1717 /* Map all possible D !! 1680 /* Map all possible DDR as inbound ranges */
1718 dma-ranges = <0x42000 !! 1681 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;
1719 interrupts = <GIC_SPI 1682 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1720 <GIC_SPI 1683 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1721 <GIC_SPI 1684 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1722 #interrupt-cells = <1 1685 #interrupt-cells = <1>;
1723 interrupt-map-mask = 1686 interrupt-map-mask = <0 0 0 0>;
1724 interrupt-map = <0 0 1687 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1725 clocks = <&cpg CPG_MO 1688 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
1726 clock-names = "pcie", 1689 clock-names = "pcie", "pcie_bus";
1727 power-domains = <&sys 1690 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1728 resets = <&cpg 319>; 1691 resets = <&cpg 319>;
1729 iommu-map = <0 &ipmmu <<
1730 iommu-map-mask = <0>; <<
1731 status = "disabled"; <<
1732 }; <<
1733 <<
1734 pciec0_ep: pcie-ep@fe000000 { <<
1735 compatible = "renesas <<
1736 "renesas <<
1737 reg = <0x0 0xfe000000 <<
1738 <0x0 0xfe100000 <<
1739 <0x0 0xfe200000 <<
1740 <0x0 0x30000000 <<
1741 <0x0 0x38000000 <<
1742 reg-names = "apb-base <<
1743 interrupts = <GIC_SPI <<
1744 <GIC_SPI <<
1745 <GIC_SPI <<
1746 clocks = <&cpg CPG_MO <<
1747 clock-names = "pcie"; <<
1748 resets = <&cpg 319>; <<
1749 power-domains = <&sys <<
1750 status = "disabled"; 1692 status = "disabled";
1751 }; 1693 };
1752 1694
1753 vspb0: vsp@fe960000 { 1695 vspb0: vsp@fe960000 {
1754 compatible = "renesas 1696 compatible = "renesas,vsp2";
1755 reg = <0 0xfe960000 0 1697 reg = <0 0xfe960000 0 0x8000>;
1756 interrupts = <GIC_SPI 1698 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
1757 clocks = <&cpg CPG_MO 1699 clocks = <&cpg CPG_MOD 626>;
1758 power-domains = <&sys 1700 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1759 resets = <&cpg 626>; 1701 resets = <&cpg 626>;
1760 renesas,fcp = <&fcpvb 1702 renesas,fcp = <&fcpvb0>;
1761 }; 1703 };
1762 1704
1763 vspd0: vsp@fea20000 { 1705 vspd0: vsp@fea20000 {
1764 compatible = "renesas 1706 compatible = "renesas,vsp2";
1765 reg = <0 0xfea20000 0 1707 reg = <0 0xfea20000 0 0x7000>;
1766 interrupts = <GIC_SPI 1708 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
1767 clocks = <&cpg CPG_MO 1709 clocks = <&cpg CPG_MOD 623>;
1768 power-domains = <&sys 1710 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1769 resets = <&cpg 623>; 1711 resets = <&cpg 623>;
1770 renesas,fcp = <&fcpvd 1712 renesas,fcp = <&fcpvd0>;
1771 }; 1713 };
1772 1714
1773 vspd1: vsp@fea28000 { 1715 vspd1: vsp@fea28000 {
1774 compatible = "renesas 1716 compatible = "renesas,vsp2";
1775 reg = <0 0xfea28000 0 1717 reg = <0 0xfea28000 0 0x7000>;
1776 interrupts = <GIC_SPI 1718 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
1777 clocks = <&cpg CPG_MO 1719 clocks = <&cpg CPG_MOD 622>;
1778 power-domains = <&sys 1720 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1779 resets = <&cpg 622>; 1721 resets = <&cpg 622>;
1780 renesas,fcp = <&fcpvd 1722 renesas,fcp = <&fcpvd1>;
1781 }; 1723 };
1782 1724
1783 vspi0: vsp@fe9a0000 { 1725 vspi0: vsp@fe9a0000 {
1784 compatible = "renesas 1726 compatible = "renesas,vsp2";
1785 reg = <0 0xfe9a0000 0 1727 reg = <0 0xfe9a0000 0 0x8000>;
1786 interrupts = <GIC_SPI 1728 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
1787 clocks = <&cpg CPG_MO 1729 clocks = <&cpg CPG_MOD 631>;
1788 power-domains = <&sys 1730 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1789 resets = <&cpg 631>; 1731 resets = <&cpg 631>;
1790 renesas,fcp = <&fcpvi 1732 renesas,fcp = <&fcpvi0>;
1791 }; 1733 };
1792 1734
1793 fcpvb0: fcp@fe96f000 { 1735 fcpvb0: fcp@fe96f000 {
1794 compatible = "renesas 1736 compatible = "renesas,fcpv";
1795 reg = <0 0xfe96f000 0 1737 reg = <0 0xfe96f000 0 0x200>;
1796 clocks = <&cpg CPG_MO 1738 clocks = <&cpg CPG_MOD 607>;
1797 power-domains = <&sys 1739 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1798 resets = <&cpg 607>; 1740 resets = <&cpg 607>;
1799 iommus = <&ipmmu_vp0 1741 iommus = <&ipmmu_vp0 5>;
1800 }; 1742 };
1801 1743
1802 fcpvd0: fcp@fea27000 { 1744 fcpvd0: fcp@fea27000 {
1803 compatible = "renesas 1745 compatible = "renesas,fcpv";
1804 reg = <0 0xfea27000 0 1746 reg = <0 0xfea27000 0 0x200>;
1805 clocks = <&cpg CPG_MO 1747 clocks = <&cpg CPG_MOD 603>;
1806 power-domains = <&sys 1748 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1807 resets = <&cpg 603>; 1749 resets = <&cpg 603>;
1808 iommus = <&ipmmu_vi0 1750 iommus = <&ipmmu_vi0 8>;
1809 }; 1751 };
1810 1752
1811 fcpvd1: fcp@fea2f000 { 1753 fcpvd1: fcp@fea2f000 {
1812 compatible = "renesas 1754 compatible = "renesas,fcpv";
1813 reg = <0 0xfea2f000 0 1755 reg = <0 0xfea2f000 0 0x200>;
1814 clocks = <&cpg CPG_MO 1756 clocks = <&cpg CPG_MOD 602>;
1815 power-domains = <&sys 1757 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1816 resets = <&cpg 602>; 1758 resets = <&cpg 602>;
1817 iommus = <&ipmmu_vi0 1759 iommus = <&ipmmu_vi0 9>;
1818 }; 1760 };
1819 1761
1820 fcpvi0: fcp@fe9af000 { 1762 fcpvi0: fcp@fe9af000 {
1821 compatible = "renesas 1763 compatible = "renesas,fcpv";
1822 reg = <0 0xfe9af000 0 1764 reg = <0 0xfe9af000 0 0x200>;
1823 clocks = <&cpg CPG_MO 1765 clocks = <&cpg CPG_MOD 611>;
1824 power-domains = <&sys 1766 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1825 resets = <&cpg 611>; 1767 resets = <&cpg 611>;
1826 iommus = <&ipmmu_vp0 1768 iommus = <&ipmmu_vp0 8>;
1827 }; 1769 };
1828 1770
1829 csi40: csi2@feaa0000 { 1771 csi40: csi2@feaa0000 {
1830 compatible = "renesas 1772 compatible = "renesas,r8a774c0-csi2";
1831 reg = <0 0xfeaa0000 0 1773 reg = <0 0xfeaa0000 0 0x10000>;
1832 interrupts = <GIC_SPI 1774 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
1833 clocks = <&cpg CPG_MO 1775 clocks = <&cpg CPG_MOD 716>;
1834 power-domains = <&sys 1776 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1835 resets = <&cpg 716>; 1777 resets = <&cpg 716>;
1836 status = "disabled"; 1778 status = "disabled";
1837 1779
1838 ports { 1780 ports {
1839 #address-cell 1781 #address-cells = <1>;
1840 #size-cells = 1782 #size-cells = <0>;
1841 1783
1842 port@0 { <<
1843 reg = <<
1844 }; <<
1845 <<
1846 port@1 { 1784 port@1 {
1847 #addr 1785 #address-cells = <1>;
1848 #size 1786 #size-cells = <0>;
1849 1787
1850 reg = 1788 reg = <1>;
1851 1789
1852 csi40 1790 csi40vin4: endpoint@0 {
1853 1791 reg = <0>;
1854 1792 remote-endpoint = <&vin4csi40>;
1855 }; 1793 };
1856 csi40 1794 csi40vin5: endpoint@1 {
1857 1795 reg = <1>;
1858 1796 remote-endpoint = <&vin5csi40>;
1859 }; 1797 };
1860 }; 1798 };
1861 }; 1799 };
1862 }; 1800 };
1863 1801
1864 du: display@feb00000 { 1802 du: display@feb00000 {
1865 compatible = "renesas 1803 compatible = "renesas,du-r8a774c0";
1866 reg = <0 0xfeb00000 0 1804 reg = <0 0xfeb00000 0 0x40000>;
1867 interrupts = <GIC_SPI 1805 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
1868 <GIC_SPI 1806 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
1869 clocks = <&cpg CPG_MO !! 1807 clocks = <&cpg CPG_MOD 724>,
>> 1808 <&cpg CPG_MOD 723>;
1870 clock-names = "du.0", 1809 clock-names = "du.0", "du.1";
1871 resets = <&cpg 724>; !! 1810 vsps = <&vspd0 0>, <&vspd1 0>;
1872 reset-names = "du.0"; <<
1873 renesas,vsps = <&vspd <<
1874 <<
1875 status = "disabled"; 1811 status = "disabled";
1876 1812
1877 ports { 1813 ports {
1878 #address-cell 1814 #address-cells = <1>;
1879 #size-cells = 1815 #size-cells = <0>;
1880 1816
1881 port@0 { 1817 port@0 {
1882 reg = 1818 reg = <0>;
>> 1819 du_out_rgb: endpoint {
>> 1820 };
1883 }; 1821 };
1884 1822
1885 port@1 { 1823 port@1 {
1886 reg = 1824 reg = <1>;
1887 du_ou 1825 du_out_lvds0: endpoint {
1888 1826 remote-endpoint = <&lvds0_in>;
1889 }; 1827 };
1890 }; 1828 };
1891 1829
1892 port@2 { 1830 port@2 {
1893 reg = 1831 reg = <2>;
1894 du_ou 1832 du_out_lvds1: endpoint {
1895 1833 remote-endpoint = <&lvds1_in>;
1896 }; 1834 };
1897 }; 1835 };
1898 }; 1836 };
1899 }; 1837 };
1900 1838
1901 lvds0: lvds-encoder@feb90000 1839 lvds0: lvds-encoder@feb90000 {
1902 compatible = "renesas 1840 compatible = "renesas,r8a774c0-lvds";
1903 reg = <0 0xfeb90000 0 1841 reg = <0 0xfeb90000 0 0x20>;
1904 clocks = <&cpg CPG_MO 1842 clocks = <&cpg CPG_MOD 727>;
1905 power-domains = <&sys 1843 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1906 resets = <&cpg 727>; 1844 resets = <&cpg 727>;
1907 status = "disabled"; 1845 status = "disabled";
1908 1846
1909 renesas,companion = < 1847 renesas,companion = <&lvds1>;
1910 1848
1911 ports { 1849 ports {
1912 #address-cell 1850 #address-cells = <1>;
1913 #size-cells = 1851 #size-cells = <0>;
1914 1852
1915 port@0 { 1853 port@0 {
1916 reg = 1854 reg = <0>;
1917 lvds0 1855 lvds0_in: endpoint {
1918 1856 remote-endpoint = <&du_out_lvds0>;
1919 }; 1857 };
1920 }; 1858 };
1921 1859
1922 port@1 { 1860 port@1 {
1923 reg = 1861 reg = <1>;
>> 1862 lvds0_out: endpoint {
>> 1863 };
1924 }; 1864 };
1925 }; 1865 };
1926 }; 1866 };
1927 1867
1928 lvds1: lvds-encoder@feb90100 1868 lvds1: lvds-encoder@feb90100 {
1929 compatible = "renesas 1869 compatible = "renesas,r8a774c0-lvds";
1930 reg = <0 0xfeb90100 0 1870 reg = <0 0xfeb90100 0 0x20>;
1931 clocks = <&cpg CPG_MO 1871 clocks = <&cpg CPG_MOD 727>;
1932 power-domains = <&sys 1872 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1933 resets = <&cpg 726>; 1873 resets = <&cpg 726>;
1934 status = "disabled"; 1874 status = "disabled";
1935 1875
1936 ports { 1876 ports {
1937 #address-cell 1877 #address-cells = <1>;
1938 #size-cells = 1878 #size-cells = <0>;
1939 1879
1940 port@0 { 1880 port@0 {
1941 reg = 1881 reg = <0>;
1942 lvds1 1882 lvds1_in: endpoint {
1943 1883 remote-endpoint = <&du_out_lvds1>;
1944 }; 1884 };
1945 }; 1885 };
1946 1886
1947 port@1 { 1887 port@1 {
1948 reg = 1888 reg = <1>;
>> 1889 lvds1_out: endpoint {
>> 1890 };
1949 }; 1891 };
1950 }; 1892 };
1951 }; 1893 };
1952 1894
1953 prr: chipid@fff00044 { 1895 prr: chipid@fff00044 {
1954 compatible = "renesas 1896 compatible = "renesas,prr";
1955 reg = <0 0xfff00044 0 1897 reg = <0 0xfff00044 0 4>;
1956 }; 1898 };
1957 }; 1899 };
1958 1900
1959 thermal-zones { 1901 thermal-zones {
1960 cpu-thermal { 1902 cpu-thermal {
1961 polling-delay-passive 1903 polling-delay-passive = <250>;
1962 polling-delay = <0>; !! 1904 polling-delay = <1000>;
1963 thermal-sensors = <&t 1905 thermal-sensors = <&thermal>;
1964 sustainable-power = < <<
1965 1906
1966 cooling-maps { 1907 cooling-maps {
1967 map0 { <<
1968 trip <<
1969 cooli <<
1970 contr <<
1971 }; <<
1972 }; 1908 };
1973 1909
1974 trips { 1910 trips {
1975 sensor1_crit: !! 1911 cpu-crit {
1976 tempe 1912 temperature = <120000>;
1977 hyste 1913 hysteresis = <2000>;
1978 type 1914 type = "critical";
1979 }; 1915 };
1980 <<
1981 target: trip- <<
1982 tempe <<
1983 hyste <<
1984 type <<
1985 }; <<
1986 }; 1916 };
1987 }; 1917 };
1988 }; 1918 };
1989 1919
1990 timer { 1920 timer {
1991 compatible = "arm,armv8-timer 1921 compatible = "arm,armv8-timer";
1992 interrupts-extended = <&gic G 1922 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1993 <&gic G 1923 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1994 <&gic G 1924 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1995 <&gic G 1925 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
1996 interrupt-names = "sec-phys", <<
1997 }; 1926 };
1998 1927
1999 /* External USB clocks - can be overr 1928 /* External USB clocks - can be overridden by the board */
2000 usb3s0_clk: usb3s0 { 1929 usb3s0_clk: usb3s0 {
2001 compatible = "fixed-clock"; 1930 compatible = "fixed-clock";
2002 #clock-cells = <0>; 1931 #clock-cells = <0>;
2003 clock-frequency = <0>; 1932 clock-frequency = <0>;
2004 }; 1933 };
2005 1934
2006 usb_extal_clk: usb_extal { 1935 usb_extal_clk: usb_extal {
2007 compatible = "fixed-clock"; 1936 compatible = "fixed-clock";
2008 #clock-cells = <0>; 1937 #clock-cells = <0>;
2009 clock-frequency = <0>; 1938 clock-frequency = <0>;
2010 }; 1939 };
2011 }; 1940 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.