1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * Device Tree Source for the RZ/G2E (R8A774C0 3 * Device Tree Source for the RZ/G2E (R8A774C0) SoC
4 * 4 *
5 * Copyright (C) 2018-2019 Renesas Electronics 5 * Copyright (C) 2018-2019 Renesas Electronics Corp.
6 */ 6 */
7 7
8 #include <dt-bindings/clock/r8a774c0-cpg-mssr. 8 #include <dt-bindings/clock/r8a774c0-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm 9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a774c0-sysc.h> 10 #include <dt-bindings/power/r8a774c0-sysc.h>
11 11
12 / { 12 / {
13 compatible = "renesas,r8a774c0"; 13 compatible = "renesas,r8a774c0";
14 #address-cells = <2>; 14 #address-cells = <2>;
15 #size-cells = <2>; 15 #size-cells = <2>;
16 16
17 /* 17 /*
18 * The external audio clocks are confi 18 * The external audio clocks are configured as 0 Hz fixed frequency
19 * clocks by default. 19 * clocks by default.
20 * Boards that provide audio clocks sh 20 * Boards that provide audio clocks should override them.
21 */ 21 */
22 audio_clk_a: audio_clk_a { 22 audio_clk_a: audio_clk_a {
23 compatible = "fixed-clock"; 23 compatible = "fixed-clock";
24 #clock-cells = <0>; 24 #clock-cells = <0>;
25 clock-frequency = <0>; 25 clock-frequency = <0>;
26 }; 26 };
27 27
28 audio_clk_b: audio_clk_b { 28 audio_clk_b: audio_clk_b {
29 compatible = "fixed-clock"; 29 compatible = "fixed-clock";
30 #clock-cells = <0>; 30 #clock-cells = <0>;
31 clock-frequency = <0>; 31 clock-frequency = <0>;
32 }; 32 };
33 33
34 audio_clk_c: audio_clk_c { 34 audio_clk_c: audio_clk_c {
35 compatible = "fixed-clock"; 35 compatible = "fixed-clock";
36 #clock-cells = <0>; 36 #clock-cells = <0>;
37 clock-frequency = <0>; 37 clock-frequency = <0>;
38 }; 38 };
39 39
40 /* External CAN clock - to be overridd 40 /* External CAN clock - to be overridden by boards that provide it */
41 can_clk: can { 41 can_clk: can {
42 compatible = "fixed-clock"; 42 compatible = "fixed-clock";
43 #clock-cells = <0>; 43 #clock-cells = <0>;
44 clock-frequency = <0>; 44 clock-frequency = <0>;
45 }; 45 };
46 46
47 cluster1_opp: opp-table-1 { !! 47 cluster1_opp: opp_table10 {
48 compatible = "operating-points 48 compatible = "operating-points-v2";
49 opp-shared; 49 opp-shared;
50 opp-800000000 { 50 opp-800000000 {
51 opp-hz = /bits/ 64 <80 51 opp-hz = /bits/ 64 <800000000>;
>> 52 opp-microvolt = <820000>;
52 clock-latency-ns = <30 53 clock-latency-ns = <300000>;
53 }; 54 };
54 opp-1000000000 { 55 opp-1000000000 {
55 opp-hz = /bits/ 64 <10 56 opp-hz = /bits/ 64 <1000000000>;
>> 57 opp-microvolt = <820000>;
56 clock-latency-ns = <30 58 clock-latency-ns = <300000>;
57 }; 59 };
58 opp-1200000000 { 60 opp-1200000000 {
59 opp-hz = /bits/ 64 <12 61 opp-hz = /bits/ 64 <1200000000>;
>> 62 opp-microvolt = <820000>;
60 clock-latency-ns = <30 63 clock-latency-ns = <300000>;
61 opp-suspend; 64 opp-suspend;
62 }; 65 };
63 }; 66 };
64 67
65 cpus { 68 cpus {
66 #address-cells = <1>; 69 #address-cells = <1>;
67 #size-cells = <0>; 70 #size-cells = <0>;
68 71
69 a53_0: cpu@0 { 72 a53_0: cpu@0 {
70 compatible = "arm,cort 73 compatible = "arm,cortex-a53";
71 reg = <0>; 74 reg = <0>;
72 device_type = "cpu"; 75 device_type = "cpu";
73 #cooling-cells = <2>; 76 #cooling-cells = <2>;
74 power-domains = <&sysc 77 power-domains = <&sysc R8A774C0_PD_CA53_CPU0>;
75 next-level-cache = <&L 78 next-level-cache = <&L2_CA53>;
76 enable-method = "psci" 79 enable-method = "psci";
77 dynamic-power-coeffici 80 dynamic-power-coefficient = <277>;
78 clocks = <&cpg CPG_COR 81 clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>;
79 operating-points-v2 = 82 operating-points-v2 = <&cluster1_opp>;
80 }; 83 };
81 84
82 a53_1: cpu@1 { 85 a53_1: cpu@1 {
83 compatible = "arm,cort 86 compatible = "arm,cortex-a53";
84 reg = <1>; 87 reg = <1>;
85 device_type = "cpu"; 88 device_type = "cpu";
86 power-domains = <&sysc 89 power-domains = <&sysc R8A774C0_PD_CA53_CPU1>;
87 next-level-cache = <&L 90 next-level-cache = <&L2_CA53>;
88 enable-method = "psci" 91 enable-method = "psci";
89 clocks = <&cpg CPG_COR 92 clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>;
90 operating-points-v2 = 93 operating-points-v2 = <&cluster1_opp>;
91 }; 94 };
92 95
93 L2_CA53: cache-controller-0 { 96 L2_CA53: cache-controller-0 {
94 compatible = "cache"; 97 compatible = "cache";
95 power-domains = <&sysc 98 power-domains = <&sysc R8A774C0_PD_CA53_SCU>;
96 cache-unified; 99 cache-unified;
97 cache-level = <2>; 100 cache-level = <2>;
98 }; 101 };
99 }; 102 };
100 103
101 extal_clk: extal { 104 extal_clk: extal {
102 compatible = "fixed-clock"; 105 compatible = "fixed-clock";
103 #clock-cells = <0>; 106 #clock-cells = <0>;
104 /* This value must be overridd 107 /* This value must be overridden by the board */
105 clock-frequency = <0>; 108 clock-frequency = <0>;
106 }; 109 };
107 110
108 /* External PCIe clock - can be overri 111 /* External PCIe clock - can be overridden by the board */
109 pcie_bus_clk: pcie_bus { 112 pcie_bus_clk: pcie_bus {
110 compatible = "fixed-clock"; 113 compatible = "fixed-clock";
111 #clock-cells = <0>; 114 #clock-cells = <0>;
112 clock-frequency = <0>; 115 clock-frequency = <0>;
113 }; 116 };
114 117
115 pmu_a53 { 118 pmu_a53 {
116 compatible = "arm,cortex-a53-p 119 compatible = "arm,cortex-a53-pmu";
117 interrupts-extended = <&gic GI 120 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
118 <&gic GI 121 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
119 interrupt-affinity = <&a53_0>, 122 interrupt-affinity = <&a53_0>, <&a53_1>;
120 }; 123 };
121 124
122 psci { 125 psci {
123 compatible = "arm,psci-1.0", " 126 compatible = "arm,psci-1.0", "arm,psci-0.2";
124 method = "smc"; 127 method = "smc";
125 }; 128 };
126 129
127 /* External SCIF clock - to be overrid 130 /* External SCIF clock - to be overridden by boards that provide it */
128 scif_clk: scif { 131 scif_clk: scif {
129 compatible = "fixed-clock"; 132 compatible = "fixed-clock";
130 #clock-cells = <0>; 133 #clock-cells = <0>;
131 clock-frequency = <0>; 134 clock-frequency = <0>;
132 }; 135 };
133 136
134 soc: soc { 137 soc: soc {
135 compatible = "simple-bus"; 138 compatible = "simple-bus";
136 interrupt-parent = <&gic>; 139 interrupt-parent = <&gic>;
137 #address-cells = <2>; 140 #address-cells = <2>;
138 #size-cells = <2>; 141 #size-cells = <2>;
139 ranges; 142 ranges;
140 143
141 rwdt: watchdog@e6020000 { 144 rwdt: watchdog@e6020000 {
142 compatible = "renesas, 145 compatible = "renesas,r8a774c0-wdt",
143 "renesas, 146 "renesas,rcar-gen3-wdt";
144 reg = <0 0xe6020000 0 147 reg = <0 0xe6020000 0 0x0c>;
145 interrupts = <GIC_SPI <<
146 clocks = <&cpg CPG_MOD 148 clocks = <&cpg CPG_MOD 402>;
147 power-domains = <&sysc 149 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
148 resets = <&cpg 402>; 150 resets = <&cpg 402>;
149 status = "disabled"; 151 status = "disabled";
150 }; 152 };
151 153
152 gpio0: gpio@e6050000 { 154 gpio0: gpio@e6050000 {
153 compatible = "renesas, 155 compatible = "renesas,gpio-r8a774c0",
154 "renesas, 156 "renesas,rcar-gen3-gpio";
155 reg = <0 0xe6050000 0 157 reg = <0 0xe6050000 0 0x50>;
156 interrupts = <GIC_SPI 158 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
157 #gpio-cells = <2>; 159 #gpio-cells = <2>;
158 gpio-controller; 160 gpio-controller;
159 gpio-ranges = <&pfc 0 161 gpio-ranges = <&pfc 0 0 18>;
160 #interrupt-cells = <2> 162 #interrupt-cells = <2>;
161 interrupt-controller; 163 interrupt-controller;
162 clocks = <&cpg CPG_MOD 164 clocks = <&cpg CPG_MOD 912>;
163 power-domains = <&sysc 165 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
164 resets = <&cpg 912>; 166 resets = <&cpg 912>;
165 }; 167 };
166 168
167 gpio1: gpio@e6051000 { 169 gpio1: gpio@e6051000 {
168 compatible = "renesas, 170 compatible = "renesas,gpio-r8a774c0",
169 "renesas, 171 "renesas,rcar-gen3-gpio";
170 reg = <0 0xe6051000 0 172 reg = <0 0xe6051000 0 0x50>;
171 interrupts = <GIC_SPI 173 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
172 #gpio-cells = <2>; 174 #gpio-cells = <2>;
173 gpio-controller; 175 gpio-controller;
174 gpio-ranges = <&pfc 0 176 gpio-ranges = <&pfc 0 32 23>;
175 #interrupt-cells = <2> 177 #interrupt-cells = <2>;
176 interrupt-controller; 178 interrupt-controller;
177 clocks = <&cpg CPG_MOD 179 clocks = <&cpg CPG_MOD 911>;
178 power-domains = <&sysc 180 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
179 resets = <&cpg 911>; 181 resets = <&cpg 911>;
180 }; 182 };
181 183
182 gpio2: gpio@e6052000 { 184 gpio2: gpio@e6052000 {
183 compatible = "renesas, 185 compatible = "renesas,gpio-r8a774c0",
184 "renesas, 186 "renesas,rcar-gen3-gpio";
185 reg = <0 0xe6052000 0 187 reg = <0 0xe6052000 0 0x50>;
186 interrupts = <GIC_SPI 188 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
187 #gpio-cells = <2>; 189 #gpio-cells = <2>;
188 gpio-controller; 190 gpio-controller;
189 gpio-ranges = <&pfc 0 191 gpio-ranges = <&pfc 0 64 26>;
190 #interrupt-cells = <2> 192 #interrupt-cells = <2>;
191 interrupt-controller; 193 interrupt-controller;
192 clocks = <&cpg CPG_MOD 194 clocks = <&cpg CPG_MOD 910>;
193 power-domains = <&sysc 195 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
194 resets = <&cpg 910>; 196 resets = <&cpg 910>;
195 }; 197 };
196 198
197 gpio3: gpio@e6053000 { 199 gpio3: gpio@e6053000 {
198 compatible = "renesas, 200 compatible = "renesas,gpio-r8a774c0",
199 "renesas, 201 "renesas,rcar-gen3-gpio";
200 reg = <0 0xe6053000 0 202 reg = <0 0xe6053000 0 0x50>;
201 interrupts = <GIC_SPI 203 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
202 #gpio-cells = <2>; 204 #gpio-cells = <2>;
203 gpio-controller; 205 gpio-controller;
204 gpio-ranges = <&pfc 0 206 gpio-ranges = <&pfc 0 96 16>;
205 #interrupt-cells = <2> 207 #interrupt-cells = <2>;
206 interrupt-controller; 208 interrupt-controller;
207 clocks = <&cpg CPG_MOD 209 clocks = <&cpg CPG_MOD 909>;
208 power-domains = <&sysc 210 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
209 resets = <&cpg 909>; 211 resets = <&cpg 909>;
210 }; 212 };
211 213
212 gpio4: gpio@e6054000 { 214 gpio4: gpio@e6054000 {
213 compatible = "renesas, 215 compatible = "renesas,gpio-r8a774c0",
214 "renesas, 216 "renesas,rcar-gen3-gpio";
215 reg = <0 0xe6054000 0 217 reg = <0 0xe6054000 0 0x50>;
216 interrupts = <GIC_SPI 218 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
217 #gpio-cells = <2>; 219 #gpio-cells = <2>;
218 gpio-controller; 220 gpio-controller;
219 gpio-ranges = <&pfc 0 221 gpio-ranges = <&pfc 0 128 11>;
220 #interrupt-cells = <2> 222 #interrupt-cells = <2>;
221 interrupt-controller; 223 interrupt-controller;
222 clocks = <&cpg CPG_MOD 224 clocks = <&cpg CPG_MOD 908>;
223 power-domains = <&sysc 225 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
224 resets = <&cpg 908>; 226 resets = <&cpg 908>;
225 }; 227 };
226 228
227 gpio5: gpio@e6055000 { 229 gpio5: gpio@e6055000 {
228 compatible = "renesas, 230 compatible = "renesas,gpio-r8a774c0",
229 "renesas, 231 "renesas,rcar-gen3-gpio";
230 reg = <0 0xe6055000 0 232 reg = <0 0xe6055000 0 0x50>;
231 interrupts = <GIC_SPI 233 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
232 #gpio-cells = <2>; 234 #gpio-cells = <2>;
233 gpio-controller; 235 gpio-controller;
234 gpio-ranges = <&pfc 0 236 gpio-ranges = <&pfc 0 160 20>;
235 #interrupt-cells = <2> 237 #interrupt-cells = <2>;
236 interrupt-controller; 238 interrupt-controller;
237 clocks = <&cpg CPG_MOD 239 clocks = <&cpg CPG_MOD 907>;
238 power-domains = <&sysc 240 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
239 resets = <&cpg 907>; 241 resets = <&cpg 907>;
240 }; 242 };
241 243
242 gpio6: gpio@e6055400 { 244 gpio6: gpio@e6055400 {
243 compatible = "renesas, 245 compatible = "renesas,gpio-r8a774c0",
244 "renesas, 246 "renesas,rcar-gen3-gpio";
245 reg = <0 0xe6055400 0 247 reg = <0 0xe6055400 0 0x50>;
246 interrupts = <GIC_SPI 248 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
247 #gpio-cells = <2>; 249 #gpio-cells = <2>;
248 gpio-controller; 250 gpio-controller;
249 gpio-ranges = <&pfc 0 251 gpio-ranges = <&pfc 0 192 18>;
250 #interrupt-cells = <2> 252 #interrupt-cells = <2>;
251 interrupt-controller; 253 interrupt-controller;
252 clocks = <&cpg CPG_MOD 254 clocks = <&cpg CPG_MOD 906>;
253 power-domains = <&sysc 255 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
254 resets = <&cpg 906>; 256 resets = <&cpg 906>;
255 }; 257 };
256 258
257 pfc: pinctrl@e6060000 { !! 259 pfc: pin-controller@e6060000 {
258 compatible = "renesas, 260 compatible = "renesas,pfc-r8a774c0";
259 reg = <0 0xe6060000 0 261 reg = <0 0xe6060000 0 0x508>;
260 }; 262 };
261 263
262 cmt0: timer@e60f0000 { 264 cmt0: timer@e60f0000 {
263 compatible = "renesas, 265 compatible = "renesas,r8a774c0-cmt0",
264 "renesas, 266 "renesas,rcar-gen3-cmt0";
265 reg = <0 0xe60f0000 0 267 reg = <0 0xe60f0000 0 0x1004>;
266 interrupts = <GIC_SPI 268 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
267 <GIC_SPI 269 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
268 clocks = <&cpg CPG_MOD 270 clocks = <&cpg CPG_MOD 303>;
269 clock-names = "fck"; 271 clock-names = "fck";
270 power-domains = <&sysc 272 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
271 resets = <&cpg 303>; 273 resets = <&cpg 303>;
272 status = "disabled"; 274 status = "disabled";
273 }; 275 };
274 276
275 cmt1: timer@e6130000 { 277 cmt1: timer@e6130000 {
276 compatible = "renesas, 278 compatible = "renesas,r8a774c0-cmt1",
277 "renesas, 279 "renesas,rcar-gen3-cmt1";
278 reg = <0 0xe6130000 0 280 reg = <0 0xe6130000 0 0x1004>;
279 interrupts = <GIC_SPI 281 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
280 <GIC_SPI 282 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
281 <GIC_SPI 283 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
282 <GIC_SPI 284 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
283 <GIC_SPI 285 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
284 <GIC_SPI 286 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
285 <GIC_SPI 287 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
286 <GIC_SPI 288 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
287 clocks = <&cpg CPG_MOD 289 clocks = <&cpg CPG_MOD 302>;
288 clock-names = "fck"; 290 clock-names = "fck";
289 power-domains = <&sysc 291 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
290 resets = <&cpg 302>; 292 resets = <&cpg 302>;
291 status = "disabled"; 293 status = "disabled";
292 }; 294 };
293 295
294 cmt2: timer@e6140000 { 296 cmt2: timer@e6140000 {
295 compatible = "renesas, 297 compatible = "renesas,r8a774c0-cmt1",
296 "renesas, 298 "renesas,rcar-gen3-cmt1";
297 reg = <0 0xe6140000 0 299 reg = <0 0xe6140000 0 0x1004>;
298 interrupts = <GIC_SPI 300 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
299 <GIC_SPI 301 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
300 <GIC_SPI 302 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
301 <GIC_SPI 303 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
302 <GIC_SPI 304 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
303 <GIC_SPI 305 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
304 <GIC_SPI 306 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
305 <GIC_SPI 307 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
306 clocks = <&cpg CPG_MOD 308 clocks = <&cpg CPG_MOD 301>;
307 clock-names = "fck"; 309 clock-names = "fck";
308 power-domains = <&sysc 310 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
309 resets = <&cpg 301>; 311 resets = <&cpg 301>;
310 status = "disabled"; 312 status = "disabled";
311 }; 313 };
312 314
313 cmt3: timer@e6148000 { 315 cmt3: timer@e6148000 {
314 compatible = "renesas, 316 compatible = "renesas,r8a774c0-cmt1",
315 "renesas, 317 "renesas,rcar-gen3-cmt1";
316 reg = <0 0xe6148000 0 318 reg = <0 0xe6148000 0 0x1004>;
317 interrupts = <GIC_SPI 319 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
318 <GIC_SPI 320 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
319 <GIC_SPI 321 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
320 <GIC_SPI 322 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
321 <GIC_SPI 323 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
322 <GIC_SPI 324 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
323 <GIC_SPI 325 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
324 <GIC_SPI 326 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
325 clocks = <&cpg CPG_MOD 327 clocks = <&cpg CPG_MOD 300>;
326 clock-names = "fck"; 328 clock-names = "fck";
327 power-domains = <&sysc 329 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
328 resets = <&cpg 300>; 330 resets = <&cpg 300>;
329 status = "disabled"; 331 status = "disabled";
330 }; 332 };
331 333
332 cpg: clock-controller@e6150000 334 cpg: clock-controller@e6150000 {
333 compatible = "renesas, 335 compatible = "renesas,r8a774c0-cpg-mssr";
334 reg = <0 0xe6150000 0 336 reg = <0 0xe6150000 0 0x1000>;
335 clocks = <&extal_clk>; 337 clocks = <&extal_clk>;
336 clock-names = "extal"; 338 clock-names = "extal";
337 #clock-cells = <2>; 339 #clock-cells = <2>;
338 #power-domain-cells = 340 #power-domain-cells = <0>;
339 #reset-cells = <1>; 341 #reset-cells = <1>;
340 }; 342 };
341 343
342 rst: reset-controller@e6160000 344 rst: reset-controller@e6160000 {
343 compatible = "renesas, 345 compatible = "renesas,r8a774c0-rst";
344 reg = <0 0xe6160000 0 346 reg = <0 0xe6160000 0 0x0200>;
345 }; 347 };
346 348
347 sysc: system-controller@e61800 349 sysc: system-controller@e6180000 {
348 compatible = "renesas, 350 compatible = "renesas,r8a774c0-sysc";
349 reg = <0 0xe6180000 0 351 reg = <0 0xe6180000 0 0x0400>;
350 #power-domain-cells = 352 #power-domain-cells = <1>;
351 }; 353 };
352 354
353 thermal: thermal@e6190000 { 355 thermal: thermal@e6190000 {
354 compatible = "renesas, 356 compatible = "renesas,thermal-r8a774c0";
355 reg = <0 0xe6190000 0 357 reg = <0 0xe6190000 0 0x10>, <0 0xe6190100 0 0x38>;
356 interrupts = <GIC_SPI 358 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
357 <GIC_SPI 359 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
358 <GIC_SPI 360 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
359 clocks = <&cpg CPG_MOD 361 clocks = <&cpg CPG_MOD 522>;
360 power-domains = <&sysc 362 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
361 resets = <&cpg 522>; 363 resets = <&cpg 522>;
362 #thermal-sensor-cells 364 #thermal-sensor-cells = <0>;
363 }; 365 };
364 366
365 intc_ex: interrupt-controller@ 367 intc_ex: interrupt-controller@e61c0000 {
366 compatible = "renesas, 368 compatible = "renesas,intc-ex-r8a774c0", "renesas,irqc";
367 #interrupt-cells = <2> 369 #interrupt-cells = <2>;
368 interrupt-controller; 370 interrupt-controller;
369 reg = <0 0xe61c0000 0 371 reg = <0 0xe61c0000 0 0x200>;
370 interrupts = <GIC_SPI 372 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
371 <GIC_SPI 373 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
372 <GIC_SPI 374 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
373 <GIC_SPI 375 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
374 <GIC_SPI 376 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
375 <GIC_SPI 377 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
376 clocks = <&cpg CPG_MOD 378 clocks = <&cpg CPG_MOD 407>;
377 power-domains = <&sysc 379 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
378 resets = <&cpg 407>; 380 resets = <&cpg 407>;
379 }; 381 };
380 382
381 tmu0: timer@e61e0000 { 383 tmu0: timer@e61e0000 {
382 compatible = "renesas, 384 compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
383 reg = <0 0xe61e0000 0 385 reg = <0 0xe61e0000 0 0x30>;
384 interrupts = <GIC_SPI 386 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
385 <GIC_SPI 387 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
386 <GIC_SPI 388 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
387 interrupt-names = "tun <<
388 clocks = <&cpg CPG_MOD 389 clocks = <&cpg CPG_MOD 125>;
389 clock-names = "fck"; 390 clock-names = "fck";
390 power-domains = <&sysc 391 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
391 resets = <&cpg 125>; 392 resets = <&cpg 125>;
392 status = "disabled"; 393 status = "disabled";
393 }; 394 };
394 395
395 tmu1: timer@e6fc0000 { 396 tmu1: timer@e6fc0000 {
396 compatible = "renesas, 397 compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
397 reg = <0 0xe6fc0000 0 398 reg = <0 0xe6fc0000 0 0x30>;
398 interrupts = <GIC_SPI 399 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
399 <GIC_SPI 400 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
400 <GIC_SPI !! 401 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
401 <GIC_SPI <<
402 interrupt-names = "tun <<
403 clocks = <&cpg CPG_MOD 402 clocks = <&cpg CPG_MOD 124>;
404 clock-names = "fck"; 403 clock-names = "fck";
405 power-domains = <&sysc 404 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
406 resets = <&cpg 124>; 405 resets = <&cpg 124>;
407 status = "disabled"; 406 status = "disabled";
408 }; 407 };
409 408
410 tmu2: timer@e6fd0000 { 409 tmu2: timer@e6fd0000 {
411 compatible = "renesas, 410 compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
412 reg = <0 0xe6fd0000 0 411 reg = <0 0xe6fd0000 0 0x30>;
413 interrupts = <GIC_SPI 412 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
414 <GIC_SPI 413 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
415 <GIC_SPI !! 414 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
416 <GIC_SPI <<
417 interrupt-names = "tun <<
418 clocks = <&cpg CPG_MOD 415 clocks = <&cpg CPG_MOD 123>;
419 clock-names = "fck"; 416 clock-names = "fck";
420 power-domains = <&sysc 417 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
421 resets = <&cpg 123>; 418 resets = <&cpg 123>;
422 status = "disabled"; 419 status = "disabled";
423 }; 420 };
424 421
425 tmu3: timer@e6fe0000 { 422 tmu3: timer@e6fe0000 {
426 compatible = "renesas, 423 compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
427 reg = <0 0xe6fe0000 0 424 reg = <0 0xe6fe0000 0 0x30>;
428 interrupts = <GIC_SPI 425 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
429 <GIC_SPI 426 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
430 <GIC_SPI 427 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
431 interrupt-names = "tun <<
432 clocks = <&cpg CPG_MOD 428 clocks = <&cpg CPG_MOD 122>;
433 clock-names = "fck"; 429 clock-names = "fck";
434 power-domains = <&sysc 430 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
435 resets = <&cpg 122>; 431 resets = <&cpg 122>;
436 status = "disabled"; 432 status = "disabled";
437 }; 433 };
438 434
439 tmu4: timer@ffc00000 { 435 tmu4: timer@ffc00000 {
440 compatible = "renesas, 436 compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
441 reg = <0 0xffc00000 0 437 reg = <0 0xffc00000 0 0x30>;
442 interrupts = <GIC_SPI 438 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
443 <GIC_SPI 439 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
444 <GIC_SPI 440 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
445 interrupt-names = "tun <<
446 clocks = <&cpg CPG_MOD 441 clocks = <&cpg CPG_MOD 121>;
447 clock-names = "fck"; 442 clock-names = "fck";
448 power-domains = <&sysc 443 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
449 resets = <&cpg 121>; 444 resets = <&cpg 121>;
450 status = "disabled"; 445 status = "disabled";
451 }; 446 };
452 447
453 i2c0: i2c@e6500000 { 448 i2c0: i2c@e6500000 {
454 #address-cells = <1>; 449 #address-cells = <1>;
455 #size-cells = <0>; 450 #size-cells = <0>;
456 compatible = "renesas, 451 compatible = "renesas,i2c-r8a774c0",
457 "renesas, 452 "renesas,rcar-gen3-i2c";
458 reg = <0 0xe6500000 0 453 reg = <0 0xe6500000 0 0x40>;
459 interrupts = <GIC_SPI 454 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
460 clocks = <&cpg CPG_MOD 455 clocks = <&cpg CPG_MOD 931>;
461 power-domains = <&sysc 456 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
462 resets = <&cpg 931>; 457 resets = <&cpg 931>;
463 dmas = <&dmac1 0x91>, 458 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
464 <&dmac2 0x91>, 459 <&dmac2 0x91>, <&dmac2 0x90>;
465 dma-names = "tx", "rx" 460 dma-names = "tx", "rx", "tx", "rx";
466 i2c-scl-internal-delay 461 i2c-scl-internal-delay-ns = <110>;
467 status = "disabled"; 462 status = "disabled";
468 }; 463 };
469 464
470 i2c1: i2c@e6508000 { 465 i2c1: i2c@e6508000 {
471 #address-cells = <1>; 466 #address-cells = <1>;
472 #size-cells = <0>; 467 #size-cells = <0>;
473 compatible = "renesas, 468 compatible = "renesas,i2c-r8a774c0",
474 "renesas, 469 "renesas,rcar-gen3-i2c";
475 reg = <0 0xe6508000 0 470 reg = <0 0xe6508000 0 0x40>;
476 interrupts = <GIC_SPI 471 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
477 clocks = <&cpg CPG_MOD 472 clocks = <&cpg CPG_MOD 930>;
478 power-domains = <&sysc 473 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
479 resets = <&cpg 930>; 474 resets = <&cpg 930>;
480 dmas = <&dmac1 0x93>, 475 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
481 <&dmac2 0x93>, 476 <&dmac2 0x93>, <&dmac2 0x92>;
482 dma-names = "tx", "rx" 477 dma-names = "tx", "rx", "tx", "rx";
483 i2c-scl-internal-delay 478 i2c-scl-internal-delay-ns = <6>;
484 status = "disabled"; 479 status = "disabled";
485 }; 480 };
486 481
487 i2c2: i2c@e6510000 { 482 i2c2: i2c@e6510000 {
488 #address-cells = <1>; 483 #address-cells = <1>;
489 #size-cells = <0>; 484 #size-cells = <0>;
490 compatible = "renesas, 485 compatible = "renesas,i2c-r8a774c0",
491 "renesas, 486 "renesas,rcar-gen3-i2c";
492 reg = <0 0xe6510000 0 487 reg = <0 0xe6510000 0 0x40>;
493 interrupts = <GIC_SPI 488 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
494 clocks = <&cpg CPG_MOD 489 clocks = <&cpg CPG_MOD 929>;
495 power-domains = <&sysc 490 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
496 resets = <&cpg 929>; 491 resets = <&cpg 929>;
497 dmas = <&dmac1 0x95>, 492 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
498 <&dmac2 0x95>, 493 <&dmac2 0x95>, <&dmac2 0x94>;
499 dma-names = "tx", "rx" 494 dma-names = "tx", "rx", "tx", "rx";
500 i2c-scl-internal-delay 495 i2c-scl-internal-delay-ns = <6>;
501 status = "disabled"; 496 status = "disabled";
502 }; 497 };
503 498
504 i2c3: i2c@e66d0000 { 499 i2c3: i2c@e66d0000 {
505 #address-cells = <1>; 500 #address-cells = <1>;
506 #size-cells = <0>; 501 #size-cells = <0>;
507 compatible = "renesas, 502 compatible = "renesas,i2c-r8a774c0",
508 "renesas, 503 "renesas,rcar-gen3-i2c";
509 reg = <0 0xe66d0000 0 504 reg = <0 0xe66d0000 0 0x40>;
510 interrupts = <GIC_SPI 505 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
511 clocks = <&cpg CPG_MOD 506 clocks = <&cpg CPG_MOD 928>;
512 power-domains = <&sysc 507 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
513 resets = <&cpg 928>; 508 resets = <&cpg 928>;
514 dmas = <&dmac0 0x97>, 509 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
515 dma-names = "tx", "rx" 510 dma-names = "tx", "rx";
516 i2c-scl-internal-delay 511 i2c-scl-internal-delay-ns = <110>;
517 status = "disabled"; 512 status = "disabled";
518 }; 513 };
519 514
520 i2c4: i2c@e66d8000 { 515 i2c4: i2c@e66d8000 {
521 #address-cells = <1>; 516 #address-cells = <1>;
522 #size-cells = <0>; 517 #size-cells = <0>;
523 compatible = "renesas, 518 compatible = "renesas,i2c-r8a774c0",
524 "renesas, 519 "renesas,rcar-gen3-i2c";
525 reg = <0 0xe66d8000 0 520 reg = <0 0xe66d8000 0 0x40>;
526 interrupts = <GIC_SPI 521 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
527 clocks = <&cpg CPG_MOD 522 clocks = <&cpg CPG_MOD 927>;
528 power-domains = <&sysc 523 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
529 resets = <&cpg 927>; 524 resets = <&cpg 927>;
530 dmas = <&dmac0 0x99>, 525 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
531 dma-names = "tx", "rx" 526 dma-names = "tx", "rx";
532 i2c-scl-internal-delay 527 i2c-scl-internal-delay-ns = <6>;
533 status = "disabled"; 528 status = "disabled";
534 }; 529 };
535 530
536 i2c5: i2c@e66e0000 { 531 i2c5: i2c@e66e0000 {
537 #address-cells = <1>; 532 #address-cells = <1>;
538 #size-cells = <0>; 533 #size-cells = <0>;
539 compatible = "renesas, 534 compatible = "renesas,i2c-r8a774c0",
540 "renesas, 535 "renesas,rcar-gen3-i2c";
541 reg = <0 0xe66e0000 0 536 reg = <0 0xe66e0000 0 0x40>;
542 interrupts = <GIC_SPI 537 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
543 clocks = <&cpg CPG_MOD 538 clocks = <&cpg CPG_MOD 919>;
544 power-domains = <&sysc 539 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
545 resets = <&cpg 919>; 540 resets = <&cpg 919>;
546 dmas = <&dmac0 0x9b>, 541 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
547 dma-names = "tx", "rx" 542 dma-names = "tx", "rx";
548 i2c-scl-internal-delay 543 i2c-scl-internal-delay-ns = <6>;
549 status = "disabled"; 544 status = "disabled";
550 }; 545 };
551 546
552 i2c6: i2c@e66e8000 { 547 i2c6: i2c@e66e8000 {
553 #address-cells = <1>; 548 #address-cells = <1>;
554 #size-cells = <0>; 549 #size-cells = <0>;
555 compatible = "renesas, 550 compatible = "renesas,i2c-r8a774c0",
556 "renesas, 551 "renesas,rcar-gen3-i2c";
557 reg = <0 0xe66e8000 0 552 reg = <0 0xe66e8000 0 0x40>;
558 interrupts = <GIC_SPI 553 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
559 clocks = <&cpg CPG_MOD 554 clocks = <&cpg CPG_MOD 918>;
560 power-domains = <&sysc 555 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
561 resets = <&cpg 918>; 556 resets = <&cpg 918>;
562 dmas = <&dmac0 0x9d>, 557 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
563 dma-names = "tx", "rx" 558 dma-names = "tx", "rx";
564 i2c-scl-internal-delay 559 i2c-scl-internal-delay-ns = <6>;
565 status = "disabled"; 560 status = "disabled";
566 }; 561 };
567 562
568 i2c7: i2c@e6690000 { 563 i2c7: i2c@e6690000 {
569 #address-cells = <1>; 564 #address-cells = <1>;
570 #size-cells = <0>; 565 #size-cells = <0>;
571 compatible = "renesas, 566 compatible = "renesas,i2c-r8a774c0",
572 "renesas, 567 "renesas,rcar-gen3-i2c";
573 reg = <0 0xe6690000 0 568 reg = <0 0xe6690000 0 0x40>;
574 interrupts = <GIC_SPI 569 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
575 clocks = <&cpg CPG_MOD 570 clocks = <&cpg CPG_MOD 1003>;
576 power-domains = <&sysc 571 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
577 resets = <&cpg 1003>; 572 resets = <&cpg 1003>;
578 i2c-scl-internal-delay 573 i2c-scl-internal-delay-ns = <6>;
579 status = "disabled"; 574 status = "disabled";
580 }; 575 };
581 576
582 iic_pmic: i2c@e60b0000 { !! 577 i2c_dvfs: i2c@e60b0000 {
583 #address-cells = <1>; 578 #address-cells = <1>;
584 #size-cells = <0>; 579 #size-cells = <0>;
585 compatible = "renesas, !! 580 compatible = "renesas,iic-r8a774c0";
586 "renesas, !! 581 reg = <0 0xe60b0000 0 0x15>;
587 "renesas, <<
588 reg = <0 0xe60b0000 0 <<
589 interrupts = <GIC_SPI 582 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
590 clocks = <&cpg CPG_MOD 583 clocks = <&cpg CPG_MOD 926>;
591 power-domains = <&sysc 584 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
592 resets = <&cpg 926>; 585 resets = <&cpg 926>;
593 dmas = <&dmac0 0x11>, 586 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
594 dma-names = "tx", "rx" 587 dma-names = "tx", "rx";
595 status = "disabled"; 588 status = "disabled";
596 }; 589 };
597 590
598 hscif0: serial@e6540000 { 591 hscif0: serial@e6540000 {
599 compatible = "renesas, 592 compatible = "renesas,hscif-r8a774c0",
600 "renesas, 593 "renesas,rcar-gen3-hscif",
601 "renesas, 594 "renesas,hscif";
602 reg = <0 0xe6540000 0 595 reg = <0 0xe6540000 0 0x60>;
603 interrupts = <GIC_SPI 596 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
604 clocks = <&cpg CPG_MOD 597 clocks = <&cpg CPG_MOD 520>,
605 <&cpg CPG_COR 598 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
606 <&scif_clk>; 599 <&scif_clk>;
607 clock-names = "fck", " 600 clock-names = "fck", "brg_int", "scif_clk";
608 dmas = <&dmac1 0x31>, 601 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
609 <&dmac2 0x31>, 602 <&dmac2 0x31>, <&dmac2 0x30>;
610 dma-names = "tx", "rx" 603 dma-names = "tx", "rx", "tx", "rx";
611 power-domains = <&sysc 604 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
612 resets = <&cpg 520>; 605 resets = <&cpg 520>;
613 status = "disabled"; 606 status = "disabled";
614 }; 607 };
615 608
616 hscif1: serial@e6550000 { 609 hscif1: serial@e6550000 {
617 compatible = "renesas, 610 compatible = "renesas,hscif-r8a774c0",
618 "renesas, 611 "renesas,rcar-gen3-hscif",
619 "renesas, 612 "renesas,hscif";
620 reg = <0 0xe6550000 0 613 reg = <0 0xe6550000 0 0x60>;
621 interrupts = <GIC_SPI 614 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
622 clocks = <&cpg CPG_MOD 615 clocks = <&cpg CPG_MOD 519>,
623 <&cpg CPG_COR 616 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
624 <&scif_clk>; 617 <&scif_clk>;
625 clock-names = "fck", " 618 clock-names = "fck", "brg_int", "scif_clk";
626 dmas = <&dmac1 0x33>, 619 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
627 <&dmac2 0x33>, 620 <&dmac2 0x33>, <&dmac2 0x32>;
628 dma-names = "tx", "rx" 621 dma-names = "tx", "rx", "tx", "rx";
629 power-domains = <&sysc 622 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
630 resets = <&cpg 519>; 623 resets = <&cpg 519>;
631 status = "disabled"; 624 status = "disabled";
632 }; 625 };
633 626
634 hscif2: serial@e6560000 { 627 hscif2: serial@e6560000 {
635 compatible = "renesas, 628 compatible = "renesas,hscif-r8a774c0",
636 "renesas, 629 "renesas,rcar-gen3-hscif",
637 "renesas, 630 "renesas,hscif";
638 reg = <0 0xe6560000 0 631 reg = <0 0xe6560000 0 0x60>;
639 interrupts = <GIC_SPI 632 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
640 clocks = <&cpg CPG_MOD 633 clocks = <&cpg CPG_MOD 518>,
641 <&cpg CPG_COR 634 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
642 <&scif_clk>; 635 <&scif_clk>;
643 clock-names = "fck", " 636 clock-names = "fck", "brg_int", "scif_clk";
644 dmas = <&dmac1 0x35>, 637 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
645 <&dmac2 0x35>, 638 <&dmac2 0x35>, <&dmac2 0x34>;
646 dma-names = "tx", "rx" 639 dma-names = "tx", "rx", "tx", "rx";
647 power-domains = <&sysc 640 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
648 resets = <&cpg 518>; 641 resets = <&cpg 518>;
649 status = "disabled"; 642 status = "disabled";
650 }; 643 };
651 644
652 hscif3: serial@e66a0000 { 645 hscif3: serial@e66a0000 {
653 compatible = "renesas, 646 compatible = "renesas,hscif-r8a774c0",
654 "renesas, 647 "renesas,rcar-gen3-hscif",
655 "renesas, 648 "renesas,hscif";
656 reg = <0 0xe66a0000 0 649 reg = <0 0xe66a0000 0 0x60>;
657 interrupts = <GIC_SPI 650 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
658 clocks = <&cpg CPG_MOD 651 clocks = <&cpg CPG_MOD 517>,
659 <&cpg CPG_COR 652 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
660 <&scif_clk>; 653 <&scif_clk>;
661 clock-names = "fck", " 654 clock-names = "fck", "brg_int", "scif_clk";
662 dmas = <&dmac0 0x37>, 655 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
663 dma-names = "tx", "rx" 656 dma-names = "tx", "rx";
664 power-domains = <&sysc 657 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
665 resets = <&cpg 517>; 658 resets = <&cpg 517>;
666 status = "disabled"; 659 status = "disabled";
667 }; 660 };
668 661
669 hscif4: serial@e66b0000 { 662 hscif4: serial@e66b0000 {
670 compatible = "renesas, 663 compatible = "renesas,hscif-r8a774c0",
671 "renesas, 664 "renesas,rcar-gen3-hscif",
672 "renesas, 665 "renesas,hscif";
673 reg = <0 0xe66b0000 0 666 reg = <0 0xe66b0000 0 0x60>;
674 interrupts = <GIC_SPI 667 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
675 clocks = <&cpg CPG_MOD 668 clocks = <&cpg CPG_MOD 516>,
676 <&cpg CPG_COR 669 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
677 <&scif_clk>; 670 <&scif_clk>;
678 clock-names = "fck", " 671 clock-names = "fck", "brg_int", "scif_clk";
679 dmas = <&dmac0 0x39>, 672 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
680 dma-names = "tx", "rx" 673 dma-names = "tx", "rx";
681 power-domains = <&sysc 674 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
682 resets = <&cpg 516>; 675 resets = <&cpg 516>;
683 status = "disabled"; 676 status = "disabled";
684 }; 677 };
685 678
686 hsusb: usb@e6590000 { 679 hsusb: usb@e6590000 {
687 compatible = "renesas, 680 compatible = "renesas,usbhs-r8a774c0",
688 "renesas, 681 "renesas,rcar-gen3-usbhs";
689 reg = <0 0xe6590000 0 682 reg = <0 0xe6590000 0 0x200>;
690 interrupts = <GIC_SPI 683 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
691 clocks = <&cpg CPG_MOD 684 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
692 dmas = <&usb_dmac0 0>, 685 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
693 <&usb_dmac1 0>, 686 <&usb_dmac1 0>, <&usb_dmac1 1>;
694 dma-names = "ch0", "ch 687 dma-names = "ch0", "ch1", "ch2", "ch3";
695 renesas,buswait = <11> 688 renesas,buswait = <11>;
696 phys = <&usb2_phy0 3>; 689 phys = <&usb2_phy0 3>;
697 phy-names = "usb"; 690 phy-names = "usb";
698 power-domains = <&sysc 691 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
699 resets = <&cpg 704>, < 692 resets = <&cpg 704>, <&cpg 703>;
700 status = "disabled"; 693 status = "disabled";
701 }; 694 };
702 695
703 usb_dmac0: dma-controller@e65a 696 usb_dmac0: dma-controller@e65a0000 {
704 compatible = "renesas, 697 compatible = "renesas,r8a774c0-usb-dmac",
705 "renesas, 698 "renesas,usb-dmac";
706 reg = <0 0xe65a0000 0 699 reg = <0 0xe65a0000 0 0x100>;
707 interrupts = <GIC_SPI 700 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
708 <GIC_SPI 701 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
709 interrupt-names = "ch0 702 interrupt-names = "ch0", "ch1";
710 clocks = <&cpg CPG_MOD 703 clocks = <&cpg CPG_MOD 330>;
711 power-domains = <&sysc 704 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
712 resets = <&cpg 330>; 705 resets = <&cpg 330>;
713 #dma-cells = <1>; 706 #dma-cells = <1>;
714 dma-channels = <2>; 707 dma-channels = <2>;
715 }; 708 };
716 709
717 usb_dmac1: dma-controller@e65b 710 usb_dmac1: dma-controller@e65b0000 {
718 compatible = "renesas, 711 compatible = "renesas,r8a774c0-usb-dmac",
719 "renesas, 712 "renesas,usb-dmac";
720 reg = <0 0xe65b0000 0 713 reg = <0 0xe65b0000 0 0x100>;
721 interrupts = <GIC_SPI 714 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
722 <GIC_SPI 715 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
723 interrupt-names = "ch0 716 interrupt-names = "ch0", "ch1";
724 clocks = <&cpg CPG_MOD 717 clocks = <&cpg CPG_MOD 331>;
725 power-domains = <&sysc 718 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
726 resets = <&cpg 331>; 719 resets = <&cpg 331>;
727 #dma-cells = <1>; 720 #dma-cells = <1>;
728 dma-channels = <2>; 721 dma-channels = <2>;
729 }; 722 };
730 723
731 dmac0: dma-controller@e6700000 724 dmac0: dma-controller@e6700000 {
732 compatible = "renesas, 725 compatible = "renesas,dmac-r8a774c0",
733 "renesas, 726 "renesas,rcar-dmac";
734 reg = <0 0xe6700000 0 727 reg = <0 0xe6700000 0 0x10000>;
735 interrupts = <GIC_SPI 728 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
736 <GIC_SPI 729 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
737 <GIC_SPI 730 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
738 <GIC_SPI 731 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
739 <GIC_SPI 732 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
740 <GIC_SPI 733 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
741 <GIC_SPI 734 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
742 <GIC_SPI 735 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
743 <GIC_SPI 736 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
744 <GIC_SPI 737 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
745 <GIC_SPI 738 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
746 <GIC_SPI 739 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
747 <GIC_SPI 740 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
748 <GIC_SPI 741 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
749 <GIC_SPI 742 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
750 <GIC_SPI 743 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
751 <GIC_SPI 744 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
752 interrupt-names = "err 745 interrupt-names = "error",
753 "ch0", 746 "ch0", "ch1", "ch2", "ch3",
754 "ch4", 747 "ch4", "ch5", "ch6", "ch7",
755 "ch8", 748 "ch8", "ch9", "ch10", "ch11",
756 "ch12" 749 "ch12", "ch13", "ch14", "ch15";
757 clocks = <&cpg CPG_MOD 750 clocks = <&cpg CPG_MOD 219>;
758 clock-names = "fck"; 751 clock-names = "fck";
759 power-domains = <&sysc 752 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
760 resets = <&cpg 219>; 753 resets = <&cpg 219>;
761 #dma-cells = <1>; 754 #dma-cells = <1>;
762 dma-channels = <16>; 755 dma-channels = <16>;
763 iommus = <&ipmmu_ds0 0 756 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
764 <&ipmmu_ds0 2>, 757 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
765 <&ipmmu_ds0 4>, 758 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
766 <&ipmmu_ds0 6>, 759 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
767 <&ipmmu_ds0 8>, 760 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
768 <&ipmmu_ds0 10> 761 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
769 <&ipmmu_ds0 12> 762 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
770 <&ipmmu_ds0 14> 763 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
771 }; 764 };
772 765
773 dmac1: dma-controller@e7300000 766 dmac1: dma-controller@e7300000 {
774 compatible = "renesas, 767 compatible = "renesas,dmac-r8a774c0",
775 "renesas, 768 "renesas,rcar-dmac";
776 reg = <0 0xe7300000 0 769 reg = <0 0xe7300000 0 0x10000>;
777 interrupts = <GIC_SPI 770 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
778 <GIC_SPI 771 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
779 <GIC_SPI 772 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
780 <GIC_SPI 773 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
781 <GIC_SPI 774 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
782 <GIC_SPI 775 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
783 <GIC_SPI 776 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
784 <GIC_SPI 777 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
785 <GIC_SPI 778 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
786 <GIC_SPI 779 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
787 <GIC_SPI 780 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
788 <GIC_SPI 781 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
789 <GIC_SPI 782 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
790 <GIC_SPI 783 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
791 <GIC_SPI 784 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
792 <GIC_SPI 785 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
793 <GIC_SPI 786 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
794 interrupt-names = "err 787 interrupt-names = "error",
795 "ch0", 788 "ch0", "ch1", "ch2", "ch3",
796 "ch4", 789 "ch4", "ch5", "ch6", "ch7",
797 "ch8", 790 "ch8", "ch9", "ch10", "ch11",
798 "ch12" 791 "ch12", "ch13", "ch14", "ch15";
799 clocks = <&cpg CPG_MOD 792 clocks = <&cpg CPG_MOD 218>;
800 clock-names = "fck"; 793 clock-names = "fck";
801 power-domains = <&sysc 794 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
802 resets = <&cpg 218>; 795 resets = <&cpg 218>;
803 #dma-cells = <1>; 796 #dma-cells = <1>;
804 dma-channels = <16>; 797 dma-channels = <16>;
805 iommus = <&ipmmu_ds1 0 798 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
806 <&ipmmu_ds1 2>, 799 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
807 <&ipmmu_ds1 4>, 800 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
808 <&ipmmu_ds1 6>, 801 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
809 <&ipmmu_ds1 8>, 802 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
810 <&ipmmu_ds1 10> 803 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
811 <&ipmmu_ds1 12> 804 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
812 <&ipmmu_ds1 14> 805 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
813 }; 806 };
814 807
815 dmac2: dma-controller@e7310000 808 dmac2: dma-controller@e7310000 {
816 compatible = "renesas, 809 compatible = "renesas,dmac-r8a774c0",
817 "renesas, 810 "renesas,rcar-dmac";
818 reg = <0 0xe7310000 0 811 reg = <0 0xe7310000 0 0x10000>;
819 interrupts = <GIC_SPI 812 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
820 <GIC_SPI 813 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
821 <GIC_SPI 814 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
822 <GIC_SPI 815 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
823 <GIC_SPI 816 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
824 <GIC_SPI 817 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
825 <GIC_SPI 818 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
826 <GIC_SPI 819 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
827 <GIC_SPI 820 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
828 <GIC_SPI 821 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
829 <GIC_SPI 822 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
830 <GIC_SPI 823 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
831 <GIC_SPI 824 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
832 <GIC_SPI 825 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
833 <GIC_SPI 826 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
834 <GIC_SPI 827 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
835 <GIC_SPI 828 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
836 interrupt-names = "err 829 interrupt-names = "error",
837 "ch0", 830 "ch0", "ch1", "ch2", "ch3",
838 "ch4", 831 "ch4", "ch5", "ch6", "ch7",
839 "ch8", 832 "ch8", "ch9", "ch10", "ch11",
840 "ch12" 833 "ch12", "ch13", "ch14", "ch15";
841 clocks = <&cpg CPG_MOD 834 clocks = <&cpg CPG_MOD 217>;
842 clock-names = "fck"; 835 clock-names = "fck";
843 power-domains = <&sysc 836 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
844 resets = <&cpg 217>; 837 resets = <&cpg 217>;
845 #dma-cells = <1>; 838 #dma-cells = <1>;
846 dma-channels = <16>; 839 dma-channels = <16>;
847 iommus = <&ipmmu_ds1 1 840 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
848 <&ipmmu_ds1 18> 841 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
849 <&ipmmu_ds1 20> 842 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
850 <&ipmmu_ds1 22> 843 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
851 <&ipmmu_ds1 24> 844 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
852 <&ipmmu_ds1 26> 845 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
853 <&ipmmu_ds1 28> 846 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
854 <&ipmmu_ds1 30> 847 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
855 }; 848 };
856 849
857 ipmmu_ds0: iommu@e6740000 { 850 ipmmu_ds0: iommu@e6740000 {
858 compatible = "renesas, 851 compatible = "renesas,ipmmu-r8a774c0";
859 reg = <0 0xe6740000 0 852 reg = <0 0xe6740000 0 0x1000>;
860 renesas,ipmmu-main = < 853 renesas,ipmmu-main = <&ipmmu_mm 0>;
861 power-domains = <&sysc 854 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
862 #iommu-cells = <1>; 855 #iommu-cells = <1>;
863 }; 856 };
864 857
865 ipmmu_ds1: iommu@e7740000 { 858 ipmmu_ds1: iommu@e7740000 {
866 compatible = "renesas, 859 compatible = "renesas,ipmmu-r8a774c0";
867 reg = <0 0xe7740000 0 860 reg = <0 0xe7740000 0 0x1000>;
868 renesas,ipmmu-main = < 861 renesas,ipmmu-main = <&ipmmu_mm 1>;
869 power-domains = <&sysc 862 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
870 #iommu-cells = <1>; 863 #iommu-cells = <1>;
871 }; 864 };
872 865
873 ipmmu_hc: iommu@e6570000 { 866 ipmmu_hc: iommu@e6570000 {
874 compatible = "renesas, 867 compatible = "renesas,ipmmu-r8a774c0";
875 reg = <0 0xe6570000 0 868 reg = <0 0xe6570000 0 0x1000>;
876 renesas,ipmmu-main = < 869 renesas,ipmmu-main = <&ipmmu_mm 2>;
877 power-domains = <&sysc 870 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
878 #iommu-cells = <1>; 871 #iommu-cells = <1>;
879 }; 872 };
880 873
881 ipmmu_mm: iommu@e67b0000 { 874 ipmmu_mm: iommu@e67b0000 {
882 compatible = "renesas, 875 compatible = "renesas,ipmmu-r8a774c0";
883 reg = <0 0xe67b0000 0 876 reg = <0 0xe67b0000 0 0x1000>;
884 interrupts = <GIC_SPI 877 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
885 <GIC_SPI 878 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
886 power-domains = <&sysc 879 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
887 #iommu-cells = <1>; 880 #iommu-cells = <1>;
888 }; 881 };
889 882
890 ipmmu_mp: iommu@ec670000 { 883 ipmmu_mp: iommu@ec670000 {
891 compatible = "renesas, 884 compatible = "renesas,ipmmu-r8a774c0";
892 reg = <0 0xec670000 0 885 reg = <0 0xec670000 0 0x1000>;
893 renesas,ipmmu-main = < 886 renesas,ipmmu-main = <&ipmmu_mm 4>;
894 power-domains = <&sysc 887 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
895 #iommu-cells = <1>; 888 #iommu-cells = <1>;
896 }; 889 };
897 890
898 ipmmu_pv0: iommu@fd800000 { 891 ipmmu_pv0: iommu@fd800000 {
899 compatible = "renesas, 892 compatible = "renesas,ipmmu-r8a774c0";
900 reg = <0 0xfd800000 0 893 reg = <0 0xfd800000 0 0x1000>;
901 renesas,ipmmu-main = < 894 renesas,ipmmu-main = <&ipmmu_mm 6>;
902 power-domains = <&sysc 895 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
903 #iommu-cells = <1>; 896 #iommu-cells = <1>;
904 }; 897 };
905 898
906 ipmmu_vc0: iommu@fe6b0000 { 899 ipmmu_vc0: iommu@fe6b0000 {
907 compatible = "renesas, 900 compatible = "renesas,ipmmu-r8a774c0";
908 reg = <0 0xfe6b0000 0 901 reg = <0 0xfe6b0000 0 0x1000>;
909 renesas,ipmmu-main = < 902 renesas,ipmmu-main = <&ipmmu_mm 12>;
910 power-domains = <&sysc 903 power-domains = <&sysc R8A774C0_PD_A3VC>;
911 #iommu-cells = <1>; 904 #iommu-cells = <1>;
912 }; 905 };
913 906
914 ipmmu_vi0: iommu@febd0000 { 907 ipmmu_vi0: iommu@febd0000 {
915 compatible = "renesas, 908 compatible = "renesas,ipmmu-r8a774c0";
916 reg = <0 0xfebd0000 0 909 reg = <0 0xfebd0000 0 0x1000>;
917 renesas,ipmmu-main = < 910 renesas,ipmmu-main = <&ipmmu_mm 14>;
918 power-domains = <&sysc 911 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
919 #iommu-cells = <1>; 912 #iommu-cells = <1>;
920 }; 913 };
921 914
922 ipmmu_vp0: iommu@fe990000 { 915 ipmmu_vp0: iommu@fe990000 {
923 compatible = "renesas, 916 compatible = "renesas,ipmmu-r8a774c0";
924 reg = <0 0xfe990000 0 917 reg = <0 0xfe990000 0 0x1000>;
925 renesas,ipmmu-main = < 918 renesas,ipmmu-main = <&ipmmu_mm 16>;
926 power-domains = <&sysc 919 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
927 #iommu-cells = <1>; 920 #iommu-cells = <1>;
928 }; 921 };
929 922
930 avb: ethernet@e6800000 { 923 avb: ethernet@e6800000 {
931 compatible = "renesas, 924 compatible = "renesas,etheravb-r8a774c0",
932 "renesas, 925 "renesas,etheravb-rcar-gen3";
933 reg = <0 0xe6800000 0 926 reg = <0 0xe6800000 0 0x800>;
934 interrupts = <GIC_SPI 927 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
935 <GIC_SPI 928 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
936 <GIC_SPI 929 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
937 <GIC_SPI 930 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
938 <GIC_SPI 931 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
939 <GIC_SPI 932 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
940 <GIC_SPI 933 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
941 <GIC_SPI 934 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
942 <GIC_SPI 935 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
943 <GIC_SPI 936 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
944 <GIC_SPI 937 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
945 <GIC_SPI 938 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
946 <GIC_SPI 939 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
947 <GIC_SPI 940 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
948 <GIC_SPI 941 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
949 <GIC_SPI 942 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
950 <GIC_SPI 943 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
951 <GIC_SPI 944 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
952 <GIC_SPI 945 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
953 <GIC_SPI 946 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
954 <GIC_SPI 947 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
955 <GIC_SPI 948 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
956 <GIC_SPI 949 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
957 <GIC_SPI 950 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
958 <GIC_SPI 951 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
959 interrupt-names = "ch0 952 interrupt-names = "ch0", "ch1", "ch2", "ch3",
960 "ch4 953 "ch4", "ch5", "ch6", "ch7",
961 "ch8 954 "ch8", "ch9", "ch10", "ch11",
962 "ch1 955 "ch12", "ch13", "ch14", "ch15",
963 "ch1 956 "ch16", "ch17", "ch18", "ch19",
964 "ch2 957 "ch20", "ch21", "ch22", "ch23",
965 "ch2 958 "ch24";
966 clocks = <&cpg CPG_MOD 959 clocks = <&cpg CPG_MOD 812>;
967 clock-names = "fck"; <<
968 power-domains = <&sysc 960 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
969 resets = <&cpg 812>; 961 resets = <&cpg 812>;
970 phy-mode = "rgmii"; 962 phy-mode = "rgmii";
971 rx-internal-delay-ps = <<
972 iommus = <&ipmmu_ds0 1 963 iommus = <&ipmmu_ds0 16>;
973 #address-cells = <1>; 964 #address-cells = <1>;
974 #size-cells = <0>; 965 #size-cells = <0>;
975 status = "disabled"; 966 status = "disabled";
976 }; 967 };
977 968
978 can0: can@e6c30000 { 969 can0: can@e6c30000 {
979 compatible = "renesas, 970 compatible = "renesas,can-r8a774c0",
980 "renesas, 971 "renesas,rcar-gen3-can";
981 reg = <0 0xe6c30000 0 972 reg = <0 0xe6c30000 0 0x1000>;
982 interrupts = <GIC_SPI 973 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
983 clocks = <&cpg CPG_MOD 974 clocks = <&cpg CPG_MOD 916>,
984 <&cpg CPG_COR 975 <&cpg CPG_CORE R8A774C0_CLK_CANFD>,
985 <&can_clk>; 976 <&can_clk>;
986 clock-names = "clkp1", 977 clock-names = "clkp1", "clkp2", "can_clk";
987 assigned-clocks = <&cp 978 assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>;
988 assigned-clock-rates = 979 assigned-clock-rates = <40000000>;
989 power-domains = <&sysc 980 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
990 resets = <&cpg 916>; 981 resets = <&cpg 916>;
991 status = "disabled"; 982 status = "disabled";
992 }; 983 };
993 984
994 can1: can@e6c38000 { 985 can1: can@e6c38000 {
995 compatible = "renesas, 986 compatible = "renesas,can-r8a774c0",
996 "renesas, 987 "renesas,rcar-gen3-can";
997 reg = <0 0xe6c38000 0 988 reg = <0 0xe6c38000 0 0x1000>;
998 interrupts = <GIC_SPI 989 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
999 clocks = <&cpg CPG_MOD 990 clocks = <&cpg CPG_MOD 915>,
1000 <&cpg CPG_CO 991 <&cpg CPG_CORE R8A774C0_CLK_CANFD>,
1001 <&can_clk>; 992 <&can_clk>;
1002 clock-names = "clkp1" 993 clock-names = "clkp1", "clkp2", "can_clk";
1003 assigned-clocks = <&c 994 assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>;
1004 assigned-clock-rates 995 assigned-clock-rates = <40000000>;
1005 power-domains = <&sys 996 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1006 resets = <&cpg 915>; 997 resets = <&cpg 915>;
1007 status = "disabled"; 998 status = "disabled";
1008 }; 999 };
1009 1000
1010 canfd: can@e66c0000 { 1001 canfd: can@e66c0000 {
1011 compatible = "renesas 1002 compatible = "renesas,r8a774c0-canfd",
1012 "renesas 1003 "renesas,rcar-gen3-canfd";
1013 reg = <0 0xe66c0000 0 1004 reg = <0 0xe66c0000 0 0x8000>;
1014 interrupts = <GIC_SPI 1005 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
1015 <GIC_SPI 1006 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1016 interrupt-names = "ch <<
1017 clocks = <&cpg CPG_MO 1007 clocks = <&cpg CPG_MOD 914>,
1018 <&cpg CPG_CO 1008 <&cpg CPG_CORE R8A774C0_CLK_CANFD>,
1019 <&can_clk>; 1009 <&can_clk>;
1020 clock-names = "fck", 1010 clock-names = "fck", "canfd", "can_clk";
1021 assigned-clocks = <&c 1011 assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>;
1022 assigned-clock-rates 1012 assigned-clock-rates = <40000000>;
1023 power-domains = <&sys 1013 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1024 resets = <&cpg 914>; 1014 resets = <&cpg 914>;
1025 status = "disabled"; 1015 status = "disabled";
1026 1016
1027 channel0 { 1017 channel0 {
1028 status = "dis 1018 status = "disabled";
1029 }; 1019 };
1030 1020
1031 channel1 { 1021 channel1 {
1032 status = "dis 1022 status = "disabled";
1033 }; 1023 };
1034 }; 1024 };
1035 1025
1036 pwm0: pwm@e6e30000 { 1026 pwm0: pwm@e6e30000 {
1037 compatible = "renesas 1027 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1038 reg = <0 0xe6e30000 0 1028 reg = <0 0xe6e30000 0 0x8>;
1039 clocks = <&cpg CPG_MO 1029 clocks = <&cpg CPG_MOD 523>;
1040 power-domains = <&sys 1030 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1041 resets = <&cpg 523>; 1031 resets = <&cpg 523>;
1042 #pwm-cells = <2>; 1032 #pwm-cells = <2>;
1043 status = "disabled"; 1033 status = "disabled";
1044 }; 1034 };
1045 1035
1046 pwm1: pwm@e6e31000 { 1036 pwm1: pwm@e6e31000 {
1047 compatible = "renesas 1037 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1048 reg = <0 0xe6e31000 0 1038 reg = <0 0xe6e31000 0 0x8>;
1049 clocks = <&cpg CPG_MO 1039 clocks = <&cpg CPG_MOD 523>;
1050 power-domains = <&sys 1040 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1051 resets = <&cpg 523>; 1041 resets = <&cpg 523>;
1052 #pwm-cells = <2>; 1042 #pwm-cells = <2>;
1053 status = "disabled"; 1043 status = "disabled";
1054 }; 1044 };
1055 1045
1056 pwm2: pwm@e6e32000 { 1046 pwm2: pwm@e6e32000 {
1057 compatible = "renesas 1047 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1058 reg = <0 0xe6e32000 0 1048 reg = <0 0xe6e32000 0 0x8>;
1059 clocks = <&cpg CPG_MO 1049 clocks = <&cpg CPG_MOD 523>;
1060 power-domains = <&sys 1050 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1061 resets = <&cpg 523>; 1051 resets = <&cpg 523>;
1062 #pwm-cells = <2>; 1052 #pwm-cells = <2>;
1063 status = "disabled"; 1053 status = "disabled";
1064 }; 1054 };
1065 1055
1066 pwm3: pwm@e6e33000 { 1056 pwm3: pwm@e6e33000 {
1067 compatible = "renesas 1057 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1068 reg = <0 0xe6e33000 0 1058 reg = <0 0xe6e33000 0 0x8>;
1069 clocks = <&cpg CPG_MO 1059 clocks = <&cpg CPG_MOD 523>;
1070 power-domains = <&sys 1060 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1071 resets = <&cpg 523>; 1061 resets = <&cpg 523>;
1072 #pwm-cells = <2>; 1062 #pwm-cells = <2>;
1073 status = "disabled"; 1063 status = "disabled";
1074 }; 1064 };
1075 1065
1076 pwm4: pwm@e6e34000 { 1066 pwm4: pwm@e6e34000 {
1077 compatible = "renesas 1067 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1078 reg = <0 0xe6e34000 0 1068 reg = <0 0xe6e34000 0 0x8>;
1079 clocks = <&cpg CPG_MO 1069 clocks = <&cpg CPG_MOD 523>;
1080 power-domains = <&sys 1070 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1081 resets = <&cpg 523>; 1071 resets = <&cpg 523>;
1082 #pwm-cells = <2>; 1072 #pwm-cells = <2>;
1083 status = "disabled"; 1073 status = "disabled";
1084 }; 1074 };
1085 1075
1086 pwm5: pwm@e6e35000 { 1076 pwm5: pwm@e6e35000 {
1087 compatible = "renesas 1077 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1088 reg = <0 0xe6e35000 0 1078 reg = <0 0xe6e35000 0 0x8>;
1089 clocks = <&cpg CPG_MO 1079 clocks = <&cpg CPG_MOD 523>;
1090 power-domains = <&sys 1080 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1091 resets = <&cpg 523>; 1081 resets = <&cpg 523>;
1092 #pwm-cells = <2>; 1082 #pwm-cells = <2>;
1093 status = "disabled"; 1083 status = "disabled";
1094 }; 1084 };
1095 1085
1096 pwm6: pwm@e6e36000 { 1086 pwm6: pwm@e6e36000 {
1097 compatible = "renesas 1087 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1098 reg = <0 0xe6e36000 0 1088 reg = <0 0xe6e36000 0 0x8>;
1099 clocks = <&cpg CPG_MO 1089 clocks = <&cpg CPG_MOD 523>;
1100 power-domains = <&sys 1090 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1101 resets = <&cpg 523>; 1091 resets = <&cpg 523>;
1102 #pwm-cells = <2>; 1092 #pwm-cells = <2>;
1103 status = "disabled"; 1093 status = "disabled";
1104 }; 1094 };
1105 1095
1106 scif0: serial@e6e60000 { 1096 scif0: serial@e6e60000 {
1107 compatible = "renesas 1097 compatible = "renesas,scif-r8a774c0",
1108 "renesas 1098 "renesas,rcar-gen3-scif", "renesas,scif";
1109 reg = <0 0xe6e60000 0 1099 reg = <0 0xe6e60000 0 64>;
1110 interrupts = <GIC_SPI 1100 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
1111 clocks = <&cpg CPG_MO 1101 clocks = <&cpg CPG_MOD 207>,
1112 <&cpg CPG_CO 1102 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
1113 <&scif_clk>; 1103 <&scif_clk>;
1114 clock-names = "fck", 1104 clock-names = "fck", "brg_int", "scif_clk";
1115 dmas = <&dmac1 0x51>, 1105 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1116 <&dmac2 0x51>, 1106 <&dmac2 0x51>, <&dmac2 0x50>;
1117 dma-names = "tx", "rx 1107 dma-names = "tx", "rx", "tx", "rx";
1118 power-domains = <&sys 1108 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1119 resets = <&cpg 207>; 1109 resets = <&cpg 207>;
1120 status = "disabled"; 1110 status = "disabled";
1121 }; 1111 };
1122 1112
1123 scif1: serial@e6e68000 { 1113 scif1: serial@e6e68000 {
1124 compatible = "renesas 1114 compatible = "renesas,scif-r8a774c0",
1125 "renesas 1115 "renesas,rcar-gen3-scif", "renesas,scif";
1126 reg = <0 0xe6e68000 0 1116 reg = <0 0xe6e68000 0 64>;
1127 interrupts = <GIC_SPI 1117 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
1128 clocks = <&cpg CPG_MO 1118 clocks = <&cpg CPG_MOD 206>,
1129 <&cpg CPG_CO 1119 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
1130 <&scif_clk>; 1120 <&scif_clk>;
1131 clock-names = "fck", 1121 clock-names = "fck", "brg_int", "scif_clk";
1132 dmas = <&dmac1 0x53>, 1122 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1133 <&dmac2 0x53>, 1123 <&dmac2 0x53>, <&dmac2 0x52>;
1134 dma-names = "tx", "rx 1124 dma-names = "tx", "rx", "tx", "rx";
1135 power-domains = <&sys 1125 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1136 resets = <&cpg 206>; 1126 resets = <&cpg 206>;
1137 status = "disabled"; 1127 status = "disabled";
1138 }; 1128 };
1139 1129
1140 scif2: serial@e6e88000 { 1130 scif2: serial@e6e88000 {
1141 compatible = "renesas 1131 compatible = "renesas,scif-r8a774c0",
1142 "renesas 1132 "renesas,rcar-gen3-scif", "renesas,scif";
1143 reg = <0 0xe6e88000 0 1133 reg = <0 0xe6e88000 0 64>;
1144 interrupts = <GIC_SPI 1134 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
1145 clocks = <&cpg CPG_MO 1135 clocks = <&cpg CPG_MOD 310>,
1146 <&cpg CPG_CO 1136 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
1147 <&scif_clk>; 1137 <&scif_clk>;
1148 clock-names = "fck", 1138 clock-names = "fck", "brg_int", "scif_clk";
1149 dmas = <&dmac1 0x13>, 1139 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1150 <&dmac2 0x13>, 1140 <&dmac2 0x13>, <&dmac2 0x12>;
1151 dma-names = "tx", "rx 1141 dma-names = "tx", "rx", "tx", "rx";
1152 power-domains = <&sys 1142 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1153 resets = <&cpg 310>; 1143 resets = <&cpg 310>;
1154 status = "disabled"; 1144 status = "disabled";
1155 }; 1145 };
1156 1146
1157 scif3: serial@e6c50000 { 1147 scif3: serial@e6c50000 {
1158 compatible = "renesas 1148 compatible = "renesas,scif-r8a774c0",
1159 "renesas 1149 "renesas,rcar-gen3-scif", "renesas,scif";
1160 reg = <0 0xe6c50000 0 1150 reg = <0 0xe6c50000 0 64>;
1161 interrupts = <GIC_SPI 1151 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1162 clocks = <&cpg CPG_MO 1152 clocks = <&cpg CPG_MOD 204>,
1163 <&cpg CPG_CO 1153 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
1164 <&scif_clk>; 1154 <&scif_clk>;
1165 clock-names = "fck", 1155 clock-names = "fck", "brg_int", "scif_clk";
1166 dmas = <&dmac0 0x57>, 1156 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1167 dma-names = "tx", "rx 1157 dma-names = "tx", "rx";
1168 power-domains = <&sys 1158 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1169 resets = <&cpg 204>; 1159 resets = <&cpg 204>;
1170 status = "disabled"; 1160 status = "disabled";
1171 }; 1161 };
1172 1162
1173 scif4: serial@e6c40000 { 1163 scif4: serial@e6c40000 {
1174 compatible = "renesas 1164 compatible = "renesas,scif-r8a774c0",
1175 "renesas 1165 "renesas,rcar-gen3-scif", "renesas,scif";
1176 reg = <0 0xe6c40000 0 1166 reg = <0 0xe6c40000 0 64>;
1177 interrupts = <GIC_SPI 1167 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1178 clocks = <&cpg CPG_MO 1168 clocks = <&cpg CPG_MOD 203>,
1179 <&cpg CPG_CO 1169 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
1180 <&scif_clk>; 1170 <&scif_clk>;
1181 clock-names = "fck", 1171 clock-names = "fck", "brg_int", "scif_clk";
1182 dmas = <&dmac0 0x59>, 1172 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1183 dma-names = "tx", "rx 1173 dma-names = "tx", "rx";
1184 power-domains = <&sys 1174 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1185 resets = <&cpg 203>; 1175 resets = <&cpg 203>;
1186 status = "disabled"; 1176 status = "disabled";
1187 }; 1177 };
1188 1178
1189 scif5: serial@e6f30000 { 1179 scif5: serial@e6f30000 {
1190 compatible = "renesas 1180 compatible = "renesas,scif-r8a774c0",
1191 "renesas 1181 "renesas,rcar-gen3-scif", "renesas,scif";
1192 reg = <0 0xe6f30000 0 1182 reg = <0 0xe6f30000 0 64>;
1193 interrupts = <GIC_SPI 1183 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1194 clocks = <&cpg CPG_MO 1184 clocks = <&cpg CPG_MOD 202>,
1195 <&cpg CPG_CO 1185 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
1196 <&scif_clk>; 1186 <&scif_clk>;
1197 clock-names = "fck", 1187 clock-names = "fck", "brg_int", "scif_clk";
1198 dmas = <&dmac0 0x5b>, 1188 dmas = <&dmac0 0x5b>, <&dmac0 0x5a>;
1199 dma-names = "tx", "rx 1189 dma-names = "tx", "rx";
1200 power-domains = <&sys 1190 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1201 resets = <&cpg 202>; 1191 resets = <&cpg 202>;
1202 status = "disabled"; 1192 status = "disabled";
1203 }; 1193 };
1204 1194
1205 msiof0: spi@e6e90000 { 1195 msiof0: spi@e6e90000 {
1206 compatible = "renesas 1196 compatible = "renesas,msiof-r8a774c0",
1207 "renesas 1197 "renesas,rcar-gen3-msiof";
1208 reg = <0 0xe6e90000 0 1198 reg = <0 0xe6e90000 0 0x0064>;
1209 interrupts = <GIC_SPI 1199 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1210 clocks = <&cpg CPG_MO 1200 clocks = <&cpg CPG_MOD 211>;
1211 dmas = <&dmac1 0x41>, 1201 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1212 <&dmac2 0x41>, 1202 <&dmac2 0x41>, <&dmac2 0x40>;
1213 dma-names = "tx", "rx 1203 dma-names = "tx", "rx", "tx", "rx";
1214 power-domains = <&sys 1204 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1215 resets = <&cpg 211>; 1205 resets = <&cpg 211>;
1216 #address-cells = <1>; 1206 #address-cells = <1>;
1217 #size-cells = <0>; 1207 #size-cells = <0>;
1218 status = "disabled"; 1208 status = "disabled";
1219 }; 1209 };
1220 1210
1221 msiof1: spi@e6ea0000 { 1211 msiof1: spi@e6ea0000 {
1222 compatible = "renesas 1212 compatible = "renesas,msiof-r8a774c0",
1223 "renesas 1213 "renesas,rcar-gen3-msiof";
1224 reg = <0 0xe6ea0000 0 1214 reg = <0 0xe6ea0000 0 0x0064>;
1225 interrupts = <GIC_SPI 1215 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1226 clocks = <&cpg CPG_MO 1216 clocks = <&cpg CPG_MOD 210>;
1227 dmas = <&dmac0 0x43>, 1217 dmas = <&dmac0 0x43>, <&dmac0 0x42>;
1228 dma-names = "tx", "rx 1218 dma-names = "tx", "rx";
1229 power-domains = <&sys 1219 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1230 resets = <&cpg 210>; 1220 resets = <&cpg 210>;
1231 #address-cells = <1>; 1221 #address-cells = <1>;
1232 #size-cells = <0>; 1222 #size-cells = <0>;
1233 status = "disabled"; 1223 status = "disabled";
1234 }; 1224 };
1235 1225
1236 msiof2: spi@e6c00000 { 1226 msiof2: spi@e6c00000 {
1237 compatible = "renesas 1227 compatible = "renesas,msiof-r8a774c0",
1238 "renesas 1228 "renesas,rcar-gen3-msiof";
1239 reg = <0 0xe6c00000 0 1229 reg = <0 0xe6c00000 0 0x0064>;
1240 interrupts = <GIC_SPI 1230 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1241 clocks = <&cpg CPG_MO 1231 clocks = <&cpg CPG_MOD 209>;
1242 dmas = <&dmac0 0x45>, 1232 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1243 dma-names = "tx", "rx 1233 dma-names = "tx", "rx";
1244 power-domains = <&sys 1234 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1245 resets = <&cpg 209>; 1235 resets = <&cpg 209>;
1246 #address-cells = <1>; 1236 #address-cells = <1>;
1247 #size-cells = <0>; 1237 #size-cells = <0>;
1248 status = "disabled"; 1238 status = "disabled";
1249 }; 1239 };
1250 1240
1251 msiof3: spi@e6c10000 { 1241 msiof3: spi@e6c10000 {
1252 compatible = "renesas 1242 compatible = "renesas,msiof-r8a774c0",
1253 "renesas 1243 "renesas,rcar-gen3-msiof";
1254 reg = <0 0xe6c10000 0 1244 reg = <0 0xe6c10000 0 0x0064>;
1255 interrupts = <GIC_SPI 1245 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1256 clocks = <&cpg CPG_MO 1246 clocks = <&cpg CPG_MOD 208>;
1257 dmas = <&dmac0 0x47>, 1247 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1258 dma-names = "tx", "rx 1248 dma-names = "tx", "rx";
1259 power-domains = <&sys 1249 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1260 resets = <&cpg 208>; 1250 resets = <&cpg 208>;
1261 #address-cells = <1>; 1251 #address-cells = <1>;
1262 #size-cells = <0>; 1252 #size-cells = <0>;
1263 status = "disabled"; 1253 status = "disabled";
1264 }; 1254 };
1265 1255
1266 vin4: video@e6ef4000 { 1256 vin4: video@e6ef4000 {
1267 compatible = "renesas 1257 compatible = "renesas,vin-r8a774c0";
1268 reg = <0 0xe6ef4000 0 1258 reg = <0 0xe6ef4000 0 0x1000>;
1269 interrupts = <GIC_SPI 1259 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
1270 clocks = <&cpg CPG_MO 1260 clocks = <&cpg CPG_MOD 807>;
1271 power-domains = <&sys 1261 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1272 resets = <&cpg 807>; 1262 resets = <&cpg 807>;
1273 renesas,id = <4>; 1263 renesas,id = <4>;
1274 status = "disabled"; 1264 status = "disabled";
1275 1265
1276 ports { 1266 ports {
1277 #address-cell 1267 #address-cells = <1>;
1278 #size-cells = 1268 #size-cells = <0>;
1279 1269
1280 port@1 { 1270 port@1 {
1281 #addr 1271 #address-cells = <1>;
1282 #size 1272 #size-cells = <0>;
1283 1273
1284 reg = 1274 reg = <1>;
1285 1275
1286 vin4c 1276 vin4csi40: endpoint@2 {
1287 1277 reg = <2>;
1288 !! 1278 remote-endpoint= <&csi40vin4>;
1289 }; 1279 };
1290 }; 1280 };
1291 }; 1281 };
1292 }; 1282 };
1293 1283
1294 vin5: video@e6ef5000 { 1284 vin5: video@e6ef5000 {
1295 compatible = "renesas 1285 compatible = "renesas,vin-r8a774c0";
1296 reg = <0 0xe6ef5000 0 1286 reg = <0 0xe6ef5000 0 0x1000>;
1297 interrupts = <GIC_SPI 1287 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
1298 clocks = <&cpg CPG_MO 1288 clocks = <&cpg CPG_MOD 806>;
1299 power-domains = <&sys 1289 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1300 resets = <&cpg 806>; 1290 resets = <&cpg 806>;
1301 renesas,id = <5>; 1291 renesas,id = <5>;
1302 status = "disabled"; 1292 status = "disabled";
1303 1293
1304 ports { 1294 ports {
1305 #address-cell 1295 #address-cells = <1>;
1306 #size-cells = 1296 #size-cells = <0>;
1307 1297
1308 port@1 { 1298 port@1 {
1309 #addr 1299 #address-cells = <1>;
1310 #size 1300 #size-cells = <0>;
1311 1301
1312 reg = 1302 reg = <1>;
1313 1303
1314 vin5c 1304 vin5csi40: endpoint@2 {
1315 1305 reg = <2>;
1316 !! 1306 remote-endpoint= <&csi40vin5>;
1317 }; 1307 };
1318 }; 1308 };
1319 }; 1309 };
1320 }; 1310 };
1321 1311
1322 rcar_sound: sound@ec500000 { 1312 rcar_sound: sound@ec500000 {
1323 /* 1313 /*
1324 * #sound-dai-cells i !! 1314 * #sound-dai-cells is required
1325 * 1315 *
1326 * Single DAI : #soun 1316 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1327 * Multi DAI : #soun 1317 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1328 */ 1318 */
1329 /* 1319 /*
1330 * #clock-cells is re 1320 * #clock-cells is required for audio_clkout0/1/2/3
1331 * 1321 *
1332 * clkout : #cl 1322 * clkout : #clock-cells = <0>; <&rcar_sound>;
1333 * clkout0/1/2/3: #cl 1323 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
1334 */ 1324 */
1335 compatible = "renesas 1325 compatible = "renesas,rcar_sound-r8a774c0",
1336 "renesas 1326 "renesas,rcar_sound-gen3";
1337 reg = <0 0xec500000 0 !! 1327 reg = <0 0xec500000 0 0x1000>, /* SCU */
1338 <0 0xec5a0000 0 !! 1328 <0 0xec5a0000 0 0x100>, /* ADG */
1339 <0 0xec540000 0 !! 1329 <0 0xec540000 0 0x1000>, /* SSIU */
1340 <0 0xec541000 0 !! 1330 <0 0xec541000 0 0x280>, /* SSI */
1341 <0 0xec760000 0 !! 1331 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
1342 reg-names = "scu", "a 1332 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1343 1333
1344 clocks = <&cpg CPG_MO 1334 clocks = <&cpg CPG_MOD 1005>,
1345 <&cpg CPG_MO 1335 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
1346 <&cpg CPG_MO 1336 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
1347 <&cpg CPG_MO 1337 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
1348 <&cpg CPG_MO 1338 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
1349 <&cpg CPG_MO 1339 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
1350 <&cpg CPG_MO 1340 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
1351 <&cpg CPG_MO 1341 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
1352 <&cpg CPG_MO 1342 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
1353 <&cpg CPG_MO 1343 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
1354 <&cpg CPG_MO 1344 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
1355 <&cpg CPG_MO 1345 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1356 <&cpg CPG_MO 1346 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1357 <&cpg CPG_MO 1347 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
1358 <&audio_clk_ 1348 <&audio_clk_a>, <&audio_clk_b>,
1359 <&audio_clk_ 1349 <&audio_clk_c>,
1360 <&cpg CPG_MO !! 1350 <&cpg CPG_CORE R8A774C0_CLK_ZA2>;
1361 clock-names = "ssi-al 1351 clock-names = "ssi-all",
1362 "ssi.9" 1352 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1363 "ssi.5" 1353 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1364 "ssi.1" 1354 "ssi.1", "ssi.0",
1365 "src.9" 1355 "src.9", "src.8", "src.7", "src.6",
1366 "src.5" 1356 "src.5", "src.4", "src.3", "src.2",
1367 "src.1" 1357 "src.1", "src.0",
1368 "mix.1" 1358 "mix.1", "mix.0",
1369 "ctu.1" 1359 "ctu.1", "ctu.0",
1370 "dvc.0" 1360 "dvc.0", "dvc.1",
1371 "clk_a" 1361 "clk_a", "clk_b", "clk_c", "clk_i";
1372 power-domains = <&sys 1362 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1373 resets = <&cpg 1005>, 1363 resets = <&cpg 1005>,
1374 <&cpg 1006>, 1364 <&cpg 1006>, <&cpg 1007>,
1375 <&cpg 1008>, 1365 <&cpg 1008>, <&cpg 1009>,
1376 <&cpg 1010>, 1366 <&cpg 1010>, <&cpg 1011>,
1377 <&cpg 1012>, 1367 <&cpg 1012>, <&cpg 1013>,
1378 <&cpg 1014>, 1368 <&cpg 1014>, <&cpg 1015>;
1379 reset-names = "ssi-al 1369 reset-names = "ssi-all",
1380 "ssi.9" 1370 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1381 "ssi.5" 1371 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1382 "ssi.1" 1372 "ssi.1", "ssi.0";
1383 status = "disabled"; 1373 status = "disabled";
1384 1374
1385 rcar_sound,ctu { 1375 rcar_sound,ctu {
1386 ctu00: ctu-0 1376 ctu00: ctu-0 { };
1387 ctu01: ctu-1 1377 ctu01: ctu-1 { };
1388 ctu02: ctu-2 1378 ctu02: ctu-2 { };
1389 ctu03: ctu-3 1379 ctu03: ctu-3 { };
1390 ctu10: ctu-4 1380 ctu10: ctu-4 { };
1391 ctu11: ctu-5 1381 ctu11: ctu-5 { };
1392 ctu12: ctu-6 1382 ctu12: ctu-6 { };
1393 ctu13: ctu-7 1383 ctu13: ctu-7 { };
1394 }; 1384 };
1395 1385
1396 rcar_sound,dvc { 1386 rcar_sound,dvc {
1397 dvc0: dvc-0 { 1387 dvc0: dvc-0 {
1398 dmas 1388 dmas = <&audma0 0xbc>;
1399 dma-n 1389 dma-names = "tx";
1400 }; 1390 };
1401 dvc1: dvc-1 { 1391 dvc1: dvc-1 {
1402 dmas 1392 dmas = <&audma0 0xbe>;
1403 dma-n 1393 dma-names = "tx";
1404 }; 1394 };
1405 }; 1395 };
1406 1396
1407 rcar_sound,mix { 1397 rcar_sound,mix {
1408 mix0: mix-0 { 1398 mix0: mix-0 { };
1409 mix1: mix-1 { 1399 mix1: mix-1 { };
1410 }; 1400 };
1411 1401
1412 rcar_sound,src { 1402 rcar_sound,src {
1413 src0: src-0 { 1403 src0: src-0 {
1414 inter 1404 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1415 dmas 1405 dmas = <&audma0 0x85>, <&audma0 0x9a>;
1416 dma-n 1406 dma-names = "rx", "tx";
1417 }; 1407 };
1418 src1: src-1 { 1408 src1: src-1 {
1419 inter 1409 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1420 dmas 1410 dmas = <&audma0 0x87>, <&audma0 0x9c>;
1421 dma-n 1411 dma-names = "rx", "tx";
1422 }; 1412 };
1423 src2: src-2 { 1413 src2: src-2 {
1424 inter 1414 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1425 dmas 1415 dmas = <&audma0 0x89>, <&audma0 0x9e>;
1426 dma-n 1416 dma-names = "rx", "tx";
1427 }; 1417 };
1428 src3: src-3 { 1418 src3: src-3 {
1429 inter 1419 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1430 dmas 1420 dmas = <&audma0 0x8b>, <&audma0 0xa0>;
1431 dma-n 1421 dma-names = "rx", "tx";
1432 }; 1422 };
1433 src4: src-4 { 1423 src4: src-4 {
1434 inter 1424 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1435 dmas 1425 dmas = <&audma0 0x8d>, <&audma0 0xb0>;
1436 dma-n 1426 dma-names = "rx", "tx";
1437 }; 1427 };
1438 src5: src-5 { 1428 src5: src-5 {
1439 inter 1429 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1440 dmas 1430 dmas = <&audma0 0x8f>, <&audma0 0xb2>;
1441 dma-n 1431 dma-names = "rx", "tx";
1442 }; 1432 };
1443 src6: src-6 { 1433 src6: src-6 {
1444 inter 1434 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1445 dmas 1435 dmas = <&audma0 0x91>, <&audma0 0xb4>;
1446 dma-n 1436 dma-names = "rx", "tx";
1447 }; 1437 };
1448 src7: src-7 { 1438 src7: src-7 {
1449 inter 1439 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1450 dmas 1440 dmas = <&audma0 0x93>, <&audma0 0xb6>;
1451 dma-n 1441 dma-names = "rx", "tx";
1452 }; 1442 };
1453 src8: src-8 { 1443 src8: src-8 {
1454 inter 1444 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1455 dmas 1445 dmas = <&audma0 0x95>, <&audma0 0xb8>;
1456 dma-n 1446 dma-names = "rx", "tx";
1457 }; 1447 };
1458 src9: src-9 { 1448 src9: src-9 {
1459 inter 1449 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
1460 dmas 1450 dmas = <&audma0 0x97>, <&audma0 0xba>;
1461 dma-n 1451 dma-names = "rx", "tx";
1462 }; 1452 };
1463 }; 1453 };
1464 1454
1465 rcar_sound,ssi { 1455 rcar_sound,ssi {
1466 ssi0: ssi-0 { 1456 ssi0: ssi-0 {
1467 inter 1457 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
1468 dmas 1458 dmas = <&audma0 0x01>, <&audma0 0x02>,
1469 1459 <&audma0 0x15>, <&audma0 0x16>;
1470 dma-n 1460 dma-names = "rx", "tx", "rxu", "txu";
1471 }; 1461 };
1472 ssi1: ssi-1 { 1462 ssi1: ssi-1 {
1473 inter 1463 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
1474 dmas 1464 dmas = <&audma0 0x03>, <&audma0 0x04>,
1475 1465 <&audma0 0x49>, <&audma0 0x4a>;
1476 dma-n 1466 dma-names = "rx", "tx", "rxu", "txu";
1477 }; 1467 };
1478 ssi2: ssi-2 { 1468 ssi2: ssi-2 {
1479 inter 1469 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
1480 dmas 1470 dmas = <&audma0 0x05>, <&audma0 0x06>,
1481 1471 <&audma0 0x63>, <&audma0 0x64>;
1482 dma-n 1472 dma-names = "rx", "tx", "rxu", "txu";
1483 }; 1473 };
1484 ssi3: ssi-3 { 1474 ssi3: ssi-3 {
1485 inter 1475 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1486 dmas 1476 dmas = <&audma0 0x07>, <&audma0 0x08>,
1487 1477 <&audma0 0x6f>, <&audma0 0x70>;
1488 dma-n 1478 dma-names = "rx", "tx", "rxu", "txu";
1489 }; 1479 };
1490 ssi4: ssi-4 { 1480 ssi4: ssi-4 {
1491 inter 1481 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1492 dmas 1482 dmas = <&audma0 0x09>, <&audma0 0x0a>,
1493 1483 <&audma0 0x71>, <&audma0 0x72>;
1494 dma-n 1484 dma-names = "rx", "tx", "rxu", "txu";
1495 }; 1485 };
1496 ssi5: ssi-5 { 1486 ssi5: ssi-5 {
1497 inter 1487 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1498 dmas 1488 dmas = <&audma0 0x0b>, <&audma0 0x0c>,
1499 1489 <&audma0 0x73>, <&audma0 0x74>;
1500 dma-n 1490 dma-names = "rx", "tx", "rxu", "txu";
1501 }; 1491 };
1502 ssi6: ssi-6 { 1492 ssi6: ssi-6 {
1503 inter 1493 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
1504 dmas 1494 dmas = <&audma0 0x0d>, <&audma0 0x0e>,
1505 1495 <&audma0 0x75>, <&audma0 0x76>;
1506 dma-n 1496 dma-names = "rx", "tx", "rxu", "txu";
1507 }; 1497 };
1508 ssi7: ssi-7 { 1498 ssi7: ssi-7 {
1509 inter 1499 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
1510 dmas 1500 dmas = <&audma0 0x0f>, <&audma0 0x10>,
1511 1501 <&audma0 0x79>, <&audma0 0x7a>;
1512 dma-n 1502 dma-names = "rx", "tx", "rxu", "txu";
1513 }; 1503 };
1514 ssi8: ssi-8 { 1504 ssi8: ssi-8 {
1515 inter 1505 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
1516 dmas 1506 dmas = <&audma0 0x11>, <&audma0 0x12>,
1517 1507 <&audma0 0x7b>, <&audma0 0x7c>;
1518 dma-n 1508 dma-names = "rx", "tx", "rxu", "txu";
1519 }; 1509 };
1520 ssi9: ssi-9 { 1510 ssi9: ssi-9 {
1521 inter 1511 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
1522 dmas 1512 dmas = <&audma0 0x13>, <&audma0 0x14>,
1523 1513 <&audma0 0x7d>, <&audma0 0x7e>;
1524 dma-n 1514 dma-names = "rx", "tx", "rxu", "txu";
1525 }; 1515 };
1526 }; 1516 };
1527 }; 1517 };
1528 1518
1529 audma0: dma-controller@ec7000 1519 audma0: dma-controller@ec700000 {
1530 compatible = "renesas 1520 compatible = "renesas,dmac-r8a774c0",
1531 "renesas 1521 "renesas,rcar-dmac";
1532 reg = <0 0xec700000 0 1522 reg = <0 0xec700000 0 0x10000>;
1533 interrupts = <GIC_SPI 1523 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
1534 <GIC_SPI 1524 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
1535 <GIC_SPI 1525 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
1536 <GIC_SPI 1526 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
1537 <GIC_SPI 1527 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
1538 <GIC_SPI 1528 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
1539 <GIC_SPI 1529 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
1540 <GIC_SPI 1530 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
1541 <GIC_SPI 1531 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
1542 <GIC_SPI 1532 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
1543 <GIC_SPI 1533 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1544 <GIC_SPI 1534 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
1545 <GIC_SPI 1535 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
1546 <GIC_SPI 1536 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
1547 <GIC_SPI 1537 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
1548 <GIC_SPI 1538 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1549 <GIC_SPI 1539 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
1550 interrupt-names = "er 1540 interrupt-names = "error",
1551 "ch0" 1541 "ch0", "ch1", "ch2", "ch3",
1552 "ch4" 1542 "ch4", "ch5", "ch6", "ch7",
1553 "ch8" 1543 "ch8", "ch9", "ch10", "ch11",
1554 "ch12 1544 "ch12", "ch13", "ch14", "ch15";
1555 clocks = <&cpg CPG_MO 1545 clocks = <&cpg CPG_MOD 502>;
1556 clock-names = "fck"; 1546 clock-names = "fck";
1557 power-domains = <&sys 1547 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1558 resets = <&cpg 502>; 1548 resets = <&cpg 502>;
1559 #dma-cells = <1>; 1549 #dma-cells = <1>;
1560 dma-channels = <16>; 1550 dma-channels = <16>;
1561 iommus = <&ipmmu_mp 0 1551 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
1562 <&ipmmu_mp 2 1552 <&ipmmu_mp 2>, <&ipmmu_mp 3>,
1563 <&ipmmu_mp 4 1553 <&ipmmu_mp 4>, <&ipmmu_mp 5>,
1564 <&ipmmu_mp 6 1554 <&ipmmu_mp 6>, <&ipmmu_mp 7>,
1565 <&ipmmu_mp 8 1555 <&ipmmu_mp 8>, <&ipmmu_mp 9>,
1566 <&ipmmu_mp 1 1556 <&ipmmu_mp 10>, <&ipmmu_mp 11>,
1567 <&ipmmu_mp 1 1557 <&ipmmu_mp 12>, <&ipmmu_mp 13>,
1568 <&ipmmu_mp 1 1558 <&ipmmu_mp 14>, <&ipmmu_mp 15>;
1569 }; 1559 };
1570 1560
1571 xhci0: usb@ee000000 { 1561 xhci0: usb@ee000000 {
1572 compatible = "renesas 1562 compatible = "renesas,xhci-r8a774c0",
1573 "renesas 1563 "renesas,rcar-gen3-xhci";
1574 reg = <0 0xee000000 0 1564 reg = <0 0xee000000 0 0xc00>;
1575 interrupts = <GIC_SPI 1565 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1576 clocks = <&cpg CPG_MO 1566 clocks = <&cpg CPG_MOD 328>;
1577 power-domains = <&sys 1567 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1578 resets = <&cpg 328>; 1568 resets = <&cpg 328>;
1579 status = "disabled"; 1569 status = "disabled";
1580 }; 1570 };
1581 1571
1582 usb3_peri0: usb@ee020000 { 1572 usb3_peri0: usb@ee020000 {
1583 compatible = "renesas 1573 compatible = "renesas,r8a774c0-usb3-peri",
1584 "renesas 1574 "renesas,rcar-gen3-usb3-peri";
1585 reg = <0 0xee020000 0 1575 reg = <0 0xee020000 0 0x400>;
1586 interrupts = <GIC_SPI 1576 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1587 clocks = <&cpg CPG_MO 1577 clocks = <&cpg CPG_MOD 328>;
1588 power-domains = <&sys 1578 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1589 resets = <&cpg 328>; 1579 resets = <&cpg 328>;
1590 status = "disabled"; 1580 status = "disabled";
1591 }; 1581 };
1592 1582
1593 ohci0: usb@ee080000 { 1583 ohci0: usb@ee080000 {
1594 compatible = "generic 1584 compatible = "generic-ohci";
1595 reg = <0 0xee080000 0 1585 reg = <0 0xee080000 0 0x100>;
1596 interrupts = <GIC_SPI 1586 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1597 clocks = <&cpg CPG_MO 1587 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
1598 phys = <&usb2_phy0 1> 1588 phys = <&usb2_phy0 1>;
1599 phy-names = "usb"; 1589 phy-names = "usb";
1600 power-domains = <&sys 1590 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1601 resets = <&cpg 703>, 1591 resets = <&cpg 703>, <&cpg 704>;
1602 status = "disabled"; 1592 status = "disabled";
1603 }; 1593 };
1604 1594
1605 ehci0: usb@ee080100 { 1595 ehci0: usb@ee080100 {
1606 compatible = "generic 1596 compatible = "generic-ehci";
1607 reg = <0 0xee080100 0 1597 reg = <0 0xee080100 0 0x100>;
1608 interrupts = <GIC_SPI 1598 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1609 clocks = <&cpg CPG_MO 1599 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
1610 phys = <&usb2_phy0 2> 1600 phys = <&usb2_phy0 2>;
1611 phy-names = "usb"; 1601 phy-names = "usb";
1612 companion = <&ohci0>; 1602 companion = <&ohci0>;
1613 power-domains = <&sys 1603 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1614 resets = <&cpg 703>, 1604 resets = <&cpg 703>, <&cpg 704>;
1615 status = "disabled"; 1605 status = "disabled";
1616 }; 1606 };
1617 1607
1618 usb2_phy0: usb-phy@ee080200 { 1608 usb2_phy0: usb-phy@ee080200 {
1619 compatible = "renesas 1609 compatible = "renesas,usb2-phy-r8a774c0",
1620 "renesas 1610 "renesas,rcar-gen3-usb2-phy";
1621 reg = <0 0xee080200 0 1611 reg = <0 0xee080200 0 0x700>;
1622 interrupts = <GIC_SPI 1612 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1623 clocks = <&cpg CPG_MO 1613 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
1624 power-domains = <&sys 1614 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1625 resets = <&cpg 703>, 1615 resets = <&cpg 703>, <&cpg 704>;
1626 #phy-cells = <1>; 1616 #phy-cells = <1>;
1627 status = "disabled"; 1617 status = "disabled";
1628 }; 1618 };
1629 1619
1630 sdhi0: mmc@ee100000 { 1620 sdhi0: mmc@ee100000 {
1631 compatible = "renesas 1621 compatible = "renesas,sdhi-r8a774c0",
1632 "renesas 1622 "renesas,rcar-gen3-sdhi";
1633 reg = <0 0xee100000 0 1623 reg = <0 0xee100000 0 0x2000>;
1634 interrupts = <GIC_SPI 1624 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
1635 clocks = <&cpg CPG_MO !! 1625 clocks = <&cpg CPG_MOD 314>;
1636 clock-names = "core", <<
1637 max-frequency = <2000 1626 max-frequency = <200000000>;
1638 power-domains = <&sys 1627 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1639 resets = <&cpg 314>; 1628 resets = <&cpg 314>;
1640 iommus = <&ipmmu_ds1 <<
1641 status = "disabled"; 1629 status = "disabled";
1642 }; 1630 };
1643 1631
1644 sdhi1: mmc@ee120000 { 1632 sdhi1: mmc@ee120000 {
1645 compatible = "renesas 1633 compatible = "renesas,sdhi-r8a774c0",
1646 "renesas 1634 "renesas,rcar-gen3-sdhi";
1647 reg = <0 0xee120000 0 1635 reg = <0 0xee120000 0 0x2000>;
1648 interrupts = <GIC_SPI 1636 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
1649 clocks = <&cpg CPG_MO !! 1637 clocks = <&cpg CPG_MOD 313>;
1650 clock-names = "core", <<
1651 max-frequency = <2000 1638 max-frequency = <200000000>;
1652 power-domains = <&sys 1639 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1653 resets = <&cpg 313>; 1640 resets = <&cpg 313>;
1654 iommus = <&ipmmu_ds1 <<
1655 status = "disabled"; 1641 status = "disabled";
1656 }; 1642 };
1657 1643
1658 sdhi3: mmc@ee160000 { 1644 sdhi3: mmc@ee160000 {
1659 compatible = "renesas 1645 compatible = "renesas,sdhi-r8a774c0",
1660 "renesas 1646 "renesas,rcar-gen3-sdhi";
1661 reg = <0 0xee160000 0 1647 reg = <0 0xee160000 0 0x2000>;
1662 interrupts = <GIC_SPI 1648 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
1663 clocks = <&cpg CPG_MO !! 1649 clocks = <&cpg CPG_MOD 311>;
1664 clock-names = "core", <<
1665 max-frequency = <2000 1650 max-frequency = <200000000>;
1666 power-domains = <&sys 1651 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1667 resets = <&cpg 311>; 1652 resets = <&cpg 311>;
1668 iommus = <&ipmmu_ds1 <<
1669 status = "disabled"; <<
1670 }; <<
1671 <<
1672 rpc: spi@ee200000 { <<
1673 compatible = "renesas <<
1674 "renesas <<
1675 reg = <0 0xee200000 0 <<
1676 <0 0x08000000 0 <<
1677 <0 0xee208000 0 <<
1678 reg-names = "regs", " <<
1679 interrupts = <GIC_SPI <<
1680 clocks = <&cpg CPG_MO <<
1681 power-domains = <&sys <<
1682 resets = <&cpg 917>; <<
1683 #address-cells = <1>; <<
1684 #size-cells = <0>; <<
1685 status = "disabled"; 1653 status = "disabled";
1686 }; 1654 };
1687 1655
1688 gic: interrupt-controller@f10 1656 gic: interrupt-controller@f1010000 {
1689 compatible = "arm,gic 1657 compatible = "arm,gic-400";
1690 #interrupt-cells = <3 1658 #interrupt-cells = <3>;
1691 #address-cells = <0>; 1659 #address-cells = <0>;
1692 interrupt-controller; 1660 interrupt-controller;
1693 reg = <0x0 0xf1010000 1661 reg = <0x0 0xf1010000 0 0x1000>,
1694 <0x0 0xf1020000 1662 <0x0 0xf1020000 0 0x20000>,
1695 <0x0 0xf1040000 1663 <0x0 0xf1040000 0 0x20000>,
1696 <0x0 0xf1060000 1664 <0x0 0xf1060000 0 0x20000>;
1697 interrupts = <GIC_PPI 1665 interrupts = <GIC_PPI 9
1698 (GIC_ 1666 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
1699 clocks = <&cpg CPG_MO 1667 clocks = <&cpg CPG_MOD 408>;
1700 clock-names = "clk"; 1668 clock-names = "clk";
1701 power-domains = <&sys 1669 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1702 resets = <&cpg 408>; 1670 resets = <&cpg 408>;
1703 }; 1671 };
1704 1672
1705 pciec0: pcie@fe000000 { 1673 pciec0: pcie@fe000000 {
1706 compatible = "renesas 1674 compatible = "renesas,pcie-r8a774c0",
1707 "renesas 1675 "renesas,pcie-rcar-gen3";
1708 reg = <0 0xfe000000 0 1676 reg = <0 0xfe000000 0 0x80000>;
1709 #address-cells = <3>; 1677 #address-cells = <3>;
1710 #size-cells = <2>; 1678 #size-cells = <2>;
1711 bus-range = <0x00 0xf 1679 bus-range = <0x00 0xff>;
1712 device_type = "pci"; 1680 device_type = "pci";
1713 ranges = <0x01000000 1681 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
1714 <0x02000000 1682 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
1715 <0x02000000 1683 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
1716 <0x42000000 1684 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1717 /* Map all possible D !! 1685 /* Map all possible DDR as inbound ranges */
1718 dma-ranges = <0x42000 !! 1686 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;
1719 interrupts = <GIC_SPI 1687 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1720 <GIC_SPI 1688 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1721 <GIC_SPI 1689 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1722 #interrupt-cells = <1 1690 #interrupt-cells = <1>;
1723 interrupt-map-mask = 1691 interrupt-map-mask = <0 0 0 0>;
1724 interrupt-map = <0 0 1692 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1725 clocks = <&cpg CPG_MO 1693 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
1726 clock-names = "pcie", 1694 clock-names = "pcie", "pcie_bus";
1727 power-domains = <&sys 1695 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1728 resets = <&cpg 319>; 1696 resets = <&cpg 319>;
1729 iommu-map = <0 &ipmmu <<
1730 iommu-map-mask = <0>; <<
1731 status = "disabled"; <<
1732 }; <<
1733 <<
1734 pciec0_ep: pcie-ep@fe000000 { <<
1735 compatible = "renesas <<
1736 "renesas <<
1737 reg = <0x0 0xfe000000 <<
1738 <0x0 0xfe100000 <<
1739 <0x0 0xfe200000 <<
1740 <0x0 0x30000000 <<
1741 <0x0 0x38000000 <<
1742 reg-names = "apb-base <<
1743 interrupts = <GIC_SPI <<
1744 <GIC_SPI <<
1745 <GIC_SPI <<
1746 clocks = <&cpg CPG_MO <<
1747 clock-names = "pcie"; <<
1748 resets = <&cpg 319>; <<
1749 power-domains = <&sys <<
1750 status = "disabled"; 1697 status = "disabled";
1751 }; 1698 };
1752 1699
1753 vspb0: vsp@fe960000 { 1700 vspb0: vsp@fe960000 {
1754 compatible = "renesas 1701 compatible = "renesas,vsp2";
1755 reg = <0 0xfe960000 0 1702 reg = <0 0xfe960000 0 0x8000>;
1756 interrupts = <GIC_SPI 1703 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
1757 clocks = <&cpg CPG_MO 1704 clocks = <&cpg CPG_MOD 626>;
1758 power-domains = <&sys 1705 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1759 resets = <&cpg 626>; 1706 resets = <&cpg 626>;
1760 renesas,fcp = <&fcpvb 1707 renesas,fcp = <&fcpvb0>;
1761 }; 1708 };
1762 1709
1763 vspd0: vsp@fea20000 { 1710 vspd0: vsp@fea20000 {
1764 compatible = "renesas 1711 compatible = "renesas,vsp2";
1765 reg = <0 0xfea20000 0 1712 reg = <0 0xfea20000 0 0x7000>;
1766 interrupts = <GIC_SPI 1713 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
1767 clocks = <&cpg CPG_MO 1714 clocks = <&cpg CPG_MOD 623>;
1768 power-domains = <&sys 1715 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1769 resets = <&cpg 623>; 1716 resets = <&cpg 623>;
1770 renesas,fcp = <&fcpvd 1717 renesas,fcp = <&fcpvd0>;
1771 }; 1718 };
1772 1719
1773 vspd1: vsp@fea28000 { 1720 vspd1: vsp@fea28000 {
1774 compatible = "renesas 1721 compatible = "renesas,vsp2";
1775 reg = <0 0xfea28000 0 1722 reg = <0 0xfea28000 0 0x7000>;
1776 interrupts = <GIC_SPI 1723 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
1777 clocks = <&cpg CPG_MO 1724 clocks = <&cpg CPG_MOD 622>;
1778 power-domains = <&sys 1725 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1779 resets = <&cpg 622>; 1726 resets = <&cpg 622>;
1780 renesas,fcp = <&fcpvd 1727 renesas,fcp = <&fcpvd1>;
1781 }; 1728 };
1782 1729
1783 vspi0: vsp@fe9a0000 { 1730 vspi0: vsp@fe9a0000 {
1784 compatible = "renesas 1731 compatible = "renesas,vsp2";
1785 reg = <0 0xfe9a0000 0 1732 reg = <0 0xfe9a0000 0 0x8000>;
1786 interrupts = <GIC_SPI 1733 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
1787 clocks = <&cpg CPG_MO 1734 clocks = <&cpg CPG_MOD 631>;
1788 power-domains = <&sys 1735 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1789 resets = <&cpg 631>; 1736 resets = <&cpg 631>;
1790 renesas,fcp = <&fcpvi 1737 renesas,fcp = <&fcpvi0>;
1791 }; 1738 };
1792 1739
1793 fcpvb0: fcp@fe96f000 { 1740 fcpvb0: fcp@fe96f000 {
1794 compatible = "renesas 1741 compatible = "renesas,fcpv";
1795 reg = <0 0xfe96f000 0 1742 reg = <0 0xfe96f000 0 0x200>;
1796 clocks = <&cpg CPG_MO 1743 clocks = <&cpg CPG_MOD 607>;
1797 power-domains = <&sys 1744 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1798 resets = <&cpg 607>; 1745 resets = <&cpg 607>;
1799 iommus = <&ipmmu_vp0 1746 iommus = <&ipmmu_vp0 5>;
1800 }; 1747 };
1801 1748
1802 fcpvd0: fcp@fea27000 { 1749 fcpvd0: fcp@fea27000 {
1803 compatible = "renesas 1750 compatible = "renesas,fcpv";
1804 reg = <0 0xfea27000 0 1751 reg = <0 0xfea27000 0 0x200>;
1805 clocks = <&cpg CPG_MO 1752 clocks = <&cpg CPG_MOD 603>;
1806 power-domains = <&sys 1753 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1807 resets = <&cpg 603>; 1754 resets = <&cpg 603>;
1808 iommus = <&ipmmu_vi0 1755 iommus = <&ipmmu_vi0 8>;
1809 }; 1756 };
1810 1757
1811 fcpvd1: fcp@fea2f000 { 1758 fcpvd1: fcp@fea2f000 {
1812 compatible = "renesas 1759 compatible = "renesas,fcpv";
1813 reg = <0 0xfea2f000 0 1760 reg = <0 0xfea2f000 0 0x200>;
1814 clocks = <&cpg CPG_MO 1761 clocks = <&cpg CPG_MOD 602>;
1815 power-domains = <&sys 1762 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1816 resets = <&cpg 602>; 1763 resets = <&cpg 602>;
1817 iommus = <&ipmmu_vi0 1764 iommus = <&ipmmu_vi0 9>;
1818 }; 1765 };
1819 1766
1820 fcpvi0: fcp@fe9af000 { 1767 fcpvi0: fcp@fe9af000 {
1821 compatible = "renesas 1768 compatible = "renesas,fcpv";
1822 reg = <0 0xfe9af000 0 1769 reg = <0 0xfe9af000 0 0x200>;
1823 clocks = <&cpg CPG_MO 1770 clocks = <&cpg CPG_MOD 611>;
1824 power-domains = <&sys 1771 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1825 resets = <&cpg 611>; 1772 resets = <&cpg 611>;
1826 iommus = <&ipmmu_vp0 1773 iommus = <&ipmmu_vp0 8>;
1827 }; 1774 };
1828 1775
1829 csi40: csi2@feaa0000 { 1776 csi40: csi2@feaa0000 {
1830 compatible = "renesas 1777 compatible = "renesas,r8a774c0-csi2";
1831 reg = <0 0xfeaa0000 0 1778 reg = <0 0xfeaa0000 0 0x10000>;
1832 interrupts = <GIC_SPI 1779 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
1833 clocks = <&cpg CPG_MO 1780 clocks = <&cpg CPG_MOD 716>;
1834 power-domains = <&sys 1781 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1835 resets = <&cpg 716>; 1782 resets = <&cpg 716>;
1836 status = "disabled"; 1783 status = "disabled";
1837 1784
1838 ports { 1785 ports {
1839 #address-cell 1786 #address-cells = <1>;
1840 #size-cells = 1787 #size-cells = <0>;
1841 1788
1842 port@0 { <<
1843 reg = <<
1844 }; <<
1845 <<
1846 port@1 { 1789 port@1 {
1847 #addr 1790 #address-cells = <1>;
1848 #size 1791 #size-cells = <0>;
1849 1792
1850 reg = 1793 reg = <1>;
1851 1794
1852 csi40 1795 csi40vin4: endpoint@0 {
1853 1796 reg = <0>;
1854 1797 remote-endpoint = <&vin4csi40>;
1855 }; 1798 };
1856 csi40 1799 csi40vin5: endpoint@1 {
1857 1800 reg = <1>;
1858 1801 remote-endpoint = <&vin5csi40>;
1859 }; 1802 };
1860 }; 1803 };
1861 }; 1804 };
1862 }; 1805 };
1863 1806
1864 du: display@feb00000 { 1807 du: display@feb00000 {
1865 compatible = "renesas 1808 compatible = "renesas,du-r8a774c0";
1866 reg = <0 0xfeb00000 0 1809 reg = <0 0xfeb00000 0 0x40000>;
1867 interrupts = <GIC_SPI 1810 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
1868 <GIC_SPI 1811 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
1869 clocks = <&cpg CPG_MO 1812 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
1870 clock-names = "du.0", 1813 clock-names = "du.0", "du.1";
1871 resets = <&cpg 724>; 1814 resets = <&cpg 724>;
1872 reset-names = "du.0"; 1815 reset-names = "du.0";
1873 renesas,vsps = <&vspd 1816 renesas,vsps = <&vspd0 0>, <&vspd1 0>;
1874 1817
1875 status = "disabled"; 1818 status = "disabled";
1876 1819
1877 ports { 1820 ports {
1878 #address-cell 1821 #address-cells = <1>;
1879 #size-cells = 1822 #size-cells = <0>;
1880 1823
1881 port@0 { 1824 port@0 {
1882 reg = 1825 reg = <0>;
>> 1826 du_out_rgb: endpoint {
>> 1827 };
1883 }; 1828 };
1884 1829
1885 port@1 { 1830 port@1 {
1886 reg = 1831 reg = <1>;
1887 du_ou 1832 du_out_lvds0: endpoint {
1888 1833 remote-endpoint = <&lvds0_in>;
1889 }; 1834 };
1890 }; 1835 };
1891 1836
1892 port@2 { 1837 port@2 {
1893 reg = 1838 reg = <2>;
1894 du_ou 1839 du_out_lvds1: endpoint {
1895 1840 remote-endpoint = <&lvds1_in>;
1896 }; 1841 };
1897 }; 1842 };
1898 }; 1843 };
1899 }; 1844 };
1900 1845
1901 lvds0: lvds-encoder@feb90000 1846 lvds0: lvds-encoder@feb90000 {
1902 compatible = "renesas 1847 compatible = "renesas,r8a774c0-lvds";
1903 reg = <0 0xfeb90000 0 1848 reg = <0 0xfeb90000 0 0x20>;
1904 clocks = <&cpg CPG_MO 1849 clocks = <&cpg CPG_MOD 727>;
1905 power-domains = <&sys 1850 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1906 resets = <&cpg 727>; 1851 resets = <&cpg 727>;
1907 status = "disabled"; 1852 status = "disabled";
1908 1853
1909 renesas,companion = < 1854 renesas,companion = <&lvds1>;
1910 1855
1911 ports { 1856 ports {
1912 #address-cell 1857 #address-cells = <1>;
1913 #size-cells = 1858 #size-cells = <0>;
1914 1859
1915 port@0 { 1860 port@0 {
1916 reg = 1861 reg = <0>;
1917 lvds0 1862 lvds0_in: endpoint {
1918 1863 remote-endpoint = <&du_out_lvds0>;
1919 }; 1864 };
1920 }; 1865 };
1921 1866
1922 port@1 { 1867 port@1 {
1923 reg = 1868 reg = <1>;
>> 1869 lvds0_out: endpoint {
>> 1870 };
1924 }; 1871 };
1925 }; 1872 };
1926 }; 1873 };
1927 1874
1928 lvds1: lvds-encoder@feb90100 1875 lvds1: lvds-encoder@feb90100 {
1929 compatible = "renesas 1876 compatible = "renesas,r8a774c0-lvds";
1930 reg = <0 0xfeb90100 0 1877 reg = <0 0xfeb90100 0 0x20>;
1931 clocks = <&cpg CPG_MO 1878 clocks = <&cpg CPG_MOD 727>;
1932 power-domains = <&sys 1879 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1933 resets = <&cpg 726>; 1880 resets = <&cpg 726>;
1934 status = "disabled"; 1881 status = "disabled";
1935 1882
1936 ports { 1883 ports {
1937 #address-cell 1884 #address-cells = <1>;
1938 #size-cells = 1885 #size-cells = <0>;
1939 1886
1940 port@0 { 1887 port@0 {
1941 reg = 1888 reg = <0>;
1942 lvds1 1889 lvds1_in: endpoint {
1943 1890 remote-endpoint = <&du_out_lvds1>;
1944 }; 1891 };
1945 }; 1892 };
1946 1893
1947 port@1 { 1894 port@1 {
1948 reg = 1895 reg = <1>;
>> 1896 lvds1_out: endpoint {
>> 1897 };
1949 }; 1898 };
1950 }; 1899 };
1951 }; 1900 };
1952 1901
1953 prr: chipid@fff00044 { 1902 prr: chipid@fff00044 {
1954 compatible = "renesas 1903 compatible = "renesas,prr";
1955 reg = <0 0xfff00044 0 1904 reg = <0 0xfff00044 0 4>;
1956 }; 1905 };
1957 }; 1906 };
1958 1907
1959 thermal-zones { 1908 thermal-zones {
1960 cpu-thermal { 1909 cpu-thermal {
1961 polling-delay-passive 1910 polling-delay-passive = <250>;
1962 polling-delay = <0>; 1911 polling-delay = <0>;
1963 thermal-sensors = <&t !! 1912 thermal-sensors = <&thermal 0>;
1964 sustainable-power = < 1913 sustainable-power = <717>;
1965 1914
1966 cooling-maps { 1915 cooling-maps {
1967 map0 { 1916 map0 {
1968 trip 1917 trip = <&target>;
1969 cooli 1918 cooling-device = <&a53_0 0 2>;
1970 contr 1919 contribution = <1024>;
1971 }; 1920 };
1972 }; 1921 };
1973 1922
1974 trips { 1923 trips {
1975 sensor1_crit: 1924 sensor1_crit: sensor1-crit {
1976 tempe 1925 temperature = <120000>;
1977 hyste 1926 hysteresis = <2000>;
1978 type 1927 type = "critical";
1979 }; 1928 };
1980 1929
1981 target: trip- 1930 target: trip-point1 {
1982 tempe 1931 temperature = <100000>;
1983 hyste 1932 hysteresis = <2000>;
1984 type 1933 type = "passive";
1985 }; 1934 };
1986 }; 1935 };
1987 }; 1936 };
1988 }; 1937 };
1989 1938
1990 timer { 1939 timer {
1991 compatible = "arm,armv8-timer 1940 compatible = "arm,armv8-timer";
1992 interrupts-extended = <&gic G 1941 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1993 <&gic G 1942 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1994 <&gic G 1943 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1995 <&gic G 1944 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
1996 interrupt-names = "sec-phys", <<
1997 }; 1945 };
1998 1946
1999 /* External USB clocks - can be overr 1947 /* External USB clocks - can be overridden by the board */
2000 usb3s0_clk: usb3s0 { 1948 usb3s0_clk: usb3s0 {
2001 compatible = "fixed-clock"; 1949 compatible = "fixed-clock";
2002 #clock-cells = <0>; 1950 #clock-cells = <0>;
2003 clock-frequency = <0>; 1951 clock-frequency = <0>;
2004 }; 1952 };
2005 1953
2006 usb_extal_clk: usb_extal { 1954 usb_extal_clk: usb_extal {
2007 compatible = "fixed-clock"; 1955 compatible = "fixed-clock";
2008 #clock-cells = <0>; 1956 #clock-cells = <0>;
2009 clock-frequency = <0>; 1957 clock-frequency = <0>;
2010 }; 1958 };
2011 }; 1959 };
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