1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * Device Tree Source for the RZ/G2E (R8A774C0 3 * Device Tree Source for the RZ/G2E (R8A774C0) SoC
4 * 4 *
5 * Copyright (C) 2018-2019 Renesas Electronics 5 * Copyright (C) 2018-2019 Renesas Electronics Corp.
6 */ 6 */
7 7
8 #include <dt-bindings/clock/r8a774c0-cpg-mssr. 8 #include <dt-bindings/clock/r8a774c0-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm 9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a774c0-sysc.h> 10 #include <dt-bindings/power/r8a774c0-sysc.h>
11 11
12 / { 12 / {
13 compatible = "renesas,r8a774c0"; 13 compatible = "renesas,r8a774c0";
14 #address-cells = <2>; 14 #address-cells = <2>;
15 #size-cells = <2>; 15 #size-cells = <2>;
16 16
17 /* 17 /*
18 * The external audio clocks are confi 18 * The external audio clocks are configured as 0 Hz fixed frequency
19 * clocks by default. 19 * clocks by default.
20 * Boards that provide audio clocks sh 20 * Boards that provide audio clocks should override them.
21 */ 21 */
22 audio_clk_a: audio_clk_a { 22 audio_clk_a: audio_clk_a {
23 compatible = "fixed-clock"; 23 compatible = "fixed-clock";
24 #clock-cells = <0>; 24 #clock-cells = <0>;
25 clock-frequency = <0>; 25 clock-frequency = <0>;
26 }; 26 };
27 27
28 audio_clk_b: audio_clk_b { 28 audio_clk_b: audio_clk_b {
29 compatible = "fixed-clock"; 29 compatible = "fixed-clock";
30 #clock-cells = <0>; 30 #clock-cells = <0>;
31 clock-frequency = <0>; 31 clock-frequency = <0>;
32 }; 32 };
33 33
34 audio_clk_c: audio_clk_c { 34 audio_clk_c: audio_clk_c {
35 compatible = "fixed-clock"; 35 compatible = "fixed-clock";
36 #clock-cells = <0>; 36 #clock-cells = <0>;
37 clock-frequency = <0>; 37 clock-frequency = <0>;
38 }; 38 };
39 39
40 /* External CAN clock - to be overridd 40 /* External CAN clock - to be overridden by boards that provide it */
41 can_clk: can { 41 can_clk: can {
42 compatible = "fixed-clock"; 42 compatible = "fixed-clock";
43 #clock-cells = <0>; 43 #clock-cells = <0>;
44 clock-frequency = <0>; 44 clock-frequency = <0>;
45 }; 45 };
46 46
47 cluster1_opp: opp-table-1 { 47 cluster1_opp: opp-table-1 {
48 compatible = "operating-points 48 compatible = "operating-points-v2";
49 opp-shared; 49 opp-shared;
50 opp-800000000 { 50 opp-800000000 {
51 opp-hz = /bits/ 64 <80 51 opp-hz = /bits/ 64 <800000000>;
>> 52 opp-microvolt = <820000>;
52 clock-latency-ns = <30 53 clock-latency-ns = <300000>;
53 }; 54 };
54 opp-1000000000 { 55 opp-1000000000 {
55 opp-hz = /bits/ 64 <10 56 opp-hz = /bits/ 64 <1000000000>;
>> 57 opp-microvolt = <820000>;
56 clock-latency-ns = <30 58 clock-latency-ns = <300000>;
57 }; 59 };
58 opp-1200000000 { 60 opp-1200000000 {
59 opp-hz = /bits/ 64 <12 61 opp-hz = /bits/ 64 <1200000000>;
>> 62 opp-microvolt = <820000>;
60 clock-latency-ns = <30 63 clock-latency-ns = <300000>;
61 opp-suspend; 64 opp-suspend;
62 }; 65 };
63 }; 66 };
64 67
65 cpus { 68 cpus {
66 #address-cells = <1>; 69 #address-cells = <1>;
67 #size-cells = <0>; 70 #size-cells = <0>;
68 71
69 a53_0: cpu@0 { 72 a53_0: cpu@0 {
70 compatible = "arm,cort 73 compatible = "arm,cortex-a53";
71 reg = <0>; 74 reg = <0>;
72 device_type = "cpu"; 75 device_type = "cpu";
73 #cooling-cells = <2>; 76 #cooling-cells = <2>;
74 power-domains = <&sysc 77 power-domains = <&sysc R8A774C0_PD_CA53_CPU0>;
75 next-level-cache = <&L 78 next-level-cache = <&L2_CA53>;
76 enable-method = "psci" 79 enable-method = "psci";
77 dynamic-power-coeffici 80 dynamic-power-coefficient = <277>;
78 clocks = <&cpg CPG_COR 81 clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>;
79 operating-points-v2 = 82 operating-points-v2 = <&cluster1_opp>;
80 }; 83 };
81 84
82 a53_1: cpu@1 { 85 a53_1: cpu@1 {
83 compatible = "arm,cort 86 compatible = "arm,cortex-a53";
84 reg = <1>; 87 reg = <1>;
85 device_type = "cpu"; 88 device_type = "cpu";
86 power-domains = <&sysc 89 power-domains = <&sysc R8A774C0_PD_CA53_CPU1>;
87 next-level-cache = <&L 90 next-level-cache = <&L2_CA53>;
88 enable-method = "psci" 91 enable-method = "psci";
89 clocks = <&cpg CPG_COR 92 clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>;
90 operating-points-v2 = 93 operating-points-v2 = <&cluster1_opp>;
91 }; 94 };
92 95
93 L2_CA53: cache-controller-0 { 96 L2_CA53: cache-controller-0 {
94 compatible = "cache"; 97 compatible = "cache";
95 power-domains = <&sysc 98 power-domains = <&sysc R8A774C0_PD_CA53_SCU>;
96 cache-unified; 99 cache-unified;
97 cache-level = <2>; 100 cache-level = <2>;
98 }; 101 };
99 }; 102 };
100 103
101 extal_clk: extal { 104 extal_clk: extal {
102 compatible = "fixed-clock"; 105 compatible = "fixed-clock";
103 #clock-cells = <0>; 106 #clock-cells = <0>;
104 /* This value must be overridd 107 /* This value must be overridden by the board */
105 clock-frequency = <0>; 108 clock-frequency = <0>;
106 }; 109 };
107 110
108 /* External PCIe clock - can be overri 111 /* External PCIe clock - can be overridden by the board */
109 pcie_bus_clk: pcie_bus { 112 pcie_bus_clk: pcie_bus {
110 compatible = "fixed-clock"; 113 compatible = "fixed-clock";
111 #clock-cells = <0>; 114 #clock-cells = <0>;
112 clock-frequency = <0>; 115 clock-frequency = <0>;
113 }; 116 };
114 117
115 pmu_a53 { 118 pmu_a53 {
116 compatible = "arm,cortex-a53-p 119 compatible = "arm,cortex-a53-pmu";
117 interrupts-extended = <&gic GI 120 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
118 <&gic GI 121 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
119 interrupt-affinity = <&a53_0>, 122 interrupt-affinity = <&a53_0>, <&a53_1>;
120 }; 123 };
121 124
122 psci { 125 psci {
123 compatible = "arm,psci-1.0", " 126 compatible = "arm,psci-1.0", "arm,psci-0.2";
124 method = "smc"; 127 method = "smc";
125 }; 128 };
126 129
127 /* External SCIF clock - to be overrid 130 /* External SCIF clock - to be overridden by boards that provide it */
128 scif_clk: scif { 131 scif_clk: scif {
129 compatible = "fixed-clock"; 132 compatible = "fixed-clock";
130 #clock-cells = <0>; 133 #clock-cells = <0>;
131 clock-frequency = <0>; 134 clock-frequency = <0>;
132 }; 135 };
133 136
134 soc: soc { 137 soc: soc {
135 compatible = "simple-bus"; 138 compatible = "simple-bus";
136 interrupt-parent = <&gic>; 139 interrupt-parent = <&gic>;
137 #address-cells = <2>; 140 #address-cells = <2>;
138 #size-cells = <2>; 141 #size-cells = <2>;
139 ranges; 142 ranges;
140 143
141 rwdt: watchdog@e6020000 { 144 rwdt: watchdog@e6020000 {
142 compatible = "renesas, 145 compatible = "renesas,r8a774c0-wdt",
143 "renesas, 146 "renesas,rcar-gen3-wdt";
144 reg = <0 0xe6020000 0 147 reg = <0 0xe6020000 0 0x0c>;
145 interrupts = <GIC_SPI 148 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
146 clocks = <&cpg CPG_MOD 149 clocks = <&cpg CPG_MOD 402>;
147 power-domains = <&sysc 150 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
148 resets = <&cpg 402>; 151 resets = <&cpg 402>;
149 status = "disabled"; 152 status = "disabled";
150 }; 153 };
151 154
152 gpio0: gpio@e6050000 { 155 gpio0: gpio@e6050000 {
153 compatible = "renesas, 156 compatible = "renesas,gpio-r8a774c0",
154 "renesas, 157 "renesas,rcar-gen3-gpio";
155 reg = <0 0xe6050000 0 158 reg = <0 0xe6050000 0 0x50>;
156 interrupts = <GIC_SPI 159 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
157 #gpio-cells = <2>; 160 #gpio-cells = <2>;
158 gpio-controller; 161 gpio-controller;
159 gpio-ranges = <&pfc 0 162 gpio-ranges = <&pfc 0 0 18>;
160 #interrupt-cells = <2> 163 #interrupt-cells = <2>;
161 interrupt-controller; 164 interrupt-controller;
162 clocks = <&cpg CPG_MOD 165 clocks = <&cpg CPG_MOD 912>;
163 power-domains = <&sysc 166 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
164 resets = <&cpg 912>; 167 resets = <&cpg 912>;
165 }; 168 };
166 169
167 gpio1: gpio@e6051000 { 170 gpio1: gpio@e6051000 {
168 compatible = "renesas, 171 compatible = "renesas,gpio-r8a774c0",
169 "renesas, 172 "renesas,rcar-gen3-gpio";
170 reg = <0 0xe6051000 0 173 reg = <0 0xe6051000 0 0x50>;
171 interrupts = <GIC_SPI 174 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
172 #gpio-cells = <2>; 175 #gpio-cells = <2>;
173 gpio-controller; 176 gpio-controller;
174 gpio-ranges = <&pfc 0 177 gpio-ranges = <&pfc 0 32 23>;
175 #interrupt-cells = <2> 178 #interrupt-cells = <2>;
176 interrupt-controller; 179 interrupt-controller;
177 clocks = <&cpg CPG_MOD 180 clocks = <&cpg CPG_MOD 911>;
178 power-domains = <&sysc 181 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
179 resets = <&cpg 911>; 182 resets = <&cpg 911>;
180 }; 183 };
181 184
182 gpio2: gpio@e6052000 { 185 gpio2: gpio@e6052000 {
183 compatible = "renesas, 186 compatible = "renesas,gpio-r8a774c0",
184 "renesas, 187 "renesas,rcar-gen3-gpio";
185 reg = <0 0xe6052000 0 188 reg = <0 0xe6052000 0 0x50>;
186 interrupts = <GIC_SPI 189 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
187 #gpio-cells = <2>; 190 #gpio-cells = <2>;
188 gpio-controller; 191 gpio-controller;
189 gpio-ranges = <&pfc 0 192 gpio-ranges = <&pfc 0 64 26>;
190 #interrupt-cells = <2> 193 #interrupt-cells = <2>;
191 interrupt-controller; 194 interrupt-controller;
192 clocks = <&cpg CPG_MOD 195 clocks = <&cpg CPG_MOD 910>;
193 power-domains = <&sysc 196 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
194 resets = <&cpg 910>; 197 resets = <&cpg 910>;
195 }; 198 };
196 199
197 gpio3: gpio@e6053000 { 200 gpio3: gpio@e6053000 {
198 compatible = "renesas, 201 compatible = "renesas,gpio-r8a774c0",
199 "renesas, 202 "renesas,rcar-gen3-gpio";
200 reg = <0 0xe6053000 0 203 reg = <0 0xe6053000 0 0x50>;
201 interrupts = <GIC_SPI 204 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
202 #gpio-cells = <2>; 205 #gpio-cells = <2>;
203 gpio-controller; 206 gpio-controller;
204 gpio-ranges = <&pfc 0 207 gpio-ranges = <&pfc 0 96 16>;
205 #interrupt-cells = <2> 208 #interrupt-cells = <2>;
206 interrupt-controller; 209 interrupt-controller;
207 clocks = <&cpg CPG_MOD 210 clocks = <&cpg CPG_MOD 909>;
208 power-domains = <&sysc 211 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
209 resets = <&cpg 909>; 212 resets = <&cpg 909>;
210 }; 213 };
211 214
212 gpio4: gpio@e6054000 { 215 gpio4: gpio@e6054000 {
213 compatible = "renesas, 216 compatible = "renesas,gpio-r8a774c0",
214 "renesas, 217 "renesas,rcar-gen3-gpio";
215 reg = <0 0xe6054000 0 218 reg = <0 0xe6054000 0 0x50>;
216 interrupts = <GIC_SPI 219 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
217 #gpio-cells = <2>; 220 #gpio-cells = <2>;
218 gpio-controller; 221 gpio-controller;
219 gpio-ranges = <&pfc 0 222 gpio-ranges = <&pfc 0 128 11>;
220 #interrupt-cells = <2> 223 #interrupt-cells = <2>;
221 interrupt-controller; 224 interrupt-controller;
222 clocks = <&cpg CPG_MOD 225 clocks = <&cpg CPG_MOD 908>;
223 power-domains = <&sysc 226 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
224 resets = <&cpg 908>; 227 resets = <&cpg 908>;
225 }; 228 };
226 229
227 gpio5: gpio@e6055000 { 230 gpio5: gpio@e6055000 {
228 compatible = "renesas, 231 compatible = "renesas,gpio-r8a774c0",
229 "renesas, 232 "renesas,rcar-gen3-gpio";
230 reg = <0 0xe6055000 0 233 reg = <0 0xe6055000 0 0x50>;
231 interrupts = <GIC_SPI 234 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
232 #gpio-cells = <2>; 235 #gpio-cells = <2>;
233 gpio-controller; 236 gpio-controller;
234 gpio-ranges = <&pfc 0 237 gpio-ranges = <&pfc 0 160 20>;
235 #interrupt-cells = <2> 238 #interrupt-cells = <2>;
236 interrupt-controller; 239 interrupt-controller;
237 clocks = <&cpg CPG_MOD 240 clocks = <&cpg CPG_MOD 907>;
238 power-domains = <&sysc 241 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
239 resets = <&cpg 907>; 242 resets = <&cpg 907>;
240 }; 243 };
241 244
242 gpio6: gpio@e6055400 { 245 gpio6: gpio@e6055400 {
243 compatible = "renesas, 246 compatible = "renesas,gpio-r8a774c0",
244 "renesas, 247 "renesas,rcar-gen3-gpio";
245 reg = <0 0xe6055400 0 248 reg = <0 0xe6055400 0 0x50>;
246 interrupts = <GIC_SPI 249 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
247 #gpio-cells = <2>; 250 #gpio-cells = <2>;
248 gpio-controller; 251 gpio-controller;
249 gpio-ranges = <&pfc 0 252 gpio-ranges = <&pfc 0 192 18>;
250 #interrupt-cells = <2> 253 #interrupt-cells = <2>;
251 interrupt-controller; 254 interrupt-controller;
252 clocks = <&cpg CPG_MOD 255 clocks = <&cpg CPG_MOD 906>;
253 power-domains = <&sysc 256 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
254 resets = <&cpg 906>; 257 resets = <&cpg 906>;
255 }; 258 };
256 259
257 pfc: pinctrl@e6060000 { 260 pfc: pinctrl@e6060000 {
258 compatible = "renesas, 261 compatible = "renesas,pfc-r8a774c0";
259 reg = <0 0xe6060000 0 262 reg = <0 0xe6060000 0 0x508>;
260 }; 263 };
261 264
262 cmt0: timer@e60f0000 { 265 cmt0: timer@e60f0000 {
263 compatible = "renesas, 266 compatible = "renesas,r8a774c0-cmt0",
264 "renesas, 267 "renesas,rcar-gen3-cmt0";
265 reg = <0 0xe60f0000 0 268 reg = <0 0xe60f0000 0 0x1004>;
266 interrupts = <GIC_SPI 269 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
267 <GIC_SPI 270 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
268 clocks = <&cpg CPG_MOD 271 clocks = <&cpg CPG_MOD 303>;
269 clock-names = "fck"; 272 clock-names = "fck";
270 power-domains = <&sysc 273 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
271 resets = <&cpg 303>; 274 resets = <&cpg 303>;
272 status = "disabled"; 275 status = "disabled";
273 }; 276 };
274 277
275 cmt1: timer@e6130000 { 278 cmt1: timer@e6130000 {
276 compatible = "renesas, 279 compatible = "renesas,r8a774c0-cmt1",
277 "renesas, 280 "renesas,rcar-gen3-cmt1";
278 reg = <0 0xe6130000 0 281 reg = <0 0xe6130000 0 0x1004>;
279 interrupts = <GIC_SPI 282 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
280 <GIC_SPI 283 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
281 <GIC_SPI 284 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
282 <GIC_SPI 285 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
283 <GIC_SPI 286 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
284 <GIC_SPI 287 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
285 <GIC_SPI 288 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
286 <GIC_SPI 289 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
287 clocks = <&cpg CPG_MOD 290 clocks = <&cpg CPG_MOD 302>;
288 clock-names = "fck"; 291 clock-names = "fck";
289 power-domains = <&sysc 292 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
290 resets = <&cpg 302>; 293 resets = <&cpg 302>;
291 status = "disabled"; 294 status = "disabled";
292 }; 295 };
293 296
294 cmt2: timer@e6140000 { 297 cmt2: timer@e6140000 {
295 compatible = "renesas, 298 compatible = "renesas,r8a774c0-cmt1",
296 "renesas, 299 "renesas,rcar-gen3-cmt1";
297 reg = <0 0xe6140000 0 300 reg = <0 0xe6140000 0 0x1004>;
298 interrupts = <GIC_SPI 301 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
299 <GIC_SPI 302 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
300 <GIC_SPI 303 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
301 <GIC_SPI 304 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
302 <GIC_SPI 305 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
303 <GIC_SPI 306 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
304 <GIC_SPI 307 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
305 <GIC_SPI 308 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
306 clocks = <&cpg CPG_MOD 309 clocks = <&cpg CPG_MOD 301>;
307 clock-names = "fck"; 310 clock-names = "fck";
308 power-domains = <&sysc 311 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
309 resets = <&cpg 301>; 312 resets = <&cpg 301>;
310 status = "disabled"; 313 status = "disabled";
311 }; 314 };
312 315
313 cmt3: timer@e6148000 { 316 cmt3: timer@e6148000 {
314 compatible = "renesas, 317 compatible = "renesas,r8a774c0-cmt1",
315 "renesas, 318 "renesas,rcar-gen3-cmt1";
316 reg = <0 0xe6148000 0 319 reg = <0 0xe6148000 0 0x1004>;
317 interrupts = <GIC_SPI 320 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
318 <GIC_SPI 321 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
319 <GIC_SPI 322 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
320 <GIC_SPI 323 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
321 <GIC_SPI 324 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
322 <GIC_SPI 325 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
323 <GIC_SPI 326 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
324 <GIC_SPI 327 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
325 clocks = <&cpg CPG_MOD 328 clocks = <&cpg CPG_MOD 300>;
326 clock-names = "fck"; 329 clock-names = "fck";
327 power-domains = <&sysc 330 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
328 resets = <&cpg 300>; 331 resets = <&cpg 300>;
329 status = "disabled"; 332 status = "disabled";
330 }; 333 };
331 334
332 cpg: clock-controller@e6150000 335 cpg: clock-controller@e6150000 {
333 compatible = "renesas, 336 compatible = "renesas,r8a774c0-cpg-mssr";
334 reg = <0 0xe6150000 0 337 reg = <0 0xe6150000 0 0x1000>;
335 clocks = <&extal_clk>; 338 clocks = <&extal_clk>;
336 clock-names = "extal"; 339 clock-names = "extal";
337 #clock-cells = <2>; 340 #clock-cells = <2>;
338 #power-domain-cells = 341 #power-domain-cells = <0>;
339 #reset-cells = <1>; 342 #reset-cells = <1>;
340 }; 343 };
341 344
342 rst: reset-controller@e6160000 345 rst: reset-controller@e6160000 {
343 compatible = "renesas, 346 compatible = "renesas,r8a774c0-rst";
344 reg = <0 0xe6160000 0 347 reg = <0 0xe6160000 0 0x0200>;
345 }; 348 };
346 349
347 sysc: system-controller@e61800 350 sysc: system-controller@e6180000 {
348 compatible = "renesas, 351 compatible = "renesas,r8a774c0-sysc";
349 reg = <0 0xe6180000 0 352 reg = <0 0xe6180000 0 0x0400>;
350 #power-domain-cells = 353 #power-domain-cells = <1>;
351 }; 354 };
352 355
353 thermal: thermal@e6190000 { 356 thermal: thermal@e6190000 {
354 compatible = "renesas, 357 compatible = "renesas,thermal-r8a774c0";
355 reg = <0 0xe6190000 0 358 reg = <0 0xe6190000 0 0x10>, <0 0xe6190100 0 0x38>;
356 interrupts = <GIC_SPI 359 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
357 <GIC_SPI 360 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
358 <GIC_SPI 361 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
359 clocks = <&cpg CPG_MOD 362 clocks = <&cpg CPG_MOD 522>;
360 power-domains = <&sysc 363 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
361 resets = <&cpg 522>; 364 resets = <&cpg 522>;
362 #thermal-sensor-cells 365 #thermal-sensor-cells = <0>;
363 }; 366 };
364 367
365 intc_ex: interrupt-controller@ 368 intc_ex: interrupt-controller@e61c0000 {
366 compatible = "renesas, 369 compatible = "renesas,intc-ex-r8a774c0", "renesas,irqc";
367 #interrupt-cells = <2> 370 #interrupt-cells = <2>;
368 interrupt-controller; 371 interrupt-controller;
369 reg = <0 0xe61c0000 0 372 reg = <0 0xe61c0000 0 0x200>;
370 interrupts = <GIC_SPI 373 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
371 <GIC_SPI 374 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
372 <GIC_SPI 375 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
373 <GIC_SPI 376 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
374 <GIC_SPI 377 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
375 <GIC_SPI 378 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
376 clocks = <&cpg CPG_MOD 379 clocks = <&cpg CPG_MOD 407>;
377 power-domains = <&sysc 380 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
378 resets = <&cpg 407>; 381 resets = <&cpg 407>;
379 }; 382 };
380 383
381 tmu0: timer@e61e0000 { 384 tmu0: timer@e61e0000 {
382 compatible = "renesas, 385 compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
383 reg = <0 0xe61e0000 0 386 reg = <0 0xe61e0000 0 0x30>;
384 interrupts = <GIC_SPI 387 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
385 <GIC_SPI 388 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
386 <GIC_SPI 389 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
387 interrupt-names = "tun <<
388 clocks = <&cpg CPG_MOD 390 clocks = <&cpg CPG_MOD 125>;
389 clock-names = "fck"; 391 clock-names = "fck";
390 power-domains = <&sysc 392 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
391 resets = <&cpg 125>; 393 resets = <&cpg 125>;
392 status = "disabled"; 394 status = "disabled";
393 }; 395 };
394 396
395 tmu1: timer@e6fc0000 { 397 tmu1: timer@e6fc0000 {
396 compatible = "renesas, 398 compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
397 reg = <0 0xe6fc0000 0 399 reg = <0 0xe6fc0000 0 0x30>;
398 interrupts = <GIC_SPI 400 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
399 <GIC_SPI 401 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
400 <GIC_SPI !! 402 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
401 <GIC_SPI <<
402 interrupt-names = "tun <<
403 clocks = <&cpg CPG_MOD 403 clocks = <&cpg CPG_MOD 124>;
404 clock-names = "fck"; 404 clock-names = "fck";
405 power-domains = <&sysc 405 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
406 resets = <&cpg 124>; 406 resets = <&cpg 124>;
407 status = "disabled"; 407 status = "disabled";
408 }; 408 };
409 409
410 tmu2: timer@e6fd0000 { 410 tmu2: timer@e6fd0000 {
411 compatible = "renesas, 411 compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
412 reg = <0 0xe6fd0000 0 412 reg = <0 0xe6fd0000 0 0x30>;
413 interrupts = <GIC_SPI 413 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
414 <GIC_SPI 414 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
415 <GIC_SPI !! 415 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
416 <GIC_SPI <<
417 interrupt-names = "tun <<
418 clocks = <&cpg CPG_MOD 416 clocks = <&cpg CPG_MOD 123>;
419 clock-names = "fck"; 417 clock-names = "fck";
420 power-domains = <&sysc 418 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
421 resets = <&cpg 123>; 419 resets = <&cpg 123>;
422 status = "disabled"; 420 status = "disabled";
423 }; 421 };
424 422
425 tmu3: timer@e6fe0000 { 423 tmu3: timer@e6fe0000 {
426 compatible = "renesas, 424 compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
427 reg = <0 0xe6fe0000 0 425 reg = <0 0xe6fe0000 0 0x30>;
428 interrupts = <GIC_SPI 426 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
429 <GIC_SPI 427 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
430 <GIC_SPI 428 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
431 interrupt-names = "tun <<
432 clocks = <&cpg CPG_MOD 429 clocks = <&cpg CPG_MOD 122>;
433 clock-names = "fck"; 430 clock-names = "fck";
434 power-domains = <&sysc 431 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
435 resets = <&cpg 122>; 432 resets = <&cpg 122>;
436 status = "disabled"; 433 status = "disabled";
437 }; 434 };
438 435
439 tmu4: timer@ffc00000 { 436 tmu4: timer@ffc00000 {
440 compatible = "renesas, 437 compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
441 reg = <0 0xffc00000 0 438 reg = <0 0xffc00000 0 0x30>;
442 interrupts = <GIC_SPI 439 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
443 <GIC_SPI 440 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
444 <GIC_SPI 441 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
445 interrupt-names = "tun <<
446 clocks = <&cpg CPG_MOD 442 clocks = <&cpg CPG_MOD 121>;
447 clock-names = "fck"; 443 clock-names = "fck";
448 power-domains = <&sysc 444 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
449 resets = <&cpg 121>; 445 resets = <&cpg 121>;
450 status = "disabled"; 446 status = "disabled";
451 }; 447 };
452 448
453 i2c0: i2c@e6500000 { 449 i2c0: i2c@e6500000 {
454 #address-cells = <1>; 450 #address-cells = <1>;
455 #size-cells = <0>; 451 #size-cells = <0>;
456 compatible = "renesas, 452 compatible = "renesas,i2c-r8a774c0",
457 "renesas, 453 "renesas,rcar-gen3-i2c";
458 reg = <0 0xe6500000 0 454 reg = <0 0xe6500000 0 0x40>;
459 interrupts = <GIC_SPI 455 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
460 clocks = <&cpg CPG_MOD 456 clocks = <&cpg CPG_MOD 931>;
461 power-domains = <&sysc 457 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
462 resets = <&cpg 931>; 458 resets = <&cpg 931>;
463 dmas = <&dmac1 0x91>, 459 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
464 <&dmac2 0x91>, 460 <&dmac2 0x91>, <&dmac2 0x90>;
465 dma-names = "tx", "rx" 461 dma-names = "tx", "rx", "tx", "rx";
466 i2c-scl-internal-delay 462 i2c-scl-internal-delay-ns = <110>;
467 status = "disabled"; 463 status = "disabled";
468 }; 464 };
469 465
470 i2c1: i2c@e6508000 { 466 i2c1: i2c@e6508000 {
471 #address-cells = <1>; 467 #address-cells = <1>;
472 #size-cells = <0>; 468 #size-cells = <0>;
473 compatible = "renesas, 469 compatible = "renesas,i2c-r8a774c0",
474 "renesas, 470 "renesas,rcar-gen3-i2c";
475 reg = <0 0xe6508000 0 471 reg = <0 0xe6508000 0 0x40>;
476 interrupts = <GIC_SPI 472 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
477 clocks = <&cpg CPG_MOD 473 clocks = <&cpg CPG_MOD 930>;
478 power-domains = <&sysc 474 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
479 resets = <&cpg 930>; 475 resets = <&cpg 930>;
480 dmas = <&dmac1 0x93>, 476 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
481 <&dmac2 0x93>, 477 <&dmac2 0x93>, <&dmac2 0x92>;
482 dma-names = "tx", "rx" 478 dma-names = "tx", "rx", "tx", "rx";
483 i2c-scl-internal-delay 479 i2c-scl-internal-delay-ns = <6>;
484 status = "disabled"; 480 status = "disabled";
485 }; 481 };
486 482
487 i2c2: i2c@e6510000 { 483 i2c2: i2c@e6510000 {
488 #address-cells = <1>; 484 #address-cells = <1>;
489 #size-cells = <0>; 485 #size-cells = <0>;
490 compatible = "renesas, 486 compatible = "renesas,i2c-r8a774c0",
491 "renesas, 487 "renesas,rcar-gen3-i2c";
492 reg = <0 0xe6510000 0 488 reg = <0 0xe6510000 0 0x40>;
493 interrupts = <GIC_SPI 489 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
494 clocks = <&cpg CPG_MOD 490 clocks = <&cpg CPG_MOD 929>;
495 power-domains = <&sysc 491 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
496 resets = <&cpg 929>; 492 resets = <&cpg 929>;
497 dmas = <&dmac1 0x95>, 493 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
498 <&dmac2 0x95>, 494 <&dmac2 0x95>, <&dmac2 0x94>;
499 dma-names = "tx", "rx" 495 dma-names = "tx", "rx", "tx", "rx";
500 i2c-scl-internal-delay 496 i2c-scl-internal-delay-ns = <6>;
501 status = "disabled"; 497 status = "disabled";
502 }; 498 };
503 499
504 i2c3: i2c@e66d0000 { 500 i2c3: i2c@e66d0000 {
505 #address-cells = <1>; 501 #address-cells = <1>;
506 #size-cells = <0>; 502 #size-cells = <0>;
507 compatible = "renesas, 503 compatible = "renesas,i2c-r8a774c0",
508 "renesas, 504 "renesas,rcar-gen3-i2c";
509 reg = <0 0xe66d0000 0 505 reg = <0 0xe66d0000 0 0x40>;
510 interrupts = <GIC_SPI 506 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
511 clocks = <&cpg CPG_MOD 507 clocks = <&cpg CPG_MOD 928>;
512 power-domains = <&sysc 508 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
513 resets = <&cpg 928>; 509 resets = <&cpg 928>;
514 dmas = <&dmac0 0x97>, 510 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
515 dma-names = "tx", "rx" 511 dma-names = "tx", "rx";
516 i2c-scl-internal-delay 512 i2c-scl-internal-delay-ns = <110>;
517 status = "disabled"; 513 status = "disabled";
518 }; 514 };
519 515
520 i2c4: i2c@e66d8000 { 516 i2c4: i2c@e66d8000 {
521 #address-cells = <1>; 517 #address-cells = <1>;
522 #size-cells = <0>; 518 #size-cells = <0>;
523 compatible = "renesas, 519 compatible = "renesas,i2c-r8a774c0",
524 "renesas, 520 "renesas,rcar-gen3-i2c";
525 reg = <0 0xe66d8000 0 521 reg = <0 0xe66d8000 0 0x40>;
526 interrupts = <GIC_SPI 522 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
527 clocks = <&cpg CPG_MOD 523 clocks = <&cpg CPG_MOD 927>;
528 power-domains = <&sysc 524 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
529 resets = <&cpg 927>; 525 resets = <&cpg 927>;
530 dmas = <&dmac0 0x99>, 526 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
531 dma-names = "tx", "rx" 527 dma-names = "tx", "rx";
532 i2c-scl-internal-delay 528 i2c-scl-internal-delay-ns = <6>;
533 status = "disabled"; 529 status = "disabled";
534 }; 530 };
535 531
536 i2c5: i2c@e66e0000 { 532 i2c5: i2c@e66e0000 {
537 #address-cells = <1>; 533 #address-cells = <1>;
538 #size-cells = <0>; 534 #size-cells = <0>;
539 compatible = "renesas, 535 compatible = "renesas,i2c-r8a774c0",
540 "renesas, 536 "renesas,rcar-gen3-i2c";
541 reg = <0 0xe66e0000 0 537 reg = <0 0xe66e0000 0 0x40>;
542 interrupts = <GIC_SPI 538 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
543 clocks = <&cpg CPG_MOD 539 clocks = <&cpg CPG_MOD 919>;
544 power-domains = <&sysc 540 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
545 resets = <&cpg 919>; 541 resets = <&cpg 919>;
546 dmas = <&dmac0 0x9b>, 542 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
547 dma-names = "tx", "rx" 543 dma-names = "tx", "rx";
548 i2c-scl-internal-delay 544 i2c-scl-internal-delay-ns = <6>;
549 status = "disabled"; 545 status = "disabled";
550 }; 546 };
551 547
552 i2c6: i2c@e66e8000 { 548 i2c6: i2c@e66e8000 {
553 #address-cells = <1>; 549 #address-cells = <1>;
554 #size-cells = <0>; 550 #size-cells = <0>;
555 compatible = "renesas, 551 compatible = "renesas,i2c-r8a774c0",
556 "renesas, 552 "renesas,rcar-gen3-i2c";
557 reg = <0 0xe66e8000 0 553 reg = <0 0xe66e8000 0 0x40>;
558 interrupts = <GIC_SPI 554 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
559 clocks = <&cpg CPG_MOD 555 clocks = <&cpg CPG_MOD 918>;
560 power-domains = <&sysc 556 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
561 resets = <&cpg 918>; 557 resets = <&cpg 918>;
562 dmas = <&dmac0 0x9d>, 558 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
563 dma-names = "tx", "rx" 559 dma-names = "tx", "rx";
564 i2c-scl-internal-delay 560 i2c-scl-internal-delay-ns = <6>;
565 status = "disabled"; 561 status = "disabled";
566 }; 562 };
567 563
568 i2c7: i2c@e6690000 { 564 i2c7: i2c@e6690000 {
569 #address-cells = <1>; 565 #address-cells = <1>;
570 #size-cells = <0>; 566 #size-cells = <0>;
571 compatible = "renesas, 567 compatible = "renesas,i2c-r8a774c0",
572 "renesas, 568 "renesas,rcar-gen3-i2c";
573 reg = <0 0xe6690000 0 569 reg = <0 0xe6690000 0 0x40>;
574 interrupts = <GIC_SPI 570 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
575 clocks = <&cpg CPG_MOD 571 clocks = <&cpg CPG_MOD 1003>;
576 power-domains = <&sysc 572 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
577 resets = <&cpg 1003>; 573 resets = <&cpg 1003>;
578 i2c-scl-internal-delay 574 i2c-scl-internal-delay-ns = <6>;
579 status = "disabled"; 575 status = "disabled";
580 }; 576 };
581 577
582 iic_pmic: i2c@e60b0000 { 578 iic_pmic: i2c@e60b0000 {
583 #address-cells = <1>; 579 #address-cells = <1>;
584 #size-cells = <0>; 580 #size-cells = <0>;
585 compatible = "renesas, 581 compatible = "renesas,iic-r8a774c0",
586 "renesas, 582 "renesas,rcar-gen3-iic",
587 "renesas, 583 "renesas,rmobile-iic";
588 reg = <0 0xe60b0000 0 584 reg = <0 0xe60b0000 0 0x425>;
589 interrupts = <GIC_SPI 585 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
590 clocks = <&cpg CPG_MOD 586 clocks = <&cpg CPG_MOD 926>;
591 power-domains = <&sysc 587 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
592 resets = <&cpg 926>; 588 resets = <&cpg 926>;
593 dmas = <&dmac0 0x11>, 589 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
594 dma-names = "tx", "rx" 590 dma-names = "tx", "rx";
595 status = "disabled"; 591 status = "disabled";
596 }; 592 };
597 593
598 hscif0: serial@e6540000 { 594 hscif0: serial@e6540000 {
599 compatible = "renesas, 595 compatible = "renesas,hscif-r8a774c0",
600 "renesas, 596 "renesas,rcar-gen3-hscif",
601 "renesas, 597 "renesas,hscif";
602 reg = <0 0xe6540000 0 598 reg = <0 0xe6540000 0 0x60>;
603 interrupts = <GIC_SPI 599 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
604 clocks = <&cpg CPG_MOD 600 clocks = <&cpg CPG_MOD 520>,
605 <&cpg CPG_COR 601 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
606 <&scif_clk>; 602 <&scif_clk>;
607 clock-names = "fck", " 603 clock-names = "fck", "brg_int", "scif_clk";
608 dmas = <&dmac1 0x31>, 604 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
609 <&dmac2 0x31>, 605 <&dmac2 0x31>, <&dmac2 0x30>;
610 dma-names = "tx", "rx" 606 dma-names = "tx", "rx", "tx", "rx";
611 power-domains = <&sysc 607 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
612 resets = <&cpg 520>; 608 resets = <&cpg 520>;
613 status = "disabled"; 609 status = "disabled";
614 }; 610 };
615 611
616 hscif1: serial@e6550000 { 612 hscif1: serial@e6550000 {
617 compatible = "renesas, 613 compatible = "renesas,hscif-r8a774c0",
618 "renesas, 614 "renesas,rcar-gen3-hscif",
619 "renesas, 615 "renesas,hscif";
620 reg = <0 0xe6550000 0 616 reg = <0 0xe6550000 0 0x60>;
621 interrupts = <GIC_SPI 617 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
622 clocks = <&cpg CPG_MOD 618 clocks = <&cpg CPG_MOD 519>,
623 <&cpg CPG_COR 619 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
624 <&scif_clk>; 620 <&scif_clk>;
625 clock-names = "fck", " 621 clock-names = "fck", "brg_int", "scif_clk";
626 dmas = <&dmac1 0x33>, 622 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
627 <&dmac2 0x33>, 623 <&dmac2 0x33>, <&dmac2 0x32>;
628 dma-names = "tx", "rx" 624 dma-names = "tx", "rx", "tx", "rx";
629 power-domains = <&sysc 625 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
630 resets = <&cpg 519>; 626 resets = <&cpg 519>;
631 status = "disabled"; 627 status = "disabled";
632 }; 628 };
633 629
634 hscif2: serial@e6560000 { 630 hscif2: serial@e6560000 {
635 compatible = "renesas, 631 compatible = "renesas,hscif-r8a774c0",
636 "renesas, 632 "renesas,rcar-gen3-hscif",
637 "renesas, 633 "renesas,hscif";
638 reg = <0 0xe6560000 0 634 reg = <0 0xe6560000 0 0x60>;
639 interrupts = <GIC_SPI 635 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
640 clocks = <&cpg CPG_MOD 636 clocks = <&cpg CPG_MOD 518>,
641 <&cpg CPG_COR 637 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
642 <&scif_clk>; 638 <&scif_clk>;
643 clock-names = "fck", " 639 clock-names = "fck", "brg_int", "scif_clk";
644 dmas = <&dmac1 0x35>, 640 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
645 <&dmac2 0x35>, 641 <&dmac2 0x35>, <&dmac2 0x34>;
646 dma-names = "tx", "rx" 642 dma-names = "tx", "rx", "tx", "rx";
647 power-domains = <&sysc 643 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
648 resets = <&cpg 518>; 644 resets = <&cpg 518>;
649 status = "disabled"; 645 status = "disabled";
650 }; 646 };
651 647
652 hscif3: serial@e66a0000 { 648 hscif3: serial@e66a0000 {
653 compatible = "renesas, 649 compatible = "renesas,hscif-r8a774c0",
654 "renesas, 650 "renesas,rcar-gen3-hscif",
655 "renesas, 651 "renesas,hscif";
656 reg = <0 0xe66a0000 0 652 reg = <0 0xe66a0000 0 0x60>;
657 interrupts = <GIC_SPI 653 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
658 clocks = <&cpg CPG_MOD 654 clocks = <&cpg CPG_MOD 517>,
659 <&cpg CPG_COR 655 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
660 <&scif_clk>; 656 <&scif_clk>;
661 clock-names = "fck", " 657 clock-names = "fck", "brg_int", "scif_clk";
662 dmas = <&dmac0 0x37>, 658 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
663 dma-names = "tx", "rx" 659 dma-names = "tx", "rx";
664 power-domains = <&sysc 660 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
665 resets = <&cpg 517>; 661 resets = <&cpg 517>;
666 status = "disabled"; 662 status = "disabled";
667 }; 663 };
668 664
669 hscif4: serial@e66b0000 { 665 hscif4: serial@e66b0000 {
670 compatible = "renesas, 666 compatible = "renesas,hscif-r8a774c0",
671 "renesas, 667 "renesas,rcar-gen3-hscif",
672 "renesas, 668 "renesas,hscif";
673 reg = <0 0xe66b0000 0 669 reg = <0 0xe66b0000 0 0x60>;
674 interrupts = <GIC_SPI 670 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
675 clocks = <&cpg CPG_MOD 671 clocks = <&cpg CPG_MOD 516>,
676 <&cpg CPG_COR 672 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
677 <&scif_clk>; 673 <&scif_clk>;
678 clock-names = "fck", " 674 clock-names = "fck", "brg_int", "scif_clk";
679 dmas = <&dmac0 0x39>, 675 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
680 dma-names = "tx", "rx" 676 dma-names = "tx", "rx";
681 power-domains = <&sysc 677 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
682 resets = <&cpg 516>; 678 resets = <&cpg 516>;
683 status = "disabled"; 679 status = "disabled";
684 }; 680 };
685 681
686 hsusb: usb@e6590000 { 682 hsusb: usb@e6590000 {
687 compatible = "renesas, 683 compatible = "renesas,usbhs-r8a774c0",
688 "renesas, 684 "renesas,rcar-gen3-usbhs";
689 reg = <0 0xe6590000 0 685 reg = <0 0xe6590000 0 0x200>;
690 interrupts = <GIC_SPI 686 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
691 clocks = <&cpg CPG_MOD 687 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
692 dmas = <&usb_dmac0 0>, 688 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
693 <&usb_dmac1 0>, 689 <&usb_dmac1 0>, <&usb_dmac1 1>;
694 dma-names = "ch0", "ch 690 dma-names = "ch0", "ch1", "ch2", "ch3";
695 renesas,buswait = <11> 691 renesas,buswait = <11>;
696 phys = <&usb2_phy0 3>; 692 phys = <&usb2_phy0 3>;
697 phy-names = "usb"; 693 phy-names = "usb";
698 power-domains = <&sysc 694 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
699 resets = <&cpg 704>, < 695 resets = <&cpg 704>, <&cpg 703>;
700 status = "disabled"; 696 status = "disabled";
701 }; 697 };
702 698
703 usb_dmac0: dma-controller@e65a 699 usb_dmac0: dma-controller@e65a0000 {
704 compatible = "renesas, 700 compatible = "renesas,r8a774c0-usb-dmac",
705 "renesas, 701 "renesas,usb-dmac";
706 reg = <0 0xe65a0000 0 702 reg = <0 0xe65a0000 0 0x100>;
707 interrupts = <GIC_SPI 703 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
708 <GIC_SPI 704 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
709 interrupt-names = "ch0 705 interrupt-names = "ch0", "ch1";
710 clocks = <&cpg CPG_MOD 706 clocks = <&cpg CPG_MOD 330>;
711 power-domains = <&sysc 707 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
712 resets = <&cpg 330>; 708 resets = <&cpg 330>;
713 #dma-cells = <1>; 709 #dma-cells = <1>;
714 dma-channels = <2>; 710 dma-channels = <2>;
715 }; 711 };
716 712
717 usb_dmac1: dma-controller@e65b 713 usb_dmac1: dma-controller@e65b0000 {
718 compatible = "renesas, 714 compatible = "renesas,r8a774c0-usb-dmac",
719 "renesas, 715 "renesas,usb-dmac";
720 reg = <0 0xe65b0000 0 716 reg = <0 0xe65b0000 0 0x100>;
721 interrupts = <GIC_SPI 717 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
722 <GIC_SPI 718 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
723 interrupt-names = "ch0 719 interrupt-names = "ch0", "ch1";
724 clocks = <&cpg CPG_MOD 720 clocks = <&cpg CPG_MOD 331>;
725 power-domains = <&sysc 721 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
726 resets = <&cpg 331>; 722 resets = <&cpg 331>;
727 #dma-cells = <1>; 723 #dma-cells = <1>;
728 dma-channels = <2>; 724 dma-channels = <2>;
729 }; 725 };
730 726
731 dmac0: dma-controller@e6700000 727 dmac0: dma-controller@e6700000 {
732 compatible = "renesas, 728 compatible = "renesas,dmac-r8a774c0",
733 "renesas, 729 "renesas,rcar-dmac";
734 reg = <0 0xe6700000 0 730 reg = <0 0xe6700000 0 0x10000>;
735 interrupts = <GIC_SPI 731 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
736 <GIC_SPI 732 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
737 <GIC_SPI 733 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
738 <GIC_SPI 734 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
739 <GIC_SPI 735 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
740 <GIC_SPI 736 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
741 <GIC_SPI 737 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
742 <GIC_SPI 738 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
743 <GIC_SPI 739 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
744 <GIC_SPI 740 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
745 <GIC_SPI 741 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
746 <GIC_SPI 742 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
747 <GIC_SPI 743 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
748 <GIC_SPI 744 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
749 <GIC_SPI 745 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
750 <GIC_SPI 746 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
751 <GIC_SPI 747 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
752 interrupt-names = "err 748 interrupt-names = "error",
753 "ch0", 749 "ch0", "ch1", "ch2", "ch3",
754 "ch4", 750 "ch4", "ch5", "ch6", "ch7",
755 "ch8", 751 "ch8", "ch9", "ch10", "ch11",
756 "ch12" 752 "ch12", "ch13", "ch14", "ch15";
757 clocks = <&cpg CPG_MOD 753 clocks = <&cpg CPG_MOD 219>;
758 clock-names = "fck"; 754 clock-names = "fck";
759 power-domains = <&sysc 755 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
760 resets = <&cpg 219>; 756 resets = <&cpg 219>;
761 #dma-cells = <1>; 757 #dma-cells = <1>;
762 dma-channels = <16>; 758 dma-channels = <16>;
763 iommus = <&ipmmu_ds0 0 759 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
764 <&ipmmu_ds0 2>, 760 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
765 <&ipmmu_ds0 4>, 761 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
766 <&ipmmu_ds0 6>, 762 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
767 <&ipmmu_ds0 8>, 763 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
768 <&ipmmu_ds0 10> 764 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
769 <&ipmmu_ds0 12> 765 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
770 <&ipmmu_ds0 14> 766 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
771 }; 767 };
772 768
773 dmac1: dma-controller@e7300000 769 dmac1: dma-controller@e7300000 {
774 compatible = "renesas, 770 compatible = "renesas,dmac-r8a774c0",
775 "renesas, 771 "renesas,rcar-dmac";
776 reg = <0 0xe7300000 0 772 reg = <0 0xe7300000 0 0x10000>;
777 interrupts = <GIC_SPI 773 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
778 <GIC_SPI 774 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
779 <GIC_SPI 775 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
780 <GIC_SPI 776 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
781 <GIC_SPI 777 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
782 <GIC_SPI 778 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
783 <GIC_SPI 779 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
784 <GIC_SPI 780 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
785 <GIC_SPI 781 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
786 <GIC_SPI 782 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
787 <GIC_SPI 783 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
788 <GIC_SPI 784 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
789 <GIC_SPI 785 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
790 <GIC_SPI 786 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
791 <GIC_SPI 787 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
792 <GIC_SPI 788 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
793 <GIC_SPI 789 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
794 interrupt-names = "err 790 interrupt-names = "error",
795 "ch0", 791 "ch0", "ch1", "ch2", "ch3",
796 "ch4", 792 "ch4", "ch5", "ch6", "ch7",
797 "ch8", 793 "ch8", "ch9", "ch10", "ch11",
798 "ch12" 794 "ch12", "ch13", "ch14", "ch15";
799 clocks = <&cpg CPG_MOD 795 clocks = <&cpg CPG_MOD 218>;
800 clock-names = "fck"; 796 clock-names = "fck";
801 power-domains = <&sysc 797 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
802 resets = <&cpg 218>; 798 resets = <&cpg 218>;
803 #dma-cells = <1>; 799 #dma-cells = <1>;
804 dma-channels = <16>; 800 dma-channels = <16>;
805 iommus = <&ipmmu_ds1 0 801 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
806 <&ipmmu_ds1 2>, 802 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
807 <&ipmmu_ds1 4>, 803 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
808 <&ipmmu_ds1 6>, 804 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
809 <&ipmmu_ds1 8>, 805 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
810 <&ipmmu_ds1 10> 806 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
811 <&ipmmu_ds1 12> 807 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
812 <&ipmmu_ds1 14> 808 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
813 }; 809 };
814 810
815 dmac2: dma-controller@e7310000 811 dmac2: dma-controller@e7310000 {
816 compatible = "renesas, 812 compatible = "renesas,dmac-r8a774c0",
817 "renesas, 813 "renesas,rcar-dmac";
818 reg = <0 0xe7310000 0 814 reg = <0 0xe7310000 0 0x10000>;
819 interrupts = <GIC_SPI 815 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
820 <GIC_SPI 816 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
821 <GIC_SPI 817 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
822 <GIC_SPI 818 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
823 <GIC_SPI 819 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
824 <GIC_SPI 820 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
825 <GIC_SPI 821 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
826 <GIC_SPI 822 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
827 <GIC_SPI 823 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
828 <GIC_SPI 824 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
829 <GIC_SPI 825 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
830 <GIC_SPI 826 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
831 <GIC_SPI 827 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
832 <GIC_SPI 828 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
833 <GIC_SPI 829 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
834 <GIC_SPI 830 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
835 <GIC_SPI 831 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
836 interrupt-names = "err 832 interrupt-names = "error",
837 "ch0", 833 "ch0", "ch1", "ch2", "ch3",
838 "ch4", 834 "ch4", "ch5", "ch6", "ch7",
839 "ch8", 835 "ch8", "ch9", "ch10", "ch11",
840 "ch12" 836 "ch12", "ch13", "ch14", "ch15";
841 clocks = <&cpg CPG_MOD 837 clocks = <&cpg CPG_MOD 217>;
842 clock-names = "fck"; 838 clock-names = "fck";
843 power-domains = <&sysc 839 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
844 resets = <&cpg 217>; 840 resets = <&cpg 217>;
845 #dma-cells = <1>; 841 #dma-cells = <1>;
846 dma-channels = <16>; 842 dma-channels = <16>;
847 iommus = <&ipmmu_ds1 1 843 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
848 <&ipmmu_ds1 18> 844 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
849 <&ipmmu_ds1 20> 845 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
850 <&ipmmu_ds1 22> 846 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
851 <&ipmmu_ds1 24> 847 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
852 <&ipmmu_ds1 26> 848 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
853 <&ipmmu_ds1 28> 849 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
854 <&ipmmu_ds1 30> 850 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
855 }; 851 };
856 852
857 ipmmu_ds0: iommu@e6740000 { 853 ipmmu_ds0: iommu@e6740000 {
858 compatible = "renesas, 854 compatible = "renesas,ipmmu-r8a774c0";
859 reg = <0 0xe6740000 0 855 reg = <0 0xe6740000 0 0x1000>;
860 renesas,ipmmu-main = < 856 renesas,ipmmu-main = <&ipmmu_mm 0>;
861 power-domains = <&sysc 857 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
862 #iommu-cells = <1>; 858 #iommu-cells = <1>;
863 }; 859 };
864 860
865 ipmmu_ds1: iommu@e7740000 { 861 ipmmu_ds1: iommu@e7740000 {
866 compatible = "renesas, 862 compatible = "renesas,ipmmu-r8a774c0";
867 reg = <0 0xe7740000 0 863 reg = <0 0xe7740000 0 0x1000>;
868 renesas,ipmmu-main = < 864 renesas,ipmmu-main = <&ipmmu_mm 1>;
869 power-domains = <&sysc 865 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
870 #iommu-cells = <1>; 866 #iommu-cells = <1>;
871 }; 867 };
872 868
873 ipmmu_hc: iommu@e6570000 { 869 ipmmu_hc: iommu@e6570000 {
874 compatible = "renesas, 870 compatible = "renesas,ipmmu-r8a774c0";
875 reg = <0 0xe6570000 0 871 reg = <0 0xe6570000 0 0x1000>;
876 renesas,ipmmu-main = < 872 renesas,ipmmu-main = <&ipmmu_mm 2>;
877 power-domains = <&sysc 873 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
878 #iommu-cells = <1>; 874 #iommu-cells = <1>;
879 }; 875 };
880 876
881 ipmmu_mm: iommu@e67b0000 { 877 ipmmu_mm: iommu@e67b0000 {
882 compatible = "renesas, 878 compatible = "renesas,ipmmu-r8a774c0";
883 reg = <0 0xe67b0000 0 879 reg = <0 0xe67b0000 0 0x1000>;
884 interrupts = <GIC_SPI 880 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
885 <GIC_SPI 881 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
886 power-domains = <&sysc 882 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
887 #iommu-cells = <1>; 883 #iommu-cells = <1>;
888 }; 884 };
889 885
890 ipmmu_mp: iommu@ec670000 { 886 ipmmu_mp: iommu@ec670000 {
891 compatible = "renesas, 887 compatible = "renesas,ipmmu-r8a774c0";
892 reg = <0 0xec670000 0 888 reg = <0 0xec670000 0 0x1000>;
893 renesas,ipmmu-main = < 889 renesas,ipmmu-main = <&ipmmu_mm 4>;
894 power-domains = <&sysc 890 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
895 #iommu-cells = <1>; 891 #iommu-cells = <1>;
896 }; 892 };
897 893
898 ipmmu_pv0: iommu@fd800000 { 894 ipmmu_pv0: iommu@fd800000 {
899 compatible = "renesas, 895 compatible = "renesas,ipmmu-r8a774c0";
900 reg = <0 0xfd800000 0 896 reg = <0 0xfd800000 0 0x1000>;
901 renesas,ipmmu-main = < 897 renesas,ipmmu-main = <&ipmmu_mm 6>;
902 power-domains = <&sysc 898 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
903 #iommu-cells = <1>; 899 #iommu-cells = <1>;
904 }; 900 };
905 901
906 ipmmu_vc0: iommu@fe6b0000 { 902 ipmmu_vc0: iommu@fe6b0000 {
907 compatible = "renesas, 903 compatible = "renesas,ipmmu-r8a774c0";
908 reg = <0 0xfe6b0000 0 904 reg = <0 0xfe6b0000 0 0x1000>;
909 renesas,ipmmu-main = < 905 renesas,ipmmu-main = <&ipmmu_mm 12>;
910 power-domains = <&sysc 906 power-domains = <&sysc R8A774C0_PD_A3VC>;
911 #iommu-cells = <1>; 907 #iommu-cells = <1>;
912 }; 908 };
913 909
914 ipmmu_vi0: iommu@febd0000 { 910 ipmmu_vi0: iommu@febd0000 {
915 compatible = "renesas, 911 compatible = "renesas,ipmmu-r8a774c0";
916 reg = <0 0xfebd0000 0 912 reg = <0 0xfebd0000 0 0x1000>;
917 renesas,ipmmu-main = < 913 renesas,ipmmu-main = <&ipmmu_mm 14>;
918 power-domains = <&sysc 914 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
919 #iommu-cells = <1>; 915 #iommu-cells = <1>;
920 }; 916 };
921 917
922 ipmmu_vp0: iommu@fe990000 { 918 ipmmu_vp0: iommu@fe990000 {
923 compatible = "renesas, 919 compatible = "renesas,ipmmu-r8a774c0";
924 reg = <0 0xfe990000 0 920 reg = <0 0xfe990000 0 0x1000>;
925 renesas,ipmmu-main = < 921 renesas,ipmmu-main = <&ipmmu_mm 16>;
926 power-domains = <&sysc 922 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
927 #iommu-cells = <1>; 923 #iommu-cells = <1>;
928 }; 924 };
929 925
930 avb: ethernet@e6800000 { 926 avb: ethernet@e6800000 {
931 compatible = "renesas, 927 compatible = "renesas,etheravb-r8a774c0",
932 "renesas, 928 "renesas,etheravb-rcar-gen3";
933 reg = <0 0xe6800000 0 929 reg = <0 0xe6800000 0 0x800>;
934 interrupts = <GIC_SPI 930 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
935 <GIC_SPI 931 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
936 <GIC_SPI 932 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
937 <GIC_SPI 933 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
938 <GIC_SPI 934 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
939 <GIC_SPI 935 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
940 <GIC_SPI 936 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
941 <GIC_SPI 937 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
942 <GIC_SPI 938 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
943 <GIC_SPI 939 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
944 <GIC_SPI 940 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
945 <GIC_SPI 941 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
946 <GIC_SPI 942 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
947 <GIC_SPI 943 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
948 <GIC_SPI 944 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
949 <GIC_SPI 945 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
950 <GIC_SPI 946 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
951 <GIC_SPI 947 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
952 <GIC_SPI 948 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
953 <GIC_SPI 949 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
954 <GIC_SPI 950 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
955 <GIC_SPI 951 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
956 <GIC_SPI 952 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
957 <GIC_SPI 953 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
958 <GIC_SPI 954 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
959 interrupt-names = "ch0 955 interrupt-names = "ch0", "ch1", "ch2", "ch3",
960 "ch4 956 "ch4", "ch5", "ch6", "ch7",
961 "ch8 957 "ch8", "ch9", "ch10", "ch11",
962 "ch1 958 "ch12", "ch13", "ch14", "ch15",
963 "ch1 959 "ch16", "ch17", "ch18", "ch19",
964 "ch2 960 "ch20", "ch21", "ch22", "ch23",
965 "ch2 961 "ch24";
966 clocks = <&cpg CPG_MOD 962 clocks = <&cpg CPG_MOD 812>;
967 clock-names = "fck"; 963 clock-names = "fck";
968 power-domains = <&sysc 964 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
969 resets = <&cpg 812>; 965 resets = <&cpg 812>;
970 phy-mode = "rgmii"; 966 phy-mode = "rgmii";
971 rx-internal-delay-ps = 967 rx-internal-delay-ps = <0>;
972 iommus = <&ipmmu_ds0 1 968 iommus = <&ipmmu_ds0 16>;
973 #address-cells = <1>; 969 #address-cells = <1>;
974 #size-cells = <0>; 970 #size-cells = <0>;
975 status = "disabled"; 971 status = "disabled";
976 }; 972 };
977 973
978 can0: can@e6c30000 { 974 can0: can@e6c30000 {
979 compatible = "renesas, 975 compatible = "renesas,can-r8a774c0",
980 "renesas, 976 "renesas,rcar-gen3-can";
981 reg = <0 0xe6c30000 0 977 reg = <0 0xe6c30000 0 0x1000>;
982 interrupts = <GIC_SPI 978 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
983 clocks = <&cpg CPG_MOD 979 clocks = <&cpg CPG_MOD 916>,
984 <&cpg CPG_COR 980 <&cpg CPG_CORE R8A774C0_CLK_CANFD>,
985 <&can_clk>; 981 <&can_clk>;
986 clock-names = "clkp1", 982 clock-names = "clkp1", "clkp2", "can_clk";
987 assigned-clocks = <&cp 983 assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>;
988 assigned-clock-rates = 984 assigned-clock-rates = <40000000>;
989 power-domains = <&sysc 985 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
990 resets = <&cpg 916>; 986 resets = <&cpg 916>;
991 status = "disabled"; 987 status = "disabled";
992 }; 988 };
993 989
994 can1: can@e6c38000 { 990 can1: can@e6c38000 {
995 compatible = "renesas, 991 compatible = "renesas,can-r8a774c0",
996 "renesas, 992 "renesas,rcar-gen3-can";
997 reg = <0 0xe6c38000 0 993 reg = <0 0xe6c38000 0 0x1000>;
998 interrupts = <GIC_SPI 994 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
999 clocks = <&cpg CPG_MOD 995 clocks = <&cpg CPG_MOD 915>,
1000 <&cpg CPG_CO 996 <&cpg CPG_CORE R8A774C0_CLK_CANFD>,
1001 <&can_clk>; 997 <&can_clk>;
1002 clock-names = "clkp1" 998 clock-names = "clkp1", "clkp2", "can_clk";
1003 assigned-clocks = <&c 999 assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>;
1004 assigned-clock-rates 1000 assigned-clock-rates = <40000000>;
1005 power-domains = <&sys 1001 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1006 resets = <&cpg 915>; 1002 resets = <&cpg 915>;
1007 status = "disabled"; 1003 status = "disabled";
1008 }; 1004 };
1009 1005
1010 canfd: can@e66c0000 { 1006 canfd: can@e66c0000 {
1011 compatible = "renesas 1007 compatible = "renesas,r8a774c0-canfd",
1012 "renesas 1008 "renesas,rcar-gen3-canfd";
1013 reg = <0 0xe66c0000 0 1009 reg = <0 0xe66c0000 0 0x8000>;
1014 interrupts = <GIC_SPI 1010 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
1015 <GIC_SPI 1011 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1016 interrupt-names = "ch 1012 interrupt-names = "ch_int", "g_int";
1017 clocks = <&cpg CPG_MO 1013 clocks = <&cpg CPG_MOD 914>,
1018 <&cpg CPG_CO 1014 <&cpg CPG_CORE R8A774C0_CLK_CANFD>,
1019 <&can_clk>; 1015 <&can_clk>;
1020 clock-names = "fck", 1016 clock-names = "fck", "canfd", "can_clk";
1021 assigned-clocks = <&c 1017 assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>;
1022 assigned-clock-rates 1018 assigned-clock-rates = <40000000>;
1023 power-domains = <&sys 1019 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1024 resets = <&cpg 914>; 1020 resets = <&cpg 914>;
1025 status = "disabled"; 1021 status = "disabled";
1026 1022
1027 channel0 { 1023 channel0 {
1028 status = "dis 1024 status = "disabled";
1029 }; 1025 };
1030 1026
1031 channel1 { 1027 channel1 {
1032 status = "dis 1028 status = "disabled";
1033 }; 1029 };
1034 }; 1030 };
1035 1031
1036 pwm0: pwm@e6e30000 { 1032 pwm0: pwm@e6e30000 {
1037 compatible = "renesas 1033 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1038 reg = <0 0xe6e30000 0 1034 reg = <0 0xe6e30000 0 0x8>;
1039 clocks = <&cpg CPG_MO 1035 clocks = <&cpg CPG_MOD 523>;
1040 power-domains = <&sys 1036 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1041 resets = <&cpg 523>; 1037 resets = <&cpg 523>;
1042 #pwm-cells = <2>; 1038 #pwm-cells = <2>;
1043 status = "disabled"; 1039 status = "disabled";
1044 }; 1040 };
1045 1041
1046 pwm1: pwm@e6e31000 { 1042 pwm1: pwm@e6e31000 {
1047 compatible = "renesas 1043 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1048 reg = <0 0xe6e31000 0 1044 reg = <0 0xe6e31000 0 0x8>;
1049 clocks = <&cpg CPG_MO 1045 clocks = <&cpg CPG_MOD 523>;
1050 power-domains = <&sys 1046 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1051 resets = <&cpg 523>; 1047 resets = <&cpg 523>;
1052 #pwm-cells = <2>; 1048 #pwm-cells = <2>;
1053 status = "disabled"; 1049 status = "disabled";
1054 }; 1050 };
1055 1051
1056 pwm2: pwm@e6e32000 { 1052 pwm2: pwm@e6e32000 {
1057 compatible = "renesas 1053 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1058 reg = <0 0xe6e32000 0 1054 reg = <0 0xe6e32000 0 0x8>;
1059 clocks = <&cpg CPG_MO 1055 clocks = <&cpg CPG_MOD 523>;
1060 power-domains = <&sys 1056 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1061 resets = <&cpg 523>; 1057 resets = <&cpg 523>;
1062 #pwm-cells = <2>; 1058 #pwm-cells = <2>;
1063 status = "disabled"; 1059 status = "disabled";
1064 }; 1060 };
1065 1061
1066 pwm3: pwm@e6e33000 { 1062 pwm3: pwm@e6e33000 {
1067 compatible = "renesas 1063 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1068 reg = <0 0xe6e33000 0 1064 reg = <0 0xe6e33000 0 0x8>;
1069 clocks = <&cpg CPG_MO 1065 clocks = <&cpg CPG_MOD 523>;
1070 power-domains = <&sys 1066 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1071 resets = <&cpg 523>; 1067 resets = <&cpg 523>;
1072 #pwm-cells = <2>; 1068 #pwm-cells = <2>;
1073 status = "disabled"; 1069 status = "disabled";
1074 }; 1070 };
1075 1071
1076 pwm4: pwm@e6e34000 { 1072 pwm4: pwm@e6e34000 {
1077 compatible = "renesas 1073 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1078 reg = <0 0xe6e34000 0 1074 reg = <0 0xe6e34000 0 0x8>;
1079 clocks = <&cpg CPG_MO 1075 clocks = <&cpg CPG_MOD 523>;
1080 power-domains = <&sys 1076 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1081 resets = <&cpg 523>; 1077 resets = <&cpg 523>;
1082 #pwm-cells = <2>; 1078 #pwm-cells = <2>;
1083 status = "disabled"; 1079 status = "disabled";
1084 }; 1080 };
1085 1081
1086 pwm5: pwm@e6e35000 { 1082 pwm5: pwm@e6e35000 {
1087 compatible = "renesas 1083 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1088 reg = <0 0xe6e35000 0 1084 reg = <0 0xe6e35000 0 0x8>;
1089 clocks = <&cpg CPG_MO 1085 clocks = <&cpg CPG_MOD 523>;
1090 power-domains = <&sys 1086 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1091 resets = <&cpg 523>; 1087 resets = <&cpg 523>;
1092 #pwm-cells = <2>; 1088 #pwm-cells = <2>;
1093 status = "disabled"; 1089 status = "disabled";
1094 }; 1090 };
1095 1091
1096 pwm6: pwm@e6e36000 { 1092 pwm6: pwm@e6e36000 {
1097 compatible = "renesas 1093 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1098 reg = <0 0xe6e36000 0 1094 reg = <0 0xe6e36000 0 0x8>;
1099 clocks = <&cpg CPG_MO 1095 clocks = <&cpg CPG_MOD 523>;
1100 power-domains = <&sys 1096 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1101 resets = <&cpg 523>; 1097 resets = <&cpg 523>;
1102 #pwm-cells = <2>; 1098 #pwm-cells = <2>;
1103 status = "disabled"; 1099 status = "disabled";
1104 }; 1100 };
1105 1101
1106 scif0: serial@e6e60000 { 1102 scif0: serial@e6e60000 {
1107 compatible = "renesas 1103 compatible = "renesas,scif-r8a774c0",
1108 "renesas 1104 "renesas,rcar-gen3-scif", "renesas,scif";
1109 reg = <0 0xe6e60000 0 1105 reg = <0 0xe6e60000 0 64>;
1110 interrupts = <GIC_SPI 1106 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
1111 clocks = <&cpg CPG_MO 1107 clocks = <&cpg CPG_MOD 207>,
1112 <&cpg CPG_CO 1108 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
1113 <&scif_clk>; 1109 <&scif_clk>;
1114 clock-names = "fck", 1110 clock-names = "fck", "brg_int", "scif_clk";
1115 dmas = <&dmac1 0x51>, 1111 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1116 <&dmac2 0x51>, 1112 <&dmac2 0x51>, <&dmac2 0x50>;
1117 dma-names = "tx", "rx 1113 dma-names = "tx", "rx", "tx", "rx";
1118 power-domains = <&sys 1114 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1119 resets = <&cpg 207>; 1115 resets = <&cpg 207>;
1120 status = "disabled"; 1116 status = "disabled";
1121 }; 1117 };
1122 1118
1123 scif1: serial@e6e68000 { 1119 scif1: serial@e6e68000 {
1124 compatible = "renesas 1120 compatible = "renesas,scif-r8a774c0",
1125 "renesas 1121 "renesas,rcar-gen3-scif", "renesas,scif";
1126 reg = <0 0xe6e68000 0 1122 reg = <0 0xe6e68000 0 64>;
1127 interrupts = <GIC_SPI 1123 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
1128 clocks = <&cpg CPG_MO 1124 clocks = <&cpg CPG_MOD 206>,
1129 <&cpg CPG_CO 1125 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
1130 <&scif_clk>; 1126 <&scif_clk>;
1131 clock-names = "fck", 1127 clock-names = "fck", "brg_int", "scif_clk";
1132 dmas = <&dmac1 0x53>, 1128 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1133 <&dmac2 0x53>, 1129 <&dmac2 0x53>, <&dmac2 0x52>;
1134 dma-names = "tx", "rx 1130 dma-names = "tx", "rx", "tx", "rx";
1135 power-domains = <&sys 1131 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1136 resets = <&cpg 206>; 1132 resets = <&cpg 206>;
1137 status = "disabled"; 1133 status = "disabled";
1138 }; 1134 };
1139 1135
1140 scif2: serial@e6e88000 { 1136 scif2: serial@e6e88000 {
1141 compatible = "renesas 1137 compatible = "renesas,scif-r8a774c0",
1142 "renesas 1138 "renesas,rcar-gen3-scif", "renesas,scif";
1143 reg = <0 0xe6e88000 0 1139 reg = <0 0xe6e88000 0 64>;
1144 interrupts = <GIC_SPI 1140 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
1145 clocks = <&cpg CPG_MO 1141 clocks = <&cpg CPG_MOD 310>,
1146 <&cpg CPG_CO 1142 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
1147 <&scif_clk>; 1143 <&scif_clk>;
1148 clock-names = "fck", 1144 clock-names = "fck", "brg_int", "scif_clk";
1149 dmas = <&dmac1 0x13>, 1145 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1150 <&dmac2 0x13>, 1146 <&dmac2 0x13>, <&dmac2 0x12>;
1151 dma-names = "tx", "rx 1147 dma-names = "tx", "rx", "tx", "rx";
1152 power-domains = <&sys 1148 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1153 resets = <&cpg 310>; 1149 resets = <&cpg 310>;
1154 status = "disabled"; 1150 status = "disabled";
1155 }; 1151 };
1156 1152
1157 scif3: serial@e6c50000 { 1153 scif3: serial@e6c50000 {
1158 compatible = "renesas 1154 compatible = "renesas,scif-r8a774c0",
1159 "renesas 1155 "renesas,rcar-gen3-scif", "renesas,scif";
1160 reg = <0 0xe6c50000 0 1156 reg = <0 0xe6c50000 0 64>;
1161 interrupts = <GIC_SPI 1157 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1162 clocks = <&cpg CPG_MO 1158 clocks = <&cpg CPG_MOD 204>,
1163 <&cpg CPG_CO 1159 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
1164 <&scif_clk>; 1160 <&scif_clk>;
1165 clock-names = "fck", 1161 clock-names = "fck", "brg_int", "scif_clk";
1166 dmas = <&dmac0 0x57>, 1162 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1167 dma-names = "tx", "rx 1163 dma-names = "tx", "rx";
1168 power-domains = <&sys 1164 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1169 resets = <&cpg 204>; 1165 resets = <&cpg 204>;
1170 status = "disabled"; 1166 status = "disabled";
1171 }; 1167 };
1172 1168
1173 scif4: serial@e6c40000 { 1169 scif4: serial@e6c40000 {
1174 compatible = "renesas 1170 compatible = "renesas,scif-r8a774c0",
1175 "renesas 1171 "renesas,rcar-gen3-scif", "renesas,scif";
1176 reg = <0 0xe6c40000 0 1172 reg = <0 0xe6c40000 0 64>;
1177 interrupts = <GIC_SPI 1173 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1178 clocks = <&cpg CPG_MO 1174 clocks = <&cpg CPG_MOD 203>,
1179 <&cpg CPG_CO 1175 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
1180 <&scif_clk>; 1176 <&scif_clk>;
1181 clock-names = "fck", 1177 clock-names = "fck", "brg_int", "scif_clk";
1182 dmas = <&dmac0 0x59>, 1178 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1183 dma-names = "tx", "rx 1179 dma-names = "tx", "rx";
1184 power-domains = <&sys 1180 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1185 resets = <&cpg 203>; 1181 resets = <&cpg 203>;
1186 status = "disabled"; 1182 status = "disabled";
1187 }; 1183 };
1188 1184
1189 scif5: serial@e6f30000 { 1185 scif5: serial@e6f30000 {
1190 compatible = "renesas 1186 compatible = "renesas,scif-r8a774c0",
1191 "renesas 1187 "renesas,rcar-gen3-scif", "renesas,scif";
1192 reg = <0 0xe6f30000 0 1188 reg = <0 0xe6f30000 0 64>;
1193 interrupts = <GIC_SPI 1189 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1194 clocks = <&cpg CPG_MO 1190 clocks = <&cpg CPG_MOD 202>,
1195 <&cpg CPG_CO 1191 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
1196 <&scif_clk>; 1192 <&scif_clk>;
1197 clock-names = "fck", 1193 clock-names = "fck", "brg_int", "scif_clk";
1198 dmas = <&dmac0 0x5b>, 1194 dmas = <&dmac0 0x5b>, <&dmac0 0x5a>;
1199 dma-names = "tx", "rx 1195 dma-names = "tx", "rx";
1200 power-domains = <&sys 1196 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1201 resets = <&cpg 202>; 1197 resets = <&cpg 202>;
1202 status = "disabled"; 1198 status = "disabled";
1203 }; 1199 };
1204 1200
1205 msiof0: spi@e6e90000 { 1201 msiof0: spi@e6e90000 {
1206 compatible = "renesas 1202 compatible = "renesas,msiof-r8a774c0",
1207 "renesas 1203 "renesas,rcar-gen3-msiof";
1208 reg = <0 0xe6e90000 0 1204 reg = <0 0xe6e90000 0 0x0064>;
1209 interrupts = <GIC_SPI 1205 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1210 clocks = <&cpg CPG_MO 1206 clocks = <&cpg CPG_MOD 211>;
1211 dmas = <&dmac1 0x41>, 1207 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1212 <&dmac2 0x41>, 1208 <&dmac2 0x41>, <&dmac2 0x40>;
1213 dma-names = "tx", "rx 1209 dma-names = "tx", "rx", "tx", "rx";
1214 power-domains = <&sys 1210 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1215 resets = <&cpg 211>; 1211 resets = <&cpg 211>;
1216 #address-cells = <1>; 1212 #address-cells = <1>;
1217 #size-cells = <0>; 1213 #size-cells = <0>;
1218 status = "disabled"; 1214 status = "disabled";
1219 }; 1215 };
1220 1216
1221 msiof1: spi@e6ea0000 { 1217 msiof1: spi@e6ea0000 {
1222 compatible = "renesas 1218 compatible = "renesas,msiof-r8a774c0",
1223 "renesas 1219 "renesas,rcar-gen3-msiof";
1224 reg = <0 0xe6ea0000 0 1220 reg = <0 0xe6ea0000 0 0x0064>;
1225 interrupts = <GIC_SPI 1221 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1226 clocks = <&cpg CPG_MO 1222 clocks = <&cpg CPG_MOD 210>;
1227 dmas = <&dmac0 0x43>, 1223 dmas = <&dmac0 0x43>, <&dmac0 0x42>;
1228 dma-names = "tx", "rx 1224 dma-names = "tx", "rx";
1229 power-domains = <&sys 1225 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1230 resets = <&cpg 210>; 1226 resets = <&cpg 210>;
1231 #address-cells = <1>; 1227 #address-cells = <1>;
1232 #size-cells = <0>; 1228 #size-cells = <0>;
1233 status = "disabled"; 1229 status = "disabled";
1234 }; 1230 };
1235 1231
1236 msiof2: spi@e6c00000 { 1232 msiof2: spi@e6c00000 {
1237 compatible = "renesas 1233 compatible = "renesas,msiof-r8a774c0",
1238 "renesas 1234 "renesas,rcar-gen3-msiof";
1239 reg = <0 0xe6c00000 0 1235 reg = <0 0xe6c00000 0 0x0064>;
1240 interrupts = <GIC_SPI 1236 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1241 clocks = <&cpg CPG_MO 1237 clocks = <&cpg CPG_MOD 209>;
1242 dmas = <&dmac0 0x45>, 1238 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1243 dma-names = "tx", "rx 1239 dma-names = "tx", "rx";
1244 power-domains = <&sys 1240 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1245 resets = <&cpg 209>; 1241 resets = <&cpg 209>;
1246 #address-cells = <1>; 1242 #address-cells = <1>;
1247 #size-cells = <0>; 1243 #size-cells = <0>;
1248 status = "disabled"; 1244 status = "disabled";
1249 }; 1245 };
1250 1246
1251 msiof3: spi@e6c10000 { 1247 msiof3: spi@e6c10000 {
1252 compatible = "renesas 1248 compatible = "renesas,msiof-r8a774c0",
1253 "renesas 1249 "renesas,rcar-gen3-msiof";
1254 reg = <0 0xe6c10000 0 1250 reg = <0 0xe6c10000 0 0x0064>;
1255 interrupts = <GIC_SPI 1251 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1256 clocks = <&cpg CPG_MO 1252 clocks = <&cpg CPG_MOD 208>;
1257 dmas = <&dmac0 0x47>, 1253 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1258 dma-names = "tx", "rx 1254 dma-names = "tx", "rx";
1259 power-domains = <&sys 1255 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1260 resets = <&cpg 208>; 1256 resets = <&cpg 208>;
1261 #address-cells = <1>; 1257 #address-cells = <1>;
1262 #size-cells = <0>; 1258 #size-cells = <0>;
1263 status = "disabled"; 1259 status = "disabled";
1264 }; 1260 };
1265 1261
1266 vin4: video@e6ef4000 { 1262 vin4: video@e6ef4000 {
1267 compatible = "renesas 1263 compatible = "renesas,vin-r8a774c0";
1268 reg = <0 0xe6ef4000 0 1264 reg = <0 0xe6ef4000 0 0x1000>;
1269 interrupts = <GIC_SPI 1265 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
1270 clocks = <&cpg CPG_MO 1266 clocks = <&cpg CPG_MOD 807>;
1271 power-domains = <&sys 1267 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1272 resets = <&cpg 807>; 1268 resets = <&cpg 807>;
1273 renesas,id = <4>; 1269 renesas,id = <4>;
1274 status = "disabled"; 1270 status = "disabled";
1275 1271
1276 ports { 1272 ports {
1277 #address-cell 1273 #address-cells = <1>;
1278 #size-cells = 1274 #size-cells = <0>;
1279 1275
1280 port@1 { 1276 port@1 {
1281 #addr 1277 #address-cells = <1>;
1282 #size 1278 #size-cells = <0>;
1283 1279
1284 reg = 1280 reg = <1>;
1285 1281
1286 vin4c 1282 vin4csi40: endpoint@2 {
1287 1283 reg = <2>;
1288 1284 remote-endpoint = <&csi40vin4>;
1289 }; 1285 };
1290 }; 1286 };
1291 }; 1287 };
1292 }; 1288 };
1293 1289
1294 vin5: video@e6ef5000 { 1290 vin5: video@e6ef5000 {
1295 compatible = "renesas 1291 compatible = "renesas,vin-r8a774c0";
1296 reg = <0 0xe6ef5000 0 1292 reg = <0 0xe6ef5000 0 0x1000>;
1297 interrupts = <GIC_SPI 1293 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
1298 clocks = <&cpg CPG_MO 1294 clocks = <&cpg CPG_MOD 806>;
1299 power-domains = <&sys 1295 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1300 resets = <&cpg 806>; 1296 resets = <&cpg 806>;
1301 renesas,id = <5>; 1297 renesas,id = <5>;
1302 status = "disabled"; 1298 status = "disabled";
1303 1299
1304 ports { 1300 ports {
1305 #address-cell 1301 #address-cells = <1>;
1306 #size-cells = 1302 #size-cells = <0>;
1307 1303
1308 port@1 { 1304 port@1 {
1309 #addr 1305 #address-cells = <1>;
1310 #size 1306 #size-cells = <0>;
1311 1307
1312 reg = 1308 reg = <1>;
1313 1309
1314 vin5c 1310 vin5csi40: endpoint@2 {
1315 1311 reg = <2>;
1316 1312 remote-endpoint = <&csi40vin5>;
1317 }; 1313 };
1318 }; 1314 };
1319 }; 1315 };
1320 }; 1316 };
1321 1317
1322 rcar_sound: sound@ec500000 { 1318 rcar_sound: sound@ec500000 {
1323 /* 1319 /*
1324 * #sound-dai-cells i !! 1320 * #sound-dai-cells is required
1325 * 1321 *
1326 * Single DAI : #soun 1322 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1327 * Multi DAI : #soun 1323 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1328 */ 1324 */
1329 /* 1325 /*
1330 * #clock-cells is re 1326 * #clock-cells is required for audio_clkout0/1/2/3
1331 * 1327 *
1332 * clkout : #cl 1328 * clkout : #clock-cells = <0>; <&rcar_sound>;
1333 * clkout0/1/2/3: #cl 1329 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
1334 */ 1330 */
1335 compatible = "renesas 1331 compatible = "renesas,rcar_sound-r8a774c0",
1336 "renesas 1332 "renesas,rcar_sound-gen3";
1337 reg = <0 0xec500000 0 1333 reg = <0 0xec500000 0 0x1000>, /* SCU */
1338 <0 0xec5a0000 0 1334 <0 0xec5a0000 0 0x100>, /* ADG */
1339 <0 0xec540000 0 1335 <0 0xec540000 0 0x1000>, /* SSIU */
1340 <0 0xec541000 0 1336 <0 0xec541000 0 0x280>, /* SSI */
1341 <0 0xec760000 0 1337 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
1342 reg-names = "scu", "a 1338 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1343 1339
1344 clocks = <&cpg CPG_MO 1340 clocks = <&cpg CPG_MOD 1005>,
1345 <&cpg CPG_MO 1341 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
1346 <&cpg CPG_MO 1342 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
1347 <&cpg CPG_MO 1343 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
1348 <&cpg CPG_MO 1344 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
1349 <&cpg CPG_MO 1345 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
1350 <&cpg CPG_MO 1346 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
1351 <&cpg CPG_MO 1347 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
1352 <&cpg CPG_MO 1348 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
1353 <&cpg CPG_MO 1349 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
1354 <&cpg CPG_MO 1350 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
1355 <&cpg CPG_MO 1351 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1356 <&cpg CPG_MO 1352 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1357 <&cpg CPG_MO 1353 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
1358 <&audio_clk_ 1354 <&audio_clk_a>, <&audio_clk_b>,
1359 <&audio_clk_ 1355 <&audio_clk_c>,
1360 <&cpg CPG_MO !! 1356 <&cpg CPG_CORE R8A774C0_CLK_ZA2>;
1361 clock-names = "ssi-al 1357 clock-names = "ssi-all",
1362 "ssi.9" 1358 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1363 "ssi.5" 1359 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1364 "ssi.1" 1360 "ssi.1", "ssi.0",
1365 "src.9" 1361 "src.9", "src.8", "src.7", "src.6",
1366 "src.5" 1362 "src.5", "src.4", "src.3", "src.2",
1367 "src.1" 1363 "src.1", "src.0",
1368 "mix.1" 1364 "mix.1", "mix.0",
1369 "ctu.1" 1365 "ctu.1", "ctu.0",
1370 "dvc.0" 1366 "dvc.0", "dvc.1",
1371 "clk_a" 1367 "clk_a", "clk_b", "clk_c", "clk_i";
1372 power-domains = <&sys 1368 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1373 resets = <&cpg 1005>, 1369 resets = <&cpg 1005>,
1374 <&cpg 1006>, 1370 <&cpg 1006>, <&cpg 1007>,
1375 <&cpg 1008>, 1371 <&cpg 1008>, <&cpg 1009>,
1376 <&cpg 1010>, 1372 <&cpg 1010>, <&cpg 1011>,
1377 <&cpg 1012>, 1373 <&cpg 1012>, <&cpg 1013>,
1378 <&cpg 1014>, 1374 <&cpg 1014>, <&cpg 1015>;
1379 reset-names = "ssi-al 1375 reset-names = "ssi-all",
1380 "ssi.9" 1376 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1381 "ssi.5" 1377 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1382 "ssi.1" 1378 "ssi.1", "ssi.0";
1383 status = "disabled"; 1379 status = "disabled";
1384 1380
1385 rcar_sound,ctu { 1381 rcar_sound,ctu {
1386 ctu00: ctu-0 1382 ctu00: ctu-0 { };
1387 ctu01: ctu-1 1383 ctu01: ctu-1 { };
1388 ctu02: ctu-2 1384 ctu02: ctu-2 { };
1389 ctu03: ctu-3 1385 ctu03: ctu-3 { };
1390 ctu10: ctu-4 1386 ctu10: ctu-4 { };
1391 ctu11: ctu-5 1387 ctu11: ctu-5 { };
1392 ctu12: ctu-6 1388 ctu12: ctu-6 { };
1393 ctu13: ctu-7 1389 ctu13: ctu-7 { };
1394 }; 1390 };
1395 1391
1396 rcar_sound,dvc { 1392 rcar_sound,dvc {
1397 dvc0: dvc-0 { 1393 dvc0: dvc-0 {
1398 dmas 1394 dmas = <&audma0 0xbc>;
1399 dma-n 1395 dma-names = "tx";
1400 }; 1396 };
1401 dvc1: dvc-1 { 1397 dvc1: dvc-1 {
1402 dmas 1398 dmas = <&audma0 0xbe>;
1403 dma-n 1399 dma-names = "tx";
1404 }; 1400 };
1405 }; 1401 };
1406 1402
1407 rcar_sound,mix { 1403 rcar_sound,mix {
1408 mix0: mix-0 { 1404 mix0: mix-0 { };
1409 mix1: mix-1 { 1405 mix1: mix-1 { };
1410 }; 1406 };
1411 1407
1412 rcar_sound,src { 1408 rcar_sound,src {
1413 src0: src-0 { 1409 src0: src-0 {
1414 inter 1410 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1415 dmas 1411 dmas = <&audma0 0x85>, <&audma0 0x9a>;
1416 dma-n 1412 dma-names = "rx", "tx";
1417 }; 1413 };
1418 src1: src-1 { 1414 src1: src-1 {
1419 inter 1415 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1420 dmas 1416 dmas = <&audma0 0x87>, <&audma0 0x9c>;
1421 dma-n 1417 dma-names = "rx", "tx";
1422 }; 1418 };
1423 src2: src-2 { 1419 src2: src-2 {
1424 inter 1420 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1425 dmas 1421 dmas = <&audma0 0x89>, <&audma0 0x9e>;
1426 dma-n 1422 dma-names = "rx", "tx";
1427 }; 1423 };
1428 src3: src-3 { 1424 src3: src-3 {
1429 inter 1425 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1430 dmas 1426 dmas = <&audma0 0x8b>, <&audma0 0xa0>;
1431 dma-n 1427 dma-names = "rx", "tx";
1432 }; 1428 };
1433 src4: src-4 { 1429 src4: src-4 {
1434 inter 1430 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1435 dmas 1431 dmas = <&audma0 0x8d>, <&audma0 0xb0>;
1436 dma-n 1432 dma-names = "rx", "tx";
1437 }; 1433 };
1438 src5: src-5 { 1434 src5: src-5 {
1439 inter 1435 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1440 dmas 1436 dmas = <&audma0 0x8f>, <&audma0 0xb2>;
1441 dma-n 1437 dma-names = "rx", "tx";
1442 }; 1438 };
1443 src6: src-6 { 1439 src6: src-6 {
1444 inter 1440 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1445 dmas 1441 dmas = <&audma0 0x91>, <&audma0 0xb4>;
1446 dma-n 1442 dma-names = "rx", "tx";
1447 }; 1443 };
1448 src7: src-7 { 1444 src7: src-7 {
1449 inter 1445 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1450 dmas 1446 dmas = <&audma0 0x93>, <&audma0 0xb6>;
1451 dma-n 1447 dma-names = "rx", "tx";
1452 }; 1448 };
1453 src8: src-8 { 1449 src8: src-8 {
1454 inter 1450 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1455 dmas 1451 dmas = <&audma0 0x95>, <&audma0 0xb8>;
1456 dma-n 1452 dma-names = "rx", "tx";
1457 }; 1453 };
1458 src9: src-9 { 1454 src9: src-9 {
1459 inter 1455 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
1460 dmas 1456 dmas = <&audma0 0x97>, <&audma0 0xba>;
1461 dma-n 1457 dma-names = "rx", "tx";
1462 }; 1458 };
1463 }; 1459 };
1464 1460
1465 rcar_sound,ssi { 1461 rcar_sound,ssi {
1466 ssi0: ssi-0 { 1462 ssi0: ssi-0 {
1467 inter 1463 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
1468 dmas 1464 dmas = <&audma0 0x01>, <&audma0 0x02>,
1469 1465 <&audma0 0x15>, <&audma0 0x16>;
1470 dma-n 1466 dma-names = "rx", "tx", "rxu", "txu";
1471 }; 1467 };
1472 ssi1: ssi-1 { 1468 ssi1: ssi-1 {
1473 inter 1469 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
1474 dmas 1470 dmas = <&audma0 0x03>, <&audma0 0x04>,
1475 1471 <&audma0 0x49>, <&audma0 0x4a>;
1476 dma-n 1472 dma-names = "rx", "tx", "rxu", "txu";
1477 }; 1473 };
1478 ssi2: ssi-2 { 1474 ssi2: ssi-2 {
1479 inter 1475 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
1480 dmas 1476 dmas = <&audma0 0x05>, <&audma0 0x06>,
1481 1477 <&audma0 0x63>, <&audma0 0x64>;
1482 dma-n 1478 dma-names = "rx", "tx", "rxu", "txu";
1483 }; 1479 };
1484 ssi3: ssi-3 { 1480 ssi3: ssi-3 {
1485 inter 1481 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1486 dmas 1482 dmas = <&audma0 0x07>, <&audma0 0x08>,
1487 1483 <&audma0 0x6f>, <&audma0 0x70>;
1488 dma-n 1484 dma-names = "rx", "tx", "rxu", "txu";
1489 }; 1485 };
1490 ssi4: ssi-4 { 1486 ssi4: ssi-4 {
1491 inter 1487 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1492 dmas 1488 dmas = <&audma0 0x09>, <&audma0 0x0a>,
1493 1489 <&audma0 0x71>, <&audma0 0x72>;
1494 dma-n 1490 dma-names = "rx", "tx", "rxu", "txu";
1495 }; 1491 };
1496 ssi5: ssi-5 { 1492 ssi5: ssi-5 {
1497 inter 1493 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1498 dmas 1494 dmas = <&audma0 0x0b>, <&audma0 0x0c>,
1499 1495 <&audma0 0x73>, <&audma0 0x74>;
1500 dma-n 1496 dma-names = "rx", "tx", "rxu", "txu";
1501 }; 1497 };
1502 ssi6: ssi-6 { 1498 ssi6: ssi-6 {
1503 inter 1499 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
1504 dmas 1500 dmas = <&audma0 0x0d>, <&audma0 0x0e>,
1505 1501 <&audma0 0x75>, <&audma0 0x76>;
1506 dma-n 1502 dma-names = "rx", "tx", "rxu", "txu";
1507 }; 1503 };
1508 ssi7: ssi-7 { 1504 ssi7: ssi-7 {
1509 inter 1505 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
1510 dmas 1506 dmas = <&audma0 0x0f>, <&audma0 0x10>,
1511 1507 <&audma0 0x79>, <&audma0 0x7a>;
1512 dma-n 1508 dma-names = "rx", "tx", "rxu", "txu";
1513 }; 1509 };
1514 ssi8: ssi-8 { 1510 ssi8: ssi-8 {
1515 inter 1511 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
1516 dmas 1512 dmas = <&audma0 0x11>, <&audma0 0x12>,
1517 1513 <&audma0 0x7b>, <&audma0 0x7c>;
1518 dma-n 1514 dma-names = "rx", "tx", "rxu", "txu";
1519 }; 1515 };
1520 ssi9: ssi-9 { 1516 ssi9: ssi-9 {
1521 inter 1517 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
1522 dmas 1518 dmas = <&audma0 0x13>, <&audma0 0x14>,
1523 1519 <&audma0 0x7d>, <&audma0 0x7e>;
1524 dma-n 1520 dma-names = "rx", "tx", "rxu", "txu";
1525 }; 1521 };
1526 }; 1522 };
1527 }; 1523 };
1528 1524
1529 audma0: dma-controller@ec7000 1525 audma0: dma-controller@ec700000 {
1530 compatible = "renesas 1526 compatible = "renesas,dmac-r8a774c0",
1531 "renesas 1527 "renesas,rcar-dmac";
1532 reg = <0 0xec700000 0 1528 reg = <0 0xec700000 0 0x10000>;
1533 interrupts = <GIC_SPI 1529 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
1534 <GIC_SPI 1530 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
1535 <GIC_SPI 1531 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
1536 <GIC_SPI 1532 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
1537 <GIC_SPI 1533 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
1538 <GIC_SPI 1534 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
1539 <GIC_SPI 1535 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
1540 <GIC_SPI 1536 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
1541 <GIC_SPI 1537 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
1542 <GIC_SPI 1538 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
1543 <GIC_SPI 1539 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1544 <GIC_SPI 1540 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
1545 <GIC_SPI 1541 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
1546 <GIC_SPI 1542 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
1547 <GIC_SPI 1543 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
1548 <GIC_SPI 1544 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1549 <GIC_SPI 1545 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
1550 interrupt-names = "er 1546 interrupt-names = "error",
1551 "ch0" 1547 "ch0", "ch1", "ch2", "ch3",
1552 "ch4" 1548 "ch4", "ch5", "ch6", "ch7",
1553 "ch8" 1549 "ch8", "ch9", "ch10", "ch11",
1554 "ch12 1550 "ch12", "ch13", "ch14", "ch15";
1555 clocks = <&cpg CPG_MO 1551 clocks = <&cpg CPG_MOD 502>;
1556 clock-names = "fck"; 1552 clock-names = "fck";
1557 power-domains = <&sys 1553 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1558 resets = <&cpg 502>; 1554 resets = <&cpg 502>;
1559 #dma-cells = <1>; 1555 #dma-cells = <1>;
1560 dma-channels = <16>; 1556 dma-channels = <16>;
1561 iommus = <&ipmmu_mp 0 1557 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
1562 <&ipmmu_mp 2 1558 <&ipmmu_mp 2>, <&ipmmu_mp 3>,
1563 <&ipmmu_mp 4 1559 <&ipmmu_mp 4>, <&ipmmu_mp 5>,
1564 <&ipmmu_mp 6 1560 <&ipmmu_mp 6>, <&ipmmu_mp 7>,
1565 <&ipmmu_mp 8 1561 <&ipmmu_mp 8>, <&ipmmu_mp 9>,
1566 <&ipmmu_mp 1 1562 <&ipmmu_mp 10>, <&ipmmu_mp 11>,
1567 <&ipmmu_mp 1 1563 <&ipmmu_mp 12>, <&ipmmu_mp 13>,
1568 <&ipmmu_mp 1 1564 <&ipmmu_mp 14>, <&ipmmu_mp 15>;
1569 }; 1565 };
1570 1566
1571 xhci0: usb@ee000000 { 1567 xhci0: usb@ee000000 {
1572 compatible = "renesas 1568 compatible = "renesas,xhci-r8a774c0",
1573 "renesas 1569 "renesas,rcar-gen3-xhci";
1574 reg = <0 0xee000000 0 1570 reg = <0 0xee000000 0 0xc00>;
1575 interrupts = <GIC_SPI 1571 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1576 clocks = <&cpg CPG_MO 1572 clocks = <&cpg CPG_MOD 328>;
1577 power-domains = <&sys 1573 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1578 resets = <&cpg 328>; 1574 resets = <&cpg 328>;
1579 status = "disabled"; 1575 status = "disabled";
1580 }; 1576 };
1581 1577
1582 usb3_peri0: usb@ee020000 { 1578 usb3_peri0: usb@ee020000 {
1583 compatible = "renesas 1579 compatible = "renesas,r8a774c0-usb3-peri",
1584 "renesas 1580 "renesas,rcar-gen3-usb3-peri";
1585 reg = <0 0xee020000 0 1581 reg = <0 0xee020000 0 0x400>;
1586 interrupts = <GIC_SPI 1582 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1587 clocks = <&cpg CPG_MO 1583 clocks = <&cpg CPG_MOD 328>;
1588 power-domains = <&sys 1584 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1589 resets = <&cpg 328>; 1585 resets = <&cpg 328>;
1590 status = "disabled"; 1586 status = "disabled";
1591 }; 1587 };
1592 1588
1593 ohci0: usb@ee080000 { 1589 ohci0: usb@ee080000 {
1594 compatible = "generic 1590 compatible = "generic-ohci";
1595 reg = <0 0xee080000 0 1591 reg = <0 0xee080000 0 0x100>;
1596 interrupts = <GIC_SPI 1592 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1597 clocks = <&cpg CPG_MO 1593 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
1598 phys = <&usb2_phy0 1> 1594 phys = <&usb2_phy0 1>;
1599 phy-names = "usb"; 1595 phy-names = "usb";
1600 power-domains = <&sys 1596 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1601 resets = <&cpg 703>, 1597 resets = <&cpg 703>, <&cpg 704>;
1602 status = "disabled"; 1598 status = "disabled";
1603 }; 1599 };
1604 1600
1605 ehci0: usb@ee080100 { 1601 ehci0: usb@ee080100 {
1606 compatible = "generic 1602 compatible = "generic-ehci";
1607 reg = <0 0xee080100 0 1603 reg = <0 0xee080100 0 0x100>;
1608 interrupts = <GIC_SPI 1604 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1609 clocks = <&cpg CPG_MO 1605 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
1610 phys = <&usb2_phy0 2> 1606 phys = <&usb2_phy0 2>;
1611 phy-names = "usb"; 1607 phy-names = "usb";
1612 companion = <&ohci0>; 1608 companion = <&ohci0>;
1613 power-domains = <&sys 1609 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1614 resets = <&cpg 703>, 1610 resets = <&cpg 703>, <&cpg 704>;
1615 status = "disabled"; 1611 status = "disabled";
1616 }; 1612 };
1617 1613
1618 usb2_phy0: usb-phy@ee080200 { 1614 usb2_phy0: usb-phy@ee080200 {
1619 compatible = "renesas 1615 compatible = "renesas,usb2-phy-r8a774c0",
1620 "renesas 1616 "renesas,rcar-gen3-usb2-phy";
1621 reg = <0 0xee080200 0 1617 reg = <0 0xee080200 0 0x700>;
1622 interrupts = <GIC_SPI 1618 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1623 clocks = <&cpg CPG_MO 1619 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
1624 power-domains = <&sys 1620 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1625 resets = <&cpg 703>, 1621 resets = <&cpg 703>, <&cpg 704>;
1626 #phy-cells = <1>; 1622 #phy-cells = <1>;
1627 status = "disabled"; 1623 status = "disabled";
1628 }; 1624 };
1629 1625
1630 sdhi0: mmc@ee100000 { 1626 sdhi0: mmc@ee100000 {
1631 compatible = "renesas 1627 compatible = "renesas,sdhi-r8a774c0",
1632 "renesas 1628 "renesas,rcar-gen3-sdhi";
1633 reg = <0 0xee100000 0 1629 reg = <0 0xee100000 0 0x2000>;
1634 interrupts = <GIC_SPI 1630 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
1635 clocks = <&cpg CPG_MO 1631 clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A774C0_CLK_SD0H>;
1636 clock-names = "core", 1632 clock-names = "core", "clkh";
1637 max-frequency = <2000 1633 max-frequency = <200000000>;
1638 power-domains = <&sys 1634 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1639 resets = <&cpg 314>; 1635 resets = <&cpg 314>;
1640 iommus = <&ipmmu_ds1 <<
1641 status = "disabled"; 1636 status = "disabled";
1642 }; 1637 };
1643 1638
1644 sdhi1: mmc@ee120000 { 1639 sdhi1: mmc@ee120000 {
1645 compatible = "renesas 1640 compatible = "renesas,sdhi-r8a774c0",
1646 "renesas 1641 "renesas,rcar-gen3-sdhi";
1647 reg = <0 0xee120000 0 1642 reg = <0 0xee120000 0 0x2000>;
1648 interrupts = <GIC_SPI 1643 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
1649 clocks = <&cpg CPG_MO 1644 clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A774C0_CLK_SD1H>;
1650 clock-names = "core", 1645 clock-names = "core", "clkh";
1651 max-frequency = <2000 1646 max-frequency = <200000000>;
1652 power-domains = <&sys 1647 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1653 resets = <&cpg 313>; 1648 resets = <&cpg 313>;
1654 iommus = <&ipmmu_ds1 <<
1655 status = "disabled"; 1649 status = "disabled";
1656 }; 1650 };
1657 1651
1658 sdhi3: mmc@ee160000 { 1652 sdhi3: mmc@ee160000 {
1659 compatible = "renesas 1653 compatible = "renesas,sdhi-r8a774c0",
1660 "renesas 1654 "renesas,rcar-gen3-sdhi";
1661 reg = <0 0xee160000 0 1655 reg = <0 0xee160000 0 0x2000>;
1662 interrupts = <GIC_SPI 1656 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
1663 clocks = <&cpg CPG_MO 1657 clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A774C0_CLK_SD3H>;
1664 clock-names = "core", 1658 clock-names = "core", "clkh";
1665 max-frequency = <2000 1659 max-frequency = <200000000>;
1666 power-domains = <&sys 1660 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1667 resets = <&cpg 311>; 1661 resets = <&cpg 311>;
1668 iommus = <&ipmmu_ds1 <<
1669 status = "disabled"; 1662 status = "disabled";
1670 }; 1663 };
1671 1664
1672 rpc: spi@ee200000 { 1665 rpc: spi@ee200000 {
1673 compatible = "renesas 1666 compatible = "renesas,r8a774c0-rpc-if",
1674 "renesas 1667 "renesas,rcar-gen3-rpc-if";
1675 reg = <0 0xee200000 0 1668 reg = <0 0xee200000 0 0x200>,
1676 <0 0x08000000 0 1669 <0 0x08000000 0 0x4000000>,
1677 <0 0xee208000 0 1670 <0 0xee208000 0 0x100>;
1678 reg-names = "regs", " 1671 reg-names = "regs", "dirmap", "wbuf";
1679 interrupts = <GIC_SPI 1672 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
1680 clocks = <&cpg CPG_MO 1673 clocks = <&cpg CPG_MOD 917>;
>> 1674 clock-names = "rpc";
1681 power-domains = <&sys 1675 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1682 resets = <&cpg 917>; 1676 resets = <&cpg 917>;
1683 #address-cells = <1>; 1677 #address-cells = <1>;
1684 #size-cells = <0>; 1678 #size-cells = <0>;
1685 status = "disabled"; 1679 status = "disabled";
1686 }; 1680 };
1687 1681
1688 gic: interrupt-controller@f10 1682 gic: interrupt-controller@f1010000 {
1689 compatible = "arm,gic 1683 compatible = "arm,gic-400";
1690 #interrupt-cells = <3 1684 #interrupt-cells = <3>;
1691 #address-cells = <0>; 1685 #address-cells = <0>;
1692 interrupt-controller; 1686 interrupt-controller;
1693 reg = <0x0 0xf1010000 1687 reg = <0x0 0xf1010000 0 0x1000>,
1694 <0x0 0xf1020000 1688 <0x0 0xf1020000 0 0x20000>,
1695 <0x0 0xf1040000 1689 <0x0 0xf1040000 0 0x20000>,
1696 <0x0 0xf1060000 1690 <0x0 0xf1060000 0 0x20000>;
1697 interrupts = <GIC_PPI 1691 interrupts = <GIC_PPI 9
1698 (GIC_ 1692 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
1699 clocks = <&cpg CPG_MO 1693 clocks = <&cpg CPG_MOD 408>;
1700 clock-names = "clk"; 1694 clock-names = "clk";
1701 power-domains = <&sys 1695 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1702 resets = <&cpg 408>; 1696 resets = <&cpg 408>;
1703 }; 1697 };
1704 1698
1705 pciec0: pcie@fe000000 { 1699 pciec0: pcie@fe000000 {
1706 compatible = "renesas 1700 compatible = "renesas,pcie-r8a774c0",
1707 "renesas 1701 "renesas,pcie-rcar-gen3";
1708 reg = <0 0xfe000000 0 1702 reg = <0 0xfe000000 0 0x80000>;
1709 #address-cells = <3>; 1703 #address-cells = <3>;
1710 #size-cells = <2>; 1704 #size-cells = <2>;
1711 bus-range = <0x00 0xf 1705 bus-range = <0x00 0xff>;
1712 device_type = "pci"; 1706 device_type = "pci";
1713 ranges = <0x01000000 1707 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
1714 <0x02000000 1708 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
1715 <0x02000000 1709 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
1716 <0x42000000 1710 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1717 /* Map all possible D !! 1711 /* Map all possible DDR as inbound ranges */
1718 dma-ranges = <0x42000 !! 1712 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;
1719 interrupts = <GIC_SPI 1713 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1720 <GIC_SPI 1714 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1721 <GIC_SPI 1715 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1722 #interrupt-cells = <1 1716 #interrupt-cells = <1>;
1723 interrupt-map-mask = 1717 interrupt-map-mask = <0 0 0 0>;
1724 interrupt-map = <0 0 1718 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1725 clocks = <&cpg CPG_MO 1719 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
1726 clock-names = "pcie", 1720 clock-names = "pcie", "pcie_bus";
1727 power-domains = <&sys 1721 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1728 resets = <&cpg 319>; 1722 resets = <&cpg 319>;
1729 iommu-map = <0 &ipmmu <<
1730 iommu-map-mask = <0>; <<
1731 status = "disabled"; 1723 status = "disabled";
1732 }; 1724 };
1733 1725
1734 pciec0_ep: pcie-ep@fe000000 { 1726 pciec0_ep: pcie-ep@fe000000 {
1735 compatible = "renesas 1727 compatible = "renesas,r8a774c0-pcie-ep",
1736 "renesas 1728 "renesas,rcar-gen3-pcie-ep";
1737 reg = <0x0 0xfe000000 1729 reg = <0x0 0xfe000000 0 0x80000>,
1738 <0x0 0xfe100000 1730 <0x0 0xfe100000 0 0x100000>,
1739 <0x0 0xfe200000 1731 <0x0 0xfe200000 0 0x200000>,
1740 <0x0 0x30000000 1732 <0x0 0x30000000 0 0x8000000>,
1741 <0x0 0x38000000 1733 <0x0 0x38000000 0 0x8000000>;
1742 reg-names = "apb-base 1734 reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
1743 interrupts = <GIC_SPI 1735 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1744 <GIC_SPI 1736 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1745 <GIC_SPI 1737 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1746 clocks = <&cpg CPG_MO 1738 clocks = <&cpg CPG_MOD 319>;
1747 clock-names = "pcie"; 1739 clock-names = "pcie";
1748 resets = <&cpg 319>; 1740 resets = <&cpg 319>;
1749 power-domains = <&sys 1741 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1750 status = "disabled"; 1742 status = "disabled";
1751 }; 1743 };
1752 1744
1753 vspb0: vsp@fe960000 { 1745 vspb0: vsp@fe960000 {
1754 compatible = "renesas 1746 compatible = "renesas,vsp2";
1755 reg = <0 0xfe960000 0 1747 reg = <0 0xfe960000 0 0x8000>;
1756 interrupts = <GIC_SPI 1748 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
1757 clocks = <&cpg CPG_MO 1749 clocks = <&cpg CPG_MOD 626>;
1758 power-domains = <&sys 1750 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1759 resets = <&cpg 626>; 1751 resets = <&cpg 626>;
1760 renesas,fcp = <&fcpvb 1752 renesas,fcp = <&fcpvb0>;
1761 }; 1753 };
1762 1754
1763 vspd0: vsp@fea20000 { 1755 vspd0: vsp@fea20000 {
1764 compatible = "renesas 1756 compatible = "renesas,vsp2";
1765 reg = <0 0xfea20000 0 1757 reg = <0 0xfea20000 0 0x7000>;
1766 interrupts = <GIC_SPI 1758 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
1767 clocks = <&cpg CPG_MO 1759 clocks = <&cpg CPG_MOD 623>;
1768 power-domains = <&sys 1760 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1769 resets = <&cpg 623>; 1761 resets = <&cpg 623>;
1770 renesas,fcp = <&fcpvd 1762 renesas,fcp = <&fcpvd0>;
1771 }; 1763 };
1772 1764
1773 vspd1: vsp@fea28000 { 1765 vspd1: vsp@fea28000 {
1774 compatible = "renesas 1766 compatible = "renesas,vsp2";
1775 reg = <0 0xfea28000 0 1767 reg = <0 0xfea28000 0 0x7000>;
1776 interrupts = <GIC_SPI 1768 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
1777 clocks = <&cpg CPG_MO 1769 clocks = <&cpg CPG_MOD 622>;
1778 power-domains = <&sys 1770 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1779 resets = <&cpg 622>; 1771 resets = <&cpg 622>;
1780 renesas,fcp = <&fcpvd 1772 renesas,fcp = <&fcpvd1>;
1781 }; 1773 };
1782 1774
1783 vspi0: vsp@fe9a0000 { 1775 vspi0: vsp@fe9a0000 {
1784 compatible = "renesas 1776 compatible = "renesas,vsp2";
1785 reg = <0 0xfe9a0000 0 1777 reg = <0 0xfe9a0000 0 0x8000>;
1786 interrupts = <GIC_SPI 1778 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
1787 clocks = <&cpg CPG_MO 1779 clocks = <&cpg CPG_MOD 631>;
1788 power-domains = <&sys 1780 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1789 resets = <&cpg 631>; 1781 resets = <&cpg 631>;
1790 renesas,fcp = <&fcpvi 1782 renesas,fcp = <&fcpvi0>;
1791 }; 1783 };
1792 1784
1793 fcpvb0: fcp@fe96f000 { 1785 fcpvb0: fcp@fe96f000 {
1794 compatible = "renesas 1786 compatible = "renesas,fcpv";
1795 reg = <0 0xfe96f000 0 1787 reg = <0 0xfe96f000 0 0x200>;
1796 clocks = <&cpg CPG_MO 1788 clocks = <&cpg CPG_MOD 607>;
1797 power-domains = <&sys 1789 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1798 resets = <&cpg 607>; 1790 resets = <&cpg 607>;
1799 iommus = <&ipmmu_vp0 1791 iommus = <&ipmmu_vp0 5>;
1800 }; 1792 };
1801 1793
1802 fcpvd0: fcp@fea27000 { 1794 fcpvd0: fcp@fea27000 {
1803 compatible = "renesas 1795 compatible = "renesas,fcpv";
1804 reg = <0 0xfea27000 0 1796 reg = <0 0xfea27000 0 0x200>;
1805 clocks = <&cpg CPG_MO 1797 clocks = <&cpg CPG_MOD 603>;
1806 power-domains = <&sys 1798 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1807 resets = <&cpg 603>; 1799 resets = <&cpg 603>;
1808 iommus = <&ipmmu_vi0 1800 iommus = <&ipmmu_vi0 8>;
1809 }; 1801 };
1810 1802
1811 fcpvd1: fcp@fea2f000 { 1803 fcpvd1: fcp@fea2f000 {
1812 compatible = "renesas 1804 compatible = "renesas,fcpv";
1813 reg = <0 0xfea2f000 0 1805 reg = <0 0xfea2f000 0 0x200>;
1814 clocks = <&cpg CPG_MO 1806 clocks = <&cpg CPG_MOD 602>;
1815 power-domains = <&sys 1807 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1816 resets = <&cpg 602>; 1808 resets = <&cpg 602>;
1817 iommus = <&ipmmu_vi0 1809 iommus = <&ipmmu_vi0 9>;
1818 }; 1810 };
1819 1811
1820 fcpvi0: fcp@fe9af000 { 1812 fcpvi0: fcp@fe9af000 {
1821 compatible = "renesas 1813 compatible = "renesas,fcpv";
1822 reg = <0 0xfe9af000 0 1814 reg = <0 0xfe9af000 0 0x200>;
1823 clocks = <&cpg CPG_MO 1815 clocks = <&cpg CPG_MOD 611>;
1824 power-domains = <&sys 1816 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1825 resets = <&cpg 611>; 1817 resets = <&cpg 611>;
1826 iommus = <&ipmmu_vp0 1818 iommus = <&ipmmu_vp0 8>;
1827 }; 1819 };
1828 1820
1829 csi40: csi2@feaa0000 { 1821 csi40: csi2@feaa0000 {
1830 compatible = "renesas 1822 compatible = "renesas,r8a774c0-csi2";
1831 reg = <0 0xfeaa0000 0 1823 reg = <0 0xfeaa0000 0 0x10000>;
1832 interrupts = <GIC_SPI 1824 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
1833 clocks = <&cpg CPG_MO 1825 clocks = <&cpg CPG_MOD 716>;
1834 power-domains = <&sys 1826 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1835 resets = <&cpg 716>; 1827 resets = <&cpg 716>;
1836 status = "disabled"; 1828 status = "disabled";
1837 1829
1838 ports { 1830 ports {
1839 #address-cell 1831 #address-cells = <1>;
1840 #size-cells = 1832 #size-cells = <0>;
1841 1833
1842 port@0 { 1834 port@0 {
1843 reg = 1835 reg = <0>;
1844 }; 1836 };
1845 1837
1846 port@1 { 1838 port@1 {
1847 #addr 1839 #address-cells = <1>;
1848 #size 1840 #size-cells = <0>;
1849 1841
1850 reg = 1842 reg = <1>;
1851 1843
1852 csi40 1844 csi40vin4: endpoint@0 {
1853 1845 reg = <0>;
1854 1846 remote-endpoint = <&vin4csi40>;
1855 }; 1847 };
1856 csi40 1848 csi40vin5: endpoint@1 {
1857 1849 reg = <1>;
1858 1850 remote-endpoint = <&vin5csi40>;
1859 }; 1851 };
1860 }; 1852 };
1861 }; 1853 };
1862 }; 1854 };
1863 1855
1864 du: display@feb00000 { 1856 du: display@feb00000 {
1865 compatible = "renesas 1857 compatible = "renesas,du-r8a774c0";
1866 reg = <0 0xfeb00000 0 1858 reg = <0 0xfeb00000 0 0x40000>;
1867 interrupts = <GIC_SPI 1859 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
1868 <GIC_SPI 1860 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
1869 clocks = <&cpg CPG_MO 1861 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
1870 clock-names = "du.0", 1862 clock-names = "du.0", "du.1";
1871 resets = <&cpg 724>; 1863 resets = <&cpg 724>;
1872 reset-names = "du.0"; 1864 reset-names = "du.0";
1873 renesas,vsps = <&vspd 1865 renesas,vsps = <&vspd0 0>, <&vspd1 0>;
1874 1866
1875 status = "disabled"; 1867 status = "disabled";
1876 1868
1877 ports { 1869 ports {
1878 #address-cell 1870 #address-cells = <1>;
1879 #size-cells = 1871 #size-cells = <0>;
1880 1872
1881 port@0 { 1873 port@0 {
1882 reg = 1874 reg = <0>;
1883 }; 1875 };
1884 1876
1885 port@1 { 1877 port@1 {
1886 reg = 1878 reg = <1>;
1887 du_ou 1879 du_out_lvds0: endpoint {
1888 1880 remote-endpoint = <&lvds0_in>;
1889 }; 1881 };
1890 }; 1882 };
1891 1883
1892 port@2 { 1884 port@2 {
1893 reg = 1885 reg = <2>;
1894 du_ou 1886 du_out_lvds1: endpoint {
1895 1887 remote-endpoint = <&lvds1_in>;
1896 }; 1888 };
1897 }; 1889 };
1898 }; 1890 };
1899 }; 1891 };
1900 1892
1901 lvds0: lvds-encoder@feb90000 1893 lvds0: lvds-encoder@feb90000 {
1902 compatible = "renesas 1894 compatible = "renesas,r8a774c0-lvds";
1903 reg = <0 0xfeb90000 0 1895 reg = <0 0xfeb90000 0 0x20>;
1904 clocks = <&cpg CPG_MO 1896 clocks = <&cpg CPG_MOD 727>;
1905 power-domains = <&sys 1897 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1906 resets = <&cpg 727>; 1898 resets = <&cpg 727>;
1907 status = "disabled"; 1899 status = "disabled";
1908 1900
1909 renesas,companion = < 1901 renesas,companion = <&lvds1>;
1910 1902
1911 ports { 1903 ports {
1912 #address-cell 1904 #address-cells = <1>;
1913 #size-cells = 1905 #size-cells = <0>;
1914 1906
1915 port@0 { 1907 port@0 {
1916 reg = 1908 reg = <0>;
1917 lvds0 1909 lvds0_in: endpoint {
1918 1910 remote-endpoint = <&du_out_lvds0>;
1919 }; 1911 };
1920 }; 1912 };
1921 1913
1922 port@1 { 1914 port@1 {
1923 reg = 1915 reg = <1>;
1924 }; 1916 };
1925 }; 1917 };
1926 }; 1918 };
1927 1919
1928 lvds1: lvds-encoder@feb90100 1920 lvds1: lvds-encoder@feb90100 {
1929 compatible = "renesas 1921 compatible = "renesas,r8a774c0-lvds";
1930 reg = <0 0xfeb90100 0 1922 reg = <0 0xfeb90100 0 0x20>;
1931 clocks = <&cpg CPG_MO 1923 clocks = <&cpg CPG_MOD 727>;
1932 power-domains = <&sys 1924 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1933 resets = <&cpg 726>; 1925 resets = <&cpg 726>;
1934 status = "disabled"; 1926 status = "disabled";
1935 1927
1936 ports { 1928 ports {
1937 #address-cell 1929 #address-cells = <1>;
1938 #size-cells = 1930 #size-cells = <0>;
1939 1931
1940 port@0 { 1932 port@0 {
1941 reg = 1933 reg = <0>;
1942 lvds1 1934 lvds1_in: endpoint {
1943 1935 remote-endpoint = <&du_out_lvds1>;
1944 }; 1936 };
1945 }; 1937 };
1946 1938
1947 port@1 { 1939 port@1 {
1948 reg = 1940 reg = <1>;
1949 }; 1941 };
1950 }; 1942 };
1951 }; 1943 };
1952 1944
1953 prr: chipid@fff00044 { 1945 prr: chipid@fff00044 {
1954 compatible = "renesas 1946 compatible = "renesas,prr";
1955 reg = <0 0xfff00044 0 1947 reg = <0 0xfff00044 0 4>;
1956 }; 1948 };
1957 }; 1949 };
1958 1950
1959 thermal-zones { 1951 thermal-zones {
1960 cpu-thermal { 1952 cpu-thermal {
1961 polling-delay-passive 1953 polling-delay-passive = <250>;
1962 polling-delay = <0>; 1954 polling-delay = <0>;
1963 thermal-sensors = <&t 1955 thermal-sensors = <&thermal>;
1964 sustainable-power = < 1956 sustainable-power = <717>;
1965 1957
1966 cooling-maps { 1958 cooling-maps {
1967 map0 { 1959 map0 {
1968 trip 1960 trip = <&target>;
1969 cooli 1961 cooling-device = <&a53_0 0 2>;
1970 contr 1962 contribution = <1024>;
1971 }; 1963 };
1972 }; 1964 };
1973 1965
1974 trips { 1966 trips {
1975 sensor1_crit: 1967 sensor1_crit: sensor1-crit {
1976 tempe 1968 temperature = <120000>;
1977 hyste 1969 hysteresis = <2000>;
1978 type 1970 type = "critical";
1979 }; 1971 };
1980 1972
1981 target: trip- 1973 target: trip-point1 {
1982 tempe 1974 temperature = <100000>;
1983 hyste 1975 hysteresis = <2000>;
1984 type 1976 type = "passive";
1985 }; 1977 };
1986 }; 1978 };
1987 }; 1979 };
1988 }; 1980 };
1989 1981
1990 timer { 1982 timer {
1991 compatible = "arm,armv8-timer 1983 compatible = "arm,armv8-timer";
1992 interrupts-extended = <&gic G 1984 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1993 <&gic G 1985 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1994 <&gic G 1986 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1995 <&gic G 1987 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
1996 interrupt-names = "sec-phys", <<
1997 }; 1988 };
1998 1989
1999 /* External USB clocks - can be overr 1990 /* External USB clocks - can be overridden by the board */
2000 usb3s0_clk: usb3s0 { 1991 usb3s0_clk: usb3s0 {
2001 compatible = "fixed-clock"; 1992 compatible = "fixed-clock";
2002 #clock-cells = <0>; 1993 #clock-cells = <0>;
2003 clock-frequency = <0>; 1994 clock-frequency = <0>;
2004 }; 1995 };
2005 1996
2006 usb_extal_clk: usb_extal { 1997 usb_extal_clk: usb_extal {
2007 compatible = "fixed-clock"; 1998 compatible = "fixed-clock";
2008 #clock-cells = <0>; 1999 #clock-cells = <0>;
2009 clock-frequency = <0>; 2000 clock-frequency = <0>;
2010 }; 2001 };
2011 }; 2002 };
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