1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * Device Tree Source for the RZ/G2E (R8A774C0 3 * Device Tree Source for the RZ/G2E (R8A774C0) SoC
4 * 4 *
5 * Copyright (C) 2018-2019 Renesas Electronics 5 * Copyright (C) 2018-2019 Renesas Electronics Corp.
6 */ 6 */
7 7
8 #include <dt-bindings/clock/r8a774c0-cpg-mssr. 8 #include <dt-bindings/clock/r8a774c0-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm 9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a774c0-sysc.h> 10 #include <dt-bindings/power/r8a774c0-sysc.h>
11 11
12 / { 12 / {
13 compatible = "renesas,r8a774c0"; 13 compatible = "renesas,r8a774c0";
14 #address-cells = <2>; 14 #address-cells = <2>;
15 #size-cells = <2>; 15 #size-cells = <2>;
16 16
17 /* 17 /*
18 * The external audio clocks are confi 18 * The external audio clocks are configured as 0 Hz fixed frequency
19 * clocks by default. 19 * clocks by default.
20 * Boards that provide audio clocks sh 20 * Boards that provide audio clocks should override them.
21 */ 21 */
22 audio_clk_a: audio_clk_a { 22 audio_clk_a: audio_clk_a {
23 compatible = "fixed-clock"; 23 compatible = "fixed-clock";
24 #clock-cells = <0>; 24 #clock-cells = <0>;
25 clock-frequency = <0>; 25 clock-frequency = <0>;
26 }; 26 };
27 27
28 audio_clk_b: audio_clk_b { 28 audio_clk_b: audio_clk_b {
29 compatible = "fixed-clock"; 29 compatible = "fixed-clock";
30 #clock-cells = <0>; 30 #clock-cells = <0>;
31 clock-frequency = <0>; 31 clock-frequency = <0>;
32 }; 32 };
33 33
34 audio_clk_c: audio_clk_c { 34 audio_clk_c: audio_clk_c {
35 compatible = "fixed-clock"; 35 compatible = "fixed-clock";
36 #clock-cells = <0>; 36 #clock-cells = <0>;
37 clock-frequency = <0>; 37 clock-frequency = <0>;
38 }; 38 };
39 39
40 /* External CAN clock - to be overridd 40 /* External CAN clock - to be overridden by boards that provide it */
41 can_clk: can { 41 can_clk: can {
42 compatible = "fixed-clock"; 42 compatible = "fixed-clock";
43 #clock-cells = <0>; 43 #clock-cells = <0>;
44 clock-frequency = <0>; 44 clock-frequency = <0>;
45 }; 45 };
46 46
47 cluster1_opp: opp-table-1 { 47 cluster1_opp: opp-table-1 {
48 compatible = "operating-points 48 compatible = "operating-points-v2";
49 opp-shared; 49 opp-shared;
50 opp-800000000 { 50 opp-800000000 {
51 opp-hz = /bits/ 64 <80 51 opp-hz = /bits/ 64 <800000000>;
52 clock-latency-ns = <30 52 clock-latency-ns = <300000>;
53 }; 53 };
54 opp-1000000000 { 54 opp-1000000000 {
55 opp-hz = /bits/ 64 <10 55 opp-hz = /bits/ 64 <1000000000>;
56 clock-latency-ns = <30 56 clock-latency-ns = <300000>;
57 }; 57 };
58 opp-1200000000 { 58 opp-1200000000 {
59 opp-hz = /bits/ 64 <12 59 opp-hz = /bits/ 64 <1200000000>;
60 clock-latency-ns = <30 60 clock-latency-ns = <300000>;
61 opp-suspend; 61 opp-suspend;
62 }; 62 };
63 }; 63 };
64 64
65 cpus { 65 cpus {
66 #address-cells = <1>; 66 #address-cells = <1>;
67 #size-cells = <0>; 67 #size-cells = <0>;
68 68
69 a53_0: cpu@0 { 69 a53_0: cpu@0 {
70 compatible = "arm,cort 70 compatible = "arm,cortex-a53";
71 reg = <0>; 71 reg = <0>;
72 device_type = "cpu"; 72 device_type = "cpu";
73 #cooling-cells = <2>; 73 #cooling-cells = <2>;
74 power-domains = <&sysc 74 power-domains = <&sysc R8A774C0_PD_CA53_CPU0>;
75 next-level-cache = <&L 75 next-level-cache = <&L2_CA53>;
76 enable-method = "psci" 76 enable-method = "psci";
77 dynamic-power-coeffici 77 dynamic-power-coefficient = <277>;
78 clocks = <&cpg CPG_COR 78 clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>;
79 operating-points-v2 = 79 operating-points-v2 = <&cluster1_opp>;
80 }; 80 };
81 81
82 a53_1: cpu@1 { 82 a53_1: cpu@1 {
83 compatible = "arm,cort 83 compatible = "arm,cortex-a53";
84 reg = <1>; 84 reg = <1>;
85 device_type = "cpu"; 85 device_type = "cpu";
86 power-domains = <&sysc 86 power-domains = <&sysc R8A774C0_PD_CA53_CPU1>;
87 next-level-cache = <&L 87 next-level-cache = <&L2_CA53>;
88 enable-method = "psci" 88 enable-method = "psci";
89 clocks = <&cpg CPG_COR 89 clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>;
90 operating-points-v2 = 90 operating-points-v2 = <&cluster1_opp>;
91 }; 91 };
92 92
93 L2_CA53: cache-controller-0 { 93 L2_CA53: cache-controller-0 {
94 compatible = "cache"; 94 compatible = "cache";
95 power-domains = <&sysc 95 power-domains = <&sysc R8A774C0_PD_CA53_SCU>;
96 cache-unified; 96 cache-unified;
97 cache-level = <2>; 97 cache-level = <2>;
98 }; 98 };
99 }; 99 };
100 100
101 extal_clk: extal { 101 extal_clk: extal {
102 compatible = "fixed-clock"; 102 compatible = "fixed-clock";
103 #clock-cells = <0>; 103 #clock-cells = <0>;
104 /* This value must be overridd 104 /* This value must be overridden by the board */
105 clock-frequency = <0>; 105 clock-frequency = <0>;
106 }; 106 };
107 107
108 /* External PCIe clock - can be overri 108 /* External PCIe clock - can be overridden by the board */
109 pcie_bus_clk: pcie_bus { 109 pcie_bus_clk: pcie_bus {
110 compatible = "fixed-clock"; 110 compatible = "fixed-clock";
111 #clock-cells = <0>; 111 #clock-cells = <0>;
112 clock-frequency = <0>; 112 clock-frequency = <0>;
113 }; 113 };
114 114
115 pmu_a53 { 115 pmu_a53 {
116 compatible = "arm,cortex-a53-p 116 compatible = "arm,cortex-a53-pmu";
117 interrupts-extended = <&gic GI 117 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
118 <&gic GI 118 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
119 interrupt-affinity = <&a53_0>, 119 interrupt-affinity = <&a53_0>, <&a53_1>;
120 }; 120 };
121 121
122 psci { 122 psci {
123 compatible = "arm,psci-1.0", " 123 compatible = "arm,psci-1.0", "arm,psci-0.2";
124 method = "smc"; 124 method = "smc";
125 }; 125 };
126 126
127 /* External SCIF clock - to be overrid 127 /* External SCIF clock - to be overridden by boards that provide it */
128 scif_clk: scif { 128 scif_clk: scif {
129 compatible = "fixed-clock"; 129 compatible = "fixed-clock";
130 #clock-cells = <0>; 130 #clock-cells = <0>;
131 clock-frequency = <0>; 131 clock-frequency = <0>;
132 }; 132 };
133 133
134 soc: soc { 134 soc: soc {
135 compatible = "simple-bus"; 135 compatible = "simple-bus";
136 interrupt-parent = <&gic>; 136 interrupt-parent = <&gic>;
137 #address-cells = <2>; 137 #address-cells = <2>;
138 #size-cells = <2>; 138 #size-cells = <2>;
139 ranges; 139 ranges;
140 140
141 rwdt: watchdog@e6020000 { 141 rwdt: watchdog@e6020000 {
142 compatible = "renesas, 142 compatible = "renesas,r8a774c0-wdt",
143 "renesas, 143 "renesas,rcar-gen3-wdt";
144 reg = <0 0xe6020000 0 144 reg = <0 0xe6020000 0 0x0c>;
145 interrupts = <GIC_SPI 145 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
146 clocks = <&cpg CPG_MOD 146 clocks = <&cpg CPG_MOD 402>;
147 power-domains = <&sysc 147 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
148 resets = <&cpg 402>; 148 resets = <&cpg 402>;
149 status = "disabled"; 149 status = "disabled";
150 }; 150 };
151 151
152 gpio0: gpio@e6050000 { 152 gpio0: gpio@e6050000 {
153 compatible = "renesas, 153 compatible = "renesas,gpio-r8a774c0",
154 "renesas, 154 "renesas,rcar-gen3-gpio";
155 reg = <0 0xe6050000 0 155 reg = <0 0xe6050000 0 0x50>;
156 interrupts = <GIC_SPI 156 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
157 #gpio-cells = <2>; 157 #gpio-cells = <2>;
158 gpio-controller; 158 gpio-controller;
159 gpio-ranges = <&pfc 0 159 gpio-ranges = <&pfc 0 0 18>;
160 #interrupt-cells = <2> 160 #interrupt-cells = <2>;
161 interrupt-controller; 161 interrupt-controller;
162 clocks = <&cpg CPG_MOD 162 clocks = <&cpg CPG_MOD 912>;
163 power-domains = <&sysc 163 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
164 resets = <&cpg 912>; 164 resets = <&cpg 912>;
165 }; 165 };
166 166
167 gpio1: gpio@e6051000 { 167 gpio1: gpio@e6051000 {
168 compatible = "renesas, 168 compatible = "renesas,gpio-r8a774c0",
169 "renesas, 169 "renesas,rcar-gen3-gpio";
170 reg = <0 0xe6051000 0 170 reg = <0 0xe6051000 0 0x50>;
171 interrupts = <GIC_SPI 171 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
172 #gpio-cells = <2>; 172 #gpio-cells = <2>;
173 gpio-controller; 173 gpio-controller;
174 gpio-ranges = <&pfc 0 174 gpio-ranges = <&pfc 0 32 23>;
175 #interrupt-cells = <2> 175 #interrupt-cells = <2>;
176 interrupt-controller; 176 interrupt-controller;
177 clocks = <&cpg CPG_MOD 177 clocks = <&cpg CPG_MOD 911>;
178 power-domains = <&sysc 178 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
179 resets = <&cpg 911>; 179 resets = <&cpg 911>;
180 }; 180 };
181 181
182 gpio2: gpio@e6052000 { 182 gpio2: gpio@e6052000 {
183 compatible = "renesas, 183 compatible = "renesas,gpio-r8a774c0",
184 "renesas, 184 "renesas,rcar-gen3-gpio";
185 reg = <0 0xe6052000 0 185 reg = <0 0xe6052000 0 0x50>;
186 interrupts = <GIC_SPI 186 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
187 #gpio-cells = <2>; 187 #gpio-cells = <2>;
188 gpio-controller; 188 gpio-controller;
189 gpio-ranges = <&pfc 0 189 gpio-ranges = <&pfc 0 64 26>;
190 #interrupt-cells = <2> 190 #interrupt-cells = <2>;
191 interrupt-controller; 191 interrupt-controller;
192 clocks = <&cpg CPG_MOD 192 clocks = <&cpg CPG_MOD 910>;
193 power-domains = <&sysc 193 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
194 resets = <&cpg 910>; 194 resets = <&cpg 910>;
195 }; 195 };
196 196
197 gpio3: gpio@e6053000 { 197 gpio3: gpio@e6053000 {
198 compatible = "renesas, 198 compatible = "renesas,gpio-r8a774c0",
199 "renesas, 199 "renesas,rcar-gen3-gpio";
200 reg = <0 0xe6053000 0 200 reg = <0 0xe6053000 0 0x50>;
201 interrupts = <GIC_SPI 201 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
202 #gpio-cells = <2>; 202 #gpio-cells = <2>;
203 gpio-controller; 203 gpio-controller;
204 gpio-ranges = <&pfc 0 204 gpio-ranges = <&pfc 0 96 16>;
205 #interrupt-cells = <2> 205 #interrupt-cells = <2>;
206 interrupt-controller; 206 interrupt-controller;
207 clocks = <&cpg CPG_MOD 207 clocks = <&cpg CPG_MOD 909>;
208 power-domains = <&sysc 208 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
209 resets = <&cpg 909>; 209 resets = <&cpg 909>;
210 }; 210 };
211 211
212 gpio4: gpio@e6054000 { 212 gpio4: gpio@e6054000 {
213 compatible = "renesas, 213 compatible = "renesas,gpio-r8a774c0",
214 "renesas, 214 "renesas,rcar-gen3-gpio";
215 reg = <0 0xe6054000 0 215 reg = <0 0xe6054000 0 0x50>;
216 interrupts = <GIC_SPI 216 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
217 #gpio-cells = <2>; 217 #gpio-cells = <2>;
218 gpio-controller; 218 gpio-controller;
219 gpio-ranges = <&pfc 0 219 gpio-ranges = <&pfc 0 128 11>;
220 #interrupt-cells = <2> 220 #interrupt-cells = <2>;
221 interrupt-controller; 221 interrupt-controller;
222 clocks = <&cpg CPG_MOD 222 clocks = <&cpg CPG_MOD 908>;
223 power-domains = <&sysc 223 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
224 resets = <&cpg 908>; 224 resets = <&cpg 908>;
225 }; 225 };
226 226
227 gpio5: gpio@e6055000 { 227 gpio5: gpio@e6055000 {
228 compatible = "renesas, 228 compatible = "renesas,gpio-r8a774c0",
229 "renesas, 229 "renesas,rcar-gen3-gpio";
230 reg = <0 0xe6055000 0 230 reg = <0 0xe6055000 0 0x50>;
231 interrupts = <GIC_SPI 231 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
232 #gpio-cells = <2>; 232 #gpio-cells = <2>;
233 gpio-controller; 233 gpio-controller;
234 gpio-ranges = <&pfc 0 234 gpio-ranges = <&pfc 0 160 20>;
235 #interrupt-cells = <2> 235 #interrupt-cells = <2>;
236 interrupt-controller; 236 interrupt-controller;
237 clocks = <&cpg CPG_MOD 237 clocks = <&cpg CPG_MOD 907>;
238 power-domains = <&sysc 238 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
239 resets = <&cpg 907>; 239 resets = <&cpg 907>;
240 }; 240 };
241 241
242 gpio6: gpio@e6055400 { 242 gpio6: gpio@e6055400 {
243 compatible = "renesas, 243 compatible = "renesas,gpio-r8a774c0",
244 "renesas, 244 "renesas,rcar-gen3-gpio";
245 reg = <0 0xe6055400 0 245 reg = <0 0xe6055400 0 0x50>;
246 interrupts = <GIC_SPI 246 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
247 #gpio-cells = <2>; 247 #gpio-cells = <2>;
248 gpio-controller; 248 gpio-controller;
249 gpio-ranges = <&pfc 0 249 gpio-ranges = <&pfc 0 192 18>;
250 #interrupt-cells = <2> 250 #interrupt-cells = <2>;
251 interrupt-controller; 251 interrupt-controller;
252 clocks = <&cpg CPG_MOD 252 clocks = <&cpg CPG_MOD 906>;
253 power-domains = <&sysc 253 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
254 resets = <&cpg 906>; 254 resets = <&cpg 906>;
255 }; 255 };
256 256
257 pfc: pinctrl@e6060000 { 257 pfc: pinctrl@e6060000 {
258 compatible = "renesas, 258 compatible = "renesas,pfc-r8a774c0";
259 reg = <0 0xe6060000 0 259 reg = <0 0xe6060000 0 0x508>;
260 }; 260 };
261 261
262 cmt0: timer@e60f0000 { 262 cmt0: timer@e60f0000 {
263 compatible = "renesas, 263 compatible = "renesas,r8a774c0-cmt0",
264 "renesas, 264 "renesas,rcar-gen3-cmt0";
265 reg = <0 0xe60f0000 0 265 reg = <0 0xe60f0000 0 0x1004>;
266 interrupts = <GIC_SPI 266 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
267 <GIC_SPI 267 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
268 clocks = <&cpg CPG_MOD 268 clocks = <&cpg CPG_MOD 303>;
269 clock-names = "fck"; 269 clock-names = "fck";
270 power-domains = <&sysc 270 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
271 resets = <&cpg 303>; 271 resets = <&cpg 303>;
272 status = "disabled"; 272 status = "disabled";
273 }; 273 };
274 274
275 cmt1: timer@e6130000 { 275 cmt1: timer@e6130000 {
276 compatible = "renesas, 276 compatible = "renesas,r8a774c0-cmt1",
277 "renesas, 277 "renesas,rcar-gen3-cmt1";
278 reg = <0 0xe6130000 0 278 reg = <0 0xe6130000 0 0x1004>;
279 interrupts = <GIC_SPI 279 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
280 <GIC_SPI 280 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
281 <GIC_SPI 281 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
282 <GIC_SPI 282 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
283 <GIC_SPI 283 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
284 <GIC_SPI 284 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
285 <GIC_SPI 285 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
286 <GIC_SPI 286 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
287 clocks = <&cpg CPG_MOD 287 clocks = <&cpg CPG_MOD 302>;
288 clock-names = "fck"; 288 clock-names = "fck";
289 power-domains = <&sysc 289 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
290 resets = <&cpg 302>; 290 resets = <&cpg 302>;
291 status = "disabled"; 291 status = "disabled";
292 }; 292 };
293 293
294 cmt2: timer@e6140000 { 294 cmt2: timer@e6140000 {
295 compatible = "renesas, 295 compatible = "renesas,r8a774c0-cmt1",
296 "renesas, 296 "renesas,rcar-gen3-cmt1";
297 reg = <0 0xe6140000 0 297 reg = <0 0xe6140000 0 0x1004>;
298 interrupts = <GIC_SPI 298 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
299 <GIC_SPI 299 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
300 <GIC_SPI 300 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
301 <GIC_SPI 301 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
302 <GIC_SPI 302 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
303 <GIC_SPI 303 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
304 <GIC_SPI 304 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
305 <GIC_SPI 305 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
306 clocks = <&cpg CPG_MOD 306 clocks = <&cpg CPG_MOD 301>;
307 clock-names = "fck"; 307 clock-names = "fck";
308 power-domains = <&sysc 308 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
309 resets = <&cpg 301>; 309 resets = <&cpg 301>;
310 status = "disabled"; 310 status = "disabled";
311 }; 311 };
312 312
313 cmt3: timer@e6148000 { 313 cmt3: timer@e6148000 {
314 compatible = "renesas, 314 compatible = "renesas,r8a774c0-cmt1",
315 "renesas, 315 "renesas,rcar-gen3-cmt1";
316 reg = <0 0xe6148000 0 316 reg = <0 0xe6148000 0 0x1004>;
317 interrupts = <GIC_SPI 317 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
318 <GIC_SPI 318 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
319 <GIC_SPI 319 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
320 <GIC_SPI 320 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
321 <GIC_SPI 321 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
322 <GIC_SPI 322 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
323 <GIC_SPI 323 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
324 <GIC_SPI 324 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
325 clocks = <&cpg CPG_MOD 325 clocks = <&cpg CPG_MOD 300>;
326 clock-names = "fck"; 326 clock-names = "fck";
327 power-domains = <&sysc 327 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
328 resets = <&cpg 300>; 328 resets = <&cpg 300>;
329 status = "disabled"; 329 status = "disabled";
330 }; 330 };
331 331
332 cpg: clock-controller@e6150000 332 cpg: clock-controller@e6150000 {
333 compatible = "renesas, 333 compatible = "renesas,r8a774c0-cpg-mssr";
334 reg = <0 0xe6150000 0 334 reg = <0 0xe6150000 0 0x1000>;
335 clocks = <&extal_clk>; 335 clocks = <&extal_clk>;
336 clock-names = "extal"; 336 clock-names = "extal";
337 #clock-cells = <2>; 337 #clock-cells = <2>;
338 #power-domain-cells = 338 #power-domain-cells = <0>;
339 #reset-cells = <1>; 339 #reset-cells = <1>;
340 }; 340 };
341 341
342 rst: reset-controller@e6160000 342 rst: reset-controller@e6160000 {
343 compatible = "renesas, 343 compatible = "renesas,r8a774c0-rst";
344 reg = <0 0xe6160000 0 344 reg = <0 0xe6160000 0 0x0200>;
345 }; 345 };
346 346
347 sysc: system-controller@e61800 347 sysc: system-controller@e6180000 {
348 compatible = "renesas, 348 compatible = "renesas,r8a774c0-sysc";
349 reg = <0 0xe6180000 0 349 reg = <0 0xe6180000 0 0x0400>;
350 #power-domain-cells = 350 #power-domain-cells = <1>;
351 }; 351 };
352 352
353 thermal: thermal@e6190000 { 353 thermal: thermal@e6190000 {
354 compatible = "renesas, 354 compatible = "renesas,thermal-r8a774c0";
355 reg = <0 0xe6190000 0 355 reg = <0 0xe6190000 0 0x10>, <0 0xe6190100 0 0x38>;
356 interrupts = <GIC_SPI 356 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
357 <GIC_SPI 357 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
358 <GIC_SPI 358 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
359 clocks = <&cpg CPG_MOD 359 clocks = <&cpg CPG_MOD 522>;
360 power-domains = <&sysc 360 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
361 resets = <&cpg 522>; 361 resets = <&cpg 522>;
362 #thermal-sensor-cells 362 #thermal-sensor-cells = <0>;
363 }; 363 };
364 364
365 intc_ex: interrupt-controller@ 365 intc_ex: interrupt-controller@e61c0000 {
366 compatible = "renesas, 366 compatible = "renesas,intc-ex-r8a774c0", "renesas,irqc";
367 #interrupt-cells = <2> 367 #interrupt-cells = <2>;
368 interrupt-controller; 368 interrupt-controller;
369 reg = <0 0xe61c0000 0 369 reg = <0 0xe61c0000 0 0x200>;
370 interrupts = <GIC_SPI 370 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
371 <GIC_SPI 371 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
372 <GIC_SPI 372 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
373 <GIC_SPI 373 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
374 <GIC_SPI 374 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
375 <GIC_SPI 375 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
376 clocks = <&cpg CPG_MOD 376 clocks = <&cpg CPG_MOD 407>;
377 power-domains = <&sysc 377 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
378 resets = <&cpg 407>; 378 resets = <&cpg 407>;
379 }; 379 };
380 380
381 tmu0: timer@e61e0000 { 381 tmu0: timer@e61e0000 {
382 compatible = "renesas, 382 compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
383 reg = <0 0xe61e0000 0 383 reg = <0 0xe61e0000 0 0x30>;
384 interrupts = <GIC_SPI 384 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
385 <GIC_SPI 385 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
386 <GIC_SPI 386 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
387 interrupt-names = "tun <<
388 clocks = <&cpg CPG_MOD 387 clocks = <&cpg CPG_MOD 125>;
389 clock-names = "fck"; 388 clock-names = "fck";
390 power-domains = <&sysc 389 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
391 resets = <&cpg 125>; 390 resets = <&cpg 125>;
392 status = "disabled"; 391 status = "disabled";
393 }; 392 };
394 393
395 tmu1: timer@e6fc0000 { 394 tmu1: timer@e6fc0000 {
396 compatible = "renesas, 395 compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
397 reg = <0 0xe6fc0000 0 396 reg = <0 0xe6fc0000 0 0x30>;
398 interrupts = <GIC_SPI 397 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
399 <GIC_SPI 398 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
400 <GIC_SPI !! 399 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
401 <GIC_SPI <<
402 interrupt-names = "tun <<
403 clocks = <&cpg CPG_MOD 400 clocks = <&cpg CPG_MOD 124>;
404 clock-names = "fck"; 401 clock-names = "fck";
405 power-domains = <&sysc 402 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
406 resets = <&cpg 124>; 403 resets = <&cpg 124>;
407 status = "disabled"; 404 status = "disabled";
408 }; 405 };
409 406
410 tmu2: timer@e6fd0000 { 407 tmu2: timer@e6fd0000 {
411 compatible = "renesas, 408 compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
412 reg = <0 0xe6fd0000 0 409 reg = <0 0xe6fd0000 0 0x30>;
413 interrupts = <GIC_SPI 410 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
414 <GIC_SPI 411 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
415 <GIC_SPI !! 412 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
416 <GIC_SPI <<
417 interrupt-names = "tun <<
418 clocks = <&cpg CPG_MOD 413 clocks = <&cpg CPG_MOD 123>;
419 clock-names = "fck"; 414 clock-names = "fck";
420 power-domains = <&sysc 415 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
421 resets = <&cpg 123>; 416 resets = <&cpg 123>;
422 status = "disabled"; 417 status = "disabled";
423 }; 418 };
424 419
425 tmu3: timer@e6fe0000 { 420 tmu3: timer@e6fe0000 {
426 compatible = "renesas, 421 compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
427 reg = <0 0xe6fe0000 0 422 reg = <0 0xe6fe0000 0 0x30>;
428 interrupts = <GIC_SPI 423 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
429 <GIC_SPI 424 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
430 <GIC_SPI 425 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
431 interrupt-names = "tun <<
432 clocks = <&cpg CPG_MOD 426 clocks = <&cpg CPG_MOD 122>;
433 clock-names = "fck"; 427 clock-names = "fck";
434 power-domains = <&sysc 428 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
435 resets = <&cpg 122>; 429 resets = <&cpg 122>;
436 status = "disabled"; 430 status = "disabled";
437 }; 431 };
438 432
439 tmu4: timer@ffc00000 { 433 tmu4: timer@ffc00000 {
440 compatible = "renesas, 434 compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
441 reg = <0 0xffc00000 0 435 reg = <0 0xffc00000 0 0x30>;
442 interrupts = <GIC_SPI 436 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
443 <GIC_SPI 437 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
444 <GIC_SPI 438 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
445 interrupt-names = "tun <<
446 clocks = <&cpg CPG_MOD 439 clocks = <&cpg CPG_MOD 121>;
447 clock-names = "fck"; 440 clock-names = "fck";
448 power-domains = <&sysc 441 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
449 resets = <&cpg 121>; 442 resets = <&cpg 121>;
450 status = "disabled"; 443 status = "disabled";
451 }; 444 };
452 445
453 i2c0: i2c@e6500000 { 446 i2c0: i2c@e6500000 {
454 #address-cells = <1>; 447 #address-cells = <1>;
455 #size-cells = <0>; 448 #size-cells = <0>;
456 compatible = "renesas, 449 compatible = "renesas,i2c-r8a774c0",
457 "renesas, 450 "renesas,rcar-gen3-i2c";
458 reg = <0 0xe6500000 0 451 reg = <0 0xe6500000 0 0x40>;
459 interrupts = <GIC_SPI 452 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
460 clocks = <&cpg CPG_MOD 453 clocks = <&cpg CPG_MOD 931>;
461 power-domains = <&sysc 454 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
462 resets = <&cpg 931>; 455 resets = <&cpg 931>;
463 dmas = <&dmac1 0x91>, 456 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
464 <&dmac2 0x91>, 457 <&dmac2 0x91>, <&dmac2 0x90>;
465 dma-names = "tx", "rx" 458 dma-names = "tx", "rx", "tx", "rx";
466 i2c-scl-internal-delay 459 i2c-scl-internal-delay-ns = <110>;
467 status = "disabled"; 460 status = "disabled";
468 }; 461 };
469 462
470 i2c1: i2c@e6508000 { 463 i2c1: i2c@e6508000 {
471 #address-cells = <1>; 464 #address-cells = <1>;
472 #size-cells = <0>; 465 #size-cells = <0>;
473 compatible = "renesas, 466 compatible = "renesas,i2c-r8a774c0",
474 "renesas, 467 "renesas,rcar-gen3-i2c";
475 reg = <0 0xe6508000 0 468 reg = <0 0xe6508000 0 0x40>;
476 interrupts = <GIC_SPI 469 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
477 clocks = <&cpg CPG_MOD 470 clocks = <&cpg CPG_MOD 930>;
478 power-domains = <&sysc 471 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
479 resets = <&cpg 930>; 472 resets = <&cpg 930>;
480 dmas = <&dmac1 0x93>, 473 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
481 <&dmac2 0x93>, 474 <&dmac2 0x93>, <&dmac2 0x92>;
482 dma-names = "tx", "rx" 475 dma-names = "tx", "rx", "tx", "rx";
483 i2c-scl-internal-delay 476 i2c-scl-internal-delay-ns = <6>;
484 status = "disabled"; 477 status = "disabled";
485 }; 478 };
486 479
487 i2c2: i2c@e6510000 { 480 i2c2: i2c@e6510000 {
488 #address-cells = <1>; 481 #address-cells = <1>;
489 #size-cells = <0>; 482 #size-cells = <0>;
490 compatible = "renesas, 483 compatible = "renesas,i2c-r8a774c0",
491 "renesas, 484 "renesas,rcar-gen3-i2c";
492 reg = <0 0xe6510000 0 485 reg = <0 0xe6510000 0 0x40>;
493 interrupts = <GIC_SPI 486 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
494 clocks = <&cpg CPG_MOD 487 clocks = <&cpg CPG_MOD 929>;
495 power-domains = <&sysc 488 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
496 resets = <&cpg 929>; 489 resets = <&cpg 929>;
497 dmas = <&dmac1 0x95>, 490 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
498 <&dmac2 0x95>, 491 <&dmac2 0x95>, <&dmac2 0x94>;
499 dma-names = "tx", "rx" 492 dma-names = "tx", "rx", "tx", "rx";
500 i2c-scl-internal-delay 493 i2c-scl-internal-delay-ns = <6>;
501 status = "disabled"; 494 status = "disabled";
502 }; 495 };
503 496
504 i2c3: i2c@e66d0000 { 497 i2c3: i2c@e66d0000 {
505 #address-cells = <1>; 498 #address-cells = <1>;
506 #size-cells = <0>; 499 #size-cells = <0>;
507 compatible = "renesas, 500 compatible = "renesas,i2c-r8a774c0",
508 "renesas, 501 "renesas,rcar-gen3-i2c";
509 reg = <0 0xe66d0000 0 502 reg = <0 0xe66d0000 0 0x40>;
510 interrupts = <GIC_SPI 503 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
511 clocks = <&cpg CPG_MOD 504 clocks = <&cpg CPG_MOD 928>;
512 power-domains = <&sysc 505 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
513 resets = <&cpg 928>; 506 resets = <&cpg 928>;
514 dmas = <&dmac0 0x97>, 507 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
515 dma-names = "tx", "rx" 508 dma-names = "tx", "rx";
516 i2c-scl-internal-delay 509 i2c-scl-internal-delay-ns = <110>;
517 status = "disabled"; 510 status = "disabled";
518 }; 511 };
519 512
520 i2c4: i2c@e66d8000 { 513 i2c4: i2c@e66d8000 {
521 #address-cells = <1>; 514 #address-cells = <1>;
522 #size-cells = <0>; 515 #size-cells = <0>;
523 compatible = "renesas, 516 compatible = "renesas,i2c-r8a774c0",
524 "renesas, 517 "renesas,rcar-gen3-i2c";
525 reg = <0 0xe66d8000 0 518 reg = <0 0xe66d8000 0 0x40>;
526 interrupts = <GIC_SPI 519 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
527 clocks = <&cpg CPG_MOD 520 clocks = <&cpg CPG_MOD 927>;
528 power-domains = <&sysc 521 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
529 resets = <&cpg 927>; 522 resets = <&cpg 927>;
530 dmas = <&dmac0 0x99>, 523 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
531 dma-names = "tx", "rx" 524 dma-names = "tx", "rx";
532 i2c-scl-internal-delay 525 i2c-scl-internal-delay-ns = <6>;
533 status = "disabled"; 526 status = "disabled";
534 }; 527 };
535 528
536 i2c5: i2c@e66e0000 { 529 i2c5: i2c@e66e0000 {
537 #address-cells = <1>; 530 #address-cells = <1>;
538 #size-cells = <0>; 531 #size-cells = <0>;
539 compatible = "renesas, 532 compatible = "renesas,i2c-r8a774c0",
540 "renesas, 533 "renesas,rcar-gen3-i2c";
541 reg = <0 0xe66e0000 0 534 reg = <0 0xe66e0000 0 0x40>;
542 interrupts = <GIC_SPI 535 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
543 clocks = <&cpg CPG_MOD 536 clocks = <&cpg CPG_MOD 919>;
544 power-domains = <&sysc 537 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
545 resets = <&cpg 919>; 538 resets = <&cpg 919>;
546 dmas = <&dmac0 0x9b>, 539 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
547 dma-names = "tx", "rx" 540 dma-names = "tx", "rx";
548 i2c-scl-internal-delay 541 i2c-scl-internal-delay-ns = <6>;
549 status = "disabled"; 542 status = "disabled";
550 }; 543 };
551 544
552 i2c6: i2c@e66e8000 { 545 i2c6: i2c@e66e8000 {
553 #address-cells = <1>; 546 #address-cells = <1>;
554 #size-cells = <0>; 547 #size-cells = <0>;
555 compatible = "renesas, 548 compatible = "renesas,i2c-r8a774c0",
556 "renesas, 549 "renesas,rcar-gen3-i2c";
557 reg = <0 0xe66e8000 0 550 reg = <0 0xe66e8000 0 0x40>;
558 interrupts = <GIC_SPI 551 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
559 clocks = <&cpg CPG_MOD 552 clocks = <&cpg CPG_MOD 918>;
560 power-domains = <&sysc 553 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
561 resets = <&cpg 918>; 554 resets = <&cpg 918>;
562 dmas = <&dmac0 0x9d>, 555 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
563 dma-names = "tx", "rx" 556 dma-names = "tx", "rx";
564 i2c-scl-internal-delay 557 i2c-scl-internal-delay-ns = <6>;
565 status = "disabled"; 558 status = "disabled";
566 }; 559 };
567 560
568 i2c7: i2c@e6690000 { 561 i2c7: i2c@e6690000 {
569 #address-cells = <1>; 562 #address-cells = <1>;
570 #size-cells = <0>; 563 #size-cells = <0>;
571 compatible = "renesas, 564 compatible = "renesas,i2c-r8a774c0",
572 "renesas, 565 "renesas,rcar-gen3-i2c";
573 reg = <0 0xe6690000 0 566 reg = <0 0xe6690000 0 0x40>;
574 interrupts = <GIC_SPI 567 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
575 clocks = <&cpg CPG_MOD 568 clocks = <&cpg CPG_MOD 1003>;
576 power-domains = <&sysc 569 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
577 resets = <&cpg 1003>; 570 resets = <&cpg 1003>;
578 i2c-scl-internal-delay 571 i2c-scl-internal-delay-ns = <6>;
579 status = "disabled"; 572 status = "disabled";
580 }; 573 };
581 574
582 iic_pmic: i2c@e60b0000 { 575 iic_pmic: i2c@e60b0000 {
583 #address-cells = <1>; 576 #address-cells = <1>;
584 #size-cells = <0>; 577 #size-cells = <0>;
585 compatible = "renesas, 578 compatible = "renesas,iic-r8a774c0",
586 "renesas, 579 "renesas,rcar-gen3-iic",
587 "renesas, 580 "renesas,rmobile-iic";
588 reg = <0 0xe60b0000 0 581 reg = <0 0xe60b0000 0 0x425>;
589 interrupts = <GIC_SPI 582 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
590 clocks = <&cpg CPG_MOD 583 clocks = <&cpg CPG_MOD 926>;
591 power-domains = <&sysc 584 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
592 resets = <&cpg 926>; 585 resets = <&cpg 926>;
593 dmas = <&dmac0 0x11>, 586 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
594 dma-names = "tx", "rx" 587 dma-names = "tx", "rx";
595 status = "disabled"; 588 status = "disabled";
596 }; 589 };
597 590
598 hscif0: serial@e6540000 { 591 hscif0: serial@e6540000 {
599 compatible = "renesas, 592 compatible = "renesas,hscif-r8a774c0",
600 "renesas, 593 "renesas,rcar-gen3-hscif",
601 "renesas, 594 "renesas,hscif";
602 reg = <0 0xe6540000 0 595 reg = <0 0xe6540000 0 0x60>;
603 interrupts = <GIC_SPI 596 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
604 clocks = <&cpg CPG_MOD 597 clocks = <&cpg CPG_MOD 520>,
605 <&cpg CPG_COR 598 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
606 <&scif_clk>; 599 <&scif_clk>;
607 clock-names = "fck", " 600 clock-names = "fck", "brg_int", "scif_clk";
608 dmas = <&dmac1 0x31>, 601 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
609 <&dmac2 0x31>, 602 <&dmac2 0x31>, <&dmac2 0x30>;
610 dma-names = "tx", "rx" 603 dma-names = "tx", "rx", "tx", "rx";
611 power-domains = <&sysc 604 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
612 resets = <&cpg 520>; 605 resets = <&cpg 520>;
613 status = "disabled"; 606 status = "disabled";
614 }; 607 };
615 608
616 hscif1: serial@e6550000 { 609 hscif1: serial@e6550000 {
617 compatible = "renesas, 610 compatible = "renesas,hscif-r8a774c0",
618 "renesas, 611 "renesas,rcar-gen3-hscif",
619 "renesas, 612 "renesas,hscif";
620 reg = <0 0xe6550000 0 613 reg = <0 0xe6550000 0 0x60>;
621 interrupts = <GIC_SPI 614 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
622 clocks = <&cpg CPG_MOD 615 clocks = <&cpg CPG_MOD 519>,
623 <&cpg CPG_COR 616 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
624 <&scif_clk>; 617 <&scif_clk>;
625 clock-names = "fck", " 618 clock-names = "fck", "brg_int", "scif_clk";
626 dmas = <&dmac1 0x33>, 619 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
627 <&dmac2 0x33>, 620 <&dmac2 0x33>, <&dmac2 0x32>;
628 dma-names = "tx", "rx" 621 dma-names = "tx", "rx", "tx", "rx";
629 power-domains = <&sysc 622 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
630 resets = <&cpg 519>; 623 resets = <&cpg 519>;
631 status = "disabled"; 624 status = "disabled";
632 }; 625 };
633 626
634 hscif2: serial@e6560000 { 627 hscif2: serial@e6560000 {
635 compatible = "renesas, 628 compatible = "renesas,hscif-r8a774c0",
636 "renesas, 629 "renesas,rcar-gen3-hscif",
637 "renesas, 630 "renesas,hscif";
638 reg = <0 0xe6560000 0 631 reg = <0 0xe6560000 0 0x60>;
639 interrupts = <GIC_SPI 632 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
640 clocks = <&cpg CPG_MOD 633 clocks = <&cpg CPG_MOD 518>,
641 <&cpg CPG_COR 634 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
642 <&scif_clk>; 635 <&scif_clk>;
643 clock-names = "fck", " 636 clock-names = "fck", "brg_int", "scif_clk";
644 dmas = <&dmac1 0x35>, 637 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
645 <&dmac2 0x35>, 638 <&dmac2 0x35>, <&dmac2 0x34>;
646 dma-names = "tx", "rx" 639 dma-names = "tx", "rx", "tx", "rx";
647 power-domains = <&sysc 640 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
648 resets = <&cpg 518>; 641 resets = <&cpg 518>;
649 status = "disabled"; 642 status = "disabled";
650 }; 643 };
651 644
652 hscif3: serial@e66a0000 { 645 hscif3: serial@e66a0000 {
653 compatible = "renesas, 646 compatible = "renesas,hscif-r8a774c0",
654 "renesas, 647 "renesas,rcar-gen3-hscif",
655 "renesas, 648 "renesas,hscif";
656 reg = <0 0xe66a0000 0 649 reg = <0 0xe66a0000 0 0x60>;
657 interrupts = <GIC_SPI 650 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
658 clocks = <&cpg CPG_MOD 651 clocks = <&cpg CPG_MOD 517>,
659 <&cpg CPG_COR 652 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
660 <&scif_clk>; 653 <&scif_clk>;
661 clock-names = "fck", " 654 clock-names = "fck", "brg_int", "scif_clk";
662 dmas = <&dmac0 0x37>, 655 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
663 dma-names = "tx", "rx" 656 dma-names = "tx", "rx";
664 power-domains = <&sysc 657 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
665 resets = <&cpg 517>; 658 resets = <&cpg 517>;
666 status = "disabled"; 659 status = "disabled";
667 }; 660 };
668 661
669 hscif4: serial@e66b0000 { 662 hscif4: serial@e66b0000 {
670 compatible = "renesas, 663 compatible = "renesas,hscif-r8a774c0",
671 "renesas, 664 "renesas,rcar-gen3-hscif",
672 "renesas, 665 "renesas,hscif";
673 reg = <0 0xe66b0000 0 666 reg = <0 0xe66b0000 0 0x60>;
674 interrupts = <GIC_SPI 667 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
675 clocks = <&cpg CPG_MOD 668 clocks = <&cpg CPG_MOD 516>,
676 <&cpg CPG_COR 669 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
677 <&scif_clk>; 670 <&scif_clk>;
678 clock-names = "fck", " 671 clock-names = "fck", "brg_int", "scif_clk";
679 dmas = <&dmac0 0x39>, 672 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
680 dma-names = "tx", "rx" 673 dma-names = "tx", "rx";
681 power-domains = <&sysc 674 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
682 resets = <&cpg 516>; 675 resets = <&cpg 516>;
683 status = "disabled"; 676 status = "disabled";
684 }; 677 };
685 678
686 hsusb: usb@e6590000 { 679 hsusb: usb@e6590000 {
687 compatible = "renesas, 680 compatible = "renesas,usbhs-r8a774c0",
688 "renesas, 681 "renesas,rcar-gen3-usbhs";
689 reg = <0 0xe6590000 0 682 reg = <0 0xe6590000 0 0x200>;
690 interrupts = <GIC_SPI 683 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
691 clocks = <&cpg CPG_MOD 684 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
692 dmas = <&usb_dmac0 0>, 685 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
693 <&usb_dmac1 0>, 686 <&usb_dmac1 0>, <&usb_dmac1 1>;
694 dma-names = "ch0", "ch 687 dma-names = "ch0", "ch1", "ch2", "ch3";
695 renesas,buswait = <11> 688 renesas,buswait = <11>;
696 phys = <&usb2_phy0 3>; 689 phys = <&usb2_phy0 3>;
697 phy-names = "usb"; 690 phy-names = "usb";
698 power-domains = <&sysc 691 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
699 resets = <&cpg 704>, < 692 resets = <&cpg 704>, <&cpg 703>;
700 status = "disabled"; 693 status = "disabled";
701 }; 694 };
702 695
703 usb_dmac0: dma-controller@e65a 696 usb_dmac0: dma-controller@e65a0000 {
704 compatible = "renesas, 697 compatible = "renesas,r8a774c0-usb-dmac",
705 "renesas, 698 "renesas,usb-dmac";
706 reg = <0 0xe65a0000 0 699 reg = <0 0xe65a0000 0 0x100>;
707 interrupts = <GIC_SPI 700 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
708 <GIC_SPI 701 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
709 interrupt-names = "ch0 702 interrupt-names = "ch0", "ch1";
710 clocks = <&cpg CPG_MOD 703 clocks = <&cpg CPG_MOD 330>;
711 power-domains = <&sysc 704 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
712 resets = <&cpg 330>; 705 resets = <&cpg 330>;
713 #dma-cells = <1>; 706 #dma-cells = <1>;
714 dma-channels = <2>; 707 dma-channels = <2>;
715 }; 708 };
716 709
717 usb_dmac1: dma-controller@e65b 710 usb_dmac1: dma-controller@e65b0000 {
718 compatible = "renesas, 711 compatible = "renesas,r8a774c0-usb-dmac",
719 "renesas, 712 "renesas,usb-dmac";
720 reg = <0 0xe65b0000 0 713 reg = <0 0xe65b0000 0 0x100>;
721 interrupts = <GIC_SPI 714 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
722 <GIC_SPI 715 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
723 interrupt-names = "ch0 716 interrupt-names = "ch0", "ch1";
724 clocks = <&cpg CPG_MOD 717 clocks = <&cpg CPG_MOD 331>;
725 power-domains = <&sysc 718 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
726 resets = <&cpg 331>; 719 resets = <&cpg 331>;
727 #dma-cells = <1>; 720 #dma-cells = <1>;
728 dma-channels = <2>; 721 dma-channels = <2>;
729 }; 722 };
730 723
731 dmac0: dma-controller@e6700000 724 dmac0: dma-controller@e6700000 {
732 compatible = "renesas, 725 compatible = "renesas,dmac-r8a774c0",
733 "renesas, 726 "renesas,rcar-dmac";
734 reg = <0 0xe6700000 0 727 reg = <0 0xe6700000 0 0x10000>;
735 interrupts = <GIC_SPI 728 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
736 <GIC_SPI 729 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
737 <GIC_SPI 730 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
738 <GIC_SPI 731 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
739 <GIC_SPI 732 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
740 <GIC_SPI 733 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
741 <GIC_SPI 734 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
742 <GIC_SPI 735 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
743 <GIC_SPI 736 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
744 <GIC_SPI 737 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
745 <GIC_SPI 738 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
746 <GIC_SPI 739 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
747 <GIC_SPI 740 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
748 <GIC_SPI 741 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
749 <GIC_SPI 742 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
750 <GIC_SPI 743 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
751 <GIC_SPI 744 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
752 interrupt-names = "err 745 interrupt-names = "error",
753 "ch0", 746 "ch0", "ch1", "ch2", "ch3",
754 "ch4", 747 "ch4", "ch5", "ch6", "ch7",
755 "ch8", 748 "ch8", "ch9", "ch10", "ch11",
756 "ch12" 749 "ch12", "ch13", "ch14", "ch15";
757 clocks = <&cpg CPG_MOD 750 clocks = <&cpg CPG_MOD 219>;
758 clock-names = "fck"; 751 clock-names = "fck";
759 power-domains = <&sysc 752 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
760 resets = <&cpg 219>; 753 resets = <&cpg 219>;
761 #dma-cells = <1>; 754 #dma-cells = <1>;
762 dma-channels = <16>; 755 dma-channels = <16>;
763 iommus = <&ipmmu_ds0 0 756 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
764 <&ipmmu_ds0 2>, 757 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
765 <&ipmmu_ds0 4>, 758 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
766 <&ipmmu_ds0 6>, 759 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
767 <&ipmmu_ds0 8>, 760 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
768 <&ipmmu_ds0 10> 761 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
769 <&ipmmu_ds0 12> 762 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
770 <&ipmmu_ds0 14> 763 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
771 }; 764 };
772 765
773 dmac1: dma-controller@e7300000 766 dmac1: dma-controller@e7300000 {
774 compatible = "renesas, 767 compatible = "renesas,dmac-r8a774c0",
775 "renesas, 768 "renesas,rcar-dmac";
776 reg = <0 0xe7300000 0 769 reg = <0 0xe7300000 0 0x10000>;
777 interrupts = <GIC_SPI 770 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
778 <GIC_SPI 771 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
779 <GIC_SPI 772 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
780 <GIC_SPI 773 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
781 <GIC_SPI 774 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
782 <GIC_SPI 775 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
783 <GIC_SPI 776 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
784 <GIC_SPI 777 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
785 <GIC_SPI 778 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
786 <GIC_SPI 779 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
787 <GIC_SPI 780 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
788 <GIC_SPI 781 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
789 <GIC_SPI 782 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
790 <GIC_SPI 783 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
791 <GIC_SPI 784 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
792 <GIC_SPI 785 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
793 <GIC_SPI 786 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
794 interrupt-names = "err 787 interrupt-names = "error",
795 "ch0", 788 "ch0", "ch1", "ch2", "ch3",
796 "ch4", 789 "ch4", "ch5", "ch6", "ch7",
797 "ch8", 790 "ch8", "ch9", "ch10", "ch11",
798 "ch12" 791 "ch12", "ch13", "ch14", "ch15";
799 clocks = <&cpg CPG_MOD 792 clocks = <&cpg CPG_MOD 218>;
800 clock-names = "fck"; 793 clock-names = "fck";
801 power-domains = <&sysc 794 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
802 resets = <&cpg 218>; 795 resets = <&cpg 218>;
803 #dma-cells = <1>; 796 #dma-cells = <1>;
804 dma-channels = <16>; 797 dma-channels = <16>;
805 iommus = <&ipmmu_ds1 0 798 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
806 <&ipmmu_ds1 2>, 799 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
807 <&ipmmu_ds1 4>, 800 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
808 <&ipmmu_ds1 6>, 801 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
809 <&ipmmu_ds1 8>, 802 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
810 <&ipmmu_ds1 10> 803 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
811 <&ipmmu_ds1 12> 804 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
812 <&ipmmu_ds1 14> 805 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
813 }; 806 };
814 807
815 dmac2: dma-controller@e7310000 808 dmac2: dma-controller@e7310000 {
816 compatible = "renesas, 809 compatible = "renesas,dmac-r8a774c0",
817 "renesas, 810 "renesas,rcar-dmac";
818 reg = <0 0xe7310000 0 811 reg = <0 0xe7310000 0 0x10000>;
819 interrupts = <GIC_SPI 812 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
820 <GIC_SPI 813 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
821 <GIC_SPI 814 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
822 <GIC_SPI 815 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
823 <GIC_SPI 816 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
824 <GIC_SPI 817 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
825 <GIC_SPI 818 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
826 <GIC_SPI 819 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
827 <GIC_SPI 820 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
828 <GIC_SPI 821 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
829 <GIC_SPI 822 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
830 <GIC_SPI 823 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
831 <GIC_SPI 824 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
832 <GIC_SPI 825 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
833 <GIC_SPI 826 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
834 <GIC_SPI 827 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
835 <GIC_SPI 828 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
836 interrupt-names = "err 829 interrupt-names = "error",
837 "ch0", 830 "ch0", "ch1", "ch2", "ch3",
838 "ch4", 831 "ch4", "ch5", "ch6", "ch7",
839 "ch8", 832 "ch8", "ch9", "ch10", "ch11",
840 "ch12" 833 "ch12", "ch13", "ch14", "ch15";
841 clocks = <&cpg CPG_MOD 834 clocks = <&cpg CPG_MOD 217>;
842 clock-names = "fck"; 835 clock-names = "fck";
843 power-domains = <&sysc 836 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
844 resets = <&cpg 217>; 837 resets = <&cpg 217>;
845 #dma-cells = <1>; 838 #dma-cells = <1>;
846 dma-channels = <16>; 839 dma-channels = <16>;
847 iommus = <&ipmmu_ds1 1 840 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
848 <&ipmmu_ds1 18> 841 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
849 <&ipmmu_ds1 20> 842 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
850 <&ipmmu_ds1 22> 843 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
851 <&ipmmu_ds1 24> 844 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
852 <&ipmmu_ds1 26> 845 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
853 <&ipmmu_ds1 28> 846 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
854 <&ipmmu_ds1 30> 847 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
855 }; 848 };
856 849
857 ipmmu_ds0: iommu@e6740000 { 850 ipmmu_ds0: iommu@e6740000 {
858 compatible = "renesas, 851 compatible = "renesas,ipmmu-r8a774c0";
859 reg = <0 0xe6740000 0 852 reg = <0 0xe6740000 0 0x1000>;
860 renesas,ipmmu-main = < 853 renesas,ipmmu-main = <&ipmmu_mm 0>;
861 power-domains = <&sysc 854 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
862 #iommu-cells = <1>; 855 #iommu-cells = <1>;
863 }; 856 };
864 857
865 ipmmu_ds1: iommu@e7740000 { 858 ipmmu_ds1: iommu@e7740000 {
866 compatible = "renesas, 859 compatible = "renesas,ipmmu-r8a774c0";
867 reg = <0 0xe7740000 0 860 reg = <0 0xe7740000 0 0x1000>;
868 renesas,ipmmu-main = < 861 renesas,ipmmu-main = <&ipmmu_mm 1>;
869 power-domains = <&sysc 862 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
870 #iommu-cells = <1>; 863 #iommu-cells = <1>;
871 }; 864 };
872 865
873 ipmmu_hc: iommu@e6570000 { 866 ipmmu_hc: iommu@e6570000 {
874 compatible = "renesas, 867 compatible = "renesas,ipmmu-r8a774c0";
875 reg = <0 0xe6570000 0 868 reg = <0 0xe6570000 0 0x1000>;
876 renesas,ipmmu-main = < 869 renesas,ipmmu-main = <&ipmmu_mm 2>;
877 power-domains = <&sysc 870 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
878 #iommu-cells = <1>; 871 #iommu-cells = <1>;
879 }; 872 };
880 873
881 ipmmu_mm: iommu@e67b0000 { 874 ipmmu_mm: iommu@e67b0000 {
882 compatible = "renesas, 875 compatible = "renesas,ipmmu-r8a774c0";
883 reg = <0 0xe67b0000 0 876 reg = <0 0xe67b0000 0 0x1000>;
884 interrupts = <GIC_SPI 877 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
885 <GIC_SPI 878 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
886 power-domains = <&sysc 879 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
887 #iommu-cells = <1>; 880 #iommu-cells = <1>;
888 }; 881 };
889 882
890 ipmmu_mp: iommu@ec670000 { 883 ipmmu_mp: iommu@ec670000 {
891 compatible = "renesas, 884 compatible = "renesas,ipmmu-r8a774c0";
892 reg = <0 0xec670000 0 885 reg = <0 0xec670000 0 0x1000>;
893 renesas,ipmmu-main = < 886 renesas,ipmmu-main = <&ipmmu_mm 4>;
894 power-domains = <&sysc 887 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
895 #iommu-cells = <1>; 888 #iommu-cells = <1>;
896 }; 889 };
897 890
898 ipmmu_pv0: iommu@fd800000 { 891 ipmmu_pv0: iommu@fd800000 {
899 compatible = "renesas, 892 compatible = "renesas,ipmmu-r8a774c0";
900 reg = <0 0xfd800000 0 893 reg = <0 0xfd800000 0 0x1000>;
901 renesas,ipmmu-main = < 894 renesas,ipmmu-main = <&ipmmu_mm 6>;
902 power-domains = <&sysc 895 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
903 #iommu-cells = <1>; 896 #iommu-cells = <1>;
904 }; 897 };
905 898
906 ipmmu_vc0: iommu@fe6b0000 { 899 ipmmu_vc0: iommu@fe6b0000 {
907 compatible = "renesas, 900 compatible = "renesas,ipmmu-r8a774c0";
908 reg = <0 0xfe6b0000 0 901 reg = <0 0xfe6b0000 0 0x1000>;
909 renesas,ipmmu-main = < 902 renesas,ipmmu-main = <&ipmmu_mm 12>;
910 power-domains = <&sysc 903 power-domains = <&sysc R8A774C0_PD_A3VC>;
911 #iommu-cells = <1>; 904 #iommu-cells = <1>;
912 }; 905 };
913 906
914 ipmmu_vi0: iommu@febd0000 { 907 ipmmu_vi0: iommu@febd0000 {
915 compatible = "renesas, 908 compatible = "renesas,ipmmu-r8a774c0";
916 reg = <0 0xfebd0000 0 909 reg = <0 0xfebd0000 0 0x1000>;
917 renesas,ipmmu-main = < 910 renesas,ipmmu-main = <&ipmmu_mm 14>;
918 power-domains = <&sysc 911 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
919 #iommu-cells = <1>; 912 #iommu-cells = <1>;
920 }; 913 };
921 914
922 ipmmu_vp0: iommu@fe990000 { 915 ipmmu_vp0: iommu@fe990000 {
923 compatible = "renesas, 916 compatible = "renesas,ipmmu-r8a774c0";
924 reg = <0 0xfe990000 0 917 reg = <0 0xfe990000 0 0x1000>;
925 renesas,ipmmu-main = < 918 renesas,ipmmu-main = <&ipmmu_mm 16>;
926 power-domains = <&sysc 919 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
927 #iommu-cells = <1>; 920 #iommu-cells = <1>;
928 }; 921 };
929 922
930 avb: ethernet@e6800000 { 923 avb: ethernet@e6800000 {
931 compatible = "renesas, 924 compatible = "renesas,etheravb-r8a774c0",
932 "renesas, 925 "renesas,etheravb-rcar-gen3";
933 reg = <0 0xe6800000 0 926 reg = <0 0xe6800000 0 0x800>;
934 interrupts = <GIC_SPI 927 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
935 <GIC_SPI 928 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
936 <GIC_SPI 929 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
937 <GIC_SPI 930 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
938 <GIC_SPI 931 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
939 <GIC_SPI 932 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
940 <GIC_SPI 933 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
941 <GIC_SPI 934 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
942 <GIC_SPI 935 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
943 <GIC_SPI 936 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
944 <GIC_SPI 937 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
945 <GIC_SPI 938 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
946 <GIC_SPI 939 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
947 <GIC_SPI 940 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
948 <GIC_SPI 941 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
949 <GIC_SPI 942 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
950 <GIC_SPI 943 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
951 <GIC_SPI 944 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
952 <GIC_SPI 945 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
953 <GIC_SPI 946 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
954 <GIC_SPI 947 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
955 <GIC_SPI 948 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
956 <GIC_SPI 949 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
957 <GIC_SPI 950 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
958 <GIC_SPI 951 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
959 interrupt-names = "ch0 952 interrupt-names = "ch0", "ch1", "ch2", "ch3",
960 "ch4 953 "ch4", "ch5", "ch6", "ch7",
961 "ch8 954 "ch8", "ch9", "ch10", "ch11",
962 "ch1 955 "ch12", "ch13", "ch14", "ch15",
963 "ch1 956 "ch16", "ch17", "ch18", "ch19",
964 "ch2 957 "ch20", "ch21", "ch22", "ch23",
965 "ch2 958 "ch24";
966 clocks = <&cpg CPG_MOD 959 clocks = <&cpg CPG_MOD 812>;
967 clock-names = "fck"; 960 clock-names = "fck";
968 power-domains = <&sysc 961 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
969 resets = <&cpg 812>; 962 resets = <&cpg 812>;
970 phy-mode = "rgmii"; 963 phy-mode = "rgmii";
971 rx-internal-delay-ps = 964 rx-internal-delay-ps = <0>;
972 iommus = <&ipmmu_ds0 1 965 iommus = <&ipmmu_ds0 16>;
973 #address-cells = <1>; 966 #address-cells = <1>;
974 #size-cells = <0>; 967 #size-cells = <0>;
975 status = "disabled"; 968 status = "disabled";
976 }; 969 };
977 970
978 can0: can@e6c30000 { 971 can0: can@e6c30000 {
979 compatible = "renesas, 972 compatible = "renesas,can-r8a774c0",
980 "renesas, 973 "renesas,rcar-gen3-can";
981 reg = <0 0xe6c30000 0 974 reg = <0 0xe6c30000 0 0x1000>;
982 interrupts = <GIC_SPI 975 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
983 clocks = <&cpg CPG_MOD 976 clocks = <&cpg CPG_MOD 916>,
984 <&cpg CPG_COR 977 <&cpg CPG_CORE R8A774C0_CLK_CANFD>,
985 <&can_clk>; 978 <&can_clk>;
986 clock-names = "clkp1", 979 clock-names = "clkp1", "clkp2", "can_clk";
987 assigned-clocks = <&cp 980 assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>;
988 assigned-clock-rates = 981 assigned-clock-rates = <40000000>;
989 power-domains = <&sysc 982 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
990 resets = <&cpg 916>; 983 resets = <&cpg 916>;
991 status = "disabled"; 984 status = "disabled";
992 }; 985 };
993 986
994 can1: can@e6c38000 { 987 can1: can@e6c38000 {
995 compatible = "renesas, 988 compatible = "renesas,can-r8a774c0",
996 "renesas, 989 "renesas,rcar-gen3-can";
997 reg = <0 0xe6c38000 0 990 reg = <0 0xe6c38000 0 0x1000>;
998 interrupts = <GIC_SPI 991 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
999 clocks = <&cpg CPG_MOD 992 clocks = <&cpg CPG_MOD 915>,
1000 <&cpg CPG_CO 993 <&cpg CPG_CORE R8A774C0_CLK_CANFD>,
1001 <&can_clk>; 994 <&can_clk>;
1002 clock-names = "clkp1" 995 clock-names = "clkp1", "clkp2", "can_clk";
1003 assigned-clocks = <&c 996 assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>;
1004 assigned-clock-rates 997 assigned-clock-rates = <40000000>;
1005 power-domains = <&sys 998 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1006 resets = <&cpg 915>; 999 resets = <&cpg 915>;
1007 status = "disabled"; 1000 status = "disabled";
1008 }; 1001 };
1009 1002
1010 canfd: can@e66c0000 { 1003 canfd: can@e66c0000 {
1011 compatible = "renesas 1004 compatible = "renesas,r8a774c0-canfd",
1012 "renesas 1005 "renesas,rcar-gen3-canfd";
1013 reg = <0 0xe66c0000 0 1006 reg = <0 0xe66c0000 0 0x8000>;
1014 interrupts = <GIC_SPI 1007 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
1015 <GIC_SPI 1008 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1016 interrupt-names = "ch 1009 interrupt-names = "ch_int", "g_int";
1017 clocks = <&cpg CPG_MO 1010 clocks = <&cpg CPG_MOD 914>,
1018 <&cpg CPG_CO 1011 <&cpg CPG_CORE R8A774C0_CLK_CANFD>,
1019 <&can_clk>; 1012 <&can_clk>;
1020 clock-names = "fck", 1013 clock-names = "fck", "canfd", "can_clk";
1021 assigned-clocks = <&c 1014 assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>;
1022 assigned-clock-rates 1015 assigned-clock-rates = <40000000>;
1023 power-domains = <&sys 1016 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1024 resets = <&cpg 914>; 1017 resets = <&cpg 914>;
1025 status = "disabled"; 1018 status = "disabled";
1026 1019
1027 channel0 { 1020 channel0 {
1028 status = "dis 1021 status = "disabled";
1029 }; 1022 };
1030 1023
1031 channel1 { 1024 channel1 {
1032 status = "dis 1025 status = "disabled";
1033 }; 1026 };
1034 }; 1027 };
1035 1028
1036 pwm0: pwm@e6e30000 { 1029 pwm0: pwm@e6e30000 {
1037 compatible = "renesas 1030 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1038 reg = <0 0xe6e30000 0 1031 reg = <0 0xe6e30000 0 0x8>;
1039 clocks = <&cpg CPG_MO 1032 clocks = <&cpg CPG_MOD 523>;
1040 power-domains = <&sys 1033 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1041 resets = <&cpg 523>; 1034 resets = <&cpg 523>;
1042 #pwm-cells = <2>; 1035 #pwm-cells = <2>;
1043 status = "disabled"; 1036 status = "disabled";
1044 }; 1037 };
1045 1038
1046 pwm1: pwm@e6e31000 { 1039 pwm1: pwm@e6e31000 {
1047 compatible = "renesas 1040 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1048 reg = <0 0xe6e31000 0 1041 reg = <0 0xe6e31000 0 0x8>;
1049 clocks = <&cpg CPG_MO 1042 clocks = <&cpg CPG_MOD 523>;
1050 power-domains = <&sys 1043 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1051 resets = <&cpg 523>; 1044 resets = <&cpg 523>;
1052 #pwm-cells = <2>; 1045 #pwm-cells = <2>;
1053 status = "disabled"; 1046 status = "disabled";
1054 }; 1047 };
1055 1048
1056 pwm2: pwm@e6e32000 { 1049 pwm2: pwm@e6e32000 {
1057 compatible = "renesas 1050 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1058 reg = <0 0xe6e32000 0 1051 reg = <0 0xe6e32000 0 0x8>;
1059 clocks = <&cpg CPG_MO 1052 clocks = <&cpg CPG_MOD 523>;
1060 power-domains = <&sys 1053 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1061 resets = <&cpg 523>; 1054 resets = <&cpg 523>;
1062 #pwm-cells = <2>; 1055 #pwm-cells = <2>;
1063 status = "disabled"; 1056 status = "disabled";
1064 }; 1057 };
1065 1058
1066 pwm3: pwm@e6e33000 { 1059 pwm3: pwm@e6e33000 {
1067 compatible = "renesas 1060 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1068 reg = <0 0xe6e33000 0 1061 reg = <0 0xe6e33000 0 0x8>;
1069 clocks = <&cpg CPG_MO 1062 clocks = <&cpg CPG_MOD 523>;
1070 power-domains = <&sys 1063 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1071 resets = <&cpg 523>; 1064 resets = <&cpg 523>;
1072 #pwm-cells = <2>; 1065 #pwm-cells = <2>;
1073 status = "disabled"; 1066 status = "disabled";
1074 }; 1067 };
1075 1068
1076 pwm4: pwm@e6e34000 { 1069 pwm4: pwm@e6e34000 {
1077 compatible = "renesas 1070 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1078 reg = <0 0xe6e34000 0 1071 reg = <0 0xe6e34000 0 0x8>;
1079 clocks = <&cpg CPG_MO 1072 clocks = <&cpg CPG_MOD 523>;
1080 power-domains = <&sys 1073 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1081 resets = <&cpg 523>; 1074 resets = <&cpg 523>;
1082 #pwm-cells = <2>; 1075 #pwm-cells = <2>;
1083 status = "disabled"; 1076 status = "disabled";
1084 }; 1077 };
1085 1078
1086 pwm5: pwm@e6e35000 { 1079 pwm5: pwm@e6e35000 {
1087 compatible = "renesas 1080 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1088 reg = <0 0xe6e35000 0 1081 reg = <0 0xe6e35000 0 0x8>;
1089 clocks = <&cpg CPG_MO 1082 clocks = <&cpg CPG_MOD 523>;
1090 power-domains = <&sys 1083 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1091 resets = <&cpg 523>; 1084 resets = <&cpg 523>;
1092 #pwm-cells = <2>; 1085 #pwm-cells = <2>;
1093 status = "disabled"; 1086 status = "disabled";
1094 }; 1087 };
1095 1088
1096 pwm6: pwm@e6e36000 { 1089 pwm6: pwm@e6e36000 {
1097 compatible = "renesas 1090 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
1098 reg = <0 0xe6e36000 0 1091 reg = <0 0xe6e36000 0 0x8>;
1099 clocks = <&cpg CPG_MO 1092 clocks = <&cpg CPG_MOD 523>;
1100 power-domains = <&sys 1093 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1101 resets = <&cpg 523>; 1094 resets = <&cpg 523>;
1102 #pwm-cells = <2>; 1095 #pwm-cells = <2>;
1103 status = "disabled"; 1096 status = "disabled";
1104 }; 1097 };
1105 1098
1106 scif0: serial@e6e60000 { 1099 scif0: serial@e6e60000 {
1107 compatible = "renesas 1100 compatible = "renesas,scif-r8a774c0",
1108 "renesas 1101 "renesas,rcar-gen3-scif", "renesas,scif";
1109 reg = <0 0xe6e60000 0 1102 reg = <0 0xe6e60000 0 64>;
1110 interrupts = <GIC_SPI 1103 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
1111 clocks = <&cpg CPG_MO 1104 clocks = <&cpg CPG_MOD 207>,
1112 <&cpg CPG_CO 1105 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
1113 <&scif_clk>; 1106 <&scif_clk>;
1114 clock-names = "fck", 1107 clock-names = "fck", "brg_int", "scif_clk";
1115 dmas = <&dmac1 0x51>, 1108 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1116 <&dmac2 0x51>, 1109 <&dmac2 0x51>, <&dmac2 0x50>;
1117 dma-names = "tx", "rx 1110 dma-names = "tx", "rx", "tx", "rx";
1118 power-domains = <&sys 1111 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1119 resets = <&cpg 207>; 1112 resets = <&cpg 207>;
1120 status = "disabled"; 1113 status = "disabled";
1121 }; 1114 };
1122 1115
1123 scif1: serial@e6e68000 { 1116 scif1: serial@e6e68000 {
1124 compatible = "renesas 1117 compatible = "renesas,scif-r8a774c0",
1125 "renesas 1118 "renesas,rcar-gen3-scif", "renesas,scif";
1126 reg = <0 0xe6e68000 0 1119 reg = <0 0xe6e68000 0 64>;
1127 interrupts = <GIC_SPI 1120 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
1128 clocks = <&cpg CPG_MO 1121 clocks = <&cpg CPG_MOD 206>,
1129 <&cpg CPG_CO 1122 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
1130 <&scif_clk>; 1123 <&scif_clk>;
1131 clock-names = "fck", 1124 clock-names = "fck", "brg_int", "scif_clk";
1132 dmas = <&dmac1 0x53>, 1125 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1133 <&dmac2 0x53>, 1126 <&dmac2 0x53>, <&dmac2 0x52>;
1134 dma-names = "tx", "rx 1127 dma-names = "tx", "rx", "tx", "rx";
1135 power-domains = <&sys 1128 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1136 resets = <&cpg 206>; 1129 resets = <&cpg 206>;
1137 status = "disabled"; 1130 status = "disabled";
1138 }; 1131 };
1139 1132
1140 scif2: serial@e6e88000 { 1133 scif2: serial@e6e88000 {
1141 compatible = "renesas 1134 compatible = "renesas,scif-r8a774c0",
1142 "renesas 1135 "renesas,rcar-gen3-scif", "renesas,scif";
1143 reg = <0 0xe6e88000 0 1136 reg = <0 0xe6e88000 0 64>;
1144 interrupts = <GIC_SPI 1137 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
1145 clocks = <&cpg CPG_MO 1138 clocks = <&cpg CPG_MOD 310>,
1146 <&cpg CPG_CO 1139 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
1147 <&scif_clk>; 1140 <&scif_clk>;
1148 clock-names = "fck", 1141 clock-names = "fck", "brg_int", "scif_clk";
1149 dmas = <&dmac1 0x13>, 1142 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1150 <&dmac2 0x13>, 1143 <&dmac2 0x13>, <&dmac2 0x12>;
1151 dma-names = "tx", "rx 1144 dma-names = "tx", "rx", "tx", "rx";
1152 power-domains = <&sys 1145 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1153 resets = <&cpg 310>; 1146 resets = <&cpg 310>;
1154 status = "disabled"; 1147 status = "disabled";
1155 }; 1148 };
1156 1149
1157 scif3: serial@e6c50000 { 1150 scif3: serial@e6c50000 {
1158 compatible = "renesas 1151 compatible = "renesas,scif-r8a774c0",
1159 "renesas 1152 "renesas,rcar-gen3-scif", "renesas,scif";
1160 reg = <0 0xe6c50000 0 1153 reg = <0 0xe6c50000 0 64>;
1161 interrupts = <GIC_SPI 1154 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1162 clocks = <&cpg CPG_MO 1155 clocks = <&cpg CPG_MOD 204>,
1163 <&cpg CPG_CO 1156 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
1164 <&scif_clk>; 1157 <&scif_clk>;
1165 clock-names = "fck", 1158 clock-names = "fck", "brg_int", "scif_clk";
1166 dmas = <&dmac0 0x57>, 1159 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1167 dma-names = "tx", "rx 1160 dma-names = "tx", "rx";
1168 power-domains = <&sys 1161 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1169 resets = <&cpg 204>; 1162 resets = <&cpg 204>;
1170 status = "disabled"; 1163 status = "disabled";
1171 }; 1164 };
1172 1165
1173 scif4: serial@e6c40000 { 1166 scif4: serial@e6c40000 {
1174 compatible = "renesas 1167 compatible = "renesas,scif-r8a774c0",
1175 "renesas 1168 "renesas,rcar-gen3-scif", "renesas,scif";
1176 reg = <0 0xe6c40000 0 1169 reg = <0 0xe6c40000 0 64>;
1177 interrupts = <GIC_SPI 1170 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1178 clocks = <&cpg CPG_MO 1171 clocks = <&cpg CPG_MOD 203>,
1179 <&cpg CPG_CO 1172 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
1180 <&scif_clk>; 1173 <&scif_clk>;
1181 clock-names = "fck", 1174 clock-names = "fck", "brg_int", "scif_clk";
1182 dmas = <&dmac0 0x59>, 1175 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1183 dma-names = "tx", "rx 1176 dma-names = "tx", "rx";
1184 power-domains = <&sys 1177 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1185 resets = <&cpg 203>; 1178 resets = <&cpg 203>;
1186 status = "disabled"; 1179 status = "disabled";
1187 }; 1180 };
1188 1181
1189 scif5: serial@e6f30000 { 1182 scif5: serial@e6f30000 {
1190 compatible = "renesas 1183 compatible = "renesas,scif-r8a774c0",
1191 "renesas 1184 "renesas,rcar-gen3-scif", "renesas,scif";
1192 reg = <0 0xe6f30000 0 1185 reg = <0 0xe6f30000 0 64>;
1193 interrupts = <GIC_SPI 1186 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1194 clocks = <&cpg CPG_MO 1187 clocks = <&cpg CPG_MOD 202>,
1195 <&cpg CPG_CO 1188 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
1196 <&scif_clk>; 1189 <&scif_clk>;
1197 clock-names = "fck", 1190 clock-names = "fck", "brg_int", "scif_clk";
1198 dmas = <&dmac0 0x5b>, 1191 dmas = <&dmac0 0x5b>, <&dmac0 0x5a>;
1199 dma-names = "tx", "rx 1192 dma-names = "tx", "rx";
1200 power-domains = <&sys 1193 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1201 resets = <&cpg 202>; 1194 resets = <&cpg 202>;
1202 status = "disabled"; 1195 status = "disabled";
1203 }; 1196 };
1204 1197
1205 msiof0: spi@e6e90000 { 1198 msiof0: spi@e6e90000 {
1206 compatible = "renesas 1199 compatible = "renesas,msiof-r8a774c0",
1207 "renesas 1200 "renesas,rcar-gen3-msiof";
1208 reg = <0 0xe6e90000 0 1201 reg = <0 0xe6e90000 0 0x0064>;
1209 interrupts = <GIC_SPI 1202 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1210 clocks = <&cpg CPG_MO 1203 clocks = <&cpg CPG_MOD 211>;
1211 dmas = <&dmac1 0x41>, 1204 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1212 <&dmac2 0x41>, 1205 <&dmac2 0x41>, <&dmac2 0x40>;
1213 dma-names = "tx", "rx 1206 dma-names = "tx", "rx", "tx", "rx";
1214 power-domains = <&sys 1207 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1215 resets = <&cpg 211>; 1208 resets = <&cpg 211>;
1216 #address-cells = <1>; 1209 #address-cells = <1>;
1217 #size-cells = <0>; 1210 #size-cells = <0>;
1218 status = "disabled"; 1211 status = "disabled";
1219 }; 1212 };
1220 1213
1221 msiof1: spi@e6ea0000 { 1214 msiof1: spi@e6ea0000 {
1222 compatible = "renesas 1215 compatible = "renesas,msiof-r8a774c0",
1223 "renesas 1216 "renesas,rcar-gen3-msiof";
1224 reg = <0 0xe6ea0000 0 1217 reg = <0 0xe6ea0000 0 0x0064>;
1225 interrupts = <GIC_SPI 1218 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1226 clocks = <&cpg CPG_MO 1219 clocks = <&cpg CPG_MOD 210>;
1227 dmas = <&dmac0 0x43>, 1220 dmas = <&dmac0 0x43>, <&dmac0 0x42>;
1228 dma-names = "tx", "rx 1221 dma-names = "tx", "rx";
1229 power-domains = <&sys 1222 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1230 resets = <&cpg 210>; 1223 resets = <&cpg 210>;
1231 #address-cells = <1>; 1224 #address-cells = <1>;
1232 #size-cells = <0>; 1225 #size-cells = <0>;
1233 status = "disabled"; 1226 status = "disabled";
1234 }; 1227 };
1235 1228
1236 msiof2: spi@e6c00000 { 1229 msiof2: spi@e6c00000 {
1237 compatible = "renesas 1230 compatible = "renesas,msiof-r8a774c0",
1238 "renesas 1231 "renesas,rcar-gen3-msiof";
1239 reg = <0 0xe6c00000 0 1232 reg = <0 0xe6c00000 0 0x0064>;
1240 interrupts = <GIC_SPI 1233 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1241 clocks = <&cpg CPG_MO 1234 clocks = <&cpg CPG_MOD 209>;
1242 dmas = <&dmac0 0x45>, 1235 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1243 dma-names = "tx", "rx 1236 dma-names = "tx", "rx";
1244 power-domains = <&sys 1237 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1245 resets = <&cpg 209>; 1238 resets = <&cpg 209>;
1246 #address-cells = <1>; 1239 #address-cells = <1>;
1247 #size-cells = <0>; 1240 #size-cells = <0>;
1248 status = "disabled"; 1241 status = "disabled";
1249 }; 1242 };
1250 1243
1251 msiof3: spi@e6c10000 { 1244 msiof3: spi@e6c10000 {
1252 compatible = "renesas 1245 compatible = "renesas,msiof-r8a774c0",
1253 "renesas 1246 "renesas,rcar-gen3-msiof";
1254 reg = <0 0xe6c10000 0 1247 reg = <0 0xe6c10000 0 0x0064>;
1255 interrupts = <GIC_SPI 1248 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1256 clocks = <&cpg CPG_MO 1249 clocks = <&cpg CPG_MOD 208>;
1257 dmas = <&dmac0 0x47>, 1250 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1258 dma-names = "tx", "rx 1251 dma-names = "tx", "rx";
1259 power-domains = <&sys 1252 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1260 resets = <&cpg 208>; 1253 resets = <&cpg 208>;
1261 #address-cells = <1>; 1254 #address-cells = <1>;
1262 #size-cells = <0>; 1255 #size-cells = <0>;
1263 status = "disabled"; 1256 status = "disabled";
1264 }; 1257 };
1265 1258
1266 vin4: video@e6ef4000 { 1259 vin4: video@e6ef4000 {
1267 compatible = "renesas 1260 compatible = "renesas,vin-r8a774c0";
1268 reg = <0 0xe6ef4000 0 1261 reg = <0 0xe6ef4000 0 0x1000>;
1269 interrupts = <GIC_SPI 1262 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
1270 clocks = <&cpg CPG_MO 1263 clocks = <&cpg CPG_MOD 807>;
1271 power-domains = <&sys 1264 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1272 resets = <&cpg 807>; 1265 resets = <&cpg 807>;
1273 renesas,id = <4>; 1266 renesas,id = <4>;
1274 status = "disabled"; 1267 status = "disabled";
1275 1268
1276 ports { 1269 ports {
1277 #address-cell 1270 #address-cells = <1>;
1278 #size-cells = 1271 #size-cells = <0>;
1279 1272
1280 port@1 { 1273 port@1 {
1281 #addr 1274 #address-cells = <1>;
1282 #size 1275 #size-cells = <0>;
1283 1276
1284 reg = 1277 reg = <1>;
1285 1278
1286 vin4c 1279 vin4csi40: endpoint@2 {
1287 1280 reg = <2>;
1288 1281 remote-endpoint = <&csi40vin4>;
1289 }; 1282 };
1290 }; 1283 };
1291 }; 1284 };
1292 }; 1285 };
1293 1286
1294 vin5: video@e6ef5000 { 1287 vin5: video@e6ef5000 {
1295 compatible = "renesas 1288 compatible = "renesas,vin-r8a774c0";
1296 reg = <0 0xe6ef5000 0 1289 reg = <0 0xe6ef5000 0 0x1000>;
1297 interrupts = <GIC_SPI 1290 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
1298 clocks = <&cpg CPG_MO 1291 clocks = <&cpg CPG_MOD 806>;
1299 power-domains = <&sys 1292 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1300 resets = <&cpg 806>; 1293 resets = <&cpg 806>;
1301 renesas,id = <5>; 1294 renesas,id = <5>;
1302 status = "disabled"; 1295 status = "disabled";
1303 1296
1304 ports { 1297 ports {
1305 #address-cell 1298 #address-cells = <1>;
1306 #size-cells = 1299 #size-cells = <0>;
1307 1300
1308 port@1 { 1301 port@1 {
1309 #addr 1302 #address-cells = <1>;
1310 #size 1303 #size-cells = <0>;
1311 1304
1312 reg = 1305 reg = <1>;
1313 1306
1314 vin5c 1307 vin5csi40: endpoint@2 {
1315 1308 reg = <2>;
1316 1309 remote-endpoint = <&csi40vin5>;
1317 }; 1310 };
1318 }; 1311 };
1319 }; 1312 };
1320 }; 1313 };
1321 1314
1322 rcar_sound: sound@ec500000 { 1315 rcar_sound: sound@ec500000 {
1323 /* 1316 /*
1324 * #sound-dai-cells i 1317 * #sound-dai-cells is required if simple-card
1325 * 1318 *
1326 * Single DAI : #soun 1319 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1327 * Multi DAI : #soun 1320 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1328 */ 1321 */
1329 /* 1322 /*
1330 * #clock-cells is re 1323 * #clock-cells is required for audio_clkout0/1/2/3
1331 * 1324 *
1332 * clkout : #cl 1325 * clkout : #clock-cells = <0>; <&rcar_sound>;
1333 * clkout0/1/2/3: #cl 1326 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
1334 */ 1327 */
1335 compatible = "renesas 1328 compatible = "renesas,rcar_sound-r8a774c0",
1336 "renesas 1329 "renesas,rcar_sound-gen3";
1337 reg = <0 0xec500000 0 1330 reg = <0 0xec500000 0 0x1000>, /* SCU */
1338 <0 0xec5a0000 0 1331 <0 0xec5a0000 0 0x100>, /* ADG */
1339 <0 0xec540000 0 1332 <0 0xec540000 0 0x1000>, /* SSIU */
1340 <0 0xec541000 0 1333 <0 0xec541000 0 0x280>, /* SSI */
1341 <0 0xec760000 0 1334 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
1342 reg-names = "scu", "a 1335 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1343 1336
1344 clocks = <&cpg CPG_MO 1337 clocks = <&cpg CPG_MOD 1005>,
1345 <&cpg CPG_MO 1338 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
1346 <&cpg CPG_MO 1339 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
1347 <&cpg CPG_MO 1340 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
1348 <&cpg CPG_MO 1341 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
1349 <&cpg CPG_MO 1342 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
1350 <&cpg CPG_MO 1343 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
1351 <&cpg CPG_MO 1344 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
1352 <&cpg CPG_MO 1345 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
1353 <&cpg CPG_MO 1346 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
1354 <&cpg CPG_MO 1347 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
1355 <&cpg CPG_MO 1348 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1356 <&cpg CPG_MO 1349 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1357 <&cpg CPG_MO 1350 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
1358 <&audio_clk_ 1351 <&audio_clk_a>, <&audio_clk_b>,
1359 <&audio_clk_ 1352 <&audio_clk_c>,
1360 <&cpg CPG_MO !! 1353 <&cpg CPG_CORE R8A774C0_CLK_ZA2>;
1361 clock-names = "ssi-al 1354 clock-names = "ssi-all",
1362 "ssi.9" 1355 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1363 "ssi.5" 1356 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1364 "ssi.1" 1357 "ssi.1", "ssi.0",
1365 "src.9" 1358 "src.9", "src.8", "src.7", "src.6",
1366 "src.5" 1359 "src.5", "src.4", "src.3", "src.2",
1367 "src.1" 1360 "src.1", "src.0",
1368 "mix.1" 1361 "mix.1", "mix.0",
1369 "ctu.1" 1362 "ctu.1", "ctu.0",
1370 "dvc.0" 1363 "dvc.0", "dvc.1",
1371 "clk_a" 1364 "clk_a", "clk_b", "clk_c", "clk_i";
1372 power-domains = <&sys 1365 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1373 resets = <&cpg 1005>, 1366 resets = <&cpg 1005>,
1374 <&cpg 1006>, 1367 <&cpg 1006>, <&cpg 1007>,
1375 <&cpg 1008>, 1368 <&cpg 1008>, <&cpg 1009>,
1376 <&cpg 1010>, 1369 <&cpg 1010>, <&cpg 1011>,
1377 <&cpg 1012>, 1370 <&cpg 1012>, <&cpg 1013>,
1378 <&cpg 1014>, 1371 <&cpg 1014>, <&cpg 1015>;
1379 reset-names = "ssi-al 1372 reset-names = "ssi-all",
1380 "ssi.9" 1373 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1381 "ssi.5" 1374 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1382 "ssi.1" 1375 "ssi.1", "ssi.0";
1383 status = "disabled"; 1376 status = "disabled";
1384 1377
1385 rcar_sound,ctu { 1378 rcar_sound,ctu {
1386 ctu00: ctu-0 1379 ctu00: ctu-0 { };
1387 ctu01: ctu-1 1380 ctu01: ctu-1 { };
1388 ctu02: ctu-2 1381 ctu02: ctu-2 { };
1389 ctu03: ctu-3 1382 ctu03: ctu-3 { };
1390 ctu10: ctu-4 1383 ctu10: ctu-4 { };
1391 ctu11: ctu-5 1384 ctu11: ctu-5 { };
1392 ctu12: ctu-6 1385 ctu12: ctu-6 { };
1393 ctu13: ctu-7 1386 ctu13: ctu-7 { };
1394 }; 1387 };
1395 1388
1396 rcar_sound,dvc { 1389 rcar_sound,dvc {
1397 dvc0: dvc-0 { 1390 dvc0: dvc-0 {
1398 dmas 1391 dmas = <&audma0 0xbc>;
1399 dma-n 1392 dma-names = "tx";
1400 }; 1393 };
1401 dvc1: dvc-1 { 1394 dvc1: dvc-1 {
1402 dmas 1395 dmas = <&audma0 0xbe>;
1403 dma-n 1396 dma-names = "tx";
1404 }; 1397 };
1405 }; 1398 };
1406 1399
1407 rcar_sound,mix { 1400 rcar_sound,mix {
1408 mix0: mix-0 { 1401 mix0: mix-0 { };
1409 mix1: mix-1 { 1402 mix1: mix-1 { };
1410 }; 1403 };
1411 1404
1412 rcar_sound,src { 1405 rcar_sound,src {
1413 src0: src-0 { 1406 src0: src-0 {
1414 inter 1407 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1415 dmas 1408 dmas = <&audma0 0x85>, <&audma0 0x9a>;
1416 dma-n 1409 dma-names = "rx", "tx";
1417 }; 1410 };
1418 src1: src-1 { 1411 src1: src-1 {
1419 inter 1412 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1420 dmas 1413 dmas = <&audma0 0x87>, <&audma0 0x9c>;
1421 dma-n 1414 dma-names = "rx", "tx";
1422 }; 1415 };
1423 src2: src-2 { 1416 src2: src-2 {
1424 inter 1417 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1425 dmas 1418 dmas = <&audma0 0x89>, <&audma0 0x9e>;
1426 dma-n 1419 dma-names = "rx", "tx";
1427 }; 1420 };
1428 src3: src-3 { 1421 src3: src-3 {
1429 inter 1422 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1430 dmas 1423 dmas = <&audma0 0x8b>, <&audma0 0xa0>;
1431 dma-n 1424 dma-names = "rx", "tx";
1432 }; 1425 };
1433 src4: src-4 { 1426 src4: src-4 {
1434 inter 1427 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1435 dmas 1428 dmas = <&audma0 0x8d>, <&audma0 0xb0>;
1436 dma-n 1429 dma-names = "rx", "tx";
1437 }; 1430 };
1438 src5: src-5 { 1431 src5: src-5 {
1439 inter 1432 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1440 dmas 1433 dmas = <&audma0 0x8f>, <&audma0 0xb2>;
1441 dma-n 1434 dma-names = "rx", "tx";
1442 }; 1435 };
1443 src6: src-6 { 1436 src6: src-6 {
1444 inter 1437 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1445 dmas 1438 dmas = <&audma0 0x91>, <&audma0 0xb4>;
1446 dma-n 1439 dma-names = "rx", "tx";
1447 }; 1440 };
1448 src7: src-7 { 1441 src7: src-7 {
1449 inter 1442 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1450 dmas 1443 dmas = <&audma0 0x93>, <&audma0 0xb6>;
1451 dma-n 1444 dma-names = "rx", "tx";
1452 }; 1445 };
1453 src8: src-8 { 1446 src8: src-8 {
1454 inter 1447 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1455 dmas 1448 dmas = <&audma0 0x95>, <&audma0 0xb8>;
1456 dma-n 1449 dma-names = "rx", "tx";
1457 }; 1450 };
1458 src9: src-9 { 1451 src9: src-9 {
1459 inter 1452 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
1460 dmas 1453 dmas = <&audma0 0x97>, <&audma0 0xba>;
1461 dma-n 1454 dma-names = "rx", "tx";
1462 }; 1455 };
1463 }; 1456 };
1464 1457
1465 rcar_sound,ssi { 1458 rcar_sound,ssi {
1466 ssi0: ssi-0 { 1459 ssi0: ssi-0 {
1467 inter 1460 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
1468 dmas 1461 dmas = <&audma0 0x01>, <&audma0 0x02>,
1469 1462 <&audma0 0x15>, <&audma0 0x16>;
1470 dma-n 1463 dma-names = "rx", "tx", "rxu", "txu";
1471 }; 1464 };
1472 ssi1: ssi-1 { 1465 ssi1: ssi-1 {
1473 inter 1466 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
1474 dmas 1467 dmas = <&audma0 0x03>, <&audma0 0x04>,
1475 1468 <&audma0 0x49>, <&audma0 0x4a>;
1476 dma-n 1469 dma-names = "rx", "tx", "rxu", "txu";
1477 }; 1470 };
1478 ssi2: ssi-2 { 1471 ssi2: ssi-2 {
1479 inter 1472 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
1480 dmas 1473 dmas = <&audma0 0x05>, <&audma0 0x06>,
1481 1474 <&audma0 0x63>, <&audma0 0x64>;
1482 dma-n 1475 dma-names = "rx", "tx", "rxu", "txu";
1483 }; 1476 };
1484 ssi3: ssi-3 { 1477 ssi3: ssi-3 {
1485 inter 1478 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1486 dmas 1479 dmas = <&audma0 0x07>, <&audma0 0x08>,
1487 1480 <&audma0 0x6f>, <&audma0 0x70>;
1488 dma-n 1481 dma-names = "rx", "tx", "rxu", "txu";
1489 }; 1482 };
1490 ssi4: ssi-4 { 1483 ssi4: ssi-4 {
1491 inter 1484 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1492 dmas 1485 dmas = <&audma0 0x09>, <&audma0 0x0a>,
1493 1486 <&audma0 0x71>, <&audma0 0x72>;
1494 dma-n 1487 dma-names = "rx", "tx", "rxu", "txu";
1495 }; 1488 };
1496 ssi5: ssi-5 { 1489 ssi5: ssi-5 {
1497 inter 1490 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1498 dmas 1491 dmas = <&audma0 0x0b>, <&audma0 0x0c>,
1499 1492 <&audma0 0x73>, <&audma0 0x74>;
1500 dma-n 1493 dma-names = "rx", "tx", "rxu", "txu";
1501 }; 1494 };
1502 ssi6: ssi-6 { 1495 ssi6: ssi-6 {
1503 inter 1496 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
1504 dmas 1497 dmas = <&audma0 0x0d>, <&audma0 0x0e>,
1505 1498 <&audma0 0x75>, <&audma0 0x76>;
1506 dma-n 1499 dma-names = "rx", "tx", "rxu", "txu";
1507 }; 1500 };
1508 ssi7: ssi-7 { 1501 ssi7: ssi-7 {
1509 inter 1502 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
1510 dmas 1503 dmas = <&audma0 0x0f>, <&audma0 0x10>,
1511 1504 <&audma0 0x79>, <&audma0 0x7a>;
1512 dma-n 1505 dma-names = "rx", "tx", "rxu", "txu";
1513 }; 1506 };
1514 ssi8: ssi-8 { 1507 ssi8: ssi-8 {
1515 inter 1508 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
1516 dmas 1509 dmas = <&audma0 0x11>, <&audma0 0x12>,
1517 1510 <&audma0 0x7b>, <&audma0 0x7c>;
1518 dma-n 1511 dma-names = "rx", "tx", "rxu", "txu";
1519 }; 1512 };
1520 ssi9: ssi-9 { 1513 ssi9: ssi-9 {
1521 inter 1514 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
1522 dmas 1515 dmas = <&audma0 0x13>, <&audma0 0x14>,
1523 1516 <&audma0 0x7d>, <&audma0 0x7e>;
1524 dma-n 1517 dma-names = "rx", "tx", "rxu", "txu";
1525 }; 1518 };
1526 }; 1519 };
1527 }; 1520 };
1528 1521
1529 audma0: dma-controller@ec7000 1522 audma0: dma-controller@ec700000 {
1530 compatible = "renesas 1523 compatible = "renesas,dmac-r8a774c0",
1531 "renesas 1524 "renesas,rcar-dmac";
1532 reg = <0 0xec700000 0 1525 reg = <0 0xec700000 0 0x10000>;
1533 interrupts = <GIC_SPI 1526 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
1534 <GIC_SPI 1527 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
1535 <GIC_SPI 1528 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
1536 <GIC_SPI 1529 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
1537 <GIC_SPI 1530 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
1538 <GIC_SPI 1531 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
1539 <GIC_SPI 1532 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
1540 <GIC_SPI 1533 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
1541 <GIC_SPI 1534 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
1542 <GIC_SPI 1535 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
1543 <GIC_SPI 1536 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1544 <GIC_SPI 1537 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
1545 <GIC_SPI 1538 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
1546 <GIC_SPI 1539 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
1547 <GIC_SPI 1540 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
1548 <GIC_SPI 1541 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1549 <GIC_SPI 1542 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
1550 interrupt-names = "er 1543 interrupt-names = "error",
1551 "ch0" 1544 "ch0", "ch1", "ch2", "ch3",
1552 "ch4" 1545 "ch4", "ch5", "ch6", "ch7",
1553 "ch8" 1546 "ch8", "ch9", "ch10", "ch11",
1554 "ch12 1547 "ch12", "ch13", "ch14", "ch15";
1555 clocks = <&cpg CPG_MO 1548 clocks = <&cpg CPG_MOD 502>;
1556 clock-names = "fck"; 1549 clock-names = "fck";
1557 power-domains = <&sys 1550 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1558 resets = <&cpg 502>; 1551 resets = <&cpg 502>;
1559 #dma-cells = <1>; 1552 #dma-cells = <1>;
1560 dma-channels = <16>; 1553 dma-channels = <16>;
1561 iommus = <&ipmmu_mp 0 1554 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
1562 <&ipmmu_mp 2 1555 <&ipmmu_mp 2>, <&ipmmu_mp 3>,
1563 <&ipmmu_mp 4 1556 <&ipmmu_mp 4>, <&ipmmu_mp 5>,
1564 <&ipmmu_mp 6 1557 <&ipmmu_mp 6>, <&ipmmu_mp 7>,
1565 <&ipmmu_mp 8 1558 <&ipmmu_mp 8>, <&ipmmu_mp 9>,
1566 <&ipmmu_mp 1 1559 <&ipmmu_mp 10>, <&ipmmu_mp 11>,
1567 <&ipmmu_mp 1 1560 <&ipmmu_mp 12>, <&ipmmu_mp 13>,
1568 <&ipmmu_mp 1 1561 <&ipmmu_mp 14>, <&ipmmu_mp 15>;
1569 }; 1562 };
1570 1563
1571 xhci0: usb@ee000000 { 1564 xhci0: usb@ee000000 {
1572 compatible = "renesas 1565 compatible = "renesas,xhci-r8a774c0",
1573 "renesas 1566 "renesas,rcar-gen3-xhci";
1574 reg = <0 0xee000000 0 1567 reg = <0 0xee000000 0 0xc00>;
1575 interrupts = <GIC_SPI 1568 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1576 clocks = <&cpg CPG_MO 1569 clocks = <&cpg CPG_MOD 328>;
1577 power-domains = <&sys 1570 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1578 resets = <&cpg 328>; 1571 resets = <&cpg 328>;
1579 status = "disabled"; 1572 status = "disabled";
1580 }; 1573 };
1581 1574
1582 usb3_peri0: usb@ee020000 { 1575 usb3_peri0: usb@ee020000 {
1583 compatible = "renesas 1576 compatible = "renesas,r8a774c0-usb3-peri",
1584 "renesas 1577 "renesas,rcar-gen3-usb3-peri";
1585 reg = <0 0xee020000 0 1578 reg = <0 0xee020000 0 0x400>;
1586 interrupts = <GIC_SPI 1579 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1587 clocks = <&cpg CPG_MO 1580 clocks = <&cpg CPG_MOD 328>;
1588 power-domains = <&sys 1581 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1589 resets = <&cpg 328>; 1582 resets = <&cpg 328>;
1590 status = "disabled"; 1583 status = "disabled";
1591 }; 1584 };
1592 1585
1593 ohci0: usb@ee080000 { 1586 ohci0: usb@ee080000 {
1594 compatible = "generic 1587 compatible = "generic-ohci";
1595 reg = <0 0xee080000 0 1588 reg = <0 0xee080000 0 0x100>;
1596 interrupts = <GIC_SPI 1589 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1597 clocks = <&cpg CPG_MO 1590 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
1598 phys = <&usb2_phy0 1> 1591 phys = <&usb2_phy0 1>;
1599 phy-names = "usb"; 1592 phy-names = "usb";
1600 power-domains = <&sys 1593 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1601 resets = <&cpg 703>, 1594 resets = <&cpg 703>, <&cpg 704>;
1602 status = "disabled"; 1595 status = "disabled";
1603 }; 1596 };
1604 1597
1605 ehci0: usb@ee080100 { 1598 ehci0: usb@ee080100 {
1606 compatible = "generic 1599 compatible = "generic-ehci";
1607 reg = <0 0xee080100 0 1600 reg = <0 0xee080100 0 0x100>;
1608 interrupts = <GIC_SPI 1601 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1609 clocks = <&cpg CPG_MO 1602 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
1610 phys = <&usb2_phy0 2> 1603 phys = <&usb2_phy0 2>;
1611 phy-names = "usb"; 1604 phy-names = "usb";
1612 companion = <&ohci0>; 1605 companion = <&ohci0>;
1613 power-domains = <&sys 1606 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1614 resets = <&cpg 703>, 1607 resets = <&cpg 703>, <&cpg 704>;
1615 status = "disabled"; 1608 status = "disabled";
1616 }; 1609 };
1617 1610
1618 usb2_phy0: usb-phy@ee080200 { 1611 usb2_phy0: usb-phy@ee080200 {
1619 compatible = "renesas 1612 compatible = "renesas,usb2-phy-r8a774c0",
1620 "renesas 1613 "renesas,rcar-gen3-usb2-phy";
1621 reg = <0 0xee080200 0 1614 reg = <0 0xee080200 0 0x700>;
1622 interrupts = <GIC_SPI 1615 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1623 clocks = <&cpg CPG_MO 1616 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
1624 power-domains = <&sys 1617 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1625 resets = <&cpg 703>, 1618 resets = <&cpg 703>, <&cpg 704>;
1626 #phy-cells = <1>; 1619 #phy-cells = <1>;
1627 status = "disabled"; 1620 status = "disabled";
1628 }; 1621 };
1629 1622
1630 sdhi0: mmc@ee100000 { 1623 sdhi0: mmc@ee100000 {
1631 compatible = "renesas 1624 compatible = "renesas,sdhi-r8a774c0",
1632 "renesas 1625 "renesas,rcar-gen3-sdhi";
1633 reg = <0 0xee100000 0 1626 reg = <0 0xee100000 0 0x2000>;
1634 interrupts = <GIC_SPI 1627 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
1635 clocks = <&cpg CPG_MO 1628 clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A774C0_CLK_SD0H>;
1636 clock-names = "core", 1629 clock-names = "core", "clkh";
1637 max-frequency = <2000 1630 max-frequency = <200000000>;
1638 power-domains = <&sys 1631 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1639 resets = <&cpg 314>; 1632 resets = <&cpg 314>;
1640 iommus = <&ipmmu_ds1 <<
1641 status = "disabled"; 1633 status = "disabled";
1642 }; 1634 };
1643 1635
1644 sdhi1: mmc@ee120000 { 1636 sdhi1: mmc@ee120000 {
1645 compatible = "renesas 1637 compatible = "renesas,sdhi-r8a774c0",
1646 "renesas 1638 "renesas,rcar-gen3-sdhi";
1647 reg = <0 0xee120000 0 1639 reg = <0 0xee120000 0 0x2000>;
1648 interrupts = <GIC_SPI 1640 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
1649 clocks = <&cpg CPG_MO 1641 clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A774C0_CLK_SD1H>;
1650 clock-names = "core", 1642 clock-names = "core", "clkh";
1651 max-frequency = <2000 1643 max-frequency = <200000000>;
1652 power-domains = <&sys 1644 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1653 resets = <&cpg 313>; 1645 resets = <&cpg 313>;
1654 iommus = <&ipmmu_ds1 <<
1655 status = "disabled"; 1646 status = "disabled";
1656 }; 1647 };
1657 1648
1658 sdhi3: mmc@ee160000 { 1649 sdhi3: mmc@ee160000 {
1659 compatible = "renesas 1650 compatible = "renesas,sdhi-r8a774c0",
1660 "renesas 1651 "renesas,rcar-gen3-sdhi";
1661 reg = <0 0xee160000 0 1652 reg = <0 0xee160000 0 0x2000>;
1662 interrupts = <GIC_SPI 1653 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
1663 clocks = <&cpg CPG_MO 1654 clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A774C0_CLK_SD3H>;
1664 clock-names = "core", 1655 clock-names = "core", "clkh";
1665 max-frequency = <2000 1656 max-frequency = <200000000>;
1666 power-domains = <&sys 1657 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1667 resets = <&cpg 311>; 1658 resets = <&cpg 311>;
1668 iommus = <&ipmmu_ds1 <<
1669 status = "disabled"; 1659 status = "disabled";
1670 }; 1660 };
1671 1661
1672 rpc: spi@ee200000 { 1662 rpc: spi@ee200000 {
1673 compatible = "renesas 1663 compatible = "renesas,r8a774c0-rpc-if",
1674 "renesas 1664 "renesas,rcar-gen3-rpc-if";
1675 reg = <0 0xee200000 0 1665 reg = <0 0xee200000 0 0x200>,
1676 <0 0x08000000 0 1666 <0 0x08000000 0 0x4000000>,
1677 <0 0xee208000 0 1667 <0 0xee208000 0 0x100>;
1678 reg-names = "regs", " 1668 reg-names = "regs", "dirmap", "wbuf";
1679 interrupts = <GIC_SPI 1669 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
1680 clocks = <&cpg CPG_MO 1670 clocks = <&cpg CPG_MOD 917>;
1681 power-domains = <&sys 1671 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1682 resets = <&cpg 917>; 1672 resets = <&cpg 917>;
1683 #address-cells = <1>; 1673 #address-cells = <1>;
1684 #size-cells = <0>; 1674 #size-cells = <0>;
1685 status = "disabled"; 1675 status = "disabled";
1686 }; 1676 };
1687 1677
1688 gic: interrupt-controller@f10 1678 gic: interrupt-controller@f1010000 {
1689 compatible = "arm,gic 1679 compatible = "arm,gic-400";
1690 #interrupt-cells = <3 1680 #interrupt-cells = <3>;
1691 #address-cells = <0>; 1681 #address-cells = <0>;
1692 interrupt-controller; 1682 interrupt-controller;
1693 reg = <0x0 0xf1010000 1683 reg = <0x0 0xf1010000 0 0x1000>,
1694 <0x0 0xf1020000 1684 <0x0 0xf1020000 0 0x20000>,
1695 <0x0 0xf1040000 1685 <0x0 0xf1040000 0 0x20000>,
1696 <0x0 0xf1060000 1686 <0x0 0xf1060000 0 0x20000>;
1697 interrupts = <GIC_PPI 1687 interrupts = <GIC_PPI 9
1698 (GIC_ 1688 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
1699 clocks = <&cpg CPG_MO 1689 clocks = <&cpg CPG_MOD 408>;
1700 clock-names = "clk"; 1690 clock-names = "clk";
1701 power-domains = <&sys 1691 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1702 resets = <&cpg 408>; 1692 resets = <&cpg 408>;
1703 }; 1693 };
1704 1694
1705 pciec0: pcie@fe000000 { 1695 pciec0: pcie@fe000000 {
1706 compatible = "renesas 1696 compatible = "renesas,pcie-r8a774c0",
1707 "renesas 1697 "renesas,pcie-rcar-gen3";
1708 reg = <0 0xfe000000 0 1698 reg = <0 0xfe000000 0 0x80000>;
1709 #address-cells = <3>; 1699 #address-cells = <3>;
1710 #size-cells = <2>; 1700 #size-cells = <2>;
1711 bus-range = <0x00 0xf 1701 bus-range = <0x00 0xff>;
1712 device_type = "pci"; 1702 device_type = "pci";
1713 ranges = <0x01000000 1703 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
1714 <0x02000000 1704 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
1715 <0x02000000 1705 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
1716 <0x42000000 1706 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1717 /* Map all possible D 1707 /* Map all possible DDR/IOMMU as inbound ranges */
1718 dma-ranges = <0x42000 1708 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
1719 interrupts = <GIC_SPI 1709 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1720 <GIC_SPI 1710 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1721 <GIC_SPI 1711 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1722 #interrupt-cells = <1 1712 #interrupt-cells = <1>;
1723 interrupt-map-mask = 1713 interrupt-map-mask = <0 0 0 0>;
1724 interrupt-map = <0 0 1714 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1725 clocks = <&cpg CPG_MO 1715 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
1726 clock-names = "pcie", 1716 clock-names = "pcie", "pcie_bus";
1727 power-domains = <&sys 1717 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1728 resets = <&cpg 319>; 1718 resets = <&cpg 319>;
1729 iommu-map = <0 &ipmmu 1719 iommu-map = <0 &ipmmu_hc 0 1>;
1730 iommu-map-mask = <0>; 1720 iommu-map-mask = <0>;
1731 status = "disabled"; 1721 status = "disabled";
1732 }; 1722 };
1733 1723
1734 pciec0_ep: pcie-ep@fe000000 { 1724 pciec0_ep: pcie-ep@fe000000 {
1735 compatible = "renesas 1725 compatible = "renesas,r8a774c0-pcie-ep",
1736 "renesas 1726 "renesas,rcar-gen3-pcie-ep";
1737 reg = <0x0 0xfe000000 1727 reg = <0x0 0xfe000000 0 0x80000>,
1738 <0x0 0xfe100000 1728 <0x0 0xfe100000 0 0x100000>,
1739 <0x0 0xfe200000 1729 <0x0 0xfe200000 0 0x200000>,
1740 <0x0 0x30000000 1730 <0x0 0x30000000 0 0x8000000>,
1741 <0x0 0x38000000 1731 <0x0 0x38000000 0 0x8000000>;
1742 reg-names = "apb-base 1732 reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
1743 interrupts = <GIC_SPI 1733 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1744 <GIC_SPI 1734 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1745 <GIC_SPI 1735 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1746 clocks = <&cpg CPG_MO 1736 clocks = <&cpg CPG_MOD 319>;
1747 clock-names = "pcie"; 1737 clock-names = "pcie";
1748 resets = <&cpg 319>; 1738 resets = <&cpg 319>;
1749 power-domains = <&sys 1739 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1750 status = "disabled"; 1740 status = "disabled";
1751 }; 1741 };
1752 1742
1753 vspb0: vsp@fe960000 { 1743 vspb0: vsp@fe960000 {
1754 compatible = "renesas 1744 compatible = "renesas,vsp2";
1755 reg = <0 0xfe960000 0 1745 reg = <0 0xfe960000 0 0x8000>;
1756 interrupts = <GIC_SPI 1746 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
1757 clocks = <&cpg CPG_MO 1747 clocks = <&cpg CPG_MOD 626>;
1758 power-domains = <&sys 1748 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1759 resets = <&cpg 626>; 1749 resets = <&cpg 626>;
1760 renesas,fcp = <&fcpvb 1750 renesas,fcp = <&fcpvb0>;
1761 }; 1751 };
1762 1752
1763 vspd0: vsp@fea20000 { 1753 vspd0: vsp@fea20000 {
1764 compatible = "renesas 1754 compatible = "renesas,vsp2";
1765 reg = <0 0xfea20000 0 1755 reg = <0 0xfea20000 0 0x7000>;
1766 interrupts = <GIC_SPI 1756 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
1767 clocks = <&cpg CPG_MO 1757 clocks = <&cpg CPG_MOD 623>;
1768 power-domains = <&sys 1758 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1769 resets = <&cpg 623>; 1759 resets = <&cpg 623>;
1770 renesas,fcp = <&fcpvd 1760 renesas,fcp = <&fcpvd0>;
1771 }; 1761 };
1772 1762
1773 vspd1: vsp@fea28000 { 1763 vspd1: vsp@fea28000 {
1774 compatible = "renesas 1764 compatible = "renesas,vsp2";
1775 reg = <0 0xfea28000 0 1765 reg = <0 0xfea28000 0 0x7000>;
1776 interrupts = <GIC_SPI 1766 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
1777 clocks = <&cpg CPG_MO 1767 clocks = <&cpg CPG_MOD 622>;
1778 power-domains = <&sys 1768 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1779 resets = <&cpg 622>; 1769 resets = <&cpg 622>;
1780 renesas,fcp = <&fcpvd 1770 renesas,fcp = <&fcpvd1>;
1781 }; 1771 };
1782 1772
1783 vspi0: vsp@fe9a0000 { 1773 vspi0: vsp@fe9a0000 {
1784 compatible = "renesas 1774 compatible = "renesas,vsp2";
1785 reg = <0 0xfe9a0000 0 1775 reg = <0 0xfe9a0000 0 0x8000>;
1786 interrupts = <GIC_SPI 1776 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
1787 clocks = <&cpg CPG_MO 1777 clocks = <&cpg CPG_MOD 631>;
1788 power-domains = <&sys 1778 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1789 resets = <&cpg 631>; 1779 resets = <&cpg 631>;
1790 renesas,fcp = <&fcpvi 1780 renesas,fcp = <&fcpvi0>;
1791 }; 1781 };
1792 1782
1793 fcpvb0: fcp@fe96f000 { 1783 fcpvb0: fcp@fe96f000 {
1794 compatible = "renesas 1784 compatible = "renesas,fcpv";
1795 reg = <0 0xfe96f000 0 1785 reg = <0 0xfe96f000 0 0x200>;
1796 clocks = <&cpg CPG_MO 1786 clocks = <&cpg CPG_MOD 607>;
1797 power-domains = <&sys 1787 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1798 resets = <&cpg 607>; 1788 resets = <&cpg 607>;
1799 iommus = <&ipmmu_vp0 1789 iommus = <&ipmmu_vp0 5>;
1800 }; 1790 };
1801 1791
1802 fcpvd0: fcp@fea27000 { 1792 fcpvd0: fcp@fea27000 {
1803 compatible = "renesas 1793 compatible = "renesas,fcpv";
1804 reg = <0 0xfea27000 0 1794 reg = <0 0xfea27000 0 0x200>;
1805 clocks = <&cpg CPG_MO 1795 clocks = <&cpg CPG_MOD 603>;
1806 power-domains = <&sys 1796 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1807 resets = <&cpg 603>; 1797 resets = <&cpg 603>;
1808 iommus = <&ipmmu_vi0 1798 iommus = <&ipmmu_vi0 8>;
1809 }; 1799 };
1810 1800
1811 fcpvd1: fcp@fea2f000 { 1801 fcpvd1: fcp@fea2f000 {
1812 compatible = "renesas 1802 compatible = "renesas,fcpv";
1813 reg = <0 0xfea2f000 0 1803 reg = <0 0xfea2f000 0 0x200>;
1814 clocks = <&cpg CPG_MO 1804 clocks = <&cpg CPG_MOD 602>;
1815 power-domains = <&sys 1805 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1816 resets = <&cpg 602>; 1806 resets = <&cpg 602>;
1817 iommus = <&ipmmu_vi0 1807 iommus = <&ipmmu_vi0 9>;
1818 }; 1808 };
1819 1809
1820 fcpvi0: fcp@fe9af000 { 1810 fcpvi0: fcp@fe9af000 {
1821 compatible = "renesas 1811 compatible = "renesas,fcpv";
1822 reg = <0 0xfe9af000 0 1812 reg = <0 0xfe9af000 0 0x200>;
1823 clocks = <&cpg CPG_MO 1813 clocks = <&cpg CPG_MOD 611>;
1824 power-domains = <&sys 1814 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1825 resets = <&cpg 611>; 1815 resets = <&cpg 611>;
1826 iommus = <&ipmmu_vp0 1816 iommus = <&ipmmu_vp0 8>;
1827 }; 1817 };
1828 1818
1829 csi40: csi2@feaa0000 { 1819 csi40: csi2@feaa0000 {
1830 compatible = "renesas 1820 compatible = "renesas,r8a774c0-csi2";
1831 reg = <0 0xfeaa0000 0 1821 reg = <0 0xfeaa0000 0 0x10000>;
1832 interrupts = <GIC_SPI 1822 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
1833 clocks = <&cpg CPG_MO 1823 clocks = <&cpg CPG_MOD 716>;
1834 power-domains = <&sys 1824 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1835 resets = <&cpg 716>; 1825 resets = <&cpg 716>;
1836 status = "disabled"; 1826 status = "disabled";
1837 1827
1838 ports { 1828 ports {
1839 #address-cell 1829 #address-cells = <1>;
1840 #size-cells = 1830 #size-cells = <0>;
1841 1831
1842 port@0 { 1832 port@0 {
1843 reg = 1833 reg = <0>;
1844 }; 1834 };
1845 1835
1846 port@1 { 1836 port@1 {
1847 #addr 1837 #address-cells = <1>;
1848 #size 1838 #size-cells = <0>;
1849 1839
1850 reg = 1840 reg = <1>;
1851 1841
1852 csi40 1842 csi40vin4: endpoint@0 {
1853 1843 reg = <0>;
1854 1844 remote-endpoint = <&vin4csi40>;
1855 }; 1845 };
1856 csi40 1846 csi40vin5: endpoint@1 {
1857 1847 reg = <1>;
1858 1848 remote-endpoint = <&vin5csi40>;
1859 }; 1849 };
1860 }; 1850 };
1861 }; 1851 };
1862 }; 1852 };
1863 1853
1864 du: display@feb00000 { 1854 du: display@feb00000 {
1865 compatible = "renesas 1855 compatible = "renesas,du-r8a774c0";
1866 reg = <0 0xfeb00000 0 1856 reg = <0 0xfeb00000 0 0x40000>;
1867 interrupts = <GIC_SPI 1857 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
1868 <GIC_SPI 1858 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
1869 clocks = <&cpg CPG_MO 1859 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
1870 clock-names = "du.0", 1860 clock-names = "du.0", "du.1";
1871 resets = <&cpg 724>; 1861 resets = <&cpg 724>;
1872 reset-names = "du.0"; 1862 reset-names = "du.0";
1873 renesas,vsps = <&vspd 1863 renesas,vsps = <&vspd0 0>, <&vspd1 0>;
1874 1864
1875 status = "disabled"; 1865 status = "disabled";
1876 1866
1877 ports { 1867 ports {
1878 #address-cell 1868 #address-cells = <1>;
1879 #size-cells = 1869 #size-cells = <0>;
1880 1870
1881 port@0 { 1871 port@0 {
1882 reg = 1872 reg = <0>;
1883 }; 1873 };
1884 1874
1885 port@1 { 1875 port@1 {
1886 reg = 1876 reg = <1>;
1887 du_ou 1877 du_out_lvds0: endpoint {
1888 1878 remote-endpoint = <&lvds0_in>;
1889 }; 1879 };
1890 }; 1880 };
1891 1881
1892 port@2 { 1882 port@2 {
1893 reg = 1883 reg = <2>;
1894 du_ou 1884 du_out_lvds1: endpoint {
1895 1885 remote-endpoint = <&lvds1_in>;
1896 }; 1886 };
1897 }; 1887 };
1898 }; 1888 };
1899 }; 1889 };
1900 1890
1901 lvds0: lvds-encoder@feb90000 1891 lvds0: lvds-encoder@feb90000 {
1902 compatible = "renesas 1892 compatible = "renesas,r8a774c0-lvds";
1903 reg = <0 0xfeb90000 0 1893 reg = <0 0xfeb90000 0 0x20>;
1904 clocks = <&cpg CPG_MO 1894 clocks = <&cpg CPG_MOD 727>;
1905 power-domains = <&sys 1895 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1906 resets = <&cpg 727>; 1896 resets = <&cpg 727>;
1907 status = "disabled"; 1897 status = "disabled";
1908 1898
1909 renesas,companion = < 1899 renesas,companion = <&lvds1>;
1910 1900
1911 ports { 1901 ports {
1912 #address-cell 1902 #address-cells = <1>;
1913 #size-cells = 1903 #size-cells = <0>;
1914 1904
1915 port@0 { 1905 port@0 {
1916 reg = 1906 reg = <0>;
1917 lvds0 1907 lvds0_in: endpoint {
1918 1908 remote-endpoint = <&du_out_lvds0>;
1919 }; 1909 };
1920 }; 1910 };
1921 1911
1922 port@1 { 1912 port@1 {
1923 reg = 1913 reg = <1>;
1924 }; 1914 };
1925 }; 1915 };
1926 }; 1916 };
1927 1917
1928 lvds1: lvds-encoder@feb90100 1918 lvds1: lvds-encoder@feb90100 {
1929 compatible = "renesas 1919 compatible = "renesas,r8a774c0-lvds";
1930 reg = <0 0xfeb90100 0 1920 reg = <0 0xfeb90100 0 0x20>;
1931 clocks = <&cpg CPG_MO 1921 clocks = <&cpg CPG_MOD 727>;
1932 power-domains = <&sys 1922 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1933 resets = <&cpg 726>; 1923 resets = <&cpg 726>;
1934 status = "disabled"; 1924 status = "disabled";
1935 1925
1936 ports { 1926 ports {
1937 #address-cell 1927 #address-cells = <1>;
1938 #size-cells = 1928 #size-cells = <0>;
1939 1929
1940 port@0 { 1930 port@0 {
1941 reg = 1931 reg = <0>;
1942 lvds1 1932 lvds1_in: endpoint {
1943 1933 remote-endpoint = <&du_out_lvds1>;
1944 }; 1934 };
1945 }; 1935 };
1946 1936
1947 port@1 { 1937 port@1 {
1948 reg = 1938 reg = <1>;
1949 }; 1939 };
1950 }; 1940 };
1951 }; 1941 };
1952 1942
1953 prr: chipid@fff00044 { 1943 prr: chipid@fff00044 {
1954 compatible = "renesas 1944 compatible = "renesas,prr";
1955 reg = <0 0xfff00044 0 1945 reg = <0 0xfff00044 0 4>;
1956 }; 1946 };
1957 }; 1947 };
1958 1948
1959 thermal-zones { 1949 thermal-zones {
1960 cpu-thermal { 1950 cpu-thermal {
1961 polling-delay-passive 1951 polling-delay-passive = <250>;
1962 polling-delay = <0>; 1952 polling-delay = <0>;
1963 thermal-sensors = <&t 1953 thermal-sensors = <&thermal>;
1964 sustainable-power = < 1954 sustainable-power = <717>;
1965 1955
1966 cooling-maps { 1956 cooling-maps {
1967 map0 { 1957 map0 {
1968 trip 1958 trip = <&target>;
1969 cooli 1959 cooling-device = <&a53_0 0 2>;
1970 contr 1960 contribution = <1024>;
1971 }; 1961 };
1972 }; 1962 };
1973 1963
1974 trips { 1964 trips {
1975 sensor1_crit: 1965 sensor1_crit: sensor1-crit {
1976 tempe 1966 temperature = <120000>;
1977 hyste 1967 hysteresis = <2000>;
1978 type 1968 type = "critical";
1979 }; 1969 };
1980 1970
1981 target: trip- 1971 target: trip-point1 {
1982 tempe 1972 temperature = <100000>;
1983 hyste 1973 hysteresis = <2000>;
1984 type 1974 type = "passive";
1985 }; 1975 };
1986 }; 1976 };
1987 }; 1977 };
1988 }; 1978 };
1989 1979
1990 timer { 1980 timer {
1991 compatible = "arm,armv8-timer 1981 compatible = "arm,armv8-timer";
1992 interrupts-extended = <&gic G 1982 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1993 <&gic G 1983 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1994 <&gic G 1984 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1995 <&gic G 1985 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
1996 interrupt-names = "sec-phys", <<
1997 }; 1986 };
1998 1987
1999 /* External USB clocks - can be overr 1988 /* External USB clocks - can be overridden by the board */
2000 usb3s0_clk: usb3s0 { 1989 usb3s0_clk: usb3s0 {
2001 compatible = "fixed-clock"; 1990 compatible = "fixed-clock";
2002 #clock-cells = <0>; 1991 #clock-cells = <0>;
2003 clock-frequency = <0>; 1992 clock-frequency = <0>;
2004 }; 1993 };
2005 1994
2006 usb_extal_clk: usb_extal { 1995 usb_extal_clk: usb_extal {
2007 compatible = "fixed-clock"; 1996 compatible = "fixed-clock";
2008 #clock-cells = <0>; 1997 #clock-cells = <0>;
2009 clock-frequency = <0>; 1998 clock-frequency = <0>;
2010 }; 1999 };
2011 }; 2000 };
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