1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * Device Tree Source for the HiHope RZ/G2H ma 3 * Device Tree Source for the HiHope RZ/G2H main board
4 * 4 *
5 * Copyright (C) 2020 Renesas Electronics Corp 5 * Copyright (C) 2020 Renesas Electronics Corp.
6 */ 6 */
7 7
8 /dts-v1/; 8 /dts-v1/;
9 #include "r8a774e1.dtsi" 9 #include "r8a774e1.dtsi"
10 #include "hihope-rev4.dtsi" 10 #include "hihope-rev4.dtsi"
11 11
12 / { 12 / {
13 model = "HopeRun HiHope RZ/G2H main bo 13 model = "HopeRun HiHope RZ/G2H main board based on r8a774e1";
14 compatible = "hoperun,hihope-rzg2h", " 14 compatible = "hoperun,hihope-rzg2h", "renesas,r8a774e1";
15 15
16 memory@48000000 { 16 memory@48000000 {
17 device_type = "memory"; 17 device_type = "memory";
18 /* first 128MB is reserved for 18 /* first 128MB is reserved for secure area. */
19 reg = <0x0 0x48000000 0x0 0x78 19 reg = <0x0 0x48000000 0x0 0x78000000>;
20 }; 20 };
21 21
22 memory@500000000 { 22 memory@500000000 {
23 device_type = "memory"; 23 device_type = "memory";
24 reg = <0x5 0x00000000 0x0 0x80 24 reg = <0x5 0x00000000 0x0 0x80000000>;
25 }; 25 };
26 }; 26 };
27 27
28 &du { 28 &du {
29 clocks = <&cpg CPG_MOD 724>, 29 clocks = <&cpg CPG_MOD 724>,
30 <&cpg CPG_MOD 723>, 30 <&cpg CPG_MOD 723>,
31 <&cpg CPG_MOD 721>, 31 <&cpg CPG_MOD 721>,
32 <&versaclock5 1>, 32 <&versaclock5 1>,
33 <&x302_clk>, 33 <&x302_clk>,
34 <&versaclock5 2>; 34 <&versaclock5 2>;
35 clock-names = "du.0", "du.1", "du.3", 35 clock-names = "du.0", "du.1", "du.3",
36 "dclkin.0", "dclkin.1", 36 "dclkin.0", "dclkin.1", "dclkin.3";
37 }; 37 };
38 38
39 &sdhi3 { 39 &sdhi3 {
40 mmc-hs400-1_8v; 40 mmc-hs400-1_8v;
41 }; 41 };
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