1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Device Tree Source for the R-Car M3-W (R8A7
4 *
5 * Copyright (C) 2016-2017 Renesas Electronics
6 */
7
8 #include <dt-bindings/clock/r8a7796-cpg-mssr.h
9 #include <dt-bindings/interrupt-controller/arm
10 #include <dt-bindings/power/r8a7796-sysc.h>
11
12 / {
13 compatible = "renesas,r8a7796";
14 #address-cells = <2>;
15 #size-cells = <2>;
16
17 /*
18 * The external audio clocks are confi
19 * clocks by default.
20 * Boards that provide audio clocks sh
21 */
22 audio_clk_a: audio_clk_a {
23 compatible = "fixed-clock";
24 #clock-cells = <0>;
25 clock-frequency = <0>;
26 };
27
28 audio_clk_b: audio_clk_b {
29 compatible = "fixed-clock";
30 #clock-cells = <0>;
31 clock-frequency = <0>;
32 };
33
34 audio_clk_c: audio_clk_c {
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
37 clock-frequency = <0>;
38 };
39
40 /* External CAN clock - to be overridd
41 can_clk: can {
42 compatible = "fixed-clock";
43 #clock-cells = <0>;
44 clock-frequency = <0>;
45 };
46
47 cluster0_opp: opp-table-0 {
48 compatible = "operating-points
49 opp-shared;
50
51 opp-500000000 {
52 opp-hz = /bits/ 64 <50
53 opp-microvolt = <83000
54 clock-latency-ns = <30
55 };
56 opp-1000000000 {
57 opp-hz = /bits/ 64 <10
58 opp-microvolt = <83000
59 clock-latency-ns = <30
60 };
61 opp-1500000000 {
62 opp-hz = /bits/ 64 <15
63 opp-microvolt = <83000
64 clock-latency-ns = <30
65 opp-suspend;
66 };
67 opp-1600000000 {
68 opp-hz = /bits/ 64 <16
69 opp-microvolt = <90000
70 clock-latency-ns = <30
71 };
72 opp-1700000000 {
73 opp-hz = /bits/ 64 <17
74 opp-microvolt = <90000
75 clock-latency-ns = <30
76 };
77 opp-1800000000 {
78 opp-hz = /bits/ 64 <18
79 opp-microvolt = <96000
80 clock-latency-ns = <30
81 turbo-mode;
82 };
83 };
84
85 cluster1_opp: opp-table-1 {
86 compatible = "operating-points
87 opp-shared;
88
89 opp-800000000 {
90 opp-hz = /bits/ 64 <80
91 opp-microvolt = <82000
92 clock-latency-ns = <30
93 };
94 opp-1000000000 {
95 opp-hz = /bits/ 64 <10
96 opp-microvolt = <82000
97 clock-latency-ns = <30
98 };
99 opp-1200000000 {
100 opp-hz = /bits/ 64 <12
101 opp-microvolt = <82000
102 clock-latency-ns = <30
103 };
104 opp-1300000000 {
105 opp-hz = /bits/ 64 <13
106 opp-microvolt = <82000
107 clock-latency-ns = <30
108 turbo-mode;
109 };
110 };
111
112 cpus {
113 #address-cells = <1>;
114 #size-cells = <0>;
115
116 cpu-map {
117 cluster0 {
118 core0 {
119 cpu =
120 };
121 core1 {
122 cpu =
123 };
124 };
125
126 cluster1 {
127 core0 {
128 cpu =
129 };
130 core1 {
131 cpu =
132 };
133 core2 {
134 cpu =
135 };
136 core3 {
137 cpu =
138 };
139 };
140 };
141
142 a57_0: cpu@0 {
143 compatible = "arm,cort
144 reg = <0x0>;
145 device_type = "cpu";
146 power-domains = <&sysc
147 next-level-cache = <&L
148 enable-method = "psci"
149 cpu-idle-states = <&CP
150 dynamic-power-coeffici
151 clocks = <&cpg CPG_COR
152 operating-points-v2 =
153 capacity-dmips-mhz = <
154 #cooling-cells = <2>;
155 };
156
157 a57_1: cpu@1 {
158 compatible = "arm,cort
159 reg = <0x1>;
160 device_type = "cpu";
161 power-domains = <&sysc
162 next-level-cache = <&L
163 enable-method = "psci"
164 cpu-idle-states = <&CP
165 clocks = <&cpg CPG_COR
166 operating-points-v2 =
167 capacity-dmips-mhz = <
168 #cooling-cells = <2>;
169 };
170
171 a53_0: cpu@100 {
172 compatible = "arm,cort
173 reg = <0x100>;
174 device_type = "cpu";
175 power-domains = <&sysc
176 next-level-cache = <&L
177 enable-method = "psci"
178 cpu-idle-states = <&CP
179 #cooling-cells = <2>;
180 dynamic-power-coeffici
181 clocks = <&cpg CPG_COR
182 operating-points-v2 =
183 capacity-dmips-mhz = <
184 };
185
186 a53_1: cpu@101 {
187 compatible = "arm,cort
188 reg = <0x101>;
189 device_type = "cpu";
190 power-domains = <&sysc
191 next-level-cache = <&L
192 enable-method = "psci"
193 cpu-idle-states = <&CP
194 clocks = <&cpg CPG_COR
195 operating-points-v2 =
196 capacity-dmips-mhz = <
197 };
198
199 a53_2: cpu@102 {
200 compatible = "arm,cort
201 reg = <0x102>;
202 device_type = "cpu";
203 power-domains = <&sysc
204 next-level-cache = <&L
205 enable-method = "psci"
206 cpu-idle-states = <&CP
207 clocks = <&cpg CPG_COR
208 operating-points-v2 =
209 capacity-dmips-mhz = <
210 };
211
212 a53_3: cpu@103 {
213 compatible = "arm,cort
214 reg = <0x103>;
215 device_type = "cpu";
216 power-domains = <&sysc
217 next-level-cache = <&L
218 enable-method = "psci"
219 cpu-idle-states = <&CP
220 clocks = <&cpg CPG_COR
221 operating-points-v2 =
222 capacity-dmips-mhz = <
223 };
224
225 L2_CA57: cache-controller-0 {
226 compatible = "cache";
227 power-domains = <&sysc
228 cache-unified;
229 cache-level = <2>;
230 };
231
232 L2_CA53: cache-controller-1 {
233 compatible = "cache";
234 power-domains = <&sysc
235 cache-unified;
236 cache-level = <2>;
237 };
238
239 idle-states {
240 entry-method = "psci";
241
242 CPU_SLEEP_0: cpu-sleep
243 compatible = "
244 arm,psci-suspe
245 local-timer-st
246 entry-latency-
247 exit-latency-u
248 min-residency-
249 };
250
251 CPU_SLEEP_1: cpu-sleep
252 compatible = "
253 arm,psci-suspe
254 local-timer-st
255 entry-latency-
256 exit-latency-u
257 min-residency-
258 };
259 };
260 };
261
262 extal_clk: extal {
263 compatible = "fixed-clock";
264 #clock-cells = <0>;
265 /* This value must be overridd
266 clock-frequency = <0>;
267 };
268
269 extalr_clk: extalr {
270 compatible = "fixed-clock";
271 #clock-cells = <0>;
272 /* This value must be overridd
273 clock-frequency = <0>;
274 };
275
276 /* External PCIe clock - can be overri
277 pcie_bus_clk: pcie_bus {
278 compatible = "fixed-clock";
279 #clock-cells = <0>;
280 clock-frequency = <0>;
281 };
282
283 pmu_a53 {
284 compatible = "arm,cortex-a53-p
285 interrupts-extended = <&gic GI
286 <&gic GI
287 <&gic GI
288 <&gic GI
289 interrupt-affinity = <&a53_0>,
290 };
291
292 pmu_a57 {
293 compatible = "arm,cortex-a57-p
294 interrupts-extended = <&gic GI
295 <&gic GI
296 interrupt-affinity = <&a57_0>,
297 };
298
299 psci {
300 compatible = "arm,psci-1.0", "
301 method = "smc";
302 };
303
304 /* External SCIF clock - to be overrid
305 scif_clk: scif {
306 compatible = "fixed-clock";
307 #clock-cells = <0>;
308 clock-frequency = <0>;
309 };
310
311 soc {
312 compatible = "simple-bus";
313 interrupt-parent = <&gic>;
314 #address-cells = <2>;
315 #size-cells = <2>;
316 ranges;
317
318 rwdt: watchdog@e6020000 {
319 compatible = "renesas,
320 "renesas,
321 reg = <0 0xe6020000 0
322 interrupts = <GIC_SPI
323 clocks = <&cpg CPG_MOD
324 power-domains = <&sysc
325 resets = <&cpg 402>;
326 status = "disabled";
327 };
328
329 gpio0: gpio@e6050000 {
330 compatible = "renesas,
331 "renesas,
332 reg = <0 0xe6050000 0
333 interrupts = <GIC_SPI
334 #gpio-cells = <2>;
335 gpio-controller;
336 gpio-ranges = <&pfc 0
337 #interrupt-cells = <2>
338 interrupt-controller;
339 clocks = <&cpg CPG_MOD
340 power-domains = <&sysc
341 resets = <&cpg 912>;
342 };
343
344 gpio1: gpio@e6051000 {
345 compatible = "renesas,
346 "renesas,
347 reg = <0 0xe6051000 0
348 interrupts = <GIC_SPI
349 #gpio-cells = <2>;
350 gpio-controller;
351 gpio-ranges = <&pfc 0
352 #interrupt-cells = <2>
353 interrupt-controller;
354 clocks = <&cpg CPG_MOD
355 power-domains = <&sysc
356 resets = <&cpg 911>;
357 };
358
359 gpio2: gpio@e6052000 {
360 compatible = "renesas,
361 "renesas,
362 reg = <0 0xe6052000 0
363 interrupts = <GIC_SPI
364 #gpio-cells = <2>;
365 gpio-controller;
366 gpio-ranges = <&pfc 0
367 #interrupt-cells = <2>
368 interrupt-controller;
369 clocks = <&cpg CPG_MOD
370 power-domains = <&sysc
371 resets = <&cpg 910>;
372 };
373
374 gpio3: gpio@e6053000 {
375 compatible = "renesas,
376 "renesas,
377 reg = <0 0xe6053000 0
378 interrupts = <GIC_SPI
379 #gpio-cells = <2>;
380 gpio-controller;
381 gpio-ranges = <&pfc 0
382 #interrupt-cells = <2>
383 interrupt-controller;
384 clocks = <&cpg CPG_MOD
385 power-domains = <&sysc
386 resets = <&cpg 909>;
387 };
388
389 gpio4: gpio@e6054000 {
390 compatible = "renesas,
391 "renesas,
392 reg = <0 0xe6054000 0
393 interrupts = <GIC_SPI
394 #gpio-cells = <2>;
395 gpio-controller;
396 gpio-ranges = <&pfc 0
397 #interrupt-cells = <2>
398 interrupt-controller;
399 clocks = <&cpg CPG_MOD
400 power-domains = <&sysc
401 resets = <&cpg 908>;
402 };
403
404 gpio5: gpio@e6055000 {
405 compatible = "renesas,
406 "renesas,
407 reg = <0 0xe6055000 0
408 interrupts = <GIC_SPI
409 #gpio-cells = <2>;
410 gpio-controller;
411 gpio-ranges = <&pfc 0
412 #interrupt-cells = <2>
413 interrupt-controller;
414 clocks = <&cpg CPG_MOD
415 power-domains = <&sysc
416 resets = <&cpg 907>;
417 };
418
419 gpio6: gpio@e6055400 {
420 compatible = "renesas,
421 "renesas,
422 reg = <0 0xe6055400 0
423 interrupts = <GIC_SPI
424 #gpio-cells = <2>;
425 gpio-controller;
426 gpio-ranges = <&pfc 0
427 #interrupt-cells = <2>
428 interrupt-controller;
429 clocks = <&cpg CPG_MOD
430 power-domains = <&sysc
431 resets = <&cpg 906>;
432 };
433
434 gpio7: gpio@e6055800 {
435 compatible = "renesas,
436 "renesas,
437 reg = <0 0xe6055800 0
438 interrupts = <GIC_SPI
439 #gpio-cells = <2>;
440 gpio-controller;
441 gpio-ranges = <&pfc 0
442 #interrupt-cells = <2>
443 interrupt-controller;
444 clocks = <&cpg CPG_MOD
445 power-domains = <&sysc
446 resets = <&cpg 905>;
447 };
448
449 pfc: pinctrl@e6060000 {
450 compatible = "renesas,
451 reg = <0 0xe6060000 0
452 };
453
454 cmt0: timer@e60f0000 {
455 compatible = "renesas,
456 "renesas,
457 reg = <0 0xe60f0000 0
458 interrupts = <GIC_SPI
459 <GIC_SPI
460 clocks = <&cpg CPG_MOD
461 clock-names = "fck";
462 power-domains = <&sysc
463 resets = <&cpg 303>;
464 status = "disabled";
465 };
466
467 cmt1: timer@e6130000 {
468 compatible = "renesas,
469 "renesas,
470 reg = <0 0xe6130000 0
471 interrupts = <GIC_SPI
472 <GIC_SPI
473 <GIC_SPI
474 <GIC_SPI
475 <GIC_SPI
476 <GIC_SPI
477 <GIC_SPI
478 <GIC_SPI
479 clocks = <&cpg CPG_MOD
480 clock-names = "fck";
481 power-domains = <&sysc
482 resets = <&cpg 302>;
483 status = "disabled";
484 };
485
486 cmt2: timer@e6140000 {
487 compatible = "renesas,
488 "renesas,
489 reg = <0 0xe6140000 0
490 interrupts = <GIC_SPI
491 <GIC_SPI
492 <GIC_SPI
493 <GIC_SPI
494 <GIC_SPI
495 <GIC_SPI
496 <GIC_SPI
497 <GIC_SPI
498 clocks = <&cpg CPG_MOD
499 clock-names = "fck";
500 power-domains = <&sysc
501 resets = <&cpg 301>;
502 status = "disabled";
503 };
504
505 cmt3: timer@e6148000 {
506 compatible = "renesas,
507 "renesas,
508 reg = <0 0xe6148000 0
509 interrupts = <GIC_SPI
510 <GIC_SPI
511 <GIC_SPI
512 <GIC_SPI
513 <GIC_SPI
514 <GIC_SPI
515 <GIC_SPI
516 <GIC_SPI
517 clocks = <&cpg CPG_MOD
518 clock-names = "fck";
519 power-domains = <&sysc
520 resets = <&cpg 300>;
521 status = "disabled";
522 };
523
524 cpg: clock-controller@e6150000
525 compatible = "renesas,
526 reg = <0 0xe6150000 0
527 clocks = <&extal_clk>,
528 clock-names = "extal",
529 #clock-cells = <2>;
530 #power-domain-cells =
531 #reset-cells = <1>;
532 };
533
534 rst: reset-controller@e6160000
535 compatible = "renesas,
536 reg = <0 0xe6160000 0
537 };
538
539 sysc: system-controller@e61800
540 compatible = "renesas,
541 reg = <0 0xe6180000 0
542 #power-domain-cells =
543 };
544
545 tsc: thermal@e6198000 {
546 compatible = "renesas,
547 reg = <0 0xe6198000 0
548 <0 0xe61a0000 0
549 <0 0xe61a8000 0
550 interrupts = <GIC_SPI
551 <GIC_SPI
552 <GIC_SPI
553 clocks = <&cpg CPG_MOD
554 power-domains = <&sysc
555 resets = <&cpg 522>;
556 #thermal-sensor-cells
557 };
558
559 intc_ex: interrupt-controller@
560 compatible = "renesas,
561 #interrupt-cells = <2>
562 interrupt-controller;
563 reg = <0 0xe61c0000 0
564 interrupts = <GIC_SPI
565 <GIC_SPI
566 <GIC_SPI
567 <GIC_SPI
568 <GIC_SPI
569 <GIC_SPI
570 clocks = <&cpg CPG_MOD
571 power-domains = <&sysc
572 resets = <&cpg 407>;
573 };
574
575 tmu0: timer@e61e0000 {
576 compatible = "renesas,
577 reg = <0 0xe61e0000 0
578 interrupts = <GIC_SPI
579 <GIC_SPI
580 <GIC_SPI
581 interrupt-names = "tun
582 clocks = <&cpg CPG_MOD
583 clock-names = "fck";
584 power-domains = <&sysc
585 resets = <&cpg 125>;
586 status = "disabled";
587 };
588
589 tmu1: timer@e6fc0000 {
590 compatible = "renesas,
591 reg = <0 0xe6fc0000 0
592 interrupts = <GIC_SPI
593 <GIC_SPI
594 <GIC_SPI
595 <GIC_SPI
596 interrupt-names = "tun
597 clocks = <&cpg CPG_MOD
598 clock-names = "fck";
599 power-domains = <&sysc
600 resets = <&cpg 124>;
601 status = "disabled";
602 };
603
604 tmu2: timer@e6fd0000 {
605 compatible = "renesas,
606 reg = <0 0xe6fd0000 0
607 interrupts = <GIC_SPI
608 <GIC_SPI
609 <GIC_SPI
610 <GIC_SPI
611 interrupt-names = "tun
612 clocks = <&cpg CPG_MOD
613 clock-names = "fck";
614 power-domains = <&sysc
615 resets = <&cpg 123>;
616 status = "disabled";
617 };
618
619 tmu3: timer@e6fe0000 {
620 compatible = "renesas,
621 reg = <0 0xe6fe0000 0
622 interrupts = <GIC_SPI
623 <GIC_SPI
624 <GIC_SPI
625 interrupt-names = "tun
626 clocks = <&cpg CPG_MOD
627 clock-names = "fck";
628 power-domains = <&sysc
629 resets = <&cpg 122>;
630 status = "disabled";
631 };
632
633 tmu4: timer@ffc00000 {
634 compatible = "renesas,
635 reg = <0 0xffc00000 0
636 interrupts = <GIC_SPI
637 <GIC_SPI
638 <GIC_SPI
639 interrupt-names = "tun
640 clocks = <&cpg CPG_MOD
641 clock-names = "fck";
642 power-domains = <&sysc
643 resets = <&cpg 121>;
644 status = "disabled";
645 };
646
647 i2c0: i2c@e6500000 {
648 #address-cells = <1>;
649 #size-cells = <0>;
650 compatible = "renesas,
651 "renesas,
652 reg = <0 0xe6500000 0
653 interrupts = <GIC_SPI
654 clocks = <&cpg CPG_MOD
655 power-domains = <&sysc
656 resets = <&cpg 931>;
657 dmas = <&dmac1 0x91>,
658 <&dmac2 0x91>,
659 dma-names = "tx", "rx"
660 i2c-scl-internal-delay
661 status = "disabled";
662 };
663
664 i2c1: i2c@e6508000 {
665 #address-cells = <1>;
666 #size-cells = <0>;
667 compatible = "renesas,
668 "renesas,
669 reg = <0 0xe6508000 0
670 interrupts = <GIC_SPI
671 clocks = <&cpg CPG_MOD
672 power-domains = <&sysc
673 resets = <&cpg 930>;
674 dmas = <&dmac1 0x93>,
675 <&dmac2 0x93>,
676 dma-names = "tx", "rx"
677 i2c-scl-internal-delay
678 status = "disabled";
679 };
680
681 i2c2: i2c@e6510000 {
682 #address-cells = <1>;
683 #size-cells = <0>;
684 compatible = "renesas,
685 "renesas,
686 reg = <0 0xe6510000 0
687 interrupts = <GIC_SPI
688 clocks = <&cpg CPG_MOD
689 power-domains = <&sysc
690 resets = <&cpg 929>;
691 dmas = <&dmac1 0x95>,
692 <&dmac2 0x95>,
693 dma-names = "tx", "rx"
694 i2c-scl-internal-delay
695 status = "disabled";
696 };
697
698 i2c3: i2c@e66d0000 {
699 #address-cells = <1>;
700 #size-cells = <0>;
701 compatible = "renesas,
702 "renesas,
703 reg = <0 0xe66d0000 0
704 interrupts = <GIC_SPI
705 clocks = <&cpg CPG_MOD
706 power-domains = <&sysc
707 resets = <&cpg 928>;
708 dmas = <&dmac0 0x97>,
709 dma-names = "tx", "rx"
710 i2c-scl-internal-delay
711 status = "disabled";
712 };
713
714 i2c4: i2c@e66d8000 {
715 #address-cells = <1>;
716 #size-cells = <0>;
717 compatible = "renesas,
718 "renesas,
719 reg = <0 0xe66d8000 0
720 interrupts = <GIC_SPI
721 clocks = <&cpg CPG_MOD
722 power-domains = <&sysc
723 resets = <&cpg 927>;
724 dmas = <&dmac0 0x99>,
725 dma-names = "tx", "rx"
726 i2c-scl-internal-delay
727 status = "disabled";
728 };
729
730 i2c5: i2c@e66e0000 {
731 #address-cells = <1>;
732 #size-cells = <0>;
733 compatible = "renesas,
734 "renesas,
735 reg = <0 0xe66e0000 0
736 interrupts = <GIC_SPI
737 clocks = <&cpg CPG_MOD
738 power-domains = <&sysc
739 resets = <&cpg 919>;
740 dmas = <&dmac0 0x9b>,
741 dma-names = "tx", "rx"
742 i2c-scl-internal-delay
743 status = "disabled";
744 };
745
746 i2c6: i2c@e66e8000 {
747 #address-cells = <1>;
748 #size-cells = <0>;
749 compatible = "renesas,
750 "renesas,
751 reg = <0 0xe66e8000 0
752 interrupts = <GIC_SPI
753 clocks = <&cpg CPG_MOD
754 power-domains = <&sysc
755 resets = <&cpg 918>;
756 dmas = <&dmac0 0x9d>,
757 dma-names = "tx", "rx"
758 i2c-scl-internal-delay
759 status = "disabled";
760 };
761
762 i2c_dvfs: i2c@e60b0000 {
763 #address-cells = <1>;
764 #size-cells = <0>;
765 compatible = "renesas,
766 "renesas,
767 "renesas,
768 reg = <0 0xe60b0000 0
769 interrupts = <GIC_SPI
770 clocks = <&cpg CPG_MOD
771 power-domains = <&sysc
772 resets = <&cpg 926>;
773 dmas = <&dmac0 0x11>,
774 dma-names = "tx", "rx"
775 status = "disabled";
776 };
777
778 hscif0: serial@e6540000 {
779 compatible = "renesas,
780 "renesas,
781 "renesas,
782 reg = <0 0xe6540000 0
783 interrupts = <GIC_SPI
784 clocks = <&cpg CPG_MOD
785 <&cpg CPG_COR
786 <&scif_clk>;
787 clock-names = "fck", "
788 dmas = <&dmac1 0x31>,
789 <&dmac2 0x31>,
790 dma-names = "tx", "rx"
791 power-domains = <&sysc
792 resets = <&cpg 520>;
793 status = "disabled";
794 };
795
796 hscif1: serial@e6550000 {
797 compatible = "renesas,
798 "renesas,
799 "renesas,
800 reg = <0 0xe6550000 0
801 interrupts = <GIC_SPI
802 clocks = <&cpg CPG_MOD
803 <&cpg CPG_COR
804 <&scif_clk>;
805 clock-names = "fck", "
806 dmas = <&dmac1 0x33>,
807 <&dmac2 0x33>,
808 dma-names = "tx", "rx"
809 power-domains = <&sysc
810 resets = <&cpg 519>;
811 status = "disabled";
812 };
813
814 hscif2: serial@e6560000 {
815 compatible = "renesas,
816 "renesas,
817 "renesas,
818 reg = <0 0xe6560000 0
819 interrupts = <GIC_SPI
820 clocks = <&cpg CPG_MOD
821 <&cpg CPG_COR
822 <&scif_clk>;
823 clock-names = "fck", "
824 dmas = <&dmac1 0x35>,
825 <&dmac2 0x35>,
826 dma-names = "tx", "rx"
827 power-domains = <&sysc
828 resets = <&cpg 518>;
829 status = "disabled";
830 };
831
832 hscif3: serial@e66a0000 {
833 compatible = "renesas,
834 "renesas,
835 "renesas,
836 reg = <0 0xe66a0000 0
837 interrupts = <GIC_SPI
838 clocks = <&cpg CPG_MOD
839 <&cpg CPG_COR
840 <&scif_clk>;
841 clock-names = "fck", "
842 dmas = <&dmac0 0x37>,
843 dma-names = "tx", "rx"
844 power-domains = <&sysc
845 resets = <&cpg 517>;
846 status = "disabled";
847 };
848
849 hscif4: serial@e66b0000 {
850 compatible = "renesas,
851 "renesas,
852 "renesas,
853 reg = <0 0xe66b0000 0
854 interrupts = <GIC_SPI
855 clocks = <&cpg CPG_MOD
856 <&cpg CPG_COR
857 <&scif_clk>;
858 clock-names = "fck", "
859 dmas = <&dmac0 0x39>,
860 dma-names = "tx", "rx"
861 power-domains = <&sysc
862 resets = <&cpg 516>;
863 status = "disabled";
864 };
865
866 hsusb: usb@e6590000 {
867 compatible = "renesas,
868 "renesas,
869 reg = <0 0xe6590000 0
870 interrupts = <GIC_SPI
871 clocks = <&cpg CPG_MOD
872 dmas = <&usb_dmac0 0>,
873 <&usb_dmac1 0>,
874 dma-names = "ch0", "ch
875 renesas,buswait = <11>
876 phys = <&usb2_phy0 3>;
877 phy-names = "usb";
878 power-domains = <&sysc
879 resets = <&cpg 704>, <
880 status = "disabled";
881 };
882
883 usb_dmac0: dma-controller@e65a
884 compatible = "renesas,
885 "renesas,
886 reg = <0 0xe65a0000 0
887 interrupts = <GIC_SPI
888 <GIC_SPI
889 interrupt-names = "ch0
890 clocks = <&cpg CPG_MOD
891 power-domains = <&sysc
892 resets = <&cpg 330>;
893 #dma-cells = <1>;
894 dma-channels = <2>;
895 };
896
897 usb_dmac1: dma-controller@e65b
898 compatible = "renesas,
899 "renesas,
900 reg = <0 0xe65b0000 0
901 interrupts = <GIC_SPI
902 <GIC_SPI
903 interrupt-names = "ch0
904 clocks = <&cpg CPG_MOD
905 power-domains = <&sysc
906 resets = <&cpg 331>;
907 #dma-cells = <1>;
908 dma-channels = <2>;
909 };
910
911 usb3_phy0: usb-phy@e65ee000 {
912 compatible = "renesas,
913 "renesas,
914 reg = <0 0xe65ee000 0
915 clocks = <&cpg CPG_MOD
916 <&usb_extal_c
917 clock-names = "usb3-if
918 power-domains = <&sysc
919 resets = <&cpg 328>;
920 #phy-cells = <0>;
921 status = "disabled";
922 };
923
924 arm_cc630p: crypto@e6601000 {
925 compatible = "arm,cryp
926 interrupts = <GIC_SPI
927 reg = <0x0 0xe6601000
928 clocks = <&cpg CPG_MOD
929 resets = <&cpg 229>;
930 power-domains = <&sysc
931 };
932
933 dmac0: dma-controller@e6700000
934 compatible = "renesas,
935 "renesas,
936 reg = <0 0xe6700000 0
937 interrupts = <GIC_SPI
938 <GIC_SPI
939 <GIC_SPI
940 <GIC_SPI
941 <GIC_SPI
942 <GIC_SPI
943 <GIC_SPI
944 <GIC_SPI
945 <GIC_SPI
946 <GIC_SPI
947 <GIC_SPI
948 <GIC_SPI
949 <GIC_SPI
950 <GIC_SPI
951 <GIC_SPI
952 <GIC_SPI
953 <GIC_SPI
954 interrupt-names = "err
955 "ch0",
956 "ch4",
957 "ch8",
958 "ch12"
959 clocks = <&cpg CPG_MOD
960 clock-names = "fck";
961 power-domains = <&sysc
962 resets = <&cpg 219>;
963 #dma-cells = <1>;
964 dma-channels = <16>;
965 iommus = <&ipmmu_ds0 0
966 <&ipmmu_ds0 2>,
967 <&ipmmu_ds0 4>,
968 <&ipmmu_ds0 6>,
969 <&ipmmu_ds0 8>,
970 <&ipmmu_ds0 10>
971 <&ipmmu_ds0 12>
972 <&ipmmu_ds0 14>
973 };
974
975 dmac1: dma-controller@e7300000
976 compatible = "renesas,
977 "renesas,
978 reg = <0 0xe7300000 0
979 interrupts = <GIC_SPI
980 <GIC_SPI
981 <GIC_SPI
982 <GIC_SPI
983 <GIC_SPI
984 <GIC_SPI
985 <GIC_SPI
986 <GIC_SPI
987 <GIC_SPI
988 <GIC_SPI
989 <GIC_SPI
990 <GIC_SPI
991 <GIC_SPI
992 <GIC_SPI
993 <GIC_SPI
994 <GIC_SPI
995 <GIC_SPI
996 interrupt-names = "err
997 "ch0",
998 "ch4",
999 "ch8",
1000 "ch12
1001 clocks = <&cpg CPG_MO
1002 clock-names = "fck";
1003 power-domains = <&sys
1004 resets = <&cpg 218>;
1005 #dma-cells = <1>;
1006 dma-channels = <16>;
1007 iommus = <&ipmmu_ds1
1008 <&ipmmu_ds1 2>
1009 <&ipmmu_ds1 4>
1010 <&ipmmu_ds1 6>
1011 <&ipmmu_ds1 8>
1012 <&ipmmu_ds1 10
1013 <&ipmmu_ds1 12
1014 <&ipmmu_ds1 14
1015 };
1016
1017 dmac2: dma-controller@e731000
1018 compatible = "renesas
1019 "renesas
1020 reg = <0 0xe7310000 0
1021 interrupts = <GIC_SPI
1022 <GIC_SPI
1023 <GIC_SPI
1024 <GIC_SPI
1025 <GIC_SPI
1026 <GIC_SPI
1027 <GIC_SPI
1028 <GIC_SPI
1029 <GIC_SPI
1030 <GIC_SPI
1031 <GIC_SPI
1032 <GIC_SPI
1033 <GIC_SPI
1034 <GIC_SPI
1035 <GIC_SPI
1036 <GIC_SPI
1037 <GIC_SPI
1038 interrupt-names = "er
1039 "ch0"
1040 "ch4"
1041 "ch8"
1042 "ch12
1043 clocks = <&cpg CPG_MO
1044 clock-names = "fck";
1045 power-domains = <&sys
1046 resets = <&cpg 217>;
1047 #dma-cells = <1>;
1048 dma-channels = <16>;
1049 iommus = <&ipmmu_ds1
1050 <&ipmmu_ds1 18
1051 <&ipmmu_ds1 20
1052 <&ipmmu_ds1 22
1053 <&ipmmu_ds1 24
1054 <&ipmmu_ds1 26
1055 <&ipmmu_ds1 28
1056 <&ipmmu_ds1 30
1057 };
1058
1059 ipmmu_ds0: iommu@e6740000 {
1060 compatible = "renesas
1061 reg = <0 0xe6740000 0
1062 renesas,ipmmu-main =
1063 power-domains = <&sys
1064 #iommu-cells = <1>;
1065 };
1066
1067 ipmmu_ds1: iommu@e7740000 {
1068 compatible = "renesas
1069 reg = <0 0xe7740000 0
1070 renesas,ipmmu-main =
1071 power-domains = <&sys
1072 #iommu-cells = <1>;
1073 };
1074
1075 ipmmu_hc: iommu@e6570000 {
1076 compatible = "renesas
1077 reg = <0 0xe6570000 0
1078 renesas,ipmmu-main =
1079 power-domains = <&sys
1080 #iommu-cells = <1>;
1081 };
1082
1083 ipmmu_ir: iommu@ff8b0000 {
1084 compatible = "renesas
1085 reg = <0 0xff8b0000 0
1086 renesas,ipmmu-main =
1087 power-domains = <&sys
1088 #iommu-cells = <1>;
1089 };
1090
1091 ipmmu_mm: iommu@e67b0000 {
1092 compatible = "renesas
1093 reg = <0 0xe67b0000 0
1094 interrupts = <GIC_SPI
1095 <GIC_SPI
1096 power-domains = <&sys
1097 #iommu-cells = <1>;
1098 };
1099
1100 ipmmu_mp: iommu@ec670000 {
1101 compatible = "renesas
1102 reg = <0 0xec670000 0
1103 renesas,ipmmu-main =
1104 power-domains = <&sys
1105 #iommu-cells = <1>;
1106 };
1107
1108 ipmmu_pv0: iommu@fd800000 {
1109 compatible = "renesas
1110 reg = <0 0xfd800000 0
1111 renesas,ipmmu-main =
1112 power-domains = <&sys
1113 #iommu-cells = <1>;
1114 };
1115
1116 ipmmu_pv1: iommu@fd950000 {
1117 compatible = "renesas
1118 reg = <0 0xfd950000 0
1119 renesas,ipmmu-main =
1120 power-domains = <&sys
1121 #iommu-cells = <1>;
1122 };
1123
1124 ipmmu_rt: iommu@ffc80000 {
1125 compatible = "renesas
1126 reg = <0 0xffc80000 0
1127 renesas,ipmmu-main =
1128 power-domains = <&sys
1129 #iommu-cells = <1>;
1130 };
1131
1132 ipmmu_vc0: iommu@fe6b0000 {
1133 compatible = "renesas
1134 reg = <0 0xfe6b0000 0
1135 renesas,ipmmu-main =
1136 power-domains = <&sys
1137 #iommu-cells = <1>;
1138 };
1139
1140 ipmmu_vi0: iommu@febd0000 {
1141 compatible = "renesas
1142 reg = <0 0xfebd0000 0
1143 renesas,ipmmu-main =
1144 power-domains = <&sys
1145 #iommu-cells = <1>;
1146 };
1147
1148 avb: ethernet@e6800000 {
1149 compatible = "renesas
1150 "renesas
1151 reg = <0 0xe6800000 0
1152 interrupts = <GIC_SPI
1153 <GIC_SPI
1154 <GIC_SPI
1155 <GIC_SPI
1156 <GIC_SPI
1157 <GIC_SPI
1158 <GIC_SPI
1159 <GIC_SPI
1160 <GIC_SPI
1161 <GIC_SPI
1162 <GIC_SPI
1163 <GIC_SPI
1164 <GIC_SPI
1165 <GIC_SPI
1166 <GIC_SPI
1167 <GIC_SPI
1168 <GIC_SPI
1169 <GIC_SPI
1170 <GIC_SPI
1171 <GIC_SPI
1172 <GIC_SPI
1173 <GIC_SPI
1174 <GIC_SPI
1175 <GIC_SPI
1176 <GIC_SPI
1177 interrupt-names = "ch
1178 "ch
1179 "ch
1180 "ch
1181 "ch
1182 "ch
1183 "ch
1184 clocks = <&cpg CPG_MO
1185 clock-names = "fck";
1186 power-domains = <&sys
1187 resets = <&cpg 812>;
1188 phy-mode = "rgmii";
1189 rx-internal-delay-ps
1190 tx-internal-delay-ps
1191 iommus = <&ipmmu_ds0
1192 #address-cells = <1>;
1193 #size-cells = <0>;
1194 status = "disabled";
1195 };
1196
1197 can0: can@e6c30000 {
1198 compatible = "renesas
1199 "renesas
1200 reg = <0 0xe6c30000 0
1201 interrupts = <GIC_SPI
1202 clocks = <&cpg CPG_MO
1203 <&cpg CPG_CORE
1204 <&can_clk>;
1205 clock-names = "clkp1"
1206 assigned-clocks = <&c
1207 assigned-clock-rates
1208 power-domains = <&sys
1209 resets = <&cpg 916>;
1210 status = "disabled";
1211 };
1212
1213 can1: can@e6c38000 {
1214 compatible = "renesas
1215 "renesas
1216 reg = <0 0xe6c38000 0
1217 interrupts = <GIC_SPI
1218 clocks = <&cpg CPG_MO
1219 <&cpg CPG_CORE
1220 <&can_clk>;
1221 clock-names = "clkp1"
1222 assigned-clocks = <&c
1223 assigned-clock-rates
1224 power-domains = <&sys
1225 resets = <&cpg 915>;
1226 status = "disabled";
1227 };
1228
1229 canfd: can@e66c0000 {
1230 compatible = "renesas
1231 "renesas
1232 reg = <0 0xe66c0000 0
1233 interrupts = <GIC_SPI
1234 <GIC_SPI 3
1235 interrupt-names = "ch
1236 clocks = <&cpg CPG_MO
1237 <&cpg CPG_CORE
1238 <&can_clk>;
1239 clock-names = "fck",
1240 assigned-clocks = <&c
1241 assigned-clock-rates
1242 power-domains = <&sys
1243 resets = <&cpg 914>;
1244 status = "disabled";
1245
1246 channel0 {
1247 status = "dis
1248 };
1249
1250 channel1 {
1251 status = "dis
1252 };
1253 };
1254
1255 pwm0: pwm@e6e30000 {
1256 compatible = "renesas
1257 reg = <0 0xe6e30000 0
1258 #pwm-cells = <2>;
1259 clocks = <&cpg CPG_MO
1260 resets = <&cpg 523>;
1261 power-domains = <&sys
1262 status = "disabled";
1263 };
1264
1265 pwm1: pwm@e6e31000 {
1266 compatible = "renesas
1267 reg = <0 0xe6e31000 0
1268 #pwm-cells = <2>;
1269 clocks = <&cpg CPG_MO
1270 resets = <&cpg 523>;
1271 power-domains = <&sys
1272 status = "disabled";
1273 };
1274
1275 pwm2: pwm@e6e32000 {
1276 compatible = "renesas
1277 reg = <0 0xe6e32000 0
1278 #pwm-cells = <2>;
1279 clocks = <&cpg CPG_MO
1280 resets = <&cpg 523>;
1281 power-domains = <&sys
1282 status = "disabled";
1283 };
1284
1285 pwm3: pwm@e6e33000 {
1286 compatible = "renesas
1287 reg = <0 0xe6e33000 0
1288 #pwm-cells = <2>;
1289 clocks = <&cpg CPG_MO
1290 resets = <&cpg 523>;
1291 power-domains = <&sys
1292 status = "disabled";
1293 };
1294
1295 pwm4: pwm@e6e34000 {
1296 compatible = "renesas
1297 reg = <0 0xe6e34000 0
1298 #pwm-cells = <2>;
1299 clocks = <&cpg CPG_MO
1300 resets = <&cpg 523>;
1301 power-domains = <&sys
1302 status = "disabled";
1303 };
1304
1305 pwm5: pwm@e6e35000 {
1306 compatible = "renesas
1307 reg = <0 0xe6e35000 0
1308 #pwm-cells = <2>;
1309 clocks = <&cpg CPG_MO
1310 resets = <&cpg 523>;
1311 power-domains = <&sys
1312 status = "disabled";
1313 };
1314
1315 pwm6: pwm@e6e36000 {
1316 compatible = "renesas
1317 reg = <0 0xe6e36000 0
1318 #pwm-cells = <2>;
1319 clocks = <&cpg CPG_MO
1320 resets = <&cpg 523>;
1321 power-domains = <&sys
1322 status = "disabled";
1323 };
1324
1325 scif0: serial@e6e60000 {
1326 compatible = "renesas
1327 "renesas
1328 reg = <0 0xe6e60000 0
1329 interrupts = <GIC_SPI
1330 clocks = <&cpg CPG_MO
1331 <&cpg CPG_CO
1332 <&scif_clk>;
1333 clock-names = "fck",
1334 dmas = <&dmac1 0x51>,
1335 <&dmac2 0x51>,
1336 dma-names = "tx", "rx
1337 power-domains = <&sys
1338 resets = <&cpg 207>;
1339 status = "disabled";
1340 };
1341
1342 scif1: serial@e6e68000 {
1343 compatible = "renesas
1344 "renesas
1345 reg = <0 0xe6e68000 0
1346 interrupts = <GIC_SPI
1347 clocks = <&cpg CPG_MO
1348 <&cpg CPG_CO
1349 <&scif_clk>;
1350 clock-names = "fck",
1351 dmas = <&dmac1 0x53>,
1352 <&dmac2 0x53>,
1353 dma-names = "tx", "rx
1354 power-domains = <&sys
1355 resets = <&cpg 206>;
1356 status = "disabled";
1357 };
1358
1359 scif2: serial@e6e88000 {
1360 compatible = "renesas
1361 "renesas
1362 reg = <0 0xe6e88000 0
1363 interrupts = <GIC_SPI
1364 clocks = <&cpg CPG_MO
1365 <&cpg CPG_CO
1366 <&scif_clk>;
1367 clock-names = "fck",
1368 dmas = <&dmac1 0x13>,
1369 <&dmac2 0x13>,
1370 dma-names = "tx", "rx
1371 power-domains = <&sys
1372 resets = <&cpg 310>;
1373 status = "disabled";
1374 };
1375
1376 scif3: serial@e6c50000 {
1377 compatible = "renesas
1378 "renesas
1379 reg = <0 0xe6c50000 0
1380 interrupts = <GIC_SPI
1381 clocks = <&cpg CPG_MO
1382 <&cpg CPG_CO
1383 <&scif_clk>;
1384 clock-names = "fck",
1385 dmas = <&dmac0 0x57>,
1386 dma-names = "tx", "rx
1387 power-domains = <&sys
1388 resets = <&cpg 204>;
1389 status = "disabled";
1390 };
1391
1392 scif4: serial@e6c40000 {
1393 compatible = "renesas
1394 "renesas
1395 reg = <0 0xe6c40000 0
1396 interrupts = <GIC_SPI
1397 clocks = <&cpg CPG_MO
1398 <&cpg CPG_CO
1399 <&scif_clk>;
1400 clock-names = "fck",
1401 dmas = <&dmac0 0x59>,
1402 dma-names = "tx", "rx
1403 power-domains = <&sys
1404 resets = <&cpg 203>;
1405 status = "disabled";
1406 };
1407
1408 scif5: serial@e6f30000 {
1409 compatible = "renesas
1410 "renesas
1411 reg = <0 0xe6f30000 0
1412 interrupts = <GIC_SPI
1413 clocks = <&cpg CPG_MO
1414 <&cpg CPG_CO
1415 <&scif_clk>;
1416 clock-names = "fck",
1417 dmas = <&dmac1 0x5b>,
1418 <&dmac2 0x5b>,
1419 dma-names = "tx", "rx
1420 power-domains = <&sys
1421 resets = <&cpg 202>;
1422 status = "disabled";
1423 };
1424
1425 tpu: pwm@e6e80000 {
1426 compatible = "renesas
1427 reg = <0 0xe6e80000 0
1428 interrupts = <GIC_SPI
1429 clocks = <&cpg CPG_MO
1430 power-domains = <&sys
1431 resets = <&cpg 304>;
1432 #pwm-cells = <3>;
1433 status = "disabled";
1434 };
1435
1436 msiof0: spi@e6e90000 {
1437 compatible = "renesas
1438 "renesas
1439 reg = <0 0xe6e90000 0
1440 interrupts = <GIC_SPI
1441 clocks = <&cpg CPG_MO
1442 dmas = <&dmac1 0x41>,
1443 <&dmac2 0x41>,
1444 dma-names = "tx", "rx
1445 power-domains = <&sys
1446 resets = <&cpg 211>;
1447 #address-cells = <1>;
1448 #size-cells = <0>;
1449 status = "disabled";
1450 };
1451
1452 msiof1: spi@e6ea0000 {
1453 compatible = "renesas
1454 "renesas
1455 reg = <0 0xe6ea0000 0
1456 interrupts = <GIC_SPI
1457 clocks = <&cpg CPG_MO
1458 dmas = <&dmac1 0x43>,
1459 <&dmac2 0x43>,
1460 dma-names = "tx", "rx
1461 power-domains = <&sys
1462 resets = <&cpg 210>;
1463 #address-cells = <1>;
1464 #size-cells = <0>;
1465 status = "disabled";
1466 };
1467
1468 msiof2: spi@e6c00000 {
1469 compatible = "renesas
1470 "renesas
1471 reg = <0 0xe6c00000 0
1472 interrupts = <GIC_SPI
1473 clocks = <&cpg CPG_MO
1474 dmas = <&dmac0 0x45>,
1475 dma-names = "tx", "rx
1476 power-domains = <&sys
1477 resets = <&cpg 209>;
1478 #address-cells = <1>;
1479 #size-cells = <0>;
1480 status = "disabled";
1481 };
1482
1483 msiof3: spi@e6c10000 {
1484 compatible = "renesas
1485 "renesas
1486 reg = <0 0xe6c10000 0
1487 interrupts = <GIC_SPI
1488 clocks = <&cpg CPG_MO
1489 dmas = <&dmac0 0x47>,
1490 dma-names = "tx", "rx
1491 power-domains = <&sys
1492 resets = <&cpg 208>;
1493 #address-cells = <1>;
1494 #size-cells = <0>;
1495 status = "disabled";
1496 };
1497
1498 vin0: video@e6ef0000 {
1499 compatible = "renesas
1500 reg = <0 0xe6ef0000 0
1501 interrupts = <GIC_SPI
1502 clocks = <&cpg CPG_MO
1503 power-domains = <&sys
1504 resets = <&cpg 811>;
1505 renesas,id = <0>;
1506 status = "disabled";
1507
1508 ports {
1509 #address-cell
1510 #size-cells =
1511
1512 port@1 {
1513 #addr
1514 #size
1515
1516 reg =
1517
1518 vin0c
1519
1520
1521 };
1522 vin0c
1523
1524
1525 };
1526 };
1527 };
1528 };
1529
1530 vin1: video@e6ef1000 {
1531 compatible = "renesas
1532 reg = <0 0xe6ef1000 0
1533 interrupts = <GIC_SPI
1534 clocks = <&cpg CPG_MO
1535 power-domains = <&sys
1536 resets = <&cpg 810>;
1537 renesas,id = <1>;
1538 status = "disabled";
1539
1540 ports {
1541 #address-cell
1542 #size-cells =
1543
1544 port@1 {
1545 #addr
1546 #size
1547
1548 reg =
1549
1550 vin1c
1551
1552
1553 };
1554 vin1c
1555
1556
1557 };
1558 };
1559 };
1560 };
1561
1562 vin2: video@e6ef2000 {
1563 compatible = "renesas
1564 reg = <0 0xe6ef2000 0
1565 interrupts = <GIC_SPI
1566 clocks = <&cpg CPG_MO
1567 power-domains = <&sys
1568 resets = <&cpg 809>;
1569 renesas,id = <2>;
1570 status = "disabled";
1571
1572 ports {
1573 #address-cell
1574 #size-cells =
1575
1576 port@1 {
1577 #addr
1578 #size
1579
1580 reg =
1581
1582 vin2c
1583
1584
1585 };
1586 vin2c
1587
1588
1589 };
1590 };
1591 };
1592 };
1593
1594 vin3: video@e6ef3000 {
1595 compatible = "renesas
1596 reg = <0 0xe6ef3000 0
1597 interrupts = <GIC_SPI
1598 clocks = <&cpg CPG_MO
1599 power-domains = <&sys
1600 resets = <&cpg 808>;
1601 renesas,id = <3>;
1602 status = "disabled";
1603
1604 ports {
1605 #address-cell
1606 #size-cells =
1607
1608 port@1 {
1609 #addr
1610 #size
1611
1612 reg =
1613
1614 vin3c
1615
1616
1617 };
1618 vin3c
1619
1620
1621 };
1622 };
1623 };
1624 };
1625
1626 vin4: video@e6ef4000 {
1627 compatible = "renesas
1628 reg = <0 0xe6ef4000 0
1629 interrupts = <GIC_SPI
1630 clocks = <&cpg CPG_MO
1631 power-domains = <&sys
1632 resets = <&cpg 807>;
1633 renesas,id = <4>;
1634 status = "disabled";
1635
1636 ports {
1637 #address-cell
1638 #size-cells =
1639
1640 port@1 {
1641 #addr
1642 #size
1643
1644 reg =
1645
1646 vin4c
1647
1648
1649 };
1650 vin4c
1651
1652
1653 };
1654 };
1655 };
1656 };
1657
1658 vin5: video@e6ef5000 {
1659 compatible = "renesas
1660 reg = <0 0xe6ef5000 0
1661 interrupts = <GIC_SPI
1662 clocks = <&cpg CPG_MO
1663 power-domains = <&sys
1664 resets = <&cpg 806>;
1665 renesas,id = <5>;
1666 status = "disabled";
1667
1668 ports {
1669 #address-cell
1670 #size-cells =
1671
1672 port@1 {
1673 #addr
1674 #size
1675
1676 reg =
1677
1678 vin5c
1679
1680
1681 };
1682 vin5c
1683
1684
1685 };
1686 };
1687 };
1688 };
1689
1690 vin6: video@e6ef6000 {
1691 compatible = "renesas
1692 reg = <0 0xe6ef6000 0
1693 interrupts = <GIC_SPI
1694 clocks = <&cpg CPG_MO
1695 power-domains = <&sys
1696 resets = <&cpg 805>;
1697 renesas,id = <6>;
1698 status = "disabled";
1699
1700 ports {
1701 #address-cell
1702 #size-cells =
1703
1704 port@1 {
1705 #addr
1706 #size
1707
1708 reg =
1709
1710 vin6c
1711
1712
1713 };
1714 vin6c
1715
1716
1717 };
1718 };
1719 };
1720 };
1721
1722 vin7: video@e6ef7000 {
1723 compatible = "renesas
1724 reg = <0 0xe6ef7000 0
1725 interrupts = <GIC_SPI
1726 clocks = <&cpg CPG_MO
1727 power-domains = <&sys
1728 resets = <&cpg 804>;
1729 renesas,id = <7>;
1730 status = "disabled";
1731
1732 ports {
1733 #address-cell
1734 #size-cells =
1735
1736 port@1 {
1737 #addr
1738 #size
1739
1740 reg =
1741
1742 vin7c
1743
1744
1745 };
1746 vin7c
1747
1748
1749 };
1750 };
1751 };
1752 };
1753
1754 drif00: rif@e6f40000 {
1755 compatible = "renesas
1756 "renesas
1757 reg = <0 0xe6f40000 0
1758 interrupts = <GIC_SPI
1759 clocks = <&cpg CPG_MO
1760 clock-names = "fck";
1761 dmas = <&dmac1 0x20>,
1762 dma-names = "rx", "rx
1763 power-domains = <&sys
1764 resets = <&cpg 515>;
1765 renesas,bonding = <&d
1766 status = "disabled";
1767 };
1768
1769 drif01: rif@e6f50000 {
1770 compatible = "renesas
1771 "renesas
1772 reg = <0 0xe6f50000 0
1773 interrupts = <GIC_SPI
1774 clocks = <&cpg CPG_MO
1775 clock-names = "fck";
1776 dmas = <&dmac1 0x22>,
1777 dma-names = "rx", "rx
1778 power-domains = <&sys
1779 resets = <&cpg 514>;
1780 renesas,bonding = <&d
1781 status = "disabled";
1782 };
1783
1784 drif10: rif@e6f60000 {
1785 compatible = "renesas
1786 "renesas
1787 reg = <0 0xe6f60000 0
1788 interrupts = <GIC_SPI
1789 clocks = <&cpg CPG_MO
1790 clock-names = "fck";
1791 dmas = <&dmac1 0x24>,
1792 dma-names = "rx", "rx
1793 power-domains = <&sys
1794 resets = <&cpg 513>;
1795 renesas,bonding = <&d
1796 status = "disabled";
1797 };
1798
1799 drif11: rif@e6f70000 {
1800 compatible = "renesas
1801 "renesas
1802 reg = <0 0xe6f70000 0
1803 interrupts = <GIC_SPI
1804 clocks = <&cpg CPG_MO
1805 clock-names = "fck";
1806 dmas = <&dmac1 0x26>,
1807 dma-names = "rx", "rx
1808 power-domains = <&sys
1809 resets = <&cpg 512>;
1810 renesas,bonding = <&d
1811 status = "disabled";
1812 };
1813
1814 drif20: rif@e6f80000 {
1815 compatible = "renesas
1816 "renesas
1817 reg = <0 0xe6f80000 0
1818 interrupts = <GIC_SPI
1819 clocks = <&cpg CPG_MO
1820 clock-names = "fck";
1821 dmas = <&dmac1 0x28>,
1822 dma-names = "rx", "rx
1823 power-domains = <&sys
1824 resets = <&cpg 511>;
1825 renesas,bonding = <&d
1826 status = "disabled";
1827 };
1828
1829 drif21: rif@e6f90000 {
1830 compatible = "renesas
1831 "renesas
1832 reg = <0 0xe6f90000 0
1833 interrupts = <GIC_SPI
1834 clocks = <&cpg CPG_MO
1835 clock-names = "fck";
1836 dmas = <&dmac1 0x2a>,
1837 dma-names = "rx", "rx
1838 power-domains = <&sys
1839 resets = <&cpg 510>;
1840 renesas,bonding = <&d
1841 status = "disabled";
1842 };
1843
1844 drif30: rif@e6fa0000 {
1845 compatible = "renesas
1846 "renesas
1847 reg = <0 0xe6fa0000 0
1848 interrupts = <GIC_SPI
1849 clocks = <&cpg CPG_MO
1850 clock-names = "fck";
1851 dmas = <&dmac1 0x2c>,
1852 dma-names = "rx", "rx
1853 power-domains = <&sys
1854 resets = <&cpg 509>;
1855 renesas,bonding = <&d
1856 status = "disabled";
1857 };
1858
1859 drif31: rif@e6fb0000 {
1860 compatible = "renesas
1861 "renesas
1862 reg = <0 0xe6fb0000 0
1863 interrupts = <GIC_SPI
1864 clocks = <&cpg CPG_MO
1865 clock-names = "fck";
1866 dmas = <&dmac1 0x2e>,
1867 dma-names = "rx", "rx
1868 power-domains = <&sys
1869 resets = <&cpg 508>;
1870 renesas,bonding = <&d
1871 status = "disabled";
1872 };
1873
1874 rcar_sound: sound@ec500000 {
1875 /*
1876 * #sound-dai-cells i
1877 *
1878 * Single DAI : #soun
1879 * Multi DAI : #soun
1880 */
1881 /*
1882 * #clock-cells is re
1883 *
1884 * clkout : #cl
1885 * clkout0/1/2/3: #cl
1886 */
1887 compatible = "renesas
1888 reg = <0 0xec500000 0
1889 <0 0xec5a0000 0
1890 <0 0xec540000 0
1891 <0 0xec541000 0
1892 <0 0xec760000 0
1893 reg-names = "scu", "a
1894
1895 clocks = <&cpg CPG_MO
1896 <&cpg CPG_MO
1897 <&cpg CPG_MO
1898 <&cpg CPG_MO
1899 <&cpg CPG_MO
1900 <&cpg CPG_MO
1901 <&cpg CPG_MO
1902 <&cpg CPG_MO
1903 <&cpg CPG_MO
1904 <&cpg CPG_MO
1905 <&cpg CPG_MO
1906 <&cpg CPG_MO
1907 <&cpg CPG_MO
1908 <&cpg CPG_MO
1909 <&audio_clk_
1910 <&audio_clk_
1911 <&cpg CPG_MO
1912 clock-names = "ssi-al
1913 "ssi.9"
1914 "ssi.5"
1915 "ssi.1"
1916 "src.9"
1917 "src.5"
1918 "src.1"
1919 "mix.1"
1920 "ctu.1"
1921 "dvc.0"
1922 "clk_a"
1923 power-domains = <&sys
1924 resets = <&cpg 1005>,
1925 <&cpg 1006>,
1926 <&cpg 1008>,
1927 <&cpg 1010>,
1928 <&cpg 1012>,
1929 <&cpg 1014>,
1930 reset-names = "ssi-al
1931 "ssi.9"
1932 "ssi.5"
1933 "ssi.1"
1934 status = "disabled";
1935
1936 rcar_sound,ctu {
1937 ctu00: ctu-0
1938 ctu01: ctu-1
1939 ctu02: ctu-2
1940 ctu03: ctu-3
1941 ctu10: ctu-4
1942 ctu11: ctu-5
1943 ctu12: ctu-6
1944 ctu13: ctu-7
1945 };
1946
1947 rcar_sound,dvc {
1948 dvc0: dvc-0 {
1949 dmas
1950 dma-n
1951 };
1952 dvc1: dvc-1 {
1953 dmas
1954 dma-n
1955 };
1956 };
1957
1958 rcar_sound,mix {
1959 mix0: mix-0 {
1960 mix1: mix-1 {
1961 };
1962
1963 rcar_sound,src {
1964 src0: src-0 {
1965 inter
1966 dmas
1967 dma-n
1968 };
1969 src1: src-1 {
1970 inter
1971 dmas
1972 dma-n
1973 };
1974 src2: src-2 {
1975 inter
1976 dmas
1977 dma-n
1978 };
1979 src3: src-3 {
1980 inter
1981 dmas
1982 dma-n
1983 };
1984 src4: src-4 {
1985 inter
1986 dmas
1987 dma-n
1988 };
1989 src5: src-5 {
1990 inter
1991 dmas
1992 dma-n
1993 };
1994 src6: src-6 {
1995 inter
1996 dmas
1997 dma-n
1998 };
1999 src7: src-7 {
2000 inter
2001 dmas
2002 dma-n
2003 };
2004 src8: src-8 {
2005 inter
2006 dmas
2007 dma-n
2008 };
2009 src9: src-9 {
2010 inter
2011 dmas
2012 dma-n
2013 };
2014 };
2015
2016 rcar_sound,ssi {
2017 ssi0: ssi-0 {
2018 inter
2019 dmas
2020 dma-n
2021 };
2022 ssi1: ssi-1 {
2023 inter
2024 dmas
2025 dma-n
2026 };
2027 ssi2: ssi-2 {
2028 inter
2029 dmas
2030 dma-n
2031 };
2032 ssi3: ssi-3 {
2033 inter
2034 dmas
2035 dma-n
2036 };
2037 ssi4: ssi-4 {
2038 inter
2039 dmas
2040 dma-n
2041 };
2042 ssi5: ssi-5 {
2043 inter
2044 dmas
2045 dma-n
2046 };
2047 ssi6: ssi-6 {
2048 inter
2049 dmas
2050 dma-n
2051 };
2052 ssi7: ssi-7 {
2053 inter
2054 dmas
2055 dma-n
2056 };
2057 ssi8: ssi-8 {
2058 inter
2059 dmas
2060 dma-n
2061 };
2062 ssi9: ssi-9 {
2063 inter
2064 dmas
2065 dma-n
2066 };
2067 };
2068
2069 rcar_sound,ssiu {
2070 ssiu00: ssiu-
2071 dmas
2072 dma-n
2073 };
2074 ssiu01: ssiu-
2075 dmas
2076 dma-n
2077 };
2078 ssiu02: ssiu-
2079 dmas
2080 dma-n
2081 };
2082 ssiu03: ssiu-
2083 dmas
2084 dma-n
2085 };
2086 ssiu04: ssiu-
2087 dmas
2088 dma-n
2089 };
2090 ssiu05: ssiu-
2091 dmas
2092 dma-n
2093 };
2094 ssiu06: ssiu-
2095 dmas
2096 dma-n
2097 };
2098 ssiu07: ssiu-
2099 dmas
2100 dma-n
2101 };
2102 ssiu10: ssiu-
2103 dmas
2104 dma-n
2105 };
2106 ssiu11: ssiu-
2107 dmas
2108 dma-n
2109 };
2110 ssiu12: ssiu-
2111 dmas
2112 dma-n
2113 };
2114 ssiu13: ssiu-
2115 dmas
2116 dma-n
2117 };
2118 ssiu14: ssiu-
2119 dmas
2120 dma-n
2121 };
2122 ssiu15: ssiu-
2123 dmas
2124 dma-n
2125 };
2126 ssiu16: ssiu-
2127 dmas
2128 dma-n
2129 };
2130 ssiu17: ssiu-
2131 dmas
2132 dma-n
2133 };
2134 ssiu20: ssiu-
2135 dmas
2136 dma-n
2137 };
2138 ssiu21: ssiu-
2139 dmas
2140 dma-n
2141 };
2142 ssiu22: ssiu-
2143 dmas
2144 dma-n
2145 };
2146 ssiu23: ssiu-
2147 dmas
2148 dma-n
2149 };
2150 ssiu24: ssiu-
2151 dmas
2152 dma-n
2153 };
2154 ssiu25: ssiu-
2155 dmas
2156 dma-n
2157 };
2158 ssiu26: ssiu-
2159 dmas
2160 dma-n
2161 };
2162 ssiu27: ssiu-
2163 dmas
2164 dma-n
2165 };
2166 ssiu30: ssiu-
2167 dmas
2168 dma-n
2169 };
2170 ssiu31: ssiu-
2171 dmas
2172 dma-n
2173 };
2174 ssiu32: ssiu-
2175 dmas
2176 dma-n
2177 };
2178 ssiu33: ssiu-
2179 dmas
2180 dma-n
2181 };
2182 ssiu34: ssiu-
2183 dmas
2184 dma-n
2185 };
2186 ssiu35: ssiu-
2187 dmas
2188 dma-n
2189 };
2190 ssiu36: ssiu-
2191 dmas
2192 dma-n
2193 };
2194 ssiu37: ssiu-
2195 dmas
2196 dma-n
2197 };
2198 ssiu40: ssiu-
2199 dmas
2200 dma-n
2201 };
2202 ssiu41: ssiu-
2203 dmas
2204 dma-n
2205 };
2206 ssiu42: ssiu-
2207 dmas
2208 dma-n
2209 };
2210 ssiu43: ssiu-
2211 dmas
2212 dma-n
2213 };
2214 ssiu44: ssiu-
2215 dmas
2216 dma-n
2217 };
2218 ssiu45: ssiu-
2219 dmas
2220 dma-n
2221 };
2222 ssiu46: ssiu-
2223 dmas
2224 dma-n
2225 };
2226 ssiu47: ssiu-
2227 dmas
2228 dma-n
2229 };
2230 ssiu50: ssiu-
2231 dmas
2232 dma-n
2233 };
2234 ssiu60: ssiu-
2235 dmas
2236 dma-n
2237 };
2238 ssiu70: ssiu-
2239 dmas
2240 dma-n
2241 };
2242 ssiu80: ssiu-
2243 dmas
2244 dma-n
2245 };
2246 ssiu90: ssiu-
2247 dmas
2248 dma-n
2249 };
2250 ssiu91: ssiu-
2251 dmas
2252 dma-n
2253 };
2254 ssiu92: ssiu-
2255 dmas
2256 dma-n
2257 };
2258 ssiu93: ssiu-
2259 dmas
2260 dma-n
2261 };
2262 ssiu94: ssiu-
2263 dmas
2264 dma-n
2265 };
2266 ssiu95: ssiu-
2267 dmas
2268 dma-n
2269 };
2270 ssiu96: ssiu-
2271 dmas
2272 dma-n
2273 };
2274 ssiu97: ssiu-
2275 dmas
2276 dma-n
2277 };
2278 };
2279 };
2280
2281 mlp: mlp@ec520000 {
2282 compatible = "renesas
2283 "renesas
2284 reg = <0 0xec520000 0
2285 interrupts = <GIC_SPI
2286 <GIC_SPI 385
2287 clocks = <&cpg CPG_MO
2288 power-domains = <&sys
2289 resets = <&cpg 802>;
2290 status = "disabled";
2291 };
2292
2293 audma0: dma-controller@ec7000
2294 compatible = "renesas
2295 "renesas
2296 reg = <0 0xec700000 0
2297 interrupts = <GIC_SPI
2298 <GIC_SPI
2299 <GIC_SPI
2300 <GIC_SPI
2301 <GIC_SPI
2302 <GIC_SPI
2303 <GIC_SPI
2304 <GIC_SPI
2305 <GIC_SPI
2306 <GIC_SPI
2307 <GIC_SPI
2308 <GIC_SPI
2309 <GIC_SPI
2310 <GIC_SPI
2311 <GIC_SPI
2312 <GIC_SPI
2313 <GIC_SPI
2314 interrupt-names = "er
2315 "ch0"
2316 "ch4"
2317 "ch8"
2318 "ch12
2319 clocks = <&cpg CPG_MO
2320 clock-names = "fck";
2321 power-domains = <&sys
2322 resets = <&cpg 502>;
2323 #dma-cells = <1>;
2324 dma-channels = <16>;
2325 iommus = <&ipmmu_mp 0
2326 <&ipmmu_mp 2>,
2327 <&ipmmu_mp 4>,
2328 <&ipmmu_mp 6>,
2329 <&ipmmu_mp 8>,
2330 <&ipmmu_mp 10>
2331 <&ipmmu_mp 12>
2332 <&ipmmu_mp 14>
2333 };
2334
2335 audma1: dma-controller@ec7200
2336 compatible = "renesas
2337 "renesas
2338 reg = <0 0xec720000 0
2339 interrupts = <GIC_SPI
2340 <GIC_SPI
2341 <GIC_SPI
2342 <GIC_SPI
2343 <GIC_SPI
2344 <GIC_SPI
2345 <GIC_SPI
2346 <GIC_SPI
2347 <GIC_SPI
2348 <GIC_SPI
2349 <GIC_SPI
2350 <GIC_SPI
2351 <GIC_SPI
2352 <GIC_SPI
2353 <GIC_SPI
2354 <GIC_SPI
2355 <GIC_SPI
2356 interrupt-names = "er
2357 "ch0"
2358 "ch4"
2359 "ch8"
2360 "ch12
2361 clocks = <&cpg CPG_MO
2362 clock-names = "fck";
2363 power-domains = <&sys
2364 resets = <&cpg 501>;
2365 #dma-cells = <1>;
2366 dma-channels = <16>;
2367 iommus = <&ipmmu_mp 1
2368 <&ipmmu_mp 18>
2369 <&ipmmu_mp 20>
2370 <&ipmmu_mp 22>
2371 <&ipmmu_mp 24>
2372 <&ipmmu_mp 26>
2373 <&ipmmu_mp 28>
2374 <&ipmmu_mp 30>
2375 };
2376
2377 xhci0: usb@ee000000 {
2378 compatible = "renesas
2379 "renesas
2380 reg = <0 0xee000000 0
2381 interrupts = <GIC_SPI
2382 clocks = <&cpg CPG_MO
2383 power-domains = <&sys
2384 resets = <&cpg 328>;
2385 status = "disabled";
2386 };
2387
2388 usb3_peri0: usb@ee020000 {
2389 compatible = "renesas
2390 "renesas
2391 reg = <0 0xee020000 0
2392 interrupts = <GIC_SPI
2393 clocks = <&cpg CPG_MO
2394 power-domains = <&sys
2395 resets = <&cpg 328>;
2396 status = "disabled";
2397 };
2398
2399 ohci0: usb@ee080000 {
2400 compatible = "generic
2401 reg = <0 0xee080000 0
2402 interrupts = <GIC_SPI
2403 clocks = <&cpg CPG_MO
2404 phys = <&usb2_phy0 1>
2405 phy-names = "usb";
2406 power-domains = <&sys
2407 resets = <&cpg 703>,
2408 status = "disabled";
2409 };
2410
2411 ohci1: usb@ee0a0000 {
2412 compatible = "generic
2413 reg = <0 0xee0a0000 0
2414 interrupts = <GIC_SPI
2415 clocks = <&cpg CPG_MO
2416 phys = <&usb2_phy1 1>
2417 phy-names = "usb";
2418 power-domains = <&sys
2419 resets = <&cpg 702>;
2420 status = "disabled";
2421 };
2422
2423 ehci0: usb@ee080100 {
2424 compatible = "generic
2425 reg = <0 0xee080100 0
2426 interrupts = <GIC_SPI
2427 clocks = <&cpg CPG_MO
2428 phys = <&usb2_phy0 2>
2429 phy-names = "usb";
2430 companion = <&ohci0>;
2431 power-domains = <&sys
2432 resets = <&cpg 703>,
2433 status = "disabled";
2434 };
2435
2436 ehci1: usb@ee0a0100 {
2437 compatible = "generic
2438 reg = <0 0xee0a0100 0
2439 interrupts = <GIC_SPI
2440 clocks = <&cpg CPG_MO
2441 phys = <&usb2_phy1 2>
2442 phy-names = "usb";
2443 companion = <&ohci1>;
2444 power-domains = <&sys
2445 resets = <&cpg 702>;
2446 status = "disabled";
2447 };
2448
2449 usb2_phy0: usb-phy@ee080200 {
2450 compatible = "renesas
2451 "renesas
2452 reg = <0 0xee080200 0
2453 interrupts = <GIC_SPI
2454 clocks = <&cpg CPG_MO
2455 power-domains = <&sys
2456 resets = <&cpg 703>,
2457 #phy-cells = <1>;
2458 status = "disabled";
2459 };
2460
2461 usb2_phy1: usb-phy@ee0a0200 {
2462 compatible = "renesas
2463 "renesas
2464 reg = <0 0xee0a0200 0
2465 clocks = <&cpg CPG_MO
2466 power-domains = <&sys
2467 resets = <&cpg 702>;
2468 #phy-cells = <1>;
2469 status = "disabled";
2470 };
2471
2472 sdhi0: mmc@ee100000 {
2473 compatible = "renesas
2474 "renesas
2475 reg = <0 0xee100000 0
2476 interrupts = <GIC_SPI
2477 clocks = <&cpg CPG_MO
2478 clock-names = "core",
2479 max-frequency = <2000
2480 power-domains = <&sys
2481 resets = <&cpg 314>;
2482 iommus = <&ipmmu_ds1
2483 status = "disabled";
2484 };
2485
2486 sdhi1: mmc@ee120000 {
2487 compatible = "renesas
2488 "renesas
2489 reg = <0 0xee120000 0
2490 interrupts = <GIC_SPI
2491 clocks = <&cpg CPG_MO
2492 clock-names = "core",
2493 max-frequency = <2000
2494 power-domains = <&sys
2495 resets = <&cpg 313>;
2496 iommus = <&ipmmu_ds1
2497 status = "disabled";
2498 };
2499
2500 sdhi2: mmc@ee140000 {
2501 compatible = "renesas
2502 "renesas
2503 reg = <0 0xee140000 0
2504 interrupts = <GIC_SPI
2505 clocks = <&cpg CPG_MO
2506 clock-names = "core",
2507 max-frequency = <2000
2508 power-domains = <&sys
2509 resets = <&cpg 312>;
2510 iommus = <&ipmmu_ds1
2511 status = "disabled";
2512 };
2513
2514 sdhi3: mmc@ee160000 {
2515 compatible = "renesas
2516 "renesas
2517 reg = <0 0xee160000 0
2518 interrupts = <GIC_SPI
2519 clocks = <&cpg CPG_MO
2520 clock-names = "core",
2521 max-frequency = <2000
2522 power-domains = <&sys
2523 resets = <&cpg 311>;
2524 iommus = <&ipmmu_ds1
2525 status = "disabled";
2526 };
2527
2528 rpc: spi@ee200000 {
2529 compatible = "renesas
2530 "renesas
2531 reg = <0 0xee200000 0
2532 <0 0x08000000 0
2533 <0 0xee208000 0
2534 reg-names = "regs", "
2535 interrupts = <GIC_SPI
2536 clocks = <&cpg CPG_MO
2537 power-domains = <&sys
2538 resets = <&cpg 917>;
2539 #address-cells = <1>;
2540 #size-cells = <0>;
2541 status = "disabled";
2542 };
2543
2544 gic: interrupt-controller@f10
2545 compatible = "arm,gic
2546 #interrupt-cells = <3
2547 #address-cells = <0>;
2548 interrupt-controller;
2549 reg = <0x0 0xf1010000
2550 <0x0 0xf1020000
2551 <0x0 0xf1040000
2552 <0x0 0xf1060000
2553 interrupts = <GIC_PPI
2554 (GIC_
2555 clocks = <&cpg CPG_MO
2556 clock-names = "clk";
2557 power-domains = <&sys
2558 resets = <&cpg 408>;
2559 };
2560
2561 pciec0: pcie@fe000000 {
2562 compatible = "renesas
2563 "renesas
2564 reg = <0 0xfe000000 0
2565 #address-cells = <3>;
2566 #size-cells = <2>;
2567 bus-range = <0x00 0xf
2568 device_type = "pci";
2569 ranges = <0x01000000
2570 <0x02000000
2571 <0x02000000
2572 <0x42000000
2573 /* Map all possible D
2574 dma-ranges = <0x42000
2575 interrupts = <GIC_SPI
2576 <GIC_SPI 117
2577 <GIC_SPI 118
2578 #interrupt-cells = <1
2579 interrupt-map-mask =
2580 interrupt-map = <0 0
2581 clocks = <&cpg CPG_MO
2582 clock-names = "pcie",
2583 power-domains = <&sys
2584 resets = <&cpg 319>;
2585 iommu-map = <0 &ipmmu
2586 iommu-map-mask = <0>;
2587 status = "disabled";
2588 };
2589
2590 pciec1: pcie@ee800000 {
2591 compatible = "renesas
2592 "renesas
2593 reg = <0 0xee800000 0
2594 #address-cells = <3>;
2595 #size-cells = <2>;
2596 bus-range = <0x00 0xf
2597 device_type = "pci";
2598 ranges = <0x01000000
2599 <0x02000000
2600 <0x02000000
2601 <0x42000000
2602 /* Map all possible D
2603 dma-ranges = <0x42000
2604 interrupts = <GIC_SPI
2605 <GIC_SPI 149
2606 <GIC_SPI 150
2607 #interrupt-cells = <1
2608 interrupt-map-mask =
2609 interrupt-map = <0 0
2610 clocks = <&cpg CPG_MO
2611 clock-names = "pcie",
2612 power-domains = <&sys
2613 resets = <&cpg 318>;
2614 iommu-map = <0 &ipmmu
2615 iommu-map-mask = <0>;
2616 status = "disabled";
2617 };
2618
2619 imr-lx4@fe860000 {
2620 compatible = "renesas
2621 "renesas
2622 reg = <0 0xfe860000 0
2623 interrupts = <GIC_SPI
2624 clocks = <&cpg CPG_MO
2625 power-domains = <&sys
2626 resets = <&cpg 823>;
2627 };
2628
2629 imr-lx4@fe870000 {
2630 compatible = "renesas
2631 "renesas
2632 reg = <0 0xfe870000 0
2633 interrupts = <GIC_SPI
2634 clocks = <&cpg CPG_MO
2635 power-domains = <&sys
2636 resets = <&cpg 822>;
2637 };
2638
2639 fdp1@fe940000 {
2640 compatible = "renesas
2641 reg = <0 0xfe940000 0
2642 interrupts = <GIC_SPI
2643 clocks = <&cpg CPG_MO
2644 power-domains = <&sys
2645 resets = <&cpg 119>;
2646 renesas,fcp = <&fcpf0
2647 };
2648
2649 fcpf0: fcp@fe950000 {
2650 compatible = "renesas
2651 reg = <0 0xfe950000 0
2652 clocks = <&cpg CPG_MO
2653 power-domains = <&sys
2654 resets = <&cpg 615>;
2655 iommus = <&ipmmu_vc0
2656 };
2657
2658 fcpvb0: fcp@fe96f000 {
2659 compatible = "renesas
2660 reg = <0 0xfe96f000 0
2661 clocks = <&cpg CPG_MO
2662 power-domains = <&sys
2663 resets = <&cpg 607>;
2664 iommus = <&ipmmu_vi0
2665 };
2666
2667 fcpvi0: fcp@fe9af000 {
2668 compatible = "renesas
2669 reg = <0 0xfe9af000 0
2670 clocks = <&cpg CPG_MO
2671 power-domains = <&sys
2672 resets = <&cpg 611>;
2673 iommus = <&ipmmu_vc0
2674 };
2675
2676 fcpvd0: fcp@fea27000 {
2677 compatible = "renesas
2678 reg = <0 0xfea27000 0
2679 clocks = <&cpg CPG_MO
2680 power-domains = <&sys
2681 resets = <&cpg 603>;
2682 iommus = <&ipmmu_vi0
2683 };
2684
2685 fcpvd1: fcp@fea2f000 {
2686 compatible = "renesas
2687 reg = <0 0xfea2f000 0
2688 clocks = <&cpg CPG_MO
2689 power-domains = <&sys
2690 resets = <&cpg 602>;
2691 iommus = <&ipmmu_vi0
2692 };
2693
2694 fcpvd2: fcp@fea37000 {
2695 compatible = "renesas
2696 reg = <0 0xfea37000 0
2697 clocks = <&cpg CPG_MO
2698 power-domains = <&sys
2699 resets = <&cpg 601>;
2700 iommus = <&ipmmu_vi0
2701 };
2702
2703 vspb: vsp@fe960000 {
2704 compatible = "renesas
2705 reg = <0 0xfe960000 0
2706 interrupts = <GIC_SPI
2707 clocks = <&cpg CPG_MO
2708 power-domains = <&sys
2709 resets = <&cpg 626>;
2710
2711 renesas,fcp = <&fcpvb
2712 };
2713
2714 vspd0: vsp@fea20000 {
2715 compatible = "renesas
2716 reg = <0 0xfea20000 0
2717 interrupts = <GIC_SPI
2718 clocks = <&cpg CPG_MO
2719 power-domains = <&sys
2720 resets = <&cpg 623>;
2721
2722 renesas,fcp = <&fcpvd
2723 };
2724
2725 vspd1: vsp@fea28000 {
2726 compatible = "renesas
2727 reg = <0 0xfea28000 0
2728 interrupts = <GIC_SPI
2729 clocks = <&cpg CPG_MO
2730 power-domains = <&sys
2731 resets = <&cpg 622>;
2732
2733 renesas,fcp = <&fcpvd
2734 };
2735
2736 vspd2: vsp@fea30000 {
2737 compatible = "renesas
2738 reg = <0 0xfea30000 0
2739 interrupts = <GIC_SPI
2740 clocks = <&cpg CPG_MO
2741 power-domains = <&sys
2742 resets = <&cpg 621>;
2743
2744 renesas,fcp = <&fcpvd
2745 };
2746
2747 vspi0: vsp@fe9a0000 {
2748 compatible = "renesas
2749 reg = <0 0xfe9a0000 0
2750 interrupts = <GIC_SPI
2751 clocks = <&cpg CPG_MO
2752 power-domains = <&sys
2753 resets = <&cpg 631>;
2754
2755 renesas,fcp = <&fcpvi
2756 };
2757
2758 cmm0: cmm@fea40000 {
2759 compatible = "renesas
2760 "renesas
2761 reg = <0 0xfea40000 0
2762 power-domains = <&sys
2763 clocks = <&cpg CPG_MO
2764 resets = <&cpg 711>;
2765 };
2766
2767 cmm1: cmm@fea50000 {
2768 compatible = "renesas
2769 "renesas
2770 reg = <0 0xfea50000 0
2771 power-domains = <&sys
2772 clocks = <&cpg CPG_MO
2773 resets = <&cpg 710>;
2774 };
2775
2776 cmm2: cmm@fea60000 {
2777 compatible = "renesas
2778 "renesas
2779 reg = <0 0xfea60000 0
2780 power-domains = <&sys
2781 clocks = <&cpg CPG_MO
2782 resets = <&cpg 709>;
2783 };
2784
2785 csi20: csi2@fea80000 {
2786 compatible = "renesas
2787 reg = <0 0xfea80000 0
2788 interrupts = <GIC_SPI
2789 clocks = <&cpg CPG_MO
2790 power-domains = <&sys
2791 resets = <&cpg 714>;
2792 status = "disabled";
2793
2794 ports {
2795 #address-cell
2796 #size-cells =
2797
2798 port@0 {
2799 reg =
2800 };
2801
2802 port@1 {
2803 #addr
2804 #size
2805
2806 reg =
2807
2808 csi20
2809
2810
2811 };
2812 csi20
2813
2814
2815 };
2816 csi20
2817
2818
2819 };
2820 csi20
2821
2822
2823 };
2824 csi20
2825
2826
2827 };
2828 csi20
2829
2830
2831 };
2832 csi20
2833
2834
2835 };
2836 csi20
2837
2838
2839 };
2840 };
2841 };
2842 };
2843
2844 csi40: csi2@feaa0000 {
2845 compatible = "renesas
2846 reg = <0 0xfeaa0000 0
2847 interrupts = <GIC_SPI
2848 clocks = <&cpg CPG_MO
2849 power-domains = <&sys
2850 resets = <&cpg 716>;
2851 status = "disabled";
2852
2853 ports {
2854 #address-cell
2855 #size-cells =
2856
2857 port@0 {
2858 reg =
2859 };
2860
2861 port@1 {
2862 #addr
2863 #size
2864
2865 reg =
2866
2867 csi40
2868
2869
2870 };
2871 csi40
2872
2873
2874 };
2875 csi40
2876
2877
2878 };
2879 csi40
2880
2881
2882 };
2883 csi40
2884
2885
2886 };
2887 csi40
2888
2889
2890 };
2891 csi40
2892
2893
2894 };
2895 csi40
2896
2897
2898 };
2899 };
2900
2901 };
2902 };
2903
2904 hdmi0: hdmi@fead0000 {
2905 compatible = "renesas
2906 reg = <0 0xfead0000 0
2907 interrupts = <GIC_SPI
2908 clocks = <&cpg CPG_MO
2909 clock-names = "iahb",
2910 power-domains = <&sys
2911 resets = <&cpg 729>;
2912 status = "disabled";
2913
2914 ports {
2915 #address-cell
2916 #size-cells =
2917 port@0 {
2918 reg =
2919 dw_hd
2920
2921 };
2922 };
2923 port@1 {
2924 reg =
2925 };
2926 port@2 {
2927 /* HD
2928 reg =
2929 };
2930 };
2931 };
2932
2933 du: display@feb00000 {
2934 compatible = "renesas
2935 reg = <0 0xfeb00000 0
2936 interrupts = <GIC_SPI
2937 <GIC_SPI
2938 <GIC_SPI
2939 clocks = <&cpg CPG_MO
2940 <&cpg CPG_MO
2941 clock-names = "du.0",
2942 resets = <&cpg 724>,
2943 reset-names = "du.0",
2944
2945 renesas,cmms = <&cmm0
2946 renesas,vsps = <&vspd
2947
2948 status = "disabled";
2949
2950 ports {
2951 #address-cell
2952 #size-cells =
2953
2954 port@0 {
2955 reg =
2956 };
2957 port@1 {
2958 reg =
2959 du_ou
2960
2961 };
2962 };
2963 port@2 {
2964 reg =
2965 du_ou
2966
2967 };
2968 };
2969 };
2970 };
2971
2972 lvds0: lvds@feb90000 {
2973 compatible = "renesas
2974 reg = <0 0xfeb90000 0
2975 clocks = <&cpg CPG_MO
2976 power-domains = <&sys
2977 resets = <&cpg 727>;
2978 status = "disabled";
2979
2980 ports {
2981 #address-cell
2982 #size-cells =
2983
2984 port@0 {
2985 reg =
2986 lvds0
2987
2988 };
2989 };
2990 port@1 {
2991 reg =
2992 };
2993 };
2994 };
2995
2996 prr: chipid@fff00044 {
2997 compatible = "renesas
2998 reg = <0 0xfff00044 0
2999 };
3000 };
3001
3002 thermal-zones {
3003 sensor1_thermal: sensor1-ther
3004 polling-delay-passive
3005 polling-delay = <1000
3006 thermal-sensors = <&t
3007 sustainable-power = <
3008
3009 trips {
3010 sensor1_crit:
3011 tempe
3012 hyste
3013 type
3014 };
3015 };
3016 };
3017
3018 sensor2_thermal: sensor2-ther
3019 polling-delay-passive
3020 polling-delay = <1000
3021 thermal-sensors = <&t
3022 sustainable-power = <
3023
3024 trips {
3025 sensor2_crit:
3026 tempe
3027 hyste
3028 type
3029 };
3030 };
3031 };
3032
3033 sensor3_thermal: sensor3-ther
3034 polling-delay-passive
3035 polling-delay = <1000
3036 thermal-sensors = <&t
3037 sustainable-power = <
3038
3039 cooling-maps {
3040 map0 {
3041 trip
3042 cooli
3043 contr
3044 };
3045 map1 {
3046 trip
3047 cooli
3048 contr
3049 };
3050 };
3051 trips {
3052 target: trip-
3053 tempe
3054 hyste
3055 type
3056 };
3057
3058 sensor3_crit:
3059 tempe
3060 hyste
3061 type
3062 };
3063 };
3064 };
3065 };
3066
3067 timer {
3068 compatible = "arm,armv8-timer
3069 interrupts-extended = <&gic G
3070 <&gic G
3071 <&gic G
3072 <&gic G
3073 interrupt-names = "sec-phys",
3074 };
3075
3076 /* External USB clocks - can be overr
3077 usb3s0_clk: usb3s0 {
3078 compatible = "fixed-clock";
3079 #clock-cells = <0>;
3080 clock-frequency = <0>;
3081 };
3082
3083 usb_extal_clk: usb_extal {
3084 compatible = "fixed-clock";
3085 #clock-cells = <0>;
3086 clock-frequency = <0>;
3087 };
3088 };
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