1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * Device Tree Source for the R-Car M3-W (R8A7 3 * Device Tree Source for the R-Car M3-W (R8A77960) SoC
4 * 4 *
5 * Copyright (C) 2016-2017 Renesas Electronics 5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
6 */ 6 */
7 7
8 #include <dt-bindings/clock/r8a7796-cpg-mssr.h 8 #include <dt-bindings/clock/r8a7796-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm 9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a7796-sysc.h> 10 #include <dt-bindings/power/r8a7796-sysc.h>
11 11
>> 12 #define CPG_AUDIO_CLK_I R8A7796_CLK_S0D4
>> 13
12 / { 14 / {
13 compatible = "renesas,r8a7796"; 15 compatible = "renesas,r8a7796";
14 #address-cells = <2>; 16 #address-cells = <2>;
15 #size-cells = <2>; 17 #size-cells = <2>;
16 18
>> 19 aliases {
>> 20 i2c0 = &i2c0;
>> 21 i2c1 = &i2c1;
>> 22 i2c2 = &i2c2;
>> 23 i2c3 = &i2c3;
>> 24 i2c4 = &i2c4;
>> 25 i2c5 = &i2c5;
>> 26 i2c6 = &i2c6;
>> 27 i2c7 = &i2c_dvfs;
>> 28 };
>> 29
17 /* 30 /*
18 * The external audio clocks are confi 31 * The external audio clocks are configured as 0 Hz fixed frequency
19 * clocks by default. 32 * clocks by default.
20 * Boards that provide audio clocks sh 33 * Boards that provide audio clocks should override them.
21 */ 34 */
22 audio_clk_a: audio_clk_a { 35 audio_clk_a: audio_clk_a {
23 compatible = "fixed-clock"; 36 compatible = "fixed-clock";
24 #clock-cells = <0>; 37 #clock-cells = <0>;
25 clock-frequency = <0>; 38 clock-frequency = <0>;
26 }; 39 };
27 40
28 audio_clk_b: audio_clk_b { 41 audio_clk_b: audio_clk_b {
29 compatible = "fixed-clock"; 42 compatible = "fixed-clock";
30 #clock-cells = <0>; 43 #clock-cells = <0>;
31 clock-frequency = <0>; 44 clock-frequency = <0>;
32 }; 45 };
33 46
34 audio_clk_c: audio_clk_c { 47 audio_clk_c: audio_clk_c {
35 compatible = "fixed-clock"; 48 compatible = "fixed-clock";
36 #clock-cells = <0>; 49 #clock-cells = <0>;
37 clock-frequency = <0>; 50 clock-frequency = <0>;
38 }; 51 };
39 52
40 /* External CAN clock - to be overridd 53 /* External CAN clock - to be overridden by boards that provide it */
41 can_clk: can { 54 can_clk: can {
42 compatible = "fixed-clock"; 55 compatible = "fixed-clock";
43 #clock-cells = <0>; 56 #clock-cells = <0>;
44 clock-frequency = <0>; 57 clock-frequency = <0>;
45 }; 58 };
46 59
47 cluster0_opp: opp-table-0 { !! 60 cluster0_opp: opp_table0 {
48 compatible = "operating-points 61 compatible = "operating-points-v2";
49 opp-shared; 62 opp-shared;
50 63
51 opp-500000000 { 64 opp-500000000 {
52 opp-hz = /bits/ 64 <50 65 opp-hz = /bits/ 64 <500000000>;
53 opp-microvolt = <83000 66 opp-microvolt = <830000>;
54 clock-latency-ns = <30 67 clock-latency-ns = <300000>;
55 }; 68 };
56 opp-1000000000 { 69 opp-1000000000 {
57 opp-hz = /bits/ 64 <10 70 opp-hz = /bits/ 64 <1000000000>;
58 opp-microvolt = <83000 71 opp-microvolt = <830000>;
59 clock-latency-ns = <30 72 clock-latency-ns = <300000>;
60 }; 73 };
61 opp-1500000000 { 74 opp-1500000000 {
62 opp-hz = /bits/ 64 <15 75 opp-hz = /bits/ 64 <1500000000>;
63 opp-microvolt = <83000 76 opp-microvolt = <830000>;
64 clock-latency-ns = <30 77 clock-latency-ns = <300000>;
65 opp-suspend; 78 opp-suspend;
66 }; 79 };
67 opp-1600000000 { 80 opp-1600000000 {
68 opp-hz = /bits/ 64 <16 81 opp-hz = /bits/ 64 <1600000000>;
69 opp-microvolt = <90000 82 opp-microvolt = <900000>;
70 clock-latency-ns = <30 83 clock-latency-ns = <300000>;
>> 84 turbo-mode;
71 }; 85 };
72 opp-1700000000 { 86 opp-1700000000 {
73 opp-hz = /bits/ 64 <17 87 opp-hz = /bits/ 64 <1700000000>;
74 opp-microvolt = <90000 88 opp-microvolt = <900000>;
75 clock-latency-ns = <30 89 clock-latency-ns = <300000>;
>> 90 turbo-mode;
76 }; 91 };
77 opp-1800000000 { 92 opp-1800000000 {
78 opp-hz = /bits/ 64 <18 93 opp-hz = /bits/ 64 <1800000000>;
79 opp-microvolt = <96000 94 opp-microvolt = <960000>;
80 clock-latency-ns = <30 95 clock-latency-ns = <300000>;
81 turbo-mode; 96 turbo-mode;
82 }; 97 };
83 }; 98 };
84 99
85 cluster1_opp: opp-table-1 { !! 100 cluster1_opp: opp_table1 {
86 compatible = "operating-points 101 compatible = "operating-points-v2";
87 opp-shared; 102 opp-shared;
88 103
89 opp-800000000 { 104 opp-800000000 {
90 opp-hz = /bits/ 64 <80 105 opp-hz = /bits/ 64 <800000000>;
91 opp-microvolt = <82000 106 opp-microvolt = <820000>;
92 clock-latency-ns = <30 107 clock-latency-ns = <300000>;
93 }; 108 };
94 opp-1000000000 { 109 opp-1000000000 {
95 opp-hz = /bits/ 64 <10 110 opp-hz = /bits/ 64 <1000000000>;
96 opp-microvolt = <82000 111 opp-microvolt = <820000>;
97 clock-latency-ns = <30 112 clock-latency-ns = <300000>;
98 }; 113 };
99 opp-1200000000 { 114 opp-1200000000 {
100 opp-hz = /bits/ 64 <12 115 opp-hz = /bits/ 64 <1200000000>;
101 opp-microvolt = <82000 116 opp-microvolt = <820000>;
102 clock-latency-ns = <30 117 clock-latency-ns = <300000>;
103 }; 118 };
104 opp-1300000000 { 119 opp-1300000000 {
105 opp-hz = /bits/ 64 <13 120 opp-hz = /bits/ 64 <1300000000>;
106 opp-microvolt = <82000 121 opp-microvolt = <820000>;
107 clock-latency-ns = <30 122 clock-latency-ns = <300000>;
108 turbo-mode; 123 turbo-mode;
109 }; 124 };
110 }; 125 };
111 126
112 cpus { 127 cpus {
113 #address-cells = <1>; 128 #address-cells = <1>;
114 #size-cells = <0>; 129 #size-cells = <0>;
115 130
116 cpu-map { 131 cpu-map {
117 cluster0 { 132 cluster0 {
118 core0 { 133 core0 {
119 cpu = 134 cpu = <&a57_0>;
120 }; 135 };
121 core1 { 136 core1 {
122 cpu = 137 cpu = <&a57_1>;
123 }; 138 };
124 }; 139 };
125 140
126 cluster1 { 141 cluster1 {
127 core0 { 142 core0 {
128 cpu = 143 cpu = <&a53_0>;
129 }; 144 };
130 core1 { 145 core1 {
131 cpu = 146 cpu = <&a53_1>;
132 }; 147 };
133 core2 { 148 core2 {
134 cpu = 149 cpu = <&a53_2>;
135 }; 150 };
136 core3 { 151 core3 {
137 cpu = 152 cpu = <&a53_3>;
138 }; 153 };
139 }; 154 };
140 }; 155 };
141 156
142 a57_0: cpu@0 { 157 a57_0: cpu@0 {
143 compatible = "arm,cort 158 compatible = "arm,cortex-a57";
144 reg = <0x0>; 159 reg = <0x0>;
145 device_type = "cpu"; 160 device_type = "cpu";
146 power-domains = <&sysc 161 power-domains = <&sysc R8A7796_PD_CA57_CPU0>;
147 next-level-cache = <&L 162 next-level-cache = <&L2_CA57>;
148 enable-method = "psci" 163 enable-method = "psci";
149 cpu-idle-states = <&CP 164 cpu-idle-states = <&CPU_SLEEP_0>;
150 dynamic-power-coeffici 165 dynamic-power-coefficient = <854>;
151 clocks = <&cpg CPG_COR 166 clocks = <&cpg CPG_CORE R8A7796_CLK_Z>;
152 operating-points-v2 = 167 operating-points-v2 = <&cluster0_opp>;
153 capacity-dmips-mhz = < 168 capacity-dmips-mhz = <1024>;
154 #cooling-cells = <2>; 169 #cooling-cells = <2>;
155 }; 170 };
156 171
157 a57_1: cpu@1 { 172 a57_1: cpu@1 {
158 compatible = "arm,cort 173 compatible = "arm,cortex-a57";
159 reg = <0x1>; 174 reg = <0x1>;
160 device_type = "cpu"; 175 device_type = "cpu";
161 power-domains = <&sysc 176 power-domains = <&sysc R8A7796_PD_CA57_CPU1>;
162 next-level-cache = <&L 177 next-level-cache = <&L2_CA57>;
163 enable-method = "psci" 178 enable-method = "psci";
164 cpu-idle-states = <&CP 179 cpu-idle-states = <&CPU_SLEEP_0>;
165 clocks = <&cpg CPG_COR 180 clocks = <&cpg CPG_CORE R8A7796_CLK_Z>;
166 operating-points-v2 = 181 operating-points-v2 = <&cluster0_opp>;
167 capacity-dmips-mhz = < 182 capacity-dmips-mhz = <1024>;
168 #cooling-cells = <2>; 183 #cooling-cells = <2>;
169 }; 184 };
170 185
171 a53_0: cpu@100 { 186 a53_0: cpu@100 {
172 compatible = "arm,cort 187 compatible = "arm,cortex-a53";
173 reg = <0x100>; 188 reg = <0x100>;
174 device_type = "cpu"; 189 device_type = "cpu";
175 power-domains = <&sysc 190 power-domains = <&sysc R8A7796_PD_CA53_CPU0>;
176 next-level-cache = <&L 191 next-level-cache = <&L2_CA53>;
177 enable-method = "psci" 192 enable-method = "psci";
178 cpu-idle-states = <&CP 193 cpu-idle-states = <&CPU_SLEEP_1>;
179 #cooling-cells = <2>; 194 #cooling-cells = <2>;
180 dynamic-power-coeffici 195 dynamic-power-coefficient = <277>;
181 clocks = <&cpg CPG_COR 196 clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
182 operating-points-v2 = 197 operating-points-v2 = <&cluster1_opp>;
183 capacity-dmips-mhz = < 198 capacity-dmips-mhz = <535>;
184 }; 199 };
185 200
186 a53_1: cpu@101 { 201 a53_1: cpu@101 {
187 compatible = "arm,cort 202 compatible = "arm,cortex-a53";
188 reg = <0x101>; 203 reg = <0x101>;
189 device_type = "cpu"; 204 device_type = "cpu";
190 power-domains = <&sysc 205 power-domains = <&sysc R8A7796_PD_CA53_CPU1>;
191 next-level-cache = <&L 206 next-level-cache = <&L2_CA53>;
192 enable-method = "psci" 207 enable-method = "psci";
193 cpu-idle-states = <&CP 208 cpu-idle-states = <&CPU_SLEEP_1>;
194 clocks = <&cpg CPG_COR 209 clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
195 operating-points-v2 = 210 operating-points-v2 = <&cluster1_opp>;
196 capacity-dmips-mhz = < 211 capacity-dmips-mhz = <535>;
197 }; 212 };
198 213
199 a53_2: cpu@102 { 214 a53_2: cpu@102 {
200 compatible = "arm,cort 215 compatible = "arm,cortex-a53";
201 reg = <0x102>; 216 reg = <0x102>;
202 device_type = "cpu"; 217 device_type = "cpu";
203 power-domains = <&sysc 218 power-domains = <&sysc R8A7796_PD_CA53_CPU2>;
204 next-level-cache = <&L 219 next-level-cache = <&L2_CA53>;
205 enable-method = "psci" 220 enable-method = "psci";
206 cpu-idle-states = <&CP 221 cpu-idle-states = <&CPU_SLEEP_1>;
207 clocks = <&cpg CPG_COR 222 clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
208 operating-points-v2 = 223 operating-points-v2 = <&cluster1_opp>;
209 capacity-dmips-mhz = < 224 capacity-dmips-mhz = <535>;
210 }; 225 };
211 226
212 a53_3: cpu@103 { 227 a53_3: cpu@103 {
213 compatible = "arm,cort 228 compatible = "arm,cortex-a53";
214 reg = <0x103>; 229 reg = <0x103>;
215 device_type = "cpu"; 230 device_type = "cpu";
216 power-domains = <&sysc 231 power-domains = <&sysc R8A7796_PD_CA53_CPU3>;
217 next-level-cache = <&L 232 next-level-cache = <&L2_CA53>;
218 enable-method = "psci" 233 enable-method = "psci";
219 cpu-idle-states = <&CP 234 cpu-idle-states = <&CPU_SLEEP_1>;
220 clocks = <&cpg CPG_COR 235 clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
221 operating-points-v2 = 236 operating-points-v2 = <&cluster1_opp>;
222 capacity-dmips-mhz = < 237 capacity-dmips-mhz = <535>;
223 }; 238 };
224 239
225 L2_CA57: cache-controller-0 { 240 L2_CA57: cache-controller-0 {
226 compatible = "cache"; 241 compatible = "cache";
227 power-domains = <&sysc 242 power-domains = <&sysc R8A7796_PD_CA57_SCU>;
228 cache-unified; 243 cache-unified;
229 cache-level = <2>; 244 cache-level = <2>;
230 }; 245 };
231 246
232 L2_CA53: cache-controller-1 { 247 L2_CA53: cache-controller-1 {
233 compatible = "cache"; 248 compatible = "cache";
234 power-domains = <&sysc 249 power-domains = <&sysc R8A7796_PD_CA53_SCU>;
235 cache-unified; 250 cache-unified;
236 cache-level = <2>; 251 cache-level = <2>;
237 }; 252 };
238 253
239 idle-states { 254 idle-states {
240 entry-method = "psci"; 255 entry-method = "psci";
241 256
242 CPU_SLEEP_0: cpu-sleep 257 CPU_SLEEP_0: cpu-sleep-0 {
243 compatible = " 258 compatible = "arm,idle-state";
244 arm,psci-suspe 259 arm,psci-suspend-param = <0x0010000>;
245 local-timer-st 260 local-timer-stop;
246 entry-latency- 261 entry-latency-us = <400>;
247 exit-latency-u 262 exit-latency-us = <500>;
248 min-residency- 263 min-residency-us = <4000>;
249 }; 264 };
250 265
251 CPU_SLEEP_1: cpu-sleep 266 CPU_SLEEP_1: cpu-sleep-1 {
252 compatible = " 267 compatible = "arm,idle-state";
253 arm,psci-suspe 268 arm,psci-suspend-param = <0x0010000>;
254 local-timer-st 269 local-timer-stop;
255 entry-latency- 270 entry-latency-us = <700>;
256 exit-latency-u 271 exit-latency-us = <700>;
257 min-residency- 272 min-residency-us = <5000>;
258 }; 273 };
259 }; 274 };
260 }; 275 };
261 276
262 extal_clk: extal { 277 extal_clk: extal {
263 compatible = "fixed-clock"; 278 compatible = "fixed-clock";
264 #clock-cells = <0>; 279 #clock-cells = <0>;
265 /* This value must be overridd 280 /* This value must be overridden by the board */
266 clock-frequency = <0>; 281 clock-frequency = <0>;
267 }; 282 };
268 283
269 extalr_clk: extalr { 284 extalr_clk: extalr {
270 compatible = "fixed-clock"; 285 compatible = "fixed-clock";
271 #clock-cells = <0>; 286 #clock-cells = <0>;
272 /* This value must be overridd 287 /* This value must be overridden by the board */
273 clock-frequency = <0>; 288 clock-frequency = <0>;
274 }; 289 };
275 290
276 /* External PCIe clock - can be overri 291 /* External PCIe clock - can be overridden by the board */
277 pcie_bus_clk: pcie_bus { 292 pcie_bus_clk: pcie_bus {
278 compatible = "fixed-clock"; 293 compatible = "fixed-clock";
279 #clock-cells = <0>; 294 #clock-cells = <0>;
280 clock-frequency = <0>; 295 clock-frequency = <0>;
281 }; 296 };
282 297
283 pmu_a53 { 298 pmu_a53 {
284 compatible = "arm,cortex-a53-p 299 compatible = "arm,cortex-a53-pmu";
285 interrupts-extended = <&gic GI 300 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
286 <&gic GI 301 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
287 <&gic GI 302 <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
288 <&gic GI 303 <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
289 interrupt-affinity = <&a53_0>, 304 interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>;
290 }; 305 };
291 306
292 pmu_a57 { 307 pmu_a57 {
293 compatible = "arm,cortex-a57-p 308 compatible = "arm,cortex-a57-pmu";
294 interrupts-extended = <&gic GI 309 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
295 <&gic GI 310 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
296 interrupt-affinity = <&a57_0>, 311 interrupt-affinity = <&a57_0>, <&a57_1>;
297 }; 312 };
298 313
299 psci { 314 psci {
300 compatible = "arm,psci-1.0", " 315 compatible = "arm,psci-1.0", "arm,psci-0.2";
301 method = "smc"; 316 method = "smc";
302 }; 317 };
303 318
304 /* External SCIF clock - to be overrid 319 /* External SCIF clock - to be overridden by boards that provide it */
305 scif_clk: scif { 320 scif_clk: scif {
306 compatible = "fixed-clock"; 321 compatible = "fixed-clock";
307 #clock-cells = <0>; 322 #clock-cells = <0>;
308 clock-frequency = <0>; 323 clock-frequency = <0>;
309 }; 324 };
310 325
311 soc { 326 soc {
312 compatible = "simple-bus"; 327 compatible = "simple-bus";
313 interrupt-parent = <&gic>; 328 interrupt-parent = <&gic>;
314 #address-cells = <2>; 329 #address-cells = <2>;
315 #size-cells = <2>; 330 #size-cells = <2>;
316 ranges; 331 ranges;
317 332
318 rwdt: watchdog@e6020000 { 333 rwdt: watchdog@e6020000 {
319 compatible = "renesas, 334 compatible = "renesas,r8a7796-wdt",
320 "renesas, 335 "renesas,rcar-gen3-wdt";
321 reg = <0 0xe6020000 0 336 reg = <0 0xe6020000 0 0x0c>;
322 interrupts = <GIC_SPI <<
323 clocks = <&cpg CPG_MOD 337 clocks = <&cpg CPG_MOD 402>;
324 power-domains = <&sysc 338 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
325 resets = <&cpg 402>; 339 resets = <&cpg 402>;
326 status = "disabled"; 340 status = "disabled";
327 }; 341 };
328 342
329 gpio0: gpio@e6050000 { 343 gpio0: gpio@e6050000 {
330 compatible = "renesas, 344 compatible = "renesas,gpio-r8a7796",
331 "renesas, 345 "renesas,rcar-gen3-gpio";
332 reg = <0 0xe6050000 0 346 reg = <0 0xe6050000 0 0x50>;
333 interrupts = <GIC_SPI 347 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
334 #gpio-cells = <2>; 348 #gpio-cells = <2>;
335 gpio-controller; 349 gpio-controller;
336 gpio-ranges = <&pfc 0 350 gpio-ranges = <&pfc 0 0 16>;
337 #interrupt-cells = <2> 351 #interrupt-cells = <2>;
338 interrupt-controller; 352 interrupt-controller;
339 clocks = <&cpg CPG_MOD 353 clocks = <&cpg CPG_MOD 912>;
340 power-domains = <&sysc 354 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
341 resets = <&cpg 912>; 355 resets = <&cpg 912>;
342 }; 356 };
343 357
344 gpio1: gpio@e6051000 { 358 gpio1: gpio@e6051000 {
345 compatible = "renesas, 359 compatible = "renesas,gpio-r8a7796",
346 "renesas, 360 "renesas,rcar-gen3-gpio";
347 reg = <0 0xe6051000 0 361 reg = <0 0xe6051000 0 0x50>;
348 interrupts = <GIC_SPI 362 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
349 #gpio-cells = <2>; 363 #gpio-cells = <2>;
350 gpio-controller; 364 gpio-controller;
351 gpio-ranges = <&pfc 0 365 gpio-ranges = <&pfc 0 32 29>;
352 #interrupt-cells = <2> 366 #interrupt-cells = <2>;
353 interrupt-controller; 367 interrupt-controller;
354 clocks = <&cpg CPG_MOD 368 clocks = <&cpg CPG_MOD 911>;
355 power-domains = <&sysc 369 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
356 resets = <&cpg 911>; 370 resets = <&cpg 911>;
357 }; 371 };
358 372
359 gpio2: gpio@e6052000 { 373 gpio2: gpio@e6052000 {
360 compatible = "renesas, 374 compatible = "renesas,gpio-r8a7796",
361 "renesas, 375 "renesas,rcar-gen3-gpio";
362 reg = <0 0xe6052000 0 376 reg = <0 0xe6052000 0 0x50>;
363 interrupts = <GIC_SPI 377 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
364 #gpio-cells = <2>; 378 #gpio-cells = <2>;
365 gpio-controller; 379 gpio-controller;
366 gpio-ranges = <&pfc 0 380 gpio-ranges = <&pfc 0 64 15>;
367 #interrupt-cells = <2> 381 #interrupt-cells = <2>;
368 interrupt-controller; 382 interrupt-controller;
369 clocks = <&cpg CPG_MOD 383 clocks = <&cpg CPG_MOD 910>;
370 power-domains = <&sysc 384 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
371 resets = <&cpg 910>; 385 resets = <&cpg 910>;
372 }; 386 };
373 387
374 gpio3: gpio@e6053000 { 388 gpio3: gpio@e6053000 {
375 compatible = "renesas, 389 compatible = "renesas,gpio-r8a7796",
376 "renesas, 390 "renesas,rcar-gen3-gpio";
377 reg = <0 0xe6053000 0 391 reg = <0 0xe6053000 0 0x50>;
378 interrupts = <GIC_SPI 392 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
379 #gpio-cells = <2>; 393 #gpio-cells = <2>;
380 gpio-controller; 394 gpio-controller;
381 gpio-ranges = <&pfc 0 395 gpio-ranges = <&pfc 0 96 16>;
382 #interrupt-cells = <2> 396 #interrupt-cells = <2>;
383 interrupt-controller; 397 interrupt-controller;
384 clocks = <&cpg CPG_MOD 398 clocks = <&cpg CPG_MOD 909>;
385 power-domains = <&sysc 399 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
386 resets = <&cpg 909>; 400 resets = <&cpg 909>;
387 }; 401 };
388 402
389 gpio4: gpio@e6054000 { 403 gpio4: gpio@e6054000 {
390 compatible = "renesas, 404 compatible = "renesas,gpio-r8a7796",
391 "renesas, 405 "renesas,rcar-gen3-gpio";
392 reg = <0 0xe6054000 0 406 reg = <0 0xe6054000 0 0x50>;
393 interrupts = <GIC_SPI 407 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
394 #gpio-cells = <2>; 408 #gpio-cells = <2>;
395 gpio-controller; 409 gpio-controller;
396 gpio-ranges = <&pfc 0 410 gpio-ranges = <&pfc 0 128 18>;
397 #interrupt-cells = <2> 411 #interrupt-cells = <2>;
398 interrupt-controller; 412 interrupt-controller;
399 clocks = <&cpg CPG_MOD 413 clocks = <&cpg CPG_MOD 908>;
400 power-domains = <&sysc 414 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
401 resets = <&cpg 908>; 415 resets = <&cpg 908>;
402 }; 416 };
403 417
404 gpio5: gpio@e6055000 { 418 gpio5: gpio@e6055000 {
405 compatible = "renesas, 419 compatible = "renesas,gpio-r8a7796",
406 "renesas, 420 "renesas,rcar-gen3-gpio";
407 reg = <0 0xe6055000 0 421 reg = <0 0xe6055000 0 0x50>;
408 interrupts = <GIC_SPI 422 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
409 #gpio-cells = <2>; 423 #gpio-cells = <2>;
410 gpio-controller; 424 gpio-controller;
411 gpio-ranges = <&pfc 0 425 gpio-ranges = <&pfc 0 160 26>;
412 #interrupt-cells = <2> 426 #interrupt-cells = <2>;
413 interrupt-controller; 427 interrupt-controller;
414 clocks = <&cpg CPG_MOD 428 clocks = <&cpg CPG_MOD 907>;
415 power-domains = <&sysc 429 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
416 resets = <&cpg 907>; 430 resets = <&cpg 907>;
417 }; 431 };
418 432
419 gpio6: gpio@e6055400 { 433 gpio6: gpio@e6055400 {
420 compatible = "renesas, 434 compatible = "renesas,gpio-r8a7796",
421 "renesas, 435 "renesas,rcar-gen3-gpio";
422 reg = <0 0xe6055400 0 436 reg = <0 0xe6055400 0 0x50>;
423 interrupts = <GIC_SPI 437 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
424 #gpio-cells = <2>; 438 #gpio-cells = <2>;
425 gpio-controller; 439 gpio-controller;
426 gpio-ranges = <&pfc 0 440 gpio-ranges = <&pfc 0 192 32>;
427 #interrupt-cells = <2> 441 #interrupt-cells = <2>;
428 interrupt-controller; 442 interrupt-controller;
429 clocks = <&cpg CPG_MOD 443 clocks = <&cpg CPG_MOD 906>;
430 power-domains = <&sysc 444 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
431 resets = <&cpg 906>; 445 resets = <&cpg 906>;
432 }; 446 };
433 447
434 gpio7: gpio@e6055800 { 448 gpio7: gpio@e6055800 {
435 compatible = "renesas, 449 compatible = "renesas,gpio-r8a7796",
436 "renesas, 450 "renesas,rcar-gen3-gpio";
437 reg = <0 0xe6055800 0 451 reg = <0 0xe6055800 0 0x50>;
438 interrupts = <GIC_SPI 452 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
439 #gpio-cells = <2>; 453 #gpio-cells = <2>;
440 gpio-controller; 454 gpio-controller;
441 gpio-ranges = <&pfc 0 455 gpio-ranges = <&pfc 0 224 4>;
442 #interrupt-cells = <2> 456 #interrupt-cells = <2>;
443 interrupt-controller; 457 interrupt-controller;
444 clocks = <&cpg CPG_MOD 458 clocks = <&cpg CPG_MOD 905>;
445 power-domains = <&sysc 459 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
446 resets = <&cpg 905>; 460 resets = <&cpg 905>;
447 }; 461 };
448 462
449 pfc: pinctrl@e6060000 { 463 pfc: pinctrl@e6060000 {
450 compatible = "renesas, 464 compatible = "renesas,pfc-r8a7796";
451 reg = <0 0xe6060000 0 465 reg = <0 0xe6060000 0 0x50c>;
452 }; 466 };
453 467
454 cmt0: timer@e60f0000 { 468 cmt0: timer@e60f0000 {
455 compatible = "renesas, 469 compatible = "renesas,r8a7796-cmt0",
456 "renesas, 470 "renesas,rcar-gen3-cmt0";
457 reg = <0 0xe60f0000 0 471 reg = <0 0xe60f0000 0 0x1004>;
458 interrupts = <GIC_SPI 472 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
459 <GIC_SPI 473 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
460 clocks = <&cpg CPG_MOD 474 clocks = <&cpg CPG_MOD 303>;
461 clock-names = "fck"; 475 clock-names = "fck";
462 power-domains = <&sysc 476 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
463 resets = <&cpg 303>; 477 resets = <&cpg 303>;
464 status = "disabled"; 478 status = "disabled";
465 }; 479 };
466 480
467 cmt1: timer@e6130000 { 481 cmt1: timer@e6130000 {
468 compatible = "renesas, 482 compatible = "renesas,r8a7796-cmt1",
469 "renesas, 483 "renesas,rcar-gen3-cmt1";
470 reg = <0 0xe6130000 0 484 reg = <0 0xe6130000 0 0x1004>;
471 interrupts = <GIC_SPI 485 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
472 <GIC_SPI 486 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
473 <GIC_SPI 487 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
474 <GIC_SPI 488 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
475 <GIC_SPI 489 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
476 <GIC_SPI 490 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
477 <GIC_SPI 491 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
478 <GIC_SPI 492 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
479 clocks = <&cpg CPG_MOD 493 clocks = <&cpg CPG_MOD 302>;
480 clock-names = "fck"; 494 clock-names = "fck";
481 power-domains = <&sysc 495 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
482 resets = <&cpg 302>; 496 resets = <&cpg 302>;
483 status = "disabled"; 497 status = "disabled";
484 }; 498 };
485 499
486 cmt2: timer@e6140000 { 500 cmt2: timer@e6140000 {
487 compatible = "renesas, 501 compatible = "renesas,r8a7796-cmt1",
488 "renesas, 502 "renesas,rcar-gen3-cmt1";
489 reg = <0 0xe6140000 0 503 reg = <0 0xe6140000 0 0x1004>;
490 interrupts = <GIC_SPI 504 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
491 <GIC_SPI 505 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
492 <GIC_SPI 506 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
493 <GIC_SPI 507 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
494 <GIC_SPI 508 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
495 <GIC_SPI 509 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
496 <GIC_SPI 510 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
497 <GIC_SPI 511 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
498 clocks = <&cpg CPG_MOD 512 clocks = <&cpg CPG_MOD 301>;
499 clock-names = "fck"; 513 clock-names = "fck";
500 power-domains = <&sysc 514 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
501 resets = <&cpg 301>; 515 resets = <&cpg 301>;
502 status = "disabled"; 516 status = "disabled";
503 }; 517 };
504 518
505 cmt3: timer@e6148000 { 519 cmt3: timer@e6148000 {
506 compatible = "renesas, 520 compatible = "renesas,r8a7796-cmt1",
507 "renesas, 521 "renesas,rcar-gen3-cmt1";
508 reg = <0 0xe6148000 0 522 reg = <0 0xe6148000 0 0x1004>;
509 interrupts = <GIC_SPI 523 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
510 <GIC_SPI 524 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
511 <GIC_SPI 525 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
512 <GIC_SPI 526 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
513 <GIC_SPI 527 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
514 <GIC_SPI 528 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
515 <GIC_SPI 529 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
516 <GIC_SPI 530 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
517 clocks = <&cpg CPG_MOD 531 clocks = <&cpg CPG_MOD 300>;
518 clock-names = "fck"; 532 clock-names = "fck";
519 power-domains = <&sysc 533 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
520 resets = <&cpg 300>; 534 resets = <&cpg 300>;
521 status = "disabled"; 535 status = "disabled";
522 }; 536 };
523 537
524 cpg: clock-controller@e6150000 538 cpg: clock-controller@e6150000 {
525 compatible = "renesas, 539 compatible = "renesas,r8a7796-cpg-mssr";
526 reg = <0 0xe6150000 0 540 reg = <0 0xe6150000 0 0x1000>;
527 clocks = <&extal_clk>, 541 clocks = <&extal_clk>, <&extalr_clk>;
528 clock-names = "extal", 542 clock-names = "extal", "extalr";
529 #clock-cells = <2>; 543 #clock-cells = <2>;
530 #power-domain-cells = 544 #power-domain-cells = <0>;
531 #reset-cells = <1>; 545 #reset-cells = <1>;
532 }; 546 };
533 547
534 rst: reset-controller@e6160000 548 rst: reset-controller@e6160000 {
535 compatible = "renesas, 549 compatible = "renesas,r8a7796-rst";
536 reg = <0 0xe6160000 0 550 reg = <0 0xe6160000 0 0x0200>;
537 }; 551 };
538 552
539 sysc: system-controller@e61800 553 sysc: system-controller@e6180000 {
540 compatible = "renesas, 554 compatible = "renesas,r8a7796-sysc";
541 reg = <0 0xe6180000 0 555 reg = <0 0xe6180000 0 0x0400>;
542 #power-domain-cells = 556 #power-domain-cells = <1>;
543 }; 557 };
544 558
545 tsc: thermal@e6198000 { 559 tsc: thermal@e6198000 {
546 compatible = "renesas, 560 compatible = "renesas,r8a7796-thermal";
547 reg = <0 0xe6198000 0 561 reg = <0 0xe6198000 0 0x100>,
548 <0 0xe61a0000 0 562 <0 0xe61a0000 0 0x100>,
549 <0 0xe61a8000 0 563 <0 0xe61a8000 0 0x100>;
550 interrupts = <GIC_SPI 564 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
551 <GIC_SPI 565 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
552 <GIC_SPI 566 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
553 clocks = <&cpg CPG_MOD 567 clocks = <&cpg CPG_MOD 522>;
554 power-domains = <&sysc 568 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
555 resets = <&cpg 522>; 569 resets = <&cpg 522>;
556 #thermal-sensor-cells 570 #thermal-sensor-cells = <1>;
557 }; 571 };
558 572
559 intc_ex: interrupt-controller@ 573 intc_ex: interrupt-controller@e61c0000 {
560 compatible = "renesas, 574 compatible = "renesas,intc-ex-r8a7796", "renesas,irqc";
561 #interrupt-cells = <2> 575 #interrupt-cells = <2>;
562 interrupt-controller; 576 interrupt-controller;
563 reg = <0 0xe61c0000 0 577 reg = <0 0xe61c0000 0 0x200>;
564 interrupts = <GIC_SPI 578 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
565 <GIC_SPI 579 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
566 <GIC_SPI 580 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
567 <GIC_SPI 581 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
568 <GIC_SPI 582 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
569 <GIC_SPI 583 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
570 clocks = <&cpg CPG_MOD 584 clocks = <&cpg CPG_MOD 407>;
571 power-domains = <&sysc 585 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
572 resets = <&cpg 407>; 586 resets = <&cpg 407>;
573 }; 587 };
574 588
575 tmu0: timer@e61e0000 { 589 tmu0: timer@e61e0000 {
576 compatible = "renesas, 590 compatible = "renesas,tmu-r8a7796", "renesas,tmu";
577 reg = <0 0xe61e0000 0 591 reg = <0 0xe61e0000 0 0x30>;
578 interrupts = <GIC_SPI 592 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
579 <GIC_SPI 593 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
580 <GIC_SPI 594 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
581 interrupt-names = "tun <<
582 clocks = <&cpg CPG_MOD 595 clocks = <&cpg CPG_MOD 125>;
583 clock-names = "fck"; 596 clock-names = "fck";
584 power-domains = <&sysc 597 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
585 resets = <&cpg 125>; 598 resets = <&cpg 125>;
586 status = "disabled"; 599 status = "disabled";
587 }; 600 };
588 601
589 tmu1: timer@e6fc0000 { 602 tmu1: timer@e6fc0000 {
590 compatible = "renesas, 603 compatible = "renesas,tmu-r8a7796", "renesas,tmu";
591 reg = <0 0xe6fc0000 0 604 reg = <0 0xe6fc0000 0 0x30>;
592 interrupts = <GIC_SPI 605 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
593 <GIC_SPI 606 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
594 <GIC_SPI !! 607 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
595 <GIC_SPI <<
596 interrupt-names = "tun <<
597 clocks = <&cpg CPG_MOD 608 clocks = <&cpg CPG_MOD 124>;
598 clock-names = "fck"; 609 clock-names = "fck";
599 power-domains = <&sysc 610 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
600 resets = <&cpg 124>; 611 resets = <&cpg 124>;
601 status = "disabled"; 612 status = "disabled";
602 }; 613 };
603 614
604 tmu2: timer@e6fd0000 { 615 tmu2: timer@e6fd0000 {
605 compatible = "renesas, 616 compatible = "renesas,tmu-r8a7796", "renesas,tmu";
606 reg = <0 0xe6fd0000 0 617 reg = <0 0xe6fd0000 0 0x30>;
607 interrupts = <GIC_SPI 618 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
608 <GIC_SPI 619 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
609 <GIC_SPI !! 620 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
610 <GIC_SPI <<
611 interrupt-names = "tun <<
612 clocks = <&cpg CPG_MOD 621 clocks = <&cpg CPG_MOD 123>;
613 clock-names = "fck"; 622 clock-names = "fck";
614 power-domains = <&sysc 623 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
615 resets = <&cpg 123>; 624 resets = <&cpg 123>;
616 status = "disabled"; 625 status = "disabled";
617 }; 626 };
618 627
619 tmu3: timer@e6fe0000 { 628 tmu3: timer@e6fe0000 {
620 compatible = "renesas, 629 compatible = "renesas,tmu-r8a7796", "renesas,tmu";
621 reg = <0 0xe6fe0000 0 630 reg = <0 0xe6fe0000 0 0x30>;
622 interrupts = <GIC_SPI 631 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
623 <GIC_SPI 632 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
624 <GIC_SPI 633 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
625 interrupt-names = "tun <<
626 clocks = <&cpg CPG_MOD 634 clocks = <&cpg CPG_MOD 122>;
627 clock-names = "fck"; 635 clock-names = "fck";
628 power-domains = <&sysc 636 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
629 resets = <&cpg 122>; 637 resets = <&cpg 122>;
630 status = "disabled"; 638 status = "disabled";
631 }; 639 };
632 640
633 tmu4: timer@ffc00000 { 641 tmu4: timer@ffc00000 {
634 compatible = "renesas, 642 compatible = "renesas,tmu-r8a7796", "renesas,tmu";
635 reg = <0 0xffc00000 0 643 reg = <0 0xffc00000 0 0x30>;
636 interrupts = <GIC_SPI 644 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
637 <GIC_SPI 645 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
638 <GIC_SPI 646 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
639 interrupt-names = "tun <<
640 clocks = <&cpg CPG_MOD 647 clocks = <&cpg CPG_MOD 121>;
641 clock-names = "fck"; 648 clock-names = "fck";
642 power-domains = <&sysc 649 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
643 resets = <&cpg 121>; 650 resets = <&cpg 121>;
644 status = "disabled"; 651 status = "disabled";
645 }; 652 };
646 653
647 i2c0: i2c@e6500000 { 654 i2c0: i2c@e6500000 {
648 #address-cells = <1>; 655 #address-cells = <1>;
649 #size-cells = <0>; 656 #size-cells = <0>;
650 compatible = "renesas, 657 compatible = "renesas,i2c-r8a7796",
651 "renesas, 658 "renesas,rcar-gen3-i2c";
652 reg = <0 0xe6500000 0 659 reg = <0 0xe6500000 0 0x40>;
653 interrupts = <GIC_SPI 660 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
654 clocks = <&cpg CPG_MOD 661 clocks = <&cpg CPG_MOD 931>;
655 power-domains = <&sysc 662 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
656 resets = <&cpg 931>; 663 resets = <&cpg 931>;
657 dmas = <&dmac1 0x91>, 664 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
658 <&dmac2 0x91>, 665 <&dmac2 0x91>, <&dmac2 0x90>;
659 dma-names = "tx", "rx" 666 dma-names = "tx", "rx", "tx", "rx";
660 i2c-scl-internal-delay 667 i2c-scl-internal-delay-ns = <110>;
661 status = "disabled"; 668 status = "disabled";
662 }; 669 };
663 670
664 i2c1: i2c@e6508000 { 671 i2c1: i2c@e6508000 {
665 #address-cells = <1>; 672 #address-cells = <1>;
666 #size-cells = <0>; 673 #size-cells = <0>;
667 compatible = "renesas, 674 compatible = "renesas,i2c-r8a7796",
668 "renesas, 675 "renesas,rcar-gen3-i2c";
669 reg = <0 0xe6508000 0 676 reg = <0 0xe6508000 0 0x40>;
670 interrupts = <GIC_SPI 677 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
671 clocks = <&cpg CPG_MOD 678 clocks = <&cpg CPG_MOD 930>;
672 power-domains = <&sysc 679 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
673 resets = <&cpg 930>; 680 resets = <&cpg 930>;
674 dmas = <&dmac1 0x93>, 681 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
675 <&dmac2 0x93>, 682 <&dmac2 0x93>, <&dmac2 0x92>;
676 dma-names = "tx", "rx" 683 dma-names = "tx", "rx", "tx", "rx";
677 i2c-scl-internal-delay 684 i2c-scl-internal-delay-ns = <6>;
678 status = "disabled"; 685 status = "disabled";
679 }; 686 };
680 687
681 i2c2: i2c@e6510000 { 688 i2c2: i2c@e6510000 {
682 #address-cells = <1>; 689 #address-cells = <1>;
683 #size-cells = <0>; 690 #size-cells = <0>;
684 compatible = "renesas, 691 compatible = "renesas,i2c-r8a7796",
685 "renesas, 692 "renesas,rcar-gen3-i2c";
686 reg = <0 0xe6510000 0 693 reg = <0 0xe6510000 0 0x40>;
687 interrupts = <GIC_SPI 694 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
688 clocks = <&cpg CPG_MOD 695 clocks = <&cpg CPG_MOD 929>;
689 power-domains = <&sysc 696 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
690 resets = <&cpg 929>; 697 resets = <&cpg 929>;
691 dmas = <&dmac1 0x95>, 698 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
692 <&dmac2 0x95>, 699 <&dmac2 0x95>, <&dmac2 0x94>;
693 dma-names = "tx", "rx" 700 dma-names = "tx", "rx", "tx", "rx";
694 i2c-scl-internal-delay 701 i2c-scl-internal-delay-ns = <6>;
695 status = "disabled"; 702 status = "disabled";
696 }; 703 };
697 704
698 i2c3: i2c@e66d0000 { 705 i2c3: i2c@e66d0000 {
699 #address-cells = <1>; 706 #address-cells = <1>;
700 #size-cells = <0>; 707 #size-cells = <0>;
701 compatible = "renesas, 708 compatible = "renesas,i2c-r8a7796",
702 "renesas, 709 "renesas,rcar-gen3-i2c";
703 reg = <0 0xe66d0000 0 710 reg = <0 0xe66d0000 0 0x40>;
704 interrupts = <GIC_SPI 711 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
705 clocks = <&cpg CPG_MOD 712 clocks = <&cpg CPG_MOD 928>;
706 power-domains = <&sysc 713 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
707 resets = <&cpg 928>; 714 resets = <&cpg 928>;
708 dmas = <&dmac0 0x97>, 715 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
709 dma-names = "tx", "rx" 716 dma-names = "tx", "rx";
710 i2c-scl-internal-delay 717 i2c-scl-internal-delay-ns = <110>;
711 status = "disabled"; 718 status = "disabled";
712 }; 719 };
713 720
714 i2c4: i2c@e66d8000 { 721 i2c4: i2c@e66d8000 {
715 #address-cells = <1>; 722 #address-cells = <1>;
716 #size-cells = <0>; 723 #size-cells = <0>;
717 compatible = "renesas, 724 compatible = "renesas,i2c-r8a7796",
718 "renesas, 725 "renesas,rcar-gen3-i2c";
719 reg = <0 0xe66d8000 0 726 reg = <0 0xe66d8000 0 0x40>;
720 interrupts = <GIC_SPI 727 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
721 clocks = <&cpg CPG_MOD 728 clocks = <&cpg CPG_MOD 927>;
722 power-domains = <&sysc 729 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
723 resets = <&cpg 927>; 730 resets = <&cpg 927>;
724 dmas = <&dmac0 0x99>, 731 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
725 dma-names = "tx", "rx" 732 dma-names = "tx", "rx";
726 i2c-scl-internal-delay 733 i2c-scl-internal-delay-ns = <110>;
727 status = "disabled"; 734 status = "disabled";
728 }; 735 };
729 736
730 i2c5: i2c@e66e0000 { 737 i2c5: i2c@e66e0000 {
731 #address-cells = <1>; 738 #address-cells = <1>;
732 #size-cells = <0>; 739 #size-cells = <0>;
733 compatible = "renesas, 740 compatible = "renesas,i2c-r8a7796",
734 "renesas, 741 "renesas,rcar-gen3-i2c";
735 reg = <0 0xe66e0000 0 742 reg = <0 0xe66e0000 0 0x40>;
736 interrupts = <GIC_SPI 743 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
737 clocks = <&cpg CPG_MOD 744 clocks = <&cpg CPG_MOD 919>;
738 power-domains = <&sysc 745 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
739 resets = <&cpg 919>; 746 resets = <&cpg 919>;
740 dmas = <&dmac0 0x9b>, 747 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
741 dma-names = "tx", "rx" 748 dma-names = "tx", "rx";
742 i2c-scl-internal-delay 749 i2c-scl-internal-delay-ns = <110>;
743 status = "disabled"; 750 status = "disabled";
744 }; 751 };
745 752
746 i2c6: i2c@e66e8000 { 753 i2c6: i2c@e66e8000 {
747 #address-cells = <1>; 754 #address-cells = <1>;
748 #size-cells = <0>; 755 #size-cells = <0>;
749 compatible = "renesas, 756 compatible = "renesas,i2c-r8a7796",
750 "renesas, 757 "renesas,rcar-gen3-i2c";
751 reg = <0 0xe66e8000 0 758 reg = <0 0xe66e8000 0 0x40>;
752 interrupts = <GIC_SPI 759 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
753 clocks = <&cpg CPG_MOD 760 clocks = <&cpg CPG_MOD 918>;
754 power-domains = <&sysc 761 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
755 resets = <&cpg 918>; 762 resets = <&cpg 918>;
756 dmas = <&dmac0 0x9d>, 763 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
757 dma-names = "tx", "rx" 764 dma-names = "tx", "rx";
758 i2c-scl-internal-delay 765 i2c-scl-internal-delay-ns = <6>;
759 status = "disabled"; 766 status = "disabled";
760 }; 767 };
761 768
762 i2c_dvfs: i2c@e60b0000 { 769 i2c_dvfs: i2c@e60b0000 {
763 #address-cells = <1>; 770 #address-cells = <1>;
764 #size-cells = <0>; 771 #size-cells = <0>;
765 compatible = "renesas, 772 compatible = "renesas,iic-r8a7796",
766 "renesas, 773 "renesas,rcar-gen3-iic",
767 "renesas, 774 "renesas,rmobile-iic";
768 reg = <0 0xe60b0000 0 775 reg = <0 0xe60b0000 0 0x425>;
769 interrupts = <GIC_SPI 776 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
770 clocks = <&cpg CPG_MOD 777 clocks = <&cpg CPG_MOD 926>;
771 power-domains = <&sysc 778 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
772 resets = <&cpg 926>; 779 resets = <&cpg 926>;
773 dmas = <&dmac0 0x11>, 780 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
774 dma-names = "tx", "rx" 781 dma-names = "tx", "rx";
775 status = "disabled"; 782 status = "disabled";
776 }; 783 };
777 784
778 hscif0: serial@e6540000 { 785 hscif0: serial@e6540000 {
779 compatible = "renesas, 786 compatible = "renesas,hscif-r8a7796",
780 "renesas, 787 "renesas,rcar-gen3-hscif",
781 "renesas, 788 "renesas,hscif";
782 reg = <0 0xe6540000 0 789 reg = <0 0xe6540000 0 0x60>;
783 interrupts = <GIC_SPI 790 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
784 clocks = <&cpg CPG_MOD 791 clocks = <&cpg CPG_MOD 520>,
785 <&cpg CPG_COR 792 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
786 <&scif_clk>; 793 <&scif_clk>;
787 clock-names = "fck", " 794 clock-names = "fck", "brg_int", "scif_clk";
788 dmas = <&dmac1 0x31>, 795 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
789 <&dmac2 0x31>, 796 <&dmac2 0x31>, <&dmac2 0x30>;
790 dma-names = "tx", "rx" 797 dma-names = "tx", "rx", "tx", "rx";
791 power-domains = <&sysc 798 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
792 resets = <&cpg 520>; 799 resets = <&cpg 520>;
793 status = "disabled"; 800 status = "disabled";
794 }; 801 };
795 802
796 hscif1: serial@e6550000 { 803 hscif1: serial@e6550000 {
797 compatible = "renesas, 804 compatible = "renesas,hscif-r8a7796",
798 "renesas, 805 "renesas,rcar-gen3-hscif",
799 "renesas, 806 "renesas,hscif";
800 reg = <0 0xe6550000 0 807 reg = <0 0xe6550000 0 0x60>;
801 interrupts = <GIC_SPI 808 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
802 clocks = <&cpg CPG_MOD 809 clocks = <&cpg CPG_MOD 519>,
803 <&cpg CPG_COR 810 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
804 <&scif_clk>; 811 <&scif_clk>;
805 clock-names = "fck", " 812 clock-names = "fck", "brg_int", "scif_clk";
806 dmas = <&dmac1 0x33>, 813 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
807 <&dmac2 0x33>, 814 <&dmac2 0x33>, <&dmac2 0x32>;
808 dma-names = "tx", "rx" 815 dma-names = "tx", "rx", "tx", "rx";
809 power-domains = <&sysc 816 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
810 resets = <&cpg 519>; 817 resets = <&cpg 519>;
811 status = "disabled"; 818 status = "disabled";
812 }; 819 };
813 820
814 hscif2: serial@e6560000 { 821 hscif2: serial@e6560000 {
815 compatible = "renesas, 822 compatible = "renesas,hscif-r8a7796",
816 "renesas, 823 "renesas,rcar-gen3-hscif",
817 "renesas, 824 "renesas,hscif";
818 reg = <0 0xe6560000 0 825 reg = <0 0xe6560000 0 0x60>;
819 interrupts = <GIC_SPI 826 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
820 clocks = <&cpg CPG_MOD 827 clocks = <&cpg CPG_MOD 518>,
821 <&cpg CPG_COR 828 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
822 <&scif_clk>; 829 <&scif_clk>;
823 clock-names = "fck", " 830 clock-names = "fck", "brg_int", "scif_clk";
824 dmas = <&dmac1 0x35>, 831 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
825 <&dmac2 0x35>, 832 <&dmac2 0x35>, <&dmac2 0x34>;
826 dma-names = "tx", "rx" 833 dma-names = "tx", "rx", "tx", "rx";
827 power-domains = <&sysc 834 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
828 resets = <&cpg 518>; 835 resets = <&cpg 518>;
829 status = "disabled"; 836 status = "disabled";
830 }; 837 };
831 838
832 hscif3: serial@e66a0000 { 839 hscif3: serial@e66a0000 {
833 compatible = "renesas, 840 compatible = "renesas,hscif-r8a7796",
834 "renesas, 841 "renesas,rcar-gen3-hscif",
835 "renesas, 842 "renesas,hscif";
836 reg = <0 0xe66a0000 0 843 reg = <0 0xe66a0000 0 0x60>;
837 interrupts = <GIC_SPI 844 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
838 clocks = <&cpg CPG_MOD 845 clocks = <&cpg CPG_MOD 517>,
839 <&cpg CPG_COR 846 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
840 <&scif_clk>; 847 <&scif_clk>;
841 clock-names = "fck", " 848 clock-names = "fck", "brg_int", "scif_clk";
842 dmas = <&dmac0 0x37>, 849 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
843 dma-names = "tx", "rx" 850 dma-names = "tx", "rx";
844 power-domains = <&sysc 851 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
845 resets = <&cpg 517>; 852 resets = <&cpg 517>;
846 status = "disabled"; 853 status = "disabled";
847 }; 854 };
848 855
849 hscif4: serial@e66b0000 { 856 hscif4: serial@e66b0000 {
850 compatible = "renesas, 857 compatible = "renesas,hscif-r8a7796",
851 "renesas, 858 "renesas,rcar-gen3-hscif",
852 "renesas, 859 "renesas,hscif";
853 reg = <0 0xe66b0000 0 860 reg = <0 0xe66b0000 0 0x60>;
854 interrupts = <GIC_SPI 861 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
855 clocks = <&cpg CPG_MOD 862 clocks = <&cpg CPG_MOD 516>,
856 <&cpg CPG_COR 863 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
857 <&scif_clk>; 864 <&scif_clk>;
858 clock-names = "fck", " 865 clock-names = "fck", "brg_int", "scif_clk";
859 dmas = <&dmac0 0x39>, 866 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
860 dma-names = "tx", "rx" 867 dma-names = "tx", "rx";
861 power-domains = <&sysc 868 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
862 resets = <&cpg 516>; 869 resets = <&cpg 516>;
863 status = "disabled"; 870 status = "disabled";
864 }; 871 };
865 872
866 hsusb: usb@e6590000 { 873 hsusb: usb@e6590000 {
867 compatible = "renesas, 874 compatible = "renesas,usbhs-r8a7796",
868 "renesas, 875 "renesas,rcar-gen3-usbhs";
869 reg = <0 0xe6590000 0 876 reg = <0 0xe6590000 0 0x200>;
870 interrupts = <GIC_SPI 877 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
871 clocks = <&cpg CPG_MOD 878 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
872 dmas = <&usb_dmac0 0>, 879 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
873 <&usb_dmac1 0>, 880 <&usb_dmac1 0>, <&usb_dmac1 1>;
874 dma-names = "ch0", "ch 881 dma-names = "ch0", "ch1", "ch2", "ch3";
875 renesas,buswait = <11> 882 renesas,buswait = <11>;
876 phys = <&usb2_phy0 3>; 883 phys = <&usb2_phy0 3>;
877 phy-names = "usb"; 884 phy-names = "usb";
878 power-domains = <&sysc 885 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
879 resets = <&cpg 704>, < 886 resets = <&cpg 704>, <&cpg 703>;
880 status = "disabled"; 887 status = "disabled";
881 }; 888 };
882 889
883 usb_dmac0: dma-controller@e65a 890 usb_dmac0: dma-controller@e65a0000 {
884 compatible = "renesas, 891 compatible = "renesas,r8a7796-usb-dmac",
885 "renesas, 892 "renesas,usb-dmac";
886 reg = <0 0xe65a0000 0 893 reg = <0 0xe65a0000 0 0x100>;
887 interrupts = <GIC_SPI 894 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
888 <GIC_SPI 895 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
889 interrupt-names = "ch0 896 interrupt-names = "ch0", "ch1";
890 clocks = <&cpg CPG_MOD 897 clocks = <&cpg CPG_MOD 330>;
891 power-domains = <&sysc 898 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
892 resets = <&cpg 330>; 899 resets = <&cpg 330>;
893 #dma-cells = <1>; 900 #dma-cells = <1>;
894 dma-channels = <2>; 901 dma-channels = <2>;
895 }; 902 };
896 903
897 usb_dmac1: dma-controller@e65b 904 usb_dmac1: dma-controller@e65b0000 {
898 compatible = "renesas, 905 compatible = "renesas,r8a7796-usb-dmac",
899 "renesas, 906 "renesas,usb-dmac";
900 reg = <0 0xe65b0000 0 907 reg = <0 0xe65b0000 0 0x100>;
901 interrupts = <GIC_SPI 908 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
902 <GIC_SPI 909 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
903 interrupt-names = "ch0 910 interrupt-names = "ch0", "ch1";
904 clocks = <&cpg CPG_MOD 911 clocks = <&cpg CPG_MOD 331>;
905 power-domains = <&sysc 912 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
906 resets = <&cpg 331>; 913 resets = <&cpg 331>;
907 #dma-cells = <1>; 914 #dma-cells = <1>;
908 dma-channels = <2>; 915 dma-channels = <2>;
909 }; 916 };
910 917
911 usb3_phy0: usb-phy@e65ee000 { 918 usb3_phy0: usb-phy@e65ee000 {
912 compatible = "renesas, 919 compatible = "renesas,r8a7796-usb3-phy",
913 "renesas, 920 "renesas,rcar-gen3-usb3-phy";
914 reg = <0 0xe65ee000 0 921 reg = <0 0xe65ee000 0 0x90>;
915 clocks = <&cpg CPG_MOD 922 clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>,
916 <&usb_extal_c 923 <&usb_extal_clk>;
917 clock-names = "usb3-if 924 clock-names = "usb3-if", "usb3s_clk", "usb_extal";
918 power-domains = <&sysc 925 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
919 resets = <&cpg 328>; 926 resets = <&cpg 328>;
920 #phy-cells = <0>; 927 #phy-cells = <0>;
921 status = "disabled"; 928 status = "disabled";
922 }; 929 };
923 930
924 arm_cc630p: crypto@e6601000 { 931 arm_cc630p: crypto@e6601000 {
925 compatible = "arm,cryp 932 compatible = "arm,cryptocell-630p-ree";
926 interrupts = <GIC_SPI 933 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
927 reg = <0x0 0xe6601000 934 reg = <0x0 0xe6601000 0 0x1000>;
928 clocks = <&cpg CPG_MOD 935 clocks = <&cpg CPG_MOD 229>;
929 resets = <&cpg 229>; 936 resets = <&cpg 229>;
930 power-domains = <&sysc 937 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
931 }; 938 };
932 939
933 dmac0: dma-controller@e6700000 940 dmac0: dma-controller@e6700000 {
934 compatible = "renesas, 941 compatible = "renesas,dmac-r8a7796",
935 "renesas, 942 "renesas,rcar-dmac";
936 reg = <0 0xe6700000 0 943 reg = <0 0xe6700000 0 0x10000>;
937 interrupts = <GIC_SPI 944 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
938 <GIC_SPI 945 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
939 <GIC_SPI 946 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
940 <GIC_SPI 947 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
941 <GIC_SPI 948 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
942 <GIC_SPI 949 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
943 <GIC_SPI 950 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
944 <GIC_SPI 951 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
945 <GIC_SPI 952 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
946 <GIC_SPI 953 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
947 <GIC_SPI 954 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
948 <GIC_SPI 955 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
949 <GIC_SPI 956 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
950 <GIC_SPI 957 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
951 <GIC_SPI 958 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
952 <GIC_SPI 959 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
953 <GIC_SPI 960 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
954 interrupt-names = "err 961 interrupt-names = "error",
955 "ch0", 962 "ch0", "ch1", "ch2", "ch3",
956 "ch4", 963 "ch4", "ch5", "ch6", "ch7",
957 "ch8", 964 "ch8", "ch9", "ch10", "ch11",
958 "ch12" 965 "ch12", "ch13", "ch14", "ch15";
959 clocks = <&cpg CPG_MOD 966 clocks = <&cpg CPG_MOD 219>;
960 clock-names = "fck"; 967 clock-names = "fck";
961 power-domains = <&sysc 968 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
962 resets = <&cpg 219>; 969 resets = <&cpg 219>;
963 #dma-cells = <1>; 970 #dma-cells = <1>;
964 dma-channels = <16>; 971 dma-channels = <16>;
965 iommus = <&ipmmu_ds0 0 972 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
966 <&ipmmu_ds0 2>, 973 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
967 <&ipmmu_ds0 4>, 974 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
968 <&ipmmu_ds0 6>, 975 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
969 <&ipmmu_ds0 8>, 976 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
970 <&ipmmu_ds0 10> 977 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
971 <&ipmmu_ds0 12> 978 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
972 <&ipmmu_ds0 14> 979 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
973 }; 980 };
974 981
975 dmac1: dma-controller@e7300000 982 dmac1: dma-controller@e7300000 {
976 compatible = "renesas, 983 compatible = "renesas,dmac-r8a7796",
977 "renesas, 984 "renesas,rcar-dmac";
978 reg = <0 0xe7300000 0 985 reg = <0 0xe7300000 0 0x10000>;
979 interrupts = <GIC_SPI 986 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
980 <GIC_SPI 987 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
981 <GIC_SPI 988 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
982 <GIC_SPI 989 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
983 <GIC_SPI 990 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
984 <GIC_SPI 991 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
985 <GIC_SPI 992 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
986 <GIC_SPI 993 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
987 <GIC_SPI 994 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
988 <GIC_SPI 995 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
989 <GIC_SPI 996 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
990 <GIC_SPI 997 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
991 <GIC_SPI 998 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
992 <GIC_SPI 999 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
993 <GIC_SPI 1000 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
994 <GIC_SPI 1001 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
995 <GIC_SPI 1002 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
996 interrupt-names = "err 1003 interrupt-names = "error",
997 "ch0", 1004 "ch0", "ch1", "ch2", "ch3",
998 "ch4", 1005 "ch4", "ch5", "ch6", "ch7",
999 "ch8", 1006 "ch8", "ch9", "ch10", "ch11",
1000 "ch12 1007 "ch12", "ch13", "ch14", "ch15";
1001 clocks = <&cpg CPG_MO 1008 clocks = <&cpg CPG_MOD 218>;
1002 clock-names = "fck"; 1009 clock-names = "fck";
1003 power-domains = <&sys 1010 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1004 resets = <&cpg 218>; 1011 resets = <&cpg 218>;
1005 #dma-cells = <1>; 1012 #dma-cells = <1>;
1006 dma-channels = <16>; 1013 dma-channels = <16>;
1007 iommus = <&ipmmu_ds1 1014 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
1008 <&ipmmu_ds1 2> 1015 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
1009 <&ipmmu_ds1 4> 1016 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
1010 <&ipmmu_ds1 6> 1017 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
1011 <&ipmmu_ds1 8> 1018 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
1012 <&ipmmu_ds1 10 1019 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
1013 <&ipmmu_ds1 12 1020 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
1014 <&ipmmu_ds1 14 1021 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
1015 }; 1022 };
1016 1023
1017 dmac2: dma-controller@e731000 1024 dmac2: dma-controller@e7310000 {
1018 compatible = "renesas 1025 compatible = "renesas,dmac-r8a7796",
1019 "renesas 1026 "renesas,rcar-dmac";
1020 reg = <0 0xe7310000 0 1027 reg = <0 0xe7310000 0 0x10000>;
1021 interrupts = <GIC_SPI 1028 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
1022 <GIC_SPI 1029 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
1023 <GIC_SPI 1030 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
1024 <GIC_SPI 1031 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
1025 <GIC_SPI 1032 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
1026 <GIC_SPI 1033 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
1027 <GIC_SPI 1034 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
1028 <GIC_SPI 1035 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
1029 <GIC_SPI 1036 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
1030 <GIC_SPI 1037 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
1031 <GIC_SPI 1038 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
1032 <GIC_SPI 1039 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
1033 <GIC_SPI 1040 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
1034 <GIC_SPI 1041 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
1035 <GIC_SPI 1042 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
1036 <GIC_SPI 1043 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
1037 <GIC_SPI 1044 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
1038 interrupt-names = "er 1045 interrupt-names = "error",
1039 "ch0" 1046 "ch0", "ch1", "ch2", "ch3",
1040 "ch4" 1047 "ch4", "ch5", "ch6", "ch7",
1041 "ch8" 1048 "ch8", "ch9", "ch10", "ch11",
1042 "ch12 1049 "ch12", "ch13", "ch14", "ch15";
1043 clocks = <&cpg CPG_MO 1050 clocks = <&cpg CPG_MOD 217>;
1044 clock-names = "fck"; 1051 clock-names = "fck";
1045 power-domains = <&sys 1052 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1046 resets = <&cpg 217>; 1053 resets = <&cpg 217>;
1047 #dma-cells = <1>; 1054 #dma-cells = <1>;
1048 dma-channels = <16>; 1055 dma-channels = <16>;
1049 iommus = <&ipmmu_ds1 1056 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
1050 <&ipmmu_ds1 18 1057 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
1051 <&ipmmu_ds1 20 1058 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
1052 <&ipmmu_ds1 22 1059 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
1053 <&ipmmu_ds1 24 1060 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
1054 <&ipmmu_ds1 26 1061 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
1055 <&ipmmu_ds1 28 1062 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
1056 <&ipmmu_ds1 30 1063 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
1057 }; 1064 };
1058 1065
1059 ipmmu_ds0: iommu@e6740000 { 1066 ipmmu_ds0: iommu@e6740000 {
1060 compatible = "renesas 1067 compatible = "renesas,ipmmu-r8a7796";
1061 reg = <0 0xe6740000 0 1068 reg = <0 0xe6740000 0 0x1000>;
1062 renesas,ipmmu-main = 1069 renesas,ipmmu-main = <&ipmmu_mm 0>;
1063 power-domains = <&sys 1070 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1064 #iommu-cells = <1>; 1071 #iommu-cells = <1>;
1065 }; 1072 };
1066 1073
1067 ipmmu_ds1: iommu@e7740000 { 1074 ipmmu_ds1: iommu@e7740000 {
1068 compatible = "renesas 1075 compatible = "renesas,ipmmu-r8a7796";
1069 reg = <0 0xe7740000 0 1076 reg = <0 0xe7740000 0 0x1000>;
1070 renesas,ipmmu-main = 1077 renesas,ipmmu-main = <&ipmmu_mm 1>;
1071 power-domains = <&sys 1078 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1072 #iommu-cells = <1>; 1079 #iommu-cells = <1>;
1073 }; 1080 };
1074 1081
1075 ipmmu_hc: iommu@e6570000 { 1082 ipmmu_hc: iommu@e6570000 {
1076 compatible = "renesas 1083 compatible = "renesas,ipmmu-r8a7796";
1077 reg = <0 0xe6570000 0 1084 reg = <0 0xe6570000 0 0x1000>;
1078 renesas,ipmmu-main = 1085 renesas,ipmmu-main = <&ipmmu_mm 2>;
1079 power-domains = <&sys 1086 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1080 #iommu-cells = <1>; 1087 #iommu-cells = <1>;
1081 }; 1088 };
1082 1089
1083 ipmmu_ir: iommu@ff8b0000 { 1090 ipmmu_ir: iommu@ff8b0000 {
1084 compatible = "renesas 1091 compatible = "renesas,ipmmu-r8a7796";
1085 reg = <0 0xff8b0000 0 1092 reg = <0 0xff8b0000 0 0x1000>;
1086 renesas,ipmmu-main = 1093 renesas,ipmmu-main = <&ipmmu_mm 3>;
1087 power-domains = <&sys 1094 power-domains = <&sysc R8A7796_PD_A3IR>;
1088 #iommu-cells = <1>; 1095 #iommu-cells = <1>;
1089 }; 1096 };
1090 1097
1091 ipmmu_mm: iommu@e67b0000 { 1098 ipmmu_mm: iommu@e67b0000 {
1092 compatible = "renesas 1099 compatible = "renesas,ipmmu-r8a7796";
1093 reg = <0 0xe67b0000 0 1100 reg = <0 0xe67b0000 0 0x1000>;
1094 interrupts = <GIC_SPI 1101 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
1095 <GIC_SPI 1102 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
1096 power-domains = <&sys 1103 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1097 #iommu-cells = <1>; 1104 #iommu-cells = <1>;
1098 }; 1105 };
1099 1106
1100 ipmmu_mp: iommu@ec670000 { 1107 ipmmu_mp: iommu@ec670000 {
1101 compatible = "renesas 1108 compatible = "renesas,ipmmu-r8a7796";
1102 reg = <0 0xec670000 0 1109 reg = <0 0xec670000 0 0x1000>;
1103 renesas,ipmmu-main = 1110 renesas,ipmmu-main = <&ipmmu_mm 4>;
1104 power-domains = <&sys 1111 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1105 #iommu-cells = <1>; 1112 #iommu-cells = <1>;
1106 }; 1113 };
1107 1114
1108 ipmmu_pv0: iommu@fd800000 { 1115 ipmmu_pv0: iommu@fd800000 {
1109 compatible = "renesas 1116 compatible = "renesas,ipmmu-r8a7796";
1110 reg = <0 0xfd800000 0 1117 reg = <0 0xfd800000 0 0x1000>;
1111 renesas,ipmmu-main = 1118 renesas,ipmmu-main = <&ipmmu_mm 5>;
1112 power-domains = <&sys 1119 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1113 #iommu-cells = <1>; 1120 #iommu-cells = <1>;
1114 }; 1121 };
1115 1122
1116 ipmmu_pv1: iommu@fd950000 { 1123 ipmmu_pv1: iommu@fd950000 {
1117 compatible = "renesas 1124 compatible = "renesas,ipmmu-r8a7796";
1118 reg = <0 0xfd950000 0 1125 reg = <0 0xfd950000 0 0x1000>;
1119 renesas,ipmmu-main = 1126 renesas,ipmmu-main = <&ipmmu_mm 6>;
1120 power-domains = <&sys 1127 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1121 #iommu-cells = <1>; 1128 #iommu-cells = <1>;
1122 }; 1129 };
1123 1130
1124 ipmmu_rt: iommu@ffc80000 { 1131 ipmmu_rt: iommu@ffc80000 {
1125 compatible = "renesas 1132 compatible = "renesas,ipmmu-r8a7796";
1126 reg = <0 0xffc80000 0 1133 reg = <0 0xffc80000 0 0x1000>;
1127 renesas,ipmmu-main = 1134 renesas,ipmmu-main = <&ipmmu_mm 7>;
1128 power-domains = <&sys 1135 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1129 #iommu-cells = <1>; 1136 #iommu-cells = <1>;
1130 }; 1137 };
1131 1138
1132 ipmmu_vc0: iommu@fe6b0000 { 1139 ipmmu_vc0: iommu@fe6b0000 {
1133 compatible = "renesas 1140 compatible = "renesas,ipmmu-r8a7796";
1134 reg = <0 0xfe6b0000 0 1141 reg = <0 0xfe6b0000 0 0x1000>;
1135 renesas,ipmmu-main = 1142 renesas,ipmmu-main = <&ipmmu_mm 8>;
1136 power-domains = <&sys 1143 power-domains = <&sysc R8A7796_PD_A3VC>;
1137 #iommu-cells = <1>; 1144 #iommu-cells = <1>;
1138 }; 1145 };
1139 1146
1140 ipmmu_vi0: iommu@febd0000 { 1147 ipmmu_vi0: iommu@febd0000 {
1141 compatible = "renesas 1148 compatible = "renesas,ipmmu-r8a7796";
1142 reg = <0 0xfebd0000 0 1149 reg = <0 0xfebd0000 0 0x1000>;
1143 renesas,ipmmu-main = 1150 renesas,ipmmu-main = <&ipmmu_mm 9>;
1144 power-domains = <&sys 1151 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1145 #iommu-cells = <1>; 1152 #iommu-cells = <1>;
1146 }; 1153 };
1147 1154
1148 avb: ethernet@e6800000 { 1155 avb: ethernet@e6800000 {
1149 compatible = "renesas 1156 compatible = "renesas,etheravb-r8a7796",
1150 "renesas 1157 "renesas,etheravb-rcar-gen3";
1151 reg = <0 0xe6800000 0 1158 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
1152 interrupts = <GIC_SPI 1159 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
1153 <GIC_SPI 1160 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1154 <GIC_SPI 1161 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
1155 <GIC_SPI 1162 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
1156 <GIC_SPI 1163 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
1157 <GIC_SPI 1164 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
1158 <GIC_SPI 1165 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
1159 <GIC_SPI 1166 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
1160 <GIC_SPI 1167 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
1161 <GIC_SPI 1168 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
1162 <GIC_SPI 1169 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
1163 <GIC_SPI 1170 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
1164 <GIC_SPI 1171 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
1165 <GIC_SPI 1172 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
1166 <GIC_SPI 1173 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
1167 <GIC_SPI 1174 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
1168 <GIC_SPI 1175 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
1169 <GIC_SPI 1176 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
1170 <GIC_SPI 1177 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
1171 <GIC_SPI 1178 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
1172 <GIC_SPI 1179 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
1173 <GIC_SPI 1180 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
1174 <GIC_SPI 1181 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
1175 <GIC_SPI 1182 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
1176 <GIC_SPI 1183 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
1177 interrupt-names = "ch 1184 interrupt-names = "ch0", "ch1", "ch2", "ch3",
1178 "ch 1185 "ch4", "ch5", "ch6", "ch7",
1179 "ch 1186 "ch8", "ch9", "ch10", "ch11",
1180 "ch 1187 "ch12", "ch13", "ch14", "ch15",
1181 "ch 1188 "ch16", "ch17", "ch18", "ch19",
1182 "ch 1189 "ch20", "ch21", "ch22", "ch23",
1183 "ch 1190 "ch24";
1184 clocks = <&cpg CPG_MO 1191 clocks = <&cpg CPG_MOD 812>;
1185 clock-names = "fck"; <<
1186 power-domains = <&sys 1192 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1187 resets = <&cpg 812>; 1193 resets = <&cpg 812>;
1188 phy-mode = "rgmii"; 1194 phy-mode = "rgmii";
1189 rx-internal-delay-ps 1195 rx-internal-delay-ps = <0>;
1190 tx-internal-delay-ps 1196 tx-internal-delay-ps = <0>;
1191 iommus = <&ipmmu_ds0 1197 iommus = <&ipmmu_ds0 16>;
1192 #address-cells = <1>; 1198 #address-cells = <1>;
1193 #size-cells = <0>; 1199 #size-cells = <0>;
1194 status = "disabled"; 1200 status = "disabled";
1195 }; 1201 };
1196 1202
1197 can0: can@e6c30000 { 1203 can0: can@e6c30000 {
1198 compatible = "renesas 1204 compatible = "renesas,can-r8a7796",
1199 "renesas 1205 "renesas,rcar-gen3-can";
1200 reg = <0 0xe6c30000 0 1206 reg = <0 0xe6c30000 0 0x1000>;
1201 interrupts = <GIC_SPI 1207 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
1202 clocks = <&cpg CPG_MO 1208 clocks = <&cpg CPG_MOD 916>,
1203 <&cpg CPG_CORE 1209 <&cpg CPG_CORE R8A7796_CLK_CANFD>,
1204 <&can_clk>; 1210 <&can_clk>;
1205 clock-names = "clkp1" 1211 clock-names = "clkp1", "clkp2", "can_clk";
1206 assigned-clocks = <&c 1212 assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>;
1207 assigned-clock-rates 1213 assigned-clock-rates = <40000000>;
1208 power-domains = <&sys 1214 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1209 resets = <&cpg 916>; 1215 resets = <&cpg 916>;
1210 status = "disabled"; 1216 status = "disabled";
1211 }; 1217 };
1212 1218
1213 can1: can@e6c38000 { 1219 can1: can@e6c38000 {
1214 compatible = "renesas 1220 compatible = "renesas,can-r8a7796",
1215 "renesas 1221 "renesas,rcar-gen3-can";
1216 reg = <0 0xe6c38000 0 1222 reg = <0 0xe6c38000 0 0x1000>;
1217 interrupts = <GIC_SPI 1223 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
1218 clocks = <&cpg CPG_MO 1224 clocks = <&cpg CPG_MOD 915>,
1219 <&cpg CPG_CORE 1225 <&cpg CPG_CORE R8A7796_CLK_CANFD>,
1220 <&can_clk>; 1226 <&can_clk>;
1221 clock-names = "clkp1" 1227 clock-names = "clkp1", "clkp2", "can_clk";
1222 assigned-clocks = <&c 1228 assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>;
1223 assigned-clock-rates 1229 assigned-clock-rates = <40000000>;
1224 power-domains = <&sys 1230 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1225 resets = <&cpg 915>; 1231 resets = <&cpg 915>;
1226 status = "disabled"; 1232 status = "disabled";
1227 }; 1233 };
1228 1234
1229 canfd: can@e66c0000 { 1235 canfd: can@e66c0000 {
1230 compatible = "renesas 1236 compatible = "renesas,r8a7796-canfd",
1231 "renesas 1237 "renesas,rcar-gen3-canfd";
1232 reg = <0 0xe66c0000 0 1238 reg = <0 0xe66c0000 0 0x8000>;
1233 interrupts = <GIC_SPI 1239 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
1234 <GIC_SPI 3 1240 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1235 interrupt-names = "ch <<
1236 clocks = <&cpg CPG_MO 1241 clocks = <&cpg CPG_MOD 914>,
1237 <&cpg CPG_CORE 1242 <&cpg CPG_CORE R8A7796_CLK_CANFD>,
1238 <&can_clk>; 1243 <&can_clk>;
1239 clock-names = "fck", 1244 clock-names = "fck", "canfd", "can_clk";
1240 assigned-clocks = <&c 1245 assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>;
1241 assigned-clock-rates 1246 assigned-clock-rates = <40000000>;
1242 power-domains = <&sys 1247 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1243 resets = <&cpg 914>; 1248 resets = <&cpg 914>;
1244 status = "disabled"; 1249 status = "disabled";
1245 1250
1246 channel0 { 1251 channel0 {
1247 status = "dis 1252 status = "disabled";
1248 }; 1253 };
1249 1254
1250 channel1 { 1255 channel1 {
1251 status = "dis 1256 status = "disabled";
1252 }; 1257 };
1253 }; 1258 };
1254 1259
1255 pwm0: pwm@e6e30000 { 1260 pwm0: pwm@e6e30000 {
1256 compatible = "renesas 1261 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
1257 reg = <0 0xe6e30000 0 1262 reg = <0 0xe6e30000 0 8>;
1258 #pwm-cells = <2>; 1263 #pwm-cells = <2>;
1259 clocks = <&cpg CPG_MO 1264 clocks = <&cpg CPG_MOD 523>;
1260 resets = <&cpg 523>; 1265 resets = <&cpg 523>;
1261 power-domains = <&sys 1266 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1262 status = "disabled"; 1267 status = "disabled";
1263 }; 1268 };
1264 1269
1265 pwm1: pwm@e6e31000 { 1270 pwm1: pwm@e6e31000 {
1266 compatible = "renesas 1271 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
1267 reg = <0 0xe6e31000 0 1272 reg = <0 0xe6e31000 0 8>;
1268 #pwm-cells = <2>; 1273 #pwm-cells = <2>;
1269 clocks = <&cpg CPG_MO 1274 clocks = <&cpg CPG_MOD 523>;
1270 resets = <&cpg 523>; 1275 resets = <&cpg 523>;
1271 power-domains = <&sys 1276 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1272 status = "disabled"; 1277 status = "disabled";
1273 }; 1278 };
1274 1279
1275 pwm2: pwm@e6e32000 { 1280 pwm2: pwm@e6e32000 {
1276 compatible = "renesas 1281 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
1277 reg = <0 0xe6e32000 0 1282 reg = <0 0xe6e32000 0 8>;
1278 #pwm-cells = <2>; 1283 #pwm-cells = <2>;
1279 clocks = <&cpg CPG_MO 1284 clocks = <&cpg CPG_MOD 523>;
1280 resets = <&cpg 523>; 1285 resets = <&cpg 523>;
1281 power-domains = <&sys 1286 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1282 status = "disabled"; 1287 status = "disabled";
1283 }; 1288 };
1284 1289
1285 pwm3: pwm@e6e33000 { 1290 pwm3: pwm@e6e33000 {
1286 compatible = "renesas 1291 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
1287 reg = <0 0xe6e33000 0 1292 reg = <0 0xe6e33000 0 8>;
1288 #pwm-cells = <2>; 1293 #pwm-cells = <2>;
1289 clocks = <&cpg CPG_MO 1294 clocks = <&cpg CPG_MOD 523>;
1290 resets = <&cpg 523>; 1295 resets = <&cpg 523>;
1291 power-domains = <&sys 1296 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1292 status = "disabled"; 1297 status = "disabled";
1293 }; 1298 };
1294 1299
1295 pwm4: pwm@e6e34000 { 1300 pwm4: pwm@e6e34000 {
1296 compatible = "renesas 1301 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
1297 reg = <0 0xe6e34000 0 1302 reg = <0 0xe6e34000 0 8>;
1298 #pwm-cells = <2>; 1303 #pwm-cells = <2>;
1299 clocks = <&cpg CPG_MO 1304 clocks = <&cpg CPG_MOD 523>;
1300 resets = <&cpg 523>; 1305 resets = <&cpg 523>;
1301 power-domains = <&sys 1306 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1302 status = "disabled"; 1307 status = "disabled";
1303 }; 1308 };
1304 1309
1305 pwm5: pwm@e6e35000 { 1310 pwm5: pwm@e6e35000 {
1306 compatible = "renesas 1311 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
1307 reg = <0 0xe6e35000 0 1312 reg = <0 0xe6e35000 0 8>;
1308 #pwm-cells = <2>; 1313 #pwm-cells = <2>;
1309 clocks = <&cpg CPG_MO 1314 clocks = <&cpg CPG_MOD 523>;
1310 resets = <&cpg 523>; 1315 resets = <&cpg 523>;
1311 power-domains = <&sys 1316 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1312 status = "disabled"; 1317 status = "disabled";
1313 }; 1318 };
1314 1319
1315 pwm6: pwm@e6e36000 { 1320 pwm6: pwm@e6e36000 {
1316 compatible = "renesas 1321 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
1317 reg = <0 0xe6e36000 0 1322 reg = <0 0xe6e36000 0 8>;
1318 #pwm-cells = <2>; 1323 #pwm-cells = <2>;
1319 clocks = <&cpg CPG_MO 1324 clocks = <&cpg CPG_MOD 523>;
1320 resets = <&cpg 523>; 1325 resets = <&cpg 523>;
1321 power-domains = <&sys 1326 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1322 status = "disabled"; 1327 status = "disabled";
1323 }; 1328 };
1324 1329
1325 scif0: serial@e6e60000 { 1330 scif0: serial@e6e60000 {
1326 compatible = "renesas 1331 compatible = "renesas,scif-r8a7796",
1327 "renesas 1332 "renesas,rcar-gen3-scif", "renesas,scif";
1328 reg = <0 0xe6e60000 0 1333 reg = <0 0xe6e60000 0 64>;
1329 interrupts = <GIC_SPI 1334 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
1330 clocks = <&cpg CPG_MO 1335 clocks = <&cpg CPG_MOD 207>,
1331 <&cpg CPG_CO 1336 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
1332 <&scif_clk>; 1337 <&scif_clk>;
1333 clock-names = "fck", 1338 clock-names = "fck", "brg_int", "scif_clk";
1334 dmas = <&dmac1 0x51>, 1339 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1335 <&dmac2 0x51>, 1340 <&dmac2 0x51>, <&dmac2 0x50>;
1336 dma-names = "tx", "rx 1341 dma-names = "tx", "rx", "tx", "rx";
1337 power-domains = <&sys 1342 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1338 resets = <&cpg 207>; 1343 resets = <&cpg 207>;
1339 status = "disabled"; 1344 status = "disabled";
1340 }; 1345 };
1341 1346
1342 scif1: serial@e6e68000 { 1347 scif1: serial@e6e68000 {
1343 compatible = "renesas 1348 compatible = "renesas,scif-r8a7796",
1344 "renesas 1349 "renesas,rcar-gen3-scif", "renesas,scif";
1345 reg = <0 0xe6e68000 0 1350 reg = <0 0xe6e68000 0 64>;
1346 interrupts = <GIC_SPI 1351 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
1347 clocks = <&cpg CPG_MO 1352 clocks = <&cpg CPG_MOD 206>,
1348 <&cpg CPG_CO 1353 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
1349 <&scif_clk>; 1354 <&scif_clk>;
1350 clock-names = "fck", 1355 clock-names = "fck", "brg_int", "scif_clk";
1351 dmas = <&dmac1 0x53>, 1356 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1352 <&dmac2 0x53>, 1357 <&dmac2 0x53>, <&dmac2 0x52>;
1353 dma-names = "tx", "rx 1358 dma-names = "tx", "rx", "tx", "rx";
1354 power-domains = <&sys 1359 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1355 resets = <&cpg 206>; 1360 resets = <&cpg 206>;
1356 status = "disabled"; 1361 status = "disabled";
1357 }; 1362 };
1358 1363
1359 scif2: serial@e6e88000 { 1364 scif2: serial@e6e88000 {
1360 compatible = "renesas 1365 compatible = "renesas,scif-r8a7796",
1361 "renesas 1366 "renesas,rcar-gen3-scif", "renesas,scif";
1362 reg = <0 0xe6e88000 0 1367 reg = <0 0xe6e88000 0 64>;
1363 interrupts = <GIC_SPI 1368 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
1364 clocks = <&cpg CPG_MO 1369 clocks = <&cpg CPG_MOD 310>,
1365 <&cpg CPG_CO 1370 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
1366 <&scif_clk>; 1371 <&scif_clk>;
1367 clock-names = "fck", 1372 clock-names = "fck", "brg_int", "scif_clk";
1368 dmas = <&dmac1 0x13>, 1373 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1369 <&dmac2 0x13>, 1374 <&dmac2 0x13>, <&dmac2 0x12>;
1370 dma-names = "tx", "rx 1375 dma-names = "tx", "rx", "tx", "rx";
1371 power-domains = <&sys 1376 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1372 resets = <&cpg 310>; 1377 resets = <&cpg 310>;
1373 status = "disabled"; 1378 status = "disabled";
1374 }; 1379 };
1375 1380
1376 scif3: serial@e6c50000 { 1381 scif3: serial@e6c50000 {
1377 compatible = "renesas 1382 compatible = "renesas,scif-r8a7796",
1378 "renesas 1383 "renesas,rcar-gen3-scif", "renesas,scif";
1379 reg = <0 0xe6c50000 0 1384 reg = <0 0xe6c50000 0 64>;
1380 interrupts = <GIC_SPI 1385 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1381 clocks = <&cpg CPG_MO 1386 clocks = <&cpg CPG_MOD 204>,
1382 <&cpg CPG_CO 1387 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
1383 <&scif_clk>; 1388 <&scif_clk>;
1384 clock-names = "fck", 1389 clock-names = "fck", "brg_int", "scif_clk";
1385 dmas = <&dmac0 0x57>, 1390 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1386 dma-names = "tx", "rx 1391 dma-names = "tx", "rx";
1387 power-domains = <&sys 1392 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1388 resets = <&cpg 204>; 1393 resets = <&cpg 204>;
1389 status = "disabled"; 1394 status = "disabled";
1390 }; 1395 };
1391 1396
1392 scif4: serial@e6c40000 { 1397 scif4: serial@e6c40000 {
1393 compatible = "renesas 1398 compatible = "renesas,scif-r8a7796",
1394 "renesas 1399 "renesas,rcar-gen3-scif", "renesas,scif";
1395 reg = <0 0xe6c40000 0 1400 reg = <0 0xe6c40000 0 64>;
1396 interrupts = <GIC_SPI 1401 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1397 clocks = <&cpg CPG_MO 1402 clocks = <&cpg CPG_MOD 203>,
1398 <&cpg CPG_CO 1403 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
1399 <&scif_clk>; 1404 <&scif_clk>;
1400 clock-names = "fck", 1405 clock-names = "fck", "brg_int", "scif_clk";
1401 dmas = <&dmac0 0x59>, 1406 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1402 dma-names = "tx", "rx 1407 dma-names = "tx", "rx";
1403 power-domains = <&sys 1408 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1404 resets = <&cpg 203>; 1409 resets = <&cpg 203>;
1405 status = "disabled"; 1410 status = "disabled";
1406 }; 1411 };
1407 1412
1408 scif5: serial@e6f30000 { 1413 scif5: serial@e6f30000 {
1409 compatible = "renesas 1414 compatible = "renesas,scif-r8a7796",
1410 "renesas 1415 "renesas,rcar-gen3-scif", "renesas,scif";
1411 reg = <0 0xe6f30000 0 1416 reg = <0 0xe6f30000 0 64>;
1412 interrupts = <GIC_SPI 1417 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1413 clocks = <&cpg CPG_MO 1418 clocks = <&cpg CPG_MOD 202>,
1414 <&cpg CPG_CO 1419 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
1415 <&scif_clk>; 1420 <&scif_clk>;
1416 clock-names = "fck", 1421 clock-names = "fck", "brg_int", "scif_clk";
1417 dmas = <&dmac1 0x5b>, 1422 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
1418 <&dmac2 0x5b>, 1423 <&dmac2 0x5b>, <&dmac2 0x5a>;
1419 dma-names = "tx", "rx 1424 dma-names = "tx", "rx", "tx", "rx";
1420 power-domains = <&sys 1425 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1421 resets = <&cpg 202>; 1426 resets = <&cpg 202>;
1422 status = "disabled"; 1427 status = "disabled";
1423 }; 1428 };
1424 1429
1425 tpu: pwm@e6e80000 { 1430 tpu: pwm@e6e80000 {
1426 compatible = "renesas 1431 compatible = "renesas,tpu-r8a7796", "renesas,tpu";
1427 reg = <0 0xe6e80000 0 1432 reg = <0 0xe6e80000 0 0x148>;
1428 interrupts = <GIC_SPI 1433 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
1429 clocks = <&cpg CPG_MO 1434 clocks = <&cpg CPG_MOD 304>;
1430 power-domains = <&sys 1435 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1431 resets = <&cpg 304>; 1436 resets = <&cpg 304>;
1432 #pwm-cells = <3>; 1437 #pwm-cells = <3>;
1433 status = "disabled"; 1438 status = "disabled";
1434 }; 1439 };
1435 1440
1436 msiof0: spi@e6e90000 { 1441 msiof0: spi@e6e90000 {
1437 compatible = "renesas 1442 compatible = "renesas,msiof-r8a7796",
1438 "renesas 1443 "renesas,rcar-gen3-msiof";
1439 reg = <0 0xe6e90000 0 1444 reg = <0 0xe6e90000 0 0x0064>;
1440 interrupts = <GIC_SPI 1445 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1441 clocks = <&cpg CPG_MO 1446 clocks = <&cpg CPG_MOD 211>;
1442 dmas = <&dmac1 0x41>, 1447 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1443 <&dmac2 0x41>, 1448 <&dmac2 0x41>, <&dmac2 0x40>;
1444 dma-names = "tx", "rx 1449 dma-names = "tx", "rx", "tx", "rx";
1445 power-domains = <&sys 1450 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1446 resets = <&cpg 211>; 1451 resets = <&cpg 211>;
1447 #address-cells = <1>; 1452 #address-cells = <1>;
1448 #size-cells = <0>; 1453 #size-cells = <0>;
1449 status = "disabled"; 1454 status = "disabled";
1450 }; 1455 };
1451 1456
1452 msiof1: spi@e6ea0000 { 1457 msiof1: spi@e6ea0000 {
1453 compatible = "renesas 1458 compatible = "renesas,msiof-r8a7796",
1454 "renesas 1459 "renesas,rcar-gen3-msiof";
1455 reg = <0 0xe6ea0000 0 1460 reg = <0 0xe6ea0000 0 0x0064>;
1456 interrupts = <GIC_SPI 1461 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1457 clocks = <&cpg CPG_MO 1462 clocks = <&cpg CPG_MOD 210>;
1458 dmas = <&dmac1 0x43>, 1463 dmas = <&dmac1 0x43>, <&dmac1 0x42>,
1459 <&dmac2 0x43>, 1464 <&dmac2 0x43>, <&dmac2 0x42>;
1460 dma-names = "tx", "rx 1465 dma-names = "tx", "rx", "tx", "rx";
1461 power-domains = <&sys 1466 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1462 resets = <&cpg 210>; 1467 resets = <&cpg 210>;
1463 #address-cells = <1>; 1468 #address-cells = <1>;
1464 #size-cells = <0>; 1469 #size-cells = <0>;
1465 status = "disabled"; 1470 status = "disabled";
1466 }; 1471 };
1467 1472
1468 msiof2: spi@e6c00000 { 1473 msiof2: spi@e6c00000 {
1469 compatible = "renesas 1474 compatible = "renesas,msiof-r8a7796",
1470 "renesas 1475 "renesas,rcar-gen3-msiof";
1471 reg = <0 0xe6c00000 0 1476 reg = <0 0xe6c00000 0 0x0064>;
1472 interrupts = <GIC_SPI 1477 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1473 clocks = <&cpg CPG_MO 1478 clocks = <&cpg CPG_MOD 209>;
1474 dmas = <&dmac0 0x45>, 1479 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1475 dma-names = "tx", "rx 1480 dma-names = "tx", "rx";
1476 power-domains = <&sys 1481 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1477 resets = <&cpg 209>; 1482 resets = <&cpg 209>;
1478 #address-cells = <1>; 1483 #address-cells = <1>;
1479 #size-cells = <0>; 1484 #size-cells = <0>;
1480 status = "disabled"; 1485 status = "disabled";
1481 }; 1486 };
1482 1487
1483 msiof3: spi@e6c10000 { 1488 msiof3: spi@e6c10000 {
1484 compatible = "renesas 1489 compatible = "renesas,msiof-r8a7796",
1485 "renesas 1490 "renesas,rcar-gen3-msiof";
1486 reg = <0 0xe6c10000 0 1491 reg = <0 0xe6c10000 0 0x0064>;
1487 interrupts = <GIC_SPI 1492 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1488 clocks = <&cpg CPG_MO 1493 clocks = <&cpg CPG_MOD 208>;
1489 dmas = <&dmac0 0x47>, 1494 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1490 dma-names = "tx", "rx 1495 dma-names = "tx", "rx";
1491 power-domains = <&sys 1496 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1492 resets = <&cpg 208>; 1497 resets = <&cpg 208>;
1493 #address-cells = <1>; 1498 #address-cells = <1>;
1494 #size-cells = <0>; 1499 #size-cells = <0>;
1495 status = "disabled"; 1500 status = "disabled";
1496 }; 1501 };
1497 1502
1498 vin0: video@e6ef0000 { 1503 vin0: video@e6ef0000 {
1499 compatible = "renesas 1504 compatible = "renesas,vin-r8a7796";
1500 reg = <0 0xe6ef0000 0 1505 reg = <0 0xe6ef0000 0 0x1000>;
1501 interrupts = <GIC_SPI 1506 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
1502 clocks = <&cpg CPG_MO 1507 clocks = <&cpg CPG_MOD 811>;
1503 power-domains = <&sys 1508 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1504 resets = <&cpg 811>; 1509 resets = <&cpg 811>;
1505 renesas,id = <0>; 1510 renesas,id = <0>;
1506 status = "disabled"; 1511 status = "disabled";
1507 1512
1508 ports { 1513 ports {
1509 #address-cell 1514 #address-cells = <1>;
1510 #size-cells = 1515 #size-cells = <0>;
1511 1516
1512 port@1 { 1517 port@1 {
1513 #addr 1518 #address-cells = <1>;
1514 #size 1519 #size-cells = <0>;
1515 1520
1516 reg = 1521 reg = <1>;
1517 1522
1518 vin0c 1523 vin0csi20: endpoint@0 {
1519 1524 reg = <0>;
1520 1525 remote-endpoint = <&csi20vin0>;
1521 }; 1526 };
1522 vin0c 1527 vin0csi40: endpoint@2 {
1523 1528 reg = <2>;
1524 1529 remote-endpoint = <&csi40vin0>;
1525 }; 1530 };
1526 }; 1531 };
1527 }; 1532 };
1528 }; 1533 };
1529 1534
1530 vin1: video@e6ef1000 { 1535 vin1: video@e6ef1000 {
1531 compatible = "renesas 1536 compatible = "renesas,vin-r8a7796";
1532 reg = <0 0xe6ef1000 0 1537 reg = <0 0xe6ef1000 0 0x1000>;
1533 interrupts = <GIC_SPI 1538 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
1534 clocks = <&cpg CPG_MO 1539 clocks = <&cpg CPG_MOD 810>;
1535 power-domains = <&sys 1540 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1536 resets = <&cpg 810>; 1541 resets = <&cpg 810>;
1537 renesas,id = <1>; 1542 renesas,id = <1>;
1538 status = "disabled"; 1543 status = "disabled";
1539 1544
1540 ports { 1545 ports {
1541 #address-cell 1546 #address-cells = <1>;
1542 #size-cells = 1547 #size-cells = <0>;
1543 1548
1544 port@1 { 1549 port@1 {
1545 #addr 1550 #address-cells = <1>;
1546 #size 1551 #size-cells = <0>;
1547 1552
1548 reg = 1553 reg = <1>;
1549 1554
1550 vin1c 1555 vin1csi20: endpoint@0 {
1551 1556 reg = <0>;
1552 1557 remote-endpoint = <&csi20vin1>;
1553 }; 1558 };
1554 vin1c 1559 vin1csi40: endpoint@2 {
1555 1560 reg = <2>;
1556 1561 remote-endpoint = <&csi40vin1>;
1557 }; 1562 };
1558 }; 1563 };
1559 }; 1564 };
1560 }; 1565 };
1561 1566
1562 vin2: video@e6ef2000 { 1567 vin2: video@e6ef2000 {
1563 compatible = "renesas 1568 compatible = "renesas,vin-r8a7796";
1564 reg = <0 0xe6ef2000 0 1569 reg = <0 0xe6ef2000 0 0x1000>;
1565 interrupts = <GIC_SPI 1570 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1566 clocks = <&cpg CPG_MO 1571 clocks = <&cpg CPG_MOD 809>;
1567 power-domains = <&sys 1572 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1568 resets = <&cpg 809>; 1573 resets = <&cpg 809>;
1569 renesas,id = <2>; 1574 renesas,id = <2>;
1570 status = "disabled"; 1575 status = "disabled";
1571 1576
1572 ports { 1577 ports {
1573 #address-cell 1578 #address-cells = <1>;
1574 #size-cells = 1579 #size-cells = <0>;
1575 1580
1576 port@1 { 1581 port@1 {
1577 #addr 1582 #address-cells = <1>;
1578 #size 1583 #size-cells = <0>;
1579 1584
1580 reg = 1585 reg = <1>;
1581 1586
1582 vin2c 1587 vin2csi20: endpoint@0 {
1583 1588 reg = <0>;
1584 1589 remote-endpoint = <&csi20vin2>;
1585 }; 1590 };
1586 vin2c 1591 vin2csi40: endpoint@2 {
1587 1592 reg = <2>;
1588 1593 remote-endpoint = <&csi40vin2>;
1589 }; 1594 };
1590 }; 1595 };
1591 }; 1596 };
1592 }; 1597 };
1593 1598
1594 vin3: video@e6ef3000 { 1599 vin3: video@e6ef3000 {
1595 compatible = "renesas 1600 compatible = "renesas,vin-r8a7796";
1596 reg = <0 0xe6ef3000 0 1601 reg = <0 0xe6ef3000 0 0x1000>;
1597 interrupts = <GIC_SPI 1602 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
1598 clocks = <&cpg CPG_MO 1603 clocks = <&cpg CPG_MOD 808>;
1599 power-domains = <&sys 1604 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1600 resets = <&cpg 808>; 1605 resets = <&cpg 808>;
1601 renesas,id = <3>; 1606 renesas,id = <3>;
1602 status = "disabled"; 1607 status = "disabled";
1603 1608
1604 ports { 1609 ports {
1605 #address-cell 1610 #address-cells = <1>;
1606 #size-cells = 1611 #size-cells = <0>;
1607 1612
1608 port@1 { 1613 port@1 {
1609 #addr 1614 #address-cells = <1>;
1610 #size 1615 #size-cells = <0>;
1611 1616
1612 reg = 1617 reg = <1>;
1613 1618
1614 vin3c 1619 vin3csi20: endpoint@0 {
1615 1620 reg = <0>;
1616 1621 remote-endpoint = <&csi20vin3>;
1617 }; 1622 };
1618 vin3c 1623 vin3csi40: endpoint@2 {
1619 1624 reg = <2>;
1620 1625 remote-endpoint = <&csi40vin3>;
1621 }; 1626 };
1622 }; 1627 };
1623 }; 1628 };
1624 }; 1629 };
1625 1630
1626 vin4: video@e6ef4000 { 1631 vin4: video@e6ef4000 {
1627 compatible = "renesas 1632 compatible = "renesas,vin-r8a7796";
1628 reg = <0 0xe6ef4000 0 1633 reg = <0 0xe6ef4000 0 0x1000>;
1629 interrupts = <GIC_SPI 1634 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
1630 clocks = <&cpg CPG_MO 1635 clocks = <&cpg CPG_MOD 807>;
1631 power-domains = <&sys 1636 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1632 resets = <&cpg 807>; 1637 resets = <&cpg 807>;
1633 renesas,id = <4>; 1638 renesas,id = <4>;
1634 status = "disabled"; 1639 status = "disabled";
1635 1640
1636 ports { 1641 ports {
1637 #address-cell 1642 #address-cells = <1>;
1638 #size-cells = 1643 #size-cells = <0>;
1639 1644
1640 port@1 { 1645 port@1 {
1641 #addr 1646 #address-cells = <1>;
1642 #size 1647 #size-cells = <0>;
1643 1648
1644 reg = 1649 reg = <1>;
1645 1650
1646 vin4c 1651 vin4csi20: endpoint@0 {
1647 1652 reg = <0>;
1648 1653 remote-endpoint = <&csi20vin4>;
1649 }; 1654 };
1650 vin4c 1655 vin4csi40: endpoint@2 {
1651 1656 reg = <2>;
1652 1657 remote-endpoint = <&csi40vin4>;
1653 }; 1658 };
1654 }; 1659 };
1655 }; 1660 };
1656 }; 1661 };
1657 1662
1658 vin5: video@e6ef5000 { 1663 vin5: video@e6ef5000 {
1659 compatible = "renesas 1664 compatible = "renesas,vin-r8a7796";
1660 reg = <0 0xe6ef5000 0 1665 reg = <0 0xe6ef5000 0 0x1000>;
1661 interrupts = <GIC_SPI 1666 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
1662 clocks = <&cpg CPG_MO 1667 clocks = <&cpg CPG_MOD 806>;
1663 power-domains = <&sys 1668 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1664 resets = <&cpg 806>; 1669 resets = <&cpg 806>;
1665 renesas,id = <5>; 1670 renesas,id = <5>;
1666 status = "disabled"; 1671 status = "disabled";
1667 1672
1668 ports { 1673 ports {
1669 #address-cell 1674 #address-cells = <1>;
1670 #size-cells = 1675 #size-cells = <0>;
1671 1676
1672 port@1 { 1677 port@1 {
1673 #addr 1678 #address-cells = <1>;
1674 #size 1679 #size-cells = <0>;
1675 1680
1676 reg = 1681 reg = <1>;
1677 1682
1678 vin5c 1683 vin5csi20: endpoint@0 {
1679 1684 reg = <0>;
1680 1685 remote-endpoint = <&csi20vin5>;
1681 }; 1686 };
1682 vin5c 1687 vin5csi40: endpoint@2 {
1683 1688 reg = <2>;
1684 1689 remote-endpoint = <&csi40vin5>;
1685 }; 1690 };
1686 }; 1691 };
1687 }; 1692 };
1688 }; 1693 };
1689 1694
1690 vin6: video@e6ef6000 { 1695 vin6: video@e6ef6000 {
1691 compatible = "renesas 1696 compatible = "renesas,vin-r8a7796";
1692 reg = <0 0xe6ef6000 0 1697 reg = <0 0xe6ef6000 0 0x1000>;
1693 interrupts = <GIC_SPI 1698 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
1694 clocks = <&cpg CPG_MO 1699 clocks = <&cpg CPG_MOD 805>;
1695 power-domains = <&sys 1700 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1696 resets = <&cpg 805>; 1701 resets = <&cpg 805>;
1697 renesas,id = <6>; 1702 renesas,id = <6>;
1698 status = "disabled"; 1703 status = "disabled";
1699 1704
1700 ports { 1705 ports {
1701 #address-cell 1706 #address-cells = <1>;
1702 #size-cells = 1707 #size-cells = <0>;
1703 1708
1704 port@1 { 1709 port@1 {
1705 #addr 1710 #address-cells = <1>;
1706 #size 1711 #size-cells = <0>;
1707 1712
1708 reg = 1713 reg = <1>;
1709 1714
1710 vin6c 1715 vin6csi20: endpoint@0 {
1711 1716 reg = <0>;
1712 1717 remote-endpoint = <&csi20vin6>;
1713 }; 1718 };
1714 vin6c 1719 vin6csi40: endpoint@2 {
1715 1720 reg = <2>;
1716 1721 remote-endpoint = <&csi40vin6>;
1717 }; 1722 };
1718 }; 1723 };
1719 }; 1724 };
1720 }; 1725 };
1721 1726
1722 vin7: video@e6ef7000 { 1727 vin7: video@e6ef7000 {
1723 compatible = "renesas 1728 compatible = "renesas,vin-r8a7796";
1724 reg = <0 0xe6ef7000 0 1729 reg = <0 0xe6ef7000 0 0x1000>;
1725 interrupts = <GIC_SPI 1730 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
1726 clocks = <&cpg CPG_MO 1731 clocks = <&cpg CPG_MOD 804>;
1727 power-domains = <&sys 1732 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1728 resets = <&cpg 804>; 1733 resets = <&cpg 804>;
1729 renesas,id = <7>; 1734 renesas,id = <7>;
1730 status = "disabled"; 1735 status = "disabled";
1731 1736
1732 ports { 1737 ports {
1733 #address-cell 1738 #address-cells = <1>;
1734 #size-cells = 1739 #size-cells = <0>;
1735 1740
1736 port@1 { 1741 port@1 {
1737 #addr 1742 #address-cells = <1>;
1738 #size 1743 #size-cells = <0>;
1739 1744
1740 reg = 1745 reg = <1>;
1741 1746
1742 vin7c 1747 vin7csi20: endpoint@0 {
1743 1748 reg = <0>;
1744 1749 remote-endpoint = <&csi20vin7>;
1745 }; 1750 };
1746 vin7c 1751 vin7csi40: endpoint@2 {
1747 1752 reg = <2>;
1748 1753 remote-endpoint = <&csi40vin7>;
1749 }; 1754 };
1750 }; 1755 };
1751 }; 1756 };
1752 }; 1757 };
1753 1758
1754 drif00: rif@e6f40000 { 1759 drif00: rif@e6f40000 {
1755 compatible = "renesas 1760 compatible = "renesas,r8a7796-drif",
1756 "renesas 1761 "renesas,rcar-gen3-drif";
1757 reg = <0 0xe6f40000 0 1762 reg = <0 0xe6f40000 0 0x64>;
1758 interrupts = <GIC_SPI 1763 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1759 clocks = <&cpg CPG_MO 1764 clocks = <&cpg CPG_MOD 515>;
1760 clock-names = "fck"; 1765 clock-names = "fck";
1761 dmas = <&dmac1 0x20>, 1766 dmas = <&dmac1 0x20>, <&dmac2 0x20>;
1762 dma-names = "rx", "rx 1767 dma-names = "rx", "rx";
1763 power-domains = <&sys 1768 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1764 resets = <&cpg 515>; 1769 resets = <&cpg 515>;
1765 renesas,bonding = <&d 1770 renesas,bonding = <&drif01>;
1766 status = "disabled"; 1771 status = "disabled";
1767 }; 1772 };
1768 1773
1769 drif01: rif@e6f50000 { 1774 drif01: rif@e6f50000 {
1770 compatible = "renesas 1775 compatible = "renesas,r8a7796-drif",
1771 "renesas 1776 "renesas,rcar-gen3-drif";
1772 reg = <0 0xe6f50000 0 1777 reg = <0 0xe6f50000 0 0x64>;
1773 interrupts = <GIC_SPI 1778 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1774 clocks = <&cpg CPG_MO 1779 clocks = <&cpg CPG_MOD 514>;
1775 clock-names = "fck"; 1780 clock-names = "fck";
1776 dmas = <&dmac1 0x22>, 1781 dmas = <&dmac1 0x22>, <&dmac2 0x22>;
1777 dma-names = "rx", "rx 1782 dma-names = "rx", "rx";
1778 power-domains = <&sys 1783 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1779 resets = <&cpg 514>; 1784 resets = <&cpg 514>;
1780 renesas,bonding = <&d 1785 renesas,bonding = <&drif00>;
1781 status = "disabled"; 1786 status = "disabled";
1782 }; 1787 };
1783 1788
1784 drif10: rif@e6f60000 { 1789 drif10: rif@e6f60000 {
1785 compatible = "renesas 1790 compatible = "renesas,r8a7796-drif",
1786 "renesas 1791 "renesas,rcar-gen3-drif";
1787 reg = <0 0xe6f60000 0 1792 reg = <0 0xe6f60000 0 0x64>;
1788 interrupts = <GIC_SPI 1793 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1789 clocks = <&cpg CPG_MO 1794 clocks = <&cpg CPG_MOD 513>;
1790 clock-names = "fck"; 1795 clock-names = "fck";
1791 dmas = <&dmac1 0x24>, 1796 dmas = <&dmac1 0x24>, <&dmac2 0x24>;
1792 dma-names = "rx", "rx 1797 dma-names = "rx", "rx";
1793 power-domains = <&sys 1798 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1794 resets = <&cpg 513>; 1799 resets = <&cpg 513>;
1795 renesas,bonding = <&d 1800 renesas,bonding = <&drif11>;
1796 status = "disabled"; 1801 status = "disabled";
1797 }; 1802 };
1798 1803
1799 drif11: rif@e6f70000 { 1804 drif11: rif@e6f70000 {
1800 compatible = "renesas 1805 compatible = "renesas,r8a7796-drif",
1801 "renesas 1806 "renesas,rcar-gen3-drif";
1802 reg = <0 0xe6f70000 0 1807 reg = <0 0xe6f70000 0 0x64>;
1803 interrupts = <GIC_SPI 1808 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1804 clocks = <&cpg CPG_MO 1809 clocks = <&cpg CPG_MOD 512>;
1805 clock-names = "fck"; 1810 clock-names = "fck";
1806 dmas = <&dmac1 0x26>, 1811 dmas = <&dmac1 0x26>, <&dmac2 0x26>;
1807 dma-names = "rx", "rx 1812 dma-names = "rx", "rx";
1808 power-domains = <&sys 1813 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1809 resets = <&cpg 512>; 1814 resets = <&cpg 512>;
1810 renesas,bonding = <&d 1815 renesas,bonding = <&drif10>;
1811 status = "disabled"; 1816 status = "disabled";
1812 }; 1817 };
1813 1818
1814 drif20: rif@e6f80000 { 1819 drif20: rif@e6f80000 {
1815 compatible = "renesas 1820 compatible = "renesas,r8a7796-drif",
1816 "renesas 1821 "renesas,rcar-gen3-drif";
1817 reg = <0 0xe6f80000 0 1822 reg = <0 0xe6f80000 0 0x64>;
1818 interrupts = <GIC_SPI 1823 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1819 clocks = <&cpg CPG_MO 1824 clocks = <&cpg CPG_MOD 511>;
1820 clock-names = "fck"; 1825 clock-names = "fck";
1821 dmas = <&dmac1 0x28>, 1826 dmas = <&dmac1 0x28>, <&dmac2 0x28>;
1822 dma-names = "rx", "rx 1827 dma-names = "rx", "rx";
1823 power-domains = <&sys 1828 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1824 resets = <&cpg 511>; 1829 resets = <&cpg 511>;
1825 renesas,bonding = <&d 1830 renesas,bonding = <&drif21>;
1826 status = "disabled"; 1831 status = "disabled";
1827 }; 1832 };
1828 1833
1829 drif21: rif@e6f90000 { 1834 drif21: rif@e6f90000 {
1830 compatible = "renesas 1835 compatible = "renesas,r8a7796-drif",
1831 "renesas 1836 "renesas,rcar-gen3-drif";
1832 reg = <0 0xe6f90000 0 1837 reg = <0 0xe6f90000 0 0x64>;
1833 interrupts = <GIC_SPI 1838 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1834 clocks = <&cpg CPG_MO 1839 clocks = <&cpg CPG_MOD 510>;
1835 clock-names = "fck"; 1840 clock-names = "fck";
1836 dmas = <&dmac1 0x2a>, 1841 dmas = <&dmac1 0x2a>, <&dmac2 0x2a>;
1837 dma-names = "rx", "rx 1842 dma-names = "rx", "rx";
1838 power-domains = <&sys 1843 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1839 resets = <&cpg 510>; 1844 resets = <&cpg 510>;
1840 renesas,bonding = <&d 1845 renesas,bonding = <&drif20>;
1841 status = "disabled"; 1846 status = "disabled";
1842 }; 1847 };
1843 1848
1844 drif30: rif@e6fa0000 { 1849 drif30: rif@e6fa0000 {
1845 compatible = "renesas 1850 compatible = "renesas,r8a7796-drif",
1846 "renesas 1851 "renesas,rcar-gen3-drif";
1847 reg = <0 0xe6fa0000 0 1852 reg = <0 0xe6fa0000 0 0x64>;
1848 interrupts = <GIC_SPI 1853 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1849 clocks = <&cpg CPG_MO 1854 clocks = <&cpg CPG_MOD 509>;
1850 clock-names = "fck"; 1855 clock-names = "fck";
1851 dmas = <&dmac1 0x2c>, 1856 dmas = <&dmac1 0x2c>, <&dmac2 0x2c>;
1852 dma-names = "rx", "rx 1857 dma-names = "rx", "rx";
1853 power-domains = <&sys 1858 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1854 resets = <&cpg 509>; 1859 resets = <&cpg 509>;
1855 renesas,bonding = <&d 1860 renesas,bonding = <&drif31>;
1856 status = "disabled"; 1861 status = "disabled";
1857 }; 1862 };
1858 1863
1859 drif31: rif@e6fb0000 { 1864 drif31: rif@e6fb0000 {
1860 compatible = "renesas 1865 compatible = "renesas,r8a7796-drif",
1861 "renesas 1866 "renesas,rcar-gen3-drif";
1862 reg = <0 0xe6fb0000 0 1867 reg = <0 0xe6fb0000 0 0x64>;
1863 interrupts = <GIC_SPI 1868 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1864 clocks = <&cpg CPG_MO 1869 clocks = <&cpg CPG_MOD 508>;
1865 clock-names = "fck"; 1870 clock-names = "fck";
1866 dmas = <&dmac1 0x2e>, 1871 dmas = <&dmac1 0x2e>, <&dmac2 0x2e>;
1867 dma-names = "rx", "rx 1872 dma-names = "rx", "rx";
1868 power-domains = <&sys 1873 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1869 resets = <&cpg 508>; 1874 resets = <&cpg 508>;
1870 renesas,bonding = <&d 1875 renesas,bonding = <&drif30>;
1871 status = "disabled"; 1876 status = "disabled";
1872 }; 1877 };
1873 1878
1874 rcar_sound: sound@ec500000 { 1879 rcar_sound: sound@ec500000 {
1875 /* 1880 /*
1876 * #sound-dai-cells i !! 1881 * #sound-dai-cells is required
1877 * 1882 *
1878 * Single DAI : #soun 1883 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1879 * Multi DAI : #soun 1884 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1880 */ 1885 */
1881 /* 1886 /*
1882 * #clock-cells is re 1887 * #clock-cells is required for audio_clkout0/1/2/3
1883 * 1888 *
1884 * clkout : #cl 1889 * clkout : #clock-cells = <0>; <&rcar_sound>;
1885 * clkout0/1/2/3: #cl 1890 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
1886 */ 1891 */
1887 compatible = "renesas !! 1892 compatible = "renesas,rcar_sound-r8a7796", "renesas,rcar_sound-gen3";
1888 reg = <0 0xec500000 0 !! 1893 reg = <0 0xec500000 0 0x1000>, /* SCU */
1889 <0 0xec5a0000 0 !! 1894 <0 0xec5a0000 0 0x100>, /* ADG */
1890 <0 0xec540000 0 !! 1895 <0 0xec540000 0 0x1000>, /* SSIU */
1891 <0 0xec541000 0 !! 1896 <0 0xec541000 0 0x280>, /* SSI */
1892 <0 0xec760000 0 !! 1897 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
1893 reg-names = "scu", "a 1898 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1894 1899
1895 clocks = <&cpg CPG_MO 1900 clocks = <&cpg CPG_MOD 1005>,
1896 <&cpg CPG_MO 1901 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
1897 <&cpg CPG_MO 1902 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
1898 <&cpg CPG_MO 1903 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
1899 <&cpg CPG_MO 1904 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
1900 <&cpg CPG_MO 1905 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
1901 <&cpg CPG_MO 1906 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
1902 <&cpg CPG_MO 1907 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
1903 <&cpg CPG_MO 1908 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
1904 <&cpg CPG_MO 1909 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
1905 <&cpg CPG_MO 1910 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
1906 <&cpg CPG_MO 1911 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1907 <&cpg CPG_MO 1912 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1908 <&cpg CPG_MO 1913 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
1909 <&audio_clk_ 1914 <&audio_clk_a>, <&audio_clk_b>,
1910 <&audio_clk_ 1915 <&audio_clk_c>,
1911 <&cpg CPG_MO !! 1916 <&cpg CPG_CORE R8A7796_CLK_S0D4>;
1912 clock-names = "ssi-al 1917 clock-names = "ssi-all",
1913 "ssi.9" 1918 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1914 "ssi.5" 1919 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1915 "ssi.1" 1920 "ssi.1", "ssi.0",
1916 "src.9" 1921 "src.9", "src.8", "src.7", "src.6",
1917 "src.5" 1922 "src.5", "src.4", "src.3", "src.2",
1918 "src.1" 1923 "src.1", "src.0",
1919 "mix.1" 1924 "mix.1", "mix.0",
1920 "ctu.1" 1925 "ctu.1", "ctu.0",
1921 "dvc.0" 1926 "dvc.0", "dvc.1",
1922 "clk_a" 1927 "clk_a", "clk_b", "clk_c", "clk_i";
1923 power-domains = <&sys 1928 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1924 resets = <&cpg 1005>, 1929 resets = <&cpg 1005>,
1925 <&cpg 1006>, 1930 <&cpg 1006>, <&cpg 1007>,
1926 <&cpg 1008>, 1931 <&cpg 1008>, <&cpg 1009>,
1927 <&cpg 1010>, 1932 <&cpg 1010>, <&cpg 1011>,
1928 <&cpg 1012>, 1933 <&cpg 1012>, <&cpg 1013>,
1929 <&cpg 1014>, 1934 <&cpg 1014>, <&cpg 1015>;
1930 reset-names = "ssi-al 1935 reset-names = "ssi-all",
1931 "ssi.9" 1936 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1932 "ssi.5" 1937 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1933 "ssi.1" 1938 "ssi.1", "ssi.0";
1934 status = "disabled"; 1939 status = "disabled";
1935 1940
1936 rcar_sound,ctu { 1941 rcar_sound,ctu {
1937 ctu00: ctu-0 1942 ctu00: ctu-0 { };
1938 ctu01: ctu-1 1943 ctu01: ctu-1 { };
1939 ctu02: ctu-2 1944 ctu02: ctu-2 { };
1940 ctu03: ctu-3 1945 ctu03: ctu-3 { };
1941 ctu10: ctu-4 1946 ctu10: ctu-4 { };
1942 ctu11: ctu-5 1947 ctu11: ctu-5 { };
1943 ctu12: ctu-6 1948 ctu12: ctu-6 { };
1944 ctu13: ctu-7 1949 ctu13: ctu-7 { };
1945 }; 1950 };
1946 1951
1947 rcar_sound,dvc { 1952 rcar_sound,dvc {
1948 dvc0: dvc-0 { 1953 dvc0: dvc-0 {
1949 dmas 1954 dmas = <&audma1 0xbc>;
1950 dma-n 1955 dma-names = "tx";
1951 }; 1956 };
1952 dvc1: dvc-1 { 1957 dvc1: dvc-1 {
1953 dmas 1958 dmas = <&audma1 0xbe>;
1954 dma-n 1959 dma-names = "tx";
1955 }; 1960 };
1956 }; 1961 };
1957 1962
1958 rcar_sound,mix { 1963 rcar_sound,mix {
1959 mix0: mix-0 { 1964 mix0: mix-0 { };
1960 mix1: mix-1 { 1965 mix1: mix-1 { };
1961 }; 1966 };
1962 1967
1963 rcar_sound,src { 1968 rcar_sound,src {
1964 src0: src-0 { 1969 src0: src-0 {
1965 inter 1970 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1966 dmas 1971 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1967 dma-n 1972 dma-names = "rx", "tx";
1968 }; 1973 };
1969 src1: src-1 { 1974 src1: src-1 {
1970 inter 1975 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1971 dmas 1976 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1972 dma-n 1977 dma-names = "rx", "tx";
1973 }; 1978 };
1974 src2: src-2 { 1979 src2: src-2 {
1975 inter 1980 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1976 dmas 1981 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1977 dma-n 1982 dma-names = "rx", "tx";
1978 }; 1983 };
1979 src3: src-3 { 1984 src3: src-3 {
1980 inter 1985 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1981 dmas 1986 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1982 dma-n 1987 dma-names = "rx", "tx";
1983 }; 1988 };
1984 src4: src-4 { 1989 src4: src-4 {
1985 inter 1990 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1986 dmas 1991 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1987 dma-n 1992 dma-names = "rx", "tx";
1988 }; 1993 };
1989 src5: src-5 { 1994 src5: src-5 {
1990 inter 1995 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1991 dmas 1996 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1992 dma-n 1997 dma-names = "rx", "tx";
1993 }; 1998 };
1994 src6: src-6 { 1999 src6: src-6 {
1995 inter 2000 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1996 dmas 2001 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1997 dma-n 2002 dma-names = "rx", "tx";
1998 }; 2003 };
1999 src7: src-7 { 2004 src7: src-7 {
2000 inter 2005 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
2001 dmas 2006 dmas = <&audma0 0x93>, <&audma1 0xb6>;
2002 dma-n 2007 dma-names = "rx", "tx";
2003 }; 2008 };
2004 src8: src-8 { 2009 src8: src-8 {
2005 inter 2010 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2006 dmas 2011 dmas = <&audma0 0x95>, <&audma1 0xb8>;
2007 dma-n 2012 dma-names = "rx", "tx";
2008 }; 2013 };
2009 src9: src-9 { 2014 src9: src-9 {
2010 inter 2015 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
2011 dmas 2016 dmas = <&audma0 0x97>, <&audma1 0xba>;
2012 dma-n 2017 dma-names = "rx", "tx";
2013 }; 2018 };
2014 }; 2019 };
2015 2020
2016 rcar_sound,ssi { 2021 rcar_sound,ssi {
2017 ssi0: ssi-0 { 2022 ssi0: ssi-0 {
2018 inter 2023 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
2019 dmas 2024 dmas = <&audma0 0x01>, <&audma1 0x02>;
2020 dma-n 2025 dma-names = "rx", "tx";
2021 }; 2026 };
2022 ssi1: ssi-1 { 2027 ssi1: ssi-1 {
2023 inter 2028 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
2024 dmas 2029 dmas = <&audma0 0x03>, <&audma1 0x04>;
2025 dma-n 2030 dma-names = "rx", "tx";
2026 }; 2031 };
2027 ssi2: ssi-2 { 2032 ssi2: ssi-2 {
2028 inter 2033 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
2029 dmas 2034 dmas = <&audma0 0x05>, <&audma1 0x06>;
2030 dma-n 2035 dma-names = "rx", "tx";
2031 }; 2036 };
2032 ssi3: ssi-3 { 2037 ssi3: ssi-3 {
2033 inter 2038 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
2034 dmas 2039 dmas = <&audma0 0x07>, <&audma1 0x08>;
2035 dma-n 2040 dma-names = "rx", "tx";
2036 }; 2041 };
2037 ssi4: ssi-4 { 2042 ssi4: ssi-4 {
2038 inter 2043 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
2039 dmas 2044 dmas = <&audma0 0x09>, <&audma1 0x0a>;
2040 dma-n 2045 dma-names = "rx", "tx";
2041 }; 2046 };
2042 ssi5: ssi-5 { 2047 ssi5: ssi-5 {
2043 inter 2048 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
2044 dmas 2049 dmas = <&audma0 0x0b>, <&audma1 0x0c>;
2045 dma-n 2050 dma-names = "rx", "tx";
2046 }; 2051 };
2047 ssi6: ssi-6 { 2052 ssi6: ssi-6 {
2048 inter 2053 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
2049 dmas 2054 dmas = <&audma0 0x0d>, <&audma1 0x0e>;
2050 dma-n 2055 dma-names = "rx", "tx";
2051 }; 2056 };
2052 ssi7: ssi-7 { 2057 ssi7: ssi-7 {
2053 inter 2058 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
2054 dmas 2059 dmas = <&audma0 0x0f>, <&audma1 0x10>;
2055 dma-n 2060 dma-names = "rx", "tx";
2056 }; 2061 };
2057 ssi8: ssi-8 { 2062 ssi8: ssi-8 {
2058 inter 2063 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
2059 dmas 2064 dmas = <&audma0 0x11>, <&audma1 0x12>;
2060 dma-n 2065 dma-names = "rx", "tx";
2061 }; 2066 };
2062 ssi9: ssi-9 { 2067 ssi9: ssi-9 {
2063 inter 2068 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
2064 dmas 2069 dmas = <&audma0 0x13>, <&audma1 0x14>;
2065 dma-n 2070 dma-names = "rx", "tx";
2066 }; 2071 };
2067 }; 2072 };
2068 2073
2069 rcar_sound,ssiu { 2074 rcar_sound,ssiu {
2070 ssiu00: ssiu- 2075 ssiu00: ssiu-0 {
2071 dmas 2076 dmas = <&audma0 0x15>, <&audma1 0x16>;
2072 dma-n 2077 dma-names = "rx", "tx";
2073 }; 2078 };
2074 ssiu01: ssiu- 2079 ssiu01: ssiu-1 {
2075 dmas 2080 dmas = <&audma0 0x35>, <&audma1 0x36>;
2076 dma-n 2081 dma-names = "rx", "tx";
2077 }; 2082 };
2078 ssiu02: ssiu- 2083 ssiu02: ssiu-2 {
2079 dmas 2084 dmas = <&audma0 0x37>, <&audma1 0x38>;
2080 dma-n 2085 dma-names = "rx", "tx";
2081 }; 2086 };
2082 ssiu03: ssiu- 2087 ssiu03: ssiu-3 {
2083 dmas 2088 dmas = <&audma0 0x47>, <&audma1 0x48>;
2084 dma-n 2089 dma-names = "rx", "tx";
2085 }; 2090 };
2086 ssiu04: ssiu- 2091 ssiu04: ssiu-4 {
2087 dmas 2092 dmas = <&audma0 0x3F>, <&audma1 0x40>;
2088 dma-n 2093 dma-names = "rx", "tx";
2089 }; 2094 };
2090 ssiu05: ssiu- 2095 ssiu05: ssiu-5 {
2091 dmas 2096 dmas = <&audma0 0x43>, <&audma1 0x44>;
2092 dma-n 2097 dma-names = "rx", "tx";
2093 }; 2098 };
2094 ssiu06: ssiu- 2099 ssiu06: ssiu-6 {
2095 dmas 2100 dmas = <&audma0 0x4F>, <&audma1 0x50>;
2096 dma-n 2101 dma-names = "rx", "tx";
2097 }; 2102 };
2098 ssiu07: ssiu- 2103 ssiu07: ssiu-7 {
2099 dmas 2104 dmas = <&audma0 0x53>, <&audma1 0x54>;
2100 dma-n 2105 dma-names = "rx", "tx";
2101 }; 2106 };
2102 ssiu10: ssiu- 2107 ssiu10: ssiu-8 {
2103 dmas 2108 dmas = <&audma0 0x49>, <&audma1 0x4a>;
2104 dma-n 2109 dma-names = "rx", "tx";
2105 }; 2110 };
2106 ssiu11: ssiu- 2111 ssiu11: ssiu-9 {
2107 dmas 2112 dmas = <&audma0 0x4B>, <&audma1 0x4C>;
2108 dma-n 2113 dma-names = "rx", "tx";
2109 }; 2114 };
2110 ssiu12: ssiu- 2115 ssiu12: ssiu-10 {
2111 dmas 2116 dmas = <&audma0 0x57>, <&audma1 0x58>;
2112 dma-n 2117 dma-names = "rx", "tx";
2113 }; 2118 };
2114 ssiu13: ssiu- 2119 ssiu13: ssiu-11 {
2115 dmas 2120 dmas = <&audma0 0x59>, <&audma1 0x5A>;
2116 dma-n 2121 dma-names = "rx", "tx";
2117 }; 2122 };
2118 ssiu14: ssiu- 2123 ssiu14: ssiu-12 {
2119 dmas 2124 dmas = <&audma0 0x5F>, <&audma1 0x60>;
2120 dma-n 2125 dma-names = "rx", "tx";
2121 }; 2126 };
2122 ssiu15: ssiu- 2127 ssiu15: ssiu-13 {
2123 dmas 2128 dmas = <&audma0 0xC3>, <&audma1 0xC4>;
2124 dma-n 2129 dma-names = "rx", "tx";
2125 }; 2130 };
2126 ssiu16: ssiu- 2131 ssiu16: ssiu-14 {
2127 dmas 2132 dmas = <&audma0 0xC7>, <&audma1 0xC8>;
2128 dma-n 2133 dma-names = "rx", "tx";
2129 }; 2134 };
2130 ssiu17: ssiu- 2135 ssiu17: ssiu-15 {
2131 dmas 2136 dmas = <&audma0 0xCB>, <&audma1 0xCC>;
2132 dma-n 2137 dma-names = "rx", "tx";
2133 }; 2138 };
2134 ssiu20: ssiu- 2139 ssiu20: ssiu-16 {
2135 dmas 2140 dmas = <&audma0 0x63>, <&audma1 0x64>;
2136 dma-n 2141 dma-names = "rx", "tx";
2137 }; 2142 };
2138 ssiu21: ssiu- 2143 ssiu21: ssiu-17 {
2139 dmas 2144 dmas = <&audma0 0x67>, <&audma1 0x68>;
2140 dma-n 2145 dma-names = "rx", "tx";
2141 }; 2146 };
2142 ssiu22: ssiu- 2147 ssiu22: ssiu-18 {
2143 dmas 2148 dmas = <&audma0 0x6B>, <&audma1 0x6C>;
2144 dma-n 2149 dma-names = "rx", "tx";
2145 }; 2150 };
2146 ssiu23: ssiu- 2151 ssiu23: ssiu-19 {
2147 dmas 2152 dmas = <&audma0 0x6D>, <&audma1 0x6E>;
2148 dma-n 2153 dma-names = "rx", "tx";
2149 }; 2154 };
2150 ssiu24: ssiu- 2155 ssiu24: ssiu-20 {
2151 dmas 2156 dmas = <&audma0 0xCF>, <&audma1 0xCE>;
2152 dma-n 2157 dma-names = "rx", "tx";
2153 }; 2158 };
2154 ssiu25: ssiu- 2159 ssiu25: ssiu-21 {
2155 dmas 2160 dmas = <&audma0 0xEB>, <&audma1 0xEC>;
2156 dma-n 2161 dma-names = "rx", "tx";
2157 }; 2162 };
2158 ssiu26: ssiu- 2163 ssiu26: ssiu-22 {
2159 dmas 2164 dmas = <&audma0 0xED>, <&audma1 0xEE>;
2160 dma-n 2165 dma-names = "rx", "tx";
2161 }; 2166 };
2162 ssiu27: ssiu- 2167 ssiu27: ssiu-23 {
2163 dmas 2168 dmas = <&audma0 0xEF>, <&audma1 0xF0>;
2164 dma-n 2169 dma-names = "rx", "tx";
2165 }; 2170 };
2166 ssiu30: ssiu- 2171 ssiu30: ssiu-24 {
2167 dmas 2172 dmas = <&audma0 0x6f>, <&audma1 0x70>;
2168 dma-n 2173 dma-names = "rx", "tx";
2169 }; 2174 };
2170 ssiu31: ssiu- 2175 ssiu31: ssiu-25 {
2171 dmas 2176 dmas = <&audma0 0x21>, <&audma1 0x22>;
2172 dma-n 2177 dma-names = "rx", "tx";
2173 }; 2178 };
2174 ssiu32: ssiu- 2179 ssiu32: ssiu-26 {
2175 dmas 2180 dmas = <&audma0 0x23>, <&audma1 0x24>;
2176 dma-n 2181 dma-names = "rx", "tx";
2177 }; 2182 };
2178 ssiu33: ssiu- 2183 ssiu33: ssiu-27 {
2179 dmas 2184 dmas = <&audma0 0x25>, <&audma1 0x26>;
2180 dma-n 2185 dma-names = "rx", "tx";
2181 }; 2186 };
2182 ssiu34: ssiu- 2187 ssiu34: ssiu-28 {
2183 dmas 2188 dmas = <&audma0 0x27>, <&audma1 0x28>;
2184 dma-n 2189 dma-names = "rx", "tx";
2185 }; 2190 };
2186 ssiu35: ssiu- 2191 ssiu35: ssiu-29 {
2187 dmas 2192 dmas = <&audma0 0x29>, <&audma1 0x2A>;
2188 dma-n 2193 dma-names = "rx", "tx";
2189 }; 2194 };
2190 ssiu36: ssiu- 2195 ssiu36: ssiu-30 {
2191 dmas 2196 dmas = <&audma0 0x2B>, <&audma1 0x2C>;
2192 dma-n 2197 dma-names = "rx", "tx";
2193 }; 2198 };
2194 ssiu37: ssiu- 2199 ssiu37: ssiu-31 {
2195 dmas 2200 dmas = <&audma0 0x2D>, <&audma1 0x2E>;
2196 dma-n 2201 dma-names = "rx", "tx";
2197 }; 2202 };
2198 ssiu40: ssiu- 2203 ssiu40: ssiu-32 {
2199 dmas !! 2204 dmas = <&audma0 0x71>, <&audma1 0x72>;
2200 dma-n 2205 dma-names = "rx", "tx";
2201 }; 2206 };
2202 ssiu41: ssiu- 2207 ssiu41: ssiu-33 {
2203 dmas 2208 dmas = <&audma0 0x17>, <&audma1 0x18>;
2204 dma-n 2209 dma-names = "rx", "tx";
2205 }; 2210 };
2206 ssiu42: ssiu- 2211 ssiu42: ssiu-34 {
2207 dmas 2212 dmas = <&audma0 0x19>, <&audma1 0x1A>;
2208 dma-n 2213 dma-names = "rx", "tx";
2209 }; 2214 };
2210 ssiu43: ssiu- 2215 ssiu43: ssiu-35 {
2211 dmas 2216 dmas = <&audma0 0x1B>, <&audma1 0x1C>;
2212 dma-n 2217 dma-names = "rx", "tx";
2213 }; 2218 };
2214 ssiu44: ssiu- 2219 ssiu44: ssiu-36 {
2215 dmas 2220 dmas = <&audma0 0x1D>, <&audma1 0x1E>;
2216 dma-n 2221 dma-names = "rx", "tx";
2217 }; 2222 };
2218 ssiu45: ssiu- 2223 ssiu45: ssiu-37 {
2219 dmas 2224 dmas = <&audma0 0x1F>, <&audma1 0x20>;
2220 dma-n 2225 dma-names = "rx", "tx";
2221 }; 2226 };
2222 ssiu46: ssiu- 2227 ssiu46: ssiu-38 {
2223 dmas 2228 dmas = <&audma0 0x31>, <&audma1 0x32>;
2224 dma-n 2229 dma-names = "rx", "tx";
2225 }; 2230 };
2226 ssiu47: ssiu- 2231 ssiu47: ssiu-39 {
2227 dmas 2232 dmas = <&audma0 0x33>, <&audma1 0x34>;
2228 dma-n 2233 dma-names = "rx", "tx";
2229 }; 2234 };
2230 ssiu50: ssiu- 2235 ssiu50: ssiu-40 {
2231 dmas 2236 dmas = <&audma0 0x73>, <&audma1 0x74>;
2232 dma-n 2237 dma-names = "rx", "tx";
2233 }; 2238 };
2234 ssiu60: ssiu- 2239 ssiu60: ssiu-41 {
2235 dmas 2240 dmas = <&audma0 0x75>, <&audma1 0x76>;
2236 dma-n 2241 dma-names = "rx", "tx";
2237 }; 2242 };
2238 ssiu70: ssiu- 2243 ssiu70: ssiu-42 {
2239 dmas 2244 dmas = <&audma0 0x79>, <&audma1 0x7a>;
2240 dma-n 2245 dma-names = "rx", "tx";
2241 }; 2246 };
2242 ssiu80: ssiu- 2247 ssiu80: ssiu-43 {
2243 dmas 2248 dmas = <&audma0 0x7b>, <&audma1 0x7c>;
2244 dma-n 2249 dma-names = "rx", "tx";
2245 }; 2250 };
2246 ssiu90: ssiu- 2251 ssiu90: ssiu-44 {
2247 dmas 2252 dmas = <&audma0 0x7d>, <&audma1 0x7e>;
2248 dma-n 2253 dma-names = "rx", "tx";
2249 }; 2254 };
2250 ssiu91: ssiu- 2255 ssiu91: ssiu-45 {
2251 dmas 2256 dmas = <&audma0 0x7F>, <&audma1 0x80>;
2252 dma-n 2257 dma-names = "rx", "tx";
2253 }; 2258 };
2254 ssiu92: ssiu- 2259 ssiu92: ssiu-46 {
2255 dmas 2260 dmas = <&audma0 0x81>, <&audma1 0x82>;
2256 dma-n 2261 dma-names = "rx", "tx";
2257 }; 2262 };
2258 ssiu93: ssiu- 2263 ssiu93: ssiu-47 {
2259 dmas 2264 dmas = <&audma0 0x83>, <&audma1 0x84>;
2260 dma-n 2265 dma-names = "rx", "tx";
2261 }; 2266 };
2262 ssiu94: ssiu- 2267 ssiu94: ssiu-48 {
2263 dmas 2268 dmas = <&audma0 0xA3>, <&audma1 0xA4>;
2264 dma-n 2269 dma-names = "rx", "tx";
2265 }; 2270 };
2266 ssiu95: ssiu- 2271 ssiu95: ssiu-49 {
2267 dmas 2272 dmas = <&audma0 0xA5>, <&audma1 0xA6>;
2268 dma-n 2273 dma-names = "rx", "tx";
2269 }; 2274 };
2270 ssiu96: ssiu- 2275 ssiu96: ssiu-50 {
2271 dmas 2276 dmas = <&audma0 0xA7>, <&audma1 0xA8>;
2272 dma-n 2277 dma-names = "rx", "tx";
2273 }; 2278 };
2274 ssiu97: ssiu- 2279 ssiu97: ssiu-51 {
2275 dmas 2280 dmas = <&audma0 0xA9>, <&audma1 0xAA>;
2276 dma-n 2281 dma-names = "rx", "tx";
2277 }; 2282 };
2278 }; 2283 };
2279 }; 2284 };
2280 2285
2281 mlp: mlp@ec520000 { <<
2282 compatible = "renesas <<
2283 "renesas <<
2284 reg = <0 0xec520000 0 <<
2285 interrupts = <GIC_SPI <<
2286 <GIC_SPI 385 <<
2287 clocks = <&cpg CPG_MO <<
2288 power-domains = <&sys <<
2289 resets = <&cpg 802>; <<
2290 status = "disabled"; <<
2291 }; <<
2292 <<
2293 audma0: dma-controller@ec7000 2286 audma0: dma-controller@ec700000 {
2294 compatible = "renesas 2287 compatible = "renesas,dmac-r8a7796",
2295 "renesas 2288 "renesas,rcar-dmac";
2296 reg = <0 0xec700000 0 2289 reg = <0 0xec700000 0 0x10000>;
2297 interrupts = <GIC_SPI 2290 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
2298 <GIC_SPI 2291 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
2299 <GIC_SPI 2292 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
2300 <GIC_SPI 2293 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
2301 <GIC_SPI 2294 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
2302 <GIC_SPI 2295 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
2303 <GIC_SPI 2296 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
2304 <GIC_SPI 2297 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
2305 <GIC_SPI 2298 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
2306 <GIC_SPI 2299 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
2307 <GIC_SPI 2300 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
2308 <GIC_SPI 2301 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
2309 <GIC_SPI 2302 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
2310 <GIC_SPI 2303 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
2311 <GIC_SPI 2304 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
2312 <GIC_SPI 2305 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
2313 <GIC_SPI 2306 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
2314 interrupt-names = "er 2307 interrupt-names = "error",
2315 "ch0" 2308 "ch0", "ch1", "ch2", "ch3",
2316 "ch4" 2309 "ch4", "ch5", "ch6", "ch7",
2317 "ch8" 2310 "ch8", "ch9", "ch10", "ch11",
2318 "ch12 2311 "ch12", "ch13", "ch14", "ch15";
2319 clocks = <&cpg CPG_MO 2312 clocks = <&cpg CPG_MOD 502>;
2320 clock-names = "fck"; 2313 clock-names = "fck";
2321 power-domains = <&sys 2314 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2322 resets = <&cpg 502>; 2315 resets = <&cpg 502>;
2323 #dma-cells = <1>; 2316 #dma-cells = <1>;
2324 dma-channels = <16>; 2317 dma-channels = <16>;
2325 iommus = <&ipmmu_mp 0 2318 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
2326 <&ipmmu_mp 2>, 2319 <&ipmmu_mp 2>, <&ipmmu_mp 3>,
2327 <&ipmmu_mp 4>, 2320 <&ipmmu_mp 4>, <&ipmmu_mp 5>,
2328 <&ipmmu_mp 6>, 2321 <&ipmmu_mp 6>, <&ipmmu_mp 7>,
2329 <&ipmmu_mp 8>, 2322 <&ipmmu_mp 8>, <&ipmmu_mp 9>,
2330 <&ipmmu_mp 10> 2323 <&ipmmu_mp 10>, <&ipmmu_mp 11>,
2331 <&ipmmu_mp 12> 2324 <&ipmmu_mp 12>, <&ipmmu_mp 13>,
2332 <&ipmmu_mp 14> 2325 <&ipmmu_mp 14>, <&ipmmu_mp 15>;
2333 }; 2326 };
2334 2327
2335 audma1: dma-controller@ec7200 2328 audma1: dma-controller@ec720000 {
2336 compatible = "renesas 2329 compatible = "renesas,dmac-r8a7796",
2337 "renesas 2330 "renesas,rcar-dmac";
2338 reg = <0 0xec720000 0 2331 reg = <0 0xec720000 0 0x10000>;
2339 interrupts = <GIC_SPI 2332 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
2340 <GIC_SPI 2333 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
2341 <GIC_SPI 2334 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
2342 <GIC_SPI 2335 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
2343 <GIC_SPI 2336 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
2344 <GIC_SPI 2337 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
2345 <GIC_SPI 2338 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
2346 <GIC_SPI 2339 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
2347 <GIC_SPI 2340 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
2348 <GIC_SPI 2341 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
2349 <GIC_SPI 2342 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
2350 <GIC_SPI 2343 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
2351 <GIC_SPI 2344 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
2352 <GIC_SPI 2345 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
2353 <GIC_SPI 2346 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
2354 <GIC_SPI 2347 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
2355 <GIC_SPI 2348 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
2356 interrupt-names = "er 2349 interrupt-names = "error",
2357 "ch0" 2350 "ch0", "ch1", "ch2", "ch3",
2358 "ch4" 2351 "ch4", "ch5", "ch6", "ch7",
2359 "ch8" 2352 "ch8", "ch9", "ch10", "ch11",
2360 "ch12 2353 "ch12", "ch13", "ch14", "ch15";
2361 clocks = <&cpg CPG_MO 2354 clocks = <&cpg CPG_MOD 501>;
2362 clock-names = "fck"; 2355 clock-names = "fck";
2363 power-domains = <&sys 2356 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2364 resets = <&cpg 501>; 2357 resets = <&cpg 501>;
2365 #dma-cells = <1>; 2358 #dma-cells = <1>;
2366 dma-channels = <16>; 2359 dma-channels = <16>;
2367 iommus = <&ipmmu_mp 1 2360 iommus = <&ipmmu_mp 16>, <&ipmmu_mp 17>,
2368 <&ipmmu_mp 18> 2361 <&ipmmu_mp 18>, <&ipmmu_mp 19>,
2369 <&ipmmu_mp 20> 2362 <&ipmmu_mp 20>, <&ipmmu_mp 21>,
2370 <&ipmmu_mp 22> 2363 <&ipmmu_mp 22>, <&ipmmu_mp 23>,
2371 <&ipmmu_mp 24> 2364 <&ipmmu_mp 24>, <&ipmmu_mp 25>,
2372 <&ipmmu_mp 26> 2365 <&ipmmu_mp 26>, <&ipmmu_mp 27>,
2373 <&ipmmu_mp 28> 2366 <&ipmmu_mp 28>, <&ipmmu_mp 29>,
2374 <&ipmmu_mp 30> 2367 <&ipmmu_mp 30>, <&ipmmu_mp 31>;
2375 }; 2368 };
2376 2369
2377 xhci0: usb@ee000000 { 2370 xhci0: usb@ee000000 {
2378 compatible = "renesas 2371 compatible = "renesas,xhci-r8a7796",
2379 "renesas 2372 "renesas,rcar-gen3-xhci";
2380 reg = <0 0xee000000 0 2373 reg = <0 0xee000000 0 0xc00>;
2381 interrupts = <GIC_SPI 2374 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
2382 clocks = <&cpg CPG_MO 2375 clocks = <&cpg CPG_MOD 328>;
2383 power-domains = <&sys 2376 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2384 resets = <&cpg 328>; 2377 resets = <&cpg 328>;
2385 status = "disabled"; 2378 status = "disabled";
2386 }; 2379 };
2387 2380
2388 usb3_peri0: usb@ee020000 { 2381 usb3_peri0: usb@ee020000 {
2389 compatible = "renesas 2382 compatible = "renesas,r8a7796-usb3-peri",
2390 "renesas 2383 "renesas,rcar-gen3-usb3-peri";
2391 reg = <0 0xee020000 0 2384 reg = <0 0xee020000 0 0x400>;
2392 interrupts = <GIC_SPI 2385 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
2393 clocks = <&cpg CPG_MO 2386 clocks = <&cpg CPG_MOD 328>;
2394 power-domains = <&sys 2387 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2395 resets = <&cpg 328>; 2388 resets = <&cpg 328>;
2396 status = "disabled"; 2389 status = "disabled";
2397 }; 2390 };
2398 2391
2399 ohci0: usb@ee080000 { 2392 ohci0: usb@ee080000 {
2400 compatible = "generic 2393 compatible = "generic-ohci";
2401 reg = <0 0xee080000 0 2394 reg = <0 0xee080000 0 0x100>;
2402 interrupts = <GIC_SPI 2395 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
2403 clocks = <&cpg CPG_MO 2396 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
2404 phys = <&usb2_phy0 1> 2397 phys = <&usb2_phy0 1>;
2405 phy-names = "usb"; 2398 phy-names = "usb";
2406 power-domains = <&sys 2399 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2407 resets = <&cpg 703>, 2400 resets = <&cpg 703>, <&cpg 704>;
2408 status = "disabled"; 2401 status = "disabled";
2409 }; 2402 };
2410 2403
2411 ohci1: usb@ee0a0000 { 2404 ohci1: usb@ee0a0000 {
2412 compatible = "generic 2405 compatible = "generic-ohci";
2413 reg = <0 0xee0a0000 0 2406 reg = <0 0xee0a0000 0 0x100>;
2414 interrupts = <GIC_SPI 2407 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
2415 clocks = <&cpg CPG_MO 2408 clocks = <&cpg CPG_MOD 702>;
2416 phys = <&usb2_phy1 1> 2409 phys = <&usb2_phy1 1>;
2417 phy-names = "usb"; 2410 phy-names = "usb";
2418 power-domains = <&sys 2411 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2419 resets = <&cpg 702>; 2412 resets = <&cpg 702>;
2420 status = "disabled"; 2413 status = "disabled";
2421 }; 2414 };
2422 2415
2423 ehci0: usb@ee080100 { 2416 ehci0: usb@ee080100 {
2424 compatible = "generic 2417 compatible = "generic-ehci";
2425 reg = <0 0xee080100 0 2418 reg = <0 0xee080100 0 0x100>;
2426 interrupts = <GIC_SPI 2419 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
2427 clocks = <&cpg CPG_MO 2420 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
2428 phys = <&usb2_phy0 2> 2421 phys = <&usb2_phy0 2>;
2429 phy-names = "usb"; 2422 phy-names = "usb";
2430 companion = <&ohci0>; 2423 companion = <&ohci0>;
2431 power-domains = <&sys 2424 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2432 resets = <&cpg 703>, 2425 resets = <&cpg 703>, <&cpg 704>;
2433 status = "disabled"; 2426 status = "disabled";
2434 }; 2427 };
2435 2428
2436 ehci1: usb@ee0a0100 { 2429 ehci1: usb@ee0a0100 {
2437 compatible = "generic 2430 compatible = "generic-ehci";
2438 reg = <0 0xee0a0100 0 2431 reg = <0 0xee0a0100 0 0x100>;
2439 interrupts = <GIC_SPI 2432 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
2440 clocks = <&cpg CPG_MO 2433 clocks = <&cpg CPG_MOD 702>;
2441 phys = <&usb2_phy1 2> 2434 phys = <&usb2_phy1 2>;
2442 phy-names = "usb"; 2435 phy-names = "usb";
2443 companion = <&ohci1>; 2436 companion = <&ohci1>;
2444 power-domains = <&sys 2437 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2445 resets = <&cpg 702>; 2438 resets = <&cpg 702>;
2446 status = "disabled"; 2439 status = "disabled";
2447 }; 2440 };
2448 2441
2449 usb2_phy0: usb-phy@ee080200 { 2442 usb2_phy0: usb-phy@ee080200 {
2450 compatible = "renesas 2443 compatible = "renesas,usb2-phy-r8a7796",
2451 "renesas 2444 "renesas,rcar-gen3-usb2-phy";
2452 reg = <0 0xee080200 0 2445 reg = <0 0xee080200 0 0x700>;
2453 interrupts = <GIC_SPI 2446 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
2454 clocks = <&cpg CPG_MO 2447 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
2455 power-domains = <&sys 2448 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2456 resets = <&cpg 703>, 2449 resets = <&cpg 703>, <&cpg 704>;
2457 #phy-cells = <1>; 2450 #phy-cells = <1>;
2458 status = "disabled"; 2451 status = "disabled";
2459 }; 2452 };
2460 2453
2461 usb2_phy1: usb-phy@ee0a0200 { 2454 usb2_phy1: usb-phy@ee0a0200 {
2462 compatible = "renesas 2455 compatible = "renesas,usb2-phy-r8a7796",
2463 "renesas 2456 "renesas,rcar-gen3-usb2-phy";
2464 reg = <0 0xee0a0200 0 2457 reg = <0 0xee0a0200 0 0x700>;
2465 clocks = <&cpg CPG_MO 2458 clocks = <&cpg CPG_MOD 702>;
2466 power-domains = <&sys 2459 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2467 resets = <&cpg 702>; 2460 resets = <&cpg 702>;
2468 #phy-cells = <1>; 2461 #phy-cells = <1>;
2469 status = "disabled"; 2462 status = "disabled";
2470 }; 2463 };
2471 2464
2472 sdhi0: mmc@ee100000 { 2465 sdhi0: mmc@ee100000 {
2473 compatible = "renesas 2466 compatible = "renesas,sdhi-r8a7796",
2474 "renesas 2467 "renesas,rcar-gen3-sdhi";
2475 reg = <0 0xee100000 0 2468 reg = <0 0xee100000 0 0x2000>;
2476 interrupts = <GIC_SPI 2469 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
2477 clocks = <&cpg CPG_MO !! 2470 clocks = <&cpg CPG_MOD 314>;
2478 clock-names = "core", <<
2479 max-frequency = <2000 2471 max-frequency = <200000000>;
2480 power-domains = <&sys 2472 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2481 resets = <&cpg 314>; 2473 resets = <&cpg 314>;
2482 iommus = <&ipmmu_ds1 2474 iommus = <&ipmmu_ds1 32>;
2483 status = "disabled"; 2475 status = "disabled";
2484 }; 2476 };
2485 2477
2486 sdhi1: mmc@ee120000 { 2478 sdhi1: mmc@ee120000 {
2487 compatible = "renesas 2479 compatible = "renesas,sdhi-r8a7796",
2488 "renesas 2480 "renesas,rcar-gen3-sdhi";
2489 reg = <0 0xee120000 0 2481 reg = <0 0xee120000 0 0x2000>;
2490 interrupts = <GIC_SPI 2482 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
2491 clocks = <&cpg CPG_MO !! 2483 clocks = <&cpg CPG_MOD 313>;
2492 clock-names = "core", <<
2493 max-frequency = <2000 2484 max-frequency = <200000000>;
2494 power-domains = <&sys 2485 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2495 resets = <&cpg 313>; 2486 resets = <&cpg 313>;
2496 iommus = <&ipmmu_ds1 2487 iommus = <&ipmmu_ds1 33>;
2497 status = "disabled"; 2488 status = "disabled";
2498 }; 2489 };
2499 2490
2500 sdhi2: mmc@ee140000 { 2491 sdhi2: mmc@ee140000 {
2501 compatible = "renesas 2492 compatible = "renesas,sdhi-r8a7796",
2502 "renesas 2493 "renesas,rcar-gen3-sdhi";
2503 reg = <0 0xee140000 0 2494 reg = <0 0xee140000 0 0x2000>;
2504 interrupts = <GIC_SPI 2495 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
2505 clocks = <&cpg CPG_MO !! 2496 clocks = <&cpg CPG_MOD 312>;
2506 clock-names = "core", <<
2507 max-frequency = <2000 2497 max-frequency = <200000000>;
2508 power-domains = <&sys 2498 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2509 resets = <&cpg 312>; 2499 resets = <&cpg 312>;
2510 iommus = <&ipmmu_ds1 2500 iommus = <&ipmmu_ds1 34>;
2511 status = "disabled"; 2501 status = "disabled";
2512 }; 2502 };
2513 2503
2514 sdhi3: mmc@ee160000 { 2504 sdhi3: mmc@ee160000 {
2515 compatible = "renesas 2505 compatible = "renesas,sdhi-r8a7796",
2516 "renesas 2506 "renesas,rcar-gen3-sdhi";
2517 reg = <0 0xee160000 0 2507 reg = <0 0xee160000 0 0x2000>;
2518 interrupts = <GIC_SPI 2508 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
2519 clocks = <&cpg CPG_MO !! 2509 clocks = <&cpg CPG_MOD 311>;
2520 clock-names = "core", <<
2521 max-frequency = <2000 2510 max-frequency = <200000000>;
2522 power-domains = <&sys 2511 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2523 resets = <&cpg 311>; 2512 resets = <&cpg 311>;
2524 iommus = <&ipmmu_ds1 2513 iommus = <&ipmmu_ds1 35>;
2525 status = "disabled"; 2514 status = "disabled";
2526 }; 2515 };
2527 2516
2528 rpc: spi@ee200000 { <<
2529 compatible = "renesas <<
2530 "renesas <<
2531 reg = <0 0xee200000 0 <<
2532 <0 0x08000000 0 <<
2533 <0 0xee208000 0 <<
2534 reg-names = "regs", " <<
2535 interrupts = <GIC_SPI <<
2536 clocks = <&cpg CPG_MO <<
2537 power-domains = <&sys <<
2538 resets = <&cpg 917>; <<
2539 #address-cells = <1>; <<
2540 #size-cells = <0>; <<
2541 status = "disabled"; <<
2542 }; <<
2543 <<
2544 gic: interrupt-controller@f10 2517 gic: interrupt-controller@f1010000 {
2545 compatible = "arm,gic 2518 compatible = "arm,gic-400";
2546 #interrupt-cells = <3 2519 #interrupt-cells = <3>;
2547 #address-cells = <0>; 2520 #address-cells = <0>;
2548 interrupt-controller; 2521 interrupt-controller;
2549 reg = <0x0 0xf1010000 2522 reg = <0x0 0xf1010000 0 0x1000>,
2550 <0x0 0xf1020000 2523 <0x0 0xf1020000 0 0x20000>,
2551 <0x0 0xf1040000 2524 <0x0 0xf1040000 0 0x20000>,
2552 <0x0 0xf1060000 2525 <0x0 0xf1060000 0 0x20000>;
2553 interrupts = <GIC_PPI 2526 interrupts = <GIC_PPI 9
2554 (GIC_ 2527 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
2555 clocks = <&cpg CPG_MO 2528 clocks = <&cpg CPG_MOD 408>;
2556 clock-names = "clk"; 2529 clock-names = "clk";
2557 power-domains = <&sys 2530 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2558 resets = <&cpg 408>; 2531 resets = <&cpg 408>;
2559 }; 2532 };
2560 2533
2561 pciec0: pcie@fe000000 { 2534 pciec0: pcie@fe000000 {
2562 compatible = "renesas 2535 compatible = "renesas,pcie-r8a7796",
2563 "renesas 2536 "renesas,pcie-rcar-gen3";
2564 reg = <0 0xfe000000 0 2537 reg = <0 0xfe000000 0 0x80000>;
2565 #address-cells = <3>; 2538 #address-cells = <3>;
2566 #size-cells = <2>; 2539 #size-cells = <2>;
2567 bus-range = <0x00 0xf 2540 bus-range = <0x00 0xff>;
2568 device_type = "pci"; 2541 device_type = "pci";
2569 ranges = <0x01000000 2542 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
2570 <0x02000000 2543 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
2571 <0x02000000 2544 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
2572 <0x42000000 2545 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
2573 /* Map all possible D !! 2546 /* Map all possible DDR as inbound ranges */
2574 dma-ranges = <0x42000 !! 2547 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
2575 interrupts = <GIC_SPI 2548 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
2576 <GIC_SPI 117 2549 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
2577 <GIC_SPI 118 2550 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
2578 #interrupt-cells = <1 2551 #interrupt-cells = <1>;
2579 interrupt-map-mask = 2552 interrupt-map-mask = <0 0 0 0>;
2580 interrupt-map = <0 0 2553 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
2581 clocks = <&cpg CPG_MO 2554 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
2582 clock-names = "pcie", 2555 clock-names = "pcie", "pcie_bus";
2583 power-domains = <&sys 2556 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2584 resets = <&cpg 319>; 2557 resets = <&cpg 319>;
2585 iommu-map = <0 &ipmmu <<
2586 iommu-map-mask = <0>; <<
2587 status = "disabled"; 2558 status = "disabled";
2588 }; 2559 };
2589 2560
2590 pciec1: pcie@ee800000 { 2561 pciec1: pcie@ee800000 {
2591 compatible = "renesas 2562 compatible = "renesas,pcie-r8a7796",
2592 "renesas 2563 "renesas,pcie-rcar-gen3";
2593 reg = <0 0xee800000 0 2564 reg = <0 0xee800000 0 0x80000>;
2594 #address-cells = <3>; 2565 #address-cells = <3>;
2595 #size-cells = <2>; 2566 #size-cells = <2>;
2596 bus-range = <0x00 0xf 2567 bus-range = <0x00 0xff>;
2597 device_type = "pci"; 2568 device_type = "pci";
2598 ranges = <0x01000000 2569 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
2599 <0x02000000 2570 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
2600 <0x02000000 2571 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
2601 <0x42000000 2572 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
2602 /* Map all possible D !! 2573 /* Map all possible DDR as inbound ranges */
2603 dma-ranges = <0x42000 !! 2574 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
2604 interrupts = <GIC_SPI 2575 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
2605 <GIC_SPI 149 2576 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
2606 <GIC_SPI 150 2577 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
2607 #interrupt-cells = <1 2578 #interrupt-cells = <1>;
2608 interrupt-map-mask = 2579 interrupt-map-mask = <0 0 0 0>;
2609 interrupt-map = <0 0 2580 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2610 clocks = <&cpg CPG_MO 2581 clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>;
2611 clock-names = "pcie", 2582 clock-names = "pcie", "pcie_bus";
2612 power-domains = <&sys 2583 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2613 resets = <&cpg 318>; 2584 resets = <&cpg 318>;
2614 iommu-map = <0 &ipmmu <<
2615 iommu-map-mask = <0>; <<
2616 status = "disabled"; 2585 status = "disabled";
2617 }; 2586 };
2618 2587
2619 imr-lx4@fe860000 { 2588 imr-lx4@fe860000 {
2620 compatible = "renesas 2589 compatible = "renesas,r8a7796-imr-lx4",
2621 "renesas 2590 "renesas,imr-lx4";
2622 reg = <0 0xfe860000 0 2591 reg = <0 0xfe860000 0 0x2000>;
2623 interrupts = <GIC_SPI 2592 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
2624 clocks = <&cpg CPG_MO 2593 clocks = <&cpg CPG_MOD 823>;
2625 power-domains = <&sys 2594 power-domains = <&sysc R8A7796_PD_A3VC>;
2626 resets = <&cpg 823>; 2595 resets = <&cpg 823>;
2627 }; 2596 };
2628 2597
2629 imr-lx4@fe870000 { 2598 imr-lx4@fe870000 {
2630 compatible = "renesas 2599 compatible = "renesas,r8a7796-imr-lx4",
2631 "renesas 2600 "renesas,imr-lx4";
2632 reg = <0 0xfe870000 0 2601 reg = <0 0xfe870000 0 0x2000>;
2633 interrupts = <GIC_SPI 2602 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
2634 clocks = <&cpg CPG_MO 2603 clocks = <&cpg CPG_MOD 822>;
2635 power-domains = <&sys 2604 power-domains = <&sysc R8A7796_PD_A3VC>;
2636 resets = <&cpg 822>; 2605 resets = <&cpg 822>;
2637 }; 2606 };
2638 2607
2639 fdp1@fe940000 { 2608 fdp1@fe940000 {
2640 compatible = "renesas 2609 compatible = "renesas,fdp1";
2641 reg = <0 0xfe940000 0 2610 reg = <0 0xfe940000 0 0x2400>;
2642 interrupts = <GIC_SPI 2611 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
2643 clocks = <&cpg CPG_MO 2612 clocks = <&cpg CPG_MOD 119>;
2644 power-domains = <&sys 2613 power-domains = <&sysc R8A7796_PD_A3VC>;
2645 resets = <&cpg 119>; 2614 resets = <&cpg 119>;
2646 renesas,fcp = <&fcpf0 2615 renesas,fcp = <&fcpf0>;
2647 }; 2616 };
2648 2617
2649 fcpf0: fcp@fe950000 { 2618 fcpf0: fcp@fe950000 {
2650 compatible = "renesas 2619 compatible = "renesas,fcpf";
2651 reg = <0 0xfe950000 0 2620 reg = <0 0xfe950000 0 0x200>;
2652 clocks = <&cpg CPG_MO 2621 clocks = <&cpg CPG_MOD 615>;
2653 power-domains = <&sys 2622 power-domains = <&sysc R8A7796_PD_A3VC>;
2654 resets = <&cpg 615>; 2623 resets = <&cpg 615>;
2655 iommus = <&ipmmu_vc0 <<
2656 }; 2624 };
2657 2625
2658 fcpvb0: fcp@fe96f000 { 2626 fcpvb0: fcp@fe96f000 {
2659 compatible = "renesas 2627 compatible = "renesas,fcpv";
2660 reg = <0 0xfe96f000 0 2628 reg = <0 0xfe96f000 0 0x200>;
2661 clocks = <&cpg CPG_MO 2629 clocks = <&cpg CPG_MOD 607>;
2662 power-domains = <&sys 2630 power-domains = <&sysc R8A7796_PD_A3VC>;
2663 resets = <&cpg 607>; 2631 resets = <&cpg 607>;
2664 iommus = <&ipmmu_vi0 <<
2665 }; 2632 };
2666 2633
2667 fcpvi0: fcp@fe9af000 { 2634 fcpvi0: fcp@fe9af000 {
2668 compatible = "renesas 2635 compatible = "renesas,fcpv";
2669 reg = <0 0xfe9af000 0 2636 reg = <0 0xfe9af000 0 0x200>;
2670 clocks = <&cpg CPG_MO 2637 clocks = <&cpg CPG_MOD 611>;
2671 power-domains = <&sys 2638 power-domains = <&sysc R8A7796_PD_A3VC>;
2672 resets = <&cpg 611>; 2639 resets = <&cpg 611>;
2673 iommus = <&ipmmu_vc0 2640 iommus = <&ipmmu_vc0 19>;
2674 }; 2641 };
2675 2642
2676 fcpvd0: fcp@fea27000 { 2643 fcpvd0: fcp@fea27000 {
2677 compatible = "renesas 2644 compatible = "renesas,fcpv";
2678 reg = <0 0xfea27000 0 2645 reg = <0 0xfea27000 0 0x200>;
2679 clocks = <&cpg CPG_MO 2646 clocks = <&cpg CPG_MOD 603>;
2680 power-domains = <&sys 2647 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2681 resets = <&cpg 603>; 2648 resets = <&cpg 603>;
2682 iommus = <&ipmmu_vi0 2649 iommus = <&ipmmu_vi0 8>;
2683 }; 2650 };
2684 2651
2685 fcpvd1: fcp@fea2f000 { 2652 fcpvd1: fcp@fea2f000 {
2686 compatible = "renesas 2653 compatible = "renesas,fcpv";
2687 reg = <0 0xfea2f000 0 2654 reg = <0 0xfea2f000 0 0x200>;
2688 clocks = <&cpg CPG_MO 2655 clocks = <&cpg CPG_MOD 602>;
2689 power-domains = <&sys 2656 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2690 resets = <&cpg 602>; 2657 resets = <&cpg 602>;
2691 iommus = <&ipmmu_vi0 2658 iommus = <&ipmmu_vi0 9>;
2692 }; 2659 };
2693 2660
2694 fcpvd2: fcp@fea37000 { 2661 fcpvd2: fcp@fea37000 {
2695 compatible = "renesas 2662 compatible = "renesas,fcpv";
2696 reg = <0 0xfea37000 0 2663 reg = <0 0xfea37000 0 0x200>;
2697 clocks = <&cpg CPG_MO 2664 clocks = <&cpg CPG_MOD 601>;
2698 power-domains = <&sys 2665 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2699 resets = <&cpg 601>; 2666 resets = <&cpg 601>;
2700 iommus = <&ipmmu_vi0 2667 iommus = <&ipmmu_vi0 10>;
2701 }; 2668 };
2702 2669
2703 vspb: vsp@fe960000 { 2670 vspb: vsp@fe960000 {
2704 compatible = "renesas 2671 compatible = "renesas,vsp2";
2705 reg = <0 0xfe960000 0 2672 reg = <0 0xfe960000 0 0x8000>;
2706 interrupts = <GIC_SPI 2673 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
2707 clocks = <&cpg CPG_MO 2674 clocks = <&cpg CPG_MOD 626>;
2708 power-domains = <&sys 2675 power-domains = <&sysc R8A7796_PD_A3VC>;
2709 resets = <&cpg 626>; 2676 resets = <&cpg 626>;
2710 2677
2711 renesas,fcp = <&fcpvb 2678 renesas,fcp = <&fcpvb0>;
2712 }; 2679 };
2713 2680
2714 vspd0: vsp@fea20000 { 2681 vspd0: vsp@fea20000 {
2715 compatible = "renesas 2682 compatible = "renesas,vsp2";
2716 reg = <0 0xfea20000 0 2683 reg = <0 0xfea20000 0 0x5000>;
2717 interrupts = <GIC_SPI 2684 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
2718 clocks = <&cpg CPG_MO 2685 clocks = <&cpg CPG_MOD 623>;
2719 power-domains = <&sys 2686 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2720 resets = <&cpg 623>; 2687 resets = <&cpg 623>;
2721 2688
2722 renesas,fcp = <&fcpvd 2689 renesas,fcp = <&fcpvd0>;
2723 }; 2690 };
2724 2691
2725 vspd1: vsp@fea28000 { 2692 vspd1: vsp@fea28000 {
2726 compatible = "renesas 2693 compatible = "renesas,vsp2";
2727 reg = <0 0xfea28000 0 2694 reg = <0 0xfea28000 0 0x5000>;
2728 interrupts = <GIC_SPI 2695 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
2729 clocks = <&cpg CPG_MO 2696 clocks = <&cpg CPG_MOD 622>;
2730 power-domains = <&sys 2697 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2731 resets = <&cpg 622>; 2698 resets = <&cpg 622>;
2732 2699
2733 renesas,fcp = <&fcpvd 2700 renesas,fcp = <&fcpvd1>;
2734 }; 2701 };
2735 2702
2736 vspd2: vsp@fea30000 { 2703 vspd2: vsp@fea30000 {
2737 compatible = "renesas 2704 compatible = "renesas,vsp2";
2738 reg = <0 0xfea30000 0 2705 reg = <0 0xfea30000 0 0x5000>;
2739 interrupts = <GIC_SPI 2706 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
2740 clocks = <&cpg CPG_MO 2707 clocks = <&cpg CPG_MOD 621>;
2741 power-domains = <&sys 2708 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2742 resets = <&cpg 621>; 2709 resets = <&cpg 621>;
2743 2710
2744 renesas,fcp = <&fcpvd 2711 renesas,fcp = <&fcpvd2>;
2745 }; 2712 };
2746 2713
2747 vspi0: vsp@fe9a0000 { 2714 vspi0: vsp@fe9a0000 {
2748 compatible = "renesas 2715 compatible = "renesas,vsp2";
2749 reg = <0 0xfe9a0000 0 2716 reg = <0 0xfe9a0000 0 0x8000>;
2750 interrupts = <GIC_SPI 2717 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
2751 clocks = <&cpg CPG_MO 2718 clocks = <&cpg CPG_MOD 631>;
2752 power-domains = <&sys 2719 power-domains = <&sysc R8A7796_PD_A3VC>;
2753 resets = <&cpg 631>; 2720 resets = <&cpg 631>;
2754 2721
2755 renesas,fcp = <&fcpvi 2722 renesas,fcp = <&fcpvi0>;
2756 }; 2723 };
2757 2724
2758 cmm0: cmm@fea40000 { 2725 cmm0: cmm@fea40000 {
2759 compatible = "renesas 2726 compatible = "renesas,r8a7796-cmm",
2760 "renesas 2727 "renesas,rcar-gen3-cmm";
2761 reg = <0 0xfea40000 0 2728 reg = <0 0xfea40000 0 0x1000>;
2762 power-domains = <&sys 2729 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2763 clocks = <&cpg CPG_MO 2730 clocks = <&cpg CPG_MOD 711>;
2764 resets = <&cpg 711>; 2731 resets = <&cpg 711>;
2765 }; 2732 };
2766 2733
2767 cmm1: cmm@fea50000 { 2734 cmm1: cmm@fea50000 {
2768 compatible = "renesas 2735 compatible = "renesas,r8a7796-cmm",
2769 "renesas 2736 "renesas,rcar-gen3-cmm";
2770 reg = <0 0xfea50000 0 2737 reg = <0 0xfea50000 0 0x1000>;
2771 power-domains = <&sys 2738 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2772 clocks = <&cpg CPG_MO 2739 clocks = <&cpg CPG_MOD 710>;
2773 resets = <&cpg 710>; 2740 resets = <&cpg 710>;
2774 }; 2741 };
2775 2742
2776 cmm2: cmm@fea60000 { 2743 cmm2: cmm@fea60000 {
2777 compatible = "renesas 2744 compatible = "renesas,r8a7796-cmm",
2778 "renesas 2745 "renesas,rcar-gen3-cmm";
2779 reg = <0 0xfea60000 0 2746 reg = <0 0xfea60000 0 0x1000>;
2780 power-domains = <&sys 2747 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2781 clocks = <&cpg CPG_MO 2748 clocks = <&cpg CPG_MOD 709>;
2782 resets = <&cpg 709>; 2749 resets = <&cpg 709>;
2783 }; 2750 };
2784 2751
2785 csi20: csi2@fea80000 { 2752 csi20: csi2@fea80000 {
2786 compatible = "renesas 2753 compatible = "renesas,r8a7796-csi2";
2787 reg = <0 0xfea80000 0 2754 reg = <0 0xfea80000 0 0x10000>;
2788 interrupts = <GIC_SPI 2755 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
2789 clocks = <&cpg CPG_MO 2756 clocks = <&cpg CPG_MOD 714>;
2790 power-domains = <&sys 2757 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2791 resets = <&cpg 714>; 2758 resets = <&cpg 714>;
2792 status = "disabled"; 2759 status = "disabled";
2793 2760
2794 ports { 2761 ports {
2795 #address-cell 2762 #address-cells = <1>;
2796 #size-cells = 2763 #size-cells = <0>;
2797 2764
2798 port@0 { <<
2799 reg = <<
2800 }; <<
2801 <<
2802 port@1 { 2765 port@1 {
2803 #addr 2766 #address-cells = <1>;
2804 #size 2767 #size-cells = <0>;
2805 2768
2806 reg = 2769 reg = <1>;
2807 2770
2808 csi20 2771 csi20vin0: endpoint@0 {
2809 2772 reg = <0>;
2810 2773 remote-endpoint = <&vin0csi20>;
2811 }; 2774 };
2812 csi20 2775 csi20vin1: endpoint@1 {
2813 2776 reg = <1>;
2814 2777 remote-endpoint = <&vin1csi20>;
2815 }; 2778 };
2816 csi20 2779 csi20vin2: endpoint@2 {
2817 2780 reg = <2>;
2818 2781 remote-endpoint = <&vin2csi20>;
2819 }; 2782 };
2820 csi20 2783 csi20vin3: endpoint@3 {
2821 2784 reg = <3>;
2822 2785 remote-endpoint = <&vin3csi20>;
2823 }; 2786 };
2824 csi20 2787 csi20vin4: endpoint@4 {
2825 2788 reg = <4>;
2826 2789 remote-endpoint = <&vin4csi20>;
2827 }; 2790 };
2828 csi20 2791 csi20vin5: endpoint@5 {
2829 2792 reg = <5>;
2830 2793 remote-endpoint = <&vin5csi20>;
2831 }; 2794 };
2832 csi20 2795 csi20vin6: endpoint@6 {
2833 2796 reg = <6>;
2834 2797 remote-endpoint = <&vin6csi20>;
2835 }; 2798 };
2836 csi20 2799 csi20vin7: endpoint@7 {
2837 2800 reg = <7>;
2838 2801 remote-endpoint = <&vin7csi20>;
2839 }; 2802 };
2840 }; 2803 };
2841 }; 2804 };
2842 }; 2805 };
2843 2806
2844 csi40: csi2@feaa0000 { 2807 csi40: csi2@feaa0000 {
2845 compatible = "renesas 2808 compatible = "renesas,r8a7796-csi2";
2846 reg = <0 0xfeaa0000 0 2809 reg = <0 0xfeaa0000 0 0x10000>;
2847 interrupts = <GIC_SPI 2810 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
2848 clocks = <&cpg CPG_MO 2811 clocks = <&cpg CPG_MOD 716>;
2849 power-domains = <&sys 2812 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2850 resets = <&cpg 716>; 2813 resets = <&cpg 716>;
2851 status = "disabled"; 2814 status = "disabled";
2852 2815
2853 ports { 2816 ports {
2854 #address-cell 2817 #address-cells = <1>;
2855 #size-cells = 2818 #size-cells = <0>;
2856 2819
2857 port@0 { <<
2858 reg = <<
2859 }; <<
2860 <<
2861 port@1 { 2820 port@1 {
2862 #addr 2821 #address-cells = <1>;
2863 #size 2822 #size-cells = <0>;
2864 2823
2865 reg = 2824 reg = <1>;
2866 2825
2867 csi40 2826 csi40vin0: endpoint@0 {
2868 2827 reg = <0>;
2869 2828 remote-endpoint = <&vin0csi40>;
2870 }; 2829 };
2871 csi40 2830 csi40vin1: endpoint@1 {
2872 2831 reg = <1>;
2873 2832 remote-endpoint = <&vin1csi40>;
2874 }; 2833 };
2875 csi40 2834 csi40vin2: endpoint@2 {
2876 2835 reg = <2>;
2877 2836 remote-endpoint = <&vin2csi40>;
2878 }; 2837 };
2879 csi40 2838 csi40vin3: endpoint@3 {
2880 2839 reg = <3>;
2881 2840 remote-endpoint = <&vin3csi40>;
2882 }; 2841 };
2883 csi40 2842 csi40vin4: endpoint@4 {
2884 2843 reg = <4>;
2885 2844 remote-endpoint = <&vin4csi40>;
2886 }; 2845 };
2887 csi40 2846 csi40vin5: endpoint@5 {
2888 2847 reg = <5>;
2889 2848 remote-endpoint = <&vin5csi40>;
2890 }; 2849 };
2891 csi40 2850 csi40vin6: endpoint@6 {
2892 2851 reg = <6>;
2893 2852 remote-endpoint = <&vin6csi40>;
2894 }; 2853 };
2895 csi40 2854 csi40vin7: endpoint@7 {
2896 2855 reg = <7>;
2897 2856 remote-endpoint = <&vin7csi40>;
2898 }; 2857 };
2899 }; 2858 };
2900 2859
2901 }; 2860 };
2902 }; 2861 };
2903 2862
2904 hdmi0: hdmi@fead0000 { 2863 hdmi0: hdmi@fead0000 {
2905 compatible = "renesas 2864 compatible = "renesas,r8a7796-hdmi", "renesas,rcar-gen3-hdmi";
2906 reg = <0 0xfead0000 0 2865 reg = <0 0xfead0000 0 0x10000>;
2907 interrupts = <GIC_SPI 2866 interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
2908 clocks = <&cpg CPG_MO 2867 clocks = <&cpg CPG_MOD 729>, <&cpg CPG_CORE R8A7796_CLK_HDMI>;
2909 clock-names = "iahb", 2868 clock-names = "iahb", "isfr";
2910 power-domains = <&sys 2869 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2911 resets = <&cpg 729>; 2870 resets = <&cpg 729>;
2912 status = "disabled"; 2871 status = "disabled";
2913 2872
2914 ports { 2873 ports {
2915 #address-cell 2874 #address-cells = <1>;
2916 #size-cells = 2875 #size-cells = <0>;
2917 port@0 { 2876 port@0 {
2918 reg = 2877 reg = <0>;
2919 dw_hd 2878 dw_hdmi0_in: endpoint {
2920 2879 remote-endpoint = <&du_out_hdmi0>;
2921 }; 2880 };
2922 }; 2881 };
2923 port@1 { 2882 port@1 {
2924 reg = 2883 reg = <1>;
2925 }; 2884 };
2926 port@2 { 2885 port@2 {
2927 /* HD 2886 /* HDMI sound */
2928 reg = 2887 reg = <2>;
2929 }; 2888 };
2930 }; 2889 };
2931 }; 2890 };
2932 2891
2933 du: display@feb00000 { 2892 du: display@feb00000 {
2934 compatible = "renesas 2893 compatible = "renesas,du-r8a7796";
2935 reg = <0 0xfeb00000 0 2894 reg = <0 0xfeb00000 0 0x70000>;
2936 interrupts = <GIC_SPI 2895 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
2937 <GIC_SPI 2896 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
2938 <GIC_SPI 2897 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
2939 clocks = <&cpg CPG_MO 2898 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
2940 <&cpg CPG_MO 2899 <&cpg CPG_MOD 722>;
2941 clock-names = "du.0", 2900 clock-names = "du.0", "du.1", "du.2";
2942 resets = <&cpg 724>, 2901 resets = <&cpg 724>, <&cpg 722>;
2943 reset-names = "du.0", 2902 reset-names = "du.0", "du.2";
2944 2903
2945 renesas,cmms = <&cmm0 2904 renesas,cmms = <&cmm0>, <&cmm1>, <&cmm2>;
2946 renesas,vsps = <&vspd 2905 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>;
2947 2906
2948 status = "disabled"; 2907 status = "disabled";
2949 2908
2950 ports { 2909 ports {
2951 #address-cell 2910 #address-cells = <1>;
2952 #size-cells = 2911 #size-cells = <0>;
2953 2912
2954 port@0 { 2913 port@0 {
2955 reg = 2914 reg = <0>;
>> 2915 du_out_rgb: endpoint {
>> 2916 };
2956 }; 2917 };
2957 port@1 { 2918 port@1 {
2958 reg = 2919 reg = <1>;
2959 du_ou 2920 du_out_hdmi0: endpoint {
2960 2921 remote-endpoint = <&dw_hdmi0_in>;
2961 }; 2922 };
2962 }; 2923 };
2963 port@2 { 2924 port@2 {
2964 reg = 2925 reg = <2>;
2965 du_ou 2926 du_out_lvds0: endpoint {
2966 2927 remote-endpoint = <&lvds0_in>;
2967 }; 2928 };
2968 }; 2929 };
2969 }; 2930 };
2970 }; 2931 };
2971 2932
2972 lvds0: lvds@feb90000 { 2933 lvds0: lvds@feb90000 {
2973 compatible = "renesas 2934 compatible = "renesas,r8a7796-lvds";
2974 reg = <0 0xfeb90000 0 2935 reg = <0 0xfeb90000 0 0x14>;
2975 clocks = <&cpg CPG_MO 2936 clocks = <&cpg CPG_MOD 727>;
2976 power-domains = <&sys 2937 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2977 resets = <&cpg 727>; 2938 resets = <&cpg 727>;
2978 status = "disabled"; 2939 status = "disabled";
2979 2940
2980 ports { 2941 ports {
2981 #address-cell 2942 #address-cells = <1>;
2982 #size-cells = 2943 #size-cells = <0>;
2983 2944
2984 port@0 { 2945 port@0 {
2985 reg = 2946 reg = <0>;
2986 lvds0 2947 lvds0_in: endpoint {
2987 2948 remote-endpoint = <&du_out_lvds0>;
2988 }; 2949 };
2989 }; 2950 };
2990 port@1 { 2951 port@1 {
2991 reg = 2952 reg = <1>;
>> 2953 lvds0_out: endpoint {
>> 2954 };
2992 }; 2955 };
2993 }; 2956 };
2994 }; 2957 };
2995 2958
2996 prr: chipid@fff00044 { 2959 prr: chipid@fff00044 {
2997 compatible = "renesas 2960 compatible = "renesas,prr";
2998 reg = <0 0xfff00044 0 2961 reg = <0 0xfff00044 0 4>;
2999 }; 2962 };
3000 }; 2963 };
3001 2964
3002 thermal-zones { 2965 thermal-zones {
3003 sensor1_thermal: sensor1-ther !! 2966 sensor_thermal1: sensor-thermal1 {
3004 polling-delay-passive 2967 polling-delay-passive = <250>;
3005 polling-delay = <1000 2968 polling-delay = <1000>;
3006 thermal-sensors = <&t 2969 thermal-sensors = <&tsc 0>;
3007 sustainable-power = < 2970 sustainable-power = <3874>;
3008 2971
3009 trips { 2972 trips {
3010 sensor1_crit: 2973 sensor1_crit: sensor1-crit {
3011 tempe 2974 temperature = <120000>;
3012 hyste 2975 hysteresis = <1000>;
3013 type 2976 type = "critical";
3014 }; 2977 };
3015 }; 2978 };
3016 }; 2979 };
3017 2980
3018 sensor2_thermal: sensor2-ther !! 2981 sensor_thermal2: sensor-thermal2 {
3019 polling-delay-passive 2982 polling-delay-passive = <250>;
3020 polling-delay = <1000 2983 polling-delay = <1000>;
3021 thermal-sensors = <&t 2984 thermal-sensors = <&tsc 1>;
3022 sustainable-power = < 2985 sustainable-power = <3874>;
3023 2986
3024 trips { 2987 trips {
3025 sensor2_crit: 2988 sensor2_crit: sensor2-crit {
3026 tempe 2989 temperature = <120000>;
3027 hyste 2990 hysteresis = <1000>;
3028 type 2991 type = "critical";
3029 }; 2992 };
3030 }; 2993 };
3031 }; 2994 };
3032 2995
3033 sensor3_thermal: sensor3-ther !! 2996 sensor_thermal3: sensor-thermal3 {
3034 polling-delay-passive 2997 polling-delay-passive = <250>;
3035 polling-delay = <1000 2998 polling-delay = <1000>;
3036 thermal-sensors = <&t 2999 thermal-sensors = <&tsc 2>;
3037 sustainable-power = < 3000 sustainable-power = <3874>;
3038 3001
3039 cooling-maps { 3002 cooling-maps {
3040 map0 { 3003 map0 {
3041 trip 3004 trip = <&target>;
3042 cooli 3005 cooling-device = <&a57_0 2 4>;
3043 contr 3006 contribution = <1024>;
3044 }; 3007 };
3045 map1 { 3008 map1 {
3046 trip 3009 trip = <&target>;
3047 cooli 3010 cooling-device = <&a53_0 0 2>;
3048 contr 3011 contribution = <1024>;
3049 }; 3012 };
3050 }; 3013 };
3051 trips { 3014 trips {
3052 target: trip- 3015 target: trip-point1 {
3053 tempe 3016 temperature = <100000>;
3054 hyste 3017 hysteresis = <1000>;
3055 type 3018 type = "passive";
3056 }; 3019 };
3057 3020
3058 sensor3_crit: 3021 sensor3_crit: sensor3-crit {
3059 tempe 3022 temperature = <120000>;
3060 hyste 3023 hysteresis = <1000>;
3061 type 3024 type = "critical";
3062 }; 3025 };
3063 }; 3026 };
3064 }; 3027 };
3065 }; 3028 };
3066 3029
3067 timer { 3030 timer {
3068 compatible = "arm,armv8-timer 3031 compatible = "arm,armv8-timer";
3069 interrupts-extended = <&gic G 3032 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
3070 <&gic G 3033 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
3071 <&gic G 3034 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
3072 <&gic G 3035 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
3073 interrupt-names = "sec-phys", <<
3074 }; 3036 };
3075 3037
3076 /* External USB clocks - can be overr 3038 /* External USB clocks - can be overridden by the board */
3077 usb3s0_clk: usb3s0 { 3039 usb3s0_clk: usb3s0 {
3078 compatible = "fixed-clock"; 3040 compatible = "fixed-clock";
3079 #clock-cells = <0>; 3041 #clock-cells = <0>;
3080 clock-frequency = <0>; 3042 clock-frequency = <0>;
3081 }; 3043 };
3082 3044
3083 usb_extal_clk: usb_extal { 3045 usb_extal_clk: usb_extal {
3084 compatible = "fixed-clock"; 3046 compatible = "fixed-clock";
3085 #clock-cells = <0>; 3047 #clock-cells = <0>;
3086 clock-frequency = <0>; 3048 clock-frequency = <0>;
3087 }; 3049 };
3088 }; 3050 };
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