1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * Device Tree Source for the R-Car M3-W (R8A7 3 * Device Tree Source for the R-Car M3-W (R8A77960) SoC
4 * 4 *
5 * Copyright (C) 2016-2017 Renesas Electronics 5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
6 */ 6 */
7 7
8 #include <dt-bindings/clock/r8a7796-cpg-mssr.h 8 #include <dt-bindings/clock/r8a7796-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm 9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a7796-sysc.h> 10 #include <dt-bindings/power/r8a7796-sysc.h>
11 11
>> 12 #define CPG_AUDIO_CLK_I R8A7796_CLK_S0D4
>> 13
12 / { 14 / {
13 compatible = "renesas,r8a7796"; 15 compatible = "renesas,r8a7796";
14 #address-cells = <2>; 16 #address-cells = <2>;
15 #size-cells = <2>; 17 #size-cells = <2>;
16 18
>> 19 aliases {
>> 20 i2c0 = &i2c0;
>> 21 i2c1 = &i2c1;
>> 22 i2c2 = &i2c2;
>> 23 i2c3 = &i2c3;
>> 24 i2c4 = &i2c4;
>> 25 i2c5 = &i2c5;
>> 26 i2c6 = &i2c6;
>> 27 i2c7 = &i2c_dvfs;
>> 28 };
>> 29
17 /* 30 /*
18 * The external audio clocks are confi 31 * The external audio clocks are configured as 0 Hz fixed frequency
19 * clocks by default. 32 * clocks by default.
20 * Boards that provide audio clocks sh 33 * Boards that provide audio clocks should override them.
21 */ 34 */
22 audio_clk_a: audio_clk_a { 35 audio_clk_a: audio_clk_a {
23 compatible = "fixed-clock"; 36 compatible = "fixed-clock";
24 #clock-cells = <0>; 37 #clock-cells = <0>;
25 clock-frequency = <0>; 38 clock-frequency = <0>;
26 }; 39 };
27 40
28 audio_clk_b: audio_clk_b { 41 audio_clk_b: audio_clk_b {
29 compatible = "fixed-clock"; 42 compatible = "fixed-clock";
30 #clock-cells = <0>; 43 #clock-cells = <0>;
31 clock-frequency = <0>; 44 clock-frequency = <0>;
32 }; 45 };
33 46
34 audio_clk_c: audio_clk_c { 47 audio_clk_c: audio_clk_c {
35 compatible = "fixed-clock"; 48 compatible = "fixed-clock";
36 #clock-cells = <0>; 49 #clock-cells = <0>;
37 clock-frequency = <0>; 50 clock-frequency = <0>;
38 }; 51 };
39 52
40 /* External CAN clock - to be overridd 53 /* External CAN clock - to be overridden by boards that provide it */
41 can_clk: can { 54 can_clk: can {
42 compatible = "fixed-clock"; 55 compatible = "fixed-clock";
43 #clock-cells = <0>; 56 #clock-cells = <0>;
44 clock-frequency = <0>; 57 clock-frequency = <0>;
45 }; 58 };
46 59
47 cluster0_opp: opp-table-0 { !! 60 cluster0_opp: opp_table0 {
48 compatible = "operating-points 61 compatible = "operating-points-v2";
49 opp-shared; 62 opp-shared;
50 63
51 opp-500000000 { 64 opp-500000000 {
52 opp-hz = /bits/ 64 <50 65 opp-hz = /bits/ 64 <500000000>;
53 opp-microvolt = <83000 !! 66 opp-microvolt = <820000>;
54 clock-latency-ns = <30 67 clock-latency-ns = <300000>;
55 }; 68 };
56 opp-1000000000 { 69 opp-1000000000 {
57 opp-hz = /bits/ 64 <10 70 opp-hz = /bits/ 64 <1000000000>;
58 opp-microvolt = <83000 !! 71 opp-microvolt = <820000>;
59 clock-latency-ns = <30 72 clock-latency-ns = <300000>;
60 }; 73 };
61 opp-1500000000 { 74 opp-1500000000 {
62 opp-hz = /bits/ 64 <15 75 opp-hz = /bits/ 64 <1500000000>;
63 opp-microvolt = <83000 !! 76 opp-microvolt = <820000>;
64 clock-latency-ns = <30 77 clock-latency-ns = <300000>;
65 opp-suspend; <<
66 }; 78 };
67 opp-1600000000 { 79 opp-1600000000 {
68 opp-hz = /bits/ 64 <16 80 opp-hz = /bits/ 64 <1600000000>;
69 opp-microvolt = <90000 81 opp-microvolt = <900000>;
70 clock-latency-ns = <30 82 clock-latency-ns = <300000>;
>> 83 turbo-mode;
71 }; 84 };
72 opp-1700000000 { 85 opp-1700000000 {
73 opp-hz = /bits/ 64 <17 86 opp-hz = /bits/ 64 <1700000000>;
74 opp-microvolt = <90000 87 opp-microvolt = <900000>;
75 clock-latency-ns = <30 88 clock-latency-ns = <300000>;
>> 89 turbo-mode;
76 }; 90 };
77 opp-1800000000 { 91 opp-1800000000 {
78 opp-hz = /bits/ 64 <18 92 opp-hz = /bits/ 64 <1800000000>;
79 opp-microvolt = <96000 93 opp-microvolt = <960000>;
80 clock-latency-ns = <30 94 clock-latency-ns = <300000>;
81 turbo-mode; 95 turbo-mode;
82 }; 96 };
83 }; 97 };
84 98
85 cluster1_opp: opp-table-1 { !! 99 cluster1_opp: opp_table1 {
86 compatible = "operating-points 100 compatible = "operating-points-v2";
87 opp-shared; 101 opp-shared;
88 102
89 opp-800000000 { 103 opp-800000000 {
90 opp-hz = /bits/ 64 <80 104 opp-hz = /bits/ 64 <800000000>;
91 opp-microvolt = <82000 105 opp-microvolt = <820000>;
92 clock-latency-ns = <30 106 clock-latency-ns = <300000>;
93 }; 107 };
94 opp-1000000000 { 108 opp-1000000000 {
95 opp-hz = /bits/ 64 <10 109 opp-hz = /bits/ 64 <1000000000>;
96 opp-microvolt = <82000 110 opp-microvolt = <820000>;
97 clock-latency-ns = <30 111 clock-latency-ns = <300000>;
98 }; 112 };
99 opp-1200000000 { 113 opp-1200000000 {
100 opp-hz = /bits/ 64 <12 114 opp-hz = /bits/ 64 <1200000000>;
101 opp-microvolt = <82000 115 opp-microvolt = <820000>;
102 clock-latency-ns = <30 116 clock-latency-ns = <300000>;
103 }; 117 };
104 opp-1300000000 { 118 opp-1300000000 {
105 opp-hz = /bits/ 64 <13 119 opp-hz = /bits/ 64 <1300000000>;
106 opp-microvolt = <82000 120 opp-microvolt = <820000>;
107 clock-latency-ns = <30 121 clock-latency-ns = <300000>;
108 turbo-mode; 122 turbo-mode;
109 }; 123 };
110 }; 124 };
111 125
112 cpus { 126 cpus {
113 #address-cells = <1>; 127 #address-cells = <1>;
114 #size-cells = <0>; 128 #size-cells = <0>;
115 129
116 cpu-map { 130 cpu-map {
117 cluster0 { 131 cluster0 {
118 core0 { 132 core0 {
119 cpu = 133 cpu = <&a57_0>;
120 }; 134 };
121 core1 { 135 core1 {
122 cpu = 136 cpu = <&a57_1>;
123 }; 137 };
124 }; 138 };
125 139
126 cluster1 { 140 cluster1 {
127 core0 { 141 core0 {
128 cpu = 142 cpu = <&a53_0>;
129 }; 143 };
130 core1 { 144 core1 {
131 cpu = 145 cpu = <&a53_1>;
132 }; 146 };
133 core2 { 147 core2 {
134 cpu = 148 cpu = <&a53_2>;
135 }; 149 };
136 core3 { 150 core3 {
137 cpu = 151 cpu = <&a53_3>;
138 }; 152 };
139 }; 153 };
140 }; 154 };
141 155
142 a57_0: cpu@0 { 156 a57_0: cpu@0 {
143 compatible = "arm,cort 157 compatible = "arm,cortex-a57";
144 reg = <0x0>; 158 reg = <0x0>;
145 device_type = "cpu"; 159 device_type = "cpu";
146 power-domains = <&sysc 160 power-domains = <&sysc R8A7796_PD_CA57_CPU0>;
147 next-level-cache = <&L 161 next-level-cache = <&L2_CA57>;
148 enable-method = "psci" 162 enable-method = "psci";
149 cpu-idle-states = <&CP 163 cpu-idle-states = <&CPU_SLEEP_0>;
150 dynamic-power-coeffici 164 dynamic-power-coefficient = <854>;
151 clocks = <&cpg CPG_COR 165 clocks = <&cpg CPG_CORE R8A7796_CLK_Z>;
152 operating-points-v2 = 166 operating-points-v2 = <&cluster0_opp>;
153 capacity-dmips-mhz = < 167 capacity-dmips-mhz = <1024>;
154 #cooling-cells = <2>; 168 #cooling-cells = <2>;
155 }; 169 };
156 170
157 a57_1: cpu@1 { 171 a57_1: cpu@1 {
158 compatible = "arm,cort 172 compatible = "arm,cortex-a57";
159 reg = <0x1>; 173 reg = <0x1>;
160 device_type = "cpu"; 174 device_type = "cpu";
161 power-domains = <&sysc 175 power-domains = <&sysc R8A7796_PD_CA57_CPU1>;
162 next-level-cache = <&L 176 next-level-cache = <&L2_CA57>;
163 enable-method = "psci" 177 enable-method = "psci";
164 cpu-idle-states = <&CP 178 cpu-idle-states = <&CPU_SLEEP_0>;
165 clocks = <&cpg CPG_COR 179 clocks = <&cpg CPG_CORE R8A7796_CLK_Z>;
166 operating-points-v2 = 180 operating-points-v2 = <&cluster0_opp>;
167 capacity-dmips-mhz = < 181 capacity-dmips-mhz = <1024>;
168 #cooling-cells = <2>; 182 #cooling-cells = <2>;
169 }; 183 };
170 184
171 a53_0: cpu@100 { 185 a53_0: cpu@100 {
172 compatible = "arm,cort 186 compatible = "arm,cortex-a53";
173 reg = <0x100>; 187 reg = <0x100>;
174 device_type = "cpu"; 188 device_type = "cpu";
175 power-domains = <&sysc 189 power-domains = <&sysc R8A7796_PD_CA53_CPU0>;
176 next-level-cache = <&L 190 next-level-cache = <&L2_CA53>;
177 enable-method = "psci" 191 enable-method = "psci";
178 cpu-idle-states = <&CP 192 cpu-idle-states = <&CPU_SLEEP_1>;
179 #cooling-cells = <2>; 193 #cooling-cells = <2>;
180 dynamic-power-coeffici 194 dynamic-power-coefficient = <277>;
181 clocks = <&cpg CPG_COR 195 clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
182 operating-points-v2 = 196 operating-points-v2 = <&cluster1_opp>;
183 capacity-dmips-mhz = < 197 capacity-dmips-mhz = <535>;
184 }; 198 };
185 199
186 a53_1: cpu@101 { 200 a53_1: cpu@101 {
187 compatible = "arm,cort 201 compatible = "arm,cortex-a53";
188 reg = <0x101>; 202 reg = <0x101>;
189 device_type = "cpu"; 203 device_type = "cpu";
190 power-domains = <&sysc 204 power-domains = <&sysc R8A7796_PD_CA53_CPU1>;
191 next-level-cache = <&L 205 next-level-cache = <&L2_CA53>;
192 enable-method = "psci" 206 enable-method = "psci";
193 cpu-idle-states = <&CP 207 cpu-idle-states = <&CPU_SLEEP_1>;
194 clocks = <&cpg CPG_COR 208 clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
195 operating-points-v2 = 209 operating-points-v2 = <&cluster1_opp>;
196 capacity-dmips-mhz = < 210 capacity-dmips-mhz = <535>;
197 }; 211 };
198 212
199 a53_2: cpu@102 { 213 a53_2: cpu@102 {
200 compatible = "arm,cort 214 compatible = "arm,cortex-a53";
201 reg = <0x102>; 215 reg = <0x102>;
202 device_type = "cpu"; 216 device_type = "cpu";
203 power-domains = <&sysc 217 power-domains = <&sysc R8A7796_PD_CA53_CPU2>;
204 next-level-cache = <&L 218 next-level-cache = <&L2_CA53>;
205 enable-method = "psci" 219 enable-method = "psci";
206 cpu-idle-states = <&CP 220 cpu-idle-states = <&CPU_SLEEP_1>;
207 clocks = <&cpg CPG_COR 221 clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
208 operating-points-v2 = 222 operating-points-v2 = <&cluster1_opp>;
209 capacity-dmips-mhz = < 223 capacity-dmips-mhz = <535>;
210 }; 224 };
211 225
212 a53_3: cpu@103 { 226 a53_3: cpu@103 {
213 compatible = "arm,cort 227 compatible = "arm,cortex-a53";
214 reg = <0x103>; 228 reg = <0x103>;
215 device_type = "cpu"; 229 device_type = "cpu";
216 power-domains = <&sysc 230 power-domains = <&sysc R8A7796_PD_CA53_CPU3>;
217 next-level-cache = <&L 231 next-level-cache = <&L2_CA53>;
218 enable-method = "psci" 232 enable-method = "psci";
219 cpu-idle-states = <&CP 233 cpu-idle-states = <&CPU_SLEEP_1>;
220 clocks = <&cpg CPG_COR 234 clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
221 operating-points-v2 = 235 operating-points-v2 = <&cluster1_opp>;
222 capacity-dmips-mhz = < 236 capacity-dmips-mhz = <535>;
223 }; 237 };
224 238
225 L2_CA57: cache-controller-0 { 239 L2_CA57: cache-controller-0 {
226 compatible = "cache"; 240 compatible = "cache";
227 power-domains = <&sysc 241 power-domains = <&sysc R8A7796_PD_CA57_SCU>;
228 cache-unified; 242 cache-unified;
229 cache-level = <2>; 243 cache-level = <2>;
230 }; 244 };
231 245
232 L2_CA53: cache-controller-1 { 246 L2_CA53: cache-controller-1 {
233 compatible = "cache"; 247 compatible = "cache";
234 power-domains = <&sysc 248 power-domains = <&sysc R8A7796_PD_CA53_SCU>;
235 cache-unified; 249 cache-unified;
236 cache-level = <2>; 250 cache-level = <2>;
237 }; 251 };
238 252
239 idle-states { 253 idle-states {
240 entry-method = "psci"; 254 entry-method = "psci";
241 255
242 CPU_SLEEP_0: cpu-sleep 256 CPU_SLEEP_0: cpu-sleep-0 {
243 compatible = " 257 compatible = "arm,idle-state";
244 arm,psci-suspe 258 arm,psci-suspend-param = <0x0010000>;
245 local-timer-st 259 local-timer-stop;
246 entry-latency- 260 entry-latency-us = <400>;
247 exit-latency-u 261 exit-latency-us = <500>;
248 min-residency- 262 min-residency-us = <4000>;
249 }; 263 };
250 264
251 CPU_SLEEP_1: cpu-sleep 265 CPU_SLEEP_1: cpu-sleep-1 {
252 compatible = " 266 compatible = "arm,idle-state";
253 arm,psci-suspe 267 arm,psci-suspend-param = <0x0010000>;
254 local-timer-st 268 local-timer-stop;
255 entry-latency- 269 entry-latency-us = <700>;
256 exit-latency-u 270 exit-latency-us = <700>;
257 min-residency- 271 min-residency-us = <5000>;
258 }; 272 };
259 }; 273 };
260 }; 274 };
261 275
262 extal_clk: extal { 276 extal_clk: extal {
263 compatible = "fixed-clock"; 277 compatible = "fixed-clock";
264 #clock-cells = <0>; 278 #clock-cells = <0>;
265 /* This value must be overridd 279 /* This value must be overridden by the board */
266 clock-frequency = <0>; 280 clock-frequency = <0>;
267 }; 281 };
268 282
269 extalr_clk: extalr { 283 extalr_clk: extalr {
270 compatible = "fixed-clock"; 284 compatible = "fixed-clock";
271 #clock-cells = <0>; 285 #clock-cells = <0>;
272 /* This value must be overridd 286 /* This value must be overridden by the board */
273 clock-frequency = <0>; 287 clock-frequency = <0>;
274 }; 288 };
275 289
276 /* External PCIe clock - can be overri 290 /* External PCIe clock - can be overridden by the board */
277 pcie_bus_clk: pcie_bus { 291 pcie_bus_clk: pcie_bus {
278 compatible = "fixed-clock"; 292 compatible = "fixed-clock";
279 #clock-cells = <0>; 293 #clock-cells = <0>;
280 clock-frequency = <0>; 294 clock-frequency = <0>;
281 }; 295 };
282 296
283 pmu_a53 { 297 pmu_a53 {
284 compatible = "arm,cortex-a53-p 298 compatible = "arm,cortex-a53-pmu";
285 interrupts-extended = <&gic GI 299 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
286 <&gic GI 300 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
287 <&gic GI 301 <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
288 <&gic GI 302 <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
289 interrupt-affinity = <&a53_0>, 303 interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>;
290 }; 304 };
291 305
292 pmu_a57 { 306 pmu_a57 {
293 compatible = "arm,cortex-a57-p 307 compatible = "arm,cortex-a57-pmu";
294 interrupts-extended = <&gic GI 308 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
295 <&gic GI 309 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
296 interrupt-affinity = <&a57_0>, 310 interrupt-affinity = <&a57_0>, <&a57_1>;
297 }; 311 };
298 312
299 psci { 313 psci {
300 compatible = "arm,psci-1.0", " 314 compatible = "arm,psci-1.0", "arm,psci-0.2";
301 method = "smc"; 315 method = "smc";
302 }; 316 };
303 317
304 /* External SCIF clock - to be overrid 318 /* External SCIF clock - to be overridden by boards that provide it */
305 scif_clk: scif { 319 scif_clk: scif {
306 compatible = "fixed-clock"; 320 compatible = "fixed-clock";
307 #clock-cells = <0>; 321 #clock-cells = <0>;
308 clock-frequency = <0>; 322 clock-frequency = <0>;
309 }; 323 };
310 324
311 soc { 325 soc {
312 compatible = "simple-bus"; 326 compatible = "simple-bus";
313 interrupt-parent = <&gic>; 327 interrupt-parent = <&gic>;
314 #address-cells = <2>; 328 #address-cells = <2>;
315 #size-cells = <2>; 329 #size-cells = <2>;
316 ranges; 330 ranges;
317 331
318 rwdt: watchdog@e6020000 { 332 rwdt: watchdog@e6020000 {
319 compatible = "renesas, 333 compatible = "renesas,r8a7796-wdt",
320 "renesas, 334 "renesas,rcar-gen3-wdt";
321 reg = <0 0xe6020000 0 335 reg = <0 0xe6020000 0 0x0c>;
322 interrupts = <GIC_SPI <<
323 clocks = <&cpg CPG_MOD 336 clocks = <&cpg CPG_MOD 402>;
324 power-domains = <&sysc 337 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
325 resets = <&cpg 402>; 338 resets = <&cpg 402>;
326 status = "disabled"; 339 status = "disabled";
327 }; 340 };
328 341
329 gpio0: gpio@e6050000 { 342 gpio0: gpio@e6050000 {
330 compatible = "renesas, 343 compatible = "renesas,gpio-r8a7796",
331 "renesas, 344 "renesas,rcar-gen3-gpio";
332 reg = <0 0xe6050000 0 345 reg = <0 0xe6050000 0 0x50>;
333 interrupts = <GIC_SPI 346 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
334 #gpio-cells = <2>; 347 #gpio-cells = <2>;
335 gpio-controller; 348 gpio-controller;
336 gpio-ranges = <&pfc 0 349 gpio-ranges = <&pfc 0 0 16>;
337 #interrupt-cells = <2> 350 #interrupt-cells = <2>;
338 interrupt-controller; 351 interrupt-controller;
339 clocks = <&cpg CPG_MOD 352 clocks = <&cpg CPG_MOD 912>;
340 power-domains = <&sysc 353 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
341 resets = <&cpg 912>; 354 resets = <&cpg 912>;
342 }; 355 };
343 356
344 gpio1: gpio@e6051000 { 357 gpio1: gpio@e6051000 {
345 compatible = "renesas, 358 compatible = "renesas,gpio-r8a7796",
346 "renesas, 359 "renesas,rcar-gen3-gpio";
347 reg = <0 0xe6051000 0 360 reg = <0 0xe6051000 0 0x50>;
348 interrupts = <GIC_SPI 361 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
349 #gpio-cells = <2>; 362 #gpio-cells = <2>;
350 gpio-controller; 363 gpio-controller;
351 gpio-ranges = <&pfc 0 364 gpio-ranges = <&pfc 0 32 29>;
352 #interrupt-cells = <2> 365 #interrupt-cells = <2>;
353 interrupt-controller; 366 interrupt-controller;
354 clocks = <&cpg CPG_MOD 367 clocks = <&cpg CPG_MOD 911>;
355 power-domains = <&sysc 368 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
356 resets = <&cpg 911>; 369 resets = <&cpg 911>;
357 }; 370 };
358 371
359 gpio2: gpio@e6052000 { 372 gpio2: gpio@e6052000 {
360 compatible = "renesas, 373 compatible = "renesas,gpio-r8a7796",
361 "renesas, 374 "renesas,rcar-gen3-gpio";
362 reg = <0 0xe6052000 0 375 reg = <0 0xe6052000 0 0x50>;
363 interrupts = <GIC_SPI 376 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
364 #gpio-cells = <2>; 377 #gpio-cells = <2>;
365 gpio-controller; 378 gpio-controller;
366 gpio-ranges = <&pfc 0 379 gpio-ranges = <&pfc 0 64 15>;
367 #interrupt-cells = <2> 380 #interrupt-cells = <2>;
368 interrupt-controller; 381 interrupt-controller;
369 clocks = <&cpg CPG_MOD 382 clocks = <&cpg CPG_MOD 910>;
370 power-domains = <&sysc 383 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
371 resets = <&cpg 910>; 384 resets = <&cpg 910>;
372 }; 385 };
373 386
374 gpio3: gpio@e6053000 { 387 gpio3: gpio@e6053000 {
375 compatible = "renesas, 388 compatible = "renesas,gpio-r8a7796",
376 "renesas, 389 "renesas,rcar-gen3-gpio";
377 reg = <0 0xe6053000 0 390 reg = <0 0xe6053000 0 0x50>;
378 interrupts = <GIC_SPI 391 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
379 #gpio-cells = <2>; 392 #gpio-cells = <2>;
380 gpio-controller; 393 gpio-controller;
381 gpio-ranges = <&pfc 0 394 gpio-ranges = <&pfc 0 96 16>;
382 #interrupt-cells = <2> 395 #interrupt-cells = <2>;
383 interrupt-controller; 396 interrupt-controller;
384 clocks = <&cpg CPG_MOD 397 clocks = <&cpg CPG_MOD 909>;
385 power-domains = <&sysc 398 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
386 resets = <&cpg 909>; 399 resets = <&cpg 909>;
387 }; 400 };
388 401
389 gpio4: gpio@e6054000 { 402 gpio4: gpio@e6054000 {
390 compatible = "renesas, 403 compatible = "renesas,gpio-r8a7796",
391 "renesas, 404 "renesas,rcar-gen3-gpio";
392 reg = <0 0xe6054000 0 405 reg = <0 0xe6054000 0 0x50>;
393 interrupts = <GIC_SPI 406 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
394 #gpio-cells = <2>; 407 #gpio-cells = <2>;
395 gpio-controller; 408 gpio-controller;
396 gpio-ranges = <&pfc 0 409 gpio-ranges = <&pfc 0 128 18>;
397 #interrupt-cells = <2> 410 #interrupt-cells = <2>;
398 interrupt-controller; 411 interrupt-controller;
399 clocks = <&cpg CPG_MOD 412 clocks = <&cpg CPG_MOD 908>;
400 power-domains = <&sysc 413 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
401 resets = <&cpg 908>; 414 resets = <&cpg 908>;
402 }; 415 };
403 416
404 gpio5: gpio@e6055000 { 417 gpio5: gpio@e6055000 {
405 compatible = "renesas, 418 compatible = "renesas,gpio-r8a7796",
406 "renesas, 419 "renesas,rcar-gen3-gpio";
407 reg = <0 0xe6055000 0 420 reg = <0 0xe6055000 0 0x50>;
408 interrupts = <GIC_SPI 421 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
409 #gpio-cells = <2>; 422 #gpio-cells = <2>;
410 gpio-controller; 423 gpio-controller;
411 gpio-ranges = <&pfc 0 424 gpio-ranges = <&pfc 0 160 26>;
412 #interrupt-cells = <2> 425 #interrupt-cells = <2>;
413 interrupt-controller; 426 interrupt-controller;
414 clocks = <&cpg CPG_MOD 427 clocks = <&cpg CPG_MOD 907>;
415 power-domains = <&sysc 428 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
416 resets = <&cpg 907>; 429 resets = <&cpg 907>;
417 }; 430 };
418 431
419 gpio6: gpio@e6055400 { 432 gpio6: gpio@e6055400 {
420 compatible = "renesas, 433 compatible = "renesas,gpio-r8a7796",
421 "renesas, 434 "renesas,rcar-gen3-gpio";
422 reg = <0 0xe6055400 0 435 reg = <0 0xe6055400 0 0x50>;
423 interrupts = <GIC_SPI 436 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
424 #gpio-cells = <2>; 437 #gpio-cells = <2>;
425 gpio-controller; 438 gpio-controller;
426 gpio-ranges = <&pfc 0 439 gpio-ranges = <&pfc 0 192 32>;
427 #interrupt-cells = <2> 440 #interrupt-cells = <2>;
428 interrupt-controller; 441 interrupt-controller;
429 clocks = <&cpg CPG_MOD 442 clocks = <&cpg CPG_MOD 906>;
430 power-domains = <&sysc 443 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
431 resets = <&cpg 906>; 444 resets = <&cpg 906>;
432 }; 445 };
433 446
434 gpio7: gpio@e6055800 { 447 gpio7: gpio@e6055800 {
435 compatible = "renesas, 448 compatible = "renesas,gpio-r8a7796",
436 "renesas, 449 "renesas,rcar-gen3-gpio";
437 reg = <0 0xe6055800 0 450 reg = <0 0xe6055800 0 0x50>;
438 interrupts = <GIC_SPI 451 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
439 #gpio-cells = <2>; 452 #gpio-cells = <2>;
440 gpio-controller; 453 gpio-controller;
441 gpio-ranges = <&pfc 0 454 gpio-ranges = <&pfc 0 224 4>;
442 #interrupt-cells = <2> 455 #interrupt-cells = <2>;
443 interrupt-controller; 456 interrupt-controller;
444 clocks = <&cpg CPG_MOD 457 clocks = <&cpg CPG_MOD 905>;
445 power-domains = <&sysc 458 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
446 resets = <&cpg 905>; 459 resets = <&cpg 905>;
447 }; 460 };
448 461
449 pfc: pinctrl@e6060000 { !! 462 pfc: pin-controller@e6060000 {
450 compatible = "renesas, 463 compatible = "renesas,pfc-r8a7796";
451 reg = <0 0xe6060000 0 464 reg = <0 0xe6060000 0 0x50c>;
452 }; 465 };
453 466
454 cmt0: timer@e60f0000 { 467 cmt0: timer@e60f0000 {
455 compatible = "renesas, 468 compatible = "renesas,r8a7796-cmt0",
456 "renesas, 469 "renesas,rcar-gen3-cmt0";
457 reg = <0 0xe60f0000 0 470 reg = <0 0xe60f0000 0 0x1004>;
458 interrupts = <GIC_SPI 471 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
459 <GIC_SPI 472 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
460 clocks = <&cpg CPG_MOD 473 clocks = <&cpg CPG_MOD 303>;
461 clock-names = "fck"; 474 clock-names = "fck";
462 power-domains = <&sysc 475 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
463 resets = <&cpg 303>; 476 resets = <&cpg 303>;
464 status = "disabled"; 477 status = "disabled";
465 }; 478 };
466 479
467 cmt1: timer@e6130000 { 480 cmt1: timer@e6130000 {
468 compatible = "renesas, 481 compatible = "renesas,r8a7796-cmt1",
469 "renesas, 482 "renesas,rcar-gen3-cmt1";
470 reg = <0 0xe6130000 0 483 reg = <0 0xe6130000 0 0x1004>;
471 interrupts = <GIC_SPI 484 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
472 <GIC_SPI 485 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
473 <GIC_SPI 486 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
474 <GIC_SPI 487 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
475 <GIC_SPI 488 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
476 <GIC_SPI 489 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
477 <GIC_SPI 490 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
478 <GIC_SPI 491 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
479 clocks = <&cpg CPG_MOD 492 clocks = <&cpg CPG_MOD 302>;
480 clock-names = "fck"; 493 clock-names = "fck";
481 power-domains = <&sysc 494 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
482 resets = <&cpg 302>; 495 resets = <&cpg 302>;
483 status = "disabled"; 496 status = "disabled";
484 }; 497 };
485 498
486 cmt2: timer@e6140000 { 499 cmt2: timer@e6140000 {
487 compatible = "renesas, 500 compatible = "renesas,r8a7796-cmt1",
488 "renesas, 501 "renesas,rcar-gen3-cmt1";
489 reg = <0 0xe6140000 0 502 reg = <0 0xe6140000 0 0x1004>;
490 interrupts = <GIC_SPI 503 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
491 <GIC_SPI 504 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
492 <GIC_SPI 505 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
493 <GIC_SPI 506 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
494 <GIC_SPI 507 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
495 <GIC_SPI 508 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
496 <GIC_SPI 509 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
497 <GIC_SPI 510 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
498 clocks = <&cpg CPG_MOD 511 clocks = <&cpg CPG_MOD 301>;
499 clock-names = "fck"; 512 clock-names = "fck";
500 power-domains = <&sysc 513 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
501 resets = <&cpg 301>; 514 resets = <&cpg 301>;
502 status = "disabled"; 515 status = "disabled";
503 }; 516 };
504 517
505 cmt3: timer@e6148000 { 518 cmt3: timer@e6148000 {
506 compatible = "renesas, 519 compatible = "renesas,r8a7796-cmt1",
507 "renesas, 520 "renesas,rcar-gen3-cmt1";
508 reg = <0 0xe6148000 0 521 reg = <0 0xe6148000 0 0x1004>;
509 interrupts = <GIC_SPI 522 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
510 <GIC_SPI 523 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
511 <GIC_SPI 524 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
512 <GIC_SPI 525 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
513 <GIC_SPI 526 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
514 <GIC_SPI 527 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
515 <GIC_SPI 528 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
516 <GIC_SPI 529 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
517 clocks = <&cpg CPG_MOD 530 clocks = <&cpg CPG_MOD 300>;
518 clock-names = "fck"; 531 clock-names = "fck";
519 power-domains = <&sysc 532 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
520 resets = <&cpg 300>; 533 resets = <&cpg 300>;
521 status = "disabled"; 534 status = "disabled";
522 }; 535 };
523 536
524 cpg: clock-controller@e6150000 537 cpg: clock-controller@e6150000 {
525 compatible = "renesas, 538 compatible = "renesas,r8a7796-cpg-mssr";
526 reg = <0 0xe6150000 0 539 reg = <0 0xe6150000 0 0x1000>;
527 clocks = <&extal_clk>, 540 clocks = <&extal_clk>, <&extalr_clk>;
528 clock-names = "extal", 541 clock-names = "extal", "extalr";
529 #clock-cells = <2>; 542 #clock-cells = <2>;
530 #power-domain-cells = 543 #power-domain-cells = <0>;
531 #reset-cells = <1>; 544 #reset-cells = <1>;
532 }; 545 };
533 546
534 rst: reset-controller@e6160000 547 rst: reset-controller@e6160000 {
535 compatible = "renesas, 548 compatible = "renesas,r8a7796-rst";
536 reg = <0 0xe6160000 0 549 reg = <0 0xe6160000 0 0x0200>;
537 }; 550 };
538 551
539 sysc: system-controller@e61800 552 sysc: system-controller@e6180000 {
540 compatible = "renesas, 553 compatible = "renesas,r8a7796-sysc";
541 reg = <0 0xe6180000 0 554 reg = <0 0xe6180000 0 0x0400>;
542 #power-domain-cells = 555 #power-domain-cells = <1>;
543 }; 556 };
544 557
545 tsc: thermal@e6198000 { 558 tsc: thermal@e6198000 {
546 compatible = "renesas, 559 compatible = "renesas,r8a7796-thermal";
547 reg = <0 0xe6198000 0 560 reg = <0 0xe6198000 0 0x100>,
548 <0 0xe61a0000 0 561 <0 0xe61a0000 0 0x100>,
549 <0 0xe61a8000 0 562 <0 0xe61a8000 0 0x100>;
550 interrupts = <GIC_SPI 563 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
551 <GIC_SPI 564 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
552 <GIC_SPI 565 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
553 clocks = <&cpg CPG_MOD 566 clocks = <&cpg CPG_MOD 522>;
554 power-domains = <&sysc 567 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
555 resets = <&cpg 522>; 568 resets = <&cpg 522>;
556 #thermal-sensor-cells 569 #thermal-sensor-cells = <1>;
557 }; 570 };
558 571
559 intc_ex: interrupt-controller@ 572 intc_ex: interrupt-controller@e61c0000 {
560 compatible = "renesas, 573 compatible = "renesas,intc-ex-r8a7796", "renesas,irqc";
561 #interrupt-cells = <2> 574 #interrupt-cells = <2>;
562 interrupt-controller; 575 interrupt-controller;
563 reg = <0 0xe61c0000 0 576 reg = <0 0xe61c0000 0 0x200>;
564 interrupts = <GIC_SPI 577 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
565 <GIC_SPI 578 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
566 <GIC_SPI 579 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
567 <GIC_SPI 580 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
568 <GIC_SPI 581 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
569 <GIC_SPI 582 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
570 clocks = <&cpg CPG_MOD 583 clocks = <&cpg CPG_MOD 407>;
571 power-domains = <&sysc 584 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
572 resets = <&cpg 407>; 585 resets = <&cpg 407>;
573 }; 586 };
574 587
575 tmu0: timer@e61e0000 { <<
576 compatible = "renesas, <<
577 reg = <0 0xe61e0000 0 <<
578 interrupts = <GIC_SPI <<
579 <GIC_SPI <<
580 <GIC_SPI <<
581 interrupt-names = "tun <<
582 clocks = <&cpg CPG_MOD <<
583 clock-names = "fck"; <<
584 power-domains = <&sysc <<
585 resets = <&cpg 125>; <<
586 status = "disabled"; <<
587 }; <<
588 <<
589 tmu1: timer@e6fc0000 { <<
590 compatible = "renesas, <<
591 reg = <0 0xe6fc0000 0 <<
592 interrupts = <GIC_SPI <<
593 <GIC_SPI <<
594 <GIC_SPI <<
595 <GIC_SPI <<
596 interrupt-names = "tun <<
597 clocks = <&cpg CPG_MOD <<
598 clock-names = "fck"; <<
599 power-domains = <&sysc <<
600 resets = <&cpg 124>; <<
601 status = "disabled"; <<
602 }; <<
603 <<
604 tmu2: timer@e6fd0000 { <<
605 compatible = "renesas, <<
606 reg = <0 0xe6fd0000 0 <<
607 interrupts = <GIC_SPI <<
608 <GIC_SPI <<
609 <GIC_SPI <<
610 <GIC_SPI <<
611 interrupt-names = "tun <<
612 clocks = <&cpg CPG_MOD <<
613 clock-names = "fck"; <<
614 power-domains = <&sysc <<
615 resets = <&cpg 123>; <<
616 status = "disabled"; <<
617 }; <<
618 <<
619 tmu3: timer@e6fe0000 { <<
620 compatible = "renesas, <<
621 reg = <0 0xe6fe0000 0 <<
622 interrupts = <GIC_SPI <<
623 <GIC_SPI <<
624 <GIC_SPI <<
625 interrupt-names = "tun <<
626 clocks = <&cpg CPG_MOD <<
627 clock-names = "fck"; <<
628 power-domains = <&sysc <<
629 resets = <&cpg 122>; <<
630 status = "disabled"; <<
631 }; <<
632 <<
633 tmu4: timer@ffc00000 { <<
634 compatible = "renesas, <<
635 reg = <0 0xffc00000 0 <<
636 interrupts = <GIC_SPI <<
637 <GIC_SPI <<
638 <GIC_SPI <<
639 interrupt-names = "tun <<
640 clocks = <&cpg CPG_MOD <<
641 clock-names = "fck"; <<
642 power-domains = <&sysc <<
643 resets = <&cpg 121>; <<
644 status = "disabled"; <<
645 }; <<
646 <<
647 i2c0: i2c@e6500000 { 588 i2c0: i2c@e6500000 {
648 #address-cells = <1>; 589 #address-cells = <1>;
649 #size-cells = <0>; 590 #size-cells = <0>;
650 compatible = "renesas, 591 compatible = "renesas,i2c-r8a7796",
651 "renesas, 592 "renesas,rcar-gen3-i2c";
652 reg = <0 0xe6500000 0 593 reg = <0 0xe6500000 0 0x40>;
653 interrupts = <GIC_SPI 594 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
654 clocks = <&cpg CPG_MOD 595 clocks = <&cpg CPG_MOD 931>;
655 power-domains = <&sysc 596 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
656 resets = <&cpg 931>; 597 resets = <&cpg 931>;
657 dmas = <&dmac1 0x91>, 598 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
658 <&dmac2 0x91>, 599 <&dmac2 0x91>, <&dmac2 0x90>;
659 dma-names = "tx", "rx" 600 dma-names = "tx", "rx", "tx", "rx";
660 i2c-scl-internal-delay 601 i2c-scl-internal-delay-ns = <110>;
661 status = "disabled"; 602 status = "disabled";
662 }; 603 };
663 604
664 i2c1: i2c@e6508000 { 605 i2c1: i2c@e6508000 {
665 #address-cells = <1>; 606 #address-cells = <1>;
666 #size-cells = <0>; 607 #size-cells = <0>;
667 compatible = "renesas, 608 compatible = "renesas,i2c-r8a7796",
668 "renesas, 609 "renesas,rcar-gen3-i2c";
669 reg = <0 0xe6508000 0 610 reg = <0 0xe6508000 0 0x40>;
670 interrupts = <GIC_SPI 611 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
671 clocks = <&cpg CPG_MOD 612 clocks = <&cpg CPG_MOD 930>;
672 power-domains = <&sysc 613 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
673 resets = <&cpg 930>; 614 resets = <&cpg 930>;
674 dmas = <&dmac1 0x93>, 615 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
675 <&dmac2 0x93>, 616 <&dmac2 0x93>, <&dmac2 0x92>;
676 dma-names = "tx", "rx" 617 dma-names = "tx", "rx", "tx", "rx";
677 i2c-scl-internal-delay 618 i2c-scl-internal-delay-ns = <6>;
678 status = "disabled"; 619 status = "disabled";
679 }; 620 };
680 621
681 i2c2: i2c@e6510000 { 622 i2c2: i2c@e6510000 {
682 #address-cells = <1>; 623 #address-cells = <1>;
683 #size-cells = <0>; 624 #size-cells = <0>;
684 compatible = "renesas, 625 compatible = "renesas,i2c-r8a7796",
685 "renesas, 626 "renesas,rcar-gen3-i2c";
686 reg = <0 0xe6510000 0 627 reg = <0 0xe6510000 0 0x40>;
687 interrupts = <GIC_SPI 628 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
688 clocks = <&cpg CPG_MOD 629 clocks = <&cpg CPG_MOD 929>;
689 power-domains = <&sysc 630 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
690 resets = <&cpg 929>; 631 resets = <&cpg 929>;
691 dmas = <&dmac1 0x95>, 632 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
692 <&dmac2 0x95>, 633 <&dmac2 0x95>, <&dmac2 0x94>;
693 dma-names = "tx", "rx" 634 dma-names = "tx", "rx", "tx", "rx";
694 i2c-scl-internal-delay 635 i2c-scl-internal-delay-ns = <6>;
695 status = "disabled"; 636 status = "disabled";
696 }; 637 };
697 638
698 i2c3: i2c@e66d0000 { 639 i2c3: i2c@e66d0000 {
699 #address-cells = <1>; 640 #address-cells = <1>;
700 #size-cells = <0>; 641 #size-cells = <0>;
701 compatible = "renesas, 642 compatible = "renesas,i2c-r8a7796",
702 "renesas, 643 "renesas,rcar-gen3-i2c";
703 reg = <0 0xe66d0000 0 644 reg = <0 0xe66d0000 0 0x40>;
704 interrupts = <GIC_SPI 645 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
705 clocks = <&cpg CPG_MOD 646 clocks = <&cpg CPG_MOD 928>;
706 power-domains = <&sysc 647 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
707 resets = <&cpg 928>; 648 resets = <&cpg 928>;
708 dmas = <&dmac0 0x97>, 649 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
709 dma-names = "tx", "rx" 650 dma-names = "tx", "rx";
710 i2c-scl-internal-delay 651 i2c-scl-internal-delay-ns = <110>;
711 status = "disabled"; 652 status = "disabled";
712 }; 653 };
713 654
714 i2c4: i2c@e66d8000 { 655 i2c4: i2c@e66d8000 {
715 #address-cells = <1>; 656 #address-cells = <1>;
716 #size-cells = <0>; 657 #size-cells = <0>;
717 compatible = "renesas, 658 compatible = "renesas,i2c-r8a7796",
718 "renesas, 659 "renesas,rcar-gen3-i2c";
719 reg = <0 0xe66d8000 0 660 reg = <0 0xe66d8000 0 0x40>;
720 interrupts = <GIC_SPI 661 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
721 clocks = <&cpg CPG_MOD 662 clocks = <&cpg CPG_MOD 927>;
722 power-domains = <&sysc 663 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
723 resets = <&cpg 927>; 664 resets = <&cpg 927>;
724 dmas = <&dmac0 0x99>, 665 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
725 dma-names = "tx", "rx" 666 dma-names = "tx", "rx";
726 i2c-scl-internal-delay 667 i2c-scl-internal-delay-ns = <110>;
727 status = "disabled"; 668 status = "disabled";
728 }; 669 };
729 670
730 i2c5: i2c@e66e0000 { 671 i2c5: i2c@e66e0000 {
731 #address-cells = <1>; 672 #address-cells = <1>;
732 #size-cells = <0>; 673 #size-cells = <0>;
733 compatible = "renesas, 674 compatible = "renesas,i2c-r8a7796",
734 "renesas, 675 "renesas,rcar-gen3-i2c";
735 reg = <0 0xe66e0000 0 676 reg = <0 0xe66e0000 0 0x40>;
736 interrupts = <GIC_SPI 677 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
737 clocks = <&cpg CPG_MOD 678 clocks = <&cpg CPG_MOD 919>;
738 power-domains = <&sysc 679 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
739 resets = <&cpg 919>; 680 resets = <&cpg 919>;
740 dmas = <&dmac0 0x9b>, 681 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
741 dma-names = "tx", "rx" 682 dma-names = "tx", "rx";
742 i2c-scl-internal-delay 683 i2c-scl-internal-delay-ns = <110>;
743 status = "disabled"; 684 status = "disabled";
744 }; 685 };
745 686
746 i2c6: i2c@e66e8000 { 687 i2c6: i2c@e66e8000 {
747 #address-cells = <1>; 688 #address-cells = <1>;
748 #size-cells = <0>; 689 #size-cells = <0>;
749 compatible = "renesas, 690 compatible = "renesas,i2c-r8a7796",
750 "renesas, 691 "renesas,rcar-gen3-i2c";
751 reg = <0 0xe66e8000 0 692 reg = <0 0xe66e8000 0 0x40>;
752 interrupts = <GIC_SPI 693 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
753 clocks = <&cpg CPG_MOD 694 clocks = <&cpg CPG_MOD 918>;
754 power-domains = <&sysc 695 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
755 resets = <&cpg 918>; 696 resets = <&cpg 918>;
756 dmas = <&dmac0 0x9d>, 697 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
757 dma-names = "tx", "rx" 698 dma-names = "tx", "rx";
758 i2c-scl-internal-delay 699 i2c-scl-internal-delay-ns = <6>;
759 status = "disabled"; 700 status = "disabled";
760 }; 701 };
761 702
762 i2c_dvfs: i2c@e60b0000 { 703 i2c_dvfs: i2c@e60b0000 {
763 #address-cells = <1>; 704 #address-cells = <1>;
764 #size-cells = <0>; 705 #size-cells = <0>;
765 compatible = "renesas, 706 compatible = "renesas,iic-r8a7796",
766 "renesas, 707 "renesas,rcar-gen3-iic",
767 "renesas, 708 "renesas,rmobile-iic";
768 reg = <0 0xe60b0000 0 709 reg = <0 0xe60b0000 0 0x425>;
769 interrupts = <GIC_SPI 710 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
770 clocks = <&cpg CPG_MOD 711 clocks = <&cpg CPG_MOD 926>;
771 power-domains = <&sysc 712 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
772 resets = <&cpg 926>; 713 resets = <&cpg 926>;
773 dmas = <&dmac0 0x11>, 714 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
774 dma-names = "tx", "rx" 715 dma-names = "tx", "rx";
775 status = "disabled"; 716 status = "disabled";
776 }; 717 };
777 718
778 hscif0: serial@e6540000 { 719 hscif0: serial@e6540000 {
779 compatible = "renesas, 720 compatible = "renesas,hscif-r8a7796",
780 "renesas, 721 "renesas,rcar-gen3-hscif",
781 "renesas, 722 "renesas,hscif";
782 reg = <0 0xe6540000 0 723 reg = <0 0xe6540000 0 0x60>;
783 interrupts = <GIC_SPI 724 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
784 clocks = <&cpg CPG_MOD 725 clocks = <&cpg CPG_MOD 520>,
785 <&cpg CPG_COR 726 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
786 <&scif_clk>; 727 <&scif_clk>;
787 clock-names = "fck", " 728 clock-names = "fck", "brg_int", "scif_clk";
788 dmas = <&dmac1 0x31>, 729 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
789 <&dmac2 0x31>, 730 <&dmac2 0x31>, <&dmac2 0x30>;
790 dma-names = "tx", "rx" 731 dma-names = "tx", "rx", "tx", "rx";
791 power-domains = <&sysc 732 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
792 resets = <&cpg 520>; 733 resets = <&cpg 520>;
793 status = "disabled"; 734 status = "disabled";
794 }; 735 };
795 736
796 hscif1: serial@e6550000 { 737 hscif1: serial@e6550000 {
797 compatible = "renesas, 738 compatible = "renesas,hscif-r8a7796",
798 "renesas, 739 "renesas,rcar-gen3-hscif",
799 "renesas, 740 "renesas,hscif";
800 reg = <0 0xe6550000 0 741 reg = <0 0xe6550000 0 0x60>;
801 interrupts = <GIC_SPI 742 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
802 clocks = <&cpg CPG_MOD 743 clocks = <&cpg CPG_MOD 519>,
803 <&cpg CPG_COR 744 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
804 <&scif_clk>; 745 <&scif_clk>;
805 clock-names = "fck", " 746 clock-names = "fck", "brg_int", "scif_clk";
806 dmas = <&dmac1 0x33>, 747 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
807 <&dmac2 0x33>, 748 <&dmac2 0x33>, <&dmac2 0x32>;
808 dma-names = "tx", "rx" 749 dma-names = "tx", "rx", "tx", "rx";
809 power-domains = <&sysc 750 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
810 resets = <&cpg 519>; 751 resets = <&cpg 519>;
811 status = "disabled"; 752 status = "disabled";
812 }; 753 };
813 754
814 hscif2: serial@e6560000 { 755 hscif2: serial@e6560000 {
815 compatible = "renesas, 756 compatible = "renesas,hscif-r8a7796",
816 "renesas, 757 "renesas,rcar-gen3-hscif",
817 "renesas, 758 "renesas,hscif";
818 reg = <0 0xe6560000 0 759 reg = <0 0xe6560000 0 0x60>;
819 interrupts = <GIC_SPI 760 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
820 clocks = <&cpg CPG_MOD 761 clocks = <&cpg CPG_MOD 518>,
821 <&cpg CPG_COR 762 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
822 <&scif_clk>; 763 <&scif_clk>;
823 clock-names = "fck", " 764 clock-names = "fck", "brg_int", "scif_clk";
824 dmas = <&dmac1 0x35>, 765 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
825 <&dmac2 0x35>, 766 <&dmac2 0x35>, <&dmac2 0x34>;
826 dma-names = "tx", "rx" 767 dma-names = "tx", "rx", "tx", "rx";
827 power-domains = <&sysc 768 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
828 resets = <&cpg 518>; 769 resets = <&cpg 518>;
829 status = "disabled"; 770 status = "disabled";
830 }; 771 };
831 772
832 hscif3: serial@e66a0000 { 773 hscif3: serial@e66a0000 {
833 compatible = "renesas, 774 compatible = "renesas,hscif-r8a7796",
834 "renesas, 775 "renesas,rcar-gen3-hscif",
835 "renesas, 776 "renesas,hscif";
836 reg = <0 0xe66a0000 0 777 reg = <0 0xe66a0000 0 0x60>;
837 interrupts = <GIC_SPI 778 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
838 clocks = <&cpg CPG_MOD 779 clocks = <&cpg CPG_MOD 517>,
839 <&cpg CPG_COR 780 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
840 <&scif_clk>; 781 <&scif_clk>;
841 clock-names = "fck", " 782 clock-names = "fck", "brg_int", "scif_clk";
842 dmas = <&dmac0 0x37>, 783 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
843 dma-names = "tx", "rx" 784 dma-names = "tx", "rx";
844 power-domains = <&sysc 785 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
845 resets = <&cpg 517>; 786 resets = <&cpg 517>;
846 status = "disabled"; 787 status = "disabled";
847 }; 788 };
848 789
849 hscif4: serial@e66b0000 { 790 hscif4: serial@e66b0000 {
850 compatible = "renesas, 791 compatible = "renesas,hscif-r8a7796",
851 "renesas, 792 "renesas,rcar-gen3-hscif",
852 "renesas, 793 "renesas,hscif";
853 reg = <0 0xe66b0000 0 794 reg = <0 0xe66b0000 0 0x60>;
854 interrupts = <GIC_SPI 795 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
855 clocks = <&cpg CPG_MOD 796 clocks = <&cpg CPG_MOD 516>,
856 <&cpg CPG_COR 797 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
857 <&scif_clk>; 798 <&scif_clk>;
858 clock-names = "fck", " 799 clock-names = "fck", "brg_int", "scif_clk";
859 dmas = <&dmac0 0x39>, 800 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
860 dma-names = "tx", "rx" 801 dma-names = "tx", "rx";
861 power-domains = <&sysc 802 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
862 resets = <&cpg 516>; 803 resets = <&cpg 516>;
863 status = "disabled"; 804 status = "disabled";
864 }; 805 };
865 806
866 hsusb: usb@e6590000 { 807 hsusb: usb@e6590000 {
867 compatible = "renesas, 808 compatible = "renesas,usbhs-r8a7796",
868 "renesas, 809 "renesas,rcar-gen3-usbhs";
869 reg = <0 0xe6590000 0 810 reg = <0 0xe6590000 0 0x200>;
870 interrupts = <GIC_SPI 811 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
871 clocks = <&cpg CPG_MOD 812 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
872 dmas = <&usb_dmac0 0>, 813 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
873 <&usb_dmac1 0>, 814 <&usb_dmac1 0>, <&usb_dmac1 1>;
874 dma-names = "ch0", "ch 815 dma-names = "ch0", "ch1", "ch2", "ch3";
875 renesas,buswait = <11> 816 renesas,buswait = <11>;
876 phys = <&usb2_phy0 3>; 817 phys = <&usb2_phy0 3>;
877 phy-names = "usb"; 818 phy-names = "usb";
878 power-domains = <&sysc 819 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
879 resets = <&cpg 704>, < 820 resets = <&cpg 704>, <&cpg 703>;
880 status = "disabled"; 821 status = "disabled";
881 }; 822 };
882 823
883 usb_dmac0: dma-controller@e65a 824 usb_dmac0: dma-controller@e65a0000 {
884 compatible = "renesas, 825 compatible = "renesas,r8a7796-usb-dmac",
885 "renesas, 826 "renesas,usb-dmac";
886 reg = <0 0xe65a0000 0 827 reg = <0 0xe65a0000 0 0x100>;
887 interrupts = <GIC_SPI 828 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
888 <GIC_SPI 829 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
889 interrupt-names = "ch0 830 interrupt-names = "ch0", "ch1";
890 clocks = <&cpg CPG_MOD 831 clocks = <&cpg CPG_MOD 330>;
891 power-domains = <&sysc 832 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
892 resets = <&cpg 330>; 833 resets = <&cpg 330>;
893 #dma-cells = <1>; 834 #dma-cells = <1>;
894 dma-channels = <2>; 835 dma-channels = <2>;
895 }; 836 };
896 837
897 usb_dmac1: dma-controller@e65b 838 usb_dmac1: dma-controller@e65b0000 {
898 compatible = "renesas, 839 compatible = "renesas,r8a7796-usb-dmac",
899 "renesas, 840 "renesas,usb-dmac";
900 reg = <0 0xe65b0000 0 841 reg = <0 0xe65b0000 0 0x100>;
901 interrupts = <GIC_SPI 842 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
902 <GIC_SPI 843 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
903 interrupt-names = "ch0 844 interrupt-names = "ch0", "ch1";
904 clocks = <&cpg CPG_MOD 845 clocks = <&cpg CPG_MOD 331>;
905 power-domains = <&sysc 846 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
906 resets = <&cpg 331>; 847 resets = <&cpg 331>;
907 #dma-cells = <1>; 848 #dma-cells = <1>;
908 dma-channels = <2>; 849 dma-channels = <2>;
909 }; 850 };
910 851
911 usb3_phy0: usb-phy@e65ee000 { 852 usb3_phy0: usb-phy@e65ee000 {
912 compatible = "renesas, 853 compatible = "renesas,r8a7796-usb3-phy",
913 "renesas, 854 "renesas,rcar-gen3-usb3-phy";
914 reg = <0 0xe65ee000 0 855 reg = <0 0xe65ee000 0 0x90>;
915 clocks = <&cpg CPG_MOD 856 clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>,
916 <&usb_extal_c 857 <&usb_extal_clk>;
917 clock-names = "usb3-if 858 clock-names = "usb3-if", "usb3s_clk", "usb_extal";
918 power-domains = <&sysc 859 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
919 resets = <&cpg 328>; 860 resets = <&cpg 328>;
920 #phy-cells = <0>; 861 #phy-cells = <0>;
921 status = "disabled"; 862 status = "disabled";
922 }; 863 };
923 864
924 arm_cc630p: crypto@e6601000 { 865 arm_cc630p: crypto@e6601000 {
925 compatible = "arm,cryp 866 compatible = "arm,cryptocell-630p-ree";
926 interrupts = <GIC_SPI 867 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
927 reg = <0x0 0xe6601000 868 reg = <0x0 0xe6601000 0 0x1000>;
928 clocks = <&cpg CPG_MOD 869 clocks = <&cpg CPG_MOD 229>;
929 resets = <&cpg 229>; 870 resets = <&cpg 229>;
930 power-domains = <&sysc 871 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
931 }; 872 };
932 873
933 dmac0: dma-controller@e6700000 874 dmac0: dma-controller@e6700000 {
934 compatible = "renesas, 875 compatible = "renesas,dmac-r8a7796",
935 "renesas, 876 "renesas,rcar-dmac";
936 reg = <0 0xe6700000 0 877 reg = <0 0xe6700000 0 0x10000>;
937 interrupts = <GIC_SPI 878 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
938 <GIC_SPI 879 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
939 <GIC_SPI 880 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
940 <GIC_SPI 881 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
941 <GIC_SPI 882 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
942 <GIC_SPI 883 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
943 <GIC_SPI 884 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
944 <GIC_SPI 885 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
945 <GIC_SPI 886 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
946 <GIC_SPI 887 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
947 <GIC_SPI 888 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
948 <GIC_SPI 889 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
949 <GIC_SPI 890 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
950 <GIC_SPI 891 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
951 <GIC_SPI 892 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
952 <GIC_SPI 893 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
953 <GIC_SPI 894 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
954 interrupt-names = "err 895 interrupt-names = "error",
955 "ch0", 896 "ch0", "ch1", "ch2", "ch3",
956 "ch4", 897 "ch4", "ch5", "ch6", "ch7",
957 "ch8", 898 "ch8", "ch9", "ch10", "ch11",
958 "ch12" 899 "ch12", "ch13", "ch14", "ch15";
959 clocks = <&cpg CPG_MOD 900 clocks = <&cpg CPG_MOD 219>;
960 clock-names = "fck"; 901 clock-names = "fck";
961 power-domains = <&sysc 902 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
962 resets = <&cpg 219>; 903 resets = <&cpg 219>;
963 #dma-cells = <1>; 904 #dma-cells = <1>;
964 dma-channels = <16>; 905 dma-channels = <16>;
965 iommus = <&ipmmu_ds0 0 906 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
966 <&ipmmu_ds0 2>, 907 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
967 <&ipmmu_ds0 4>, 908 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
968 <&ipmmu_ds0 6>, 909 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
969 <&ipmmu_ds0 8>, 910 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
970 <&ipmmu_ds0 10> 911 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
971 <&ipmmu_ds0 12> 912 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
972 <&ipmmu_ds0 14> 913 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
973 }; 914 };
974 915
975 dmac1: dma-controller@e7300000 916 dmac1: dma-controller@e7300000 {
976 compatible = "renesas, 917 compatible = "renesas,dmac-r8a7796",
977 "renesas, 918 "renesas,rcar-dmac";
978 reg = <0 0xe7300000 0 919 reg = <0 0xe7300000 0 0x10000>;
979 interrupts = <GIC_SPI 920 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
980 <GIC_SPI 921 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
981 <GIC_SPI 922 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
982 <GIC_SPI 923 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
983 <GIC_SPI 924 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
984 <GIC_SPI 925 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
985 <GIC_SPI 926 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
986 <GIC_SPI 927 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
987 <GIC_SPI 928 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
988 <GIC_SPI 929 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
989 <GIC_SPI 930 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
990 <GIC_SPI 931 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
991 <GIC_SPI 932 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
992 <GIC_SPI 933 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
993 <GIC_SPI 934 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
994 <GIC_SPI 935 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
995 <GIC_SPI 936 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
996 interrupt-names = "err 937 interrupt-names = "error",
997 "ch0", 938 "ch0", "ch1", "ch2", "ch3",
998 "ch4", 939 "ch4", "ch5", "ch6", "ch7",
999 "ch8", 940 "ch8", "ch9", "ch10", "ch11",
1000 "ch12 941 "ch12", "ch13", "ch14", "ch15";
1001 clocks = <&cpg CPG_MO 942 clocks = <&cpg CPG_MOD 218>;
1002 clock-names = "fck"; 943 clock-names = "fck";
1003 power-domains = <&sys 944 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1004 resets = <&cpg 218>; 945 resets = <&cpg 218>;
1005 #dma-cells = <1>; 946 #dma-cells = <1>;
1006 dma-channels = <16>; 947 dma-channels = <16>;
1007 iommus = <&ipmmu_ds1 948 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
1008 <&ipmmu_ds1 2> 949 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
1009 <&ipmmu_ds1 4> 950 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
1010 <&ipmmu_ds1 6> 951 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
1011 <&ipmmu_ds1 8> 952 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
1012 <&ipmmu_ds1 10 953 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
1013 <&ipmmu_ds1 12 954 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
1014 <&ipmmu_ds1 14 955 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
1015 }; 956 };
1016 957
1017 dmac2: dma-controller@e731000 958 dmac2: dma-controller@e7310000 {
1018 compatible = "renesas 959 compatible = "renesas,dmac-r8a7796",
1019 "renesas 960 "renesas,rcar-dmac";
1020 reg = <0 0xe7310000 0 961 reg = <0 0xe7310000 0 0x10000>;
1021 interrupts = <GIC_SPI 962 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
1022 <GIC_SPI 963 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
1023 <GIC_SPI 964 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
1024 <GIC_SPI 965 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
1025 <GIC_SPI 966 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
1026 <GIC_SPI 967 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
1027 <GIC_SPI 968 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
1028 <GIC_SPI 969 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
1029 <GIC_SPI 970 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
1030 <GIC_SPI 971 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
1031 <GIC_SPI 972 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
1032 <GIC_SPI 973 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
1033 <GIC_SPI 974 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
1034 <GIC_SPI 975 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
1035 <GIC_SPI 976 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
1036 <GIC_SPI 977 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
1037 <GIC_SPI 978 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
1038 interrupt-names = "er 979 interrupt-names = "error",
1039 "ch0" 980 "ch0", "ch1", "ch2", "ch3",
1040 "ch4" 981 "ch4", "ch5", "ch6", "ch7",
1041 "ch8" 982 "ch8", "ch9", "ch10", "ch11",
1042 "ch12 983 "ch12", "ch13", "ch14", "ch15";
1043 clocks = <&cpg CPG_MO 984 clocks = <&cpg CPG_MOD 217>;
1044 clock-names = "fck"; 985 clock-names = "fck";
1045 power-domains = <&sys 986 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1046 resets = <&cpg 217>; 987 resets = <&cpg 217>;
1047 #dma-cells = <1>; 988 #dma-cells = <1>;
1048 dma-channels = <16>; 989 dma-channels = <16>;
1049 iommus = <&ipmmu_ds1 990 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
1050 <&ipmmu_ds1 18 991 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
1051 <&ipmmu_ds1 20 992 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
1052 <&ipmmu_ds1 22 993 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
1053 <&ipmmu_ds1 24 994 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
1054 <&ipmmu_ds1 26 995 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
1055 <&ipmmu_ds1 28 996 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
1056 <&ipmmu_ds1 30 997 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
1057 }; 998 };
1058 999
1059 ipmmu_ds0: iommu@e6740000 { 1000 ipmmu_ds0: iommu@e6740000 {
1060 compatible = "renesas 1001 compatible = "renesas,ipmmu-r8a7796";
1061 reg = <0 0xe6740000 0 1002 reg = <0 0xe6740000 0 0x1000>;
1062 renesas,ipmmu-main = 1003 renesas,ipmmu-main = <&ipmmu_mm 0>;
1063 power-domains = <&sys 1004 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1064 #iommu-cells = <1>; 1005 #iommu-cells = <1>;
1065 }; 1006 };
1066 1007
1067 ipmmu_ds1: iommu@e7740000 { 1008 ipmmu_ds1: iommu@e7740000 {
1068 compatible = "renesas 1009 compatible = "renesas,ipmmu-r8a7796";
1069 reg = <0 0xe7740000 0 1010 reg = <0 0xe7740000 0 0x1000>;
1070 renesas,ipmmu-main = 1011 renesas,ipmmu-main = <&ipmmu_mm 1>;
1071 power-domains = <&sys 1012 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1072 #iommu-cells = <1>; 1013 #iommu-cells = <1>;
1073 }; 1014 };
1074 1015
1075 ipmmu_hc: iommu@e6570000 { 1016 ipmmu_hc: iommu@e6570000 {
1076 compatible = "renesas 1017 compatible = "renesas,ipmmu-r8a7796";
1077 reg = <0 0xe6570000 0 1018 reg = <0 0xe6570000 0 0x1000>;
1078 renesas,ipmmu-main = 1019 renesas,ipmmu-main = <&ipmmu_mm 2>;
1079 power-domains = <&sys 1020 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1080 #iommu-cells = <1>; 1021 #iommu-cells = <1>;
1081 }; 1022 };
1082 1023
1083 ipmmu_ir: iommu@ff8b0000 { 1024 ipmmu_ir: iommu@ff8b0000 {
1084 compatible = "renesas 1025 compatible = "renesas,ipmmu-r8a7796";
1085 reg = <0 0xff8b0000 0 1026 reg = <0 0xff8b0000 0 0x1000>;
1086 renesas,ipmmu-main = 1027 renesas,ipmmu-main = <&ipmmu_mm 3>;
1087 power-domains = <&sys 1028 power-domains = <&sysc R8A7796_PD_A3IR>;
1088 #iommu-cells = <1>; 1029 #iommu-cells = <1>;
1089 }; 1030 };
1090 1031
1091 ipmmu_mm: iommu@e67b0000 { 1032 ipmmu_mm: iommu@e67b0000 {
1092 compatible = "renesas 1033 compatible = "renesas,ipmmu-r8a7796";
1093 reg = <0 0xe67b0000 0 1034 reg = <0 0xe67b0000 0 0x1000>;
1094 interrupts = <GIC_SPI 1035 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
1095 <GIC_SPI 1036 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
1096 power-domains = <&sys 1037 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1097 #iommu-cells = <1>; 1038 #iommu-cells = <1>;
1098 }; 1039 };
1099 1040
1100 ipmmu_mp: iommu@ec670000 { 1041 ipmmu_mp: iommu@ec670000 {
1101 compatible = "renesas 1042 compatible = "renesas,ipmmu-r8a7796";
1102 reg = <0 0xec670000 0 1043 reg = <0 0xec670000 0 0x1000>;
1103 renesas,ipmmu-main = 1044 renesas,ipmmu-main = <&ipmmu_mm 4>;
1104 power-domains = <&sys 1045 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1105 #iommu-cells = <1>; 1046 #iommu-cells = <1>;
1106 }; 1047 };
1107 1048
1108 ipmmu_pv0: iommu@fd800000 { 1049 ipmmu_pv0: iommu@fd800000 {
1109 compatible = "renesas 1050 compatible = "renesas,ipmmu-r8a7796";
1110 reg = <0 0xfd800000 0 1051 reg = <0 0xfd800000 0 0x1000>;
1111 renesas,ipmmu-main = 1052 renesas,ipmmu-main = <&ipmmu_mm 5>;
1112 power-domains = <&sys 1053 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1113 #iommu-cells = <1>; 1054 #iommu-cells = <1>;
1114 }; 1055 };
1115 1056
1116 ipmmu_pv1: iommu@fd950000 { 1057 ipmmu_pv1: iommu@fd950000 {
1117 compatible = "renesas 1058 compatible = "renesas,ipmmu-r8a7796";
1118 reg = <0 0xfd950000 0 1059 reg = <0 0xfd950000 0 0x1000>;
1119 renesas,ipmmu-main = 1060 renesas,ipmmu-main = <&ipmmu_mm 6>;
1120 power-domains = <&sys 1061 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1121 #iommu-cells = <1>; 1062 #iommu-cells = <1>;
1122 }; 1063 };
1123 1064
1124 ipmmu_rt: iommu@ffc80000 { 1065 ipmmu_rt: iommu@ffc80000 {
1125 compatible = "renesas 1066 compatible = "renesas,ipmmu-r8a7796";
1126 reg = <0 0xffc80000 0 1067 reg = <0 0xffc80000 0 0x1000>;
1127 renesas,ipmmu-main = 1068 renesas,ipmmu-main = <&ipmmu_mm 7>;
1128 power-domains = <&sys 1069 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1129 #iommu-cells = <1>; 1070 #iommu-cells = <1>;
1130 }; 1071 };
1131 1072
1132 ipmmu_vc0: iommu@fe6b0000 { 1073 ipmmu_vc0: iommu@fe6b0000 {
1133 compatible = "renesas 1074 compatible = "renesas,ipmmu-r8a7796";
1134 reg = <0 0xfe6b0000 0 1075 reg = <0 0xfe6b0000 0 0x1000>;
1135 renesas,ipmmu-main = 1076 renesas,ipmmu-main = <&ipmmu_mm 8>;
1136 power-domains = <&sys 1077 power-domains = <&sysc R8A7796_PD_A3VC>;
1137 #iommu-cells = <1>; 1078 #iommu-cells = <1>;
1138 }; 1079 };
1139 1080
1140 ipmmu_vi0: iommu@febd0000 { 1081 ipmmu_vi0: iommu@febd0000 {
1141 compatible = "renesas 1082 compatible = "renesas,ipmmu-r8a7796";
1142 reg = <0 0xfebd0000 0 1083 reg = <0 0xfebd0000 0 0x1000>;
1143 renesas,ipmmu-main = 1084 renesas,ipmmu-main = <&ipmmu_mm 9>;
1144 power-domains = <&sys 1085 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1145 #iommu-cells = <1>; 1086 #iommu-cells = <1>;
1146 }; 1087 };
1147 1088
1148 avb: ethernet@e6800000 { 1089 avb: ethernet@e6800000 {
1149 compatible = "renesas 1090 compatible = "renesas,etheravb-r8a7796",
1150 "renesas 1091 "renesas,etheravb-rcar-gen3";
1151 reg = <0 0xe6800000 0 1092 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
1152 interrupts = <GIC_SPI 1093 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
1153 <GIC_SPI 1094 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1154 <GIC_SPI 1095 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
1155 <GIC_SPI 1096 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
1156 <GIC_SPI 1097 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
1157 <GIC_SPI 1098 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
1158 <GIC_SPI 1099 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
1159 <GIC_SPI 1100 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
1160 <GIC_SPI 1101 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
1161 <GIC_SPI 1102 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
1162 <GIC_SPI 1103 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
1163 <GIC_SPI 1104 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
1164 <GIC_SPI 1105 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
1165 <GIC_SPI 1106 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
1166 <GIC_SPI 1107 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
1167 <GIC_SPI 1108 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
1168 <GIC_SPI 1109 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
1169 <GIC_SPI 1110 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
1170 <GIC_SPI 1111 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
1171 <GIC_SPI 1112 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
1172 <GIC_SPI 1113 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
1173 <GIC_SPI 1114 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
1174 <GIC_SPI 1115 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
1175 <GIC_SPI 1116 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
1176 <GIC_SPI 1117 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
1177 interrupt-names = "ch 1118 interrupt-names = "ch0", "ch1", "ch2", "ch3",
1178 "ch 1119 "ch4", "ch5", "ch6", "ch7",
1179 "ch 1120 "ch8", "ch9", "ch10", "ch11",
1180 "ch 1121 "ch12", "ch13", "ch14", "ch15",
1181 "ch 1122 "ch16", "ch17", "ch18", "ch19",
1182 "ch 1123 "ch20", "ch21", "ch22", "ch23",
1183 "ch 1124 "ch24";
1184 clocks = <&cpg CPG_MO 1125 clocks = <&cpg CPG_MOD 812>;
1185 clock-names = "fck"; <<
1186 power-domains = <&sys 1126 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1187 resets = <&cpg 812>; 1127 resets = <&cpg 812>;
1188 phy-mode = "rgmii"; 1128 phy-mode = "rgmii";
1189 rx-internal-delay-ps <<
1190 tx-internal-delay-ps <<
1191 iommus = <&ipmmu_ds0 1129 iommus = <&ipmmu_ds0 16>;
1192 #address-cells = <1>; 1130 #address-cells = <1>;
1193 #size-cells = <0>; 1131 #size-cells = <0>;
1194 status = "disabled"; 1132 status = "disabled";
1195 }; 1133 };
1196 1134
1197 can0: can@e6c30000 { 1135 can0: can@e6c30000 {
1198 compatible = "renesas 1136 compatible = "renesas,can-r8a7796",
1199 "renesas 1137 "renesas,rcar-gen3-can";
1200 reg = <0 0xe6c30000 0 1138 reg = <0 0xe6c30000 0 0x1000>;
1201 interrupts = <GIC_SPI 1139 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
1202 clocks = <&cpg CPG_MO 1140 clocks = <&cpg CPG_MOD 916>,
1203 <&cpg CPG_CORE 1141 <&cpg CPG_CORE R8A7796_CLK_CANFD>,
1204 <&can_clk>; 1142 <&can_clk>;
1205 clock-names = "clkp1" 1143 clock-names = "clkp1", "clkp2", "can_clk";
1206 assigned-clocks = <&c 1144 assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>;
1207 assigned-clock-rates 1145 assigned-clock-rates = <40000000>;
1208 power-domains = <&sys 1146 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1209 resets = <&cpg 916>; 1147 resets = <&cpg 916>;
1210 status = "disabled"; 1148 status = "disabled";
1211 }; 1149 };
1212 1150
1213 can1: can@e6c38000 { 1151 can1: can@e6c38000 {
1214 compatible = "renesas 1152 compatible = "renesas,can-r8a7796",
1215 "renesas 1153 "renesas,rcar-gen3-can";
1216 reg = <0 0xe6c38000 0 1154 reg = <0 0xe6c38000 0 0x1000>;
1217 interrupts = <GIC_SPI 1155 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
1218 clocks = <&cpg CPG_MO 1156 clocks = <&cpg CPG_MOD 915>,
1219 <&cpg CPG_CORE 1157 <&cpg CPG_CORE R8A7796_CLK_CANFD>,
1220 <&can_clk>; 1158 <&can_clk>;
1221 clock-names = "clkp1" 1159 clock-names = "clkp1", "clkp2", "can_clk";
1222 assigned-clocks = <&c 1160 assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>;
1223 assigned-clock-rates 1161 assigned-clock-rates = <40000000>;
1224 power-domains = <&sys 1162 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1225 resets = <&cpg 915>; 1163 resets = <&cpg 915>;
1226 status = "disabled"; 1164 status = "disabled";
1227 }; 1165 };
1228 1166
1229 canfd: can@e66c0000 { 1167 canfd: can@e66c0000 {
1230 compatible = "renesas 1168 compatible = "renesas,r8a7796-canfd",
1231 "renesas 1169 "renesas,rcar-gen3-canfd";
1232 reg = <0 0xe66c0000 0 1170 reg = <0 0xe66c0000 0 0x8000>;
1233 interrupts = <GIC_SPI 1171 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
1234 <GIC_SPI 3 1172 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1235 interrupt-names = "ch <<
1236 clocks = <&cpg CPG_MO 1173 clocks = <&cpg CPG_MOD 914>,
1237 <&cpg CPG_CORE 1174 <&cpg CPG_CORE R8A7796_CLK_CANFD>,
1238 <&can_clk>; 1175 <&can_clk>;
1239 clock-names = "fck", 1176 clock-names = "fck", "canfd", "can_clk";
1240 assigned-clocks = <&c 1177 assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>;
1241 assigned-clock-rates 1178 assigned-clock-rates = <40000000>;
1242 power-domains = <&sys 1179 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1243 resets = <&cpg 914>; 1180 resets = <&cpg 914>;
1244 status = "disabled"; 1181 status = "disabled";
1245 1182
1246 channel0 { 1183 channel0 {
1247 status = "dis 1184 status = "disabled";
1248 }; 1185 };
1249 1186
1250 channel1 { 1187 channel1 {
1251 status = "dis 1188 status = "disabled";
1252 }; 1189 };
1253 }; 1190 };
1254 1191
1255 pwm0: pwm@e6e30000 { 1192 pwm0: pwm@e6e30000 {
1256 compatible = "renesas 1193 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
1257 reg = <0 0xe6e30000 0 1194 reg = <0 0xe6e30000 0 8>;
1258 #pwm-cells = <2>; 1195 #pwm-cells = <2>;
1259 clocks = <&cpg CPG_MO 1196 clocks = <&cpg CPG_MOD 523>;
1260 resets = <&cpg 523>; 1197 resets = <&cpg 523>;
1261 power-domains = <&sys 1198 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1262 status = "disabled"; 1199 status = "disabled";
1263 }; 1200 };
1264 1201
1265 pwm1: pwm@e6e31000 { 1202 pwm1: pwm@e6e31000 {
1266 compatible = "renesas 1203 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
1267 reg = <0 0xe6e31000 0 1204 reg = <0 0xe6e31000 0 8>;
1268 #pwm-cells = <2>; 1205 #pwm-cells = <2>;
1269 clocks = <&cpg CPG_MO 1206 clocks = <&cpg CPG_MOD 523>;
1270 resets = <&cpg 523>; 1207 resets = <&cpg 523>;
1271 power-domains = <&sys 1208 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1272 status = "disabled"; 1209 status = "disabled";
1273 }; 1210 };
1274 1211
1275 pwm2: pwm@e6e32000 { 1212 pwm2: pwm@e6e32000 {
1276 compatible = "renesas 1213 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
1277 reg = <0 0xe6e32000 0 1214 reg = <0 0xe6e32000 0 8>;
1278 #pwm-cells = <2>; 1215 #pwm-cells = <2>;
1279 clocks = <&cpg CPG_MO 1216 clocks = <&cpg CPG_MOD 523>;
1280 resets = <&cpg 523>; 1217 resets = <&cpg 523>;
1281 power-domains = <&sys 1218 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1282 status = "disabled"; 1219 status = "disabled";
1283 }; 1220 };
1284 1221
1285 pwm3: pwm@e6e33000 { 1222 pwm3: pwm@e6e33000 {
1286 compatible = "renesas 1223 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
1287 reg = <0 0xe6e33000 0 1224 reg = <0 0xe6e33000 0 8>;
1288 #pwm-cells = <2>; 1225 #pwm-cells = <2>;
1289 clocks = <&cpg CPG_MO 1226 clocks = <&cpg CPG_MOD 523>;
1290 resets = <&cpg 523>; 1227 resets = <&cpg 523>;
1291 power-domains = <&sys 1228 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1292 status = "disabled"; 1229 status = "disabled";
1293 }; 1230 };
1294 1231
1295 pwm4: pwm@e6e34000 { 1232 pwm4: pwm@e6e34000 {
1296 compatible = "renesas 1233 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
1297 reg = <0 0xe6e34000 0 1234 reg = <0 0xe6e34000 0 8>;
1298 #pwm-cells = <2>; 1235 #pwm-cells = <2>;
1299 clocks = <&cpg CPG_MO 1236 clocks = <&cpg CPG_MOD 523>;
1300 resets = <&cpg 523>; 1237 resets = <&cpg 523>;
1301 power-domains = <&sys 1238 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1302 status = "disabled"; 1239 status = "disabled";
1303 }; 1240 };
1304 1241
1305 pwm5: pwm@e6e35000 { 1242 pwm5: pwm@e6e35000 {
1306 compatible = "renesas 1243 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
1307 reg = <0 0xe6e35000 0 1244 reg = <0 0xe6e35000 0 8>;
1308 #pwm-cells = <2>; 1245 #pwm-cells = <2>;
1309 clocks = <&cpg CPG_MO 1246 clocks = <&cpg CPG_MOD 523>;
1310 resets = <&cpg 523>; 1247 resets = <&cpg 523>;
1311 power-domains = <&sys 1248 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1312 status = "disabled"; 1249 status = "disabled";
1313 }; 1250 };
1314 1251
1315 pwm6: pwm@e6e36000 { 1252 pwm6: pwm@e6e36000 {
1316 compatible = "renesas 1253 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
1317 reg = <0 0xe6e36000 0 1254 reg = <0 0xe6e36000 0 8>;
1318 #pwm-cells = <2>; 1255 #pwm-cells = <2>;
1319 clocks = <&cpg CPG_MO 1256 clocks = <&cpg CPG_MOD 523>;
1320 resets = <&cpg 523>; 1257 resets = <&cpg 523>;
1321 power-domains = <&sys 1258 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1322 status = "disabled"; 1259 status = "disabled";
1323 }; 1260 };
1324 1261
1325 scif0: serial@e6e60000 { 1262 scif0: serial@e6e60000 {
1326 compatible = "renesas 1263 compatible = "renesas,scif-r8a7796",
1327 "renesas 1264 "renesas,rcar-gen3-scif", "renesas,scif";
1328 reg = <0 0xe6e60000 0 1265 reg = <0 0xe6e60000 0 64>;
1329 interrupts = <GIC_SPI 1266 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
1330 clocks = <&cpg CPG_MO 1267 clocks = <&cpg CPG_MOD 207>,
1331 <&cpg CPG_CO 1268 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
1332 <&scif_clk>; 1269 <&scif_clk>;
1333 clock-names = "fck", 1270 clock-names = "fck", "brg_int", "scif_clk";
1334 dmas = <&dmac1 0x51>, 1271 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1335 <&dmac2 0x51>, 1272 <&dmac2 0x51>, <&dmac2 0x50>;
1336 dma-names = "tx", "rx 1273 dma-names = "tx", "rx", "tx", "rx";
1337 power-domains = <&sys 1274 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1338 resets = <&cpg 207>; 1275 resets = <&cpg 207>;
1339 status = "disabled"; 1276 status = "disabled";
1340 }; 1277 };
1341 1278
1342 scif1: serial@e6e68000 { 1279 scif1: serial@e6e68000 {
1343 compatible = "renesas 1280 compatible = "renesas,scif-r8a7796",
1344 "renesas 1281 "renesas,rcar-gen3-scif", "renesas,scif";
1345 reg = <0 0xe6e68000 0 1282 reg = <0 0xe6e68000 0 64>;
1346 interrupts = <GIC_SPI 1283 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
1347 clocks = <&cpg CPG_MO 1284 clocks = <&cpg CPG_MOD 206>,
1348 <&cpg CPG_CO 1285 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
1349 <&scif_clk>; 1286 <&scif_clk>;
1350 clock-names = "fck", 1287 clock-names = "fck", "brg_int", "scif_clk";
1351 dmas = <&dmac1 0x53>, 1288 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1352 <&dmac2 0x53>, 1289 <&dmac2 0x53>, <&dmac2 0x52>;
1353 dma-names = "tx", "rx 1290 dma-names = "tx", "rx", "tx", "rx";
1354 power-domains = <&sys 1291 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1355 resets = <&cpg 206>; 1292 resets = <&cpg 206>;
1356 status = "disabled"; 1293 status = "disabled";
1357 }; 1294 };
1358 1295
1359 scif2: serial@e6e88000 { 1296 scif2: serial@e6e88000 {
1360 compatible = "renesas 1297 compatible = "renesas,scif-r8a7796",
1361 "renesas 1298 "renesas,rcar-gen3-scif", "renesas,scif";
1362 reg = <0 0xe6e88000 0 1299 reg = <0 0xe6e88000 0 64>;
1363 interrupts = <GIC_SPI 1300 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
1364 clocks = <&cpg CPG_MO 1301 clocks = <&cpg CPG_MOD 310>,
1365 <&cpg CPG_CO 1302 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
1366 <&scif_clk>; 1303 <&scif_clk>;
1367 clock-names = "fck", 1304 clock-names = "fck", "brg_int", "scif_clk";
1368 dmas = <&dmac1 0x13>, 1305 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1369 <&dmac2 0x13>, 1306 <&dmac2 0x13>, <&dmac2 0x12>;
1370 dma-names = "tx", "rx 1307 dma-names = "tx", "rx", "tx", "rx";
1371 power-domains = <&sys 1308 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1372 resets = <&cpg 310>; 1309 resets = <&cpg 310>;
1373 status = "disabled"; 1310 status = "disabled";
1374 }; 1311 };
1375 1312
1376 scif3: serial@e6c50000 { 1313 scif3: serial@e6c50000 {
1377 compatible = "renesas 1314 compatible = "renesas,scif-r8a7796",
1378 "renesas 1315 "renesas,rcar-gen3-scif", "renesas,scif";
1379 reg = <0 0xe6c50000 0 1316 reg = <0 0xe6c50000 0 64>;
1380 interrupts = <GIC_SPI 1317 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1381 clocks = <&cpg CPG_MO 1318 clocks = <&cpg CPG_MOD 204>,
1382 <&cpg CPG_CO 1319 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
1383 <&scif_clk>; 1320 <&scif_clk>;
1384 clock-names = "fck", 1321 clock-names = "fck", "brg_int", "scif_clk";
1385 dmas = <&dmac0 0x57>, 1322 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1386 dma-names = "tx", "rx 1323 dma-names = "tx", "rx";
1387 power-domains = <&sys 1324 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1388 resets = <&cpg 204>; 1325 resets = <&cpg 204>;
1389 status = "disabled"; 1326 status = "disabled";
1390 }; 1327 };
1391 1328
1392 scif4: serial@e6c40000 { 1329 scif4: serial@e6c40000 {
1393 compatible = "renesas 1330 compatible = "renesas,scif-r8a7796",
1394 "renesas 1331 "renesas,rcar-gen3-scif", "renesas,scif";
1395 reg = <0 0xe6c40000 0 1332 reg = <0 0xe6c40000 0 64>;
1396 interrupts = <GIC_SPI 1333 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1397 clocks = <&cpg CPG_MO 1334 clocks = <&cpg CPG_MOD 203>,
1398 <&cpg CPG_CO 1335 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
1399 <&scif_clk>; 1336 <&scif_clk>;
1400 clock-names = "fck", 1337 clock-names = "fck", "brg_int", "scif_clk";
1401 dmas = <&dmac0 0x59>, 1338 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1402 dma-names = "tx", "rx 1339 dma-names = "tx", "rx";
1403 power-domains = <&sys 1340 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1404 resets = <&cpg 203>; 1341 resets = <&cpg 203>;
1405 status = "disabled"; 1342 status = "disabled";
1406 }; 1343 };
1407 1344
1408 scif5: serial@e6f30000 { 1345 scif5: serial@e6f30000 {
1409 compatible = "renesas 1346 compatible = "renesas,scif-r8a7796",
1410 "renesas 1347 "renesas,rcar-gen3-scif", "renesas,scif";
1411 reg = <0 0xe6f30000 0 1348 reg = <0 0xe6f30000 0 64>;
1412 interrupts = <GIC_SPI 1349 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1413 clocks = <&cpg CPG_MO 1350 clocks = <&cpg CPG_MOD 202>,
1414 <&cpg CPG_CO 1351 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
1415 <&scif_clk>; 1352 <&scif_clk>;
1416 clock-names = "fck", 1353 clock-names = "fck", "brg_int", "scif_clk";
1417 dmas = <&dmac1 0x5b>, 1354 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
1418 <&dmac2 0x5b>, 1355 <&dmac2 0x5b>, <&dmac2 0x5a>;
1419 dma-names = "tx", "rx 1356 dma-names = "tx", "rx", "tx", "rx";
1420 power-domains = <&sys 1357 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1421 resets = <&cpg 202>; 1358 resets = <&cpg 202>;
1422 status = "disabled"; 1359 status = "disabled";
1423 }; 1360 };
1424 1361
1425 tpu: pwm@e6e80000 { 1362 tpu: pwm@e6e80000 {
1426 compatible = "renesas 1363 compatible = "renesas,tpu-r8a7796", "renesas,tpu";
1427 reg = <0 0xe6e80000 0 1364 reg = <0 0xe6e80000 0 0x148>;
1428 interrupts = <GIC_SPI 1365 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
1429 clocks = <&cpg CPG_MO 1366 clocks = <&cpg CPG_MOD 304>;
1430 power-domains = <&sys 1367 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1431 resets = <&cpg 304>; 1368 resets = <&cpg 304>;
1432 #pwm-cells = <3>; 1369 #pwm-cells = <3>;
1433 status = "disabled"; 1370 status = "disabled";
1434 }; 1371 };
1435 1372
1436 msiof0: spi@e6e90000 { 1373 msiof0: spi@e6e90000 {
1437 compatible = "renesas 1374 compatible = "renesas,msiof-r8a7796",
1438 "renesas 1375 "renesas,rcar-gen3-msiof";
1439 reg = <0 0xe6e90000 0 1376 reg = <0 0xe6e90000 0 0x0064>;
1440 interrupts = <GIC_SPI 1377 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1441 clocks = <&cpg CPG_MO 1378 clocks = <&cpg CPG_MOD 211>;
1442 dmas = <&dmac1 0x41>, 1379 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1443 <&dmac2 0x41>, 1380 <&dmac2 0x41>, <&dmac2 0x40>;
1444 dma-names = "tx", "rx 1381 dma-names = "tx", "rx", "tx", "rx";
1445 power-domains = <&sys 1382 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1446 resets = <&cpg 211>; 1383 resets = <&cpg 211>;
1447 #address-cells = <1>; 1384 #address-cells = <1>;
1448 #size-cells = <0>; 1385 #size-cells = <0>;
1449 status = "disabled"; 1386 status = "disabled";
1450 }; 1387 };
1451 1388
1452 msiof1: spi@e6ea0000 { 1389 msiof1: spi@e6ea0000 {
1453 compatible = "renesas 1390 compatible = "renesas,msiof-r8a7796",
1454 "renesas 1391 "renesas,rcar-gen3-msiof";
1455 reg = <0 0xe6ea0000 0 1392 reg = <0 0xe6ea0000 0 0x0064>;
1456 interrupts = <GIC_SPI 1393 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1457 clocks = <&cpg CPG_MO 1394 clocks = <&cpg CPG_MOD 210>;
1458 dmas = <&dmac1 0x43>, 1395 dmas = <&dmac1 0x43>, <&dmac1 0x42>,
1459 <&dmac2 0x43>, 1396 <&dmac2 0x43>, <&dmac2 0x42>;
1460 dma-names = "tx", "rx 1397 dma-names = "tx", "rx", "tx", "rx";
1461 power-domains = <&sys 1398 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1462 resets = <&cpg 210>; 1399 resets = <&cpg 210>;
1463 #address-cells = <1>; 1400 #address-cells = <1>;
1464 #size-cells = <0>; 1401 #size-cells = <0>;
1465 status = "disabled"; 1402 status = "disabled";
1466 }; 1403 };
1467 1404
1468 msiof2: spi@e6c00000 { 1405 msiof2: spi@e6c00000 {
1469 compatible = "renesas 1406 compatible = "renesas,msiof-r8a7796",
1470 "renesas 1407 "renesas,rcar-gen3-msiof";
1471 reg = <0 0xe6c00000 0 1408 reg = <0 0xe6c00000 0 0x0064>;
1472 interrupts = <GIC_SPI 1409 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1473 clocks = <&cpg CPG_MO 1410 clocks = <&cpg CPG_MOD 209>;
1474 dmas = <&dmac0 0x45>, 1411 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1475 dma-names = "tx", "rx 1412 dma-names = "tx", "rx";
1476 power-domains = <&sys 1413 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1477 resets = <&cpg 209>; 1414 resets = <&cpg 209>;
1478 #address-cells = <1>; 1415 #address-cells = <1>;
1479 #size-cells = <0>; 1416 #size-cells = <0>;
1480 status = "disabled"; 1417 status = "disabled";
1481 }; 1418 };
1482 1419
1483 msiof3: spi@e6c10000 { 1420 msiof3: spi@e6c10000 {
1484 compatible = "renesas 1421 compatible = "renesas,msiof-r8a7796",
1485 "renesas 1422 "renesas,rcar-gen3-msiof";
1486 reg = <0 0xe6c10000 0 1423 reg = <0 0xe6c10000 0 0x0064>;
1487 interrupts = <GIC_SPI 1424 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1488 clocks = <&cpg CPG_MO 1425 clocks = <&cpg CPG_MOD 208>;
1489 dmas = <&dmac0 0x47>, 1426 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1490 dma-names = "tx", "rx 1427 dma-names = "tx", "rx";
1491 power-domains = <&sys 1428 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1492 resets = <&cpg 208>; 1429 resets = <&cpg 208>;
1493 #address-cells = <1>; 1430 #address-cells = <1>;
1494 #size-cells = <0>; 1431 #size-cells = <0>;
1495 status = "disabled"; 1432 status = "disabled";
1496 }; 1433 };
1497 1434
1498 vin0: video@e6ef0000 { 1435 vin0: video@e6ef0000 {
1499 compatible = "renesas 1436 compatible = "renesas,vin-r8a7796";
1500 reg = <0 0xe6ef0000 0 1437 reg = <0 0xe6ef0000 0 0x1000>;
1501 interrupts = <GIC_SPI 1438 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
1502 clocks = <&cpg CPG_MO 1439 clocks = <&cpg CPG_MOD 811>;
1503 power-domains = <&sys 1440 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1504 resets = <&cpg 811>; 1441 resets = <&cpg 811>;
1505 renesas,id = <0>; 1442 renesas,id = <0>;
1506 status = "disabled"; 1443 status = "disabled";
1507 1444
1508 ports { 1445 ports {
1509 #address-cell 1446 #address-cells = <1>;
1510 #size-cells = 1447 #size-cells = <0>;
1511 1448
1512 port@1 { 1449 port@1 {
1513 #addr 1450 #address-cells = <1>;
1514 #size 1451 #size-cells = <0>;
1515 1452
1516 reg = 1453 reg = <1>;
1517 1454
1518 vin0c 1455 vin0csi20: endpoint@0 {
1519 1456 reg = <0>;
1520 1457 remote-endpoint = <&csi20vin0>;
1521 }; 1458 };
1522 vin0c 1459 vin0csi40: endpoint@2 {
1523 1460 reg = <2>;
1524 1461 remote-endpoint = <&csi40vin0>;
1525 }; 1462 };
1526 }; 1463 };
1527 }; 1464 };
1528 }; 1465 };
1529 1466
1530 vin1: video@e6ef1000 { 1467 vin1: video@e6ef1000 {
1531 compatible = "renesas 1468 compatible = "renesas,vin-r8a7796";
1532 reg = <0 0xe6ef1000 0 1469 reg = <0 0xe6ef1000 0 0x1000>;
1533 interrupts = <GIC_SPI 1470 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
1534 clocks = <&cpg CPG_MO 1471 clocks = <&cpg CPG_MOD 810>;
1535 power-domains = <&sys 1472 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1536 resets = <&cpg 810>; 1473 resets = <&cpg 810>;
1537 renesas,id = <1>; 1474 renesas,id = <1>;
1538 status = "disabled"; 1475 status = "disabled";
1539 1476
1540 ports { 1477 ports {
1541 #address-cell 1478 #address-cells = <1>;
1542 #size-cells = 1479 #size-cells = <0>;
1543 1480
1544 port@1 { 1481 port@1 {
1545 #addr 1482 #address-cells = <1>;
1546 #size 1483 #size-cells = <0>;
1547 1484
1548 reg = 1485 reg = <1>;
1549 1486
1550 vin1c 1487 vin1csi20: endpoint@0 {
1551 1488 reg = <0>;
1552 1489 remote-endpoint = <&csi20vin1>;
1553 }; 1490 };
1554 vin1c 1491 vin1csi40: endpoint@2 {
1555 1492 reg = <2>;
1556 1493 remote-endpoint = <&csi40vin1>;
1557 }; 1494 };
1558 }; 1495 };
1559 }; 1496 };
1560 }; 1497 };
1561 1498
1562 vin2: video@e6ef2000 { 1499 vin2: video@e6ef2000 {
1563 compatible = "renesas 1500 compatible = "renesas,vin-r8a7796";
1564 reg = <0 0xe6ef2000 0 1501 reg = <0 0xe6ef2000 0 0x1000>;
1565 interrupts = <GIC_SPI 1502 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1566 clocks = <&cpg CPG_MO 1503 clocks = <&cpg CPG_MOD 809>;
1567 power-domains = <&sys 1504 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1568 resets = <&cpg 809>; 1505 resets = <&cpg 809>;
1569 renesas,id = <2>; 1506 renesas,id = <2>;
1570 status = "disabled"; 1507 status = "disabled";
1571 1508
1572 ports { 1509 ports {
1573 #address-cell 1510 #address-cells = <1>;
1574 #size-cells = 1511 #size-cells = <0>;
1575 1512
1576 port@1 { 1513 port@1 {
1577 #addr 1514 #address-cells = <1>;
1578 #size 1515 #size-cells = <0>;
1579 1516
1580 reg = 1517 reg = <1>;
1581 1518
1582 vin2c 1519 vin2csi20: endpoint@0 {
1583 1520 reg = <0>;
1584 1521 remote-endpoint = <&csi20vin2>;
1585 }; 1522 };
1586 vin2c 1523 vin2csi40: endpoint@2 {
1587 1524 reg = <2>;
1588 1525 remote-endpoint = <&csi40vin2>;
1589 }; 1526 };
1590 }; 1527 };
1591 }; 1528 };
1592 }; 1529 };
1593 1530
1594 vin3: video@e6ef3000 { 1531 vin3: video@e6ef3000 {
1595 compatible = "renesas 1532 compatible = "renesas,vin-r8a7796";
1596 reg = <0 0xe6ef3000 0 1533 reg = <0 0xe6ef3000 0 0x1000>;
1597 interrupts = <GIC_SPI 1534 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
1598 clocks = <&cpg CPG_MO 1535 clocks = <&cpg CPG_MOD 808>;
1599 power-domains = <&sys 1536 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1600 resets = <&cpg 808>; 1537 resets = <&cpg 808>;
1601 renesas,id = <3>; 1538 renesas,id = <3>;
1602 status = "disabled"; 1539 status = "disabled";
1603 1540
1604 ports { 1541 ports {
1605 #address-cell 1542 #address-cells = <1>;
1606 #size-cells = 1543 #size-cells = <0>;
1607 1544
1608 port@1 { 1545 port@1 {
1609 #addr 1546 #address-cells = <1>;
1610 #size 1547 #size-cells = <0>;
1611 1548
1612 reg = 1549 reg = <1>;
1613 1550
1614 vin3c 1551 vin3csi20: endpoint@0 {
1615 1552 reg = <0>;
1616 1553 remote-endpoint = <&csi20vin3>;
1617 }; 1554 };
1618 vin3c 1555 vin3csi40: endpoint@2 {
1619 1556 reg = <2>;
1620 1557 remote-endpoint = <&csi40vin3>;
1621 }; 1558 };
1622 }; 1559 };
1623 }; 1560 };
1624 }; 1561 };
1625 1562
1626 vin4: video@e6ef4000 { 1563 vin4: video@e6ef4000 {
1627 compatible = "renesas 1564 compatible = "renesas,vin-r8a7796";
1628 reg = <0 0xe6ef4000 0 1565 reg = <0 0xe6ef4000 0 0x1000>;
1629 interrupts = <GIC_SPI 1566 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
1630 clocks = <&cpg CPG_MO 1567 clocks = <&cpg CPG_MOD 807>;
1631 power-domains = <&sys 1568 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1632 resets = <&cpg 807>; 1569 resets = <&cpg 807>;
1633 renesas,id = <4>; 1570 renesas,id = <4>;
1634 status = "disabled"; 1571 status = "disabled";
1635 1572
1636 ports { 1573 ports {
1637 #address-cell 1574 #address-cells = <1>;
1638 #size-cells = 1575 #size-cells = <0>;
1639 1576
1640 port@1 { 1577 port@1 {
1641 #addr 1578 #address-cells = <1>;
1642 #size 1579 #size-cells = <0>;
1643 1580
1644 reg = 1581 reg = <1>;
1645 1582
1646 vin4c 1583 vin4csi20: endpoint@0 {
1647 1584 reg = <0>;
1648 1585 remote-endpoint = <&csi20vin4>;
1649 }; 1586 };
1650 vin4c 1587 vin4csi40: endpoint@2 {
1651 1588 reg = <2>;
1652 1589 remote-endpoint = <&csi40vin4>;
1653 }; 1590 };
1654 }; 1591 };
1655 }; 1592 };
1656 }; 1593 };
1657 1594
1658 vin5: video@e6ef5000 { 1595 vin5: video@e6ef5000 {
1659 compatible = "renesas 1596 compatible = "renesas,vin-r8a7796";
1660 reg = <0 0xe6ef5000 0 1597 reg = <0 0xe6ef5000 0 0x1000>;
1661 interrupts = <GIC_SPI 1598 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
1662 clocks = <&cpg CPG_MO 1599 clocks = <&cpg CPG_MOD 806>;
1663 power-domains = <&sys 1600 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1664 resets = <&cpg 806>; 1601 resets = <&cpg 806>;
1665 renesas,id = <5>; 1602 renesas,id = <5>;
1666 status = "disabled"; 1603 status = "disabled";
1667 1604
1668 ports { 1605 ports {
1669 #address-cell 1606 #address-cells = <1>;
1670 #size-cells = 1607 #size-cells = <0>;
1671 1608
1672 port@1 { 1609 port@1 {
1673 #addr 1610 #address-cells = <1>;
1674 #size 1611 #size-cells = <0>;
1675 1612
1676 reg = 1613 reg = <1>;
1677 1614
1678 vin5c 1615 vin5csi20: endpoint@0 {
1679 1616 reg = <0>;
1680 1617 remote-endpoint = <&csi20vin5>;
1681 }; 1618 };
1682 vin5c 1619 vin5csi40: endpoint@2 {
1683 1620 reg = <2>;
1684 1621 remote-endpoint = <&csi40vin5>;
1685 }; 1622 };
1686 }; 1623 };
1687 }; 1624 };
1688 }; 1625 };
1689 1626
1690 vin6: video@e6ef6000 { 1627 vin6: video@e6ef6000 {
1691 compatible = "renesas 1628 compatible = "renesas,vin-r8a7796";
1692 reg = <0 0xe6ef6000 0 1629 reg = <0 0xe6ef6000 0 0x1000>;
1693 interrupts = <GIC_SPI 1630 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
1694 clocks = <&cpg CPG_MO 1631 clocks = <&cpg CPG_MOD 805>;
1695 power-domains = <&sys 1632 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1696 resets = <&cpg 805>; 1633 resets = <&cpg 805>;
1697 renesas,id = <6>; 1634 renesas,id = <6>;
1698 status = "disabled"; 1635 status = "disabled";
1699 1636
1700 ports { 1637 ports {
1701 #address-cell 1638 #address-cells = <1>;
1702 #size-cells = 1639 #size-cells = <0>;
1703 1640
1704 port@1 { 1641 port@1 {
1705 #addr 1642 #address-cells = <1>;
1706 #size 1643 #size-cells = <0>;
1707 1644
1708 reg = 1645 reg = <1>;
1709 1646
1710 vin6c 1647 vin6csi20: endpoint@0 {
1711 1648 reg = <0>;
1712 1649 remote-endpoint = <&csi20vin6>;
1713 }; 1650 };
1714 vin6c 1651 vin6csi40: endpoint@2 {
1715 1652 reg = <2>;
1716 1653 remote-endpoint = <&csi40vin6>;
1717 }; 1654 };
1718 }; 1655 };
1719 }; 1656 };
1720 }; 1657 };
1721 1658
1722 vin7: video@e6ef7000 { 1659 vin7: video@e6ef7000 {
1723 compatible = "renesas 1660 compatible = "renesas,vin-r8a7796";
1724 reg = <0 0xe6ef7000 0 1661 reg = <0 0xe6ef7000 0 0x1000>;
1725 interrupts = <GIC_SPI 1662 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
1726 clocks = <&cpg CPG_MO 1663 clocks = <&cpg CPG_MOD 804>;
1727 power-domains = <&sys 1664 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1728 resets = <&cpg 804>; 1665 resets = <&cpg 804>;
1729 renesas,id = <7>; 1666 renesas,id = <7>;
1730 status = "disabled"; 1667 status = "disabled";
1731 1668
1732 ports { 1669 ports {
1733 #address-cell 1670 #address-cells = <1>;
1734 #size-cells = 1671 #size-cells = <0>;
1735 1672
1736 port@1 { 1673 port@1 {
1737 #addr 1674 #address-cells = <1>;
1738 #size 1675 #size-cells = <0>;
1739 1676
1740 reg = 1677 reg = <1>;
1741 1678
1742 vin7c 1679 vin7csi20: endpoint@0 {
1743 1680 reg = <0>;
1744 1681 remote-endpoint = <&csi20vin7>;
1745 }; 1682 };
1746 vin7c 1683 vin7csi40: endpoint@2 {
1747 1684 reg = <2>;
1748 1685 remote-endpoint = <&csi40vin7>;
1749 }; 1686 };
1750 }; 1687 };
1751 }; 1688 };
1752 }; 1689 };
1753 1690
1754 drif00: rif@e6f40000 { 1691 drif00: rif@e6f40000 {
1755 compatible = "renesas 1692 compatible = "renesas,r8a7796-drif",
1756 "renesas 1693 "renesas,rcar-gen3-drif";
1757 reg = <0 0xe6f40000 0 1694 reg = <0 0xe6f40000 0 0x64>;
1758 interrupts = <GIC_SPI 1695 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1759 clocks = <&cpg CPG_MO 1696 clocks = <&cpg CPG_MOD 515>;
1760 clock-names = "fck"; 1697 clock-names = "fck";
1761 dmas = <&dmac1 0x20>, 1698 dmas = <&dmac1 0x20>, <&dmac2 0x20>;
1762 dma-names = "rx", "rx 1699 dma-names = "rx", "rx";
1763 power-domains = <&sys 1700 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1764 resets = <&cpg 515>; 1701 resets = <&cpg 515>;
1765 renesas,bonding = <&d 1702 renesas,bonding = <&drif01>;
1766 status = "disabled"; 1703 status = "disabled";
1767 }; 1704 };
1768 1705
1769 drif01: rif@e6f50000 { 1706 drif01: rif@e6f50000 {
1770 compatible = "renesas 1707 compatible = "renesas,r8a7796-drif",
1771 "renesas 1708 "renesas,rcar-gen3-drif";
1772 reg = <0 0xe6f50000 0 1709 reg = <0 0xe6f50000 0 0x64>;
1773 interrupts = <GIC_SPI 1710 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1774 clocks = <&cpg CPG_MO 1711 clocks = <&cpg CPG_MOD 514>;
1775 clock-names = "fck"; 1712 clock-names = "fck";
1776 dmas = <&dmac1 0x22>, 1713 dmas = <&dmac1 0x22>, <&dmac2 0x22>;
1777 dma-names = "rx", "rx 1714 dma-names = "rx", "rx";
1778 power-domains = <&sys 1715 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1779 resets = <&cpg 514>; 1716 resets = <&cpg 514>;
1780 renesas,bonding = <&d 1717 renesas,bonding = <&drif00>;
1781 status = "disabled"; 1718 status = "disabled";
1782 }; 1719 };
1783 1720
1784 drif10: rif@e6f60000 { 1721 drif10: rif@e6f60000 {
1785 compatible = "renesas 1722 compatible = "renesas,r8a7796-drif",
1786 "renesas 1723 "renesas,rcar-gen3-drif";
1787 reg = <0 0xe6f60000 0 1724 reg = <0 0xe6f60000 0 0x64>;
1788 interrupts = <GIC_SPI 1725 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1789 clocks = <&cpg CPG_MO 1726 clocks = <&cpg CPG_MOD 513>;
1790 clock-names = "fck"; 1727 clock-names = "fck";
1791 dmas = <&dmac1 0x24>, 1728 dmas = <&dmac1 0x24>, <&dmac2 0x24>;
1792 dma-names = "rx", "rx 1729 dma-names = "rx", "rx";
1793 power-domains = <&sys 1730 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1794 resets = <&cpg 513>; 1731 resets = <&cpg 513>;
1795 renesas,bonding = <&d 1732 renesas,bonding = <&drif11>;
1796 status = "disabled"; 1733 status = "disabled";
1797 }; 1734 };
1798 1735
1799 drif11: rif@e6f70000 { 1736 drif11: rif@e6f70000 {
1800 compatible = "renesas 1737 compatible = "renesas,r8a7796-drif",
1801 "renesas 1738 "renesas,rcar-gen3-drif";
1802 reg = <0 0xe6f70000 0 1739 reg = <0 0xe6f70000 0 0x64>;
1803 interrupts = <GIC_SPI 1740 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1804 clocks = <&cpg CPG_MO 1741 clocks = <&cpg CPG_MOD 512>;
1805 clock-names = "fck"; 1742 clock-names = "fck";
1806 dmas = <&dmac1 0x26>, 1743 dmas = <&dmac1 0x26>, <&dmac2 0x26>;
1807 dma-names = "rx", "rx 1744 dma-names = "rx", "rx";
1808 power-domains = <&sys 1745 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1809 resets = <&cpg 512>; 1746 resets = <&cpg 512>;
1810 renesas,bonding = <&d 1747 renesas,bonding = <&drif10>;
1811 status = "disabled"; 1748 status = "disabled";
1812 }; 1749 };
1813 1750
1814 drif20: rif@e6f80000 { 1751 drif20: rif@e6f80000 {
1815 compatible = "renesas 1752 compatible = "renesas,r8a7796-drif",
1816 "renesas 1753 "renesas,rcar-gen3-drif";
1817 reg = <0 0xe6f80000 0 1754 reg = <0 0xe6f80000 0 0x64>;
1818 interrupts = <GIC_SPI 1755 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1819 clocks = <&cpg CPG_MO 1756 clocks = <&cpg CPG_MOD 511>;
1820 clock-names = "fck"; 1757 clock-names = "fck";
1821 dmas = <&dmac1 0x28>, 1758 dmas = <&dmac1 0x28>, <&dmac2 0x28>;
1822 dma-names = "rx", "rx 1759 dma-names = "rx", "rx";
1823 power-domains = <&sys 1760 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1824 resets = <&cpg 511>; 1761 resets = <&cpg 511>;
1825 renesas,bonding = <&d 1762 renesas,bonding = <&drif21>;
1826 status = "disabled"; 1763 status = "disabled";
1827 }; 1764 };
1828 1765
1829 drif21: rif@e6f90000 { 1766 drif21: rif@e6f90000 {
1830 compatible = "renesas 1767 compatible = "renesas,r8a7796-drif",
1831 "renesas 1768 "renesas,rcar-gen3-drif";
1832 reg = <0 0xe6f90000 0 1769 reg = <0 0xe6f90000 0 0x64>;
1833 interrupts = <GIC_SPI 1770 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1834 clocks = <&cpg CPG_MO 1771 clocks = <&cpg CPG_MOD 510>;
1835 clock-names = "fck"; 1772 clock-names = "fck";
1836 dmas = <&dmac1 0x2a>, 1773 dmas = <&dmac1 0x2a>, <&dmac2 0x2a>;
1837 dma-names = "rx", "rx 1774 dma-names = "rx", "rx";
1838 power-domains = <&sys 1775 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1839 resets = <&cpg 510>; 1776 resets = <&cpg 510>;
1840 renesas,bonding = <&d 1777 renesas,bonding = <&drif20>;
1841 status = "disabled"; 1778 status = "disabled";
1842 }; 1779 };
1843 1780
1844 drif30: rif@e6fa0000 { 1781 drif30: rif@e6fa0000 {
1845 compatible = "renesas 1782 compatible = "renesas,r8a7796-drif",
1846 "renesas 1783 "renesas,rcar-gen3-drif";
1847 reg = <0 0xe6fa0000 0 1784 reg = <0 0xe6fa0000 0 0x64>;
1848 interrupts = <GIC_SPI 1785 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1849 clocks = <&cpg CPG_MO 1786 clocks = <&cpg CPG_MOD 509>;
1850 clock-names = "fck"; 1787 clock-names = "fck";
1851 dmas = <&dmac1 0x2c>, 1788 dmas = <&dmac1 0x2c>, <&dmac2 0x2c>;
1852 dma-names = "rx", "rx 1789 dma-names = "rx", "rx";
1853 power-domains = <&sys 1790 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1854 resets = <&cpg 509>; 1791 resets = <&cpg 509>;
1855 renesas,bonding = <&d 1792 renesas,bonding = <&drif31>;
1856 status = "disabled"; 1793 status = "disabled";
1857 }; 1794 };
1858 1795
1859 drif31: rif@e6fb0000 { 1796 drif31: rif@e6fb0000 {
1860 compatible = "renesas 1797 compatible = "renesas,r8a7796-drif",
1861 "renesas 1798 "renesas,rcar-gen3-drif";
1862 reg = <0 0xe6fb0000 0 1799 reg = <0 0xe6fb0000 0 0x64>;
1863 interrupts = <GIC_SPI 1800 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1864 clocks = <&cpg CPG_MO 1801 clocks = <&cpg CPG_MOD 508>;
1865 clock-names = "fck"; 1802 clock-names = "fck";
1866 dmas = <&dmac1 0x2e>, 1803 dmas = <&dmac1 0x2e>, <&dmac2 0x2e>;
1867 dma-names = "rx", "rx 1804 dma-names = "rx", "rx";
1868 power-domains = <&sys 1805 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1869 resets = <&cpg 508>; 1806 resets = <&cpg 508>;
1870 renesas,bonding = <&d 1807 renesas,bonding = <&drif30>;
1871 status = "disabled"; 1808 status = "disabled";
1872 }; 1809 };
1873 1810
1874 rcar_sound: sound@ec500000 { 1811 rcar_sound: sound@ec500000 {
1875 /* 1812 /*
1876 * #sound-dai-cells i !! 1813 * #sound-dai-cells is required
1877 * 1814 *
1878 * Single DAI : #soun 1815 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1879 * Multi DAI : #soun 1816 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1880 */ 1817 */
1881 /* 1818 /*
1882 * #clock-cells is re 1819 * #clock-cells is required for audio_clkout0/1/2/3
1883 * 1820 *
1884 * clkout : #cl 1821 * clkout : #clock-cells = <0>; <&rcar_sound>;
1885 * clkout0/1/2/3: #cl 1822 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
1886 */ 1823 */
1887 compatible = "renesas !! 1824 compatible = "renesas,rcar_sound-r8a7796", "renesas,rcar_sound-gen3";
1888 reg = <0 0xec500000 0 !! 1825 reg = <0 0xec500000 0 0x1000>, /* SCU */
1889 <0 0xec5a0000 0 !! 1826 <0 0xec5a0000 0 0x100>, /* ADG */
1890 <0 0xec540000 0 !! 1827 <0 0xec540000 0 0x1000>, /* SSIU */
1891 <0 0xec541000 0 !! 1828 <0 0xec541000 0 0x280>, /* SSI */
1892 <0 0xec760000 0 !! 1829 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
1893 reg-names = "scu", "a 1830 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1894 1831
1895 clocks = <&cpg CPG_MO 1832 clocks = <&cpg CPG_MOD 1005>,
1896 <&cpg CPG_MO 1833 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
1897 <&cpg CPG_MO 1834 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
1898 <&cpg CPG_MO 1835 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
1899 <&cpg CPG_MO 1836 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
1900 <&cpg CPG_MO 1837 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
1901 <&cpg CPG_MO 1838 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
1902 <&cpg CPG_MO 1839 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
1903 <&cpg CPG_MO 1840 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
1904 <&cpg CPG_MO 1841 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
1905 <&cpg CPG_MO 1842 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
1906 <&cpg CPG_MO 1843 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1907 <&cpg CPG_MO 1844 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1908 <&cpg CPG_MO 1845 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
1909 <&audio_clk_ 1846 <&audio_clk_a>, <&audio_clk_b>,
1910 <&audio_clk_ 1847 <&audio_clk_c>,
1911 <&cpg CPG_MO !! 1848 <&cpg CPG_CORE R8A7796_CLK_S0D4>;
1912 clock-names = "ssi-al 1849 clock-names = "ssi-all",
1913 "ssi.9" 1850 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1914 "ssi.5" 1851 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1915 "ssi.1" 1852 "ssi.1", "ssi.0",
1916 "src.9" 1853 "src.9", "src.8", "src.7", "src.6",
1917 "src.5" 1854 "src.5", "src.4", "src.3", "src.2",
1918 "src.1" 1855 "src.1", "src.0",
1919 "mix.1" 1856 "mix.1", "mix.0",
1920 "ctu.1" 1857 "ctu.1", "ctu.0",
1921 "dvc.0" 1858 "dvc.0", "dvc.1",
1922 "clk_a" 1859 "clk_a", "clk_b", "clk_c", "clk_i";
1923 power-domains = <&sys 1860 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1924 resets = <&cpg 1005>, 1861 resets = <&cpg 1005>,
1925 <&cpg 1006>, 1862 <&cpg 1006>, <&cpg 1007>,
1926 <&cpg 1008>, 1863 <&cpg 1008>, <&cpg 1009>,
1927 <&cpg 1010>, 1864 <&cpg 1010>, <&cpg 1011>,
1928 <&cpg 1012>, 1865 <&cpg 1012>, <&cpg 1013>,
1929 <&cpg 1014>, 1866 <&cpg 1014>, <&cpg 1015>;
1930 reset-names = "ssi-al 1867 reset-names = "ssi-all",
1931 "ssi.9" 1868 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1932 "ssi.5" 1869 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1933 "ssi.1" 1870 "ssi.1", "ssi.0";
1934 status = "disabled"; 1871 status = "disabled";
1935 1872
1936 rcar_sound,ctu { 1873 rcar_sound,ctu {
1937 ctu00: ctu-0 1874 ctu00: ctu-0 { };
1938 ctu01: ctu-1 1875 ctu01: ctu-1 { };
1939 ctu02: ctu-2 1876 ctu02: ctu-2 { };
1940 ctu03: ctu-3 1877 ctu03: ctu-3 { };
1941 ctu10: ctu-4 1878 ctu10: ctu-4 { };
1942 ctu11: ctu-5 1879 ctu11: ctu-5 { };
1943 ctu12: ctu-6 1880 ctu12: ctu-6 { };
1944 ctu13: ctu-7 1881 ctu13: ctu-7 { };
1945 }; 1882 };
1946 1883
1947 rcar_sound,dvc { 1884 rcar_sound,dvc {
1948 dvc0: dvc-0 { 1885 dvc0: dvc-0 {
1949 dmas 1886 dmas = <&audma1 0xbc>;
1950 dma-n 1887 dma-names = "tx";
1951 }; 1888 };
1952 dvc1: dvc-1 { 1889 dvc1: dvc-1 {
1953 dmas 1890 dmas = <&audma1 0xbe>;
1954 dma-n 1891 dma-names = "tx";
1955 }; 1892 };
1956 }; 1893 };
1957 1894
1958 rcar_sound,mix { 1895 rcar_sound,mix {
1959 mix0: mix-0 { 1896 mix0: mix-0 { };
1960 mix1: mix-1 { 1897 mix1: mix-1 { };
1961 }; 1898 };
1962 1899
1963 rcar_sound,src { 1900 rcar_sound,src {
1964 src0: src-0 { 1901 src0: src-0 {
1965 inter 1902 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1966 dmas 1903 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1967 dma-n 1904 dma-names = "rx", "tx";
1968 }; 1905 };
1969 src1: src-1 { 1906 src1: src-1 {
1970 inter 1907 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1971 dmas 1908 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1972 dma-n 1909 dma-names = "rx", "tx";
1973 }; 1910 };
1974 src2: src-2 { 1911 src2: src-2 {
1975 inter 1912 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1976 dmas 1913 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1977 dma-n 1914 dma-names = "rx", "tx";
1978 }; 1915 };
1979 src3: src-3 { 1916 src3: src-3 {
1980 inter 1917 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1981 dmas 1918 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1982 dma-n 1919 dma-names = "rx", "tx";
1983 }; 1920 };
1984 src4: src-4 { 1921 src4: src-4 {
1985 inter 1922 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1986 dmas 1923 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1987 dma-n 1924 dma-names = "rx", "tx";
1988 }; 1925 };
1989 src5: src-5 { 1926 src5: src-5 {
1990 inter 1927 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1991 dmas 1928 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1992 dma-n 1929 dma-names = "rx", "tx";
1993 }; 1930 };
1994 src6: src-6 { 1931 src6: src-6 {
1995 inter 1932 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1996 dmas 1933 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1997 dma-n 1934 dma-names = "rx", "tx";
1998 }; 1935 };
1999 src7: src-7 { 1936 src7: src-7 {
2000 inter 1937 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
2001 dmas 1938 dmas = <&audma0 0x93>, <&audma1 0xb6>;
2002 dma-n 1939 dma-names = "rx", "tx";
2003 }; 1940 };
2004 src8: src-8 { 1941 src8: src-8 {
2005 inter 1942 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2006 dmas 1943 dmas = <&audma0 0x95>, <&audma1 0xb8>;
2007 dma-n 1944 dma-names = "rx", "tx";
2008 }; 1945 };
2009 src9: src-9 { 1946 src9: src-9 {
2010 inter 1947 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
2011 dmas 1948 dmas = <&audma0 0x97>, <&audma1 0xba>;
2012 dma-n 1949 dma-names = "rx", "tx";
2013 }; 1950 };
2014 }; 1951 };
2015 1952
2016 rcar_sound,ssi { 1953 rcar_sound,ssi {
2017 ssi0: ssi-0 { 1954 ssi0: ssi-0 {
2018 inter 1955 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
2019 dmas 1956 dmas = <&audma0 0x01>, <&audma1 0x02>;
2020 dma-n 1957 dma-names = "rx", "tx";
2021 }; 1958 };
2022 ssi1: ssi-1 { 1959 ssi1: ssi-1 {
2023 inter 1960 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
2024 dmas 1961 dmas = <&audma0 0x03>, <&audma1 0x04>;
2025 dma-n 1962 dma-names = "rx", "tx";
2026 }; 1963 };
2027 ssi2: ssi-2 { 1964 ssi2: ssi-2 {
2028 inter 1965 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
2029 dmas 1966 dmas = <&audma0 0x05>, <&audma1 0x06>;
2030 dma-n 1967 dma-names = "rx", "tx";
2031 }; 1968 };
2032 ssi3: ssi-3 { 1969 ssi3: ssi-3 {
2033 inter 1970 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
2034 dmas 1971 dmas = <&audma0 0x07>, <&audma1 0x08>;
2035 dma-n 1972 dma-names = "rx", "tx";
2036 }; 1973 };
2037 ssi4: ssi-4 { 1974 ssi4: ssi-4 {
2038 inter 1975 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
2039 dmas 1976 dmas = <&audma0 0x09>, <&audma1 0x0a>;
2040 dma-n 1977 dma-names = "rx", "tx";
2041 }; 1978 };
2042 ssi5: ssi-5 { 1979 ssi5: ssi-5 {
2043 inter 1980 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
2044 dmas 1981 dmas = <&audma0 0x0b>, <&audma1 0x0c>;
2045 dma-n 1982 dma-names = "rx", "tx";
2046 }; 1983 };
2047 ssi6: ssi-6 { 1984 ssi6: ssi-6 {
2048 inter 1985 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
2049 dmas 1986 dmas = <&audma0 0x0d>, <&audma1 0x0e>;
2050 dma-n 1987 dma-names = "rx", "tx";
2051 }; 1988 };
2052 ssi7: ssi-7 { 1989 ssi7: ssi-7 {
2053 inter 1990 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
2054 dmas 1991 dmas = <&audma0 0x0f>, <&audma1 0x10>;
2055 dma-n 1992 dma-names = "rx", "tx";
2056 }; 1993 };
2057 ssi8: ssi-8 { 1994 ssi8: ssi-8 {
2058 inter 1995 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
2059 dmas 1996 dmas = <&audma0 0x11>, <&audma1 0x12>;
2060 dma-n 1997 dma-names = "rx", "tx";
2061 }; 1998 };
2062 ssi9: ssi-9 { 1999 ssi9: ssi-9 {
2063 inter 2000 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
2064 dmas 2001 dmas = <&audma0 0x13>, <&audma1 0x14>;
2065 dma-n 2002 dma-names = "rx", "tx";
2066 }; 2003 };
2067 }; 2004 };
2068 2005
2069 rcar_sound,ssiu { 2006 rcar_sound,ssiu {
2070 ssiu00: ssiu- 2007 ssiu00: ssiu-0 {
2071 dmas 2008 dmas = <&audma0 0x15>, <&audma1 0x16>;
2072 dma-n 2009 dma-names = "rx", "tx";
2073 }; 2010 };
2074 ssiu01: ssiu- 2011 ssiu01: ssiu-1 {
2075 dmas 2012 dmas = <&audma0 0x35>, <&audma1 0x36>;
2076 dma-n 2013 dma-names = "rx", "tx";
2077 }; 2014 };
2078 ssiu02: ssiu- 2015 ssiu02: ssiu-2 {
2079 dmas 2016 dmas = <&audma0 0x37>, <&audma1 0x38>;
2080 dma-n 2017 dma-names = "rx", "tx";
2081 }; 2018 };
2082 ssiu03: ssiu- 2019 ssiu03: ssiu-3 {
2083 dmas 2020 dmas = <&audma0 0x47>, <&audma1 0x48>;
2084 dma-n 2021 dma-names = "rx", "tx";
2085 }; 2022 };
2086 ssiu04: ssiu- 2023 ssiu04: ssiu-4 {
2087 dmas 2024 dmas = <&audma0 0x3F>, <&audma1 0x40>;
2088 dma-n 2025 dma-names = "rx", "tx";
2089 }; 2026 };
2090 ssiu05: ssiu- 2027 ssiu05: ssiu-5 {
2091 dmas 2028 dmas = <&audma0 0x43>, <&audma1 0x44>;
2092 dma-n 2029 dma-names = "rx", "tx";
2093 }; 2030 };
2094 ssiu06: ssiu- 2031 ssiu06: ssiu-6 {
2095 dmas 2032 dmas = <&audma0 0x4F>, <&audma1 0x50>;
2096 dma-n 2033 dma-names = "rx", "tx";
2097 }; 2034 };
2098 ssiu07: ssiu- 2035 ssiu07: ssiu-7 {
2099 dmas 2036 dmas = <&audma0 0x53>, <&audma1 0x54>;
2100 dma-n 2037 dma-names = "rx", "tx";
2101 }; 2038 };
2102 ssiu10: ssiu- 2039 ssiu10: ssiu-8 {
2103 dmas 2040 dmas = <&audma0 0x49>, <&audma1 0x4a>;
2104 dma-n 2041 dma-names = "rx", "tx";
2105 }; 2042 };
2106 ssiu11: ssiu- 2043 ssiu11: ssiu-9 {
2107 dmas 2044 dmas = <&audma0 0x4B>, <&audma1 0x4C>;
2108 dma-n 2045 dma-names = "rx", "tx";
2109 }; 2046 };
2110 ssiu12: ssiu- 2047 ssiu12: ssiu-10 {
2111 dmas 2048 dmas = <&audma0 0x57>, <&audma1 0x58>;
2112 dma-n 2049 dma-names = "rx", "tx";
2113 }; 2050 };
2114 ssiu13: ssiu- 2051 ssiu13: ssiu-11 {
2115 dmas 2052 dmas = <&audma0 0x59>, <&audma1 0x5A>;
2116 dma-n 2053 dma-names = "rx", "tx";
2117 }; 2054 };
2118 ssiu14: ssiu- 2055 ssiu14: ssiu-12 {
2119 dmas 2056 dmas = <&audma0 0x5F>, <&audma1 0x60>;
2120 dma-n 2057 dma-names = "rx", "tx";
2121 }; 2058 };
2122 ssiu15: ssiu- 2059 ssiu15: ssiu-13 {
2123 dmas 2060 dmas = <&audma0 0xC3>, <&audma1 0xC4>;
2124 dma-n 2061 dma-names = "rx", "tx";
2125 }; 2062 };
2126 ssiu16: ssiu- 2063 ssiu16: ssiu-14 {
2127 dmas 2064 dmas = <&audma0 0xC7>, <&audma1 0xC8>;
2128 dma-n 2065 dma-names = "rx", "tx";
2129 }; 2066 };
2130 ssiu17: ssiu- 2067 ssiu17: ssiu-15 {
2131 dmas 2068 dmas = <&audma0 0xCB>, <&audma1 0xCC>;
2132 dma-n 2069 dma-names = "rx", "tx";
2133 }; 2070 };
2134 ssiu20: ssiu- 2071 ssiu20: ssiu-16 {
2135 dmas 2072 dmas = <&audma0 0x63>, <&audma1 0x64>;
2136 dma-n 2073 dma-names = "rx", "tx";
2137 }; 2074 };
2138 ssiu21: ssiu- 2075 ssiu21: ssiu-17 {
2139 dmas 2076 dmas = <&audma0 0x67>, <&audma1 0x68>;
2140 dma-n 2077 dma-names = "rx", "tx";
2141 }; 2078 };
2142 ssiu22: ssiu- 2079 ssiu22: ssiu-18 {
2143 dmas 2080 dmas = <&audma0 0x6B>, <&audma1 0x6C>;
2144 dma-n 2081 dma-names = "rx", "tx";
2145 }; 2082 };
2146 ssiu23: ssiu- 2083 ssiu23: ssiu-19 {
2147 dmas 2084 dmas = <&audma0 0x6D>, <&audma1 0x6E>;
2148 dma-n 2085 dma-names = "rx", "tx";
2149 }; 2086 };
2150 ssiu24: ssiu- 2087 ssiu24: ssiu-20 {
2151 dmas 2088 dmas = <&audma0 0xCF>, <&audma1 0xCE>;
2152 dma-n 2089 dma-names = "rx", "tx";
2153 }; 2090 };
2154 ssiu25: ssiu- 2091 ssiu25: ssiu-21 {
2155 dmas 2092 dmas = <&audma0 0xEB>, <&audma1 0xEC>;
2156 dma-n 2093 dma-names = "rx", "tx";
2157 }; 2094 };
2158 ssiu26: ssiu- 2095 ssiu26: ssiu-22 {
2159 dmas 2096 dmas = <&audma0 0xED>, <&audma1 0xEE>;
2160 dma-n 2097 dma-names = "rx", "tx";
2161 }; 2098 };
2162 ssiu27: ssiu- 2099 ssiu27: ssiu-23 {
2163 dmas 2100 dmas = <&audma0 0xEF>, <&audma1 0xF0>;
2164 dma-n 2101 dma-names = "rx", "tx";
2165 }; 2102 };
2166 ssiu30: ssiu- 2103 ssiu30: ssiu-24 {
2167 dmas 2104 dmas = <&audma0 0x6f>, <&audma1 0x70>;
2168 dma-n 2105 dma-names = "rx", "tx";
2169 }; 2106 };
2170 ssiu31: ssiu- 2107 ssiu31: ssiu-25 {
2171 dmas 2108 dmas = <&audma0 0x21>, <&audma1 0x22>;
2172 dma-n 2109 dma-names = "rx", "tx";
2173 }; 2110 };
2174 ssiu32: ssiu- 2111 ssiu32: ssiu-26 {
2175 dmas 2112 dmas = <&audma0 0x23>, <&audma1 0x24>;
2176 dma-n 2113 dma-names = "rx", "tx";
2177 }; 2114 };
2178 ssiu33: ssiu- 2115 ssiu33: ssiu-27 {
2179 dmas 2116 dmas = <&audma0 0x25>, <&audma1 0x26>;
2180 dma-n 2117 dma-names = "rx", "tx";
2181 }; 2118 };
2182 ssiu34: ssiu- 2119 ssiu34: ssiu-28 {
2183 dmas 2120 dmas = <&audma0 0x27>, <&audma1 0x28>;
2184 dma-n 2121 dma-names = "rx", "tx";
2185 }; 2122 };
2186 ssiu35: ssiu- 2123 ssiu35: ssiu-29 {
2187 dmas 2124 dmas = <&audma0 0x29>, <&audma1 0x2A>;
2188 dma-n 2125 dma-names = "rx", "tx";
2189 }; 2126 };
2190 ssiu36: ssiu- 2127 ssiu36: ssiu-30 {
2191 dmas 2128 dmas = <&audma0 0x2B>, <&audma1 0x2C>;
2192 dma-n 2129 dma-names = "rx", "tx";
2193 }; 2130 };
2194 ssiu37: ssiu- 2131 ssiu37: ssiu-31 {
2195 dmas 2132 dmas = <&audma0 0x2D>, <&audma1 0x2E>;
2196 dma-n 2133 dma-names = "rx", "tx";
2197 }; 2134 };
2198 ssiu40: ssiu- 2135 ssiu40: ssiu-32 {
2199 dmas !! 2136 dmas = <&audma0 0x71>, <&audma1 0x72>;
2200 dma-n 2137 dma-names = "rx", "tx";
2201 }; 2138 };
2202 ssiu41: ssiu- 2139 ssiu41: ssiu-33 {
2203 dmas 2140 dmas = <&audma0 0x17>, <&audma1 0x18>;
2204 dma-n 2141 dma-names = "rx", "tx";
2205 }; 2142 };
2206 ssiu42: ssiu- 2143 ssiu42: ssiu-34 {
2207 dmas 2144 dmas = <&audma0 0x19>, <&audma1 0x1A>;
2208 dma-n 2145 dma-names = "rx", "tx";
2209 }; 2146 };
2210 ssiu43: ssiu- 2147 ssiu43: ssiu-35 {
2211 dmas 2148 dmas = <&audma0 0x1B>, <&audma1 0x1C>;
2212 dma-n 2149 dma-names = "rx", "tx";
2213 }; 2150 };
2214 ssiu44: ssiu- 2151 ssiu44: ssiu-36 {
2215 dmas 2152 dmas = <&audma0 0x1D>, <&audma1 0x1E>;
2216 dma-n 2153 dma-names = "rx", "tx";
2217 }; 2154 };
2218 ssiu45: ssiu- 2155 ssiu45: ssiu-37 {
2219 dmas 2156 dmas = <&audma0 0x1F>, <&audma1 0x20>;
2220 dma-n 2157 dma-names = "rx", "tx";
2221 }; 2158 };
2222 ssiu46: ssiu- 2159 ssiu46: ssiu-38 {
2223 dmas 2160 dmas = <&audma0 0x31>, <&audma1 0x32>;
2224 dma-n 2161 dma-names = "rx", "tx";
2225 }; 2162 };
2226 ssiu47: ssiu- 2163 ssiu47: ssiu-39 {
2227 dmas 2164 dmas = <&audma0 0x33>, <&audma1 0x34>;
2228 dma-n 2165 dma-names = "rx", "tx";
2229 }; 2166 };
2230 ssiu50: ssiu- 2167 ssiu50: ssiu-40 {
2231 dmas 2168 dmas = <&audma0 0x73>, <&audma1 0x74>;
2232 dma-n 2169 dma-names = "rx", "tx";
2233 }; 2170 };
2234 ssiu60: ssiu- 2171 ssiu60: ssiu-41 {
2235 dmas 2172 dmas = <&audma0 0x75>, <&audma1 0x76>;
2236 dma-n 2173 dma-names = "rx", "tx";
2237 }; 2174 };
2238 ssiu70: ssiu- 2175 ssiu70: ssiu-42 {
2239 dmas 2176 dmas = <&audma0 0x79>, <&audma1 0x7a>;
2240 dma-n 2177 dma-names = "rx", "tx";
2241 }; 2178 };
2242 ssiu80: ssiu- 2179 ssiu80: ssiu-43 {
2243 dmas 2180 dmas = <&audma0 0x7b>, <&audma1 0x7c>;
2244 dma-n 2181 dma-names = "rx", "tx";
2245 }; 2182 };
2246 ssiu90: ssiu- 2183 ssiu90: ssiu-44 {
2247 dmas 2184 dmas = <&audma0 0x7d>, <&audma1 0x7e>;
2248 dma-n 2185 dma-names = "rx", "tx";
2249 }; 2186 };
2250 ssiu91: ssiu- 2187 ssiu91: ssiu-45 {
2251 dmas 2188 dmas = <&audma0 0x7F>, <&audma1 0x80>;
2252 dma-n 2189 dma-names = "rx", "tx";
2253 }; 2190 };
2254 ssiu92: ssiu- 2191 ssiu92: ssiu-46 {
2255 dmas 2192 dmas = <&audma0 0x81>, <&audma1 0x82>;
2256 dma-n 2193 dma-names = "rx", "tx";
2257 }; 2194 };
2258 ssiu93: ssiu- 2195 ssiu93: ssiu-47 {
2259 dmas 2196 dmas = <&audma0 0x83>, <&audma1 0x84>;
2260 dma-n 2197 dma-names = "rx", "tx";
2261 }; 2198 };
2262 ssiu94: ssiu- 2199 ssiu94: ssiu-48 {
2263 dmas 2200 dmas = <&audma0 0xA3>, <&audma1 0xA4>;
2264 dma-n 2201 dma-names = "rx", "tx";
2265 }; 2202 };
2266 ssiu95: ssiu- 2203 ssiu95: ssiu-49 {
2267 dmas 2204 dmas = <&audma0 0xA5>, <&audma1 0xA6>;
2268 dma-n 2205 dma-names = "rx", "tx";
2269 }; 2206 };
2270 ssiu96: ssiu- 2207 ssiu96: ssiu-50 {
2271 dmas 2208 dmas = <&audma0 0xA7>, <&audma1 0xA8>;
2272 dma-n 2209 dma-names = "rx", "tx";
2273 }; 2210 };
2274 ssiu97: ssiu- 2211 ssiu97: ssiu-51 {
2275 dmas 2212 dmas = <&audma0 0xA9>, <&audma1 0xAA>;
2276 dma-n 2213 dma-names = "rx", "tx";
2277 }; 2214 };
2278 }; 2215 };
2279 }; 2216 };
2280 2217
2281 mlp: mlp@ec520000 { <<
2282 compatible = "renesas <<
2283 "renesas <<
2284 reg = <0 0xec520000 0 <<
2285 interrupts = <GIC_SPI <<
2286 <GIC_SPI 385 <<
2287 clocks = <&cpg CPG_MO <<
2288 power-domains = <&sys <<
2289 resets = <&cpg 802>; <<
2290 status = "disabled"; <<
2291 }; <<
2292 <<
2293 audma0: dma-controller@ec7000 2218 audma0: dma-controller@ec700000 {
2294 compatible = "renesas 2219 compatible = "renesas,dmac-r8a7796",
2295 "renesas 2220 "renesas,rcar-dmac";
2296 reg = <0 0xec700000 0 2221 reg = <0 0xec700000 0 0x10000>;
2297 interrupts = <GIC_SPI 2222 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
2298 <GIC_SPI 2223 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
2299 <GIC_SPI 2224 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
2300 <GIC_SPI 2225 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
2301 <GIC_SPI 2226 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
2302 <GIC_SPI 2227 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
2303 <GIC_SPI 2228 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
2304 <GIC_SPI 2229 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
2305 <GIC_SPI 2230 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
2306 <GIC_SPI 2231 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
2307 <GIC_SPI 2232 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
2308 <GIC_SPI 2233 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
2309 <GIC_SPI 2234 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
2310 <GIC_SPI 2235 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
2311 <GIC_SPI 2236 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
2312 <GIC_SPI 2237 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
2313 <GIC_SPI 2238 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
2314 interrupt-names = "er 2239 interrupt-names = "error",
2315 "ch0" 2240 "ch0", "ch1", "ch2", "ch3",
2316 "ch4" 2241 "ch4", "ch5", "ch6", "ch7",
2317 "ch8" 2242 "ch8", "ch9", "ch10", "ch11",
2318 "ch12 2243 "ch12", "ch13", "ch14", "ch15";
2319 clocks = <&cpg CPG_MO 2244 clocks = <&cpg CPG_MOD 502>;
2320 clock-names = "fck"; 2245 clock-names = "fck";
2321 power-domains = <&sys 2246 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2322 resets = <&cpg 502>; 2247 resets = <&cpg 502>;
2323 #dma-cells = <1>; 2248 #dma-cells = <1>;
2324 dma-channels = <16>; 2249 dma-channels = <16>;
2325 iommus = <&ipmmu_mp 0 2250 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
2326 <&ipmmu_mp 2>, 2251 <&ipmmu_mp 2>, <&ipmmu_mp 3>,
2327 <&ipmmu_mp 4>, 2252 <&ipmmu_mp 4>, <&ipmmu_mp 5>,
2328 <&ipmmu_mp 6>, 2253 <&ipmmu_mp 6>, <&ipmmu_mp 7>,
2329 <&ipmmu_mp 8>, 2254 <&ipmmu_mp 8>, <&ipmmu_mp 9>,
2330 <&ipmmu_mp 10> 2255 <&ipmmu_mp 10>, <&ipmmu_mp 11>,
2331 <&ipmmu_mp 12> 2256 <&ipmmu_mp 12>, <&ipmmu_mp 13>,
2332 <&ipmmu_mp 14> 2257 <&ipmmu_mp 14>, <&ipmmu_mp 15>;
2333 }; 2258 };
2334 2259
2335 audma1: dma-controller@ec7200 2260 audma1: dma-controller@ec720000 {
2336 compatible = "renesas 2261 compatible = "renesas,dmac-r8a7796",
2337 "renesas 2262 "renesas,rcar-dmac";
2338 reg = <0 0xec720000 0 2263 reg = <0 0xec720000 0 0x10000>;
2339 interrupts = <GIC_SPI 2264 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
2340 <GIC_SPI 2265 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
2341 <GIC_SPI 2266 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
2342 <GIC_SPI 2267 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
2343 <GIC_SPI 2268 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
2344 <GIC_SPI 2269 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
2345 <GIC_SPI 2270 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
2346 <GIC_SPI 2271 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
2347 <GIC_SPI 2272 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
2348 <GIC_SPI 2273 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
2349 <GIC_SPI 2274 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
2350 <GIC_SPI 2275 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
2351 <GIC_SPI 2276 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
2352 <GIC_SPI 2277 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
2353 <GIC_SPI 2278 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
2354 <GIC_SPI 2279 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
2355 <GIC_SPI 2280 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
2356 interrupt-names = "er 2281 interrupt-names = "error",
2357 "ch0" 2282 "ch0", "ch1", "ch2", "ch3",
2358 "ch4" 2283 "ch4", "ch5", "ch6", "ch7",
2359 "ch8" 2284 "ch8", "ch9", "ch10", "ch11",
2360 "ch12 2285 "ch12", "ch13", "ch14", "ch15";
2361 clocks = <&cpg CPG_MO 2286 clocks = <&cpg CPG_MOD 501>;
2362 clock-names = "fck"; 2287 clock-names = "fck";
2363 power-domains = <&sys 2288 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2364 resets = <&cpg 501>; 2289 resets = <&cpg 501>;
2365 #dma-cells = <1>; 2290 #dma-cells = <1>;
2366 dma-channels = <16>; 2291 dma-channels = <16>;
2367 iommus = <&ipmmu_mp 1 2292 iommus = <&ipmmu_mp 16>, <&ipmmu_mp 17>,
2368 <&ipmmu_mp 18> 2293 <&ipmmu_mp 18>, <&ipmmu_mp 19>,
2369 <&ipmmu_mp 20> 2294 <&ipmmu_mp 20>, <&ipmmu_mp 21>,
2370 <&ipmmu_mp 22> 2295 <&ipmmu_mp 22>, <&ipmmu_mp 23>,
2371 <&ipmmu_mp 24> 2296 <&ipmmu_mp 24>, <&ipmmu_mp 25>,
2372 <&ipmmu_mp 26> 2297 <&ipmmu_mp 26>, <&ipmmu_mp 27>,
2373 <&ipmmu_mp 28> 2298 <&ipmmu_mp 28>, <&ipmmu_mp 29>,
2374 <&ipmmu_mp 30> 2299 <&ipmmu_mp 30>, <&ipmmu_mp 31>;
2375 }; 2300 };
2376 2301
2377 xhci0: usb@ee000000 { 2302 xhci0: usb@ee000000 {
2378 compatible = "renesas 2303 compatible = "renesas,xhci-r8a7796",
2379 "renesas 2304 "renesas,rcar-gen3-xhci";
2380 reg = <0 0xee000000 0 2305 reg = <0 0xee000000 0 0xc00>;
2381 interrupts = <GIC_SPI 2306 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
2382 clocks = <&cpg CPG_MO 2307 clocks = <&cpg CPG_MOD 328>;
2383 power-domains = <&sys 2308 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2384 resets = <&cpg 328>; 2309 resets = <&cpg 328>;
2385 status = "disabled"; 2310 status = "disabled";
2386 }; 2311 };
2387 2312
2388 usb3_peri0: usb@ee020000 { 2313 usb3_peri0: usb@ee020000 {
2389 compatible = "renesas 2314 compatible = "renesas,r8a7796-usb3-peri",
2390 "renesas 2315 "renesas,rcar-gen3-usb3-peri";
2391 reg = <0 0xee020000 0 2316 reg = <0 0xee020000 0 0x400>;
2392 interrupts = <GIC_SPI 2317 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
2393 clocks = <&cpg CPG_MO 2318 clocks = <&cpg CPG_MOD 328>;
2394 power-domains = <&sys 2319 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2395 resets = <&cpg 328>; 2320 resets = <&cpg 328>;
2396 status = "disabled"; 2321 status = "disabled";
2397 }; 2322 };
2398 2323
2399 ohci0: usb@ee080000 { 2324 ohci0: usb@ee080000 {
2400 compatible = "generic 2325 compatible = "generic-ohci";
2401 reg = <0 0xee080000 0 2326 reg = <0 0xee080000 0 0x100>;
2402 interrupts = <GIC_SPI 2327 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
2403 clocks = <&cpg CPG_MO 2328 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
2404 phys = <&usb2_phy0 1> 2329 phys = <&usb2_phy0 1>;
2405 phy-names = "usb"; 2330 phy-names = "usb";
2406 power-domains = <&sys 2331 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2407 resets = <&cpg 703>, 2332 resets = <&cpg 703>, <&cpg 704>;
2408 status = "disabled"; 2333 status = "disabled";
2409 }; 2334 };
2410 2335
2411 ohci1: usb@ee0a0000 { 2336 ohci1: usb@ee0a0000 {
2412 compatible = "generic 2337 compatible = "generic-ohci";
2413 reg = <0 0xee0a0000 0 2338 reg = <0 0xee0a0000 0 0x100>;
2414 interrupts = <GIC_SPI 2339 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
2415 clocks = <&cpg CPG_MO 2340 clocks = <&cpg CPG_MOD 702>;
2416 phys = <&usb2_phy1 1> 2341 phys = <&usb2_phy1 1>;
2417 phy-names = "usb"; 2342 phy-names = "usb";
2418 power-domains = <&sys 2343 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2419 resets = <&cpg 702>; 2344 resets = <&cpg 702>;
2420 status = "disabled"; 2345 status = "disabled";
2421 }; 2346 };
2422 2347
2423 ehci0: usb@ee080100 { 2348 ehci0: usb@ee080100 {
2424 compatible = "generic 2349 compatible = "generic-ehci";
2425 reg = <0 0xee080100 0 2350 reg = <0 0xee080100 0 0x100>;
2426 interrupts = <GIC_SPI 2351 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
2427 clocks = <&cpg CPG_MO 2352 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
2428 phys = <&usb2_phy0 2> 2353 phys = <&usb2_phy0 2>;
2429 phy-names = "usb"; 2354 phy-names = "usb";
2430 companion = <&ohci0>; 2355 companion = <&ohci0>;
2431 power-domains = <&sys 2356 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2432 resets = <&cpg 703>, 2357 resets = <&cpg 703>, <&cpg 704>;
2433 status = "disabled"; 2358 status = "disabled";
2434 }; 2359 };
2435 2360
2436 ehci1: usb@ee0a0100 { 2361 ehci1: usb@ee0a0100 {
2437 compatible = "generic 2362 compatible = "generic-ehci";
2438 reg = <0 0xee0a0100 0 2363 reg = <0 0xee0a0100 0 0x100>;
2439 interrupts = <GIC_SPI 2364 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
2440 clocks = <&cpg CPG_MO 2365 clocks = <&cpg CPG_MOD 702>;
2441 phys = <&usb2_phy1 2> 2366 phys = <&usb2_phy1 2>;
2442 phy-names = "usb"; 2367 phy-names = "usb";
2443 companion = <&ohci1>; 2368 companion = <&ohci1>;
2444 power-domains = <&sys 2369 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2445 resets = <&cpg 702>; 2370 resets = <&cpg 702>;
2446 status = "disabled"; 2371 status = "disabled";
2447 }; 2372 };
2448 2373
2449 usb2_phy0: usb-phy@ee080200 { 2374 usb2_phy0: usb-phy@ee080200 {
2450 compatible = "renesas 2375 compatible = "renesas,usb2-phy-r8a7796",
2451 "renesas 2376 "renesas,rcar-gen3-usb2-phy";
2452 reg = <0 0xee080200 0 2377 reg = <0 0xee080200 0 0x700>;
2453 interrupts = <GIC_SPI 2378 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
2454 clocks = <&cpg CPG_MO 2379 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
2455 power-domains = <&sys 2380 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2456 resets = <&cpg 703>, 2381 resets = <&cpg 703>, <&cpg 704>;
2457 #phy-cells = <1>; 2382 #phy-cells = <1>;
2458 status = "disabled"; 2383 status = "disabled";
2459 }; 2384 };
2460 2385
2461 usb2_phy1: usb-phy@ee0a0200 { 2386 usb2_phy1: usb-phy@ee0a0200 {
2462 compatible = "renesas 2387 compatible = "renesas,usb2-phy-r8a7796",
2463 "renesas 2388 "renesas,rcar-gen3-usb2-phy";
2464 reg = <0 0xee0a0200 0 2389 reg = <0 0xee0a0200 0 0x700>;
2465 clocks = <&cpg CPG_MO 2390 clocks = <&cpg CPG_MOD 702>;
2466 power-domains = <&sys 2391 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2467 resets = <&cpg 702>; 2392 resets = <&cpg 702>;
2468 #phy-cells = <1>; 2393 #phy-cells = <1>;
2469 status = "disabled"; 2394 status = "disabled";
2470 }; 2395 };
2471 2396
2472 sdhi0: mmc@ee100000 { 2397 sdhi0: mmc@ee100000 {
2473 compatible = "renesas 2398 compatible = "renesas,sdhi-r8a7796",
2474 "renesas 2399 "renesas,rcar-gen3-sdhi";
2475 reg = <0 0xee100000 0 2400 reg = <0 0xee100000 0 0x2000>;
2476 interrupts = <GIC_SPI 2401 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
2477 clocks = <&cpg CPG_MO !! 2402 clocks = <&cpg CPG_MOD 314>;
2478 clock-names = "core", <<
2479 max-frequency = <2000 2403 max-frequency = <200000000>;
2480 power-domains = <&sys 2404 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2481 resets = <&cpg 314>; 2405 resets = <&cpg 314>;
2482 iommus = <&ipmmu_ds1 2406 iommus = <&ipmmu_ds1 32>;
2483 status = "disabled"; 2407 status = "disabled";
2484 }; 2408 };
2485 2409
2486 sdhi1: mmc@ee120000 { 2410 sdhi1: mmc@ee120000 {
2487 compatible = "renesas 2411 compatible = "renesas,sdhi-r8a7796",
2488 "renesas 2412 "renesas,rcar-gen3-sdhi";
2489 reg = <0 0xee120000 0 2413 reg = <0 0xee120000 0 0x2000>;
2490 interrupts = <GIC_SPI 2414 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
2491 clocks = <&cpg CPG_MO !! 2415 clocks = <&cpg CPG_MOD 313>;
2492 clock-names = "core", <<
2493 max-frequency = <2000 2416 max-frequency = <200000000>;
2494 power-domains = <&sys 2417 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2495 resets = <&cpg 313>; 2418 resets = <&cpg 313>;
2496 iommus = <&ipmmu_ds1 2419 iommus = <&ipmmu_ds1 33>;
2497 status = "disabled"; 2420 status = "disabled";
2498 }; 2421 };
2499 2422
2500 sdhi2: mmc@ee140000 { 2423 sdhi2: mmc@ee140000 {
2501 compatible = "renesas 2424 compatible = "renesas,sdhi-r8a7796",
2502 "renesas 2425 "renesas,rcar-gen3-sdhi";
2503 reg = <0 0xee140000 0 2426 reg = <0 0xee140000 0 0x2000>;
2504 interrupts = <GIC_SPI 2427 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
2505 clocks = <&cpg CPG_MO !! 2428 clocks = <&cpg CPG_MOD 312>;
2506 clock-names = "core", <<
2507 max-frequency = <2000 2429 max-frequency = <200000000>;
2508 power-domains = <&sys 2430 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2509 resets = <&cpg 312>; 2431 resets = <&cpg 312>;
2510 iommus = <&ipmmu_ds1 2432 iommus = <&ipmmu_ds1 34>;
2511 status = "disabled"; 2433 status = "disabled";
2512 }; 2434 };
2513 2435
2514 sdhi3: mmc@ee160000 { 2436 sdhi3: mmc@ee160000 {
2515 compatible = "renesas 2437 compatible = "renesas,sdhi-r8a7796",
2516 "renesas 2438 "renesas,rcar-gen3-sdhi";
2517 reg = <0 0xee160000 0 2439 reg = <0 0xee160000 0 0x2000>;
2518 interrupts = <GIC_SPI 2440 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
2519 clocks = <&cpg CPG_MO !! 2441 clocks = <&cpg CPG_MOD 311>;
2520 clock-names = "core", <<
2521 max-frequency = <2000 2442 max-frequency = <200000000>;
2522 power-domains = <&sys 2443 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2523 resets = <&cpg 311>; 2444 resets = <&cpg 311>;
2524 iommus = <&ipmmu_ds1 2445 iommus = <&ipmmu_ds1 35>;
2525 status = "disabled"; 2446 status = "disabled";
2526 }; 2447 };
2527 2448
2528 rpc: spi@ee200000 { <<
2529 compatible = "renesas <<
2530 "renesas <<
2531 reg = <0 0xee200000 0 <<
2532 <0 0x08000000 0 <<
2533 <0 0xee208000 0 <<
2534 reg-names = "regs", " <<
2535 interrupts = <GIC_SPI <<
2536 clocks = <&cpg CPG_MO <<
2537 power-domains = <&sys <<
2538 resets = <&cpg 917>; <<
2539 #address-cells = <1>; <<
2540 #size-cells = <0>; <<
2541 status = "disabled"; <<
2542 }; <<
2543 <<
2544 gic: interrupt-controller@f10 2449 gic: interrupt-controller@f1010000 {
2545 compatible = "arm,gic 2450 compatible = "arm,gic-400";
2546 #interrupt-cells = <3 2451 #interrupt-cells = <3>;
2547 #address-cells = <0>; 2452 #address-cells = <0>;
2548 interrupt-controller; 2453 interrupt-controller;
2549 reg = <0x0 0xf1010000 2454 reg = <0x0 0xf1010000 0 0x1000>,
2550 <0x0 0xf1020000 2455 <0x0 0xf1020000 0 0x20000>,
2551 <0x0 0xf1040000 2456 <0x0 0xf1040000 0 0x20000>,
2552 <0x0 0xf1060000 2457 <0x0 0xf1060000 0 0x20000>;
2553 interrupts = <GIC_PPI 2458 interrupts = <GIC_PPI 9
2554 (GIC_ 2459 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
2555 clocks = <&cpg CPG_MO 2460 clocks = <&cpg CPG_MOD 408>;
2556 clock-names = "clk"; 2461 clock-names = "clk";
2557 power-domains = <&sys 2462 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2558 resets = <&cpg 408>; 2463 resets = <&cpg 408>;
2559 }; 2464 };
2560 2465
2561 pciec0: pcie@fe000000 { 2466 pciec0: pcie@fe000000 {
2562 compatible = "renesas 2467 compatible = "renesas,pcie-r8a7796",
2563 "renesas 2468 "renesas,pcie-rcar-gen3";
2564 reg = <0 0xfe000000 0 2469 reg = <0 0xfe000000 0 0x80000>;
2565 #address-cells = <3>; 2470 #address-cells = <3>;
2566 #size-cells = <2>; 2471 #size-cells = <2>;
2567 bus-range = <0x00 0xf 2472 bus-range = <0x00 0xff>;
2568 device_type = "pci"; 2473 device_type = "pci";
2569 ranges = <0x01000000 2474 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
2570 <0x02000000 2475 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
2571 <0x02000000 2476 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
2572 <0x42000000 2477 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
2573 /* Map all possible D !! 2478 /* Map all possible DDR as inbound ranges */
2574 dma-ranges = <0x42000 !! 2479 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
2575 interrupts = <GIC_SPI 2480 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
2576 <GIC_SPI 117 2481 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
2577 <GIC_SPI 118 2482 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
2578 #interrupt-cells = <1 2483 #interrupt-cells = <1>;
2579 interrupt-map-mask = 2484 interrupt-map-mask = <0 0 0 0>;
2580 interrupt-map = <0 0 2485 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
2581 clocks = <&cpg CPG_MO 2486 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
2582 clock-names = "pcie", 2487 clock-names = "pcie", "pcie_bus";
2583 power-domains = <&sys 2488 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2584 resets = <&cpg 319>; 2489 resets = <&cpg 319>;
2585 iommu-map = <0 &ipmmu <<
2586 iommu-map-mask = <0>; <<
2587 status = "disabled"; 2490 status = "disabled";
2588 }; 2491 };
2589 2492
2590 pciec1: pcie@ee800000 { 2493 pciec1: pcie@ee800000 {
2591 compatible = "renesas 2494 compatible = "renesas,pcie-r8a7796",
2592 "renesas 2495 "renesas,pcie-rcar-gen3";
2593 reg = <0 0xee800000 0 2496 reg = <0 0xee800000 0 0x80000>;
2594 #address-cells = <3>; 2497 #address-cells = <3>;
2595 #size-cells = <2>; 2498 #size-cells = <2>;
2596 bus-range = <0x00 0xf 2499 bus-range = <0x00 0xff>;
2597 device_type = "pci"; 2500 device_type = "pci";
2598 ranges = <0x01000000 2501 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
2599 <0x02000000 2502 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
2600 <0x02000000 2503 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
2601 <0x42000000 2504 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
2602 /* Map all possible D !! 2505 /* Map all possible DDR as inbound ranges */
2603 dma-ranges = <0x42000 !! 2506 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
2604 interrupts = <GIC_SPI 2507 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
2605 <GIC_SPI 149 2508 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
2606 <GIC_SPI 150 2509 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
2607 #interrupt-cells = <1 2510 #interrupt-cells = <1>;
2608 interrupt-map-mask = 2511 interrupt-map-mask = <0 0 0 0>;
2609 interrupt-map = <0 0 2512 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2610 clocks = <&cpg CPG_MO 2513 clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>;
2611 clock-names = "pcie", 2514 clock-names = "pcie", "pcie_bus";
2612 power-domains = <&sys 2515 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2613 resets = <&cpg 318>; 2516 resets = <&cpg 318>;
2614 iommu-map = <0 &ipmmu <<
2615 iommu-map-mask = <0>; <<
2616 status = "disabled"; 2517 status = "disabled";
2617 }; 2518 };
2618 2519
2619 imr-lx4@fe860000 { 2520 imr-lx4@fe860000 {
2620 compatible = "renesas 2521 compatible = "renesas,r8a7796-imr-lx4",
2621 "renesas 2522 "renesas,imr-lx4";
2622 reg = <0 0xfe860000 0 2523 reg = <0 0xfe860000 0 0x2000>;
2623 interrupts = <GIC_SPI 2524 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
2624 clocks = <&cpg CPG_MO 2525 clocks = <&cpg CPG_MOD 823>;
2625 power-domains = <&sys 2526 power-domains = <&sysc R8A7796_PD_A3VC>;
2626 resets = <&cpg 823>; 2527 resets = <&cpg 823>;
2627 }; 2528 };
2628 2529
2629 imr-lx4@fe870000 { 2530 imr-lx4@fe870000 {
2630 compatible = "renesas 2531 compatible = "renesas,r8a7796-imr-lx4",
2631 "renesas 2532 "renesas,imr-lx4";
2632 reg = <0 0xfe870000 0 2533 reg = <0 0xfe870000 0 0x2000>;
2633 interrupts = <GIC_SPI 2534 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
2634 clocks = <&cpg CPG_MO 2535 clocks = <&cpg CPG_MOD 822>;
2635 power-domains = <&sys 2536 power-domains = <&sysc R8A7796_PD_A3VC>;
2636 resets = <&cpg 822>; 2537 resets = <&cpg 822>;
2637 }; 2538 };
2638 2539
2639 fdp1@fe940000 { 2540 fdp1@fe940000 {
2640 compatible = "renesas 2541 compatible = "renesas,fdp1";
2641 reg = <0 0xfe940000 0 2542 reg = <0 0xfe940000 0 0x2400>;
2642 interrupts = <GIC_SPI 2543 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
2643 clocks = <&cpg CPG_MO 2544 clocks = <&cpg CPG_MOD 119>;
2644 power-domains = <&sys 2545 power-domains = <&sysc R8A7796_PD_A3VC>;
2645 resets = <&cpg 119>; 2546 resets = <&cpg 119>;
2646 renesas,fcp = <&fcpf0 2547 renesas,fcp = <&fcpf0>;
2647 }; 2548 };
2648 2549
2649 fcpf0: fcp@fe950000 { 2550 fcpf0: fcp@fe950000 {
2650 compatible = "renesas 2551 compatible = "renesas,fcpf";
2651 reg = <0 0xfe950000 0 2552 reg = <0 0xfe950000 0 0x200>;
2652 clocks = <&cpg CPG_MO 2553 clocks = <&cpg CPG_MOD 615>;
2653 power-domains = <&sys 2554 power-domains = <&sysc R8A7796_PD_A3VC>;
2654 resets = <&cpg 615>; 2555 resets = <&cpg 615>;
2655 iommus = <&ipmmu_vc0 <<
2656 }; 2556 };
2657 2557
2658 fcpvb0: fcp@fe96f000 { 2558 fcpvb0: fcp@fe96f000 {
2659 compatible = "renesas 2559 compatible = "renesas,fcpv";
2660 reg = <0 0xfe96f000 0 2560 reg = <0 0xfe96f000 0 0x200>;
2661 clocks = <&cpg CPG_MO 2561 clocks = <&cpg CPG_MOD 607>;
2662 power-domains = <&sys 2562 power-domains = <&sysc R8A7796_PD_A3VC>;
2663 resets = <&cpg 607>; 2563 resets = <&cpg 607>;
2664 iommus = <&ipmmu_vi0 <<
2665 }; 2564 };
2666 2565
2667 fcpvi0: fcp@fe9af000 { 2566 fcpvi0: fcp@fe9af000 {
2668 compatible = "renesas 2567 compatible = "renesas,fcpv";
2669 reg = <0 0xfe9af000 0 2568 reg = <0 0xfe9af000 0 0x200>;
2670 clocks = <&cpg CPG_MO 2569 clocks = <&cpg CPG_MOD 611>;
2671 power-domains = <&sys 2570 power-domains = <&sysc R8A7796_PD_A3VC>;
2672 resets = <&cpg 611>; 2571 resets = <&cpg 611>;
2673 iommus = <&ipmmu_vc0 2572 iommus = <&ipmmu_vc0 19>;
2674 }; 2573 };
2675 2574
2676 fcpvd0: fcp@fea27000 { 2575 fcpvd0: fcp@fea27000 {
2677 compatible = "renesas 2576 compatible = "renesas,fcpv";
2678 reg = <0 0xfea27000 0 2577 reg = <0 0xfea27000 0 0x200>;
2679 clocks = <&cpg CPG_MO 2578 clocks = <&cpg CPG_MOD 603>;
2680 power-domains = <&sys 2579 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2681 resets = <&cpg 603>; 2580 resets = <&cpg 603>;
2682 iommus = <&ipmmu_vi0 2581 iommus = <&ipmmu_vi0 8>;
2683 }; 2582 };
2684 2583
2685 fcpvd1: fcp@fea2f000 { 2584 fcpvd1: fcp@fea2f000 {
2686 compatible = "renesas 2585 compatible = "renesas,fcpv";
2687 reg = <0 0xfea2f000 0 2586 reg = <0 0xfea2f000 0 0x200>;
2688 clocks = <&cpg CPG_MO 2587 clocks = <&cpg CPG_MOD 602>;
2689 power-domains = <&sys 2588 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2690 resets = <&cpg 602>; 2589 resets = <&cpg 602>;
2691 iommus = <&ipmmu_vi0 2590 iommus = <&ipmmu_vi0 9>;
2692 }; 2591 };
2693 2592
2694 fcpvd2: fcp@fea37000 { 2593 fcpvd2: fcp@fea37000 {
2695 compatible = "renesas 2594 compatible = "renesas,fcpv";
2696 reg = <0 0xfea37000 0 2595 reg = <0 0xfea37000 0 0x200>;
2697 clocks = <&cpg CPG_MO 2596 clocks = <&cpg CPG_MOD 601>;
2698 power-domains = <&sys 2597 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2699 resets = <&cpg 601>; 2598 resets = <&cpg 601>;
2700 iommus = <&ipmmu_vi0 2599 iommus = <&ipmmu_vi0 10>;
2701 }; 2600 };
2702 2601
2703 vspb: vsp@fe960000 { 2602 vspb: vsp@fe960000 {
2704 compatible = "renesas 2603 compatible = "renesas,vsp2";
2705 reg = <0 0xfe960000 0 2604 reg = <0 0xfe960000 0 0x8000>;
2706 interrupts = <GIC_SPI 2605 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
2707 clocks = <&cpg CPG_MO 2606 clocks = <&cpg CPG_MOD 626>;
2708 power-domains = <&sys 2607 power-domains = <&sysc R8A7796_PD_A3VC>;
2709 resets = <&cpg 626>; 2608 resets = <&cpg 626>;
2710 2609
2711 renesas,fcp = <&fcpvb 2610 renesas,fcp = <&fcpvb0>;
2712 }; 2611 };
2713 2612
2714 vspd0: vsp@fea20000 { 2613 vspd0: vsp@fea20000 {
2715 compatible = "renesas 2614 compatible = "renesas,vsp2";
2716 reg = <0 0xfea20000 0 2615 reg = <0 0xfea20000 0 0x5000>;
2717 interrupts = <GIC_SPI 2616 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
2718 clocks = <&cpg CPG_MO 2617 clocks = <&cpg CPG_MOD 623>;
2719 power-domains = <&sys 2618 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2720 resets = <&cpg 623>; 2619 resets = <&cpg 623>;
2721 2620
2722 renesas,fcp = <&fcpvd 2621 renesas,fcp = <&fcpvd0>;
2723 }; 2622 };
2724 2623
2725 vspd1: vsp@fea28000 { 2624 vspd1: vsp@fea28000 {
2726 compatible = "renesas 2625 compatible = "renesas,vsp2";
2727 reg = <0 0xfea28000 0 2626 reg = <0 0xfea28000 0 0x5000>;
2728 interrupts = <GIC_SPI 2627 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
2729 clocks = <&cpg CPG_MO 2628 clocks = <&cpg CPG_MOD 622>;
2730 power-domains = <&sys 2629 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2731 resets = <&cpg 622>; 2630 resets = <&cpg 622>;
2732 2631
2733 renesas,fcp = <&fcpvd 2632 renesas,fcp = <&fcpvd1>;
2734 }; 2633 };
2735 2634
2736 vspd2: vsp@fea30000 { 2635 vspd2: vsp@fea30000 {
2737 compatible = "renesas 2636 compatible = "renesas,vsp2";
2738 reg = <0 0xfea30000 0 2637 reg = <0 0xfea30000 0 0x5000>;
2739 interrupts = <GIC_SPI 2638 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
2740 clocks = <&cpg CPG_MO 2639 clocks = <&cpg CPG_MOD 621>;
2741 power-domains = <&sys 2640 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2742 resets = <&cpg 621>; 2641 resets = <&cpg 621>;
2743 2642
2744 renesas,fcp = <&fcpvd 2643 renesas,fcp = <&fcpvd2>;
2745 }; 2644 };
2746 2645
2747 vspi0: vsp@fe9a0000 { 2646 vspi0: vsp@fe9a0000 {
2748 compatible = "renesas 2647 compatible = "renesas,vsp2";
2749 reg = <0 0xfe9a0000 0 2648 reg = <0 0xfe9a0000 0 0x8000>;
2750 interrupts = <GIC_SPI 2649 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
2751 clocks = <&cpg CPG_MO 2650 clocks = <&cpg CPG_MOD 631>;
2752 power-domains = <&sys 2651 power-domains = <&sysc R8A7796_PD_A3VC>;
2753 resets = <&cpg 631>; 2652 resets = <&cpg 631>;
2754 2653
2755 renesas,fcp = <&fcpvi 2654 renesas,fcp = <&fcpvi0>;
2756 }; 2655 };
2757 2656
2758 cmm0: cmm@fea40000 { 2657 cmm0: cmm@fea40000 {
2759 compatible = "renesas 2658 compatible = "renesas,r8a7796-cmm",
2760 "renesas 2659 "renesas,rcar-gen3-cmm";
2761 reg = <0 0xfea40000 0 2660 reg = <0 0xfea40000 0 0x1000>;
2762 power-domains = <&sys 2661 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2763 clocks = <&cpg CPG_MO 2662 clocks = <&cpg CPG_MOD 711>;
2764 resets = <&cpg 711>; 2663 resets = <&cpg 711>;
2765 }; 2664 };
2766 2665
2767 cmm1: cmm@fea50000 { 2666 cmm1: cmm@fea50000 {
2768 compatible = "renesas 2667 compatible = "renesas,r8a7796-cmm",
2769 "renesas 2668 "renesas,rcar-gen3-cmm";
2770 reg = <0 0xfea50000 0 2669 reg = <0 0xfea50000 0 0x1000>;
2771 power-domains = <&sys 2670 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2772 clocks = <&cpg CPG_MO 2671 clocks = <&cpg CPG_MOD 710>;
2773 resets = <&cpg 710>; 2672 resets = <&cpg 710>;
2774 }; 2673 };
2775 2674
2776 cmm2: cmm@fea60000 { 2675 cmm2: cmm@fea60000 {
2777 compatible = "renesas 2676 compatible = "renesas,r8a7796-cmm",
2778 "renesas 2677 "renesas,rcar-gen3-cmm";
2779 reg = <0 0xfea60000 0 2678 reg = <0 0xfea60000 0 0x1000>;
2780 power-domains = <&sys 2679 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2781 clocks = <&cpg CPG_MO 2680 clocks = <&cpg CPG_MOD 709>;
2782 resets = <&cpg 709>; 2681 resets = <&cpg 709>;
2783 }; 2682 };
2784 2683
2785 csi20: csi2@fea80000 { 2684 csi20: csi2@fea80000 {
2786 compatible = "renesas 2685 compatible = "renesas,r8a7796-csi2";
2787 reg = <0 0xfea80000 0 2686 reg = <0 0xfea80000 0 0x10000>;
2788 interrupts = <GIC_SPI 2687 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
2789 clocks = <&cpg CPG_MO 2688 clocks = <&cpg CPG_MOD 714>;
2790 power-domains = <&sys 2689 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2791 resets = <&cpg 714>; 2690 resets = <&cpg 714>;
2792 status = "disabled"; 2691 status = "disabled";
2793 2692
2794 ports { 2693 ports {
2795 #address-cell 2694 #address-cells = <1>;
2796 #size-cells = 2695 #size-cells = <0>;
2797 2696
2798 port@0 { <<
2799 reg = <<
2800 }; <<
2801 <<
2802 port@1 { 2697 port@1 {
2803 #addr 2698 #address-cells = <1>;
2804 #size 2699 #size-cells = <0>;
2805 2700
2806 reg = 2701 reg = <1>;
2807 2702
2808 csi20 2703 csi20vin0: endpoint@0 {
2809 2704 reg = <0>;
2810 2705 remote-endpoint = <&vin0csi20>;
2811 }; 2706 };
2812 csi20 2707 csi20vin1: endpoint@1 {
2813 2708 reg = <1>;
2814 2709 remote-endpoint = <&vin1csi20>;
2815 }; 2710 };
2816 csi20 2711 csi20vin2: endpoint@2 {
2817 2712 reg = <2>;
2818 2713 remote-endpoint = <&vin2csi20>;
2819 }; 2714 };
2820 csi20 2715 csi20vin3: endpoint@3 {
2821 2716 reg = <3>;
2822 2717 remote-endpoint = <&vin3csi20>;
2823 }; 2718 };
2824 csi20 2719 csi20vin4: endpoint@4 {
2825 2720 reg = <4>;
2826 2721 remote-endpoint = <&vin4csi20>;
2827 }; 2722 };
2828 csi20 2723 csi20vin5: endpoint@5 {
2829 2724 reg = <5>;
2830 2725 remote-endpoint = <&vin5csi20>;
2831 }; 2726 };
2832 csi20 2727 csi20vin6: endpoint@6 {
2833 2728 reg = <6>;
2834 2729 remote-endpoint = <&vin6csi20>;
2835 }; 2730 };
2836 csi20 2731 csi20vin7: endpoint@7 {
2837 2732 reg = <7>;
2838 2733 remote-endpoint = <&vin7csi20>;
2839 }; 2734 };
2840 }; 2735 };
2841 }; 2736 };
2842 }; 2737 };
2843 2738
2844 csi40: csi2@feaa0000 { 2739 csi40: csi2@feaa0000 {
2845 compatible = "renesas 2740 compatible = "renesas,r8a7796-csi2";
2846 reg = <0 0xfeaa0000 0 2741 reg = <0 0xfeaa0000 0 0x10000>;
2847 interrupts = <GIC_SPI 2742 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
2848 clocks = <&cpg CPG_MO 2743 clocks = <&cpg CPG_MOD 716>;
2849 power-domains = <&sys 2744 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2850 resets = <&cpg 716>; 2745 resets = <&cpg 716>;
2851 status = "disabled"; 2746 status = "disabled";
2852 2747
2853 ports { 2748 ports {
2854 #address-cell 2749 #address-cells = <1>;
2855 #size-cells = 2750 #size-cells = <0>;
2856 2751
2857 port@0 { <<
2858 reg = <<
2859 }; <<
2860 <<
2861 port@1 { 2752 port@1 {
2862 #addr 2753 #address-cells = <1>;
2863 #size 2754 #size-cells = <0>;
2864 2755
2865 reg = 2756 reg = <1>;
2866 2757
2867 csi40 2758 csi40vin0: endpoint@0 {
2868 2759 reg = <0>;
2869 2760 remote-endpoint = <&vin0csi40>;
2870 }; 2761 };
2871 csi40 2762 csi40vin1: endpoint@1 {
2872 2763 reg = <1>;
2873 2764 remote-endpoint = <&vin1csi40>;
2874 }; 2765 };
2875 csi40 2766 csi40vin2: endpoint@2 {
2876 2767 reg = <2>;
2877 2768 remote-endpoint = <&vin2csi40>;
2878 }; 2769 };
2879 csi40 2770 csi40vin3: endpoint@3 {
2880 2771 reg = <3>;
2881 2772 remote-endpoint = <&vin3csi40>;
2882 }; 2773 };
2883 csi40 2774 csi40vin4: endpoint@4 {
2884 2775 reg = <4>;
2885 2776 remote-endpoint = <&vin4csi40>;
2886 }; 2777 };
2887 csi40 2778 csi40vin5: endpoint@5 {
2888 2779 reg = <5>;
2889 2780 remote-endpoint = <&vin5csi40>;
2890 }; 2781 };
2891 csi40 2782 csi40vin6: endpoint@6 {
2892 2783 reg = <6>;
2893 2784 remote-endpoint = <&vin6csi40>;
2894 }; 2785 };
2895 csi40 2786 csi40vin7: endpoint@7 {
2896 2787 reg = <7>;
2897 2788 remote-endpoint = <&vin7csi40>;
2898 }; 2789 };
2899 }; 2790 };
2900 2791
2901 }; 2792 };
2902 }; 2793 };
2903 2794
2904 hdmi0: hdmi@fead0000 { 2795 hdmi0: hdmi@fead0000 {
2905 compatible = "renesas 2796 compatible = "renesas,r8a7796-hdmi", "renesas,rcar-gen3-hdmi";
2906 reg = <0 0xfead0000 0 2797 reg = <0 0xfead0000 0 0x10000>;
2907 interrupts = <GIC_SPI 2798 interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
2908 clocks = <&cpg CPG_MO 2799 clocks = <&cpg CPG_MOD 729>, <&cpg CPG_CORE R8A7796_CLK_HDMI>;
2909 clock-names = "iahb", 2800 clock-names = "iahb", "isfr";
2910 power-domains = <&sys 2801 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2911 resets = <&cpg 729>; 2802 resets = <&cpg 729>;
2912 status = "disabled"; 2803 status = "disabled";
2913 2804
2914 ports { 2805 ports {
2915 #address-cell 2806 #address-cells = <1>;
2916 #size-cells = 2807 #size-cells = <0>;
2917 port@0 { 2808 port@0 {
2918 reg = 2809 reg = <0>;
2919 dw_hd 2810 dw_hdmi0_in: endpoint {
2920 2811 remote-endpoint = <&du_out_hdmi0>;
2921 }; 2812 };
2922 }; 2813 };
2923 port@1 { 2814 port@1 {
2924 reg = 2815 reg = <1>;
2925 }; 2816 };
2926 port@2 { 2817 port@2 {
2927 /* HD 2818 /* HDMI sound */
2928 reg = 2819 reg = <2>;
2929 }; 2820 };
2930 }; 2821 };
2931 }; 2822 };
2932 2823
2933 du: display@feb00000 { 2824 du: display@feb00000 {
2934 compatible = "renesas 2825 compatible = "renesas,du-r8a7796";
2935 reg = <0 0xfeb00000 0 2826 reg = <0 0xfeb00000 0 0x70000>;
2936 interrupts = <GIC_SPI 2827 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
2937 <GIC_SPI 2828 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
2938 <GIC_SPI 2829 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
2939 clocks = <&cpg CPG_MO 2830 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
2940 <&cpg CPG_MO 2831 <&cpg CPG_MOD 722>;
2941 clock-names = "du.0", 2832 clock-names = "du.0", "du.1", "du.2";
2942 resets = <&cpg 724>, 2833 resets = <&cpg 724>, <&cpg 722>;
2943 reset-names = "du.0", 2834 reset-names = "du.0", "du.2";
2944 2835
2945 renesas,cmms = <&cmm0 2836 renesas,cmms = <&cmm0>, <&cmm1>, <&cmm2>;
2946 renesas,vsps = <&vspd 2837 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>;
2947 2838
2948 status = "disabled"; 2839 status = "disabled";
2949 2840
2950 ports { 2841 ports {
2951 #address-cell 2842 #address-cells = <1>;
2952 #size-cells = 2843 #size-cells = <0>;
2953 2844
2954 port@0 { 2845 port@0 {
2955 reg = 2846 reg = <0>;
>> 2847 du_out_rgb: endpoint {
>> 2848 };
2956 }; 2849 };
2957 port@1 { 2850 port@1 {
2958 reg = 2851 reg = <1>;
2959 du_ou 2852 du_out_hdmi0: endpoint {
2960 2853 remote-endpoint = <&dw_hdmi0_in>;
2961 }; 2854 };
2962 }; 2855 };
2963 port@2 { 2856 port@2 {
2964 reg = 2857 reg = <2>;
2965 du_ou 2858 du_out_lvds0: endpoint {
2966 2859 remote-endpoint = <&lvds0_in>;
2967 }; 2860 };
2968 }; 2861 };
2969 }; 2862 };
2970 }; 2863 };
2971 2864
2972 lvds0: lvds@feb90000 { 2865 lvds0: lvds@feb90000 {
2973 compatible = "renesas 2866 compatible = "renesas,r8a7796-lvds";
2974 reg = <0 0xfeb90000 0 2867 reg = <0 0xfeb90000 0 0x14>;
2975 clocks = <&cpg CPG_MO 2868 clocks = <&cpg CPG_MOD 727>;
2976 power-domains = <&sys 2869 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2977 resets = <&cpg 727>; 2870 resets = <&cpg 727>;
2978 status = "disabled"; 2871 status = "disabled";
2979 2872
2980 ports { 2873 ports {
2981 #address-cell 2874 #address-cells = <1>;
2982 #size-cells = 2875 #size-cells = <0>;
2983 2876
2984 port@0 { 2877 port@0 {
2985 reg = 2878 reg = <0>;
2986 lvds0 2879 lvds0_in: endpoint {
2987 2880 remote-endpoint = <&du_out_lvds0>;
2988 }; 2881 };
2989 }; 2882 };
2990 port@1 { 2883 port@1 {
2991 reg = 2884 reg = <1>;
>> 2885 lvds0_out: endpoint {
>> 2886 };
2992 }; 2887 };
2993 }; 2888 };
2994 }; 2889 };
2995 2890
2996 prr: chipid@fff00044 { 2891 prr: chipid@fff00044 {
2997 compatible = "renesas 2892 compatible = "renesas,prr";
2998 reg = <0 0xfff00044 0 2893 reg = <0 0xfff00044 0 4>;
2999 }; 2894 };
3000 }; 2895 };
3001 2896
3002 thermal-zones { 2897 thermal-zones {
3003 sensor1_thermal: sensor1-ther !! 2898 sensor_thermal1: sensor-thermal1 {
3004 polling-delay-passive 2899 polling-delay-passive = <250>;
3005 polling-delay = <1000 2900 polling-delay = <1000>;
3006 thermal-sensors = <&t 2901 thermal-sensors = <&tsc 0>;
3007 sustainable-power = < 2902 sustainable-power = <3874>;
3008 2903
3009 trips { 2904 trips {
3010 sensor1_crit: 2905 sensor1_crit: sensor1-crit {
3011 tempe 2906 temperature = <120000>;
3012 hyste 2907 hysteresis = <1000>;
3013 type 2908 type = "critical";
3014 }; 2909 };
3015 }; 2910 };
3016 }; 2911 };
3017 2912
3018 sensor2_thermal: sensor2-ther !! 2913 sensor_thermal2: sensor-thermal2 {
3019 polling-delay-passive 2914 polling-delay-passive = <250>;
3020 polling-delay = <1000 2915 polling-delay = <1000>;
3021 thermal-sensors = <&t 2916 thermal-sensors = <&tsc 1>;
3022 sustainable-power = < 2917 sustainable-power = <3874>;
3023 2918
3024 trips { 2919 trips {
3025 sensor2_crit: 2920 sensor2_crit: sensor2-crit {
3026 tempe 2921 temperature = <120000>;
3027 hyste 2922 hysteresis = <1000>;
3028 type 2923 type = "critical";
3029 }; 2924 };
3030 }; 2925 };
3031 }; 2926 };
3032 2927
3033 sensor3_thermal: sensor3-ther !! 2928 sensor_thermal3: sensor-thermal3 {
3034 polling-delay-passive 2929 polling-delay-passive = <250>;
3035 polling-delay = <1000 2930 polling-delay = <1000>;
3036 thermal-sensors = <&t 2931 thermal-sensors = <&tsc 2>;
3037 sustainable-power = < 2932 sustainable-power = <3874>;
3038 2933
3039 cooling-maps { 2934 cooling-maps {
3040 map0 { 2935 map0 {
3041 trip 2936 trip = <&target>;
3042 cooli 2937 cooling-device = <&a57_0 2 4>;
3043 contr 2938 contribution = <1024>;
3044 }; 2939 };
3045 map1 { 2940 map1 {
3046 trip 2941 trip = <&target>;
3047 cooli 2942 cooling-device = <&a53_0 0 2>;
3048 contr 2943 contribution = <1024>;
3049 }; 2944 };
3050 }; 2945 };
3051 trips { 2946 trips {
3052 target: trip- 2947 target: trip-point1 {
3053 tempe 2948 temperature = <100000>;
3054 hyste 2949 hysteresis = <1000>;
3055 type 2950 type = "passive";
3056 }; 2951 };
3057 2952
3058 sensor3_crit: 2953 sensor3_crit: sensor3-crit {
3059 tempe 2954 temperature = <120000>;
3060 hyste 2955 hysteresis = <1000>;
3061 type 2956 type = "critical";
3062 }; 2957 };
3063 }; 2958 };
3064 }; 2959 };
3065 }; 2960 };
3066 2961
3067 timer { 2962 timer {
3068 compatible = "arm,armv8-timer 2963 compatible = "arm,armv8-timer";
3069 interrupts-extended = <&gic G 2964 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
3070 <&gic G 2965 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
3071 <&gic G 2966 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
3072 <&gic G 2967 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
3073 interrupt-names = "sec-phys", <<
3074 }; 2968 };
3075 2969
3076 /* External USB clocks - can be overr 2970 /* External USB clocks - can be overridden by the board */
3077 usb3s0_clk: usb3s0 { 2971 usb3s0_clk: usb3s0 {
3078 compatible = "fixed-clock"; 2972 compatible = "fixed-clock";
3079 #clock-cells = <0>; 2973 #clock-cells = <0>;
3080 clock-frequency = <0>; 2974 clock-frequency = <0>;
3081 }; 2975 };
3082 2976
3083 usb_extal_clk: usb_extal { 2977 usb_extal_clk: usb_extal {
3084 compatible = "fixed-clock"; 2978 compatible = "fixed-clock";
3085 #clock-cells = <0>; 2979 #clock-cells = <0>;
3086 clock-frequency = <0>; 2980 clock-frequency = <0>;
3087 }; 2981 };
3088 }; 2982 };
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