1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * Device Tree Source for the R-Car M3-W (R8A7 3 * Device Tree Source for the R-Car M3-W (R8A77960) SoC
4 * 4 *
5 * Copyright (C) 2016-2017 Renesas Electronics 5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
6 */ 6 */
7 7
8 #include <dt-bindings/clock/r8a7796-cpg-mssr.h 8 #include <dt-bindings/clock/r8a7796-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm 9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a7796-sysc.h> 10 #include <dt-bindings/power/r8a7796-sysc.h>
11 11
>> 12 #define CPG_AUDIO_CLK_I R8A7796_CLK_S0D4
>> 13
12 / { 14 / {
13 compatible = "renesas,r8a7796"; 15 compatible = "renesas,r8a7796";
14 #address-cells = <2>; 16 #address-cells = <2>;
15 #size-cells = <2>; 17 #size-cells = <2>;
16 18
>> 19 aliases {
>> 20 i2c0 = &i2c0;
>> 21 i2c1 = &i2c1;
>> 22 i2c2 = &i2c2;
>> 23 i2c3 = &i2c3;
>> 24 i2c4 = &i2c4;
>> 25 i2c5 = &i2c5;
>> 26 i2c6 = &i2c6;
>> 27 i2c7 = &i2c_dvfs;
>> 28 };
>> 29
17 /* 30 /*
18 * The external audio clocks are confi 31 * The external audio clocks are configured as 0 Hz fixed frequency
19 * clocks by default. 32 * clocks by default.
20 * Boards that provide audio clocks sh 33 * Boards that provide audio clocks should override them.
21 */ 34 */
22 audio_clk_a: audio_clk_a { 35 audio_clk_a: audio_clk_a {
23 compatible = "fixed-clock"; 36 compatible = "fixed-clock";
24 #clock-cells = <0>; 37 #clock-cells = <0>;
25 clock-frequency = <0>; 38 clock-frequency = <0>;
26 }; 39 };
27 40
28 audio_clk_b: audio_clk_b { 41 audio_clk_b: audio_clk_b {
29 compatible = "fixed-clock"; 42 compatible = "fixed-clock";
30 #clock-cells = <0>; 43 #clock-cells = <0>;
31 clock-frequency = <0>; 44 clock-frequency = <0>;
32 }; 45 };
33 46
34 audio_clk_c: audio_clk_c { 47 audio_clk_c: audio_clk_c {
35 compatible = "fixed-clock"; 48 compatible = "fixed-clock";
36 #clock-cells = <0>; 49 #clock-cells = <0>;
37 clock-frequency = <0>; 50 clock-frequency = <0>;
38 }; 51 };
39 52
40 /* External CAN clock - to be overridd 53 /* External CAN clock - to be overridden by boards that provide it */
41 can_clk: can { 54 can_clk: can {
42 compatible = "fixed-clock"; 55 compatible = "fixed-clock";
43 #clock-cells = <0>; 56 #clock-cells = <0>;
44 clock-frequency = <0>; 57 clock-frequency = <0>;
45 }; 58 };
46 59
47 cluster0_opp: opp-table-0 { 60 cluster0_opp: opp-table-0 {
48 compatible = "operating-points 61 compatible = "operating-points-v2";
49 opp-shared; 62 opp-shared;
50 63
51 opp-500000000 { 64 opp-500000000 {
52 opp-hz = /bits/ 64 <50 65 opp-hz = /bits/ 64 <500000000>;
53 opp-microvolt = <83000 66 opp-microvolt = <830000>;
54 clock-latency-ns = <30 67 clock-latency-ns = <300000>;
55 }; 68 };
56 opp-1000000000 { 69 opp-1000000000 {
57 opp-hz = /bits/ 64 <10 70 opp-hz = /bits/ 64 <1000000000>;
58 opp-microvolt = <83000 71 opp-microvolt = <830000>;
59 clock-latency-ns = <30 72 clock-latency-ns = <300000>;
60 }; 73 };
61 opp-1500000000 { 74 opp-1500000000 {
62 opp-hz = /bits/ 64 <15 75 opp-hz = /bits/ 64 <1500000000>;
63 opp-microvolt = <83000 76 opp-microvolt = <830000>;
64 clock-latency-ns = <30 77 clock-latency-ns = <300000>;
65 opp-suspend; 78 opp-suspend;
66 }; 79 };
67 opp-1600000000 { 80 opp-1600000000 {
68 opp-hz = /bits/ 64 <16 81 opp-hz = /bits/ 64 <1600000000>;
69 opp-microvolt = <90000 82 opp-microvolt = <900000>;
70 clock-latency-ns = <30 83 clock-latency-ns = <300000>;
>> 84 turbo-mode;
71 }; 85 };
72 opp-1700000000 { 86 opp-1700000000 {
73 opp-hz = /bits/ 64 <17 87 opp-hz = /bits/ 64 <1700000000>;
74 opp-microvolt = <90000 88 opp-microvolt = <900000>;
75 clock-latency-ns = <30 89 clock-latency-ns = <300000>;
>> 90 turbo-mode;
76 }; 91 };
77 opp-1800000000 { 92 opp-1800000000 {
78 opp-hz = /bits/ 64 <18 93 opp-hz = /bits/ 64 <1800000000>;
79 opp-microvolt = <96000 94 opp-microvolt = <960000>;
80 clock-latency-ns = <30 95 clock-latency-ns = <300000>;
81 turbo-mode; 96 turbo-mode;
82 }; 97 };
83 }; 98 };
84 99
85 cluster1_opp: opp-table-1 { 100 cluster1_opp: opp-table-1 {
86 compatible = "operating-points 101 compatible = "operating-points-v2";
87 opp-shared; 102 opp-shared;
88 103
89 opp-800000000 { 104 opp-800000000 {
90 opp-hz = /bits/ 64 <80 105 opp-hz = /bits/ 64 <800000000>;
91 opp-microvolt = <82000 106 opp-microvolt = <820000>;
92 clock-latency-ns = <30 107 clock-latency-ns = <300000>;
93 }; 108 };
94 opp-1000000000 { 109 opp-1000000000 {
95 opp-hz = /bits/ 64 <10 110 opp-hz = /bits/ 64 <1000000000>;
96 opp-microvolt = <82000 111 opp-microvolt = <820000>;
97 clock-latency-ns = <30 112 clock-latency-ns = <300000>;
98 }; 113 };
99 opp-1200000000 { 114 opp-1200000000 {
100 opp-hz = /bits/ 64 <12 115 opp-hz = /bits/ 64 <1200000000>;
101 opp-microvolt = <82000 116 opp-microvolt = <820000>;
102 clock-latency-ns = <30 117 clock-latency-ns = <300000>;
103 }; 118 };
104 opp-1300000000 { 119 opp-1300000000 {
105 opp-hz = /bits/ 64 <13 120 opp-hz = /bits/ 64 <1300000000>;
106 opp-microvolt = <82000 121 opp-microvolt = <820000>;
107 clock-latency-ns = <30 122 clock-latency-ns = <300000>;
108 turbo-mode; 123 turbo-mode;
109 }; 124 };
110 }; 125 };
111 126
112 cpus { 127 cpus {
113 #address-cells = <1>; 128 #address-cells = <1>;
114 #size-cells = <0>; 129 #size-cells = <0>;
115 130
116 cpu-map { 131 cpu-map {
117 cluster0 { 132 cluster0 {
118 core0 { 133 core0 {
119 cpu = 134 cpu = <&a57_0>;
120 }; 135 };
121 core1 { 136 core1 {
122 cpu = 137 cpu = <&a57_1>;
123 }; 138 };
124 }; 139 };
125 140
126 cluster1 { 141 cluster1 {
127 core0 { 142 core0 {
128 cpu = 143 cpu = <&a53_0>;
129 }; 144 };
130 core1 { 145 core1 {
131 cpu = 146 cpu = <&a53_1>;
132 }; 147 };
133 core2 { 148 core2 {
134 cpu = 149 cpu = <&a53_2>;
135 }; 150 };
136 core3 { 151 core3 {
137 cpu = 152 cpu = <&a53_3>;
138 }; 153 };
139 }; 154 };
140 }; 155 };
141 156
142 a57_0: cpu@0 { 157 a57_0: cpu@0 {
143 compatible = "arm,cort 158 compatible = "arm,cortex-a57";
144 reg = <0x0>; 159 reg = <0x0>;
145 device_type = "cpu"; 160 device_type = "cpu";
146 power-domains = <&sysc 161 power-domains = <&sysc R8A7796_PD_CA57_CPU0>;
147 next-level-cache = <&L 162 next-level-cache = <&L2_CA57>;
148 enable-method = "psci" 163 enable-method = "psci";
149 cpu-idle-states = <&CP 164 cpu-idle-states = <&CPU_SLEEP_0>;
150 dynamic-power-coeffici 165 dynamic-power-coefficient = <854>;
151 clocks = <&cpg CPG_COR 166 clocks = <&cpg CPG_CORE R8A7796_CLK_Z>;
152 operating-points-v2 = 167 operating-points-v2 = <&cluster0_opp>;
153 capacity-dmips-mhz = < 168 capacity-dmips-mhz = <1024>;
154 #cooling-cells = <2>; 169 #cooling-cells = <2>;
155 }; 170 };
156 171
157 a57_1: cpu@1 { 172 a57_1: cpu@1 {
158 compatible = "arm,cort 173 compatible = "arm,cortex-a57";
159 reg = <0x1>; 174 reg = <0x1>;
160 device_type = "cpu"; 175 device_type = "cpu";
161 power-domains = <&sysc 176 power-domains = <&sysc R8A7796_PD_CA57_CPU1>;
162 next-level-cache = <&L 177 next-level-cache = <&L2_CA57>;
163 enable-method = "psci" 178 enable-method = "psci";
164 cpu-idle-states = <&CP 179 cpu-idle-states = <&CPU_SLEEP_0>;
165 clocks = <&cpg CPG_COR 180 clocks = <&cpg CPG_CORE R8A7796_CLK_Z>;
166 operating-points-v2 = 181 operating-points-v2 = <&cluster0_opp>;
167 capacity-dmips-mhz = < 182 capacity-dmips-mhz = <1024>;
168 #cooling-cells = <2>; 183 #cooling-cells = <2>;
169 }; 184 };
170 185
171 a53_0: cpu@100 { 186 a53_0: cpu@100 {
172 compatible = "arm,cort 187 compatible = "arm,cortex-a53";
173 reg = <0x100>; 188 reg = <0x100>;
174 device_type = "cpu"; 189 device_type = "cpu";
175 power-domains = <&sysc 190 power-domains = <&sysc R8A7796_PD_CA53_CPU0>;
176 next-level-cache = <&L 191 next-level-cache = <&L2_CA53>;
177 enable-method = "psci" 192 enable-method = "psci";
178 cpu-idle-states = <&CP 193 cpu-idle-states = <&CPU_SLEEP_1>;
179 #cooling-cells = <2>; 194 #cooling-cells = <2>;
180 dynamic-power-coeffici 195 dynamic-power-coefficient = <277>;
181 clocks = <&cpg CPG_COR 196 clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
182 operating-points-v2 = 197 operating-points-v2 = <&cluster1_opp>;
183 capacity-dmips-mhz = < 198 capacity-dmips-mhz = <535>;
184 }; 199 };
185 200
186 a53_1: cpu@101 { 201 a53_1: cpu@101 {
187 compatible = "arm,cort 202 compatible = "arm,cortex-a53";
188 reg = <0x101>; 203 reg = <0x101>;
189 device_type = "cpu"; 204 device_type = "cpu";
190 power-domains = <&sysc 205 power-domains = <&sysc R8A7796_PD_CA53_CPU1>;
191 next-level-cache = <&L 206 next-level-cache = <&L2_CA53>;
192 enable-method = "psci" 207 enable-method = "psci";
193 cpu-idle-states = <&CP 208 cpu-idle-states = <&CPU_SLEEP_1>;
194 clocks = <&cpg CPG_COR 209 clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
195 operating-points-v2 = 210 operating-points-v2 = <&cluster1_opp>;
196 capacity-dmips-mhz = < 211 capacity-dmips-mhz = <535>;
197 }; 212 };
198 213
199 a53_2: cpu@102 { 214 a53_2: cpu@102 {
200 compatible = "arm,cort 215 compatible = "arm,cortex-a53";
201 reg = <0x102>; 216 reg = <0x102>;
202 device_type = "cpu"; 217 device_type = "cpu";
203 power-domains = <&sysc 218 power-domains = <&sysc R8A7796_PD_CA53_CPU2>;
204 next-level-cache = <&L 219 next-level-cache = <&L2_CA53>;
205 enable-method = "psci" 220 enable-method = "psci";
206 cpu-idle-states = <&CP 221 cpu-idle-states = <&CPU_SLEEP_1>;
207 clocks = <&cpg CPG_COR 222 clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
208 operating-points-v2 = 223 operating-points-v2 = <&cluster1_opp>;
209 capacity-dmips-mhz = < 224 capacity-dmips-mhz = <535>;
210 }; 225 };
211 226
212 a53_3: cpu@103 { 227 a53_3: cpu@103 {
213 compatible = "arm,cort 228 compatible = "arm,cortex-a53";
214 reg = <0x103>; 229 reg = <0x103>;
215 device_type = "cpu"; 230 device_type = "cpu";
216 power-domains = <&sysc 231 power-domains = <&sysc R8A7796_PD_CA53_CPU3>;
217 next-level-cache = <&L 232 next-level-cache = <&L2_CA53>;
218 enable-method = "psci" 233 enable-method = "psci";
219 cpu-idle-states = <&CP 234 cpu-idle-states = <&CPU_SLEEP_1>;
220 clocks = <&cpg CPG_COR 235 clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
221 operating-points-v2 = 236 operating-points-v2 = <&cluster1_opp>;
222 capacity-dmips-mhz = < 237 capacity-dmips-mhz = <535>;
223 }; 238 };
224 239
225 L2_CA57: cache-controller-0 { 240 L2_CA57: cache-controller-0 {
226 compatible = "cache"; 241 compatible = "cache";
227 power-domains = <&sysc 242 power-domains = <&sysc R8A7796_PD_CA57_SCU>;
228 cache-unified; 243 cache-unified;
229 cache-level = <2>; 244 cache-level = <2>;
230 }; 245 };
231 246
232 L2_CA53: cache-controller-1 { 247 L2_CA53: cache-controller-1 {
233 compatible = "cache"; 248 compatible = "cache";
234 power-domains = <&sysc 249 power-domains = <&sysc R8A7796_PD_CA53_SCU>;
235 cache-unified; 250 cache-unified;
236 cache-level = <2>; 251 cache-level = <2>;
237 }; 252 };
238 253
239 idle-states { 254 idle-states {
240 entry-method = "psci"; 255 entry-method = "psci";
241 256
242 CPU_SLEEP_0: cpu-sleep 257 CPU_SLEEP_0: cpu-sleep-0 {
243 compatible = " 258 compatible = "arm,idle-state";
244 arm,psci-suspe 259 arm,psci-suspend-param = <0x0010000>;
245 local-timer-st 260 local-timer-stop;
246 entry-latency- 261 entry-latency-us = <400>;
247 exit-latency-u 262 exit-latency-us = <500>;
248 min-residency- 263 min-residency-us = <4000>;
249 }; 264 };
250 265
251 CPU_SLEEP_1: cpu-sleep 266 CPU_SLEEP_1: cpu-sleep-1 {
252 compatible = " 267 compatible = "arm,idle-state";
253 arm,psci-suspe 268 arm,psci-suspend-param = <0x0010000>;
254 local-timer-st 269 local-timer-stop;
255 entry-latency- 270 entry-latency-us = <700>;
256 exit-latency-u 271 exit-latency-us = <700>;
257 min-residency- 272 min-residency-us = <5000>;
258 }; 273 };
259 }; 274 };
260 }; 275 };
261 276
262 extal_clk: extal { 277 extal_clk: extal {
263 compatible = "fixed-clock"; 278 compatible = "fixed-clock";
264 #clock-cells = <0>; 279 #clock-cells = <0>;
265 /* This value must be overridd 280 /* This value must be overridden by the board */
266 clock-frequency = <0>; 281 clock-frequency = <0>;
267 }; 282 };
268 283
269 extalr_clk: extalr { 284 extalr_clk: extalr {
270 compatible = "fixed-clock"; 285 compatible = "fixed-clock";
271 #clock-cells = <0>; 286 #clock-cells = <0>;
272 /* This value must be overridd 287 /* This value must be overridden by the board */
273 clock-frequency = <0>; 288 clock-frequency = <0>;
274 }; 289 };
275 290
276 /* External PCIe clock - can be overri 291 /* External PCIe clock - can be overridden by the board */
277 pcie_bus_clk: pcie_bus { 292 pcie_bus_clk: pcie_bus {
278 compatible = "fixed-clock"; 293 compatible = "fixed-clock";
279 #clock-cells = <0>; 294 #clock-cells = <0>;
280 clock-frequency = <0>; 295 clock-frequency = <0>;
281 }; 296 };
282 297
283 pmu_a53 { 298 pmu_a53 {
284 compatible = "arm,cortex-a53-p 299 compatible = "arm,cortex-a53-pmu";
285 interrupts-extended = <&gic GI 300 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
286 <&gic GI 301 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
287 <&gic GI 302 <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
288 <&gic GI 303 <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
289 interrupt-affinity = <&a53_0>, 304 interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>;
290 }; 305 };
291 306
292 pmu_a57 { 307 pmu_a57 {
293 compatible = "arm,cortex-a57-p 308 compatible = "arm,cortex-a57-pmu";
294 interrupts-extended = <&gic GI 309 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
295 <&gic GI 310 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
296 interrupt-affinity = <&a57_0>, 311 interrupt-affinity = <&a57_0>, <&a57_1>;
297 }; 312 };
298 313
299 psci { 314 psci {
300 compatible = "arm,psci-1.0", " 315 compatible = "arm,psci-1.0", "arm,psci-0.2";
301 method = "smc"; 316 method = "smc";
302 }; 317 };
303 318
304 /* External SCIF clock - to be overrid 319 /* External SCIF clock - to be overridden by boards that provide it */
305 scif_clk: scif { 320 scif_clk: scif {
306 compatible = "fixed-clock"; 321 compatible = "fixed-clock";
307 #clock-cells = <0>; 322 #clock-cells = <0>;
308 clock-frequency = <0>; 323 clock-frequency = <0>;
309 }; 324 };
310 325
311 soc { 326 soc {
312 compatible = "simple-bus"; 327 compatible = "simple-bus";
313 interrupt-parent = <&gic>; 328 interrupt-parent = <&gic>;
314 #address-cells = <2>; 329 #address-cells = <2>;
315 #size-cells = <2>; 330 #size-cells = <2>;
316 ranges; 331 ranges;
317 332
318 rwdt: watchdog@e6020000 { 333 rwdt: watchdog@e6020000 {
319 compatible = "renesas, 334 compatible = "renesas,r8a7796-wdt",
320 "renesas, 335 "renesas,rcar-gen3-wdt";
321 reg = <0 0xe6020000 0 336 reg = <0 0xe6020000 0 0x0c>;
322 interrupts = <GIC_SPI 337 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
323 clocks = <&cpg CPG_MOD 338 clocks = <&cpg CPG_MOD 402>;
324 power-domains = <&sysc 339 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
325 resets = <&cpg 402>; 340 resets = <&cpg 402>;
326 status = "disabled"; 341 status = "disabled";
327 }; 342 };
328 343
329 gpio0: gpio@e6050000 { 344 gpio0: gpio@e6050000 {
330 compatible = "renesas, 345 compatible = "renesas,gpio-r8a7796",
331 "renesas, 346 "renesas,rcar-gen3-gpio";
332 reg = <0 0xe6050000 0 347 reg = <0 0xe6050000 0 0x50>;
333 interrupts = <GIC_SPI 348 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
334 #gpio-cells = <2>; 349 #gpio-cells = <2>;
335 gpio-controller; 350 gpio-controller;
336 gpio-ranges = <&pfc 0 351 gpio-ranges = <&pfc 0 0 16>;
337 #interrupt-cells = <2> 352 #interrupt-cells = <2>;
338 interrupt-controller; 353 interrupt-controller;
339 clocks = <&cpg CPG_MOD 354 clocks = <&cpg CPG_MOD 912>;
340 power-domains = <&sysc 355 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
341 resets = <&cpg 912>; 356 resets = <&cpg 912>;
342 }; 357 };
343 358
344 gpio1: gpio@e6051000 { 359 gpio1: gpio@e6051000 {
345 compatible = "renesas, 360 compatible = "renesas,gpio-r8a7796",
346 "renesas, 361 "renesas,rcar-gen3-gpio";
347 reg = <0 0xe6051000 0 362 reg = <0 0xe6051000 0 0x50>;
348 interrupts = <GIC_SPI 363 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
349 #gpio-cells = <2>; 364 #gpio-cells = <2>;
350 gpio-controller; 365 gpio-controller;
351 gpio-ranges = <&pfc 0 366 gpio-ranges = <&pfc 0 32 29>;
352 #interrupt-cells = <2> 367 #interrupt-cells = <2>;
353 interrupt-controller; 368 interrupt-controller;
354 clocks = <&cpg CPG_MOD 369 clocks = <&cpg CPG_MOD 911>;
355 power-domains = <&sysc 370 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
356 resets = <&cpg 911>; 371 resets = <&cpg 911>;
357 }; 372 };
358 373
359 gpio2: gpio@e6052000 { 374 gpio2: gpio@e6052000 {
360 compatible = "renesas, 375 compatible = "renesas,gpio-r8a7796",
361 "renesas, 376 "renesas,rcar-gen3-gpio";
362 reg = <0 0xe6052000 0 377 reg = <0 0xe6052000 0 0x50>;
363 interrupts = <GIC_SPI 378 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
364 #gpio-cells = <2>; 379 #gpio-cells = <2>;
365 gpio-controller; 380 gpio-controller;
366 gpio-ranges = <&pfc 0 381 gpio-ranges = <&pfc 0 64 15>;
367 #interrupt-cells = <2> 382 #interrupt-cells = <2>;
368 interrupt-controller; 383 interrupt-controller;
369 clocks = <&cpg CPG_MOD 384 clocks = <&cpg CPG_MOD 910>;
370 power-domains = <&sysc 385 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
371 resets = <&cpg 910>; 386 resets = <&cpg 910>;
372 }; 387 };
373 388
374 gpio3: gpio@e6053000 { 389 gpio3: gpio@e6053000 {
375 compatible = "renesas, 390 compatible = "renesas,gpio-r8a7796",
376 "renesas, 391 "renesas,rcar-gen3-gpio";
377 reg = <0 0xe6053000 0 392 reg = <0 0xe6053000 0 0x50>;
378 interrupts = <GIC_SPI 393 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
379 #gpio-cells = <2>; 394 #gpio-cells = <2>;
380 gpio-controller; 395 gpio-controller;
381 gpio-ranges = <&pfc 0 396 gpio-ranges = <&pfc 0 96 16>;
382 #interrupt-cells = <2> 397 #interrupt-cells = <2>;
383 interrupt-controller; 398 interrupt-controller;
384 clocks = <&cpg CPG_MOD 399 clocks = <&cpg CPG_MOD 909>;
385 power-domains = <&sysc 400 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
386 resets = <&cpg 909>; 401 resets = <&cpg 909>;
387 }; 402 };
388 403
389 gpio4: gpio@e6054000 { 404 gpio4: gpio@e6054000 {
390 compatible = "renesas, 405 compatible = "renesas,gpio-r8a7796",
391 "renesas, 406 "renesas,rcar-gen3-gpio";
392 reg = <0 0xe6054000 0 407 reg = <0 0xe6054000 0 0x50>;
393 interrupts = <GIC_SPI 408 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
394 #gpio-cells = <2>; 409 #gpio-cells = <2>;
395 gpio-controller; 410 gpio-controller;
396 gpio-ranges = <&pfc 0 411 gpio-ranges = <&pfc 0 128 18>;
397 #interrupt-cells = <2> 412 #interrupt-cells = <2>;
398 interrupt-controller; 413 interrupt-controller;
399 clocks = <&cpg CPG_MOD 414 clocks = <&cpg CPG_MOD 908>;
400 power-domains = <&sysc 415 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
401 resets = <&cpg 908>; 416 resets = <&cpg 908>;
402 }; 417 };
403 418
404 gpio5: gpio@e6055000 { 419 gpio5: gpio@e6055000 {
405 compatible = "renesas, 420 compatible = "renesas,gpio-r8a7796",
406 "renesas, 421 "renesas,rcar-gen3-gpio";
407 reg = <0 0xe6055000 0 422 reg = <0 0xe6055000 0 0x50>;
408 interrupts = <GIC_SPI 423 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
409 #gpio-cells = <2>; 424 #gpio-cells = <2>;
410 gpio-controller; 425 gpio-controller;
411 gpio-ranges = <&pfc 0 426 gpio-ranges = <&pfc 0 160 26>;
412 #interrupt-cells = <2> 427 #interrupt-cells = <2>;
413 interrupt-controller; 428 interrupt-controller;
414 clocks = <&cpg CPG_MOD 429 clocks = <&cpg CPG_MOD 907>;
415 power-domains = <&sysc 430 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
416 resets = <&cpg 907>; 431 resets = <&cpg 907>;
417 }; 432 };
418 433
419 gpio6: gpio@e6055400 { 434 gpio6: gpio@e6055400 {
420 compatible = "renesas, 435 compatible = "renesas,gpio-r8a7796",
421 "renesas, 436 "renesas,rcar-gen3-gpio";
422 reg = <0 0xe6055400 0 437 reg = <0 0xe6055400 0 0x50>;
423 interrupts = <GIC_SPI 438 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
424 #gpio-cells = <2>; 439 #gpio-cells = <2>;
425 gpio-controller; 440 gpio-controller;
426 gpio-ranges = <&pfc 0 441 gpio-ranges = <&pfc 0 192 32>;
427 #interrupt-cells = <2> 442 #interrupt-cells = <2>;
428 interrupt-controller; 443 interrupt-controller;
429 clocks = <&cpg CPG_MOD 444 clocks = <&cpg CPG_MOD 906>;
430 power-domains = <&sysc 445 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
431 resets = <&cpg 906>; 446 resets = <&cpg 906>;
432 }; 447 };
433 448
434 gpio7: gpio@e6055800 { 449 gpio7: gpio@e6055800 {
435 compatible = "renesas, 450 compatible = "renesas,gpio-r8a7796",
436 "renesas, 451 "renesas,rcar-gen3-gpio";
437 reg = <0 0xe6055800 0 452 reg = <0 0xe6055800 0 0x50>;
438 interrupts = <GIC_SPI 453 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
439 #gpio-cells = <2>; 454 #gpio-cells = <2>;
440 gpio-controller; 455 gpio-controller;
441 gpio-ranges = <&pfc 0 456 gpio-ranges = <&pfc 0 224 4>;
442 #interrupt-cells = <2> 457 #interrupt-cells = <2>;
443 interrupt-controller; 458 interrupt-controller;
444 clocks = <&cpg CPG_MOD 459 clocks = <&cpg CPG_MOD 905>;
445 power-domains = <&sysc 460 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
446 resets = <&cpg 905>; 461 resets = <&cpg 905>;
447 }; 462 };
448 463
449 pfc: pinctrl@e6060000 { 464 pfc: pinctrl@e6060000 {
450 compatible = "renesas, 465 compatible = "renesas,pfc-r8a7796";
451 reg = <0 0xe6060000 0 466 reg = <0 0xe6060000 0 0x50c>;
452 }; 467 };
453 468
454 cmt0: timer@e60f0000 { 469 cmt0: timer@e60f0000 {
455 compatible = "renesas, 470 compatible = "renesas,r8a7796-cmt0",
456 "renesas, 471 "renesas,rcar-gen3-cmt0";
457 reg = <0 0xe60f0000 0 472 reg = <0 0xe60f0000 0 0x1004>;
458 interrupts = <GIC_SPI 473 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
459 <GIC_SPI 474 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
460 clocks = <&cpg CPG_MOD 475 clocks = <&cpg CPG_MOD 303>;
461 clock-names = "fck"; 476 clock-names = "fck";
462 power-domains = <&sysc 477 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
463 resets = <&cpg 303>; 478 resets = <&cpg 303>;
464 status = "disabled"; 479 status = "disabled";
465 }; 480 };
466 481
467 cmt1: timer@e6130000 { 482 cmt1: timer@e6130000 {
468 compatible = "renesas, 483 compatible = "renesas,r8a7796-cmt1",
469 "renesas, 484 "renesas,rcar-gen3-cmt1";
470 reg = <0 0xe6130000 0 485 reg = <0 0xe6130000 0 0x1004>;
471 interrupts = <GIC_SPI 486 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
472 <GIC_SPI 487 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
473 <GIC_SPI 488 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
474 <GIC_SPI 489 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
475 <GIC_SPI 490 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
476 <GIC_SPI 491 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
477 <GIC_SPI 492 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
478 <GIC_SPI 493 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
479 clocks = <&cpg CPG_MOD 494 clocks = <&cpg CPG_MOD 302>;
480 clock-names = "fck"; 495 clock-names = "fck";
481 power-domains = <&sysc 496 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
482 resets = <&cpg 302>; 497 resets = <&cpg 302>;
483 status = "disabled"; 498 status = "disabled";
484 }; 499 };
485 500
486 cmt2: timer@e6140000 { 501 cmt2: timer@e6140000 {
487 compatible = "renesas, 502 compatible = "renesas,r8a7796-cmt1",
488 "renesas, 503 "renesas,rcar-gen3-cmt1";
489 reg = <0 0xe6140000 0 504 reg = <0 0xe6140000 0 0x1004>;
490 interrupts = <GIC_SPI 505 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
491 <GIC_SPI 506 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
492 <GIC_SPI 507 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
493 <GIC_SPI 508 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
494 <GIC_SPI 509 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
495 <GIC_SPI 510 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
496 <GIC_SPI 511 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
497 <GIC_SPI 512 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
498 clocks = <&cpg CPG_MOD 513 clocks = <&cpg CPG_MOD 301>;
499 clock-names = "fck"; 514 clock-names = "fck";
500 power-domains = <&sysc 515 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
501 resets = <&cpg 301>; 516 resets = <&cpg 301>;
502 status = "disabled"; 517 status = "disabled";
503 }; 518 };
504 519
505 cmt3: timer@e6148000 { 520 cmt3: timer@e6148000 {
506 compatible = "renesas, 521 compatible = "renesas,r8a7796-cmt1",
507 "renesas, 522 "renesas,rcar-gen3-cmt1";
508 reg = <0 0xe6148000 0 523 reg = <0 0xe6148000 0 0x1004>;
509 interrupts = <GIC_SPI 524 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
510 <GIC_SPI 525 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
511 <GIC_SPI 526 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
512 <GIC_SPI 527 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
513 <GIC_SPI 528 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
514 <GIC_SPI 529 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
515 <GIC_SPI 530 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
516 <GIC_SPI 531 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
517 clocks = <&cpg CPG_MOD 532 clocks = <&cpg CPG_MOD 300>;
518 clock-names = "fck"; 533 clock-names = "fck";
519 power-domains = <&sysc 534 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
520 resets = <&cpg 300>; 535 resets = <&cpg 300>;
521 status = "disabled"; 536 status = "disabled";
522 }; 537 };
523 538
524 cpg: clock-controller@e6150000 539 cpg: clock-controller@e6150000 {
525 compatible = "renesas, 540 compatible = "renesas,r8a7796-cpg-mssr";
526 reg = <0 0xe6150000 0 541 reg = <0 0xe6150000 0 0x1000>;
527 clocks = <&extal_clk>, 542 clocks = <&extal_clk>, <&extalr_clk>;
528 clock-names = "extal", 543 clock-names = "extal", "extalr";
529 #clock-cells = <2>; 544 #clock-cells = <2>;
530 #power-domain-cells = 545 #power-domain-cells = <0>;
531 #reset-cells = <1>; 546 #reset-cells = <1>;
532 }; 547 };
533 548
534 rst: reset-controller@e6160000 549 rst: reset-controller@e6160000 {
535 compatible = "renesas, 550 compatible = "renesas,r8a7796-rst";
536 reg = <0 0xe6160000 0 551 reg = <0 0xe6160000 0 0x0200>;
537 }; 552 };
538 553
539 sysc: system-controller@e61800 554 sysc: system-controller@e6180000 {
540 compatible = "renesas, 555 compatible = "renesas,r8a7796-sysc";
541 reg = <0 0xe6180000 0 556 reg = <0 0xe6180000 0 0x0400>;
542 #power-domain-cells = 557 #power-domain-cells = <1>;
543 }; 558 };
544 559
545 tsc: thermal@e6198000 { 560 tsc: thermal@e6198000 {
546 compatible = "renesas, 561 compatible = "renesas,r8a7796-thermal";
547 reg = <0 0xe6198000 0 562 reg = <0 0xe6198000 0 0x100>,
548 <0 0xe61a0000 0 563 <0 0xe61a0000 0 0x100>,
549 <0 0xe61a8000 0 564 <0 0xe61a8000 0 0x100>;
550 interrupts = <GIC_SPI 565 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
551 <GIC_SPI 566 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
552 <GIC_SPI 567 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
553 clocks = <&cpg CPG_MOD 568 clocks = <&cpg CPG_MOD 522>;
554 power-domains = <&sysc 569 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
555 resets = <&cpg 522>; 570 resets = <&cpg 522>;
556 #thermal-sensor-cells 571 #thermal-sensor-cells = <1>;
557 }; 572 };
558 573
559 intc_ex: interrupt-controller@ 574 intc_ex: interrupt-controller@e61c0000 {
560 compatible = "renesas, 575 compatible = "renesas,intc-ex-r8a7796", "renesas,irqc";
561 #interrupt-cells = <2> 576 #interrupt-cells = <2>;
562 interrupt-controller; 577 interrupt-controller;
563 reg = <0 0xe61c0000 0 578 reg = <0 0xe61c0000 0 0x200>;
564 interrupts = <GIC_SPI 579 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
565 <GIC_SPI 580 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
566 <GIC_SPI 581 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
567 <GIC_SPI 582 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
568 <GIC_SPI 583 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
569 <GIC_SPI 584 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
570 clocks = <&cpg CPG_MOD 585 clocks = <&cpg CPG_MOD 407>;
571 power-domains = <&sysc 586 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
572 resets = <&cpg 407>; 587 resets = <&cpg 407>;
573 }; 588 };
574 589
575 tmu0: timer@e61e0000 { 590 tmu0: timer@e61e0000 {
576 compatible = "renesas, 591 compatible = "renesas,tmu-r8a7796", "renesas,tmu";
577 reg = <0 0xe61e0000 0 592 reg = <0 0xe61e0000 0 0x30>;
578 interrupts = <GIC_SPI 593 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
579 <GIC_SPI 594 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
580 <GIC_SPI 595 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
581 interrupt-names = "tun <<
582 clocks = <&cpg CPG_MOD 596 clocks = <&cpg CPG_MOD 125>;
583 clock-names = "fck"; 597 clock-names = "fck";
584 power-domains = <&sysc 598 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
585 resets = <&cpg 125>; 599 resets = <&cpg 125>;
586 status = "disabled"; 600 status = "disabled";
587 }; 601 };
588 602
589 tmu1: timer@e6fc0000 { 603 tmu1: timer@e6fc0000 {
590 compatible = "renesas, 604 compatible = "renesas,tmu-r8a7796", "renesas,tmu";
591 reg = <0 0xe6fc0000 0 605 reg = <0 0xe6fc0000 0 0x30>;
592 interrupts = <GIC_SPI 606 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
593 <GIC_SPI 607 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
594 <GIC_SPI !! 608 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
595 <GIC_SPI <<
596 interrupt-names = "tun <<
597 clocks = <&cpg CPG_MOD 609 clocks = <&cpg CPG_MOD 124>;
598 clock-names = "fck"; 610 clock-names = "fck";
599 power-domains = <&sysc 611 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
600 resets = <&cpg 124>; 612 resets = <&cpg 124>;
601 status = "disabled"; 613 status = "disabled";
602 }; 614 };
603 615
604 tmu2: timer@e6fd0000 { 616 tmu2: timer@e6fd0000 {
605 compatible = "renesas, 617 compatible = "renesas,tmu-r8a7796", "renesas,tmu";
606 reg = <0 0xe6fd0000 0 618 reg = <0 0xe6fd0000 0 0x30>;
607 interrupts = <GIC_SPI 619 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
608 <GIC_SPI 620 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
609 <GIC_SPI !! 621 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
610 <GIC_SPI <<
611 interrupt-names = "tun <<
612 clocks = <&cpg CPG_MOD 622 clocks = <&cpg CPG_MOD 123>;
613 clock-names = "fck"; 623 clock-names = "fck";
614 power-domains = <&sysc 624 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
615 resets = <&cpg 123>; 625 resets = <&cpg 123>;
616 status = "disabled"; 626 status = "disabled";
617 }; 627 };
618 628
619 tmu3: timer@e6fe0000 { 629 tmu3: timer@e6fe0000 {
620 compatible = "renesas, 630 compatible = "renesas,tmu-r8a7796", "renesas,tmu";
621 reg = <0 0xe6fe0000 0 631 reg = <0 0xe6fe0000 0 0x30>;
622 interrupts = <GIC_SPI 632 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
623 <GIC_SPI 633 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
624 <GIC_SPI 634 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
625 interrupt-names = "tun <<
626 clocks = <&cpg CPG_MOD 635 clocks = <&cpg CPG_MOD 122>;
627 clock-names = "fck"; 636 clock-names = "fck";
628 power-domains = <&sysc 637 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
629 resets = <&cpg 122>; 638 resets = <&cpg 122>;
630 status = "disabled"; 639 status = "disabled";
631 }; 640 };
632 641
633 tmu4: timer@ffc00000 { 642 tmu4: timer@ffc00000 {
634 compatible = "renesas, 643 compatible = "renesas,tmu-r8a7796", "renesas,tmu";
635 reg = <0 0xffc00000 0 644 reg = <0 0xffc00000 0 0x30>;
636 interrupts = <GIC_SPI 645 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
637 <GIC_SPI 646 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
638 <GIC_SPI 647 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
639 interrupt-names = "tun <<
640 clocks = <&cpg CPG_MOD 648 clocks = <&cpg CPG_MOD 121>;
641 clock-names = "fck"; 649 clock-names = "fck";
642 power-domains = <&sysc 650 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
643 resets = <&cpg 121>; 651 resets = <&cpg 121>;
644 status = "disabled"; 652 status = "disabled";
645 }; 653 };
646 654
647 i2c0: i2c@e6500000 { 655 i2c0: i2c@e6500000 {
648 #address-cells = <1>; 656 #address-cells = <1>;
649 #size-cells = <0>; 657 #size-cells = <0>;
650 compatible = "renesas, 658 compatible = "renesas,i2c-r8a7796",
651 "renesas, 659 "renesas,rcar-gen3-i2c";
652 reg = <0 0xe6500000 0 660 reg = <0 0xe6500000 0 0x40>;
653 interrupts = <GIC_SPI 661 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
654 clocks = <&cpg CPG_MOD 662 clocks = <&cpg CPG_MOD 931>;
655 power-domains = <&sysc 663 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
656 resets = <&cpg 931>; 664 resets = <&cpg 931>;
657 dmas = <&dmac1 0x91>, 665 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
658 <&dmac2 0x91>, 666 <&dmac2 0x91>, <&dmac2 0x90>;
659 dma-names = "tx", "rx" 667 dma-names = "tx", "rx", "tx", "rx";
660 i2c-scl-internal-delay 668 i2c-scl-internal-delay-ns = <110>;
661 status = "disabled"; 669 status = "disabled";
662 }; 670 };
663 671
664 i2c1: i2c@e6508000 { 672 i2c1: i2c@e6508000 {
665 #address-cells = <1>; 673 #address-cells = <1>;
666 #size-cells = <0>; 674 #size-cells = <0>;
667 compatible = "renesas, 675 compatible = "renesas,i2c-r8a7796",
668 "renesas, 676 "renesas,rcar-gen3-i2c";
669 reg = <0 0xe6508000 0 677 reg = <0 0xe6508000 0 0x40>;
670 interrupts = <GIC_SPI 678 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
671 clocks = <&cpg CPG_MOD 679 clocks = <&cpg CPG_MOD 930>;
672 power-domains = <&sysc 680 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
673 resets = <&cpg 930>; 681 resets = <&cpg 930>;
674 dmas = <&dmac1 0x93>, 682 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
675 <&dmac2 0x93>, 683 <&dmac2 0x93>, <&dmac2 0x92>;
676 dma-names = "tx", "rx" 684 dma-names = "tx", "rx", "tx", "rx";
677 i2c-scl-internal-delay 685 i2c-scl-internal-delay-ns = <6>;
678 status = "disabled"; 686 status = "disabled";
679 }; 687 };
680 688
681 i2c2: i2c@e6510000 { 689 i2c2: i2c@e6510000 {
682 #address-cells = <1>; 690 #address-cells = <1>;
683 #size-cells = <0>; 691 #size-cells = <0>;
684 compatible = "renesas, 692 compatible = "renesas,i2c-r8a7796",
685 "renesas, 693 "renesas,rcar-gen3-i2c";
686 reg = <0 0xe6510000 0 694 reg = <0 0xe6510000 0 0x40>;
687 interrupts = <GIC_SPI 695 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
688 clocks = <&cpg CPG_MOD 696 clocks = <&cpg CPG_MOD 929>;
689 power-domains = <&sysc 697 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
690 resets = <&cpg 929>; 698 resets = <&cpg 929>;
691 dmas = <&dmac1 0x95>, 699 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
692 <&dmac2 0x95>, 700 <&dmac2 0x95>, <&dmac2 0x94>;
693 dma-names = "tx", "rx" 701 dma-names = "tx", "rx", "tx", "rx";
694 i2c-scl-internal-delay 702 i2c-scl-internal-delay-ns = <6>;
695 status = "disabled"; 703 status = "disabled";
696 }; 704 };
697 705
698 i2c3: i2c@e66d0000 { 706 i2c3: i2c@e66d0000 {
699 #address-cells = <1>; 707 #address-cells = <1>;
700 #size-cells = <0>; 708 #size-cells = <0>;
701 compatible = "renesas, 709 compatible = "renesas,i2c-r8a7796",
702 "renesas, 710 "renesas,rcar-gen3-i2c";
703 reg = <0 0xe66d0000 0 711 reg = <0 0xe66d0000 0 0x40>;
704 interrupts = <GIC_SPI 712 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
705 clocks = <&cpg CPG_MOD 713 clocks = <&cpg CPG_MOD 928>;
706 power-domains = <&sysc 714 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
707 resets = <&cpg 928>; 715 resets = <&cpg 928>;
708 dmas = <&dmac0 0x97>, 716 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
709 dma-names = "tx", "rx" 717 dma-names = "tx", "rx";
710 i2c-scl-internal-delay 718 i2c-scl-internal-delay-ns = <110>;
711 status = "disabled"; 719 status = "disabled";
712 }; 720 };
713 721
714 i2c4: i2c@e66d8000 { 722 i2c4: i2c@e66d8000 {
715 #address-cells = <1>; 723 #address-cells = <1>;
716 #size-cells = <0>; 724 #size-cells = <0>;
717 compatible = "renesas, 725 compatible = "renesas,i2c-r8a7796",
718 "renesas, 726 "renesas,rcar-gen3-i2c";
719 reg = <0 0xe66d8000 0 727 reg = <0 0xe66d8000 0 0x40>;
720 interrupts = <GIC_SPI 728 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
721 clocks = <&cpg CPG_MOD 729 clocks = <&cpg CPG_MOD 927>;
722 power-domains = <&sysc 730 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
723 resets = <&cpg 927>; 731 resets = <&cpg 927>;
724 dmas = <&dmac0 0x99>, 732 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
725 dma-names = "tx", "rx" 733 dma-names = "tx", "rx";
726 i2c-scl-internal-delay 734 i2c-scl-internal-delay-ns = <110>;
727 status = "disabled"; 735 status = "disabled";
728 }; 736 };
729 737
730 i2c5: i2c@e66e0000 { 738 i2c5: i2c@e66e0000 {
731 #address-cells = <1>; 739 #address-cells = <1>;
732 #size-cells = <0>; 740 #size-cells = <0>;
733 compatible = "renesas, 741 compatible = "renesas,i2c-r8a7796",
734 "renesas, 742 "renesas,rcar-gen3-i2c";
735 reg = <0 0xe66e0000 0 743 reg = <0 0xe66e0000 0 0x40>;
736 interrupts = <GIC_SPI 744 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
737 clocks = <&cpg CPG_MOD 745 clocks = <&cpg CPG_MOD 919>;
738 power-domains = <&sysc 746 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
739 resets = <&cpg 919>; 747 resets = <&cpg 919>;
740 dmas = <&dmac0 0x9b>, 748 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
741 dma-names = "tx", "rx" 749 dma-names = "tx", "rx";
742 i2c-scl-internal-delay 750 i2c-scl-internal-delay-ns = <110>;
743 status = "disabled"; 751 status = "disabled";
744 }; 752 };
745 753
746 i2c6: i2c@e66e8000 { 754 i2c6: i2c@e66e8000 {
747 #address-cells = <1>; 755 #address-cells = <1>;
748 #size-cells = <0>; 756 #size-cells = <0>;
749 compatible = "renesas, 757 compatible = "renesas,i2c-r8a7796",
750 "renesas, 758 "renesas,rcar-gen3-i2c";
751 reg = <0 0xe66e8000 0 759 reg = <0 0xe66e8000 0 0x40>;
752 interrupts = <GIC_SPI 760 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
753 clocks = <&cpg CPG_MOD 761 clocks = <&cpg CPG_MOD 918>;
754 power-domains = <&sysc 762 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
755 resets = <&cpg 918>; 763 resets = <&cpg 918>;
756 dmas = <&dmac0 0x9d>, 764 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
757 dma-names = "tx", "rx" 765 dma-names = "tx", "rx";
758 i2c-scl-internal-delay 766 i2c-scl-internal-delay-ns = <6>;
759 status = "disabled"; 767 status = "disabled";
760 }; 768 };
761 769
762 i2c_dvfs: i2c@e60b0000 { 770 i2c_dvfs: i2c@e60b0000 {
763 #address-cells = <1>; 771 #address-cells = <1>;
764 #size-cells = <0>; 772 #size-cells = <0>;
765 compatible = "renesas, 773 compatible = "renesas,iic-r8a7796",
766 "renesas, 774 "renesas,rcar-gen3-iic",
767 "renesas, 775 "renesas,rmobile-iic";
768 reg = <0 0xe60b0000 0 776 reg = <0 0xe60b0000 0 0x425>;
769 interrupts = <GIC_SPI 777 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
770 clocks = <&cpg CPG_MOD 778 clocks = <&cpg CPG_MOD 926>;
771 power-domains = <&sysc 779 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
772 resets = <&cpg 926>; 780 resets = <&cpg 926>;
773 dmas = <&dmac0 0x11>, 781 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
774 dma-names = "tx", "rx" 782 dma-names = "tx", "rx";
775 status = "disabled"; 783 status = "disabled";
776 }; 784 };
777 785
778 hscif0: serial@e6540000 { 786 hscif0: serial@e6540000 {
779 compatible = "renesas, 787 compatible = "renesas,hscif-r8a7796",
780 "renesas, 788 "renesas,rcar-gen3-hscif",
781 "renesas, 789 "renesas,hscif";
782 reg = <0 0xe6540000 0 790 reg = <0 0xe6540000 0 0x60>;
783 interrupts = <GIC_SPI 791 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
784 clocks = <&cpg CPG_MOD 792 clocks = <&cpg CPG_MOD 520>,
785 <&cpg CPG_COR 793 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
786 <&scif_clk>; 794 <&scif_clk>;
787 clock-names = "fck", " 795 clock-names = "fck", "brg_int", "scif_clk";
788 dmas = <&dmac1 0x31>, 796 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
789 <&dmac2 0x31>, 797 <&dmac2 0x31>, <&dmac2 0x30>;
790 dma-names = "tx", "rx" 798 dma-names = "tx", "rx", "tx", "rx";
791 power-domains = <&sysc 799 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
792 resets = <&cpg 520>; 800 resets = <&cpg 520>;
793 status = "disabled"; 801 status = "disabled";
794 }; 802 };
795 803
796 hscif1: serial@e6550000 { 804 hscif1: serial@e6550000 {
797 compatible = "renesas, 805 compatible = "renesas,hscif-r8a7796",
798 "renesas, 806 "renesas,rcar-gen3-hscif",
799 "renesas, 807 "renesas,hscif";
800 reg = <0 0xe6550000 0 808 reg = <0 0xe6550000 0 0x60>;
801 interrupts = <GIC_SPI 809 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
802 clocks = <&cpg CPG_MOD 810 clocks = <&cpg CPG_MOD 519>,
803 <&cpg CPG_COR 811 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
804 <&scif_clk>; 812 <&scif_clk>;
805 clock-names = "fck", " 813 clock-names = "fck", "brg_int", "scif_clk";
806 dmas = <&dmac1 0x33>, 814 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
807 <&dmac2 0x33>, 815 <&dmac2 0x33>, <&dmac2 0x32>;
808 dma-names = "tx", "rx" 816 dma-names = "tx", "rx", "tx", "rx";
809 power-domains = <&sysc 817 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
810 resets = <&cpg 519>; 818 resets = <&cpg 519>;
811 status = "disabled"; 819 status = "disabled";
812 }; 820 };
813 821
814 hscif2: serial@e6560000 { 822 hscif2: serial@e6560000 {
815 compatible = "renesas, 823 compatible = "renesas,hscif-r8a7796",
816 "renesas, 824 "renesas,rcar-gen3-hscif",
817 "renesas, 825 "renesas,hscif";
818 reg = <0 0xe6560000 0 826 reg = <0 0xe6560000 0 0x60>;
819 interrupts = <GIC_SPI 827 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
820 clocks = <&cpg CPG_MOD 828 clocks = <&cpg CPG_MOD 518>,
821 <&cpg CPG_COR 829 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
822 <&scif_clk>; 830 <&scif_clk>;
823 clock-names = "fck", " 831 clock-names = "fck", "brg_int", "scif_clk";
824 dmas = <&dmac1 0x35>, 832 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
825 <&dmac2 0x35>, 833 <&dmac2 0x35>, <&dmac2 0x34>;
826 dma-names = "tx", "rx" 834 dma-names = "tx", "rx", "tx", "rx";
827 power-domains = <&sysc 835 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
828 resets = <&cpg 518>; 836 resets = <&cpg 518>;
829 status = "disabled"; 837 status = "disabled";
830 }; 838 };
831 839
832 hscif3: serial@e66a0000 { 840 hscif3: serial@e66a0000 {
833 compatible = "renesas, 841 compatible = "renesas,hscif-r8a7796",
834 "renesas, 842 "renesas,rcar-gen3-hscif",
835 "renesas, 843 "renesas,hscif";
836 reg = <0 0xe66a0000 0 844 reg = <0 0xe66a0000 0 0x60>;
837 interrupts = <GIC_SPI 845 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
838 clocks = <&cpg CPG_MOD 846 clocks = <&cpg CPG_MOD 517>,
839 <&cpg CPG_COR 847 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
840 <&scif_clk>; 848 <&scif_clk>;
841 clock-names = "fck", " 849 clock-names = "fck", "brg_int", "scif_clk";
842 dmas = <&dmac0 0x37>, 850 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
843 dma-names = "tx", "rx" 851 dma-names = "tx", "rx";
844 power-domains = <&sysc 852 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
845 resets = <&cpg 517>; 853 resets = <&cpg 517>;
846 status = "disabled"; 854 status = "disabled";
847 }; 855 };
848 856
849 hscif4: serial@e66b0000 { 857 hscif4: serial@e66b0000 {
850 compatible = "renesas, 858 compatible = "renesas,hscif-r8a7796",
851 "renesas, 859 "renesas,rcar-gen3-hscif",
852 "renesas, 860 "renesas,hscif";
853 reg = <0 0xe66b0000 0 861 reg = <0 0xe66b0000 0 0x60>;
854 interrupts = <GIC_SPI 862 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
855 clocks = <&cpg CPG_MOD 863 clocks = <&cpg CPG_MOD 516>,
856 <&cpg CPG_COR 864 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
857 <&scif_clk>; 865 <&scif_clk>;
858 clock-names = "fck", " 866 clock-names = "fck", "brg_int", "scif_clk";
859 dmas = <&dmac0 0x39>, 867 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
860 dma-names = "tx", "rx" 868 dma-names = "tx", "rx";
861 power-domains = <&sysc 869 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
862 resets = <&cpg 516>; 870 resets = <&cpg 516>;
863 status = "disabled"; 871 status = "disabled";
864 }; 872 };
865 873
866 hsusb: usb@e6590000 { 874 hsusb: usb@e6590000 {
867 compatible = "renesas, 875 compatible = "renesas,usbhs-r8a7796",
868 "renesas, 876 "renesas,rcar-gen3-usbhs";
869 reg = <0 0xe6590000 0 877 reg = <0 0xe6590000 0 0x200>;
870 interrupts = <GIC_SPI 878 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
871 clocks = <&cpg CPG_MOD 879 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
872 dmas = <&usb_dmac0 0>, 880 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
873 <&usb_dmac1 0>, 881 <&usb_dmac1 0>, <&usb_dmac1 1>;
874 dma-names = "ch0", "ch 882 dma-names = "ch0", "ch1", "ch2", "ch3";
875 renesas,buswait = <11> 883 renesas,buswait = <11>;
876 phys = <&usb2_phy0 3>; 884 phys = <&usb2_phy0 3>;
877 phy-names = "usb"; 885 phy-names = "usb";
878 power-domains = <&sysc 886 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
879 resets = <&cpg 704>, < 887 resets = <&cpg 704>, <&cpg 703>;
880 status = "disabled"; 888 status = "disabled";
881 }; 889 };
882 890
883 usb_dmac0: dma-controller@e65a 891 usb_dmac0: dma-controller@e65a0000 {
884 compatible = "renesas, 892 compatible = "renesas,r8a7796-usb-dmac",
885 "renesas, 893 "renesas,usb-dmac";
886 reg = <0 0xe65a0000 0 894 reg = <0 0xe65a0000 0 0x100>;
887 interrupts = <GIC_SPI 895 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
888 <GIC_SPI 896 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
889 interrupt-names = "ch0 897 interrupt-names = "ch0", "ch1";
890 clocks = <&cpg CPG_MOD 898 clocks = <&cpg CPG_MOD 330>;
891 power-domains = <&sysc 899 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
892 resets = <&cpg 330>; 900 resets = <&cpg 330>;
893 #dma-cells = <1>; 901 #dma-cells = <1>;
894 dma-channels = <2>; 902 dma-channels = <2>;
895 }; 903 };
896 904
897 usb_dmac1: dma-controller@e65b 905 usb_dmac1: dma-controller@e65b0000 {
898 compatible = "renesas, 906 compatible = "renesas,r8a7796-usb-dmac",
899 "renesas, 907 "renesas,usb-dmac";
900 reg = <0 0xe65b0000 0 908 reg = <0 0xe65b0000 0 0x100>;
901 interrupts = <GIC_SPI 909 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
902 <GIC_SPI 910 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
903 interrupt-names = "ch0 911 interrupt-names = "ch0", "ch1";
904 clocks = <&cpg CPG_MOD 912 clocks = <&cpg CPG_MOD 331>;
905 power-domains = <&sysc 913 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
906 resets = <&cpg 331>; 914 resets = <&cpg 331>;
907 #dma-cells = <1>; 915 #dma-cells = <1>;
908 dma-channels = <2>; 916 dma-channels = <2>;
909 }; 917 };
910 918
911 usb3_phy0: usb-phy@e65ee000 { 919 usb3_phy0: usb-phy@e65ee000 {
912 compatible = "renesas, 920 compatible = "renesas,r8a7796-usb3-phy",
913 "renesas, 921 "renesas,rcar-gen3-usb3-phy";
914 reg = <0 0xe65ee000 0 922 reg = <0 0xe65ee000 0 0x90>;
915 clocks = <&cpg CPG_MOD 923 clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>,
916 <&usb_extal_c 924 <&usb_extal_clk>;
917 clock-names = "usb3-if 925 clock-names = "usb3-if", "usb3s_clk", "usb_extal";
918 power-domains = <&sysc 926 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
919 resets = <&cpg 328>; 927 resets = <&cpg 328>;
920 #phy-cells = <0>; 928 #phy-cells = <0>;
921 status = "disabled"; 929 status = "disabled";
922 }; 930 };
923 931
924 arm_cc630p: crypto@e6601000 { 932 arm_cc630p: crypto@e6601000 {
925 compatible = "arm,cryp 933 compatible = "arm,cryptocell-630p-ree";
926 interrupts = <GIC_SPI 934 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
927 reg = <0x0 0xe6601000 935 reg = <0x0 0xe6601000 0 0x1000>;
928 clocks = <&cpg CPG_MOD 936 clocks = <&cpg CPG_MOD 229>;
929 resets = <&cpg 229>; 937 resets = <&cpg 229>;
930 power-domains = <&sysc 938 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
931 }; 939 };
932 940
933 dmac0: dma-controller@e6700000 941 dmac0: dma-controller@e6700000 {
934 compatible = "renesas, 942 compatible = "renesas,dmac-r8a7796",
935 "renesas, 943 "renesas,rcar-dmac";
936 reg = <0 0xe6700000 0 944 reg = <0 0xe6700000 0 0x10000>;
937 interrupts = <GIC_SPI 945 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
938 <GIC_SPI 946 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
939 <GIC_SPI 947 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
940 <GIC_SPI 948 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
941 <GIC_SPI 949 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
942 <GIC_SPI 950 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
943 <GIC_SPI 951 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
944 <GIC_SPI 952 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
945 <GIC_SPI 953 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
946 <GIC_SPI 954 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
947 <GIC_SPI 955 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
948 <GIC_SPI 956 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
949 <GIC_SPI 957 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
950 <GIC_SPI 958 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
951 <GIC_SPI 959 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
952 <GIC_SPI 960 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
953 <GIC_SPI 961 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
954 interrupt-names = "err 962 interrupt-names = "error",
955 "ch0", 963 "ch0", "ch1", "ch2", "ch3",
956 "ch4", 964 "ch4", "ch5", "ch6", "ch7",
957 "ch8", 965 "ch8", "ch9", "ch10", "ch11",
958 "ch12" 966 "ch12", "ch13", "ch14", "ch15";
959 clocks = <&cpg CPG_MOD 967 clocks = <&cpg CPG_MOD 219>;
960 clock-names = "fck"; 968 clock-names = "fck";
961 power-domains = <&sysc 969 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
962 resets = <&cpg 219>; 970 resets = <&cpg 219>;
963 #dma-cells = <1>; 971 #dma-cells = <1>;
964 dma-channels = <16>; 972 dma-channels = <16>;
965 iommus = <&ipmmu_ds0 0 973 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
966 <&ipmmu_ds0 2>, 974 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
967 <&ipmmu_ds0 4>, 975 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
968 <&ipmmu_ds0 6>, 976 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
969 <&ipmmu_ds0 8>, 977 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
970 <&ipmmu_ds0 10> 978 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
971 <&ipmmu_ds0 12> 979 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
972 <&ipmmu_ds0 14> 980 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
973 }; 981 };
974 982
975 dmac1: dma-controller@e7300000 983 dmac1: dma-controller@e7300000 {
976 compatible = "renesas, 984 compatible = "renesas,dmac-r8a7796",
977 "renesas, 985 "renesas,rcar-dmac";
978 reg = <0 0xe7300000 0 986 reg = <0 0xe7300000 0 0x10000>;
979 interrupts = <GIC_SPI 987 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
980 <GIC_SPI 988 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
981 <GIC_SPI 989 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
982 <GIC_SPI 990 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
983 <GIC_SPI 991 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
984 <GIC_SPI 992 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
985 <GIC_SPI 993 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
986 <GIC_SPI 994 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
987 <GIC_SPI 995 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
988 <GIC_SPI 996 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
989 <GIC_SPI 997 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
990 <GIC_SPI 998 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
991 <GIC_SPI 999 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
992 <GIC_SPI 1000 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
993 <GIC_SPI 1001 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
994 <GIC_SPI 1002 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
995 <GIC_SPI 1003 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
996 interrupt-names = "err 1004 interrupt-names = "error",
997 "ch0", 1005 "ch0", "ch1", "ch2", "ch3",
998 "ch4", 1006 "ch4", "ch5", "ch6", "ch7",
999 "ch8", 1007 "ch8", "ch9", "ch10", "ch11",
1000 "ch12 1008 "ch12", "ch13", "ch14", "ch15";
1001 clocks = <&cpg CPG_MO 1009 clocks = <&cpg CPG_MOD 218>;
1002 clock-names = "fck"; 1010 clock-names = "fck";
1003 power-domains = <&sys 1011 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1004 resets = <&cpg 218>; 1012 resets = <&cpg 218>;
1005 #dma-cells = <1>; 1013 #dma-cells = <1>;
1006 dma-channels = <16>; 1014 dma-channels = <16>;
1007 iommus = <&ipmmu_ds1 1015 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
1008 <&ipmmu_ds1 2> 1016 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
1009 <&ipmmu_ds1 4> 1017 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
1010 <&ipmmu_ds1 6> 1018 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
1011 <&ipmmu_ds1 8> 1019 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
1012 <&ipmmu_ds1 10 1020 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
1013 <&ipmmu_ds1 12 1021 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
1014 <&ipmmu_ds1 14 1022 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
1015 }; 1023 };
1016 1024
1017 dmac2: dma-controller@e731000 1025 dmac2: dma-controller@e7310000 {
1018 compatible = "renesas 1026 compatible = "renesas,dmac-r8a7796",
1019 "renesas 1027 "renesas,rcar-dmac";
1020 reg = <0 0xe7310000 0 1028 reg = <0 0xe7310000 0 0x10000>;
1021 interrupts = <GIC_SPI 1029 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
1022 <GIC_SPI 1030 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
1023 <GIC_SPI 1031 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
1024 <GIC_SPI 1032 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
1025 <GIC_SPI 1033 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
1026 <GIC_SPI 1034 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
1027 <GIC_SPI 1035 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
1028 <GIC_SPI 1036 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
1029 <GIC_SPI 1037 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
1030 <GIC_SPI 1038 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
1031 <GIC_SPI 1039 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
1032 <GIC_SPI 1040 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
1033 <GIC_SPI 1041 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
1034 <GIC_SPI 1042 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
1035 <GIC_SPI 1043 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
1036 <GIC_SPI 1044 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
1037 <GIC_SPI 1045 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
1038 interrupt-names = "er 1046 interrupt-names = "error",
1039 "ch0" 1047 "ch0", "ch1", "ch2", "ch3",
1040 "ch4" 1048 "ch4", "ch5", "ch6", "ch7",
1041 "ch8" 1049 "ch8", "ch9", "ch10", "ch11",
1042 "ch12 1050 "ch12", "ch13", "ch14", "ch15";
1043 clocks = <&cpg CPG_MO 1051 clocks = <&cpg CPG_MOD 217>;
1044 clock-names = "fck"; 1052 clock-names = "fck";
1045 power-domains = <&sys 1053 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1046 resets = <&cpg 217>; 1054 resets = <&cpg 217>;
1047 #dma-cells = <1>; 1055 #dma-cells = <1>;
1048 dma-channels = <16>; 1056 dma-channels = <16>;
1049 iommus = <&ipmmu_ds1 1057 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
1050 <&ipmmu_ds1 18 1058 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
1051 <&ipmmu_ds1 20 1059 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
1052 <&ipmmu_ds1 22 1060 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
1053 <&ipmmu_ds1 24 1061 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
1054 <&ipmmu_ds1 26 1062 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
1055 <&ipmmu_ds1 28 1063 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
1056 <&ipmmu_ds1 30 1064 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
1057 }; 1065 };
1058 1066
1059 ipmmu_ds0: iommu@e6740000 { 1067 ipmmu_ds0: iommu@e6740000 {
1060 compatible = "renesas 1068 compatible = "renesas,ipmmu-r8a7796";
1061 reg = <0 0xe6740000 0 1069 reg = <0 0xe6740000 0 0x1000>;
1062 renesas,ipmmu-main = 1070 renesas,ipmmu-main = <&ipmmu_mm 0>;
1063 power-domains = <&sys 1071 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1064 #iommu-cells = <1>; 1072 #iommu-cells = <1>;
1065 }; 1073 };
1066 1074
1067 ipmmu_ds1: iommu@e7740000 { 1075 ipmmu_ds1: iommu@e7740000 {
1068 compatible = "renesas 1076 compatible = "renesas,ipmmu-r8a7796";
1069 reg = <0 0xe7740000 0 1077 reg = <0 0xe7740000 0 0x1000>;
1070 renesas,ipmmu-main = 1078 renesas,ipmmu-main = <&ipmmu_mm 1>;
1071 power-domains = <&sys 1079 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1072 #iommu-cells = <1>; 1080 #iommu-cells = <1>;
1073 }; 1081 };
1074 1082
1075 ipmmu_hc: iommu@e6570000 { 1083 ipmmu_hc: iommu@e6570000 {
1076 compatible = "renesas 1084 compatible = "renesas,ipmmu-r8a7796";
1077 reg = <0 0xe6570000 0 1085 reg = <0 0xe6570000 0 0x1000>;
1078 renesas,ipmmu-main = 1086 renesas,ipmmu-main = <&ipmmu_mm 2>;
1079 power-domains = <&sys 1087 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1080 #iommu-cells = <1>; 1088 #iommu-cells = <1>;
1081 }; 1089 };
1082 1090
1083 ipmmu_ir: iommu@ff8b0000 { 1091 ipmmu_ir: iommu@ff8b0000 {
1084 compatible = "renesas 1092 compatible = "renesas,ipmmu-r8a7796";
1085 reg = <0 0xff8b0000 0 1093 reg = <0 0xff8b0000 0 0x1000>;
1086 renesas,ipmmu-main = 1094 renesas,ipmmu-main = <&ipmmu_mm 3>;
1087 power-domains = <&sys 1095 power-domains = <&sysc R8A7796_PD_A3IR>;
1088 #iommu-cells = <1>; 1096 #iommu-cells = <1>;
1089 }; 1097 };
1090 1098
1091 ipmmu_mm: iommu@e67b0000 { 1099 ipmmu_mm: iommu@e67b0000 {
1092 compatible = "renesas 1100 compatible = "renesas,ipmmu-r8a7796";
1093 reg = <0 0xe67b0000 0 1101 reg = <0 0xe67b0000 0 0x1000>;
1094 interrupts = <GIC_SPI 1102 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
1095 <GIC_SPI 1103 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
1096 power-domains = <&sys 1104 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1097 #iommu-cells = <1>; 1105 #iommu-cells = <1>;
1098 }; 1106 };
1099 1107
1100 ipmmu_mp: iommu@ec670000 { 1108 ipmmu_mp: iommu@ec670000 {
1101 compatible = "renesas 1109 compatible = "renesas,ipmmu-r8a7796";
1102 reg = <0 0xec670000 0 1110 reg = <0 0xec670000 0 0x1000>;
1103 renesas,ipmmu-main = 1111 renesas,ipmmu-main = <&ipmmu_mm 4>;
1104 power-domains = <&sys 1112 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1105 #iommu-cells = <1>; 1113 #iommu-cells = <1>;
1106 }; 1114 };
1107 1115
1108 ipmmu_pv0: iommu@fd800000 { 1116 ipmmu_pv0: iommu@fd800000 {
1109 compatible = "renesas 1117 compatible = "renesas,ipmmu-r8a7796";
1110 reg = <0 0xfd800000 0 1118 reg = <0 0xfd800000 0 0x1000>;
1111 renesas,ipmmu-main = 1119 renesas,ipmmu-main = <&ipmmu_mm 5>;
1112 power-domains = <&sys 1120 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1113 #iommu-cells = <1>; 1121 #iommu-cells = <1>;
1114 }; 1122 };
1115 1123
1116 ipmmu_pv1: iommu@fd950000 { 1124 ipmmu_pv1: iommu@fd950000 {
1117 compatible = "renesas 1125 compatible = "renesas,ipmmu-r8a7796";
1118 reg = <0 0xfd950000 0 1126 reg = <0 0xfd950000 0 0x1000>;
1119 renesas,ipmmu-main = 1127 renesas,ipmmu-main = <&ipmmu_mm 6>;
1120 power-domains = <&sys 1128 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1121 #iommu-cells = <1>; 1129 #iommu-cells = <1>;
1122 }; 1130 };
1123 1131
1124 ipmmu_rt: iommu@ffc80000 { 1132 ipmmu_rt: iommu@ffc80000 {
1125 compatible = "renesas 1133 compatible = "renesas,ipmmu-r8a7796";
1126 reg = <0 0xffc80000 0 1134 reg = <0 0xffc80000 0 0x1000>;
1127 renesas,ipmmu-main = 1135 renesas,ipmmu-main = <&ipmmu_mm 7>;
1128 power-domains = <&sys 1136 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1129 #iommu-cells = <1>; 1137 #iommu-cells = <1>;
1130 }; 1138 };
1131 1139
1132 ipmmu_vc0: iommu@fe6b0000 { 1140 ipmmu_vc0: iommu@fe6b0000 {
1133 compatible = "renesas 1141 compatible = "renesas,ipmmu-r8a7796";
1134 reg = <0 0xfe6b0000 0 1142 reg = <0 0xfe6b0000 0 0x1000>;
1135 renesas,ipmmu-main = 1143 renesas,ipmmu-main = <&ipmmu_mm 8>;
1136 power-domains = <&sys 1144 power-domains = <&sysc R8A7796_PD_A3VC>;
1137 #iommu-cells = <1>; 1145 #iommu-cells = <1>;
1138 }; 1146 };
1139 1147
1140 ipmmu_vi0: iommu@febd0000 { 1148 ipmmu_vi0: iommu@febd0000 {
1141 compatible = "renesas 1149 compatible = "renesas,ipmmu-r8a7796";
1142 reg = <0 0xfebd0000 0 1150 reg = <0 0xfebd0000 0 0x1000>;
1143 renesas,ipmmu-main = 1151 renesas,ipmmu-main = <&ipmmu_mm 9>;
1144 power-domains = <&sys 1152 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1145 #iommu-cells = <1>; 1153 #iommu-cells = <1>;
1146 }; 1154 };
1147 1155
1148 avb: ethernet@e6800000 { 1156 avb: ethernet@e6800000 {
1149 compatible = "renesas 1157 compatible = "renesas,etheravb-r8a7796",
1150 "renesas 1158 "renesas,etheravb-rcar-gen3";
1151 reg = <0 0xe6800000 0 1159 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
1152 interrupts = <GIC_SPI 1160 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
1153 <GIC_SPI 1161 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1154 <GIC_SPI 1162 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
1155 <GIC_SPI 1163 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
1156 <GIC_SPI 1164 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
1157 <GIC_SPI 1165 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
1158 <GIC_SPI 1166 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
1159 <GIC_SPI 1167 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
1160 <GIC_SPI 1168 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
1161 <GIC_SPI 1169 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
1162 <GIC_SPI 1170 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
1163 <GIC_SPI 1171 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
1164 <GIC_SPI 1172 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
1165 <GIC_SPI 1173 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
1166 <GIC_SPI 1174 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
1167 <GIC_SPI 1175 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
1168 <GIC_SPI 1176 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
1169 <GIC_SPI 1177 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
1170 <GIC_SPI 1178 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
1171 <GIC_SPI 1179 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
1172 <GIC_SPI 1180 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
1173 <GIC_SPI 1181 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
1174 <GIC_SPI 1182 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
1175 <GIC_SPI 1183 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
1176 <GIC_SPI 1184 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
1177 interrupt-names = "ch 1185 interrupt-names = "ch0", "ch1", "ch2", "ch3",
1178 "ch 1186 "ch4", "ch5", "ch6", "ch7",
1179 "ch 1187 "ch8", "ch9", "ch10", "ch11",
1180 "ch 1188 "ch12", "ch13", "ch14", "ch15",
1181 "ch 1189 "ch16", "ch17", "ch18", "ch19",
1182 "ch 1190 "ch20", "ch21", "ch22", "ch23",
1183 "ch 1191 "ch24";
1184 clocks = <&cpg CPG_MO 1192 clocks = <&cpg CPG_MOD 812>;
1185 clock-names = "fck"; 1193 clock-names = "fck";
1186 power-domains = <&sys 1194 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1187 resets = <&cpg 812>; 1195 resets = <&cpg 812>;
1188 phy-mode = "rgmii"; 1196 phy-mode = "rgmii";
1189 rx-internal-delay-ps 1197 rx-internal-delay-ps = <0>;
1190 tx-internal-delay-ps 1198 tx-internal-delay-ps = <0>;
1191 iommus = <&ipmmu_ds0 1199 iommus = <&ipmmu_ds0 16>;
1192 #address-cells = <1>; 1200 #address-cells = <1>;
1193 #size-cells = <0>; 1201 #size-cells = <0>;
1194 status = "disabled"; 1202 status = "disabled";
1195 }; 1203 };
1196 1204
1197 can0: can@e6c30000 { 1205 can0: can@e6c30000 {
1198 compatible = "renesas 1206 compatible = "renesas,can-r8a7796",
1199 "renesas 1207 "renesas,rcar-gen3-can";
1200 reg = <0 0xe6c30000 0 1208 reg = <0 0xe6c30000 0 0x1000>;
1201 interrupts = <GIC_SPI 1209 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
1202 clocks = <&cpg CPG_MO 1210 clocks = <&cpg CPG_MOD 916>,
1203 <&cpg CPG_CORE 1211 <&cpg CPG_CORE R8A7796_CLK_CANFD>,
1204 <&can_clk>; 1212 <&can_clk>;
1205 clock-names = "clkp1" 1213 clock-names = "clkp1", "clkp2", "can_clk";
1206 assigned-clocks = <&c 1214 assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>;
1207 assigned-clock-rates 1215 assigned-clock-rates = <40000000>;
1208 power-domains = <&sys 1216 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1209 resets = <&cpg 916>; 1217 resets = <&cpg 916>;
1210 status = "disabled"; 1218 status = "disabled";
1211 }; 1219 };
1212 1220
1213 can1: can@e6c38000 { 1221 can1: can@e6c38000 {
1214 compatible = "renesas 1222 compatible = "renesas,can-r8a7796",
1215 "renesas 1223 "renesas,rcar-gen3-can";
1216 reg = <0 0xe6c38000 0 1224 reg = <0 0xe6c38000 0 0x1000>;
1217 interrupts = <GIC_SPI 1225 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
1218 clocks = <&cpg CPG_MO 1226 clocks = <&cpg CPG_MOD 915>,
1219 <&cpg CPG_CORE 1227 <&cpg CPG_CORE R8A7796_CLK_CANFD>,
1220 <&can_clk>; 1228 <&can_clk>;
1221 clock-names = "clkp1" 1229 clock-names = "clkp1", "clkp2", "can_clk";
1222 assigned-clocks = <&c 1230 assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>;
1223 assigned-clock-rates 1231 assigned-clock-rates = <40000000>;
1224 power-domains = <&sys 1232 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1225 resets = <&cpg 915>; 1233 resets = <&cpg 915>;
1226 status = "disabled"; 1234 status = "disabled";
1227 }; 1235 };
1228 1236
1229 canfd: can@e66c0000 { 1237 canfd: can@e66c0000 {
1230 compatible = "renesas 1238 compatible = "renesas,r8a7796-canfd",
1231 "renesas 1239 "renesas,rcar-gen3-canfd";
1232 reg = <0 0xe66c0000 0 1240 reg = <0 0xe66c0000 0 0x8000>;
1233 interrupts = <GIC_SPI 1241 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
1234 <GIC_SPI 3 1242 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1235 interrupt-names = "ch 1243 interrupt-names = "ch_int", "g_int";
1236 clocks = <&cpg CPG_MO 1244 clocks = <&cpg CPG_MOD 914>,
1237 <&cpg CPG_CORE 1245 <&cpg CPG_CORE R8A7796_CLK_CANFD>,
1238 <&can_clk>; 1246 <&can_clk>;
1239 clock-names = "fck", 1247 clock-names = "fck", "canfd", "can_clk";
1240 assigned-clocks = <&c 1248 assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>;
1241 assigned-clock-rates 1249 assigned-clock-rates = <40000000>;
1242 power-domains = <&sys 1250 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1243 resets = <&cpg 914>; 1251 resets = <&cpg 914>;
1244 status = "disabled"; 1252 status = "disabled";
1245 1253
1246 channel0 { 1254 channel0 {
1247 status = "dis 1255 status = "disabled";
1248 }; 1256 };
1249 1257
1250 channel1 { 1258 channel1 {
1251 status = "dis 1259 status = "disabled";
1252 }; 1260 };
1253 }; 1261 };
1254 1262
1255 pwm0: pwm@e6e30000 { 1263 pwm0: pwm@e6e30000 {
1256 compatible = "renesas 1264 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
1257 reg = <0 0xe6e30000 0 1265 reg = <0 0xe6e30000 0 8>;
1258 #pwm-cells = <2>; 1266 #pwm-cells = <2>;
1259 clocks = <&cpg CPG_MO 1267 clocks = <&cpg CPG_MOD 523>;
1260 resets = <&cpg 523>; 1268 resets = <&cpg 523>;
1261 power-domains = <&sys 1269 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1262 status = "disabled"; 1270 status = "disabled";
1263 }; 1271 };
1264 1272
1265 pwm1: pwm@e6e31000 { 1273 pwm1: pwm@e6e31000 {
1266 compatible = "renesas 1274 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
1267 reg = <0 0xe6e31000 0 1275 reg = <0 0xe6e31000 0 8>;
1268 #pwm-cells = <2>; 1276 #pwm-cells = <2>;
1269 clocks = <&cpg CPG_MO 1277 clocks = <&cpg CPG_MOD 523>;
1270 resets = <&cpg 523>; 1278 resets = <&cpg 523>;
1271 power-domains = <&sys 1279 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1272 status = "disabled"; 1280 status = "disabled";
1273 }; 1281 };
1274 1282
1275 pwm2: pwm@e6e32000 { 1283 pwm2: pwm@e6e32000 {
1276 compatible = "renesas 1284 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
1277 reg = <0 0xe6e32000 0 1285 reg = <0 0xe6e32000 0 8>;
1278 #pwm-cells = <2>; 1286 #pwm-cells = <2>;
1279 clocks = <&cpg CPG_MO 1287 clocks = <&cpg CPG_MOD 523>;
1280 resets = <&cpg 523>; 1288 resets = <&cpg 523>;
1281 power-domains = <&sys 1289 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1282 status = "disabled"; 1290 status = "disabled";
1283 }; 1291 };
1284 1292
1285 pwm3: pwm@e6e33000 { 1293 pwm3: pwm@e6e33000 {
1286 compatible = "renesas 1294 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
1287 reg = <0 0xe6e33000 0 1295 reg = <0 0xe6e33000 0 8>;
1288 #pwm-cells = <2>; 1296 #pwm-cells = <2>;
1289 clocks = <&cpg CPG_MO 1297 clocks = <&cpg CPG_MOD 523>;
1290 resets = <&cpg 523>; 1298 resets = <&cpg 523>;
1291 power-domains = <&sys 1299 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1292 status = "disabled"; 1300 status = "disabled";
1293 }; 1301 };
1294 1302
1295 pwm4: pwm@e6e34000 { 1303 pwm4: pwm@e6e34000 {
1296 compatible = "renesas 1304 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
1297 reg = <0 0xe6e34000 0 1305 reg = <0 0xe6e34000 0 8>;
1298 #pwm-cells = <2>; 1306 #pwm-cells = <2>;
1299 clocks = <&cpg CPG_MO 1307 clocks = <&cpg CPG_MOD 523>;
1300 resets = <&cpg 523>; 1308 resets = <&cpg 523>;
1301 power-domains = <&sys 1309 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1302 status = "disabled"; 1310 status = "disabled";
1303 }; 1311 };
1304 1312
1305 pwm5: pwm@e6e35000 { 1313 pwm5: pwm@e6e35000 {
1306 compatible = "renesas 1314 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
1307 reg = <0 0xe6e35000 0 1315 reg = <0 0xe6e35000 0 8>;
1308 #pwm-cells = <2>; 1316 #pwm-cells = <2>;
1309 clocks = <&cpg CPG_MO 1317 clocks = <&cpg CPG_MOD 523>;
1310 resets = <&cpg 523>; 1318 resets = <&cpg 523>;
1311 power-domains = <&sys 1319 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1312 status = "disabled"; 1320 status = "disabled";
1313 }; 1321 };
1314 1322
1315 pwm6: pwm@e6e36000 { 1323 pwm6: pwm@e6e36000 {
1316 compatible = "renesas 1324 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
1317 reg = <0 0xe6e36000 0 1325 reg = <0 0xe6e36000 0 8>;
1318 #pwm-cells = <2>; 1326 #pwm-cells = <2>;
1319 clocks = <&cpg CPG_MO 1327 clocks = <&cpg CPG_MOD 523>;
1320 resets = <&cpg 523>; 1328 resets = <&cpg 523>;
1321 power-domains = <&sys 1329 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1322 status = "disabled"; 1330 status = "disabled";
1323 }; 1331 };
1324 1332
1325 scif0: serial@e6e60000 { 1333 scif0: serial@e6e60000 {
1326 compatible = "renesas 1334 compatible = "renesas,scif-r8a7796",
1327 "renesas 1335 "renesas,rcar-gen3-scif", "renesas,scif";
1328 reg = <0 0xe6e60000 0 1336 reg = <0 0xe6e60000 0 64>;
1329 interrupts = <GIC_SPI 1337 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
1330 clocks = <&cpg CPG_MO 1338 clocks = <&cpg CPG_MOD 207>,
1331 <&cpg CPG_CO 1339 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
1332 <&scif_clk>; 1340 <&scif_clk>;
1333 clock-names = "fck", 1341 clock-names = "fck", "brg_int", "scif_clk";
1334 dmas = <&dmac1 0x51>, 1342 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1335 <&dmac2 0x51>, 1343 <&dmac2 0x51>, <&dmac2 0x50>;
1336 dma-names = "tx", "rx 1344 dma-names = "tx", "rx", "tx", "rx";
1337 power-domains = <&sys 1345 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1338 resets = <&cpg 207>; 1346 resets = <&cpg 207>;
1339 status = "disabled"; 1347 status = "disabled";
1340 }; 1348 };
1341 1349
1342 scif1: serial@e6e68000 { 1350 scif1: serial@e6e68000 {
1343 compatible = "renesas 1351 compatible = "renesas,scif-r8a7796",
1344 "renesas 1352 "renesas,rcar-gen3-scif", "renesas,scif";
1345 reg = <0 0xe6e68000 0 1353 reg = <0 0xe6e68000 0 64>;
1346 interrupts = <GIC_SPI 1354 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
1347 clocks = <&cpg CPG_MO 1355 clocks = <&cpg CPG_MOD 206>,
1348 <&cpg CPG_CO 1356 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
1349 <&scif_clk>; 1357 <&scif_clk>;
1350 clock-names = "fck", 1358 clock-names = "fck", "brg_int", "scif_clk";
1351 dmas = <&dmac1 0x53>, 1359 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1352 <&dmac2 0x53>, 1360 <&dmac2 0x53>, <&dmac2 0x52>;
1353 dma-names = "tx", "rx 1361 dma-names = "tx", "rx", "tx", "rx";
1354 power-domains = <&sys 1362 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1355 resets = <&cpg 206>; 1363 resets = <&cpg 206>;
1356 status = "disabled"; 1364 status = "disabled";
1357 }; 1365 };
1358 1366
1359 scif2: serial@e6e88000 { 1367 scif2: serial@e6e88000 {
1360 compatible = "renesas 1368 compatible = "renesas,scif-r8a7796",
1361 "renesas 1369 "renesas,rcar-gen3-scif", "renesas,scif";
1362 reg = <0 0xe6e88000 0 1370 reg = <0 0xe6e88000 0 64>;
1363 interrupts = <GIC_SPI 1371 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
1364 clocks = <&cpg CPG_MO 1372 clocks = <&cpg CPG_MOD 310>,
1365 <&cpg CPG_CO 1373 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
1366 <&scif_clk>; 1374 <&scif_clk>;
1367 clock-names = "fck", 1375 clock-names = "fck", "brg_int", "scif_clk";
1368 dmas = <&dmac1 0x13>, 1376 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1369 <&dmac2 0x13>, 1377 <&dmac2 0x13>, <&dmac2 0x12>;
1370 dma-names = "tx", "rx 1378 dma-names = "tx", "rx", "tx", "rx";
1371 power-domains = <&sys 1379 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1372 resets = <&cpg 310>; 1380 resets = <&cpg 310>;
1373 status = "disabled"; 1381 status = "disabled";
1374 }; 1382 };
1375 1383
1376 scif3: serial@e6c50000 { 1384 scif3: serial@e6c50000 {
1377 compatible = "renesas 1385 compatible = "renesas,scif-r8a7796",
1378 "renesas 1386 "renesas,rcar-gen3-scif", "renesas,scif";
1379 reg = <0 0xe6c50000 0 1387 reg = <0 0xe6c50000 0 64>;
1380 interrupts = <GIC_SPI 1388 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1381 clocks = <&cpg CPG_MO 1389 clocks = <&cpg CPG_MOD 204>,
1382 <&cpg CPG_CO 1390 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
1383 <&scif_clk>; 1391 <&scif_clk>;
1384 clock-names = "fck", 1392 clock-names = "fck", "brg_int", "scif_clk";
1385 dmas = <&dmac0 0x57>, 1393 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1386 dma-names = "tx", "rx 1394 dma-names = "tx", "rx";
1387 power-domains = <&sys 1395 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1388 resets = <&cpg 204>; 1396 resets = <&cpg 204>;
1389 status = "disabled"; 1397 status = "disabled";
1390 }; 1398 };
1391 1399
1392 scif4: serial@e6c40000 { 1400 scif4: serial@e6c40000 {
1393 compatible = "renesas 1401 compatible = "renesas,scif-r8a7796",
1394 "renesas 1402 "renesas,rcar-gen3-scif", "renesas,scif";
1395 reg = <0 0xe6c40000 0 1403 reg = <0 0xe6c40000 0 64>;
1396 interrupts = <GIC_SPI 1404 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1397 clocks = <&cpg CPG_MO 1405 clocks = <&cpg CPG_MOD 203>,
1398 <&cpg CPG_CO 1406 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
1399 <&scif_clk>; 1407 <&scif_clk>;
1400 clock-names = "fck", 1408 clock-names = "fck", "brg_int", "scif_clk";
1401 dmas = <&dmac0 0x59>, 1409 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1402 dma-names = "tx", "rx 1410 dma-names = "tx", "rx";
1403 power-domains = <&sys 1411 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1404 resets = <&cpg 203>; 1412 resets = <&cpg 203>;
1405 status = "disabled"; 1413 status = "disabled";
1406 }; 1414 };
1407 1415
1408 scif5: serial@e6f30000 { 1416 scif5: serial@e6f30000 {
1409 compatible = "renesas 1417 compatible = "renesas,scif-r8a7796",
1410 "renesas 1418 "renesas,rcar-gen3-scif", "renesas,scif";
1411 reg = <0 0xe6f30000 0 1419 reg = <0 0xe6f30000 0 64>;
1412 interrupts = <GIC_SPI 1420 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1413 clocks = <&cpg CPG_MO 1421 clocks = <&cpg CPG_MOD 202>,
1414 <&cpg CPG_CO 1422 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
1415 <&scif_clk>; 1423 <&scif_clk>;
1416 clock-names = "fck", 1424 clock-names = "fck", "brg_int", "scif_clk";
1417 dmas = <&dmac1 0x5b>, 1425 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
1418 <&dmac2 0x5b>, 1426 <&dmac2 0x5b>, <&dmac2 0x5a>;
1419 dma-names = "tx", "rx 1427 dma-names = "tx", "rx", "tx", "rx";
1420 power-domains = <&sys 1428 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1421 resets = <&cpg 202>; 1429 resets = <&cpg 202>;
1422 status = "disabled"; 1430 status = "disabled";
1423 }; 1431 };
1424 1432
1425 tpu: pwm@e6e80000 { 1433 tpu: pwm@e6e80000 {
1426 compatible = "renesas 1434 compatible = "renesas,tpu-r8a7796", "renesas,tpu";
1427 reg = <0 0xe6e80000 0 1435 reg = <0 0xe6e80000 0 0x148>;
1428 interrupts = <GIC_SPI 1436 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
1429 clocks = <&cpg CPG_MO 1437 clocks = <&cpg CPG_MOD 304>;
1430 power-domains = <&sys 1438 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1431 resets = <&cpg 304>; 1439 resets = <&cpg 304>;
1432 #pwm-cells = <3>; 1440 #pwm-cells = <3>;
1433 status = "disabled"; 1441 status = "disabled";
1434 }; 1442 };
1435 1443
1436 msiof0: spi@e6e90000 { 1444 msiof0: spi@e6e90000 {
1437 compatible = "renesas 1445 compatible = "renesas,msiof-r8a7796",
1438 "renesas 1446 "renesas,rcar-gen3-msiof";
1439 reg = <0 0xe6e90000 0 1447 reg = <0 0xe6e90000 0 0x0064>;
1440 interrupts = <GIC_SPI 1448 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1441 clocks = <&cpg CPG_MO 1449 clocks = <&cpg CPG_MOD 211>;
1442 dmas = <&dmac1 0x41>, 1450 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1443 <&dmac2 0x41>, 1451 <&dmac2 0x41>, <&dmac2 0x40>;
1444 dma-names = "tx", "rx 1452 dma-names = "tx", "rx", "tx", "rx";
1445 power-domains = <&sys 1453 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1446 resets = <&cpg 211>; 1454 resets = <&cpg 211>;
1447 #address-cells = <1>; 1455 #address-cells = <1>;
1448 #size-cells = <0>; 1456 #size-cells = <0>;
1449 status = "disabled"; 1457 status = "disabled";
1450 }; 1458 };
1451 1459
1452 msiof1: spi@e6ea0000 { 1460 msiof1: spi@e6ea0000 {
1453 compatible = "renesas 1461 compatible = "renesas,msiof-r8a7796",
1454 "renesas 1462 "renesas,rcar-gen3-msiof";
1455 reg = <0 0xe6ea0000 0 1463 reg = <0 0xe6ea0000 0 0x0064>;
1456 interrupts = <GIC_SPI 1464 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1457 clocks = <&cpg CPG_MO 1465 clocks = <&cpg CPG_MOD 210>;
1458 dmas = <&dmac1 0x43>, 1466 dmas = <&dmac1 0x43>, <&dmac1 0x42>,
1459 <&dmac2 0x43>, 1467 <&dmac2 0x43>, <&dmac2 0x42>;
1460 dma-names = "tx", "rx 1468 dma-names = "tx", "rx", "tx", "rx";
1461 power-domains = <&sys 1469 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1462 resets = <&cpg 210>; 1470 resets = <&cpg 210>;
1463 #address-cells = <1>; 1471 #address-cells = <1>;
1464 #size-cells = <0>; 1472 #size-cells = <0>;
1465 status = "disabled"; 1473 status = "disabled";
1466 }; 1474 };
1467 1475
1468 msiof2: spi@e6c00000 { 1476 msiof2: spi@e6c00000 {
1469 compatible = "renesas 1477 compatible = "renesas,msiof-r8a7796",
1470 "renesas 1478 "renesas,rcar-gen3-msiof";
1471 reg = <0 0xe6c00000 0 1479 reg = <0 0xe6c00000 0 0x0064>;
1472 interrupts = <GIC_SPI 1480 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1473 clocks = <&cpg CPG_MO 1481 clocks = <&cpg CPG_MOD 209>;
1474 dmas = <&dmac0 0x45>, 1482 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1475 dma-names = "tx", "rx 1483 dma-names = "tx", "rx";
1476 power-domains = <&sys 1484 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1477 resets = <&cpg 209>; 1485 resets = <&cpg 209>;
1478 #address-cells = <1>; 1486 #address-cells = <1>;
1479 #size-cells = <0>; 1487 #size-cells = <0>;
1480 status = "disabled"; 1488 status = "disabled";
1481 }; 1489 };
1482 1490
1483 msiof3: spi@e6c10000 { 1491 msiof3: spi@e6c10000 {
1484 compatible = "renesas 1492 compatible = "renesas,msiof-r8a7796",
1485 "renesas 1493 "renesas,rcar-gen3-msiof";
1486 reg = <0 0xe6c10000 0 1494 reg = <0 0xe6c10000 0 0x0064>;
1487 interrupts = <GIC_SPI 1495 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1488 clocks = <&cpg CPG_MO 1496 clocks = <&cpg CPG_MOD 208>;
1489 dmas = <&dmac0 0x47>, 1497 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1490 dma-names = "tx", "rx 1498 dma-names = "tx", "rx";
1491 power-domains = <&sys 1499 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1492 resets = <&cpg 208>; 1500 resets = <&cpg 208>;
1493 #address-cells = <1>; 1501 #address-cells = <1>;
1494 #size-cells = <0>; 1502 #size-cells = <0>;
1495 status = "disabled"; 1503 status = "disabled";
1496 }; 1504 };
1497 1505
1498 vin0: video@e6ef0000 { 1506 vin0: video@e6ef0000 {
1499 compatible = "renesas 1507 compatible = "renesas,vin-r8a7796";
1500 reg = <0 0xe6ef0000 0 1508 reg = <0 0xe6ef0000 0 0x1000>;
1501 interrupts = <GIC_SPI 1509 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
1502 clocks = <&cpg CPG_MO 1510 clocks = <&cpg CPG_MOD 811>;
1503 power-domains = <&sys 1511 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1504 resets = <&cpg 811>; 1512 resets = <&cpg 811>;
1505 renesas,id = <0>; 1513 renesas,id = <0>;
1506 status = "disabled"; 1514 status = "disabled";
1507 1515
1508 ports { 1516 ports {
1509 #address-cell 1517 #address-cells = <1>;
1510 #size-cells = 1518 #size-cells = <0>;
1511 1519
1512 port@1 { 1520 port@1 {
1513 #addr 1521 #address-cells = <1>;
1514 #size 1522 #size-cells = <0>;
1515 1523
1516 reg = 1524 reg = <1>;
1517 1525
1518 vin0c 1526 vin0csi20: endpoint@0 {
1519 1527 reg = <0>;
1520 1528 remote-endpoint = <&csi20vin0>;
1521 }; 1529 };
1522 vin0c 1530 vin0csi40: endpoint@2 {
1523 1531 reg = <2>;
1524 1532 remote-endpoint = <&csi40vin0>;
1525 }; 1533 };
1526 }; 1534 };
1527 }; 1535 };
1528 }; 1536 };
1529 1537
1530 vin1: video@e6ef1000 { 1538 vin1: video@e6ef1000 {
1531 compatible = "renesas 1539 compatible = "renesas,vin-r8a7796";
1532 reg = <0 0xe6ef1000 0 1540 reg = <0 0xe6ef1000 0 0x1000>;
1533 interrupts = <GIC_SPI 1541 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
1534 clocks = <&cpg CPG_MO 1542 clocks = <&cpg CPG_MOD 810>;
1535 power-domains = <&sys 1543 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1536 resets = <&cpg 810>; 1544 resets = <&cpg 810>;
1537 renesas,id = <1>; 1545 renesas,id = <1>;
1538 status = "disabled"; 1546 status = "disabled";
1539 1547
1540 ports { 1548 ports {
1541 #address-cell 1549 #address-cells = <1>;
1542 #size-cells = 1550 #size-cells = <0>;
1543 1551
1544 port@1 { 1552 port@1 {
1545 #addr 1553 #address-cells = <1>;
1546 #size 1554 #size-cells = <0>;
1547 1555
1548 reg = 1556 reg = <1>;
1549 1557
1550 vin1c 1558 vin1csi20: endpoint@0 {
1551 1559 reg = <0>;
1552 1560 remote-endpoint = <&csi20vin1>;
1553 }; 1561 };
1554 vin1c 1562 vin1csi40: endpoint@2 {
1555 1563 reg = <2>;
1556 1564 remote-endpoint = <&csi40vin1>;
1557 }; 1565 };
1558 }; 1566 };
1559 }; 1567 };
1560 }; 1568 };
1561 1569
1562 vin2: video@e6ef2000 { 1570 vin2: video@e6ef2000 {
1563 compatible = "renesas 1571 compatible = "renesas,vin-r8a7796";
1564 reg = <0 0xe6ef2000 0 1572 reg = <0 0xe6ef2000 0 0x1000>;
1565 interrupts = <GIC_SPI 1573 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1566 clocks = <&cpg CPG_MO 1574 clocks = <&cpg CPG_MOD 809>;
1567 power-domains = <&sys 1575 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1568 resets = <&cpg 809>; 1576 resets = <&cpg 809>;
1569 renesas,id = <2>; 1577 renesas,id = <2>;
1570 status = "disabled"; 1578 status = "disabled";
1571 1579
1572 ports { 1580 ports {
1573 #address-cell 1581 #address-cells = <1>;
1574 #size-cells = 1582 #size-cells = <0>;
1575 1583
1576 port@1 { 1584 port@1 {
1577 #addr 1585 #address-cells = <1>;
1578 #size 1586 #size-cells = <0>;
1579 1587
1580 reg = 1588 reg = <1>;
1581 1589
1582 vin2c 1590 vin2csi20: endpoint@0 {
1583 1591 reg = <0>;
1584 1592 remote-endpoint = <&csi20vin2>;
1585 }; 1593 };
1586 vin2c 1594 vin2csi40: endpoint@2 {
1587 1595 reg = <2>;
1588 1596 remote-endpoint = <&csi40vin2>;
1589 }; 1597 };
1590 }; 1598 };
1591 }; 1599 };
1592 }; 1600 };
1593 1601
1594 vin3: video@e6ef3000 { 1602 vin3: video@e6ef3000 {
1595 compatible = "renesas 1603 compatible = "renesas,vin-r8a7796";
1596 reg = <0 0xe6ef3000 0 1604 reg = <0 0xe6ef3000 0 0x1000>;
1597 interrupts = <GIC_SPI 1605 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
1598 clocks = <&cpg CPG_MO 1606 clocks = <&cpg CPG_MOD 808>;
1599 power-domains = <&sys 1607 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1600 resets = <&cpg 808>; 1608 resets = <&cpg 808>;
1601 renesas,id = <3>; 1609 renesas,id = <3>;
1602 status = "disabled"; 1610 status = "disabled";
1603 1611
1604 ports { 1612 ports {
1605 #address-cell 1613 #address-cells = <1>;
1606 #size-cells = 1614 #size-cells = <0>;
1607 1615
1608 port@1 { 1616 port@1 {
1609 #addr 1617 #address-cells = <1>;
1610 #size 1618 #size-cells = <0>;
1611 1619
1612 reg = 1620 reg = <1>;
1613 1621
1614 vin3c 1622 vin3csi20: endpoint@0 {
1615 1623 reg = <0>;
1616 1624 remote-endpoint = <&csi20vin3>;
1617 }; 1625 };
1618 vin3c 1626 vin3csi40: endpoint@2 {
1619 1627 reg = <2>;
1620 1628 remote-endpoint = <&csi40vin3>;
1621 }; 1629 };
1622 }; 1630 };
1623 }; 1631 };
1624 }; 1632 };
1625 1633
1626 vin4: video@e6ef4000 { 1634 vin4: video@e6ef4000 {
1627 compatible = "renesas 1635 compatible = "renesas,vin-r8a7796";
1628 reg = <0 0xe6ef4000 0 1636 reg = <0 0xe6ef4000 0 0x1000>;
1629 interrupts = <GIC_SPI 1637 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
1630 clocks = <&cpg CPG_MO 1638 clocks = <&cpg CPG_MOD 807>;
1631 power-domains = <&sys 1639 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1632 resets = <&cpg 807>; 1640 resets = <&cpg 807>;
1633 renesas,id = <4>; 1641 renesas,id = <4>;
1634 status = "disabled"; 1642 status = "disabled";
1635 1643
1636 ports { 1644 ports {
1637 #address-cell 1645 #address-cells = <1>;
1638 #size-cells = 1646 #size-cells = <0>;
1639 1647
1640 port@1 { 1648 port@1 {
1641 #addr 1649 #address-cells = <1>;
1642 #size 1650 #size-cells = <0>;
1643 1651
1644 reg = 1652 reg = <1>;
1645 1653
1646 vin4c 1654 vin4csi20: endpoint@0 {
1647 1655 reg = <0>;
1648 1656 remote-endpoint = <&csi20vin4>;
1649 }; 1657 };
1650 vin4c 1658 vin4csi40: endpoint@2 {
1651 1659 reg = <2>;
1652 1660 remote-endpoint = <&csi40vin4>;
1653 }; 1661 };
1654 }; 1662 };
1655 }; 1663 };
1656 }; 1664 };
1657 1665
1658 vin5: video@e6ef5000 { 1666 vin5: video@e6ef5000 {
1659 compatible = "renesas 1667 compatible = "renesas,vin-r8a7796";
1660 reg = <0 0xe6ef5000 0 1668 reg = <0 0xe6ef5000 0 0x1000>;
1661 interrupts = <GIC_SPI 1669 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
1662 clocks = <&cpg CPG_MO 1670 clocks = <&cpg CPG_MOD 806>;
1663 power-domains = <&sys 1671 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1664 resets = <&cpg 806>; 1672 resets = <&cpg 806>;
1665 renesas,id = <5>; 1673 renesas,id = <5>;
1666 status = "disabled"; 1674 status = "disabled";
1667 1675
1668 ports { 1676 ports {
1669 #address-cell 1677 #address-cells = <1>;
1670 #size-cells = 1678 #size-cells = <0>;
1671 1679
1672 port@1 { 1680 port@1 {
1673 #addr 1681 #address-cells = <1>;
1674 #size 1682 #size-cells = <0>;
1675 1683
1676 reg = 1684 reg = <1>;
1677 1685
1678 vin5c 1686 vin5csi20: endpoint@0 {
1679 1687 reg = <0>;
1680 1688 remote-endpoint = <&csi20vin5>;
1681 }; 1689 };
1682 vin5c 1690 vin5csi40: endpoint@2 {
1683 1691 reg = <2>;
1684 1692 remote-endpoint = <&csi40vin5>;
1685 }; 1693 };
1686 }; 1694 };
1687 }; 1695 };
1688 }; 1696 };
1689 1697
1690 vin6: video@e6ef6000 { 1698 vin6: video@e6ef6000 {
1691 compatible = "renesas 1699 compatible = "renesas,vin-r8a7796";
1692 reg = <0 0xe6ef6000 0 1700 reg = <0 0xe6ef6000 0 0x1000>;
1693 interrupts = <GIC_SPI 1701 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
1694 clocks = <&cpg CPG_MO 1702 clocks = <&cpg CPG_MOD 805>;
1695 power-domains = <&sys 1703 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1696 resets = <&cpg 805>; 1704 resets = <&cpg 805>;
1697 renesas,id = <6>; 1705 renesas,id = <6>;
1698 status = "disabled"; 1706 status = "disabled";
1699 1707
1700 ports { 1708 ports {
1701 #address-cell 1709 #address-cells = <1>;
1702 #size-cells = 1710 #size-cells = <0>;
1703 1711
1704 port@1 { 1712 port@1 {
1705 #addr 1713 #address-cells = <1>;
1706 #size 1714 #size-cells = <0>;
1707 1715
1708 reg = 1716 reg = <1>;
1709 1717
1710 vin6c 1718 vin6csi20: endpoint@0 {
1711 1719 reg = <0>;
1712 1720 remote-endpoint = <&csi20vin6>;
1713 }; 1721 };
1714 vin6c 1722 vin6csi40: endpoint@2 {
1715 1723 reg = <2>;
1716 1724 remote-endpoint = <&csi40vin6>;
1717 }; 1725 };
1718 }; 1726 };
1719 }; 1727 };
1720 }; 1728 };
1721 1729
1722 vin7: video@e6ef7000 { 1730 vin7: video@e6ef7000 {
1723 compatible = "renesas 1731 compatible = "renesas,vin-r8a7796";
1724 reg = <0 0xe6ef7000 0 1732 reg = <0 0xe6ef7000 0 0x1000>;
1725 interrupts = <GIC_SPI 1733 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
1726 clocks = <&cpg CPG_MO 1734 clocks = <&cpg CPG_MOD 804>;
1727 power-domains = <&sys 1735 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1728 resets = <&cpg 804>; 1736 resets = <&cpg 804>;
1729 renesas,id = <7>; 1737 renesas,id = <7>;
1730 status = "disabled"; 1738 status = "disabled";
1731 1739
1732 ports { 1740 ports {
1733 #address-cell 1741 #address-cells = <1>;
1734 #size-cells = 1742 #size-cells = <0>;
1735 1743
1736 port@1 { 1744 port@1 {
1737 #addr 1745 #address-cells = <1>;
1738 #size 1746 #size-cells = <0>;
1739 1747
1740 reg = 1748 reg = <1>;
1741 1749
1742 vin7c 1750 vin7csi20: endpoint@0 {
1743 1751 reg = <0>;
1744 1752 remote-endpoint = <&csi20vin7>;
1745 }; 1753 };
1746 vin7c 1754 vin7csi40: endpoint@2 {
1747 1755 reg = <2>;
1748 1756 remote-endpoint = <&csi40vin7>;
1749 }; 1757 };
1750 }; 1758 };
1751 }; 1759 };
1752 }; 1760 };
1753 1761
1754 drif00: rif@e6f40000 { 1762 drif00: rif@e6f40000 {
1755 compatible = "renesas 1763 compatible = "renesas,r8a7796-drif",
1756 "renesas 1764 "renesas,rcar-gen3-drif";
1757 reg = <0 0xe6f40000 0 1765 reg = <0 0xe6f40000 0 0x64>;
1758 interrupts = <GIC_SPI 1766 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1759 clocks = <&cpg CPG_MO 1767 clocks = <&cpg CPG_MOD 515>;
1760 clock-names = "fck"; 1768 clock-names = "fck";
1761 dmas = <&dmac1 0x20>, 1769 dmas = <&dmac1 0x20>, <&dmac2 0x20>;
1762 dma-names = "rx", "rx 1770 dma-names = "rx", "rx";
1763 power-domains = <&sys 1771 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1764 resets = <&cpg 515>; 1772 resets = <&cpg 515>;
1765 renesas,bonding = <&d 1773 renesas,bonding = <&drif01>;
1766 status = "disabled"; 1774 status = "disabled";
1767 }; 1775 };
1768 1776
1769 drif01: rif@e6f50000 { 1777 drif01: rif@e6f50000 {
1770 compatible = "renesas 1778 compatible = "renesas,r8a7796-drif",
1771 "renesas 1779 "renesas,rcar-gen3-drif";
1772 reg = <0 0xe6f50000 0 1780 reg = <0 0xe6f50000 0 0x64>;
1773 interrupts = <GIC_SPI 1781 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1774 clocks = <&cpg CPG_MO 1782 clocks = <&cpg CPG_MOD 514>;
1775 clock-names = "fck"; 1783 clock-names = "fck";
1776 dmas = <&dmac1 0x22>, 1784 dmas = <&dmac1 0x22>, <&dmac2 0x22>;
1777 dma-names = "rx", "rx 1785 dma-names = "rx", "rx";
1778 power-domains = <&sys 1786 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1779 resets = <&cpg 514>; 1787 resets = <&cpg 514>;
1780 renesas,bonding = <&d 1788 renesas,bonding = <&drif00>;
1781 status = "disabled"; 1789 status = "disabled";
1782 }; 1790 };
1783 1791
1784 drif10: rif@e6f60000 { 1792 drif10: rif@e6f60000 {
1785 compatible = "renesas 1793 compatible = "renesas,r8a7796-drif",
1786 "renesas 1794 "renesas,rcar-gen3-drif";
1787 reg = <0 0xe6f60000 0 1795 reg = <0 0xe6f60000 0 0x64>;
1788 interrupts = <GIC_SPI 1796 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1789 clocks = <&cpg CPG_MO 1797 clocks = <&cpg CPG_MOD 513>;
1790 clock-names = "fck"; 1798 clock-names = "fck";
1791 dmas = <&dmac1 0x24>, 1799 dmas = <&dmac1 0x24>, <&dmac2 0x24>;
1792 dma-names = "rx", "rx 1800 dma-names = "rx", "rx";
1793 power-domains = <&sys 1801 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1794 resets = <&cpg 513>; 1802 resets = <&cpg 513>;
1795 renesas,bonding = <&d 1803 renesas,bonding = <&drif11>;
1796 status = "disabled"; 1804 status = "disabled";
1797 }; 1805 };
1798 1806
1799 drif11: rif@e6f70000 { 1807 drif11: rif@e6f70000 {
1800 compatible = "renesas 1808 compatible = "renesas,r8a7796-drif",
1801 "renesas 1809 "renesas,rcar-gen3-drif";
1802 reg = <0 0xe6f70000 0 1810 reg = <0 0xe6f70000 0 0x64>;
1803 interrupts = <GIC_SPI 1811 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1804 clocks = <&cpg CPG_MO 1812 clocks = <&cpg CPG_MOD 512>;
1805 clock-names = "fck"; 1813 clock-names = "fck";
1806 dmas = <&dmac1 0x26>, 1814 dmas = <&dmac1 0x26>, <&dmac2 0x26>;
1807 dma-names = "rx", "rx 1815 dma-names = "rx", "rx";
1808 power-domains = <&sys 1816 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1809 resets = <&cpg 512>; 1817 resets = <&cpg 512>;
1810 renesas,bonding = <&d 1818 renesas,bonding = <&drif10>;
1811 status = "disabled"; 1819 status = "disabled";
1812 }; 1820 };
1813 1821
1814 drif20: rif@e6f80000 { 1822 drif20: rif@e6f80000 {
1815 compatible = "renesas 1823 compatible = "renesas,r8a7796-drif",
1816 "renesas 1824 "renesas,rcar-gen3-drif";
1817 reg = <0 0xe6f80000 0 1825 reg = <0 0xe6f80000 0 0x64>;
1818 interrupts = <GIC_SPI 1826 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1819 clocks = <&cpg CPG_MO 1827 clocks = <&cpg CPG_MOD 511>;
1820 clock-names = "fck"; 1828 clock-names = "fck";
1821 dmas = <&dmac1 0x28>, 1829 dmas = <&dmac1 0x28>, <&dmac2 0x28>;
1822 dma-names = "rx", "rx 1830 dma-names = "rx", "rx";
1823 power-domains = <&sys 1831 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1824 resets = <&cpg 511>; 1832 resets = <&cpg 511>;
1825 renesas,bonding = <&d 1833 renesas,bonding = <&drif21>;
1826 status = "disabled"; 1834 status = "disabled";
1827 }; 1835 };
1828 1836
1829 drif21: rif@e6f90000 { 1837 drif21: rif@e6f90000 {
1830 compatible = "renesas 1838 compatible = "renesas,r8a7796-drif",
1831 "renesas 1839 "renesas,rcar-gen3-drif";
1832 reg = <0 0xe6f90000 0 1840 reg = <0 0xe6f90000 0 0x64>;
1833 interrupts = <GIC_SPI 1841 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1834 clocks = <&cpg CPG_MO 1842 clocks = <&cpg CPG_MOD 510>;
1835 clock-names = "fck"; 1843 clock-names = "fck";
1836 dmas = <&dmac1 0x2a>, 1844 dmas = <&dmac1 0x2a>, <&dmac2 0x2a>;
1837 dma-names = "rx", "rx 1845 dma-names = "rx", "rx";
1838 power-domains = <&sys 1846 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1839 resets = <&cpg 510>; 1847 resets = <&cpg 510>;
1840 renesas,bonding = <&d 1848 renesas,bonding = <&drif20>;
1841 status = "disabled"; 1849 status = "disabled";
1842 }; 1850 };
1843 1851
1844 drif30: rif@e6fa0000 { 1852 drif30: rif@e6fa0000 {
1845 compatible = "renesas 1853 compatible = "renesas,r8a7796-drif",
1846 "renesas 1854 "renesas,rcar-gen3-drif";
1847 reg = <0 0xe6fa0000 0 1855 reg = <0 0xe6fa0000 0 0x64>;
1848 interrupts = <GIC_SPI 1856 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1849 clocks = <&cpg CPG_MO 1857 clocks = <&cpg CPG_MOD 509>;
1850 clock-names = "fck"; 1858 clock-names = "fck";
1851 dmas = <&dmac1 0x2c>, 1859 dmas = <&dmac1 0x2c>, <&dmac2 0x2c>;
1852 dma-names = "rx", "rx 1860 dma-names = "rx", "rx";
1853 power-domains = <&sys 1861 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1854 resets = <&cpg 509>; 1862 resets = <&cpg 509>;
1855 renesas,bonding = <&d 1863 renesas,bonding = <&drif31>;
1856 status = "disabled"; 1864 status = "disabled";
1857 }; 1865 };
1858 1866
1859 drif31: rif@e6fb0000 { 1867 drif31: rif@e6fb0000 {
1860 compatible = "renesas 1868 compatible = "renesas,r8a7796-drif",
1861 "renesas 1869 "renesas,rcar-gen3-drif";
1862 reg = <0 0xe6fb0000 0 1870 reg = <0 0xe6fb0000 0 0x64>;
1863 interrupts = <GIC_SPI 1871 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1864 clocks = <&cpg CPG_MO 1872 clocks = <&cpg CPG_MOD 508>;
1865 clock-names = "fck"; 1873 clock-names = "fck";
1866 dmas = <&dmac1 0x2e>, 1874 dmas = <&dmac1 0x2e>, <&dmac2 0x2e>;
1867 dma-names = "rx", "rx 1875 dma-names = "rx", "rx";
1868 power-domains = <&sys 1876 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1869 resets = <&cpg 508>; 1877 resets = <&cpg 508>;
1870 renesas,bonding = <&d 1878 renesas,bonding = <&drif30>;
1871 status = "disabled"; 1879 status = "disabled";
1872 }; 1880 };
1873 1881
1874 rcar_sound: sound@ec500000 { 1882 rcar_sound: sound@ec500000 {
1875 /* 1883 /*
1876 * #sound-dai-cells i !! 1884 * #sound-dai-cells is required
1877 * 1885 *
1878 * Single DAI : #soun 1886 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1879 * Multi DAI : #soun 1887 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1880 */ 1888 */
1881 /* 1889 /*
1882 * #clock-cells is re 1890 * #clock-cells is required for audio_clkout0/1/2/3
1883 * 1891 *
1884 * clkout : #cl 1892 * clkout : #clock-cells = <0>; <&rcar_sound>;
1885 * clkout0/1/2/3: #cl 1893 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
1886 */ 1894 */
1887 compatible = "renesas 1895 compatible = "renesas,rcar_sound-r8a7796", "renesas,rcar_sound-gen3";
1888 reg = <0 0xec500000 0 1896 reg = <0 0xec500000 0 0x1000>, /* SCU */
1889 <0 0xec5a0000 0 1897 <0 0xec5a0000 0 0x100>, /* ADG */
1890 <0 0xec540000 0 1898 <0 0xec540000 0 0x1000>, /* SSIU */
1891 <0 0xec541000 0 1899 <0 0xec541000 0 0x280>, /* SSI */
1892 <0 0xec760000 0 1900 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
1893 reg-names = "scu", "a 1901 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1894 1902
1895 clocks = <&cpg CPG_MO 1903 clocks = <&cpg CPG_MOD 1005>,
1896 <&cpg CPG_MO 1904 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
1897 <&cpg CPG_MO 1905 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
1898 <&cpg CPG_MO 1906 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
1899 <&cpg CPG_MO 1907 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
1900 <&cpg CPG_MO 1908 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
1901 <&cpg CPG_MO 1909 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
1902 <&cpg CPG_MO 1910 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
1903 <&cpg CPG_MO 1911 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
1904 <&cpg CPG_MO 1912 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
1905 <&cpg CPG_MO 1913 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
1906 <&cpg CPG_MO 1914 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1907 <&cpg CPG_MO 1915 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1908 <&cpg CPG_MO 1916 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
1909 <&audio_clk_ 1917 <&audio_clk_a>, <&audio_clk_b>,
1910 <&audio_clk_ 1918 <&audio_clk_c>,
1911 <&cpg CPG_MO !! 1919 <&cpg CPG_CORE R8A7796_CLK_S0D4>;
1912 clock-names = "ssi-al 1920 clock-names = "ssi-all",
1913 "ssi.9" 1921 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1914 "ssi.5" 1922 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1915 "ssi.1" 1923 "ssi.1", "ssi.0",
1916 "src.9" 1924 "src.9", "src.8", "src.7", "src.6",
1917 "src.5" 1925 "src.5", "src.4", "src.3", "src.2",
1918 "src.1" 1926 "src.1", "src.0",
1919 "mix.1" 1927 "mix.1", "mix.0",
1920 "ctu.1" 1928 "ctu.1", "ctu.0",
1921 "dvc.0" 1929 "dvc.0", "dvc.1",
1922 "clk_a" 1930 "clk_a", "clk_b", "clk_c", "clk_i";
1923 power-domains = <&sys 1931 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1924 resets = <&cpg 1005>, 1932 resets = <&cpg 1005>,
1925 <&cpg 1006>, 1933 <&cpg 1006>, <&cpg 1007>,
1926 <&cpg 1008>, 1934 <&cpg 1008>, <&cpg 1009>,
1927 <&cpg 1010>, 1935 <&cpg 1010>, <&cpg 1011>,
1928 <&cpg 1012>, 1936 <&cpg 1012>, <&cpg 1013>,
1929 <&cpg 1014>, 1937 <&cpg 1014>, <&cpg 1015>;
1930 reset-names = "ssi-al 1938 reset-names = "ssi-all",
1931 "ssi.9" 1939 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1932 "ssi.5" 1940 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1933 "ssi.1" 1941 "ssi.1", "ssi.0";
1934 status = "disabled"; 1942 status = "disabled";
1935 1943
1936 rcar_sound,ctu { 1944 rcar_sound,ctu {
1937 ctu00: ctu-0 1945 ctu00: ctu-0 { };
1938 ctu01: ctu-1 1946 ctu01: ctu-1 { };
1939 ctu02: ctu-2 1947 ctu02: ctu-2 { };
1940 ctu03: ctu-3 1948 ctu03: ctu-3 { };
1941 ctu10: ctu-4 1949 ctu10: ctu-4 { };
1942 ctu11: ctu-5 1950 ctu11: ctu-5 { };
1943 ctu12: ctu-6 1951 ctu12: ctu-6 { };
1944 ctu13: ctu-7 1952 ctu13: ctu-7 { };
1945 }; 1953 };
1946 1954
1947 rcar_sound,dvc { 1955 rcar_sound,dvc {
1948 dvc0: dvc-0 { 1956 dvc0: dvc-0 {
1949 dmas 1957 dmas = <&audma1 0xbc>;
1950 dma-n 1958 dma-names = "tx";
1951 }; 1959 };
1952 dvc1: dvc-1 { 1960 dvc1: dvc-1 {
1953 dmas 1961 dmas = <&audma1 0xbe>;
1954 dma-n 1962 dma-names = "tx";
1955 }; 1963 };
1956 }; 1964 };
1957 1965
1958 rcar_sound,mix { 1966 rcar_sound,mix {
1959 mix0: mix-0 { 1967 mix0: mix-0 { };
1960 mix1: mix-1 { 1968 mix1: mix-1 { };
1961 }; 1969 };
1962 1970
1963 rcar_sound,src { 1971 rcar_sound,src {
1964 src0: src-0 { 1972 src0: src-0 {
1965 inter 1973 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1966 dmas 1974 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1967 dma-n 1975 dma-names = "rx", "tx";
1968 }; 1976 };
1969 src1: src-1 { 1977 src1: src-1 {
1970 inter 1978 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1971 dmas 1979 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1972 dma-n 1980 dma-names = "rx", "tx";
1973 }; 1981 };
1974 src2: src-2 { 1982 src2: src-2 {
1975 inter 1983 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1976 dmas 1984 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1977 dma-n 1985 dma-names = "rx", "tx";
1978 }; 1986 };
1979 src3: src-3 { 1987 src3: src-3 {
1980 inter 1988 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1981 dmas 1989 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1982 dma-n 1990 dma-names = "rx", "tx";
1983 }; 1991 };
1984 src4: src-4 { 1992 src4: src-4 {
1985 inter 1993 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1986 dmas 1994 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1987 dma-n 1995 dma-names = "rx", "tx";
1988 }; 1996 };
1989 src5: src-5 { 1997 src5: src-5 {
1990 inter 1998 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1991 dmas 1999 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1992 dma-n 2000 dma-names = "rx", "tx";
1993 }; 2001 };
1994 src6: src-6 { 2002 src6: src-6 {
1995 inter 2003 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1996 dmas 2004 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1997 dma-n 2005 dma-names = "rx", "tx";
1998 }; 2006 };
1999 src7: src-7 { 2007 src7: src-7 {
2000 inter 2008 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
2001 dmas 2009 dmas = <&audma0 0x93>, <&audma1 0xb6>;
2002 dma-n 2010 dma-names = "rx", "tx";
2003 }; 2011 };
2004 src8: src-8 { 2012 src8: src-8 {
2005 inter 2013 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2006 dmas 2014 dmas = <&audma0 0x95>, <&audma1 0xb8>;
2007 dma-n 2015 dma-names = "rx", "tx";
2008 }; 2016 };
2009 src9: src-9 { 2017 src9: src-9 {
2010 inter 2018 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
2011 dmas 2019 dmas = <&audma0 0x97>, <&audma1 0xba>;
2012 dma-n 2020 dma-names = "rx", "tx";
2013 }; 2021 };
2014 }; 2022 };
2015 2023
2016 rcar_sound,ssi { 2024 rcar_sound,ssi {
2017 ssi0: ssi-0 { 2025 ssi0: ssi-0 {
2018 inter 2026 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
2019 dmas 2027 dmas = <&audma0 0x01>, <&audma1 0x02>;
2020 dma-n 2028 dma-names = "rx", "tx";
2021 }; 2029 };
2022 ssi1: ssi-1 { 2030 ssi1: ssi-1 {
2023 inter 2031 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
2024 dmas 2032 dmas = <&audma0 0x03>, <&audma1 0x04>;
2025 dma-n 2033 dma-names = "rx", "tx";
2026 }; 2034 };
2027 ssi2: ssi-2 { 2035 ssi2: ssi-2 {
2028 inter 2036 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
2029 dmas 2037 dmas = <&audma0 0x05>, <&audma1 0x06>;
2030 dma-n 2038 dma-names = "rx", "tx";
2031 }; 2039 };
2032 ssi3: ssi-3 { 2040 ssi3: ssi-3 {
2033 inter 2041 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
2034 dmas 2042 dmas = <&audma0 0x07>, <&audma1 0x08>;
2035 dma-n 2043 dma-names = "rx", "tx";
2036 }; 2044 };
2037 ssi4: ssi-4 { 2045 ssi4: ssi-4 {
2038 inter 2046 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
2039 dmas 2047 dmas = <&audma0 0x09>, <&audma1 0x0a>;
2040 dma-n 2048 dma-names = "rx", "tx";
2041 }; 2049 };
2042 ssi5: ssi-5 { 2050 ssi5: ssi-5 {
2043 inter 2051 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
2044 dmas 2052 dmas = <&audma0 0x0b>, <&audma1 0x0c>;
2045 dma-n 2053 dma-names = "rx", "tx";
2046 }; 2054 };
2047 ssi6: ssi-6 { 2055 ssi6: ssi-6 {
2048 inter 2056 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
2049 dmas 2057 dmas = <&audma0 0x0d>, <&audma1 0x0e>;
2050 dma-n 2058 dma-names = "rx", "tx";
2051 }; 2059 };
2052 ssi7: ssi-7 { 2060 ssi7: ssi-7 {
2053 inter 2061 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
2054 dmas 2062 dmas = <&audma0 0x0f>, <&audma1 0x10>;
2055 dma-n 2063 dma-names = "rx", "tx";
2056 }; 2064 };
2057 ssi8: ssi-8 { 2065 ssi8: ssi-8 {
2058 inter 2066 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
2059 dmas 2067 dmas = <&audma0 0x11>, <&audma1 0x12>;
2060 dma-n 2068 dma-names = "rx", "tx";
2061 }; 2069 };
2062 ssi9: ssi-9 { 2070 ssi9: ssi-9 {
2063 inter 2071 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
2064 dmas 2072 dmas = <&audma0 0x13>, <&audma1 0x14>;
2065 dma-n 2073 dma-names = "rx", "tx";
2066 }; 2074 };
2067 }; 2075 };
2068 2076
2069 rcar_sound,ssiu { 2077 rcar_sound,ssiu {
2070 ssiu00: ssiu- 2078 ssiu00: ssiu-0 {
2071 dmas 2079 dmas = <&audma0 0x15>, <&audma1 0x16>;
2072 dma-n 2080 dma-names = "rx", "tx";
2073 }; 2081 };
2074 ssiu01: ssiu- 2082 ssiu01: ssiu-1 {
2075 dmas 2083 dmas = <&audma0 0x35>, <&audma1 0x36>;
2076 dma-n 2084 dma-names = "rx", "tx";
2077 }; 2085 };
2078 ssiu02: ssiu- 2086 ssiu02: ssiu-2 {
2079 dmas 2087 dmas = <&audma0 0x37>, <&audma1 0x38>;
2080 dma-n 2088 dma-names = "rx", "tx";
2081 }; 2089 };
2082 ssiu03: ssiu- 2090 ssiu03: ssiu-3 {
2083 dmas 2091 dmas = <&audma0 0x47>, <&audma1 0x48>;
2084 dma-n 2092 dma-names = "rx", "tx";
2085 }; 2093 };
2086 ssiu04: ssiu- 2094 ssiu04: ssiu-4 {
2087 dmas 2095 dmas = <&audma0 0x3F>, <&audma1 0x40>;
2088 dma-n 2096 dma-names = "rx", "tx";
2089 }; 2097 };
2090 ssiu05: ssiu- 2098 ssiu05: ssiu-5 {
2091 dmas 2099 dmas = <&audma0 0x43>, <&audma1 0x44>;
2092 dma-n 2100 dma-names = "rx", "tx";
2093 }; 2101 };
2094 ssiu06: ssiu- 2102 ssiu06: ssiu-6 {
2095 dmas 2103 dmas = <&audma0 0x4F>, <&audma1 0x50>;
2096 dma-n 2104 dma-names = "rx", "tx";
2097 }; 2105 };
2098 ssiu07: ssiu- 2106 ssiu07: ssiu-7 {
2099 dmas 2107 dmas = <&audma0 0x53>, <&audma1 0x54>;
2100 dma-n 2108 dma-names = "rx", "tx";
2101 }; 2109 };
2102 ssiu10: ssiu- 2110 ssiu10: ssiu-8 {
2103 dmas 2111 dmas = <&audma0 0x49>, <&audma1 0x4a>;
2104 dma-n 2112 dma-names = "rx", "tx";
2105 }; 2113 };
2106 ssiu11: ssiu- 2114 ssiu11: ssiu-9 {
2107 dmas 2115 dmas = <&audma0 0x4B>, <&audma1 0x4C>;
2108 dma-n 2116 dma-names = "rx", "tx";
2109 }; 2117 };
2110 ssiu12: ssiu- 2118 ssiu12: ssiu-10 {
2111 dmas 2119 dmas = <&audma0 0x57>, <&audma1 0x58>;
2112 dma-n 2120 dma-names = "rx", "tx";
2113 }; 2121 };
2114 ssiu13: ssiu- 2122 ssiu13: ssiu-11 {
2115 dmas 2123 dmas = <&audma0 0x59>, <&audma1 0x5A>;
2116 dma-n 2124 dma-names = "rx", "tx";
2117 }; 2125 };
2118 ssiu14: ssiu- 2126 ssiu14: ssiu-12 {
2119 dmas 2127 dmas = <&audma0 0x5F>, <&audma1 0x60>;
2120 dma-n 2128 dma-names = "rx", "tx";
2121 }; 2129 };
2122 ssiu15: ssiu- 2130 ssiu15: ssiu-13 {
2123 dmas 2131 dmas = <&audma0 0xC3>, <&audma1 0xC4>;
2124 dma-n 2132 dma-names = "rx", "tx";
2125 }; 2133 };
2126 ssiu16: ssiu- 2134 ssiu16: ssiu-14 {
2127 dmas 2135 dmas = <&audma0 0xC7>, <&audma1 0xC8>;
2128 dma-n 2136 dma-names = "rx", "tx";
2129 }; 2137 };
2130 ssiu17: ssiu- 2138 ssiu17: ssiu-15 {
2131 dmas 2139 dmas = <&audma0 0xCB>, <&audma1 0xCC>;
2132 dma-n 2140 dma-names = "rx", "tx";
2133 }; 2141 };
2134 ssiu20: ssiu- 2142 ssiu20: ssiu-16 {
2135 dmas 2143 dmas = <&audma0 0x63>, <&audma1 0x64>;
2136 dma-n 2144 dma-names = "rx", "tx";
2137 }; 2145 };
2138 ssiu21: ssiu- 2146 ssiu21: ssiu-17 {
2139 dmas 2147 dmas = <&audma0 0x67>, <&audma1 0x68>;
2140 dma-n 2148 dma-names = "rx", "tx";
2141 }; 2149 };
2142 ssiu22: ssiu- 2150 ssiu22: ssiu-18 {
2143 dmas 2151 dmas = <&audma0 0x6B>, <&audma1 0x6C>;
2144 dma-n 2152 dma-names = "rx", "tx";
2145 }; 2153 };
2146 ssiu23: ssiu- 2154 ssiu23: ssiu-19 {
2147 dmas 2155 dmas = <&audma0 0x6D>, <&audma1 0x6E>;
2148 dma-n 2156 dma-names = "rx", "tx";
2149 }; 2157 };
2150 ssiu24: ssiu- 2158 ssiu24: ssiu-20 {
2151 dmas 2159 dmas = <&audma0 0xCF>, <&audma1 0xCE>;
2152 dma-n 2160 dma-names = "rx", "tx";
2153 }; 2161 };
2154 ssiu25: ssiu- 2162 ssiu25: ssiu-21 {
2155 dmas 2163 dmas = <&audma0 0xEB>, <&audma1 0xEC>;
2156 dma-n 2164 dma-names = "rx", "tx";
2157 }; 2165 };
2158 ssiu26: ssiu- 2166 ssiu26: ssiu-22 {
2159 dmas 2167 dmas = <&audma0 0xED>, <&audma1 0xEE>;
2160 dma-n 2168 dma-names = "rx", "tx";
2161 }; 2169 };
2162 ssiu27: ssiu- 2170 ssiu27: ssiu-23 {
2163 dmas 2171 dmas = <&audma0 0xEF>, <&audma1 0xF0>;
2164 dma-n 2172 dma-names = "rx", "tx";
2165 }; 2173 };
2166 ssiu30: ssiu- 2174 ssiu30: ssiu-24 {
2167 dmas 2175 dmas = <&audma0 0x6f>, <&audma1 0x70>;
2168 dma-n 2176 dma-names = "rx", "tx";
2169 }; 2177 };
2170 ssiu31: ssiu- 2178 ssiu31: ssiu-25 {
2171 dmas 2179 dmas = <&audma0 0x21>, <&audma1 0x22>;
2172 dma-n 2180 dma-names = "rx", "tx";
2173 }; 2181 };
2174 ssiu32: ssiu- 2182 ssiu32: ssiu-26 {
2175 dmas 2183 dmas = <&audma0 0x23>, <&audma1 0x24>;
2176 dma-n 2184 dma-names = "rx", "tx";
2177 }; 2185 };
2178 ssiu33: ssiu- 2186 ssiu33: ssiu-27 {
2179 dmas 2187 dmas = <&audma0 0x25>, <&audma1 0x26>;
2180 dma-n 2188 dma-names = "rx", "tx";
2181 }; 2189 };
2182 ssiu34: ssiu- 2190 ssiu34: ssiu-28 {
2183 dmas 2191 dmas = <&audma0 0x27>, <&audma1 0x28>;
2184 dma-n 2192 dma-names = "rx", "tx";
2185 }; 2193 };
2186 ssiu35: ssiu- 2194 ssiu35: ssiu-29 {
2187 dmas 2195 dmas = <&audma0 0x29>, <&audma1 0x2A>;
2188 dma-n 2196 dma-names = "rx", "tx";
2189 }; 2197 };
2190 ssiu36: ssiu- 2198 ssiu36: ssiu-30 {
2191 dmas 2199 dmas = <&audma0 0x2B>, <&audma1 0x2C>;
2192 dma-n 2200 dma-names = "rx", "tx";
2193 }; 2201 };
2194 ssiu37: ssiu- 2202 ssiu37: ssiu-31 {
2195 dmas 2203 dmas = <&audma0 0x2D>, <&audma1 0x2E>;
2196 dma-n 2204 dma-names = "rx", "tx";
2197 }; 2205 };
2198 ssiu40: ssiu- 2206 ssiu40: ssiu-32 {
2199 dmas 2207 dmas = <&audma0 0x71>, <&audma1 0x72>;
2200 dma-n 2208 dma-names = "rx", "tx";
2201 }; 2209 };
2202 ssiu41: ssiu- 2210 ssiu41: ssiu-33 {
2203 dmas 2211 dmas = <&audma0 0x17>, <&audma1 0x18>;
2204 dma-n 2212 dma-names = "rx", "tx";
2205 }; 2213 };
2206 ssiu42: ssiu- 2214 ssiu42: ssiu-34 {
2207 dmas 2215 dmas = <&audma0 0x19>, <&audma1 0x1A>;
2208 dma-n 2216 dma-names = "rx", "tx";
2209 }; 2217 };
2210 ssiu43: ssiu- 2218 ssiu43: ssiu-35 {
2211 dmas 2219 dmas = <&audma0 0x1B>, <&audma1 0x1C>;
2212 dma-n 2220 dma-names = "rx", "tx";
2213 }; 2221 };
2214 ssiu44: ssiu- 2222 ssiu44: ssiu-36 {
2215 dmas 2223 dmas = <&audma0 0x1D>, <&audma1 0x1E>;
2216 dma-n 2224 dma-names = "rx", "tx";
2217 }; 2225 };
2218 ssiu45: ssiu- 2226 ssiu45: ssiu-37 {
2219 dmas 2227 dmas = <&audma0 0x1F>, <&audma1 0x20>;
2220 dma-n 2228 dma-names = "rx", "tx";
2221 }; 2229 };
2222 ssiu46: ssiu- 2230 ssiu46: ssiu-38 {
2223 dmas 2231 dmas = <&audma0 0x31>, <&audma1 0x32>;
2224 dma-n 2232 dma-names = "rx", "tx";
2225 }; 2233 };
2226 ssiu47: ssiu- 2234 ssiu47: ssiu-39 {
2227 dmas 2235 dmas = <&audma0 0x33>, <&audma1 0x34>;
2228 dma-n 2236 dma-names = "rx", "tx";
2229 }; 2237 };
2230 ssiu50: ssiu- 2238 ssiu50: ssiu-40 {
2231 dmas 2239 dmas = <&audma0 0x73>, <&audma1 0x74>;
2232 dma-n 2240 dma-names = "rx", "tx";
2233 }; 2241 };
2234 ssiu60: ssiu- 2242 ssiu60: ssiu-41 {
2235 dmas 2243 dmas = <&audma0 0x75>, <&audma1 0x76>;
2236 dma-n 2244 dma-names = "rx", "tx";
2237 }; 2245 };
2238 ssiu70: ssiu- 2246 ssiu70: ssiu-42 {
2239 dmas 2247 dmas = <&audma0 0x79>, <&audma1 0x7a>;
2240 dma-n 2248 dma-names = "rx", "tx";
2241 }; 2249 };
2242 ssiu80: ssiu- 2250 ssiu80: ssiu-43 {
2243 dmas 2251 dmas = <&audma0 0x7b>, <&audma1 0x7c>;
2244 dma-n 2252 dma-names = "rx", "tx";
2245 }; 2253 };
2246 ssiu90: ssiu- 2254 ssiu90: ssiu-44 {
2247 dmas 2255 dmas = <&audma0 0x7d>, <&audma1 0x7e>;
2248 dma-n 2256 dma-names = "rx", "tx";
2249 }; 2257 };
2250 ssiu91: ssiu- 2258 ssiu91: ssiu-45 {
2251 dmas 2259 dmas = <&audma0 0x7F>, <&audma1 0x80>;
2252 dma-n 2260 dma-names = "rx", "tx";
2253 }; 2261 };
2254 ssiu92: ssiu- 2262 ssiu92: ssiu-46 {
2255 dmas 2263 dmas = <&audma0 0x81>, <&audma1 0x82>;
2256 dma-n 2264 dma-names = "rx", "tx";
2257 }; 2265 };
2258 ssiu93: ssiu- 2266 ssiu93: ssiu-47 {
2259 dmas 2267 dmas = <&audma0 0x83>, <&audma1 0x84>;
2260 dma-n 2268 dma-names = "rx", "tx";
2261 }; 2269 };
2262 ssiu94: ssiu- 2270 ssiu94: ssiu-48 {
2263 dmas 2271 dmas = <&audma0 0xA3>, <&audma1 0xA4>;
2264 dma-n 2272 dma-names = "rx", "tx";
2265 }; 2273 };
2266 ssiu95: ssiu- 2274 ssiu95: ssiu-49 {
2267 dmas 2275 dmas = <&audma0 0xA5>, <&audma1 0xA6>;
2268 dma-n 2276 dma-names = "rx", "tx";
2269 }; 2277 };
2270 ssiu96: ssiu- 2278 ssiu96: ssiu-50 {
2271 dmas 2279 dmas = <&audma0 0xA7>, <&audma1 0xA8>;
2272 dma-n 2280 dma-names = "rx", "tx";
2273 }; 2281 };
2274 ssiu97: ssiu- 2282 ssiu97: ssiu-51 {
2275 dmas 2283 dmas = <&audma0 0xA9>, <&audma1 0xAA>;
2276 dma-n 2284 dma-names = "rx", "tx";
2277 }; 2285 };
2278 }; 2286 };
2279 }; 2287 };
2280 2288
2281 mlp: mlp@ec520000 { 2289 mlp: mlp@ec520000 {
2282 compatible = "renesas 2290 compatible = "renesas,r8a7796-mlp",
2283 "renesas 2291 "renesas,rcar-gen3-mlp";
2284 reg = <0 0xec520000 0 2292 reg = <0 0xec520000 0 0x800>;
2285 interrupts = <GIC_SPI 2293 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
2286 <GIC_SPI 385 2294 <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>;
2287 clocks = <&cpg CPG_MO 2295 clocks = <&cpg CPG_MOD 802>;
2288 power-domains = <&sys 2296 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2289 resets = <&cpg 802>; 2297 resets = <&cpg 802>;
2290 status = "disabled"; 2298 status = "disabled";
2291 }; 2299 };
2292 2300
2293 audma0: dma-controller@ec7000 2301 audma0: dma-controller@ec700000 {
2294 compatible = "renesas 2302 compatible = "renesas,dmac-r8a7796",
2295 "renesas 2303 "renesas,rcar-dmac";
2296 reg = <0 0xec700000 0 2304 reg = <0 0xec700000 0 0x10000>;
2297 interrupts = <GIC_SPI 2305 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
2298 <GIC_SPI 2306 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
2299 <GIC_SPI 2307 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
2300 <GIC_SPI 2308 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
2301 <GIC_SPI 2309 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
2302 <GIC_SPI 2310 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
2303 <GIC_SPI 2311 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
2304 <GIC_SPI 2312 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
2305 <GIC_SPI 2313 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
2306 <GIC_SPI 2314 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
2307 <GIC_SPI 2315 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
2308 <GIC_SPI 2316 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
2309 <GIC_SPI 2317 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
2310 <GIC_SPI 2318 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
2311 <GIC_SPI 2319 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
2312 <GIC_SPI 2320 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
2313 <GIC_SPI 2321 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
2314 interrupt-names = "er 2322 interrupt-names = "error",
2315 "ch0" 2323 "ch0", "ch1", "ch2", "ch3",
2316 "ch4" 2324 "ch4", "ch5", "ch6", "ch7",
2317 "ch8" 2325 "ch8", "ch9", "ch10", "ch11",
2318 "ch12 2326 "ch12", "ch13", "ch14", "ch15";
2319 clocks = <&cpg CPG_MO 2327 clocks = <&cpg CPG_MOD 502>;
2320 clock-names = "fck"; 2328 clock-names = "fck";
2321 power-domains = <&sys 2329 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2322 resets = <&cpg 502>; 2330 resets = <&cpg 502>;
2323 #dma-cells = <1>; 2331 #dma-cells = <1>;
2324 dma-channels = <16>; 2332 dma-channels = <16>;
2325 iommus = <&ipmmu_mp 0 2333 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
2326 <&ipmmu_mp 2>, 2334 <&ipmmu_mp 2>, <&ipmmu_mp 3>,
2327 <&ipmmu_mp 4>, 2335 <&ipmmu_mp 4>, <&ipmmu_mp 5>,
2328 <&ipmmu_mp 6>, 2336 <&ipmmu_mp 6>, <&ipmmu_mp 7>,
2329 <&ipmmu_mp 8>, 2337 <&ipmmu_mp 8>, <&ipmmu_mp 9>,
2330 <&ipmmu_mp 10> 2338 <&ipmmu_mp 10>, <&ipmmu_mp 11>,
2331 <&ipmmu_mp 12> 2339 <&ipmmu_mp 12>, <&ipmmu_mp 13>,
2332 <&ipmmu_mp 14> 2340 <&ipmmu_mp 14>, <&ipmmu_mp 15>;
2333 }; 2341 };
2334 2342
2335 audma1: dma-controller@ec7200 2343 audma1: dma-controller@ec720000 {
2336 compatible = "renesas 2344 compatible = "renesas,dmac-r8a7796",
2337 "renesas 2345 "renesas,rcar-dmac";
2338 reg = <0 0xec720000 0 2346 reg = <0 0xec720000 0 0x10000>;
2339 interrupts = <GIC_SPI 2347 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
2340 <GIC_SPI 2348 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
2341 <GIC_SPI 2349 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
2342 <GIC_SPI 2350 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
2343 <GIC_SPI 2351 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
2344 <GIC_SPI 2352 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
2345 <GIC_SPI 2353 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
2346 <GIC_SPI 2354 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
2347 <GIC_SPI 2355 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
2348 <GIC_SPI 2356 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
2349 <GIC_SPI 2357 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
2350 <GIC_SPI 2358 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
2351 <GIC_SPI 2359 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
2352 <GIC_SPI 2360 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
2353 <GIC_SPI 2361 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
2354 <GIC_SPI 2362 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
2355 <GIC_SPI 2363 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
2356 interrupt-names = "er 2364 interrupt-names = "error",
2357 "ch0" 2365 "ch0", "ch1", "ch2", "ch3",
2358 "ch4" 2366 "ch4", "ch5", "ch6", "ch7",
2359 "ch8" 2367 "ch8", "ch9", "ch10", "ch11",
2360 "ch12 2368 "ch12", "ch13", "ch14", "ch15";
2361 clocks = <&cpg CPG_MO 2369 clocks = <&cpg CPG_MOD 501>;
2362 clock-names = "fck"; 2370 clock-names = "fck";
2363 power-domains = <&sys 2371 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2364 resets = <&cpg 501>; 2372 resets = <&cpg 501>;
2365 #dma-cells = <1>; 2373 #dma-cells = <1>;
2366 dma-channels = <16>; 2374 dma-channels = <16>;
2367 iommus = <&ipmmu_mp 1 2375 iommus = <&ipmmu_mp 16>, <&ipmmu_mp 17>,
2368 <&ipmmu_mp 18> 2376 <&ipmmu_mp 18>, <&ipmmu_mp 19>,
2369 <&ipmmu_mp 20> 2377 <&ipmmu_mp 20>, <&ipmmu_mp 21>,
2370 <&ipmmu_mp 22> 2378 <&ipmmu_mp 22>, <&ipmmu_mp 23>,
2371 <&ipmmu_mp 24> 2379 <&ipmmu_mp 24>, <&ipmmu_mp 25>,
2372 <&ipmmu_mp 26> 2380 <&ipmmu_mp 26>, <&ipmmu_mp 27>,
2373 <&ipmmu_mp 28> 2381 <&ipmmu_mp 28>, <&ipmmu_mp 29>,
2374 <&ipmmu_mp 30> 2382 <&ipmmu_mp 30>, <&ipmmu_mp 31>;
2375 }; 2383 };
2376 2384
2377 xhci0: usb@ee000000 { 2385 xhci0: usb@ee000000 {
2378 compatible = "renesas 2386 compatible = "renesas,xhci-r8a7796",
2379 "renesas 2387 "renesas,rcar-gen3-xhci";
2380 reg = <0 0xee000000 0 2388 reg = <0 0xee000000 0 0xc00>;
2381 interrupts = <GIC_SPI 2389 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
2382 clocks = <&cpg CPG_MO 2390 clocks = <&cpg CPG_MOD 328>;
2383 power-domains = <&sys 2391 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2384 resets = <&cpg 328>; 2392 resets = <&cpg 328>;
2385 status = "disabled"; 2393 status = "disabled";
2386 }; 2394 };
2387 2395
2388 usb3_peri0: usb@ee020000 { 2396 usb3_peri0: usb@ee020000 {
2389 compatible = "renesas 2397 compatible = "renesas,r8a7796-usb3-peri",
2390 "renesas 2398 "renesas,rcar-gen3-usb3-peri";
2391 reg = <0 0xee020000 0 2399 reg = <0 0xee020000 0 0x400>;
2392 interrupts = <GIC_SPI 2400 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
2393 clocks = <&cpg CPG_MO 2401 clocks = <&cpg CPG_MOD 328>;
2394 power-domains = <&sys 2402 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2395 resets = <&cpg 328>; 2403 resets = <&cpg 328>;
2396 status = "disabled"; 2404 status = "disabled";
2397 }; 2405 };
2398 2406
2399 ohci0: usb@ee080000 { 2407 ohci0: usb@ee080000 {
2400 compatible = "generic 2408 compatible = "generic-ohci";
2401 reg = <0 0xee080000 0 2409 reg = <0 0xee080000 0 0x100>;
2402 interrupts = <GIC_SPI 2410 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
2403 clocks = <&cpg CPG_MO 2411 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
2404 phys = <&usb2_phy0 1> 2412 phys = <&usb2_phy0 1>;
2405 phy-names = "usb"; 2413 phy-names = "usb";
2406 power-domains = <&sys 2414 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2407 resets = <&cpg 703>, 2415 resets = <&cpg 703>, <&cpg 704>;
2408 status = "disabled"; 2416 status = "disabled";
2409 }; 2417 };
2410 2418
2411 ohci1: usb@ee0a0000 { 2419 ohci1: usb@ee0a0000 {
2412 compatible = "generic 2420 compatible = "generic-ohci";
2413 reg = <0 0xee0a0000 0 2421 reg = <0 0xee0a0000 0 0x100>;
2414 interrupts = <GIC_SPI 2422 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
2415 clocks = <&cpg CPG_MO 2423 clocks = <&cpg CPG_MOD 702>;
2416 phys = <&usb2_phy1 1> 2424 phys = <&usb2_phy1 1>;
2417 phy-names = "usb"; 2425 phy-names = "usb";
2418 power-domains = <&sys 2426 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2419 resets = <&cpg 702>; 2427 resets = <&cpg 702>;
2420 status = "disabled"; 2428 status = "disabled";
2421 }; 2429 };
2422 2430
2423 ehci0: usb@ee080100 { 2431 ehci0: usb@ee080100 {
2424 compatible = "generic 2432 compatible = "generic-ehci";
2425 reg = <0 0xee080100 0 2433 reg = <0 0xee080100 0 0x100>;
2426 interrupts = <GIC_SPI 2434 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
2427 clocks = <&cpg CPG_MO 2435 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
2428 phys = <&usb2_phy0 2> 2436 phys = <&usb2_phy0 2>;
2429 phy-names = "usb"; 2437 phy-names = "usb";
2430 companion = <&ohci0>; 2438 companion = <&ohci0>;
2431 power-domains = <&sys 2439 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2432 resets = <&cpg 703>, 2440 resets = <&cpg 703>, <&cpg 704>;
2433 status = "disabled"; 2441 status = "disabled";
2434 }; 2442 };
2435 2443
2436 ehci1: usb@ee0a0100 { 2444 ehci1: usb@ee0a0100 {
2437 compatible = "generic 2445 compatible = "generic-ehci";
2438 reg = <0 0xee0a0100 0 2446 reg = <0 0xee0a0100 0 0x100>;
2439 interrupts = <GIC_SPI 2447 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
2440 clocks = <&cpg CPG_MO 2448 clocks = <&cpg CPG_MOD 702>;
2441 phys = <&usb2_phy1 2> 2449 phys = <&usb2_phy1 2>;
2442 phy-names = "usb"; 2450 phy-names = "usb";
2443 companion = <&ohci1>; 2451 companion = <&ohci1>;
2444 power-domains = <&sys 2452 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2445 resets = <&cpg 702>; 2453 resets = <&cpg 702>;
2446 status = "disabled"; 2454 status = "disabled";
2447 }; 2455 };
2448 2456
2449 usb2_phy0: usb-phy@ee080200 { 2457 usb2_phy0: usb-phy@ee080200 {
2450 compatible = "renesas 2458 compatible = "renesas,usb2-phy-r8a7796",
2451 "renesas 2459 "renesas,rcar-gen3-usb2-phy";
2452 reg = <0 0xee080200 0 2460 reg = <0 0xee080200 0 0x700>;
2453 interrupts = <GIC_SPI 2461 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
2454 clocks = <&cpg CPG_MO 2462 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
2455 power-domains = <&sys 2463 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2456 resets = <&cpg 703>, 2464 resets = <&cpg 703>, <&cpg 704>;
2457 #phy-cells = <1>; 2465 #phy-cells = <1>;
2458 status = "disabled"; 2466 status = "disabled";
2459 }; 2467 };
2460 2468
2461 usb2_phy1: usb-phy@ee0a0200 { 2469 usb2_phy1: usb-phy@ee0a0200 {
2462 compatible = "renesas 2470 compatible = "renesas,usb2-phy-r8a7796",
2463 "renesas 2471 "renesas,rcar-gen3-usb2-phy";
2464 reg = <0 0xee0a0200 0 2472 reg = <0 0xee0a0200 0 0x700>;
2465 clocks = <&cpg CPG_MO 2473 clocks = <&cpg CPG_MOD 702>;
2466 power-domains = <&sys 2474 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2467 resets = <&cpg 702>; 2475 resets = <&cpg 702>;
2468 #phy-cells = <1>; 2476 #phy-cells = <1>;
2469 status = "disabled"; 2477 status = "disabled";
2470 }; 2478 };
2471 2479
2472 sdhi0: mmc@ee100000 { 2480 sdhi0: mmc@ee100000 {
2473 compatible = "renesas 2481 compatible = "renesas,sdhi-r8a7796",
2474 "renesas 2482 "renesas,rcar-gen3-sdhi";
2475 reg = <0 0xee100000 0 2483 reg = <0 0xee100000 0 0x2000>;
2476 interrupts = <GIC_SPI 2484 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
2477 clocks = <&cpg CPG_MO 2485 clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A7796_CLK_SD0H>;
2478 clock-names = "core", 2486 clock-names = "core", "clkh";
2479 max-frequency = <2000 2487 max-frequency = <200000000>;
2480 power-domains = <&sys 2488 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2481 resets = <&cpg 314>; 2489 resets = <&cpg 314>;
2482 iommus = <&ipmmu_ds1 2490 iommus = <&ipmmu_ds1 32>;
2483 status = "disabled"; 2491 status = "disabled";
2484 }; 2492 };
2485 2493
2486 sdhi1: mmc@ee120000 { 2494 sdhi1: mmc@ee120000 {
2487 compatible = "renesas 2495 compatible = "renesas,sdhi-r8a7796",
2488 "renesas 2496 "renesas,rcar-gen3-sdhi";
2489 reg = <0 0xee120000 0 2497 reg = <0 0xee120000 0 0x2000>;
2490 interrupts = <GIC_SPI 2498 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
2491 clocks = <&cpg CPG_MO 2499 clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A7796_CLK_SD1H>;
2492 clock-names = "core", 2500 clock-names = "core", "clkh";
2493 max-frequency = <2000 2501 max-frequency = <200000000>;
2494 power-domains = <&sys 2502 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2495 resets = <&cpg 313>; 2503 resets = <&cpg 313>;
2496 iommus = <&ipmmu_ds1 2504 iommus = <&ipmmu_ds1 33>;
2497 status = "disabled"; 2505 status = "disabled";
2498 }; 2506 };
2499 2507
2500 sdhi2: mmc@ee140000 { 2508 sdhi2: mmc@ee140000 {
2501 compatible = "renesas 2509 compatible = "renesas,sdhi-r8a7796",
2502 "renesas 2510 "renesas,rcar-gen3-sdhi";
2503 reg = <0 0xee140000 0 2511 reg = <0 0xee140000 0 0x2000>;
2504 interrupts = <GIC_SPI 2512 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
2505 clocks = <&cpg CPG_MO 2513 clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A7796_CLK_SD2H>;
2506 clock-names = "core", 2514 clock-names = "core", "clkh";
2507 max-frequency = <2000 2515 max-frequency = <200000000>;
2508 power-domains = <&sys 2516 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2509 resets = <&cpg 312>; 2517 resets = <&cpg 312>;
2510 iommus = <&ipmmu_ds1 2518 iommus = <&ipmmu_ds1 34>;
2511 status = "disabled"; 2519 status = "disabled";
2512 }; 2520 };
2513 2521
2514 sdhi3: mmc@ee160000 { 2522 sdhi3: mmc@ee160000 {
2515 compatible = "renesas 2523 compatible = "renesas,sdhi-r8a7796",
2516 "renesas 2524 "renesas,rcar-gen3-sdhi";
2517 reg = <0 0xee160000 0 2525 reg = <0 0xee160000 0 0x2000>;
2518 interrupts = <GIC_SPI 2526 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
2519 clocks = <&cpg CPG_MO 2527 clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A7796_CLK_SD3H>;
2520 clock-names = "core", 2528 clock-names = "core", "clkh";
2521 max-frequency = <2000 2529 max-frequency = <200000000>;
2522 power-domains = <&sys 2530 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2523 resets = <&cpg 311>; 2531 resets = <&cpg 311>;
2524 iommus = <&ipmmu_ds1 2532 iommus = <&ipmmu_ds1 35>;
2525 status = "disabled"; 2533 status = "disabled";
2526 }; 2534 };
2527 2535
2528 rpc: spi@ee200000 { 2536 rpc: spi@ee200000 {
2529 compatible = "renesas 2537 compatible = "renesas,r8a7796-rpc-if",
2530 "renesas 2538 "renesas,rcar-gen3-rpc-if";
2531 reg = <0 0xee200000 0 2539 reg = <0 0xee200000 0 0x200>,
2532 <0 0x08000000 0 2540 <0 0x08000000 0 0x04000000>,
2533 <0 0xee208000 0 2541 <0 0xee208000 0 0x100>;
2534 reg-names = "regs", " 2542 reg-names = "regs", "dirmap", "wbuf";
2535 interrupts = <GIC_SPI 2543 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
2536 clocks = <&cpg CPG_MO 2544 clocks = <&cpg CPG_MOD 917>;
2537 power-domains = <&sys 2545 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2538 resets = <&cpg 917>; 2546 resets = <&cpg 917>;
2539 #address-cells = <1>; 2547 #address-cells = <1>;
2540 #size-cells = <0>; 2548 #size-cells = <0>;
2541 status = "disabled"; 2549 status = "disabled";
2542 }; 2550 };
2543 2551
2544 gic: interrupt-controller@f10 2552 gic: interrupt-controller@f1010000 {
2545 compatible = "arm,gic 2553 compatible = "arm,gic-400";
2546 #interrupt-cells = <3 2554 #interrupt-cells = <3>;
2547 #address-cells = <0>; 2555 #address-cells = <0>;
2548 interrupt-controller; 2556 interrupt-controller;
2549 reg = <0x0 0xf1010000 2557 reg = <0x0 0xf1010000 0 0x1000>,
2550 <0x0 0xf1020000 2558 <0x0 0xf1020000 0 0x20000>,
2551 <0x0 0xf1040000 2559 <0x0 0xf1040000 0 0x20000>,
2552 <0x0 0xf1060000 2560 <0x0 0xf1060000 0 0x20000>;
2553 interrupts = <GIC_PPI 2561 interrupts = <GIC_PPI 9
2554 (GIC_ 2562 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
2555 clocks = <&cpg CPG_MO 2563 clocks = <&cpg CPG_MOD 408>;
2556 clock-names = "clk"; 2564 clock-names = "clk";
2557 power-domains = <&sys 2565 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2558 resets = <&cpg 408>; 2566 resets = <&cpg 408>;
2559 }; 2567 };
2560 2568
2561 pciec0: pcie@fe000000 { 2569 pciec0: pcie@fe000000 {
2562 compatible = "renesas 2570 compatible = "renesas,pcie-r8a7796",
2563 "renesas 2571 "renesas,pcie-rcar-gen3";
2564 reg = <0 0xfe000000 0 2572 reg = <0 0xfe000000 0 0x80000>;
2565 #address-cells = <3>; 2573 #address-cells = <3>;
2566 #size-cells = <2>; 2574 #size-cells = <2>;
2567 bus-range = <0x00 0xf 2575 bus-range = <0x00 0xff>;
2568 device_type = "pci"; 2576 device_type = "pci";
2569 ranges = <0x01000000 2577 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
2570 <0x02000000 2578 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
2571 <0x02000000 2579 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
2572 <0x42000000 2580 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
2573 /* Map all possible D !! 2581 /* Map all possible DDR as inbound ranges */
2574 dma-ranges = <0x42000 !! 2582 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
2575 interrupts = <GIC_SPI 2583 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
2576 <GIC_SPI 117 2584 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
2577 <GIC_SPI 118 2585 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
2578 #interrupt-cells = <1 2586 #interrupt-cells = <1>;
2579 interrupt-map-mask = 2587 interrupt-map-mask = <0 0 0 0>;
2580 interrupt-map = <0 0 2588 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
2581 clocks = <&cpg CPG_MO 2589 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
2582 clock-names = "pcie", 2590 clock-names = "pcie", "pcie_bus";
2583 power-domains = <&sys 2591 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2584 resets = <&cpg 319>; 2592 resets = <&cpg 319>;
2585 iommu-map = <0 &ipmmu <<
2586 iommu-map-mask = <0>; <<
2587 status = "disabled"; 2593 status = "disabled";
2588 }; 2594 };
2589 2595
2590 pciec1: pcie@ee800000 { 2596 pciec1: pcie@ee800000 {
2591 compatible = "renesas 2597 compatible = "renesas,pcie-r8a7796",
2592 "renesas 2598 "renesas,pcie-rcar-gen3";
2593 reg = <0 0xee800000 0 2599 reg = <0 0xee800000 0 0x80000>;
2594 #address-cells = <3>; 2600 #address-cells = <3>;
2595 #size-cells = <2>; 2601 #size-cells = <2>;
2596 bus-range = <0x00 0xf 2602 bus-range = <0x00 0xff>;
2597 device_type = "pci"; 2603 device_type = "pci";
2598 ranges = <0x01000000 2604 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
2599 <0x02000000 2605 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
2600 <0x02000000 2606 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
2601 <0x42000000 2607 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
2602 /* Map all possible D !! 2608 /* Map all possible DDR as inbound ranges */
2603 dma-ranges = <0x42000 !! 2609 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
2604 interrupts = <GIC_SPI 2610 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
2605 <GIC_SPI 149 2611 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
2606 <GIC_SPI 150 2612 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
2607 #interrupt-cells = <1 2613 #interrupt-cells = <1>;
2608 interrupt-map-mask = 2614 interrupt-map-mask = <0 0 0 0>;
2609 interrupt-map = <0 0 2615 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2610 clocks = <&cpg CPG_MO 2616 clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>;
2611 clock-names = "pcie", 2617 clock-names = "pcie", "pcie_bus";
2612 power-domains = <&sys 2618 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2613 resets = <&cpg 318>; 2619 resets = <&cpg 318>;
2614 iommu-map = <0 &ipmmu <<
2615 iommu-map-mask = <0>; <<
2616 status = "disabled"; 2620 status = "disabled";
2617 }; 2621 };
2618 2622
2619 imr-lx4@fe860000 { 2623 imr-lx4@fe860000 {
2620 compatible = "renesas 2624 compatible = "renesas,r8a7796-imr-lx4",
2621 "renesas 2625 "renesas,imr-lx4";
2622 reg = <0 0xfe860000 0 2626 reg = <0 0xfe860000 0 0x2000>;
2623 interrupts = <GIC_SPI 2627 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
2624 clocks = <&cpg CPG_MO 2628 clocks = <&cpg CPG_MOD 823>;
2625 power-domains = <&sys 2629 power-domains = <&sysc R8A7796_PD_A3VC>;
2626 resets = <&cpg 823>; 2630 resets = <&cpg 823>;
2627 }; 2631 };
2628 2632
2629 imr-lx4@fe870000 { 2633 imr-lx4@fe870000 {
2630 compatible = "renesas 2634 compatible = "renesas,r8a7796-imr-lx4",
2631 "renesas 2635 "renesas,imr-lx4";
2632 reg = <0 0xfe870000 0 2636 reg = <0 0xfe870000 0 0x2000>;
2633 interrupts = <GIC_SPI 2637 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
2634 clocks = <&cpg CPG_MO 2638 clocks = <&cpg CPG_MOD 822>;
2635 power-domains = <&sys 2639 power-domains = <&sysc R8A7796_PD_A3VC>;
2636 resets = <&cpg 822>; 2640 resets = <&cpg 822>;
2637 }; 2641 };
2638 2642
2639 fdp1@fe940000 { 2643 fdp1@fe940000 {
2640 compatible = "renesas 2644 compatible = "renesas,fdp1";
2641 reg = <0 0xfe940000 0 2645 reg = <0 0xfe940000 0 0x2400>;
2642 interrupts = <GIC_SPI 2646 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
2643 clocks = <&cpg CPG_MO 2647 clocks = <&cpg CPG_MOD 119>;
2644 power-domains = <&sys 2648 power-domains = <&sysc R8A7796_PD_A3VC>;
2645 resets = <&cpg 119>; 2649 resets = <&cpg 119>;
2646 renesas,fcp = <&fcpf0 2650 renesas,fcp = <&fcpf0>;
2647 }; 2651 };
2648 2652
2649 fcpf0: fcp@fe950000 { 2653 fcpf0: fcp@fe950000 {
2650 compatible = "renesas 2654 compatible = "renesas,fcpf";
2651 reg = <0 0xfe950000 0 2655 reg = <0 0xfe950000 0 0x200>;
2652 clocks = <&cpg CPG_MO 2656 clocks = <&cpg CPG_MOD 615>;
2653 power-domains = <&sys 2657 power-domains = <&sysc R8A7796_PD_A3VC>;
2654 resets = <&cpg 615>; 2658 resets = <&cpg 615>;
2655 iommus = <&ipmmu_vc0 <<
2656 }; 2659 };
2657 2660
2658 fcpvb0: fcp@fe96f000 { 2661 fcpvb0: fcp@fe96f000 {
2659 compatible = "renesas 2662 compatible = "renesas,fcpv";
2660 reg = <0 0xfe96f000 0 2663 reg = <0 0xfe96f000 0 0x200>;
2661 clocks = <&cpg CPG_MO 2664 clocks = <&cpg CPG_MOD 607>;
2662 power-domains = <&sys 2665 power-domains = <&sysc R8A7796_PD_A3VC>;
2663 resets = <&cpg 607>; 2666 resets = <&cpg 607>;
2664 iommus = <&ipmmu_vi0 <<
2665 }; 2667 };
2666 2668
2667 fcpvi0: fcp@fe9af000 { 2669 fcpvi0: fcp@fe9af000 {
2668 compatible = "renesas 2670 compatible = "renesas,fcpv";
2669 reg = <0 0xfe9af000 0 2671 reg = <0 0xfe9af000 0 0x200>;
2670 clocks = <&cpg CPG_MO 2672 clocks = <&cpg CPG_MOD 611>;
2671 power-domains = <&sys 2673 power-domains = <&sysc R8A7796_PD_A3VC>;
2672 resets = <&cpg 611>; 2674 resets = <&cpg 611>;
2673 iommus = <&ipmmu_vc0 2675 iommus = <&ipmmu_vc0 19>;
2674 }; 2676 };
2675 2677
2676 fcpvd0: fcp@fea27000 { 2678 fcpvd0: fcp@fea27000 {
2677 compatible = "renesas 2679 compatible = "renesas,fcpv";
2678 reg = <0 0xfea27000 0 2680 reg = <0 0xfea27000 0 0x200>;
2679 clocks = <&cpg CPG_MO 2681 clocks = <&cpg CPG_MOD 603>;
2680 power-domains = <&sys 2682 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2681 resets = <&cpg 603>; 2683 resets = <&cpg 603>;
2682 iommus = <&ipmmu_vi0 2684 iommus = <&ipmmu_vi0 8>;
2683 }; 2685 };
2684 2686
2685 fcpvd1: fcp@fea2f000 { 2687 fcpvd1: fcp@fea2f000 {
2686 compatible = "renesas 2688 compatible = "renesas,fcpv";
2687 reg = <0 0xfea2f000 0 2689 reg = <0 0xfea2f000 0 0x200>;
2688 clocks = <&cpg CPG_MO 2690 clocks = <&cpg CPG_MOD 602>;
2689 power-domains = <&sys 2691 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2690 resets = <&cpg 602>; 2692 resets = <&cpg 602>;
2691 iommus = <&ipmmu_vi0 2693 iommus = <&ipmmu_vi0 9>;
2692 }; 2694 };
2693 2695
2694 fcpvd2: fcp@fea37000 { 2696 fcpvd2: fcp@fea37000 {
2695 compatible = "renesas 2697 compatible = "renesas,fcpv";
2696 reg = <0 0xfea37000 0 2698 reg = <0 0xfea37000 0 0x200>;
2697 clocks = <&cpg CPG_MO 2699 clocks = <&cpg CPG_MOD 601>;
2698 power-domains = <&sys 2700 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2699 resets = <&cpg 601>; 2701 resets = <&cpg 601>;
2700 iommus = <&ipmmu_vi0 2702 iommus = <&ipmmu_vi0 10>;
2701 }; 2703 };
2702 2704
2703 vspb: vsp@fe960000 { 2705 vspb: vsp@fe960000 {
2704 compatible = "renesas 2706 compatible = "renesas,vsp2";
2705 reg = <0 0xfe960000 0 2707 reg = <0 0xfe960000 0 0x8000>;
2706 interrupts = <GIC_SPI 2708 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
2707 clocks = <&cpg CPG_MO 2709 clocks = <&cpg CPG_MOD 626>;
2708 power-domains = <&sys 2710 power-domains = <&sysc R8A7796_PD_A3VC>;
2709 resets = <&cpg 626>; 2711 resets = <&cpg 626>;
2710 2712
2711 renesas,fcp = <&fcpvb 2713 renesas,fcp = <&fcpvb0>;
2712 }; 2714 };
2713 2715
2714 vspd0: vsp@fea20000 { 2716 vspd0: vsp@fea20000 {
2715 compatible = "renesas 2717 compatible = "renesas,vsp2";
2716 reg = <0 0xfea20000 0 2718 reg = <0 0xfea20000 0 0x5000>;
2717 interrupts = <GIC_SPI 2719 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
2718 clocks = <&cpg CPG_MO 2720 clocks = <&cpg CPG_MOD 623>;
2719 power-domains = <&sys 2721 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2720 resets = <&cpg 623>; 2722 resets = <&cpg 623>;
2721 2723
2722 renesas,fcp = <&fcpvd 2724 renesas,fcp = <&fcpvd0>;
2723 }; 2725 };
2724 2726
2725 vspd1: vsp@fea28000 { 2727 vspd1: vsp@fea28000 {
2726 compatible = "renesas 2728 compatible = "renesas,vsp2";
2727 reg = <0 0xfea28000 0 2729 reg = <0 0xfea28000 0 0x5000>;
2728 interrupts = <GIC_SPI 2730 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
2729 clocks = <&cpg CPG_MO 2731 clocks = <&cpg CPG_MOD 622>;
2730 power-domains = <&sys 2732 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2731 resets = <&cpg 622>; 2733 resets = <&cpg 622>;
2732 2734
2733 renesas,fcp = <&fcpvd 2735 renesas,fcp = <&fcpvd1>;
2734 }; 2736 };
2735 2737
2736 vspd2: vsp@fea30000 { 2738 vspd2: vsp@fea30000 {
2737 compatible = "renesas 2739 compatible = "renesas,vsp2";
2738 reg = <0 0xfea30000 0 2740 reg = <0 0xfea30000 0 0x5000>;
2739 interrupts = <GIC_SPI 2741 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
2740 clocks = <&cpg CPG_MO 2742 clocks = <&cpg CPG_MOD 621>;
2741 power-domains = <&sys 2743 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2742 resets = <&cpg 621>; 2744 resets = <&cpg 621>;
2743 2745
2744 renesas,fcp = <&fcpvd 2746 renesas,fcp = <&fcpvd2>;
2745 }; 2747 };
2746 2748
2747 vspi0: vsp@fe9a0000 { 2749 vspi0: vsp@fe9a0000 {
2748 compatible = "renesas 2750 compatible = "renesas,vsp2";
2749 reg = <0 0xfe9a0000 0 2751 reg = <0 0xfe9a0000 0 0x8000>;
2750 interrupts = <GIC_SPI 2752 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
2751 clocks = <&cpg CPG_MO 2753 clocks = <&cpg CPG_MOD 631>;
2752 power-domains = <&sys 2754 power-domains = <&sysc R8A7796_PD_A3VC>;
2753 resets = <&cpg 631>; 2755 resets = <&cpg 631>;
2754 2756
2755 renesas,fcp = <&fcpvi 2757 renesas,fcp = <&fcpvi0>;
2756 }; 2758 };
2757 2759
2758 cmm0: cmm@fea40000 { 2760 cmm0: cmm@fea40000 {
2759 compatible = "renesas 2761 compatible = "renesas,r8a7796-cmm",
2760 "renesas 2762 "renesas,rcar-gen3-cmm";
2761 reg = <0 0xfea40000 0 2763 reg = <0 0xfea40000 0 0x1000>;
2762 power-domains = <&sys 2764 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2763 clocks = <&cpg CPG_MO 2765 clocks = <&cpg CPG_MOD 711>;
2764 resets = <&cpg 711>; 2766 resets = <&cpg 711>;
2765 }; 2767 };
2766 2768
2767 cmm1: cmm@fea50000 { 2769 cmm1: cmm@fea50000 {
2768 compatible = "renesas 2770 compatible = "renesas,r8a7796-cmm",
2769 "renesas 2771 "renesas,rcar-gen3-cmm";
2770 reg = <0 0xfea50000 0 2772 reg = <0 0xfea50000 0 0x1000>;
2771 power-domains = <&sys 2773 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2772 clocks = <&cpg CPG_MO 2774 clocks = <&cpg CPG_MOD 710>;
2773 resets = <&cpg 710>; 2775 resets = <&cpg 710>;
2774 }; 2776 };
2775 2777
2776 cmm2: cmm@fea60000 { 2778 cmm2: cmm@fea60000 {
2777 compatible = "renesas 2779 compatible = "renesas,r8a7796-cmm",
2778 "renesas 2780 "renesas,rcar-gen3-cmm";
2779 reg = <0 0xfea60000 0 2781 reg = <0 0xfea60000 0 0x1000>;
2780 power-domains = <&sys 2782 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2781 clocks = <&cpg CPG_MO 2783 clocks = <&cpg CPG_MOD 709>;
2782 resets = <&cpg 709>; 2784 resets = <&cpg 709>;
2783 }; 2785 };
2784 2786
2785 csi20: csi2@fea80000 { 2787 csi20: csi2@fea80000 {
2786 compatible = "renesas 2788 compatible = "renesas,r8a7796-csi2";
2787 reg = <0 0xfea80000 0 2789 reg = <0 0xfea80000 0 0x10000>;
2788 interrupts = <GIC_SPI 2790 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
2789 clocks = <&cpg CPG_MO 2791 clocks = <&cpg CPG_MOD 714>;
2790 power-domains = <&sys 2792 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2791 resets = <&cpg 714>; 2793 resets = <&cpg 714>;
2792 status = "disabled"; 2794 status = "disabled";
2793 2795
2794 ports { 2796 ports {
2795 #address-cell 2797 #address-cells = <1>;
2796 #size-cells = 2798 #size-cells = <0>;
2797 2799
2798 port@0 { 2800 port@0 {
2799 reg = 2801 reg = <0>;
2800 }; 2802 };
2801 2803
2802 port@1 { 2804 port@1 {
2803 #addr 2805 #address-cells = <1>;
2804 #size 2806 #size-cells = <0>;
2805 2807
2806 reg = 2808 reg = <1>;
2807 2809
2808 csi20 2810 csi20vin0: endpoint@0 {
2809 2811 reg = <0>;
2810 2812 remote-endpoint = <&vin0csi20>;
2811 }; 2813 };
2812 csi20 2814 csi20vin1: endpoint@1 {
2813 2815 reg = <1>;
2814 2816 remote-endpoint = <&vin1csi20>;
2815 }; 2817 };
2816 csi20 2818 csi20vin2: endpoint@2 {
2817 2819 reg = <2>;
2818 2820 remote-endpoint = <&vin2csi20>;
2819 }; 2821 };
2820 csi20 2822 csi20vin3: endpoint@3 {
2821 2823 reg = <3>;
2822 2824 remote-endpoint = <&vin3csi20>;
2823 }; 2825 };
2824 csi20 2826 csi20vin4: endpoint@4 {
2825 2827 reg = <4>;
2826 2828 remote-endpoint = <&vin4csi20>;
2827 }; 2829 };
2828 csi20 2830 csi20vin5: endpoint@5 {
2829 2831 reg = <5>;
2830 2832 remote-endpoint = <&vin5csi20>;
2831 }; 2833 };
2832 csi20 2834 csi20vin6: endpoint@6 {
2833 2835 reg = <6>;
2834 2836 remote-endpoint = <&vin6csi20>;
2835 }; 2837 };
2836 csi20 2838 csi20vin7: endpoint@7 {
2837 2839 reg = <7>;
2838 2840 remote-endpoint = <&vin7csi20>;
2839 }; 2841 };
2840 }; 2842 };
2841 }; 2843 };
2842 }; 2844 };
2843 2845
2844 csi40: csi2@feaa0000 { 2846 csi40: csi2@feaa0000 {
2845 compatible = "renesas 2847 compatible = "renesas,r8a7796-csi2";
2846 reg = <0 0xfeaa0000 0 2848 reg = <0 0xfeaa0000 0 0x10000>;
2847 interrupts = <GIC_SPI 2849 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
2848 clocks = <&cpg CPG_MO 2850 clocks = <&cpg CPG_MOD 716>;
2849 power-domains = <&sys 2851 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2850 resets = <&cpg 716>; 2852 resets = <&cpg 716>;
2851 status = "disabled"; 2853 status = "disabled";
2852 2854
2853 ports { 2855 ports {
2854 #address-cell 2856 #address-cells = <1>;
2855 #size-cells = 2857 #size-cells = <0>;
2856 2858
2857 port@0 { 2859 port@0 {
2858 reg = 2860 reg = <0>;
2859 }; 2861 };
2860 2862
2861 port@1 { 2863 port@1 {
2862 #addr 2864 #address-cells = <1>;
2863 #size 2865 #size-cells = <0>;
2864 2866
2865 reg = 2867 reg = <1>;
2866 2868
2867 csi40 2869 csi40vin0: endpoint@0 {
2868 2870 reg = <0>;
2869 2871 remote-endpoint = <&vin0csi40>;
2870 }; 2872 };
2871 csi40 2873 csi40vin1: endpoint@1 {
2872 2874 reg = <1>;
2873 2875 remote-endpoint = <&vin1csi40>;
2874 }; 2876 };
2875 csi40 2877 csi40vin2: endpoint@2 {
2876 2878 reg = <2>;
2877 2879 remote-endpoint = <&vin2csi40>;
2878 }; 2880 };
2879 csi40 2881 csi40vin3: endpoint@3 {
2880 2882 reg = <3>;
2881 2883 remote-endpoint = <&vin3csi40>;
2882 }; 2884 };
2883 csi40 2885 csi40vin4: endpoint@4 {
2884 2886 reg = <4>;
2885 2887 remote-endpoint = <&vin4csi40>;
2886 }; 2888 };
2887 csi40 2889 csi40vin5: endpoint@5 {
2888 2890 reg = <5>;
2889 2891 remote-endpoint = <&vin5csi40>;
2890 }; 2892 };
2891 csi40 2893 csi40vin6: endpoint@6 {
2892 2894 reg = <6>;
2893 2895 remote-endpoint = <&vin6csi40>;
2894 }; 2896 };
2895 csi40 2897 csi40vin7: endpoint@7 {
2896 2898 reg = <7>;
2897 2899 remote-endpoint = <&vin7csi40>;
2898 }; 2900 };
2899 }; 2901 };
2900 2902
2901 }; 2903 };
2902 }; 2904 };
2903 2905
2904 hdmi0: hdmi@fead0000 { 2906 hdmi0: hdmi@fead0000 {
2905 compatible = "renesas 2907 compatible = "renesas,r8a7796-hdmi", "renesas,rcar-gen3-hdmi";
2906 reg = <0 0xfead0000 0 2908 reg = <0 0xfead0000 0 0x10000>;
2907 interrupts = <GIC_SPI 2909 interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
2908 clocks = <&cpg CPG_MO 2910 clocks = <&cpg CPG_MOD 729>, <&cpg CPG_CORE R8A7796_CLK_HDMI>;
2909 clock-names = "iahb", 2911 clock-names = "iahb", "isfr";
2910 power-domains = <&sys 2912 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2911 resets = <&cpg 729>; 2913 resets = <&cpg 729>;
2912 status = "disabled"; 2914 status = "disabled";
2913 2915
2914 ports { 2916 ports {
2915 #address-cell 2917 #address-cells = <1>;
2916 #size-cells = 2918 #size-cells = <0>;
2917 port@0 { 2919 port@0 {
2918 reg = 2920 reg = <0>;
2919 dw_hd 2921 dw_hdmi0_in: endpoint {
2920 2922 remote-endpoint = <&du_out_hdmi0>;
2921 }; 2923 };
2922 }; 2924 };
2923 port@1 { 2925 port@1 {
2924 reg = 2926 reg = <1>;
2925 }; 2927 };
2926 port@2 { 2928 port@2 {
2927 /* HD 2929 /* HDMI sound */
2928 reg = 2930 reg = <2>;
2929 }; 2931 };
2930 }; 2932 };
2931 }; 2933 };
2932 2934
2933 du: display@feb00000 { 2935 du: display@feb00000 {
2934 compatible = "renesas 2936 compatible = "renesas,du-r8a7796";
2935 reg = <0 0xfeb00000 0 2937 reg = <0 0xfeb00000 0 0x70000>;
2936 interrupts = <GIC_SPI 2938 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
2937 <GIC_SPI 2939 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
2938 <GIC_SPI 2940 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
2939 clocks = <&cpg CPG_MO 2941 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
2940 <&cpg CPG_MO 2942 <&cpg CPG_MOD 722>;
2941 clock-names = "du.0", 2943 clock-names = "du.0", "du.1", "du.2";
2942 resets = <&cpg 724>, 2944 resets = <&cpg 724>, <&cpg 722>;
2943 reset-names = "du.0", 2945 reset-names = "du.0", "du.2";
2944 2946
2945 renesas,cmms = <&cmm0 2947 renesas,cmms = <&cmm0>, <&cmm1>, <&cmm2>;
2946 renesas,vsps = <&vspd 2948 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>;
2947 2949
2948 status = "disabled"; 2950 status = "disabled";
2949 2951
2950 ports { 2952 ports {
2951 #address-cell 2953 #address-cells = <1>;
2952 #size-cells = 2954 #size-cells = <0>;
2953 2955
2954 port@0 { 2956 port@0 {
2955 reg = 2957 reg = <0>;
2956 }; 2958 };
2957 port@1 { 2959 port@1 {
2958 reg = 2960 reg = <1>;
2959 du_ou 2961 du_out_hdmi0: endpoint {
2960 2962 remote-endpoint = <&dw_hdmi0_in>;
2961 }; 2963 };
2962 }; 2964 };
2963 port@2 { 2965 port@2 {
2964 reg = 2966 reg = <2>;
2965 du_ou 2967 du_out_lvds0: endpoint {
2966 2968 remote-endpoint = <&lvds0_in>;
2967 }; 2969 };
2968 }; 2970 };
2969 }; 2971 };
2970 }; 2972 };
2971 2973
2972 lvds0: lvds@feb90000 { 2974 lvds0: lvds@feb90000 {
2973 compatible = "renesas 2975 compatible = "renesas,r8a7796-lvds";
2974 reg = <0 0xfeb90000 0 2976 reg = <0 0xfeb90000 0 0x14>;
2975 clocks = <&cpg CPG_MO 2977 clocks = <&cpg CPG_MOD 727>;
2976 power-domains = <&sys 2978 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2977 resets = <&cpg 727>; 2979 resets = <&cpg 727>;
2978 status = "disabled"; 2980 status = "disabled";
2979 2981
2980 ports { 2982 ports {
2981 #address-cell 2983 #address-cells = <1>;
2982 #size-cells = 2984 #size-cells = <0>;
2983 2985
2984 port@0 { 2986 port@0 {
2985 reg = 2987 reg = <0>;
2986 lvds0 2988 lvds0_in: endpoint {
2987 2989 remote-endpoint = <&du_out_lvds0>;
2988 }; 2990 };
2989 }; 2991 };
2990 port@1 { 2992 port@1 {
2991 reg = 2993 reg = <1>;
2992 }; 2994 };
2993 }; 2995 };
2994 }; 2996 };
2995 2997
2996 prr: chipid@fff00044 { 2998 prr: chipid@fff00044 {
2997 compatible = "renesas 2999 compatible = "renesas,prr";
2998 reg = <0 0xfff00044 0 3000 reg = <0 0xfff00044 0 4>;
2999 }; 3001 };
3000 }; 3002 };
3001 3003
3002 thermal-zones { 3004 thermal-zones {
3003 sensor1_thermal: sensor1-ther 3005 sensor1_thermal: sensor1-thermal {
3004 polling-delay-passive 3006 polling-delay-passive = <250>;
3005 polling-delay = <1000 3007 polling-delay = <1000>;
3006 thermal-sensors = <&t 3008 thermal-sensors = <&tsc 0>;
3007 sustainable-power = < 3009 sustainable-power = <3874>;
3008 3010
3009 trips { 3011 trips {
3010 sensor1_crit: 3012 sensor1_crit: sensor1-crit {
3011 tempe 3013 temperature = <120000>;
3012 hyste 3014 hysteresis = <1000>;
3013 type 3015 type = "critical";
3014 }; 3016 };
3015 }; 3017 };
3016 }; 3018 };
3017 3019
3018 sensor2_thermal: sensor2-ther 3020 sensor2_thermal: sensor2-thermal {
3019 polling-delay-passive 3021 polling-delay-passive = <250>;
3020 polling-delay = <1000 3022 polling-delay = <1000>;
3021 thermal-sensors = <&t 3023 thermal-sensors = <&tsc 1>;
3022 sustainable-power = < 3024 sustainable-power = <3874>;
3023 3025
3024 trips { 3026 trips {
3025 sensor2_crit: 3027 sensor2_crit: sensor2-crit {
3026 tempe 3028 temperature = <120000>;
3027 hyste 3029 hysteresis = <1000>;
3028 type 3030 type = "critical";
3029 }; 3031 };
3030 }; 3032 };
3031 }; 3033 };
3032 3034
3033 sensor3_thermal: sensor3-ther 3035 sensor3_thermal: sensor3-thermal {
3034 polling-delay-passive 3036 polling-delay-passive = <250>;
3035 polling-delay = <1000 3037 polling-delay = <1000>;
3036 thermal-sensors = <&t 3038 thermal-sensors = <&tsc 2>;
3037 sustainable-power = < 3039 sustainable-power = <3874>;
3038 3040
3039 cooling-maps { 3041 cooling-maps {
3040 map0 { 3042 map0 {
3041 trip 3043 trip = <&target>;
3042 cooli 3044 cooling-device = <&a57_0 2 4>;
3043 contr 3045 contribution = <1024>;
3044 }; 3046 };
3045 map1 { 3047 map1 {
3046 trip 3048 trip = <&target>;
3047 cooli 3049 cooling-device = <&a53_0 0 2>;
3048 contr 3050 contribution = <1024>;
3049 }; 3051 };
3050 }; 3052 };
3051 trips { 3053 trips {
3052 target: trip- 3054 target: trip-point1 {
3053 tempe 3055 temperature = <100000>;
3054 hyste 3056 hysteresis = <1000>;
3055 type 3057 type = "passive";
3056 }; 3058 };
3057 3059
3058 sensor3_crit: 3060 sensor3_crit: sensor3-crit {
3059 tempe 3061 temperature = <120000>;
3060 hyste 3062 hysteresis = <1000>;
3061 type 3063 type = "critical";
3062 }; 3064 };
3063 }; 3065 };
3064 }; 3066 };
3065 }; 3067 };
3066 3068
3067 timer { 3069 timer {
3068 compatible = "arm,armv8-timer 3070 compatible = "arm,armv8-timer";
3069 interrupts-extended = <&gic G 3071 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
3070 <&gic G 3072 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
3071 <&gic G 3073 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
3072 <&gic G 3074 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
3073 interrupt-names = "sec-phys", <<
3074 }; 3075 };
3075 3076
3076 /* External USB clocks - can be overr 3077 /* External USB clocks - can be overridden by the board */
3077 usb3s0_clk: usb3s0 { 3078 usb3s0_clk: usb3s0 {
3078 compatible = "fixed-clock"; 3079 compatible = "fixed-clock";
3079 #clock-cells = <0>; 3080 #clock-cells = <0>;
3080 clock-frequency = <0>; 3081 clock-frequency = <0>;
3081 }; 3082 };
3082 3083
3083 usb_extal_clk: usb_extal { 3084 usb_extal_clk: usb_extal {
3084 compatible = "fixed-clock"; 3085 compatible = "fixed-clock";
3085 #clock-cells = <0>; 3086 #clock-cells = <0>;
3086 clock-frequency = <0>; 3087 clock-frequency = <0>;
3087 }; 3088 };
3088 }; 3089 };
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