1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * Device Tree Source for the R-Car M3-W (R8A7 3 * Device Tree Source for the R-Car M3-W (R8A77960) SoC
4 * 4 *
5 * Copyright (C) 2016-2017 Renesas Electronics 5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
6 */ 6 */
7 7
8 #include <dt-bindings/clock/r8a7796-cpg-mssr.h 8 #include <dt-bindings/clock/r8a7796-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm 9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a7796-sysc.h> 10 #include <dt-bindings/power/r8a7796-sysc.h>
11 11
>> 12 #define CPG_AUDIO_CLK_I R8A7796_CLK_S0D4
>> 13
12 / { 14 / {
13 compatible = "renesas,r8a7796"; 15 compatible = "renesas,r8a7796";
14 #address-cells = <2>; 16 #address-cells = <2>;
15 #size-cells = <2>; 17 #size-cells = <2>;
16 18
17 /* 19 /*
18 * The external audio clocks are confi 20 * The external audio clocks are configured as 0 Hz fixed frequency
19 * clocks by default. 21 * clocks by default.
20 * Boards that provide audio clocks sh 22 * Boards that provide audio clocks should override them.
21 */ 23 */
22 audio_clk_a: audio_clk_a { 24 audio_clk_a: audio_clk_a {
23 compatible = "fixed-clock"; 25 compatible = "fixed-clock";
24 #clock-cells = <0>; 26 #clock-cells = <0>;
25 clock-frequency = <0>; 27 clock-frequency = <0>;
26 }; 28 };
27 29
28 audio_clk_b: audio_clk_b { 30 audio_clk_b: audio_clk_b {
29 compatible = "fixed-clock"; 31 compatible = "fixed-clock";
30 #clock-cells = <0>; 32 #clock-cells = <0>;
31 clock-frequency = <0>; 33 clock-frequency = <0>;
32 }; 34 };
33 35
34 audio_clk_c: audio_clk_c { 36 audio_clk_c: audio_clk_c {
35 compatible = "fixed-clock"; 37 compatible = "fixed-clock";
36 #clock-cells = <0>; 38 #clock-cells = <0>;
37 clock-frequency = <0>; 39 clock-frequency = <0>;
38 }; 40 };
39 41
40 /* External CAN clock - to be overridd 42 /* External CAN clock - to be overridden by boards that provide it */
41 can_clk: can { 43 can_clk: can {
42 compatible = "fixed-clock"; 44 compatible = "fixed-clock";
43 #clock-cells = <0>; 45 #clock-cells = <0>;
44 clock-frequency = <0>; 46 clock-frequency = <0>;
45 }; 47 };
46 48
47 cluster0_opp: opp-table-0 { 49 cluster0_opp: opp-table-0 {
48 compatible = "operating-points 50 compatible = "operating-points-v2";
49 opp-shared; 51 opp-shared;
50 52
51 opp-500000000 { 53 opp-500000000 {
52 opp-hz = /bits/ 64 <50 54 opp-hz = /bits/ 64 <500000000>;
53 opp-microvolt = <83000 55 opp-microvolt = <830000>;
54 clock-latency-ns = <30 56 clock-latency-ns = <300000>;
55 }; 57 };
56 opp-1000000000 { 58 opp-1000000000 {
57 opp-hz = /bits/ 64 <10 59 opp-hz = /bits/ 64 <1000000000>;
58 opp-microvolt = <83000 60 opp-microvolt = <830000>;
59 clock-latency-ns = <30 61 clock-latency-ns = <300000>;
60 }; 62 };
61 opp-1500000000 { 63 opp-1500000000 {
62 opp-hz = /bits/ 64 <15 64 opp-hz = /bits/ 64 <1500000000>;
63 opp-microvolt = <83000 65 opp-microvolt = <830000>;
64 clock-latency-ns = <30 66 clock-latency-ns = <300000>;
65 opp-suspend; 67 opp-suspend;
66 }; 68 };
67 opp-1600000000 { 69 opp-1600000000 {
68 opp-hz = /bits/ 64 <16 70 opp-hz = /bits/ 64 <1600000000>;
69 opp-microvolt = <90000 71 opp-microvolt = <900000>;
70 clock-latency-ns = <30 72 clock-latency-ns = <300000>;
>> 73 turbo-mode;
71 }; 74 };
72 opp-1700000000 { 75 opp-1700000000 {
73 opp-hz = /bits/ 64 <17 76 opp-hz = /bits/ 64 <1700000000>;
74 opp-microvolt = <90000 77 opp-microvolt = <900000>;
75 clock-latency-ns = <30 78 clock-latency-ns = <300000>;
>> 79 turbo-mode;
76 }; 80 };
77 opp-1800000000 { 81 opp-1800000000 {
78 opp-hz = /bits/ 64 <18 82 opp-hz = /bits/ 64 <1800000000>;
79 opp-microvolt = <96000 83 opp-microvolt = <960000>;
80 clock-latency-ns = <30 84 clock-latency-ns = <300000>;
81 turbo-mode; 85 turbo-mode;
82 }; 86 };
83 }; 87 };
84 88
85 cluster1_opp: opp-table-1 { 89 cluster1_opp: opp-table-1 {
86 compatible = "operating-points 90 compatible = "operating-points-v2";
87 opp-shared; 91 opp-shared;
88 92
89 opp-800000000 { 93 opp-800000000 {
90 opp-hz = /bits/ 64 <80 94 opp-hz = /bits/ 64 <800000000>;
91 opp-microvolt = <82000 95 opp-microvolt = <820000>;
92 clock-latency-ns = <30 96 clock-latency-ns = <300000>;
93 }; 97 };
94 opp-1000000000 { 98 opp-1000000000 {
95 opp-hz = /bits/ 64 <10 99 opp-hz = /bits/ 64 <1000000000>;
96 opp-microvolt = <82000 100 opp-microvolt = <820000>;
97 clock-latency-ns = <30 101 clock-latency-ns = <300000>;
98 }; 102 };
99 opp-1200000000 { 103 opp-1200000000 {
100 opp-hz = /bits/ 64 <12 104 opp-hz = /bits/ 64 <1200000000>;
101 opp-microvolt = <82000 105 opp-microvolt = <820000>;
102 clock-latency-ns = <30 106 clock-latency-ns = <300000>;
103 }; 107 };
104 opp-1300000000 { 108 opp-1300000000 {
105 opp-hz = /bits/ 64 <13 109 opp-hz = /bits/ 64 <1300000000>;
106 opp-microvolt = <82000 110 opp-microvolt = <820000>;
107 clock-latency-ns = <30 111 clock-latency-ns = <300000>;
108 turbo-mode; 112 turbo-mode;
109 }; 113 };
110 }; 114 };
111 115
112 cpus { 116 cpus {
113 #address-cells = <1>; 117 #address-cells = <1>;
114 #size-cells = <0>; 118 #size-cells = <0>;
115 119
116 cpu-map { 120 cpu-map {
117 cluster0 { 121 cluster0 {
118 core0 { 122 core0 {
119 cpu = 123 cpu = <&a57_0>;
120 }; 124 };
121 core1 { 125 core1 {
122 cpu = 126 cpu = <&a57_1>;
123 }; 127 };
124 }; 128 };
125 129
126 cluster1 { 130 cluster1 {
127 core0 { 131 core0 {
128 cpu = 132 cpu = <&a53_0>;
129 }; 133 };
130 core1 { 134 core1 {
131 cpu = 135 cpu = <&a53_1>;
132 }; 136 };
133 core2 { 137 core2 {
134 cpu = 138 cpu = <&a53_2>;
135 }; 139 };
136 core3 { 140 core3 {
137 cpu = 141 cpu = <&a53_3>;
138 }; 142 };
139 }; 143 };
140 }; 144 };
141 145
142 a57_0: cpu@0 { 146 a57_0: cpu@0 {
143 compatible = "arm,cort 147 compatible = "arm,cortex-a57";
144 reg = <0x0>; 148 reg = <0x0>;
145 device_type = "cpu"; 149 device_type = "cpu";
146 power-domains = <&sysc 150 power-domains = <&sysc R8A7796_PD_CA57_CPU0>;
147 next-level-cache = <&L 151 next-level-cache = <&L2_CA57>;
148 enable-method = "psci" 152 enable-method = "psci";
149 cpu-idle-states = <&CP 153 cpu-idle-states = <&CPU_SLEEP_0>;
150 dynamic-power-coeffici 154 dynamic-power-coefficient = <854>;
151 clocks = <&cpg CPG_COR 155 clocks = <&cpg CPG_CORE R8A7796_CLK_Z>;
152 operating-points-v2 = 156 operating-points-v2 = <&cluster0_opp>;
153 capacity-dmips-mhz = < 157 capacity-dmips-mhz = <1024>;
154 #cooling-cells = <2>; 158 #cooling-cells = <2>;
155 }; 159 };
156 160
157 a57_1: cpu@1 { 161 a57_1: cpu@1 {
158 compatible = "arm,cort 162 compatible = "arm,cortex-a57";
159 reg = <0x1>; 163 reg = <0x1>;
160 device_type = "cpu"; 164 device_type = "cpu";
161 power-domains = <&sysc 165 power-domains = <&sysc R8A7796_PD_CA57_CPU1>;
162 next-level-cache = <&L 166 next-level-cache = <&L2_CA57>;
163 enable-method = "psci" 167 enable-method = "psci";
164 cpu-idle-states = <&CP 168 cpu-idle-states = <&CPU_SLEEP_0>;
165 clocks = <&cpg CPG_COR 169 clocks = <&cpg CPG_CORE R8A7796_CLK_Z>;
166 operating-points-v2 = 170 operating-points-v2 = <&cluster0_opp>;
167 capacity-dmips-mhz = < 171 capacity-dmips-mhz = <1024>;
168 #cooling-cells = <2>; 172 #cooling-cells = <2>;
169 }; 173 };
170 174
171 a53_0: cpu@100 { 175 a53_0: cpu@100 {
172 compatible = "arm,cort 176 compatible = "arm,cortex-a53";
173 reg = <0x100>; 177 reg = <0x100>;
174 device_type = "cpu"; 178 device_type = "cpu";
175 power-domains = <&sysc 179 power-domains = <&sysc R8A7796_PD_CA53_CPU0>;
176 next-level-cache = <&L 180 next-level-cache = <&L2_CA53>;
177 enable-method = "psci" 181 enable-method = "psci";
178 cpu-idle-states = <&CP 182 cpu-idle-states = <&CPU_SLEEP_1>;
179 #cooling-cells = <2>; 183 #cooling-cells = <2>;
180 dynamic-power-coeffici 184 dynamic-power-coefficient = <277>;
181 clocks = <&cpg CPG_COR 185 clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
182 operating-points-v2 = 186 operating-points-v2 = <&cluster1_opp>;
183 capacity-dmips-mhz = < 187 capacity-dmips-mhz = <535>;
184 }; 188 };
185 189
186 a53_1: cpu@101 { 190 a53_1: cpu@101 {
187 compatible = "arm,cort 191 compatible = "arm,cortex-a53";
188 reg = <0x101>; 192 reg = <0x101>;
189 device_type = "cpu"; 193 device_type = "cpu";
190 power-domains = <&sysc 194 power-domains = <&sysc R8A7796_PD_CA53_CPU1>;
191 next-level-cache = <&L 195 next-level-cache = <&L2_CA53>;
192 enable-method = "psci" 196 enable-method = "psci";
193 cpu-idle-states = <&CP 197 cpu-idle-states = <&CPU_SLEEP_1>;
194 clocks = <&cpg CPG_COR 198 clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
195 operating-points-v2 = 199 operating-points-v2 = <&cluster1_opp>;
196 capacity-dmips-mhz = < 200 capacity-dmips-mhz = <535>;
197 }; 201 };
198 202
199 a53_2: cpu@102 { 203 a53_2: cpu@102 {
200 compatible = "arm,cort 204 compatible = "arm,cortex-a53";
201 reg = <0x102>; 205 reg = <0x102>;
202 device_type = "cpu"; 206 device_type = "cpu";
203 power-domains = <&sysc 207 power-domains = <&sysc R8A7796_PD_CA53_CPU2>;
204 next-level-cache = <&L 208 next-level-cache = <&L2_CA53>;
205 enable-method = "psci" 209 enable-method = "psci";
206 cpu-idle-states = <&CP 210 cpu-idle-states = <&CPU_SLEEP_1>;
207 clocks = <&cpg CPG_COR 211 clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
208 operating-points-v2 = 212 operating-points-v2 = <&cluster1_opp>;
209 capacity-dmips-mhz = < 213 capacity-dmips-mhz = <535>;
210 }; 214 };
211 215
212 a53_3: cpu@103 { 216 a53_3: cpu@103 {
213 compatible = "arm,cort 217 compatible = "arm,cortex-a53";
214 reg = <0x103>; 218 reg = <0x103>;
215 device_type = "cpu"; 219 device_type = "cpu";
216 power-domains = <&sysc 220 power-domains = <&sysc R8A7796_PD_CA53_CPU3>;
217 next-level-cache = <&L 221 next-level-cache = <&L2_CA53>;
218 enable-method = "psci" 222 enable-method = "psci";
219 cpu-idle-states = <&CP 223 cpu-idle-states = <&CPU_SLEEP_1>;
220 clocks = <&cpg CPG_COR 224 clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
221 operating-points-v2 = 225 operating-points-v2 = <&cluster1_opp>;
222 capacity-dmips-mhz = < 226 capacity-dmips-mhz = <535>;
223 }; 227 };
224 228
225 L2_CA57: cache-controller-0 { 229 L2_CA57: cache-controller-0 {
226 compatible = "cache"; 230 compatible = "cache";
227 power-domains = <&sysc 231 power-domains = <&sysc R8A7796_PD_CA57_SCU>;
228 cache-unified; 232 cache-unified;
229 cache-level = <2>; 233 cache-level = <2>;
230 }; 234 };
231 235
232 L2_CA53: cache-controller-1 { 236 L2_CA53: cache-controller-1 {
233 compatible = "cache"; 237 compatible = "cache";
234 power-domains = <&sysc 238 power-domains = <&sysc R8A7796_PD_CA53_SCU>;
235 cache-unified; 239 cache-unified;
236 cache-level = <2>; 240 cache-level = <2>;
237 }; 241 };
238 242
239 idle-states { 243 idle-states {
240 entry-method = "psci"; 244 entry-method = "psci";
241 245
242 CPU_SLEEP_0: cpu-sleep 246 CPU_SLEEP_0: cpu-sleep-0 {
243 compatible = " 247 compatible = "arm,idle-state";
244 arm,psci-suspe 248 arm,psci-suspend-param = <0x0010000>;
245 local-timer-st 249 local-timer-stop;
246 entry-latency- 250 entry-latency-us = <400>;
247 exit-latency-u 251 exit-latency-us = <500>;
248 min-residency- 252 min-residency-us = <4000>;
249 }; 253 };
250 254
251 CPU_SLEEP_1: cpu-sleep 255 CPU_SLEEP_1: cpu-sleep-1 {
252 compatible = " 256 compatible = "arm,idle-state";
253 arm,psci-suspe 257 arm,psci-suspend-param = <0x0010000>;
254 local-timer-st 258 local-timer-stop;
255 entry-latency- 259 entry-latency-us = <700>;
256 exit-latency-u 260 exit-latency-us = <700>;
257 min-residency- 261 min-residency-us = <5000>;
258 }; 262 };
259 }; 263 };
260 }; 264 };
261 265
262 extal_clk: extal { 266 extal_clk: extal {
263 compatible = "fixed-clock"; 267 compatible = "fixed-clock";
264 #clock-cells = <0>; 268 #clock-cells = <0>;
265 /* This value must be overridd 269 /* This value must be overridden by the board */
266 clock-frequency = <0>; 270 clock-frequency = <0>;
267 }; 271 };
268 272
269 extalr_clk: extalr { 273 extalr_clk: extalr {
270 compatible = "fixed-clock"; 274 compatible = "fixed-clock";
271 #clock-cells = <0>; 275 #clock-cells = <0>;
272 /* This value must be overridd 276 /* This value must be overridden by the board */
273 clock-frequency = <0>; 277 clock-frequency = <0>;
274 }; 278 };
275 279
276 /* External PCIe clock - can be overri 280 /* External PCIe clock - can be overridden by the board */
277 pcie_bus_clk: pcie_bus { 281 pcie_bus_clk: pcie_bus {
278 compatible = "fixed-clock"; 282 compatible = "fixed-clock";
279 #clock-cells = <0>; 283 #clock-cells = <0>;
280 clock-frequency = <0>; 284 clock-frequency = <0>;
281 }; 285 };
282 286
283 pmu_a53 { 287 pmu_a53 {
284 compatible = "arm,cortex-a53-p 288 compatible = "arm,cortex-a53-pmu";
285 interrupts-extended = <&gic GI 289 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
286 <&gic GI 290 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
287 <&gic GI 291 <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
288 <&gic GI 292 <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
289 interrupt-affinity = <&a53_0>, 293 interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>;
290 }; 294 };
291 295
292 pmu_a57 { 296 pmu_a57 {
293 compatible = "arm,cortex-a57-p 297 compatible = "arm,cortex-a57-pmu";
294 interrupts-extended = <&gic GI 298 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
295 <&gic GI 299 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
296 interrupt-affinity = <&a57_0>, 300 interrupt-affinity = <&a57_0>, <&a57_1>;
297 }; 301 };
298 302
299 psci { 303 psci {
300 compatible = "arm,psci-1.0", " 304 compatible = "arm,psci-1.0", "arm,psci-0.2";
301 method = "smc"; 305 method = "smc";
302 }; 306 };
303 307
304 /* External SCIF clock - to be overrid 308 /* External SCIF clock - to be overridden by boards that provide it */
305 scif_clk: scif { 309 scif_clk: scif {
306 compatible = "fixed-clock"; 310 compatible = "fixed-clock";
307 #clock-cells = <0>; 311 #clock-cells = <0>;
308 clock-frequency = <0>; 312 clock-frequency = <0>;
309 }; 313 };
310 314
311 soc { 315 soc {
312 compatible = "simple-bus"; 316 compatible = "simple-bus";
313 interrupt-parent = <&gic>; 317 interrupt-parent = <&gic>;
314 #address-cells = <2>; 318 #address-cells = <2>;
315 #size-cells = <2>; 319 #size-cells = <2>;
316 ranges; 320 ranges;
317 321
318 rwdt: watchdog@e6020000 { 322 rwdt: watchdog@e6020000 {
319 compatible = "renesas, 323 compatible = "renesas,r8a7796-wdt",
320 "renesas, 324 "renesas,rcar-gen3-wdt";
321 reg = <0 0xe6020000 0 325 reg = <0 0xe6020000 0 0x0c>;
322 interrupts = <GIC_SPI 326 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
323 clocks = <&cpg CPG_MOD 327 clocks = <&cpg CPG_MOD 402>;
324 power-domains = <&sysc 328 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
325 resets = <&cpg 402>; 329 resets = <&cpg 402>;
326 status = "disabled"; 330 status = "disabled";
327 }; 331 };
328 332
329 gpio0: gpio@e6050000 { 333 gpio0: gpio@e6050000 {
330 compatible = "renesas, 334 compatible = "renesas,gpio-r8a7796",
331 "renesas, 335 "renesas,rcar-gen3-gpio";
332 reg = <0 0xe6050000 0 336 reg = <0 0xe6050000 0 0x50>;
333 interrupts = <GIC_SPI 337 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
334 #gpio-cells = <2>; 338 #gpio-cells = <2>;
335 gpio-controller; 339 gpio-controller;
336 gpio-ranges = <&pfc 0 340 gpio-ranges = <&pfc 0 0 16>;
337 #interrupt-cells = <2> 341 #interrupt-cells = <2>;
338 interrupt-controller; 342 interrupt-controller;
339 clocks = <&cpg CPG_MOD 343 clocks = <&cpg CPG_MOD 912>;
340 power-domains = <&sysc 344 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
341 resets = <&cpg 912>; 345 resets = <&cpg 912>;
342 }; 346 };
343 347
344 gpio1: gpio@e6051000 { 348 gpio1: gpio@e6051000 {
345 compatible = "renesas, 349 compatible = "renesas,gpio-r8a7796",
346 "renesas, 350 "renesas,rcar-gen3-gpio";
347 reg = <0 0xe6051000 0 351 reg = <0 0xe6051000 0 0x50>;
348 interrupts = <GIC_SPI 352 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
349 #gpio-cells = <2>; 353 #gpio-cells = <2>;
350 gpio-controller; 354 gpio-controller;
351 gpio-ranges = <&pfc 0 355 gpio-ranges = <&pfc 0 32 29>;
352 #interrupt-cells = <2> 356 #interrupt-cells = <2>;
353 interrupt-controller; 357 interrupt-controller;
354 clocks = <&cpg CPG_MOD 358 clocks = <&cpg CPG_MOD 911>;
355 power-domains = <&sysc 359 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
356 resets = <&cpg 911>; 360 resets = <&cpg 911>;
357 }; 361 };
358 362
359 gpio2: gpio@e6052000 { 363 gpio2: gpio@e6052000 {
360 compatible = "renesas, 364 compatible = "renesas,gpio-r8a7796",
361 "renesas, 365 "renesas,rcar-gen3-gpio";
362 reg = <0 0xe6052000 0 366 reg = <0 0xe6052000 0 0x50>;
363 interrupts = <GIC_SPI 367 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
364 #gpio-cells = <2>; 368 #gpio-cells = <2>;
365 gpio-controller; 369 gpio-controller;
366 gpio-ranges = <&pfc 0 370 gpio-ranges = <&pfc 0 64 15>;
367 #interrupt-cells = <2> 371 #interrupt-cells = <2>;
368 interrupt-controller; 372 interrupt-controller;
369 clocks = <&cpg CPG_MOD 373 clocks = <&cpg CPG_MOD 910>;
370 power-domains = <&sysc 374 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
371 resets = <&cpg 910>; 375 resets = <&cpg 910>;
372 }; 376 };
373 377
374 gpio3: gpio@e6053000 { 378 gpio3: gpio@e6053000 {
375 compatible = "renesas, 379 compatible = "renesas,gpio-r8a7796",
376 "renesas, 380 "renesas,rcar-gen3-gpio";
377 reg = <0 0xe6053000 0 381 reg = <0 0xe6053000 0 0x50>;
378 interrupts = <GIC_SPI 382 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
379 #gpio-cells = <2>; 383 #gpio-cells = <2>;
380 gpio-controller; 384 gpio-controller;
381 gpio-ranges = <&pfc 0 385 gpio-ranges = <&pfc 0 96 16>;
382 #interrupt-cells = <2> 386 #interrupt-cells = <2>;
383 interrupt-controller; 387 interrupt-controller;
384 clocks = <&cpg CPG_MOD 388 clocks = <&cpg CPG_MOD 909>;
385 power-domains = <&sysc 389 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
386 resets = <&cpg 909>; 390 resets = <&cpg 909>;
387 }; 391 };
388 392
389 gpio4: gpio@e6054000 { 393 gpio4: gpio@e6054000 {
390 compatible = "renesas, 394 compatible = "renesas,gpio-r8a7796",
391 "renesas, 395 "renesas,rcar-gen3-gpio";
392 reg = <0 0xe6054000 0 396 reg = <0 0xe6054000 0 0x50>;
393 interrupts = <GIC_SPI 397 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
394 #gpio-cells = <2>; 398 #gpio-cells = <2>;
395 gpio-controller; 399 gpio-controller;
396 gpio-ranges = <&pfc 0 400 gpio-ranges = <&pfc 0 128 18>;
397 #interrupt-cells = <2> 401 #interrupt-cells = <2>;
398 interrupt-controller; 402 interrupt-controller;
399 clocks = <&cpg CPG_MOD 403 clocks = <&cpg CPG_MOD 908>;
400 power-domains = <&sysc 404 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
401 resets = <&cpg 908>; 405 resets = <&cpg 908>;
402 }; 406 };
403 407
404 gpio5: gpio@e6055000 { 408 gpio5: gpio@e6055000 {
405 compatible = "renesas, 409 compatible = "renesas,gpio-r8a7796",
406 "renesas, 410 "renesas,rcar-gen3-gpio";
407 reg = <0 0xe6055000 0 411 reg = <0 0xe6055000 0 0x50>;
408 interrupts = <GIC_SPI 412 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
409 #gpio-cells = <2>; 413 #gpio-cells = <2>;
410 gpio-controller; 414 gpio-controller;
411 gpio-ranges = <&pfc 0 415 gpio-ranges = <&pfc 0 160 26>;
412 #interrupt-cells = <2> 416 #interrupt-cells = <2>;
413 interrupt-controller; 417 interrupt-controller;
414 clocks = <&cpg CPG_MOD 418 clocks = <&cpg CPG_MOD 907>;
415 power-domains = <&sysc 419 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
416 resets = <&cpg 907>; 420 resets = <&cpg 907>;
417 }; 421 };
418 422
419 gpio6: gpio@e6055400 { 423 gpio6: gpio@e6055400 {
420 compatible = "renesas, 424 compatible = "renesas,gpio-r8a7796",
421 "renesas, 425 "renesas,rcar-gen3-gpio";
422 reg = <0 0xe6055400 0 426 reg = <0 0xe6055400 0 0x50>;
423 interrupts = <GIC_SPI 427 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
424 #gpio-cells = <2>; 428 #gpio-cells = <2>;
425 gpio-controller; 429 gpio-controller;
426 gpio-ranges = <&pfc 0 430 gpio-ranges = <&pfc 0 192 32>;
427 #interrupt-cells = <2> 431 #interrupt-cells = <2>;
428 interrupt-controller; 432 interrupt-controller;
429 clocks = <&cpg CPG_MOD 433 clocks = <&cpg CPG_MOD 906>;
430 power-domains = <&sysc 434 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
431 resets = <&cpg 906>; 435 resets = <&cpg 906>;
432 }; 436 };
433 437
434 gpio7: gpio@e6055800 { 438 gpio7: gpio@e6055800 {
435 compatible = "renesas, 439 compatible = "renesas,gpio-r8a7796",
436 "renesas, 440 "renesas,rcar-gen3-gpio";
437 reg = <0 0xe6055800 0 441 reg = <0 0xe6055800 0 0x50>;
438 interrupts = <GIC_SPI 442 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
439 #gpio-cells = <2>; 443 #gpio-cells = <2>;
440 gpio-controller; 444 gpio-controller;
441 gpio-ranges = <&pfc 0 445 gpio-ranges = <&pfc 0 224 4>;
442 #interrupt-cells = <2> 446 #interrupt-cells = <2>;
443 interrupt-controller; 447 interrupt-controller;
444 clocks = <&cpg CPG_MOD 448 clocks = <&cpg CPG_MOD 905>;
445 power-domains = <&sysc 449 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
446 resets = <&cpg 905>; 450 resets = <&cpg 905>;
447 }; 451 };
448 452
449 pfc: pinctrl@e6060000 { 453 pfc: pinctrl@e6060000 {
450 compatible = "renesas, 454 compatible = "renesas,pfc-r8a7796";
451 reg = <0 0xe6060000 0 455 reg = <0 0xe6060000 0 0x50c>;
452 }; 456 };
453 457
454 cmt0: timer@e60f0000 { 458 cmt0: timer@e60f0000 {
455 compatible = "renesas, 459 compatible = "renesas,r8a7796-cmt0",
456 "renesas, 460 "renesas,rcar-gen3-cmt0";
457 reg = <0 0xe60f0000 0 461 reg = <0 0xe60f0000 0 0x1004>;
458 interrupts = <GIC_SPI 462 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
459 <GIC_SPI 463 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
460 clocks = <&cpg CPG_MOD 464 clocks = <&cpg CPG_MOD 303>;
461 clock-names = "fck"; 465 clock-names = "fck";
462 power-domains = <&sysc 466 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
463 resets = <&cpg 303>; 467 resets = <&cpg 303>;
464 status = "disabled"; 468 status = "disabled";
465 }; 469 };
466 470
467 cmt1: timer@e6130000 { 471 cmt1: timer@e6130000 {
468 compatible = "renesas, 472 compatible = "renesas,r8a7796-cmt1",
469 "renesas, 473 "renesas,rcar-gen3-cmt1";
470 reg = <0 0xe6130000 0 474 reg = <0 0xe6130000 0 0x1004>;
471 interrupts = <GIC_SPI 475 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
472 <GIC_SPI 476 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
473 <GIC_SPI 477 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
474 <GIC_SPI 478 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
475 <GIC_SPI 479 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
476 <GIC_SPI 480 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
477 <GIC_SPI 481 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
478 <GIC_SPI 482 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
479 clocks = <&cpg CPG_MOD 483 clocks = <&cpg CPG_MOD 302>;
480 clock-names = "fck"; 484 clock-names = "fck";
481 power-domains = <&sysc 485 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
482 resets = <&cpg 302>; 486 resets = <&cpg 302>;
483 status = "disabled"; 487 status = "disabled";
484 }; 488 };
485 489
486 cmt2: timer@e6140000 { 490 cmt2: timer@e6140000 {
487 compatible = "renesas, 491 compatible = "renesas,r8a7796-cmt1",
488 "renesas, 492 "renesas,rcar-gen3-cmt1";
489 reg = <0 0xe6140000 0 493 reg = <0 0xe6140000 0 0x1004>;
490 interrupts = <GIC_SPI 494 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
491 <GIC_SPI 495 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
492 <GIC_SPI 496 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
493 <GIC_SPI 497 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
494 <GIC_SPI 498 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
495 <GIC_SPI 499 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
496 <GIC_SPI 500 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
497 <GIC_SPI 501 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
498 clocks = <&cpg CPG_MOD 502 clocks = <&cpg CPG_MOD 301>;
499 clock-names = "fck"; 503 clock-names = "fck";
500 power-domains = <&sysc 504 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
501 resets = <&cpg 301>; 505 resets = <&cpg 301>;
502 status = "disabled"; 506 status = "disabled";
503 }; 507 };
504 508
505 cmt3: timer@e6148000 { 509 cmt3: timer@e6148000 {
506 compatible = "renesas, 510 compatible = "renesas,r8a7796-cmt1",
507 "renesas, 511 "renesas,rcar-gen3-cmt1";
508 reg = <0 0xe6148000 0 512 reg = <0 0xe6148000 0 0x1004>;
509 interrupts = <GIC_SPI 513 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
510 <GIC_SPI 514 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
511 <GIC_SPI 515 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
512 <GIC_SPI 516 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
513 <GIC_SPI 517 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
514 <GIC_SPI 518 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
515 <GIC_SPI 519 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
516 <GIC_SPI 520 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
517 clocks = <&cpg CPG_MOD 521 clocks = <&cpg CPG_MOD 300>;
518 clock-names = "fck"; 522 clock-names = "fck";
519 power-domains = <&sysc 523 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
520 resets = <&cpg 300>; 524 resets = <&cpg 300>;
521 status = "disabled"; 525 status = "disabled";
522 }; 526 };
523 527
524 cpg: clock-controller@e6150000 528 cpg: clock-controller@e6150000 {
525 compatible = "renesas, 529 compatible = "renesas,r8a7796-cpg-mssr";
526 reg = <0 0xe6150000 0 530 reg = <0 0xe6150000 0 0x1000>;
527 clocks = <&extal_clk>, 531 clocks = <&extal_clk>, <&extalr_clk>;
528 clock-names = "extal", 532 clock-names = "extal", "extalr";
529 #clock-cells = <2>; 533 #clock-cells = <2>;
530 #power-domain-cells = 534 #power-domain-cells = <0>;
531 #reset-cells = <1>; 535 #reset-cells = <1>;
532 }; 536 };
533 537
534 rst: reset-controller@e6160000 538 rst: reset-controller@e6160000 {
535 compatible = "renesas, 539 compatible = "renesas,r8a7796-rst";
536 reg = <0 0xe6160000 0 540 reg = <0 0xe6160000 0 0x0200>;
537 }; 541 };
538 542
539 sysc: system-controller@e61800 543 sysc: system-controller@e6180000 {
540 compatible = "renesas, 544 compatible = "renesas,r8a7796-sysc";
541 reg = <0 0xe6180000 0 545 reg = <0 0xe6180000 0 0x0400>;
542 #power-domain-cells = 546 #power-domain-cells = <1>;
543 }; 547 };
544 548
545 tsc: thermal@e6198000 { 549 tsc: thermal@e6198000 {
546 compatible = "renesas, 550 compatible = "renesas,r8a7796-thermal";
547 reg = <0 0xe6198000 0 551 reg = <0 0xe6198000 0 0x100>,
548 <0 0xe61a0000 0 552 <0 0xe61a0000 0 0x100>,
549 <0 0xe61a8000 0 553 <0 0xe61a8000 0 0x100>;
550 interrupts = <GIC_SPI 554 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
551 <GIC_SPI 555 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
552 <GIC_SPI 556 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
553 clocks = <&cpg CPG_MOD 557 clocks = <&cpg CPG_MOD 522>;
554 power-domains = <&sysc 558 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
555 resets = <&cpg 522>; 559 resets = <&cpg 522>;
556 #thermal-sensor-cells 560 #thermal-sensor-cells = <1>;
557 }; 561 };
558 562
559 intc_ex: interrupt-controller@ 563 intc_ex: interrupt-controller@e61c0000 {
560 compatible = "renesas, 564 compatible = "renesas,intc-ex-r8a7796", "renesas,irqc";
561 #interrupt-cells = <2> 565 #interrupt-cells = <2>;
562 interrupt-controller; 566 interrupt-controller;
563 reg = <0 0xe61c0000 0 567 reg = <0 0xe61c0000 0 0x200>;
564 interrupts = <GIC_SPI 568 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
565 <GIC_SPI 569 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
566 <GIC_SPI 570 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
567 <GIC_SPI 571 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
568 <GIC_SPI 572 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
569 <GIC_SPI 573 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
570 clocks = <&cpg CPG_MOD 574 clocks = <&cpg CPG_MOD 407>;
571 power-domains = <&sysc 575 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
572 resets = <&cpg 407>; 576 resets = <&cpg 407>;
573 }; 577 };
574 578
575 tmu0: timer@e61e0000 { 579 tmu0: timer@e61e0000 {
576 compatible = "renesas, 580 compatible = "renesas,tmu-r8a7796", "renesas,tmu";
577 reg = <0 0xe61e0000 0 581 reg = <0 0xe61e0000 0 0x30>;
578 interrupts = <GIC_SPI 582 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
579 <GIC_SPI 583 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
580 <GIC_SPI 584 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
581 interrupt-names = "tun <<
582 clocks = <&cpg CPG_MOD 585 clocks = <&cpg CPG_MOD 125>;
583 clock-names = "fck"; 586 clock-names = "fck";
584 power-domains = <&sysc 587 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
585 resets = <&cpg 125>; 588 resets = <&cpg 125>;
586 status = "disabled"; 589 status = "disabled";
587 }; 590 };
588 591
589 tmu1: timer@e6fc0000 { 592 tmu1: timer@e6fc0000 {
590 compatible = "renesas, 593 compatible = "renesas,tmu-r8a7796", "renesas,tmu";
591 reg = <0 0xe6fc0000 0 594 reg = <0 0xe6fc0000 0 0x30>;
592 interrupts = <GIC_SPI 595 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
593 <GIC_SPI 596 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
594 <GIC_SPI !! 597 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
595 <GIC_SPI <<
596 interrupt-names = "tun <<
597 clocks = <&cpg CPG_MOD 598 clocks = <&cpg CPG_MOD 124>;
598 clock-names = "fck"; 599 clock-names = "fck";
599 power-domains = <&sysc 600 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
600 resets = <&cpg 124>; 601 resets = <&cpg 124>;
601 status = "disabled"; 602 status = "disabled";
602 }; 603 };
603 604
604 tmu2: timer@e6fd0000 { 605 tmu2: timer@e6fd0000 {
605 compatible = "renesas, 606 compatible = "renesas,tmu-r8a7796", "renesas,tmu";
606 reg = <0 0xe6fd0000 0 607 reg = <0 0xe6fd0000 0 0x30>;
607 interrupts = <GIC_SPI 608 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
608 <GIC_SPI 609 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
609 <GIC_SPI !! 610 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
610 <GIC_SPI <<
611 interrupt-names = "tun <<
612 clocks = <&cpg CPG_MOD 611 clocks = <&cpg CPG_MOD 123>;
613 clock-names = "fck"; 612 clock-names = "fck";
614 power-domains = <&sysc 613 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
615 resets = <&cpg 123>; 614 resets = <&cpg 123>;
616 status = "disabled"; 615 status = "disabled";
617 }; 616 };
618 617
619 tmu3: timer@e6fe0000 { 618 tmu3: timer@e6fe0000 {
620 compatible = "renesas, 619 compatible = "renesas,tmu-r8a7796", "renesas,tmu";
621 reg = <0 0xe6fe0000 0 620 reg = <0 0xe6fe0000 0 0x30>;
622 interrupts = <GIC_SPI 621 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
623 <GIC_SPI 622 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
624 <GIC_SPI 623 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
625 interrupt-names = "tun <<
626 clocks = <&cpg CPG_MOD 624 clocks = <&cpg CPG_MOD 122>;
627 clock-names = "fck"; 625 clock-names = "fck";
628 power-domains = <&sysc 626 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
629 resets = <&cpg 122>; 627 resets = <&cpg 122>;
630 status = "disabled"; 628 status = "disabled";
631 }; 629 };
632 630
633 tmu4: timer@ffc00000 { 631 tmu4: timer@ffc00000 {
634 compatible = "renesas, 632 compatible = "renesas,tmu-r8a7796", "renesas,tmu";
635 reg = <0 0xffc00000 0 633 reg = <0 0xffc00000 0 0x30>;
636 interrupts = <GIC_SPI 634 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
637 <GIC_SPI 635 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
638 <GIC_SPI 636 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
639 interrupt-names = "tun <<
640 clocks = <&cpg CPG_MOD 637 clocks = <&cpg CPG_MOD 121>;
641 clock-names = "fck"; 638 clock-names = "fck";
642 power-domains = <&sysc 639 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
643 resets = <&cpg 121>; 640 resets = <&cpg 121>;
644 status = "disabled"; 641 status = "disabled";
645 }; 642 };
646 643
647 i2c0: i2c@e6500000 { 644 i2c0: i2c@e6500000 {
648 #address-cells = <1>; 645 #address-cells = <1>;
649 #size-cells = <0>; 646 #size-cells = <0>;
650 compatible = "renesas, 647 compatible = "renesas,i2c-r8a7796",
651 "renesas, 648 "renesas,rcar-gen3-i2c";
652 reg = <0 0xe6500000 0 649 reg = <0 0xe6500000 0 0x40>;
653 interrupts = <GIC_SPI 650 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
654 clocks = <&cpg CPG_MOD 651 clocks = <&cpg CPG_MOD 931>;
655 power-domains = <&sysc 652 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
656 resets = <&cpg 931>; 653 resets = <&cpg 931>;
657 dmas = <&dmac1 0x91>, 654 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
658 <&dmac2 0x91>, 655 <&dmac2 0x91>, <&dmac2 0x90>;
659 dma-names = "tx", "rx" 656 dma-names = "tx", "rx", "tx", "rx";
660 i2c-scl-internal-delay 657 i2c-scl-internal-delay-ns = <110>;
661 status = "disabled"; 658 status = "disabled";
662 }; 659 };
663 660
664 i2c1: i2c@e6508000 { 661 i2c1: i2c@e6508000 {
665 #address-cells = <1>; 662 #address-cells = <1>;
666 #size-cells = <0>; 663 #size-cells = <0>;
667 compatible = "renesas, 664 compatible = "renesas,i2c-r8a7796",
668 "renesas, 665 "renesas,rcar-gen3-i2c";
669 reg = <0 0xe6508000 0 666 reg = <0 0xe6508000 0 0x40>;
670 interrupts = <GIC_SPI 667 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
671 clocks = <&cpg CPG_MOD 668 clocks = <&cpg CPG_MOD 930>;
672 power-domains = <&sysc 669 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
673 resets = <&cpg 930>; 670 resets = <&cpg 930>;
674 dmas = <&dmac1 0x93>, 671 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
675 <&dmac2 0x93>, 672 <&dmac2 0x93>, <&dmac2 0x92>;
676 dma-names = "tx", "rx" 673 dma-names = "tx", "rx", "tx", "rx";
677 i2c-scl-internal-delay 674 i2c-scl-internal-delay-ns = <6>;
678 status = "disabled"; 675 status = "disabled";
679 }; 676 };
680 677
681 i2c2: i2c@e6510000 { 678 i2c2: i2c@e6510000 {
682 #address-cells = <1>; 679 #address-cells = <1>;
683 #size-cells = <0>; 680 #size-cells = <0>;
684 compatible = "renesas, 681 compatible = "renesas,i2c-r8a7796",
685 "renesas, 682 "renesas,rcar-gen3-i2c";
686 reg = <0 0xe6510000 0 683 reg = <0 0xe6510000 0 0x40>;
687 interrupts = <GIC_SPI 684 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
688 clocks = <&cpg CPG_MOD 685 clocks = <&cpg CPG_MOD 929>;
689 power-domains = <&sysc 686 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
690 resets = <&cpg 929>; 687 resets = <&cpg 929>;
691 dmas = <&dmac1 0x95>, 688 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
692 <&dmac2 0x95>, 689 <&dmac2 0x95>, <&dmac2 0x94>;
693 dma-names = "tx", "rx" 690 dma-names = "tx", "rx", "tx", "rx";
694 i2c-scl-internal-delay 691 i2c-scl-internal-delay-ns = <6>;
695 status = "disabled"; 692 status = "disabled";
696 }; 693 };
697 694
698 i2c3: i2c@e66d0000 { 695 i2c3: i2c@e66d0000 {
699 #address-cells = <1>; 696 #address-cells = <1>;
700 #size-cells = <0>; 697 #size-cells = <0>;
701 compatible = "renesas, 698 compatible = "renesas,i2c-r8a7796",
702 "renesas, 699 "renesas,rcar-gen3-i2c";
703 reg = <0 0xe66d0000 0 700 reg = <0 0xe66d0000 0 0x40>;
704 interrupts = <GIC_SPI 701 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
705 clocks = <&cpg CPG_MOD 702 clocks = <&cpg CPG_MOD 928>;
706 power-domains = <&sysc 703 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
707 resets = <&cpg 928>; 704 resets = <&cpg 928>;
708 dmas = <&dmac0 0x97>, 705 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
709 dma-names = "tx", "rx" 706 dma-names = "tx", "rx";
710 i2c-scl-internal-delay 707 i2c-scl-internal-delay-ns = <110>;
711 status = "disabled"; 708 status = "disabled";
712 }; 709 };
713 710
714 i2c4: i2c@e66d8000 { 711 i2c4: i2c@e66d8000 {
715 #address-cells = <1>; 712 #address-cells = <1>;
716 #size-cells = <0>; 713 #size-cells = <0>;
717 compatible = "renesas, 714 compatible = "renesas,i2c-r8a7796",
718 "renesas, 715 "renesas,rcar-gen3-i2c";
719 reg = <0 0xe66d8000 0 716 reg = <0 0xe66d8000 0 0x40>;
720 interrupts = <GIC_SPI 717 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
721 clocks = <&cpg CPG_MOD 718 clocks = <&cpg CPG_MOD 927>;
722 power-domains = <&sysc 719 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
723 resets = <&cpg 927>; 720 resets = <&cpg 927>;
724 dmas = <&dmac0 0x99>, 721 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
725 dma-names = "tx", "rx" 722 dma-names = "tx", "rx";
726 i2c-scl-internal-delay 723 i2c-scl-internal-delay-ns = <110>;
727 status = "disabled"; 724 status = "disabled";
728 }; 725 };
729 726
730 i2c5: i2c@e66e0000 { 727 i2c5: i2c@e66e0000 {
731 #address-cells = <1>; 728 #address-cells = <1>;
732 #size-cells = <0>; 729 #size-cells = <0>;
733 compatible = "renesas, 730 compatible = "renesas,i2c-r8a7796",
734 "renesas, 731 "renesas,rcar-gen3-i2c";
735 reg = <0 0xe66e0000 0 732 reg = <0 0xe66e0000 0 0x40>;
736 interrupts = <GIC_SPI 733 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
737 clocks = <&cpg CPG_MOD 734 clocks = <&cpg CPG_MOD 919>;
738 power-domains = <&sysc 735 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
739 resets = <&cpg 919>; 736 resets = <&cpg 919>;
740 dmas = <&dmac0 0x9b>, 737 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
741 dma-names = "tx", "rx" 738 dma-names = "tx", "rx";
742 i2c-scl-internal-delay 739 i2c-scl-internal-delay-ns = <110>;
743 status = "disabled"; 740 status = "disabled";
744 }; 741 };
745 742
746 i2c6: i2c@e66e8000 { 743 i2c6: i2c@e66e8000 {
747 #address-cells = <1>; 744 #address-cells = <1>;
748 #size-cells = <0>; 745 #size-cells = <0>;
749 compatible = "renesas, 746 compatible = "renesas,i2c-r8a7796",
750 "renesas, 747 "renesas,rcar-gen3-i2c";
751 reg = <0 0xe66e8000 0 748 reg = <0 0xe66e8000 0 0x40>;
752 interrupts = <GIC_SPI 749 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
753 clocks = <&cpg CPG_MOD 750 clocks = <&cpg CPG_MOD 918>;
754 power-domains = <&sysc 751 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
755 resets = <&cpg 918>; 752 resets = <&cpg 918>;
756 dmas = <&dmac0 0x9d>, 753 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
757 dma-names = "tx", "rx" 754 dma-names = "tx", "rx";
758 i2c-scl-internal-delay 755 i2c-scl-internal-delay-ns = <6>;
759 status = "disabled"; 756 status = "disabled";
760 }; 757 };
761 758
762 i2c_dvfs: i2c@e60b0000 { 759 i2c_dvfs: i2c@e60b0000 {
763 #address-cells = <1>; 760 #address-cells = <1>;
764 #size-cells = <0>; 761 #size-cells = <0>;
765 compatible = "renesas, 762 compatible = "renesas,iic-r8a7796",
766 "renesas, 763 "renesas,rcar-gen3-iic",
767 "renesas, 764 "renesas,rmobile-iic";
768 reg = <0 0xe60b0000 0 765 reg = <0 0xe60b0000 0 0x425>;
769 interrupts = <GIC_SPI 766 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
770 clocks = <&cpg CPG_MOD 767 clocks = <&cpg CPG_MOD 926>;
771 power-domains = <&sysc 768 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
772 resets = <&cpg 926>; 769 resets = <&cpg 926>;
773 dmas = <&dmac0 0x11>, 770 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
774 dma-names = "tx", "rx" 771 dma-names = "tx", "rx";
775 status = "disabled"; 772 status = "disabled";
776 }; 773 };
777 774
778 hscif0: serial@e6540000 { 775 hscif0: serial@e6540000 {
779 compatible = "renesas, 776 compatible = "renesas,hscif-r8a7796",
780 "renesas, 777 "renesas,rcar-gen3-hscif",
781 "renesas, 778 "renesas,hscif";
782 reg = <0 0xe6540000 0 779 reg = <0 0xe6540000 0 0x60>;
783 interrupts = <GIC_SPI 780 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
784 clocks = <&cpg CPG_MOD 781 clocks = <&cpg CPG_MOD 520>,
785 <&cpg CPG_COR 782 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
786 <&scif_clk>; 783 <&scif_clk>;
787 clock-names = "fck", " 784 clock-names = "fck", "brg_int", "scif_clk";
788 dmas = <&dmac1 0x31>, 785 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
789 <&dmac2 0x31>, 786 <&dmac2 0x31>, <&dmac2 0x30>;
790 dma-names = "tx", "rx" 787 dma-names = "tx", "rx", "tx", "rx";
791 power-domains = <&sysc 788 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
792 resets = <&cpg 520>; 789 resets = <&cpg 520>;
793 status = "disabled"; 790 status = "disabled";
794 }; 791 };
795 792
796 hscif1: serial@e6550000 { 793 hscif1: serial@e6550000 {
797 compatible = "renesas, 794 compatible = "renesas,hscif-r8a7796",
798 "renesas, 795 "renesas,rcar-gen3-hscif",
799 "renesas, 796 "renesas,hscif";
800 reg = <0 0xe6550000 0 797 reg = <0 0xe6550000 0 0x60>;
801 interrupts = <GIC_SPI 798 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
802 clocks = <&cpg CPG_MOD 799 clocks = <&cpg CPG_MOD 519>,
803 <&cpg CPG_COR 800 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
804 <&scif_clk>; 801 <&scif_clk>;
805 clock-names = "fck", " 802 clock-names = "fck", "brg_int", "scif_clk";
806 dmas = <&dmac1 0x33>, 803 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
807 <&dmac2 0x33>, 804 <&dmac2 0x33>, <&dmac2 0x32>;
808 dma-names = "tx", "rx" 805 dma-names = "tx", "rx", "tx", "rx";
809 power-domains = <&sysc 806 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
810 resets = <&cpg 519>; 807 resets = <&cpg 519>;
811 status = "disabled"; 808 status = "disabled";
812 }; 809 };
813 810
814 hscif2: serial@e6560000 { 811 hscif2: serial@e6560000 {
815 compatible = "renesas, 812 compatible = "renesas,hscif-r8a7796",
816 "renesas, 813 "renesas,rcar-gen3-hscif",
817 "renesas, 814 "renesas,hscif";
818 reg = <0 0xe6560000 0 815 reg = <0 0xe6560000 0 0x60>;
819 interrupts = <GIC_SPI 816 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
820 clocks = <&cpg CPG_MOD 817 clocks = <&cpg CPG_MOD 518>,
821 <&cpg CPG_COR 818 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
822 <&scif_clk>; 819 <&scif_clk>;
823 clock-names = "fck", " 820 clock-names = "fck", "brg_int", "scif_clk";
824 dmas = <&dmac1 0x35>, 821 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
825 <&dmac2 0x35>, 822 <&dmac2 0x35>, <&dmac2 0x34>;
826 dma-names = "tx", "rx" 823 dma-names = "tx", "rx", "tx", "rx";
827 power-domains = <&sysc 824 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
828 resets = <&cpg 518>; 825 resets = <&cpg 518>;
829 status = "disabled"; 826 status = "disabled";
830 }; 827 };
831 828
832 hscif3: serial@e66a0000 { 829 hscif3: serial@e66a0000 {
833 compatible = "renesas, 830 compatible = "renesas,hscif-r8a7796",
834 "renesas, 831 "renesas,rcar-gen3-hscif",
835 "renesas, 832 "renesas,hscif";
836 reg = <0 0xe66a0000 0 833 reg = <0 0xe66a0000 0 0x60>;
837 interrupts = <GIC_SPI 834 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
838 clocks = <&cpg CPG_MOD 835 clocks = <&cpg CPG_MOD 517>,
839 <&cpg CPG_COR 836 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
840 <&scif_clk>; 837 <&scif_clk>;
841 clock-names = "fck", " 838 clock-names = "fck", "brg_int", "scif_clk";
842 dmas = <&dmac0 0x37>, 839 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
843 dma-names = "tx", "rx" 840 dma-names = "tx", "rx";
844 power-domains = <&sysc 841 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
845 resets = <&cpg 517>; 842 resets = <&cpg 517>;
846 status = "disabled"; 843 status = "disabled";
847 }; 844 };
848 845
849 hscif4: serial@e66b0000 { 846 hscif4: serial@e66b0000 {
850 compatible = "renesas, 847 compatible = "renesas,hscif-r8a7796",
851 "renesas, 848 "renesas,rcar-gen3-hscif",
852 "renesas, 849 "renesas,hscif";
853 reg = <0 0xe66b0000 0 850 reg = <0 0xe66b0000 0 0x60>;
854 interrupts = <GIC_SPI 851 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
855 clocks = <&cpg CPG_MOD 852 clocks = <&cpg CPG_MOD 516>,
856 <&cpg CPG_COR 853 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
857 <&scif_clk>; 854 <&scif_clk>;
858 clock-names = "fck", " 855 clock-names = "fck", "brg_int", "scif_clk";
859 dmas = <&dmac0 0x39>, 856 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
860 dma-names = "tx", "rx" 857 dma-names = "tx", "rx";
861 power-domains = <&sysc 858 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
862 resets = <&cpg 516>; 859 resets = <&cpg 516>;
863 status = "disabled"; 860 status = "disabled";
864 }; 861 };
865 862
866 hsusb: usb@e6590000 { 863 hsusb: usb@e6590000 {
867 compatible = "renesas, 864 compatible = "renesas,usbhs-r8a7796",
868 "renesas, 865 "renesas,rcar-gen3-usbhs";
869 reg = <0 0xe6590000 0 866 reg = <0 0xe6590000 0 0x200>;
870 interrupts = <GIC_SPI 867 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
871 clocks = <&cpg CPG_MOD 868 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
872 dmas = <&usb_dmac0 0>, 869 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
873 <&usb_dmac1 0>, 870 <&usb_dmac1 0>, <&usb_dmac1 1>;
874 dma-names = "ch0", "ch 871 dma-names = "ch0", "ch1", "ch2", "ch3";
875 renesas,buswait = <11> 872 renesas,buswait = <11>;
876 phys = <&usb2_phy0 3>; 873 phys = <&usb2_phy0 3>;
877 phy-names = "usb"; 874 phy-names = "usb";
878 power-domains = <&sysc 875 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
879 resets = <&cpg 704>, < 876 resets = <&cpg 704>, <&cpg 703>;
880 status = "disabled"; 877 status = "disabled";
881 }; 878 };
882 879
883 usb_dmac0: dma-controller@e65a 880 usb_dmac0: dma-controller@e65a0000 {
884 compatible = "renesas, 881 compatible = "renesas,r8a7796-usb-dmac",
885 "renesas, 882 "renesas,usb-dmac";
886 reg = <0 0xe65a0000 0 883 reg = <0 0xe65a0000 0 0x100>;
887 interrupts = <GIC_SPI 884 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
888 <GIC_SPI 885 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
889 interrupt-names = "ch0 886 interrupt-names = "ch0", "ch1";
890 clocks = <&cpg CPG_MOD 887 clocks = <&cpg CPG_MOD 330>;
891 power-domains = <&sysc 888 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
892 resets = <&cpg 330>; 889 resets = <&cpg 330>;
893 #dma-cells = <1>; 890 #dma-cells = <1>;
894 dma-channels = <2>; 891 dma-channels = <2>;
895 }; 892 };
896 893
897 usb_dmac1: dma-controller@e65b 894 usb_dmac1: dma-controller@e65b0000 {
898 compatible = "renesas, 895 compatible = "renesas,r8a7796-usb-dmac",
899 "renesas, 896 "renesas,usb-dmac";
900 reg = <0 0xe65b0000 0 897 reg = <0 0xe65b0000 0 0x100>;
901 interrupts = <GIC_SPI 898 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
902 <GIC_SPI 899 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
903 interrupt-names = "ch0 900 interrupt-names = "ch0", "ch1";
904 clocks = <&cpg CPG_MOD 901 clocks = <&cpg CPG_MOD 331>;
905 power-domains = <&sysc 902 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
906 resets = <&cpg 331>; 903 resets = <&cpg 331>;
907 #dma-cells = <1>; 904 #dma-cells = <1>;
908 dma-channels = <2>; 905 dma-channels = <2>;
909 }; 906 };
910 907
911 usb3_phy0: usb-phy@e65ee000 { 908 usb3_phy0: usb-phy@e65ee000 {
912 compatible = "renesas, 909 compatible = "renesas,r8a7796-usb3-phy",
913 "renesas, 910 "renesas,rcar-gen3-usb3-phy";
914 reg = <0 0xe65ee000 0 911 reg = <0 0xe65ee000 0 0x90>;
915 clocks = <&cpg CPG_MOD 912 clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>,
916 <&usb_extal_c 913 <&usb_extal_clk>;
917 clock-names = "usb3-if 914 clock-names = "usb3-if", "usb3s_clk", "usb_extal";
918 power-domains = <&sysc 915 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
919 resets = <&cpg 328>; 916 resets = <&cpg 328>;
920 #phy-cells = <0>; 917 #phy-cells = <0>;
921 status = "disabled"; 918 status = "disabled";
922 }; 919 };
923 920
924 arm_cc630p: crypto@e6601000 { 921 arm_cc630p: crypto@e6601000 {
925 compatible = "arm,cryp 922 compatible = "arm,cryptocell-630p-ree";
926 interrupts = <GIC_SPI 923 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
927 reg = <0x0 0xe6601000 924 reg = <0x0 0xe6601000 0 0x1000>;
928 clocks = <&cpg CPG_MOD 925 clocks = <&cpg CPG_MOD 229>;
929 resets = <&cpg 229>; 926 resets = <&cpg 229>;
930 power-domains = <&sysc 927 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
931 }; 928 };
932 929
933 dmac0: dma-controller@e6700000 930 dmac0: dma-controller@e6700000 {
934 compatible = "renesas, 931 compatible = "renesas,dmac-r8a7796",
935 "renesas, 932 "renesas,rcar-dmac";
936 reg = <0 0xe6700000 0 933 reg = <0 0xe6700000 0 0x10000>;
937 interrupts = <GIC_SPI 934 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
938 <GIC_SPI 935 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
939 <GIC_SPI 936 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
940 <GIC_SPI 937 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
941 <GIC_SPI 938 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
942 <GIC_SPI 939 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
943 <GIC_SPI 940 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
944 <GIC_SPI 941 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
945 <GIC_SPI 942 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
946 <GIC_SPI 943 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
947 <GIC_SPI 944 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
948 <GIC_SPI 945 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
949 <GIC_SPI 946 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
950 <GIC_SPI 947 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
951 <GIC_SPI 948 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
952 <GIC_SPI 949 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
953 <GIC_SPI 950 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
954 interrupt-names = "err 951 interrupt-names = "error",
955 "ch0", 952 "ch0", "ch1", "ch2", "ch3",
956 "ch4", 953 "ch4", "ch5", "ch6", "ch7",
957 "ch8", 954 "ch8", "ch9", "ch10", "ch11",
958 "ch12" 955 "ch12", "ch13", "ch14", "ch15";
959 clocks = <&cpg CPG_MOD 956 clocks = <&cpg CPG_MOD 219>;
960 clock-names = "fck"; 957 clock-names = "fck";
961 power-domains = <&sysc 958 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
962 resets = <&cpg 219>; 959 resets = <&cpg 219>;
963 #dma-cells = <1>; 960 #dma-cells = <1>;
964 dma-channels = <16>; 961 dma-channels = <16>;
965 iommus = <&ipmmu_ds0 0 962 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
966 <&ipmmu_ds0 2>, 963 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
967 <&ipmmu_ds0 4>, 964 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
968 <&ipmmu_ds0 6>, 965 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
969 <&ipmmu_ds0 8>, 966 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
970 <&ipmmu_ds0 10> 967 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
971 <&ipmmu_ds0 12> 968 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
972 <&ipmmu_ds0 14> 969 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
973 }; 970 };
974 971
975 dmac1: dma-controller@e7300000 972 dmac1: dma-controller@e7300000 {
976 compatible = "renesas, 973 compatible = "renesas,dmac-r8a7796",
977 "renesas, 974 "renesas,rcar-dmac";
978 reg = <0 0xe7300000 0 975 reg = <0 0xe7300000 0 0x10000>;
979 interrupts = <GIC_SPI 976 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
980 <GIC_SPI 977 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
981 <GIC_SPI 978 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
982 <GIC_SPI 979 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
983 <GIC_SPI 980 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
984 <GIC_SPI 981 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
985 <GIC_SPI 982 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
986 <GIC_SPI 983 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
987 <GIC_SPI 984 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
988 <GIC_SPI 985 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
989 <GIC_SPI 986 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
990 <GIC_SPI 987 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
991 <GIC_SPI 988 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
992 <GIC_SPI 989 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
993 <GIC_SPI 990 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
994 <GIC_SPI 991 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
995 <GIC_SPI 992 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
996 interrupt-names = "err 993 interrupt-names = "error",
997 "ch0", 994 "ch0", "ch1", "ch2", "ch3",
998 "ch4", 995 "ch4", "ch5", "ch6", "ch7",
999 "ch8", 996 "ch8", "ch9", "ch10", "ch11",
1000 "ch12 997 "ch12", "ch13", "ch14", "ch15";
1001 clocks = <&cpg CPG_MO 998 clocks = <&cpg CPG_MOD 218>;
1002 clock-names = "fck"; 999 clock-names = "fck";
1003 power-domains = <&sys 1000 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1004 resets = <&cpg 218>; 1001 resets = <&cpg 218>;
1005 #dma-cells = <1>; 1002 #dma-cells = <1>;
1006 dma-channels = <16>; 1003 dma-channels = <16>;
1007 iommus = <&ipmmu_ds1 1004 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
1008 <&ipmmu_ds1 2> 1005 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
1009 <&ipmmu_ds1 4> 1006 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
1010 <&ipmmu_ds1 6> 1007 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
1011 <&ipmmu_ds1 8> 1008 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
1012 <&ipmmu_ds1 10 1009 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
1013 <&ipmmu_ds1 12 1010 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
1014 <&ipmmu_ds1 14 1011 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
1015 }; 1012 };
1016 1013
1017 dmac2: dma-controller@e731000 1014 dmac2: dma-controller@e7310000 {
1018 compatible = "renesas 1015 compatible = "renesas,dmac-r8a7796",
1019 "renesas 1016 "renesas,rcar-dmac";
1020 reg = <0 0xe7310000 0 1017 reg = <0 0xe7310000 0 0x10000>;
1021 interrupts = <GIC_SPI 1018 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
1022 <GIC_SPI 1019 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
1023 <GIC_SPI 1020 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
1024 <GIC_SPI 1021 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
1025 <GIC_SPI 1022 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
1026 <GIC_SPI 1023 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
1027 <GIC_SPI 1024 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
1028 <GIC_SPI 1025 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
1029 <GIC_SPI 1026 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
1030 <GIC_SPI 1027 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
1031 <GIC_SPI 1028 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
1032 <GIC_SPI 1029 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
1033 <GIC_SPI 1030 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
1034 <GIC_SPI 1031 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
1035 <GIC_SPI 1032 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
1036 <GIC_SPI 1033 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
1037 <GIC_SPI 1034 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
1038 interrupt-names = "er 1035 interrupt-names = "error",
1039 "ch0" 1036 "ch0", "ch1", "ch2", "ch3",
1040 "ch4" 1037 "ch4", "ch5", "ch6", "ch7",
1041 "ch8" 1038 "ch8", "ch9", "ch10", "ch11",
1042 "ch12 1039 "ch12", "ch13", "ch14", "ch15";
1043 clocks = <&cpg CPG_MO 1040 clocks = <&cpg CPG_MOD 217>;
1044 clock-names = "fck"; 1041 clock-names = "fck";
1045 power-domains = <&sys 1042 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1046 resets = <&cpg 217>; 1043 resets = <&cpg 217>;
1047 #dma-cells = <1>; 1044 #dma-cells = <1>;
1048 dma-channels = <16>; 1045 dma-channels = <16>;
1049 iommus = <&ipmmu_ds1 1046 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
1050 <&ipmmu_ds1 18 1047 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
1051 <&ipmmu_ds1 20 1048 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
1052 <&ipmmu_ds1 22 1049 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
1053 <&ipmmu_ds1 24 1050 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
1054 <&ipmmu_ds1 26 1051 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
1055 <&ipmmu_ds1 28 1052 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
1056 <&ipmmu_ds1 30 1053 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
1057 }; 1054 };
1058 1055
1059 ipmmu_ds0: iommu@e6740000 { 1056 ipmmu_ds0: iommu@e6740000 {
1060 compatible = "renesas 1057 compatible = "renesas,ipmmu-r8a7796";
1061 reg = <0 0xe6740000 0 1058 reg = <0 0xe6740000 0 0x1000>;
1062 renesas,ipmmu-main = 1059 renesas,ipmmu-main = <&ipmmu_mm 0>;
1063 power-domains = <&sys 1060 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1064 #iommu-cells = <1>; 1061 #iommu-cells = <1>;
1065 }; 1062 };
1066 1063
1067 ipmmu_ds1: iommu@e7740000 { 1064 ipmmu_ds1: iommu@e7740000 {
1068 compatible = "renesas 1065 compatible = "renesas,ipmmu-r8a7796";
1069 reg = <0 0xe7740000 0 1066 reg = <0 0xe7740000 0 0x1000>;
1070 renesas,ipmmu-main = 1067 renesas,ipmmu-main = <&ipmmu_mm 1>;
1071 power-domains = <&sys 1068 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1072 #iommu-cells = <1>; 1069 #iommu-cells = <1>;
1073 }; 1070 };
1074 1071
1075 ipmmu_hc: iommu@e6570000 { 1072 ipmmu_hc: iommu@e6570000 {
1076 compatible = "renesas 1073 compatible = "renesas,ipmmu-r8a7796";
1077 reg = <0 0xe6570000 0 1074 reg = <0 0xe6570000 0 0x1000>;
1078 renesas,ipmmu-main = 1075 renesas,ipmmu-main = <&ipmmu_mm 2>;
1079 power-domains = <&sys 1076 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1080 #iommu-cells = <1>; 1077 #iommu-cells = <1>;
1081 }; 1078 };
1082 1079
1083 ipmmu_ir: iommu@ff8b0000 { 1080 ipmmu_ir: iommu@ff8b0000 {
1084 compatible = "renesas 1081 compatible = "renesas,ipmmu-r8a7796";
1085 reg = <0 0xff8b0000 0 1082 reg = <0 0xff8b0000 0 0x1000>;
1086 renesas,ipmmu-main = 1083 renesas,ipmmu-main = <&ipmmu_mm 3>;
1087 power-domains = <&sys 1084 power-domains = <&sysc R8A7796_PD_A3IR>;
1088 #iommu-cells = <1>; 1085 #iommu-cells = <1>;
1089 }; 1086 };
1090 1087
1091 ipmmu_mm: iommu@e67b0000 { 1088 ipmmu_mm: iommu@e67b0000 {
1092 compatible = "renesas 1089 compatible = "renesas,ipmmu-r8a7796";
1093 reg = <0 0xe67b0000 0 1090 reg = <0 0xe67b0000 0 0x1000>;
1094 interrupts = <GIC_SPI 1091 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
1095 <GIC_SPI 1092 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
1096 power-domains = <&sys 1093 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1097 #iommu-cells = <1>; 1094 #iommu-cells = <1>;
1098 }; 1095 };
1099 1096
1100 ipmmu_mp: iommu@ec670000 { 1097 ipmmu_mp: iommu@ec670000 {
1101 compatible = "renesas 1098 compatible = "renesas,ipmmu-r8a7796";
1102 reg = <0 0xec670000 0 1099 reg = <0 0xec670000 0 0x1000>;
1103 renesas,ipmmu-main = 1100 renesas,ipmmu-main = <&ipmmu_mm 4>;
1104 power-domains = <&sys 1101 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1105 #iommu-cells = <1>; 1102 #iommu-cells = <1>;
1106 }; 1103 };
1107 1104
1108 ipmmu_pv0: iommu@fd800000 { 1105 ipmmu_pv0: iommu@fd800000 {
1109 compatible = "renesas 1106 compatible = "renesas,ipmmu-r8a7796";
1110 reg = <0 0xfd800000 0 1107 reg = <0 0xfd800000 0 0x1000>;
1111 renesas,ipmmu-main = 1108 renesas,ipmmu-main = <&ipmmu_mm 5>;
1112 power-domains = <&sys 1109 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1113 #iommu-cells = <1>; 1110 #iommu-cells = <1>;
1114 }; 1111 };
1115 1112
1116 ipmmu_pv1: iommu@fd950000 { 1113 ipmmu_pv1: iommu@fd950000 {
1117 compatible = "renesas 1114 compatible = "renesas,ipmmu-r8a7796";
1118 reg = <0 0xfd950000 0 1115 reg = <0 0xfd950000 0 0x1000>;
1119 renesas,ipmmu-main = 1116 renesas,ipmmu-main = <&ipmmu_mm 6>;
1120 power-domains = <&sys 1117 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1121 #iommu-cells = <1>; 1118 #iommu-cells = <1>;
1122 }; 1119 };
1123 1120
1124 ipmmu_rt: iommu@ffc80000 { 1121 ipmmu_rt: iommu@ffc80000 {
1125 compatible = "renesas 1122 compatible = "renesas,ipmmu-r8a7796";
1126 reg = <0 0xffc80000 0 1123 reg = <0 0xffc80000 0 0x1000>;
1127 renesas,ipmmu-main = 1124 renesas,ipmmu-main = <&ipmmu_mm 7>;
1128 power-domains = <&sys 1125 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1129 #iommu-cells = <1>; 1126 #iommu-cells = <1>;
1130 }; 1127 };
1131 1128
1132 ipmmu_vc0: iommu@fe6b0000 { 1129 ipmmu_vc0: iommu@fe6b0000 {
1133 compatible = "renesas 1130 compatible = "renesas,ipmmu-r8a7796";
1134 reg = <0 0xfe6b0000 0 1131 reg = <0 0xfe6b0000 0 0x1000>;
1135 renesas,ipmmu-main = 1132 renesas,ipmmu-main = <&ipmmu_mm 8>;
1136 power-domains = <&sys 1133 power-domains = <&sysc R8A7796_PD_A3VC>;
1137 #iommu-cells = <1>; 1134 #iommu-cells = <1>;
1138 }; 1135 };
1139 1136
1140 ipmmu_vi0: iommu@febd0000 { 1137 ipmmu_vi0: iommu@febd0000 {
1141 compatible = "renesas 1138 compatible = "renesas,ipmmu-r8a7796";
1142 reg = <0 0xfebd0000 0 1139 reg = <0 0xfebd0000 0 0x1000>;
1143 renesas,ipmmu-main = 1140 renesas,ipmmu-main = <&ipmmu_mm 9>;
1144 power-domains = <&sys 1141 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1145 #iommu-cells = <1>; 1142 #iommu-cells = <1>;
1146 }; 1143 };
1147 1144
1148 avb: ethernet@e6800000 { 1145 avb: ethernet@e6800000 {
1149 compatible = "renesas 1146 compatible = "renesas,etheravb-r8a7796",
1150 "renesas 1147 "renesas,etheravb-rcar-gen3";
1151 reg = <0 0xe6800000 0 1148 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
1152 interrupts = <GIC_SPI 1149 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
1153 <GIC_SPI 1150 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1154 <GIC_SPI 1151 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
1155 <GIC_SPI 1152 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
1156 <GIC_SPI 1153 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
1157 <GIC_SPI 1154 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
1158 <GIC_SPI 1155 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
1159 <GIC_SPI 1156 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
1160 <GIC_SPI 1157 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
1161 <GIC_SPI 1158 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
1162 <GIC_SPI 1159 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
1163 <GIC_SPI 1160 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
1164 <GIC_SPI 1161 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
1165 <GIC_SPI 1162 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
1166 <GIC_SPI 1163 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
1167 <GIC_SPI 1164 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
1168 <GIC_SPI 1165 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
1169 <GIC_SPI 1166 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
1170 <GIC_SPI 1167 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
1171 <GIC_SPI 1168 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
1172 <GIC_SPI 1169 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
1173 <GIC_SPI 1170 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
1174 <GIC_SPI 1171 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
1175 <GIC_SPI 1172 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
1176 <GIC_SPI 1173 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
1177 interrupt-names = "ch 1174 interrupt-names = "ch0", "ch1", "ch2", "ch3",
1178 "ch 1175 "ch4", "ch5", "ch6", "ch7",
1179 "ch 1176 "ch8", "ch9", "ch10", "ch11",
1180 "ch 1177 "ch12", "ch13", "ch14", "ch15",
1181 "ch 1178 "ch16", "ch17", "ch18", "ch19",
1182 "ch 1179 "ch20", "ch21", "ch22", "ch23",
1183 "ch 1180 "ch24";
1184 clocks = <&cpg CPG_MO 1181 clocks = <&cpg CPG_MOD 812>;
1185 clock-names = "fck"; 1182 clock-names = "fck";
1186 power-domains = <&sys 1183 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1187 resets = <&cpg 812>; 1184 resets = <&cpg 812>;
1188 phy-mode = "rgmii"; 1185 phy-mode = "rgmii";
1189 rx-internal-delay-ps 1186 rx-internal-delay-ps = <0>;
1190 tx-internal-delay-ps 1187 tx-internal-delay-ps = <0>;
1191 iommus = <&ipmmu_ds0 1188 iommus = <&ipmmu_ds0 16>;
1192 #address-cells = <1>; 1189 #address-cells = <1>;
1193 #size-cells = <0>; 1190 #size-cells = <0>;
1194 status = "disabled"; 1191 status = "disabled";
1195 }; 1192 };
1196 1193
1197 can0: can@e6c30000 { 1194 can0: can@e6c30000 {
1198 compatible = "renesas 1195 compatible = "renesas,can-r8a7796",
1199 "renesas 1196 "renesas,rcar-gen3-can";
1200 reg = <0 0xe6c30000 0 1197 reg = <0 0xe6c30000 0 0x1000>;
1201 interrupts = <GIC_SPI 1198 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
1202 clocks = <&cpg CPG_MO 1199 clocks = <&cpg CPG_MOD 916>,
1203 <&cpg CPG_CORE 1200 <&cpg CPG_CORE R8A7796_CLK_CANFD>,
1204 <&can_clk>; 1201 <&can_clk>;
1205 clock-names = "clkp1" 1202 clock-names = "clkp1", "clkp2", "can_clk";
1206 assigned-clocks = <&c 1203 assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>;
1207 assigned-clock-rates 1204 assigned-clock-rates = <40000000>;
1208 power-domains = <&sys 1205 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1209 resets = <&cpg 916>; 1206 resets = <&cpg 916>;
1210 status = "disabled"; 1207 status = "disabled";
1211 }; 1208 };
1212 1209
1213 can1: can@e6c38000 { 1210 can1: can@e6c38000 {
1214 compatible = "renesas 1211 compatible = "renesas,can-r8a7796",
1215 "renesas 1212 "renesas,rcar-gen3-can";
1216 reg = <0 0xe6c38000 0 1213 reg = <0 0xe6c38000 0 0x1000>;
1217 interrupts = <GIC_SPI 1214 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
1218 clocks = <&cpg CPG_MO 1215 clocks = <&cpg CPG_MOD 915>,
1219 <&cpg CPG_CORE 1216 <&cpg CPG_CORE R8A7796_CLK_CANFD>,
1220 <&can_clk>; 1217 <&can_clk>;
1221 clock-names = "clkp1" 1218 clock-names = "clkp1", "clkp2", "can_clk";
1222 assigned-clocks = <&c 1219 assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>;
1223 assigned-clock-rates 1220 assigned-clock-rates = <40000000>;
1224 power-domains = <&sys 1221 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1225 resets = <&cpg 915>; 1222 resets = <&cpg 915>;
1226 status = "disabled"; 1223 status = "disabled";
1227 }; 1224 };
1228 1225
1229 canfd: can@e66c0000 { 1226 canfd: can@e66c0000 {
1230 compatible = "renesas 1227 compatible = "renesas,r8a7796-canfd",
1231 "renesas 1228 "renesas,rcar-gen3-canfd";
1232 reg = <0 0xe66c0000 0 1229 reg = <0 0xe66c0000 0 0x8000>;
1233 interrupts = <GIC_SPI 1230 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
1234 <GIC_SPI 3 1231 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1235 interrupt-names = "ch 1232 interrupt-names = "ch_int", "g_int";
1236 clocks = <&cpg CPG_MO 1233 clocks = <&cpg CPG_MOD 914>,
1237 <&cpg CPG_CORE 1234 <&cpg CPG_CORE R8A7796_CLK_CANFD>,
1238 <&can_clk>; 1235 <&can_clk>;
1239 clock-names = "fck", 1236 clock-names = "fck", "canfd", "can_clk";
1240 assigned-clocks = <&c 1237 assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>;
1241 assigned-clock-rates 1238 assigned-clock-rates = <40000000>;
1242 power-domains = <&sys 1239 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1243 resets = <&cpg 914>; 1240 resets = <&cpg 914>;
1244 status = "disabled"; 1241 status = "disabled";
1245 1242
1246 channel0 { 1243 channel0 {
1247 status = "dis 1244 status = "disabled";
1248 }; 1245 };
1249 1246
1250 channel1 { 1247 channel1 {
1251 status = "dis 1248 status = "disabled";
1252 }; 1249 };
1253 }; 1250 };
1254 1251
1255 pwm0: pwm@e6e30000 { 1252 pwm0: pwm@e6e30000 {
1256 compatible = "renesas 1253 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
1257 reg = <0 0xe6e30000 0 1254 reg = <0 0xe6e30000 0 8>;
1258 #pwm-cells = <2>; 1255 #pwm-cells = <2>;
1259 clocks = <&cpg CPG_MO 1256 clocks = <&cpg CPG_MOD 523>;
1260 resets = <&cpg 523>; 1257 resets = <&cpg 523>;
1261 power-domains = <&sys 1258 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1262 status = "disabled"; 1259 status = "disabled";
1263 }; 1260 };
1264 1261
1265 pwm1: pwm@e6e31000 { 1262 pwm1: pwm@e6e31000 {
1266 compatible = "renesas 1263 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
1267 reg = <0 0xe6e31000 0 1264 reg = <0 0xe6e31000 0 8>;
1268 #pwm-cells = <2>; 1265 #pwm-cells = <2>;
1269 clocks = <&cpg CPG_MO 1266 clocks = <&cpg CPG_MOD 523>;
1270 resets = <&cpg 523>; 1267 resets = <&cpg 523>;
1271 power-domains = <&sys 1268 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1272 status = "disabled"; 1269 status = "disabled";
1273 }; 1270 };
1274 1271
1275 pwm2: pwm@e6e32000 { 1272 pwm2: pwm@e6e32000 {
1276 compatible = "renesas 1273 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
1277 reg = <0 0xe6e32000 0 1274 reg = <0 0xe6e32000 0 8>;
1278 #pwm-cells = <2>; 1275 #pwm-cells = <2>;
1279 clocks = <&cpg CPG_MO 1276 clocks = <&cpg CPG_MOD 523>;
1280 resets = <&cpg 523>; 1277 resets = <&cpg 523>;
1281 power-domains = <&sys 1278 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1282 status = "disabled"; 1279 status = "disabled";
1283 }; 1280 };
1284 1281
1285 pwm3: pwm@e6e33000 { 1282 pwm3: pwm@e6e33000 {
1286 compatible = "renesas 1283 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
1287 reg = <0 0xe6e33000 0 1284 reg = <0 0xe6e33000 0 8>;
1288 #pwm-cells = <2>; 1285 #pwm-cells = <2>;
1289 clocks = <&cpg CPG_MO 1286 clocks = <&cpg CPG_MOD 523>;
1290 resets = <&cpg 523>; 1287 resets = <&cpg 523>;
1291 power-domains = <&sys 1288 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1292 status = "disabled"; 1289 status = "disabled";
1293 }; 1290 };
1294 1291
1295 pwm4: pwm@e6e34000 { 1292 pwm4: pwm@e6e34000 {
1296 compatible = "renesas 1293 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
1297 reg = <0 0xe6e34000 0 1294 reg = <0 0xe6e34000 0 8>;
1298 #pwm-cells = <2>; 1295 #pwm-cells = <2>;
1299 clocks = <&cpg CPG_MO 1296 clocks = <&cpg CPG_MOD 523>;
1300 resets = <&cpg 523>; 1297 resets = <&cpg 523>;
1301 power-domains = <&sys 1298 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1302 status = "disabled"; 1299 status = "disabled";
1303 }; 1300 };
1304 1301
1305 pwm5: pwm@e6e35000 { 1302 pwm5: pwm@e6e35000 {
1306 compatible = "renesas 1303 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
1307 reg = <0 0xe6e35000 0 1304 reg = <0 0xe6e35000 0 8>;
1308 #pwm-cells = <2>; 1305 #pwm-cells = <2>;
1309 clocks = <&cpg CPG_MO 1306 clocks = <&cpg CPG_MOD 523>;
1310 resets = <&cpg 523>; 1307 resets = <&cpg 523>;
1311 power-domains = <&sys 1308 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1312 status = "disabled"; 1309 status = "disabled";
1313 }; 1310 };
1314 1311
1315 pwm6: pwm@e6e36000 { 1312 pwm6: pwm@e6e36000 {
1316 compatible = "renesas 1313 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
1317 reg = <0 0xe6e36000 0 1314 reg = <0 0xe6e36000 0 8>;
1318 #pwm-cells = <2>; 1315 #pwm-cells = <2>;
1319 clocks = <&cpg CPG_MO 1316 clocks = <&cpg CPG_MOD 523>;
1320 resets = <&cpg 523>; 1317 resets = <&cpg 523>;
1321 power-domains = <&sys 1318 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1322 status = "disabled"; 1319 status = "disabled";
1323 }; 1320 };
1324 1321
1325 scif0: serial@e6e60000 { 1322 scif0: serial@e6e60000 {
1326 compatible = "renesas 1323 compatible = "renesas,scif-r8a7796",
1327 "renesas 1324 "renesas,rcar-gen3-scif", "renesas,scif";
1328 reg = <0 0xe6e60000 0 1325 reg = <0 0xe6e60000 0 64>;
1329 interrupts = <GIC_SPI 1326 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
1330 clocks = <&cpg CPG_MO 1327 clocks = <&cpg CPG_MOD 207>,
1331 <&cpg CPG_CO 1328 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
1332 <&scif_clk>; 1329 <&scif_clk>;
1333 clock-names = "fck", 1330 clock-names = "fck", "brg_int", "scif_clk";
1334 dmas = <&dmac1 0x51>, 1331 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1335 <&dmac2 0x51>, 1332 <&dmac2 0x51>, <&dmac2 0x50>;
1336 dma-names = "tx", "rx 1333 dma-names = "tx", "rx", "tx", "rx";
1337 power-domains = <&sys 1334 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1338 resets = <&cpg 207>; 1335 resets = <&cpg 207>;
1339 status = "disabled"; 1336 status = "disabled";
1340 }; 1337 };
1341 1338
1342 scif1: serial@e6e68000 { 1339 scif1: serial@e6e68000 {
1343 compatible = "renesas 1340 compatible = "renesas,scif-r8a7796",
1344 "renesas 1341 "renesas,rcar-gen3-scif", "renesas,scif";
1345 reg = <0 0xe6e68000 0 1342 reg = <0 0xe6e68000 0 64>;
1346 interrupts = <GIC_SPI 1343 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
1347 clocks = <&cpg CPG_MO 1344 clocks = <&cpg CPG_MOD 206>,
1348 <&cpg CPG_CO 1345 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
1349 <&scif_clk>; 1346 <&scif_clk>;
1350 clock-names = "fck", 1347 clock-names = "fck", "brg_int", "scif_clk";
1351 dmas = <&dmac1 0x53>, 1348 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1352 <&dmac2 0x53>, 1349 <&dmac2 0x53>, <&dmac2 0x52>;
1353 dma-names = "tx", "rx 1350 dma-names = "tx", "rx", "tx", "rx";
1354 power-domains = <&sys 1351 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1355 resets = <&cpg 206>; 1352 resets = <&cpg 206>;
1356 status = "disabled"; 1353 status = "disabled";
1357 }; 1354 };
1358 1355
1359 scif2: serial@e6e88000 { 1356 scif2: serial@e6e88000 {
1360 compatible = "renesas 1357 compatible = "renesas,scif-r8a7796",
1361 "renesas 1358 "renesas,rcar-gen3-scif", "renesas,scif";
1362 reg = <0 0xe6e88000 0 1359 reg = <0 0xe6e88000 0 64>;
1363 interrupts = <GIC_SPI 1360 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
1364 clocks = <&cpg CPG_MO 1361 clocks = <&cpg CPG_MOD 310>,
1365 <&cpg CPG_CO 1362 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
1366 <&scif_clk>; 1363 <&scif_clk>;
1367 clock-names = "fck", 1364 clock-names = "fck", "brg_int", "scif_clk";
1368 dmas = <&dmac1 0x13>, 1365 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1369 <&dmac2 0x13>, 1366 <&dmac2 0x13>, <&dmac2 0x12>;
1370 dma-names = "tx", "rx 1367 dma-names = "tx", "rx", "tx", "rx";
1371 power-domains = <&sys 1368 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1372 resets = <&cpg 310>; 1369 resets = <&cpg 310>;
1373 status = "disabled"; 1370 status = "disabled";
1374 }; 1371 };
1375 1372
1376 scif3: serial@e6c50000 { 1373 scif3: serial@e6c50000 {
1377 compatible = "renesas 1374 compatible = "renesas,scif-r8a7796",
1378 "renesas 1375 "renesas,rcar-gen3-scif", "renesas,scif";
1379 reg = <0 0xe6c50000 0 1376 reg = <0 0xe6c50000 0 64>;
1380 interrupts = <GIC_SPI 1377 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1381 clocks = <&cpg CPG_MO 1378 clocks = <&cpg CPG_MOD 204>,
1382 <&cpg CPG_CO 1379 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
1383 <&scif_clk>; 1380 <&scif_clk>;
1384 clock-names = "fck", 1381 clock-names = "fck", "brg_int", "scif_clk";
1385 dmas = <&dmac0 0x57>, 1382 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1386 dma-names = "tx", "rx 1383 dma-names = "tx", "rx";
1387 power-domains = <&sys 1384 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1388 resets = <&cpg 204>; 1385 resets = <&cpg 204>;
1389 status = "disabled"; 1386 status = "disabled";
1390 }; 1387 };
1391 1388
1392 scif4: serial@e6c40000 { 1389 scif4: serial@e6c40000 {
1393 compatible = "renesas 1390 compatible = "renesas,scif-r8a7796",
1394 "renesas 1391 "renesas,rcar-gen3-scif", "renesas,scif";
1395 reg = <0 0xe6c40000 0 1392 reg = <0 0xe6c40000 0 64>;
1396 interrupts = <GIC_SPI 1393 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1397 clocks = <&cpg CPG_MO 1394 clocks = <&cpg CPG_MOD 203>,
1398 <&cpg CPG_CO 1395 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
1399 <&scif_clk>; 1396 <&scif_clk>;
1400 clock-names = "fck", 1397 clock-names = "fck", "brg_int", "scif_clk";
1401 dmas = <&dmac0 0x59>, 1398 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1402 dma-names = "tx", "rx 1399 dma-names = "tx", "rx";
1403 power-domains = <&sys 1400 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1404 resets = <&cpg 203>; 1401 resets = <&cpg 203>;
1405 status = "disabled"; 1402 status = "disabled";
1406 }; 1403 };
1407 1404
1408 scif5: serial@e6f30000 { 1405 scif5: serial@e6f30000 {
1409 compatible = "renesas 1406 compatible = "renesas,scif-r8a7796",
1410 "renesas 1407 "renesas,rcar-gen3-scif", "renesas,scif";
1411 reg = <0 0xe6f30000 0 1408 reg = <0 0xe6f30000 0 64>;
1412 interrupts = <GIC_SPI 1409 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1413 clocks = <&cpg CPG_MO 1410 clocks = <&cpg CPG_MOD 202>,
1414 <&cpg CPG_CO 1411 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
1415 <&scif_clk>; 1412 <&scif_clk>;
1416 clock-names = "fck", 1413 clock-names = "fck", "brg_int", "scif_clk";
1417 dmas = <&dmac1 0x5b>, 1414 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
1418 <&dmac2 0x5b>, 1415 <&dmac2 0x5b>, <&dmac2 0x5a>;
1419 dma-names = "tx", "rx 1416 dma-names = "tx", "rx", "tx", "rx";
1420 power-domains = <&sys 1417 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1421 resets = <&cpg 202>; 1418 resets = <&cpg 202>;
1422 status = "disabled"; 1419 status = "disabled";
1423 }; 1420 };
1424 1421
1425 tpu: pwm@e6e80000 { 1422 tpu: pwm@e6e80000 {
1426 compatible = "renesas 1423 compatible = "renesas,tpu-r8a7796", "renesas,tpu";
1427 reg = <0 0xe6e80000 0 1424 reg = <0 0xe6e80000 0 0x148>;
1428 interrupts = <GIC_SPI 1425 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
1429 clocks = <&cpg CPG_MO 1426 clocks = <&cpg CPG_MOD 304>;
1430 power-domains = <&sys 1427 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1431 resets = <&cpg 304>; 1428 resets = <&cpg 304>;
1432 #pwm-cells = <3>; 1429 #pwm-cells = <3>;
1433 status = "disabled"; 1430 status = "disabled";
1434 }; 1431 };
1435 1432
1436 msiof0: spi@e6e90000 { 1433 msiof0: spi@e6e90000 {
1437 compatible = "renesas 1434 compatible = "renesas,msiof-r8a7796",
1438 "renesas 1435 "renesas,rcar-gen3-msiof";
1439 reg = <0 0xe6e90000 0 1436 reg = <0 0xe6e90000 0 0x0064>;
1440 interrupts = <GIC_SPI 1437 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1441 clocks = <&cpg CPG_MO 1438 clocks = <&cpg CPG_MOD 211>;
1442 dmas = <&dmac1 0x41>, 1439 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1443 <&dmac2 0x41>, 1440 <&dmac2 0x41>, <&dmac2 0x40>;
1444 dma-names = "tx", "rx 1441 dma-names = "tx", "rx", "tx", "rx";
1445 power-domains = <&sys 1442 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1446 resets = <&cpg 211>; 1443 resets = <&cpg 211>;
1447 #address-cells = <1>; 1444 #address-cells = <1>;
1448 #size-cells = <0>; 1445 #size-cells = <0>;
1449 status = "disabled"; 1446 status = "disabled";
1450 }; 1447 };
1451 1448
1452 msiof1: spi@e6ea0000 { 1449 msiof1: spi@e6ea0000 {
1453 compatible = "renesas 1450 compatible = "renesas,msiof-r8a7796",
1454 "renesas 1451 "renesas,rcar-gen3-msiof";
1455 reg = <0 0xe6ea0000 0 1452 reg = <0 0xe6ea0000 0 0x0064>;
1456 interrupts = <GIC_SPI 1453 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1457 clocks = <&cpg CPG_MO 1454 clocks = <&cpg CPG_MOD 210>;
1458 dmas = <&dmac1 0x43>, 1455 dmas = <&dmac1 0x43>, <&dmac1 0x42>,
1459 <&dmac2 0x43>, 1456 <&dmac2 0x43>, <&dmac2 0x42>;
1460 dma-names = "tx", "rx 1457 dma-names = "tx", "rx", "tx", "rx";
1461 power-domains = <&sys 1458 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1462 resets = <&cpg 210>; 1459 resets = <&cpg 210>;
1463 #address-cells = <1>; 1460 #address-cells = <1>;
1464 #size-cells = <0>; 1461 #size-cells = <0>;
1465 status = "disabled"; 1462 status = "disabled";
1466 }; 1463 };
1467 1464
1468 msiof2: spi@e6c00000 { 1465 msiof2: spi@e6c00000 {
1469 compatible = "renesas 1466 compatible = "renesas,msiof-r8a7796",
1470 "renesas 1467 "renesas,rcar-gen3-msiof";
1471 reg = <0 0xe6c00000 0 1468 reg = <0 0xe6c00000 0 0x0064>;
1472 interrupts = <GIC_SPI 1469 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1473 clocks = <&cpg CPG_MO 1470 clocks = <&cpg CPG_MOD 209>;
1474 dmas = <&dmac0 0x45>, 1471 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1475 dma-names = "tx", "rx 1472 dma-names = "tx", "rx";
1476 power-domains = <&sys 1473 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1477 resets = <&cpg 209>; 1474 resets = <&cpg 209>;
1478 #address-cells = <1>; 1475 #address-cells = <1>;
1479 #size-cells = <0>; 1476 #size-cells = <0>;
1480 status = "disabled"; 1477 status = "disabled";
1481 }; 1478 };
1482 1479
1483 msiof3: spi@e6c10000 { 1480 msiof3: spi@e6c10000 {
1484 compatible = "renesas 1481 compatible = "renesas,msiof-r8a7796",
1485 "renesas 1482 "renesas,rcar-gen3-msiof";
1486 reg = <0 0xe6c10000 0 1483 reg = <0 0xe6c10000 0 0x0064>;
1487 interrupts = <GIC_SPI 1484 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1488 clocks = <&cpg CPG_MO 1485 clocks = <&cpg CPG_MOD 208>;
1489 dmas = <&dmac0 0x47>, 1486 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1490 dma-names = "tx", "rx 1487 dma-names = "tx", "rx";
1491 power-domains = <&sys 1488 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1492 resets = <&cpg 208>; 1489 resets = <&cpg 208>;
1493 #address-cells = <1>; 1490 #address-cells = <1>;
1494 #size-cells = <0>; 1491 #size-cells = <0>;
1495 status = "disabled"; 1492 status = "disabled";
1496 }; 1493 };
1497 1494
1498 vin0: video@e6ef0000 { 1495 vin0: video@e6ef0000 {
1499 compatible = "renesas 1496 compatible = "renesas,vin-r8a7796";
1500 reg = <0 0xe6ef0000 0 1497 reg = <0 0xe6ef0000 0 0x1000>;
1501 interrupts = <GIC_SPI 1498 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
1502 clocks = <&cpg CPG_MO 1499 clocks = <&cpg CPG_MOD 811>;
1503 power-domains = <&sys 1500 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1504 resets = <&cpg 811>; 1501 resets = <&cpg 811>;
1505 renesas,id = <0>; 1502 renesas,id = <0>;
1506 status = "disabled"; 1503 status = "disabled";
1507 1504
1508 ports { 1505 ports {
1509 #address-cell 1506 #address-cells = <1>;
1510 #size-cells = 1507 #size-cells = <0>;
1511 1508
1512 port@1 { 1509 port@1 {
1513 #addr 1510 #address-cells = <1>;
1514 #size 1511 #size-cells = <0>;
1515 1512
1516 reg = 1513 reg = <1>;
1517 1514
1518 vin0c 1515 vin0csi20: endpoint@0 {
1519 1516 reg = <0>;
1520 1517 remote-endpoint = <&csi20vin0>;
1521 }; 1518 };
1522 vin0c 1519 vin0csi40: endpoint@2 {
1523 1520 reg = <2>;
1524 1521 remote-endpoint = <&csi40vin0>;
1525 }; 1522 };
1526 }; 1523 };
1527 }; 1524 };
1528 }; 1525 };
1529 1526
1530 vin1: video@e6ef1000 { 1527 vin1: video@e6ef1000 {
1531 compatible = "renesas 1528 compatible = "renesas,vin-r8a7796";
1532 reg = <0 0xe6ef1000 0 1529 reg = <0 0xe6ef1000 0 0x1000>;
1533 interrupts = <GIC_SPI 1530 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
1534 clocks = <&cpg CPG_MO 1531 clocks = <&cpg CPG_MOD 810>;
1535 power-domains = <&sys 1532 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1536 resets = <&cpg 810>; 1533 resets = <&cpg 810>;
1537 renesas,id = <1>; 1534 renesas,id = <1>;
1538 status = "disabled"; 1535 status = "disabled";
1539 1536
1540 ports { 1537 ports {
1541 #address-cell 1538 #address-cells = <1>;
1542 #size-cells = 1539 #size-cells = <0>;
1543 1540
1544 port@1 { 1541 port@1 {
1545 #addr 1542 #address-cells = <1>;
1546 #size 1543 #size-cells = <0>;
1547 1544
1548 reg = 1545 reg = <1>;
1549 1546
1550 vin1c 1547 vin1csi20: endpoint@0 {
1551 1548 reg = <0>;
1552 1549 remote-endpoint = <&csi20vin1>;
1553 }; 1550 };
1554 vin1c 1551 vin1csi40: endpoint@2 {
1555 1552 reg = <2>;
1556 1553 remote-endpoint = <&csi40vin1>;
1557 }; 1554 };
1558 }; 1555 };
1559 }; 1556 };
1560 }; 1557 };
1561 1558
1562 vin2: video@e6ef2000 { 1559 vin2: video@e6ef2000 {
1563 compatible = "renesas 1560 compatible = "renesas,vin-r8a7796";
1564 reg = <0 0xe6ef2000 0 1561 reg = <0 0xe6ef2000 0 0x1000>;
1565 interrupts = <GIC_SPI 1562 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1566 clocks = <&cpg CPG_MO 1563 clocks = <&cpg CPG_MOD 809>;
1567 power-domains = <&sys 1564 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1568 resets = <&cpg 809>; 1565 resets = <&cpg 809>;
1569 renesas,id = <2>; 1566 renesas,id = <2>;
1570 status = "disabled"; 1567 status = "disabled";
1571 1568
1572 ports { 1569 ports {
1573 #address-cell 1570 #address-cells = <1>;
1574 #size-cells = 1571 #size-cells = <0>;
1575 1572
1576 port@1 { 1573 port@1 {
1577 #addr 1574 #address-cells = <1>;
1578 #size 1575 #size-cells = <0>;
1579 1576
1580 reg = 1577 reg = <1>;
1581 1578
1582 vin2c 1579 vin2csi20: endpoint@0 {
1583 1580 reg = <0>;
1584 1581 remote-endpoint = <&csi20vin2>;
1585 }; 1582 };
1586 vin2c 1583 vin2csi40: endpoint@2 {
1587 1584 reg = <2>;
1588 1585 remote-endpoint = <&csi40vin2>;
1589 }; 1586 };
1590 }; 1587 };
1591 }; 1588 };
1592 }; 1589 };
1593 1590
1594 vin3: video@e6ef3000 { 1591 vin3: video@e6ef3000 {
1595 compatible = "renesas 1592 compatible = "renesas,vin-r8a7796";
1596 reg = <0 0xe6ef3000 0 1593 reg = <0 0xe6ef3000 0 0x1000>;
1597 interrupts = <GIC_SPI 1594 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
1598 clocks = <&cpg CPG_MO 1595 clocks = <&cpg CPG_MOD 808>;
1599 power-domains = <&sys 1596 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1600 resets = <&cpg 808>; 1597 resets = <&cpg 808>;
1601 renesas,id = <3>; 1598 renesas,id = <3>;
1602 status = "disabled"; 1599 status = "disabled";
1603 1600
1604 ports { 1601 ports {
1605 #address-cell 1602 #address-cells = <1>;
1606 #size-cells = 1603 #size-cells = <0>;
1607 1604
1608 port@1 { 1605 port@1 {
1609 #addr 1606 #address-cells = <1>;
1610 #size 1607 #size-cells = <0>;
1611 1608
1612 reg = 1609 reg = <1>;
1613 1610
1614 vin3c 1611 vin3csi20: endpoint@0 {
1615 1612 reg = <0>;
1616 1613 remote-endpoint = <&csi20vin3>;
1617 }; 1614 };
1618 vin3c 1615 vin3csi40: endpoint@2 {
1619 1616 reg = <2>;
1620 1617 remote-endpoint = <&csi40vin3>;
1621 }; 1618 };
1622 }; 1619 };
1623 }; 1620 };
1624 }; 1621 };
1625 1622
1626 vin4: video@e6ef4000 { 1623 vin4: video@e6ef4000 {
1627 compatible = "renesas 1624 compatible = "renesas,vin-r8a7796";
1628 reg = <0 0xe6ef4000 0 1625 reg = <0 0xe6ef4000 0 0x1000>;
1629 interrupts = <GIC_SPI 1626 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
1630 clocks = <&cpg CPG_MO 1627 clocks = <&cpg CPG_MOD 807>;
1631 power-domains = <&sys 1628 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1632 resets = <&cpg 807>; 1629 resets = <&cpg 807>;
1633 renesas,id = <4>; 1630 renesas,id = <4>;
1634 status = "disabled"; 1631 status = "disabled";
1635 1632
1636 ports { 1633 ports {
1637 #address-cell 1634 #address-cells = <1>;
1638 #size-cells = 1635 #size-cells = <0>;
1639 1636
1640 port@1 { 1637 port@1 {
1641 #addr 1638 #address-cells = <1>;
1642 #size 1639 #size-cells = <0>;
1643 1640
1644 reg = 1641 reg = <1>;
1645 1642
1646 vin4c 1643 vin4csi20: endpoint@0 {
1647 1644 reg = <0>;
1648 1645 remote-endpoint = <&csi20vin4>;
1649 }; 1646 };
1650 vin4c 1647 vin4csi40: endpoint@2 {
1651 1648 reg = <2>;
1652 1649 remote-endpoint = <&csi40vin4>;
1653 }; 1650 };
1654 }; 1651 };
1655 }; 1652 };
1656 }; 1653 };
1657 1654
1658 vin5: video@e6ef5000 { 1655 vin5: video@e6ef5000 {
1659 compatible = "renesas 1656 compatible = "renesas,vin-r8a7796";
1660 reg = <0 0xe6ef5000 0 1657 reg = <0 0xe6ef5000 0 0x1000>;
1661 interrupts = <GIC_SPI 1658 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
1662 clocks = <&cpg CPG_MO 1659 clocks = <&cpg CPG_MOD 806>;
1663 power-domains = <&sys 1660 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1664 resets = <&cpg 806>; 1661 resets = <&cpg 806>;
1665 renesas,id = <5>; 1662 renesas,id = <5>;
1666 status = "disabled"; 1663 status = "disabled";
1667 1664
1668 ports { 1665 ports {
1669 #address-cell 1666 #address-cells = <1>;
1670 #size-cells = 1667 #size-cells = <0>;
1671 1668
1672 port@1 { 1669 port@1 {
1673 #addr 1670 #address-cells = <1>;
1674 #size 1671 #size-cells = <0>;
1675 1672
1676 reg = 1673 reg = <1>;
1677 1674
1678 vin5c 1675 vin5csi20: endpoint@0 {
1679 1676 reg = <0>;
1680 1677 remote-endpoint = <&csi20vin5>;
1681 }; 1678 };
1682 vin5c 1679 vin5csi40: endpoint@2 {
1683 1680 reg = <2>;
1684 1681 remote-endpoint = <&csi40vin5>;
1685 }; 1682 };
1686 }; 1683 };
1687 }; 1684 };
1688 }; 1685 };
1689 1686
1690 vin6: video@e6ef6000 { 1687 vin6: video@e6ef6000 {
1691 compatible = "renesas 1688 compatible = "renesas,vin-r8a7796";
1692 reg = <0 0xe6ef6000 0 1689 reg = <0 0xe6ef6000 0 0x1000>;
1693 interrupts = <GIC_SPI 1690 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
1694 clocks = <&cpg CPG_MO 1691 clocks = <&cpg CPG_MOD 805>;
1695 power-domains = <&sys 1692 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1696 resets = <&cpg 805>; 1693 resets = <&cpg 805>;
1697 renesas,id = <6>; 1694 renesas,id = <6>;
1698 status = "disabled"; 1695 status = "disabled";
1699 1696
1700 ports { 1697 ports {
1701 #address-cell 1698 #address-cells = <1>;
1702 #size-cells = 1699 #size-cells = <0>;
1703 1700
1704 port@1 { 1701 port@1 {
1705 #addr 1702 #address-cells = <1>;
1706 #size 1703 #size-cells = <0>;
1707 1704
1708 reg = 1705 reg = <1>;
1709 1706
1710 vin6c 1707 vin6csi20: endpoint@0 {
1711 1708 reg = <0>;
1712 1709 remote-endpoint = <&csi20vin6>;
1713 }; 1710 };
1714 vin6c 1711 vin6csi40: endpoint@2 {
1715 1712 reg = <2>;
1716 1713 remote-endpoint = <&csi40vin6>;
1717 }; 1714 };
1718 }; 1715 };
1719 }; 1716 };
1720 }; 1717 };
1721 1718
1722 vin7: video@e6ef7000 { 1719 vin7: video@e6ef7000 {
1723 compatible = "renesas 1720 compatible = "renesas,vin-r8a7796";
1724 reg = <0 0xe6ef7000 0 1721 reg = <0 0xe6ef7000 0 0x1000>;
1725 interrupts = <GIC_SPI 1722 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
1726 clocks = <&cpg CPG_MO 1723 clocks = <&cpg CPG_MOD 804>;
1727 power-domains = <&sys 1724 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1728 resets = <&cpg 804>; 1725 resets = <&cpg 804>;
1729 renesas,id = <7>; 1726 renesas,id = <7>;
1730 status = "disabled"; 1727 status = "disabled";
1731 1728
1732 ports { 1729 ports {
1733 #address-cell 1730 #address-cells = <1>;
1734 #size-cells = 1731 #size-cells = <0>;
1735 1732
1736 port@1 { 1733 port@1 {
1737 #addr 1734 #address-cells = <1>;
1738 #size 1735 #size-cells = <0>;
1739 1736
1740 reg = 1737 reg = <1>;
1741 1738
1742 vin7c 1739 vin7csi20: endpoint@0 {
1743 1740 reg = <0>;
1744 1741 remote-endpoint = <&csi20vin7>;
1745 }; 1742 };
1746 vin7c 1743 vin7csi40: endpoint@2 {
1747 1744 reg = <2>;
1748 1745 remote-endpoint = <&csi40vin7>;
1749 }; 1746 };
1750 }; 1747 };
1751 }; 1748 };
1752 }; 1749 };
1753 1750
1754 drif00: rif@e6f40000 { 1751 drif00: rif@e6f40000 {
1755 compatible = "renesas 1752 compatible = "renesas,r8a7796-drif",
1756 "renesas 1753 "renesas,rcar-gen3-drif";
1757 reg = <0 0xe6f40000 0 1754 reg = <0 0xe6f40000 0 0x64>;
1758 interrupts = <GIC_SPI 1755 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1759 clocks = <&cpg CPG_MO 1756 clocks = <&cpg CPG_MOD 515>;
1760 clock-names = "fck"; 1757 clock-names = "fck";
1761 dmas = <&dmac1 0x20>, 1758 dmas = <&dmac1 0x20>, <&dmac2 0x20>;
1762 dma-names = "rx", "rx 1759 dma-names = "rx", "rx";
1763 power-domains = <&sys 1760 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1764 resets = <&cpg 515>; 1761 resets = <&cpg 515>;
1765 renesas,bonding = <&d 1762 renesas,bonding = <&drif01>;
1766 status = "disabled"; 1763 status = "disabled";
1767 }; 1764 };
1768 1765
1769 drif01: rif@e6f50000 { 1766 drif01: rif@e6f50000 {
1770 compatible = "renesas 1767 compatible = "renesas,r8a7796-drif",
1771 "renesas 1768 "renesas,rcar-gen3-drif";
1772 reg = <0 0xe6f50000 0 1769 reg = <0 0xe6f50000 0 0x64>;
1773 interrupts = <GIC_SPI 1770 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1774 clocks = <&cpg CPG_MO 1771 clocks = <&cpg CPG_MOD 514>;
1775 clock-names = "fck"; 1772 clock-names = "fck";
1776 dmas = <&dmac1 0x22>, 1773 dmas = <&dmac1 0x22>, <&dmac2 0x22>;
1777 dma-names = "rx", "rx 1774 dma-names = "rx", "rx";
1778 power-domains = <&sys 1775 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1779 resets = <&cpg 514>; 1776 resets = <&cpg 514>;
1780 renesas,bonding = <&d 1777 renesas,bonding = <&drif00>;
1781 status = "disabled"; 1778 status = "disabled";
1782 }; 1779 };
1783 1780
1784 drif10: rif@e6f60000 { 1781 drif10: rif@e6f60000 {
1785 compatible = "renesas 1782 compatible = "renesas,r8a7796-drif",
1786 "renesas 1783 "renesas,rcar-gen3-drif";
1787 reg = <0 0xe6f60000 0 1784 reg = <0 0xe6f60000 0 0x64>;
1788 interrupts = <GIC_SPI 1785 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1789 clocks = <&cpg CPG_MO 1786 clocks = <&cpg CPG_MOD 513>;
1790 clock-names = "fck"; 1787 clock-names = "fck";
1791 dmas = <&dmac1 0x24>, 1788 dmas = <&dmac1 0x24>, <&dmac2 0x24>;
1792 dma-names = "rx", "rx 1789 dma-names = "rx", "rx";
1793 power-domains = <&sys 1790 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1794 resets = <&cpg 513>; 1791 resets = <&cpg 513>;
1795 renesas,bonding = <&d 1792 renesas,bonding = <&drif11>;
1796 status = "disabled"; 1793 status = "disabled";
1797 }; 1794 };
1798 1795
1799 drif11: rif@e6f70000 { 1796 drif11: rif@e6f70000 {
1800 compatible = "renesas 1797 compatible = "renesas,r8a7796-drif",
1801 "renesas 1798 "renesas,rcar-gen3-drif";
1802 reg = <0 0xe6f70000 0 1799 reg = <0 0xe6f70000 0 0x64>;
1803 interrupts = <GIC_SPI 1800 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1804 clocks = <&cpg CPG_MO 1801 clocks = <&cpg CPG_MOD 512>;
1805 clock-names = "fck"; 1802 clock-names = "fck";
1806 dmas = <&dmac1 0x26>, 1803 dmas = <&dmac1 0x26>, <&dmac2 0x26>;
1807 dma-names = "rx", "rx 1804 dma-names = "rx", "rx";
1808 power-domains = <&sys 1805 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1809 resets = <&cpg 512>; 1806 resets = <&cpg 512>;
1810 renesas,bonding = <&d 1807 renesas,bonding = <&drif10>;
1811 status = "disabled"; 1808 status = "disabled";
1812 }; 1809 };
1813 1810
1814 drif20: rif@e6f80000 { 1811 drif20: rif@e6f80000 {
1815 compatible = "renesas 1812 compatible = "renesas,r8a7796-drif",
1816 "renesas 1813 "renesas,rcar-gen3-drif";
1817 reg = <0 0xe6f80000 0 1814 reg = <0 0xe6f80000 0 0x64>;
1818 interrupts = <GIC_SPI 1815 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1819 clocks = <&cpg CPG_MO 1816 clocks = <&cpg CPG_MOD 511>;
1820 clock-names = "fck"; 1817 clock-names = "fck";
1821 dmas = <&dmac1 0x28>, 1818 dmas = <&dmac1 0x28>, <&dmac2 0x28>;
1822 dma-names = "rx", "rx 1819 dma-names = "rx", "rx";
1823 power-domains = <&sys 1820 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1824 resets = <&cpg 511>; 1821 resets = <&cpg 511>;
1825 renesas,bonding = <&d 1822 renesas,bonding = <&drif21>;
1826 status = "disabled"; 1823 status = "disabled";
1827 }; 1824 };
1828 1825
1829 drif21: rif@e6f90000 { 1826 drif21: rif@e6f90000 {
1830 compatible = "renesas 1827 compatible = "renesas,r8a7796-drif",
1831 "renesas 1828 "renesas,rcar-gen3-drif";
1832 reg = <0 0xe6f90000 0 1829 reg = <0 0xe6f90000 0 0x64>;
1833 interrupts = <GIC_SPI 1830 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1834 clocks = <&cpg CPG_MO 1831 clocks = <&cpg CPG_MOD 510>;
1835 clock-names = "fck"; 1832 clock-names = "fck";
1836 dmas = <&dmac1 0x2a>, 1833 dmas = <&dmac1 0x2a>, <&dmac2 0x2a>;
1837 dma-names = "rx", "rx 1834 dma-names = "rx", "rx";
1838 power-domains = <&sys 1835 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1839 resets = <&cpg 510>; 1836 resets = <&cpg 510>;
1840 renesas,bonding = <&d 1837 renesas,bonding = <&drif20>;
1841 status = "disabled"; 1838 status = "disabled";
1842 }; 1839 };
1843 1840
1844 drif30: rif@e6fa0000 { 1841 drif30: rif@e6fa0000 {
1845 compatible = "renesas 1842 compatible = "renesas,r8a7796-drif",
1846 "renesas 1843 "renesas,rcar-gen3-drif";
1847 reg = <0 0xe6fa0000 0 1844 reg = <0 0xe6fa0000 0 0x64>;
1848 interrupts = <GIC_SPI 1845 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1849 clocks = <&cpg CPG_MO 1846 clocks = <&cpg CPG_MOD 509>;
1850 clock-names = "fck"; 1847 clock-names = "fck";
1851 dmas = <&dmac1 0x2c>, 1848 dmas = <&dmac1 0x2c>, <&dmac2 0x2c>;
1852 dma-names = "rx", "rx 1849 dma-names = "rx", "rx";
1853 power-domains = <&sys 1850 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1854 resets = <&cpg 509>; 1851 resets = <&cpg 509>;
1855 renesas,bonding = <&d 1852 renesas,bonding = <&drif31>;
1856 status = "disabled"; 1853 status = "disabled";
1857 }; 1854 };
1858 1855
1859 drif31: rif@e6fb0000 { 1856 drif31: rif@e6fb0000 {
1860 compatible = "renesas 1857 compatible = "renesas,r8a7796-drif",
1861 "renesas 1858 "renesas,rcar-gen3-drif";
1862 reg = <0 0xe6fb0000 0 1859 reg = <0 0xe6fb0000 0 0x64>;
1863 interrupts = <GIC_SPI 1860 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1864 clocks = <&cpg CPG_MO 1861 clocks = <&cpg CPG_MOD 508>;
1865 clock-names = "fck"; 1862 clock-names = "fck";
1866 dmas = <&dmac1 0x2e>, 1863 dmas = <&dmac1 0x2e>, <&dmac2 0x2e>;
1867 dma-names = "rx", "rx 1864 dma-names = "rx", "rx";
1868 power-domains = <&sys 1865 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1869 resets = <&cpg 508>; 1866 resets = <&cpg 508>;
1870 renesas,bonding = <&d 1867 renesas,bonding = <&drif30>;
1871 status = "disabled"; 1868 status = "disabled";
1872 }; 1869 };
1873 1870
1874 rcar_sound: sound@ec500000 { 1871 rcar_sound: sound@ec500000 {
1875 /* 1872 /*
1876 * #sound-dai-cells i !! 1873 * #sound-dai-cells is required
1877 * 1874 *
1878 * Single DAI : #soun 1875 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1879 * Multi DAI : #soun 1876 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1880 */ 1877 */
1881 /* 1878 /*
1882 * #clock-cells is re 1879 * #clock-cells is required for audio_clkout0/1/2/3
1883 * 1880 *
1884 * clkout : #cl 1881 * clkout : #clock-cells = <0>; <&rcar_sound>;
1885 * clkout0/1/2/3: #cl 1882 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
1886 */ 1883 */
1887 compatible = "renesas 1884 compatible = "renesas,rcar_sound-r8a7796", "renesas,rcar_sound-gen3";
1888 reg = <0 0xec500000 0 1885 reg = <0 0xec500000 0 0x1000>, /* SCU */
1889 <0 0xec5a0000 0 1886 <0 0xec5a0000 0 0x100>, /* ADG */
1890 <0 0xec540000 0 1887 <0 0xec540000 0 0x1000>, /* SSIU */
1891 <0 0xec541000 0 1888 <0 0xec541000 0 0x280>, /* SSI */
1892 <0 0xec760000 0 1889 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
1893 reg-names = "scu", "a 1890 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1894 1891
1895 clocks = <&cpg CPG_MO 1892 clocks = <&cpg CPG_MOD 1005>,
1896 <&cpg CPG_MO 1893 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
1897 <&cpg CPG_MO 1894 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
1898 <&cpg CPG_MO 1895 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
1899 <&cpg CPG_MO 1896 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
1900 <&cpg CPG_MO 1897 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
1901 <&cpg CPG_MO 1898 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
1902 <&cpg CPG_MO 1899 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
1903 <&cpg CPG_MO 1900 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
1904 <&cpg CPG_MO 1901 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
1905 <&cpg CPG_MO 1902 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
1906 <&cpg CPG_MO 1903 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1907 <&cpg CPG_MO 1904 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1908 <&cpg CPG_MO 1905 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
1909 <&audio_clk_ 1906 <&audio_clk_a>, <&audio_clk_b>,
1910 <&audio_clk_ 1907 <&audio_clk_c>,
1911 <&cpg CPG_MO !! 1908 <&cpg CPG_CORE R8A7796_CLK_S0D4>;
1912 clock-names = "ssi-al 1909 clock-names = "ssi-all",
1913 "ssi.9" 1910 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1914 "ssi.5" 1911 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1915 "ssi.1" 1912 "ssi.1", "ssi.0",
1916 "src.9" 1913 "src.9", "src.8", "src.7", "src.6",
1917 "src.5" 1914 "src.5", "src.4", "src.3", "src.2",
1918 "src.1" 1915 "src.1", "src.0",
1919 "mix.1" 1916 "mix.1", "mix.0",
1920 "ctu.1" 1917 "ctu.1", "ctu.0",
1921 "dvc.0" 1918 "dvc.0", "dvc.1",
1922 "clk_a" 1919 "clk_a", "clk_b", "clk_c", "clk_i";
1923 power-domains = <&sys 1920 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1924 resets = <&cpg 1005>, 1921 resets = <&cpg 1005>,
1925 <&cpg 1006>, 1922 <&cpg 1006>, <&cpg 1007>,
1926 <&cpg 1008>, 1923 <&cpg 1008>, <&cpg 1009>,
1927 <&cpg 1010>, 1924 <&cpg 1010>, <&cpg 1011>,
1928 <&cpg 1012>, 1925 <&cpg 1012>, <&cpg 1013>,
1929 <&cpg 1014>, 1926 <&cpg 1014>, <&cpg 1015>;
1930 reset-names = "ssi-al 1927 reset-names = "ssi-all",
1931 "ssi.9" 1928 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1932 "ssi.5" 1929 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1933 "ssi.1" 1930 "ssi.1", "ssi.0";
1934 status = "disabled"; 1931 status = "disabled";
1935 1932
1936 rcar_sound,ctu { 1933 rcar_sound,ctu {
1937 ctu00: ctu-0 1934 ctu00: ctu-0 { };
1938 ctu01: ctu-1 1935 ctu01: ctu-1 { };
1939 ctu02: ctu-2 1936 ctu02: ctu-2 { };
1940 ctu03: ctu-3 1937 ctu03: ctu-3 { };
1941 ctu10: ctu-4 1938 ctu10: ctu-4 { };
1942 ctu11: ctu-5 1939 ctu11: ctu-5 { };
1943 ctu12: ctu-6 1940 ctu12: ctu-6 { };
1944 ctu13: ctu-7 1941 ctu13: ctu-7 { };
1945 }; 1942 };
1946 1943
1947 rcar_sound,dvc { 1944 rcar_sound,dvc {
1948 dvc0: dvc-0 { 1945 dvc0: dvc-0 {
1949 dmas 1946 dmas = <&audma1 0xbc>;
1950 dma-n 1947 dma-names = "tx";
1951 }; 1948 };
1952 dvc1: dvc-1 { 1949 dvc1: dvc-1 {
1953 dmas 1950 dmas = <&audma1 0xbe>;
1954 dma-n 1951 dma-names = "tx";
1955 }; 1952 };
1956 }; 1953 };
1957 1954
1958 rcar_sound,mix { 1955 rcar_sound,mix {
1959 mix0: mix-0 { 1956 mix0: mix-0 { };
1960 mix1: mix-1 { 1957 mix1: mix-1 { };
1961 }; 1958 };
1962 1959
1963 rcar_sound,src { 1960 rcar_sound,src {
1964 src0: src-0 { 1961 src0: src-0 {
1965 inter 1962 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1966 dmas 1963 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1967 dma-n 1964 dma-names = "rx", "tx";
1968 }; 1965 };
1969 src1: src-1 { 1966 src1: src-1 {
1970 inter 1967 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1971 dmas 1968 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1972 dma-n 1969 dma-names = "rx", "tx";
1973 }; 1970 };
1974 src2: src-2 { 1971 src2: src-2 {
1975 inter 1972 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1976 dmas 1973 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1977 dma-n 1974 dma-names = "rx", "tx";
1978 }; 1975 };
1979 src3: src-3 { 1976 src3: src-3 {
1980 inter 1977 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1981 dmas 1978 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1982 dma-n 1979 dma-names = "rx", "tx";
1983 }; 1980 };
1984 src4: src-4 { 1981 src4: src-4 {
1985 inter 1982 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1986 dmas 1983 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1987 dma-n 1984 dma-names = "rx", "tx";
1988 }; 1985 };
1989 src5: src-5 { 1986 src5: src-5 {
1990 inter 1987 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1991 dmas 1988 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1992 dma-n 1989 dma-names = "rx", "tx";
1993 }; 1990 };
1994 src6: src-6 { 1991 src6: src-6 {
1995 inter 1992 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1996 dmas 1993 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1997 dma-n 1994 dma-names = "rx", "tx";
1998 }; 1995 };
1999 src7: src-7 { 1996 src7: src-7 {
2000 inter 1997 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
2001 dmas 1998 dmas = <&audma0 0x93>, <&audma1 0xb6>;
2002 dma-n 1999 dma-names = "rx", "tx";
2003 }; 2000 };
2004 src8: src-8 { 2001 src8: src-8 {
2005 inter 2002 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2006 dmas 2003 dmas = <&audma0 0x95>, <&audma1 0xb8>;
2007 dma-n 2004 dma-names = "rx", "tx";
2008 }; 2005 };
2009 src9: src-9 { 2006 src9: src-9 {
2010 inter 2007 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
2011 dmas 2008 dmas = <&audma0 0x97>, <&audma1 0xba>;
2012 dma-n 2009 dma-names = "rx", "tx";
2013 }; 2010 };
2014 }; 2011 };
2015 2012
2016 rcar_sound,ssi { 2013 rcar_sound,ssi {
2017 ssi0: ssi-0 { 2014 ssi0: ssi-0 {
2018 inter 2015 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
2019 dmas 2016 dmas = <&audma0 0x01>, <&audma1 0x02>;
2020 dma-n 2017 dma-names = "rx", "tx";
2021 }; 2018 };
2022 ssi1: ssi-1 { 2019 ssi1: ssi-1 {
2023 inter 2020 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
2024 dmas 2021 dmas = <&audma0 0x03>, <&audma1 0x04>;
2025 dma-n 2022 dma-names = "rx", "tx";
2026 }; 2023 };
2027 ssi2: ssi-2 { 2024 ssi2: ssi-2 {
2028 inter 2025 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
2029 dmas 2026 dmas = <&audma0 0x05>, <&audma1 0x06>;
2030 dma-n 2027 dma-names = "rx", "tx";
2031 }; 2028 };
2032 ssi3: ssi-3 { 2029 ssi3: ssi-3 {
2033 inter 2030 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
2034 dmas 2031 dmas = <&audma0 0x07>, <&audma1 0x08>;
2035 dma-n 2032 dma-names = "rx", "tx";
2036 }; 2033 };
2037 ssi4: ssi-4 { 2034 ssi4: ssi-4 {
2038 inter 2035 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
2039 dmas 2036 dmas = <&audma0 0x09>, <&audma1 0x0a>;
2040 dma-n 2037 dma-names = "rx", "tx";
2041 }; 2038 };
2042 ssi5: ssi-5 { 2039 ssi5: ssi-5 {
2043 inter 2040 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
2044 dmas 2041 dmas = <&audma0 0x0b>, <&audma1 0x0c>;
2045 dma-n 2042 dma-names = "rx", "tx";
2046 }; 2043 };
2047 ssi6: ssi-6 { 2044 ssi6: ssi-6 {
2048 inter 2045 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
2049 dmas 2046 dmas = <&audma0 0x0d>, <&audma1 0x0e>;
2050 dma-n 2047 dma-names = "rx", "tx";
2051 }; 2048 };
2052 ssi7: ssi-7 { 2049 ssi7: ssi-7 {
2053 inter 2050 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
2054 dmas 2051 dmas = <&audma0 0x0f>, <&audma1 0x10>;
2055 dma-n 2052 dma-names = "rx", "tx";
2056 }; 2053 };
2057 ssi8: ssi-8 { 2054 ssi8: ssi-8 {
2058 inter 2055 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
2059 dmas 2056 dmas = <&audma0 0x11>, <&audma1 0x12>;
2060 dma-n 2057 dma-names = "rx", "tx";
2061 }; 2058 };
2062 ssi9: ssi-9 { 2059 ssi9: ssi-9 {
2063 inter 2060 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
2064 dmas 2061 dmas = <&audma0 0x13>, <&audma1 0x14>;
2065 dma-n 2062 dma-names = "rx", "tx";
2066 }; 2063 };
2067 }; 2064 };
2068 2065
2069 rcar_sound,ssiu { 2066 rcar_sound,ssiu {
2070 ssiu00: ssiu- 2067 ssiu00: ssiu-0 {
2071 dmas 2068 dmas = <&audma0 0x15>, <&audma1 0x16>;
2072 dma-n 2069 dma-names = "rx", "tx";
2073 }; 2070 };
2074 ssiu01: ssiu- 2071 ssiu01: ssiu-1 {
2075 dmas 2072 dmas = <&audma0 0x35>, <&audma1 0x36>;
2076 dma-n 2073 dma-names = "rx", "tx";
2077 }; 2074 };
2078 ssiu02: ssiu- 2075 ssiu02: ssiu-2 {
2079 dmas 2076 dmas = <&audma0 0x37>, <&audma1 0x38>;
2080 dma-n 2077 dma-names = "rx", "tx";
2081 }; 2078 };
2082 ssiu03: ssiu- 2079 ssiu03: ssiu-3 {
2083 dmas 2080 dmas = <&audma0 0x47>, <&audma1 0x48>;
2084 dma-n 2081 dma-names = "rx", "tx";
2085 }; 2082 };
2086 ssiu04: ssiu- 2083 ssiu04: ssiu-4 {
2087 dmas 2084 dmas = <&audma0 0x3F>, <&audma1 0x40>;
2088 dma-n 2085 dma-names = "rx", "tx";
2089 }; 2086 };
2090 ssiu05: ssiu- 2087 ssiu05: ssiu-5 {
2091 dmas 2088 dmas = <&audma0 0x43>, <&audma1 0x44>;
2092 dma-n 2089 dma-names = "rx", "tx";
2093 }; 2090 };
2094 ssiu06: ssiu- 2091 ssiu06: ssiu-6 {
2095 dmas 2092 dmas = <&audma0 0x4F>, <&audma1 0x50>;
2096 dma-n 2093 dma-names = "rx", "tx";
2097 }; 2094 };
2098 ssiu07: ssiu- 2095 ssiu07: ssiu-7 {
2099 dmas 2096 dmas = <&audma0 0x53>, <&audma1 0x54>;
2100 dma-n 2097 dma-names = "rx", "tx";
2101 }; 2098 };
2102 ssiu10: ssiu- 2099 ssiu10: ssiu-8 {
2103 dmas 2100 dmas = <&audma0 0x49>, <&audma1 0x4a>;
2104 dma-n 2101 dma-names = "rx", "tx";
2105 }; 2102 };
2106 ssiu11: ssiu- 2103 ssiu11: ssiu-9 {
2107 dmas 2104 dmas = <&audma0 0x4B>, <&audma1 0x4C>;
2108 dma-n 2105 dma-names = "rx", "tx";
2109 }; 2106 };
2110 ssiu12: ssiu- 2107 ssiu12: ssiu-10 {
2111 dmas 2108 dmas = <&audma0 0x57>, <&audma1 0x58>;
2112 dma-n 2109 dma-names = "rx", "tx";
2113 }; 2110 };
2114 ssiu13: ssiu- 2111 ssiu13: ssiu-11 {
2115 dmas 2112 dmas = <&audma0 0x59>, <&audma1 0x5A>;
2116 dma-n 2113 dma-names = "rx", "tx";
2117 }; 2114 };
2118 ssiu14: ssiu- 2115 ssiu14: ssiu-12 {
2119 dmas 2116 dmas = <&audma0 0x5F>, <&audma1 0x60>;
2120 dma-n 2117 dma-names = "rx", "tx";
2121 }; 2118 };
2122 ssiu15: ssiu- 2119 ssiu15: ssiu-13 {
2123 dmas 2120 dmas = <&audma0 0xC3>, <&audma1 0xC4>;
2124 dma-n 2121 dma-names = "rx", "tx";
2125 }; 2122 };
2126 ssiu16: ssiu- 2123 ssiu16: ssiu-14 {
2127 dmas 2124 dmas = <&audma0 0xC7>, <&audma1 0xC8>;
2128 dma-n 2125 dma-names = "rx", "tx";
2129 }; 2126 };
2130 ssiu17: ssiu- 2127 ssiu17: ssiu-15 {
2131 dmas 2128 dmas = <&audma0 0xCB>, <&audma1 0xCC>;
2132 dma-n 2129 dma-names = "rx", "tx";
2133 }; 2130 };
2134 ssiu20: ssiu- 2131 ssiu20: ssiu-16 {
2135 dmas 2132 dmas = <&audma0 0x63>, <&audma1 0x64>;
2136 dma-n 2133 dma-names = "rx", "tx";
2137 }; 2134 };
2138 ssiu21: ssiu- 2135 ssiu21: ssiu-17 {
2139 dmas 2136 dmas = <&audma0 0x67>, <&audma1 0x68>;
2140 dma-n 2137 dma-names = "rx", "tx";
2141 }; 2138 };
2142 ssiu22: ssiu- 2139 ssiu22: ssiu-18 {
2143 dmas 2140 dmas = <&audma0 0x6B>, <&audma1 0x6C>;
2144 dma-n 2141 dma-names = "rx", "tx";
2145 }; 2142 };
2146 ssiu23: ssiu- 2143 ssiu23: ssiu-19 {
2147 dmas 2144 dmas = <&audma0 0x6D>, <&audma1 0x6E>;
2148 dma-n 2145 dma-names = "rx", "tx";
2149 }; 2146 };
2150 ssiu24: ssiu- 2147 ssiu24: ssiu-20 {
2151 dmas 2148 dmas = <&audma0 0xCF>, <&audma1 0xCE>;
2152 dma-n 2149 dma-names = "rx", "tx";
2153 }; 2150 };
2154 ssiu25: ssiu- 2151 ssiu25: ssiu-21 {
2155 dmas 2152 dmas = <&audma0 0xEB>, <&audma1 0xEC>;
2156 dma-n 2153 dma-names = "rx", "tx";
2157 }; 2154 };
2158 ssiu26: ssiu- 2155 ssiu26: ssiu-22 {
2159 dmas 2156 dmas = <&audma0 0xED>, <&audma1 0xEE>;
2160 dma-n 2157 dma-names = "rx", "tx";
2161 }; 2158 };
2162 ssiu27: ssiu- 2159 ssiu27: ssiu-23 {
2163 dmas 2160 dmas = <&audma0 0xEF>, <&audma1 0xF0>;
2164 dma-n 2161 dma-names = "rx", "tx";
2165 }; 2162 };
2166 ssiu30: ssiu- 2163 ssiu30: ssiu-24 {
2167 dmas 2164 dmas = <&audma0 0x6f>, <&audma1 0x70>;
2168 dma-n 2165 dma-names = "rx", "tx";
2169 }; 2166 };
2170 ssiu31: ssiu- 2167 ssiu31: ssiu-25 {
2171 dmas 2168 dmas = <&audma0 0x21>, <&audma1 0x22>;
2172 dma-n 2169 dma-names = "rx", "tx";
2173 }; 2170 };
2174 ssiu32: ssiu- 2171 ssiu32: ssiu-26 {
2175 dmas 2172 dmas = <&audma0 0x23>, <&audma1 0x24>;
2176 dma-n 2173 dma-names = "rx", "tx";
2177 }; 2174 };
2178 ssiu33: ssiu- 2175 ssiu33: ssiu-27 {
2179 dmas 2176 dmas = <&audma0 0x25>, <&audma1 0x26>;
2180 dma-n 2177 dma-names = "rx", "tx";
2181 }; 2178 };
2182 ssiu34: ssiu- 2179 ssiu34: ssiu-28 {
2183 dmas 2180 dmas = <&audma0 0x27>, <&audma1 0x28>;
2184 dma-n 2181 dma-names = "rx", "tx";
2185 }; 2182 };
2186 ssiu35: ssiu- 2183 ssiu35: ssiu-29 {
2187 dmas 2184 dmas = <&audma0 0x29>, <&audma1 0x2A>;
2188 dma-n 2185 dma-names = "rx", "tx";
2189 }; 2186 };
2190 ssiu36: ssiu- 2187 ssiu36: ssiu-30 {
2191 dmas 2188 dmas = <&audma0 0x2B>, <&audma1 0x2C>;
2192 dma-n 2189 dma-names = "rx", "tx";
2193 }; 2190 };
2194 ssiu37: ssiu- 2191 ssiu37: ssiu-31 {
2195 dmas 2192 dmas = <&audma0 0x2D>, <&audma1 0x2E>;
2196 dma-n 2193 dma-names = "rx", "tx";
2197 }; 2194 };
2198 ssiu40: ssiu- 2195 ssiu40: ssiu-32 {
2199 dmas 2196 dmas = <&audma0 0x71>, <&audma1 0x72>;
2200 dma-n 2197 dma-names = "rx", "tx";
2201 }; 2198 };
2202 ssiu41: ssiu- 2199 ssiu41: ssiu-33 {
2203 dmas 2200 dmas = <&audma0 0x17>, <&audma1 0x18>;
2204 dma-n 2201 dma-names = "rx", "tx";
2205 }; 2202 };
2206 ssiu42: ssiu- 2203 ssiu42: ssiu-34 {
2207 dmas 2204 dmas = <&audma0 0x19>, <&audma1 0x1A>;
2208 dma-n 2205 dma-names = "rx", "tx";
2209 }; 2206 };
2210 ssiu43: ssiu- 2207 ssiu43: ssiu-35 {
2211 dmas 2208 dmas = <&audma0 0x1B>, <&audma1 0x1C>;
2212 dma-n 2209 dma-names = "rx", "tx";
2213 }; 2210 };
2214 ssiu44: ssiu- 2211 ssiu44: ssiu-36 {
2215 dmas 2212 dmas = <&audma0 0x1D>, <&audma1 0x1E>;
2216 dma-n 2213 dma-names = "rx", "tx";
2217 }; 2214 };
2218 ssiu45: ssiu- 2215 ssiu45: ssiu-37 {
2219 dmas 2216 dmas = <&audma0 0x1F>, <&audma1 0x20>;
2220 dma-n 2217 dma-names = "rx", "tx";
2221 }; 2218 };
2222 ssiu46: ssiu- 2219 ssiu46: ssiu-38 {
2223 dmas 2220 dmas = <&audma0 0x31>, <&audma1 0x32>;
2224 dma-n 2221 dma-names = "rx", "tx";
2225 }; 2222 };
2226 ssiu47: ssiu- 2223 ssiu47: ssiu-39 {
2227 dmas 2224 dmas = <&audma0 0x33>, <&audma1 0x34>;
2228 dma-n 2225 dma-names = "rx", "tx";
2229 }; 2226 };
2230 ssiu50: ssiu- 2227 ssiu50: ssiu-40 {
2231 dmas 2228 dmas = <&audma0 0x73>, <&audma1 0x74>;
2232 dma-n 2229 dma-names = "rx", "tx";
2233 }; 2230 };
2234 ssiu60: ssiu- 2231 ssiu60: ssiu-41 {
2235 dmas 2232 dmas = <&audma0 0x75>, <&audma1 0x76>;
2236 dma-n 2233 dma-names = "rx", "tx";
2237 }; 2234 };
2238 ssiu70: ssiu- 2235 ssiu70: ssiu-42 {
2239 dmas 2236 dmas = <&audma0 0x79>, <&audma1 0x7a>;
2240 dma-n 2237 dma-names = "rx", "tx";
2241 }; 2238 };
2242 ssiu80: ssiu- 2239 ssiu80: ssiu-43 {
2243 dmas 2240 dmas = <&audma0 0x7b>, <&audma1 0x7c>;
2244 dma-n 2241 dma-names = "rx", "tx";
2245 }; 2242 };
2246 ssiu90: ssiu- 2243 ssiu90: ssiu-44 {
2247 dmas 2244 dmas = <&audma0 0x7d>, <&audma1 0x7e>;
2248 dma-n 2245 dma-names = "rx", "tx";
2249 }; 2246 };
2250 ssiu91: ssiu- 2247 ssiu91: ssiu-45 {
2251 dmas 2248 dmas = <&audma0 0x7F>, <&audma1 0x80>;
2252 dma-n 2249 dma-names = "rx", "tx";
2253 }; 2250 };
2254 ssiu92: ssiu- 2251 ssiu92: ssiu-46 {
2255 dmas 2252 dmas = <&audma0 0x81>, <&audma1 0x82>;
2256 dma-n 2253 dma-names = "rx", "tx";
2257 }; 2254 };
2258 ssiu93: ssiu- 2255 ssiu93: ssiu-47 {
2259 dmas 2256 dmas = <&audma0 0x83>, <&audma1 0x84>;
2260 dma-n 2257 dma-names = "rx", "tx";
2261 }; 2258 };
2262 ssiu94: ssiu- 2259 ssiu94: ssiu-48 {
2263 dmas 2260 dmas = <&audma0 0xA3>, <&audma1 0xA4>;
2264 dma-n 2261 dma-names = "rx", "tx";
2265 }; 2262 };
2266 ssiu95: ssiu- 2263 ssiu95: ssiu-49 {
2267 dmas 2264 dmas = <&audma0 0xA5>, <&audma1 0xA6>;
2268 dma-n 2265 dma-names = "rx", "tx";
2269 }; 2266 };
2270 ssiu96: ssiu- 2267 ssiu96: ssiu-50 {
2271 dmas 2268 dmas = <&audma0 0xA7>, <&audma1 0xA8>;
2272 dma-n 2269 dma-names = "rx", "tx";
2273 }; 2270 };
2274 ssiu97: ssiu- 2271 ssiu97: ssiu-51 {
2275 dmas 2272 dmas = <&audma0 0xA9>, <&audma1 0xAA>;
2276 dma-n 2273 dma-names = "rx", "tx";
2277 }; 2274 };
2278 }; 2275 };
2279 }; 2276 };
2280 2277
2281 mlp: mlp@ec520000 { 2278 mlp: mlp@ec520000 {
2282 compatible = "renesas 2279 compatible = "renesas,r8a7796-mlp",
2283 "renesas 2280 "renesas,rcar-gen3-mlp";
2284 reg = <0 0xec520000 0 2281 reg = <0 0xec520000 0 0x800>;
2285 interrupts = <GIC_SPI 2282 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
2286 <GIC_SPI 385 2283 <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>;
2287 clocks = <&cpg CPG_MO 2284 clocks = <&cpg CPG_MOD 802>;
2288 power-domains = <&sys 2285 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2289 resets = <&cpg 802>; 2286 resets = <&cpg 802>;
2290 status = "disabled"; 2287 status = "disabled";
2291 }; 2288 };
2292 2289
2293 audma0: dma-controller@ec7000 2290 audma0: dma-controller@ec700000 {
2294 compatible = "renesas 2291 compatible = "renesas,dmac-r8a7796",
2295 "renesas 2292 "renesas,rcar-dmac";
2296 reg = <0 0xec700000 0 2293 reg = <0 0xec700000 0 0x10000>;
2297 interrupts = <GIC_SPI 2294 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
2298 <GIC_SPI 2295 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
2299 <GIC_SPI 2296 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
2300 <GIC_SPI 2297 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
2301 <GIC_SPI 2298 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
2302 <GIC_SPI 2299 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
2303 <GIC_SPI 2300 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
2304 <GIC_SPI 2301 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
2305 <GIC_SPI 2302 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
2306 <GIC_SPI 2303 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
2307 <GIC_SPI 2304 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
2308 <GIC_SPI 2305 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
2309 <GIC_SPI 2306 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
2310 <GIC_SPI 2307 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
2311 <GIC_SPI 2308 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
2312 <GIC_SPI 2309 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
2313 <GIC_SPI 2310 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
2314 interrupt-names = "er 2311 interrupt-names = "error",
2315 "ch0" 2312 "ch0", "ch1", "ch2", "ch3",
2316 "ch4" 2313 "ch4", "ch5", "ch6", "ch7",
2317 "ch8" 2314 "ch8", "ch9", "ch10", "ch11",
2318 "ch12 2315 "ch12", "ch13", "ch14", "ch15";
2319 clocks = <&cpg CPG_MO 2316 clocks = <&cpg CPG_MOD 502>;
2320 clock-names = "fck"; 2317 clock-names = "fck";
2321 power-domains = <&sys 2318 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2322 resets = <&cpg 502>; 2319 resets = <&cpg 502>;
2323 #dma-cells = <1>; 2320 #dma-cells = <1>;
2324 dma-channels = <16>; 2321 dma-channels = <16>;
2325 iommus = <&ipmmu_mp 0 2322 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
2326 <&ipmmu_mp 2>, 2323 <&ipmmu_mp 2>, <&ipmmu_mp 3>,
2327 <&ipmmu_mp 4>, 2324 <&ipmmu_mp 4>, <&ipmmu_mp 5>,
2328 <&ipmmu_mp 6>, 2325 <&ipmmu_mp 6>, <&ipmmu_mp 7>,
2329 <&ipmmu_mp 8>, 2326 <&ipmmu_mp 8>, <&ipmmu_mp 9>,
2330 <&ipmmu_mp 10> 2327 <&ipmmu_mp 10>, <&ipmmu_mp 11>,
2331 <&ipmmu_mp 12> 2328 <&ipmmu_mp 12>, <&ipmmu_mp 13>,
2332 <&ipmmu_mp 14> 2329 <&ipmmu_mp 14>, <&ipmmu_mp 15>;
2333 }; 2330 };
2334 2331
2335 audma1: dma-controller@ec7200 2332 audma1: dma-controller@ec720000 {
2336 compatible = "renesas 2333 compatible = "renesas,dmac-r8a7796",
2337 "renesas 2334 "renesas,rcar-dmac";
2338 reg = <0 0xec720000 0 2335 reg = <0 0xec720000 0 0x10000>;
2339 interrupts = <GIC_SPI 2336 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
2340 <GIC_SPI 2337 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
2341 <GIC_SPI 2338 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
2342 <GIC_SPI 2339 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
2343 <GIC_SPI 2340 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
2344 <GIC_SPI 2341 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
2345 <GIC_SPI 2342 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
2346 <GIC_SPI 2343 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
2347 <GIC_SPI 2344 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
2348 <GIC_SPI 2345 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
2349 <GIC_SPI 2346 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
2350 <GIC_SPI 2347 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
2351 <GIC_SPI 2348 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
2352 <GIC_SPI 2349 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
2353 <GIC_SPI 2350 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
2354 <GIC_SPI 2351 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
2355 <GIC_SPI 2352 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
2356 interrupt-names = "er 2353 interrupt-names = "error",
2357 "ch0" 2354 "ch0", "ch1", "ch2", "ch3",
2358 "ch4" 2355 "ch4", "ch5", "ch6", "ch7",
2359 "ch8" 2356 "ch8", "ch9", "ch10", "ch11",
2360 "ch12 2357 "ch12", "ch13", "ch14", "ch15";
2361 clocks = <&cpg CPG_MO 2358 clocks = <&cpg CPG_MOD 501>;
2362 clock-names = "fck"; 2359 clock-names = "fck";
2363 power-domains = <&sys 2360 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2364 resets = <&cpg 501>; 2361 resets = <&cpg 501>;
2365 #dma-cells = <1>; 2362 #dma-cells = <1>;
2366 dma-channels = <16>; 2363 dma-channels = <16>;
2367 iommus = <&ipmmu_mp 1 2364 iommus = <&ipmmu_mp 16>, <&ipmmu_mp 17>,
2368 <&ipmmu_mp 18> 2365 <&ipmmu_mp 18>, <&ipmmu_mp 19>,
2369 <&ipmmu_mp 20> 2366 <&ipmmu_mp 20>, <&ipmmu_mp 21>,
2370 <&ipmmu_mp 22> 2367 <&ipmmu_mp 22>, <&ipmmu_mp 23>,
2371 <&ipmmu_mp 24> 2368 <&ipmmu_mp 24>, <&ipmmu_mp 25>,
2372 <&ipmmu_mp 26> 2369 <&ipmmu_mp 26>, <&ipmmu_mp 27>,
2373 <&ipmmu_mp 28> 2370 <&ipmmu_mp 28>, <&ipmmu_mp 29>,
2374 <&ipmmu_mp 30> 2371 <&ipmmu_mp 30>, <&ipmmu_mp 31>;
2375 }; 2372 };
2376 2373
2377 xhci0: usb@ee000000 { 2374 xhci0: usb@ee000000 {
2378 compatible = "renesas 2375 compatible = "renesas,xhci-r8a7796",
2379 "renesas 2376 "renesas,rcar-gen3-xhci";
2380 reg = <0 0xee000000 0 2377 reg = <0 0xee000000 0 0xc00>;
2381 interrupts = <GIC_SPI 2378 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
2382 clocks = <&cpg CPG_MO 2379 clocks = <&cpg CPG_MOD 328>;
2383 power-domains = <&sys 2380 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2384 resets = <&cpg 328>; 2381 resets = <&cpg 328>;
2385 status = "disabled"; 2382 status = "disabled";
2386 }; 2383 };
2387 2384
2388 usb3_peri0: usb@ee020000 { 2385 usb3_peri0: usb@ee020000 {
2389 compatible = "renesas 2386 compatible = "renesas,r8a7796-usb3-peri",
2390 "renesas 2387 "renesas,rcar-gen3-usb3-peri";
2391 reg = <0 0xee020000 0 2388 reg = <0 0xee020000 0 0x400>;
2392 interrupts = <GIC_SPI 2389 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
2393 clocks = <&cpg CPG_MO 2390 clocks = <&cpg CPG_MOD 328>;
2394 power-domains = <&sys 2391 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2395 resets = <&cpg 328>; 2392 resets = <&cpg 328>;
2396 status = "disabled"; 2393 status = "disabled";
2397 }; 2394 };
2398 2395
2399 ohci0: usb@ee080000 { 2396 ohci0: usb@ee080000 {
2400 compatible = "generic 2397 compatible = "generic-ohci";
2401 reg = <0 0xee080000 0 2398 reg = <0 0xee080000 0 0x100>;
2402 interrupts = <GIC_SPI 2399 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
2403 clocks = <&cpg CPG_MO 2400 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
2404 phys = <&usb2_phy0 1> 2401 phys = <&usb2_phy0 1>;
2405 phy-names = "usb"; 2402 phy-names = "usb";
2406 power-domains = <&sys 2403 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2407 resets = <&cpg 703>, 2404 resets = <&cpg 703>, <&cpg 704>;
2408 status = "disabled"; 2405 status = "disabled";
2409 }; 2406 };
2410 2407
2411 ohci1: usb@ee0a0000 { 2408 ohci1: usb@ee0a0000 {
2412 compatible = "generic 2409 compatible = "generic-ohci";
2413 reg = <0 0xee0a0000 0 2410 reg = <0 0xee0a0000 0 0x100>;
2414 interrupts = <GIC_SPI 2411 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
2415 clocks = <&cpg CPG_MO 2412 clocks = <&cpg CPG_MOD 702>;
2416 phys = <&usb2_phy1 1> 2413 phys = <&usb2_phy1 1>;
2417 phy-names = "usb"; 2414 phy-names = "usb";
2418 power-domains = <&sys 2415 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2419 resets = <&cpg 702>; 2416 resets = <&cpg 702>;
2420 status = "disabled"; 2417 status = "disabled";
2421 }; 2418 };
2422 2419
2423 ehci0: usb@ee080100 { 2420 ehci0: usb@ee080100 {
2424 compatible = "generic 2421 compatible = "generic-ehci";
2425 reg = <0 0xee080100 0 2422 reg = <0 0xee080100 0 0x100>;
2426 interrupts = <GIC_SPI 2423 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
2427 clocks = <&cpg CPG_MO 2424 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
2428 phys = <&usb2_phy0 2> 2425 phys = <&usb2_phy0 2>;
2429 phy-names = "usb"; 2426 phy-names = "usb";
2430 companion = <&ohci0>; 2427 companion = <&ohci0>;
2431 power-domains = <&sys 2428 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2432 resets = <&cpg 703>, 2429 resets = <&cpg 703>, <&cpg 704>;
2433 status = "disabled"; 2430 status = "disabled";
2434 }; 2431 };
2435 2432
2436 ehci1: usb@ee0a0100 { 2433 ehci1: usb@ee0a0100 {
2437 compatible = "generic 2434 compatible = "generic-ehci";
2438 reg = <0 0xee0a0100 0 2435 reg = <0 0xee0a0100 0 0x100>;
2439 interrupts = <GIC_SPI 2436 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
2440 clocks = <&cpg CPG_MO 2437 clocks = <&cpg CPG_MOD 702>;
2441 phys = <&usb2_phy1 2> 2438 phys = <&usb2_phy1 2>;
2442 phy-names = "usb"; 2439 phy-names = "usb";
2443 companion = <&ohci1>; 2440 companion = <&ohci1>;
2444 power-domains = <&sys 2441 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2445 resets = <&cpg 702>; 2442 resets = <&cpg 702>;
2446 status = "disabled"; 2443 status = "disabled";
2447 }; 2444 };
2448 2445
2449 usb2_phy0: usb-phy@ee080200 { 2446 usb2_phy0: usb-phy@ee080200 {
2450 compatible = "renesas 2447 compatible = "renesas,usb2-phy-r8a7796",
2451 "renesas 2448 "renesas,rcar-gen3-usb2-phy";
2452 reg = <0 0xee080200 0 2449 reg = <0 0xee080200 0 0x700>;
2453 interrupts = <GIC_SPI 2450 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
2454 clocks = <&cpg CPG_MO 2451 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
2455 power-domains = <&sys 2452 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2456 resets = <&cpg 703>, 2453 resets = <&cpg 703>, <&cpg 704>;
2457 #phy-cells = <1>; 2454 #phy-cells = <1>;
2458 status = "disabled"; 2455 status = "disabled";
2459 }; 2456 };
2460 2457
2461 usb2_phy1: usb-phy@ee0a0200 { 2458 usb2_phy1: usb-phy@ee0a0200 {
2462 compatible = "renesas 2459 compatible = "renesas,usb2-phy-r8a7796",
2463 "renesas 2460 "renesas,rcar-gen3-usb2-phy";
2464 reg = <0 0xee0a0200 0 2461 reg = <0 0xee0a0200 0 0x700>;
2465 clocks = <&cpg CPG_MO 2462 clocks = <&cpg CPG_MOD 702>;
2466 power-domains = <&sys 2463 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2467 resets = <&cpg 702>; 2464 resets = <&cpg 702>;
2468 #phy-cells = <1>; 2465 #phy-cells = <1>;
2469 status = "disabled"; 2466 status = "disabled";
2470 }; 2467 };
2471 2468
2472 sdhi0: mmc@ee100000 { 2469 sdhi0: mmc@ee100000 {
2473 compatible = "renesas 2470 compatible = "renesas,sdhi-r8a7796",
2474 "renesas 2471 "renesas,rcar-gen3-sdhi";
2475 reg = <0 0xee100000 0 2472 reg = <0 0xee100000 0 0x2000>;
2476 interrupts = <GIC_SPI 2473 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
2477 clocks = <&cpg CPG_MO 2474 clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A7796_CLK_SD0H>;
2478 clock-names = "core", 2475 clock-names = "core", "clkh";
2479 max-frequency = <2000 2476 max-frequency = <200000000>;
2480 power-domains = <&sys 2477 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2481 resets = <&cpg 314>; 2478 resets = <&cpg 314>;
2482 iommus = <&ipmmu_ds1 2479 iommus = <&ipmmu_ds1 32>;
2483 status = "disabled"; 2480 status = "disabled";
2484 }; 2481 };
2485 2482
2486 sdhi1: mmc@ee120000 { 2483 sdhi1: mmc@ee120000 {
2487 compatible = "renesas 2484 compatible = "renesas,sdhi-r8a7796",
2488 "renesas 2485 "renesas,rcar-gen3-sdhi";
2489 reg = <0 0xee120000 0 2486 reg = <0 0xee120000 0 0x2000>;
2490 interrupts = <GIC_SPI 2487 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
2491 clocks = <&cpg CPG_MO 2488 clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A7796_CLK_SD1H>;
2492 clock-names = "core", 2489 clock-names = "core", "clkh";
2493 max-frequency = <2000 2490 max-frequency = <200000000>;
2494 power-domains = <&sys 2491 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2495 resets = <&cpg 313>; 2492 resets = <&cpg 313>;
2496 iommus = <&ipmmu_ds1 2493 iommus = <&ipmmu_ds1 33>;
2497 status = "disabled"; 2494 status = "disabled";
2498 }; 2495 };
2499 2496
2500 sdhi2: mmc@ee140000 { 2497 sdhi2: mmc@ee140000 {
2501 compatible = "renesas 2498 compatible = "renesas,sdhi-r8a7796",
2502 "renesas 2499 "renesas,rcar-gen3-sdhi";
2503 reg = <0 0xee140000 0 2500 reg = <0 0xee140000 0 0x2000>;
2504 interrupts = <GIC_SPI 2501 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
2505 clocks = <&cpg CPG_MO 2502 clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A7796_CLK_SD2H>;
2506 clock-names = "core", 2503 clock-names = "core", "clkh";
2507 max-frequency = <2000 2504 max-frequency = <200000000>;
2508 power-domains = <&sys 2505 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2509 resets = <&cpg 312>; 2506 resets = <&cpg 312>;
2510 iommus = <&ipmmu_ds1 2507 iommus = <&ipmmu_ds1 34>;
2511 status = "disabled"; 2508 status = "disabled";
2512 }; 2509 };
2513 2510
2514 sdhi3: mmc@ee160000 { 2511 sdhi3: mmc@ee160000 {
2515 compatible = "renesas 2512 compatible = "renesas,sdhi-r8a7796",
2516 "renesas 2513 "renesas,rcar-gen3-sdhi";
2517 reg = <0 0xee160000 0 2514 reg = <0 0xee160000 0 0x2000>;
2518 interrupts = <GIC_SPI 2515 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
2519 clocks = <&cpg CPG_MO 2516 clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A7796_CLK_SD3H>;
2520 clock-names = "core", 2517 clock-names = "core", "clkh";
2521 max-frequency = <2000 2518 max-frequency = <200000000>;
2522 power-domains = <&sys 2519 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2523 resets = <&cpg 311>; 2520 resets = <&cpg 311>;
2524 iommus = <&ipmmu_ds1 2521 iommus = <&ipmmu_ds1 35>;
2525 status = "disabled"; 2522 status = "disabled";
2526 }; 2523 };
2527 2524
2528 rpc: spi@ee200000 { 2525 rpc: spi@ee200000 {
2529 compatible = "renesas 2526 compatible = "renesas,r8a7796-rpc-if",
2530 "renesas 2527 "renesas,rcar-gen3-rpc-if";
2531 reg = <0 0xee200000 0 2528 reg = <0 0xee200000 0 0x200>,
2532 <0 0x08000000 0 2529 <0 0x08000000 0 0x04000000>,
2533 <0 0xee208000 0 2530 <0 0xee208000 0 0x100>;
2534 reg-names = "regs", " 2531 reg-names = "regs", "dirmap", "wbuf";
2535 interrupts = <GIC_SPI 2532 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
2536 clocks = <&cpg CPG_MO 2533 clocks = <&cpg CPG_MOD 917>;
2537 power-domains = <&sys 2534 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2538 resets = <&cpg 917>; 2535 resets = <&cpg 917>;
2539 #address-cells = <1>; 2536 #address-cells = <1>;
2540 #size-cells = <0>; 2537 #size-cells = <0>;
2541 status = "disabled"; 2538 status = "disabled";
2542 }; 2539 };
2543 2540
2544 gic: interrupt-controller@f10 2541 gic: interrupt-controller@f1010000 {
2545 compatible = "arm,gic 2542 compatible = "arm,gic-400";
2546 #interrupt-cells = <3 2543 #interrupt-cells = <3>;
2547 #address-cells = <0>; 2544 #address-cells = <0>;
2548 interrupt-controller; 2545 interrupt-controller;
2549 reg = <0x0 0xf1010000 2546 reg = <0x0 0xf1010000 0 0x1000>,
2550 <0x0 0xf1020000 2547 <0x0 0xf1020000 0 0x20000>,
2551 <0x0 0xf1040000 2548 <0x0 0xf1040000 0 0x20000>,
2552 <0x0 0xf1060000 2549 <0x0 0xf1060000 0 0x20000>;
2553 interrupts = <GIC_PPI 2550 interrupts = <GIC_PPI 9
2554 (GIC_ 2551 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
2555 clocks = <&cpg CPG_MO 2552 clocks = <&cpg CPG_MOD 408>;
2556 clock-names = "clk"; 2553 clock-names = "clk";
2557 power-domains = <&sys 2554 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2558 resets = <&cpg 408>; 2555 resets = <&cpg 408>;
2559 }; 2556 };
2560 2557
2561 pciec0: pcie@fe000000 { 2558 pciec0: pcie@fe000000 {
2562 compatible = "renesas 2559 compatible = "renesas,pcie-r8a7796",
2563 "renesas 2560 "renesas,pcie-rcar-gen3";
2564 reg = <0 0xfe000000 0 2561 reg = <0 0xfe000000 0 0x80000>;
2565 #address-cells = <3>; 2562 #address-cells = <3>;
2566 #size-cells = <2>; 2563 #size-cells = <2>;
2567 bus-range = <0x00 0xf 2564 bus-range = <0x00 0xff>;
2568 device_type = "pci"; 2565 device_type = "pci";
2569 ranges = <0x01000000 2566 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
2570 <0x02000000 2567 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
2571 <0x02000000 2568 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
2572 <0x42000000 2569 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
2573 /* Map all possible D !! 2570 /* Map all possible DDR as inbound ranges */
2574 dma-ranges = <0x42000 !! 2571 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
2575 interrupts = <GIC_SPI 2572 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
2576 <GIC_SPI 117 2573 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
2577 <GIC_SPI 118 2574 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
2578 #interrupt-cells = <1 2575 #interrupt-cells = <1>;
2579 interrupt-map-mask = 2576 interrupt-map-mask = <0 0 0 0>;
2580 interrupt-map = <0 0 2577 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
2581 clocks = <&cpg CPG_MO 2578 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
2582 clock-names = "pcie", 2579 clock-names = "pcie", "pcie_bus";
2583 power-domains = <&sys 2580 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2584 resets = <&cpg 319>; 2581 resets = <&cpg 319>;
2585 iommu-map = <0 &ipmmu <<
2586 iommu-map-mask = <0>; <<
2587 status = "disabled"; 2582 status = "disabled";
2588 }; 2583 };
2589 2584
2590 pciec1: pcie@ee800000 { 2585 pciec1: pcie@ee800000 {
2591 compatible = "renesas 2586 compatible = "renesas,pcie-r8a7796",
2592 "renesas 2587 "renesas,pcie-rcar-gen3";
2593 reg = <0 0xee800000 0 2588 reg = <0 0xee800000 0 0x80000>;
2594 #address-cells = <3>; 2589 #address-cells = <3>;
2595 #size-cells = <2>; 2590 #size-cells = <2>;
2596 bus-range = <0x00 0xf 2591 bus-range = <0x00 0xff>;
2597 device_type = "pci"; 2592 device_type = "pci";
2598 ranges = <0x01000000 2593 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
2599 <0x02000000 2594 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
2600 <0x02000000 2595 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
2601 <0x42000000 2596 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
2602 /* Map all possible D !! 2597 /* Map all possible DDR as inbound ranges */
2603 dma-ranges = <0x42000 !! 2598 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
2604 interrupts = <GIC_SPI 2599 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
2605 <GIC_SPI 149 2600 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
2606 <GIC_SPI 150 2601 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
2607 #interrupt-cells = <1 2602 #interrupt-cells = <1>;
2608 interrupt-map-mask = 2603 interrupt-map-mask = <0 0 0 0>;
2609 interrupt-map = <0 0 2604 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2610 clocks = <&cpg CPG_MO 2605 clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>;
2611 clock-names = "pcie", 2606 clock-names = "pcie", "pcie_bus";
2612 power-domains = <&sys 2607 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2613 resets = <&cpg 318>; 2608 resets = <&cpg 318>;
2614 iommu-map = <0 &ipmmu <<
2615 iommu-map-mask = <0>; <<
2616 status = "disabled"; 2609 status = "disabled";
2617 }; 2610 };
2618 2611
2619 imr-lx4@fe860000 { 2612 imr-lx4@fe860000 {
2620 compatible = "renesas 2613 compatible = "renesas,r8a7796-imr-lx4",
2621 "renesas 2614 "renesas,imr-lx4";
2622 reg = <0 0xfe860000 0 2615 reg = <0 0xfe860000 0 0x2000>;
2623 interrupts = <GIC_SPI 2616 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
2624 clocks = <&cpg CPG_MO 2617 clocks = <&cpg CPG_MOD 823>;
2625 power-domains = <&sys 2618 power-domains = <&sysc R8A7796_PD_A3VC>;
2626 resets = <&cpg 823>; 2619 resets = <&cpg 823>;
2627 }; 2620 };
2628 2621
2629 imr-lx4@fe870000 { 2622 imr-lx4@fe870000 {
2630 compatible = "renesas 2623 compatible = "renesas,r8a7796-imr-lx4",
2631 "renesas 2624 "renesas,imr-lx4";
2632 reg = <0 0xfe870000 0 2625 reg = <0 0xfe870000 0 0x2000>;
2633 interrupts = <GIC_SPI 2626 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
2634 clocks = <&cpg CPG_MO 2627 clocks = <&cpg CPG_MOD 822>;
2635 power-domains = <&sys 2628 power-domains = <&sysc R8A7796_PD_A3VC>;
2636 resets = <&cpg 822>; 2629 resets = <&cpg 822>;
2637 }; 2630 };
2638 2631
2639 fdp1@fe940000 { 2632 fdp1@fe940000 {
2640 compatible = "renesas 2633 compatible = "renesas,fdp1";
2641 reg = <0 0xfe940000 0 2634 reg = <0 0xfe940000 0 0x2400>;
2642 interrupts = <GIC_SPI 2635 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
2643 clocks = <&cpg CPG_MO 2636 clocks = <&cpg CPG_MOD 119>;
2644 power-domains = <&sys 2637 power-domains = <&sysc R8A7796_PD_A3VC>;
2645 resets = <&cpg 119>; 2638 resets = <&cpg 119>;
2646 renesas,fcp = <&fcpf0 2639 renesas,fcp = <&fcpf0>;
2647 }; 2640 };
2648 2641
2649 fcpf0: fcp@fe950000 { 2642 fcpf0: fcp@fe950000 {
2650 compatible = "renesas 2643 compatible = "renesas,fcpf";
2651 reg = <0 0xfe950000 0 2644 reg = <0 0xfe950000 0 0x200>;
2652 clocks = <&cpg CPG_MO 2645 clocks = <&cpg CPG_MOD 615>;
2653 power-domains = <&sys 2646 power-domains = <&sysc R8A7796_PD_A3VC>;
2654 resets = <&cpg 615>; 2647 resets = <&cpg 615>;
2655 iommus = <&ipmmu_vc0 <<
2656 }; 2648 };
2657 2649
2658 fcpvb0: fcp@fe96f000 { 2650 fcpvb0: fcp@fe96f000 {
2659 compatible = "renesas 2651 compatible = "renesas,fcpv";
2660 reg = <0 0xfe96f000 0 2652 reg = <0 0xfe96f000 0 0x200>;
2661 clocks = <&cpg CPG_MO 2653 clocks = <&cpg CPG_MOD 607>;
2662 power-domains = <&sys 2654 power-domains = <&sysc R8A7796_PD_A3VC>;
2663 resets = <&cpg 607>; 2655 resets = <&cpg 607>;
2664 iommus = <&ipmmu_vi0 <<
2665 }; 2656 };
2666 2657
2667 fcpvi0: fcp@fe9af000 { 2658 fcpvi0: fcp@fe9af000 {
2668 compatible = "renesas 2659 compatible = "renesas,fcpv";
2669 reg = <0 0xfe9af000 0 2660 reg = <0 0xfe9af000 0 0x200>;
2670 clocks = <&cpg CPG_MO 2661 clocks = <&cpg CPG_MOD 611>;
2671 power-domains = <&sys 2662 power-domains = <&sysc R8A7796_PD_A3VC>;
2672 resets = <&cpg 611>; 2663 resets = <&cpg 611>;
2673 iommus = <&ipmmu_vc0 2664 iommus = <&ipmmu_vc0 19>;
2674 }; 2665 };
2675 2666
2676 fcpvd0: fcp@fea27000 { 2667 fcpvd0: fcp@fea27000 {
2677 compatible = "renesas 2668 compatible = "renesas,fcpv";
2678 reg = <0 0xfea27000 0 2669 reg = <0 0xfea27000 0 0x200>;
2679 clocks = <&cpg CPG_MO 2670 clocks = <&cpg CPG_MOD 603>;
2680 power-domains = <&sys 2671 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2681 resets = <&cpg 603>; 2672 resets = <&cpg 603>;
2682 iommus = <&ipmmu_vi0 2673 iommus = <&ipmmu_vi0 8>;
2683 }; 2674 };
2684 2675
2685 fcpvd1: fcp@fea2f000 { 2676 fcpvd1: fcp@fea2f000 {
2686 compatible = "renesas 2677 compatible = "renesas,fcpv";
2687 reg = <0 0xfea2f000 0 2678 reg = <0 0xfea2f000 0 0x200>;
2688 clocks = <&cpg CPG_MO 2679 clocks = <&cpg CPG_MOD 602>;
2689 power-domains = <&sys 2680 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2690 resets = <&cpg 602>; 2681 resets = <&cpg 602>;
2691 iommus = <&ipmmu_vi0 2682 iommus = <&ipmmu_vi0 9>;
2692 }; 2683 };
2693 2684
2694 fcpvd2: fcp@fea37000 { 2685 fcpvd2: fcp@fea37000 {
2695 compatible = "renesas 2686 compatible = "renesas,fcpv";
2696 reg = <0 0xfea37000 0 2687 reg = <0 0xfea37000 0 0x200>;
2697 clocks = <&cpg CPG_MO 2688 clocks = <&cpg CPG_MOD 601>;
2698 power-domains = <&sys 2689 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2699 resets = <&cpg 601>; 2690 resets = <&cpg 601>;
2700 iommus = <&ipmmu_vi0 2691 iommus = <&ipmmu_vi0 10>;
2701 }; 2692 };
2702 2693
2703 vspb: vsp@fe960000 { 2694 vspb: vsp@fe960000 {
2704 compatible = "renesas 2695 compatible = "renesas,vsp2";
2705 reg = <0 0xfe960000 0 2696 reg = <0 0xfe960000 0 0x8000>;
2706 interrupts = <GIC_SPI 2697 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
2707 clocks = <&cpg CPG_MO 2698 clocks = <&cpg CPG_MOD 626>;
2708 power-domains = <&sys 2699 power-domains = <&sysc R8A7796_PD_A3VC>;
2709 resets = <&cpg 626>; 2700 resets = <&cpg 626>;
2710 2701
2711 renesas,fcp = <&fcpvb 2702 renesas,fcp = <&fcpvb0>;
2712 }; 2703 };
2713 2704
2714 vspd0: vsp@fea20000 { 2705 vspd0: vsp@fea20000 {
2715 compatible = "renesas 2706 compatible = "renesas,vsp2";
2716 reg = <0 0xfea20000 0 2707 reg = <0 0xfea20000 0 0x5000>;
2717 interrupts = <GIC_SPI 2708 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
2718 clocks = <&cpg CPG_MO 2709 clocks = <&cpg CPG_MOD 623>;
2719 power-domains = <&sys 2710 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2720 resets = <&cpg 623>; 2711 resets = <&cpg 623>;
2721 2712
2722 renesas,fcp = <&fcpvd 2713 renesas,fcp = <&fcpvd0>;
2723 }; 2714 };
2724 2715
2725 vspd1: vsp@fea28000 { 2716 vspd1: vsp@fea28000 {
2726 compatible = "renesas 2717 compatible = "renesas,vsp2";
2727 reg = <0 0xfea28000 0 2718 reg = <0 0xfea28000 0 0x5000>;
2728 interrupts = <GIC_SPI 2719 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
2729 clocks = <&cpg CPG_MO 2720 clocks = <&cpg CPG_MOD 622>;
2730 power-domains = <&sys 2721 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2731 resets = <&cpg 622>; 2722 resets = <&cpg 622>;
2732 2723
2733 renesas,fcp = <&fcpvd 2724 renesas,fcp = <&fcpvd1>;
2734 }; 2725 };
2735 2726
2736 vspd2: vsp@fea30000 { 2727 vspd2: vsp@fea30000 {
2737 compatible = "renesas 2728 compatible = "renesas,vsp2";
2738 reg = <0 0xfea30000 0 2729 reg = <0 0xfea30000 0 0x5000>;
2739 interrupts = <GIC_SPI 2730 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
2740 clocks = <&cpg CPG_MO 2731 clocks = <&cpg CPG_MOD 621>;
2741 power-domains = <&sys 2732 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2742 resets = <&cpg 621>; 2733 resets = <&cpg 621>;
2743 2734
2744 renesas,fcp = <&fcpvd 2735 renesas,fcp = <&fcpvd2>;
2745 }; 2736 };
2746 2737
2747 vspi0: vsp@fe9a0000 { 2738 vspi0: vsp@fe9a0000 {
2748 compatible = "renesas 2739 compatible = "renesas,vsp2";
2749 reg = <0 0xfe9a0000 0 2740 reg = <0 0xfe9a0000 0 0x8000>;
2750 interrupts = <GIC_SPI 2741 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
2751 clocks = <&cpg CPG_MO 2742 clocks = <&cpg CPG_MOD 631>;
2752 power-domains = <&sys 2743 power-domains = <&sysc R8A7796_PD_A3VC>;
2753 resets = <&cpg 631>; 2744 resets = <&cpg 631>;
2754 2745
2755 renesas,fcp = <&fcpvi 2746 renesas,fcp = <&fcpvi0>;
2756 }; 2747 };
2757 2748
2758 cmm0: cmm@fea40000 { 2749 cmm0: cmm@fea40000 {
2759 compatible = "renesas 2750 compatible = "renesas,r8a7796-cmm",
2760 "renesas 2751 "renesas,rcar-gen3-cmm";
2761 reg = <0 0xfea40000 0 2752 reg = <0 0xfea40000 0 0x1000>;
2762 power-domains = <&sys 2753 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2763 clocks = <&cpg CPG_MO 2754 clocks = <&cpg CPG_MOD 711>;
2764 resets = <&cpg 711>; 2755 resets = <&cpg 711>;
2765 }; 2756 };
2766 2757
2767 cmm1: cmm@fea50000 { 2758 cmm1: cmm@fea50000 {
2768 compatible = "renesas 2759 compatible = "renesas,r8a7796-cmm",
2769 "renesas 2760 "renesas,rcar-gen3-cmm";
2770 reg = <0 0xfea50000 0 2761 reg = <0 0xfea50000 0 0x1000>;
2771 power-domains = <&sys 2762 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2772 clocks = <&cpg CPG_MO 2763 clocks = <&cpg CPG_MOD 710>;
2773 resets = <&cpg 710>; 2764 resets = <&cpg 710>;
2774 }; 2765 };
2775 2766
2776 cmm2: cmm@fea60000 { 2767 cmm2: cmm@fea60000 {
2777 compatible = "renesas 2768 compatible = "renesas,r8a7796-cmm",
2778 "renesas 2769 "renesas,rcar-gen3-cmm";
2779 reg = <0 0xfea60000 0 2770 reg = <0 0xfea60000 0 0x1000>;
2780 power-domains = <&sys 2771 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2781 clocks = <&cpg CPG_MO 2772 clocks = <&cpg CPG_MOD 709>;
2782 resets = <&cpg 709>; 2773 resets = <&cpg 709>;
2783 }; 2774 };
2784 2775
2785 csi20: csi2@fea80000 { 2776 csi20: csi2@fea80000 {
2786 compatible = "renesas 2777 compatible = "renesas,r8a7796-csi2";
2787 reg = <0 0xfea80000 0 2778 reg = <0 0xfea80000 0 0x10000>;
2788 interrupts = <GIC_SPI 2779 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
2789 clocks = <&cpg CPG_MO 2780 clocks = <&cpg CPG_MOD 714>;
2790 power-domains = <&sys 2781 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2791 resets = <&cpg 714>; 2782 resets = <&cpg 714>;
2792 status = "disabled"; 2783 status = "disabled";
2793 2784
2794 ports { 2785 ports {
2795 #address-cell 2786 #address-cells = <1>;
2796 #size-cells = 2787 #size-cells = <0>;
2797 2788
2798 port@0 { 2789 port@0 {
2799 reg = 2790 reg = <0>;
2800 }; 2791 };
2801 2792
2802 port@1 { 2793 port@1 {
2803 #addr 2794 #address-cells = <1>;
2804 #size 2795 #size-cells = <0>;
2805 2796
2806 reg = 2797 reg = <1>;
2807 2798
2808 csi20 2799 csi20vin0: endpoint@0 {
2809 2800 reg = <0>;
2810 2801 remote-endpoint = <&vin0csi20>;
2811 }; 2802 };
2812 csi20 2803 csi20vin1: endpoint@1 {
2813 2804 reg = <1>;
2814 2805 remote-endpoint = <&vin1csi20>;
2815 }; 2806 };
2816 csi20 2807 csi20vin2: endpoint@2 {
2817 2808 reg = <2>;
2818 2809 remote-endpoint = <&vin2csi20>;
2819 }; 2810 };
2820 csi20 2811 csi20vin3: endpoint@3 {
2821 2812 reg = <3>;
2822 2813 remote-endpoint = <&vin3csi20>;
2823 }; 2814 };
2824 csi20 2815 csi20vin4: endpoint@4 {
2825 2816 reg = <4>;
2826 2817 remote-endpoint = <&vin4csi20>;
2827 }; 2818 };
2828 csi20 2819 csi20vin5: endpoint@5 {
2829 2820 reg = <5>;
2830 2821 remote-endpoint = <&vin5csi20>;
2831 }; 2822 };
2832 csi20 2823 csi20vin6: endpoint@6 {
2833 2824 reg = <6>;
2834 2825 remote-endpoint = <&vin6csi20>;
2835 }; 2826 };
2836 csi20 2827 csi20vin7: endpoint@7 {
2837 2828 reg = <7>;
2838 2829 remote-endpoint = <&vin7csi20>;
2839 }; 2830 };
2840 }; 2831 };
2841 }; 2832 };
2842 }; 2833 };
2843 2834
2844 csi40: csi2@feaa0000 { 2835 csi40: csi2@feaa0000 {
2845 compatible = "renesas 2836 compatible = "renesas,r8a7796-csi2";
2846 reg = <0 0xfeaa0000 0 2837 reg = <0 0xfeaa0000 0 0x10000>;
2847 interrupts = <GIC_SPI 2838 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
2848 clocks = <&cpg CPG_MO 2839 clocks = <&cpg CPG_MOD 716>;
2849 power-domains = <&sys 2840 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2850 resets = <&cpg 716>; 2841 resets = <&cpg 716>;
2851 status = "disabled"; 2842 status = "disabled";
2852 2843
2853 ports { 2844 ports {
2854 #address-cell 2845 #address-cells = <1>;
2855 #size-cells = 2846 #size-cells = <0>;
2856 2847
2857 port@0 { 2848 port@0 {
2858 reg = 2849 reg = <0>;
2859 }; 2850 };
2860 2851
2861 port@1 { 2852 port@1 {
2862 #addr 2853 #address-cells = <1>;
2863 #size 2854 #size-cells = <0>;
2864 2855
2865 reg = 2856 reg = <1>;
2866 2857
2867 csi40 2858 csi40vin0: endpoint@0 {
2868 2859 reg = <0>;
2869 2860 remote-endpoint = <&vin0csi40>;
2870 }; 2861 };
2871 csi40 2862 csi40vin1: endpoint@1 {
2872 2863 reg = <1>;
2873 2864 remote-endpoint = <&vin1csi40>;
2874 }; 2865 };
2875 csi40 2866 csi40vin2: endpoint@2 {
2876 2867 reg = <2>;
2877 2868 remote-endpoint = <&vin2csi40>;
2878 }; 2869 };
2879 csi40 2870 csi40vin3: endpoint@3 {
2880 2871 reg = <3>;
2881 2872 remote-endpoint = <&vin3csi40>;
2882 }; 2873 };
2883 csi40 2874 csi40vin4: endpoint@4 {
2884 2875 reg = <4>;
2885 2876 remote-endpoint = <&vin4csi40>;
2886 }; 2877 };
2887 csi40 2878 csi40vin5: endpoint@5 {
2888 2879 reg = <5>;
2889 2880 remote-endpoint = <&vin5csi40>;
2890 }; 2881 };
2891 csi40 2882 csi40vin6: endpoint@6 {
2892 2883 reg = <6>;
2893 2884 remote-endpoint = <&vin6csi40>;
2894 }; 2885 };
2895 csi40 2886 csi40vin7: endpoint@7 {
2896 2887 reg = <7>;
2897 2888 remote-endpoint = <&vin7csi40>;
2898 }; 2889 };
2899 }; 2890 };
2900 2891
2901 }; 2892 };
2902 }; 2893 };
2903 2894
2904 hdmi0: hdmi@fead0000 { 2895 hdmi0: hdmi@fead0000 {
2905 compatible = "renesas 2896 compatible = "renesas,r8a7796-hdmi", "renesas,rcar-gen3-hdmi";
2906 reg = <0 0xfead0000 0 2897 reg = <0 0xfead0000 0 0x10000>;
2907 interrupts = <GIC_SPI 2898 interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
2908 clocks = <&cpg CPG_MO 2899 clocks = <&cpg CPG_MOD 729>, <&cpg CPG_CORE R8A7796_CLK_HDMI>;
2909 clock-names = "iahb", 2900 clock-names = "iahb", "isfr";
2910 power-domains = <&sys 2901 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2911 resets = <&cpg 729>; 2902 resets = <&cpg 729>;
2912 status = "disabled"; 2903 status = "disabled";
2913 2904
2914 ports { 2905 ports {
2915 #address-cell 2906 #address-cells = <1>;
2916 #size-cells = 2907 #size-cells = <0>;
2917 port@0 { 2908 port@0 {
2918 reg = 2909 reg = <0>;
2919 dw_hd 2910 dw_hdmi0_in: endpoint {
2920 2911 remote-endpoint = <&du_out_hdmi0>;
2921 }; 2912 };
2922 }; 2913 };
2923 port@1 { 2914 port@1 {
2924 reg = 2915 reg = <1>;
2925 }; 2916 };
2926 port@2 { 2917 port@2 {
2927 /* HD 2918 /* HDMI sound */
2928 reg = 2919 reg = <2>;
2929 }; 2920 };
2930 }; 2921 };
2931 }; 2922 };
2932 2923
2933 du: display@feb00000 { 2924 du: display@feb00000 {
2934 compatible = "renesas 2925 compatible = "renesas,du-r8a7796";
2935 reg = <0 0xfeb00000 0 2926 reg = <0 0xfeb00000 0 0x70000>;
2936 interrupts = <GIC_SPI 2927 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
2937 <GIC_SPI 2928 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
2938 <GIC_SPI 2929 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
2939 clocks = <&cpg CPG_MO 2930 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
2940 <&cpg CPG_MO 2931 <&cpg CPG_MOD 722>;
2941 clock-names = "du.0", 2932 clock-names = "du.0", "du.1", "du.2";
2942 resets = <&cpg 724>, 2933 resets = <&cpg 724>, <&cpg 722>;
2943 reset-names = "du.0", 2934 reset-names = "du.0", "du.2";
2944 2935
2945 renesas,cmms = <&cmm0 2936 renesas,cmms = <&cmm0>, <&cmm1>, <&cmm2>;
2946 renesas,vsps = <&vspd 2937 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>;
2947 2938
2948 status = "disabled"; 2939 status = "disabled";
2949 2940
2950 ports { 2941 ports {
2951 #address-cell 2942 #address-cells = <1>;
2952 #size-cells = 2943 #size-cells = <0>;
2953 2944
2954 port@0 { 2945 port@0 {
2955 reg = 2946 reg = <0>;
2956 }; 2947 };
2957 port@1 { 2948 port@1 {
2958 reg = 2949 reg = <1>;
2959 du_ou 2950 du_out_hdmi0: endpoint {
2960 2951 remote-endpoint = <&dw_hdmi0_in>;
2961 }; 2952 };
2962 }; 2953 };
2963 port@2 { 2954 port@2 {
2964 reg = 2955 reg = <2>;
2965 du_ou 2956 du_out_lvds0: endpoint {
2966 2957 remote-endpoint = <&lvds0_in>;
2967 }; 2958 };
2968 }; 2959 };
2969 }; 2960 };
2970 }; 2961 };
2971 2962
2972 lvds0: lvds@feb90000 { 2963 lvds0: lvds@feb90000 {
2973 compatible = "renesas 2964 compatible = "renesas,r8a7796-lvds";
2974 reg = <0 0xfeb90000 0 2965 reg = <0 0xfeb90000 0 0x14>;
2975 clocks = <&cpg CPG_MO 2966 clocks = <&cpg CPG_MOD 727>;
2976 power-domains = <&sys 2967 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2977 resets = <&cpg 727>; 2968 resets = <&cpg 727>;
2978 status = "disabled"; 2969 status = "disabled";
2979 2970
2980 ports { 2971 ports {
2981 #address-cell 2972 #address-cells = <1>;
2982 #size-cells = 2973 #size-cells = <0>;
2983 2974
2984 port@0 { 2975 port@0 {
2985 reg = 2976 reg = <0>;
2986 lvds0 2977 lvds0_in: endpoint {
2987 2978 remote-endpoint = <&du_out_lvds0>;
2988 }; 2979 };
2989 }; 2980 };
2990 port@1 { 2981 port@1 {
2991 reg = 2982 reg = <1>;
2992 }; 2983 };
2993 }; 2984 };
2994 }; 2985 };
2995 2986
2996 prr: chipid@fff00044 { 2987 prr: chipid@fff00044 {
2997 compatible = "renesas 2988 compatible = "renesas,prr";
2998 reg = <0 0xfff00044 0 2989 reg = <0 0xfff00044 0 4>;
2999 }; 2990 };
3000 }; 2991 };
3001 2992
3002 thermal-zones { 2993 thermal-zones {
3003 sensor1_thermal: sensor1-ther 2994 sensor1_thermal: sensor1-thermal {
3004 polling-delay-passive 2995 polling-delay-passive = <250>;
3005 polling-delay = <1000 2996 polling-delay = <1000>;
3006 thermal-sensors = <&t 2997 thermal-sensors = <&tsc 0>;
3007 sustainable-power = < 2998 sustainable-power = <3874>;
3008 2999
3009 trips { 3000 trips {
3010 sensor1_crit: 3001 sensor1_crit: sensor1-crit {
3011 tempe 3002 temperature = <120000>;
3012 hyste 3003 hysteresis = <1000>;
3013 type 3004 type = "critical";
3014 }; 3005 };
3015 }; 3006 };
3016 }; 3007 };
3017 3008
3018 sensor2_thermal: sensor2-ther 3009 sensor2_thermal: sensor2-thermal {
3019 polling-delay-passive 3010 polling-delay-passive = <250>;
3020 polling-delay = <1000 3011 polling-delay = <1000>;
3021 thermal-sensors = <&t 3012 thermal-sensors = <&tsc 1>;
3022 sustainable-power = < 3013 sustainable-power = <3874>;
3023 3014
3024 trips { 3015 trips {
3025 sensor2_crit: 3016 sensor2_crit: sensor2-crit {
3026 tempe 3017 temperature = <120000>;
3027 hyste 3018 hysteresis = <1000>;
3028 type 3019 type = "critical";
3029 }; 3020 };
3030 }; 3021 };
3031 }; 3022 };
3032 3023
3033 sensor3_thermal: sensor3-ther 3024 sensor3_thermal: sensor3-thermal {
3034 polling-delay-passive 3025 polling-delay-passive = <250>;
3035 polling-delay = <1000 3026 polling-delay = <1000>;
3036 thermal-sensors = <&t 3027 thermal-sensors = <&tsc 2>;
3037 sustainable-power = < 3028 sustainable-power = <3874>;
3038 3029
3039 cooling-maps { 3030 cooling-maps {
3040 map0 { 3031 map0 {
3041 trip 3032 trip = <&target>;
3042 cooli 3033 cooling-device = <&a57_0 2 4>;
3043 contr 3034 contribution = <1024>;
3044 }; 3035 };
3045 map1 { 3036 map1 {
3046 trip 3037 trip = <&target>;
3047 cooli 3038 cooling-device = <&a53_0 0 2>;
3048 contr 3039 contribution = <1024>;
3049 }; 3040 };
3050 }; 3041 };
3051 trips { 3042 trips {
3052 target: trip- 3043 target: trip-point1 {
3053 tempe 3044 temperature = <100000>;
3054 hyste 3045 hysteresis = <1000>;
3055 type 3046 type = "passive";
3056 }; 3047 };
3057 3048
3058 sensor3_crit: 3049 sensor3_crit: sensor3-crit {
3059 tempe 3050 temperature = <120000>;
3060 hyste 3051 hysteresis = <1000>;
3061 type 3052 type = "critical";
3062 }; 3053 };
3063 }; 3054 };
3064 }; 3055 };
3065 }; 3056 };
3066 3057
3067 timer { 3058 timer {
3068 compatible = "arm,armv8-timer 3059 compatible = "arm,armv8-timer";
3069 interrupts-extended = <&gic G 3060 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
3070 <&gic G 3061 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
3071 <&gic G 3062 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
3072 <&gic G 3063 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
3073 interrupt-names = "sec-phys", <<
3074 }; 3064 };
3075 3065
3076 /* External USB clocks - can be overr 3066 /* External USB clocks - can be overridden by the board */
3077 usb3s0_clk: usb3s0 { 3067 usb3s0_clk: usb3s0 {
3078 compatible = "fixed-clock"; 3068 compatible = "fixed-clock";
3079 #clock-cells = <0>; 3069 #clock-cells = <0>;
3080 clock-frequency = <0>; 3070 clock-frequency = <0>;
3081 }; 3071 };
3082 3072
3083 usb_extal_clk: usb_extal { 3073 usb_extal_clk: usb_extal {
3084 compatible = "fixed-clock"; 3074 compatible = "fixed-clock";
3085 #clock-cells = <0>; 3075 #clock-cells = <0>;
3086 clock-frequency = <0>; 3076 clock-frequency = <0>;
3087 }; 3077 };
3088 }; 3078 };
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