1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * Device Tree Source for the R-Car M3-W (R8A7 3 * Device Tree Source for the R-Car M3-W (R8A77960) SoC
4 * 4 *
5 * Copyright (C) 2016-2017 Renesas Electronics 5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
6 */ 6 */
7 7
8 #include <dt-bindings/clock/r8a7796-cpg-mssr.h 8 #include <dt-bindings/clock/r8a7796-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm 9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a7796-sysc.h> 10 #include <dt-bindings/power/r8a7796-sysc.h>
11 11
12 / { 12 / {
13 compatible = "renesas,r8a7796"; 13 compatible = "renesas,r8a7796";
14 #address-cells = <2>; 14 #address-cells = <2>;
15 #size-cells = <2>; 15 #size-cells = <2>;
16 16
17 /* 17 /*
18 * The external audio clocks are confi 18 * The external audio clocks are configured as 0 Hz fixed frequency
19 * clocks by default. 19 * clocks by default.
20 * Boards that provide audio clocks sh 20 * Boards that provide audio clocks should override them.
21 */ 21 */
22 audio_clk_a: audio_clk_a { 22 audio_clk_a: audio_clk_a {
23 compatible = "fixed-clock"; 23 compatible = "fixed-clock";
24 #clock-cells = <0>; 24 #clock-cells = <0>;
25 clock-frequency = <0>; 25 clock-frequency = <0>;
26 }; 26 };
27 27
28 audio_clk_b: audio_clk_b { 28 audio_clk_b: audio_clk_b {
29 compatible = "fixed-clock"; 29 compatible = "fixed-clock";
30 #clock-cells = <0>; 30 #clock-cells = <0>;
31 clock-frequency = <0>; 31 clock-frequency = <0>;
32 }; 32 };
33 33
34 audio_clk_c: audio_clk_c { 34 audio_clk_c: audio_clk_c {
35 compatible = "fixed-clock"; 35 compatible = "fixed-clock";
36 #clock-cells = <0>; 36 #clock-cells = <0>;
37 clock-frequency = <0>; 37 clock-frequency = <0>;
38 }; 38 };
39 39
40 /* External CAN clock - to be overridd 40 /* External CAN clock - to be overridden by boards that provide it */
41 can_clk: can { 41 can_clk: can {
42 compatible = "fixed-clock"; 42 compatible = "fixed-clock";
43 #clock-cells = <0>; 43 #clock-cells = <0>;
44 clock-frequency = <0>; 44 clock-frequency = <0>;
45 }; 45 };
46 46
47 cluster0_opp: opp-table-0 { 47 cluster0_opp: opp-table-0 {
48 compatible = "operating-points 48 compatible = "operating-points-v2";
49 opp-shared; 49 opp-shared;
50 50
51 opp-500000000 { 51 opp-500000000 {
52 opp-hz = /bits/ 64 <50 52 opp-hz = /bits/ 64 <500000000>;
53 opp-microvolt = <83000 53 opp-microvolt = <830000>;
54 clock-latency-ns = <30 54 clock-latency-ns = <300000>;
55 }; 55 };
56 opp-1000000000 { 56 opp-1000000000 {
57 opp-hz = /bits/ 64 <10 57 opp-hz = /bits/ 64 <1000000000>;
58 opp-microvolt = <83000 58 opp-microvolt = <830000>;
59 clock-latency-ns = <30 59 clock-latency-ns = <300000>;
60 }; 60 };
61 opp-1500000000 { 61 opp-1500000000 {
62 opp-hz = /bits/ 64 <15 62 opp-hz = /bits/ 64 <1500000000>;
63 opp-microvolt = <83000 63 opp-microvolt = <830000>;
64 clock-latency-ns = <30 64 clock-latency-ns = <300000>;
65 opp-suspend; 65 opp-suspend;
66 }; 66 };
67 opp-1600000000 { 67 opp-1600000000 {
68 opp-hz = /bits/ 64 <16 68 opp-hz = /bits/ 64 <1600000000>;
69 opp-microvolt = <90000 69 opp-microvolt = <900000>;
70 clock-latency-ns = <30 70 clock-latency-ns = <300000>;
71 }; 71 };
72 opp-1700000000 { 72 opp-1700000000 {
73 opp-hz = /bits/ 64 <17 73 opp-hz = /bits/ 64 <1700000000>;
74 opp-microvolt = <90000 74 opp-microvolt = <900000>;
75 clock-latency-ns = <30 75 clock-latency-ns = <300000>;
76 }; 76 };
77 opp-1800000000 { 77 opp-1800000000 {
78 opp-hz = /bits/ 64 <18 78 opp-hz = /bits/ 64 <1800000000>;
79 opp-microvolt = <96000 79 opp-microvolt = <960000>;
80 clock-latency-ns = <30 80 clock-latency-ns = <300000>;
81 turbo-mode; 81 turbo-mode;
82 }; 82 };
83 }; 83 };
84 84
85 cluster1_opp: opp-table-1 { 85 cluster1_opp: opp-table-1 {
86 compatible = "operating-points 86 compatible = "operating-points-v2";
87 opp-shared; 87 opp-shared;
88 88
89 opp-800000000 { 89 opp-800000000 {
90 opp-hz = /bits/ 64 <80 90 opp-hz = /bits/ 64 <800000000>;
91 opp-microvolt = <82000 91 opp-microvolt = <820000>;
92 clock-latency-ns = <30 92 clock-latency-ns = <300000>;
93 }; 93 };
94 opp-1000000000 { 94 opp-1000000000 {
95 opp-hz = /bits/ 64 <10 95 opp-hz = /bits/ 64 <1000000000>;
96 opp-microvolt = <82000 96 opp-microvolt = <820000>;
97 clock-latency-ns = <30 97 clock-latency-ns = <300000>;
98 }; 98 };
99 opp-1200000000 { 99 opp-1200000000 {
100 opp-hz = /bits/ 64 <12 100 opp-hz = /bits/ 64 <1200000000>;
101 opp-microvolt = <82000 101 opp-microvolt = <820000>;
102 clock-latency-ns = <30 102 clock-latency-ns = <300000>;
103 }; 103 };
104 opp-1300000000 { 104 opp-1300000000 {
105 opp-hz = /bits/ 64 <13 105 opp-hz = /bits/ 64 <1300000000>;
106 opp-microvolt = <82000 106 opp-microvolt = <820000>;
107 clock-latency-ns = <30 107 clock-latency-ns = <300000>;
108 turbo-mode; 108 turbo-mode;
109 }; 109 };
110 }; 110 };
111 111
112 cpus { 112 cpus {
113 #address-cells = <1>; 113 #address-cells = <1>;
114 #size-cells = <0>; 114 #size-cells = <0>;
115 115
116 cpu-map { 116 cpu-map {
117 cluster0 { 117 cluster0 {
118 core0 { 118 core0 {
119 cpu = 119 cpu = <&a57_0>;
120 }; 120 };
121 core1 { 121 core1 {
122 cpu = 122 cpu = <&a57_1>;
123 }; 123 };
124 }; 124 };
125 125
126 cluster1 { 126 cluster1 {
127 core0 { 127 core0 {
128 cpu = 128 cpu = <&a53_0>;
129 }; 129 };
130 core1 { 130 core1 {
131 cpu = 131 cpu = <&a53_1>;
132 }; 132 };
133 core2 { 133 core2 {
134 cpu = 134 cpu = <&a53_2>;
135 }; 135 };
136 core3 { 136 core3 {
137 cpu = 137 cpu = <&a53_3>;
138 }; 138 };
139 }; 139 };
140 }; 140 };
141 141
142 a57_0: cpu@0 { 142 a57_0: cpu@0 {
143 compatible = "arm,cort 143 compatible = "arm,cortex-a57";
144 reg = <0x0>; 144 reg = <0x0>;
145 device_type = "cpu"; 145 device_type = "cpu";
146 power-domains = <&sysc 146 power-domains = <&sysc R8A7796_PD_CA57_CPU0>;
147 next-level-cache = <&L 147 next-level-cache = <&L2_CA57>;
148 enable-method = "psci" 148 enable-method = "psci";
149 cpu-idle-states = <&CP 149 cpu-idle-states = <&CPU_SLEEP_0>;
150 dynamic-power-coeffici 150 dynamic-power-coefficient = <854>;
151 clocks = <&cpg CPG_COR 151 clocks = <&cpg CPG_CORE R8A7796_CLK_Z>;
152 operating-points-v2 = 152 operating-points-v2 = <&cluster0_opp>;
153 capacity-dmips-mhz = < 153 capacity-dmips-mhz = <1024>;
154 #cooling-cells = <2>; 154 #cooling-cells = <2>;
155 }; 155 };
156 156
157 a57_1: cpu@1 { 157 a57_1: cpu@1 {
158 compatible = "arm,cort 158 compatible = "arm,cortex-a57";
159 reg = <0x1>; 159 reg = <0x1>;
160 device_type = "cpu"; 160 device_type = "cpu";
161 power-domains = <&sysc 161 power-domains = <&sysc R8A7796_PD_CA57_CPU1>;
162 next-level-cache = <&L 162 next-level-cache = <&L2_CA57>;
163 enable-method = "psci" 163 enable-method = "psci";
164 cpu-idle-states = <&CP 164 cpu-idle-states = <&CPU_SLEEP_0>;
165 clocks = <&cpg CPG_COR 165 clocks = <&cpg CPG_CORE R8A7796_CLK_Z>;
166 operating-points-v2 = 166 operating-points-v2 = <&cluster0_opp>;
167 capacity-dmips-mhz = < 167 capacity-dmips-mhz = <1024>;
168 #cooling-cells = <2>; 168 #cooling-cells = <2>;
169 }; 169 };
170 170
171 a53_0: cpu@100 { 171 a53_0: cpu@100 {
172 compatible = "arm,cort 172 compatible = "arm,cortex-a53";
173 reg = <0x100>; 173 reg = <0x100>;
174 device_type = "cpu"; 174 device_type = "cpu";
175 power-domains = <&sysc 175 power-domains = <&sysc R8A7796_PD_CA53_CPU0>;
176 next-level-cache = <&L 176 next-level-cache = <&L2_CA53>;
177 enable-method = "psci" 177 enable-method = "psci";
178 cpu-idle-states = <&CP 178 cpu-idle-states = <&CPU_SLEEP_1>;
179 #cooling-cells = <2>; 179 #cooling-cells = <2>;
180 dynamic-power-coeffici 180 dynamic-power-coefficient = <277>;
181 clocks = <&cpg CPG_COR 181 clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
182 operating-points-v2 = 182 operating-points-v2 = <&cluster1_opp>;
183 capacity-dmips-mhz = < 183 capacity-dmips-mhz = <535>;
184 }; 184 };
185 185
186 a53_1: cpu@101 { 186 a53_1: cpu@101 {
187 compatible = "arm,cort 187 compatible = "arm,cortex-a53";
188 reg = <0x101>; 188 reg = <0x101>;
189 device_type = "cpu"; 189 device_type = "cpu";
190 power-domains = <&sysc 190 power-domains = <&sysc R8A7796_PD_CA53_CPU1>;
191 next-level-cache = <&L 191 next-level-cache = <&L2_CA53>;
192 enable-method = "psci" 192 enable-method = "psci";
193 cpu-idle-states = <&CP 193 cpu-idle-states = <&CPU_SLEEP_1>;
194 clocks = <&cpg CPG_COR 194 clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
195 operating-points-v2 = 195 operating-points-v2 = <&cluster1_opp>;
196 capacity-dmips-mhz = < 196 capacity-dmips-mhz = <535>;
197 }; 197 };
198 198
199 a53_2: cpu@102 { 199 a53_2: cpu@102 {
200 compatible = "arm,cort 200 compatible = "arm,cortex-a53";
201 reg = <0x102>; 201 reg = <0x102>;
202 device_type = "cpu"; 202 device_type = "cpu";
203 power-domains = <&sysc 203 power-domains = <&sysc R8A7796_PD_CA53_CPU2>;
204 next-level-cache = <&L 204 next-level-cache = <&L2_CA53>;
205 enable-method = "psci" 205 enable-method = "psci";
206 cpu-idle-states = <&CP 206 cpu-idle-states = <&CPU_SLEEP_1>;
207 clocks = <&cpg CPG_COR 207 clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
208 operating-points-v2 = 208 operating-points-v2 = <&cluster1_opp>;
209 capacity-dmips-mhz = < 209 capacity-dmips-mhz = <535>;
210 }; 210 };
211 211
212 a53_3: cpu@103 { 212 a53_3: cpu@103 {
213 compatible = "arm,cort 213 compatible = "arm,cortex-a53";
214 reg = <0x103>; 214 reg = <0x103>;
215 device_type = "cpu"; 215 device_type = "cpu";
216 power-domains = <&sysc 216 power-domains = <&sysc R8A7796_PD_CA53_CPU3>;
217 next-level-cache = <&L 217 next-level-cache = <&L2_CA53>;
218 enable-method = "psci" 218 enable-method = "psci";
219 cpu-idle-states = <&CP 219 cpu-idle-states = <&CPU_SLEEP_1>;
220 clocks = <&cpg CPG_COR 220 clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
221 operating-points-v2 = 221 operating-points-v2 = <&cluster1_opp>;
222 capacity-dmips-mhz = < 222 capacity-dmips-mhz = <535>;
223 }; 223 };
224 224
225 L2_CA57: cache-controller-0 { 225 L2_CA57: cache-controller-0 {
226 compatible = "cache"; 226 compatible = "cache";
227 power-domains = <&sysc 227 power-domains = <&sysc R8A7796_PD_CA57_SCU>;
228 cache-unified; 228 cache-unified;
229 cache-level = <2>; 229 cache-level = <2>;
230 }; 230 };
231 231
232 L2_CA53: cache-controller-1 { 232 L2_CA53: cache-controller-1 {
233 compatible = "cache"; 233 compatible = "cache";
234 power-domains = <&sysc 234 power-domains = <&sysc R8A7796_PD_CA53_SCU>;
235 cache-unified; 235 cache-unified;
236 cache-level = <2>; 236 cache-level = <2>;
237 }; 237 };
238 238
239 idle-states { 239 idle-states {
240 entry-method = "psci"; 240 entry-method = "psci";
241 241
242 CPU_SLEEP_0: cpu-sleep 242 CPU_SLEEP_0: cpu-sleep-0 {
243 compatible = " 243 compatible = "arm,idle-state";
244 arm,psci-suspe 244 arm,psci-suspend-param = <0x0010000>;
245 local-timer-st 245 local-timer-stop;
246 entry-latency- 246 entry-latency-us = <400>;
247 exit-latency-u 247 exit-latency-us = <500>;
248 min-residency- 248 min-residency-us = <4000>;
249 }; 249 };
250 250
251 CPU_SLEEP_1: cpu-sleep 251 CPU_SLEEP_1: cpu-sleep-1 {
252 compatible = " 252 compatible = "arm,idle-state";
253 arm,psci-suspe 253 arm,psci-suspend-param = <0x0010000>;
254 local-timer-st 254 local-timer-stop;
255 entry-latency- 255 entry-latency-us = <700>;
256 exit-latency-u 256 exit-latency-us = <700>;
257 min-residency- 257 min-residency-us = <5000>;
258 }; 258 };
259 }; 259 };
260 }; 260 };
261 261
262 extal_clk: extal { 262 extal_clk: extal {
263 compatible = "fixed-clock"; 263 compatible = "fixed-clock";
264 #clock-cells = <0>; 264 #clock-cells = <0>;
265 /* This value must be overridd 265 /* This value must be overridden by the board */
266 clock-frequency = <0>; 266 clock-frequency = <0>;
267 }; 267 };
268 268
269 extalr_clk: extalr { 269 extalr_clk: extalr {
270 compatible = "fixed-clock"; 270 compatible = "fixed-clock";
271 #clock-cells = <0>; 271 #clock-cells = <0>;
272 /* This value must be overridd 272 /* This value must be overridden by the board */
273 clock-frequency = <0>; 273 clock-frequency = <0>;
274 }; 274 };
275 275
276 /* External PCIe clock - can be overri 276 /* External PCIe clock - can be overridden by the board */
277 pcie_bus_clk: pcie_bus { 277 pcie_bus_clk: pcie_bus {
278 compatible = "fixed-clock"; 278 compatible = "fixed-clock";
279 #clock-cells = <0>; 279 #clock-cells = <0>;
280 clock-frequency = <0>; 280 clock-frequency = <0>;
281 }; 281 };
282 282
283 pmu_a53 { 283 pmu_a53 {
284 compatible = "arm,cortex-a53-p 284 compatible = "arm,cortex-a53-pmu";
285 interrupts-extended = <&gic GI 285 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
286 <&gic GI 286 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
287 <&gic GI 287 <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
288 <&gic GI 288 <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
289 interrupt-affinity = <&a53_0>, 289 interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>;
290 }; 290 };
291 291
292 pmu_a57 { 292 pmu_a57 {
293 compatible = "arm,cortex-a57-p 293 compatible = "arm,cortex-a57-pmu";
294 interrupts-extended = <&gic GI 294 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
295 <&gic GI 295 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
296 interrupt-affinity = <&a57_0>, 296 interrupt-affinity = <&a57_0>, <&a57_1>;
297 }; 297 };
298 298
299 psci { 299 psci {
300 compatible = "arm,psci-1.0", " 300 compatible = "arm,psci-1.0", "arm,psci-0.2";
301 method = "smc"; 301 method = "smc";
302 }; 302 };
303 303
304 /* External SCIF clock - to be overrid 304 /* External SCIF clock - to be overridden by boards that provide it */
305 scif_clk: scif { 305 scif_clk: scif {
306 compatible = "fixed-clock"; 306 compatible = "fixed-clock";
307 #clock-cells = <0>; 307 #clock-cells = <0>;
308 clock-frequency = <0>; 308 clock-frequency = <0>;
309 }; 309 };
310 310
311 soc { 311 soc {
312 compatible = "simple-bus"; 312 compatible = "simple-bus";
313 interrupt-parent = <&gic>; 313 interrupt-parent = <&gic>;
314 #address-cells = <2>; 314 #address-cells = <2>;
315 #size-cells = <2>; 315 #size-cells = <2>;
316 ranges; 316 ranges;
317 317
318 rwdt: watchdog@e6020000 { 318 rwdt: watchdog@e6020000 {
319 compatible = "renesas, 319 compatible = "renesas,r8a7796-wdt",
320 "renesas, 320 "renesas,rcar-gen3-wdt";
321 reg = <0 0xe6020000 0 321 reg = <0 0xe6020000 0 0x0c>;
322 interrupts = <GIC_SPI 322 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
323 clocks = <&cpg CPG_MOD 323 clocks = <&cpg CPG_MOD 402>;
324 power-domains = <&sysc 324 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
325 resets = <&cpg 402>; 325 resets = <&cpg 402>;
326 status = "disabled"; 326 status = "disabled";
327 }; 327 };
328 328
329 gpio0: gpio@e6050000 { 329 gpio0: gpio@e6050000 {
330 compatible = "renesas, 330 compatible = "renesas,gpio-r8a7796",
331 "renesas, 331 "renesas,rcar-gen3-gpio";
332 reg = <0 0xe6050000 0 332 reg = <0 0xe6050000 0 0x50>;
333 interrupts = <GIC_SPI 333 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
334 #gpio-cells = <2>; 334 #gpio-cells = <2>;
335 gpio-controller; 335 gpio-controller;
336 gpio-ranges = <&pfc 0 336 gpio-ranges = <&pfc 0 0 16>;
337 #interrupt-cells = <2> 337 #interrupt-cells = <2>;
338 interrupt-controller; 338 interrupt-controller;
339 clocks = <&cpg CPG_MOD 339 clocks = <&cpg CPG_MOD 912>;
340 power-domains = <&sysc 340 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
341 resets = <&cpg 912>; 341 resets = <&cpg 912>;
342 }; 342 };
343 343
344 gpio1: gpio@e6051000 { 344 gpio1: gpio@e6051000 {
345 compatible = "renesas, 345 compatible = "renesas,gpio-r8a7796",
346 "renesas, 346 "renesas,rcar-gen3-gpio";
347 reg = <0 0xe6051000 0 347 reg = <0 0xe6051000 0 0x50>;
348 interrupts = <GIC_SPI 348 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
349 #gpio-cells = <2>; 349 #gpio-cells = <2>;
350 gpio-controller; 350 gpio-controller;
351 gpio-ranges = <&pfc 0 351 gpio-ranges = <&pfc 0 32 29>;
352 #interrupt-cells = <2> 352 #interrupt-cells = <2>;
353 interrupt-controller; 353 interrupt-controller;
354 clocks = <&cpg CPG_MOD 354 clocks = <&cpg CPG_MOD 911>;
355 power-domains = <&sysc 355 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
356 resets = <&cpg 911>; 356 resets = <&cpg 911>;
357 }; 357 };
358 358
359 gpio2: gpio@e6052000 { 359 gpio2: gpio@e6052000 {
360 compatible = "renesas, 360 compatible = "renesas,gpio-r8a7796",
361 "renesas, 361 "renesas,rcar-gen3-gpio";
362 reg = <0 0xe6052000 0 362 reg = <0 0xe6052000 0 0x50>;
363 interrupts = <GIC_SPI 363 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
364 #gpio-cells = <2>; 364 #gpio-cells = <2>;
365 gpio-controller; 365 gpio-controller;
366 gpio-ranges = <&pfc 0 366 gpio-ranges = <&pfc 0 64 15>;
367 #interrupt-cells = <2> 367 #interrupt-cells = <2>;
368 interrupt-controller; 368 interrupt-controller;
369 clocks = <&cpg CPG_MOD 369 clocks = <&cpg CPG_MOD 910>;
370 power-domains = <&sysc 370 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
371 resets = <&cpg 910>; 371 resets = <&cpg 910>;
372 }; 372 };
373 373
374 gpio3: gpio@e6053000 { 374 gpio3: gpio@e6053000 {
375 compatible = "renesas, 375 compatible = "renesas,gpio-r8a7796",
376 "renesas, 376 "renesas,rcar-gen3-gpio";
377 reg = <0 0xe6053000 0 377 reg = <0 0xe6053000 0 0x50>;
378 interrupts = <GIC_SPI 378 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
379 #gpio-cells = <2>; 379 #gpio-cells = <2>;
380 gpio-controller; 380 gpio-controller;
381 gpio-ranges = <&pfc 0 381 gpio-ranges = <&pfc 0 96 16>;
382 #interrupt-cells = <2> 382 #interrupt-cells = <2>;
383 interrupt-controller; 383 interrupt-controller;
384 clocks = <&cpg CPG_MOD 384 clocks = <&cpg CPG_MOD 909>;
385 power-domains = <&sysc 385 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
386 resets = <&cpg 909>; 386 resets = <&cpg 909>;
387 }; 387 };
388 388
389 gpio4: gpio@e6054000 { 389 gpio4: gpio@e6054000 {
390 compatible = "renesas, 390 compatible = "renesas,gpio-r8a7796",
391 "renesas, 391 "renesas,rcar-gen3-gpio";
392 reg = <0 0xe6054000 0 392 reg = <0 0xe6054000 0 0x50>;
393 interrupts = <GIC_SPI 393 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
394 #gpio-cells = <2>; 394 #gpio-cells = <2>;
395 gpio-controller; 395 gpio-controller;
396 gpio-ranges = <&pfc 0 396 gpio-ranges = <&pfc 0 128 18>;
397 #interrupt-cells = <2> 397 #interrupt-cells = <2>;
398 interrupt-controller; 398 interrupt-controller;
399 clocks = <&cpg CPG_MOD 399 clocks = <&cpg CPG_MOD 908>;
400 power-domains = <&sysc 400 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
401 resets = <&cpg 908>; 401 resets = <&cpg 908>;
402 }; 402 };
403 403
404 gpio5: gpio@e6055000 { 404 gpio5: gpio@e6055000 {
405 compatible = "renesas, 405 compatible = "renesas,gpio-r8a7796",
406 "renesas, 406 "renesas,rcar-gen3-gpio";
407 reg = <0 0xe6055000 0 407 reg = <0 0xe6055000 0 0x50>;
408 interrupts = <GIC_SPI 408 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
409 #gpio-cells = <2>; 409 #gpio-cells = <2>;
410 gpio-controller; 410 gpio-controller;
411 gpio-ranges = <&pfc 0 411 gpio-ranges = <&pfc 0 160 26>;
412 #interrupt-cells = <2> 412 #interrupt-cells = <2>;
413 interrupt-controller; 413 interrupt-controller;
414 clocks = <&cpg CPG_MOD 414 clocks = <&cpg CPG_MOD 907>;
415 power-domains = <&sysc 415 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
416 resets = <&cpg 907>; 416 resets = <&cpg 907>;
417 }; 417 };
418 418
419 gpio6: gpio@e6055400 { 419 gpio6: gpio@e6055400 {
420 compatible = "renesas, 420 compatible = "renesas,gpio-r8a7796",
421 "renesas, 421 "renesas,rcar-gen3-gpio";
422 reg = <0 0xe6055400 0 422 reg = <0 0xe6055400 0 0x50>;
423 interrupts = <GIC_SPI 423 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
424 #gpio-cells = <2>; 424 #gpio-cells = <2>;
425 gpio-controller; 425 gpio-controller;
426 gpio-ranges = <&pfc 0 426 gpio-ranges = <&pfc 0 192 32>;
427 #interrupt-cells = <2> 427 #interrupt-cells = <2>;
428 interrupt-controller; 428 interrupt-controller;
429 clocks = <&cpg CPG_MOD 429 clocks = <&cpg CPG_MOD 906>;
430 power-domains = <&sysc 430 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
431 resets = <&cpg 906>; 431 resets = <&cpg 906>;
432 }; 432 };
433 433
434 gpio7: gpio@e6055800 { 434 gpio7: gpio@e6055800 {
435 compatible = "renesas, 435 compatible = "renesas,gpio-r8a7796",
436 "renesas, 436 "renesas,rcar-gen3-gpio";
437 reg = <0 0xe6055800 0 437 reg = <0 0xe6055800 0 0x50>;
438 interrupts = <GIC_SPI 438 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
439 #gpio-cells = <2>; 439 #gpio-cells = <2>;
440 gpio-controller; 440 gpio-controller;
441 gpio-ranges = <&pfc 0 441 gpio-ranges = <&pfc 0 224 4>;
442 #interrupt-cells = <2> 442 #interrupt-cells = <2>;
443 interrupt-controller; 443 interrupt-controller;
444 clocks = <&cpg CPG_MOD 444 clocks = <&cpg CPG_MOD 905>;
445 power-domains = <&sysc 445 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
446 resets = <&cpg 905>; 446 resets = <&cpg 905>;
447 }; 447 };
448 448
449 pfc: pinctrl@e6060000 { 449 pfc: pinctrl@e6060000 {
450 compatible = "renesas, 450 compatible = "renesas,pfc-r8a7796";
451 reg = <0 0xe6060000 0 451 reg = <0 0xe6060000 0 0x50c>;
452 }; 452 };
453 453
454 cmt0: timer@e60f0000 { 454 cmt0: timer@e60f0000 {
455 compatible = "renesas, 455 compatible = "renesas,r8a7796-cmt0",
456 "renesas, 456 "renesas,rcar-gen3-cmt0";
457 reg = <0 0xe60f0000 0 457 reg = <0 0xe60f0000 0 0x1004>;
458 interrupts = <GIC_SPI 458 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
459 <GIC_SPI 459 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
460 clocks = <&cpg CPG_MOD 460 clocks = <&cpg CPG_MOD 303>;
461 clock-names = "fck"; 461 clock-names = "fck";
462 power-domains = <&sysc 462 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
463 resets = <&cpg 303>; 463 resets = <&cpg 303>;
464 status = "disabled"; 464 status = "disabled";
465 }; 465 };
466 466
467 cmt1: timer@e6130000 { 467 cmt1: timer@e6130000 {
468 compatible = "renesas, 468 compatible = "renesas,r8a7796-cmt1",
469 "renesas, 469 "renesas,rcar-gen3-cmt1";
470 reg = <0 0xe6130000 0 470 reg = <0 0xe6130000 0 0x1004>;
471 interrupts = <GIC_SPI 471 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
472 <GIC_SPI 472 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
473 <GIC_SPI 473 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
474 <GIC_SPI 474 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
475 <GIC_SPI 475 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
476 <GIC_SPI 476 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
477 <GIC_SPI 477 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
478 <GIC_SPI 478 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
479 clocks = <&cpg CPG_MOD 479 clocks = <&cpg CPG_MOD 302>;
480 clock-names = "fck"; 480 clock-names = "fck";
481 power-domains = <&sysc 481 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
482 resets = <&cpg 302>; 482 resets = <&cpg 302>;
483 status = "disabled"; 483 status = "disabled";
484 }; 484 };
485 485
486 cmt2: timer@e6140000 { 486 cmt2: timer@e6140000 {
487 compatible = "renesas, 487 compatible = "renesas,r8a7796-cmt1",
488 "renesas, 488 "renesas,rcar-gen3-cmt1";
489 reg = <0 0xe6140000 0 489 reg = <0 0xe6140000 0 0x1004>;
490 interrupts = <GIC_SPI 490 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
491 <GIC_SPI 491 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
492 <GIC_SPI 492 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
493 <GIC_SPI 493 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
494 <GIC_SPI 494 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
495 <GIC_SPI 495 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
496 <GIC_SPI 496 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
497 <GIC_SPI 497 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
498 clocks = <&cpg CPG_MOD 498 clocks = <&cpg CPG_MOD 301>;
499 clock-names = "fck"; 499 clock-names = "fck";
500 power-domains = <&sysc 500 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
501 resets = <&cpg 301>; 501 resets = <&cpg 301>;
502 status = "disabled"; 502 status = "disabled";
503 }; 503 };
504 504
505 cmt3: timer@e6148000 { 505 cmt3: timer@e6148000 {
506 compatible = "renesas, 506 compatible = "renesas,r8a7796-cmt1",
507 "renesas, 507 "renesas,rcar-gen3-cmt1";
508 reg = <0 0xe6148000 0 508 reg = <0 0xe6148000 0 0x1004>;
509 interrupts = <GIC_SPI 509 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
510 <GIC_SPI 510 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
511 <GIC_SPI 511 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
512 <GIC_SPI 512 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
513 <GIC_SPI 513 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
514 <GIC_SPI 514 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
515 <GIC_SPI 515 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
516 <GIC_SPI 516 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
517 clocks = <&cpg CPG_MOD 517 clocks = <&cpg CPG_MOD 300>;
518 clock-names = "fck"; 518 clock-names = "fck";
519 power-domains = <&sysc 519 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
520 resets = <&cpg 300>; 520 resets = <&cpg 300>;
521 status = "disabled"; 521 status = "disabled";
522 }; 522 };
523 523
524 cpg: clock-controller@e6150000 524 cpg: clock-controller@e6150000 {
525 compatible = "renesas, 525 compatible = "renesas,r8a7796-cpg-mssr";
526 reg = <0 0xe6150000 0 526 reg = <0 0xe6150000 0 0x1000>;
527 clocks = <&extal_clk>, 527 clocks = <&extal_clk>, <&extalr_clk>;
528 clock-names = "extal", 528 clock-names = "extal", "extalr";
529 #clock-cells = <2>; 529 #clock-cells = <2>;
530 #power-domain-cells = 530 #power-domain-cells = <0>;
531 #reset-cells = <1>; 531 #reset-cells = <1>;
532 }; 532 };
533 533
534 rst: reset-controller@e6160000 534 rst: reset-controller@e6160000 {
535 compatible = "renesas, 535 compatible = "renesas,r8a7796-rst";
536 reg = <0 0xe6160000 0 536 reg = <0 0xe6160000 0 0x0200>;
537 }; 537 };
538 538
539 sysc: system-controller@e61800 539 sysc: system-controller@e6180000 {
540 compatible = "renesas, 540 compatible = "renesas,r8a7796-sysc";
541 reg = <0 0xe6180000 0 541 reg = <0 0xe6180000 0 0x0400>;
542 #power-domain-cells = 542 #power-domain-cells = <1>;
543 }; 543 };
544 544
545 tsc: thermal@e6198000 { 545 tsc: thermal@e6198000 {
546 compatible = "renesas, 546 compatible = "renesas,r8a7796-thermal";
547 reg = <0 0xe6198000 0 547 reg = <0 0xe6198000 0 0x100>,
548 <0 0xe61a0000 0 548 <0 0xe61a0000 0 0x100>,
549 <0 0xe61a8000 0 549 <0 0xe61a8000 0 0x100>;
550 interrupts = <GIC_SPI 550 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
551 <GIC_SPI 551 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
552 <GIC_SPI 552 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
553 clocks = <&cpg CPG_MOD 553 clocks = <&cpg CPG_MOD 522>;
554 power-domains = <&sysc 554 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
555 resets = <&cpg 522>; 555 resets = <&cpg 522>;
556 #thermal-sensor-cells 556 #thermal-sensor-cells = <1>;
557 }; 557 };
558 558
559 intc_ex: interrupt-controller@ 559 intc_ex: interrupt-controller@e61c0000 {
560 compatible = "renesas, 560 compatible = "renesas,intc-ex-r8a7796", "renesas,irqc";
561 #interrupt-cells = <2> 561 #interrupt-cells = <2>;
562 interrupt-controller; 562 interrupt-controller;
563 reg = <0 0xe61c0000 0 563 reg = <0 0xe61c0000 0 0x200>;
564 interrupts = <GIC_SPI 564 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
565 <GIC_SPI 565 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
566 <GIC_SPI 566 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
567 <GIC_SPI 567 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
568 <GIC_SPI 568 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
569 <GIC_SPI 569 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
570 clocks = <&cpg CPG_MOD 570 clocks = <&cpg CPG_MOD 407>;
571 power-domains = <&sysc 571 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
572 resets = <&cpg 407>; 572 resets = <&cpg 407>;
573 }; 573 };
574 574
575 tmu0: timer@e61e0000 { 575 tmu0: timer@e61e0000 {
576 compatible = "renesas, 576 compatible = "renesas,tmu-r8a7796", "renesas,tmu";
577 reg = <0 0xe61e0000 0 577 reg = <0 0xe61e0000 0 0x30>;
578 interrupts = <GIC_SPI 578 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
579 <GIC_SPI 579 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
580 <GIC_SPI 580 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
581 interrupt-names = "tun 581 interrupt-names = "tuni0", "tuni1", "tuni2";
582 clocks = <&cpg CPG_MOD 582 clocks = <&cpg CPG_MOD 125>;
583 clock-names = "fck"; 583 clock-names = "fck";
584 power-domains = <&sysc 584 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
585 resets = <&cpg 125>; 585 resets = <&cpg 125>;
586 status = "disabled"; 586 status = "disabled";
587 }; 587 };
588 588
589 tmu1: timer@e6fc0000 { 589 tmu1: timer@e6fc0000 {
590 compatible = "renesas, 590 compatible = "renesas,tmu-r8a7796", "renesas,tmu";
591 reg = <0 0xe6fc0000 0 591 reg = <0 0xe6fc0000 0 0x30>;
592 interrupts = <GIC_SPI 592 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
593 <GIC_SPI 593 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
594 <GIC_SPI 594 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
595 <GIC_SPI 595 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
596 interrupt-names = "tun 596 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
597 clocks = <&cpg CPG_MOD 597 clocks = <&cpg CPG_MOD 124>;
598 clock-names = "fck"; 598 clock-names = "fck";
599 power-domains = <&sysc 599 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
600 resets = <&cpg 124>; 600 resets = <&cpg 124>;
601 status = "disabled"; 601 status = "disabled";
602 }; 602 };
603 603
604 tmu2: timer@e6fd0000 { 604 tmu2: timer@e6fd0000 {
605 compatible = "renesas, 605 compatible = "renesas,tmu-r8a7796", "renesas,tmu";
606 reg = <0 0xe6fd0000 0 606 reg = <0 0xe6fd0000 0 0x30>;
607 interrupts = <GIC_SPI 607 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
608 <GIC_SPI 608 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
609 <GIC_SPI 609 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
610 <GIC_SPI 610 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
611 interrupt-names = "tun 611 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
612 clocks = <&cpg CPG_MOD 612 clocks = <&cpg CPG_MOD 123>;
613 clock-names = "fck"; 613 clock-names = "fck";
614 power-domains = <&sysc 614 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
615 resets = <&cpg 123>; 615 resets = <&cpg 123>;
616 status = "disabled"; 616 status = "disabled";
617 }; 617 };
618 618
619 tmu3: timer@e6fe0000 { 619 tmu3: timer@e6fe0000 {
620 compatible = "renesas, 620 compatible = "renesas,tmu-r8a7796", "renesas,tmu";
621 reg = <0 0xe6fe0000 0 621 reg = <0 0xe6fe0000 0 0x30>;
622 interrupts = <GIC_SPI 622 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
623 <GIC_SPI 623 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
624 <GIC_SPI 624 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
625 interrupt-names = "tun 625 interrupt-names = "tuni0", "tuni1", "tuni2";
626 clocks = <&cpg CPG_MOD 626 clocks = <&cpg CPG_MOD 122>;
627 clock-names = "fck"; 627 clock-names = "fck";
628 power-domains = <&sysc 628 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
629 resets = <&cpg 122>; 629 resets = <&cpg 122>;
630 status = "disabled"; 630 status = "disabled";
631 }; 631 };
632 632
633 tmu4: timer@ffc00000 { 633 tmu4: timer@ffc00000 {
634 compatible = "renesas, 634 compatible = "renesas,tmu-r8a7796", "renesas,tmu";
635 reg = <0 0xffc00000 0 635 reg = <0 0xffc00000 0 0x30>;
636 interrupts = <GIC_SPI 636 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
637 <GIC_SPI 637 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
638 <GIC_SPI 638 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
639 interrupt-names = "tun 639 interrupt-names = "tuni0", "tuni1", "tuni2";
640 clocks = <&cpg CPG_MOD 640 clocks = <&cpg CPG_MOD 121>;
641 clock-names = "fck"; 641 clock-names = "fck";
642 power-domains = <&sysc 642 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
643 resets = <&cpg 121>; 643 resets = <&cpg 121>;
644 status = "disabled"; 644 status = "disabled";
645 }; 645 };
646 646
647 i2c0: i2c@e6500000 { 647 i2c0: i2c@e6500000 {
648 #address-cells = <1>; 648 #address-cells = <1>;
649 #size-cells = <0>; 649 #size-cells = <0>;
650 compatible = "renesas, 650 compatible = "renesas,i2c-r8a7796",
651 "renesas, 651 "renesas,rcar-gen3-i2c";
652 reg = <0 0xe6500000 0 652 reg = <0 0xe6500000 0 0x40>;
653 interrupts = <GIC_SPI 653 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
654 clocks = <&cpg CPG_MOD 654 clocks = <&cpg CPG_MOD 931>;
655 power-domains = <&sysc 655 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
656 resets = <&cpg 931>; 656 resets = <&cpg 931>;
657 dmas = <&dmac1 0x91>, 657 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
658 <&dmac2 0x91>, 658 <&dmac2 0x91>, <&dmac2 0x90>;
659 dma-names = "tx", "rx" 659 dma-names = "tx", "rx", "tx", "rx";
660 i2c-scl-internal-delay 660 i2c-scl-internal-delay-ns = <110>;
661 status = "disabled"; 661 status = "disabled";
662 }; 662 };
663 663
664 i2c1: i2c@e6508000 { 664 i2c1: i2c@e6508000 {
665 #address-cells = <1>; 665 #address-cells = <1>;
666 #size-cells = <0>; 666 #size-cells = <0>;
667 compatible = "renesas, 667 compatible = "renesas,i2c-r8a7796",
668 "renesas, 668 "renesas,rcar-gen3-i2c";
669 reg = <0 0xe6508000 0 669 reg = <0 0xe6508000 0 0x40>;
670 interrupts = <GIC_SPI 670 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
671 clocks = <&cpg CPG_MOD 671 clocks = <&cpg CPG_MOD 930>;
672 power-domains = <&sysc 672 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
673 resets = <&cpg 930>; 673 resets = <&cpg 930>;
674 dmas = <&dmac1 0x93>, 674 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
675 <&dmac2 0x93>, 675 <&dmac2 0x93>, <&dmac2 0x92>;
676 dma-names = "tx", "rx" 676 dma-names = "tx", "rx", "tx", "rx";
677 i2c-scl-internal-delay 677 i2c-scl-internal-delay-ns = <6>;
678 status = "disabled"; 678 status = "disabled";
679 }; 679 };
680 680
681 i2c2: i2c@e6510000 { 681 i2c2: i2c@e6510000 {
682 #address-cells = <1>; 682 #address-cells = <1>;
683 #size-cells = <0>; 683 #size-cells = <0>;
684 compatible = "renesas, 684 compatible = "renesas,i2c-r8a7796",
685 "renesas, 685 "renesas,rcar-gen3-i2c";
686 reg = <0 0xe6510000 0 686 reg = <0 0xe6510000 0 0x40>;
687 interrupts = <GIC_SPI 687 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
688 clocks = <&cpg CPG_MOD 688 clocks = <&cpg CPG_MOD 929>;
689 power-domains = <&sysc 689 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
690 resets = <&cpg 929>; 690 resets = <&cpg 929>;
691 dmas = <&dmac1 0x95>, 691 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
692 <&dmac2 0x95>, 692 <&dmac2 0x95>, <&dmac2 0x94>;
693 dma-names = "tx", "rx" 693 dma-names = "tx", "rx", "tx", "rx";
694 i2c-scl-internal-delay 694 i2c-scl-internal-delay-ns = <6>;
695 status = "disabled"; 695 status = "disabled";
696 }; 696 };
697 697
698 i2c3: i2c@e66d0000 { 698 i2c3: i2c@e66d0000 {
699 #address-cells = <1>; 699 #address-cells = <1>;
700 #size-cells = <0>; 700 #size-cells = <0>;
701 compatible = "renesas, 701 compatible = "renesas,i2c-r8a7796",
702 "renesas, 702 "renesas,rcar-gen3-i2c";
703 reg = <0 0xe66d0000 0 703 reg = <0 0xe66d0000 0 0x40>;
704 interrupts = <GIC_SPI 704 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
705 clocks = <&cpg CPG_MOD 705 clocks = <&cpg CPG_MOD 928>;
706 power-domains = <&sysc 706 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
707 resets = <&cpg 928>; 707 resets = <&cpg 928>;
708 dmas = <&dmac0 0x97>, 708 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
709 dma-names = "tx", "rx" 709 dma-names = "tx", "rx";
710 i2c-scl-internal-delay 710 i2c-scl-internal-delay-ns = <110>;
711 status = "disabled"; 711 status = "disabled";
712 }; 712 };
713 713
714 i2c4: i2c@e66d8000 { 714 i2c4: i2c@e66d8000 {
715 #address-cells = <1>; 715 #address-cells = <1>;
716 #size-cells = <0>; 716 #size-cells = <0>;
717 compatible = "renesas, 717 compatible = "renesas,i2c-r8a7796",
718 "renesas, 718 "renesas,rcar-gen3-i2c";
719 reg = <0 0xe66d8000 0 719 reg = <0 0xe66d8000 0 0x40>;
720 interrupts = <GIC_SPI 720 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
721 clocks = <&cpg CPG_MOD 721 clocks = <&cpg CPG_MOD 927>;
722 power-domains = <&sysc 722 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
723 resets = <&cpg 927>; 723 resets = <&cpg 927>;
724 dmas = <&dmac0 0x99>, 724 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
725 dma-names = "tx", "rx" 725 dma-names = "tx", "rx";
726 i2c-scl-internal-delay 726 i2c-scl-internal-delay-ns = <110>;
727 status = "disabled"; 727 status = "disabled";
728 }; 728 };
729 729
730 i2c5: i2c@e66e0000 { 730 i2c5: i2c@e66e0000 {
731 #address-cells = <1>; 731 #address-cells = <1>;
732 #size-cells = <0>; 732 #size-cells = <0>;
733 compatible = "renesas, 733 compatible = "renesas,i2c-r8a7796",
734 "renesas, 734 "renesas,rcar-gen3-i2c";
735 reg = <0 0xe66e0000 0 735 reg = <0 0xe66e0000 0 0x40>;
736 interrupts = <GIC_SPI 736 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
737 clocks = <&cpg CPG_MOD 737 clocks = <&cpg CPG_MOD 919>;
738 power-domains = <&sysc 738 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
739 resets = <&cpg 919>; 739 resets = <&cpg 919>;
740 dmas = <&dmac0 0x9b>, 740 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
741 dma-names = "tx", "rx" 741 dma-names = "tx", "rx";
742 i2c-scl-internal-delay 742 i2c-scl-internal-delay-ns = <110>;
743 status = "disabled"; 743 status = "disabled";
744 }; 744 };
745 745
746 i2c6: i2c@e66e8000 { 746 i2c6: i2c@e66e8000 {
747 #address-cells = <1>; 747 #address-cells = <1>;
748 #size-cells = <0>; 748 #size-cells = <0>;
749 compatible = "renesas, 749 compatible = "renesas,i2c-r8a7796",
750 "renesas, 750 "renesas,rcar-gen3-i2c";
751 reg = <0 0xe66e8000 0 751 reg = <0 0xe66e8000 0 0x40>;
752 interrupts = <GIC_SPI 752 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
753 clocks = <&cpg CPG_MOD 753 clocks = <&cpg CPG_MOD 918>;
754 power-domains = <&sysc 754 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
755 resets = <&cpg 918>; 755 resets = <&cpg 918>;
756 dmas = <&dmac0 0x9d>, 756 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
757 dma-names = "tx", "rx" 757 dma-names = "tx", "rx";
758 i2c-scl-internal-delay 758 i2c-scl-internal-delay-ns = <6>;
759 status = "disabled"; 759 status = "disabled";
760 }; 760 };
761 761
762 i2c_dvfs: i2c@e60b0000 { 762 i2c_dvfs: i2c@e60b0000 {
763 #address-cells = <1>; 763 #address-cells = <1>;
764 #size-cells = <0>; 764 #size-cells = <0>;
765 compatible = "renesas, 765 compatible = "renesas,iic-r8a7796",
766 "renesas, 766 "renesas,rcar-gen3-iic",
767 "renesas, 767 "renesas,rmobile-iic";
768 reg = <0 0xe60b0000 0 768 reg = <0 0xe60b0000 0 0x425>;
769 interrupts = <GIC_SPI 769 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
770 clocks = <&cpg CPG_MOD 770 clocks = <&cpg CPG_MOD 926>;
771 power-domains = <&sysc 771 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
772 resets = <&cpg 926>; 772 resets = <&cpg 926>;
773 dmas = <&dmac0 0x11>, 773 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
774 dma-names = "tx", "rx" 774 dma-names = "tx", "rx";
775 status = "disabled"; 775 status = "disabled";
776 }; 776 };
777 777
778 hscif0: serial@e6540000 { 778 hscif0: serial@e6540000 {
779 compatible = "renesas, 779 compatible = "renesas,hscif-r8a7796",
780 "renesas, 780 "renesas,rcar-gen3-hscif",
781 "renesas, 781 "renesas,hscif";
782 reg = <0 0xe6540000 0 782 reg = <0 0xe6540000 0 0x60>;
783 interrupts = <GIC_SPI 783 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
784 clocks = <&cpg CPG_MOD 784 clocks = <&cpg CPG_MOD 520>,
785 <&cpg CPG_COR 785 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
786 <&scif_clk>; 786 <&scif_clk>;
787 clock-names = "fck", " 787 clock-names = "fck", "brg_int", "scif_clk";
788 dmas = <&dmac1 0x31>, 788 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
789 <&dmac2 0x31>, 789 <&dmac2 0x31>, <&dmac2 0x30>;
790 dma-names = "tx", "rx" 790 dma-names = "tx", "rx", "tx", "rx";
791 power-domains = <&sysc 791 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
792 resets = <&cpg 520>; 792 resets = <&cpg 520>;
793 status = "disabled"; 793 status = "disabled";
794 }; 794 };
795 795
796 hscif1: serial@e6550000 { 796 hscif1: serial@e6550000 {
797 compatible = "renesas, 797 compatible = "renesas,hscif-r8a7796",
798 "renesas, 798 "renesas,rcar-gen3-hscif",
799 "renesas, 799 "renesas,hscif";
800 reg = <0 0xe6550000 0 800 reg = <0 0xe6550000 0 0x60>;
801 interrupts = <GIC_SPI 801 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
802 clocks = <&cpg CPG_MOD 802 clocks = <&cpg CPG_MOD 519>,
803 <&cpg CPG_COR 803 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
804 <&scif_clk>; 804 <&scif_clk>;
805 clock-names = "fck", " 805 clock-names = "fck", "brg_int", "scif_clk";
806 dmas = <&dmac1 0x33>, 806 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
807 <&dmac2 0x33>, 807 <&dmac2 0x33>, <&dmac2 0x32>;
808 dma-names = "tx", "rx" 808 dma-names = "tx", "rx", "tx", "rx";
809 power-domains = <&sysc 809 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
810 resets = <&cpg 519>; 810 resets = <&cpg 519>;
811 status = "disabled"; 811 status = "disabled";
812 }; 812 };
813 813
814 hscif2: serial@e6560000 { 814 hscif2: serial@e6560000 {
815 compatible = "renesas, 815 compatible = "renesas,hscif-r8a7796",
816 "renesas, 816 "renesas,rcar-gen3-hscif",
817 "renesas, 817 "renesas,hscif";
818 reg = <0 0xe6560000 0 818 reg = <0 0xe6560000 0 0x60>;
819 interrupts = <GIC_SPI 819 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
820 clocks = <&cpg CPG_MOD 820 clocks = <&cpg CPG_MOD 518>,
821 <&cpg CPG_COR 821 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
822 <&scif_clk>; 822 <&scif_clk>;
823 clock-names = "fck", " 823 clock-names = "fck", "brg_int", "scif_clk";
824 dmas = <&dmac1 0x35>, 824 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
825 <&dmac2 0x35>, 825 <&dmac2 0x35>, <&dmac2 0x34>;
826 dma-names = "tx", "rx" 826 dma-names = "tx", "rx", "tx", "rx";
827 power-domains = <&sysc 827 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
828 resets = <&cpg 518>; 828 resets = <&cpg 518>;
829 status = "disabled"; 829 status = "disabled";
830 }; 830 };
831 831
832 hscif3: serial@e66a0000 { 832 hscif3: serial@e66a0000 {
833 compatible = "renesas, 833 compatible = "renesas,hscif-r8a7796",
834 "renesas, 834 "renesas,rcar-gen3-hscif",
835 "renesas, 835 "renesas,hscif";
836 reg = <0 0xe66a0000 0 836 reg = <0 0xe66a0000 0 0x60>;
837 interrupts = <GIC_SPI 837 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
838 clocks = <&cpg CPG_MOD 838 clocks = <&cpg CPG_MOD 517>,
839 <&cpg CPG_COR 839 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
840 <&scif_clk>; 840 <&scif_clk>;
841 clock-names = "fck", " 841 clock-names = "fck", "brg_int", "scif_clk";
842 dmas = <&dmac0 0x37>, 842 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
843 dma-names = "tx", "rx" 843 dma-names = "tx", "rx";
844 power-domains = <&sysc 844 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
845 resets = <&cpg 517>; 845 resets = <&cpg 517>;
846 status = "disabled"; 846 status = "disabled";
847 }; 847 };
848 848
849 hscif4: serial@e66b0000 { 849 hscif4: serial@e66b0000 {
850 compatible = "renesas, 850 compatible = "renesas,hscif-r8a7796",
851 "renesas, 851 "renesas,rcar-gen3-hscif",
852 "renesas, 852 "renesas,hscif";
853 reg = <0 0xe66b0000 0 853 reg = <0 0xe66b0000 0 0x60>;
854 interrupts = <GIC_SPI 854 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
855 clocks = <&cpg CPG_MOD 855 clocks = <&cpg CPG_MOD 516>,
856 <&cpg CPG_COR 856 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
857 <&scif_clk>; 857 <&scif_clk>;
858 clock-names = "fck", " 858 clock-names = "fck", "brg_int", "scif_clk";
859 dmas = <&dmac0 0x39>, 859 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
860 dma-names = "tx", "rx" 860 dma-names = "tx", "rx";
861 power-domains = <&sysc 861 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
862 resets = <&cpg 516>; 862 resets = <&cpg 516>;
863 status = "disabled"; 863 status = "disabled";
864 }; 864 };
865 865
866 hsusb: usb@e6590000 { 866 hsusb: usb@e6590000 {
867 compatible = "renesas, 867 compatible = "renesas,usbhs-r8a7796",
868 "renesas, 868 "renesas,rcar-gen3-usbhs";
869 reg = <0 0xe6590000 0 869 reg = <0 0xe6590000 0 0x200>;
870 interrupts = <GIC_SPI 870 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
871 clocks = <&cpg CPG_MOD 871 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
872 dmas = <&usb_dmac0 0>, 872 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
873 <&usb_dmac1 0>, 873 <&usb_dmac1 0>, <&usb_dmac1 1>;
874 dma-names = "ch0", "ch 874 dma-names = "ch0", "ch1", "ch2", "ch3";
875 renesas,buswait = <11> 875 renesas,buswait = <11>;
876 phys = <&usb2_phy0 3>; 876 phys = <&usb2_phy0 3>;
877 phy-names = "usb"; 877 phy-names = "usb";
878 power-domains = <&sysc 878 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
879 resets = <&cpg 704>, < 879 resets = <&cpg 704>, <&cpg 703>;
880 status = "disabled"; 880 status = "disabled";
881 }; 881 };
882 882
883 usb_dmac0: dma-controller@e65a 883 usb_dmac0: dma-controller@e65a0000 {
884 compatible = "renesas, 884 compatible = "renesas,r8a7796-usb-dmac",
885 "renesas, 885 "renesas,usb-dmac";
886 reg = <0 0xe65a0000 0 886 reg = <0 0xe65a0000 0 0x100>;
887 interrupts = <GIC_SPI 887 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
888 <GIC_SPI 888 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
889 interrupt-names = "ch0 889 interrupt-names = "ch0", "ch1";
890 clocks = <&cpg CPG_MOD 890 clocks = <&cpg CPG_MOD 330>;
891 power-domains = <&sysc 891 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
892 resets = <&cpg 330>; 892 resets = <&cpg 330>;
893 #dma-cells = <1>; 893 #dma-cells = <1>;
894 dma-channels = <2>; 894 dma-channels = <2>;
895 }; 895 };
896 896
897 usb_dmac1: dma-controller@e65b 897 usb_dmac1: dma-controller@e65b0000 {
898 compatible = "renesas, 898 compatible = "renesas,r8a7796-usb-dmac",
899 "renesas, 899 "renesas,usb-dmac";
900 reg = <0 0xe65b0000 0 900 reg = <0 0xe65b0000 0 0x100>;
901 interrupts = <GIC_SPI 901 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
902 <GIC_SPI 902 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
903 interrupt-names = "ch0 903 interrupt-names = "ch0", "ch1";
904 clocks = <&cpg CPG_MOD 904 clocks = <&cpg CPG_MOD 331>;
905 power-domains = <&sysc 905 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
906 resets = <&cpg 331>; 906 resets = <&cpg 331>;
907 #dma-cells = <1>; 907 #dma-cells = <1>;
908 dma-channels = <2>; 908 dma-channels = <2>;
909 }; 909 };
910 910
911 usb3_phy0: usb-phy@e65ee000 { 911 usb3_phy0: usb-phy@e65ee000 {
912 compatible = "renesas, 912 compatible = "renesas,r8a7796-usb3-phy",
913 "renesas, 913 "renesas,rcar-gen3-usb3-phy";
914 reg = <0 0xe65ee000 0 914 reg = <0 0xe65ee000 0 0x90>;
915 clocks = <&cpg CPG_MOD 915 clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>,
916 <&usb_extal_c 916 <&usb_extal_clk>;
917 clock-names = "usb3-if 917 clock-names = "usb3-if", "usb3s_clk", "usb_extal";
918 power-domains = <&sysc 918 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
919 resets = <&cpg 328>; 919 resets = <&cpg 328>;
920 #phy-cells = <0>; 920 #phy-cells = <0>;
921 status = "disabled"; 921 status = "disabled";
922 }; 922 };
923 923
924 arm_cc630p: crypto@e6601000 { 924 arm_cc630p: crypto@e6601000 {
925 compatible = "arm,cryp 925 compatible = "arm,cryptocell-630p-ree";
926 interrupts = <GIC_SPI 926 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
927 reg = <0x0 0xe6601000 927 reg = <0x0 0xe6601000 0 0x1000>;
928 clocks = <&cpg CPG_MOD 928 clocks = <&cpg CPG_MOD 229>;
929 resets = <&cpg 229>; 929 resets = <&cpg 229>;
930 power-domains = <&sysc 930 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
931 }; 931 };
932 932
933 dmac0: dma-controller@e6700000 933 dmac0: dma-controller@e6700000 {
934 compatible = "renesas, 934 compatible = "renesas,dmac-r8a7796",
935 "renesas, 935 "renesas,rcar-dmac";
936 reg = <0 0xe6700000 0 936 reg = <0 0xe6700000 0 0x10000>;
937 interrupts = <GIC_SPI 937 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
938 <GIC_SPI 938 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
939 <GIC_SPI 939 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
940 <GIC_SPI 940 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
941 <GIC_SPI 941 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
942 <GIC_SPI 942 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
943 <GIC_SPI 943 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
944 <GIC_SPI 944 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
945 <GIC_SPI 945 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
946 <GIC_SPI 946 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
947 <GIC_SPI 947 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
948 <GIC_SPI 948 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
949 <GIC_SPI 949 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
950 <GIC_SPI 950 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
951 <GIC_SPI 951 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
952 <GIC_SPI 952 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
953 <GIC_SPI 953 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
954 interrupt-names = "err 954 interrupt-names = "error",
955 "ch0", 955 "ch0", "ch1", "ch2", "ch3",
956 "ch4", 956 "ch4", "ch5", "ch6", "ch7",
957 "ch8", 957 "ch8", "ch9", "ch10", "ch11",
958 "ch12" 958 "ch12", "ch13", "ch14", "ch15";
959 clocks = <&cpg CPG_MOD 959 clocks = <&cpg CPG_MOD 219>;
960 clock-names = "fck"; 960 clock-names = "fck";
961 power-domains = <&sysc 961 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
962 resets = <&cpg 219>; 962 resets = <&cpg 219>;
963 #dma-cells = <1>; 963 #dma-cells = <1>;
964 dma-channels = <16>; 964 dma-channels = <16>;
965 iommus = <&ipmmu_ds0 0 965 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
966 <&ipmmu_ds0 2>, 966 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
967 <&ipmmu_ds0 4>, 967 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
968 <&ipmmu_ds0 6>, 968 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
969 <&ipmmu_ds0 8>, 969 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
970 <&ipmmu_ds0 10> 970 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
971 <&ipmmu_ds0 12> 971 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
972 <&ipmmu_ds0 14> 972 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
973 }; 973 };
974 974
975 dmac1: dma-controller@e7300000 975 dmac1: dma-controller@e7300000 {
976 compatible = "renesas, 976 compatible = "renesas,dmac-r8a7796",
977 "renesas, 977 "renesas,rcar-dmac";
978 reg = <0 0xe7300000 0 978 reg = <0 0xe7300000 0 0x10000>;
979 interrupts = <GIC_SPI 979 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
980 <GIC_SPI 980 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
981 <GIC_SPI 981 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
982 <GIC_SPI 982 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
983 <GIC_SPI 983 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
984 <GIC_SPI 984 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
985 <GIC_SPI 985 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
986 <GIC_SPI 986 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
987 <GIC_SPI 987 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
988 <GIC_SPI 988 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
989 <GIC_SPI 989 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
990 <GIC_SPI 990 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
991 <GIC_SPI 991 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
992 <GIC_SPI 992 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
993 <GIC_SPI 993 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
994 <GIC_SPI 994 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
995 <GIC_SPI 995 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
996 interrupt-names = "err 996 interrupt-names = "error",
997 "ch0", 997 "ch0", "ch1", "ch2", "ch3",
998 "ch4", 998 "ch4", "ch5", "ch6", "ch7",
999 "ch8", 999 "ch8", "ch9", "ch10", "ch11",
1000 "ch12 1000 "ch12", "ch13", "ch14", "ch15";
1001 clocks = <&cpg CPG_MO 1001 clocks = <&cpg CPG_MOD 218>;
1002 clock-names = "fck"; 1002 clock-names = "fck";
1003 power-domains = <&sys 1003 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1004 resets = <&cpg 218>; 1004 resets = <&cpg 218>;
1005 #dma-cells = <1>; 1005 #dma-cells = <1>;
1006 dma-channels = <16>; 1006 dma-channels = <16>;
1007 iommus = <&ipmmu_ds1 1007 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
1008 <&ipmmu_ds1 2> 1008 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
1009 <&ipmmu_ds1 4> 1009 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
1010 <&ipmmu_ds1 6> 1010 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
1011 <&ipmmu_ds1 8> 1011 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
1012 <&ipmmu_ds1 10 1012 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
1013 <&ipmmu_ds1 12 1013 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
1014 <&ipmmu_ds1 14 1014 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
1015 }; 1015 };
1016 1016
1017 dmac2: dma-controller@e731000 1017 dmac2: dma-controller@e7310000 {
1018 compatible = "renesas 1018 compatible = "renesas,dmac-r8a7796",
1019 "renesas 1019 "renesas,rcar-dmac";
1020 reg = <0 0xe7310000 0 1020 reg = <0 0xe7310000 0 0x10000>;
1021 interrupts = <GIC_SPI 1021 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
1022 <GIC_SPI 1022 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
1023 <GIC_SPI 1023 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
1024 <GIC_SPI 1024 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
1025 <GIC_SPI 1025 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
1026 <GIC_SPI 1026 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
1027 <GIC_SPI 1027 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
1028 <GIC_SPI 1028 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
1029 <GIC_SPI 1029 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
1030 <GIC_SPI 1030 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
1031 <GIC_SPI 1031 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
1032 <GIC_SPI 1032 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
1033 <GIC_SPI 1033 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
1034 <GIC_SPI 1034 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
1035 <GIC_SPI 1035 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
1036 <GIC_SPI 1036 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
1037 <GIC_SPI 1037 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
1038 interrupt-names = "er 1038 interrupt-names = "error",
1039 "ch0" 1039 "ch0", "ch1", "ch2", "ch3",
1040 "ch4" 1040 "ch4", "ch5", "ch6", "ch7",
1041 "ch8" 1041 "ch8", "ch9", "ch10", "ch11",
1042 "ch12 1042 "ch12", "ch13", "ch14", "ch15";
1043 clocks = <&cpg CPG_MO 1043 clocks = <&cpg CPG_MOD 217>;
1044 clock-names = "fck"; 1044 clock-names = "fck";
1045 power-domains = <&sys 1045 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1046 resets = <&cpg 217>; 1046 resets = <&cpg 217>;
1047 #dma-cells = <1>; 1047 #dma-cells = <1>;
1048 dma-channels = <16>; 1048 dma-channels = <16>;
1049 iommus = <&ipmmu_ds1 1049 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
1050 <&ipmmu_ds1 18 1050 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
1051 <&ipmmu_ds1 20 1051 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
1052 <&ipmmu_ds1 22 1052 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
1053 <&ipmmu_ds1 24 1053 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
1054 <&ipmmu_ds1 26 1054 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
1055 <&ipmmu_ds1 28 1055 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
1056 <&ipmmu_ds1 30 1056 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
1057 }; 1057 };
1058 1058
1059 ipmmu_ds0: iommu@e6740000 { 1059 ipmmu_ds0: iommu@e6740000 {
1060 compatible = "renesas 1060 compatible = "renesas,ipmmu-r8a7796";
1061 reg = <0 0xe6740000 0 1061 reg = <0 0xe6740000 0 0x1000>;
1062 renesas,ipmmu-main = 1062 renesas,ipmmu-main = <&ipmmu_mm 0>;
1063 power-domains = <&sys 1063 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1064 #iommu-cells = <1>; 1064 #iommu-cells = <1>;
1065 }; 1065 };
1066 1066
1067 ipmmu_ds1: iommu@e7740000 { 1067 ipmmu_ds1: iommu@e7740000 {
1068 compatible = "renesas 1068 compatible = "renesas,ipmmu-r8a7796";
1069 reg = <0 0xe7740000 0 1069 reg = <0 0xe7740000 0 0x1000>;
1070 renesas,ipmmu-main = 1070 renesas,ipmmu-main = <&ipmmu_mm 1>;
1071 power-domains = <&sys 1071 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1072 #iommu-cells = <1>; 1072 #iommu-cells = <1>;
1073 }; 1073 };
1074 1074
1075 ipmmu_hc: iommu@e6570000 { 1075 ipmmu_hc: iommu@e6570000 {
1076 compatible = "renesas 1076 compatible = "renesas,ipmmu-r8a7796";
1077 reg = <0 0xe6570000 0 1077 reg = <0 0xe6570000 0 0x1000>;
1078 renesas,ipmmu-main = 1078 renesas,ipmmu-main = <&ipmmu_mm 2>;
1079 power-domains = <&sys 1079 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1080 #iommu-cells = <1>; 1080 #iommu-cells = <1>;
1081 }; 1081 };
1082 1082
1083 ipmmu_ir: iommu@ff8b0000 { 1083 ipmmu_ir: iommu@ff8b0000 {
1084 compatible = "renesas 1084 compatible = "renesas,ipmmu-r8a7796";
1085 reg = <0 0xff8b0000 0 1085 reg = <0 0xff8b0000 0 0x1000>;
1086 renesas,ipmmu-main = 1086 renesas,ipmmu-main = <&ipmmu_mm 3>;
1087 power-domains = <&sys 1087 power-domains = <&sysc R8A7796_PD_A3IR>;
1088 #iommu-cells = <1>; 1088 #iommu-cells = <1>;
1089 }; 1089 };
1090 1090
1091 ipmmu_mm: iommu@e67b0000 { 1091 ipmmu_mm: iommu@e67b0000 {
1092 compatible = "renesas 1092 compatible = "renesas,ipmmu-r8a7796";
1093 reg = <0 0xe67b0000 0 1093 reg = <0 0xe67b0000 0 0x1000>;
1094 interrupts = <GIC_SPI 1094 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
1095 <GIC_SPI 1095 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
1096 power-domains = <&sys 1096 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1097 #iommu-cells = <1>; 1097 #iommu-cells = <1>;
1098 }; 1098 };
1099 1099
1100 ipmmu_mp: iommu@ec670000 { 1100 ipmmu_mp: iommu@ec670000 {
1101 compatible = "renesas 1101 compatible = "renesas,ipmmu-r8a7796";
1102 reg = <0 0xec670000 0 1102 reg = <0 0xec670000 0 0x1000>;
1103 renesas,ipmmu-main = 1103 renesas,ipmmu-main = <&ipmmu_mm 4>;
1104 power-domains = <&sys 1104 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1105 #iommu-cells = <1>; 1105 #iommu-cells = <1>;
1106 }; 1106 };
1107 1107
1108 ipmmu_pv0: iommu@fd800000 { 1108 ipmmu_pv0: iommu@fd800000 {
1109 compatible = "renesas 1109 compatible = "renesas,ipmmu-r8a7796";
1110 reg = <0 0xfd800000 0 1110 reg = <0 0xfd800000 0 0x1000>;
1111 renesas,ipmmu-main = 1111 renesas,ipmmu-main = <&ipmmu_mm 5>;
1112 power-domains = <&sys 1112 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1113 #iommu-cells = <1>; 1113 #iommu-cells = <1>;
1114 }; 1114 };
1115 1115
1116 ipmmu_pv1: iommu@fd950000 { 1116 ipmmu_pv1: iommu@fd950000 {
1117 compatible = "renesas 1117 compatible = "renesas,ipmmu-r8a7796";
1118 reg = <0 0xfd950000 0 1118 reg = <0 0xfd950000 0 0x1000>;
1119 renesas,ipmmu-main = 1119 renesas,ipmmu-main = <&ipmmu_mm 6>;
1120 power-domains = <&sys 1120 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1121 #iommu-cells = <1>; 1121 #iommu-cells = <1>;
1122 }; 1122 };
1123 1123
1124 ipmmu_rt: iommu@ffc80000 { 1124 ipmmu_rt: iommu@ffc80000 {
1125 compatible = "renesas 1125 compatible = "renesas,ipmmu-r8a7796";
1126 reg = <0 0xffc80000 0 1126 reg = <0 0xffc80000 0 0x1000>;
1127 renesas,ipmmu-main = 1127 renesas,ipmmu-main = <&ipmmu_mm 7>;
1128 power-domains = <&sys 1128 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1129 #iommu-cells = <1>; 1129 #iommu-cells = <1>;
1130 }; 1130 };
1131 1131
1132 ipmmu_vc0: iommu@fe6b0000 { 1132 ipmmu_vc0: iommu@fe6b0000 {
1133 compatible = "renesas 1133 compatible = "renesas,ipmmu-r8a7796";
1134 reg = <0 0xfe6b0000 0 1134 reg = <0 0xfe6b0000 0 0x1000>;
1135 renesas,ipmmu-main = 1135 renesas,ipmmu-main = <&ipmmu_mm 8>;
1136 power-domains = <&sys 1136 power-domains = <&sysc R8A7796_PD_A3VC>;
1137 #iommu-cells = <1>; 1137 #iommu-cells = <1>;
1138 }; 1138 };
1139 1139
1140 ipmmu_vi0: iommu@febd0000 { 1140 ipmmu_vi0: iommu@febd0000 {
1141 compatible = "renesas 1141 compatible = "renesas,ipmmu-r8a7796";
1142 reg = <0 0xfebd0000 0 1142 reg = <0 0xfebd0000 0 0x1000>;
1143 renesas,ipmmu-main = 1143 renesas,ipmmu-main = <&ipmmu_mm 9>;
1144 power-domains = <&sys 1144 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1145 #iommu-cells = <1>; 1145 #iommu-cells = <1>;
1146 }; 1146 };
1147 1147
1148 avb: ethernet@e6800000 { 1148 avb: ethernet@e6800000 {
1149 compatible = "renesas 1149 compatible = "renesas,etheravb-r8a7796",
1150 "renesas 1150 "renesas,etheravb-rcar-gen3";
1151 reg = <0 0xe6800000 0 1151 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
1152 interrupts = <GIC_SPI 1152 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
1153 <GIC_SPI 1153 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1154 <GIC_SPI 1154 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
1155 <GIC_SPI 1155 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
1156 <GIC_SPI 1156 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
1157 <GIC_SPI 1157 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
1158 <GIC_SPI 1158 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
1159 <GIC_SPI 1159 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
1160 <GIC_SPI 1160 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
1161 <GIC_SPI 1161 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
1162 <GIC_SPI 1162 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
1163 <GIC_SPI 1163 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
1164 <GIC_SPI 1164 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
1165 <GIC_SPI 1165 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
1166 <GIC_SPI 1166 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
1167 <GIC_SPI 1167 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
1168 <GIC_SPI 1168 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
1169 <GIC_SPI 1169 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
1170 <GIC_SPI 1170 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
1171 <GIC_SPI 1171 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
1172 <GIC_SPI 1172 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
1173 <GIC_SPI 1173 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
1174 <GIC_SPI 1174 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
1175 <GIC_SPI 1175 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
1176 <GIC_SPI 1176 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
1177 interrupt-names = "ch 1177 interrupt-names = "ch0", "ch1", "ch2", "ch3",
1178 "ch 1178 "ch4", "ch5", "ch6", "ch7",
1179 "ch 1179 "ch8", "ch9", "ch10", "ch11",
1180 "ch 1180 "ch12", "ch13", "ch14", "ch15",
1181 "ch 1181 "ch16", "ch17", "ch18", "ch19",
1182 "ch 1182 "ch20", "ch21", "ch22", "ch23",
1183 "ch 1183 "ch24";
1184 clocks = <&cpg CPG_MO 1184 clocks = <&cpg CPG_MOD 812>;
1185 clock-names = "fck"; 1185 clock-names = "fck";
1186 power-domains = <&sys 1186 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1187 resets = <&cpg 812>; 1187 resets = <&cpg 812>;
1188 phy-mode = "rgmii"; 1188 phy-mode = "rgmii";
1189 rx-internal-delay-ps 1189 rx-internal-delay-ps = <0>;
1190 tx-internal-delay-ps 1190 tx-internal-delay-ps = <0>;
1191 iommus = <&ipmmu_ds0 1191 iommus = <&ipmmu_ds0 16>;
1192 #address-cells = <1>; 1192 #address-cells = <1>;
1193 #size-cells = <0>; 1193 #size-cells = <0>;
1194 status = "disabled"; 1194 status = "disabled";
1195 }; 1195 };
1196 1196
1197 can0: can@e6c30000 { 1197 can0: can@e6c30000 {
1198 compatible = "renesas 1198 compatible = "renesas,can-r8a7796",
1199 "renesas 1199 "renesas,rcar-gen3-can";
1200 reg = <0 0xe6c30000 0 1200 reg = <0 0xe6c30000 0 0x1000>;
1201 interrupts = <GIC_SPI 1201 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
1202 clocks = <&cpg CPG_MO 1202 clocks = <&cpg CPG_MOD 916>,
1203 <&cpg CPG_CORE 1203 <&cpg CPG_CORE R8A7796_CLK_CANFD>,
1204 <&can_clk>; 1204 <&can_clk>;
1205 clock-names = "clkp1" 1205 clock-names = "clkp1", "clkp2", "can_clk";
1206 assigned-clocks = <&c 1206 assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>;
1207 assigned-clock-rates 1207 assigned-clock-rates = <40000000>;
1208 power-domains = <&sys 1208 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1209 resets = <&cpg 916>; 1209 resets = <&cpg 916>;
1210 status = "disabled"; 1210 status = "disabled";
1211 }; 1211 };
1212 1212
1213 can1: can@e6c38000 { 1213 can1: can@e6c38000 {
1214 compatible = "renesas 1214 compatible = "renesas,can-r8a7796",
1215 "renesas 1215 "renesas,rcar-gen3-can";
1216 reg = <0 0xe6c38000 0 1216 reg = <0 0xe6c38000 0 0x1000>;
1217 interrupts = <GIC_SPI 1217 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
1218 clocks = <&cpg CPG_MO 1218 clocks = <&cpg CPG_MOD 915>,
1219 <&cpg CPG_CORE 1219 <&cpg CPG_CORE R8A7796_CLK_CANFD>,
1220 <&can_clk>; 1220 <&can_clk>;
1221 clock-names = "clkp1" 1221 clock-names = "clkp1", "clkp2", "can_clk";
1222 assigned-clocks = <&c 1222 assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>;
1223 assigned-clock-rates 1223 assigned-clock-rates = <40000000>;
1224 power-domains = <&sys 1224 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1225 resets = <&cpg 915>; 1225 resets = <&cpg 915>;
1226 status = "disabled"; 1226 status = "disabled";
1227 }; 1227 };
1228 1228
1229 canfd: can@e66c0000 { 1229 canfd: can@e66c0000 {
1230 compatible = "renesas 1230 compatible = "renesas,r8a7796-canfd",
1231 "renesas 1231 "renesas,rcar-gen3-canfd";
1232 reg = <0 0xe66c0000 0 1232 reg = <0 0xe66c0000 0 0x8000>;
1233 interrupts = <GIC_SPI 1233 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
1234 <GIC_SPI 3 1234 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1235 interrupt-names = "ch 1235 interrupt-names = "ch_int", "g_int";
1236 clocks = <&cpg CPG_MO 1236 clocks = <&cpg CPG_MOD 914>,
1237 <&cpg CPG_CORE 1237 <&cpg CPG_CORE R8A7796_CLK_CANFD>,
1238 <&can_clk>; 1238 <&can_clk>;
1239 clock-names = "fck", 1239 clock-names = "fck", "canfd", "can_clk";
1240 assigned-clocks = <&c 1240 assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>;
1241 assigned-clock-rates 1241 assigned-clock-rates = <40000000>;
1242 power-domains = <&sys 1242 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1243 resets = <&cpg 914>; 1243 resets = <&cpg 914>;
1244 status = "disabled"; 1244 status = "disabled";
1245 1245
1246 channel0 { 1246 channel0 {
1247 status = "dis 1247 status = "disabled";
1248 }; 1248 };
1249 1249
1250 channel1 { 1250 channel1 {
1251 status = "dis 1251 status = "disabled";
1252 }; 1252 };
1253 }; 1253 };
1254 1254
1255 pwm0: pwm@e6e30000 { 1255 pwm0: pwm@e6e30000 {
1256 compatible = "renesas 1256 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
1257 reg = <0 0xe6e30000 0 1257 reg = <0 0xe6e30000 0 8>;
1258 #pwm-cells = <2>; 1258 #pwm-cells = <2>;
1259 clocks = <&cpg CPG_MO 1259 clocks = <&cpg CPG_MOD 523>;
1260 resets = <&cpg 523>; 1260 resets = <&cpg 523>;
1261 power-domains = <&sys 1261 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1262 status = "disabled"; 1262 status = "disabled";
1263 }; 1263 };
1264 1264
1265 pwm1: pwm@e6e31000 { 1265 pwm1: pwm@e6e31000 {
1266 compatible = "renesas 1266 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
1267 reg = <0 0xe6e31000 0 1267 reg = <0 0xe6e31000 0 8>;
1268 #pwm-cells = <2>; 1268 #pwm-cells = <2>;
1269 clocks = <&cpg CPG_MO 1269 clocks = <&cpg CPG_MOD 523>;
1270 resets = <&cpg 523>; 1270 resets = <&cpg 523>;
1271 power-domains = <&sys 1271 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1272 status = "disabled"; 1272 status = "disabled";
1273 }; 1273 };
1274 1274
1275 pwm2: pwm@e6e32000 { 1275 pwm2: pwm@e6e32000 {
1276 compatible = "renesas 1276 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
1277 reg = <0 0xe6e32000 0 1277 reg = <0 0xe6e32000 0 8>;
1278 #pwm-cells = <2>; 1278 #pwm-cells = <2>;
1279 clocks = <&cpg CPG_MO 1279 clocks = <&cpg CPG_MOD 523>;
1280 resets = <&cpg 523>; 1280 resets = <&cpg 523>;
1281 power-domains = <&sys 1281 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1282 status = "disabled"; 1282 status = "disabled";
1283 }; 1283 };
1284 1284
1285 pwm3: pwm@e6e33000 { 1285 pwm3: pwm@e6e33000 {
1286 compatible = "renesas 1286 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
1287 reg = <0 0xe6e33000 0 1287 reg = <0 0xe6e33000 0 8>;
1288 #pwm-cells = <2>; 1288 #pwm-cells = <2>;
1289 clocks = <&cpg CPG_MO 1289 clocks = <&cpg CPG_MOD 523>;
1290 resets = <&cpg 523>; 1290 resets = <&cpg 523>;
1291 power-domains = <&sys 1291 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1292 status = "disabled"; 1292 status = "disabled";
1293 }; 1293 };
1294 1294
1295 pwm4: pwm@e6e34000 { 1295 pwm4: pwm@e6e34000 {
1296 compatible = "renesas 1296 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
1297 reg = <0 0xe6e34000 0 1297 reg = <0 0xe6e34000 0 8>;
1298 #pwm-cells = <2>; 1298 #pwm-cells = <2>;
1299 clocks = <&cpg CPG_MO 1299 clocks = <&cpg CPG_MOD 523>;
1300 resets = <&cpg 523>; 1300 resets = <&cpg 523>;
1301 power-domains = <&sys 1301 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1302 status = "disabled"; 1302 status = "disabled";
1303 }; 1303 };
1304 1304
1305 pwm5: pwm@e6e35000 { 1305 pwm5: pwm@e6e35000 {
1306 compatible = "renesas 1306 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
1307 reg = <0 0xe6e35000 0 1307 reg = <0 0xe6e35000 0 8>;
1308 #pwm-cells = <2>; 1308 #pwm-cells = <2>;
1309 clocks = <&cpg CPG_MO 1309 clocks = <&cpg CPG_MOD 523>;
1310 resets = <&cpg 523>; 1310 resets = <&cpg 523>;
1311 power-domains = <&sys 1311 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1312 status = "disabled"; 1312 status = "disabled";
1313 }; 1313 };
1314 1314
1315 pwm6: pwm@e6e36000 { 1315 pwm6: pwm@e6e36000 {
1316 compatible = "renesas 1316 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
1317 reg = <0 0xe6e36000 0 1317 reg = <0 0xe6e36000 0 8>;
1318 #pwm-cells = <2>; 1318 #pwm-cells = <2>;
1319 clocks = <&cpg CPG_MO 1319 clocks = <&cpg CPG_MOD 523>;
1320 resets = <&cpg 523>; 1320 resets = <&cpg 523>;
1321 power-domains = <&sys 1321 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1322 status = "disabled"; 1322 status = "disabled";
1323 }; 1323 };
1324 1324
1325 scif0: serial@e6e60000 { 1325 scif0: serial@e6e60000 {
1326 compatible = "renesas 1326 compatible = "renesas,scif-r8a7796",
1327 "renesas 1327 "renesas,rcar-gen3-scif", "renesas,scif";
1328 reg = <0 0xe6e60000 0 1328 reg = <0 0xe6e60000 0 64>;
1329 interrupts = <GIC_SPI 1329 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
1330 clocks = <&cpg CPG_MO 1330 clocks = <&cpg CPG_MOD 207>,
1331 <&cpg CPG_CO 1331 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
1332 <&scif_clk>; 1332 <&scif_clk>;
1333 clock-names = "fck", 1333 clock-names = "fck", "brg_int", "scif_clk";
1334 dmas = <&dmac1 0x51>, 1334 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1335 <&dmac2 0x51>, 1335 <&dmac2 0x51>, <&dmac2 0x50>;
1336 dma-names = "tx", "rx 1336 dma-names = "tx", "rx", "tx", "rx";
1337 power-domains = <&sys 1337 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1338 resets = <&cpg 207>; 1338 resets = <&cpg 207>;
1339 status = "disabled"; 1339 status = "disabled";
1340 }; 1340 };
1341 1341
1342 scif1: serial@e6e68000 { 1342 scif1: serial@e6e68000 {
1343 compatible = "renesas 1343 compatible = "renesas,scif-r8a7796",
1344 "renesas 1344 "renesas,rcar-gen3-scif", "renesas,scif";
1345 reg = <0 0xe6e68000 0 1345 reg = <0 0xe6e68000 0 64>;
1346 interrupts = <GIC_SPI 1346 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
1347 clocks = <&cpg CPG_MO 1347 clocks = <&cpg CPG_MOD 206>,
1348 <&cpg CPG_CO 1348 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
1349 <&scif_clk>; 1349 <&scif_clk>;
1350 clock-names = "fck", 1350 clock-names = "fck", "brg_int", "scif_clk";
1351 dmas = <&dmac1 0x53>, 1351 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1352 <&dmac2 0x53>, 1352 <&dmac2 0x53>, <&dmac2 0x52>;
1353 dma-names = "tx", "rx 1353 dma-names = "tx", "rx", "tx", "rx";
1354 power-domains = <&sys 1354 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1355 resets = <&cpg 206>; 1355 resets = <&cpg 206>;
1356 status = "disabled"; 1356 status = "disabled";
1357 }; 1357 };
1358 1358
1359 scif2: serial@e6e88000 { 1359 scif2: serial@e6e88000 {
1360 compatible = "renesas 1360 compatible = "renesas,scif-r8a7796",
1361 "renesas 1361 "renesas,rcar-gen3-scif", "renesas,scif";
1362 reg = <0 0xe6e88000 0 1362 reg = <0 0xe6e88000 0 64>;
1363 interrupts = <GIC_SPI 1363 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
1364 clocks = <&cpg CPG_MO 1364 clocks = <&cpg CPG_MOD 310>,
1365 <&cpg CPG_CO 1365 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
1366 <&scif_clk>; 1366 <&scif_clk>;
1367 clock-names = "fck", 1367 clock-names = "fck", "brg_int", "scif_clk";
1368 dmas = <&dmac1 0x13>, 1368 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1369 <&dmac2 0x13>, 1369 <&dmac2 0x13>, <&dmac2 0x12>;
1370 dma-names = "tx", "rx 1370 dma-names = "tx", "rx", "tx", "rx";
1371 power-domains = <&sys 1371 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1372 resets = <&cpg 310>; 1372 resets = <&cpg 310>;
1373 status = "disabled"; 1373 status = "disabled";
1374 }; 1374 };
1375 1375
1376 scif3: serial@e6c50000 { 1376 scif3: serial@e6c50000 {
1377 compatible = "renesas 1377 compatible = "renesas,scif-r8a7796",
1378 "renesas 1378 "renesas,rcar-gen3-scif", "renesas,scif";
1379 reg = <0 0xe6c50000 0 1379 reg = <0 0xe6c50000 0 64>;
1380 interrupts = <GIC_SPI 1380 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1381 clocks = <&cpg CPG_MO 1381 clocks = <&cpg CPG_MOD 204>,
1382 <&cpg CPG_CO 1382 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
1383 <&scif_clk>; 1383 <&scif_clk>;
1384 clock-names = "fck", 1384 clock-names = "fck", "brg_int", "scif_clk";
1385 dmas = <&dmac0 0x57>, 1385 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1386 dma-names = "tx", "rx 1386 dma-names = "tx", "rx";
1387 power-domains = <&sys 1387 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1388 resets = <&cpg 204>; 1388 resets = <&cpg 204>;
1389 status = "disabled"; 1389 status = "disabled";
1390 }; 1390 };
1391 1391
1392 scif4: serial@e6c40000 { 1392 scif4: serial@e6c40000 {
1393 compatible = "renesas 1393 compatible = "renesas,scif-r8a7796",
1394 "renesas 1394 "renesas,rcar-gen3-scif", "renesas,scif";
1395 reg = <0 0xe6c40000 0 1395 reg = <0 0xe6c40000 0 64>;
1396 interrupts = <GIC_SPI 1396 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1397 clocks = <&cpg CPG_MO 1397 clocks = <&cpg CPG_MOD 203>,
1398 <&cpg CPG_CO 1398 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
1399 <&scif_clk>; 1399 <&scif_clk>;
1400 clock-names = "fck", 1400 clock-names = "fck", "brg_int", "scif_clk";
1401 dmas = <&dmac0 0x59>, 1401 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1402 dma-names = "tx", "rx 1402 dma-names = "tx", "rx";
1403 power-domains = <&sys 1403 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1404 resets = <&cpg 203>; 1404 resets = <&cpg 203>;
1405 status = "disabled"; 1405 status = "disabled";
1406 }; 1406 };
1407 1407
1408 scif5: serial@e6f30000 { 1408 scif5: serial@e6f30000 {
1409 compatible = "renesas 1409 compatible = "renesas,scif-r8a7796",
1410 "renesas 1410 "renesas,rcar-gen3-scif", "renesas,scif";
1411 reg = <0 0xe6f30000 0 1411 reg = <0 0xe6f30000 0 64>;
1412 interrupts = <GIC_SPI 1412 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1413 clocks = <&cpg CPG_MO 1413 clocks = <&cpg CPG_MOD 202>,
1414 <&cpg CPG_CO 1414 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
1415 <&scif_clk>; 1415 <&scif_clk>;
1416 clock-names = "fck", 1416 clock-names = "fck", "brg_int", "scif_clk";
1417 dmas = <&dmac1 0x5b>, 1417 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
1418 <&dmac2 0x5b>, 1418 <&dmac2 0x5b>, <&dmac2 0x5a>;
1419 dma-names = "tx", "rx 1419 dma-names = "tx", "rx", "tx", "rx";
1420 power-domains = <&sys 1420 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1421 resets = <&cpg 202>; 1421 resets = <&cpg 202>;
1422 status = "disabled"; 1422 status = "disabled";
1423 }; 1423 };
1424 1424
1425 tpu: pwm@e6e80000 { 1425 tpu: pwm@e6e80000 {
1426 compatible = "renesas 1426 compatible = "renesas,tpu-r8a7796", "renesas,tpu";
1427 reg = <0 0xe6e80000 0 1427 reg = <0 0xe6e80000 0 0x148>;
1428 interrupts = <GIC_SPI 1428 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
1429 clocks = <&cpg CPG_MO 1429 clocks = <&cpg CPG_MOD 304>;
1430 power-domains = <&sys 1430 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1431 resets = <&cpg 304>; 1431 resets = <&cpg 304>;
1432 #pwm-cells = <3>; 1432 #pwm-cells = <3>;
1433 status = "disabled"; 1433 status = "disabled";
1434 }; 1434 };
1435 1435
1436 msiof0: spi@e6e90000 { 1436 msiof0: spi@e6e90000 {
1437 compatible = "renesas 1437 compatible = "renesas,msiof-r8a7796",
1438 "renesas 1438 "renesas,rcar-gen3-msiof";
1439 reg = <0 0xe6e90000 0 1439 reg = <0 0xe6e90000 0 0x0064>;
1440 interrupts = <GIC_SPI 1440 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1441 clocks = <&cpg CPG_MO 1441 clocks = <&cpg CPG_MOD 211>;
1442 dmas = <&dmac1 0x41>, 1442 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1443 <&dmac2 0x41>, 1443 <&dmac2 0x41>, <&dmac2 0x40>;
1444 dma-names = "tx", "rx 1444 dma-names = "tx", "rx", "tx", "rx";
1445 power-domains = <&sys 1445 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1446 resets = <&cpg 211>; 1446 resets = <&cpg 211>;
1447 #address-cells = <1>; 1447 #address-cells = <1>;
1448 #size-cells = <0>; 1448 #size-cells = <0>;
1449 status = "disabled"; 1449 status = "disabled";
1450 }; 1450 };
1451 1451
1452 msiof1: spi@e6ea0000 { 1452 msiof1: spi@e6ea0000 {
1453 compatible = "renesas 1453 compatible = "renesas,msiof-r8a7796",
1454 "renesas 1454 "renesas,rcar-gen3-msiof";
1455 reg = <0 0xe6ea0000 0 1455 reg = <0 0xe6ea0000 0 0x0064>;
1456 interrupts = <GIC_SPI 1456 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1457 clocks = <&cpg CPG_MO 1457 clocks = <&cpg CPG_MOD 210>;
1458 dmas = <&dmac1 0x43>, 1458 dmas = <&dmac1 0x43>, <&dmac1 0x42>,
1459 <&dmac2 0x43>, 1459 <&dmac2 0x43>, <&dmac2 0x42>;
1460 dma-names = "tx", "rx 1460 dma-names = "tx", "rx", "tx", "rx";
1461 power-domains = <&sys 1461 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1462 resets = <&cpg 210>; 1462 resets = <&cpg 210>;
1463 #address-cells = <1>; 1463 #address-cells = <1>;
1464 #size-cells = <0>; 1464 #size-cells = <0>;
1465 status = "disabled"; 1465 status = "disabled";
1466 }; 1466 };
1467 1467
1468 msiof2: spi@e6c00000 { 1468 msiof2: spi@e6c00000 {
1469 compatible = "renesas 1469 compatible = "renesas,msiof-r8a7796",
1470 "renesas 1470 "renesas,rcar-gen3-msiof";
1471 reg = <0 0xe6c00000 0 1471 reg = <0 0xe6c00000 0 0x0064>;
1472 interrupts = <GIC_SPI 1472 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1473 clocks = <&cpg CPG_MO 1473 clocks = <&cpg CPG_MOD 209>;
1474 dmas = <&dmac0 0x45>, 1474 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1475 dma-names = "tx", "rx 1475 dma-names = "tx", "rx";
1476 power-domains = <&sys 1476 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1477 resets = <&cpg 209>; 1477 resets = <&cpg 209>;
1478 #address-cells = <1>; 1478 #address-cells = <1>;
1479 #size-cells = <0>; 1479 #size-cells = <0>;
1480 status = "disabled"; 1480 status = "disabled";
1481 }; 1481 };
1482 1482
1483 msiof3: spi@e6c10000 { 1483 msiof3: spi@e6c10000 {
1484 compatible = "renesas 1484 compatible = "renesas,msiof-r8a7796",
1485 "renesas 1485 "renesas,rcar-gen3-msiof";
1486 reg = <0 0xe6c10000 0 1486 reg = <0 0xe6c10000 0 0x0064>;
1487 interrupts = <GIC_SPI 1487 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1488 clocks = <&cpg CPG_MO 1488 clocks = <&cpg CPG_MOD 208>;
1489 dmas = <&dmac0 0x47>, 1489 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1490 dma-names = "tx", "rx 1490 dma-names = "tx", "rx";
1491 power-domains = <&sys 1491 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1492 resets = <&cpg 208>; 1492 resets = <&cpg 208>;
1493 #address-cells = <1>; 1493 #address-cells = <1>;
1494 #size-cells = <0>; 1494 #size-cells = <0>;
1495 status = "disabled"; 1495 status = "disabled";
1496 }; 1496 };
1497 1497
1498 vin0: video@e6ef0000 { 1498 vin0: video@e6ef0000 {
1499 compatible = "renesas 1499 compatible = "renesas,vin-r8a7796";
1500 reg = <0 0xe6ef0000 0 1500 reg = <0 0xe6ef0000 0 0x1000>;
1501 interrupts = <GIC_SPI 1501 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
1502 clocks = <&cpg CPG_MO 1502 clocks = <&cpg CPG_MOD 811>;
1503 power-domains = <&sys 1503 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1504 resets = <&cpg 811>; 1504 resets = <&cpg 811>;
1505 renesas,id = <0>; 1505 renesas,id = <0>;
1506 status = "disabled"; 1506 status = "disabled";
1507 1507
1508 ports { 1508 ports {
1509 #address-cell 1509 #address-cells = <1>;
1510 #size-cells = 1510 #size-cells = <0>;
1511 1511
1512 port@1 { 1512 port@1 {
1513 #addr 1513 #address-cells = <1>;
1514 #size 1514 #size-cells = <0>;
1515 1515
1516 reg = 1516 reg = <1>;
1517 1517
1518 vin0c 1518 vin0csi20: endpoint@0 {
1519 1519 reg = <0>;
1520 1520 remote-endpoint = <&csi20vin0>;
1521 }; 1521 };
1522 vin0c 1522 vin0csi40: endpoint@2 {
1523 1523 reg = <2>;
1524 1524 remote-endpoint = <&csi40vin0>;
1525 }; 1525 };
1526 }; 1526 };
1527 }; 1527 };
1528 }; 1528 };
1529 1529
1530 vin1: video@e6ef1000 { 1530 vin1: video@e6ef1000 {
1531 compatible = "renesas 1531 compatible = "renesas,vin-r8a7796";
1532 reg = <0 0xe6ef1000 0 1532 reg = <0 0xe6ef1000 0 0x1000>;
1533 interrupts = <GIC_SPI 1533 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
1534 clocks = <&cpg CPG_MO 1534 clocks = <&cpg CPG_MOD 810>;
1535 power-domains = <&sys 1535 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1536 resets = <&cpg 810>; 1536 resets = <&cpg 810>;
1537 renesas,id = <1>; 1537 renesas,id = <1>;
1538 status = "disabled"; 1538 status = "disabled";
1539 1539
1540 ports { 1540 ports {
1541 #address-cell 1541 #address-cells = <1>;
1542 #size-cells = 1542 #size-cells = <0>;
1543 1543
1544 port@1 { 1544 port@1 {
1545 #addr 1545 #address-cells = <1>;
1546 #size 1546 #size-cells = <0>;
1547 1547
1548 reg = 1548 reg = <1>;
1549 1549
1550 vin1c 1550 vin1csi20: endpoint@0 {
1551 1551 reg = <0>;
1552 1552 remote-endpoint = <&csi20vin1>;
1553 }; 1553 };
1554 vin1c 1554 vin1csi40: endpoint@2 {
1555 1555 reg = <2>;
1556 1556 remote-endpoint = <&csi40vin1>;
1557 }; 1557 };
1558 }; 1558 };
1559 }; 1559 };
1560 }; 1560 };
1561 1561
1562 vin2: video@e6ef2000 { 1562 vin2: video@e6ef2000 {
1563 compatible = "renesas 1563 compatible = "renesas,vin-r8a7796";
1564 reg = <0 0xe6ef2000 0 1564 reg = <0 0xe6ef2000 0 0x1000>;
1565 interrupts = <GIC_SPI 1565 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1566 clocks = <&cpg CPG_MO 1566 clocks = <&cpg CPG_MOD 809>;
1567 power-domains = <&sys 1567 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1568 resets = <&cpg 809>; 1568 resets = <&cpg 809>;
1569 renesas,id = <2>; 1569 renesas,id = <2>;
1570 status = "disabled"; 1570 status = "disabled";
1571 1571
1572 ports { 1572 ports {
1573 #address-cell 1573 #address-cells = <1>;
1574 #size-cells = 1574 #size-cells = <0>;
1575 1575
1576 port@1 { 1576 port@1 {
1577 #addr 1577 #address-cells = <1>;
1578 #size 1578 #size-cells = <0>;
1579 1579
1580 reg = 1580 reg = <1>;
1581 1581
1582 vin2c 1582 vin2csi20: endpoint@0 {
1583 1583 reg = <0>;
1584 1584 remote-endpoint = <&csi20vin2>;
1585 }; 1585 };
1586 vin2c 1586 vin2csi40: endpoint@2 {
1587 1587 reg = <2>;
1588 1588 remote-endpoint = <&csi40vin2>;
1589 }; 1589 };
1590 }; 1590 };
1591 }; 1591 };
1592 }; 1592 };
1593 1593
1594 vin3: video@e6ef3000 { 1594 vin3: video@e6ef3000 {
1595 compatible = "renesas 1595 compatible = "renesas,vin-r8a7796";
1596 reg = <0 0xe6ef3000 0 1596 reg = <0 0xe6ef3000 0 0x1000>;
1597 interrupts = <GIC_SPI 1597 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
1598 clocks = <&cpg CPG_MO 1598 clocks = <&cpg CPG_MOD 808>;
1599 power-domains = <&sys 1599 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1600 resets = <&cpg 808>; 1600 resets = <&cpg 808>;
1601 renesas,id = <3>; 1601 renesas,id = <3>;
1602 status = "disabled"; 1602 status = "disabled";
1603 1603
1604 ports { 1604 ports {
1605 #address-cell 1605 #address-cells = <1>;
1606 #size-cells = 1606 #size-cells = <0>;
1607 1607
1608 port@1 { 1608 port@1 {
1609 #addr 1609 #address-cells = <1>;
1610 #size 1610 #size-cells = <0>;
1611 1611
1612 reg = 1612 reg = <1>;
1613 1613
1614 vin3c 1614 vin3csi20: endpoint@0 {
1615 1615 reg = <0>;
1616 1616 remote-endpoint = <&csi20vin3>;
1617 }; 1617 };
1618 vin3c 1618 vin3csi40: endpoint@2 {
1619 1619 reg = <2>;
1620 1620 remote-endpoint = <&csi40vin3>;
1621 }; 1621 };
1622 }; 1622 };
1623 }; 1623 };
1624 }; 1624 };
1625 1625
1626 vin4: video@e6ef4000 { 1626 vin4: video@e6ef4000 {
1627 compatible = "renesas 1627 compatible = "renesas,vin-r8a7796";
1628 reg = <0 0xe6ef4000 0 1628 reg = <0 0xe6ef4000 0 0x1000>;
1629 interrupts = <GIC_SPI 1629 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
1630 clocks = <&cpg CPG_MO 1630 clocks = <&cpg CPG_MOD 807>;
1631 power-domains = <&sys 1631 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1632 resets = <&cpg 807>; 1632 resets = <&cpg 807>;
1633 renesas,id = <4>; 1633 renesas,id = <4>;
1634 status = "disabled"; 1634 status = "disabled";
1635 1635
1636 ports { 1636 ports {
1637 #address-cell 1637 #address-cells = <1>;
1638 #size-cells = 1638 #size-cells = <0>;
1639 1639
1640 port@1 { 1640 port@1 {
1641 #addr 1641 #address-cells = <1>;
1642 #size 1642 #size-cells = <0>;
1643 1643
1644 reg = 1644 reg = <1>;
1645 1645
1646 vin4c 1646 vin4csi20: endpoint@0 {
1647 1647 reg = <0>;
1648 1648 remote-endpoint = <&csi20vin4>;
1649 }; 1649 };
1650 vin4c 1650 vin4csi40: endpoint@2 {
1651 1651 reg = <2>;
1652 1652 remote-endpoint = <&csi40vin4>;
1653 }; 1653 };
1654 }; 1654 };
1655 }; 1655 };
1656 }; 1656 };
1657 1657
1658 vin5: video@e6ef5000 { 1658 vin5: video@e6ef5000 {
1659 compatible = "renesas 1659 compatible = "renesas,vin-r8a7796";
1660 reg = <0 0xe6ef5000 0 1660 reg = <0 0xe6ef5000 0 0x1000>;
1661 interrupts = <GIC_SPI 1661 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
1662 clocks = <&cpg CPG_MO 1662 clocks = <&cpg CPG_MOD 806>;
1663 power-domains = <&sys 1663 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1664 resets = <&cpg 806>; 1664 resets = <&cpg 806>;
1665 renesas,id = <5>; 1665 renesas,id = <5>;
1666 status = "disabled"; 1666 status = "disabled";
1667 1667
1668 ports { 1668 ports {
1669 #address-cell 1669 #address-cells = <1>;
1670 #size-cells = 1670 #size-cells = <0>;
1671 1671
1672 port@1 { 1672 port@1 {
1673 #addr 1673 #address-cells = <1>;
1674 #size 1674 #size-cells = <0>;
1675 1675
1676 reg = 1676 reg = <1>;
1677 1677
1678 vin5c 1678 vin5csi20: endpoint@0 {
1679 1679 reg = <0>;
1680 1680 remote-endpoint = <&csi20vin5>;
1681 }; 1681 };
1682 vin5c 1682 vin5csi40: endpoint@2 {
1683 1683 reg = <2>;
1684 1684 remote-endpoint = <&csi40vin5>;
1685 }; 1685 };
1686 }; 1686 };
1687 }; 1687 };
1688 }; 1688 };
1689 1689
1690 vin6: video@e6ef6000 { 1690 vin6: video@e6ef6000 {
1691 compatible = "renesas 1691 compatible = "renesas,vin-r8a7796";
1692 reg = <0 0xe6ef6000 0 1692 reg = <0 0xe6ef6000 0 0x1000>;
1693 interrupts = <GIC_SPI 1693 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
1694 clocks = <&cpg CPG_MO 1694 clocks = <&cpg CPG_MOD 805>;
1695 power-domains = <&sys 1695 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1696 resets = <&cpg 805>; 1696 resets = <&cpg 805>;
1697 renesas,id = <6>; 1697 renesas,id = <6>;
1698 status = "disabled"; 1698 status = "disabled";
1699 1699
1700 ports { 1700 ports {
1701 #address-cell 1701 #address-cells = <1>;
1702 #size-cells = 1702 #size-cells = <0>;
1703 1703
1704 port@1 { 1704 port@1 {
1705 #addr 1705 #address-cells = <1>;
1706 #size 1706 #size-cells = <0>;
1707 1707
1708 reg = 1708 reg = <1>;
1709 1709
1710 vin6c 1710 vin6csi20: endpoint@0 {
1711 1711 reg = <0>;
1712 1712 remote-endpoint = <&csi20vin6>;
1713 }; 1713 };
1714 vin6c 1714 vin6csi40: endpoint@2 {
1715 1715 reg = <2>;
1716 1716 remote-endpoint = <&csi40vin6>;
1717 }; 1717 };
1718 }; 1718 };
1719 }; 1719 };
1720 }; 1720 };
1721 1721
1722 vin7: video@e6ef7000 { 1722 vin7: video@e6ef7000 {
1723 compatible = "renesas 1723 compatible = "renesas,vin-r8a7796";
1724 reg = <0 0xe6ef7000 0 1724 reg = <0 0xe6ef7000 0 0x1000>;
1725 interrupts = <GIC_SPI 1725 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
1726 clocks = <&cpg CPG_MO 1726 clocks = <&cpg CPG_MOD 804>;
1727 power-domains = <&sys 1727 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1728 resets = <&cpg 804>; 1728 resets = <&cpg 804>;
1729 renesas,id = <7>; 1729 renesas,id = <7>;
1730 status = "disabled"; 1730 status = "disabled";
1731 1731
1732 ports { 1732 ports {
1733 #address-cell 1733 #address-cells = <1>;
1734 #size-cells = 1734 #size-cells = <0>;
1735 1735
1736 port@1 { 1736 port@1 {
1737 #addr 1737 #address-cells = <1>;
1738 #size 1738 #size-cells = <0>;
1739 1739
1740 reg = 1740 reg = <1>;
1741 1741
1742 vin7c 1742 vin7csi20: endpoint@0 {
1743 1743 reg = <0>;
1744 1744 remote-endpoint = <&csi20vin7>;
1745 }; 1745 };
1746 vin7c 1746 vin7csi40: endpoint@2 {
1747 1747 reg = <2>;
1748 1748 remote-endpoint = <&csi40vin7>;
1749 }; 1749 };
1750 }; 1750 };
1751 }; 1751 };
1752 }; 1752 };
1753 1753
1754 drif00: rif@e6f40000 { 1754 drif00: rif@e6f40000 {
1755 compatible = "renesas 1755 compatible = "renesas,r8a7796-drif",
1756 "renesas 1756 "renesas,rcar-gen3-drif";
1757 reg = <0 0xe6f40000 0 1757 reg = <0 0xe6f40000 0 0x64>;
1758 interrupts = <GIC_SPI 1758 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1759 clocks = <&cpg CPG_MO 1759 clocks = <&cpg CPG_MOD 515>;
1760 clock-names = "fck"; 1760 clock-names = "fck";
1761 dmas = <&dmac1 0x20>, 1761 dmas = <&dmac1 0x20>, <&dmac2 0x20>;
1762 dma-names = "rx", "rx 1762 dma-names = "rx", "rx";
1763 power-domains = <&sys 1763 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1764 resets = <&cpg 515>; 1764 resets = <&cpg 515>;
1765 renesas,bonding = <&d 1765 renesas,bonding = <&drif01>;
1766 status = "disabled"; 1766 status = "disabled";
1767 }; 1767 };
1768 1768
1769 drif01: rif@e6f50000 { 1769 drif01: rif@e6f50000 {
1770 compatible = "renesas 1770 compatible = "renesas,r8a7796-drif",
1771 "renesas 1771 "renesas,rcar-gen3-drif";
1772 reg = <0 0xe6f50000 0 1772 reg = <0 0xe6f50000 0 0x64>;
1773 interrupts = <GIC_SPI 1773 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1774 clocks = <&cpg CPG_MO 1774 clocks = <&cpg CPG_MOD 514>;
1775 clock-names = "fck"; 1775 clock-names = "fck";
1776 dmas = <&dmac1 0x22>, 1776 dmas = <&dmac1 0x22>, <&dmac2 0x22>;
1777 dma-names = "rx", "rx 1777 dma-names = "rx", "rx";
1778 power-domains = <&sys 1778 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1779 resets = <&cpg 514>; 1779 resets = <&cpg 514>;
1780 renesas,bonding = <&d 1780 renesas,bonding = <&drif00>;
1781 status = "disabled"; 1781 status = "disabled";
1782 }; 1782 };
1783 1783
1784 drif10: rif@e6f60000 { 1784 drif10: rif@e6f60000 {
1785 compatible = "renesas 1785 compatible = "renesas,r8a7796-drif",
1786 "renesas 1786 "renesas,rcar-gen3-drif";
1787 reg = <0 0xe6f60000 0 1787 reg = <0 0xe6f60000 0 0x64>;
1788 interrupts = <GIC_SPI 1788 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1789 clocks = <&cpg CPG_MO 1789 clocks = <&cpg CPG_MOD 513>;
1790 clock-names = "fck"; 1790 clock-names = "fck";
1791 dmas = <&dmac1 0x24>, 1791 dmas = <&dmac1 0x24>, <&dmac2 0x24>;
1792 dma-names = "rx", "rx 1792 dma-names = "rx", "rx";
1793 power-domains = <&sys 1793 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1794 resets = <&cpg 513>; 1794 resets = <&cpg 513>;
1795 renesas,bonding = <&d 1795 renesas,bonding = <&drif11>;
1796 status = "disabled"; 1796 status = "disabled";
1797 }; 1797 };
1798 1798
1799 drif11: rif@e6f70000 { 1799 drif11: rif@e6f70000 {
1800 compatible = "renesas 1800 compatible = "renesas,r8a7796-drif",
1801 "renesas 1801 "renesas,rcar-gen3-drif";
1802 reg = <0 0xe6f70000 0 1802 reg = <0 0xe6f70000 0 0x64>;
1803 interrupts = <GIC_SPI 1803 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1804 clocks = <&cpg CPG_MO 1804 clocks = <&cpg CPG_MOD 512>;
1805 clock-names = "fck"; 1805 clock-names = "fck";
1806 dmas = <&dmac1 0x26>, 1806 dmas = <&dmac1 0x26>, <&dmac2 0x26>;
1807 dma-names = "rx", "rx 1807 dma-names = "rx", "rx";
1808 power-domains = <&sys 1808 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1809 resets = <&cpg 512>; 1809 resets = <&cpg 512>;
1810 renesas,bonding = <&d 1810 renesas,bonding = <&drif10>;
1811 status = "disabled"; 1811 status = "disabled";
1812 }; 1812 };
1813 1813
1814 drif20: rif@e6f80000 { 1814 drif20: rif@e6f80000 {
1815 compatible = "renesas 1815 compatible = "renesas,r8a7796-drif",
1816 "renesas 1816 "renesas,rcar-gen3-drif";
1817 reg = <0 0xe6f80000 0 1817 reg = <0 0xe6f80000 0 0x64>;
1818 interrupts = <GIC_SPI 1818 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1819 clocks = <&cpg CPG_MO 1819 clocks = <&cpg CPG_MOD 511>;
1820 clock-names = "fck"; 1820 clock-names = "fck";
1821 dmas = <&dmac1 0x28>, 1821 dmas = <&dmac1 0x28>, <&dmac2 0x28>;
1822 dma-names = "rx", "rx 1822 dma-names = "rx", "rx";
1823 power-domains = <&sys 1823 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1824 resets = <&cpg 511>; 1824 resets = <&cpg 511>;
1825 renesas,bonding = <&d 1825 renesas,bonding = <&drif21>;
1826 status = "disabled"; 1826 status = "disabled";
1827 }; 1827 };
1828 1828
1829 drif21: rif@e6f90000 { 1829 drif21: rif@e6f90000 {
1830 compatible = "renesas 1830 compatible = "renesas,r8a7796-drif",
1831 "renesas 1831 "renesas,rcar-gen3-drif";
1832 reg = <0 0xe6f90000 0 1832 reg = <0 0xe6f90000 0 0x64>;
1833 interrupts = <GIC_SPI 1833 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1834 clocks = <&cpg CPG_MO 1834 clocks = <&cpg CPG_MOD 510>;
1835 clock-names = "fck"; 1835 clock-names = "fck";
1836 dmas = <&dmac1 0x2a>, 1836 dmas = <&dmac1 0x2a>, <&dmac2 0x2a>;
1837 dma-names = "rx", "rx 1837 dma-names = "rx", "rx";
1838 power-domains = <&sys 1838 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1839 resets = <&cpg 510>; 1839 resets = <&cpg 510>;
1840 renesas,bonding = <&d 1840 renesas,bonding = <&drif20>;
1841 status = "disabled"; 1841 status = "disabled";
1842 }; 1842 };
1843 1843
1844 drif30: rif@e6fa0000 { 1844 drif30: rif@e6fa0000 {
1845 compatible = "renesas 1845 compatible = "renesas,r8a7796-drif",
1846 "renesas 1846 "renesas,rcar-gen3-drif";
1847 reg = <0 0xe6fa0000 0 1847 reg = <0 0xe6fa0000 0 0x64>;
1848 interrupts = <GIC_SPI 1848 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1849 clocks = <&cpg CPG_MO 1849 clocks = <&cpg CPG_MOD 509>;
1850 clock-names = "fck"; 1850 clock-names = "fck";
1851 dmas = <&dmac1 0x2c>, 1851 dmas = <&dmac1 0x2c>, <&dmac2 0x2c>;
1852 dma-names = "rx", "rx 1852 dma-names = "rx", "rx";
1853 power-domains = <&sys 1853 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1854 resets = <&cpg 509>; 1854 resets = <&cpg 509>;
1855 renesas,bonding = <&d 1855 renesas,bonding = <&drif31>;
1856 status = "disabled"; 1856 status = "disabled";
1857 }; 1857 };
1858 1858
1859 drif31: rif@e6fb0000 { 1859 drif31: rif@e6fb0000 {
1860 compatible = "renesas 1860 compatible = "renesas,r8a7796-drif",
1861 "renesas 1861 "renesas,rcar-gen3-drif";
1862 reg = <0 0xe6fb0000 0 1862 reg = <0 0xe6fb0000 0 0x64>;
1863 interrupts = <GIC_SPI 1863 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1864 clocks = <&cpg CPG_MO 1864 clocks = <&cpg CPG_MOD 508>;
1865 clock-names = "fck"; 1865 clock-names = "fck";
1866 dmas = <&dmac1 0x2e>, 1866 dmas = <&dmac1 0x2e>, <&dmac2 0x2e>;
1867 dma-names = "rx", "rx 1867 dma-names = "rx", "rx";
1868 power-domains = <&sys 1868 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1869 resets = <&cpg 508>; 1869 resets = <&cpg 508>;
1870 renesas,bonding = <&d 1870 renesas,bonding = <&drif30>;
1871 status = "disabled"; 1871 status = "disabled";
1872 }; 1872 };
1873 1873
1874 rcar_sound: sound@ec500000 { 1874 rcar_sound: sound@ec500000 {
1875 /* 1875 /*
1876 * #sound-dai-cells i 1876 * #sound-dai-cells is required if simple-card
1877 * 1877 *
1878 * Single DAI : #soun 1878 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1879 * Multi DAI : #soun 1879 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1880 */ 1880 */
1881 /* 1881 /*
1882 * #clock-cells is re 1882 * #clock-cells is required for audio_clkout0/1/2/3
1883 * 1883 *
1884 * clkout : #cl 1884 * clkout : #clock-cells = <0>; <&rcar_sound>;
1885 * clkout0/1/2/3: #cl 1885 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
1886 */ 1886 */
1887 compatible = "renesas 1887 compatible = "renesas,rcar_sound-r8a7796", "renesas,rcar_sound-gen3";
1888 reg = <0 0xec500000 0 1888 reg = <0 0xec500000 0 0x1000>, /* SCU */
1889 <0 0xec5a0000 0 1889 <0 0xec5a0000 0 0x100>, /* ADG */
1890 <0 0xec540000 0 1890 <0 0xec540000 0 0x1000>, /* SSIU */
1891 <0 0xec541000 0 1891 <0 0xec541000 0 0x280>, /* SSI */
1892 <0 0xec760000 0 1892 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
1893 reg-names = "scu", "a 1893 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1894 1894
1895 clocks = <&cpg CPG_MO 1895 clocks = <&cpg CPG_MOD 1005>,
1896 <&cpg CPG_MO 1896 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
1897 <&cpg CPG_MO 1897 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
1898 <&cpg CPG_MO 1898 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
1899 <&cpg CPG_MO 1899 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
1900 <&cpg CPG_MO 1900 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
1901 <&cpg CPG_MO 1901 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
1902 <&cpg CPG_MO 1902 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
1903 <&cpg CPG_MO 1903 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
1904 <&cpg CPG_MO 1904 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
1905 <&cpg CPG_MO 1905 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
1906 <&cpg CPG_MO 1906 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1907 <&cpg CPG_MO 1907 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1908 <&cpg CPG_MO 1908 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
1909 <&audio_clk_ 1909 <&audio_clk_a>, <&audio_clk_b>,
1910 <&audio_clk_ 1910 <&audio_clk_c>,
1911 <&cpg CPG_MO 1911 <&cpg CPG_MOD 922>;
1912 clock-names = "ssi-al 1912 clock-names = "ssi-all",
1913 "ssi.9" 1913 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1914 "ssi.5" 1914 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1915 "ssi.1" 1915 "ssi.1", "ssi.0",
1916 "src.9" 1916 "src.9", "src.8", "src.7", "src.6",
1917 "src.5" 1917 "src.5", "src.4", "src.3", "src.2",
1918 "src.1" 1918 "src.1", "src.0",
1919 "mix.1" 1919 "mix.1", "mix.0",
1920 "ctu.1" 1920 "ctu.1", "ctu.0",
1921 "dvc.0" 1921 "dvc.0", "dvc.1",
1922 "clk_a" 1922 "clk_a", "clk_b", "clk_c", "clk_i";
1923 power-domains = <&sys 1923 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1924 resets = <&cpg 1005>, 1924 resets = <&cpg 1005>,
1925 <&cpg 1006>, 1925 <&cpg 1006>, <&cpg 1007>,
1926 <&cpg 1008>, 1926 <&cpg 1008>, <&cpg 1009>,
1927 <&cpg 1010>, 1927 <&cpg 1010>, <&cpg 1011>,
1928 <&cpg 1012>, 1928 <&cpg 1012>, <&cpg 1013>,
1929 <&cpg 1014>, 1929 <&cpg 1014>, <&cpg 1015>;
1930 reset-names = "ssi-al 1930 reset-names = "ssi-all",
1931 "ssi.9" 1931 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1932 "ssi.5" 1932 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1933 "ssi.1" 1933 "ssi.1", "ssi.0";
1934 status = "disabled"; 1934 status = "disabled";
1935 1935
1936 rcar_sound,ctu { 1936 rcar_sound,ctu {
1937 ctu00: ctu-0 1937 ctu00: ctu-0 { };
1938 ctu01: ctu-1 1938 ctu01: ctu-1 { };
1939 ctu02: ctu-2 1939 ctu02: ctu-2 { };
1940 ctu03: ctu-3 1940 ctu03: ctu-3 { };
1941 ctu10: ctu-4 1941 ctu10: ctu-4 { };
1942 ctu11: ctu-5 1942 ctu11: ctu-5 { };
1943 ctu12: ctu-6 1943 ctu12: ctu-6 { };
1944 ctu13: ctu-7 1944 ctu13: ctu-7 { };
1945 }; 1945 };
1946 1946
1947 rcar_sound,dvc { 1947 rcar_sound,dvc {
1948 dvc0: dvc-0 { 1948 dvc0: dvc-0 {
1949 dmas 1949 dmas = <&audma1 0xbc>;
1950 dma-n 1950 dma-names = "tx";
1951 }; 1951 };
1952 dvc1: dvc-1 { 1952 dvc1: dvc-1 {
1953 dmas 1953 dmas = <&audma1 0xbe>;
1954 dma-n 1954 dma-names = "tx";
1955 }; 1955 };
1956 }; 1956 };
1957 1957
1958 rcar_sound,mix { 1958 rcar_sound,mix {
1959 mix0: mix-0 { 1959 mix0: mix-0 { };
1960 mix1: mix-1 { 1960 mix1: mix-1 { };
1961 }; 1961 };
1962 1962
1963 rcar_sound,src { 1963 rcar_sound,src {
1964 src0: src-0 { 1964 src0: src-0 {
1965 inter 1965 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1966 dmas 1966 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1967 dma-n 1967 dma-names = "rx", "tx";
1968 }; 1968 };
1969 src1: src-1 { 1969 src1: src-1 {
1970 inter 1970 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1971 dmas 1971 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1972 dma-n 1972 dma-names = "rx", "tx";
1973 }; 1973 };
1974 src2: src-2 { 1974 src2: src-2 {
1975 inter 1975 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1976 dmas 1976 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1977 dma-n 1977 dma-names = "rx", "tx";
1978 }; 1978 };
1979 src3: src-3 { 1979 src3: src-3 {
1980 inter 1980 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1981 dmas 1981 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1982 dma-n 1982 dma-names = "rx", "tx";
1983 }; 1983 };
1984 src4: src-4 { 1984 src4: src-4 {
1985 inter 1985 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1986 dmas 1986 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1987 dma-n 1987 dma-names = "rx", "tx";
1988 }; 1988 };
1989 src5: src-5 { 1989 src5: src-5 {
1990 inter 1990 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1991 dmas 1991 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1992 dma-n 1992 dma-names = "rx", "tx";
1993 }; 1993 };
1994 src6: src-6 { 1994 src6: src-6 {
1995 inter 1995 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1996 dmas 1996 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1997 dma-n 1997 dma-names = "rx", "tx";
1998 }; 1998 };
1999 src7: src-7 { 1999 src7: src-7 {
2000 inter 2000 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
2001 dmas 2001 dmas = <&audma0 0x93>, <&audma1 0xb6>;
2002 dma-n 2002 dma-names = "rx", "tx";
2003 }; 2003 };
2004 src8: src-8 { 2004 src8: src-8 {
2005 inter 2005 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2006 dmas 2006 dmas = <&audma0 0x95>, <&audma1 0xb8>;
2007 dma-n 2007 dma-names = "rx", "tx";
2008 }; 2008 };
2009 src9: src-9 { 2009 src9: src-9 {
2010 inter 2010 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
2011 dmas 2011 dmas = <&audma0 0x97>, <&audma1 0xba>;
2012 dma-n 2012 dma-names = "rx", "tx";
2013 }; 2013 };
2014 }; 2014 };
2015 2015
2016 rcar_sound,ssi { 2016 rcar_sound,ssi {
2017 ssi0: ssi-0 { 2017 ssi0: ssi-0 {
2018 inter 2018 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
2019 dmas 2019 dmas = <&audma0 0x01>, <&audma1 0x02>;
2020 dma-n 2020 dma-names = "rx", "tx";
2021 }; 2021 };
2022 ssi1: ssi-1 { 2022 ssi1: ssi-1 {
2023 inter 2023 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
2024 dmas 2024 dmas = <&audma0 0x03>, <&audma1 0x04>;
2025 dma-n 2025 dma-names = "rx", "tx";
2026 }; 2026 };
2027 ssi2: ssi-2 { 2027 ssi2: ssi-2 {
2028 inter 2028 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
2029 dmas 2029 dmas = <&audma0 0x05>, <&audma1 0x06>;
2030 dma-n 2030 dma-names = "rx", "tx";
2031 }; 2031 };
2032 ssi3: ssi-3 { 2032 ssi3: ssi-3 {
2033 inter 2033 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
2034 dmas 2034 dmas = <&audma0 0x07>, <&audma1 0x08>;
2035 dma-n 2035 dma-names = "rx", "tx";
2036 }; 2036 };
2037 ssi4: ssi-4 { 2037 ssi4: ssi-4 {
2038 inter 2038 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
2039 dmas 2039 dmas = <&audma0 0x09>, <&audma1 0x0a>;
2040 dma-n 2040 dma-names = "rx", "tx";
2041 }; 2041 };
2042 ssi5: ssi-5 { 2042 ssi5: ssi-5 {
2043 inter 2043 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
2044 dmas 2044 dmas = <&audma0 0x0b>, <&audma1 0x0c>;
2045 dma-n 2045 dma-names = "rx", "tx";
2046 }; 2046 };
2047 ssi6: ssi-6 { 2047 ssi6: ssi-6 {
2048 inter 2048 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
2049 dmas 2049 dmas = <&audma0 0x0d>, <&audma1 0x0e>;
2050 dma-n 2050 dma-names = "rx", "tx";
2051 }; 2051 };
2052 ssi7: ssi-7 { 2052 ssi7: ssi-7 {
2053 inter 2053 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
2054 dmas 2054 dmas = <&audma0 0x0f>, <&audma1 0x10>;
2055 dma-n 2055 dma-names = "rx", "tx";
2056 }; 2056 };
2057 ssi8: ssi-8 { 2057 ssi8: ssi-8 {
2058 inter 2058 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
2059 dmas 2059 dmas = <&audma0 0x11>, <&audma1 0x12>;
2060 dma-n 2060 dma-names = "rx", "tx";
2061 }; 2061 };
2062 ssi9: ssi-9 { 2062 ssi9: ssi-9 {
2063 inter 2063 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
2064 dmas 2064 dmas = <&audma0 0x13>, <&audma1 0x14>;
2065 dma-n 2065 dma-names = "rx", "tx";
2066 }; 2066 };
2067 }; 2067 };
2068 2068
2069 rcar_sound,ssiu { 2069 rcar_sound,ssiu {
2070 ssiu00: ssiu- 2070 ssiu00: ssiu-0 {
2071 dmas 2071 dmas = <&audma0 0x15>, <&audma1 0x16>;
2072 dma-n 2072 dma-names = "rx", "tx";
2073 }; 2073 };
2074 ssiu01: ssiu- 2074 ssiu01: ssiu-1 {
2075 dmas 2075 dmas = <&audma0 0x35>, <&audma1 0x36>;
2076 dma-n 2076 dma-names = "rx", "tx";
2077 }; 2077 };
2078 ssiu02: ssiu- 2078 ssiu02: ssiu-2 {
2079 dmas 2079 dmas = <&audma0 0x37>, <&audma1 0x38>;
2080 dma-n 2080 dma-names = "rx", "tx";
2081 }; 2081 };
2082 ssiu03: ssiu- 2082 ssiu03: ssiu-3 {
2083 dmas 2083 dmas = <&audma0 0x47>, <&audma1 0x48>;
2084 dma-n 2084 dma-names = "rx", "tx";
2085 }; 2085 };
2086 ssiu04: ssiu- 2086 ssiu04: ssiu-4 {
2087 dmas 2087 dmas = <&audma0 0x3F>, <&audma1 0x40>;
2088 dma-n 2088 dma-names = "rx", "tx";
2089 }; 2089 };
2090 ssiu05: ssiu- 2090 ssiu05: ssiu-5 {
2091 dmas 2091 dmas = <&audma0 0x43>, <&audma1 0x44>;
2092 dma-n 2092 dma-names = "rx", "tx";
2093 }; 2093 };
2094 ssiu06: ssiu- 2094 ssiu06: ssiu-6 {
2095 dmas 2095 dmas = <&audma0 0x4F>, <&audma1 0x50>;
2096 dma-n 2096 dma-names = "rx", "tx";
2097 }; 2097 };
2098 ssiu07: ssiu- 2098 ssiu07: ssiu-7 {
2099 dmas 2099 dmas = <&audma0 0x53>, <&audma1 0x54>;
2100 dma-n 2100 dma-names = "rx", "tx";
2101 }; 2101 };
2102 ssiu10: ssiu- 2102 ssiu10: ssiu-8 {
2103 dmas 2103 dmas = <&audma0 0x49>, <&audma1 0x4a>;
2104 dma-n 2104 dma-names = "rx", "tx";
2105 }; 2105 };
2106 ssiu11: ssiu- 2106 ssiu11: ssiu-9 {
2107 dmas 2107 dmas = <&audma0 0x4B>, <&audma1 0x4C>;
2108 dma-n 2108 dma-names = "rx", "tx";
2109 }; 2109 };
2110 ssiu12: ssiu- 2110 ssiu12: ssiu-10 {
2111 dmas 2111 dmas = <&audma0 0x57>, <&audma1 0x58>;
2112 dma-n 2112 dma-names = "rx", "tx";
2113 }; 2113 };
2114 ssiu13: ssiu- 2114 ssiu13: ssiu-11 {
2115 dmas 2115 dmas = <&audma0 0x59>, <&audma1 0x5A>;
2116 dma-n 2116 dma-names = "rx", "tx";
2117 }; 2117 };
2118 ssiu14: ssiu- 2118 ssiu14: ssiu-12 {
2119 dmas 2119 dmas = <&audma0 0x5F>, <&audma1 0x60>;
2120 dma-n 2120 dma-names = "rx", "tx";
2121 }; 2121 };
2122 ssiu15: ssiu- 2122 ssiu15: ssiu-13 {
2123 dmas 2123 dmas = <&audma0 0xC3>, <&audma1 0xC4>;
2124 dma-n 2124 dma-names = "rx", "tx";
2125 }; 2125 };
2126 ssiu16: ssiu- 2126 ssiu16: ssiu-14 {
2127 dmas 2127 dmas = <&audma0 0xC7>, <&audma1 0xC8>;
2128 dma-n 2128 dma-names = "rx", "tx";
2129 }; 2129 };
2130 ssiu17: ssiu- 2130 ssiu17: ssiu-15 {
2131 dmas 2131 dmas = <&audma0 0xCB>, <&audma1 0xCC>;
2132 dma-n 2132 dma-names = "rx", "tx";
2133 }; 2133 };
2134 ssiu20: ssiu- 2134 ssiu20: ssiu-16 {
2135 dmas 2135 dmas = <&audma0 0x63>, <&audma1 0x64>;
2136 dma-n 2136 dma-names = "rx", "tx";
2137 }; 2137 };
2138 ssiu21: ssiu- 2138 ssiu21: ssiu-17 {
2139 dmas 2139 dmas = <&audma0 0x67>, <&audma1 0x68>;
2140 dma-n 2140 dma-names = "rx", "tx";
2141 }; 2141 };
2142 ssiu22: ssiu- 2142 ssiu22: ssiu-18 {
2143 dmas 2143 dmas = <&audma0 0x6B>, <&audma1 0x6C>;
2144 dma-n 2144 dma-names = "rx", "tx";
2145 }; 2145 };
2146 ssiu23: ssiu- 2146 ssiu23: ssiu-19 {
2147 dmas 2147 dmas = <&audma0 0x6D>, <&audma1 0x6E>;
2148 dma-n 2148 dma-names = "rx", "tx";
2149 }; 2149 };
2150 ssiu24: ssiu- 2150 ssiu24: ssiu-20 {
2151 dmas 2151 dmas = <&audma0 0xCF>, <&audma1 0xCE>;
2152 dma-n 2152 dma-names = "rx", "tx";
2153 }; 2153 };
2154 ssiu25: ssiu- 2154 ssiu25: ssiu-21 {
2155 dmas 2155 dmas = <&audma0 0xEB>, <&audma1 0xEC>;
2156 dma-n 2156 dma-names = "rx", "tx";
2157 }; 2157 };
2158 ssiu26: ssiu- 2158 ssiu26: ssiu-22 {
2159 dmas 2159 dmas = <&audma0 0xED>, <&audma1 0xEE>;
2160 dma-n 2160 dma-names = "rx", "tx";
2161 }; 2161 };
2162 ssiu27: ssiu- 2162 ssiu27: ssiu-23 {
2163 dmas 2163 dmas = <&audma0 0xEF>, <&audma1 0xF0>;
2164 dma-n 2164 dma-names = "rx", "tx";
2165 }; 2165 };
2166 ssiu30: ssiu- 2166 ssiu30: ssiu-24 {
2167 dmas 2167 dmas = <&audma0 0x6f>, <&audma1 0x70>;
2168 dma-n 2168 dma-names = "rx", "tx";
2169 }; 2169 };
2170 ssiu31: ssiu- 2170 ssiu31: ssiu-25 {
2171 dmas 2171 dmas = <&audma0 0x21>, <&audma1 0x22>;
2172 dma-n 2172 dma-names = "rx", "tx";
2173 }; 2173 };
2174 ssiu32: ssiu- 2174 ssiu32: ssiu-26 {
2175 dmas 2175 dmas = <&audma0 0x23>, <&audma1 0x24>;
2176 dma-n 2176 dma-names = "rx", "tx";
2177 }; 2177 };
2178 ssiu33: ssiu- 2178 ssiu33: ssiu-27 {
2179 dmas 2179 dmas = <&audma0 0x25>, <&audma1 0x26>;
2180 dma-n 2180 dma-names = "rx", "tx";
2181 }; 2181 };
2182 ssiu34: ssiu- 2182 ssiu34: ssiu-28 {
2183 dmas 2183 dmas = <&audma0 0x27>, <&audma1 0x28>;
2184 dma-n 2184 dma-names = "rx", "tx";
2185 }; 2185 };
2186 ssiu35: ssiu- 2186 ssiu35: ssiu-29 {
2187 dmas 2187 dmas = <&audma0 0x29>, <&audma1 0x2A>;
2188 dma-n 2188 dma-names = "rx", "tx";
2189 }; 2189 };
2190 ssiu36: ssiu- 2190 ssiu36: ssiu-30 {
2191 dmas 2191 dmas = <&audma0 0x2B>, <&audma1 0x2C>;
2192 dma-n 2192 dma-names = "rx", "tx";
2193 }; 2193 };
2194 ssiu37: ssiu- 2194 ssiu37: ssiu-31 {
2195 dmas 2195 dmas = <&audma0 0x2D>, <&audma1 0x2E>;
2196 dma-n 2196 dma-names = "rx", "tx";
2197 }; 2197 };
2198 ssiu40: ssiu- 2198 ssiu40: ssiu-32 {
2199 dmas 2199 dmas = <&audma0 0x71>, <&audma1 0x72>;
2200 dma-n 2200 dma-names = "rx", "tx";
2201 }; 2201 };
2202 ssiu41: ssiu- 2202 ssiu41: ssiu-33 {
2203 dmas 2203 dmas = <&audma0 0x17>, <&audma1 0x18>;
2204 dma-n 2204 dma-names = "rx", "tx";
2205 }; 2205 };
2206 ssiu42: ssiu- 2206 ssiu42: ssiu-34 {
2207 dmas 2207 dmas = <&audma0 0x19>, <&audma1 0x1A>;
2208 dma-n 2208 dma-names = "rx", "tx";
2209 }; 2209 };
2210 ssiu43: ssiu- 2210 ssiu43: ssiu-35 {
2211 dmas 2211 dmas = <&audma0 0x1B>, <&audma1 0x1C>;
2212 dma-n 2212 dma-names = "rx", "tx";
2213 }; 2213 };
2214 ssiu44: ssiu- 2214 ssiu44: ssiu-36 {
2215 dmas 2215 dmas = <&audma0 0x1D>, <&audma1 0x1E>;
2216 dma-n 2216 dma-names = "rx", "tx";
2217 }; 2217 };
2218 ssiu45: ssiu- 2218 ssiu45: ssiu-37 {
2219 dmas 2219 dmas = <&audma0 0x1F>, <&audma1 0x20>;
2220 dma-n 2220 dma-names = "rx", "tx";
2221 }; 2221 };
2222 ssiu46: ssiu- 2222 ssiu46: ssiu-38 {
2223 dmas 2223 dmas = <&audma0 0x31>, <&audma1 0x32>;
2224 dma-n 2224 dma-names = "rx", "tx";
2225 }; 2225 };
2226 ssiu47: ssiu- 2226 ssiu47: ssiu-39 {
2227 dmas 2227 dmas = <&audma0 0x33>, <&audma1 0x34>;
2228 dma-n 2228 dma-names = "rx", "tx";
2229 }; 2229 };
2230 ssiu50: ssiu- 2230 ssiu50: ssiu-40 {
2231 dmas 2231 dmas = <&audma0 0x73>, <&audma1 0x74>;
2232 dma-n 2232 dma-names = "rx", "tx";
2233 }; 2233 };
2234 ssiu60: ssiu- 2234 ssiu60: ssiu-41 {
2235 dmas 2235 dmas = <&audma0 0x75>, <&audma1 0x76>;
2236 dma-n 2236 dma-names = "rx", "tx";
2237 }; 2237 };
2238 ssiu70: ssiu- 2238 ssiu70: ssiu-42 {
2239 dmas 2239 dmas = <&audma0 0x79>, <&audma1 0x7a>;
2240 dma-n 2240 dma-names = "rx", "tx";
2241 }; 2241 };
2242 ssiu80: ssiu- 2242 ssiu80: ssiu-43 {
2243 dmas 2243 dmas = <&audma0 0x7b>, <&audma1 0x7c>;
2244 dma-n 2244 dma-names = "rx", "tx";
2245 }; 2245 };
2246 ssiu90: ssiu- 2246 ssiu90: ssiu-44 {
2247 dmas 2247 dmas = <&audma0 0x7d>, <&audma1 0x7e>;
2248 dma-n 2248 dma-names = "rx", "tx";
2249 }; 2249 };
2250 ssiu91: ssiu- 2250 ssiu91: ssiu-45 {
2251 dmas 2251 dmas = <&audma0 0x7F>, <&audma1 0x80>;
2252 dma-n 2252 dma-names = "rx", "tx";
2253 }; 2253 };
2254 ssiu92: ssiu- 2254 ssiu92: ssiu-46 {
2255 dmas 2255 dmas = <&audma0 0x81>, <&audma1 0x82>;
2256 dma-n 2256 dma-names = "rx", "tx";
2257 }; 2257 };
2258 ssiu93: ssiu- 2258 ssiu93: ssiu-47 {
2259 dmas 2259 dmas = <&audma0 0x83>, <&audma1 0x84>;
2260 dma-n 2260 dma-names = "rx", "tx";
2261 }; 2261 };
2262 ssiu94: ssiu- 2262 ssiu94: ssiu-48 {
2263 dmas 2263 dmas = <&audma0 0xA3>, <&audma1 0xA4>;
2264 dma-n 2264 dma-names = "rx", "tx";
2265 }; 2265 };
2266 ssiu95: ssiu- 2266 ssiu95: ssiu-49 {
2267 dmas 2267 dmas = <&audma0 0xA5>, <&audma1 0xA6>;
2268 dma-n 2268 dma-names = "rx", "tx";
2269 }; 2269 };
2270 ssiu96: ssiu- 2270 ssiu96: ssiu-50 {
2271 dmas 2271 dmas = <&audma0 0xA7>, <&audma1 0xA8>;
2272 dma-n 2272 dma-names = "rx", "tx";
2273 }; 2273 };
2274 ssiu97: ssiu- 2274 ssiu97: ssiu-51 {
2275 dmas 2275 dmas = <&audma0 0xA9>, <&audma1 0xAA>;
2276 dma-n 2276 dma-names = "rx", "tx";
2277 }; 2277 };
2278 }; 2278 };
2279 }; 2279 };
2280 2280
2281 mlp: mlp@ec520000 { 2281 mlp: mlp@ec520000 {
2282 compatible = "renesas 2282 compatible = "renesas,r8a7796-mlp",
2283 "renesas 2283 "renesas,rcar-gen3-mlp";
2284 reg = <0 0xec520000 0 2284 reg = <0 0xec520000 0 0x800>;
2285 interrupts = <GIC_SPI 2285 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
2286 <GIC_SPI 385 2286 <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>;
2287 clocks = <&cpg CPG_MO 2287 clocks = <&cpg CPG_MOD 802>;
2288 power-domains = <&sys 2288 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2289 resets = <&cpg 802>; 2289 resets = <&cpg 802>;
2290 status = "disabled"; 2290 status = "disabled";
2291 }; 2291 };
2292 2292
2293 audma0: dma-controller@ec7000 2293 audma0: dma-controller@ec700000 {
2294 compatible = "renesas 2294 compatible = "renesas,dmac-r8a7796",
2295 "renesas 2295 "renesas,rcar-dmac";
2296 reg = <0 0xec700000 0 2296 reg = <0 0xec700000 0 0x10000>;
2297 interrupts = <GIC_SPI 2297 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
2298 <GIC_SPI 2298 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
2299 <GIC_SPI 2299 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
2300 <GIC_SPI 2300 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
2301 <GIC_SPI 2301 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
2302 <GIC_SPI 2302 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
2303 <GIC_SPI 2303 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
2304 <GIC_SPI 2304 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
2305 <GIC_SPI 2305 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
2306 <GIC_SPI 2306 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
2307 <GIC_SPI 2307 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
2308 <GIC_SPI 2308 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
2309 <GIC_SPI 2309 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
2310 <GIC_SPI 2310 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
2311 <GIC_SPI 2311 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
2312 <GIC_SPI 2312 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
2313 <GIC_SPI 2313 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
2314 interrupt-names = "er 2314 interrupt-names = "error",
2315 "ch0" 2315 "ch0", "ch1", "ch2", "ch3",
2316 "ch4" 2316 "ch4", "ch5", "ch6", "ch7",
2317 "ch8" 2317 "ch8", "ch9", "ch10", "ch11",
2318 "ch12 2318 "ch12", "ch13", "ch14", "ch15";
2319 clocks = <&cpg CPG_MO 2319 clocks = <&cpg CPG_MOD 502>;
2320 clock-names = "fck"; 2320 clock-names = "fck";
2321 power-domains = <&sys 2321 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2322 resets = <&cpg 502>; 2322 resets = <&cpg 502>;
2323 #dma-cells = <1>; 2323 #dma-cells = <1>;
2324 dma-channels = <16>; 2324 dma-channels = <16>;
2325 iommus = <&ipmmu_mp 0 2325 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
2326 <&ipmmu_mp 2>, 2326 <&ipmmu_mp 2>, <&ipmmu_mp 3>,
2327 <&ipmmu_mp 4>, 2327 <&ipmmu_mp 4>, <&ipmmu_mp 5>,
2328 <&ipmmu_mp 6>, 2328 <&ipmmu_mp 6>, <&ipmmu_mp 7>,
2329 <&ipmmu_mp 8>, 2329 <&ipmmu_mp 8>, <&ipmmu_mp 9>,
2330 <&ipmmu_mp 10> 2330 <&ipmmu_mp 10>, <&ipmmu_mp 11>,
2331 <&ipmmu_mp 12> 2331 <&ipmmu_mp 12>, <&ipmmu_mp 13>,
2332 <&ipmmu_mp 14> 2332 <&ipmmu_mp 14>, <&ipmmu_mp 15>;
2333 }; 2333 };
2334 2334
2335 audma1: dma-controller@ec7200 2335 audma1: dma-controller@ec720000 {
2336 compatible = "renesas 2336 compatible = "renesas,dmac-r8a7796",
2337 "renesas 2337 "renesas,rcar-dmac";
2338 reg = <0 0xec720000 0 2338 reg = <0 0xec720000 0 0x10000>;
2339 interrupts = <GIC_SPI 2339 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
2340 <GIC_SPI 2340 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
2341 <GIC_SPI 2341 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
2342 <GIC_SPI 2342 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
2343 <GIC_SPI 2343 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
2344 <GIC_SPI 2344 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
2345 <GIC_SPI 2345 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
2346 <GIC_SPI 2346 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
2347 <GIC_SPI 2347 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
2348 <GIC_SPI 2348 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
2349 <GIC_SPI 2349 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
2350 <GIC_SPI 2350 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
2351 <GIC_SPI 2351 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
2352 <GIC_SPI 2352 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
2353 <GIC_SPI 2353 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
2354 <GIC_SPI 2354 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
2355 <GIC_SPI 2355 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
2356 interrupt-names = "er 2356 interrupt-names = "error",
2357 "ch0" 2357 "ch0", "ch1", "ch2", "ch3",
2358 "ch4" 2358 "ch4", "ch5", "ch6", "ch7",
2359 "ch8" 2359 "ch8", "ch9", "ch10", "ch11",
2360 "ch12 2360 "ch12", "ch13", "ch14", "ch15";
2361 clocks = <&cpg CPG_MO 2361 clocks = <&cpg CPG_MOD 501>;
2362 clock-names = "fck"; 2362 clock-names = "fck";
2363 power-domains = <&sys 2363 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2364 resets = <&cpg 501>; 2364 resets = <&cpg 501>;
2365 #dma-cells = <1>; 2365 #dma-cells = <1>;
2366 dma-channels = <16>; 2366 dma-channels = <16>;
2367 iommus = <&ipmmu_mp 1 2367 iommus = <&ipmmu_mp 16>, <&ipmmu_mp 17>,
2368 <&ipmmu_mp 18> 2368 <&ipmmu_mp 18>, <&ipmmu_mp 19>,
2369 <&ipmmu_mp 20> 2369 <&ipmmu_mp 20>, <&ipmmu_mp 21>,
2370 <&ipmmu_mp 22> 2370 <&ipmmu_mp 22>, <&ipmmu_mp 23>,
2371 <&ipmmu_mp 24> 2371 <&ipmmu_mp 24>, <&ipmmu_mp 25>,
2372 <&ipmmu_mp 26> 2372 <&ipmmu_mp 26>, <&ipmmu_mp 27>,
2373 <&ipmmu_mp 28> 2373 <&ipmmu_mp 28>, <&ipmmu_mp 29>,
2374 <&ipmmu_mp 30> 2374 <&ipmmu_mp 30>, <&ipmmu_mp 31>;
2375 }; 2375 };
2376 2376
2377 xhci0: usb@ee000000 { 2377 xhci0: usb@ee000000 {
2378 compatible = "renesas 2378 compatible = "renesas,xhci-r8a7796",
2379 "renesas 2379 "renesas,rcar-gen3-xhci";
2380 reg = <0 0xee000000 0 2380 reg = <0 0xee000000 0 0xc00>;
2381 interrupts = <GIC_SPI 2381 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
2382 clocks = <&cpg CPG_MO 2382 clocks = <&cpg CPG_MOD 328>;
2383 power-domains = <&sys 2383 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2384 resets = <&cpg 328>; 2384 resets = <&cpg 328>;
2385 status = "disabled"; 2385 status = "disabled";
2386 }; 2386 };
2387 2387
2388 usb3_peri0: usb@ee020000 { 2388 usb3_peri0: usb@ee020000 {
2389 compatible = "renesas 2389 compatible = "renesas,r8a7796-usb3-peri",
2390 "renesas 2390 "renesas,rcar-gen3-usb3-peri";
2391 reg = <0 0xee020000 0 2391 reg = <0 0xee020000 0 0x400>;
2392 interrupts = <GIC_SPI 2392 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
2393 clocks = <&cpg CPG_MO 2393 clocks = <&cpg CPG_MOD 328>;
2394 power-domains = <&sys 2394 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2395 resets = <&cpg 328>; 2395 resets = <&cpg 328>;
2396 status = "disabled"; 2396 status = "disabled";
2397 }; 2397 };
2398 2398
2399 ohci0: usb@ee080000 { 2399 ohci0: usb@ee080000 {
2400 compatible = "generic 2400 compatible = "generic-ohci";
2401 reg = <0 0xee080000 0 2401 reg = <0 0xee080000 0 0x100>;
2402 interrupts = <GIC_SPI 2402 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
2403 clocks = <&cpg CPG_MO 2403 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
2404 phys = <&usb2_phy0 1> 2404 phys = <&usb2_phy0 1>;
2405 phy-names = "usb"; 2405 phy-names = "usb";
2406 power-domains = <&sys 2406 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2407 resets = <&cpg 703>, 2407 resets = <&cpg 703>, <&cpg 704>;
2408 status = "disabled"; 2408 status = "disabled";
2409 }; 2409 };
2410 2410
2411 ohci1: usb@ee0a0000 { 2411 ohci1: usb@ee0a0000 {
2412 compatible = "generic 2412 compatible = "generic-ohci";
2413 reg = <0 0xee0a0000 0 2413 reg = <0 0xee0a0000 0 0x100>;
2414 interrupts = <GIC_SPI 2414 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
2415 clocks = <&cpg CPG_MO 2415 clocks = <&cpg CPG_MOD 702>;
2416 phys = <&usb2_phy1 1> 2416 phys = <&usb2_phy1 1>;
2417 phy-names = "usb"; 2417 phy-names = "usb";
2418 power-domains = <&sys 2418 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2419 resets = <&cpg 702>; 2419 resets = <&cpg 702>;
2420 status = "disabled"; 2420 status = "disabled";
2421 }; 2421 };
2422 2422
2423 ehci0: usb@ee080100 { 2423 ehci0: usb@ee080100 {
2424 compatible = "generic 2424 compatible = "generic-ehci";
2425 reg = <0 0xee080100 0 2425 reg = <0 0xee080100 0 0x100>;
2426 interrupts = <GIC_SPI 2426 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
2427 clocks = <&cpg CPG_MO 2427 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
2428 phys = <&usb2_phy0 2> 2428 phys = <&usb2_phy0 2>;
2429 phy-names = "usb"; 2429 phy-names = "usb";
2430 companion = <&ohci0>; 2430 companion = <&ohci0>;
2431 power-domains = <&sys 2431 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2432 resets = <&cpg 703>, 2432 resets = <&cpg 703>, <&cpg 704>;
2433 status = "disabled"; 2433 status = "disabled";
2434 }; 2434 };
2435 2435
2436 ehci1: usb@ee0a0100 { 2436 ehci1: usb@ee0a0100 {
2437 compatible = "generic 2437 compatible = "generic-ehci";
2438 reg = <0 0xee0a0100 0 2438 reg = <0 0xee0a0100 0 0x100>;
2439 interrupts = <GIC_SPI 2439 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
2440 clocks = <&cpg CPG_MO 2440 clocks = <&cpg CPG_MOD 702>;
2441 phys = <&usb2_phy1 2> 2441 phys = <&usb2_phy1 2>;
2442 phy-names = "usb"; 2442 phy-names = "usb";
2443 companion = <&ohci1>; 2443 companion = <&ohci1>;
2444 power-domains = <&sys 2444 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2445 resets = <&cpg 702>; 2445 resets = <&cpg 702>;
2446 status = "disabled"; 2446 status = "disabled";
2447 }; 2447 };
2448 2448
2449 usb2_phy0: usb-phy@ee080200 { 2449 usb2_phy0: usb-phy@ee080200 {
2450 compatible = "renesas 2450 compatible = "renesas,usb2-phy-r8a7796",
2451 "renesas 2451 "renesas,rcar-gen3-usb2-phy";
2452 reg = <0 0xee080200 0 2452 reg = <0 0xee080200 0 0x700>;
2453 interrupts = <GIC_SPI 2453 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
2454 clocks = <&cpg CPG_MO 2454 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
2455 power-domains = <&sys 2455 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2456 resets = <&cpg 703>, 2456 resets = <&cpg 703>, <&cpg 704>;
2457 #phy-cells = <1>; 2457 #phy-cells = <1>;
2458 status = "disabled"; 2458 status = "disabled";
2459 }; 2459 };
2460 2460
2461 usb2_phy1: usb-phy@ee0a0200 { 2461 usb2_phy1: usb-phy@ee0a0200 {
2462 compatible = "renesas 2462 compatible = "renesas,usb2-phy-r8a7796",
2463 "renesas 2463 "renesas,rcar-gen3-usb2-phy";
2464 reg = <0 0xee0a0200 0 2464 reg = <0 0xee0a0200 0 0x700>;
2465 clocks = <&cpg CPG_MO 2465 clocks = <&cpg CPG_MOD 702>;
2466 power-domains = <&sys 2466 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2467 resets = <&cpg 702>; 2467 resets = <&cpg 702>;
2468 #phy-cells = <1>; 2468 #phy-cells = <1>;
2469 status = "disabled"; 2469 status = "disabled";
2470 }; 2470 };
2471 2471
2472 sdhi0: mmc@ee100000 { 2472 sdhi0: mmc@ee100000 {
2473 compatible = "renesas 2473 compatible = "renesas,sdhi-r8a7796",
2474 "renesas 2474 "renesas,rcar-gen3-sdhi";
2475 reg = <0 0xee100000 0 2475 reg = <0 0xee100000 0 0x2000>;
2476 interrupts = <GIC_SPI 2476 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
2477 clocks = <&cpg CPG_MO 2477 clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A7796_CLK_SD0H>;
2478 clock-names = "core", 2478 clock-names = "core", "clkh";
2479 max-frequency = <2000 2479 max-frequency = <200000000>;
2480 power-domains = <&sys 2480 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2481 resets = <&cpg 314>; 2481 resets = <&cpg 314>;
2482 iommus = <&ipmmu_ds1 2482 iommus = <&ipmmu_ds1 32>;
2483 status = "disabled"; 2483 status = "disabled";
2484 }; 2484 };
2485 2485
2486 sdhi1: mmc@ee120000 { 2486 sdhi1: mmc@ee120000 {
2487 compatible = "renesas 2487 compatible = "renesas,sdhi-r8a7796",
2488 "renesas 2488 "renesas,rcar-gen3-sdhi";
2489 reg = <0 0xee120000 0 2489 reg = <0 0xee120000 0 0x2000>;
2490 interrupts = <GIC_SPI 2490 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
2491 clocks = <&cpg CPG_MO 2491 clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A7796_CLK_SD1H>;
2492 clock-names = "core", 2492 clock-names = "core", "clkh";
2493 max-frequency = <2000 2493 max-frequency = <200000000>;
2494 power-domains = <&sys 2494 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2495 resets = <&cpg 313>; 2495 resets = <&cpg 313>;
2496 iommus = <&ipmmu_ds1 2496 iommus = <&ipmmu_ds1 33>;
2497 status = "disabled"; 2497 status = "disabled";
2498 }; 2498 };
2499 2499
2500 sdhi2: mmc@ee140000 { 2500 sdhi2: mmc@ee140000 {
2501 compatible = "renesas 2501 compatible = "renesas,sdhi-r8a7796",
2502 "renesas 2502 "renesas,rcar-gen3-sdhi";
2503 reg = <0 0xee140000 0 2503 reg = <0 0xee140000 0 0x2000>;
2504 interrupts = <GIC_SPI 2504 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
2505 clocks = <&cpg CPG_MO 2505 clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A7796_CLK_SD2H>;
2506 clock-names = "core", 2506 clock-names = "core", "clkh";
2507 max-frequency = <2000 2507 max-frequency = <200000000>;
2508 power-domains = <&sys 2508 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2509 resets = <&cpg 312>; 2509 resets = <&cpg 312>;
2510 iommus = <&ipmmu_ds1 2510 iommus = <&ipmmu_ds1 34>;
2511 status = "disabled"; 2511 status = "disabled";
2512 }; 2512 };
2513 2513
2514 sdhi3: mmc@ee160000 { 2514 sdhi3: mmc@ee160000 {
2515 compatible = "renesas 2515 compatible = "renesas,sdhi-r8a7796",
2516 "renesas 2516 "renesas,rcar-gen3-sdhi";
2517 reg = <0 0xee160000 0 2517 reg = <0 0xee160000 0 0x2000>;
2518 interrupts = <GIC_SPI 2518 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
2519 clocks = <&cpg CPG_MO 2519 clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A7796_CLK_SD3H>;
2520 clock-names = "core", 2520 clock-names = "core", "clkh";
2521 max-frequency = <2000 2521 max-frequency = <200000000>;
2522 power-domains = <&sys 2522 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2523 resets = <&cpg 311>; 2523 resets = <&cpg 311>;
2524 iommus = <&ipmmu_ds1 2524 iommus = <&ipmmu_ds1 35>;
2525 status = "disabled"; 2525 status = "disabled";
2526 }; 2526 };
2527 2527
2528 rpc: spi@ee200000 { 2528 rpc: spi@ee200000 {
2529 compatible = "renesas 2529 compatible = "renesas,r8a7796-rpc-if",
2530 "renesas 2530 "renesas,rcar-gen3-rpc-if";
2531 reg = <0 0xee200000 0 2531 reg = <0 0xee200000 0 0x200>,
2532 <0 0x08000000 0 2532 <0 0x08000000 0 0x04000000>,
2533 <0 0xee208000 0 2533 <0 0xee208000 0 0x100>;
2534 reg-names = "regs", " 2534 reg-names = "regs", "dirmap", "wbuf";
2535 interrupts = <GIC_SPI 2535 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
2536 clocks = <&cpg CPG_MO 2536 clocks = <&cpg CPG_MOD 917>;
2537 power-domains = <&sys 2537 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2538 resets = <&cpg 917>; 2538 resets = <&cpg 917>;
2539 #address-cells = <1>; 2539 #address-cells = <1>;
2540 #size-cells = <0>; 2540 #size-cells = <0>;
2541 status = "disabled"; 2541 status = "disabled";
2542 }; 2542 };
2543 2543
2544 gic: interrupt-controller@f10 2544 gic: interrupt-controller@f1010000 {
2545 compatible = "arm,gic 2545 compatible = "arm,gic-400";
2546 #interrupt-cells = <3 2546 #interrupt-cells = <3>;
2547 #address-cells = <0>; 2547 #address-cells = <0>;
2548 interrupt-controller; 2548 interrupt-controller;
2549 reg = <0x0 0xf1010000 2549 reg = <0x0 0xf1010000 0 0x1000>,
2550 <0x0 0xf1020000 2550 <0x0 0xf1020000 0 0x20000>,
2551 <0x0 0xf1040000 2551 <0x0 0xf1040000 0 0x20000>,
2552 <0x0 0xf1060000 2552 <0x0 0xf1060000 0 0x20000>;
2553 interrupts = <GIC_PPI 2553 interrupts = <GIC_PPI 9
2554 (GIC_ 2554 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
2555 clocks = <&cpg CPG_MO 2555 clocks = <&cpg CPG_MOD 408>;
2556 clock-names = "clk"; 2556 clock-names = "clk";
2557 power-domains = <&sys 2557 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2558 resets = <&cpg 408>; 2558 resets = <&cpg 408>;
2559 }; 2559 };
2560 2560
2561 pciec0: pcie@fe000000 { 2561 pciec0: pcie@fe000000 {
2562 compatible = "renesas 2562 compatible = "renesas,pcie-r8a7796",
2563 "renesas 2563 "renesas,pcie-rcar-gen3";
2564 reg = <0 0xfe000000 0 2564 reg = <0 0xfe000000 0 0x80000>;
2565 #address-cells = <3>; 2565 #address-cells = <3>;
2566 #size-cells = <2>; 2566 #size-cells = <2>;
2567 bus-range = <0x00 0xf 2567 bus-range = <0x00 0xff>;
2568 device_type = "pci"; 2568 device_type = "pci";
2569 ranges = <0x01000000 2569 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
2570 <0x02000000 2570 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
2571 <0x02000000 2571 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
2572 <0x42000000 2572 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
2573 /* Map all possible D 2573 /* Map all possible DDR/IOMMU as inbound ranges */
2574 dma-ranges = <0x42000 2574 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
2575 interrupts = <GIC_SPI 2575 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
2576 <GIC_SPI 117 2576 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
2577 <GIC_SPI 118 2577 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
2578 #interrupt-cells = <1 2578 #interrupt-cells = <1>;
2579 interrupt-map-mask = 2579 interrupt-map-mask = <0 0 0 0>;
2580 interrupt-map = <0 0 2580 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
2581 clocks = <&cpg CPG_MO 2581 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
2582 clock-names = "pcie", 2582 clock-names = "pcie", "pcie_bus";
2583 power-domains = <&sys 2583 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2584 resets = <&cpg 319>; 2584 resets = <&cpg 319>;
2585 iommu-map = <0 &ipmmu 2585 iommu-map = <0 &ipmmu_hc 0 1>;
2586 iommu-map-mask = <0>; 2586 iommu-map-mask = <0>;
2587 status = "disabled"; 2587 status = "disabled";
2588 }; 2588 };
2589 2589
2590 pciec1: pcie@ee800000 { 2590 pciec1: pcie@ee800000 {
2591 compatible = "renesas 2591 compatible = "renesas,pcie-r8a7796",
2592 "renesas 2592 "renesas,pcie-rcar-gen3";
2593 reg = <0 0xee800000 0 2593 reg = <0 0xee800000 0 0x80000>;
2594 #address-cells = <3>; 2594 #address-cells = <3>;
2595 #size-cells = <2>; 2595 #size-cells = <2>;
2596 bus-range = <0x00 0xf 2596 bus-range = <0x00 0xff>;
2597 device_type = "pci"; 2597 device_type = "pci";
2598 ranges = <0x01000000 2598 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
2599 <0x02000000 2599 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
2600 <0x02000000 2600 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
2601 <0x42000000 2601 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
2602 /* Map all possible D 2602 /* Map all possible DDR/IOMMU as inbound ranges */
2603 dma-ranges = <0x42000 2603 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
2604 interrupts = <GIC_SPI 2604 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
2605 <GIC_SPI 149 2605 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
2606 <GIC_SPI 150 2606 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
2607 #interrupt-cells = <1 2607 #interrupt-cells = <1>;
2608 interrupt-map-mask = 2608 interrupt-map-mask = <0 0 0 0>;
2609 interrupt-map = <0 0 2609 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2610 clocks = <&cpg CPG_MO 2610 clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>;
2611 clock-names = "pcie", 2611 clock-names = "pcie", "pcie_bus";
2612 power-domains = <&sys 2612 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2613 resets = <&cpg 318>; 2613 resets = <&cpg 318>;
2614 iommu-map = <0 &ipmmu 2614 iommu-map = <0 &ipmmu_hc 1 1>;
2615 iommu-map-mask = <0>; 2615 iommu-map-mask = <0>;
2616 status = "disabled"; 2616 status = "disabled";
2617 }; 2617 };
2618 2618
2619 imr-lx4@fe860000 { 2619 imr-lx4@fe860000 {
2620 compatible = "renesas 2620 compatible = "renesas,r8a7796-imr-lx4",
2621 "renesas 2621 "renesas,imr-lx4";
2622 reg = <0 0xfe860000 0 2622 reg = <0 0xfe860000 0 0x2000>;
2623 interrupts = <GIC_SPI 2623 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
2624 clocks = <&cpg CPG_MO 2624 clocks = <&cpg CPG_MOD 823>;
2625 power-domains = <&sys 2625 power-domains = <&sysc R8A7796_PD_A3VC>;
2626 resets = <&cpg 823>; 2626 resets = <&cpg 823>;
2627 }; 2627 };
2628 2628
2629 imr-lx4@fe870000 { 2629 imr-lx4@fe870000 {
2630 compatible = "renesas 2630 compatible = "renesas,r8a7796-imr-lx4",
2631 "renesas 2631 "renesas,imr-lx4";
2632 reg = <0 0xfe870000 0 2632 reg = <0 0xfe870000 0 0x2000>;
2633 interrupts = <GIC_SPI 2633 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
2634 clocks = <&cpg CPG_MO 2634 clocks = <&cpg CPG_MOD 822>;
2635 power-domains = <&sys 2635 power-domains = <&sysc R8A7796_PD_A3VC>;
2636 resets = <&cpg 822>; 2636 resets = <&cpg 822>;
2637 }; 2637 };
2638 2638
2639 fdp1@fe940000 { 2639 fdp1@fe940000 {
2640 compatible = "renesas 2640 compatible = "renesas,fdp1";
2641 reg = <0 0xfe940000 0 2641 reg = <0 0xfe940000 0 0x2400>;
2642 interrupts = <GIC_SPI 2642 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
2643 clocks = <&cpg CPG_MO 2643 clocks = <&cpg CPG_MOD 119>;
2644 power-domains = <&sys 2644 power-domains = <&sysc R8A7796_PD_A3VC>;
2645 resets = <&cpg 119>; 2645 resets = <&cpg 119>;
2646 renesas,fcp = <&fcpf0 2646 renesas,fcp = <&fcpf0>;
2647 }; 2647 };
2648 2648
2649 fcpf0: fcp@fe950000 { 2649 fcpf0: fcp@fe950000 {
2650 compatible = "renesas 2650 compatible = "renesas,fcpf";
2651 reg = <0 0xfe950000 0 2651 reg = <0 0xfe950000 0 0x200>;
2652 clocks = <&cpg CPG_MO 2652 clocks = <&cpg CPG_MOD 615>;
2653 power-domains = <&sys 2653 power-domains = <&sysc R8A7796_PD_A3VC>;
2654 resets = <&cpg 615>; 2654 resets = <&cpg 615>;
2655 iommus = <&ipmmu_vc0 <<
2656 }; 2655 };
2657 2656
2658 fcpvb0: fcp@fe96f000 { 2657 fcpvb0: fcp@fe96f000 {
2659 compatible = "renesas 2658 compatible = "renesas,fcpv";
2660 reg = <0 0xfe96f000 0 2659 reg = <0 0xfe96f000 0 0x200>;
2661 clocks = <&cpg CPG_MO 2660 clocks = <&cpg CPG_MOD 607>;
2662 power-domains = <&sys 2661 power-domains = <&sysc R8A7796_PD_A3VC>;
2663 resets = <&cpg 607>; 2662 resets = <&cpg 607>;
2664 iommus = <&ipmmu_vi0 <<
2665 }; 2663 };
2666 2664
2667 fcpvi0: fcp@fe9af000 { 2665 fcpvi0: fcp@fe9af000 {
2668 compatible = "renesas 2666 compatible = "renesas,fcpv";
2669 reg = <0 0xfe9af000 0 2667 reg = <0 0xfe9af000 0 0x200>;
2670 clocks = <&cpg CPG_MO 2668 clocks = <&cpg CPG_MOD 611>;
2671 power-domains = <&sys 2669 power-domains = <&sysc R8A7796_PD_A3VC>;
2672 resets = <&cpg 611>; 2670 resets = <&cpg 611>;
2673 iommus = <&ipmmu_vc0 2671 iommus = <&ipmmu_vc0 19>;
2674 }; 2672 };
2675 2673
2676 fcpvd0: fcp@fea27000 { 2674 fcpvd0: fcp@fea27000 {
2677 compatible = "renesas 2675 compatible = "renesas,fcpv";
2678 reg = <0 0xfea27000 0 2676 reg = <0 0xfea27000 0 0x200>;
2679 clocks = <&cpg CPG_MO 2677 clocks = <&cpg CPG_MOD 603>;
2680 power-domains = <&sys 2678 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2681 resets = <&cpg 603>; 2679 resets = <&cpg 603>;
2682 iommus = <&ipmmu_vi0 2680 iommus = <&ipmmu_vi0 8>;
2683 }; 2681 };
2684 2682
2685 fcpvd1: fcp@fea2f000 { 2683 fcpvd1: fcp@fea2f000 {
2686 compatible = "renesas 2684 compatible = "renesas,fcpv";
2687 reg = <0 0xfea2f000 0 2685 reg = <0 0xfea2f000 0 0x200>;
2688 clocks = <&cpg CPG_MO 2686 clocks = <&cpg CPG_MOD 602>;
2689 power-domains = <&sys 2687 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2690 resets = <&cpg 602>; 2688 resets = <&cpg 602>;
2691 iommus = <&ipmmu_vi0 2689 iommus = <&ipmmu_vi0 9>;
2692 }; 2690 };
2693 2691
2694 fcpvd2: fcp@fea37000 { 2692 fcpvd2: fcp@fea37000 {
2695 compatible = "renesas 2693 compatible = "renesas,fcpv";
2696 reg = <0 0xfea37000 0 2694 reg = <0 0xfea37000 0 0x200>;
2697 clocks = <&cpg CPG_MO 2695 clocks = <&cpg CPG_MOD 601>;
2698 power-domains = <&sys 2696 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2699 resets = <&cpg 601>; 2697 resets = <&cpg 601>;
2700 iommus = <&ipmmu_vi0 2698 iommus = <&ipmmu_vi0 10>;
2701 }; 2699 };
2702 2700
2703 vspb: vsp@fe960000 { 2701 vspb: vsp@fe960000 {
2704 compatible = "renesas 2702 compatible = "renesas,vsp2";
2705 reg = <0 0xfe960000 0 2703 reg = <0 0xfe960000 0 0x8000>;
2706 interrupts = <GIC_SPI 2704 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
2707 clocks = <&cpg CPG_MO 2705 clocks = <&cpg CPG_MOD 626>;
2708 power-domains = <&sys 2706 power-domains = <&sysc R8A7796_PD_A3VC>;
2709 resets = <&cpg 626>; 2707 resets = <&cpg 626>;
2710 2708
2711 renesas,fcp = <&fcpvb 2709 renesas,fcp = <&fcpvb0>;
2712 }; 2710 };
2713 2711
2714 vspd0: vsp@fea20000 { 2712 vspd0: vsp@fea20000 {
2715 compatible = "renesas 2713 compatible = "renesas,vsp2";
2716 reg = <0 0xfea20000 0 2714 reg = <0 0xfea20000 0 0x5000>;
2717 interrupts = <GIC_SPI 2715 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
2718 clocks = <&cpg CPG_MO 2716 clocks = <&cpg CPG_MOD 623>;
2719 power-domains = <&sys 2717 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2720 resets = <&cpg 623>; 2718 resets = <&cpg 623>;
2721 2719
2722 renesas,fcp = <&fcpvd 2720 renesas,fcp = <&fcpvd0>;
2723 }; 2721 };
2724 2722
2725 vspd1: vsp@fea28000 { 2723 vspd1: vsp@fea28000 {
2726 compatible = "renesas 2724 compatible = "renesas,vsp2";
2727 reg = <0 0xfea28000 0 2725 reg = <0 0xfea28000 0 0x5000>;
2728 interrupts = <GIC_SPI 2726 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
2729 clocks = <&cpg CPG_MO 2727 clocks = <&cpg CPG_MOD 622>;
2730 power-domains = <&sys 2728 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2731 resets = <&cpg 622>; 2729 resets = <&cpg 622>;
2732 2730
2733 renesas,fcp = <&fcpvd 2731 renesas,fcp = <&fcpvd1>;
2734 }; 2732 };
2735 2733
2736 vspd2: vsp@fea30000 { 2734 vspd2: vsp@fea30000 {
2737 compatible = "renesas 2735 compatible = "renesas,vsp2";
2738 reg = <0 0xfea30000 0 2736 reg = <0 0xfea30000 0 0x5000>;
2739 interrupts = <GIC_SPI 2737 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
2740 clocks = <&cpg CPG_MO 2738 clocks = <&cpg CPG_MOD 621>;
2741 power-domains = <&sys 2739 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2742 resets = <&cpg 621>; 2740 resets = <&cpg 621>;
2743 2741
2744 renesas,fcp = <&fcpvd 2742 renesas,fcp = <&fcpvd2>;
2745 }; 2743 };
2746 2744
2747 vspi0: vsp@fe9a0000 { 2745 vspi0: vsp@fe9a0000 {
2748 compatible = "renesas 2746 compatible = "renesas,vsp2";
2749 reg = <0 0xfe9a0000 0 2747 reg = <0 0xfe9a0000 0 0x8000>;
2750 interrupts = <GIC_SPI 2748 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
2751 clocks = <&cpg CPG_MO 2749 clocks = <&cpg CPG_MOD 631>;
2752 power-domains = <&sys 2750 power-domains = <&sysc R8A7796_PD_A3VC>;
2753 resets = <&cpg 631>; 2751 resets = <&cpg 631>;
2754 2752
2755 renesas,fcp = <&fcpvi 2753 renesas,fcp = <&fcpvi0>;
2756 }; 2754 };
2757 2755
2758 cmm0: cmm@fea40000 { 2756 cmm0: cmm@fea40000 {
2759 compatible = "renesas 2757 compatible = "renesas,r8a7796-cmm",
2760 "renesas 2758 "renesas,rcar-gen3-cmm";
2761 reg = <0 0xfea40000 0 2759 reg = <0 0xfea40000 0 0x1000>;
2762 power-domains = <&sys 2760 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2763 clocks = <&cpg CPG_MO 2761 clocks = <&cpg CPG_MOD 711>;
2764 resets = <&cpg 711>; 2762 resets = <&cpg 711>;
2765 }; 2763 };
2766 2764
2767 cmm1: cmm@fea50000 { 2765 cmm1: cmm@fea50000 {
2768 compatible = "renesas 2766 compatible = "renesas,r8a7796-cmm",
2769 "renesas 2767 "renesas,rcar-gen3-cmm";
2770 reg = <0 0xfea50000 0 2768 reg = <0 0xfea50000 0 0x1000>;
2771 power-domains = <&sys 2769 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2772 clocks = <&cpg CPG_MO 2770 clocks = <&cpg CPG_MOD 710>;
2773 resets = <&cpg 710>; 2771 resets = <&cpg 710>;
2774 }; 2772 };
2775 2773
2776 cmm2: cmm@fea60000 { 2774 cmm2: cmm@fea60000 {
2777 compatible = "renesas 2775 compatible = "renesas,r8a7796-cmm",
2778 "renesas 2776 "renesas,rcar-gen3-cmm";
2779 reg = <0 0xfea60000 0 2777 reg = <0 0xfea60000 0 0x1000>;
2780 power-domains = <&sys 2778 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2781 clocks = <&cpg CPG_MO 2779 clocks = <&cpg CPG_MOD 709>;
2782 resets = <&cpg 709>; 2780 resets = <&cpg 709>;
2783 }; 2781 };
2784 2782
2785 csi20: csi2@fea80000 { 2783 csi20: csi2@fea80000 {
2786 compatible = "renesas 2784 compatible = "renesas,r8a7796-csi2";
2787 reg = <0 0xfea80000 0 2785 reg = <0 0xfea80000 0 0x10000>;
2788 interrupts = <GIC_SPI 2786 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
2789 clocks = <&cpg CPG_MO 2787 clocks = <&cpg CPG_MOD 714>;
2790 power-domains = <&sys 2788 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2791 resets = <&cpg 714>; 2789 resets = <&cpg 714>;
2792 status = "disabled"; 2790 status = "disabled";
2793 2791
2794 ports { 2792 ports {
2795 #address-cell 2793 #address-cells = <1>;
2796 #size-cells = 2794 #size-cells = <0>;
2797 2795
2798 port@0 { 2796 port@0 {
2799 reg = 2797 reg = <0>;
2800 }; 2798 };
2801 2799
2802 port@1 { 2800 port@1 {
2803 #addr 2801 #address-cells = <1>;
2804 #size 2802 #size-cells = <0>;
2805 2803
2806 reg = 2804 reg = <1>;
2807 2805
2808 csi20 2806 csi20vin0: endpoint@0 {
2809 2807 reg = <0>;
2810 2808 remote-endpoint = <&vin0csi20>;
2811 }; 2809 };
2812 csi20 2810 csi20vin1: endpoint@1 {
2813 2811 reg = <1>;
2814 2812 remote-endpoint = <&vin1csi20>;
2815 }; 2813 };
2816 csi20 2814 csi20vin2: endpoint@2 {
2817 2815 reg = <2>;
2818 2816 remote-endpoint = <&vin2csi20>;
2819 }; 2817 };
2820 csi20 2818 csi20vin3: endpoint@3 {
2821 2819 reg = <3>;
2822 2820 remote-endpoint = <&vin3csi20>;
2823 }; 2821 };
2824 csi20 2822 csi20vin4: endpoint@4 {
2825 2823 reg = <4>;
2826 2824 remote-endpoint = <&vin4csi20>;
2827 }; 2825 };
2828 csi20 2826 csi20vin5: endpoint@5 {
2829 2827 reg = <5>;
2830 2828 remote-endpoint = <&vin5csi20>;
2831 }; 2829 };
2832 csi20 2830 csi20vin6: endpoint@6 {
2833 2831 reg = <6>;
2834 2832 remote-endpoint = <&vin6csi20>;
2835 }; 2833 };
2836 csi20 2834 csi20vin7: endpoint@7 {
2837 2835 reg = <7>;
2838 2836 remote-endpoint = <&vin7csi20>;
2839 }; 2837 };
2840 }; 2838 };
2841 }; 2839 };
2842 }; 2840 };
2843 2841
2844 csi40: csi2@feaa0000 { 2842 csi40: csi2@feaa0000 {
2845 compatible = "renesas 2843 compatible = "renesas,r8a7796-csi2";
2846 reg = <0 0xfeaa0000 0 2844 reg = <0 0xfeaa0000 0 0x10000>;
2847 interrupts = <GIC_SPI 2845 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
2848 clocks = <&cpg CPG_MO 2846 clocks = <&cpg CPG_MOD 716>;
2849 power-domains = <&sys 2847 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2850 resets = <&cpg 716>; 2848 resets = <&cpg 716>;
2851 status = "disabled"; 2849 status = "disabled";
2852 2850
2853 ports { 2851 ports {
2854 #address-cell 2852 #address-cells = <1>;
2855 #size-cells = 2853 #size-cells = <0>;
2856 2854
2857 port@0 { 2855 port@0 {
2858 reg = 2856 reg = <0>;
2859 }; 2857 };
2860 2858
2861 port@1 { 2859 port@1 {
2862 #addr 2860 #address-cells = <1>;
2863 #size 2861 #size-cells = <0>;
2864 2862
2865 reg = 2863 reg = <1>;
2866 2864
2867 csi40 2865 csi40vin0: endpoint@0 {
2868 2866 reg = <0>;
2869 2867 remote-endpoint = <&vin0csi40>;
2870 }; 2868 };
2871 csi40 2869 csi40vin1: endpoint@1 {
2872 2870 reg = <1>;
2873 2871 remote-endpoint = <&vin1csi40>;
2874 }; 2872 };
2875 csi40 2873 csi40vin2: endpoint@2 {
2876 2874 reg = <2>;
2877 2875 remote-endpoint = <&vin2csi40>;
2878 }; 2876 };
2879 csi40 2877 csi40vin3: endpoint@3 {
2880 2878 reg = <3>;
2881 2879 remote-endpoint = <&vin3csi40>;
2882 }; 2880 };
2883 csi40 2881 csi40vin4: endpoint@4 {
2884 2882 reg = <4>;
2885 2883 remote-endpoint = <&vin4csi40>;
2886 }; 2884 };
2887 csi40 2885 csi40vin5: endpoint@5 {
2888 2886 reg = <5>;
2889 2887 remote-endpoint = <&vin5csi40>;
2890 }; 2888 };
2891 csi40 2889 csi40vin6: endpoint@6 {
2892 2890 reg = <6>;
2893 2891 remote-endpoint = <&vin6csi40>;
2894 }; 2892 };
2895 csi40 2893 csi40vin7: endpoint@7 {
2896 2894 reg = <7>;
2897 2895 remote-endpoint = <&vin7csi40>;
2898 }; 2896 };
2899 }; 2897 };
2900 2898
2901 }; 2899 };
2902 }; 2900 };
2903 2901
2904 hdmi0: hdmi@fead0000 { 2902 hdmi0: hdmi@fead0000 {
2905 compatible = "renesas 2903 compatible = "renesas,r8a7796-hdmi", "renesas,rcar-gen3-hdmi";
2906 reg = <0 0xfead0000 0 2904 reg = <0 0xfead0000 0 0x10000>;
2907 interrupts = <GIC_SPI 2905 interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
2908 clocks = <&cpg CPG_MO 2906 clocks = <&cpg CPG_MOD 729>, <&cpg CPG_CORE R8A7796_CLK_HDMI>;
2909 clock-names = "iahb", 2907 clock-names = "iahb", "isfr";
2910 power-domains = <&sys 2908 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2911 resets = <&cpg 729>; 2909 resets = <&cpg 729>;
2912 status = "disabled"; 2910 status = "disabled";
2913 2911
2914 ports { 2912 ports {
2915 #address-cell 2913 #address-cells = <1>;
2916 #size-cells = 2914 #size-cells = <0>;
2917 port@0 { 2915 port@0 {
2918 reg = 2916 reg = <0>;
2919 dw_hd 2917 dw_hdmi0_in: endpoint {
2920 2918 remote-endpoint = <&du_out_hdmi0>;
2921 }; 2919 };
2922 }; 2920 };
2923 port@1 { 2921 port@1 {
2924 reg = 2922 reg = <1>;
2925 }; 2923 };
2926 port@2 { 2924 port@2 {
2927 /* HD 2925 /* HDMI sound */
2928 reg = 2926 reg = <2>;
2929 }; 2927 };
2930 }; 2928 };
2931 }; 2929 };
2932 2930
2933 du: display@feb00000 { 2931 du: display@feb00000 {
2934 compatible = "renesas 2932 compatible = "renesas,du-r8a7796";
2935 reg = <0 0xfeb00000 0 2933 reg = <0 0xfeb00000 0 0x70000>;
2936 interrupts = <GIC_SPI 2934 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
2937 <GIC_SPI 2935 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
2938 <GIC_SPI 2936 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
2939 clocks = <&cpg CPG_MO 2937 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
2940 <&cpg CPG_MO 2938 <&cpg CPG_MOD 722>;
2941 clock-names = "du.0", 2939 clock-names = "du.0", "du.1", "du.2";
2942 resets = <&cpg 724>, 2940 resets = <&cpg 724>, <&cpg 722>;
2943 reset-names = "du.0", 2941 reset-names = "du.0", "du.2";
2944 2942
2945 renesas,cmms = <&cmm0 2943 renesas,cmms = <&cmm0>, <&cmm1>, <&cmm2>;
2946 renesas,vsps = <&vspd 2944 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>;
2947 2945
2948 status = "disabled"; 2946 status = "disabled";
2949 2947
2950 ports { 2948 ports {
2951 #address-cell 2949 #address-cells = <1>;
2952 #size-cells = 2950 #size-cells = <0>;
2953 2951
2954 port@0 { 2952 port@0 {
2955 reg = 2953 reg = <0>;
2956 }; 2954 };
2957 port@1 { 2955 port@1 {
2958 reg = 2956 reg = <1>;
2959 du_ou 2957 du_out_hdmi0: endpoint {
2960 2958 remote-endpoint = <&dw_hdmi0_in>;
2961 }; 2959 };
2962 }; 2960 };
2963 port@2 { 2961 port@2 {
2964 reg = 2962 reg = <2>;
2965 du_ou 2963 du_out_lvds0: endpoint {
2966 2964 remote-endpoint = <&lvds0_in>;
2967 }; 2965 };
2968 }; 2966 };
2969 }; 2967 };
2970 }; 2968 };
2971 2969
2972 lvds0: lvds@feb90000 { 2970 lvds0: lvds@feb90000 {
2973 compatible = "renesas 2971 compatible = "renesas,r8a7796-lvds";
2974 reg = <0 0xfeb90000 0 2972 reg = <0 0xfeb90000 0 0x14>;
2975 clocks = <&cpg CPG_MO 2973 clocks = <&cpg CPG_MOD 727>;
2976 power-domains = <&sys 2974 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2977 resets = <&cpg 727>; 2975 resets = <&cpg 727>;
2978 status = "disabled"; 2976 status = "disabled";
2979 2977
2980 ports { 2978 ports {
2981 #address-cell 2979 #address-cells = <1>;
2982 #size-cells = 2980 #size-cells = <0>;
2983 2981
2984 port@0 { 2982 port@0 {
2985 reg = 2983 reg = <0>;
2986 lvds0 2984 lvds0_in: endpoint {
2987 2985 remote-endpoint = <&du_out_lvds0>;
2988 }; 2986 };
2989 }; 2987 };
2990 port@1 { 2988 port@1 {
2991 reg = 2989 reg = <1>;
2992 }; 2990 };
2993 }; 2991 };
2994 }; 2992 };
2995 2993
2996 prr: chipid@fff00044 { 2994 prr: chipid@fff00044 {
2997 compatible = "renesas 2995 compatible = "renesas,prr";
2998 reg = <0 0xfff00044 0 2996 reg = <0 0xfff00044 0 4>;
2999 }; 2997 };
3000 }; 2998 };
3001 2999
3002 thermal-zones { 3000 thermal-zones {
3003 sensor1_thermal: sensor1-ther 3001 sensor1_thermal: sensor1-thermal {
3004 polling-delay-passive 3002 polling-delay-passive = <250>;
3005 polling-delay = <1000 3003 polling-delay = <1000>;
3006 thermal-sensors = <&t 3004 thermal-sensors = <&tsc 0>;
3007 sustainable-power = < 3005 sustainable-power = <3874>;
3008 3006
3009 trips { 3007 trips {
3010 sensor1_crit: 3008 sensor1_crit: sensor1-crit {
3011 tempe 3009 temperature = <120000>;
3012 hyste 3010 hysteresis = <1000>;
3013 type 3011 type = "critical";
3014 }; 3012 };
3015 }; 3013 };
3016 }; 3014 };
3017 3015
3018 sensor2_thermal: sensor2-ther 3016 sensor2_thermal: sensor2-thermal {
3019 polling-delay-passive 3017 polling-delay-passive = <250>;
3020 polling-delay = <1000 3018 polling-delay = <1000>;
3021 thermal-sensors = <&t 3019 thermal-sensors = <&tsc 1>;
3022 sustainable-power = < 3020 sustainable-power = <3874>;
3023 3021
3024 trips { 3022 trips {
3025 sensor2_crit: 3023 sensor2_crit: sensor2-crit {
3026 tempe 3024 temperature = <120000>;
3027 hyste 3025 hysteresis = <1000>;
3028 type 3026 type = "critical";
3029 }; 3027 };
3030 }; 3028 };
3031 }; 3029 };
3032 3030
3033 sensor3_thermal: sensor3-ther 3031 sensor3_thermal: sensor3-thermal {
3034 polling-delay-passive 3032 polling-delay-passive = <250>;
3035 polling-delay = <1000 3033 polling-delay = <1000>;
3036 thermal-sensors = <&t 3034 thermal-sensors = <&tsc 2>;
3037 sustainable-power = < 3035 sustainable-power = <3874>;
3038 3036
3039 cooling-maps { 3037 cooling-maps {
3040 map0 { 3038 map0 {
3041 trip 3039 trip = <&target>;
3042 cooli 3040 cooling-device = <&a57_0 2 4>;
3043 contr 3041 contribution = <1024>;
3044 }; 3042 };
3045 map1 { 3043 map1 {
3046 trip 3044 trip = <&target>;
3047 cooli 3045 cooling-device = <&a53_0 0 2>;
3048 contr 3046 contribution = <1024>;
3049 }; 3047 };
3050 }; 3048 };
3051 trips { 3049 trips {
3052 target: trip- 3050 target: trip-point1 {
3053 tempe 3051 temperature = <100000>;
3054 hyste 3052 hysteresis = <1000>;
3055 type 3053 type = "passive";
3056 }; 3054 };
3057 3055
3058 sensor3_crit: 3056 sensor3_crit: sensor3-crit {
3059 tempe 3057 temperature = <120000>;
3060 hyste 3058 hysteresis = <1000>;
3061 type 3059 type = "critical";
3062 }; 3060 };
3063 }; 3061 };
3064 }; 3062 };
3065 }; 3063 };
3066 3064
3067 timer { 3065 timer {
3068 compatible = "arm,armv8-timer 3066 compatible = "arm,armv8-timer";
3069 interrupts-extended = <&gic G 3067 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
3070 <&gic G 3068 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
3071 <&gic G 3069 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
3072 <&gic G 3070 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
3073 interrupt-names = "sec-phys", <<
3074 }; 3071 };
3075 3072
3076 /* External USB clocks - can be overr 3073 /* External USB clocks - can be overridden by the board */
3077 usb3s0_clk: usb3s0 { 3074 usb3s0_clk: usb3s0 {
3078 compatible = "fixed-clock"; 3075 compatible = "fixed-clock";
3079 #clock-cells = <0>; 3076 #clock-cells = <0>;
3080 clock-frequency = <0>; 3077 clock-frequency = <0>;
3081 }; 3078 };
3082 3079
3083 usb_extal_clk: usb_extal { 3080 usb_extal_clk: usb_extal {
3084 compatible = "fixed-clock"; 3081 compatible = "fixed-clock";
3085 #clock-cells = <0>; 3082 #clock-cells = <0>;
3086 clock-frequency = <0>; 3083 clock-frequency = <0>;
3087 }; 3084 };
3088 }; 3085 };
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