1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * Device Tree Source for the R-Car M3-W (R8A7 3 * Device Tree Source for the R-Car M3-W (R8A77960) SoC
4 * 4 *
5 * Copyright (C) 2016-2017 Renesas Electronics 5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
6 */ 6 */
7 7
8 #include <dt-bindings/clock/r8a7796-cpg-mssr.h 8 #include <dt-bindings/clock/r8a7796-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm 9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a7796-sysc.h> 10 #include <dt-bindings/power/r8a7796-sysc.h>
11 11
>> 12 #define CPG_AUDIO_CLK_I R8A7796_CLK_S0D4
>> 13
12 / { 14 / {
13 compatible = "renesas,r8a7796"; 15 compatible = "renesas,r8a7796";
14 #address-cells = <2>; 16 #address-cells = <2>;
15 #size-cells = <2>; 17 #size-cells = <2>;
16 18
17 /* 19 /*
18 * The external audio clocks are confi 20 * The external audio clocks are configured as 0 Hz fixed frequency
19 * clocks by default. 21 * clocks by default.
20 * Boards that provide audio clocks sh 22 * Boards that provide audio clocks should override them.
21 */ 23 */
22 audio_clk_a: audio_clk_a { 24 audio_clk_a: audio_clk_a {
23 compatible = "fixed-clock"; 25 compatible = "fixed-clock";
24 #clock-cells = <0>; 26 #clock-cells = <0>;
25 clock-frequency = <0>; 27 clock-frequency = <0>;
26 }; 28 };
27 29
28 audio_clk_b: audio_clk_b { 30 audio_clk_b: audio_clk_b {
29 compatible = "fixed-clock"; 31 compatible = "fixed-clock";
30 #clock-cells = <0>; 32 #clock-cells = <0>;
31 clock-frequency = <0>; 33 clock-frequency = <0>;
32 }; 34 };
33 35
34 audio_clk_c: audio_clk_c { 36 audio_clk_c: audio_clk_c {
35 compatible = "fixed-clock"; 37 compatible = "fixed-clock";
36 #clock-cells = <0>; 38 #clock-cells = <0>;
37 clock-frequency = <0>; 39 clock-frequency = <0>;
38 }; 40 };
39 41
40 /* External CAN clock - to be overridd 42 /* External CAN clock - to be overridden by boards that provide it */
41 can_clk: can { 43 can_clk: can {
42 compatible = "fixed-clock"; 44 compatible = "fixed-clock";
43 #clock-cells = <0>; 45 #clock-cells = <0>;
44 clock-frequency = <0>; 46 clock-frequency = <0>;
45 }; 47 };
46 48
47 cluster0_opp: opp-table-0 { 49 cluster0_opp: opp-table-0 {
48 compatible = "operating-points 50 compatible = "operating-points-v2";
49 opp-shared; 51 opp-shared;
50 52
51 opp-500000000 { 53 opp-500000000 {
52 opp-hz = /bits/ 64 <50 54 opp-hz = /bits/ 64 <500000000>;
53 opp-microvolt = <83000 55 opp-microvolt = <830000>;
54 clock-latency-ns = <30 56 clock-latency-ns = <300000>;
55 }; 57 };
56 opp-1000000000 { 58 opp-1000000000 {
57 opp-hz = /bits/ 64 <10 59 opp-hz = /bits/ 64 <1000000000>;
58 opp-microvolt = <83000 60 opp-microvolt = <830000>;
59 clock-latency-ns = <30 61 clock-latency-ns = <300000>;
60 }; 62 };
61 opp-1500000000 { 63 opp-1500000000 {
62 opp-hz = /bits/ 64 <15 64 opp-hz = /bits/ 64 <1500000000>;
63 opp-microvolt = <83000 65 opp-microvolt = <830000>;
64 clock-latency-ns = <30 66 clock-latency-ns = <300000>;
65 opp-suspend; 67 opp-suspend;
66 }; 68 };
67 opp-1600000000 { 69 opp-1600000000 {
68 opp-hz = /bits/ 64 <16 70 opp-hz = /bits/ 64 <1600000000>;
69 opp-microvolt = <90000 71 opp-microvolt = <900000>;
70 clock-latency-ns = <30 72 clock-latency-ns = <300000>;
71 }; 73 };
72 opp-1700000000 { 74 opp-1700000000 {
73 opp-hz = /bits/ 64 <17 75 opp-hz = /bits/ 64 <1700000000>;
74 opp-microvolt = <90000 76 opp-microvolt = <900000>;
75 clock-latency-ns = <30 77 clock-latency-ns = <300000>;
76 }; 78 };
77 opp-1800000000 { 79 opp-1800000000 {
78 opp-hz = /bits/ 64 <18 80 opp-hz = /bits/ 64 <1800000000>;
79 opp-microvolt = <96000 81 opp-microvolt = <960000>;
80 clock-latency-ns = <30 82 clock-latency-ns = <300000>;
81 turbo-mode; 83 turbo-mode;
82 }; 84 };
83 }; 85 };
84 86
85 cluster1_opp: opp-table-1 { 87 cluster1_opp: opp-table-1 {
86 compatible = "operating-points 88 compatible = "operating-points-v2";
87 opp-shared; 89 opp-shared;
88 90
89 opp-800000000 { 91 opp-800000000 {
90 opp-hz = /bits/ 64 <80 92 opp-hz = /bits/ 64 <800000000>;
91 opp-microvolt = <82000 93 opp-microvolt = <820000>;
92 clock-latency-ns = <30 94 clock-latency-ns = <300000>;
93 }; 95 };
94 opp-1000000000 { 96 opp-1000000000 {
95 opp-hz = /bits/ 64 <10 97 opp-hz = /bits/ 64 <1000000000>;
96 opp-microvolt = <82000 98 opp-microvolt = <820000>;
97 clock-latency-ns = <30 99 clock-latency-ns = <300000>;
98 }; 100 };
99 opp-1200000000 { 101 opp-1200000000 {
100 opp-hz = /bits/ 64 <12 102 opp-hz = /bits/ 64 <1200000000>;
101 opp-microvolt = <82000 103 opp-microvolt = <820000>;
102 clock-latency-ns = <30 104 clock-latency-ns = <300000>;
103 }; 105 };
104 opp-1300000000 { 106 opp-1300000000 {
105 opp-hz = /bits/ 64 <13 107 opp-hz = /bits/ 64 <1300000000>;
106 opp-microvolt = <82000 108 opp-microvolt = <820000>;
107 clock-latency-ns = <30 109 clock-latency-ns = <300000>;
108 turbo-mode; 110 turbo-mode;
109 }; 111 };
110 }; 112 };
111 113
112 cpus { 114 cpus {
113 #address-cells = <1>; 115 #address-cells = <1>;
114 #size-cells = <0>; 116 #size-cells = <0>;
115 117
116 cpu-map { 118 cpu-map {
117 cluster0 { 119 cluster0 {
118 core0 { 120 core0 {
119 cpu = 121 cpu = <&a57_0>;
120 }; 122 };
121 core1 { 123 core1 {
122 cpu = 124 cpu = <&a57_1>;
123 }; 125 };
124 }; 126 };
125 127
126 cluster1 { 128 cluster1 {
127 core0 { 129 core0 {
128 cpu = 130 cpu = <&a53_0>;
129 }; 131 };
130 core1 { 132 core1 {
131 cpu = 133 cpu = <&a53_1>;
132 }; 134 };
133 core2 { 135 core2 {
134 cpu = 136 cpu = <&a53_2>;
135 }; 137 };
136 core3 { 138 core3 {
137 cpu = 139 cpu = <&a53_3>;
138 }; 140 };
139 }; 141 };
140 }; 142 };
141 143
142 a57_0: cpu@0 { 144 a57_0: cpu@0 {
143 compatible = "arm,cort 145 compatible = "arm,cortex-a57";
144 reg = <0x0>; 146 reg = <0x0>;
145 device_type = "cpu"; 147 device_type = "cpu";
146 power-domains = <&sysc 148 power-domains = <&sysc R8A7796_PD_CA57_CPU0>;
147 next-level-cache = <&L 149 next-level-cache = <&L2_CA57>;
148 enable-method = "psci" 150 enable-method = "psci";
149 cpu-idle-states = <&CP 151 cpu-idle-states = <&CPU_SLEEP_0>;
150 dynamic-power-coeffici 152 dynamic-power-coefficient = <854>;
151 clocks = <&cpg CPG_COR 153 clocks = <&cpg CPG_CORE R8A7796_CLK_Z>;
152 operating-points-v2 = 154 operating-points-v2 = <&cluster0_opp>;
153 capacity-dmips-mhz = < 155 capacity-dmips-mhz = <1024>;
154 #cooling-cells = <2>; 156 #cooling-cells = <2>;
155 }; 157 };
156 158
157 a57_1: cpu@1 { 159 a57_1: cpu@1 {
158 compatible = "arm,cort 160 compatible = "arm,cortex-a57";
159 reg = <0x1>; 161 reg = <0x1>;
160 device_type = "cpu"; 162 device_type = "cpu";
161 power-domains = <&sysc 163 power-domains = <&sysc R8A7796_PD_CA57_CPU1>;
162 next-level-cache = <&L 164 next-level-cache = <&L2_CA57>;
163 enable-method = "psci" 165 enable-method = "psci";
164 cpu-idle-states = <&CP 166 cpu-idle-states = <&CPU_SLEEP_0>;
165 clocks = <&cpg CPG_COR 167 clocks = <&cpg CPG_CORE R8A7796_CLK_Z>;
166 operating-points-v2 = 168 operating-points-v2 = <&cluster0_opp>;
167 capacity-dmips-mhz = < 169 capacity-dmips-mhz = <1024>;
168 #cooling-cells = <2>; 170 #cooling-cells = <2>;
169 }; 171 };
170 172
171 a53_0: cpu@100 { 173 a53_0: cpu@100 {
172 compatible = "arm,cort 174 compatible = "arm,cortex-a53";
173 reg = <0x100>; 175 reg = <0x100>;
174 device_type = "cpu"; 176 device_type = "cpu";
175 power-domains = <&sysc 177 power-domains = <&sysc R8A7796_PD_CA53_CPU0>;
176 next-level-cache = <&L 178 next-level-cache = <&L2_CA53>;
177 enable-method = "psci" 179 enable-method = "psci";
178 cpu-idle-states = <&CP 180 cpu-idle-states = <&CPU_SLEEP_1>;
179 #cooling-cells = <2>; 181 #cooling-cells = <2>;
180 dynamic-power-coeffici 182 dynamic-power-coefficient = <277>;
181 clocks = <&cpg CPG_COR 183 clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
182 operating-points-v2 = 184 operating-points-v2 = <&cluster1_opp>;
183 capacity-dmips-mhz = < 185 capacity-dmips-mhz = <535>;
184 }; 186 };
185 187
186 a53_1: cpu@101 { 188 a53_1: cpu@101 {
187 compatible = "arm,cort 189 compatible = "arm,cortex-a53";
188 reg = <0x101>; 190 reg = <0x101>;
189 device_type = "cpu"; 191 device_type = "cpu";
190 power-domains = <&sysc 192 power-domains = <&sysc R8A7796_PD_CA53_CPU1>;
191 next-level-cache = <&L 193 next-level-cache = <&L2_CA53>;
192 enable-method = "psci" 194 enable-method = "psci";
193 cpu-idle-states = <&CP 195 cpu-idle-states = <&CPU_SLEEP_1>;
194 clocks = <&cpg CPG_COR 196 clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
195 operating-points-v2 = 197 operating-points-v2 = <&cluster1_opp>;
196 capacity-dmips-mhz = < 198 capacity-dmips-mhz = <535>;
197 }; 199 };
198 200
199 a53_2: cpu@102 { 201 a53_2: cpu@102 {
200 compatible = "arm,cort 202 compatible = "arm,cortex-a53";
201 reg = <0x102>; 203 reg = <0x102>;
202 device_type = "cpu"; 204 device_type = "cpu";
203 power-domains = <&sysc 205 power-domains = <&sysc R8A7796_PD_CA53_CPU2>;
204 next-level-cache = <&L 206 next-level-cache = <&L2_CA53>;
205 enable-method = "psci" 207 enable-method = "psci";
206 cpu-idle-states = <&CP 208 cpu-idle-states = <&CPU_SLEEP_1>;
207 clocks = <&cpg CPG_COR 209 clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
208 operating-points-v2 = 210 operating-points-v2 = <&cluster1_opp>;
209 capacity-dmips-mhz = < 211 capacity-dmips-mhz = <535>;
210 }; 212 };
211 213
212 a53_3: cpu@103 { 214 a53_3: cpu@103 {
213 compatible = "arm,cort 215 compatible = "arm,cortex-a53";
214 reg = <0x103>; 216 reg = <0x103>;
215 device_type = "cpu"; 217 device_type = "cpu";
216 power-domains = <&sysc 218 power-domains = <&sysc R8A7796_PD_CA53_CPU3>;
217 next-level-cache = <&L 219 next-level-cache = <&L2_CA53>;
218 enable-method = "psci" 220 enable-method = "psci";
219 cpu-idle-states = <&CP 221 cpu-idle-states = <&CPU_SLEEP_1>;
220 clocks = <&cpg CPG_COR 222 clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
221 operating-points-v2 = 223 operating-points-v2 = <&cluster1_opp>;
222 capacity-dmips-mhz = < 224 capacity-dmips-mhz = <535>;
223 }; 225 };
224 226
225 L2_CA57: cache-controller-0 { 227 L2_CA57: cache-controller-0 {
226 compatible = "cache"; 228 compatible = "cache";
227 power-domains = <&sysc 229 power-domains = <&sysc R8A7796_PD_CA57_SCU>;
228 cache-unified; 230 cache-unified;
229 cache-level = <2>; 231 cache-level = <2>;
230 }; 232 };
231 233
232 L2_CA53: cache-controller-1 { 234 L2_CA53: cache-controller-1 {
233 compatible = "cache"; 235 compatible = "cache";
234 power-domains = <&sysc 236 power-domains = <&sysc R8A7796_PD_CA53_SCU>;
235 cache-unified; 237 cache-unified;
236 cache-level = <2>; 238 cache-level = <2>;
237 }; 239 };
238 240
239 idle-states { 241 idle-states {
240 entry-method = "psci"; 242 entry-method = "psci";
241 243
242 CPU_SLEEP_0: cpu-sleep 244 CPU_SLEEP_0: cpu-sleep-0 {
243 compatible = " 245 compatible = "arm,idle-state";
244 arm,psci-suspe 246 arm,psci-suspend-param = <0x0010000>;
245 local-timer-st 247 local-timer-stop;
246 entry-latency- 248 entry-latency-us = <400>;
247 exit-latency-u 249 exit-latency-us = <500>;
248 min-residency- 250 min-residency-us = <4000>;
249 }; 251 };
250 252
251 CPU_SLEEP_1: cpu-sleep 253 CPU_SLEEP_1: cpu-sleep-1 {
252 compatible = " 254 compatible = "arm,idle-state";
253 arm,psci-suspe 255 arm,psci-suspend-param = <0x0010000>;
254 local-timer-st 256 local-timer-stop;
255 entry-latency- 257 entry-latency-us = <700>;
256 exit-latency-u 258 exit-latency-us = <700>;
257 min-residency- 259 min-residency-us = <5000>;
258 }; 260 };
259 }; 261 };
260 }; 262 };
261 263
262 extal_clk: extal { 264 extal_clk: extal {
263 compatible = "fixed-clock"; 265 compatible = "fixed-clock";
264 #clock-cells = <0>; 266 #clock-cells = <0>;
265 /* This value must be overridd 267 /* This value must be overridden by the board */
266 clock-frequency = <0>; 268 clock-frequency = <0>;
267 }; 269 };
268 270
269 extalr_clk: extalr { 271 extalr_clk: extalr {
270 compatible = "fixed-clock"; 272 compatible = "fixed-clock";
271 #clock-cells = <0>; 273 #clock-cells = <0>;
272 /* This value must be overridd 274 /* This value must be overridden by the board */
273 clock-frequency = <0>; 275 clock-frequency = <0>;
274 }; 276 };
275 277
276 /* External PCIe clock - can be overri 278 /* External PCIe clock - can be overridden by the board */
277 pcie_bus_clk: pcie_bus { 279 pcie_bus_clk: pcie_bus {
278 compatible = "fixed-clock"; 280 compatible = "fixed-clock";
279 #clock-cells = <0>; 281 #clock-cells = <0>;
280 clock-frequency = <0>; 282 clock-frequency = <0>;
281 }; 283 };
282 284
283 pmu_a53 { 285 pmu_a53 {
284 compatible = "arm,cortex-a53-p 286 compatible = "arm,cortex-a53-pmu";
285 interrupts-extended = <&gic GI 287 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
286 <&gic GI 288 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
287 <&gic GI 289 <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
288 <&gic GI 290 <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
289 interrupt-affinity = <&a53_0>, 291 interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>;
290 }; 292 };
291 293
292 pmu_a57 { 294 pmu_a57 {
293 compatible = "arm,cortex-a57-p 295 compatible = "arm,cortex-a57-pmu";
294 interrupts-extended = <&gic GI 296 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
295 <&gic GI 297 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
296 interrupt-affinity = <&a57_0>, 298 interrupt-affinity = <&a57_0>, <&a57_1>;
297 }; 299 };
298 300
299 psci { 301 psci {
300 compatible = "arm,psci-1.0", " 302 compatible = "arm,psci-1.0", "arm,psci-0.2";
301 method = "smc"; 303 method = "smc";
302 }; 304 };
303 305
304 /* External SCIF clock - to be overrid 306 /* External SCIF clock - to be overridden by boards that provide it */
305 scif_clk: scif { 307 scif_clk: scif {
306 compatible = "fixed-clock"; 308 compatible = "fixed-clock";
307 #clock-cells = <0>; 309 #clock-cells = <0>;
308 clock-frequency = <0>; 310 clock-frequency = <0>;
309 }; 311 };
310 312
311 soc { 313 soc {
312 compatible = "simple-bus"; 314 compatible = "simple-bus";
313 interrupt-parent = <&gic>; 315 interrupt-parent = <&gic>;
314 #address-cells = <2>; 316 #address-cells = <2>;
315 #size-cells = <2>; 317 #size-cells = <2>;
316 ranges; 318 ranges;
317 319
318 rwdt: watchdog@e6020000 { 320 rwdt: watchdog@e6020000 {
319 compatible = "renesas, 321 compatible = "renesas,r8a7796-wdt",
320 "renesas, 322 "renesas,rcar-gen3-wdt";
321 reg = <0 0xe6020000 0 323 reg = <0 0xe6020000 0 0x0c>;
322 interrupts = <GIC_SPI 324 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
323 clocks = <&cpg CPG_MOD 325 clocks = <&cpg CPG_MOD 402>;
324 power-domains = <&sysc 326 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
325 resets = <&cpg 402>; 327 resets = <&cpg 402>;
326 status = "disabled"; 328 status = "disabled";
327 }; 329 };
328 330
329 gpio0: gpio@e6050000 { 331 gpio0: gpio@e6050000 {
330 compatible = "renesas, 332 compatible = "renesas,gpio-r8a7796",
331 "renesas, 333 "renesas,rcar-gen3-gpio";
332 reg = <0 0xe6050000 0 334 reg = <0 0xe6050000 0 0x50>;
333 interrupts = <GIC_SPI 335 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
334 #gpio-cells = <2>; 336 #gpio-cells = <2>;
335 gpio-controller; 337 gpio-controller;
336 gpio-ranges = <&pfc 0 338 gpio-ranges = <&pfc 0 0 16>;
337 #interrupt-cells = <2> 339 #interrupt-cells = <2>;
338 interrupt-controller; 340 interrupt-controller;
339 clocks = <&cpg CPG_MOD 341 clocks = <&cpg CPG_MOD 912>;
340 power-domains = <&sysc 342 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
341 resets = <&cpg 912>; 343 resets = <&cpg 912>;
342 }; 344 };
343 345
344 gpio1: gpio@e6051000 { 346 gpio1: gpio@e6051000 {
345 compatible = "renesas, 347 compatible = "renesas,gpio-r8a7796",
346 "renesas, 348 "renesas,rcar-gen3-gpio";
347 reg = <0 0xe6051000 0 349 reg = <0 0xe6051000 0 0x50>;
348 interrupts = <GIC_SPI 350 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
349 #gpio-cells = <2>; 351 #gpio-cells = <2>;
350 gpio-controller; 352 gpio-controller;
351 gpio-ranges = <&pfc 0 353 gpio-ranges = <&pfc 0 32 29>;
352 #interrupt-cells = <2> 354 #interrupt-cells = <2>;
353 interrupt-controller; 355 interrupt-controller;
354 clocks = <&cpg CPG_MOD 356 clocks = <&cpg CPG_MOD 911>;
355 power-domains = <&sysc 357 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
356 resets = <&cpg 911>; 358 resets = <&cpg 911>;
357 }; 359 };
358 360
359 gpio2: gpio@e6052000 { 361 gpio2: gpio@e6052000 {
360 compatible = "renesas, 362 compatible = "renesas,gpio-r8a7796",
361 "renesas, 363 "renesas,rcar-gen3-gpio";
362 reg = <0 0xe6052000 0 364 reg = <0 0xe6052000 0 0x50>;
363 interrupts = <GIC_SPI 365 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
364 #gpio-cells = <2>; 366 #gpio-cells = <2>;
365 gpio-controller; 367 gpio-controller;
366 gpio-ranges = <&pfc 0 368 gpio-ranges = <&pfc 0 64 15>;
367 #interrupt-cells = <2> 369 #interrupt-cells = <2>;
368 interrupt-controller; 370 interrupt-controller;
369 clocks = <&cpg CPG_MOD 371 clocks = <&cpg CPG_MOD 910>;
370 power-domains = <&sysc 372 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
371 resets = <&cpg 910>; 373 resets = <&cpg 910>;
372 }; 374 };
373 375
374 gpio3: gpio@e6053000 { 376 gpio3: gpio@e6053000 {
375 compatible = "renesas, 377 compatible = "renesas,gpio-r8a7796",
376 "renesas, 378 "renesas,rcar-gen3-gpio";
377 reg = <0 0xe6053000 0 379 reg = <0 0xe6053000 0 0x50>;
378 interrupts = <GIC_SPI 380 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
379 #gpio-cells = <2>; 381 #gpio-cells = <2>;
380 gpio-controller; 382 gpio-controller;
381 gpio-ranges = <&pfc 0 383 gpio-ranges = <&pfc 0 96 16>;
382 #interrupt-cells = <2> 384 #interrupt-cells = <2>;
383 interrupt-controller; 385 interrupt-controller;
384 clocks = <&cpg CPG_MOD 386 clocks = <&cpg CPG_MOD 909>;
385 power-domains = <&sysc 387 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
386 resets = <&cpg 909>; 388 resets = <&cpg 909>;
387 }; 389 };
388 390
389 gpio4: gpio@e6054000 { 391 gpio4: gpio@e6054000 {
390 compatible = "renesas, 392 compatible = "renesas,gpio-r8a7796",
391 "renesas, 393 "renesas,rcar-gen3-gpio";
392 reg = <0 0xe6054000 0 394 reg = <0 0xe6054000 0 0x50>;
393 interrupts = <GIC_SPI 395 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
394 #gpio-cells = <2>; 396 #gpio-cells = <2>;
395 gpio-controller; 397 gpio-controller;
396 gpio-ranges = <&pfc 0 398 gpio-ranges = <&pfc 0 128 18>;
397 #interrupt-cells = <2> 399 #interrupt-cells = <2>;
398 interrupt-controller; 400 interrupt-controller;
399 clocks = <&cpg CPG_MOD 401 clocks = <&cpg CPG_MOD 908>;
400 power-domains = <&sysc 402 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
401 resets = <&cpg 908>; 403 resets = <&cpg 908>;
402 }; 404 };
403 405
404 gpio5: gpio@e6055000 { 406 gpio5: gpio@e6055000 {
405 compatible = "renesas, 407 compatible = "renesas,gpio-r8a7796",
406 "renesas, 408 "renesas,rcar-gen3-gpio";
407 reg = <0 0xe6055000 0 409 reg = <0 0xe6055000 0 0x50>;
408 interrupts = <GIC_SPI 410 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
409 #gpio-cells = <2>; 411 #gpio-cells = <2>;
410 gpio-controller; 412 gpio-controller;
411 gpio-ranges = <&pfc 0 413 gpio-ranges = <&pfc 0 160 26>;
412 #interrupt-cells = <2> 414 #interrupt-cells = <2>;
413 interrupt-controller; 415 interrupt-controller;
414 clocks = <&cpg CPG_MOD 416 clocks = <&cpg CPG_MOD 907>;
415 power-domains = <&sysc 417 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
416 resets = <&cpg 907>; 418 resets = <&cpg 907>;
417 }; 419 };
418 420
419 gpio6: gpio@e6055400 { 421 gpio6: gpio@e6055400 {
420 compatible = "renesas, 422 compatible = "renesas,gpio-r8a7796",
421 "renesas, 423 "renesas,rcar-gen3-gpio";
422 reg = <0 0xe6055400 0 424 reg = <0 0xe6055400 0 0x50>;
423 interrupts = <GIC_SPI 425 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
424 #gpio-cells = <2>; 426 #gpio-cells = <2>;
425 gpio-controller; 427 gpio-controller;
426 gpio-ranges = <&pfc 0 428 gpio-ranges = <&pfc 0 192 32>;
427 #interrupt-cells = <2> 429 #interrupt-cells = <2>;
428 interrupt-controller; 430 interrupt-controller;
429 clocks = <&cpg CPG_MOD 431 clocks = <&cpg CPG_MOD 906>;
430 power-domains = <&sysc 432 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
431 resets = <&cpg 906>; 433 resets = <&cpg 906>;
432 }; 434 };
433 435
434 gpio7: gpio@e6055800 { 436 gpio7: gpio@e6055800 {
435 compatible = "renesas, 437 compatible = "renesas,gpio-r8a7796",
436 "renesas, 438 "renesas,rcar-gen3-gpio";
437 reg = <0 0xe6055800 0 439 reg = <0 0xe6055800 0 0x50>;
438 interrupts = <GIC_SPI 440 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
439 #gpio-cells = <2>; 441 #gpio-cells = <2>;
440 gpio-controller; 442 gpio-controller;
441 gpio-ranges = <&pfc 0 443 gpio-ranges = <&pfc 0 224 4>;
442 #interrupt-cells = <2> 444 #interrupt-cells = <2>;
443 interrupt-controller; 445 interrupt-controller;
444 clocks = <&cpg CPG_MOD 446 clocks = <&cpg CPG_MOD 905>;
445 power-domains = <&sysc 447 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
446 resets = <&cpg 905>; 448 resets = <&cpg 905>;
447 }; 449 };
448 450
449 pfc: pinctrl@e6060000 { 451 pfc: pinctrl@e6060000 {
450 compatible = "renesas, 452 compatible = "renesas,pfc-r8a7796";
451 reg = <0 0xe6060000 0 453 reg = <0 0xe6060000 0 0x50c>;
452 }; 454 };
453 455
454 cmt0: timer@e60f0000 { 456 cmt0: timer@e60f0000 {
455 compatible = "renesas, 457 compatible = "renesas,r8a7796-cmt0",
456 "renesas, 458 "renesas,rcar-gen3-cmt0";
457 reg = <0 0xe60f0000 0 459 reg = <0 0xe60f0000 0 0x1004>;
458 interrupts = <GIC_SPI 460 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
459 <GIC_SPI 461 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
460 clocks = <&cpg CPG_MOD 462 clocks = <&cpg CPG_MOD 303>;
461 clock-names = "fck"; 463 clock-names = "fck";
462 power-domains = <&sysc 464 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
463 resets = <&cpg 303>; 465 resets = <&cpg 303>;
464 status = "disabled"; 466 status = "disabled";
465 }; 467 };
466 468
467 cmt1: timer@e6130000 { 469 cmt1: timer@e6130000 {
468 compatible = "renesas, 470 compatible = "renesas,r8a7796-cmt1",
469 "renesas, 471 "renesas,rcar-gen3-cmt1";
470 reg = <0 0xe6130000 0 472 reg = <0 0xe6130000 0 0x1004>;
471 interrupts = <GIC_SPI 473 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
472 <GIC_SPI 474 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
473 <GIC_SPI 475 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
474 <GIC_SPI 476 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
475 <GIC_SPI 477 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
476 <GIC_SPI 478 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
477 <GIC_SPI 479 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
478 <GIC_SPI 480 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
479 clocks = <&cpg CPG_MOD 481 clocks = <&cpg CPG_MOD 302>;
480 clock-names = "fck"; 482 clock-names = "fck";
481 power-domains = <&sysc 483 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
482 resets = <&cpg 302>; 484 resets = <&cpg 302>;
483 status = "disabled"; 485 status = "disabled";
484 }; 486 };
485 487
486 cmt2: timer@e6140000 { 488 cmt2: timer@e6140000 {
487 compatible = "renesas, 489 compatible = "renesas,r8a7796-cmt1",
488 "renesas, 490 "renesas,rcar-gen3-cmt1";
489 reg = <0 0xe6140000 0 491 reg = <0 0xe6140000 0 0x1004>;
490 interrupts = <GIC_SPI 492 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
491 <GIC_SPI 493 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
492 <GIC_SPI 494 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
493 <GIC_SPI 495 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
494 <GIC_SPI 496 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
495 <GIC_SPI 497 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
496 <GIC_SPI 498 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
497 <GIC_SPI 499 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
498 clocks = <&cpg CPG_MOD 500 clocks = <&cpg CPG_MOD 301>;
499 clock-names = "fck"; 501 clock-names = "fck";
500 power-domains = <&sysc 502 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
501 resets = <&cpg 301>; 503 resets = <&cpg 301>;
502 status = "disabled"; 504 status = "disabled";
503 }; 505 };
504 506
505 cmt3: timer@e6148000 { 507 cmt3: timer@e6148000 {
506 compatible = "renesas, 508 compatible = "renesas,r8a7796-cmt1",
507 "renesas, 509 "renesas,rcar-gen3-cmt1";
508 reg = <0 0xe6148000 0 510 reg = <0 0xe6148000 0 0x1004>;
509 interrupts = <GIC_SPI 511 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
510 <GIC_SPI 512 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
511 <GIC_SPI 513 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
512 <GIC_SPI 514 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
513 <GIC_SPI 515 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
514 <GIC_SPI 516 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
515 <GIC_SPI 517 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
516 <GIC_SPI 518 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
517 clocks = <&cpg CPG_MOD 519 clocks = <&cpg CPG_MOD 300>;
518 clock-names = "fck"; 520 clock-names = "fck";
519 power-domains = <&sysc 521 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
520 resets = <&cpg 300>; 522 resets = <&cpg 300>;
521 status = "disabled"; 523 status = "disabled";
522 }; 524 };
523 525
524 cpg: clock-controller@e6150000 526 cpg: clock-controller@e6150000 {
525 compatible = "renesas, 527 compatible = "renesas,r8a7796-cpg-mssr";
526 reg = <0 0xe6150000 0 528 reg = <0 0xe6150000 0 0x1000>;
527 clocks = <&extal_clk>, 529 clocks = <&extal_clk>, <&extalr_clk>;
528 clock-names = "extal", 530 clock-names = "extal", "extalr";
529 #clock-cells = <2>; 531 #clock-cells = <2>;
530 #power-domain-cells = 532 #power-domain-cells = <0>;
531 #reset-cells = <1>; 533 #reset-cells = <1>;
532 }; 534 };
533 535
534 rst: reset-controller@e6160000 536 rst: reset-controller@e6160000 {
535 compatible = "renesas, 537 compatible = "renesas,r8a7796-rst";
536 reg = <0 0xe6160000 0 538 reg = <0 0xe6160000 0 0x0200>;
537 }; 539 };
538 540
539 sysc: system-controller@e61800 541 sysc: system-controller@e6180000 {
540 compatible = "renesas, 542 compatible = "renesas,r8a7796-sysc";
541 reg = <0 0xe6180000 0 543 reg = <0 0xe6180000 0 0x0400>;
542 #power-domain-cells = 544 #power-domain-cells = <1>;
543 }; 545 };
544 546
545 tsc: thermal@e6198000 { 547 tsc: thermal@e6198000 {
546 compatible = "renesas, 548 compatible = "renesas,r8a7796-thermal";
547 reg = <0 0xe6198000 0 549 reg = <0 0xe6198000 0 0x100>,
548 <0 0xe61a0000 0 550 <0 0xe61a0000 0 0x100>,
549 <0 0xe61a8000 0 551 <0 0xe61a8000 0 0x100>;
550 interrupts = <GIC_SPI 552 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
551 <GIC_SPI 553 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
552 <GIC_SPI 554 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
553 clocks = <&cpg CPG_MOD 555 clocks = <&cpg CPG_MOD 522>;
554 power-domains = <&sysc 556 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
555 resets = <&cpg 522>; 557 resets = <&cpg 522>;
556 #thermal-sensor-cells 558 #thermal-sensor-cells = <1>;
557 }; 559 };
558 560
559 intc_ex: interrupt-controller@ 561 intc_ex: interrupt-controller@e61c0000 {
560 compatible = "renesas, 562 compatible = "renesas,intc-ex-r8a7796", "renesas,irqc";
561 #interrupt-cells = <2> 563 #interrupt-cells = <2>;
562 interrupt-controller; 564 interrupt-controller;
563 reg = <0 0xe61c0000 0 565 reg = <0 0xe61c0000 0 0x200>;
564 interrupts = <GIC_SPI 566 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
565 <GIC_SPI 567 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
566 <GIC_SPI 568 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
567 <GIC_SPI 569 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
568 <GIC_SPI 570 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
569 <GIC_SPI 571 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
570 clocks = <&cpg CPG_MOD 572 clocks = <&cpg CPG_MOD 407>;
571 power-domains = <&sysc 573 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
572 resets = <&cpg 407>; 574 resets = <&cpg 407>;
573 }; 575 };
574 576
575 tmu0: timer@e61e0000 { 577 tmu0: timer@e61e0000 {
576 compatible = "renesas, 578 compatible = "renesas,tmu-r8a7796", "renesas,tmu";
577 reg = <0 0xe61e0000 0 579 reg = <0 0xe61e0000 0 0x30>;
578 interrupts = <GIC_SPI 580 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
579 <GIC_SPI 581 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
580 <GIC_SPI 582 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
581 interrupt-names = "tun <<
582 clocks = <&cpg CPG_MOD 583 clocks = <&cpg CPG_MOD 125>;
583 clock-names = "fck"; 584 clock-names = "fck";
584 power-domains = <&sysc 585 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
585 resets = <&cpg 125>; 586 resets = <&cpg 125>;
586 status = "disabled"; 587 status = "disabled";
587 }; 588 };
588 589
589 tmu1: timer@e6fc0000 { 590 tmu1: timer@e6fc0000 {
590 compatible = "renesas, 591 compatible = "renesas,tmu-r8a7796", "renesas,tmu";
591 reg = <0 0xe6fc0000 0 592 reg = <0 0xe6fc0000 0 0x30>;
592 interrupts = <GIC_SPI 593 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
593 <GIC_SPI 594 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
594 <GIC_SPI !! 595 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
595 <GIC_SPI <<
596 interrupt-names = "tun <<
597 clocks = <&cpg CPG_MOD 596 clocks = <&cpg CPG_MOD 124>;
598 clock-names = "fck"; 597 clock-names = "fck";
599 power-domains = <&sysc 598 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
600 resets = <&cpg 124>; 599 resets = <&cpg 124>;
601 status = "disabled"; 600 status = "disabled";
602 }; 601 };
603 602
604 tmu2: timer@e6fd0000 { 603 tmu2: timer@e6fd0000 {
605 compatible = "renesas, 604 compatible = "renesas,tmu-r8a7796", "renesas,tmu";
606 reg = <0 0xe6fd0000 0 605 reg = <0 0xe6fd0000 0 0x30>;
607 interrupts = <GIC_SPI 606 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
608 <GIC_SPI 607 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
609 <GIC_SPI !! 608 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
610 <GIC_SPI <<
611 interrupt-names = "tun <<
612 clocks = <&cpg CPG_MOD 609 clocks = <&cpg CPG_MOD 123>;
613 clock-names = "fck"; 610 clock-names = "fck";
614 power-domains = <&sysc 611 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
615 resets = <&cpg 123>; 612 resets = <&cpg 123>;
616 status = "disabled"; 613 status = "disabled";
617 }; 614 };
618 615
619 tmu3: timer@e6fe0000 { 616 tmu3: timer@e6fe0000 {
620 compatible = "renesas, 617 compatible = "renesas,tmu-r8a7796", "renesas,tmu";
621 reg = <0 0xe6fe0000 0 618 reg = <0 0xe6fe0000 0 0x30>;
622 interrupts = <GIC_SPI 619 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
623 <GIC_SPI 620 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
624 <GIC_SPI 621 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
625 interrupt-names = "tun <<
626 clocks = <&cpg CPG_MOD 622 clocks = <&cpg CPG_MOD 122>;
627 clock-names = "fck"; 623 clock-names = "fck";
628 power-domains = <&sysc 624 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
629 resets = <&cpg 122>; 625 resets = <&cpg 122>;
630 status = "disabled"; 626 status = "disabled";
631 }; 627 };
632 628
633 tmu4: timer@ffc00000 { 629 tmu4: timer@ffc00000 {
634 compatible = "renesas, 630 compatible = "renesas,tmu-r8a7796", "renesas,tmu";
635 reg = <0 0xffc00000 0 631 reg = <0 0xffc00000 0 0x30>;
636 interrupts = <GIC_SPI 632 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
637 <GIC_SPI 633 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
638 <GIC_SPI 634 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
639 interrupt-names = "tun <<
640 clocks = <&cpg CPG_MOD 635 clocks = <&cpg CPG_MOD 121>;
641 clock-names = "fck"; 636 clock-names = "fck";
642 power-domains = <&sysc 637 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
643 resets = <&cpg 121>; 638 resets = <&cpg 121>;
644 status = "disabled"; 639 status = "disabled";
645 }; 640 };
646 641
647 i2c0: i2c@e6500000 { 642 i2c0: i2c@e6500000 {
648 #address-cells = <1>; 643 #address-cells = <1>;
649 #size-cells = <0>; 644 #size-cells = <0>;
650 compatible = "renesas, 645 compatible = "renesas,i2c-r8a7796",
651 "renesas, 646 "renesas,rcar-gen3-i2c";
652 reg = <0 0xe6500000 0 647 reg = <0 0xe6500000 0 0x40>;
653 interrupts = <GIC_SPI 648 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
654 clocks = <&cpg CPG_MOD 649 clocks = <&cpg CPG_MOD 931>;
655 power-domains = <&sysc 650 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
656 resets = <&cpg 931>; 651 resets = <&cpg 931>;
657 dmas = <&dmac1 0x91>, 652 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
658 <&dmac2 0x91>, 653 <&dmac2 0x91>, <&dmac2 0x90>;
659 dma-names = "tx", "rx" 654 dma-names = "tx", "rx", "tx", "rx";
660 i2c-scl-internal-delay 655 i2c-scl-internal-delay-ns = <110>;
661 status = "disabled"; 656 status = "disabled";
662 }; 657 };
663 658
664 i2c1: i2c@e6508000 { 659 i2c1: i2c@e6508000 {
665 #address-cells = <1>; 660 #address-cells = <1>;
666 #size-cells = <0>; 661 #size-cells = <0>;
667 compatible = "renesas, 662 compatible = "renesas,i2c-r8a7796",
668 "renesas, 663 "renesas,rcar-gen3-i2c";
669 reg = <0 0xe6508000 0 664 reg = <0 0xe6508000 0 0x40>;
670 interrupts = <GIC_SPI 665 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
671 clocks = <&cpg CPG_MOD 666 clocks = <&cpg CPG_MOD 930>;
672 power-domains = <&sysc 667 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
673 resets = <&cpg 930>; 668 resets = <&cpg 930>;
674 dmas = <&dmac1 0x93>, 669 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
675 <&dmac2 0x93>, 670 <&dmac2 0x93>, <&dmac2 0x92>;
676 dma-names = "tx", "rx" 671 dma-names = "tx", "rx", "tx", "rx";
677 i2c-scl-internal-delay 672 i2c-scl-internal-delay-ns = <6>;
678 status = "disabled"; 673 status = "disabled";
679 }; 674 };
680 675
681 i2c2: i2c@e6510000 { 676 i2c2: i2c@e6510000 {
682 #address-cells = <1>; 677 #address-cells = <1>;
683 #size-cells = <0>; 678 #size-cells = <0>;
684 compatible = "renesas, 679 compatible = "renesas,i2c-r8a7796",
685 "renesas, 680 "renesas,rcar-gen3-i2c";
686 reg = <0 0xe6510000 0 681 reg = <0 0xe6510000 0 0x40>;
687 interrupts = <GIC_SPI 682 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
688 clocks = <&cpg CPG_MOD 683 clocks = <&cpg CPG_MOD 929>;
689 power-domains = <&sysc 684 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
690 resets = <&cpg 929>; 685 resets = <&cpg 929>;
691 dmas = <&dmac1 0x95>, 686 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
692 <&dmac2 0x95>, 687 <&dmac2 0x95>, <&dmac2 0x94>;
693 dma-names = "tx", "rx" 688 dma-names = "tx", "rx", "tx", "rx";
694 i2c-scl-internal-delay 689 i2c-scl-internal-delay-ns = <6>;
695 status = "disabled"; 690 status = "disabled";
696 }; 691 };
697 692
698 i2c3: i2c@e66d0000 { 693 i2c3: i2c@e66d0000 {
699 #address-cells = <1>; 694 #address-cells = <1>;
700 #size-cells = <0>; 695 #size-cells = <0>;
701 compatible = "renesas, 696 compatible = "renesas,i2c-r8a7796",
702 "renesas, 697 "renesas,rcar-gen3-i2c";
703 reg = <0 0xe66d0000 0 698 reg = <0 0xe66d0000 0 0x40>;
704 interrupts = <GIC_SPI 699 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
705 clocks = <&cpg CPG_MOD 700 clocks = <&cpg CPG_MOD 928>;
706 power-domains = <&sysc 701 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
707 resets = <&cpg 928>; 702 resets = <&cpg 928>;
708 dmas = <&dmac0 0x97>, 703 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
709 dma-names = "tx", "rx" 704 dma-names = "tx", "rx";
710 i2c-scl-internal-delay 705 i2c-scl-internal-delay-ns = <110>;
711 status = "disabled"; 706 status = "disabled";
712 }; 707 };
713 708
714 i2c4: i2c@e66d8000 { 709 i2c4: i2c@e66d8000 {
715 #address-cells = <1>; 710 #address-cells = <1>;
716 #size-cells = <0>; 711 #size-cells = <0>;
717 compatible = "renesas, 712 compatible = "renesas,i2c-r8a7796",
718 "renesas, 713 "renesas,rcar-gen3-i2c";
719 reg = <0 0xe66d8000 0 714 reg = <0 0xe66d8000 0 0x40>;
720 interrupts = <GIC_SPI 715 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
721 clocks = <&cpg CPG_MOD 716 clocks = <&cpg CPG_MOD 927>;
722 power-domains = <&sysc 717 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
723 resets = <&cpg 927>; 718 resets = <&cpg 927>;
724 dmas = <&dmac0 0x99>, 719 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
725 dma-names = "tx", "rx" 720 dma-names = "tx", "rx";
726 i2c-scl-internal-delay 721 i2c-scl-internal-delay-ns = <110>;
727 status = "disabled"; 722 status = "disabled";
728 }; 723 };
729 724
730 i2c5: i2c@e66e0000 { 725 i2c5: i2c@e66e0000 {
731 #address-cells = <1>; 726 #address-cells = <1>;
732 #size-cells = <0>; 727 #size-cells = <0>;
733 compatible = "renesas, 728 compatible = "renesas,i2c-r8a7796",
734 "renesas, 729 "renesas,rcar-gen3-i2c";
735 reg = <0 0xe66e0000 0 730 reg = <0 0xe66e0000 0 0x40>;
736 interrupts = <GIC_SPI 731 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
737 clocks = <&cpg CPG_MOD 732 clocks = <&cpg CPG_MOD 919>;
738 power-domains = <&sysc 733 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
739 resets = <&cpg 919>; 734 resets = <&cpg 919>;
740 dmas = <&dmac0 0x9b>, 735 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
741 dma-names = "tx", "rx" 736 dma-names = "tx", "rx";
742 i2c-scl-internal-delay 737 i2c-scl-internal-delay-ns = <110>;
743 status = "disabled"; 738 status = "disabled";
744 }; 739 };
745 740
746 i2c6: i2c@e66e8000 { 741 i2c6: i2c@e66e8000 {
747 #address-cells = <1>; 742 #address-cells = <1>;
748 #size-cells = <0>; 743 #size-cells = <0>;
749 compatible = "renesas, 744 compatible = "renesas,i2c-r8a7796",
750 "renesas, 745 "renesas,rcar-gen3-i2c";
751 reg = <0 0xe66e8000 0 746 reg = <0 0xe66e8000 0 0x40>;
752 interrupts = <GIC_SPI 747 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
753 clocks = <&cpg CPG_MOD 748 clocks = <&cpg CPG_MOD 918>;
754 power-domains = <&sysc 749 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
755 resets = <&cpg 918>; 750 resets = <&cpg 918>;
756 dmas = <&dmac0 0x9d>, 751 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
757 dma-names = "tx", "rx" 752 dma-names = "tx", "rx";
758 i2c-scl-internal-delay 753 i2c-scl-internal-delay-ns = <6>;
759 status = "disabled"; 754 status = "disabled";
760 }; 755 };
761 756
762 i2c_dvfs: i2c@e60b0000 { 757 i2c_dvfs: i2c@e60b0000 {
763 #address-cells = <1>; 758 #address-cells = <1>;
764 #size-cells = <0>; 759 #size-cells = <0>;
765 compatible = "renesas, 760 compatible = "renesas,iic-r8a7796",
766 "renesas, 761 "renesas,rcar-gen3-iic",
767 "renesas, 762 "renesas,rmobile-iic";
768 reg = <0 0xe60b0000 0 763 reg = <0 0xe60b0000 0 0x425>;
769 interrupts = <GIC_SPI 764 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
770 clocks = <&cpg CPG_MOD 765 clocks = <&cpg CPG_MOD 926>;
771 power-domains = <&sysc 766 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
772 resets = <&cpg 926>; 767 resets = <&cpg 926>;
773 dmas = <&dmac0 0x11>, 768 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
774 dma-names = "tx", "rx" 769 dma-names = "tx", "rx";
775 status = "disabled"; 770 status = "disabled";
776 }; 771 };
777 772
778 hscif0: serial@e6540000 { 773 hscif0: serial@e6540000 {
779 compatible = "renesas, 774 compatible = "renesas,hscif-r8a7796",
780 "renesas, 775 "renesas,rcar-gen3-hscif",
781 "renesas, 776 "renesas,hscif";
782 reg = <0 0xe6540000 0 777 reg = <0 0xe6540000 0 0x60>;
783 interrupts = <GIC_SPI 778 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
784 clocks = <&cpg CPG_MOD 779 clocks = <&cpg CPG_MOD 520>,
785 <&cpg CPG_COR 780 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
786 <&scif_clk>; 781 <&scif_clk>;
787 clock-names = "fck", " 782 clock-names = "fck", "brg_int", "scif_clk";
788 dmas = <&dmac1 0x31>, 783 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
789 <&dmac2 0x31>, 784 <&dmac2 0x31>, <&dmac2 0x30>;
790 dma-names = "tx", "rx" 785 dma-names = "tx", "rx", "tx", "rx";
791 power-domains = <&sysc 786 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
792 resets = <&cpg 520>; 787 resets = <&cpg 520>;
793 status = "disabled"; 788 status = "disabled";
794 }; 789 };
795 790
796 hscif1: serial@e6550000 { 791 hscif1: serial@e6550000 {
797 compatible = "renesas, 792 compatible = "renesas,hscif-r8a7796",
798 "renesas, 793 "renesas,rcar-gen3-hscif",
799 "renesas, 794 "renesas,hscif";
800 reg = <0 0xe6550000 0 795 reg = <0 0xe6550000 0 0x60>;
801 interrupts = <GIC_SPI 796 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
802 clocks = <&cpg CPG_MOD 797 clocks = <&cpg CPG_MOD 519>,
803 <&cpg CPG_COR 798 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
804 <&scif_clk>; 799 <&scif_clk>;
805 clock-names = "fck", " 800 clock-names = "fck", "brg_int", "scif_clk";
806 dmas = <&dmac1 0x33>, 801 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
807 <&dmac2 0x33>, 802 <&dmac2 0x33>, <&dmac2 0x32>;
808 dma-names = "tx", "rx" 803 dma-names = "tx", "rx", "tx", "rx";
809 power-domains = <&sysc 804 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
810 resets = <&cpg 519>; 805 resets = <&cpg 519>;
811 status = "disabled"; 806 status = "disabled";
812 }; 807 };
813 808
814 hscif2: serial@e6560000 { 809 hscif2: serial@e6560000 {
815 compatible = "renesas, 810 compatible = "renesas,hscif-r8a7796",
816 "renesas, 811 "renesas,rcar-gen3-hscif",
817 "renesas, 812 "renesas,hscif";
818 reg = <0 0xe6560000 0 813 reg = <0 0xe6560000 0 0x60>;
819 interrupts = <GIC_SPI 814 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
820 clocks = <&cpg CPG_MOD 815 clocks = <&cpg CPG_MOD 518>,
821 <&cpg CPG_COR 816 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
822 <&scif_clk>; 817 <&scif_clk>;
823 clock-names = "fck", " 818 clock-names = "fck", "brg_int", "scif_clk";
824 dmas = <&dmac1 0x35>, 819 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
825 <&dmac2 0x35>, 820 <&dmac2 0x35>, <&dmac2 0x34>;
826 dma-names = "tx", "rx" 821 dma-names = "tx", "rx", "tx", "rx";
827 power-domains = <&sysc 822 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
828 resets = <&cpg 518>; 823 resets = <&cpg 518>;
829 status = "disabled"; 824 status = "disabled";
830 }; 825 };
831 826
832 hscif3: serial@e66a0000 { 827 hscif3: serial@e66a0000 {
833 compatible = "renesas, 828 compatible = "renesas,hscif-r8a7796",
834 "renesas, 829 "renesas,rcar-gen3-hscif",
835 "renesas, 830 "renesas,hscif";
836 reg = <0 0xe66a0000 0 831 reg = <0 0xe66a0000 0 0x60>;
837 interrupts = <GIC_SPI 832 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
838 clocks = <&cpg CPG_MOD 833 clocks = <&cpg CPG_MOD 517>,
839 <&cpg CPG_COR 834 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
840 <&scif_clk>; 835 <&scif_clk>;
841 clock-names = "fck", " 836 clock-names = "fck", "brg_int", "scif_clk";
842 dmas = <&dmac0 0x37>, 837 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
843 dma-names = "tx", "rx" 838 dma-names = "tx", "rx";
844 power-domains = <&sysc 839 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
845 resets = <&cpg 517>; 840 resets = <&cpg 517>;
846 status = "disabled"; 841 status = "disabled";
847 }; 842 };
848 843
849 hscif4: serial@e66b0000 { 844 hscif4: serial@e66b0000 {
850 compatible = "renesas, 845 compatible = "renesas,hscif-r8a7796",
851 "renesas, 846 "renesas,rcar-gen3-hscif",
852 "renesas, 847 "renesas,hscif";
853 reg = <0 0xe66b0000 0 848 reg = <0 0xe66b0000 0 0x60>;
854 interrupts = <GIC_SPI 849 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
855 clocks = <&cpg CPG_MOD 850 clocks = <&cpg CPG_MOD 516>,
856 <&cpg CPG_COR 851 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
857 <&scif_clk>; 852 <&scif_clk>;
858 clock-names = "fck", " 853 clock-names = "fck", "brg_int", "scif_clk";
859 dmas = <&dmac0 0x39>, 854 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
860 dma-names = "tx", "rx" 855 dma-names = "tx", "rx";
861 power-domains = <&sysc 856 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
862 resets = <&cpg 516>; 857 resets = <&cpg 516>;
863 status = "disabled"; 858 status = "disabled";
864 }; 859 };
865 860
866 hsusb: usb@e6590000 { 861 hsusb: usb@e6590000 {
867 compatible = "renesas, 862 compatible = "renesas,usbhs-r8a7796",
868 "renesas, 863 "renesas,rcar-gen3-usbhs";
869 reg = <0 0xe6590000 0 864 reg = <0 0xe6590000 0 0x200>;
870 interrupts = <GIC_SPI 865 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
871 clocks = <&cpg CPG_MOD 866 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
872 dmas = <&usb_dmac0 0>, 867 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
873 <&usb_dmac1 0>, 868 <&usb_dmac1 0>, <&usb_dmac1 1>;
874 dma-names = "ch0", "ch 869 dma-names = "ch0", "ch1", "ch2", "ch3";
875 renesas,buswait = <11> 870 renesas,buswait = <11>;
876 phys = <&usb2_phy0 3>; 871 phys = <&usb2_phy0 3>;
877 phy-names = "usb"; 872 phy-names = "usb";
878 power-domains = <&sysc 873 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
879 resets = <&cpg 704>, < 874 resets = <&cpg 704>, <&cpg 703>;
880 status = "disabled"; 875 status = "disabled";
881 }; 876 };
882 877
883 usb_dmac0: dma-controller@e65a 878 usb_dmac0: dma-controller@e65a0000 {
884 compatible = "renesas, 879 compatible = "renesas,r8a7796-usb-dmac",
885 "renesas, 880 "renesas,usb-dmac";
886 reg = <0 0xe65a0000 0 881 reg = <0 0xe65a0000 0 0x100>;
887 interrupts = <GIC_SPI 882 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
888 <GIC_SPI 883 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
889 interrupt-names = "ch0 884 interrupt-names = "ch0", "ch1";
890 clocks = <&cpg CPG_MOD 885 clocks = <&cpg CPG_MOD 330>;
891 power-domains = <&sysc 886 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
892 resets = <&cpg 330>; 887 resets = <&cpg 330>;
893 #dma-cells = <1>; 888 #dma-cells = <1>;
894 dma-channels = <2>; 889 dma-channels = <2>;
895 }; 890 };
896 891
897 usb_dmac1: dma-controller@e65b 892 usb_dmac1: dma-controller@e65b0000 {
898 compatible = "renesas, 893 compatible = "renesas,r8a7796-usb-dmac",
899 "renesas, 894 "renesas,usb-dmac";
900 reg = <0 0xe65b0000 0 895 reg = <0 0xe65b0000 0 0x100>;
901 interrupts = <GIC_SPI 896 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
902 <GIC_SPI 897 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
903 interrupt-names = "ch0 898 interrupt-names = "ch0", "ch1";
904 clocks = <&cpg CPG_MOD 899 clocks = <&cpg CPG_MOD 331>;
905 power-domains = <&sysc 900 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
906 resets = <&cpg 331>; 901 resets = <&cpg 331>;
907 #dma-cells = <1>; 902 #dma-cells = <1>;
908 dma-channels = <2>; 903 dma-channels = <2>;
909 }; 904 };
910 905
911 usb3_phy0: usb-phy@e65ee000 { 906 usb3_phy0: usb-phy@e65ee000 {
912 compatible = "renesas, 907 compatible = "renesas,r8a7796-usb3-phy",
913 "renesas, 908 "renesas,rcar-gen3-usb3-phy";
914 reg = <0 0xe65ee000 0 909 reg = <0 0xe65ee000 0 0x90>;
915 clocks = <&cpg CPG_MOD 910 clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>,
916 <&usb_extal_c 911 <&usb_extal_clk>;
917 clock-names = "usb3-if 912 clock-names = "usb3-if", "usb3s_clk", "usb_extal";
918 power-domains = <&sysc 913 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
919 resets = <&cpg 328>; 914 resets = <&cpg 328>;
920 #phy-cells = <0>; 915 #phy-cells = <0>;
921 status = "disabled"; 916 status = "disabled";
922 }; 917 };
923 918
924 arm_cc630p: crypto@e6601000 { 919 arm_cc630p: crypto@e6601000 {
925 compatible = "arm,cryp 920 compatible = "arm,cryptocell-630p-ree";
926 interrupts = <GIC_SPI 921 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
927 reg = <0x0 0xe6601000 922 reg = <0x0 0xe6601000 0 0x1000>;
928 clocks = <&cpg CPG_MOD 923 clocks = <&cpg CPG_MOD 229>;
929 resets = <&cpg 229>; 924 resets = <&cpg 229>;
930 power-domains = <&sysc 925 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
931 }; 926 };
932 927
933 dmac0: dma-controller@e6700000 928 dmac0: dma-controller@e6700000 {
934 compatible = "renesas, 929 compatible = "renesas,dmac-r8a7796",
935 "renesas, 930 "renesas,rcar-dmac";
936 reg = <0 0xe6700000 0 931 reg = <0 0xe6700000 0 0x10000>;
937 interrupts = <GIC_SPI 932 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
938 <GIC_SPI 933 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
939 <GIC_SPI 934 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
940 <GIC_SPI 935 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
941 <GIC_SPI 936 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
942 <GIC_SPI 937 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
943 <GIC_SPI 938 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
944 <GIC_SPI 939 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
945 <GIC_SPI 940 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
946 <GIC_SPI 941 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
947 <GIC_SPI 942 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
948 <GIC_SPI 943 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
949 <GIC_SPI 944 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
950 <GIC_SPI 945 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
951 <GIC_SPI 946 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
952 <GIC_SPI 947 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
953 <GIC_SPI 948 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
954 interrupt-names = "err 949 interrupt-names = "error",
955 "ch0", 950 "ch0", "ch1", "ch2", "ch3",
956 "ch4", 951 "ch4", "ch5", "ch6", "ch7",
957 "ch8", 952 "ch8", "ch9", "ch10", "ch11",
958 "ch12" 953 "ch12", "ch13", "ch14", "ch15";
959 clocks = <&cpg CPG_MOD 954 clocks = <&cpg CPG_MOD 219>;
960 clock-names = "fck"; 955 clock-names = "fck";
961 power-domains = <&sysc 956 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
962 resets = <&cpg 219>; 957 resets = <&cpg 219>;
963 #dma-cells = <1>; 958 #dma-cells = <1>;
964 dma-channels = <16>; 959 dma-channels = <16>;
965 iommus = <&ipmmu_ds0 0 960 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
966 <&ipmmu_ds0 2>, 961 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
967 <&ipmmu_ds0 4>, 962 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
968 <&ipmmu_ds0 6>, 963 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
969 <&ipmmu_ds0 8>, 964 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
970 <&ipmmu_ds0 10> 965 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
971 <&ipmmu_ds0 12> 966 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
972 <&ipmmu_ds0 14> 967 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
973 }; 968 };
974 969
975 dmac1: dma-controller@e7300000 970 dmac1: dma-controller@e7300000 {
976 compatible = "renesas, 971 compatible = "renesas,dmac-r8a7796",
977 "renesas, 972 "renesas,rcar-dmac";
978 reg = <0 0xe7300000 0 973 reg = <0 0xe7300000 0 0x10000>;
979 interrupts = <GIC_SPI 974 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
980 <GIC_SPI 975 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
981 <GIC_SPI 976 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
982 <GIC_SPI 977 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
983 <GIC_SPI 978 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
984 <GIC_SPI 979 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
985 <GIC_SPI 980 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
986 <GIC_SPI 981 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
987 <GIC_SPI 982 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
988 <GIC_SPI 983 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
989 <GIC_SPI 984 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
990 <GIC_SPI 985 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
991 <GIC_SPI 986 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
992 <GIC_SPI 987 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
993 <GIC_SPI 988 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
994 <GIC_SPI 989 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
995 <GIC_SPI 990 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
996 interrupt-names = "err 991 interrupt-names = "error",
997 "ch0", 992 "ch0", "ch1", "ch2", "ch3",
998 "ch4", 993 "ch4", "ch5", "ch6", "ch7",
999 "ch8", 994 "ch8", "ch9", "ch10", "ch11",
1000 "ch12 995 "ch12", "ch13", "ch14", "ch15";
1001 clocks = <&cpg CPG_MO 996 clocks = <&cpg CPG_MOD 218>;
1002 clock-names = "fck"; 997 clock-names = "fck";
1003 power-domains = <&sys 998 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1004 resets = <&cpg 218>; 999 resets = <&cpg 218>;
1005 #dma-cells = <1>; 1000 #dma-cells = <1>;
1006 dma-channels = <16>; 1001 dma-channels = <16>;
1007 iommus = <&ipmmu_ds1 1002 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
1008 <&ipmmu_ds1 2> 1003 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
1009 <&ipmmu_ds1 4> 1004 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
1010 <&ipmmu_ds1 6> 1005 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
1011 <&ipmmu_ds1 8> 1006 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
1012 <&ipmmu_ds1 10 1007 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
1013 <&ipmmu_ds1 12 1008 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
1014 <&ipmmu_ds1 14 1009 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
1015 }; 1010 };
1016 1011
1017 dmac2: dma-controller@e731000 1012 dmac2: dma-controller@e7310000 {
1018 compatible = "renesas 1013 compatible = "renesas,dmac-r8a7796",
1019 "renesas 1014 "renesas,rcar-dmac";
1020 reg = <0 0xe7310000 0 1015 reg = <0 0xe7310000 0 0x10000>;
1021 interrupts = <GIC_SPI 1016 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
1022 <GIC_SPI 1017 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
1023 <GIC_SPI 1018 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
1024 <GIC_SPI 1019 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
1025 <GIC_SPI 1020 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
1026 <GIC_SPI 1021 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
1027 <GIC_SPI 1022 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
1028 <GIC_SPI 1023 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
1029 <GIC_SPI 1024 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
1030 <GIC_SPI 1025 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
1031 <GIC_SPI 1026 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
1032 <GIC_SPI 1027 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
1033 <GIC_SPI 1028 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
1034 <GIC_SPI 1029 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
1035 <GIC_SPI 1030 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
1036 <GIC_SPI 1031 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
1037 <GIC_SPI 1032 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
1038 interrupt-names = "er 1033 interrupt-names = "error",
1039 "ch0" 1034 "ch0", "ch1", "ch2", "ch3",
1040 "ch4" 1035 "ch4", "ch5", "ch6", "ch7",
1041 "ch8" 1036 "ch8", "ch9", "ch10", "ch11",
1042 "ch12 1037 "ch12", "ch13", "ch14", "ch15";
1043 clocks = <&cpg CPG_MO 1038 clocks = <&cpg CPG_MOD 217>;
1044 clock-names = "fck"; 1039 clock-names = "fck";
1045 power-domains = <&sys 1040 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1046 resets = <&cpg 217>; 1041 resets = <&cpg 217>;
1047 #dma-cells = <1>; 1042 #dma-cells = <1>;
1048 dma-channels = <16>; 1043 dma-channels = <16>;
1049 iommus = <&ipmmu_ds1 1044 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
1050 <&ipmmu_ds1 18 1045 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
1051 <&ipmmu_ds1 20 1046 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
1052 <&ipmmu_ds1 22 1047 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
1053 <&ipmmu_ds1 24 1048 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
1054 <&ipmmu_ds1 26 1049 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
1055 <&ipmmu_ds1 28 1050 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
1056 <&ipmmu_ds1 30 1051 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
1057 }; 1052 };
1058 1053
1059 ipmmu_ds0: iommu@e6740000 { 1054 ipmmu_ds0: iommu@e6740000 {
1060 compatible = "renesas 1055 compatible = "renesas,ipmmu-r8a7796";
1061 reg = <0 0xe6740000 0 1056 reg = <0 0xe6740000 0 0x1000>;
1062 renesas,ipmmu-main = 1057 renesas,ipmmu-main = <&ipmmu_mm 0>;
1063 power-domains = <&sys 1058 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1064 #iommu-cells = <1>; 1059 #iommu-cells = <1>;
1065 }; 1060 };
1066 1061
1067 ipmmu_ds1: iommu@e7740000 { 1062 ipmmu_ds1: iommu@e7740000 {
1068 compatible = "renesas 1063 compatible = "renesas,ipmmu-r8a7796";
1069 reg = <0 0xe7740000 0 1064 reg = <0 0xe7740000 0 0x1000>;
1070 renesas,ipmmu-main = 1065 renesas,ipmmu-main = <&ipmmu_mm 1>;
1071 power-domains = <&sys 1066 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1072 #iommu-cells = <1>; 1067 #iommu-cells = <1>;
1073 }; 1068 };
1074 1069
1075 ipmmu_hc: iommu@e6570000 { 1070 ipmmu_hc: iommu@e6570000 {
1076 compatible = "renesas 1071 compatible = "renesas,ipmmu-r8a7796";
1077 reg = <0 0xe6570000 0 1072 reg = <0 0xe6570000 0 0x1000>;
1078 renesas,ipmmu-main = 1073 renesas,ipmmu-main = <&ipmmu_mm 2>;
1079 power-domains = <&sys 1074 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1080 #iommu-cells = <1>; 1075 #iommu-cells = <1>;
1081 }; 1076 };
1082 1077
1083 ipmmu_ir: iommu@ff8b0000 { 1078 ipmmu_ir: iommu@ff8b0000 {
1084 compatible = "renesas 1079 compatible = "renesas,ipmmu-r8a7796";
1085 reg = <0 0xff8b0000 0 1080 reg = <0 0xff8b0000 0 0x1000>;
1086 renesas,ipmmu-main = 1081 renesas,ipmmu-main = <&ipmmu_mm 3>;
1087 power-domains = <&sys 1082 power-domains = <&sysc R8A7796_PD_A3IR>;
1088 #iommu-cells = <1>; 1083 #iommu-cells = <1>;
1089 }; 1084 };
1090 1085
1091 ipmmu_mm: iommu@e67b0000 { 1086 ipmmu_mm: iommu@e67b0000 {
1092 compatible = "renesas 1087 compatible = "renesas,ipmmu-r8a7796";
1093 reg = <0 0xe67b0000 0 1088 reg = <0 0xe67b0000 0 0x1000>;
1094 interrupts = <GIC_SPI 1089 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
1095 <GIC_SPI 1090 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
1096 power-domains = <&sys 1091 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1097 #iommu-cells = <1>; 1092 #iommu-cells = <1>;
1098 }; 1093 };
1099 1094
1100 ipmmu_mp: iommu@ec670000 { 1095 ipmmu_mp: iommu@ec670000 {
1101 compatible = "renesas 1096 compatible = "renesas,ipmmu-r8a7796";
1102 reg = <0 0xec670000 0 1097 reg = <0 0xec670000 0 0x1000>;
1103 renesas,ipmmu-main = 1098 renesas,ipmmu-main = <&ipmmu_mm 4>;
1104 power-domains = <&sys 1099 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1105 #iommu-cells = <1>; 1100 #iommu-cells = <1>;
1106 }; 1101 };
1107 1102
1108 ipmmu_pv0: iommu@fd800000 { 1103 ipmmu_pv0: iommu@fd800000 {
1109 compatible = "renesas 1104 compatible = "renesas,ipmmu-r8a7796";
1110 reg = <0 0xfd800000 0 1105 reg = <0 0xfd800000 0 0x1000>;
1111 renesas,ipmmu-main = 1106 renesas,ipmmu-main = <&ipmmu_mm 5>;
1112 power-domains = <&sys 1107 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1113 #iommu-cells = <1>; 1108 #iommu-cells = <1>;
1114 }; 1109 };
1115 1110
1116 ipmmu_pv1: iommu@fd950000 { 1111 ipmmu_pv1: iommu@fd950000 {
1117 compatible = "renesas 1112 compatible = "renesas,ipmmu-r8a7796";
1118 reg = <0 0xfd950000 0 1113 reg = <0 0xfd950000 0 0x1000>;
1119 renesas,ipmmu-main = 1114 renesas,ipmmu-main = <&ipmmu_mm 6>;
1120 power-domains = <&sys 1115 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1121 #iommu-cells = <1>; 1116 #iommu-cells = <1>;
1122 }; 1117 };
1123 1118
1124 ipmmu_rt: iommu@ffc80000 { 1119 ipmmu_rt: iommu@ffc80000 {
1125 compatible = "renesas 1120 compatible = "renesas,ipmmu-r8a7796";
1126 reg = <0 0xffc80000 0 1121 reg = <0 0xffc80000 0 0x1000>;
1127 renesas,ipmmu-main = 1122 renesas,ipmmu-main = <&ipmmu_mm 7>;
1128 power-domains = <&sys 1123 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1129 #iommu-cells = <1>; 1124 #iommu-cells = <1>;
1130 }; 1125 };
1131 1126
1132 ipmmu_vc0: iommu@fe6b0000 { 1127 ipmmu_vc0: iommu@fe6b0000 {
1133 compatible = "renesas 1128 compatible = "renesas,ipmmu-r8a7796";
1134 reg = <0 0xfe6b0000 0 1129 reg = <0 0xfe6b0000 0 0x1000>;
1135 renesas,ipmmu-main = 1130 renesas,ipmmu-main = <&ipmmu_mm 8>;
1136 power-domains = <&sys 1131 power-domains = <&sysc R8A7796_PD_A3VC>;
1137 #iommu-cells = <1>; 1132 #iommu-cells = <1>;
1138 }; 1133 };
1139 1134
1140 ipmmu_vi0: iommu@febd0000 { 1135 ipmmu_vi0: iommu@febd0000 {
1141 compatible = "renesas 1136 compatible = "renesas,ipmmu-r8a7796";
1142 reg = <0 0xfebd0000 0 1137 reg = <0 0xfebd0000 0 0x1000>;
1143 renesas,ipmmu-main = 1138 renesas,ipmmu-main = <&ipmmu_mm 9>;
1144 power-domains = <&sys 1139 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1145 #iommu-cells = <1>; 1140 #iommu-cells = <1>;
1146 }; 1141 };
1147 1142
1148 avb: ethernet@e6800000 { 1143 avb: ethernet@e6800000 {
1149 compatible = "renesas 1144 compatible = "renesas,etheravb-r8a7796",
1150 "renesas 1145 "renesas,etheravb-rcar-gen3";
1151 reg = <0 0xe6800000 0 1146 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
1152 interrupts = <GIC_SPI 1147 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
1153 <GIC_SPI 1148 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1154 <GIC_SPI 1149 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
1155 <GIC_SPI 1150 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
1156 <GIC_SPI 1151 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
1157 <GIC_SPI 1152 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
1158 <GIC_SPI 1153 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
1159 <GIC_SPI 1154 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
1160 <GIC_SPI 1155 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
1161 <GIC_SPI 1156 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
1162 <GIC_SPI 1157 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
1163 <GIC_SPI 1158 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
1164 <GIC_SPI 1159 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
1165 <GIC_SPI 1160 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
1166 <GIC_SPI 1161 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
1167 <GIC_SPI 1162 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
1168 <GIC_SPI 1163 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
1169 <GIC_SPI 1164 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
1170 <GIC_SPI 1165 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
1171 <GIC_SPI 1166 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
1172 <GIC_SPI 1167 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
1173 <GIC_SPI 1168 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
1174 <GIC_SPI 1169 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
1175 <GIC_SPI 1170 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
1176 <GIC_SPI 1171 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
1177 interrupt-names = "ch 1172 interrupt-names = "ch0", "ch1", "ch2", "ch3",
1178 "ch 1173 "ch4", "ch5", "ch6", "ch7",
1179 "ch 1174 "ch8", "ch9", "ch10", "ch11",
1180 "ch 1175 "ch12", "ch13", "ch14", "ch15",
1181 "ch 1176 "ch16", "ch17", "ch18", "ch19",
1182 "ch 1177 "ch20", "ch21", "ch22", "ch23",
1183 "ch 1178 "ch24";
1184 clocks = <&cpg CPG_MO 1179 clocks = <&cpg CPG_MOD 812>;
1185 clock-names = "fck"; 1180 clock-names = "fck";
1186 power-domains = <&sys 1181 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1187 resets = <&cpg 812>; 1182 resets = <&cpg 812>;
1188 phy-mode = "rgmii"; 1183 phy-mode = "rgmii";
1189 rx-internal-delay-ps 1184 rx-internal-delay-ps = <0>;
1190 tx-internal-delay-ps 1185 tx-internal-delay-ps = <0>;
1191 iommus = <&ipmmu_ds0 1186 iommus = <&ipmmu_ds0 16>;
1192 #address-cells = <1>; 1187 #address-cells = <1>;
1193 #size-cells = <0>; 1188 #size-cells = <0>;
1194 status = "disabled"; 1189 status = "disabled";
1195 }; 1190 };
1196 1191
1197 can0: can@e6c30000 { 1192 can0: can@e6c30000 {
1198 compatible = "renesas 1193 compatible = "renesas,can-r8a7796",
1199 "renesas 1194 "renesas,rcar-gen3-can";
1200 reg = <0 0xe6c30000 0 1195 reg = <0 0xe6c30000 0 0x1000>;
1201 interrupts = <GIC_SPI 1196 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
1202 clocks = <&cpg CPG_MO 1197 clocks = <&cpg CPG_MOD 916>,
1203 <&cpg CPG_CORE 1198 <&cpg CPG_CORE R8A7796_CLK_CANFD>,
1204 <&can_clk>; 1199 <&can_clk>;
1205 clock-names = "clkp1" 1200 clock-names = "clkp1", "clkp2", "can_clk";
1206 assigned-clocks = <&c 1201 assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>;
1207 assigned-clock-rates 1202 assigned-clock-rates = <40000000>;
1208 power-domains = <&sys 1203 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1209 resets = <&cpg 916>; 1204 resets = <&cpg 916>;
1210 status = "disabled"; 1205 status = "disabled";
1211 }; 1206 };
1212 1207
1213 can1: can@e6c38000 { 1208 can1: can@e6c38000 {
1214 compatible = "renesas 1209 compatible = "renesas,can-r8a7796",
1215 "renesas 1210 "renesas,rcar-gen3-can";
1216 reg = <0 0xe6c38000 0 1211 reg = <0 0xe6c38000 0 0x1000>;
1217 interrupts = <GIC_SPI 1212 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
1218 clocks = <&cpg CPG_MO 1213 clocks = <&cpg CPG_MOD 915>,
1219 <&cpg CPG_CORE 1214 <&cpg CPG_CORE R8A7796_CLK_CANFD>,
1220 <&can_clk>; 1215 <&can_clk>;
1221 clock-names = "clkp1" 1216 clock-names = "clkp1", "clkp2", "can_clk";
1222 assigned-clocks = <&c 1217 assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>;
1223 assigned-clock-rates 1218 assigned-clock-rates = <40000000>;
1224 power-domains = <&sys 1219 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1225 resets = <&cpg 915>; 1220 resets = <&cpg 915>;
1226 status = "disabled"; 1221 status = "disabled";
1227 }; 1222 };
1228 1223
1229 canfd: can@e66c0000 { 1224 canfd: can@e66c0000 {
1230 compatible = "renesas 1225 compatible = "renesas,r8a7796-canfd",
1231 "renesas 1226 "renesas,rcar-gen3-canfd";
1232 reg = <0 0xe66c0000 0 1227 reg = <0 0xe66c0000 0 0x8000>;
1233 interrupts = <GIC_SPI 1228 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
1234 <GIC_SPI 3 1229 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1235 interrupt-names = "ch 1230 interrupt-names = "ch_int", "g_int";
1236 clocks = <&cpg CPG_MO 1231 clocks = <&cpg CPG_MOD 914>,
1237 <&cpg CPG_CORE 1232 <&cpg CPG_CORE R8A7796_CLK_CANFD>,
1238 <&can_clk>; 1233 <&can_clk>;
1239 clock-names = "fck", 1234 clock-names = "fck", "canfd", "can_clk";
1240 assigned-clocks = <&c 1235 assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>;
1241 assigned-clock-rates 1236 assigned-clock-rates = <40000000>;
1242 power-domains = <&sys 1237 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1243 resets = <&cpg 914>; 1238 resets = <&cpg 914>;
1244 status = "disabled"; 1239 status = "disabled";
1245 1240
1246 channel0 { 1241 channel0 {
1247 status = "dis 1242 status = "disabled";
1248 }; 1243 };
1249 1244
1250 channel1 { 1245 channel1 {
1251 status = "dis 1246 status = "disabled";
1252 }; 1247 };
1253 }; 1248 };
1254 1249
1255 pwm0: pwm@e6e30000 { 1250 pwm0: pwm@e6e30000 {
1256 compatible = "renesas 1251 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
1257 reg = <0 0xe6e30000 0 1252 reg = <0 0xe6e30000 0 8>;
1258 #pwm-cells = <2>; 1253 #pwm-cells = <2>;
1259 clocks = <&cpg CPG_MO 1254 clocks = <&cpg CPG_MOD 523>;
1260 resets = <&cpg 523>; 1255 resets = <&cpg 523>;
1261 power-domains = <&sys 1256 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1262 status = "disabled"; 1257 status = "disabled";
1263 }; 1258 };
1264 1259
1265 pwm1: pwm@e6e31000 { 1260 pwm1: pwm@e6e31000 {
1266 compatible = "renesas 1261 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
1267 reg = <0 0xe6e31000 0 1262 reg = <0 0xe6e31000 0 8>;
1268 #pwm-cells = <2>; 1263 #pwm-cells = <2>;
1269 clocks = <&cpg CPG_MO 1264 clocks = <&cpg CPG_MOD 523>;
1270 resets = <&cpg 523>; 1265 resets = <&cpg 523>;
1271 power-domains = <&sys 1266 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1272 status = "disabled"; 1267 status = "disabled";
1273 }; 1268 };
1274 1269
1275 pwm2: pwm@e6e32000 { 1270 pwm2: pwm@e6e32000 {
1276 compatible = "renesas 1271 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
1277 reg = <0 0xe6e32000 0 1272 reg = <0 0xe6e32000 0 8>;
1278 #pwm-cells = <2>; 1273 #pwm-cells = <2>;
1279 clocks = <&cpg CPG_MO 1274 clocks = <&cpg CPG_MOD 523>;
1280 resets = <&cpg 523>; 1275 resets = <&cpg 523>;
1281 power-domains = <&sys 1276 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1282 status = "disabled"; 1277 status = "disabled";
1283 }; 1278 };
1284 1279
1285 pwm3: pwm@e6e33000 { 1280 pwm3: pwm@e6e33000 {
1286 compatible = "renesas 1281 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
1287 reg = <0 0xe6e33000 0 1282 reg = <0 0xe6e33000 0 8>;
1288 #pwm-cells = <2>; 1283 #pwm-cells = <2>;
1289 clocks = <&cpg CPG_MO 1284 clocks = <&cpg CPG_MOD 523>;
1290 resets = <&cpg 523>; 1285 resets = <&cpg 523>;
1291 power-domains = <&sys 1286 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1292 status = "disabled"; 1287 status = "disabled";
1293 }; 1288 };
1294 1289
1295 pwm4: pwm@e6e34000 { 1290 pwm4: pwm@e6e34000 {
1296 compatible = "renesas 1291 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
1297 reg = <0 0xe6e34000 0 1292 reg = <0 0xe6e34000 0 8>;
1298 #pwm-cells = <2>; 1293 #pwm-cells = <2>;
1299 clocks = <&cpg CPG_MO 1294 clocks = <&cpg CPG_MOD 523>;
1300 resets = <&cpg 523>; 1295 resets = <&cpg 523>;
1301 power-domains = <&sys 1296 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1302 status = "disabled"; 1297 status = "disabled";
1303 }; 1298 };
1304 1299
1305 pwm5: pwm@e6e35000 { 1300 pwm5: pwm@e6e35000 {
1306 compatible = "renesas 1301 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
1307 reg = <0 0xe6e35000 0 1302 reg = <0 0xe6e35000 0 8>;
1308 #pwm-cells = <2>; 1303 #pwm-cells = <2>;
1309 clocks = <&cpg CPG_MO 1304 clocks = <&cpg CPG_MOD 523>;
1310 resets = <&cpg 523>; 1305 resets = <&cpg 523>;
1311 power-domains = <&sys 1306 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1312 status = "disabled"; 1307 status = "disabled";
1313 }; 1308 };
1314 1309
1315 pwm6: pwm@e6e36000 { 1310 pwm6: pwm@e6e36000 {
1316 compatible = "renesas 1311 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
1317 reg = <0 0xe6e36000 0 1312 reg = <0 0xe6e36000 0 8>;
1318 #pwm-cells = <2>; 1313 #pwm-cells = <2>;
1319 clocks = <&cpg CPG_MO 1314 clocks = <&cpg CPG_MOD 523>;
1320 resets = <&cpg 523>; 1315 resets = <&cpg 523>;
1321 power-domains = <&sys 1316 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1322 status = "disabled"; 1317 status = "disabled";
1323 }; 1318 };
1324 1319
1325 scif0: serial@e6e60000 { 1320 scif0: serial@e6e60000 {
1326 compatible = "renesas 1321 compatible = "renesas,scif-r8a7796",
1327 "renesas 1322 "renesas,rcar-gen3-scif", "renesas,scif";
1328 reg = <0 0xe6e60000 0 1323 reg = <0 0xe6e60000 0 64>;
1329 interrupts = <GIC_SPI 1324 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
1330 clocks = <&cpg CPG_MO 1325 clocks = <&cpg CPG_MOD 207>,
1331 <&cpg CPG_CO 1326 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
1332 <&scif_clk>; 1327 <&scif_clk>;
1333 clock-names = "fck", 1328 clock-names = "fck", "brg_int", "scif_clk";
1334 dmas = <&dmac1 0x51>, 1329 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1335 <&dmac2 0x51>, 1330 <&dmac2 0x51>, <&dmac2 0x50>;
1336 dma-names = "tx", "rx 1331 dma-names = "tx", "rx", "tx", "rx";
1337 power-domains = <&sys 1332 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1338 resets = <&cpg 207>; 1333 resets = <&cpg 207>;
1339 status = "disabled"; 1334 status = "disabled";
1340 }; 1335 };
1341 1336
1342 scif1: serial@e6e68000 { 1337 scif1: serial@e6e68000 {
1343 compatible = "renesas 1338 compatible = "renesas,scif-r8a7796",
1344 "renesas 1339 "renesas,rcar-gen3-scif", "renesas,scif";
1345 reg = <0 0xe6e68000 0 1340 reg = <0 0xe6e68000 0 64>;
1346 interrupts = <GIC_SPI 1341 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
1347 clocks = <&cpg CPG_MO 1342 clocks = <&cpg CPG_MOD 206>,
1348 <&cpg CPG_CO 1343 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
1349 <&scif_clk>; 1344 <&scif_clk>;
1350 clock-names = "fck", 1345 clock-names = "fck", "brg_int", "scif_clk";
1351 dmas = <&dmac1 0x53>, 1346 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1352 <&dmac2 0x53>, 1347 <&dmac2 0x53>, <&dmac2 0x52>;
1353 dma-names = "tx", "rx 1348 dma-names = "tx", "rx", "tx", "rx";
1354 power-domains = <&sys 1349 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1355 resets = <&cpg 206>; 1350 resets = <&cpg 206>;
1356 status = "disabled"; 1351 status = "disabled";
1357 }; 1352 };
1358 1353
1359 scif2: serial@e6e88000 { 1354 scif2: serial@e6e88000 {
1360 compatible = "renesas 1355 compatible = "renesas,scif-r8a7796",
1361 "renesas 1356 "renesas,rcar-gen3-scif", "renesas,scif";
1362 reg = <0 0xe6e88000 0 1357 reg = <0 0xe6e88000 0 64>;
1363 interrupts = <GIC_SPI 1358 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
1364 clocks = <&cpg CPG_MO 1359 clocks = <&cpg CPG_MOD 310>,
1365 <&cpg CPG_CO 1360 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
1366 <&scif_clk>; 1361 <&scif_clk>;
1367 clock-names = "fck", 1362 clock-names = "fck", "brg_int", "scif_clk";
1368 dmas = <&dmac1 0x13>, 1363 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1369 <&dmac2 0x13>, 1364 <&dmac2 0x13>, <&dmac2 0x12>;
1370 dma-names = "tx", "rx 1365 dma-names = "tx", "rx", "tx", "rx";
1371 power-domains = <&sys 1366 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1372 resets = <&cpg 310>; 1367 resets = <&cpg 310>;
1373 status = "disabled"; 1368 status = "disabled";
1374 }; 1369 };
1375 1370
1376 scif3: serial@e6c50000 { 1371 scif3: serial@e6c50000 {
1377 compatible = "renesas 1372 compatible = "renesas,scif-r8a7796",
1378 "renesas 1373 "renesas,rcar-gen3-scif", "renesas,scif";
1379 reg = <0 0xe6c50000 0 1374 reg = <0 0xe6c50000 0 64>;
1380 interrupts = <GIC_SPI 1375 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1381 clocks = <&cpg CPG_MO 1376 clocks = <&cpg CPG_MOD 204>,
1382 <&cpg CPG_CO 1377 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
1383 <&scif_clk>; 1378 <&scif_clk>;
1384 clock-names = "fck", 1379 clock-names = "fck", "brg_int", "scif_clk";
1385 dmas = <&dmac0 0x57>, 1380 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1386 dma-names = "tx", "rx 1381 dma-names = "tx", "rx";
1387 power-domains = <&sys 1382 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1388 resets = <&cpg 204>; 1383 resets = <&cpg 204>;
1389 status = "disabled"; 1384 status = "disabled";
1390 }; 1385 };
1391 1386
1392 scif4: serial@e6c40000 { 1387 scif4: serial@e6c40000 {
1393 compatible = "renesas 1388 compatible = "renesas,scif-r8a7796",
1394 "renesas 1389 "renesas,rcar-gen3-scif", "renesas,scif";
1395 reg = <0 0xe6c40000 0 1390 reg = <0 0xe6c40000 0 64>;
1396 interrupts = <GIC_SPI 1391 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1397 clocks = <&cpg CPG_MO 1392 clocks = <&cpg CPG_MOD 203>,
1398 <&cpg CPG_CO 1393 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
1399 <&scif_clk>; 1394 <&scif_clk>;
1400 clock-names = "fck", 1395 clock-names = "fck", "brg_int", "scif_clk";
1401 dmas = <&dmac0 0x59>, 1396 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1402 dma-names = "tx", "rx 1397 dma-names = "tx", "rx";
1403 power-domains = <&sys 1398 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1404 resets = <&cpg 203>; 1399 resets = <&cpg 203>;
1405 status = "disabled"; 1400 status = "disabled";
1406 }; 1401 };
1407 1402
1408 scif5: serial@e6f30000 { 1403 scif5: serial@e6f30000 {
1409 compatible = "renesas 1404 compatible = "renesas,scif-r8a7796",
1410 "renesas 1405 "renesas,rcar-gen3-scif", "renesas,scif";
1411 reg = <0 0xe6f30000 0 1406 reg = <0 0xe6f30000 0 64>;
1412 interrupts = <GIC_SPI 1407 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1413 clocks = <&cpg CPG_MO 1408 clocks = <&cpg CPG_MOD 202>,
1414 <&cpg CPG_CO 1409 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
1415 <&scif_clk>; 1410 <&scif_clk>;
1416 clock-names = "fck", 1411 clock-names = "fck", "brg_int", "scif_clk";
1417 dmas = <&dmac1 0x5b>, 1412 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
1418 <&dmac2 0x5b>, 1413 <&dmac2 0x5b>, <&dmac2 0x5a>;
1419 dma-names = "tx", "rx 1414 dma-names = "tx", "rx", "tx", "rx";
1420 power-domains = <&sys 1415 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1421 resets = <&cpg 202>; 1416 resets = <&cpg 202>;
1422 status = "disabled"; 1417 status = "disabled";
1423 }; 1418 };
1424 1419
1425 tpu: pwm@e6e80000 { 1420 tpu: pwm@e6e80000 {
1426 compatible = "renesas 1421 compatible = "renesas,tpu-r8a7796", "renesas,tpu";
1427 reg = <0 0xe6e80000 0 1422 reg = <0 0xe6e80000 0 0x148>;
1428 interrupts = <GIC_SPI 1423 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
1429 clocks = <&cpg CPG_MO 1424 clocks = <&cpg CPG_MOD 304>;
1430 power-domains = <&sys 1425 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1431 resets = <&cpg 304>; 1426 resets = <&cpg 304>;
1432 #pwm-cells = <3>; 1427 #pwm-cells = <3>;
1433 status = "disabled"; 1428 status = "disabled";
1434 }; 1429 };
1435 1430
1436 msiof0: spi@e6e90000 { 1431 msiof0: spi@e6e90000 {
1437 compatible = "renesas 1432 compatible = "renesas,msiof-r8a7796",
1438 "renesas 1433 "renesas,rcar-gen3-msiof";
1439 reg = <0 0xe6e90000 0 1434 reg = <0 0xe6e90000 0 0x0064>;
1440 interrupts = <GIC_SPI 1435 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1441 clocks = <&cpg CPG_MO 1436 clocks = <&cpg CPG_MOD 211>;
1442 dmas = <&dmac1 0x41>, 1437 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1443 <&dmac2 0x41>, 1438 <&dmac2 0x41>, <&dmac2 0x40>;
1444 dma-names = "tx", "rx 1439 dma-names = "tx", "rx", "tx", "rx";
1445 power-domains = <&sys 1440 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1446 resets = <&cpg 211>; 1441 resets = <&cpg 211>;
1447 #address-cells = <1>; 1442 #address-cells = <1>;
1448 #size-cells = <0>; 1443 #size-cells = <0>;
1449 status = "disabled"; 1444 status = "disabled";
1450 }; 1445 };
1451 1446
1452 msiof1: spi@e6ea0000 { 1447 msiof1: spi@e6ea0000 {
1453 compatible = "renesas 1448 compatible = "renesas,msiof-r8a7796",
1454 "renesas 1449 "renesas,rcar-gen3-msiof";
1455 reg = <0 0xe6ea0000 0 1450 reg = <0 0xe6ea0000 0 0x0064>;
1456 interrupts = <GIC_SPI 1451 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1457 clocks = <&cpg CPG_MO 1452 clocks = <&cpg CPG_MOD 210>;
1458 dmas = <&dmac1 0x43>, 1453 dmas = <&dmac1 0x43>, <&dmac1 0x42>,
1459 <&dmac2 0x43>, 1454 <&dmac2 0x43>, <&dmac2 0x42>;
1460 dma-names = "tx", "rx 1455 dma-names = "tx", "rx", "tx", "rx";
1461 power-domains = <&sys 1456 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1462 resets = <&cpg 210>; 1457 resets = <&cpg 210>;
1463 #address-cells = <1>; 1458 #address-cells = <1>;
1464 #size-cells = <0>; 1459 #size-cells = <0>;
1465 status = "disabled"; 1460 status = "disabled";
1466 }; 1461 };
1467 1462
1468 msiof2: spi@e6c00000 { 1463 msiof2: spi@e6c00000 {
1469 compatible = "renesas 1464 compatible = "renesas,msiof-r8a7796",
1470 "renesas 1465 "renesas,rcar-gen3-msiof";
1471 reg = <0 0xe6c00000 0 1466 reg = <0 0xe6c00000 0 0x0064>;
1472 interrupts = <GIC_SPI 1467 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1473 clocks = <&cpg CPG_MO 1468 clocks = <&cpg CPG_MOD 209>;
1474 dmas = <&dmac0 0x45>, 1469 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1475 dma-names = "tx", "rx 1470 dma-names = "tx", "rx";
1476 power-domains = <&sys 1471 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1477 resets = <&cpg 209>; 1472 resets = <&cpg 209>;
1478 #address-cells = <1>; 1473 #address-cells = <1>;
1479 #size-cells = <0>; 1474 #size-cells = <0>;
1480 status = "disabled"; 1475 status = "disabled";
1481 }; 1476 };
1482 1477
1483 msiof3: spi@e6c10000 { 1478 msiof3: spi@e6c10000 {
1484 compatible = "renesas 1479 compatible = "renesas,msiof-r8a7796",
1485 "renesas 1480 "renesas,rcar-gen3-msiof";
1486 reg = <0 0xe6c10000 0 1481 reg = <0 0xe6c10000 0 0x0064>;
1487 interrupts = <GIC_SPI 1482 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1488 clocks = <&cpg CPG_MO 1483 clocks = <&cpg CPG_MOD 208>;
1489 dmas = <&dmac0 0x47>, 1484 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1490 dma-names = "tx", "rx 1485 dma-names = "tx", "rx";
1491 power-domains = <&sys 1486 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1492 resets = <&cpg 208>; 1487 resets = <&cpg 208>;
1493 #address-cells = <1>; 1488 #address-cells = <1>;
1494 #size-cells = <0>; 1489 #size-cells = <0>;
1495 status = "disabled"; 1490 status = "disabled";
1496 }; 1491 };
1497 1492
1498 vin0: video@e6ef0000 { 1493 vin0: video@e6ef0000 {
1499 compatible = "renesas 1494 compatible = "renesas,vin-r8a7796";
1500 reg = <0 0xe6ef0000 0 1495 reg = <0 0xe6ef0000 0 0x1000>;
1501 interrupts = <GIC_SPI 1496 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
1502 clocks = <&cpg CPG_MO 1497 clocks = <&cpg CPG_MOD 811>;
1503 power-domains = <&sys 1498 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1504 resets = <&cpg 811>; 1499 resets = <&cpg 811>;
1505 renesas,id = <0>; 1500 renesas,id = <0>;
1506 status = "disabled"; 1501 status = "disabled";
1507 1502
1508 ports { 1503 ports {
1509 #address-cell 1504 #address-cells = <1>;
1510 #size-cells = 1505 #size-cells = <0>;
1511 1506
1512 port@1 { 1507 port@1 {
1513 #addr 1508 #address-cells = <1>;
1514 #size 1509 #size-cells = <0>;
1515 1510
1516 reg = 1511 reg = <1>;
1517 1512
1518 vin0c 1513 vin0csi20: endpoint@0 {
1519 1514 reg = <0>;
1520 1515 remote-endpoint = <&csi20vin0>;
1521 }; 1516 };
1522 vin0c 1517 vin0csi40: endpoint@2 {
1523 1518 reg = <2>;
1524 1519 remote-endpoint = <&csi40vin0>;
1525 }; 1520 };
1526 }; 1521 };
1527 }; 1522 };
1528 }; 1523 };
1529 1524
1530 vin1: video@e6ef1000 { 1525 vin1: video@e6ef1000 {
1531 compatible = "renesas 1526 compatible = "renesas,vin-r8a7796";
1532 reg = <0 0xe6ef1000 0 1527 reg = <0 0xe6ef1000 0 0x1000>;
1533 interrupts = <GIC_SPI 1528 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
1534 clocks = <&cpg CPG_MO 1529 clocks = <&cpg CPG_MOD 810>;
1535 power-domains = <&sys 1530 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1536 resets = <&cpg 810>; 1531 resets = <&cpg 810>;
1537 renesas,id = <1>; 1532 renesas,id = <1>;
1538 status = "disabled"; 1533 status = "disabled";
1539 1534
1540 ports { 1535 ports {
1541 #address-cell 1536 #address-cells = <1>;
1542 #size-cells = 1537 #size-cells = <0>;
1543 1538
1544 port@1 { 1539 port@1 {
1545 #addr 1540 #address-cells = <1>;
1546 #size 1541 #size-cells = <0>;
1547 1542
1548 reg = 1543 reg = <1>;
1549 1544
1550 vin1c 1545 vin1csi20: endpoint@0 {
1551 1546 reg = <0>;
1552 1547 remote-endpoint = <&csi20vin1>;
1553 }; 1548 };
1554 vin1c 1549 vin1csi40: endpoint@2 {
1555 1550 reg = <2>;
1556 1551 remote-endpoint = <&csi40vin1>;
1557 }; 1552 };
1558 }; 1553 };
1559 }; 1554 };
1560 }; 1555 };
1561 1556
1562 vin2: video@e6ef2000 { 1557 vin2: video@e6ef2000 {
1563 compatible = "renesas 1558 compatible = "renesas,vin-r8a7796";
1564 reg = <0 0xe6ef2000 0 1559 reg = <0 0xe6ef2000 0 0x1000>;
1565 interrupts = <GIC_SPI 1560 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1566 clocks = <&cpg CPG_MO 1561 clocks = <&cpg CPG_MOD 809>;
1567 power-domains = <&sys 1562 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1568 resets = <&cpg 809>; 1563 resets = <&cpg 809>;
1569 renesas,id = <2>; 1564 renesas,id = <2>;
1570 status = "disabled"; 1565 status = "disabled";
1571 1566
1572 ports { 1567 ports {
1573 #address-cell 1568 #address-cells = <1>;
1574 #size-cells = 1569 #size-cells = <0>;
1575 1570
1576 port@1 { 1571 port@1 {
1577 #addr 1572 #address-cells = <1>;
1578 #size 1573 #size-cells = <0>;
1579 1574
1580 reg = 1575 reg = <1>;
1581 1576
1582 vin2c 1577 vin2csi20: endpoint@0 {
1583 1578 reg = <0>;
1584 1579 remote-endpoint = <&csi20vin2>;
1585 }; 1580 };
1586 vin2c 1581 vin2csi40: endpoint@2 {
1587 1582 reg = <2>;
1588 1583 remote-endpoint = <&csi40vin2>;
1589 }; 1584 };
1590 }; 1585 };
1591 }; 1586 };
1592 }; 1587 };
1593 1588
1594 vin3: video@e6ef3000 { 1589 vin3: video@e6ef3000 {
1595 compatible = "renesas 1590 compatible = "renesas,vin-r8a7796";
1596 reg = <0 0xe6ef3000 0 1591 reg = <0 0xe6ef3000 0 0x1000>;
1597 interrupts = <GIC_SPI 1592 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
1598 clocks = <&cpg CPG_MO 1593 clocks = <&cpg CPG_MOD 808>;
1599 power-domains = <&sys 1594 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1600 resets = <&cpg 808>; 1595 resets = <&cpg 808>;
1601 renesas,id = <3>; 1596 renesas,id = <3>;
1602 status = "disabled"; 1597 status = "disabled";
1603 1598
1604 ports { 1599 ports {
1605 #address-cell 1600 #address-cells = <1>;
1606 #size-cells = 1601 #size-cells = <0>;
1607 1602
1608 port@1 { 1603 port@1 {
1609 #addr 1604 #address-cells = <1>;
1610 #size 1605 #size-cells = <0>;
1611 1606
1612 reg = 1607 reg = <1>;
1613 1608
1614 vin3c 1609 vin3csi20: endpoint@0 {
1615 1610 reg = <0>;
1616 1611 remote-endpoint = <&csi20vin3>;
1617 }; 1612 };
1618 vin3c 1613 vin3csi40: endpoint@2 {
1619 1614 reg = <2>;
1620 1615 remote-endpoint = <&csi40vin3>;
1621 }; 1616 };
1622 }; 1617 };
1623 }; 1618 };
1624 }; 1619 };
1625 1620
1626 vin4: video@e6ef4000 { 1621 vin4: video@e6ef4000 {
1627 compatible = "renesas 1622 compatible = "renesas,vin-r8a7796";
1628 reg = <0 0xe6ef4000 0 1623 reg = <0 0xe6ef4000 0 0x1000>;
1629 interrupts = <GIC_SPI 1624 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
1630 clocks = <&cpg CPG_MO 1625 clocks = <&cpg CPG_MOD 807>;
1631 power-domains = <&sys 1626 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1632 resets = <&cpg 807>; 1627 resets = <&cpg 807>;
1633 renesas,id = <4>; 1628 renesas,id = <4>;
1634 status = "disabled"; 1629 status = "disabled";
1635 1630
1636 ports { 1631 ports {
1637 #address-cell 1632 #address-cells = <1>;
1638 #size-cells = 1633 #size-cells = <0>;
1639 1634
1640 port@1 { 1635 port@1 {
1641 #addr 1636 #address-cells = <1>;
1642 #size 1637 #size-cells = <0>;
1643 1638
1644 reg = 1639 reg = <1>;
1645 1640
1646 vin4c 1641 vin4csi20: endpoint@0 {
1647 1642 reg = <0>;
1648 1643 remote-endpoint = <&csi20vin4>;
1649 }; 1644 };
1650 vin4c 1645 vin4csi40: endpoint@2 {
1651 1646 reg = <2>;
1652 1647 remote-endpoint = <&csi40vin4>;
1653 }; 1648 };
1654 }; 1649 };
1655 }; 1650 };
1656 }; 1651 };
1657 1652
1658 vin5: video@e6ef5000 { 1653 vin5: video@e6ef5000 {
1659 compatible = "renesas 1654 compatible = "renesas,vin-r8a7796";
1660 reg = <0 0xe6ef5000 0 1655 reg = <0 0xe6ef5000 0 0x1000>;
1661 interrupts = <GIC_SPI 1656 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
1662 clocks = <&cpg CPG_MO 1657 clocks = <&cpg CPG_MOD 806>;
1663 power-domains = <&sys 1658 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1664 resets = <&cpg 806>; 1659 resets = <&cpg 806>;
1665 renesas,id = <5>; 1660 renesas,id = <5>;
1666 status = "disabled"; 1661 status = "disabled";
1667 1662
1668 ports { 1663 ports {
1669 #address-cell 1664 #address-cells = <1>;
1670 #size-cells = 1665 #size-cells = <0>;
1671 1666
1672 port@1 { 1667 port@1 {
1673 #addr 1668 #address-cells = <1>;
1674 #size 1669 #size-cells = <0>;
1675 1670
1676 reg = 1671 reg = <1>;
1677 1672
1678 vin5c 1673 vin5csi20: endpoint@0 {
1679 1674 reg = <0>;
1680 1675 remote-endpoint = <&csi20vin5>;
1681 }; 1676 };
1682 vin5c 1677 vin5csi40: endpoint@2 {
1683 1678 reg = <2>;
1684 1679 remote-endpoint = <&csi40vin5>;
1685 }; 1680 };
1686 }; 1681 };
1687 }; 1682 };
1688 }; 1683 };
1689 1684
1690 vin6: video@e6ef6000 { 1685 vin6: video@e6ef6000 {
1691 compatible = "renesas 1686 compatible = "renesas,vin-r8a7796";
1692 reg = <0 0xe6ef6000 0 1687 reg = <0 0xe6ef6000 0 0x1000>;
1693 interrupts = <GIC_SPI 1688 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
1694 clocks = <&cpg CPG_MO 1689 clocks = <&cpg CPG_MOD 805>;
1695 power-domains = <&sys 1690 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1696 resets = <&cpg 805>; 1691 resets = <&cpg 805>;
1697 renesas,id = <6>; 1692 renesas,id = <6>;
1698 status = "disabled"; 1693 status = "disabled";
1699 1694
1700 ports { 1695 ports {
1701 #address-cell 1696 #address-cells = <1>;
1702 #size-cells = 1697 #size-cells = <0>;
1703 1698
1704 port@1 { 1699 port@1 {
1705 #addr 1700 #address-cells = <1>;
1706 #size 1701 #size-cells = <0>;
1707 1702
1708 reg = 1703 reg = <1>;
1709 1704
1710 vin6c 1705 vin6csi20: endpoint@0 {
1711 1706 reg = <0>;
1712 1707 remote-endpoint = <&csi20vin6>;
1713 }; 1708 };
1714 vin6c 1709 vin6csi40: endpoint@2 {
1715 1710 reg = <2>;
1716 1711 remote-endpoint = <&csi40vin6>;
1717 }; 1712 };
1718 }; 1713 };
1719 }; 1714 };
1720 }; 1715 };
1721 1716
1722 vin7: video@e6ef7000 { 1717 vin7: video@e6ef7000 {
1723 compatible = "renesas 1718 compatible = "renesas,vin-r8a7796";
1724 reg = <0 0xe6ef7000 0 1719 reg = <0 0xe6ef7000 0 0x1000>;
1725 interrupts = <GIC_SPI 1720 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
1726 clocks = <&cpg CPG_MO 1721 clocks = <&cpg CPG_MOD 804>;
1727 power-domains = <&sys 1722 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1728 resets = <&cpg 804>; 1723 resets = <&cpg 804>;
1729 renesas,id = <7>; 1724 renesas,id = <7>;
1730 status = "disabled"; 1725 status = "disabled";
1731 1726
1732 ports { 1727 ports {
1733 #address-cell 1728 #address-cells = <1>;
1734 #size-cells = 1729 #size-cells = <0>;
1735 1730
1736 port@1 { 1731 port@1 {
1737 #addr 1732 #address-cells = <1>;
1738 #size 1733 #size-cells = <0>;
1739 1734
1740 reg = 1735 reg = <1>;
1741 1736
1742 vin7c 1737 vin7csi20: endpoint@0 {
1743 1738 reg = <0>;
1744 1739 remote-endpoint = <&csi20vin7>;
1745 }; 1740 };
1746 vin7c 1741 vin7csi40: endpoint@2 {
1747 1742 reg = <2>;
1748 1743 remote-endpoint = <&csi40vin7>;
1749 }; 1744 };
1750 }; 1745 };
1751 }; 1746 };
1752 }; 1747 };
1753 1748
1754 drif00: rif@e6f40000 { 1749 drif00: rif@e6f40000 {
1755 compatible = "renesas 1750 compatible = "renesas,r8a7796-drif",
1756 "renesas 1751 "renesas,rcar-gen3-drif";
1757 reg = <0 0xe6f40000 0 1752 reg = <0 0xe6f40000 0 0x64>;
1758 interrupts = <GIC_SPI 1753 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1759 clocks = <&cpg CPG_MO 1754 clocks = <&cpg CPG_MOD 515>;
1760 clock-names = "fck"; 1755 clock-names = "fck";
1761 dmas = <&dmac1 0x20>, 1756 dmas = <&dmac1 0x20>, <&dmac2 0x20>;
1762 dma-names = "rx", "rx 1757 dma-names = "rx", "rx";
1763 power-domains = <&sys 1758 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1764 resets = <&cpg 515>; 1759 resets = <&cpg 515>;
1765 renesas,bonding = <&d 1760 renesas,bonding = <&drif01>;
1766 status = "disabled"; 1761 status = "disabled";
1767 }; 1762 };
1768 1763
1769 drif01: rif@e6f50000 { 1764 drif01: rif@e6f50000 {
1770 compatible = "renesas 1765 compatible = "renesas,r8a7796-drif",
1771 "renesas 1766 "renesas,rcar-gen3-drif";
1772 reg = <0 0xe6f50000 0 1767 reg = <0 0xe6f50000 0 0x64>;
1773 interrupts = <GIC_SPI 1768 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1774 clocks = <&cpg CPG_MO 1769 clocks = <&cpg CPG_MOD 514>;
1775 clock-names = "fck"; 1770 clock-names = "fck";
1776 dmas = <&dmac1 0x22>, 1771 dmas = <&dmac1 0x22>, <&dmac2 0x22>;
1777 dma-names = "rx", "rx 1772 dma-names = "rx", "rx";
1778 power-domains = <&sys 1773 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1779 resets = <&cpg 514>; 1774 resets = <&cpg 514>;
1780 renesas,bonding = <&d 1775 renesas,bonding = <&drif00>;
1781 status = "disabled"; 1776 status = "disabled";
1782 }; 1777 };
1783 1778
1784 drif10: rif@e6f60000 { 1779 drif10: rif@e6f60000 {
1785 compatible = "renesas 1780 compatible = "renesas,r8a7796-drif",
1786 "renesas 1781 "renesas,rcar-gen3-drif";
1787 reg = <0 0xe6f60000 0 1782 reg = <0 0xe6f60000 0 0x64>;
1788 interrupts = <GIC_SPI 1783 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1789 clocks = <&cpg CPG_MO 1784 clocks = <&cpg CPG_MOD 513>;
1790 clock-names = "fck"; 1785 clock-names = "fck";
1791 dmas = <&dmac1 0x24>, 1786 dmas = <&dmac1 0x24>, <&dmac2 0x24>;
1792 dma-names = "rx", "rx 1787 dma-names = "rx", "rx";
1793 power-domains = <&sys 1788 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1794 resets = <&cpg 513>; 1789 resets = <&cpg 513>;
1795 renesas,bonding = <&d 1790 renesas,bonding = <&drif11>;
1796 status = "disabled"; 1791 status = "disabled";
1797 }; 1792 };
1798 1793
1799 drif11: rif@e6f70000 { 1794 drif11: rif@e6f70000 {
1800 compatible = "renesas 1795 compatible = "renesas,r8a7796-drif",
1801 "renesas 1796 "renesas,rcar-gen3-drif";
1802 reg = <0 0xe6f70000 0 1797 reg = <0 0xe6f70000 0 0x64>;
1803 interrupts = <GIC_SPI 1798 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1804 clocks = <&cpg CPG_MO 1799 clocks = <&cpg CPG_MOD 512>;
1805 clock-names = "fck"; 1800 clock-names = "fck";
1806 dmas = <&dmac1 0x26>, 1801 dmas = <&dmac1 0x26>, <&dmac2 0x26>;
1807 dma-names = "rx", "rx 1802 dma-names = "rx", "rx";
1808 power-domains = <&sys 1803 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1809 resets = <&cpg 512>; 1804 resets = <&cpg 512>;
1810 renesas,bonding = <&d 1805 renesas,bonding = <&drif10>;
1811 status = "disabled"; 1806 status = "disabled";
1812 }; 1807 };
1813 1808
1814 drif20: rif@e6f80000 { 1809 drif20: rif@e6f80000 {
1815 compatible = "renesas 1810 compatible = "renesas,r8a7796-drif",
1816 "renesas 1811 "renesas,rcar-gen3-drif";
1817 reg = <0 0xe6f80000 0 1812 reg = <0 0xe6f80000 0 0x64>;
1818 interrupts = <GIC_SPI 1813 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1819 clocks = <&cpg CPG_MO 1814 clocks = <&cpg CPG_MOD 511>;
1820 clock-names = "fck"; 1815 clock-names = "fck";
1821 dmas = <&dmac1 0x28>, 1816 dmas = <&dmac1 0x28>, <&dmac2 0x28>;
1822 dma-names = "rx", "rx 1817 dma-names = "rx", "rx";
1823 power-domains = <&sys 1818 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1824 resets = <&cpg 511>; 1819 resets = <&cpg 511>;
1825 renesas,bonding = <&d 1820 renesas,bonding = <&drif21>;
1826 status = "disabled"; 1821 status = "disabled";
1827 }; 1822 };
1828 1823
1829 drif21: rif@e6f90000 { 1824 drif21: rif@e6f90000 {
1830 compatible = "renesas 1825 compatible = "renesas,r8a7796-drif",
1831 "renesas 1826 "renesas,rcar-gen3-drif";
1832 reg = <0 0xe6f90000 0 1827 reg = <0 0xe6f90000 0 0x64>;
1833 interrupts = <GIC_SPI 1828 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1834 clocks = <&cpg CPG_MO 1829 clocks = <&cpg CPG_MOD 510>;
1835 clock-names = "fck"; 1830 clock-names = "fck";
1836 dmas = <&dmac1 0x2a>, 1831 dmas = <&dmac1 0x2a>, <&dmac2 0x2a>;
1837 dma-names = "rx", "rx 1832 dma-names = "rx", "rx";
1838 power-domains = <&sys 1833 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1839 resets = <&cpg 510>; 1834 resets = <&cpg 510>;
1840 renesas,bonding = <&d 1835 renesas,bonding = <&drif20>;
1841 status = "disabled"; 1836 status = "disabled";
1842 }; 1837 };
1843 1838
1844 drif30: rif@e6fa0000 { 1839 drif30: rif@e6fa0000 {
1845 compatible = "renesas 1840 compatible = "renesas,r8a7796-drif",
1846 "renesas 1841 "renesas,rcar-gen3-drif";
1847 reg = <0 0xe6fa0000 0 1842 reg = <0 0xe6fa0000 0 0x64>;
1848 interrupts = <GIC_SPI 1843 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1849 clocks = <&cpg CPG_MO 1844 clocks = <&cpg CPG_MOD 509>;
1850 clock-names = "fck"; 1845 clock-names = "fck";
1851 dmas = <&dmac1 0x2c>, 1846 dmas = <&dmac1 0x2c>, <&dmac2 0x2c>;
1852 dma-names = "rx", "rx 1847 dma-names = "rx", "rx";
1853 power-domains = <&sys 1848 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1854 resets = <&cpg 509>; 1849 resets = <&cpg 509>;
1855 renesas,bonding = <&d 1850 renesas,bonding = <&drif31>;
1856 status = "disabled"; 1851 status = "disabled";
1857 }; 1852 };
1858 1853
1859 drif31: rif@e6fb0000 { 1854 drif31: rif@e6fb0000 {
1860 compatible = "renesas 1855 compatible = "renesas,r8a7796-drif",
1861 "renesas 1856 "renesas,rcar-gen3-drif";
1862 reg = <0 0xe6fb0000 0 1857 reg = <0 0xe6fb0000 0 0x64>;
1863 interrupts = <GIC_SPI 1858 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1864 clocks = <&cpg CPG_MO 1859 clocks = <&cpg CPG_MOD 508>;
1865 clock-names = "fck"; 1860 clock-names = "fck";
1866 dmas = <&dmac1 0x2e>, 1861 dmas = <&dmac1 0x2e>, <&dmac2 0x2e>;
1867 dma-names = "rx", "rx 1862 dma-names = "rx", "rx";
1868 power-domains = <&sys 1863 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1869 resets = <&cpg 508>; 1864 resets = <&cpg 508>;
1870 renesas,bonding = <&d 1865 renesas,bonding = <&drif30>;
1871 status = "disabled"; 1866 status = "disabled";
1872 }; 1867 };
1873 1868
1874 rcar_sound: sound@ec500000 { 1869 rcar_sound: sound@ec500000 {
1875 /* 1870 /*
1876 * #sound-dai-cells i 1871 * #sound-dai-cells is required if simple-card
1877 * 1872 *
1878 * Single DAI : #soun 1873 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1879 * Multi DAI : #soun 1874 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1880 */ 1875 */
1881 /* 1876 /*
1882 * #clock-cells is re 1877 * #clock-cells is required for audio_clkout0/1/2/3
1883 * 1878 *
1884 * clkout : #cl 1879 * clkout : #clock-cells = <0>; <&rcar_sound>;
1885 * clkout0/1/2/3: #cl 1880 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
1886 */ 1881 */
1887 compatible = "renesas 1882 compatible = "renesas,rcar_sound-r8a7796", "renesas,rcar_sound-gen3";
1888 reg = <0 0xec500000 0 1883 reg = <0 0xec500000 0 0x1000>, /* SCU */
1889 <0 0xec5a0000 0 1884 <0 0xec5a0000 0 0x100>, /* ADG */
1890 <0 0xec540000 0 1885 <0 0xec540000 0 0x1000>, /* SSIU */
1891 <0 0xec541000 0 1886 <0 0xec541000 0 0x280>, /* SSI */
1892 <0 0xec760000 0 1887 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
1893 reg-names = "scu", "a 1888 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1894 1889
1895 clocks = <&cpg CPG_MO 1890 clocks = <&cpg CPG_MOD 1005>,
1896 <&cpg CPG_MO 1891 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
1897 <&cpg CPG_MO 1892 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
1898 <&cpg CPG_MO 1893 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
1899 <&cpg CPG_MO 1894 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
1900 <&cpg CPG_MO 1895 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
1901 <&cpg CPG_MO 1896 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
1902 <&cpg CPG_MO 1897 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
1903 <&cpg CPG_MO 1898 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
1904 <&cpg CPG_MO 1899 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
1905 <&cpg CPG_MO 1900 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
1906 <&cpg CPG_MO 1901 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1907 <&cpg CPG_MO 1902 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1908 <&cpg CPG_MO 1903 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
1909 <&audio_clk_ 1904 <&audio_clk_a>, <&audio_clk_b>,
1910 <&audio_clk_ 1905 <&audio_clk_c>,
1911 <&cpg CPG_MO !! 1906 <&cpg CPG_CORE R8A7796_CLK_S0D4>;
1912 clock-names = "ssi-al 1907 clock-names = "ssi-all",
1913 "ssi.9" 1908 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1914 "ssi.5" 1909 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1915 "ssi.1" 1910 "ssi.1", "ssi.0",
1916 "src.9" 1911 "src.9", "src.8", "src.7", "src.6",
1917 "src.5" 1912 "src.5", "src.4", "src.3", "src.2",
1918 "src.1" 1913 "src.1", "src.0",
1919 "mix.1" 1914 "mix.1", "mix.0",
1920 "ctu.1" 1915 "ctu.1", "ctu.0",
1921 "dvc.0" 1916 "dvc.0", "dvc.1",
1922 "clk_a" 1917 "clk_a", "clk_b", "clk_c", "clk_i";
1923 power-domains = <&sys 1918 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1924 resets = <&cpg 1005>, 1919 resets = <&cpg 1005>,
1925 <&cpg 1006>, 1920 <&cpg 1006>, <&cpg 1007>,
1926 <&cpg 1008>, 1921 <&cpg 1008>, <&cpg 1009>,
1927 <&cpg 1010>, 1922 <&cpg 1010>, <&cpg 1011>,
1928 <&cpg 1012>, 1923 <&cpg 1012>, <&cpg 1013>,
1929 <&cpg 1014>, 1924 <&cpg 1014>, <&cpg 1015>;
1930 reset-names = "ssi-al 1925 reset-names = "ssi-all",
1931 "ssi.9" 1926 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1932 "ssi.5" 1927 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1933 "ssi.1" 1928 "ssi.1", "ssi.0";
1934 status = "disabled"; 1929 status = "disabled";
1935 1930
1936 rcar_sound,ctu { 1931 rcar_sound,ctu {
1937 ctu00: ctu-0 1932 ctu00: ctu-0 { };
1938 ctu01: ctu-1 1933 ctu01: ctu-1 { };
1939 ctu02: ctu-2 1934 ctu02: ctu-2 { };
1940 ctu03: ctu-3 1935 ctu03: ctu-3 { };
1941 ctu10: ctu-4 1936 ctu10: ctu-4 { };
1942 ctu11: ctu-5 1937 ctu11: ctu-5 { };
1943 ctu12: ctu-6 1938 ctu12: ctu-6 { };
1944 ctu13: ctu-7 1939 ctu13: ctu-7 { };
1945 }; 1940 };
1946 1941
1947 rcar_sound,dvc { 1942 rcar_sound,dvc {
1948 dvc0: dvc-0 { 1943 dvc0: dvc-0 {
1949 dmas 1944 dmas = <&audma1 0xbc>;
1950 dma-n 1945 dma-names = "tx";
1951 }; 1946 };
1952 dvc1: dvc-1 { 1947 dvc1: dvc-1 {
1953 dmas 1948 dmas = <&audma1 0xbe>;
1954 dma-n 1949 dma-names = "tx";
1955 }; 1950 };
1956 }; 1951 };
1957 1952
1958 rcar_sound,mix { 1953 rcar_sound,mix {
1959 mix0: mix-0 { 1954 mix0: mix-0 { };
1960 mix1: mix-1 { 1955 mix1: mix-1 { };
1961 }; 1956 };
1962 1957
1963 rcar_sound,src { 1958 rcar_sound,src {
1964 src0: src-0 { 1959 src0: src-0 {
1965 inter 1960 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1966 dmas 1961 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1967 dma-n 1962 dma-names = "rx", "tx";
1968 }; 1963 };
1969 src1: src-1 { 1964 src1: src-1 {
1970 inter 1965 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1971 dmas 1966 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1972 dma-n 1967 dma-names = "rx", "tx";
1973 }; 1968 };
1974 src2: src-2 { 1969 src2: src-2 {
1975 inter 1970 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1976 dmas 1971 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1977 dma-n 1972 dma-names = "rx", "tx";
1978 }; 1973 };
1979 src3: src-3 { 1974 src3: src-3 {
1980 inter 1975 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1981 dmas 1976 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1982 dma-n 1977 dma-names = "rx", "tx";
1983 }; 1978 };
1984 src4: src-4 { 1979 src4: src-4 {
1985 inter 1980 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1986 dmas 1981 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1987 dma-n 1982 dma-names = "rx", "tx";
1988 }; 1983 };
1989 src5: src-5 { 1984 src5: src-5 {
1990 inter 1985 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1991 dmas 1986 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1992 dma-n 1987 dma-names = "rx", "tx";
1993 }; 1988 };
1994 src6: src-6 { 1989 src6: src-6 {
1995 inter 1990 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1996 dmas 1991 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1997 dma-n 1992 dma-names = "rx", "tx";
1998 }; 1993 };
1999 src7: src-7 { 1994 src7: src-7 {
2000 inter 1995 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
2001 dmas 1996 dmas = <&audma0 0x93>, <&audma1 0xb6>;
2002 dma-n 1997 dma-names = "rx", "tx";
2003 }; 1998 };
2004 src8: src-8 { 1999 src8: src-8 {
2005 inter 2000 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2006 dmas 2001 dmas = <&audma0 0x95>, <&audma1 0xb8>;
2007 dma-n 2002 dma-names = "rx", "tx";
2008 }; 2003 };
2009 src9: src-9 { 2004 src9: src-9 {
2010 inter 2005 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
2011 dmas 2006 dmas = <&audma0 0x97>, <&audma1 0xba>;
2012 dma-n 2007 dma-names = "rx", "tx";
2013 }; 2008 };
2014 }; 2009 };
2015 2010
2016 rcar_sound,ssi { 2011 rcar_sound,ssi {
2017 ssi0: ssi-0 { 2012 ssi0: ssi-0 {
2018 inter 2013 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
2019 dmas 2014 dmas = <&audma0 0x01>, <&audma1 0x02>;
2020 dma-n 2015 dma-names = "rx", "tx";
2021 }; 2016 };
2022 ssi1: ssi-1 { 2017 ssi1: ssi-1 {
2023 inter 2018 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
2024 dmas 2019 dmas = <&audma0 0x03>, <&audma1 0x04>;
2025 dma-n 2020 dma-names = "rx", "tx";
2026 }; 2021 };
2027 ssi2: ssi-2 { 2022 ssi2: ssi-2 {
2028 inter 2023 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
2029 dmas 2024 dmas = <&audma0 0x05>, <&audma1 0x06>;
2030 dma-n 2025 dma-names = "rx", "tx";
2031 }; 2026 };
2032 ssi3: ssi-3 { 2027 ssi3: ssi-3 {
2033 inter 2028 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
2034 dmas 2029 dmas = <&audma0 0x07>, <&audma1 0x08>;
2035 dma-n 2030 dma-names = "rx", "tx";
2036 }; 2031 };
2037 ssi4: ssi-4 { 2032 ssi4: ssi-4 {
2038 inter 2033 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
2039 dmas 2034 dmas = <&audma0 0x09>, <&audma1 0x0a>;
2040 dma-n 2035 dma-names = "rx", "tx";
2041 }; 2036 };
2042 ssi5: ssi-5 { 2037 ssi5: ssi-5 {
2043 inter 2038 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
2044 dmas 2039 dmas = <&audma0 0x0b>, <&audma1 0x0c>;
2045 dma-n 2040 dma-names = "rx", "tx";
2046 }; 2041 };
2047 ssi6: ssi-6 { 2042 ssi6: ssi-6 {
2048 inter 2043 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
2049 dmas 2044 dmas = <&audma0 0x0d>, <&audma1 0x0e>;
2050 dma-n 2045 dma-names = "rx", "tx";
2051 }; 2046 };
2052 ssi7: ssi-7 { 2047 ssi7: ssi-7 {
2053 inter 2048 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
2054 dmas 2049 dmas = <&audma0 0x0f>, <&audma1 0x10>;
2055 dma-n 2050 dma-names = "rx", "tx";
2056 }; 2051 };
2057 ssi8: ssi-8 { 2052 ssi8: ssi-8 {
2058 inter 2053 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
2059 dmas 2054 dmas = <&audma0 0x11>, <&audma1 0x12>;
2060 dma-n 2055 dma-names = "rx", "tx";
2061 }; 2056 };
2062 ssi9: ssi-9 { 2057 ssi9: ssi-9 {
2063 inter 2058 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
2064 dmas 2059 dmas = <&audma0 0x13>, <&audma1 0x14>;
2065 dma-n 2060 dma-names = "rx", "tx";
2066 }; 2061 };
2067 }; 2062 };
2068 2063
2069 rcar_sound,ssiu { 2064 rcar_sound,ssiu {
2070 ssiu00: ssiu- 2065 ssiu00: ssiu-0 {
2071 dmas 2066 dmas = <&audma0 0x15>, <&audma1 0x16>;
2072 dma-n 2067 dma-names = "rx", "tx";
2073 }; 2068 };
2074 ssiu01: ssiu- 2069 ssiu01: ssiu-1 {
2075 dmas 2070 dmas = <&audma0 0x35>, <&audma1 0x36>;
2076 dma-n 2071 dma-names = "rx", "tx";
2077 }; 2072 };
2078 ssiu02: ssiu- 2073 ssiu02: ssiu-2 {
2079 dmas 2074 dmas = <&audma0 0x37>, <&audma1 0x38>;
2080 dma-n 2075 dma-names = "rx", "tx";
2081 }; 2076 };
2082 ssiu03: ssiu- 2077 ssiu03: ssiu-3 {
2083 dmas 2078 dmas = <&audma0 0x47>, <&audma1 0x48>;
2084 dma-n 2079 dma-names = "rx", "tx";
2085 }; 2080 };
2086 ssiu04: ssiu- 2081 ssiu04: ssiu-4 {
2087 dmas 2082 dmas = <&audma0 0x3F>, <&audma1 0x40>;
2088 dma-n 2083 dma-names = "rx", "tx";
2089 }; 2084 };
2090 ssiu05: ssiu- 2085 ssiu05: ssiu-5 {
2091 dmas 2086 dmas = <&audma0 0x43>, <&audma1 0x44>;
2092 dma-n 2087 dma-names = "rx", "tx";
2093 }; 2088 };
2094 ssiu06: ssiu- 2089 ssiu06: ssiu-6 {
2095 dmas 2090 dmas = <&audma0 0x4F>, <&audma1 0x50>;
2096 dma-n 2091 dma-names = "rx", "tx";
2097 }; 2092 };
2098 ssiu07: ssiu- 2093 ssiu07: ssiu-7 {
2099 dmas 2094 dmas = <&audma0 0x53>, <&audma1 0x54>;
2100 dma-n 2095 dma-names = "rx", "tx";
2101 }; 2096 };
2102 ssiu10: ssiu- 2097 ssiu10: ssiu-8 {
2103 dmas 2098 dmas = <&audma0 0x49>, <&audma1 0x4a>;
2104 dma-n 2099 dma-names = "rx", "tx";
2105 }; 2100 };
2106 ssiu11: ssiu- 2101 ssiu11: ssiu-9 {
2107 dmas 2102 dmas = <&audma0 0x4B>, <&audma1 0x4C>;
2108 dma-n 2103 dma-names = "rx", "tx";
2109 }; 2104 };
2110 ssiu12: ssiu- 2105 ssiu12: ssiu-10 {
2111 dmas 2106 dmas = <&audma0 0x57>, <&audma1 0x58>;
2112 dma-n 2107 dma-names = "rx", "tx";
2113 }; 2108 };
2114 ssiu13: ssiu- 2109 ssiu13: ssiu-11 {
2115 dmas 2110 dmas = <&audma0 0x59>, <&audma1 0x5A>;
2116 dma-n 2111 dma-names = "rx", "tx";
2117 }; 2112 };
2118 ssiu14: ssiu- 2113 ssiu14: ssiu-12 {
2119 dmas 2114 dmas = <&audma0 0x5F>, <&audma1 0x60>;
2120 dma-n 2115 dma-names = "rx", "tx";
2121 }; 2116 };
2122 ssiu15: ssiu- 2117 ssiu15: ssiu-13 {
2123 dmas 2118 dmas = <&audma0 0xC3>, <&audma1 0xC4>;
2124 dma-n 2119 dma-names = "rx", "tx";
2125 }; 2120 };
2126 ssiu16: ssiu- 2121 ssiu16: ssiu-14 {
2127 dmas 2122 dmas = <&audma0 0xC7>, <&audma1 0xC8>;
2128 dma-n 2123 dma-names = "rx", "tx";
2129 }; 2124 };
2130 ssiu17: ssiu- 2125 ssiu17: ssiu-15 {
2131 dmas 2126 dmas = <&audma0 0xCB>, <&audma1 0xCC>;
2132 dma-n 2127 dma-names = "rx", "tx";
2133 }; 2128 };
2134 ssiu20: ssiu- 2129 ssiu20: ssiu-16 {
2135 dmas 2130 dmas = <&audma0 0x63>, <&audma1 0x64>;
2136 dma-n 2131 dma-names = "rx", "tx";
2137 }; 2132 };
2138 ssiu21: ssiu- 2133 ssiu21: ssiu-17 {
2139 dmas 2134 dmas = <&audma0 0x67>, <&audma1 0x68>;
2140 dma-n 2135 dma-names = "rx", "tx";
2141 }; 2136 };
2142 ssiu22: ssiu- 2137 ssiu22: ssiu-18 {
2143 dmas 2138 dmas = <&audma0 0x6B>, <&audma1 0x6C>;
2144 dma-n 2139 dma-names = "rx", "tx";
2145 }; 2140 };
2146 ssiu23: ssiu- 2141 ssiu23: ssiu-19 {
2147 dmas 2142 dmas = <&audma0 0x6D>, <&audma1 0x6E>;
2148 dma-n 2143 dma-names = "rx", "tx";
2149 }; 2144 };
2150 ssiu24: ssiu- 2145 ssiu24: ssiu-20 {
2151 dmas 2146 dmas = <&audma0 0xCF>, <&audma1 0xCE>;
2152 dma-n 2147 dma-names = "rx", "tx";
2153 }; 2148 };
2154 ssiu25: ssiu- 2149 ssiu25: ssiu-21 {
2155 dmas 2150 dmas = <&audma0 0xEB>, <&audma1 0xEC>;
2156 dma-n 2151 dma-names = "rx", "tx";
2157 }; 2152 };
2158 ssiu26: ssiu- 2153 ssiu26: ssiu-22 {
2159 dmas 2154 dmas = <&audma0 0xED>, <&audma1 0xEE>;
2160 dma-n 2155 dma-names = "rx", "tx";
2161 }; 2156 };
2162 ssiu27: ssiu- 2157 ssiu27: ssiu-23 {
2163 dmas 2158 dmas = <&audma0 0xEF>, <&audma1 0xF0>;
2164 dma-n 2159 dma-names = "rx", "tx";
2165 }; 2160 };
2166 ssiu30: ssiu- 2161 ssiu30: ssiu-24 {
2167 dmas 2162 dmas = <&audma0 0x6f>, <&audma1 0x70>;
2168 dma-n 2163 dma-names = "rx", "tx";
2169 }; 2164 };
2170 ssiu31: ssiu- 2165 ssiu31: ssiu-25 {
2171 dmas 2166 dmas = <&audma0 0x21>, <&audma1 0x22>;
2172 dma-n 2167 dma-names = "rx", "tx";
2173 }; 2168 };
2174 ssiu32: ssiu- 2169 ssiu32: ssiu-26 {
2175 dmas 2170 dmas = <&audma0 0x23>, <&audma1 0x24>;
2176 dma-n 2171 dma-names = "rx", "tx";
2177 }; 2172 };
2178 ssiu33: ssiu- 2173 ssiu33: ssiu-27 {
2179 dmas 2174 dmas = <&audma0 0x25>, <&audma1 0x26>;
2180 dma-n 2175 dma-names = "rx", "tx";
2181 }; 2176 };
2182 ssiu34: ssiu- 2177 ssiu34: ssiu-28 {
2183 dmas 2178 dmas = <&audma0 0x27>, <&audma1 0x28>;
2184 dma-n 2179 dma-names = "rx", "tx";
2185 }; 2180 };
2186 ssiu35: ssiu- 2181 ssiu35: ssiu-29 {
2187 dmas 2182 dmas = <&audma0 0x29>, <&audma1 0x2A>;
2188 dma-n 2183 dma-names = "rx", "tx";
2189 }; 2184 };
2190 ssiu36: ssiu- 2185 ssiu36: ssiu-30 {
2191 dmas 2186 dmas = <&audma0 0x2B>, <&audma1 0x2C>;
2192 dma-n 2187 dma-names = "rx", "tx";
2193 }; 2188 };
2194 ssiu37: ssiu- 2189 ssiu37: ssiu-31 {
2195 dmas 2190 dmas = <&audma0 0x2D>, <&audma1 0x2E>;
2196 dma-n 2191 dma-names = "rx", "tx";
2197 }; 2192 };
2198 ssiu40: ssiu- 2193 ssiu40: ssiu-32 {
2199 dmas 2194 dmas = <&audma0 0x71>, <&audma1 0x72>;
2200 dma-n 2195 dma-names = "rx", "tx";
2201 }; 2196 };
2202 ssiu41: ssiu- 2197 ssiu41: ssiu-33 {
2203 dmas 2198 dmas = <&audma0 0x17>, <&audma1 0x18>;
2204 dma-n 2199 dma-names = "rx", "tx";
2205 }; 2200 };
2206 ssiu42: ssiu- 2201 ssiu42: ssiu-34 {
2207 dmas 2202 dmas = <&audma0 0x19>, <&audma1 0x1A>;
2208 dma-n 2203 dma-names = "rx", "tx";
2209 }; 2204 };
2210 ssiu43: ssiu- 2205 ssiu43: ssiu-35 {
2211 dmas 2206 dmas = <&audma0 0x1B>, <&audma1 0x1C>;
2212 dma-n 2207 dma-names = "rx", "tx";
2213 }; 2208 };
2214 ssiu44: ssiu- 2209 ssiu44: ssiu-36 {
2215 dmas 2210 dmas = <&audma0 0x1D>, <&audma1 0x1E>;
2216 dma-n 2211 dma-names = "rx", "tx";
2217 }; 2212 };
2218 ssiu45: ssiu- 2213 ssiu45: ssiu-37 {
2219 dmas 2214 dmas = <&audma0 0x1F>, <&audma1 0x20>;
2220 dma-n 2215 dma-names = "rx", "tx";
2221 }; 2216 };
2222 ssiu46: ssiu- 2217 ssiu46: ssiu-38 {
2223 dmas 2218 dmas = <&audma0 0x31>, <&audma1 0x32>;
2224 dma-n 2219 dma-names = "rx", "tx";
2225 }; 2220 };
2226 ssiu47: ssiu- 2221 ssiu47: ssiu-39 {
2227 dmas 2222 dmas = <&audma0 0x33>, <&audma1 0x34>;
2228 dma-n 2223 dma-names = "rx", "tx";
2229 }; 2224 };
2230 ssiu50: ssiu- 2225 ssiu50: ssiu-40 {
2231 dmas 2226 dmas = <&audma0 0x73>, <&audma1 0x74>;
2232 dma-n 2227 dma-names = "rx", "tx";
2233 }; 2228 };
2234 ssiu60: ssiu- 2229 ssiu60: ssiu-41 {
2235 dmas 2230 dmas = <&audma0 0x75>, <&audma1 0x76>;
2236 dma-n 2231 dma-names = "rx", "tx";
2237 }; 2232 };
2238 ssiu70: ssiu- 2233 ssiu70: ssiu-42 {
2239 dmas 2234 dmas = <&audma0 0x79>, <&audma1 0x7a>;
2240 dma-n 2235 dma-names = "rx", "tx";
2241 }; 2236 };
2242 ssiu80: ssiu- 2237 ssiu80: ssiu-43 {
2243 dmas 2238 dmas = <&audma0 0x7b>, <&audma1 0x7c>;
2244 dma-n 2239 dma-names = "rx", "tx";
2245 }; 2240 };
2246 ssiu90: ssiu- 2241 ssiu90: ssiu-44 {
2247 dmas 2242 dmas = <&audma0 0x7d>, <&audma1 0x7e>;
2248 dma-n 2243 dma-names = "rx", "tx";
2249 }; 2244 };
2250 ssiu91: ssiu- 2245 ssiu91: ssiu-45 {
2251 dmas 2246 dmas = <&audma0 0x7F>, <&audma1 0x80>;
2252 dma-n 2247 dma-names = "rx", "tx";
2253 }; 2248 };
2254 ssiu92: ssiu- 2249 ssiu92: ssiu-46 {
2255 dmas 2250 dmas = <&audma0 0x81>, <&audma1 0x82>;
2256 dma-n 2251 dma-names = "rx", "tx";
2257 }; 2252 };
2258 ssiu93: ssiu- 2253 ssiu93: ssiu-47 {
2259 dmas 2254 dmas = <&audma0 0x83>, <&audma1 0x84>;
2260 dma-n 2255 dma-names = "rx", "tx";
2261 }; 2256 };
2262 ssiu94: ssiu- 2257 ssiu94: ssiu-48 {
2263 dmas 2258 dmas = <&audma0 0xA3>, <&audma1 0xA4>;
2264 dma-n 2259 dma-names = "rx", "tx";
2265 }; 2260 };
2266 ssiu95: ssiu- 2261 ssiu95: ssiu-49 {
2267 dmas 2262 dmas = <&audma0 0xA5>, <&audma1 0xA6>;
2268 dma-n 2263 dma-names = "rx", "tx";
2269 }; 2264 };
2270 ssiu96: ssiu- 2265 ssiu96: ssiu-50 {
2271 dmas 2266 dmas = <&audma0 0xA7>, <&audma1 0xA8>;
2272 dma-n 2267 dma-names = "rx", "tx";
2273 }; 2268 };
2274 ssiu97: ssiu- 2269 ssiu97: ssiu-51 {
2275 dmas 2270 dmas = <&audma0 0xA9>, <&audma1 0xAA>;
2276 dma-n 2271 dma-names = "rx", "tx";
2277 }; 2272 };
2278 }; 2273 };
2279 }; 2274 };
2280 2275
2281 mlp: mlp@ec520000 { 2276 mlp: mlp@ec520000 {
2282 compatible = "renesas 2277 compatible = "renesas,r8a7796-mlp",
2283 "renesas 2278 "renesas,rcar-gen3-mlp";
2284 reg = <0 0xec520000 0 2279 reg = <0 0xec520000 0 0x800>;
2285 interrupts = <GIC_SPI 2280 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
2286 <GIC_SPI 385 2281 <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>;
2287 clocks = <&cpg CPG_MO 2282 clocks = <&cpg CPG_MOD 802>;
2288 power-domains = <&sys 2283 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2289 resets = <&cpg 802>; 2284 resets = <&cpg 802>;
2290 status = "disabled"; 2285 status = "disabled";
2291 }; 2286 };
2292 2287
2293 audma0: dma-controller@ec7000 2288 audma0: dma-controller@ec700000 {
2294 compatible = "renesas 2289 compatible = "renesas,dmac-r8a7796",
2295 "renesas 2290 "renesas,rcar-dmac";
2296 reg = <0 0xec700000 0 2291 reg = <0 0xec700000 0 0x10000>;
2297 interrupts = <GIC_SPI 2292 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
2298 <GIC_SPI 2293 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
2299 <GIC_SPI 2294 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
2300 <GIC_SPI 2295 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
2301 <GIC_SPI 2296 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
2302 <GIC_SPI 2297 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
2303 <GIC_SPI 2298 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
2304 <GIC_SPI 2299 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
2305 <GIC_SPI 2300 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
2306 <GIC_SPI 2301 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
2307 <GIC_SPI 2302 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
2308 <GIC_SPI 2303 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
2309 <GIC_SPI 2304 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
2310 <GIC_SPI 2305 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
2311 <GIC_SPI 2306 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
2312 <GIC_SPI 2307 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
2313 <GIC_SPI 2308 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
2314 interrupt-names = "er 2309 interrupt-names = "error",
2315 "ch0" 2310 "ch0", "ch1", "ch2", "ch3",
2316 "ch4" 2311 "ch4", "ch5", "ch6", "ch7",
2317 "ch8" 2312 "ch8", "ch9", "ch10", "ch11",
2318 "ch12 2313 "ch12", "ch13", "ch14", "ch15";
2319 clocks = <&cpg CPG_MO 2314 clocks = <&cpg CPG_MOD 502>;
2320 clock-names = "fck"; 2315 clock-names = "fck";
2321 power-domains = <&sys 2316 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2322 resets = <&cpg 502>; 2317 resets = <&cpg 502>;
2323 #dma-cells = <1>; 2318 #dma-cells = <1>;
2324 dma-channels = <16>; 2319 dma-channels = <16>;
2325 iommus = <&ipmmu_mp 0 2320 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
2326 <&ipmmu_mp 2>, 2321 <&ipmmu_mp 2>, <&ipmmu_mp 3>,
2327 <&ipmmu_mp 4>, 2322 <&ipmmu_mp 4>, <&ipmmu_mp 5>,
2328 <&ipmmu_mp 6>, 2323 <&ipmmu_mp 6>, <&ipmmu_mp 7>,
2329 <&ipmmu_mp 8>, 2324 <&ipmmu_mp 8>, <&ipmmu_mp 9>,
2330 <&ipmmu_mp 10> 2325 <&ipmmu_mp 10>, <&ipmmu_mp 11>,
2331 <&ipmmu_mp 12> 2326 <&ipmmu_mp 12>, <&ipmmu_mp 13>,
2332 <&ipmmu_mp 14> 2327 <&ipmmu_mp 14>, <&ipmmu_mp 15>;
2333 }; 2328 };
2334 2329
2335 audma1: dma-controller@ec7200 2330 audma1: dma-controller@ec720000 {
2336 compatible = "renesas 2331 compatible = "renesas,dmac-r8a7796",
2337 "renesas 2332 "renesas,rcar-dmac";
2338 reg = <0 0xec720000 0 2333 reg = <0 0xec720000 0 0x10000>;
2339 interrupts = <GIC_SPI 2334 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
2340 <GIC_SPI 2335 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
2341 <GIC_SPI 2336 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
2342 <GIC_SPI 2337 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
2343 <GIC_SPI 2338 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
2344 <GIC_SPI 2339 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
2345 <GIC_SPI 2340 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
2346 <GIC_SPI 2341 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
2347 <GIC_SPI 2342 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
2348 <GIC_SPI 2343 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
2349 <GIC_SPI 2344 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
2350 <GIC_SPI 2345 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
2351 <GIC_SPI 2346 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
2352 <GIC_SPI 2347 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
2353 <GIC_SPI 2348 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
2354 <GIC_SPI 2349 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
2355 <GIC_SPI 2350 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
2356 interrupt-names = "er 2351 interrupt-names = "error",
2357 "ch0" 2352 "ch0", "ch1", "ch2", "ch3",
2358 "ch4" 2353 "ch4", "ch5", "ch6", "ch7",
2359 "ch8" 2354 "ch8", "ch9", "ch10", "ch11",
2360 "ch12 2355 "ch12", "ch13", "ch14", "ch15";
2361 clocks = <&cpg CPG_MO 2356 clocks = <&cpg CPG_MOD 501>;
2362 clock-names = "fck"; 2357 clock-names = "fck";
2363 power-domains = <&sys 2358 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2364 resets = <&cpg 501>; 2359 resets = <&cpg 501>;
2365 #dma-cells = <1>; 2360 #dma-cells = <1>;
2366 dma-channels = <16>; 2361 dma-channels = <16>;
2367 iommus = <&ipmmu_mp 1 2362 iommus = <&ipmmu_mp 16>, <&ipmmu_mp 17>,
2368 <&ipmmu_mp 18> 2363 <&ipmmu_mp 18>, <&ipmmu_mp 19>,
2369 <&ipmmu_mp 20> 2364 <&ipmmu_mp 20>, <&ipmmu_mp 21>,
2370 <&ipmmu_mp 22> 2365 <&ipmmu_mp 22>, <&ipmmu_mp 23>,
2371 <&ipmmu_mp 24> 2366 <&ipmmu_mp 24>, <&ipmmu_mp 25>,
2372 <&ipmmu_mp 26> 2367 <&ipmmu_mp 26>, <&ipmmu_mp 27>,
2373 <&ipmmu_mp 28> 2368 <&ipmmu_mp 28>, <&ipmmu_mp 29>,
2374 <&ipmmu_mp 30> 2369 <&ipmmu_mp 30>, <&ipmmu_mp 31>;
2375 }; 2370 };
2376 2371
2377 xhci0: usb@ee000000 { 2372 xhci0: usb@ee000000 {
2378 compatible = "renesas 2373 compatible = "renesas,xhci-r8a7796",
2379 "renesas 2374 "renesas,rcar-gen3-xhci";
2380 reg = <0 0xee000000 0 2375 reg = <0 0xee000000 0 0xc00>;
2381 interrupts = <GIC_SPI 2376 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
2382 clocks = <&cpg CPG_MO 2377 clocks = <&cpg CPG_MOD 328>;
2383 power-domains = <&sys 2378 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2384 resets = <&cpg 328>; 2379 resets = <&cpg 328>;
2385 status = "disabled"; 2380 status = "disabled";
2386 }; 2381 };
2387 2382
2388 usb3_peri0: usb@ee020000 { 2383 usb3_peri0: usb@ee020000 {
2389 compatible = "renesas 2384 compatible = "renesas,r8a7796-usb3-peri",
2390 "renesas 2385 "renesas,rcar-gen3-usb3-peri";
2391 reg = <0 0xee020000 0 2386 reg = <0 0xee020000 0 0x400>;
2392 interrupts = <GIC_SPI 2387 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
2393 clocks = <&cpg CPG_MO 2388 clocks = <&cpg CPG_MOD 328>;
2394 power-domains = <&sys 2389 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2395 resets = <&cpg 328>; 2390 resets = <&cpg 328>;
2396 status = "disabled"; 2391 status = "disabled";
2397 }; 2392 };
2398 2393
2399 ohci0: usb@ee080000 { 2394 ohci0: usb@ee080000 {
2400 compatible = "generic 2395 compatible = "generic-ohci";
2401 reg = <0 0xee080000 0 2396 reg = <0 0xee080000 0 0x100>;
2402 interrupts = <GIC_SPI 2397 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
2403 clocks = <&cpg CPG_MO 2398 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
2404 phys = <&usb2_phy0 1> 2399 phys = <&usb2_phy0 1>;
2405 phy-names = "usb"; 2400 phy-names = "usb";
2406 power-domains = <&sys 2401 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2407 resets = <&cpg 703>, 2402 resets = <&cpg 703>, <&cpg 704>;
2408 status = "disabled"; 2403 status = "disabled";
2409 }; 2404 };
2410 2405
2411 ohci1: usb@ee0a0000 { 2406 ohci1: usb@ee0a0000 {
2412 compatible = "generic 2407 compatible = "generic-ohci";
2413 reg = <0 0xee0a0000 0 2408 reg = <0 0xee0a0000 0 0x100>;
2414 interrupts = <GIC_SPI 2409 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
2415 clocks = <&cpg CPG_MO 2410 clocks = <&cpg CPG_MOD 702>;
2416 phys = <&usb2_phy1 1> 2411 phys = <&usb2_phy1 1>;
2417 phy-names = "usb"; 2412 phy-names = "usb";
2418 power-domains = <&sys 2413 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2419 resets = <&cpg 702>; 2414 resets = <&cpg 702>;
2420 status = "disabled"; 2415 status = "disabled";
2421 }; 2416 };
2422 2417
2423 ehci0: usb@ee080100 { 2418 ehci0: usb@ee080100 {
2424 compatible = "generic 2419 compatible = "generic-ehci";
2425 reg = <0 0xee080100 0 2420 reg = <0 0xee080100 0 0x100>;
2426 interrupts = <GIC_SPI 2421 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
2427 clocks = <&cpg CPG_MO 2422 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
2428 phys = <&usb2_phy0 2> 2423 phys = <&usb2_phy0 2>;
2429 phy-names = "usb"; 2424 phy-names = "usb";
2430 companion = <&ohci0>; 2425 companion = <&ohci0>;
2431 power-domains = <&sys 2426 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2432 resets = <&cpg 703>, 2427 resets = <&cpg 703>, <&cpg 704>;
2433 status = "disabled"; 2428 status = "disabled";
2434 }; 2429 };
2435 2430
2436 ehci1: usb@ee0a0100 { 2431 ehci1: usb@ee0a0100 {
2437 compatible = "generic 2432 compatible = "generic-ehci";
2438 reg = <0 0xee0a0100 0 2433 reg = <0 0xee0a0100 0 0x100>;
2439 interrupts = <GIC_SPI 2434 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
2440 clocks = <&cpg CPG_MO 2435 clocks = <&cpg CPG_MOD 702>;
2441 phys = <&usb2_phy1 2> 2436 phys = <&usb2_phy1 2>;
2442 phy-names = "usb"; 2437 phy-names = "usb";
2443 companion = <&ohci1>; 2438 companion = <&ohci1>;
2444 power-domains = <&sys 2439 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2445 resets = <&cpg 702>; 2440 resets = <&cpg 702>;
2446 status = "disabled"; 2441 status = "disabled";
2447 }; 2442 };
2448 2443
2449 usb2_phy0: usb-phy@ee080200 { 2444 usb2_phy0: usb-phy@ee080200 {
2450 compatible = "renesas 2445 compatible = "renesas,usb2-phy-r8a7796",
2451 "renesas 2446 "renesas,rcar-gen3-usb2-phy";
2452 reg = <0 0xee080200 0 2447 reg = <0 0xee080200 0 0x700>;
2453 interrupts = <GIC_SPI 2448 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
2454 clocks = <&cpg CPG_MO 2449 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
2455 power-domains = <&sys 2450 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2456 resets = <&cpg 703>, 2451 resets = <&cpg 703>, <&cpg 704>;
2457 #phy-cells = <1>; 2452 #phy-cells = <1>;
2458 status = "disabled"; 2453 status = "disabled";
2459 }; 2454 };
2460 2455
2461 usb2_phy1: usb-phy@ee0a0200 { 2456 usb2_phy1: usb-phy@ee0a0200 {
2462 compatible = "renesas 2457 compatible = "renesas,usb2-phy-r8a7796",
2463 "renesas 2458 "renesas,rcar-gen3-usb2-phy";
2464 reg = <0 0xee0a0200 0 2459 reg = <0 0xee0a0200 0 0x700>;
2465 clocks = <&cpg CPG_MO 2460 clocks = <&cpg CPG_MOD 702>;
2466 power-domains = <&sys 2461 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2467 resets = <&cpg 702>; 2462 resets = <&cpg 702>;
2468 #phy-cells = <1>; 2463 #phy-cells = <1>;
2469 status = "disabled"; 2464 status = "disabled";
2470 }; 2465 };
2471 2466
2472 sdhi0: mmc@ee100000 { 2467 sdhi0: mmc@ee100000 {
2473 compatible = "renesas 2468 compatible = "renesas,sdhi-r8a7796",
2474 "renesas 2469 "renesas,rcar-gen3-sdhi";
2475 reg = <0 0xee100000 0 2470 reg = <0 0xee100000 0 0x2000>;
2476 interrupts = <GIC_SPI 2471 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
2477 clocks = <&cpg CPG_MO 2472 clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A7796_CLK_SD0H>;
2478 clock-names = "core", 2473 clock-names = "core", "clkh";
2479 max-frequency = <2000 2474 max-frequency = <200000000>;
2480 power-domains = <&sys 2475 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2481 resets = <&cpg 314>; 2476 resets = <&cpg 314>;
2482 iommus = <&ipmmu_ds1 2477 iommus = <&ipmmu_ds1 32>;
2483 status = "disabled"; 2478 status = "disabled";
2484 }; 2479 };
2485 2480
2486 sdhi1: mmc@ee120000 { 2481 sdhi1: mmc@ee120000 {
2487 compatible = "renesas 2482 compatible = "renesas,sdhi-r8a7796",
2488 "renesas 2483 "renesas,rcar-gen3-sdhi";
2489 reg = <0 0xee120000 0 2484 reg = <0 0xee120000 0 0x2000>;
2490 interrupts = <GIC_SPI 2485 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
2491 clocks = <&cpg CPG_MO 2486 clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A7796_CLK_SD1H>;
2492 clock-names = "core", 2487 clock-names = "core", "clkh";
2493 max-frequency = <2000 2488 max-frequency = <200000000>;
2494 power-domains = <&sys 2489 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2495 resets = <&cpg 313>; 2490 resets = <&cpg 313>;
2496 iommus = <&ipmmu_ds1 2491 iommus = <&ipmmu_ds1 33>;
2497 status = "disabled"; 2492 status = "disabled";
2498 }; 2493 };
2499 2494
2500 sdhi2: mmc@ee140000 { 2495 sdhi2: mmc@ee140000 {
2501 compatible = "renesas 2496 compatible = "renesas,sdhi-r8a7796",
2502 "renesas 2497 "renesas,rcar-gen3-sdhi";
2503 reg = <0 0xee140000 0 2498 reg = <0 0xee140000 0 0x2000>;
2504 interrupts = <GIC_SPI 2499 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
2505 clocks = <&cpg CPG_MO 2500 clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A7796_CLK_SD2H>;
2506 clock-names = "core", 2501 clock-names = "core", "clkh";
2507 max-frequency = <2000 2502 max-frequency = <200000000>;
2508 power-domains = <&sys 2503 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2509 resets = <&cpg 312>; 2504 resets = <&cpg 312>;
2510 iommus = <&ipmmu_ds1 2505 iommus = <&ipmmu_ds1 34>;
2511 status = "disabled"; 2506 status = "disabled";
2512 }; 2507 };
2513 2508
2514 sdhi3: mmc@ee160000 { 2509 sdhi3: mmc@ee160000 {
2515 compatible = "renesas 2510 compatible = "renesas,sdhi-r8a7796",
2516 "renesas 2511 "renesas,rcar-gen3-sdhi";
2517 reg = <0 0xee160000 0 2512 reg = <0 0xee160000 0 0x2000>;
2518 interrupts = <GIC_SPI 2513 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
2519 clocks = <&cpg CPG_MO 2514 clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A7796_CLK_SD3H>;
2520 clock-names = "core", 2515 clock-names = "core", "clkh";
2521 max-frequency = <2000 2516 max-frequency = <200000000>;
2522 power-domains = <&sys 2517 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2523 resets = <&cpg 311>; 2518 resets = <&cpg 311>;
2524 iommus = <&ipmmu_ds1 2519 iommus = <&ipmmu_ds1 35>;
2525 status = "disabled"; 2520 status = "disabled";
2526 }; 2521 };
2527 2522
2528 rpc: spi@ee200000 { 2523 rpc: spi@ee200000 {
2529 compatible = "renesas 2524 compatible = "renesas,r8a7796-rpc-if",
2530 "renesas 2525 "renesas,rcar-gen3-rpc-if";
2531 reg = <0 0xee200000 0 2526 reg = <0 0xee200000 0 0x200>,
2532 <0 0x08000000 0 2527 <0 0x08000000 0 0x04000000>,
2533 <0 0xee208000 0 2528 <0 0xee208000 0 0x100>;
2534 reg-names = "regs", " 2529 reg-names = "regs", "dirmap", "wbuf";
2535 interrupts = <GIC_SPI 2530 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
2536 clocks = <&cpg CPG_MO 2531 clocks = <&cpg CPG_MOD 917>;
2537 power-domains = <&sys 2532 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2538 resets = <&cpg 917>; 2533 resets = <&cpg 917>;
2539 #address-cells = <1>; 2534 #address-cells = <1>;
2540 #size-cells = <0>; 2535 #size-cells = <0>;
2541 status = "disabled"; 2536 status = "disabled";
2542 }; 2537 };
2543 2538
2544 gic: interrupt-controller@f10 2539 gic: interrupt-controller@f1010000 {
2545 compatible = "arm,gic 2540 compatible = "arm,gic-400";
2546 #interrupt-cells = <3 2541 #interrupt-cells = <3>;
2547 #address-cells = <0>; 2542 #address-cells = <0>;
2548 interrupt-controller; 2543 interrupt-controller;
2549 reg = <0x0 0xf1010000 2544 reg = <0x0 0xf1010000 0 0x1000>,
2550 <0x0 0xf1020000 2545 <0x0 0xf1020000 0 0x20000>,
2551 <0x0 0xf1040000 2546 <0x0 0xf1040000 0 0x20000>,
2552 <0x0 0xf1060000 2547 <0x0 0xf1060000 0 0x20000>;
2553 interrupts = <GIC_PPI 2548 interrupts = <GIC_PPI 9
2554 (GIC_ 2549 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
2555 clocks = <&cpg CPG_MO 2550 clocks = <&cpg CPG_MOD 408>;
2556 clock-names = "clk"; 2551 clock-names = "clk";
2557 power-domains = <&sys 2552 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2558 resets = <&cpg 408>; 2553 resets = <&cpg 408>;
2559 }; 2554 };
2560 2555
2561 pciec0: pcie@fe000000 { 2556 pciec0: pcie@fe000000 {
2562 compatible = "renesas 2557 compatible = "renesas,pcie-r8a7796",
2563 "renesas 2558 "renesas,pcie-rcar-gen3";
2564 reg = <0 0xfe000000 0 2559 reg = <0 0xfe000000 0 0x80000>;
2565 #address-cells = <3>; 2560 #address-cells = <3>;
2566 #size-cells = <2>; 2561 #size-cells = <2>;
2567 bus-range = <0x00 0xf 2562 bus-range = <0x00 0xff>;
2568 device_type = "pci"; 2563 device_type = "pci";
2569 ranges = <0x01000000 2564 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
2570 <0x02000000 2565 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
2571 <0x02000000 2566 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
2572 <0x42000000 2567 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
2573 /* Map all possible D !! 2568 /* Map all possible DDR as inbound ranges */
2574 dma-ranges = <0x42000 !! 2569 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
2575 interrupts = <GIC_SPI 2570 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
2576 <GIC_SPI 117 2571 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
2577 <GIC_SPI 118 2572 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
2578 #interrupt-cells = <1 2573 #interrupt-cells = <1>;
2579 interrupt-map-mask = 2574 interrupt-map-mask = <0 0 0 0>;
2580 interrupt-map = <0 0 2575 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
2581 clocks = <&cpg CPG_MO 2576 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
2582 clock-names = "pcie", 2577 clock-names = "pcie", "pcie_bus";
2583 power-domains = <&sys 2578 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2584 resets = <&cpg 319>; 2579 resets = <&cpg 319>;
2585 iommu-map = <0 &ipmmu <<
2586 iommu-map-mask = <0>; <<
2587 status = "disabled"; 2580 status = "disabled";
2588 }; 2581 };
2589 2582
2590 pciec1: pcie@ee800000 { 2583 pciec1: pcie@ee800000 {
2591 compatible = "renesas 2584 compatible = "renesas,pcie-r8a7796",
2592 "renesas 2585 "renesas,pcie-rcar-gen3";
2593 reg = <0 0xee800000 0 2586 reg = <0 0xee800000 0 0x80000>;
2594 #address-cells = <3>; 2587 #address-cells = <3>;
2595 #size-cells = <2>; 2588 #size-cells = <2>;
2596 bus-range = <0x00 0xf 2589 bus-range = <0x00 0xff>;
2597 device_type = "pci"; 2590 device_type = "pci";
2598 ranges = <0x01000000 2591 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
2599 <0x02000000 2592 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
2600 <0x02000000 2593 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
2601 <0x42000000 2594 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
2602 /* Map all possible D !! 2595 /* Map all possible DDR as inbound ranges */
2603 dma-ranges = <0x42000 !! 2596 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
2604 interrupts = <GIC_SPI 2597 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
2605 <GIC_SPI 149 2598 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
2606 <GIC_SPI 150 2599 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
2607 #interrupt-cells = <1 2600 #interrupt-cells = <1>;
2608 interrupt-map-mask = 2601 interrupt-map-mask = <0 0 0 0>;
2609 interrupt-map = <0 0 2602 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2610 clocks = <&cpg CPG_MO 2603 clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>;
2611 clock-names = "pcie", 2604 clock-names = "pcie", "pcie_bus";
2612 power-domains = <&sys 2605 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2613 resets = <&cpg 318>; 2606 resets = <&cpg 318>;
2614 iommu-map = <0 &ipmmu <<
2615 iommu-map-mask = <0>; <<
2616 status = "disabled"; 2607 status = "disabled";
2617 }; 2608 };
2618 2609
2619 imr-lx4@fe860000 { 2610 imr-lx4@fe860000 {
2620 compatible = "renesas 2611 compatible = "renesas,r8a7796-imr-lx4",
2621 "renesas 2612 "renesas,imr-lx4";
2622 reg = <0 0xfe860000 0 2613 reg = <0 0xfe860000 0 0x2000>;
2623 interrupts = <GIC_SPI 2614 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
2624 clocks = <&cpg CPG_MO 2615 clocks = <&cpg CPG_MOD 823>;
2625 power-domains = <&sys 2616 power-domains = <&sysc R8A7796_PD_A3VC>;
2626 resets = <&cpg 823>; 2617 resets = <&cpg 823>;
2627 }; 2618 };
2628 2619
2629 imr-lx4@fe870000 { 2620 imr-lx4@fe870000 {
2630 compatible = "renesas 2621 compatible = "renesas,r8a7796-imr-lx4",
2631 "renesas 2622 "renesas,imr-lx4";
2632 reg = <0 0xfe870000 0 2623 reg = <0 0xfe870000 0 0x2000>;
2633 interrupts = <GIC_SPI 2624 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
2634 clocks = <&cpg CPG_MO 2625 clocks = <&cpg CPG_MOD 822>;
2635 power-domains = <&sys 2626 power-domains = <&sysc R8A7796_PD_A3VC>;
2636 resets = <&cpg 822>; 2627 resets = <&cpg 822>;
2637 }; 2628 };
2638 2629
2639 fdp1@fe940000 { 2630 fdp1@fe940000 {
2640 compatible = "renesas 2631 compatible = "renesas,fdp1";
2641 reg = <0 0xfe940000 0 2632 reg = <0 0xfe940000 0 0x2400>;
2642 interrupts = <GIC_SPI 2633 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
2643 clocks = <&cpg CPG_MO 2634 clocks = <&cpg CPG_MOD 119>;
2644 power-domains = <&sys 2635 power-domains = <&sysc R8A7796_PD_A3VC>;
2645 resets = <&cpg 119>; 2636 resets = <&cpg 119>;
2646 renesas,fcp = <&fcpf0 2637 renesas,fcp = <&fcpf0>;
2647 }; 2638 };
2648 2639
2649 fcpf0: fcp@fe950000 { 2640 fcpf0: fcp@fe950000 {
2650 compatible = "renesas 2641 compatible = "renesas,fcpf";
2651 reg = <0 0xfe950000 0 2642 reg = <0 0xfe950000 0 0x200>;
2652 clocks = <&cpg CPG_MO 2643 clocks = <&cpg CPG_MOD 615>;
2653 power-domains = <&sys 2644 power-domains = <&sysc R8A7796_PD_A3VC>;
2654 resets = <&cpg 615>; 2645 resets = <&cpg 615>;
2655 iommus = <&ipmmu_vc0 <<
2656 }; 2646 };
2657 2647
2658 fcpvb0: fcp@fe96f000 { 2648 fcpvb0: fcp@fe96f000 {
2659 compatible = "renesas 2649 compatible = "renesas,fcpv";
2660 reg = <0 0xfe96f000 0 2650 reg = <0 0xfe96f000 0 0x200>;
2661 clocks = <&cpg CPG_MO 2651 clocks = <&cpg CPG_MOD 607>;
2662 power-domains = <&sys 2652 power-domains = <&sysc R8A7796_PD_A3VC>;
2663 resets = <&cpg 607>; 2653 resets = <&cpg 607>;
2664 iommus = <&ipmmu_vi0 <<
2665 }; 2654 };
2666 2655
2667 fcpvi0: fcp@fe9af000 { 2656 fcpvi0: fcp@fe9af000 {
2668 compatible = "renesas 2657 compatible = "renesas,fcpv";
2669 reg = <0 0xfe9af000 0 2658 reg = <0 0xfe9af000 0 0x200>;
2670 clocks = <&cpg CPG_MO 2659 clocks = <&cpg CPG_MOD 611>;
2671 power-domains = <&sys 2660 power-domains = <&sysc R8A7796_PD_A3VC>;
2672 resets = <&cpg 611>; 2661 resets = <&cpg 611>;
2673 iommus = <&ipmmu_vc0 2662 iommus = <&ipmmu_vc0 19>;
2674 }; 2663 };
2675 2664
2676 fcpvd0: fcp@fea27000 { 2665 fcpvd0: fcp@fea27000 {
2677 compatible = "renesas 2666 compatible = "renesas,fcpv";
2678 reg = <0 0xfea27000 0 2667 reg = <0 0xfea27000 0 0x200>;
2679 clocks = <&cpg CPG_MO 2668 clocks = <&cpg CPG_MOD 603>;
2680 power-domains = <&sys 2669 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2681 resets = <&cpg 603>; 2670 resets = <&cpg 603>;
2682 iommus = <&ipmmu_vi0 2671 iommus = <&ipmmu_vi0 8>;
2683 }; 2672 };
2684 2673
2685 fcpvd1: fcp@fea2f000 { 2674 fcpvd1: fcp@fea2f000 {
2686 compatible = "renesas 2675 compatible = "renesas,fcpv";
2687 reg = <0 0xfea2f000 0 2676 reg = <0 0xfea2f000 0 0x200>;
2688 clocks = <&cpg CPG_MO 2677 clocks = <&cpg CPG_MOD 602>;
2689 power-domains = <&sys 2678 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2690 resets = <&cpg 602>; 2679 resets = <&cpg 602>;
2691 iommus = <&ipmmu_vi0 2680 iommus = <&ipmmu_vi0 9>;
2692 }; 2681 };
2693 2682
2694 fcpvd2: fcp@fea37000 { 2683 fcpvd2: fcp@fea37000 {
2695 compatible = "renesas 2684 compatible = "renesas,fcpv";
2696 reg = <0 0xfea37000 0 2685 reg = <0 0xfea37000 0 0x200>;
2697 clocks = <&cpg CPG_MO 2686 clocks = <&cpg CPG_MOD 601>;
2698 power-domains = <&sys 2687 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2699 resets = <&cpg 601>; 2688 resets = <&cpg 601>;
2700 iommus = <&ipmmu_vi0 2689 iommus = <&ipmmu_vi0 10>;
2701 }; 2690 };
2702 2691
2703 vspb: vsp@fe960000 { 2692 vspb: vsp@fe960000 {
2704 compatible = "renesas 2693 compatible = "renesas,vsp2";
2705 reg = <0 0xfe960000 0 2694 reg = <0 0xfe960000 0 0x8000>;
2706 interrupts = <GIC_SPI 2695 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
2707 clocks = <&cpg CPG_MO 2696 clocks = <&cpg CPG_MOD 626>;
2708 power-domains = <&sys 2697 power-domains = <&sysc R8A7796_PD_A3VC>;
2709 resets = <&cpg 626>; 2698 resets = <&cpg 626>;
2710 2699
2711 renesas,fcp = <&fcpvb 2700 renesas,fcp = <&fcpvb0>;
2712 }; 2701 };
2713 2702
2714 vspd0: vsp@fea20000 { 2703 vspd0: vsp@fea20000 {
2715 compatible = "renesas 2704 compatible = "renesas,vsp2";
2716 reg = <0 0xfea20000 0 2705 reg = <0 0xfea20000 0 0x5000>;
2717 interrupts = <GIC_SPI 2706 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
2718 clocks = <&cpg CPG_MO 2707 clocks = <&cpg CPG_MOD 623>;
2719 power-domains = <&sys 2708 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2720 resets = <&cpg 623>; 2709 resets = <&cpg 623>;
2721 2710
2722 renesas,fcp = <&fcpvd 2711 renesas,fcp = <&fcpvd0>;
2723 }; 2712 };
2724 2713
2725 vspd1: vsp@fea28000 { 2714 vspd1: vsp@fea28000 {
2726 compatible = "renesas 2715 compatible = "renesas,vsp2";
2727 reg = <0 0xfea28000 0 2716 reg = <0 0xfea28000 0 0x5000>;
2728 interrupts = <GIC_SPI 2717 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
2729 clocks = <&cpg CPG_MO 2718 clocks = <&cpg CPG_MOD 622>;
2730 power-domains = <&sys 2719 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2731 resets = <&cpg 622>; 2720 resets = <&cpg 622>;
2732 2721
2733 renesas,fcp = <&fcpvd 2722 renesas,fcp = <&fcpvd1>;
2734 }; 2723 };
2735 2724
2736 vspd2: vsp@fea30000 { 2725 vspd2: vsp@fea30000 {
2737 compatible = "renesas 2726 compatible = "renesas,vsp2";
2738 reg = <0 0xfea30000 0 2727 reg = <0 0xfea30000 0 0x5000>;
2739 interrupts = <GIC_SPI 2728 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
2740 clocks = <&cpg CPG_MO 2729 clocks = <&cpg CPG_MOD 621>;
2741 power-domains = <&sys 2730 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2742 resets = <&cpg 621>; 2731 resets = <&cpg 621>;
2743 2732
2744 renesas,fcp = <&fcpvd 2733 renesas,fcp = <&fcpvd2>;
2745 }; 2734 };
2746 2735
2747 vspi0: vsp@fe9a0000 { 2736 vspi0: vsp@fe9a0000 {
2748 compatible = "renesas 2737 compatible = "renesas,vsp2";
2749 reg = <0 0xfe9a0000 0 2738 reg = <0 0xfe9a0000 0 0x8000>;
2750 interrupts = <GIC_SPI 2739 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
2751 clocks = <&cpg CPG_MO 2740 clocks = <&cpg CPG_MOD 631>;
2752 power-domains = <&sys 2741 power-domains = <&sysc R8A7796_PD_A3VC>;
2753 resets = <&cpg 631>; 2742 resets = <&cpg 631>;
2754 2743
2755 renesas,fcp = <&fcpvi 2744 renesas,fcp = <&fcpvi0>;
2756 }; 2745 };
2757 2746
2758 cmm0: cmm@fea40000 { 2747 cmm0: cmm@fea40000 {
2759 compatible = "renesas 2748 compatible = "renesas,r8a7796-cmm",
2760 "renesas 2749 "renesas,rcar-gen3-cmm";
2761 reg = <0 0xfea40000 0 2750 reg = <0 0xfea40000 0 0x1000>;
2762 power-domains = <&sys 2751 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2763 clocks = <&cpg CPG_MO 2752 clocks = <&cpg CPG_MOD 711>;
2764 resets = <&cpg 711>; 2753 resets = <&cpg 711>;
2765 }; 2754 };
2766 2755
2767 cmm1: cmm@fea50000 { 2756 cmm1: cmm@fea50000 {
2768 compatible = "renesas 2757 compatible = "renesas,r8a7796-cmm",
2769 "renesas 2758 "renesas,rcar-gen3-cmm";
2770 reg = <0 0xfea50000 0 2759 reg = <0 0xfea50000 0 0x1000>;
2771 power-domains = <&sys 2760 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2772 clocks = <&cpg CPG_MO 2761 clocks = <&cpg CPG_MOD 710>;
2773 resets = <&cpg 710>; 2762 resets = <&cpg 710>;
2774 }; 2763 };
2775 2764
2776 cmm2: cmm@fea60000 { 2765 cmm2: cmm@fea60000 {
2777 compatible = "renesas 2766 compatible = "renesas,r8a7796-cmm",
2778 "renesas 2767 "renesas,rcar-gen3-cmm";
2779 reg = <0 0xfea60000 0 2768 reg = <0 0xfea60000 0 0x1000>;
2780 power-domains = <&sys 2769 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2781 clocks = <&cpg CPG_MO 2770 clocks = <&cpg CPG_MOD 709>;
2782 resets = <&cpg 709>; 2771 resets = <&cpg 709>;
2783 }; 2772 };
2784 2773
2785 csi20: csi2@fea80000 { 2774 csi20: csi2@fea80000 {
2786 compatible = "renesas 2775 compatible = "renesas,r8a7796-csi2";
2787 reg = <0 0xfea80000 0 2776 reg = <0 0xfea80000 0 0x10000>;
2788 interrupts = <GIC_SPI 2777 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
2789 clocks = <&cpg CPG_MO 2778 clocks = <&cpg CPG_MOD 714>;
2790 power-domains = <&sys 2779 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2791 resets = <&cpg 714>; 2780 resets = <&cpg 714>;
2792 status = "disabled"; 2781 status = "disabled";
2793 2782
2794 ports { 2783 ports {
2795 #address-cell 2784 #address-cells = <1>;
2796 #size-cells = 2785 #size-cells = <0>;
2797 2786
2798 port@0 { 2787 port@0 {
2799 reg = 2788 reg = <0>;
2800 }; 2789 };
2801 2790
2802 port@1 { 2791 port@1 {
2803 #addr 2792 #address-cells = <1>;
2804 #size 2793 #size-cells = <0>;
2805 2794
2806 reg = 2795 reg = <1>;
2807 2796
2808 csi20 2797 csi20vin0: endpoint@0 {
2809 2798 reg = <0>;
2810 2799 remote-endpoint = <&vin0csi20>;
2811 }; 2800 };
2812 csi20 2801 csi20vin1: endpoint@1 {
2813 2802 reg = <1>;
2814 2803 remote-endpoint = <&vin1csi20>;
2815 }; 2804 };
2816 csi20 2805 csi20vin2: endpoint@2 {
2817 2806 reg = <2>;
2818 2807 remote-endpoint = <&vin2csi20>;
2819 }; 2808 };
2820 csi20 2809 csi20vin3: endpoint@3 {
2821 2810 reg = <3>;
2822 2811 remote-endpoint = <&vin3csi20>;
2823 }; 2812 };
2824 csi20 2813 csi20vin4: endpoint@4 {
2825 2814 reg = <4>;
2826 2815 remote-endpoint = <&vin4csi20>;
2827 }; 2816 };
2828 csi20 2817 csi20vin5: endpoint@5 {
2829 2818 reg = <5>;
2830 2819 remote-endpoint = <&vin5csi20>;
2831 }; 2820 };
2832 csi20 2821 csi20vin6: endpoint@6 {
2833 2822 reg = <6>;
2834 2823 remote-endpoint = <&vin6csi20>;
2835 }; 2824 };
2836 csi20 2825 csi20vin7: endpoint@7 {
2837 2826 reg = <7>;
2838 2827 remote-endpoint = <&vin7csi20>;
2839 }; 2828 };
2840 }; 2829 };
2841 }; 2830 };
2842 }; 2831 };
2843 2832
2844 csi40: csi2@feaa0000 { 2833 csi40: csi2@feaa0000 {
2845 compatible = "renesas 2834 compatible = "renesas,r8a7796-csi2";
2846 reg = <0 0xfeaa0000 0 2835 reg = <0 0xfeaa0000 0 0x10000>;
2847 interrupts = <GIC_SPI 2836 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
2848 clocks = <&cpg CPG_MO 2837 clocks = <&cpg CPG_MOD 716>;
2849 power-domains = <&sys 2838 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2850 resets = <&cpg 716>; 2839 resets = <&cpg 716>;
2851 status = "disabled"; 2840 status = "disabled";
2852 2841
2853 ports { 2842 ports {
2854 #address-cell 2843 #address-cells = <1>;
2855 #size-cells = 2844 #size-cells = <0>;
2856 2845
2857 port@0 { 2846 port@0 {
2858 reg = 2847 reg = <0>;
2859 }; 2848 };
2860 2849
2861 port@1 { 2850 port@1 {
2862 #addr 2851 #address-cells = <1>;
2863 #size 2852 #size-cells = <0>;
2864 2853
2865 reg = 2854 reg = <1>;
2866 2855
2867 csi40 2856 csi40vin0: endpoint@0 {
2868 2857 reg = <0>;
2869 2858 remote-endpoint = <&vin0csi40>;
2870 }; 2859 };
2871 csi40 2860 csi40vin1: endpoint@1 {
2872 2861 reg = <1>;
2873 2862 remote-endpoint = <&vin1csi40>;
2874 }; 2863 };
2875 csi40 2864 csi40vin2: endpoint@2 {
2876 2865 reg = <2>;
2877 2866 remote-endpoint = <&vin2csi40>;
2878 }; 2867 };
2879 csi40 2868 csi40vin3: endpoint@3 {
2880 2869 reg = <3>;
2881 2870 remote-endpoint = <&vin3csi40>;
2882 }; 2871 };
2883 csi40 2872 csi40vin4: endpoint@4 {
2884 2873 reg = <4>;
2885 2874 remote-endpoint = <&vin4csi40>;
2886 }; 2875 };
2887 csi40 2876 csi40vin5: endpoint@5 {
2888 2877 reg = <5>;
2889 2878 remote-endpoint = <&vin5csi40>;
2890 }; 2879 };
2891 csi40 2880 csi40vin6: endpoint@6 {
2892 2881 reg = <6>;
2893 2882 remote-endpoint = <&vin6csi40>;
2894 }; 2883 };
2895 csi40 2884 csi40vin7: endpoint@7 {
2896 2885 reg = <7>;
2897 2886 remote-endpoint = <&vin7csi40>;
2898 }; 2887 };
2899 }; 2888 };
2900 2889
2901 }; 2890 };
2902 }; 2891 };
2903 2892
2904 hdmi0: hdmi@fead0000 { 2893 hdmi0: hdmi@fead0000 {
2905 compatible = "renesas 2894 compatible = "renesas,r8a7796-hdmi", "renesas,rcar-gen3-hdmi";
2906 reg = <0 0xfead0000 0 2895 reg = <0 0xfead0000 0 0x10000>;
2907 interrupts = <GIC_SPI 2896 interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
2908 clocks = <&cpg CPG_MO 2897 clocks = <&cpg CPG_MOD 729>, <&cpg CPG_CORE R8A7796_CLK_HDMI>;
2909 clock-names = "iahb", 2898 clock-names = "iahb", "isfr";
2910 power-domains = <&sys 2899 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2911 resets = <&cpg 729>; 2900 resets = <&cpg 729>;
2912 status = "disabled"; 2901 status = "disabled";
2913 2902
2914 ports { 2903 ports {
2915 #address-cell 2904 #address-cells = <1>;
2916 #size-cells = 2905 #size-cells = <0>;
2917 port@0 { 2906 port@0 {
2918 reg = 2907 reg = <0>;
2919 dw_hd 2908 dw_hdmi0_in: endpoint {
2920 2909 remote-endpoint = <&du_out_hdmi0>;
2921 }; 2910 };
2922 }; 2911 };
2923 port@1 { 2912 port@1 {
2924 reg = 2913 reg = <1>;
2925 }; 2914 };
2926 port@2 { 2915 port@2 {
2927 /* HD 2916 /* HDMI sound */
2928 reg = 2917 reg = <2>;
2929 }; 2918 };
2930 }; 2919 };
2931 }; 2920 };
2932 2921
2933 du: display@feb00000 { 2922 du: display@feb00000 {
2934 compatible = "renesas 2923 compatible = "renesas,du-r8a7796";
2935 reg = <0 0xfeb00000 0 2924 reg = <0 0xfeb00000 0 0x70000>;
2936 interrupts = <GIC_SPI 2925 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
2937 <GIC_SPI 2926 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
2938 <GIC_SPI 2927 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
2939 clocks = <&cpg CPG_MO 2928 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
2940 <&cpg CPG_MO 2929 <&cpg CPG_MOD 722>;
2941 clock-names = "du.0", 2930 clock-names = "du.0", "du.1", "du.2";
2942 resets = <&cpg 724>, 2931 resets = <&cpg 724>, <&cpg 722>;
2943 reset-names = "du.0", 2932 reset-names = "du.0", "du.2";
2944 2933
2945 renesas,cmms = <&cmm0 2934 renesas,cmms = <&cmm0>, <&cmm1>, <&cmm2>;
2946 renesas,vsps = <&vspd 2935 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>;
2947 2936
2948 status = "disabled"; 2937 status = "disabled";
2949 2938
2950 ports { 2939 ports {
2951 #address-cell 2940 #address-cells = <1>;
2952 #size-cells = 2941 #size-cells = <0>;
2953 2942
2954 port@0 { 2943 port@0 {
2955 reg = 2944 reg = <0>;
2956 }; 2945 };
2957 port@1 { 2946 port@1 {
2958 reg = 2947 reg = <1>;
2959 du_ou 2948 du_out_hdmi0: endpoint {
2960 2949 remote-endpoint = <&dw_hdmi0_in>;
2961 }; 2950 };
2962 }; 2951 };
2963 port@2 { 2952 port@2 {
2964 reg = 2953 reg = <2>;
2965 du_ou 2954 du_out_lvds0: endpoint {
2966 2955 remote-endpoint = <&lvds0_in>;
2967 }; 2956 };
2968 }; 2957 };
2969 }; 2958 };
2970 }; 2959 };
2971 2960
2972 lvds0: lvds@feb90000 { 2961 lvds0: lvds@feb90000 {
2973 compatible = "renesas 2962 compatible = "renesas,r8a7796-lvds";
2974 reg = <0 0xfeb90000 0 2963 reg = <0 0xfeb90000 0 0x14>;
2975 clocks = <&cpg CPG_MO 2964 clocks = <&cpg CPG_MOD 727>;
2976 power-domains = <&sys 2965 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2977 resets = <&cpg 727>; 2966 resets = <&cpg 727>;
2978 status = "disabled"; 2967 status = "disabled";
2979 2968
2980 ports { 2969 ports {
2981 #address-cell 2970 #address-cells = <1>;
2982 #size-cells = 2971 #size-cells = <0>;
2983 2972
2984 port@0 { 2973 port@0 {
2985 reg = 2974 reg = <0>;
2986 lvds0 2975 lvds0_in: endpoint {
2987 2976 remote-endpoint = <&du_out_lvds0>;
2988 }; 2977 };
2989 }; 2978 };
2990 port@1 { 2979 port@1 {
2991 reg = 2980 reg = <1>;
2992 }; 2981 };
2993 }; 2982 };
2994 }; 2983 };
2995 2984
2996 prr: chipid@fff00044 { 2985 prr: chipid@fff00044 {
2997 compatible = "renesas 2986 compatible = "renesas,prr";
2998 reg = <0 0xfff00044 0 2987 reg = <0 0xfff00044 0 4>;
2999 }; 2988 };
3000 }; 2989 };
3001 2990
3002 thermal-zones { 2991 thermal-zones {
3003 sensor1_thermal: sensor1-ther 2992 sensor1_thermal: sensor1-thermal {
3004 polling-delay-passive 2993 polling-delay-passive = <250>;
3005 polling-delay = <1000 2994 polling-delay = <1000>;
3006 thermal-sensors = <&t 2995 thermal-sensors = <&tsc 0>;
3007 sustainable-power = < 2996 sustainable-power = <3874>;
3008 2997
3009 trips { 2998 trips {
3010 sensor1_crit: 2999 sensor1_crit: sensor1-crit {
3011 tempe 3000 temperature = <120000>;
3012 hyste 3001 hysteresis = <1000>;
3013 type 3002 type = "critical";
3014 }; 3003 };
3015 }; 3004 };
3016 }; 3005 };
3017 3006
3018 sensor2_thermal: sensor2-ther 3007 sensor2_thermal: sensor2-thermal {
3019 polling-delay-passive 3008 polling-delay-passive = <250>;
3020 polling-delay = <1000 3009 polling-delay = <1000>;
3021 thermal-sensors = <&t 3010 thermal-sensors = <&tsc 1>;
3022 sustainable-power = < 3011 sustainable-power = <3874>;
3023 3012
3024 trips { 3013 trips {
3025 sensor2_crit: 3014 sensor2_crit: sensor2-crit {
3026 tempe 3015 temperature = <120000>;
3027 hyste 3016 hysteresis = <1000>;
3028 type 3017 type = "critical";
3029 }; 3018 };
3030 }; 3019 };
3031 }; 3020 };
3032 3021
3033 sensor3_thermal: sensor3-ther 3022 sensor3_thermal: sensor3-thermal {
3034 polling-delay-passive 3023 polling-delay-passive = <250>;
3035 polling-delay = <1000 3024 polling-delay = <1000>;
3036 thermal-sensors = <&t 3025 thermal-sensors = <&tsc 2>;
3037 sustainable-power = < 3026 sustainable-power = <3874>;
3038 3027
3039 cooling-maps { 3028 cooling-maps {
3040 map0 { 3029 map0 {
3041 trip 3030 trip = <&target>;
3042 cooli 3031 cooling-device = <&a57_0 2 4>;
3043 contr 3032 contribution = <1024>;
3044 }; 3033 };
3045 map1 { 3034 map1 {
3046 trip 3035 trip = <&target>;
3047 cooli 3036 cooling-device = <&a53_0 0 2>;
3048 contr 3037 contribution = <1024>;
3049 }; 3038 };
3050 }; 3039 };
3051 trips { 3040 trips {
3052 target: trip- 3041 target: trip-point1 {
3053 tempe 3042 temperature = <100000>;
3054 hyste 3043 hysteresis = <1000>;
3055 type 3044 type = "passive";
3056 }; 3045 };
3057 3046
3058 sensor3_crit: 3047 sensor3_crit: sensor3-crit {
3059 tempe 3048 temperature = <120000>;
3060 hyste 3049 hysteresis = <1000>;
3061 type 3050 type = "critical";
3062 }; 3051 };
3063 }; 3052 };
3064 }; 3053 };
3065 }; 3054 };
3066 3055
3067 timer { 3056 timer {
3068 compatible = "arm,armv8-timer 3057 compatible = "arm,armv8-timer";
3069 interrupts-extended = <&gic G 3058 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
3070 <&gic G 3059 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
3071 <&gic G 3060 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
3072 <&gic G 3061 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
3073 interrupt-names = "sec-phys", <<
3074 }; 3062 };
3075 3063
3076 /* External USB clocks - can be overr 3064 /* External USB clocks - can be overridden by the board */
3077 usb3s0_clk: usb3s0 { 3065 usb3s0_clk: usb3s0 {
3078 compatible = "fixed-clock"; 3066 compatible = "fixed-clock";
3079 #clock-cells = <0>; 3067 #clock-cells = <0>;
3080 clock-frequency = <0>; 3068 clock-frequency = <0>;
3081 }; 3069 };
3082 3070
3083 usb_extal_clk: usb_extal { 3071 usb_extal_clk: usb_extal {
3084 compatible = "fixed-clock"; 3072 compatible = "fixed-clock";
3085 #clock-cells = <0>; 3073 #clock-cells = <0>;
3086 clock-frequency = <0>; 3074 clock-frequency = <0>;
3087 }; 3075 };
3088 }; 3076 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.