1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * Device Tree Source for the M3ULCB (R-Car St !! 3 * Device Tree Source for the M3ULCB (R-Car Starter Kit Pro) board with R-Car
>> 4 * M3-W+
4 * 5 *
5 * Copyright (C) 2020 Renesas Electronics Corp 6 * Copyright (C) 2020 Renesas Electronics Corp.
6 */ 7 */
7 8
8 /dts-v1/; 9 /dts-v1/;
9 #include "r8a77961.dtsi" 10 #include "r8a77961.dtsi"
10 #include "ulcb.dtsi" 11 #include "ulcb.dtsi"
11 12
12 / { 13 / {
13 model = "Renesas M3ULCB board based on 14 model = "Renesas M3ULCB board based on r8a77961";
14 compatible = "renesas,m3ulcb", "renesa 15 compatible = "renesas,m3ulcb", "renesas,r8a77961";
15 16
16 memory@48000000 { 17 memory@48000000 {
17 device_type = "memory"; 18 device_type = "memory";
18 /* first 128MB is reserved for 19 /* first 128MB is reserved for secure area. */
19 reg = <0x0 0x48000000 0x0 0x78 20 reg = <0x0 0x48000000 0x0 0x78000000>;
20 }; 21 };
21 22
22 memory@480000000 { 23 memory@480000000 {
23 device_type = "memory"; 24 device_type = "memory";
24 reg = <0x4 0x80000000 0x0 0x80 25 reg = <0x4 0x80000000 0x0 0x80000000>;
25 }; 26 };
26 27
27 memory@600000000 { 28 memory@600000000 {
28 device_type = "memory"; 29 device_type = "memory";
29 reg = <0x6 0x00000000 0x1 0x00 30 reg = <0x6 0x00000000 0x1 0x00000000>;
30 }; 31 };
31 }; 32 };
32 33
33 &du { 34 &du {
34 clocks = <&cpg CPG_MOD 724>, 35 clocks = <&cpg CPG_MOD 724>,
35 <&cpg CPG_MOD 723>, 36 <&cpg CPG_MOD 723>,
36 <&cpg CPG_MOD 722>, 37 <&cpg CPG_MOD 722>,
37 <&versaclock5 1>, 38 <&versaclock5 1>,
38 <&versaclock5 3>, 39 <&versaclock5 3>,
39 <&versaclock5 2>; 40 <&versaclock5 2>;
40 clock-names = "du.0", "du.1", "du.2", 41 clock-names = "du.0", "du.1", "du.2",
41 "dclkin.0", "dclkin.1", 42 "dclkin.0", "dclkin.1", "dclkin.2";
42 }; 43 };
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