1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * Device Tree Source for the M3NULCB (R-Car S 3 * Device Tree Source for the M3NULCB (R-Car Starter Kit Pro) board with R-Car M3-N
4 * 4 *
5 * Copyright (C) 2018 Renesas Electronics Corp 5 * Copyright (C) 2018 Renesas Electronics Corp.
6 * Copyright (C) 2018 Cogent Embedded, Inc. 6 * Copyright (C) 2018 Cogent Embedded, Inc.
7 */ 7 */
8 8
9 /dts-v1/; 9 /dts-v1/;
10 #include "r8a77965.dtsi" 10 #include "r8a77965.dtsi"
11 #include "ulcb.dtsi" 11 #include "ulcb.dtsi"
12 12
13 / { 13 / {
14 model = "Renesas M3NULCB board based o 14 model = "Renesas M3NULCB board based on r8a77965";
15 compatible = "renesas,m3nulcb", "renes 15 compatible = "renesas,m3nulcb", "renesas,r8a77965";
16 16
17 memory@48000000 { 17 memory@48000000 {
18 device_type = "memory"; 18 device_type = "memory";
19 /* first 128MB is reserved for 19 /* first 128MB is reserved for secure area. */
20 reg = <0x0 0x48000000 0x0 0x78 20 reg = <0x0 0x48000000 0x0 0x78000000>;
21 }; 21 };
22 }; 22 };
23 23
24 &du { 24 &du {
25 clocks = <&cpg CPG_MOD 724>, 25 clocks = <&cpg CPG_MOD 724>,
26 <&cpg CPG_MOD 723>, 26 <&cpg CPG_MOD 723>,
27 <&cpg CPG_MOD 721>, 27 <&cpg CPG_MOD 721>,
28 <&versaclock5 1>, 28 <&versaclock5 1>,
29 <&versaclock5 3>, 29 <&versaclock5 3>,
30 <&versaclock5 2>; 30 <&versaclock5 2>;
31 clock-names = "du.0", "du.1", "du.3", 31 clock-names = "du.0", "du.1", "du.3",
32 "dclkin.0", "dclkin.1", 32 "dclkin.0", "dclkin.1", "dclkin.3";
33 }; 33 };
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