1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Device Tree Source for the R-Car M3-N (R8A7
4 *
5 * Copyright (C) 2018 Jacopo Mondi <jacopo+rene
6 *
7 * Based on r8a7796.dtsi
8 * Copyright (C) 2016 Renesas Electronics Corp
9 */
10
11 #include <dt-bindings/clock/r8a77965-cpg-mssr.
12 #include <dt-bindings/interrupt-controller/arm
13 #include <dt-bindings/power/r8a77965-sysc.h>
14
15 #define SOC_HAS_SATA
16
17 / {
18 compatible = "renesas,r8a77965";
19 #address-cells = <2>;
20 #size-cells = <2>;
21
22 /*
23 * The external audio clocks are confi
24 * clocks by default.
25 * Boards that provide audio clocks sh
26 */
27 audio_clk_a: audio_clk_a {
28 compatible = "fixed-clock";
29 #clock-cells = <0>;
30 clock-frequency = <0>;
31 };
32
33 audio_clk_b: audio_clk_b {
34 compatible = "fixed-clock";
35 #clock-cells = <0>;
36 clock-frequency = <0>;
37 };
38
39 audio_clk_c: audio_clk_c {
40 compatible = "fixed-clock";
41 #clock-cells = <0>;
42 clock-frequency = <0>;
43 };
44
45 /* External CAN clock - to be overridd
46 can_clk: can {
47 compatible = "fixed-clock";
48 #clock-cells = <0>;
49 clock-frequency = <0>;
50 };
51
52 cluster0_opp: opp-table-0 {
53 compatible = "operating-points
54 opp-shared;
55
56 opp-500000000 {
57 opp-hz = /bits/ 64 <50
58 opp-microvolt = <83000
59 clock-latency-ns = <30
60 };
61 opp-1000000000 {
62 opp-hz = /bits/ 64 <10
63 opp-microvolt = <83000
64 clock-latency-ns = <30
65 };
66 opp-1500000000 {
67 opp-hz = /bits/ 64 <15
68 opp-microvolt = <83000
69 clock-latency-ns = <30
70 opp-suspend;
71 };
72 opp-1600000000 {
73 opp-hz = /bits/ 64 <16
74 opp-microvolt = <90000
75 clock-latency-ns = <30
76 };
77 opp-1700000000 {
78 opp-hz = /bits/ 64 <17
79 opp-microvolt = <90000
80 clock-latency-ns = <30
81 };
82 opp-1800000000 {
83 opp-hz = /bits/ 64 <18
84 opp-microvolt = <96000
85 clock-latency-ns = <30
86 turbo-mode;
87 };
88 };
89
90 cpus {
91 #address-cells = <1>;
92 #size-cells = <0>;
93
94 a57_0: cpu@0 {
95 compatible = "arm,cort
96 reg = <0x0>;
97 device_type = "cpu";
98 power-domains = <&sysc
99 next-level-cache = <&L
100 enable-method = "psci"
101 cpu-idle-states = <&CP
102 #cooling-cells = <2>;
103 dynamic-power-coeffici
104 clocks = <&cpg CPG_COR
105 operating-points-v2 =
106 };
107
108 a57_1: cpu@1 {
109 compatible = "arm,cort
110 reg = <0x1>;
111 device_type = "cpu";
112 power-domains = <&sysc
113 next-level-cache = <&L
114 enable-method = "psci"
115 cpu-idle-states = <&CP
116 clocks = <&cpg CPG_COR
117 operating-points-v2 =
118 };
119
120 L2_CA57: cache-controller-0 {
121 compatible = "cache";
122 power-domains = <&sysc
123 cache-unified;
124 cache-level = <2>;
125 };
126
127 idle-states {
128 entry-method = "psci";
129
130 CPU_SLEEP_0: cpu-sleep
131 compatible = "
132 arm,psci-suspe
133 local-timer-st
134 entry-latency-
135 exit-latency-u
136 min-residency-
137 };
138 };
139 };
140
141 extal_clk: extal {
142 compatible = "fixed-clock";
143 #clock-cells = <0>;
144 /* This value must be overridd
145 clock-frequency = <0>;
146 };
147
148 extalr_clk: extalr {
149 compatible = "fixed-clock";
150 #clock-cells = <0>;
151 /* This value must be overridd
152 clock-frequency = <0>;
153 };
154
155 /* External PCIe clock - can be overri
156 pcie_bus_clk: pcie_bus {
157 compatible = "fixed-clock";
158 #clock-cells = <0>;
159 clock-frequency = <0>;
160 };
161
162 pmu_a57 {
163 compatible = "arm,cortex-a57-p
164 interrupts-extended = <&gic GI
165 <&gic GI
166 interrupt-affinity = <&a57_0>,
167 <&a57_1>;
168 };
169
170 psci {
171 compatible = "arm,psci-1.0", "
172 method = "smc";
173 };
174
175 /* External SCIF clock - to be overrid
176 scif_clk: scif {
177 compatible = "fixed-clock";
178 #clock-cells = <0>;
179 clock-frequency = <0>;
180 };
181
182 soc {
183 compatible = "simple-bus";
184 interrupt-parent = <&gic>;
185 #address-cells = <2>;
186 #size-cells = <2>;
187 ranges;
188
189 rwdt: watchdog@e6020000 {
190 compatible = "renesas,
191 "renesas,
192 reg = <0 0xe6020000 0
193 interrupts = <GIC_SPI
194 clocks = <&cpg CPG_MOD
195 power-domains = <&sysc
196 resets = <&cpg 402>;
197 status = "disabled";
198 };
199
200 gpio0: gpio@e6050000 {
201 compatible = "renesas,
202 "renesas,
203 reg = <0 0xe6050000 0
204 interrupts = <GIC_SPI
205 #gpio-cells = <2>;
206 gpio-controller;
207 gpio-ranges = <&pfc 0
208 #interrupt-cells = <2>
209 interrupt-controller;
210 clocks = <&cpg CPG_MOD
211 power-domains = <&sysc
212 resets = <&cpg 912>;
213 };
214
215 gpio1: gpio@e6051000 {
216 compatible = "renesas,
217 "renesas,
218 reg = <0 0xe6051000 0
219 interrupts = <GIC_SPI
220 #gpio-cells = <2>;
221 gpio-controller;
222 gpio-ranges = <&pfc 0
223 #interrupt-cells = <2>
224 interrupt-controller;
225 clocks = <&cpg CPG_MOD
226 power-domains = <&sysc
227 resets = <&cpg 911>;
228 };
229
230 gpio2: gpio@e6052000 {
231 compatible = "renesas,
232 "renesas,
233 reg = <0 0xe6052000 0
234 interrupts = <GIC_SPI
235 #gpio-cells = <2>;
236 gpio-controller;
237 gpio-ranges = <&pfc 0
238 #interrupt-cells = <2>
239 interrupt-controller;
240 clocks = <&cpg CPG_MOD
241 power-domains = <&sysc
242 resets = <&cpg 910>;
243 };
244
245 gpio3: gpio@e6053000 {
246 compatible = "renesas,
247 "renesas,
248 reg = <0 0xe6053000 0
249 interrupts = <GIC_SPI
250 #gpio-cells = <2>;
251 gpio-controller;
252 gpio-ranges = <&pfc 0
253 #interrupt-cells = <2>
254 interrupt-controller;
255 clocks = <&cpg CPG_MOD
256 power-domains = <&sysc
257 resets = <&cpg 909>;
258 };
259
260 gpio4: gpio@e6054000 {
261 compatible = "renesas,
262 "renesas,
263 reg = <0 0xe6054000 0
264 interrupts = <GIC_SPI
265 #gpio-cells = <2>;
266 gpio-controller;
267 gpio-ranges = <&pfc 0
268 #interrupt-cells = <2>
269 interrupt-controller;
270 clocks = <&cpg CPG_MOD
271 power-domains = <&sysc
272 resets = <&cpg 908>;
273 };
274
275 gpio5: gpio@e6055000 {
276 compatible = "renesas,
277 "renesas,
278 reg = <0 0xe6055000 0
279 interrupts = <GIC_SPI
280 #gpio-cells = <2>;
281 gpio-controller;
282 gpio-ranges = <&pfc 0
283 #interrupt-cells = <2>
284 interrupt-controller;
285 clocks = <&cpg CPG_MOD
286 power-domains = <&sysc
287 resets = <&cpg 907>;
288 };
289
290 gpio6: gpio@e6055400 {
291 compatible = "renesas,
292 "renesas,
293 reg = <0 0xe6055400 0
294 interrupts = <GIC_SPI
295 #gpio-cells = <2>;
296 gpio-controller;
297 gpio-ranges = <&pfc 0
298 #interrupt-cells = <2>
299 interrupt-controller;
300 clocks = <&cpg CPG_MOD
301 power-domains = <&sysc
302 resets = <&cpg 906>;
303 };
304
305 gpio7: gpio@e6055800 {
306 compatible = "renesas,
307 "renesas,
308 reg = <0 0xe6055800 0
309 interrupts = <GIC_SPI
310 #gpio-cells = <2>;
311 gpio-controller;
312 gpio-ranges = <&pfc 0
313 #interrupt-cells = <2>
314 interrupt-controller;
315 clocks = <&cpg CPG_MOD
316 power-domains = <&sysc
317 resets = <&cpg 905>;
318 };
319
320 pfc: pinctrl@e6060000 {
321 compatible = "renesas,
322 reg = <0 0xe6060000 0
323 };
324
325 cmt0: timer@e60f0000 {
326 compatible = "renesas,
327 "renesas,
328 reg = <0 0xe60f0000 0
329 interrupts = <GIC_SPI
330 <GIC_SPI
331 clocks = <&cpg CPG_MOD
332 clock-names = "fck";
333 power-domains = <&sysc
334 resets = <&cpg 303>;
335 status = "disabled";
336 };
337
338 cmt1: timer@e6130000 {
339 compatible = "renesas,
340 "renesas,
341 reg = <0 0xe6130000 0
342 interrupts = <GIC_SPI
343 <GIC_SPI
344 <GIC_SPI
345 <GIC_SPI
346 <GIC_SPI
347 <GIC_SPI
348 <GIC_SPI
349 <GIC_SPI
350 clocks = <&cpg CPG_MOD
351 clock-names = "fck";
352 power-domains = <&sysc
353 resets = <&cpg 302>;
354 status = "disabled";
355 };
356
357 cmt2: timer@e6140000 {
358 compatible = "renesas,
359 "renesas,
360 reg = <0 0xe6140000 0
361 interrupts = <GIC_SPI
362 <GIC_SPI
363 <GIC_SPI
364 <GIC_SPI
365 <GIC_SPI
366 <GIC_SPI
367 <GIC_SPI
368 <GIC_SPI
369 clocks = <&cpg CPG_MOD
370 clock-names = "fck";
371 power-domains = <&sysc
372 resets = <&cpg 301>;
373 status = "disabled";
374 };
375
376 cmt3: timer@e6148000 {
377 compatible = "renesas,
378 "renesas,
379 reg = <0 0xe6148000 0
380 interrupts = <GIC_SPI
381 <GIC_SPI
382 <GIC_SPI
383 <GIC_SPI
384 <GIC_SPI
385 <GIC_SPI
386 <GIC_SPI
387 <GIC_SPI
388 clocks = <&cpg CPG_MOD
389 clock-names = "fck";
390 power-domains = <&sysc
391 resets = <&cpg 300>;
392 status = "disabled";
393 };
394
395 cpg: clock-controller@e6150000
396 compatible = "renesas,
397 reg = <0 0xe6150000 0
398 clocks = <&extal_clk>,
399 clock-names = "extal",
400 #clock-cells = <2>;
401 #power-domain-cells =
402 #reset-cells = <1>;
403 };
404
405 rst: reset-controller@e6160000
406 compatible = "renesas,
407 reg = <0 0xe6160000 0
408 };
409
410 sysc: system-controller@e61800
411 compatible = "renesas,
412 reg = <0 0xe6180000 0
413 #power-domain-cells =
414 };
415
416 tsc: thermal@e6198000 {
417 compatible = "renesas,
418 reg = <0 0xe6198000 0
419 <0 0xe61a0000 0
420 <0 0xe61a8000 0
421 interrupts = <GIC_SPI
422 <GIC_SPI
423 <GIC_SPI
424 clocks = <&cpg CPG_MOD
425 power-domains = <&sysc
426 resets = <&cpg 522>;
427 #thermal-sensor-cells
428 };
429
430 intc_ex: interrupt-controller@
431 compatible = "renesas,
432 #interrupt-cells = <2>
433 interrupt-controller;
434 reg = <0 0xe61c0000 0
435 interrupts = <GIC_SPI
436 <GIC_SPI
437 <GIC_SPI
438 <GIC_SPI
439 <GIC_SPI
440 <GIC_SPI
441 clocks = <&cpg CPG_MOD
442 power-domains = <&sysc
443 resets = <&cpg 407>;
444 };
445
446 tmu0: timer@e61e0000 {
447 compatible = "renesas,
448 reg = <0 0xe61e0000 0
449 interrupts = <GIC_SPI
450 <GIC_SPI
451 <GIC_SPI
452 interrupt-names = "tun
453 clocks = <&cpg CPG_MOD
454 clock-names = "fck";
455 power-domains = <&sysc
456 resets = <&cpg 125>;
457 status = "disabled";
458 };
459
460 tmu1: timer@e6fc0000 {
461 compatible = "renesas,
462 reg = <0 0xe6fc0000 0
463 interrupts = <GIC_SPI
464 <GIC_SPI
465 <GIC_SPI
466 <GIC_SPI
467 interrupt-names = "tun
468 clocks = <&cpg CPG_MOD
469 clock-names = "fck";
470 power-domains = <&sysc
471 resets = <&cpg 124>;
472 status = "disabled";
473 };
474
475 tmu2: timer@e6fd0000 {
476 compatible = "renesas,
477 reg = <0 0xe6fd0000 0
478 interrupts = <GIC_SPI
479 <GIC_SPI
480 <GIC_SPI
481 <GIC_SPI
482 interrupt-names = "tun
483 clocks = <&cpg CPG_MOD
484 clock-names = "fck";
485 power-domains = <&sysc
486 resets = <&cpg 123>;
487 status = "disabled";
488 };
489
490 tmu3: timer@e6fe0000 {
491 compatible = "renesas,
492 reg = <0 0xe6fe0000 0
493 interrupts = <GIC_SPI
494 <GIC_SPI
495 <GIC_SPI
496 interrupt-names = "tun
497 clocks = <&cpg CPG_MOD
498 clock-names = "fck";
499 power-domains = <&sysc
500 resets = <&cpg 122>;
501 status = "disabled";
502 };
503
504 tmu4: timer@ffc00000 {
505 compatible = "renesas,
506 reg = <0 0xffc00000 0
507 interrupts = <GIC_SPI
508 <GIC_SPI
509 <GIC_SPI
510 interrupt-names = "tun
511 clocks = <&cpg CPG_MOD
512 clock-names = "fck";
513 power-domains = <&sysc
514 resets = <&cpg 121>;
515 status = "disabled";
516 };
517
518 i2c0: i2c@e6500000 {
519 #address-cells = <1>;
520 #size-cells = <0>;
521 compatible = "renesas,
522 "renesas,
523 reg = <0 0xe6500000 0
524 interrupts = <GIC_SPI
525 clocks = <&cpg CPG_MOD
526 power-domains = <&sysc
527 resets = <&cpg 931>;
528 dmas = <&dmac1 0x91>,
529 <&dmac2 0x91>,
530 dma-names = "tx", "rx"
531 i2c-scl-internal-delay
532 status = "disabled";
533 };
534
535 i2c1: i2c@e6508000 {
536 #address-cells = <1>;
537 #size-cells = <0>;
538 compatible = "renesas,
539 "renesas,
540 reg = <0 0xe6508000 0
541 interrupts = <GIC_SPI
542 clocks = <&cpg CPG_MOD
543 power-domains = <&sysc
544 resets = <&cpg 930>;
545 dmas = <&dmac1 0x93>,
546 <&dmac2 0x93>,
547 dma-names = "tx", "rx"
548 i2c-scl-internal-delay
549 status = "disabled";
550 };
551
552 i2c2: i2c@e6510000 {
553 #address-cells = <1>;
554 #size-cells = <0>;
555 compatible = "renesas,
556 "renesas,
557 reg = <0 0xe6510000 0
558 interrupts = <GIC_SPI
559 clocks = <&cpg CPG_MOD
560 power-domains = <&sysc
561 resets = <&cpg 929>;
562 dmas = <&dmac1 0x95>,
563 <&dmac2 0x95>,
564 dma-names = "tx", "rx"
565 i2c-scl-internal-delay
566 status = "disabled";
567 };
568
569 i2c3: i2c@e66d0000 {
570 #address-cells = <1>;
571 #size-cells = <0>;
572 compatible = "renesas,
573 "renesas,
574 reg = <0 0xe66d0000 0
575 interrupts = <GIC_SPI
576 clocks = <&cpg CPG_MOD
577 power-domains = <&sysc
578 resets = <&cpg 928>;
579 dmas = <&dmac0 0x97>,
580 dma-names = "tx", "rx"
581 i2c-scl-internal-delay
582 status = "disabled";
583 };
584
585 i2c4: i2c@e66d8000 {
586 #address-cells = <1>;
587 #size-cells = <0>;
588 compatible = "renesas,
589 "renesas,
590 reg = <0 0xe66d8000 0
591 interrupts = <GIC_SPI
592 clocks = <&cpg CPG_MOD
593 power-domains = <&sysc
594 resets = <&cpg 927>;
595 dmas = <&dmac0 0x99>,
596 dma-names = "tx", "rx"
597 i2c-scl-internal-delay
598 status = "disabled";
599 };
600
601 i2c5: i2c@e66e0000 {
602 #address-cells = <1>;
603 #size-cells = <0>;
604 compatible = "renesas,
605 "renesas,
606 reg = <0 0xe66e0000 0
607 interrupts = <GIC_SPI
608 clocks = <&cpg CPG_MOD
609 power-domains = <&sysc
610 resets = <&cpg 919>;
611 dmas = <&dmac0 0x9b>,
612 dma-names = "tx", "rx"
613 i2c-scl-internal-delay
614 status = "disabled";
615 };
616
617 i2c6: i2c@e66e8000 {
618 #address-cells = <1>;
619 #size-cells = <0>;
620 compatible = "renesas,
621 "renesas,
622 reg = <0 0xe66e8000 0
623 interrupts = <GIC_SPI
624 clocks = <&cpg CPG_MOD
625 power-domains = <&sysc
626 resets = <&cpg 918>;
627 dmas = <&dmac0 0x9d>,
628 dma-names = "tx", "rx"
629 i2c-scl-internal-delay
630 status = "disabled";
631 };
632
633 i2c_dvfs: i2c@e60b0000 {
634 #address-cells = <1>;
635 #size-cells = <0>;
636 compatible = "renesas,
637 "renesas,
638 "renesas,
639 reg = <0 0xe60b0000 0
640 interrupts = <GIC_SPI
641 clocks = <&cpg CPG_MOD
642 power-domains = <&sysc
643 resets = <&cpg 926>;
644 dmas = <&dmac0 0x11>,
645 dma-names = "tx", "rx"
646 status = "disabled";
647 };
648
649 hscif0: serial@e6540000 {
650 compatible = "renesas,
651 "renesas,
652 "renesas,
653 reg = <0 0xe6540000 0
654 interrupts = <GIC_SPI
655 clocks = <&cpg CPG_MOD
656 <&cpg CPG_COR
657 <&scif_clk>;
658 clock-names = "fck", "
659 dmas = <&dmac1 0x31>,
660 <&dmac2 0x31>,
661 dma-names = "tx", "rx"
662 power-domains = <&sysc
663 resets = <&cpg 520>;
664 status = "disabled";
665 };
666
667 hscif1: serial@e6550000 {
668 compatible = "renesas,
669 "renesas,
670 "renesas,
671 reg = <0 0xe6550000 0
672 interrupts = <GIC_SPI
673 clocks = <&cpg CPG_MOD
674 <&cpg CPG_COR
675 <&scif_clk>;
676 clock-names = "fck", "
677 dmas = <&dmac1 0x33>,
678 <&dmac2 0x33>,
679 dma-names = "tx", "rx"
680 power-domains = <&sysc
681 resets = <&cpg 519>;
682 status = "disabled";
683 };
684
685 hscif2: serial@e6560000 {
686 compatible = "renesas,
687 "renesas,
688 "renesas,
689 reg = <0 0xe6560000 0
690 interrupts = <GIC_SPI
691 clocks = <&cpg CPG_MOD
692 <&cpg CPG_COR
693 <&scif_clk>;
694 clock-names = "fck", "
695 dmas = <&dmac1 0x35>,
696 <&dmac2 0x35>,
697 dma-names = "tx", "rx"
698 power-domains = <&sysc
699 resets = <&cpg 518>;
700 status = "disabled";
701 };
702
703 hscif3: serial@e66a0000 {
704 compatible = "renesas,
705 "renesas,
706 "renesas,
707 reg = <0 0xe66a0000 0
708 interrupts = <GIC_SPI
709 clocks = <&cpg CPG_MOD
710 <&cpg CPG_COR
711 <&scif_clk>;
712 clock-names = "fck", "
713 dmas = <&dmac0 0x37>,
714 dma-names = "tx", "rx"
715 power-domains = <&sysc
716 resets = <&cpg 517>;
717 status = "disabled";
718 };
719
720 hscif4: serial@e66b0000 {
721 compatible = "renesas,
722 "renesas,
723 "renesas,
724 reg = <0 0xe66b0000 0
725 interrupts = <GIC_SPI
726 clocks = <&cpg CPG_MOD
727 <&cpg CPG_COR
728 <&scif_clk>;
729 clock-names = "fck", "
730 dmas = <&dmac0 0x39>,
731 dma-names = "tx", "rx"
732 power-domains = <&sysc
733 resets = <&cpg 516>;
734 status = "disabled";
735 };
736
737 hsusb: usb@e6590000 {
738 compatible = "renesas,
739 "renesas,
740 reg = <0 0xe6590000 0
741 interrupts = <GIC_SPI
742 clocks = <&cpg CPG_MOD
743 dmas = <&usb_dmac0 0>,
744 <&usb_dmac1 0>,
745 dma-names = "ch0", "ch
746 renesas,buswait = <11>
747 phys = <&usb2_phy0 3>;
748 phy-names = "usb";
749 power-domains = <&sysc
750 resets = <&cpg 704>, <
751 status = "disabled";
752 };
753
754 usb_dmac0: dma-controller@e65a
755 compatible = "renesas,
756 "renesas,
757 reg = <0 0xe65a0000 0
758 interrupts = <GIC_SPI
759 <GIC_SPI
760 interrupt-names = "ch0
761 clocks = <&cpg CPG_MOD
762 power-domains = <&sysc
763 resets = <&cpg 330>;
764 #dma-cells = <1>;
765 dma-channels = <2>;
766 };
767
768 usb_dmac1: dma-controller@e65b
769 compatible = "renesas,
770 "renesas,
771 reg = <0 0xe65b0000 0
772 interrupts = <GIC_SPI
773 <GIC_SPI
774 interrupt-names = "ch0
775 clocks = <&cpg CPG_MOD
776 power-domains = <&sysc
777 resets = <&cpg 331>;
778 #dma-cells = <1>;
779 dma-channels = <2>;
780 };
781
782 usb3_phy0: usb-phy@e65ee000 {
783 compatible = "renesas,
784 "renesas,
785 reg = <0 0xe65ee000 0
786 clocks = <&cpg CPG_MOD
787 <&usb_extal_c
788 clock-names = "usb3-if
789 power-domains = <&sysc
790 resets = <&cpg 328>;
791 #phy-cells = <0>;
792 status = "disabled";
793 };
794
795 arm_cc630p: crypto@e6601000 {
796 compatible = "arm,cryp
797 interrupts = <GIC_SPI
798 reg = <0x0 0xe6601000
799 clocks = <&cpg CPG_MOD
800 resets = <&cpg 229>;
801 power-domains = <&sysc
802 };
803
804 dmac0: dma-controller@e6700000
805 compatible = "renesas,
806 "renesas,
807 reg = <0 0xe6700000 0
808 interrupts = <GIC_SPI
809 <GIC_SPI
810 <GIC_SPI
811 <GIC_SPI
812 <GIC_SPI
813 <GIC_SPI
814 <GIC_SPI
815 <GIC_SPI
816 <GIC_SPI
817 <GIC_SPI
818 <GIC_SPI
819 <GIC_SPI
820 <GIC_SPI
821 <GIC_SPI
822 <GIC_SPI
823 <GIC_SPI
824 <GIC_SPI
825 interrupt-names = "err
826 "ch0",
827 "ch4",
828 "ch8",
829 "ch12"
830 clocks = <&cpg CPG_MOD
831 clock-names = "fck";
832 power-domains = <&sysc
833 resets = <&cpg 219>;
834 #dma-cells = <1>;
835 dma-channels = <16>;
836 iommus = <&ipmmu_ds0 0
837 <&ipmmu_ds0 2>,
838 <&ipmmu_ds0 4>,
839 <&ipmmu_ds0 6>,
840 <&ipmmu_ds0 8>,
841 <&ipmmu_ds0 10>
842 <&ipmmu_ds0 12>
843 <&ipmmu_ds0 14>
844 };
845
846 dmac1: dma-controller@e7300000
847 compatible = "renesas,
848 "renesas,
849 reg = <0 0xe7300000 0
850 interrupts = <GIC_SPI
851 <GIC_SPI
852 <GIC_SPI
853 <GIC_SPI
854 <GIC_SPI
855 <GIC_SPI
856 <GIC_SPI
857 <GIC_SPI
858 <GIC_SPI
859 <GIC_SPI
860 <GIC_SPI
861 <GIC_SPI
862 <GIC_SPI
863 <GIC_SPI
864 <GIC_SPI
865 <GIC_SPI
866 <GIC_SPI
867 interrupt-names = "err
868 "ch0",
869 "ch4",
870 "ch8",
871 "ch12"
872 clocks = <&cpg CPG_MOD
873 clock-names = "fck";
874 power-domains = <&sysc
875 resets = <&cpg 218>;
876 #dma-cells = <1>;
877 dma-channels = <16>;
878 iommus = <&ipmmu_ds1 0
879 <&ipmmu_ds1 2>,
880 <&ipmmu_ds1 4>,
881 <&ipmmu_ds1 6>,
882 <&ipmmu_ds1 8>,
883 <&ipmmu_ds1 10>
884 <&ipmmu_ds1 12>
885 <&ipmmu_ds1 14>
886 };
887
888 dmac2: dma-controller@e7310000
889 compatible = "renesas,
890 "renesas,
891 reg = <0 0xe7310000 0
892 interrupts = <GIC_SPI
893 <GIC_SPI
894 <GIC_SPI
895 <GIC_SPI
896 <GIC_SPI
897 <GIC_SPI
898 <GIC_SPI
899 <GIC_SPI
900 <GIC_SPI
901 <GIC_SPI
902 <GIC_SPI
903 <GIC_SPI
904 <GIC_SPI
905 <GIC_SPI
906 <GIC_SPI
907 <GIC_SPI
908 <GIC_SPI
909 interrupt-names = "err
910 "ch0",
911 "ch4",
912 "ch8",
913 "ch12"
914 clocks = <&cpg CPG_MOD
915 clock-names = "fck";
916 power-domains = <&sysc
917 resets = <&cpg 217>;
918 #dma-cells = <1>;
919 dma-channels = <16>;
920 iommus = <&ipmmu_ds1 1
921 <&ipmmu_ds1 18>
922 <&ipmmu_ds1 20>
923 <&ipmmu_ds1 22>
924 <&ipmmu_ds1 24>
925 <&ipmmu_ds1 26>
926 <&ipmmu_ds1 28>
927 <&ipmmu_ds1 30>
928 };
929
930 ipmmu_ds0: iommu@e6740000 {
931 compatible = "renesas,
932 reg = <0 0xe6740000 0
933 renesas,ipmmu-main = <
934 power-domains = <&sysc
935 #iommu-cells = <1>;
936 };
937
938 ipmmu_ds1: iommu@e7740000 {
939 compatible = "renesas,
940 reg = <0 0xe7740000 0
941 renesas,ipmmu-main = <
942 power-domains = <&sysc
943 #iommu-cells = <1>;
944 };
945
946 ipmmu_hc: iommu@e6570000 {
947 compatible = "renesas,
948 reg = <0 0xe6570000 0
949 renesas,ipmmu-main = <
950 power-domains = <&sysc
951 #iommu-cells = <1>;
952 };
953
954 ipmmu_mm: iommu@e67b0000 {
955 compatible = "renesas,
956 reg = <0 0xe67b0000 0
957 interrupts = <GIC_SPI
958 <GIC_SPI
959 power-domains = <&sysc
960 #iommu-cells = <1>;
961 };
962
963 ipmmu_mp: iommu@ec670000 {
964 compatible = "renesas,
965 reg = <0 0xec670000 0
966 renesas,ipmmu-main = <
967 power-domains = <&sysc
968 #iommu-cells = <1>;
969 };
970
971 ipmmu_pv0: iommu@fd800000 {
972 compatible = "renesas,
973 reg = <0 0xfd800000 0
974 renesas,ipmmu-main = <
975 power-domains = <&sysc
976 #iommu-cells = <1>;
977 };
978
979 ipmmu_rt: iommu@ffc80000 {
980 compatible = "renesas,
981 reg = <0 0xffc80000 0
982 renesas,ipmmu-main = <
983 power-domains = <&sysc
984 #iommu-cells = <1>;
985 };
986
987 ipmmu_vc0: iommu@fe6b0000 {
988 compatible = "renesas,
989 reg = <0 0xfe6b0000 0
990 renesas,ipmmu-main = <
991 power-domains = <&sysc
992 #iommu-cells = <1>;
993 };
994
995 ipmmu_vi0: iommu@febd0000 {
996 compatible = "renesas,
997 reg = <0 0xfebd0000 0
998 renesas,ipmmu-main = <
999 power-domains = <&sysc
1000 #iommu-cells = <1>;
1001 };
1002
1003 ipmmu_vp0: iommu@fe990000 {
1004 compatible = "renesas
1005 reg = <0 0xfe990000 0
1006 renesas,ipmmu-main =
1007 power-domains = <&sys
1008 #iommu-cells = <1>;
1009 };
1010
1011 avb: ethernet@e6800000 {
1012 compatible = "renesas
1013 "renesas
1014 reg = <0 0xe6800000 0
1015 interrupts = <GIC_SPI
1016 <GIC_SPI
1017 <GIC_SPI
1018 <GIC_SPI
1019 <GIC_SPI
1020 <GIC_SPI
1021 <GIC_SPI
1022 <GIC_SPI
1023 <GIC_SPI
1024 <GIC_SPI
1025 <GIC_SPI
1026 <GIC_SPI
1027 <GIC_SPI
1028 <GIC_SPI
1029 <GIC_SPI
1030 <GIC_SPI
1031 <GIC_SPI
1032 <GIC_SPI
1033 <GIC_SPI
1034 <GIC_SPI
1035 <GIC_SPI
1036 <GIC_SPI
1037 <GIC_SPI
1038 <GIC_SPI
1039 <GIC_SPI
1040 interrupt-names = "ch
1041 "ch
1042 "ch
1043 "ch
1044 "ch
1045 "ch
1046 "ch
1047 clocks = <&cpg CPG_MO
1048 clock-names = "fck";
1049 power-domains = <&sys
1050 resets = <&cpg 812>;
1051 phy-mode = "rgmii";
1052 rx-internal-delay-ps
1053 tx-internal-delay-ps
1054 iommus = <&ipmmu_ds0
1055 #address-cells = <1>;
1056 #size-cells = <0>;
1057 status = "disabled";
1058 };
1059
1060 can0: can@e6c30000 {
1061 compatible = "renesas
1062 "renesas
1063 reg = <0 0xe6c30000 0
1064 interrupts = <GIC_SPI
1065 clocks = <&cpg CPG_MO
1066 <&cpg CPG_CORE
1067 <&can_clk>;
1068 clock-names = "clkp1"
1069 assigned-clocks = <&c
1070 assigned-clock-rates
1071 power-domains = <&sys
1072 resets = <&cpg 916>;
1073 status = "disabled";
1074 };
1075
1076 can1: can@e6c38000 {
1077 compatible = "renesas
1078 "renesas
1079 reg = <0 0xe6c38000 0
1080 interrupts = <GIC_SPI
1081 clocks = <&cpg CPG_MO
1082 <&cpg CPG_CORE
1083 <&can_clk>;
1084 clock-names = "clkp1"
1085 assigned-clocks = <&c
1086 assigned-clock-rates
1087 power-domains = <&sys
1088 resets = <&cpg 915>;
1089 status = "disabled";
1090 };
1091
1092 canfd: can@e66c0000 {
1093 compatible = "renesas
1094 "renesas
1095 reg = <0 0xe66c0000 0
1096 interrupts = <GIC_SPI
1097 <GIC_SPI 3
1098 interrupt-names = "ch
1099 clocks = <&cpg CPG_MO
1100 <&cpg CPG_CORE
1101 <&can_clk>;
1102 clock-names = "fck",
1103 assigned-clocks = <&c
1104 assigned-clock-rates
1105 power-domains = <&sys
1106 resets = <&cpg 914>;
1107 status = "disabled";
1108
1109 channel0 {
1110 status = "dis
1111 };
1112
1113 channel1 {
1114 status = "dis
1115 };
1116 };
1117
1118 pwm0: pwm@e6e30000 {
1119 compatible = "renesas
1120 reg = <0 0xe6e30000 0
1121 #pwm-cells = <2>;
1122 clocks = <&cpg CPG_MO
1123 resets = <&cpg 523>;
1124 power-domains = <&sys
1125 status = "disabled";
1126 };
1127
1128 pwm1: pwm@e6e31000 {
1129 compatible = "renesas
1130 reg = <0 0xe6e31000 0
1131 #pwm-cells = <2>;
1132 clocks = <&cpg CPG_MO
1133 resets = <&cpg 523>;
1134 power-domains = <&sys
1135 status = "disabled";
1136 };
1137
1138 pwm2: pwm@e6e32000 {
1139 compatible = "renesas
1140 reg = <0 0xe6e32000 0
1141 #pwm-cells = <2>;
1142 clocks = <&cpg CPG_MO
1143 resets = <&cpg 523>;
1144 power-domains = <&sys
1145 status = "disabled";
1146 };
1147
1148 pwm3: pwm@e6e33000 {
1149 compatible = "renesas
1150 reg = <0 0xe6e33000 0
1151 #pwm-cells = <2>;
1152 clocks = <&cpg CPG_MO
1153 resets = <&cpg 523>;
1154 power-domains = <&sys
1155 status = "disabled";
1156 };
1157
1158 pwm4: pwm@e6e34000 {
1159 compatible = "renesas
1160 reg = <0 0xe6e34000 0
1161 #pwm-cells = <2>;
1162 clocks = <&cpg CPG_MO
1163 resets = <&cpg 523>;
1164 power-domains = <&sys
1165 status = "disabled";
1166 };
1167
1168 pwm5: pwm@e6e35000 {
1169 compatible = "renesas
1170 reg = <0 0xe6e35000 0
1171 #pwm-cells = <2>;
1172 clocks = <&cpg CPG_MO
1173 resets = <&cpg 523>;
1174 power-domains = <&sys
1175 status = "disabled";
1176 };
1177
1178 pwm6: pwm@e6e36000 {
1179 compatible = "renesas
1180 reg = <0 0xe6e36000 0
1181 #pwm-cells = <2>;
1182 clocks = <&cpg CPG_MO
1183 resets = <&cpg 523>;
1184 power-domains = <&sys
1185 status = "disabled";
1186 };
1187
1188 scif0: serial@e6e60000 {
1189 compatible = "renesas
1190 "renesas
1191 reg = <0 0xe6e60000 0
1192 interrupts = <GIC_SPI
1193 clocks = <&cpg CPG_MO
1194 <&cpg CPG_CO
1195 <&scif_clk>;
1196 clock-names = "fck",
1197 dmas = <&dmac1 0x51>,
1198 <&dmac2 0x51>,
1199 dma-names = "tx", "rx
1200 power-domains = <&sys
1201 resets = <&cpg 207>;
1202 status = "disabled";
1203 };
1204
1205 scif1: serial@e6e68000 {
1206 compatible = "renesas
1207 "renesas
1208 reg = <0 0xe6e68000 0
1209 interrupts = <GIC_SPI
1210 clocks = <&cpg CPG_MO
1211 <&cpg CPG_CO
1212 <&scif_clk>;
1213 clock-names = "fck",
1214 dmas = <&dmac1 0x53>,
1215 <&dmac2 0x53>,
1216 dma-names = "tx", "rx
1217 power-domains = <&sys
1218 resets = <&cpg 206>;
1219 status = "disabled";
1220 };
1221
1222 scif2: serial@e6e88000 {
1223 compatible = "renesas
1224 "renesas
1225 reg = <0 0xe6e88000 0
1226 interrupts = <GIC_SPI
1227 clocks = <&cpg CPG_MO
1228 <&cpg CPG_CO
1229 <&scif_clk>;
1230 clock-names = "fck",
1231 dmas = <&dmac1 0x13>,
1232 <&dmac2 0x13>,
1233 dma-names = "tx", "rx
1234 power-domains = <&sys
1235 resets = <&cpg 310>;
1236 status = "disabled";
1237 };
1238
1239 scif3: serial@e6c50000 {
1240 compatible = "renesas
1241 "renesas
1242 reg = <0 0xe6c50000 0
1243 interrupts = <GIC_SPI
1244 clocks = <&cpg CPG_MO
1245 <&cpg CPG_CO
1246 <&scif_clk>;
1247 clock-names = "fck",
1248 dmas = <&dmac0 0x57>,
1249 dma-names = "tx", "rx
1250 power-domains = <&sys
1251 resets = <&cpg 204>;
1252 status = "disabled";
1253 };
1254
1255 scif4: serial@e6c40000 {
1256 compatible = "renesas
1257 "renesas
1258 reg = <0 0xe6c40000 0
1259 interrupts = <GIC_SPI
1260 clocks = <&cpg CPG_MO
1261 <&cpg CPG_CO
1262 <&scif_clk>;
1263 clock-names = "fck",
1264 dmas = <&dmac0 0x59>,
1265 dma-names = "tx", "rx
1266 power-domains = <&sys
1267 resets = <&cpg 203>;
1268 status = "disabled";
1269 };
1270
1271 scif5: serial@e6f30000 {
1272 compatible = "renesas
1273 "renesas
1274 reg = <0 0xe6f30000 0
1275 interrupts = <GIC_SPI
1276 clocks = <&cpg CPG_MO
1277 <&cpg CPG_CO
1278 <&scif_clk>;
1279 clock-names = "fck",
1280 dmas = <&dmac1 0x5b>,
1281 <&dmac2 0x5b>,
1282 dma-names = "tx", "rx
1283 power-domains = <&sys
1284 resets = <&cpg 202>;
1285 status = "disabled";
1286 };
1287
1288 tpu: pwm@e6e80000 {
1289 compatible = "renesas
1290 reg = <0 0xe6e80000 0
1291 interrupts = <GIC_SPI
1292 clocks = <&cpg CPG_MO
1293 power-domains = <&sys
1294 resets = <&cpg 304>;
1295 #pwm-cells = <3>;
1296 status = "disabled";
1297 };
1298
1299 msiof0: spi@e6e90000 {
1300 compatible = "renesas
1301 "renesas
1302 reg = <0 0xe6e90000 0
1303 interrupts = <GIC_SPI
1304 clocks = <&cpg CPG_MO
1305 dmas = <&dmac1 0x41>,
1306 <&dmac2 0x41>,
1307 dma-names = "tx", "rx
1308 power-domains = <&sys
1309 resets = <&cpg 211>;
1310 #address-cells = <1>;
1311 #size-cells = <0>;
1312 status = "disabled";
1313 };
1314
1315 msiof1: spi@e6ea0000 {
1316 compatible = "renesas
1317 "renesas
1318 reg = <0 0xe6ea0000 0
1319 interrupts = <GIC_SPI
1320 clocks = <&cpg CPG_MO
1321 dmas = <&dmac1 0x43>,
1322 <&dmac2 0x43>,
1323 dma-names = "tx", "rx
1324 power-domains = <&sys
1325 resets = <&cpg 210>;
1326 #address-cells = <1>;
1327 #size-cells = <0>;
1328 status = "disabled";
1329 };
1330
1331 msiof2: spi@e6c00000 {
1332 compatible = "renesas
1333 "renesas
1334 reg = <0 0xe6c00000 0
1335 interrupts = <GIC_SPI
1336 clocks = <&cpg CPG_MO
1337 dmas = <&dmac0 0x45>,
1338 dma-names = "tx", "rx
1339 power-domains = <&sys
1340 resets = <&cpg 209>;
1341 #address-cells = <1>;
1342 #size-cells = <0>;
1343 status = "disabled";
1344 };
1345
1346 msiof3: spi@e6c10000 {
1347 compatible = "renesas
1348 "renesas
1349 reg = <0 0xe6c10000 0
1350 interrupts = <GIC_SPI
1351 clocks = <&cpg CPG_MO
1352 dmas = <&dmac0 0x47>,
1353 dma-names = "tx", "rx
1354 power-domains = <&sys
1355 resets = <&cpg 208>;
1356 #address-cells = <1>;
1357 #size-cells = <0>;
1358 status = "disabled";
1359 };
1360
1361 vin0: video@e6ef0000 {
1362 compatible = "renesas
1363 reg = <0 0xe6ef0000 0
1364 interrupts = <GIC_SPI
1365 clocks = <&cpg CPG_MO
1366 power-domains = <&sys
1367 resets = <&cpg 811>;
1368 renesas,id = <0>;
1369 status = "disabled";
1370
1371 ports {
1372 #address-cell
1373 #size-cells =
1374
1375 port@1 {
1376 #addr
1377 #size
1378
1379 reg =
1380
1381 vin0c
1382
1383
1384 };
1385 vin0c
1386
1387
1388 };
1389 };
1390 };
1391 };
1392
1393 vin1: video@e6ef1000 {
1394 compatible = "renesas
1395 reg = <0 0xe6ef1000 0
1396 interrupts = <GIC_SPI
1397 clocks = <&cpg CPG_MO
1398 power-domains = <&sys
1399 resets = <&cpg 810>;
1400 renesas,id = <1>;
1401 status = "disabled";
1402
1403 ports {
1404 #address-cell
1405 #size-cells =
1406
1407 port@1 {
1408 #addr
1409 #size
1410
1411 reg =
1412
1413 vin1c
1414
1415
1416 };
1417 vin1c
1418
1419
1420 };
1421 };
1422 };
1423 };
1424
1425 vin2: video@e6ef2000 {
1426 compatible = "renesas
1427 reg = <0 0xe6ef2000 0
1428 interrupts = <GIC_SPI
1429 clocks = <&cpg CPG_MO
1430 power-domains = <&sys
1431 resets = <&cpg 809>;
1432 renesas,id = <2>;
1433 status = "disabled";
1434
1435 ports {
1436 #address-cell
1437 #size-cells =
1438
1439 port@1 {
1440 #addr
1441 #size
1442
1443 reg =
1444
1445 vin2c
1446
1447
1448 };
1449 vin2c
1450
1451
1452 };
1453 };
1454 };
1455 };
1456
1457 vin3: video@e6ef3000 {
1458 compatible = "renesas
1459 reg = <0 0xe6ef3000 0
1460 interrupts = <GIC_SPI
1461 clocks = <&cpg CPG_MO
1462 power-domains = <&sys
1463 resets = <&cpg 808>;
1464 renesas,id = <3>;
1465 status = "disabled";
1466
1467 ports {
1468 #address-cell
1469 #size-cells =
1470
1471 port@1 {
1472 #addr
1473 #size
1474
1475 reg =
1476
1477 vin3c
1478
1479
1480 };
1481 vin3c
1482
1483
1484 };
1485 };
1486 };
1487 };
1488
1489 vin4: video@e6ef4000 {
1490 compatible = "renesas
1491 reg = <0 0xe6ef4000 0
1492 interrupts = <GIC_SPI
1493 clocks = <&cpg CPG_MO
1494 power-domains = <&sys
1495 resets = <&cpg 807>;
1496 renesas,id = <4>;
1497 status = "disabled";
1498
1499 ports {
1500 #address-cell
1501 #size-cells =
1502
1503 port@1 {
1504 #addr
1505 #size
1506
1507 reg =
1508
1509 vin4c
1510
1511
1512 };
1513 vin4c
1514
1515
1516 };
1517 };
1518 };
1519 };
1520
1521 vin5: video@e6ef5000 {
1522 compatible = "renesas
1523 reg = <0 0xe6ef5000 0
1524 interrupts = <GIC_SPI
1525 clocks = <&cpg CPG_MO
1526 power-domains = <&sys
1527 resets = <&cpg 806>;
1528 renesas,id = <5>;
1529 status = "disabled";
1530
1531 ports {
1532 #address-cell
1533 #size-cells =
1534
1535 port@1 {
1536 #addr
1537 #size
1538
1539 reg =
1540
1541 vin5c
1542
1543
1544 };
1545 vin5c
1546
1547
1548 };
1549 };
1550 };
1551 };
1552
1553 vin6: video@e6ef6000 {
1554 compatible = "renesas
1555 reg = <0 0xe6ef6000 0
1556 interrupts = <GIC_SPI
1557 clocks = <&cpg CPG_MO
1558 power-domains = <&sys
1559 resets = <&cpg 805>;
1560 renesas,id = <6>;
1561 status = "disabled";
1562
1563 ports {
1564 #address-cell
1565 #size-cells =
1566
1567 port@1 {
1568 #addr
1569 #size
1570
1571 reg =
1572
1573 vin6c
1574
1575
1576 };
1577 vin6c
1578
1579
1580 };
1581 };
1582 };
1583 };
1584
1585 vin7: video@e6ef7000 {
1586 compatible = "renesas
1587 reg = <0 0xe6ef7000 0
1588 interrupts = <GIC_SPI
1589 clocks = <&cpg CPG_MO
1590 power-domains = <&sys
1591 resets = <&cpg 804>;
1592 renesas,id = <7>;
1593 status = "disabled";
1594
1595 ports {
1596 #address-cell
1597 #size-cells =
1598
1599 port@1 {
1600 #addr
1601 #size
1602
1603 reg =
1604
1605 vin7c
1606
1607
1608 };
1609 vin7c
1610
1611
1612 };
1613 };
1614 };
1615 };
1616
1617 drif00: rif@e6f40000 {
1618 compatible = "renesas
1619 "renesas
1620 reg = <0 0xe6f40000 0
1621 interrupts = <GIC_SPI
1622 clocks = <&cpg CPG_MO
1623 clock-names = "fck";
1624 dmas = <&dmac1 0x20>,
1625 dma-names = "rx", "rx
1626 power-domains = <&sys
1627 resets = <&cpg 515>;
1628 renesas,bonding = <&d
1629 status = "disabled";
1630 };
1631
1632 drif01: rif@e6f50000 {
1633 compatible = "renesas
1634 "renesas
1635 reg = <0 0xe6f50000 0
1636 interrupts = <GIC_SPI
1637 clocks = <&cpg CPG_MO
1638 clock-names = "fck";
1639 dmas = <&dmac1 0x22>,
1640 dma-names = "rx", "rx
1641 power-domains = <&sys
1642 resets = <&cpg 514>;
1643 renesas,bonding = <&d
1644 status = "disabled";
1645 };
1646
1647 drif10: rif@e6f60000 {
1648 compatible = "renesas
1649 "renesas
1650 reg = <0 0xe6f60000 0
1651 interrupts = <GIC_SPI
1652 clocks = <&cpg CPG_MO
1653 clock-names = "fck";
1654 dmas = <&dmac1 0x24>,
1655 dma-names = "rx", "rx
1656 power-domains = <&sys
1657 resets = <&cpg 513>;
1658 renesas,bonding = <&d
1659 status = "disabled";
1660 };
1661
1662 drif11: rif@e6f70000 {
1663 compatible = "renesas
1664 "renesas
1665 reg = <0 0xe6f70000 0
1666 interrupts = <GIC_SPI
1667 clocks = <&cpg CPG_MO
1668 clock-names = "fck";
1669 dmas = <&dmac1 0x26>,
1670 dma-names = "rx", "rx
1671 power-domains = <&sys
1672 resets = <&cpg 512>;
1673 renesas,bonding = <&d
1674 status = "disabled";
1675 };
1676
1677 drif20: rif@e6f80000 {
1678 compatible = "renesas
1679 "renesas
1680 reg = <0 0xe6f80000 0
1681 interrupts = <GIC_SPI
1682 clocks = <&cpg CPG_MO
1683 clock-names = "fck";
1684 dmas = <&dmac1 0x28>,
1685 dma-names = "rx", "rx
1686 power-domains = <&sys
1687 resets = <&cpg 511>;
1688 renesas,bonding = <&d
1689 status = "disabled";
1690 };
1691
1692 drif21: rif@e6f90000 {
1693 compatible = "renesas
1694 "renesas
1695 reg = <0 0xe6f90000 0
1696 interrupts = <GIC_SPI
1697 clocks = <&cpg CPG_MO
1698 clock-names = "fck";
1699 dmas = <&dmac1 0x2a>,
1700 dma-names = "rx", "rx
1701 power-domains = <&sys
1702 resets = <&cpg 510>;
1703 renesas,bonding = <&d
1704 status = "disabled";
1705 };
1706
1707 drif30: rif@e6fa0000 {
1708 compatible = "renesas
1709 "renesas
1710 reg = <0 0xe6fa0000 0
1711 interrupts = <GIC_SPI
1712 clocks = <&cpg CPG_MO
1713 clock-names = "fck";
1714 dmas = <&dmac1 0x2c>,
1715 dma-names = "rx", "rx
1716 power-domains = <&sys
1717 resets = <&cpg 509>;
1718 renesas,bonding = <&d
1719 status = "disabled";
1720 };
1721
1722 drif31: rif@e6fb0000 {
1723 compatible = "renesas
1724 "renesas
1725 reg = <0 0xe6fb0000 0
1726 interrupts = <GIC_SPI
1727 clocks = <&cpg CPG_MO
1728 clock-names = "fck";
1729 dmas = <&dmac1 0x2e>,
1730 dma-names = "rx", "rx
1731 power-domains = <&sys
1732 resets = <&cpg 508>;
1733 renesas,bonding = <&d
1734 status = "disabled";
1735 };
1736
1737 rcar_sound: sound@ec500000 {
1738 /*
1739 * #sound-dai-cells i
1740 *
1741 * Single DAI : #soun
1742 * Multi DAI : #soun
1743 */
1744 /*
1745 * #clock-cells is re
1746 *
1747 * clkout : #cl
1748 * clkout0/1/2/3: #cl
1749 */
1750 compatible = "renesas
1751 reg = <0 0xec500000 0
1752 <0 0xec5a0000 0
1753 <0 0xec540000 0
1754 <0 0xec541000 0
1755 <0 0xec760000 0
1756 reg-names = "scu", "a
1757
1758 clocks = <&cpg CPG_MO
1759 <&cpg CPG_MO
1760 <&cpg CPG_MO
1761 <&cpg CPG_MO
1762 <&cpg CPG_MO
1763 <&cpg CPG_MO
1764 <&cpg CPG_MO
1765 <&cpg CPG_MO
1766 <&cpg CPG_MO
1767 <&cpg CPG_MO
1768 <&cpg CPG_MO
1769 <&cpg CPG_MO
1770 <&cpg CPG_MO
1771 <&cpg CPG_MO
1772 <&audio_clk_
1773 <&audio_clk_
1774 <&cpg CPG_MO
1775 clock-names = "ssi-al
1776 "ssi.9"
1777 "ssi.5"
1778 "ssi.1"
1779 "src.9"
1780 "src.5"
1781 "src.1"
1782 "mix.1"
1783 "ctu.1"
1784 "dvc.0"
1785 "clk_a"
1786 power-domains = <&sys
1787 resets = <&cpg 1005>,
1788 <&cpg 1006>,
1789 <&cpg 1008>,
1790 <&cpg 1010>,
1791 <&cpg 1012>,
1792 <&cpg 1014>,
1793 reset-names = "ssi-al
1794 "ssi.9"
1795 "ssi.5"
1796 "ssi.1"
1797 status = "disabled";
1798
1799 rcar_sound,dvc {
1800 dvc0: dvc-0 {
1801 dmas
1802 dma-n
1803 };
1804 dvc1: dvc-1 {
1805 dmas
1806 dma-n
1807 };
1808 };
1809
1810 rcar_sound,mix {
1811 mix0: mix-0 {
1812 mix1: mix-1 {
1813 };
1814
1815 rcar_sound,ctu {
1816 ctu00: ctu-0
1817 ctu01: ctu-1
1818 ctu02: ctu-2
1819 ctu03: ctu-3
1820 ctu10: ctu-4
1821 ctu11: ctu-5
1822 ctu12: ctu-6
1823 ctu13: ctu-7
1824 };
1825
1826 rcar_sound,src {
1827 src0: src-0 {
1828 inter
1829 dmas
1830 dma-n
1831 };
1832 src1: src-1 {
1833 inter
1834 dmas
1835 dma-n
1836 };
1837 src2: src-2 {
1838 inter
1839 dmas
1840 dma-n
1841 };
1842 src3: src-3 {
1843 inter
1844 dmas
1845 dma-n
1846 };
1847 src4: src-4 {
1848 inter
1849 dmas
1850 dma-n
1851 };
1852 src5: src-5 {
1853 inter
1854 dmas
1855 dma-n
1856 };
1857 src6: src-6 {
1858 inter
1859 dmas
1860 dma-n
1861 };
1862 src7: src-7 {
1863 inter
1864 dmas
1865 dma-n
1866 };
1867 src8: src-8 {
1868 inter
1869 dmas
1870 dma-n
1871 };
1872 src9: src-9 {
1873 inter
1874 dmas
1875 dma-n
1876 };
1877 };
1878
1879 rcar_sound,ssiu {
1880 ssiu00: ssiu-
1881 dmas
1882 dma-n
1883 };
1884 ssiu01: ssiu-
1885 dmas
1886 dma-n
1887 };
1888 ssiu02: ssiu-
1889 dmas
1890 dma-n
1891 };
1892 ssiu03: ssiu-
1893 dmas
1894 dma-n
1895 };
1896 ssiu04: ssiu-
1897 dmas
1898 dma-n
1899 };
1900 ssiu05: ssiu-
1901 dmas
1902 dma-n
1903 };
1904 ssiu06: ssiu-
1905 dmas
1906 dma-n
1907 };
1908 ssiu07: ssiu-
1909 dmas
1910 dma-n
1911 };
1912 ssiu10: ssiu-
1913 dmas
1914 dma-n
1915 };
1916 ssiu11: ssiu-
1917 dmas
1918 dma-n
1919 };
1920 ssiu12: ssiu-
1921 dmas
1922 dma-n
1923 };
1924 ssiu13: ssiu-
1925 dmas
1926 dma-n
1927 };
1928 ssiu14: ssiu-
1929 dmas
1930 dma-n
1931 };
1932 ssiu15: ssiu-
1933 dmas
1934 dma-n
1935 };
1936 ssiu16: ssiu-
1937 dmas
1938 dma-n
1939 };
1940 ssiu17: ssiu-
1941 dmas
1942 dma-n
1943 };
1944 ssiu20: ssiu-
1945 dmas
1946 dma-n
1947 };
1948 ssiu21: ssiu-
1949 dmas
1950 dma-n
1951 };
1952 ssiu22: ssiu-
1953 dmas
1954 dma-n
1955 };
1956 ssiu23: ssiu-
1957 dmas
1958 dma-n
1959 };
1960 ssiu24: ssiu-
1961 dmas
1962 dma-n
1963 };
1964 ssiu25: ssiu-
1965 dmas
1966 dma-n
1967 };
1968 ssiu26: ssiu-
1969 dmas
1970 dma-n
1971 };
1972 ssiu27: ssiu-
1973 dmas
1974 dma-n
1975 };
1976 ssiu30: ssiu-
1977 dmas
1978 dma-n
1979 };
1980 ssiu31: ssiu-
1981 dmas
1982 dma-n
1983 };
1984 ssiu32: ssiu-
1985 dmas
1986 dma-n
1987 };
1988 ssiu33: ssiu-
1989 dmas
1990 dma-n
1991 };
1992 ssiu34: ssiu-
1993 dmas
1994 dma-n
1995 };
1996 ssiu35: ssiu-
1997 dmas
1998 dma-n
1999 };
2000 ssiu36: ssiu-
2001 dmas
2002 dma-n
2003 };
2004 ssiu37: ssiu-
2005 dmas
2006 dma-n
2007 };
2008 ssiu40: ssiu-
2009 dmas
2010 dma-n
2011 };
2012 ssiu41: ssiu-
2013 dmas
2014 dma-n
2015 };
2016 ssiu42: ssiu-
2017 dmas
2018 dma-n
2019 };
2020 ssiu43: ssiu-
2021 dmas
2022 dma-n
2023 };
2024 ssiu44: ssiu-
2025 dmas
2026 dma-n
2027 };
2028 ssiu45: ssiu-
2029 dmas
2030 dma-n
2031 };
2032 ssiu46: ssiu-
2033 dmas
2034 dma-n
2035 };
2036 ssiu47: ssiu-
2037 dmas
2038 dma-n
2039 };
2040 ssiu50: ssiu-
2041 dmas
2042 dma-n
2043 };
2044 ssiu60: ssiu-
2045 dmas
2046 dma-n
2047 };
2048 ssiu70: ssiu-
2049 dmas
2050 dma-n
2051 };
2052 ssiu80: ssiu-
2053 dmas
2054 dma-n
2055 };
2056 ssiu90: ssiu-
2057 dmas
2058 dma-n
2059 };
2060 ssiu91: ssiu-
2061 dmas
2062 dma-n
2063 };
2064 ssiu92: ssiu-
2065 dmas
2066 dma-n
2067 };
2068 ssiu93: ssiu-
2069 dmas
2070 dma-n
2071 };
2072 ssiu94: ssiu-
2073 dmas
2074 dma-n
2075 };
2076 ssiu95: ssiu-
2077 dmas
2078 dma-n
2079 };
2080 ssiu96: ssiu-
2081 dmas
2082 dma-n
2083 };
2084 ssiu97: ssiu-
2085 dmas
2086 dma-n
2087 };
2088 };
2089
2090 rcar_sound,ssi {
2091 ssi0: ssi-0 {
2092 inter
2093 dmas
2094 dma-n
2095 };
2096 ssi1: ssi-1 {
2097 inter
2098 dmas
2099 dma-n
2100 };
2101 ssi2: ssi-2 {
2102 inter
2103 dmas
2104 dma-n
2105 };
2106 ssi3: ssi-3 {
2107 inter
2108 dmas
2109 dma-n
2110 };
2111 ssi4: ssi-4 {
2112 inter
2113 dmas
2114 dma-n
2115 };
2116 ssi5: ssi-5 {
2117 inter
2118 dmas
2119 dma-n
2120 };
2121 ssi6: ssi-6 {
2122 inter
2123 dmas
2124 dma-n
2125 };
2126 ssi7: ssi-7 {
2127 inter
2128 dmas
2129 dma-n
2130 };
2131 ssi8: ssi-8 {
2132 inter
2133 dmas
2134 dma-n
2135 };
2136 ssi9: ssi-9 {
2137 inter
2138 dmas
2139 dma-n
2140 };
2141 };
2142 };
2143
2144 mlp: mlp@ec520000 {
2145 compatible = "renesas
2146 "renesas
2147 reg = <0 0xec520000 0
2148 interrupts = <GIC_SPI
2149 <GIC_SPI 385
2150 clocks = <&cpg CPG_MO
2151 power-domains = <&sys
2152 resets = <&cpg 802>;
2153 status = "disabled";
2154 };
2155
2156 audma0: dma-controller@ec7000
2157 compatible = "renesas
2158 "renesas
2159 reg = <0 0xec700000 0
2160 interrupts = <GIC_SPI
2161 <GIC_SPI
2162 <GIC_SPI
2163 <GIC_SPI
2164 <GIC_SPI
2165 <GIC_SPI
2166 <GIC_SPI
2167 <GIC_SPI
2168 <GIC_SPI
2169 <GIC_SPI
2170 <GIC_SPI
2171 <GIC_SPI
2172 <GIC_SPI
2173 <GIC_SPI
2174 <GIC_SPI
2175 <GIC_SPI
2176 <GIC_SPI
2177 interrupt-names = "er
2178 "ch0"
2179 "ch4"
2180 "ch8"
2181 "ch12
2182 clocks = <&cpg CPG_MO
2183 clock-names = "fck";
2184 power-domains = <&sys
2185 resets = <&cpg 502>;
2186 #dma-cells = <1>;
2187 dma-channels = <16>;
2188 iommus = <&ipmmu_mp 0
2189 <&ipmmu_mp 2
2190 <&ipmmu_mp 4
2191 <&ipmmu_mp 6
2192 <&ipmmu_mp 8
2193 <&ipmmu_mp 1
2194 <&ipmmu_mp 1
2195 <&ipmmu_mp 1
2196 };
2197
2198 audma1: dma-controller@ec7200
2199 compatible = "renesas
2200 "renesas
2201 reg = <0 0xec720000 0
2202 interrupts = <GIC_SPI
2203 <GIC_SPI
2204 <GIC_SPI
2205 <GIC_SPI
2206 <GIC_SPI
2207 <GIC_SPI
2208 <GIC_SPI
2209 <GIC_SPI
2210 <GIC_SPI
2211 <GIC_SPI
2212 <GIC_SPI
2213 <GIC_SPI
2214 <GIC_SPI
2215 <GIC_SPI
2216 <GIC_SPI
2217 <GIC_SPI
2218 <GIC_SPI
2219 interrupt-names = "er
2220 "ch0"
2221 "ch4"
2222 "ch8"
2223 "ch12
2224 clocks = <&cpg CPG_MO
2225 clock-names = "fck";
2226 power-domains = <&sys
2227 resets = <&cpg 501>;
2228 #dma-cells = <1>;
2229 dma-channels = <16>;
2230 iommus = <&ipmmu_mp 1
2231 <&ipmmu_mp 1
2232 <&ipmmu_mp 2
2233 <&ipmmu_mp 2
2234 <&ipmmu_mp 2
2235 <&ipmmu_mp 2
2236 <&ipmmu_mp 2
2237 <&ipmmu_mp 3
2238 };
2239
2240 xhci0: usb@ee000000 {
2241 compatible = "renesas
2242 "renesas
2243 reg = <0 0xee000000 0
2244 interrupts = <GIC_SPI
2245 clocks = <&cpg CPG_MO
2246 power-domains = <&sys
2247 resets = <&cpg 328>;
2248 status = "disabled";
2249 };
2250
2251 usb3_peri0: usb@ee020000 {
2252 compatible = "renesas
2253 "renesas
2254 reg = <0 0xee020000 0
2255 interrupts = <GIC_SPI
2256 clocks = <&cpg CPG_MO
2257 power-domains = <&sys
2258 resets = <&cpg 328>;
2259 status = "disabled";
2260 };
2261
2262 ohci0: usb@ee080000 {
2263 compatible = "generic
2264 reg = <0 0xee080000 0
2265 interrupts = <GIC_SPI
2266 clocks = <&cpg CPG_MO
2267 phys = <&usb2_phy0 1>
2268 phy-names = "usb";
2269 power-domains = <&sys
2270 resets = <&cpg 703>,
2271 status = "disabled";
2272 };
2273
2274 ohci1: usb@ee0a0000 {
2275 compatible = "generic
2276 reg = <0 0xee0a0000 0
2277 interrupts = <GIC_SPI
2278 clocks = <&cpg CPG_MO
2279 phys = <&usb2_phy1 1>
2280 phy-names = "usb";
2281 power-domains = <&sys
2282 resets = <&cpg 702>;
2283 status = "disabled";
2284 };
2285
2286 ehci0: usb@ee080100 {
2287 compatible = "generic
2288 reg = <0 0xee080100 0
2289 interrupts = <GIC_SPI
2290 clocks = <&cpg CPG_MO
2291 phys = <&usb2_phy0 2>
2292 phy-names = "usb";
2293 companion = <&ohci0>;
2294 power-domains = <&sys
2295 resets = <&cpg 703>,
2296 status = "disabled";
2297 };
2298
2299 ehci1: usb@ee0a0100 {
2300 compatible = "generic
2301 reg = <0 0xee0a0100 0
2302 interrupts = <GIC_SPI
2303 clocks = <&cpg CPG_MO
2304 phys = <&usb2_phy1 2>
2305 phy-names = "usb";
2306 companion = <&ohci1>;
2307 power-domains = <&sys
2308 resets = <&cpg 702>;
2309 status = "disabled";
2310 };
2311
2312 usb2_phy0: usb-phy@ee080200 {
2313 compatible = "renesas
2314 "renesas
2315 reg = <0 0xee080200 0
2316 interrupts = <GIC_SPI
2317 clocks = <&cpg CPG_MO
2318 power-domains = <&sys
2319 resets = <&cpg 703>,
2320 #phy-cells = <1>;
2321 status = "disabled";
2322 };
2323
2324 usb2_phy1: usb-phy@ee0a0200 {
2325 compatible = "renesas
2326 "renesas
2327 reg = <0 0xee0a0200 0
2328 clocks = <&cpg CPG_MO
2329 power-domains = <&sys
2330 resets = <&cpg 702>;
2331 #phy-cells = <1>;
2332 status = "disabled";
2333 };
2334
2335 sdhi0: mmc@ee100000 {
2336 compatible = "renesas
2337 "renesas
2338 reg = <0 0xee100000 0
2339 interrupts = <GIC_SPI
2340 clocks = <&cpg CPG_MO
2341 clock-names = "core",
2342 max-frequency = <2000
2343 power-domains = <&sys
2344 resets = <&cpg 314>;
2345 iommus = <&ipmmu_ds1
2346 status = "disabled";
2347 };
2348
2349 sdhi1: mmc@ee120000 {
2350 compatible = "renesas
2351 "renesas
2352 reg = <0 0xee120000 0
2353 interrupts = <GIC_SPI
2354 clocks = <&cpg CPG_MO
2355 clock-names = "core",
2356 max-frequency = <2000
2357 power-domains = <&sys
2358 resets = <&cpg 313>;
2359 iommus = <&ipmmu_ds1
2360 status = "disabled";
2361 };
2362
2363 sdhi2: mmc@ee140000 {
2364 compatible = "renesas
2365 "renesas
2366 reg = <0 0xee140000 0
2367 interrupts = <GIC_SPI
2368 clocks = <&cpg CPG_MO
2369 clock-names = "core",
2370 max-frequency = <2000
2371 power-domains = <&sys
2372 resets = <&cpg 312>;
2373 iommus = <&ipmmu_ds1
2374 status = "disabled";
2375 };
2376
2377 sdhi3: mmc@ee160000 {
2378 compatible = "renesas
2379 "renesas
2380 reg = <0 0xee160000 0
2381 interrupts = <GIC_SPI
2382 clocks = <&cpg CPG_MO
2383 clock-names = "core",
2384 max-frequency = <2000
2385 power-domains = <&sys
2386 resets = <&cpg 311>;
2387 iommus = <&ipmmu_ds1
2388 status = "disabled";
2389 };
2390
2391 rpc: spi@ee200000 {
2392 compatible = "renesas
2393 "renesas
2394 reg = <0 0xee200000 0
2395 <0 0x08000000 0
2396 <0 0xee208000 0
2397 reg-names = "regs", "
2398 interrupts = <GIC_SPI
2399 clocks = <&cpg CPG_MO
2400 power-domains = <&sys
2401 resets = <&cpg 917>;
2402 #address-cells = <1>;
2403 #size-cells = <0>;
2404 status = "disabled";
2405 };
2406
2407 sata: sata@ee300000 {
2408 compatible = "renesas
2409 "renesas
2410 reg = <0 0xee300000 0
2411 interrupts = <GIC_SPI
2412 clocks = <&cpg CPG_MO
2413 power-domains = <&sys
2414 resets = <&cpg 815>;
2415 iommus = <&ipmmu_hc 2
2416 status = "disabled";
2417 };
2418
2419 gic: interrupt-controller@f10
2420 compatible = "arm,gic
2421 #interrupt-cells = <3
2422 #address-cells = <0>;
2423 interrupt-controller;
2424 reg = <0x0 0xf1010000
2425 <0x0 0xf1020000
2426 <0x0 0xf1040000
2427 <0x0 0xf1060000
2428 interrupts = <GIC_PPI
2429 (GIC_
2430 clocks = <&cpg CPG_MO
2431 clock-names = "clk";
2432 power-domains = <&sys
2433 resets = <&cpg 408>;
2434 };
2435
2436 pciec0: pcie@fe000000 {
2437 compatible = "renesas
2438 "renesas
2439 reg = <0 0xfe000000 0
2440 #address-cells = <3>;
2441 #size-cells = <2>;
2442 bus-range = <0x00 0xf
2443 device_type = "pci";
2444 ranges = <0x01000000
2445 <0x02000000
2446 <0x02000000
2447 <0x42000000
2448 /* Map all possible D
2449 dma-ranges = <0x42000
2450 interrupts = <GIC_SPI
2451 <GIC_SPI 117
2452 <GIC_SPI 118
2453 #interrupt-cells = <1
2454 interrupt-map-mask =
2455 interrupt-map = <0 0
2456 clocks = <&cpg CPG_MO
2457 clock-names = "pcie",
2458 power-domains = <&sys
2459 resets = <&cpg 319>;
2460 iommu-map = <0 &ipmmu
2461 iommu-map-mask = <0>;
2462 status = "disabled";
2463 };
2464
2465 pciec1: pcie@ee800000 {
2466 compatible = "renesas
2467 "renesas
2468 reg = <0 0xee800000 0
2469 #address-cells = <3>;
2470 #size-cells = <2>;
2471 bus-range = <0x00 0xf
2472 device_type = "pci";
2473 ranges = <0x01000000
2474 <0x02000000
2475 <0x02000000
2476 <0x42000000
2477 /* Map all possible D
2478 dma-ranges = <0x42000
2479 interrupts = <GIC_SPI
2480 <GIC_SPI 149
2481 <GIC_SPI 150
2482 #interrupt-cells = <1
2483 interrupt-map-mask =
2484 interrupt-map = <0 0
2485 clocks = <&cpg CPG_MO
2486 clock-names = "pcie",
2487 power-domains = <&sys
2488 resets = <&cpg 318>;
2489 iommu-map = <0 &ipmmu
2490 iommu-map-mask = <0>;
2491 status = "disabled";
2492 };
2493
2494 fdp1@fe940000 {
2495 compatible = "renesas
2496 reg = <0 0xfe940000 0
2497 interrupts = <GIC_SPI
2498 clocks = <&cpg CPG_MO
2499 power-domains = <&sys
2500 resets = <&cpg 119>;
2501 renesas,fcp = <&fcpf0
2502 };
2503
2504 fcpf0: fcp@fe950000 {
2505 compatible = "renesas
2506 reg = <0 0xfe950000 0
2507 clocks = <&cpg CPG_MO
2508 power-domains = <&sys
2509 resets = <&cpg 615>;
2510 iommus = <&ipmmu_vp0
2511 };
2512
2513 vspb: vsp@fe960000 {
2514 compatible = "renesas
2515 reg = <0 0xfe960000 0
2516 interrupts = <GIC_SPI
2517 clocks = <&cpg CPG_MO
2518 power-domains = <&sys
2519 resets = <&cpg 626>;
2520
2521 renesas,fcp = <&fcpvb
2522 };
2523
2524 vspi0: vsp@fe9a0000 {
2525 compatible = "renesas
2526 reg = <0 0xfe9a0000 0
2527 interrupts = <GIC_SPI
2528 clocks = <&cpg CPG_MO
2529 power-domains = <&sys
2530 resets = <&cpg 631>;
2531
2532 renesas,fcp = <&fcpvi
2533 };
2534
2535 vspd0: vsp@fea20000 {
2536 compatible = "renesas
2537 reg = <0 0xfea20000 0
2538 interrupts = <GIC_SPI
2539 clocks = <&cpg CPG_MO
2540 power-domains = <&sys
2541 resets = <&cpg 623>;
2542
2543 renesas,fcp = <&fcpvd
2544 };
2545
2546 vspd1: vsp@fea28000 {
2547 compatible = "renesas
2548 reg = <0 0xfea28000 0
2549 interrupts = <GIC_SPI
2550 clocks = <&cpg CPG_MO
2551 power-domains = <&sys
2552 resets = <&cpg 622>;
2553
2554 renesas,fcp = <&fcpvd
2555 };
2556
2557 fcpvb0: fcp@fe96f000 {
2558 compatible = "renesas
2559 reg = <0 0xfe96f000 0
2560 clocks = <&cpg CPG_MO
2561 power-domains = <&sys
2562 resets = <&cpg 607>;
2563 iommus = <&ipmmu_vp0
2564 };
2565
2566 fcpvd0: fcp@fea27000 {
2567 compatible = "renesas
2568 reg = <0 0xfea27000 0
2569 clocks = <&cpg CPG_MO
2570 power-domains = <&sys
2571 resets = <&cpg 603>;
2572 iommus = <&ipmmu_vi0
2573 };
2574
2575 fcpvd1: fcp@fea2f000 {
2576 compatible = "renesas
2577 reg = <0 0xfea2f000 0
2578 clocks = <&cpg CPG_MO
2579 power-domains = <&sys
2580 resets = <&cpg 602>;
2581 iommus = <&ipmmu_vi0
2582 };
2583
2584 fcpvi0: fcp@fe9af000 {
2585 compatible = "renesas
2586 reg = <0 0xfe9af000 0
2587 clocks = <&cpg CPG_MO
2588 power-domains = <&sys
2589 resets = <&cpg 611>;
2590 iommus = <&ipmmu_vp0
2591 };
2592
2593 cmm0: cmm@fea40000 {
2594 compatible = "renesas
2595 "renesas
2596 reg = <0 0xfea40000 0
2597 power-domains = <&sys
2598 clocks = <&cpg CPG_MO
2599 resets = <&cpg 711>;
2600 };
2601
2602 cmm1: cmm@fea50000 {
2603 compatible = "renesas
2604 "renesas
2605 reg = <0 0xfea50000 0
2606 power-domains = <&sys
2607 clocks = <&cpg CPG_MO
2608 resets = <&cpg 710>;
2609 };
2610
2611 cmm3: cmm@fea70000 {
2612 compatible = "renesas
2613 "renesas
2614 reg = <0 0xfea70000 0
2615 power-domains = <&sys
2616 clocks = <&cpg CPG_MO
2617 resets = <&cpg 708>;
2618 };
2619
2620 csi20: csi2@fea80000 {
2621 compatible = "renesas
2622 reg = <0 0xfea80000 0
2623 interrupts = <GIC_SPI
2624 clocks = <&cpg CPG_MO
2625 power-domains = <&sys
2626 resets = <&cpg 714>;
2627 status = "disabled";
2628
2629 ports {
2630 #address-cell
2631 #size-cells =
2632
2633 port@0 {
2634 reg =
2635 };
2636
2637 port@1 {
2638 #addr
2639 #size
2640
2641 reg =
2642
2643 csi20
2644
2645
2646 };
2647 csi20
2648
2649
2650 };
2651 csi20
2652
2653
2654 };
2655 csi20
2656
2657
2658 };
2659 csi20
2660
2661
2662 };
2663 csi20
2664
2665
2666 };
2667 csi20
2668
2669
2670 };
2671 csi20
2672
2673
2674 };
2675 };
2676 };
2677 };
2678
2679 csi40: csi2@feaa0000 {
2680 compatible = "renesas
2681 reg = <0 0xfeaa0000 0
2682 interrupts = <GIC_SPI
2683 clocks = <&cpg CPG_MO
2684 power-domains = <&sys
2685 resets = <&cpg 716>;
2686 status = "disabled";
2687
2688 ports {
2689 #address-cell
2690 #size-cells =
2691
2692 port@0 {
2693 reg =
2694 };
2695
2696 port@1 {
2697 #addr
2698 #size
2699
2700 reg =
2701
2702 csi40
2703
2704
2705 };
2706 csi40
2707
2708
2709 };
2710 csi40
2711
2712
2713 };
2714 csi40
2715
2716
2717 };
2718 csi40
2719
2720
2721 };
2722 csi40
2723
2724
2725 };
2726 csi40
2727
2728
2729 };
2730 csi40
2731
2732
2733 };
2734 };
2735 };
2736 };
2737
2738 hdmi0: hdmi@fead0000 {
2739 compatible = "renesas
2740 "renesas
2741 reg = <0 0xfead0000 0
2742 interrupts = <GIC_SPI
2743 clocks = <&cpg CPG_MO
2744 <&cpg CPG_CO
2745 clock-names = "iahb",
2746 power-domains = <&sys
2747 resets = <&cpg 729>;
2748 status = "disabled";
2749
2750 ports {
2751 #address-cell
2752 #size-cells =
2753 port@0 {
2754 reg =
2755 dw_hd
2756
2757 };
2758 };
2759 port@1 {
2760 reg =
2761 };
2762 };
2763 };
2764
2765 du: display@feb00000 {
2766 compatible = "renesas
2767 reg = <0 0xfeb00000 0
2768 interrupts = <GIC_SPI
2769 <GIC_SPI
2770 <GIC_SPI
2771 clocks = <&cpg CPG_MO
2772 <&cpg CPG_MO
2773 clock-names = "du.0",
2774 resets = <&cpg 724>,
2775 reset-names = "du.0",
2776
2777 renesas,cmms = <&cmm0
2778 renesas,vsps = <&vspd
2779
2780 status = "disabled";
2781
2782 ports {
2783 #address-cell
2784 #size-cells =
2785
2786 port@0 {
2787 reg =
2788 };
2789 port@1 {
2790 reg =
2791 du_ou
2792
2793 };
2794 };
2795 port@2 {
2796 reg =
2797 du_ou
2798
2799 };
2800 };
2801 };
2802 };
2803
2804 lvds0: lvds@feb90000 {
2805 compatible = "renesas
2806 reg = <0 0xfeb90000 0
2807 clocks = <&cpg CPG_MO
2808 power-domains = <&sys
2809 resets = <&cpg 727>;
2810 status = "disabled";
2811
2812 ports {
2813 #address-cell
2814 #size-cells =
2815
2816 port@0 {
2817 reg =
2818 lvds0
2819
2820 };
2821 };
2822 port@1 {
2823 reg =
2824 };
2825 };
2826 };
2827
2828 prr: chipid@fff00044 {
2829 compatible = "renesas
2830 reg = <0 0xfff00044 0
2831 };
2832 };
2833
2834 thermal-zones {
2835 sensor1_thermal: sensor1-ther
2836 polling-delay-passive
2837 polling-delay = <1000
2838 thermal-sensors = <&t
2839 sustainable-power = <
2840
2841 trips {
2842 sensor1_crit:
2843 tempe
2844 hyste
2845 type
2846 };
2847 };
2848 };
2849
2850 sensor2_thermal: sensor2-ther
2851 polling-delay-passive
2852 polling-delay = <1000
2853 thermal-sensors = <&t
2854 sustainable-power = <
2855
2856 trips {
2857 sensor2_crit:
2858 tempe
2859 hyste
2860 type
2861 };
2862 };
2863 };
2864
2865 sensor3_thermal: sensor3-ther
2866 polling-delay-passive
2867 polling-delay = <1000
2868 thermal-sensors = <&t
2869 sustainable-power = <
2870
2871 trips {
2872 target: trip-
2873 /* mi
2874 tempe
2875 hyste
2876 type
2877 };
2878
2879 sensor3_crit:
2880 tempe
2881 hyste
2882 type
2883 };
2884 };
2885
2886 cooling-maps {
2887 map0 {
2888 trip
2889 cooli
2890 contr
2891 };
2892 };
2893 };
2894 };
2895
2896 timer {
2897 compatible = "arm,armv8-timer
2898 interrupts-extended = <&gic G
2899 <&gic G
2900 <&gic G
2901 <&gic G
2902 interrupt-names = "sec-phys",
2903 };
2904
2905 /* External USB clocks - can be overr
2906 usb3s0_clk: usb3s0 {
2907 compatible = "fixed-clock";
2908 #clock-cells = <0>;
2909 clock-frequency = <0>;
2910 };
2911
2912 usb_extal_clk: usb_extal {
2913 compatible = "fixed-clock";
2914 #clock-cells = <0>;
2915 clock-frequency = <0>;
2916 };
2917 };
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