1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * Device Tree Source for the R-Car M3-N (R8A7 3 * Device Tree Source for the R-Car M3-N (R8A77965) SoC
4 * 4 *
5 * Copyright (C) 2018 Jacopo Mondi <jacopo+rene 5 * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
6 * 6 *
7 * Based on r8a7796.dtsi 7 * Based on r8a7796.dtsi
8 * Copyright (C) 2016 Renesas Electronics Corp 8 * Copyright (C) 2016 Renesas Electronics Corp.
9 */ 9 */
10 10
11 #include <dt-bindings/clock/r8a77965-cpg-mssr. 11 #include <dt-bindings/clock/r8a77965-cpg-mssr.h>
12 #include <dt-bindings/interrupt-controller/arm 12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/power/r8a77965-sysc.h> 13 #include <dt-bindings/power/r8a77965-sysc.h>
14 14
15 #define SOC_HAS_SATA 15 #define SOC_HAS_SATA
16 16
17 / { 17 / {
18 compatible = "renesas,r8a77965"; 18 compatible = "renesas,r8a77965";
19 #address-cells = <2>; 19 #address-cells = <2>;
20 #size-cells = <2>; 20 #size-cells = <2>;
21 21
22 /* 22 /*
23 * The external audio clocks are confi 23 * The external audio clocks are configured as 0 Hz fixed frequency
24 * clocks by default. 24 * clocks by default.
25 * Boards that provide audio clocks sh 25 * Boards that provide audio clocks should override them.
26 */ 26 */
27 audio_clk_a: audio_clk_a { 27 audio_clk_a: audio_clk_a {
28 compatible = "fixed-clock"; 28 compatible = "fixed-clock";
29 #clock-cells = <0>; 29 #clock-cells = <0>;
30 clock-frequency = <0>; 30 clock-frequency = <0>;
31 }; 31 };
32 32
33 audio_clk_b: audio_clk_b { 33 audio_clk_b: audio_clk_b {
34 compatible = "fixed-clock"; 34 compatible = "fixed-clock";
35 #clock-cells = <0>; 35 #clock-cells = <0>;
36 clock-frequency = <0>; 36 clock-frequency = <0>;
37 }; 37 };
38 38
39 audio_clk_c: audio_clk_c { 39 audio_clk_c: audio_clk_c {
40 compatible = "fixed-clock"; 40 compatible = "fixed-clock";
41 #clock-cells = <0>; 41 #clock-cells = <0>;
42 clock-frequency = <0>; 42 clock-frequency = <0>;
43 }; 43 };
44 44
45 /* External CAN clock - to be overridd 45 /* External CAN clock - to be overridden by boards that provide it */
46 can_clk: can { 46 can_clk: can {
47 compatible = "fixed-clock"; 47 compatible = "fixed-clock";
48 #clock-cells = <0>; 48 #clock-cells = <0>;
49 clock-frequency = <0>; 49 clock-frequency = <0>;
50 }; 50 };
51 51
52 cluster0_opp: opp-table-0 { 52 cluster0_opp: opp-table-0 {
53 compatible = "operating-points 53 compatible = "operating-points-v2";
54 opp-shared; 54 opp-shared;
55 55
56 opp-500000000 { 56 opp-500000000 {
57 opp-hz = /bits/ 64 <50 57 opp-hz = /bits/ 64 <500000000>;
58 opp-microvolt = <83000 58 opp-microvolt = <830000>;
59 clock-latency-ns = <30 59 clock-latency-ns = <300000>;
60 }; 60 };
61 opp-1000000000 { 61 opp-1000000000 {
62 opp-hz = /bits/ 64 <10 62 opp-hz = /bits/ 64 <1000000000>;
63 opp-microvolt = <83000 63 opp-microvolt = <830000>;
64 clock-latency-ns = <30 64 clock-latency-ns = <300000>;
65 }; 65 };
66 opp-1500000000 { 66 opp-1500000000 {
67 opp-hz = /bits/ 64 <15 67 opp-hz = /bits/ 64 <1500000000>;
68 opp-microvolt = <83000 68 opp-microvolt = <830000>;
69 clock-latency-ns = <30 69 clock-latency-ns = <300000>;
70 opp-suspend; 70 opp-suspend;
71 }; 71 };
72 opp-1600000000 { 72 opp-1600000000 {
73 opp-hz = /bits/ 64 <16 73 opp-hz = /bits/ 64 <1600000000>;
74 opp-microvolt = <90000 74 opp-microvolt = <900000>;
75 clock-latency-ns = <30 75 clock-latency-ns = <300000>;
76 }; 76 };
77 opp-1700000000 { 77 opp-1700000000 {
78 opp-hz = /bits/ 64 <17 78 opp-hz = /bits/ 64 <1700000000>;
79 opp-microvolt = <90000 79 opp-microvolt = <900000>;
80 clock-latency-ns = <30 80 clock-latency-ns = <300000>;
81 }; 81 };
82 opp-1800000000 { 82 opp-1800000000 {
83 opp-hz = /bits/ 64 <18 83 opp-hz = /bits/ 64 <1800000000>;
84 opp-microvolt = <96000 84 opp-microvolt = <960000>;
85 clock-latency-ns = <30 85 clock-latency-ns = <300000>;
86 turbo-mode; 86 turbo-mode;
87 }; 87 };
88 }; 88 };
89 89
90 cpus { 90 cpus {
91 #address-cells = <1>; 91 #address-cells = <1>;
92 #size-cells = <0>; 92 #size-cells = <0>;
93 93
94 a57_0: cpu@0 { 94 a57_0: cpu@0 {
95 compatible = "arm,cort 95 compatible = "arm,cortex-a57";
96 reg = <0x0>; 96 reg = <0x0>;
97 device_type = "cpu"; 97 device_type = "cpu";
98 power-domains = <&sysc 98 power-domains = <&sysc R8A77965_PD_CA57_CPU0>;
99 next-level-cache = <&L 99 next-level-cache = <&L2_CA57>;
100 enable-method = "psci" 100 enable-method = "psci";
101 cpu-idle-states = <&CP 101 cpu-idle-states = <&CPU_SLEEP_0>;
102 #cooling-cells = <2>; 102 #cooling-cells = <2>;
103 dynamic-power-coeffici 103 dynamic-power-coefficient = <854>;
104 clocks = <&cpg CPG_COR 104 clocks = <&cpg CPG_CORE R8A77965_CLK_Z>;
105 operating-points-v2 = 105 operating-points-v2 = <&cluster0_opp>;
106 }; 106 };
107 107
108 a57_1: cpu@1 { 108 a57_1: cpu@1 {
109 compatible = "arm,cort 109 compatible = "arm,cortex-a57";
110 reg = <0x1>; 110 reg = <0x1>;
111 device_type = "cpu"; 111 device_type = "cpu";
112 power-domains = <&sysc 112 power-domains = <&sysc R8A77965_PD_CA57_CPU1>;
113 next-level-cache = <&L 113 next-level-cache = <&L2_CA57>;
114 enable-method = "psci" 114 enable-method = "psci";
115 cpu-idle-states = <&CP 115 cpu-idle-states = <&CPU_SLEEP_0>;
116 clocks = <&cpg CPG_COR 116 clocks = <&cpg CPG_CORE R8A77965_CLK_Z>;
117 operating-points-v2 = 117 operating-points-v2 = <&cluster0_opp>;
118 }; 118 };
119 119
120 L2_CA57: cache-controller-0 { 120 L2_CA57: cache-controller-0 {
121 compatible = "cache"; 121 compatible = "cache";
122 power-domains = <&sysc 122 power-domains = <&sysc R8A77965_PD_CA57_SCU>;
123 cache-unified; 123 cache-unified;
124 cache-level = <2>; 124 cache-level = <2>;
125 }; 125 };
126 126
127 idle-states { 127 idle-states {
128 entry-method = "psci"; 128 entry-method = "psci";
129 129
130 CPU_SLEEP_0: cpu-sleep 130 CPU_SLEEP_0: cpu-sleep-0 {
131 compatible = " 131 compatible = "arm,idle-state";
132 arm,psci-suspe 132 arm,psci-suspend-param = <0x0010000>;
133 local-timer-st 133 local-timer-stop;
134 entry-latency- 134 entry-latency-us = <400>;
135 exit-latency-u 135 exit-latency-us = <500>;
136 min-residency- 136 min-residency-us = <4000>;
137 }; 137 };
138 }; 138 };
139 }; 139 };
140 140
141 extal_clk: extal { 141 extal_clk: extal {
142 compatible = "fixed-clock"; 142 compatible = "fixed-clock";
143 #clock-cells = <0>; 143 #clock-cells = <0>;
144 /* This value must be overridd 144 /* This value must be overridden by the board */
145 clock-frequency = <0>; 145 clock-frequency = <0>;
146 }; 146 };
147 147
148 extalr_clk: extalr { 148 extalr_clk: extalr {
149 compatible = "fixed-clock"; 149 compatible = "fixed-clock";
150 #clock-cells = <0>; 150 #clock-cells = <0>;
151 /* This value must be overridd 151 /* This value must be overridden by the board */
152 clock-frequency = <0>; 152 clock-frequency = <0>;
153 }; 153 };
154 154
155 /* External PCIe clock - can be overri 155 /* External PCIe clock - can be overridden by the board */
156 pcie_bus_clk: pcie_bus { 156 pcie_bus_clk: pcie_bus {
157 compatible = "fixed-clock"; 157 compatible = "fixed-clock";
158 #clock-cells = <0>; 158 #clock-cells = <0>;
159 clock-frequency = <0>; 159 clock-frequency = <0>;
160 }; 160 };
161 161
162 pmu_a57 { 162 pmu_a57 {
163 compatible = "arm,cortex-a57-p 163 compatible = "arm,cortex-a57-pmu";
164 interrupts-extended = <&gic GI 164 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
165 <&gic GI 165 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
166 interrupt-affinity = <&a57_0>, 166 interrupt-affinity = <&a57_0>,
167 <&a57_1>; 167 <&a57_1>;
168 }; 168 };
169 169
170 psci { 170 psci {
171 compatible = "arm,psci-1.0", " 171 compatible = "arm,psci-1.0", "arm,psci-0.2";
172 method = "smc"; 172 method = "smc";
173 }; 173 };
174 174
175 /* External SCIF clock - to be overrid 175 /* External SCIF clock - to be overridden by boards that provide it */
176 scif_clk: scif { 176 scif_clk: scif {
177 compatible = "fixed-clock"; 177 compatible = "fixed-clock";
178 #clock-cells = <0>; 178 #clock-cells = <0>;
179 clock-frequency = <0>; 179 clock-frequency = <0>;
180 }; 180 };
181 181
182 soc { 182 soc {
183 compatible = "simple-bus"; 183 compatible = "simple-bus";
184 interrupt-parent = <&gic>; 184 interrupt-parent = <&gic>;
185 #address-cells = <2>; 185 #address-cells = <2>;
186 #size-cells = <2>; 186 #size-cells = <2>;
187 ranges; 187 ranges;
188 188
189 rwdt: watchdog@e6020000 { 189 rwdt: watchdog@e6020000 {
190 compatible = "renesas, 190 compatible = "renesas,r8a77965-wdt",
191 "renesas, 191 "renesas,rcar-gen3-wdt";
192 reg = <0 0xe6020000 0 192 reg = <0 0xe6020000 0 0x0c>;
193 interrupts = <GIC_SPI 193 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
194 clocks = <&cpg CPG_MOD 194 clocks = <&cpg CPG_MOD 402>;
195 power-domains = <&sysc 195 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
196 resets = <&cpg 402>; 196 resets = <&cpg 402>;
197 status = "disabled"; 197 status = "disabled";
198 }; 198 };
199 199
200 gpio0: gpio@e6050000 { 200 gpio0: gpio@e6050000 {
201 compatible = "renesas, 201 compatible = "renesas,gpio-r8a77965",
202 "renesas, 202 "renesas,rcar-gen3-gpio";
203 reg = <0 0xe6050000 0 203 reg = <0 0xe6050000 0 0x50>;
204 interrupts = <GIC_SPI 204 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
205 #gpio-cells = <2>; 205 #gpio-cells = <2>;
206 gpio-controller; 206 gpio-controller;
207 gpio-ranges = <&pfc 0 207 gpio-ranges = <&pfc 0 0 16>;
208 #interrupt-cells = <2> 208 #interrupt-cells = <2>;
209 interrupt-controller; 209 interrupt-controller;
210 clocks = <&cpg CPG_MOD 210 clocks = <&cpg CPG_MOD 912>;
211 power-domains = <&sysc 211 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
212 resets = <&cpg 912>; 212 resets = <&cpg 912>;
213 }; 213 };
214 214
215 gpio1: gpio@e6051000 { 215 gpio1: gpio@e6051000 {
216 compatible = "renesas, 216 compatible = "renesas,gpio-r8a77965",
217 "renesas, 217 "renesas,rcar-gen3-gpio";
218 reg = <0 0xe6051000 0 218 reg = <0 0xe6051000 0 0x50>;
219 interrupts = <GIC_SPI 219 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
220 #gpio-cells = <2>; 220 #gpio-cells = <2>;
221 gpio-controller; 221 gpio-controller;
222 gpio-ranges = <&pfc 0 222 gpio-ranges = <&pfc 0 32 29>;
223 #interrupt-cells = <2> 223 #interrupt-cells = <2>;
224 interrupt-controller; 224 interrupt-controller;
225 clocks = <&cpg CPG_MOD 225 clocks = <&cpg CPG_MOD 911>;
226 power-domains = <&sysc 226 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
227 resets = <&cpg 911>; 227 resets = <&cpg 911>;
228 }; 228 };
229 229
230 gpio2: gpio@e6052000 { 230 gpio2: gpio@e6052000 {
231 compatible = "renesas, 231 compatible = "renesas,gpio-r8a77965",
232 "renesas, 232 "renesas,rcar-gen3-gpio";
233 reg = <0 0xe6052000 0 233 reg = <0 0xe6052000 0 0x50>;
234 interrupts = <GIC_SPI 234 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
235 #gpio-cells = <2>; 235 #gpio-cells = <2>;
236 gpio-controller; 236 gpio-controller;
237 gpio-ranges = <&pfc 0 237 gpio-ranges = <&pfc 0 64 15>;
238 #interrupt-cells = <2> 238 #interrupt-cells = <2>;
239 interrupt-controller; 239 interrupt-controller;
240 clocks = <&cpg CPG_MOD 240 clocks = <&cpg CPG_MOD 910>;
241 power-domains = <&sysc 241 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
242 resets = <&cpg 910>; 242 resets = <&cpg 910>;
243 }; 243 };
244 244
245 gpio3: gpio@e6053000 { 245 gpio3: gpio@e6053000 {
246 compatible = "renesas, 246 compatible = "renesas,gpio-r8a77965",
247 "renesas, 247 "renesas,rcar-gen3-gpio";
248 reg = <0 0xe6053000 0 248 reg = <0 0xe6053000 0 0x50>;
249 interrupts = <GIC_SPI 249 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
250 #gpio-cells = <2>; 250 #gpio-cells = <2>;
251 gpio-controller; 251 gpio-controller;
252 gpio-ranges = <&pfc 0 252 gpio-ranges = <&pfc 0 96 16>;
253 #interrupt-cells = <2> 253 #interrupt-cells = <2>;
254 interrupt-controller; 254 interrupt-controller;
255 clocks = <&cpg CPG_MOD 255 clocks = <&cpg CPG_MOD 909>;
256 power-domains = <&sysc 256 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
257 resets = <&cpg 909>; 257 resets = <&cpg 909>;
258 }; 258 };
259 259
260 gpio4: gpio@e6054000 { 260 gpio4: gpio@e6054000 {
261 compatible = "renesas, 261 compatible = "renesas,gpio-r8a77965",
262 "renesas, 262 "renesas,rcar-gen3-gpio";
263 reg = <0 0xe6054000 0 263 reg = <0 0xe6054000 0 0x50>;
264 interrupts = <GIC_SPI 264 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
265 #gpio-cells = <2>; 265 #gpio-cells = <2>;
266 gpio-controller; 266 gpio-controller;
267 gpio-ranges = <&pfc 0 267 gpio-ranges = <&pfc 0 128 18>;
268 #interrupt-cells = <2> 268 #interrupt-cells = <2>;
269 interrupt-controller; 269 interrupt-controller;
270 clocks = <&cpg CPG_MOD 270 clocks = <&cpg CPG_MOD 908>;
271 power-domains = <&sysc 271 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
272 resets = <&cpg 908>; 272 resets = <&cpg 908>;
273 }; 273 };
274 274
275 gpio5: gpio@e6055000 { 275 gpio5: gpio@e6055000 {
276 compatible = "renesas, 276 compatible = "renesas,gpio-r8a77965",
277 "renesas, 277 "renesas,rcar-gen3-gpio";
278 reg = <0 0xe6055000 0 278 reg = <0 0xe6055000 0 0x50>;
279 interrupts = <GIC_SPI 279 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
280 #gpio-cells = <2>; 280 #gpio-cells = <2>;
281 gpio-controller; 281 gpio-controller;
282 gpio-ranges = <&pfc 0 282 gpio-ranges = <&pfc 0 160 26>;
283 #interrupt-cells = <2> 283 #interrupt-cells = <2>;
284 interrupt-controller; 284 interrupt-controller;
285 clocks = <&cpg CPG_MOD 285 clocks = <&cpg CPG_MOD 907>;
286 power-domains = <&sysc 286 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
287 resets = <&cpg 907>; 287 resets = <&cpg 907>;
288 }; 288 };
289 289
290 gpio6: gpio@e6055400 { 290 gpio6: gpio@e6055400 {
291 compatible = "renesas, 291 compatible = "renesas,gpio-r8a77965",
292 "renesas, 292 "renesas,rcar-gen3-gpio";
293 reg = <0 0xe6055400 0 293 reg = <0 0xe6055400 0 0x50>;
294 interrupts = <GIC_SPI 294 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
295 #gpio-cells = <2>; 295 #gpio-cells = <2>;
296 gpio-controller; 296 gpio-controller;
297 gpio-ranges = <&pfc 0 297 gpio-ranges = <&pfc 0 192 32>;
298 #interrupt-cells = <2> 298 #interrupt-cells = <2>;
299 interrupt-controller; 299 interrupt-controller;
300 clocks = <&cpg CPG_MOD 300 clocks = <&cpg CPG_MOD 906>;
301 power-domains = <&sysc 301 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
302 resets = <&cpg 906>; 302 resets = <&cpg 906>;
303 }; 303 };
304 304
305 gpio7: gpio@e6055800 { 305 gpio7: gpio@e6055800 {
306 compatible = "renesas, 306 compatible = "renesas,gpio-r8a77965",
307 "renesas, 307 "renesas,rcar-gen3-gpio";
308 reg = <0 0xe6055800 0 308 reg = <0 0xe6055800 0 0x50>;
309 interrupts = <GIC_SPI 309 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
310 #gpio-cells = <2>; 310 #gpio-cells = <2>;
311 gpio-controller; 311 gpio-controller;
312 gpio-ranges = <&pfc 0 312 gpio-ranges = <&pfc 0 224 4>;
313 #interrupt-cells = <2> 313 #interrupt-cells = <2>;
314 interrupt-controller; 314 interrupt-controller;
315 clocks = <&cpg CPG_MOD 315 clocks = <&cpg CPG_MOD 905>;
316 power-domains = <&sysc 316 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
317 resets = <&cpg 905>; 317 resets = <&cpg 905>;
318 }; 318 };
319 319
320 pfc: pinctrl@e6060000 { 320 pfc: pinctrl@e6060000 {
321 compatible = "renesas, 321 compatible = "renesas,pfc-r8a77965";
322 reg = <0 0xe6060000 0 322 reg = <0 0xe6060000 0 0x50c>;
323 }; 323 };
324 324
325 cmt0: timer@e60f0000 { 325 cmt0: timer@e60f0000 {
326 compatible = "renesas, 326 compatible = "renesas,r8a77965-cmt0",
327 "renesas, 327 "renesas,rcar-gen3-cmt0";
328 reg = <0 0xe60f0000 0 328 reg = <0 0xe60f0000 0 0x1004>;
329 interrupts = <GIC_SPI 329 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
330 <GIC_SPI 330 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
331 clocks = <&cpg CPG_MOD 331 clocks = <&cpg CPG_MOD 303>;
332 clock-names = "fck"; 332 clock-names = "fck";
333 power-domains = <&sysc 333 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
334 resets = <&cpg 303>; 334 resets = <&cpg 303>;
335 status = "disabled"; 335 status = "disabled";
336 }; 336 };
337 337
338 cmt1: timer@e6130000 { 338 cmt1: timer@e6130000 {
339 compatible = "renesas, 339 compatible = "renesas,r8a77965-cmt1",
340 "renesas, 340 "renesas,rcar-gen3-cmt1";
341 reg = <0 0xe6130000 0 341 reg = <0 0xe6130000 0 0x1004>;
342 interrupts = <GIC_SPI 342 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
343 <GIC_SPI 343 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
344 <GIC_SPI 344 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
345 <GIC_SPI 345 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
346 <GIC_SPI 346 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
347 <GIC_SPI 347 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
348 <GIC_SPI 348 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
349 <GIC_SPI 349 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
350 clocks = <&cpg CPG_MOD 350 clocks = <&cpg CPG_MOD 302>;
351 clock-names = "fck"; 351 clock-names = "fck";
352 power-domains = <&sysc 352 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
353 resets = <&cpg 302>; 353 resets = <&cpg 302>;
354 status = "disabled"; 354 status = "disabled";
355 }; 355 };
356 356
357 cmt2: timer@e6140000 { 357 cmt2: timer@e6140000 {
358 compatible = "renesas, 358 compatible = "renesas,r8a77965-cmt1",
359 "renesas, 359 "renesas,rcar-gen3-cmt1";
360 reg = <0 0xe6140000 0 360 reg = <0 0xe6140000 0 0x1004>;
361 interrupts = <GIC_SPI 361 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
362 <GIC_SPI 362 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
363 <GIC_SPI 363 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
364 <GIC_SPI 364 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
365 <GIC_SPI 365 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
366 <GIC_SPI 366 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
367 <GIC_SPI 367 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
368 <GIC_SPI 368 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
369 clocks = <&cpg CPG_MOD 369 clocks = <&cpg CPG_MOD 301>;
370 clock-names = "fck"; 370 clock-names = "fck";
371 power-domains = <&sysc 371 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
372 resets = <&cpg 301>; 372 resets = <&cpg 301>;
373 status = "disabled"; 373 status = "disabled";
374 }; 374 };
375 375
376 cmt3: timer@e6148000 { 376 cmt3: timer@e6148000 {
377 compatible = "renesas, 377 compatible = "renesas,r8a77965-cmt1",
378 "renesas, 378 "renesas,rcar-gen3-cmt1";
379 reg = <0 0xe6148000 0 379 reg = <0 0xe6148000 0 0x1004>;
380 interrupts = <GIC_SPI 380 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
381 <GIC_SPI 381 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
382 <GIC_SPI 382 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
383 <GIC_SPI 383 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
384 <GIC_SPI 384 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
385 <GIC_SPI 385 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
386 <GIC_SPI 386 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
387 <GIC_SPI 387 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
388 clocks = <&cpg CPG_MOD 388 clocks = <&cpg CPG_MOD 300>;
389 clock-names = "fck"; 389 clock-names = "fck";
390 power-domains = <&sysc 390 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
391 resets = <&cpg 300>; 391 resets = <&cpg 300>;
392 status = "disabled"; 392 status = "disabled";
393 }; 393 };
394 394
395 cpg: clock-controller@e6150000 395 cpg: clock-controller@e6150000 {
396 compatible = "renesas, 396 compatible = "renesas,r8a77965-cpg-mssr";
397 reg = <0 0xe6150000 0 397 reg = <0 0xe6150000 0 0x1000>;
398 clocks = <&extal_clk>, 398 clocks = <&extal_clk>, <&extalr_clk>;
399 clock-names = "extal", 399 clock-names = "extal", "extalr";
400 #clock-cells = <2>; 400 #clock-cells = <2>;
401 #power-domain-cells = 401 #power-domain-cells = <0>;
402 #reset-cells = <1>; 402 #reset-cells = <1>;
403 }; 403 };
404 404
405 rst: reset-controller@e6160000 405 rst: reset-controller@e6160000 {
406 compatible = "renesas, 406 compatible = "renesas,r8a77965-rst";
407 reg = <0 0xe6160000 0 407 reg = <0 0xe6160000 0 0x0200>;
408 }; 408 };
409 409
410 sysc: system-controller@e61800 410 sysc: system-controller@e6180000 {
411 compatible = "renesas, 411 compatible = "renesas,r8a77965-sysc";
412 reg = <0 0xe6180000 0 412 reg = <0 0xe6180000 0 0x0400>;
413 #power-domain-cells = 413 #power-domain-cells = <1>;
414 }; 414 };
415 415
416 tsc: thermal@e6198000 { 416 tsc: thermal@e6198000 {
417 compatible = "renesas, 417 compatible = "renesas,r8a77965-thermal";
418 reg = <0 0xe6198000 0 418 reg = <0 0xe6198000 0 0x100>,
419 <0 0xe61a0000 0 419 <0 0xe61a0000 0 0x100>,
420 <0 0xe61a8000 0 420 <0 0xe61a8000 0 0x100>;
421 interrupts = <GIC_SPI 421 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
422 <GIC_SPI 422 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
423 <GIC_SPI 423 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
424 clocks = <&cpg CPG_MOD 424 clocks = <&cpg CPG_MOD 522>;
425 power-domains = <&sysc 425 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
426 resets = <&cpg 522>; 426 resets = <&cpg 522>;
427 #thermal-sensor-cells 427 #thermal-sensor-cells = <1>;
428 }; 428 };
429 429
430 intc_ex: interrupt-controller@ 430 intc_ex: interrupt-controller@e61c0000 {
431 compatible = "renesas, 431 compatible = "renesas,intc-ex-r8a77965", "renesas,irqc";
432 #interrupt-cells = <2> 432 #interrupt-cells = <2>;
433 interrupt-controller; 433 interrupt-controller;
434 reg = <0 0xe61c0000 0 434 reg = <0 0xe61c0000 0 0x200>;
435 interrupts = <GIC_SPI 435 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
436 <GIC_SPI 436 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
437 <GIC_SPI 437 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
438 <GIC_SPI 438 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
439 <GIC_SPI 439 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
440 <GIC_SPI 440 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
441 clocks = <&cpg CPG_MOD 441 clocks = <&cpg CPG_MOD 407>;
442 power-domains = <&sysc 442 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
443 resets = <&cpg 407>; 443 resets = <&cpg 407>;
444 }; 444 };
445 445
446 tmu0: timer@e61e0000 { 446 tmu0: timer@e61e0000 {
447 compatible = "renesas, 447 compatible = "renesas,tmu-r8a77965", "renesas,tmu";
448 reg = <0 0xe61e0000 0 448 reg = <0 0xe61e0000 0 0x30>;
449 interrupts = <GIC_SPI 449 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
450 <GIC_SPI 450 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
451 <GIC_SPI 451 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
452 interrupt-names = "tun 452 interrupt-names = "tuni0", "tuni1", "tuni2";
453 clocks = <&cpg CPG_MOD 453 clocks = <&cpg CPG_MOD 125>;
454 clock-names = "fck"; 454 clock-names = "fck";
455 power-domains = <&sysc 455 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
456 resets = <&cpg 125>; 456 resets = <&cpg 125>;
457 status = "disabled"; 457 status = "disabled";
458 }; 458 };
459 459
460 tmu1: timer@e6fc0000 { 460 tmu1: timer@e6fc0000 {
461 compatible = "renesas, 461 compatible = "renesas,tmu-r8a77965", "renesas,tmu";
462 reg = <0 0xe6fc0000 0 462 reg = <0 0xe6fc0000 0 0x30>;
463 interrupts = <GIC_SPI 463 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
464 <GIC_SPI 464 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
465 <GIC_SPI 465 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
466 <GIC_SPI 466 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
467 interrupt-names = "tun 467 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
468 clocks = <&cpg CPG_MOD 468 clocks = <&cpg CPG_MOD 124>;
469 clock-names = "fck"; 469 clock-names = "fck";
470 power-domains = <&sysc 470 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
471 resets = <&cpg 124>; 471 resets = <&cpg 124>;
472 status = "disabled"; 472 status = "disabled";
473 }; 473 };
474 474
475 tmu2: timer@e6fd0000 { 475 tmu2: timer@e6fd0000 {
476 compatible = "renesas, 476 compatible = "renesas,tmu-r8a77965", "renesas,tmu";
477 reg = <0 0xe6fd0000 0 477 reg = <0 0xe6fd0000 0 0x30>;
478 interrupts = <GIC_SPI 478 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
479 <GIC_SPI 479 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
480 <GIC_SPI 480 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
481 <GIC_SPI 481 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
482 interrupt-names = "tun 482 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
483 clocks = <&cpg CPG_MOD 483 clocks = <&cpg CPG_MOD 123>;
484 clock-names = "fck"; 484 clock-names = "fck";
485 power-domains = <&sysc 485 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
486 resets = <&cpg 123>; 486 resets = <&cpg 123>;
487 status = "disabled"; 487 status = "disabled";
488 }; 488 };
489 489
490 tmu3: timer@e6fe0000 { 490 tmu3: timer@e6fe0000 {
491 compatible = "renesas, 491 compatible = "renesas,tmu-r8a77965", "renesas,tmu";
492 reg = <0 0xe6fe0000 0 492 reg = <0 0xe6fe0000 0 0x30>;
493 interrupts = <GIC_SPI 493 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
494 <GIC_SPI 494 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
495 <GIC_SPI 495 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
496 interrupt-names = "tun 496 interrupt-names = "tuni0", "tuni1", "tuni2";
497 clocks = <&cpg CPG_MOD 497 clocks = <&cpg CPG_MOD 122>;
498 clock-names = "fck"; 498 clock-names = "fck";
499 power-domains = <&sysc 499 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
500 resets = <&cpg 122>; 500 resets = <&cpg 122>;
501 status = "disabled"; 501 status = "disabled";
502 }; 502 };
503 503
504 tmu4: timer@ffc00000 { 504 tmu4: timer@ffc00000 {
505 compatible = "renesas, 505 compatible = "renesas,tmu-r8a77965", "renesas,tmu";
506 reg = <0 0xffc00000 0 506 reg = <0 0xffc00000 0 0x30>;
507 interrupts = <GIC_SPI 507 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
508 <GIC_SPI 508 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
509 <GIC_SPI 509 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
510 interrupt-names = "tun 510 interrupt-names = "tuni0", "tuni1", "tuni2";
511 clocks = <&cpg CPG_MOD 511 clocks = <&cpg CPG_MOD 121>;
512 clock-names = "fck"; 512 clock-names = "fck";
513 power-domains = <&sysc 513 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
514 resets = <&cpg 121>; 514 resets = <&cpg 121>;
515 status = "disabled"; 515 status = "disabled";
516 }; 516 };
517 517
518 i2c0: i2c@e6500000 { 518 i2c0: i2c@e6500000 {
519 #address-cells = <1>; 519 #address-cells = <1>;
520 #size-cells = <0>; 520 #size-cells = <0>;
521 compatible = "renesas, 521 compatible = "renesas,i2c-r8a77965",
522 "renesas, 522 "renesas,rcar-gen3-i2c";
523 reg = <0 0xe6500000 0 523 reg = <0 0xe6500000 0 0x40>;
524 interrupts = <GIC_SPI 524 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
525 clocks = <&cpg CPG_MOD 525 clocks = <&cpg CPG_MOD 931>;
526 power-domains = <&sysc 526 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
527 resets = <&cpg 931>; 527 resets = <&cpg 931>;
528 dmas = <&dmac1 0x91>, 528 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
529 <&dmac2 0x91>, 529 <&dmac2 0x91>, <&dmac2 0x90>;
530 dma-names = "tx", "rx" 530 dma-names = "tx", "rx", "tx", "rx";
531 i2c-scl-internal-delay 531 i2c-scl-internal-delay-ns = <110>;
532 status = "disabled"; 532 status = "disabled";
533 }; 533 };
534 534
535 i2c1: i2c@e6508000 { 535 i2c1: i2c@e6508000 {
536 #address-cells = <1>; 536 #address-cells = <1>;
537 #size-cells = <0>; 537 #size-cells = <0>;
538 compatible = "renesas, 538 compatible = "renesas,i2c-r8a77965",
539 "renesas, 539 "renesas,rcar-gen3-i2c";
540 reg = <0 0xe6508000 0 540 reg = <0 0xe6508000 0 0x40>;
541 interrupts = <GIC_SPI 541 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
542 clocks = <&cpg CPG_MOD 542 clocks = <&cpg CPG_MOD 930>;
543 power-domains = <&sysc 543 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
544 resets = <&cpg 930>; 544 resets = <&cpg 930>;
545 dmas = <&dmac1 0x93>, 545 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
546 <&dmac2 0x93>, 546 <&dmac2 0x93>, <&dmac2 0x92>;
547 dma-names = "tx", "rx" 547 dma-names = "tx", "rx", "tx", "rx";
548 i2c-scl-internal-delay 548 i2c-scl-internal-delay-ns = <6>;
549 status = "disabled"; 549 status = "disabled";
550 }; 550 };
551 551
552 i2c2: i2c@e6510000 { 552 i2c2: i2c@e6510000 {
553 #address-cells = <1>; 553 #address-cells = <1>;
554 #size-cells = <0>; 554 #size-cells = <0>;
555 compatible = "renesas, 555 compatible = "renesas,i2c-r8a77965",
556 "renesas, 556 "renesas,rcar-gen3-i2c";
557 reg = <0 0xe6510000 0 557 reg = <0 0xe6510000 0 0x40>;
558 interrupts = <GIC_SPI 558 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
559 clocks = <&cpg CPG_MOD 559 clocks = <&cpg CPG_MOD 929>;
560 power-domains = <&sysc 560 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
561 resets = <&cpg 929>; 561 resets = <&cpg 929>;
562 dmas = <&dmac1 0x95>, 562 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
563 <&dmac2 0x95>, 563 <&dmac2 0x95>, <&dmac2 0x94>;
564 dma-names = "tx", "rx" 564 dma-names = "tx", "rx", "tx", "rx";
565 i2c-scl-internal-delay 565 i2c-scl-internal-delay-ns = <6>;
566 status = "disabled"; 566 status = "disabled";
567 }; 567 };
568 568
569 i2c3: i2c@e66d0000 { 569 i2c3: i2c@e66d0000 {
570 #address-cells = <1>; 570 #address-cells = <1>;
571 #size-cells = <0>; 571 #size-cells = <0>;
572 compatible = "renesas, 572 compatible = "renesas,i2c-r8a77965",
573 "renesas, 573 "renesas,rcar-gen3-i2c";
574 reg = <0 0xe66d0000 0 574 reg = <0 0xe66d0000 0 0x40>;
575 interrupts = <GIC_SPI 575 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
576 clocks = <&cpg CPG_MOD 576 clocks = <&cpg CPG_MOD 928>;
577 power-domains = <&sysc 577 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
578 resets = <&cpg 928>; 578 resets = <&cpg 928>;
579 dmas = <&dmac0 0x97>, 579 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
580 dma-names = "tx", "rx" 580 dma-names = "tx", "rx";
581 i2c-scl-internal-delay 581 i2c-scl-internal-delay-ns = <110>;
582 status = "disabled"; 582 status = "disabled";
583 }; 583 };
584 584
585 i2c4: i2c@e66d8000 { 585 i2c4: i2c@e66d8000 {
586 #address-cells = <1>; 586 #address-cells = <1>;
587 #size-cells = <0>; 587 #size-cells = <0>;
588 compatible = "renesas, 588 compatible = "renesas,i2c-r8a77965",
589 "renesas, 589 "renesas,rcar-gen3-i2c";
590 reg = <0 0xe66d8000 0 590 reg = <0 0xe66d8000 0 0x40>;
591 interrupts = <GIC_SPI 591 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
592 clocks = <&cpg CPG_MOD 592 clocks = <&cpg CPG_MOD 927>;
593 power-domains = <&sysc 593 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
594 resets = <&cpg 927>; 594 resets = <&cpg 927>;
595 dmas = <&dmac0 0x99>, 595 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
596 dma-names = "tx", "rx" 596 dma-names = "tx", "rx";
597 i2c-scl-internal-delay 597 i2c-scl-internal-delay-ns = <110>;
598 status = "disabled"; 598 status = "disabled";
599 }; 599 };
600 600
601 i2c5: i2c@e66e0000 { 601 i2c5: i2c@e66e0000 {
602 #address-cells = <1>; 602 #address-cells = <1>;
603 #size-cells = <0>; 603 #size-cells = <0>;
604 compatible = "renesas, 604 compatible = "renesas,i2c-r8a77965",
605 "renesas, 605 "renesas,rcar-gen3-i2c";
606 reg = <0 0xe66e0000 0 606 reg = <0 0xe66e0000 0 0x40>;
607 interrupts = <GIC_SPI 607 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
608 clocks = <&cpg CPG_MOD 608 clocks = <&cpg CPG_MOD 919>;
609 power-domains = <&sysc 609 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
610 resets = <&cpg 919>; 610 resets = <&cpg 919>;
611 dmas = <&dmac0 0x9b>, 611 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
612 dma-names = "tx", "rx" 612 dma-names = "tx", "rx";
613 i2c-scl-internal-delay 613 i2c-scl-internal-delay-ns = <110>;
614 status = "disabled"; 614 status = "disabled";
615 }; 615 };
616 616
617 i2c6: i2c@e66e8000 { 617 i2c6: i2c@e66e8000 {
618 #address-cells = <1>; 618 #address-cells = <1>;
619 #size-cells = <0>; 619 #size-cells = <0>;
620 compatible = "renesas, 620 compatible = "renesas,i2c-r8a77965",
621 "renesas, 621 "renesas,rcar-gen3-i2c";
622 reg = <0 0xe66e8000 0 622 reg = <0 0xe66e8000 0 0x40>;
623 interrupts = <GIC_SPI 623 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
624 clocks = <&cpg CPG_MOD 624 clocks = <&cpg CPG_MOD 918>;
625 power-domains = <&sysc 625 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
626 resets = <&cpg 918>; 626 resets = <&cpg 918>;
627 dmas = <&dmac0 0x9d>, 627 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
628 dma-names = "tx", "rx" 628 dma-names = "tx", "rx";
629 i2c-scl-internal-delay 629 i2c-scl-internal-delay-ns = <6>;
630 status = "disabled"; 630 status = "disabled";
631 }; 631 };
632 632
633 i2c_dvfs: i2c@e60b0000 { 633 i2c_dvfs: i2c@e60b0000 {
634 #address-cells = <1>; 634 #address-cells = <1>;
635 #size-cells = <0>; 635 #size-cells = <0>;
636 compatible = "renesas, 636 compatible = "renesas,iic-r8a77965",
637 "renesas, 637 "renesas,rcar-gen3-iic",
638 "renesas, 638 "renesas,rmobile-iic";
639 reg = <0 0xe60b0000 0 639 reg = <0 0xe60b0000 0 0x425>;
640 interrupts = <GIC_SPI 640 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
641 clocks = <&cpg CPG_MOD 641 clocks = <&cpg CPG_MOD 926>;
642 power-domains = <&sysc 642 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
643 resets = <&cpg 926>; 643 resets = <&cpg 926>;
644 dmas = <&dmac0 0x11>, 644 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
645 dma-names = "tx", "rx" 645 dma-names = "tx", "rx";
646 status = "disabled"; 646 status = "disabled";
647 }; 647 };
648 648
649 hscif0: serial@e6540000 { 649 hscif0: serial@e6540000 {
650 compatible = "renesas, 650 compatible = "renesas,hscif-r8a77965",
651 "renesas, 651 "renesas,rcar-gen3-hscif",
652 "renesas, 652 "renesas,hscif";
653 reg = <0 0xe6540000 0 653 reg = <0 0xe6540000 0 0x60>;
654 interrupts = <GIC_SPI 654 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
655 clocks = <&cpg CPG_MOD 655 clocks = <&cpg CPG_MOD 520>,
656 <&cpg CPG_COR 656 <&cpg CPG_CORE R8A77965_CLK_S3D1>,
657 <&scif_clk>; 657 <&scif_clk>;
658 clock-names = "fck", " 658 clock-names = "fck", "brg_int", "scif_clk";
659 dmas = <&dmac1 0x31>, 659 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
660 <&dmac2 0x31>, 660 <&dmac2 0x31>, <&dmac2 0x30>;
661 dma-names = "tx", "rx" 661 dma-names = "tx", "rx", "tx", "rx";
662 power-domains = <&sysc 662 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
663 resets = <&cpg 520>; 663 resets = <&cpg 520>;
664 status = "disabled"; 664 status = "disabled";
665 }; 665 };
666 666
667 hscif1: serial@e6550000 { 667 hscif1: serial@e6550000 {
668 compatible = "renesas, 668 compatible = "renesas,hscif-r8a77965",
669 "renesas, 669 "renesas,rcar-gen3-hscif",
670 "renesas, 670 "renesas,hscif";
671 reg = <0 0xe6550000 0 671 reg = <0 0xe6550000 0 0x60>;
672 interrupts = <GIC_SPI 672 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
673 clocks = <&cpg CPG_MOD 673 clocks = <&cpg CPG_MOD 519>,
674 <&cpg CPG_COR 674 <&cpg CPG_CORE R8A77965_CLK_S3D1>,
675 <&scif_clk>; 675 <&scif_clk>;
676 clock-names = "fck", " 676 clock-names = "fck", "brg_int", "scif_clk";
677 dmas = <&dmac1 0x33>, 677 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
678 <&dmac2 0x33>, 678 <&dmac2 0x33>, <&dmac2 0x32>;
679 dma-names = "tx", "rx" 679 dma-names = "tx", "rx", "tx", "rx";
680 power-domains = <&sysc 680 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
681 resets = <&cpg 519>; 681 resets = <&cpg 519>;
682 status = "disabled"; 682 status = "disabled";
683 }; 683 };
684 684
685 hscif2: serial@e6560000 { 685 hscif2: serial@e6560000 {
686 compatible = "renesas, 686 compatible = "renesas,hscif-r8a77965",
687 "renesas, 687 "renesas,rcar-gen3-hscif",
688 "renesas, 688 "renesas,hscif";
689 reg = <0 0xe6560000 0 689 reg = <0 0xe6560000 0 0x60>;
690 interrupts = <GIC_SPI 690 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
691 clocks = <&cpg CPG_MOD 691 clocks = <&cpg CPG_MOD 518>,
692 <&cpg CPG_COR 692 <&cpg CPG_CORE R8A77965_CLK_S3D1>,
693 <&scif_clk>; 693 <&scif_clk>;
694 clock-names = "fck", " 694 clock-names = "fck", "brg_int", "scif_clk";
695 dmas = <&dmac1 0x35>, 695 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
696 <&dmac2 0x35>, 696 <&dmac2 0x35>, <&dmac2 0x34>;
697 dma-names = "tx", "rx" 697 dma-names = "tx", "rx", "tx", "rx";
698 power-domains = <&sysc 698 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
699 resets = <&cpg 518>; 699 resets = <&cpg 518>;
700 status = "disabled"; 700 status = "disabled";
701 }; 701 };
702 702
703 hscif3: serial@e66a0000 { 703 hscif3: serial@e66a0000 {
704 compatible = "renesas, 704 compatible = "renesas,hscif-r8a77965",
705 "renesas, 705 "renesas,rcar-gen3-hscif",
706 "renesas, 706 "renesas,hscif";
707 reg = <0 0xe66a0000 0 707 reg = <0 0xe66a0000 0 0x60>;
708 interrupts = <GIC_SPI 708 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
709 clocks = <&cpg CPG_MOD 709 clocks = <&cpg CPG_MOD 517>,
710 <&cpg CPG_COR 710 <&cpg CPG_CORE R8A77965_CLK_S3D1>,
711 <&scif_clk>; 711 <&scif_clk>;
712 clock-names = "fck", " 712 clock-names = "fck", "brg_int", "scif_clk";
713 dmas = <&dmac0 0x37>, 713 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
714 dma-names = "tx", "rx" 714 dma-names = "tx", "rx";
715 power-domains = <&sysc 715 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
716 resets = <&cpg 517>; 716 resets = <&cpg 517>;
717 status = "disabled"; 717 status = "disabled";
718 }; 718 };
719 719
720 hscif4: serial@e66b0000 { 720 hscif4: serial@e66b0000 {
721 compatible = "renesas, 721 compatible = "renesas,hscif-r8a77965",
722 "renesas, 722 "renesas,rcar-gen3-hscif",
723 "renesas, 723 "renesas,hscif";
724 reg = <0 0xe66b0000 0 724 reg = <0 0xe66b0000 0 0x60>;
725 interrupts = <GIC_SPI 725 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
726 clocks = <&cpg CPG_MOD 726 clocks = <&cpg CPG_MOD 516>,
727 <&cpg CPG_COR 727 <&cpg CPG_CORE R8A77965_CLK_S3D1>,
728 <&scif_clk>; 728 <&scif_clk>;
729 clock-names = "fck", " 729 clock-names = "fck", "brg_int", "scif_clk";
730 dmas = <&dmac0 0x39>, 730 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
731 dma-names = "tx", "rx" 731 dma-names = "tx", "rx";
732 power-domains = <&sysc 732 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
733 resets = <&cpg 516>; 733 resets = <&cpg 516>;
734 status = "disabled"; 734 status = "disabled";
735 }; 735 };
736 736
737 hsusb: usb@e6590000 { 737 hsusb: usb@e6590000 {
738 compatible = "renesas, 738 compatible = "renesas,usbhs-r8a77965",
739 "renesas, 739 "renesas,rcar-gen3-usbhs";
740 reg = <0 0xe6590000 0 740 reg = <0 0xe6590000 0 0x200>;
741 interrupts = <GIC_SPI 741 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
742 clocks = <&cpg CPG_MOD 742 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
743 dmas = <&usb_dmac0 0>, 743 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
744 <&usb_dmac1 0>, 744 <&usb_dmac1 0>, <&usb_dmac1 1>;
745 dma-names = "ch0", "ch 745 dma-names = "ch0", "ch1", "ch2", "ch3";
746 renesas,buswait = <11> 746 renesas,buswait = <11>;
747 phys = <&usb2_phy0 3>; 747 phys = <&usb2_phy0 3>;
748 phy-names = "usb"; 748 phy-names = "usb";
749 power-domains = <&sysc 749 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
750 resets = <&cpg 704>, < 750 resets = <&cpg 704>, <&cpg 703>;
751 status = "disabled"; 751 status = "disabled";
752 }; 752 };
753 753
754 usb_dmac0: dma-controller@e65a 754 usb_dmac0: dma-controller@e65a0000 {
755 compatible = "renesas, 755 compatible = "renesas,r8a77965-usb-dmac",
756 "renesas, 756 "renesas,usb-dmac";
757 reg = <0 0xe65a0000 0 757 reg = <0 0xe65a0000 0 0x100>;
758 interrupts = <GIC_SPI 758 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
759 <GIC_SPI 759 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
760 interrupt-names = "ch0 760 interrupt-names = "ch0", "ch1";
761 clocks = <&cpg CPG_MOD 761 clocks = <&cpg CPG_MOD 330>;
762 power-domains = <&sysc 762 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
763 resets = <&cpg 330>; 763 resets = <&cpg 330>;
764 #dma-cells = <1>; 764 #dma-cells = <1>;
765 dma-channels = <2>; 765 dma-channels = <2>;
766 }; 766 };
767 767
768 usb_dmac1: dma-controller@e65b 768 usb_dmac1: dma-controller@e65b0000 {
769 compatible = "renesas, 769 compatible = "renesas,r8a77965-usb-dmac",
770 "renesas, 770 "renesas,usb-dmac";
771 reg = <0 0xe65b0000 0 771 reg = <0 0xe65b0000 0 0x100>;
772 interrupts = <GIC_SPI 772 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
773 <GIC_SPI 773 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
774 interrupt-names = "ch0 774 interrupt-names = "ch0", "ch1";
775 clocks = <&cpg CPG_MOD 775 clocks = <&cpg CPG_MOD 331>;
776 power-domains = <&sysc 776 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
777 resets = <&cpg 331>; 777 resets = <&cpg 331>;
778 #dma-cells = <1>; 778 #dma-cells = <1>;
779 dma-channels = <2>; 779 dma-channels = <2>;
780 }; 780 };
781 781
782 usb3_phy0: usb-phy@e65ee000 { 782 usb3_phy0: usb-phy@e65ee000 {
783 compatible = "renesas, 783 compatible = "renesas,r8a77965-usb3-phy",
784 "renesas, 784 "renesas,rcar-gen3-usb3-phy";
785 reg = <0 0xe65ee000 0 785 reg = <0 0xe65ee000 0 0x90>;
786 clocks = <&cpg CPG_MOD 786 clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>,
787 <&usb_extal_c 787 <&usb_extal_clk>;
788 clock-names = "usb3-if 788 clock-names = "usb3-if", "usb3s_clk", "usb_extal";
789 power-domains = <&sysc 789 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
790 resets = <&cpg 328>; 790 resets = <&cpg 328>;
791 #phy-cells = <0>; 791 #phy-cells = <0>;
792 status = "disabled"; 792 status = "disabled";
793 }; 793 };
794 794
795 arm_cc630p: crypto@e6601000 { 795 arm_cc630p: crypto@e6601000 {
796 compatible = "arm,cryp 796 compatible = "arm,cryptocell-630p-ree";
797 interrupts = <GIC_SPI 797 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
798 reg = <0x0 0xe6601000 798 reg = <0x0 0xe6601000 0 0x1000>;
799 clocks = <&cpg CPG_MOD 799 clocks = <&cpg CPG_MOD 229>;
800 resets = <&cpg 229>; 800 resets = <&cpg 229>;
801 power-domains = <&sysc 801 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
802 }; 802 };
803 803
804 dmac0: dma-controller@e6700000 804 dmac0: dma-controller@e6700000 {
805 compatible = "renesas, 805 compatible = "renesas,dmac-r8a77965",
806 "renesas, 806 "renesas,rcar-dmac";
807 reg = <0 0xe6700000 0 807 reg = <0 0xe6700000 0 0x10000>;
808 interrupts = <GIC_SPI 808 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
809 <GIC_SPI 809 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
810 <GIC_SPI 810 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
811 <GIC_SPI 811 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
812 <GIC_SPI 812 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
813 <GIC_SPI 813 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
814 <GIC_SPI 814 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
815 <GIC_SPI 815 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
816 <GIC_SPI 816 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
817 <GIC_SPI 817 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
818 <GIC_SPI 818 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
819 <GIC_SPI 819 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
820 <GIC_SPI 820 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
821 <GIC_SPI 821 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
822 <GIC_SPI 822 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
823 <GIC_SPI 823 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
824 <GIC_SPI 824 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
825 interrupt-names = "err 825 interrupt-names = "error",
826 "ch0", 826 "ch0", "ch1", "ch2", "ch3",
827 "ch4", 827 "ch4", "ch5", "ch6", "ch7",
828 "ch8", 828 "ch8", "ch9", "ch10", "ch11",
829 "ch12" 829 "ch12", "ch13", "ch14", "ch15";
830 clocks = <&cpg CPG_MOD 830 clocks = <&cpg CPG_MOD 219>;
831 clock-names = "fck"; 831 clock-names = "fck";
832 power-domains = <&sysc 832 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
833 resets = <&cpg 219>; 833 resets = <&cpg 219>;
834 #dma-cells = <1>; 834 #dma-cells = <1>;
835 dma-channels = <16>; 835 dma-channels = <16>;
836 iommus = <&ipmmu_ds0 0 836 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
837 <&ipmmu_ds0 2>, 837 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
838 <&ipmmu_ds0 4>, 838 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
839 <&ipmmu_ds0 6>, 839 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
840 <&ipmmu_ds0 8>, 840 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
841 <&ipmmu_ds0 10> 841 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
842 <&ipmmu_ds0 12> 842 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
843 <&ipmmu_ds0 14> 843 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
844 }; 844 };
845 845
846 dmac1: dma-controller@e7300000 846 dmac1: dma-controller@e7300000 {
847 compatible = "renesas, 847 compatible = "renesas,dmac-r8a77965",
848 "renesas, 848 "renesas,rcar-dmac";
849 reg = <0 0xe7300000 0 849 reg = <0 0xe7300000 0 0x10000>;
850 interrupts = <GIC_SPI 850 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
851 <GIC_SPI 851 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
852 <GIC_SPI 852 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
853 <GIC_SPI 853 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
854 <GIC_SPI 854 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
855 <GIC_SPI 855 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
856 <GIC_SPI 856 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
857 <GIC_SPI 857 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
858 <GIC_SPI 858 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
859 <GIC_SPI 859 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
860 <GIC_SPI 860 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
861 <GIC_SPI 861 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
862 <GIC_SPI 862 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
863 <GIC_SPI 863 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
864 <GIC_SPI 864 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
865 <GIC_SPI 865 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
866 <GIC_SPI 866 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
867 interrupt-names = "err 867 interrupt-names = "error",
868 "ch0", 868 "ch0", "ch1", "ch2", "ch3",
869 "ch4", 869 "ch4", "ch5", "ch6", "ch7",
870 "ch8", 870 "ch8", "ch9", "ch10", "ch11",
871 "ch12" 871 "ch12", "ch13", "ch14", "ch15";
872 clocks = <&cpg CPG_MOD 872 clocks = <&cpg CPG_MOD 218>;
873 clock-names = "fck"; 873 clock-names = "fck";
874 power-domains = <&sysc 874 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
875 resets = <&cpg 218>; 875 resets = <&cpg 218>;
876 #dma-cells = <1>; 876 #dma-cells = <1>;
877 dma-channels = <16>; 877 dma-channels = <16>;
878 iommus = <&ipmmu_ds1 0 878 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
879 <&ipmmu_ds1 2>, 879 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
880 <&ipmmu_ds1 4>, 880 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
881 <&ipmmu_ds1 6>, 881 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
882 <&ipmmu_ds1 8>, 882 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
883 <&ipmmu_ds1 10> 883 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
884 <&ipmmu_ds1 12> 884 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
885 <&ipmmu_ds1 14> 885 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
886 }; 886 };
887 887
888 dmac2: dma-controller@e7310000 888 dmac2: dma-controller@e7310000 {
889 compatible = "renesas, 889 compatible = "renesas,dmac-r8a77965",
890 "renesas, 890 "renesas,rcar-dmac";
891 reg = <0 0xe7310000 0 891 reg = <0 0xe7310000 0 0x10000>;
892 interrupts = <GIC_SPI 892 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
893 <GIC_SPI 893 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
894 <GIC_SPI 894 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
895 <GIC_SPI 895 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
896 <GIC_SPI 896 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
897 <GIC_SPI 897 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
898 <GIC_SPI 898 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
899 <GIC_SPI 899 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
900 <GIC_SPI 900 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
901 <GIC_SPI 901 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
902 <GIC_SPI 902 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
903 <GIC_SPI 903 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
904 <GIC_SPI 904 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
905 <GIC_SPI 905 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
906 <GIC_SPI 906 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
907 <GIC_SPI 907 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
908 <GIC_SPI 908 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
909 interrupt-names = "err 909 interrupt-names = "error",
910 "ch0", 910 "ch0", "ch1", "ch2", "ch3",
911 "ch4", 911 "ch4", "ch5", "ch6", "ch7",
912 "ch8", 912 "ch8", "ch9", "ch10", "ch11",
913 "ch12" 913 "ch12", "ch13", "ch14", "ch15";
914 clocks = <&cpg CPG_MOD 914 clocks = <&cpg CPG_MOD 217>;
915 clock-names = "fck"; 915 clock-names = "fck";
916 power-domains = <&sysc 916 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
917 resets = <&cpg 217>; 917 resets = <&cpg 217>;
918 #dma-cells = <1>; 918 #dma-cells = <1>;
919 dma-channels = <16>; 919 dma-channels = <16>;
920 iommus = <&ipmmu_ds1 1 920 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
921 <&ipmmu_ds1 18> 921 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
922 <&ipmmu_ds1 20> 922 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
923 <&ipmmu_ds1 22> 923 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
924 <&ipmmu_ds1 24> 924 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
925 <&ipmmu_ds1 26> 925 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
926 <&ipmmu_ds1 28> 926 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
927 <&ipmmu_ds1 30> 927 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
928 }; 928 };
929 929
930 ipmmu_ds0: iommu@e6740000 { 930 ipmmu_ds0: iommu@e6740000 {
931 compatible = "renesas, 931 compatible = "renesas,ipmmu-r8a77965";
932 reg = <0 0xe6740000 0 932 reg = <0 0xe6740000 0 0x1000>;
933 renesas,ipmmu-main = < 933 renesas,ipmmu-main = <&ipmmu_mm 0>;
934 power-domains = <&sysc 934 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
935 #iommu-cells = <1>; 935 #iommu-cells = <1>;
936 }; 936 };
937 937
938 ipmmu_ds1: iommu@e7740000 { 938 ipmmu_ds1: iommu@e7740000 {
939 compatible = "renesas, 939 compatible = "renesas,ipmmu-r8a77965";
940 reg = <0 0xe7740000 0 940 reg = <0 0xe7740000 0 0x1000>;
941 renesas,ipmmu-main = < 941 renesas,ipmmu-main = <&ipmmu_mm 1>;
942 power-domains = <&sysc 942 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
943 #iommu-cells = <1>; 943 #iommu-cells = <1>;
944 }; 944 };
945 945
946 ipmmu_hc: iommu@e6570000 { 946 ipmmu_hc: iommu@e6570000 {
947 compatible = "renesas, 947 compatible = "renesas,ipmmu-r8a77965";
948 reg = <0 0xe6570000 0 948 reg = <0 0xe6570000 0 0x1000>;
949 renesas,ipmmu-main = < 949 renesas,ipmmu-main = <&ipmmu_mm 2>;
950 power-domains = <&sysc 950 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
951 #iommu-cells = <1>; 951 #iommu-cells = <1>;
952 }; 952 };
953 953
954 ipmmu_mm: iommu@e67b0000 { 954 ipmmu_mm: iommu@e67b0000 {
955 compatible = "renesas, 955 compatible = "renesas,ipmmu-r8a77965";
956 reg = <0 0xe67b0000 0 956 reg = <0 0xe67b0000 0 0x1000>;
957 interrupts = <GIC_SPI 957 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
958 <GIC_SPI 958 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
959 power-domains = <&sysc 959 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
960 #iommu-cells = <1>; 960 #iommu-cells = <1>;
961 }; 961 };
962 962
963 ipmmu_mp: iommu@ec670000 { 963 ipmmu_mp: iommu@ec670000 {
964 compatible = "renesas, 964 compatible = "renesas,ipmmu-r8a77965";
965 reg = <0 0xec670000 0 965 reg = <0 0xec670000 0 0x1000>;
966 renesas,ipmmu-main = < 966 renesas,ipmmu-main = <&ipmmu_mm 4>;
967 power-domains = <&sysc 967 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
968 #iommu-cells = <1>; 968 #iommu-cells = <1>;
969 }; 969 };
970 970
971 ipmmu_pv0: iommu@fd800000 { 971 ipmmu_pv0: iommu@fd800000 {
972 compatible = "renesas, 972 compatible = "renesas,ipmmu-r8a77965";
973 reg = <0 0xfd800000 0 973 reg = <0 0xfd800000 0 0x1000>;
974 renesas,ipmmu-main = < 974 renesas,ipmmu-main = <&ipmmu_mm 6>;
975 power-domains = <&sysc 975 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
976 #iommu-cells = <1>; 976 #iommu-cells = <1>;
977 }; 977 };
978 978
979 ipmmu_rt: iommu@ffc80000 { 979 ipmmu_rt: iommu@ffc80000 {
980 compatible = "renesas, 980 compatible = "renesas,ipmmu-r8a77965";
981 reg = <0 0xffc80000 0 981 reg = <0 0xffc80000 0 0x1000>;
982 renesas,ipmmu-main = < 982 renesas,ipmmu-main = <&ipmmu_mm 10>;
983 power-domains = <&sysc 983 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
984 #iommu-cells = <1>; 984 #iommu-cells = <1>;
985 }; 985 };
986 986
987 ipmmu_vc0: iommu@fe6b0000 { 987 ipmmu_vc0: iommu@fe6b0000 {
988 compatible = "renesas, 988 compatible = "renesas,ipmmu-r8a77965";
989 reg = <0 0xfe6b0000 0 989 reg = <0 0xfe6b0000 0 0x1000>;
990 renesas,ipmmu-main = < 990 renesas,ipmmu-main = <&ipmmu_mm 12>;
991 power-domains = <&sysc 991 power-domains = <&sysc R8A77965_PD_A3VC>;
992 #iommu-cells = <1>; 992 #iommu-cells = <1>;
993 }; 993 };
994 994
995 ipmmu_vi0: iommu@febd0000 { 995 ipmmu_vi0: iommu@febd0000 {
996 compatible = "renesas, 996 compatible = "renesas,ipmmu-r8a77965";
997 reg = <0 0xfebd0000 0 997 reg = <0 0xfebd0000 0 0x1000>;
998 renesas,ipmmu-main = < 998 renesas,ipmmu-main = <&ipmmu_mm 14>;
999 power-domains = <&sysc 999 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
1000 #iommu-cells = <1>; 1000 #iommu-cells = <1>;
1001 }; 1001 };
1002 1002
1003 ipmmu_vp0: iommu@fe990000 { 1003 ipmmu_vp0: iommu@fe990000 {
1004 compatible = "renesas 1004 compatible = "renesas,ipmmu-r8a77965";
1005 reg = <0 0xfe990000 0 1005 reg = <0 0xfe990000 0 0x1000>;
1006 renesas,ipmmu-main = 1006 renesas,ipmmu-main = <&ipmmu_mm 16>;
1007 power-domains = <&sys 1007 power-domains = <&sysc R8A77965_PD_A3VP>;
1008 #iommu-cells = <1>; 1008 #iommu-cells = <1>;
1009 }; 1009 };
1010 1010
1011 avb: ethernet@e6800000 { 1011 avb: ethernet@e6800000 {
1012 compatible = "renesas 1012 compatible = "renesas,etheravb-r8a77965",
1013 "renesas 1013 "renesas,etheravb-rcar-gen3";
1014 reg = <0 0xe6800000 0 1014 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
1015 interrupts = <GIC_SPI 1015 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
1016 <GIC_SPI 1016 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1017 <GIC_SPI 1017 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
1018 <GIC_SPI 1018 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
1019 <GIC_SPI 1019 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
1020 <GIC_SPI 1020 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
1021 <GIC_SPI 1021 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
1022 <GIC_SPI 1022 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
1023 <GIC_SPI 1023 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
1024 <GIC_SPI 1024 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
1025 <GIC_SPI 1025 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
1026 <GIC_SPI 1026 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
1027 <GIC_SPI 1027 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
1028 <GIC_SPI 1028 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
1029 <GIC_SPI 1029 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
1030 <GIC_SPI 1030 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
1031 <GIC_SPI 1031 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
1032 <GIC_SPI 1032 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
1033 <GIC_SPI 1033 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
1034 <GIC_SPI 1034 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
1035 <GIC_SPI 1035 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
1036 <GIC_SPI 1036 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
1037 <GIC_SPI 1037 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
1038 <GIC_SPI 1038 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
1039 <GIC_SPI 1039 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
1040 interrupt-names = "ch 1040 interrupt-names = "ch0", "ch1", "ch2", "ch3",
1041 "ch 1041 "ch4", "ch5", "ch6", "ch7",
1042 "ch 1042 "ch8", "ch9", "ch10", "ch11",
1043 "ch 1043 "ch12", "ch13", "ch14", "ch15",
1044 "ch 1044 "ch16", "ch17", "ch18", "ch19",
1045 "ch 1045 "ch20", "ch21", "ch22", "ch23",
1046 "ch 1046 "ch24";
1047 clocks = <&cpg CPG_MO 1047 clocks = <&cpg CPG_MOD 812>;
1048 clock-names = "fck"; 1048 clock-names = "fck";
1049 power-domains = <&sys 1049 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
1050 resets = <&cpg 812>; 1050 resets = <&cpg 812>;
1051 phy-mode = "rgmii"; 1051 phy-mode = "rgmii";
1052 rx-internal-delay-ps 1052 rx-internal-delay-ps = <0>;
1053 tx-internal-delay-ps 1053 tx-internal-delay-ps = <0>;
1054 iommus = <&ipmmu_ds0 1054 iommus = <&ipmmu_ds0 16>;
1055 #address-cells = <1>; 1055 #address-cells = <1>;
1056 #size-cells = <0>; 1056 #size-cells = <0>;
1057 status = "disabled"; 1057 status = "disabled";
1058 }; 1058 };
1059 1059
1060 can0: can@e6c30000 { 1060 can0: can@e6c30000 {
1061 compatible = "renesas 1061 compatible = "renesas,can-r8a77965",
1062 "renesas 1062 "renesas,rcar-gen3-can";
1063 reg = <0 0xe6c30000 0 1063 reg = <0 0xe6c30000 0 0x1000>;
1064 interrupts = <GIC_SPI 1064 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
1065 clocks = <&cpg CPG_MO 1065 clocks = <&cpg CPG_MOD 916>,
1066 <&cpg CPG_CORE 1066 <&cpg CPG_CORE R8A77965_CLK_CANFD>,
1067 <&can_clk>; 1067 <&can_clk>;
1068 clock-names = "clkp1" 1068 clock-names = "clkp1", "clkp2", "can_clk";
1069 assigned-clocks = <&c 1069 assigned-clocks = <&cpg CPG_CORE R8A77965_CLK_CANFD>;
1070 assigned-clock-rates 1070 assigned-clock-rates = <40000000>;
1071 power-domains = <&sys 1071 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
1072 resets = <&cpg 916>; 1072 resets = <&cpg 916>;
1073 status = "disabled"; 1073 status = "disabled";
1074 }; 1074 };
1075 1075
1076 can1: can@e6c38000 { 1076 can1: can@e6c38000 {
1077 compatible = "renesas 1077 compatible = "renesas,can-r8a77965",
1078 "renesas 1078 "renesas,rcar-gen3-can";
1079 reg = <0 0xe6c38000 0 1079 reg = <0 0xe6c38000 0 0x1000>;
1080 interrupts = <GIC_SPI 1080 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
1081 clocks = <&cpg CPG_MO 1081 clocks = <&cpg CPG_MOD 915>,
1082 <&cpg CPG_CORE 1082 <&cpg CPG_CORE R8A77965_CLK_CANFD>,
1083 <&can_clk>; 1083 <&can_clk>;
1084 clock-names = "clkp1" 1084 clock-names = "clkp1", "clkp2", "can_clk";
1085 assigned-clocks = <&c 1085 assigned-clocks = <&cpg CPG_CORE R8A77965_CLK_CANFD>;
1086 assigned-clock-rates 1086 assigned-clock-rates = <40000000>;
1087 power-domains = <&sys 1087 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
1088 resets = <&cpg 915>; 1088 resets = <&cpg 915>;
1089 status = "disabled"; 1089 status = "disabled";
1090 }; 1090 };
1091 1091
1092 canfd: can@e66c0000 { 1092 canfd: can@e66c0000 {
1093 compatible = "renesas 1093 compatible = "renesas,r8a77965-canfd",
1094 "renesas 1094 "renesas,rcar-gen3-canfd";
1095 reg = <0 0xe66c0000 0 1095 reg = <0 0xe66c0000 0 0x8000>;
1096 interrupts = <GIC_SPI 1096 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
1097 <GIC_SPI 3 1097 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1098 interrupt-names = "ch 1098 interrupt-names = "ch_int", "g_int";
1099 clocks = <&cpg CPG_MO 1099 clocks = <&cpg CPG_MOD 914>,
1100 <&cpg CPG_CORE 1100 <&cpg CPG_CORE R8A77965_CLK_CANFD>,
1101 <&can_clk>; 1101 <&can_clk>;
1102 clock-names = "fck", 1102 clock-names = "fck", "canfd", "can_clk";
1103 assigned-clocks = <&c 1103 assigned-clocks = <&cpg CPG_CORE R8A77965_CLK_CANFD>;
1104 assigned-clock-rates 1104 assigned-clock-rates = <40000000>;
1105 power-domains = <&sys 1105 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
1106 resets = <&cpg 914>; 1106 resets = <&cpg 914>;
1107 status = "disabled"; 1107 status = "disabled";
1108 1108
1109 channel0 { 1109 channel0 {
1110 status = "dis 1110 status = "disabled";
1111 }; 1111 };
1112 1112
1113 channel1 { 1113 channel1 {
1114 status = "dis 1114 status = "disabled";
1115 }; 1115 };
1116 }; 1116 };
1117 1117
1118 pwm0: pwm@e6e30000 { 1118 pwm0: pwm@e6e30000 {
1119 compatible = "renesas 1119 compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar";
1120 reg = <0 0xe6e30000 0 1120 reg = <0 0xe6e30000 0 8>;
1121 #pwm-cells = <2>; 1121 #pwm-cells = <2>;
1122 clocks = <&cpg CPG_MO 1122 clocks = <&cpg CPG_MOD 523>;
1123 resets = <&cpg 523>; 1123 resets = <&cpg 523>;
1124 power-domains = <&sys 1124 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
1125 status = "disabled"; 1125 status = "disabled";
1126 }; 1126 };
1127 1127
1128 pwm1: pwm@e6e31000 { 1128 pwm1: pwm@e6e31000 {
1129 compatible = "renesas 1129 compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar";
1130 reg = <0 0xe6e31000 0 1130 reg = <0 0xe6e31000 0 8>;
1131 #pwm-cells = <2>; 1131 #pwm-cells = <2>;
1132 clocks = <&cpg CPG_MO 1132 clocks = <&cpg CPG_MOD 523>;
1133 resets = <&cpg 523>; 1133 resets = <&cpg 523>;
1134 power-domains = <&sys 1134 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
1135 status = "disabled"; 1135 status = "disabled";
1136 }; 1136 };
1137 1137
1138 pwm2: pwm@e6e32000 { 1138 pwm2: pwm@e6e32000 {
1139 compatible = "renesas 1139 compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar";
1140 reg = <0 0xe6e32000 0 1140 reg = <0 0xe6e32000 0 8>;
1141 #pwm-cells = <2>; 1141 #pwm-cells = <2>;
1142 clocks = <&cpg CPG_MO 1142 clocks = <&cpg CPG_MOD 523>;
1143 resets = <&cpg 523>; 1143 resets = <&cpg 523>;
1144 power-domains = <&sys 1144 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
1145 status = "disabled"; 1145 status = "disabled";
1146 }; 1146 };
1147 1147
1148 pwm3: pwm@e6e33000 { 1148 pwm3: pwm@e6e33000 {
1149 compatible = "renesas 1149 compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar";
1150 reg = <0 0xe6e33000 0 1150 reg = <0 0xe6e33000 0 8>;
1151 #pwm-cells = <2>; 1151 #pwm-cells = <2>;
1152 clocks = <&cpg CPG_MO 1152 clocks = <&cpg CPG_MOD 523>;
1153 resets = <&cpg 523>; 1153 resets = <&cpg 523>;
1154 power-domains = <&sys 1154 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
1155 status = "disabled"; 1155 status = "disabled";
1156 }; 1156 };
1157 1157
1158 pwm4: pwm@e6e34000 { 1158 pwm4: pwm@e6e34000 {
1159 compatible = "renesas 1159 compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar";
1160 reg = <0 0xe6e34000 0 1160 reg = <0 0xe6e34000 0 8>;
1161 #pwm-cells = <2>; 1161 #pwm-cells = <2>;
1162 clocks = <&cpg CPG_MO 1162 clocks = <&cpg CPG_MOD 523>;
1163 resets = <&cpg 523>; 1163 resets = <&cpg 523>;
1164 power-domains = <&sys 1164 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
1165 status = "disabled"; 1165 status = "disabled";
1166 }; 1166 };
1167 1167
1168 pwm5: pwm@e6e35000 { 1168 pwm5: pwm@e6e35000 {
1169 compatible = "renesas 1169 compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar";
1170 reg = <0 0xe6e35000 0 1170 reg = <0 0xe6e35000 0 8>;
1171 #pwm-cells = <2>; 1171 #pwm-cells = <2>;
1172 clocks = <&cpg CPG_MO 1172 clocks = <&cpg CPG_MOD 523>;
1173 resets = <&cpg 523>; 1173 resets = <&cpg 523>;
1174 power-domains = <&sys 1174 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
1175 status = "disabled"; 1175 status = "disabled";
1176 }; 1176 };
1177 1177
1178 pwm6: pwm@e6e36000 { 1178 pwm6: pwm@e6e36000 {
1179 compatible = "renesas 1179 compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar";
1180 reg = <0 0xe6e36000 0 1180 reg = <0 0xe6e36000 0 8>;
1181 #pwm-cells = <2>; 1181 #pwm-cells = <2>;
1182 clocks = <&cpg CPG_MO 1182 clocks = <&cpg CPG_MOD 523>;
1183 resets = <&cpg 523>; 1183 resets = <&cpg 523>;
1184 power-domains = <&sys 1184 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
1185 status = "disabled"; 1185 status = "disabled";
1186 }; 1186 };
1187 1187
1188 scif0: serial@e6e60000 { 1188 scif0: serial@e6e60000 {
1189 compatible = "renesas 1189 compatible = "renesas,scif-r8a77965",
1190 "renesas 1190 "renesas,rcar-gen3-scif", "renesas,scif";
1191 reg = <0 0xe6e60000 0 1191 reg = <0 0xe6e60000 0 64>;
1192 interrupts = <GIC_SPI 1192 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
1193 clocks = <&cpg CPG_MO 1193 clocks = <&cpg CPG_MOD 207>,
1194 <&cpg CPG_CO 1194 <&cpg CPG_CORE R8A77965_CLK_S3D1>,
1195 <&scif_clk>; 1195 <&scif_clk>;
1196 clock-names = "fck", 1196 clock-names = "fck", "brg_int", "scif_clk";
1197 dmas = <&dmac1 0x51>, 1197 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1198 <&dmac2 0x51>, 1198 <&dmac2 0x51>, <&dmac2 0x50>;
1199 dma-names = "tx", "rx 1199 dma-names = "tx", "rx", "tx", "rx";
1200 power-domains = <&sys 1200 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
1201 resets = <&cpg 207>; 1201 resets = <&cpg 207>;
1202 status = "disabled"; 1202 status = "disabled";
1203 }; 1203 };
1204 1204
1205 scif1: serial@e6e68000 { 1205 scif1: serial@e6e68000 {
1206 compatible = "renesas 1206 compatible = "renesas,scif-r8a77965",
1207 "renesas 1207 "renesas,rcar-gen3-scif", "renesas,scif";
1208 reg = <0 0xe6e68000 0 1208 reg = <0 0xe6e68000 0 64>;
1209 interrupts = <GIC_SPI 1209 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
1210 clocks = <&cpg CPG_MO 1210 clocks = <&cpg CPG_MOD 206>,
1211 <&cpg CPG_CO 1211 <&cpg CPG_CORE R8A77965_CLK_S3D1>,
1212 <&scif_clk>; 1212 <&scif_clk>;
1213 clock-names = "fck", 1213 clock-names = "fck", "brg_int", "scif_clk";
1214 dmas = <&dmac1 0x53>, 1214 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1215 <&dmac2 0x53>, 1215 <&dmac2 0x53>, <&dmac2 0x52>;
1216 dma-names = "tx", "rx 1216 dma-names = "tx", "rx", "tx", "rx";
1217 power-domains = <&sys 1217 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
1218 resets = <&cpg 206>; 1218 resets = <&cpg 206>;
1219 status = "disabled"; 1219 status = "disabled";
1220 }; 1220 };
1221 1221
1222 scif2: serial@e6e88000 { 1222 scif2: serial@e6e88000 {
1223 compatible = "renesas 1223 compatible = "renesas,scif-r8a77965",
1224 "renesas 1224 "renesas,rcar-gen3-scif", "renesas,scif";
1225 reg = <0 0xe6e88000 0 1225 reg = <0 0xe6e88000 0 64>;
1226 interrupts = <GIC_SPI 1226 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
1227 clocks = <&cpg CPG_MO 1227 clocks = <&cpg CPG_MOD 310>,
1228 <&cpg CPG_CO 1228 <&cpg CPG_CORE R8A77965_CLK_S3D1>,
1229 <&scif_clk>; 1229 <&scif_clk>;
1230 clock-names = "fck", 1230 clock-names = "fck", "brg_int", "scif_clk";
1231 dmas = <&dmac1 0x13>, 1231 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1232 <&dmac2 0x13>, 1232 <&dmac2 0x13>, <&dmac2 0x12>;
1233 dma-names = "tx", "rx 1233 dma-names = "tx", "rx", "tx", "rx";
1234 power-domains = <&sys 1234 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
1235 resets = <&cpg 310>; 1235 resets = <&cpg 310>;
1236 status = "disabled"; 1236 status = "disabled";
1237 }; 1237 };
1238 1238
1239 scif3: serial@e6c50000 { 1239 scif3: serial@e6c50000 {
1240 compatible = "renesas 1240 compatible = "renesas,scif-r8a77965",
1241 "renesas 1241 "renesas,rcar-gen3-scif", "renesas,scif";
1242 reg = <0 0xe6c50000 0 1242 reg = <0 0xe6c50000 0 64>;
1243 interrupts = <GIC_SPI 1243 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1244 clocks = <&cpg CPG_MO 1244 clocks = <&cpg CPG_MOD 204>,
1245 <&cpg CPG_CO 1245 <&cpg CPG_CORE R8A77965_CLK_S3D1>,
1246 <&scif_clk>; 1246 <&scif_clk>;
1247 clock-names = "fck", 1247 clock-names = "fck", "brg_int", "scif_clk";
1248 dmas = <&dmac0 0x57>, 1248 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1249 dma-names = "tx", "rx 1249 dma-names = "tx", "rx";
1250 power-domains = <&sys 1250 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
1251 resets = <&cpg 204>; 1251 resets = <&cpg 204>;
1252 status = "disabled"; 1252 status = "disabled";
1253 }; 1253 };
1254 1254
1255 scif4: serial@e6c40000 { 1255 scif4: serial@e6c40000 {
1256 compatible = "renesas 1256 compatible = "renesas,scif-r8a77965",
1257 "renesas 1257 "renesas,rcar-gen3-scif", "renesas,scif";
1258 reg = <0 0xe6c40000 0 1258 reg = <0 0xe6c40000 0 64>;
1259 interrupts = <GIC_SPI 1259 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1260 clocks = <&cpg CPG_MO 1260 clocks = <&cpg CPG_MOD 203>,
1261 <&cpg CPG_CO 1261 <&cpg CPG_CORE R8A77965_CLK_S3D1>,
1262 <&scif_clk>; 1262 <&scif_clk>;
1263 clock-names = "fck", 1263 clock-names = "fck", "brg_int", "scif_clk";
1264 dmas = <&dmac0 0x59>, 1264 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1265 dma-names = "tx", "rx 1265 dma-names = "tx", "rx";
1266 power-domains = <&sys 1266 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
1267 resets = <&cpg 203>; 1267 resets = <&cpg 203>;
1268 status = "disabled"; 1268 status = "disabled";
1269 }; 1269 };
1270 1270
1271 scif5: serial@e6f30000 { 1271 scif5: serial@e6f30000 {
1272 compatible = "renesas 1272 compatible = "renesas,scif-r8a77965",
1273 "renesas 1273 "renesas,rcar-gen3-scif", "renesas,scif";
1274 reg = <0 0xe6f30000 0 1274 reg = <0 0xe6f30000 0 64>;
1275 interrupts = <GIC_SPI 1275 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1276 clocks = <&cpg CPG_MO 1276 clocks = <&cpg CPG_MOD 202>,
1277 <&cpg CPG_CO 1277 <&cpg CPG_CORE R8A77965_CLK_S3D1>,
1278 <&scif_clk>; 1278 <&scif_clk>;
1279 clock-names = "fck", 1279 clock-names = "fck", "brg_int", "scif_clk";
1280 dmas = <&dmac1 0x5b>, 1280 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
1281 <&dmac2 0x5b>, 1281 <&dmac2 0x5b>, <&dmac2 0x5a>;
1282 dma-names = "tx", "rx 1282 dma-names = "tx", "rx", "tx", "rx";
1283 power-domains = <&sys 1283 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
1284 resets = <&cpg 202>; 1284 resets = <&cpg 202>;
1285 status = "disabled"; 1285 status = "disabled";
1286 }; 1286 };
1287 1287
1288 tpu: pwm@e6e80000 { 1288 tpu: pwm@e6e80000 {
1289 compatible = "renesas 1289 compatible = "renesas,tpu-r8a77965", "renesas,tpu";
1290 reg = <0 0xe6e80000 0 1290 reg = <0 0xe6e80000 0 0x148>;
1291 interrupts = <GIC_SPI 1291 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
1292 clocks = <&cpg CPG_MO 1292 clocks = <&cpg CPG_MOD 304>;
1293 power-domains = <&sys 1293 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
1294 resets = <&cpg 304>; 1294 resets = <&cpg 304>;
1295 #pwm-cells = <3>; 1295 #pwm-cells = <3>;
1296 status = "disabled"; 1296 status = "disabled";
1297 }; 1297 };
1298 1298
1299 msiof0: spi@e6e90000 { 1299 msiof0: spi@e6e90000 {
1300 compatible = "renesas 1300 compatible = "renesas,msiof-r8a77965",
1301 "renesas 1301 "renesas,rcar-gen3-msiof";
1302 reg = <0 0xe6e90000 0 1302 reg = <0 0xe6e90000 0 0x0064>;
1303 interrupts = <GIC_SPI 1303 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1304 clocks = <&cpg CPG_MO 1304 clocks = <&cpg CPG_MOD 211>;
1305 dmas = <&dmac1 0x41>, 1305 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1306 <&dmac2 0x41>, 1306 <&dmac2 0x41>, <&dmac2 0x40>;
1307 dma-names = "tx", "rx 1307 dma-names = "tx", "rx", "tx", "rx";
1308 power-domains = <&sys 1308 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
1309 resets = <&cpg 211>; 1309 resets = <&cpg 211>;
1310 #address-cells = <1>; 1310 #address-cells = <1>;
1311 #size-cells = <0>; 1311 #size-cells = <0>;
1312 status = "disabled"; 1312 status = "disabled";
1313 }; 1313 };
1314 1314
1315 msiof1: spi@e6ea0000 { 1315 msiof1: spi@e6ea0000 {
1316 compatible = "renesas 1316 compatible = "renesas,msiof-r8a77965",
1317 "renesas 1317 "renesas,rcar-gen3-msiof";
1318 reg = <0 0xe6ea0000 0 1318 reg = <0 0xe6ea0000 0 0x0064>;
1319 interrupts = <GIC_SPI 1319 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1320 clocks = <&cpg CPG_MO 1320 clocks = <&cpg CPG_MOD 210>;
1321 dmas = <&dmac1 0x43>, 1321 dmas = <&dmac1 0x43>, <&dmac1 0x42>,
1322 <&dmac2 0x43>, 1322 <&dmac2 0x43>, <&dmac2 0x42>;
1323 dma-names = "tx", "rx 1323 dma-names = "tx", "rx", "tx", "rx";
1324 power-domains = <&sys 1324 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
1325 resets = <&cpg 210>; 1325 resets = <&cpg 210>;
1326 #address-cells = <1>; 1326 #address-cells = <1>;
1327 #size-cells = <0>; 1327 #size-cells = <0>;
1328 status = "disabled"; 1328 status = "disabled";
1329 }; 1329 };
1330 1330
1331 msiof2: spi@e6c00000 { 1331 msiof2: spi@e6c00000 {
1332 compatible = "renesas 1332 compatible = "renesas,msiof-r8a77965",
1333 "renesas 1333 "renesas,rcar-gen3-msiof";
1334 reg = <0 0xe6c00000 0 1334 reg = <0 0xe6c00000 0 0x0064>;
1335 interrupts = <GIC_SPI 1335 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1336 clocks = <&cpg CPG_MO 1336 clocks = <&cpg CPG_MOD 209>;
1337 dmas = <&dmac0 0x45>, 1337 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1338 dma-names = "tx", "rx 1338 dma-names = "tx", "rx";
1339 power-domains = <&sys 1339 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
1340 resets = <&cpg 209>; 1340 resets = <&cpg 209>;
1341 #address-cells = <1>; 1341 #address-cells = <1>;
1342 #size-cells = <0>; 1342 #size-cells = <0>;
1343 status = "disabled"; 1343 status = "disabled";
1344 }; 1344 };
1345 1345
1346 msiof3: spi@e6c10000 { 1346 msiof3: spi@e6c10000 {
1347 compatible = "renesas 1347 compatible = "renesas,msiof-r8a77965",
1348 "renesas 1348 "renesas,rcar-gen3-msiof";
1349 reg = <0 0xe6c10000 0 1349 reg = <0 0xe6c10000 0 0x0064>;
1350 interrupts = <GIC_SPI 1350 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1351 clocks = <&cpg CPG_MO 1351 clocks = <&cpg CPG_MOD 208>;
1352 dmas = <&dmac0 0x47>, 1352 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1353 dma-names = "tx", "rx 1353 dma-names = "tx", "rx";
1354 power-domains = <&sys 1354 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
1355 resets = <&cpg 208>; 1355 resets = <&cpg 208>;
1356 #address-cells = <1>; 1356 #address-cells = <1>;
1357 #size-cells = <0>; 1357 #size-cells = <0>;
1358 status = "disabled"; 1358 status = "disabled";
1359 }; 1359 };
1360 1360
1361 vin0: video@e6ef0000 { 1361 vin0: video@e6ef0000 {
1362 compatible = "renesas 1362 compatible = "renesas,vin-r8a77965";
1363 reg = <0 0xe6ef0000 0 1363 reg = <0 0xe6ef0000 0 0x1000>;
1364 interrupts = <GIC_SPI 1364 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
1365 clocks = <&cpg CPG_MO 1365 clocks = <&cpg CPG_MOD 811>;
1366 power-domains = <&sys 1366 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
1367 resets = <&cpg 811>; 1367 resets = <&cpg 811>;
1368 renesas,id = <0>; 1368 renesas,id = <0>;
1369 status = "disabled"; 1369 status = "disabled";
1370 1370
1371 ports { 1371 ports {
1372 #address-cell 1372 #address-cells = <1>;
1373 #size-cells = 1373 #size-cells = <0>;
1374 1374
1375 port@1 { 1375 port@1 {
1376 #addr 1376 #address-cells = <1>;
1377 #size 1377 #size-cells = <0>;
1378 1378
1379 reg = 1379 reg = <1>;
1380 1380
1381 vin0c 1381 vin0csi20: endpoint@0 {
1382 1382 reg = <0>;
1383 1383 remote-endpoint = <&csi20vin0>;
1384 }; 1384 };
1385 vin0c 1385 vin0csi40: endpoint@2 {
1386 1386 reg = <2>;
1387 1387 remote-endpoint = <&csi40vin0>;
1388 }; 1388 };
1389 }; 1389 };
1390 }; 1390 };
1391 }; 1391 };
1392 1392
1393 vin1: video@e6ef1000 { 1393 vin1: video@e6ef1000 {
1394 compatible = "renesas 1394 compatible = "renesas,vin-r8a77965";
1395 reg = <0 0xe6ef1000 0 1395 reg = <0 0xe6ef1000 0 0x1000>;
1396 interrupts = <GIC_SPI 1396 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
1397 clocks = <&cpg CPG_MO 1397 clocks = <&cpg CPG_MOD 810>;
1398 power-domains = <&sys 1398 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
1399 resets = <&cpg 810>; 1399 resets = <&cpg 810>;
1400 renesas,id = <1>; 1400 renesas,id = <1>;
1401 status = "disabled"; 1401 status = "disabled";
1402 1402
1403 ports { 1403 ports {
1404 #address-cell 1404 #address-cells = <1>;
1405 #size-cells = 1405 #size-cells = <0>;
1406 1406
1407 port@1 { 1407 port@1 {
1408 #addr 1408 #address-cells = <1>;
1409 #size 1409 #size-cells = <0>;
1410 1410
1411 reg = 1411 reg = <1>;
1412 1412
1413 vin1c 1413 vin1csi20: endpoint@0 {
1414 1414 reg = <0>;
1415 1415 remote-endpoint = <&csi20vin1>;
1416 }; 1416 };
1417 vin1c 1417 vin1csi40: endpoint@2 {
1418 1418 reg = <2>;
1419 1419 remote-endpoint = <&csi40vin1>;
1420 }; 1420 };
1421 }; 1421 };
1422 }; 1422 };
1423 }; 1423 };
1424 1424
1425 vin2: video@e6ef2000 { 1425 vin2: video@e6ef2000 {
1426 compatible = "renesas 1426 compatible = "renesas,vin-r8a77965";
1427 reg = <0 0xe6ef2000 0 1427 reg = <0 0xe6ef2000 0 0x1000>;
1428 interrupts = <GIC_SPI 1428 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1429 clocks = <&cpg CPG_MO 1429 clocks = <&cpg CPG_MOD 809>;
1430 power-domains = <&sys 1430 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
1431 resets = <&cpg 809>; 1431 resets = <&cpg 809>;
1432 renesas,id = <2>; 1432 renesas,id = <2>;
1433 status = "disabled"; 1433 status = "disabled";
1434 1434
1435 ports { 1435 ports {
1436 #address-cell 1436 #address-cells = <1>;
1437 #size-cells = 1437 #size-cells = <0>;
1438 1438
1439 port@1 { 1439 port@1 {
1440 #addr 1440 #address-cells = <1>;
1441 #size 1441 #size-cells = <0>;
1442 1442
1443 reg = 1443 reg = <1>;
1444 1444
1445 vin2c 1445 vin2csi20: endpoint@0 {
1446 1446 reg = <0>;
1447 1447 remote-endpoint = <&csi20vin2>;
1448 }; 1448 };
1449 vin2c 1449 vin2csi40: endpoint@2 {
1450 1450 reg = <2>;
1451 1451 remote-endpoint = <&csi40vin2>;
1452 }; 1452 };
1453 }; 1453 };
1454 }; 1454 };
1455 }; 1455 };
1456 1456
1457 vin3: video@e6ef3000 { 1457 vin3: video@e6ef3000 {
1458 compatible = "renesas 1458 compatible = "renesas,vin-r8a77965";
1459 reg = <0 0xe6ef3000 0 1459 reg = <0 0xe6ef3000 0 0x1000>;
1460 interrupts = <GIC_SPI 1460 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
1461 clocks = <&cpg CPG_MO 1461 clocks = <&cpg CPG_MOD 808>;
1462 power-domains = <&sys 1462 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
1463 resets = <&cpg 808>; 1463 resets = <&cpg 808>;
1464 renesas,id = <3>; 1464 renesas,id = <3>;
1465 status = "disabled"; 1465 status = "disabled";
1466 1466
1467 ports { 1467 ports {
1468 #address-cell 1468 #address-cells = <1>;
1469 #size-cells = 1469 #size-cells = <0>;
1470 1470
1471 port@1 { 1471 port@1 {
1472 #addr 1472 #address-cells = <1>;
1473 #size 1473 #size-cells = <0>;
1474 1474
1475 reg = 1475 reg = <1>;
1476 1476
1477 vin3c 1477 vin3csi20: endpoint@0 {
1478 1478 reg = <0>;
1479 1479 remote-endpoint = <&csi20vin3>;
1480 }; 1480 };
1481 vin3c 1481 vin3csi40: endpoint@2 {
1482 1482 reg = <2>;
1483 1483 remote-endpoint = <&csi40vin3>;
1484 }; 1484 };
1485 }; 1485 };
1486 }; 1486 };
1487 }; 1487 };
1488 1488
1489 vin4: video@e6ef4000 { 1489 vin4: video@e6ef4000 {
1490 compatible = "renesas 1490 compatible = "renesas,vin-r8a77965";
1491 reg = <0 0xe6ef4000 0 1491 reg = <0 0xe6ef4000 0 0x1000>;
1492 interrupts = <GIC_SPI 1492 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
1493 clocks = <&cpg CPG_MO 1493 clocks = <&cpg CPG_MOD 807>;
1494 power-domains = <&sys 1494 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
1495 resets = <&cpg 807>; 1495 resets = <&cpg 807>;
1496 renesas,id = <4>; 1496 renesas,id = <4>;
1497 status = "disabled"; 1497 status = "disabled";
1498 1498
1499 ports { 1499 ports {
1500 #address-cell 1500 #address-cells = <1>;
1501 #size-cells = 1501 #size-cells = <0>;
1502 1502
1503 port@1 { 1503 port@1 {
1504 #addr 1504 #address-cells = <1>;
1505 #size 1505 #size-cells = <0>;
1506 1506
1507 reg = 1507 reg = <1>;
1508 1508
1509 vin4c 1509 vin4csi20: endpoint@0 {
1510 1510 reg = <0>;
1511 1511 remote-endpoint = <&csi20vin4>;
1512 }; 1512 };
1513 vin4c 1513 vin4csi40: endpoint@2 {
1514 1514 reg = <2>;
1515 1515 remote-endpoint = <&csi40vin4>;
1516 }; 1516 };
1517 }; 1517 };
1518 }; 1518 };
1519 }; 1519 };
1520 1520
1521 vin5: video@e6ef5000 { 1521 vin5: video@e6ef5000 {
1522 compatible = "renesas 1522 compatible = "renesas,vin-r8a77965";
1523 reg = <0 0xe6ef5000 0 1523 reg = <0 0xe6ef5000 0 0x1000>;
1524 interrupts = <GIC_SPI 1524 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
1525 clocks = <&cpg CPG_MO 1525 clocks = <&cpg CPG_MOD 806>;
1526 power-domains = <&sys 1526 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
1527 resets = <&cpg 806>; 1527 resets = <&cpg 806>;
1528 renesas,id = <5>; 1528 renesas,id = <5>;
1529 status = "disabled"; 1529 status = "disabled";
1530 1530
1531 ports { 1531 ports {
1532 #address-cell 1532 #address-cells = <1>;
1533 #size-cells = 1533 #size-cells = <0>;
1534 1534
1535 port@1 { 1535 port@1 {
1536 #addr 1536 #address-cells = <1>;
1537 #size 1537 #size-cells = <0>;
1538 1538
1539 reg = 1539 reg = <1>;
1540 1540
1541 vin5c 1541 vin5csi20: endpoint@0 {
1542 1542 reg = <0>;
1543 1543 remote-endpoint = <&csi20vin5>;
1544 }; 1544 };
1545 vin5c 1545 vin5csi40: endpoint@2 {
1546 1546 reg = <2>;
1547 1547 remote-endpoint = <&csi40vin5>;
1548 }; 1548 };
1549 }; 1549 };
1550 }; 1550 };
1551 }; 1551 };
1552 1552
1553 vin6: video@e6ef6000 { 1553 vin6: video@e6ef6000 {
1554 compatible = "renesas 1554 compatible = "renesas,vin-r8a77965";
1555 reg = <0 0xe6ef6000 0 1555 reg = <0 0xe6ef6000 0 0x1000>;
1556 interrupts = <GIC_SPI 1556 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
1557 clocks = <&cpg CPG_MO 1557 clocks = <&cpg CPG_MOD 805>;
1558 power-domains = <&sys 1558 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
1559 resets = <&cpg 805>; 1559 resets = <&cpg 805>;
1560 renesas,id = <6>; 1560 renesas,id = <6>;
1561 status = "disabled"; 1561 status = "disabled";
1562 1562
1563 ports { 1563 ports {
1564 #address-cell 1564 #address-cells = <1>;
1565 #size-cells = 1565 #size-cells = <0>;
1566 1566
1567 port@1 { 1567 port@1 {
1568 #addr 1568 #address-cells = <1>;
1569 #size 1569 #size-cells = <0>;
1570 1570
1571 reg = 1571 reg = <1>;
1572 1572
1573 vin6c 1573 vin6csi20: endpoint@0 {
1574 1574 reg = <0>;
1575 1575 remote-endpoint = <&csi20vin6>;
1576 }; 1576 };
1577 vin6c 1577 vin6csi40: endpoint@2 {
1578 1578 reg = <2>;
1579 1579 remote-endpoint = <&csi40vin6>;
1580 }; 1580 };
1581 }; 1581 };
1582 }; 1582 };
1583 }; 1583 };
1584 1584
1585 vin7: video@e6ef7000 { 1585 vin7: video@e6ef7000 {
1586 compatible = "renesas 1586 compatible = "renesas,vin-r8a77965";
1587 reg = <0 0xe6ef7000 0 1587 reg = <0 0xe6ef7000 0 0x1000>;
1588 interrupts = <GIC_SPI 1588 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
1589 clocks = <&cpg CPG_MO 1589 clocks = <&cpg CPG_MOD 804>;
1590 power-domains = <&sys 1590 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
1591 resets = <&cpg 804>; 1591 resets = <&cpg 804>;
1592 renesas,id = <7>; 1592 renesas,id = <7>;
1593 status = "disabled"; 1593 status = "disabled";
1594 1594
1595 ports { 1595 ports {
1596 #address-cell 1596 #address-cells = <1>;
1597 #size-cells = 1597 #size-cells = <0>;
1598 1598
1599 port@1 { 1599 port@1 {
1600 #addr 1600 #address-cells = <1>;
1601 #size 1601 #size-cells = <0>;
1602 1602
1603 reg = 1603 reg = <1>;
1604 1604
1605 vin7c 1605 vin7csi20: endpoint@0 {
1606 1606 reg = <0>;
1607 1607 remote-endpoint = <&csi20vin7>;
1608 }; 1608 };
1609 vin7c 1609 vin7csi40: endpoint@2 {
1610 1610 reg = <2>;
1611 1611 remote-endpoint = <&csi40vin7>;
1612 }; 1612 };
1613 }; 1613 };
1614 }; 1614 };
1615 }; 1615 };
1616 1616
1617 drif00: rif@e6f40000 { 1617 drif00: rif@e6f40000 {
1618 compatible = "renesas 1618 compatible = "renesas,r8a77965-drif",
1619 "renesas 1619 "renesas,rcar-gen3-drif";
1620 reg = <0 0xe6f40000 0 1620 reg = <0 0xe6f40000 0 0x84>;
1621 interrupts = <GIC_SPI 1621 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1622 clocks = <&cpg CPG_MO 1622 clocks = <&cpg CPG_MOD 515>;
1623 clock-names = "fck"; 1623 clock-names = "fck";
1624 dmas = <&dmac1 0x20>, 1624 dmas = <&dmac1 0x20>, <&dmac2 0x20>;
1625 dma-names = "rx", "rx 1625 dma-names = "rx", "rx";
1626 power-domains = <&sys 1626 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
1627 resets = <&cpg 515>; 1627 resets = <&cpg 515>;
1628 renesas,bonding = <&d 1628 renesas,bonding = <&drif01>;
1629 status = "disabled"; 1629 status = "disabled";
1630 }; 1630 };
1631 1631
1632 drif01: rif@e6f50000 { 1632 drif01: rif@e6f50000 {
1633 compatible = "renesas 1633 compatible = "renesas,r8a77965-drif",
1634 "renesas 1634 "renesas,rcar-gen3-drif";
1635 reg = <0 0xe6f50000 0 1635 reg = <0 0xe6f50000 0 0x84>;
1636 interrupts = <GIC_SPI 1636 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1637 clocks = <&cpg CPG_MO 1637 clocks = <&cpg CPG_MOD 514>;
1638 clock-names = "fck"; 1638 clock-names = "fck";
1639 dmas = <&dmac1 0x22>, 1639 dmas = <&dmac1 0x22>, <&dmac2 0x22>;
1640 dma-names = "rx", "rx 1640 dma-names = "rx", "rx";
1641 power-domains = <&sys 1641 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
1642 resets = <&cpg 514>; 1642 resets = <&cpg 514>;
1643 renesas,bonding = <&d 1643 renesas,bonding = <&drif00>;
1644 status = "disabled"; 1644 status = "disabled";
1645 }; 1645 };
1646 1646
1647 drif10: rif@e6f60000 { 1647 drif10: rif@e6f60000 {
1648 compatible = "renesas 1648 compatible = "renesas,r8a77965-drif",
1649 "renesas 1649 "renesas,rcar-gen3-drif";
1650 reg = <0 0xe6f60000 0 1650 reg = <0 0xe6f60000 0 0x84>;
1651 interrupts = <GIC_SPI 1651 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1652 clocks = <&cpg CPG_MO 1652 clocks = <&cpg CPG_MOD 513>;
1653 clock-names = "fck"; 1653 clock-names = "fck";
1654 dmas = <&dmac1 0x24>, 1654 dmas = <&dmac1 0x24>, <&dmac2 0x24>;
1655 dma-names = "rx", "rx 1655 dma-names = "rx", "rx";
1656 power-domains = <&sys 1656 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
1657 resets = <&cpg 513>; 1657 resets = <&cpg 513>;
1658 renesas,bonding = <&d 1658 renesas,bonding = <&drif11>;
1659 status = "disabled"; 1659 status = "disabled";
1660 }; 1660 };
1661 1661
1662 drif11: rif@e6f70000 { 1662 drif11: rif@e6f70000 {
1663 compatible = "renesas 1663 compatible = "renesas,r8a77965-drif",
1664 "renesas 1664 "renesas,rcar-gen3-drif";
1665 reg = <0 0xe6f70000 0 1665 reg = <0 0xe6f70000 0 0x84>;
1666 interrupts = <GIC_SPI 1666 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1667 clocks = <&cpg CPG_MO 1667 clocks = <&cpg CPG_MOD 512>;
1668 clock-names = "fck"; 1668 clock-names = "fck";
1669 dmas = <&dmac1 0x26>, 1669 dmas = <&dmac1 0x26>, <&dmac2 0x26>;
1670 dma-names = "rx", "rx 1670 dma-names = "rx", "rx";
1671 power-domains = <&sys 1671 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
1672 resets = <&cpg 512>; 1672 resets = <&cpg 512>;
1673 renesas,bonding = <&d 1673 renesas,bonding = <&drif10>;
1674 status = "disabled"; 1674 status = "disabled";
1675 }; 1675 };
1676 1676
1677 drif20: rif@e6f80000 { 1677 drif20: rif@e6f80000 {
1678 compatible = "renesas 1678 compatible = "renesas,r8a77965-drif",
1679 "renesas 1679 "renesas,rcar-gen3-drif";
1680 reg = <0 0xe6f80000 0 1680 reg = <0 0xe6f80000 0 0x84>;
1681 interrupts = <GIC_SPI 1681 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1682 clocks = <&cpg CPG_MO 1682 clocks = <&cpg CPG_MOD 511>;
1683 clock-names = "fck"; 1683 clock-names = "fck";
1684 dmas = <&dmac1 0x28>, 1684 dmas = <&dmac1 0x28>, <&dmac2 0x28>;
1685 dma-names = "rx", "rx 1685 dma-names = "rx", "rx";
1686 power-domains = <&sys 1686 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
1687 resets = <&cpg 511>; 1687 resets = <&cpg 511>;
1688 renesas,bonding = <&d 1688 renesas,bonding = <&drif21>;
1689 status = "disabled"; 1689 status = "disabled";
1690 }; 1690 };
1691 1691
1692 drif21: rif@e6f90000 { 1692 drif21: rif@e6f90000 {
1693 compatible = "renesas 1693 compatible = "renesas,r8a77965-drif",
1694 "renesas 1694 "renesas,rcar-gen3-drif";
1695 reg = <0 0xe6f90000 0 1695 reg = <0 0xe6f90000 0 0x84>;
1696 interrupts = <GIC_SPI 1696 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1697 clocks = <&cpg CPG_MO 1697 clocks = <&cpg CPG_MOD 510>;
1698 clock-names = "fck"; 1698 clock-names = "fck";
1699 dmas = <&dmac1 0x2a>, 1699 dmas = <&dmac1 0x2a>, <&dmac2 0x2a>;
1700 dma-names = "rx", "rx 1700 dma-names = "rx", "rx";
1701 power-domains = <&sys 1701 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
1702 resets = <&cpg 510>; 1702 resets = <&cpg 510>;
1703 renesas,bonding = <&d 1703 renesas,bonding = <&drif20>;
1704 status = "disabled"; 1704 status = "disabled";
1705 }; 1705 };
1706 1706
1707 drif30: rif@e6fa0000 { 1707 drif30: rif@e6fa0000 {
1708 compatible = "renesas 1708 compatible = "renesas,r8a77965-drif",
1709 "renesas 1709 "renesas,rcar-gen3-drif";
1710 reg = <0 0xe6fa0000 0 1710 reg = <0 0xe6fa0000 0 0x84>;
1711 interrupts = <GIC_SPI 1711 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1712 clocks = <&cpg CPG_MO 1712 clocks = <&cpg CPG_MOD 509>;
1713 clock-names = "fck"; 1713 clock-names = "fck";
1714 dmas = <&dmac1 0x2c>, 1714 dmas = <&dmac1 0x2c>, <&dmac2 0x2c>;
1715 dma-names = "rx", "rx 1715 dma-names = "rx", "rx";
1716 power-domains = <&sys 1716 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
1717 resets = <&cpg 509>; 1717 resets = <&cpg 509>;
1718 renesas,bonding = <&d 1718 renesas,bonding = <&drif31>;
1719 status = "disabled"; 1719 status = "disabled";
1720 }; 1720 };
1721 1721
1722 drif31: rif@e6fb0000 { 1722 drif31: rif@e6fb0000 {
1723 compatible = "renesas 1723 compatible = "renesas,r8a77965-drif",
1724 "renesas 1724 "renesas,rcar-gen3-drif";
1725 reg = <0 0xe6fb0000 0 1725 reg = <0 0xe6fb0000 0 0x84>;
1726 interrupts = <GIC_SPI 1726 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1727 clocks = <&cpg CPG_MO 1727 clocks = <&cpg CPG_MOD 508>;
1728 clock-names = "fck"; 1728 clock-names = "fck";
1729 dmas = <&dmac1 0x2e>, 1729 dmas = <&dmac1 0x2e>, <&dmac2 0x2e>;
1730 dma-names = "rx", "rx 1730 dma-names = "rx", "rx";
1731 power-domains = <&sys 1731 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
1732 resets = <&cpg 508>; 1732 resets = <&cpg 508>;
1733 renesas,bonding = <&d 1733 renesas,bonding = <&drif30>;
1734 status = "disabled"; 1734 status = "disabled";
1735 }; 1735 };
1736 1736
1737 rcar_sound: sound@ec500000 { 1737 rcar_sound: sound@ec500000 {
1738 /* 1738 /*
1739 * #sound-dai-cells i 1739 * #sound-dai-cells is required if simple-card
1740 * 1740 *
1741 * Single DAI : #soun 1741 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1742 * Multi DAI : #soun 1742 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1743 */ 1743 */
1744 /* 1744 /*
1745 * #clock-cells is re 1745 * #clock-cells is required for audio_clkout0/1/2/3
1746 * 1746 *
1747 * clkout : #cl 1747 * clkout : #clock-cells = <0>; <&rcar_sound>;
1748 * clkout0/1/2/3: #cl 1748 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
1749 */ 1749 */
1750 compatible = "renesas 1750 compatible = "renesas,rcar_sound-r8a77965", "renesas,rcar_sound-gen3";
1751 reg = <0 0xec500000 0 1751 reg = <0 0xec500000 0 0x1000>, /* SCU */
1752 <0 0xec5a0000 0 1752 <0 0xec5a0000 0 0x100>, /* ADG */
1753 <0 0xec540000 0 1753 <0 0xec540000 0 0x1000>, /* SSIU */
1754 <0 0xec541000 0 1754 <0 0xec541000 0 0x280>, /* SSI */
1755 <0 0xec760000 0 1755 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
1756 reg-names = "scu", "a 1756 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1757 1757
1758 clocks = <&cpg CPG_MO 1758 clocks = <&cpg CPG_MOD 1005>,
1759 <&cpg CPG_MO 1759 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
1760 <&cpg CPG_MO 1760 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
1761 <&cpg CPG_MO 1761 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
1762 <&cpg CPG_MO 1762 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
1763 <&cpg CPG_MO 1763 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
1764 <&cpg CPG_MO 1764 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
1765 <&cpg CPG_MO 1765 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
1766 <&cpg CPG_MO 1766 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
1767 <&cpg CPG_MO 1767 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
1768 <&cpg CPG_MO 1768 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
1769 <&cpg CPG_MO 1769 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1770 <&cpg CPG_MO 1770 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1771 <&cpg CPG_MO 1771 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
1772 <&audio_clk_ 1772 <&audio_clk_a>, <&audio_clk_b>,
1773 <&audio_clk_ 1773 <&audio_clk_c>,
1774 <&cpg CPG_MO 1774 <&cpg CPG_MOD 922>;
1775 clock-names = "ssi-al 1775 clock-names = "ssi-all",
1776 "ssi.9" 1776 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1777 "ssi.5" 1777 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1778 "ssi.1" 1778 "ssi.1", "ssi.0",
1779 "src.9" 1779 "src.9", "src.8", "src.7", "src.6",
1780 "src.5" 1780 "src.5", "src.4", "src.3", "src.2",
1781 "src.1" 1781 "src.1", "src.0",
1782 "mix.1" 1782 "mix.1", "mix.0",
1783 "ctu.1" 1783 "ctu.1", "ctu.0",
1784 "dvc.0" 1784 "dvc.0", "dvc.1",
1785 "clk_a" 1785 "clk_a", "clk_b", "clk_c", "clk_i";
1786 power-domains = <&sys 1786 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
1787 resets = <&cpg 1005>, 1787 resets = <&cpg 1005>,
1788 <&cpg 1006>, 1788 <&cpg 1006>, <&cpg 1007>,
1789 <&cpg 1008>, 1789 <&cpg 1008>, <&cpg 1009>,
1790 <&cpg 1010>, 1790 <&cpg 1010>, <&cpg 1011>,
1791 <&cpg 1012>, 1791 <&cpg 1012>, <&cpg 1013>,
1792 <&cpg 1014>, 1792 <&cpg 1014>, <&cpg 1015>;
1793 reset-names = "ssi-al 1793 reset-names = "ssi-all",
1794 "ssi.9" 1794 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1795 "ssi.5" 1795 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1796 "ssi.1" 1796 "ssi.1", "ssi.0";
1797 status = "disabled"; 1797 status = "disabled";
1798 1798
1799 rcar_sound,dvc { 1799 rcar_sound,dvc {
1800 dvc0: dvc-0 { 1800 dvc0: dvc-0 {
1801 dmas 1801 dmas = <&audma1 0xbc>;
1802 dma-n 1802 dma-names = "tx";
1803 }; 1803 };
1804 dvc1: dvc-1 { 1804 dvc1: dvc-1 {
1805 dmas 1805 dmas = <&audma1 0xbe>;
1806 dma-n 1806 dma-names = "tx";
1807 }; 1807 };
1808 }; 1808 };
1809 1809
1810 rcar_sound,mix { 1810 rcar_sound,mix {
1811 mix0: mix-0 { 1811 mix0: mix-0 { };
1812 mix1: mix-1 { 1812 mix1: mix-1 { };
1813 }; 1813 };
1814 1814
1815 rcar_sound,ctu { 1815 rcar_sound,ctu {
1816 ctu00: ctu-0 1816 ctu00: ctu-0 { };
1817 ctu01: ctu-1 1817 ctu01: ctu-1 { };
1818 ctu02: ctu-2 1818 ctu02: ctu-2 { };
1819 ctu03: ctu-3 1819 ctu03: ctu-3 { };
1820 ctu10: ctu-4 1820 ctu10: ctu-4 { };
1821 ctu11: ctu-5 1821 ctu11: ctu-5 { };
1822 ctu12: ctu-6 1822 ctu12: ctu-6 { };
1823 ctu13: ctu-7 1823 ctu13: ctu-7 { };
1824 }; 1824 };
1825 1825
1826 rcar_sound,src { 1826 rcar_sound,src {
1827 src0: src-0 { 1827 src0: src-0 {
1828 inter 1828 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1829 dmas 1829 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1830 dma-n 1830 dma-names = "rx", "tx";
1831 }; 1831 };
1832 src1: src-1 { 1832 src1: src-1 {
1833 inter 1833 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1834 dmas 1834 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1835 dma-n 1835 dma-names = "rx", "tx";
1836 }; 1836 };
1837 src2: src-2 { 1837 src2: src-2 {
1838 inter 1838 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1839 dmas 1839 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1840 dma-n 1840 dma-names = "rx", "tx";
1841 }; 1841 };
1842 src3: src-3 { 1842 src3: src-3 {
1843 inter 1843 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1844 dmas 1844 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1845 dma-n 1845 dma-names = "rx", "tx";
1846 }; 1846 };
1847 src4: src-4 { 1847 src4: src-4 {
1848 inter 1848 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1849 dmas 1849 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1850 dma-n 1850 dma-names = "rx", "tx";
1851 }; 1851 };
1852 src5: src-5 { 1852 src5: src-5 {
1853 inter 1853 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1854 dmas 1854 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1855 dma-n 1855 dma-names = "rx", "tx";
1856 }; 1856 };
1857 src6: src-6 { 1857 src6: src-6 {
1858 inter 1858 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1859 dmas 1859 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1860 dma-n 1860 dma-names = "rx", "tx";
1861 }; 1861 };
1862 src7: src-7 { 1862 src7: src-7 {
1863 inter 1863 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1864 dmas 1864 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1865 dma-n 1865 dma-names = "rx", "tx";
1866 }; 1866 };
1867 src8: src-8 { 1867 src8: src-8 {
1868 inter 1868 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1869 dmas 1869 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1870 dma-n 1870 dma-names = "rx", "tx";
1871 }; 1871 };
1872 src9: src-9 { 1872 src9: src-9 {
1873 inter 1873 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
1874 dmas 1874 dmas = <&audma0 0x97>, <&audma1 0xba>;
1875 dma-n 1875 dma-names = "rx", "tx";
1876 }; 1876 };
1877 }; 1877 };
1878 1878
1879 rcar_sound,ssiu { 1879 rcar_sound,ssiu {
1880 ssiu00: ssiu- 1880 ssiu00: ssiu-0 {
1881 dmas 1881 dmas = <&audma0 0x15>, <&audma1 0x16>;
1882 dma-n 1882 dma-names = "rx", "tx";
1883 }; 1883 };
1884 ssiu01: ssiu- 1884 ssiu01: ssiu-1 {
1885 dmas 1885 dmas = <&audma0 0x35>, <&audma1 0x36>;
1886 dma-n 1886 dma-names = "rx", "tx";
1887 }; 1887 };
1888 ssiu02: ssiu- 1888 ssiu02: ssiu-2 {
1889 dmas 1889 dmas = <&audma0 0x37>, <&audma1 0x38>;
1890 dma-n 1890 dma-names = "rx", "tx";
1891 }; 1891 };
1892 ssiu03: ssiu- 1892 ssiu03: ssiu-3 {
1893 dmas 1893 dmas = <&audma0 0x47>, <&audma1 0x48>;
1894 dma-n 1894 dma-names = "rx", "tx";
1895 }; 1895 };
1896 ssiu04: ssiu- 1896 ssiu04: ssiu-4 {
1897 dmas 1897 dmas = <&audma0 0x3F>, <&audma1 0x40>;
1898 dma-n 1898 dma-names = "rx", "tx";
1899 }; 1899 };
1900 ssiu05: ssiu- 1900 ssiu05: ssiu-5 {
1901 dmas 1901 dmas = <&audma0 0x43>, <&audma1 0x44>;
1902 dma-n 1902 dma-names = "rx", "tx";
1903 }; 1903 };
1904 ssiu06: ssiu- 1904 ssiu06: ssiu-6 {
1905 dmas 1905 dmas = <&audma0 0x4F>, <&audma1 0x50>;
1906 dma-n 1906 dma-names = "rx", "tx";
1907 }; 1907 };
1908 ssiu07: ssiu- 1908 ssiu07: ssiu-7 {
1909 dmas 1909 dmas = <&audma0 0x53>, <&audma1 0x54>;
1910 dma-n 1910 dma-names = "rx", "tx";
1911 }; 1911 };
1912 ssiu10: ssiu- 1912 ssiu10: ssiu-8 {
1913 dmas 1913 dmas = <&audma0 0x49>, <&audma1 0x4a>;
1914 dma-n 1914 dma-names = "rx", "tx";
1915 }; 1915 };
1916 ssiu11: ssiu- 1916 ssiu11: ssiu-9 {
1917 dmas 1917 dmas = <&audma0 0x4B>, <&audma1 0x4C>;
1918 dma-n 1918 dma-names = "rx", "tx";
1919 }; 1919 };
1920 ssiu12: ssiu- 1920 ssiu12: ssiu-10 {
1921 dmas 1921 dmas = <&audma0 0x57>, <&audma1 0x58>;
1922 dma-n 1922 dma-names = "rx", "tx";
1923 }; 1923 };
1924 ssiu13: ssiu- 1924 ssiu13: ssiu-11 {
1925 dmas 1925 dmas = <&audma0 0x59>, <&audma1 0x5A>;
1926 dma-n 1926 dma-names = "rx", "tx";
1927 }; 1927 };
1928 ssiu14: ssiu- 1928 ssiu14: ssiu-12 {
1929 dmas 1929 dmas = <&audma0 0x5F>, <&audma1 0x60>;
1930 dma-n 1930 dma-names = "rx", "tx";
1931 }; 1931 };
1932 ssiu15: ssiu- 1932 ssiu15: ssiu-13 {
1933 dmas 1933 dmas = <&audma0 0xC3>, <&audma1 0xC4>;
1934 dma-n 1934 dma-names = "rx", "tx";
1935 }; 1935 };
1936 ssiu16: ssiu- 1936 ssiu16: ssiu-14 {
1937 dmas 1937 dmas = <&audma0 0xC7>, <&audma1 0xC8>;
1938 dma-n 1938 dma-names = "rx", "tx";
1939 }; 1939 };
1940 ssiu17: ssiu- 1940 ssiu17: ssiu-15 {
1941 dmas 1941 dmas = <&audma0 0xCB>, <&audma1 0xCC>;
1942 dma-n 1942 dma-names = "rx", "tx";
1943 }; 1943 };
1944 ssiu20: ssiu- 1944 ssiu20: ssiu-16 {
1945 dmas 1945 dmas = <&audma0 0x63>, <&audma1 0x64>;
1946 dma-n 1946 dma-names = "rx", "tx";
1947 }; 1947 };
1948 ssiu21: ssiu- 1948 ssiu21: ssiu-17 {
1949 dmas 1949 dmas = <&audma0 0x67>, <&audma1 0x68>;
1950 dma-n 1950 dma-names = "rx", "tx";
1951 }; 1951 };
1952 ssiu22: ssiu- 1952 ssiu22: ssiu-18 {
1953 dmas 1953 dmas = <&audma0 0x6B>, <&audma1 0x6C>;
1954 dma-n 1954 dma-names = "rx", "tx";
1955 }; 1955 };
1956 ssiu23: ssiu- 1956 ssiu23: ssiu-19 {
1957 dmas 1957 dmas = <&audma0 0x6D>, <&audma1 0x6E>;
1958 dma-n 1958 dma-names = "rx", "tx";
1959 }; 1959 };
1960 ssiu24: ssiu- 1960 ssiu24: ssiu-20 {
1961 dmas 1961 dmas = <&audma0 0xCF>, <&audma1 0xCE>;
1962 dma-n 1962 dma-names = "rx", "tx";
1963 }; 1963 };
1964 ssiu25: ssiu- 1964 ssiu25: ssiu-21 {
1965 dmas 1965 dmas = <&audma0 0xEB>, <&audma1 0xEC>;
1966 dma-n 1966 dma-names = "rx", "tx";
1967 }; 1967 };
1968 ssiu26: ssiu- 1968 ssiu26: ssiu-22 {
1969 dmas 1969 dmas = <&audma0 0xED>, <&audma1 0xEE>;
1970 dma-n 1970 dma-names = "rx", "tx";
1971 }; 1971 };
1972 ssiu27: ssiu- 1972 ssiu27: ssiu-23 {
1973 dmas 1973 dmas = <&audma0 0xEF>, <&audma1 0xF0>;
1974 dma-n 1974 dma-names = "rx", "tx";
1975 }; 1975 };
1976 ssiu30: ssiu- 1976 ssiu30: ssiu-24 {
1977 dmas 1977 dmas = <&audma0 0x6f>, <&audma1 0x70>;
1978 dma-n 1978 dma-names = "rx", "tx";
1979 }; 1979 };
1980 ssiu31: ssiu- 1980 ssiu31: ssiu-25 {
1981 dmas 1981 dmas = <&audma0 0x21>, <&audma1 0x22>;
1982 dma-n 1982 dma-names = "rx", "tx";
1983 }; 1983 };
1984 ssiu32: ssiu- 1984 ssiu32: ssiu-26 {
1985 dmas 1985 dmas = <&audma0 0x23>, <&audma1 0x24>;
1986 dma-n 1986 dma-names = "rx", "tx";
1987 }; 1987 };
1988 ssiu33: ssiu- 1988 ssiu33: ssiu-27 {
1989 dmas 1989 dmas = <&audma0 0x25>, <&audma1 0x26>;
1990 dma-n 1990 dma-names = "rx", "tx";
1991 }; 1991 };
1992 ssiu34: ssiu- 1992 ssiu34: ssiu-28 {
1993 dmas 1993 dmas = <&audma0 0x27>, <&audma1 0x28>;
1994 dma-n 1994 dma-names = "rx", "tx";
1995 }; 1995 };
1996 ssiu35: ssiu- 1996 ssiu35: ssiu-29 {
1997 dmas 1997 dmas = <&audma0 0x29>, <&audma1 0x2A>;
1998 dma-n 1998 dma-names = "rx", "tx";
1999 }; 1999 };
2000 ssiu36: ssiu- 2000 ssiu36: ssiu-30 {
2001 dmas 2001 dmas = <&audma0 0x2B>, <&audma1 0x2C>;
2002 dma-n 2002 dma-names = "rx", "tx";
2003 }; 2003 };
2004 ssiu37: ssiu- 2004 ssiu37: ssiu-31 {
2005 dmas 2005 dmas = <&audma0 0x2D>, <&audma1 0x2E>;
2006 dma-n 2006 dma-names = "rx", "tx";
2007 }; 2007 };
2008 ssiu40: ssiu- 2008 ssiu40: ssiu-32 {
2009 dmas 2009 dmas = <&audma0 0x71>, <&audma1 0x72>;
2010 dma-n 2010 dma-names = "rx", "tx";
2011 }; 2011 };
2012 ssiu41: ssiu- 2012 ssiu41: ssiu-33 {
2013 dmas 2013 dmas = <&audma0 0x17>, <&audma1 0x18>;
2014 dma-n 2014 dma-names = "rx", "tx";
2015 }; 2015 };
2016 ssiu42: ssiu- 2016 ssiu42: ssiu-34 {
2017 dmas 2017 dmas = <&audma0 0x19>, <&audma1 0x1A>;
2018 dma-n 2018 dma-names = "rx", "tx";
2019 }; 2019 };
2020 ssiu43: ssiu- 2020 ssiu43: ssiu-35 {
2021 dmas 2021 dmas = <&audma0 0x1B>, <&audma1 0x1C>;
2022 dma-n 2022 dma-names = "rx", "tx";
2023 }; 2023 };
2024 ssiu44: ssiu- 2024 ssiu44: ssiu-36 {
2025 dmas 2025 dmas = <&audma0 0x1D>, <&audma1 0x1E>;
2026 dma-n 2026 dma-names = "rx", "tx";
2027 }; 2027 };
2028 ssiu45: ssiu- 2028 ssiu45: ssiu-37 {
2029 dmas 2029 dmas = <&audma0 0x1F>, <&audma1 0x20>;
2030 dma-n 2030 dma-names = "rx", "tx";
2031 }; 2031 };
2032 ssiu46: ssiu- 2032 ssiu46: ssiu-38 {
2033 dmas 2033 dmas = <&audma0 0x31>, <&audma1 0x32>;
2034 dma-n 2034 dma-names = "rx", "tx";
2035 }; 2035 };
2036 ssiu47: ssiu- 2036 ssiu47: ssiu-39 {
2037 dmas 2037 dmas = <&audma0 0x33>, <&audma1 0x34>;
2038 dma-n 2038 dma-names = "rx", "tx";
2039 }; 2039 };
2040 ssiu50: ssiu- 2040 ssiu50: ssiu-40 {
2041 dmas 2041 dmas = <&audma0 0x73>, <&audma1 0x74>;
2042 dma-n 2042 dma-names = "rx", "tx";
2043 }; 2043 };
2044 ssiu60: ssiu- 2044 ssiu60: ssiu-41 {
2045 dmas 2045 dmas = <&audma0 0x75>, <&audma1 0x76>;
2046 dma-n 2046 dma-names = "rx", "tx";
2047 }; 2047 };
2048 ssiu70: ssiu- 2048 ssiu70: ssiu-42 {
2049 dmas 2049 dmas = <&audma0 0x79>, <&audma1 0x7a>;
2050 dma-n 2050 dma-names = "rx", "tx";
2051 }; 2051 };
2052 ssiu80: ssiu- 2052 ssiu80: ssiu-43 {
2053 dmas 2053 dmas = <&audma0 0x7b>, <&audma1 0x7c>;
2054 dma-n 2054 dma-names = "rx", "tx";
2055 }; 2055 };
2056 ssiu90: ssiu- 2056 ssiu90: ssiu-44 {
2057 dmas 2057 dmas = <&audma0 0x7d>, <&audma1 0x7e>;
2058 dma-n 2058 dma-names = "rx", "tx";
2059 }; 2059 };
2060 ssiu91: ssiu- 2060 ssiu91: ssiu-45 {
2061 dmas 2061 dmas = <&audma0 0x7F>, <&audma1 0x80>;
2062 dma-n 2062 dma-names = "rx", "tx";
2063 }; 2063 };
2064 ssiu92: ssiu- 2064 ssiu92: ssiu-46 {
2065 dmas 2065 dmas = <&audma0 0x81>, <&audma1 0x82>;
2066 dma-n 2066 dma-names = "rx", "tx";
2067 }; 2067 };
2068 ssiu93: ssiu- 2068 ssiu93: ssiu-47 {
2069 dmas 2069 dmas = <&audma0 0x83>, <&audma1 0x84>;
2070 dma-n 2070 dma-names = "rx", "tx";
2071 }; 2071 };
2072 ssiu94: ssiu- 2072 ssiu94: ssiu-48 {
2073 dmas 2073 dmas = <&audma0 0xA3>, <&audma1 0xA4>;
2074 dma-n 2074 dma-names = "rx", "tx";
2075 }; 2075 };
2076 ssiu95: ssiu- 2076 ssiu95: ssiu-49 {
2077 dmas 2077 dmas = <&audma0 0xA5>, <&audma1 0xA6>;
2078 dma-n 2078 dma-names = "rx", "tx";
2079 }; 2079 };
2080 ssiu96: ssiu- 2080 ssiu96: ssiu-50 {
2081 dmas 2081 dmas = <&audma0 0xA7>, <&audma1 0xA8>;
2082 dma-n 2082 dma-names = "rx", "tx";
2083 }; 2083 };
2084 ssiu97: ssiu- 2084 ssiu97: ssiu-51 {
2085 dmas 2085 dmas = <&audma0 0xA9>, <&audma1 0xAA>;
2086 dma-n 2086 dma-names = "rx", "tx";
2087 }; 2087 };
2088 }; 2088 };
2089 2089
2090 rcar_sound,ssi { 2090 rcar_sound,ssi {
2091 ssi0: ssi-0 { 2091 ssi0: ssi-0 {
2092 inter 2092 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
2093 dmas 2093 dmas = <&audma0 0x01>, <&audma1 0x02>;
2094 dma-n 2094 dma-names = "rx", "tx";
2095 }; 2095 };
2096 ssi1: ssi-1 { 2096 ssi1: ssi-1 {
2097 inter 2097 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
2098 dmas 2098 dmas = <&audma0 0x03>, <&audma1 0x04>;
2099 dma-n 2099 dma-names = "rx", "tx";
2100 }; 2100 };
2101 ssi2: ssi-2 { 2101 ssi2: ssi-2 {
2102 inter 2102 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
2103 dmas 2103 dmas = <&audma0 0x05>, <&audma1 0x06>;
2104 dma-n 2104 dma-names = "rx", "tx";
2105 }; 2105 };
2106 ssi3: ssi-3 { 2106 ssi3: ssi-3 {
2107 inter 2107 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
2108 dmas 2108 dmas = <&audma0 0x07>, <&audma1 0x08>;
2109 dma-n 2109 dma-names = "rx", "tx";
2110 }; 2110 };
2111 ssi4: ssi-4 { 2111 ssi4: ssi-4 {
2112 inter 2112 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
2113 dmas 2113 dmas = <&audma0 0x09>, <&audma1 0x0a>;
2114 dma-n 2114 dma-names = "rx", "tx";
2115 }; 2115 };
2116 ssi5: ssi-5 { 2116 ssi5: ssi-5 {
2117 inter 2117 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
2118 dmas 2118 dmas = <&audma0 0x0b>, <&audma1 0x0c>;
2119 dma-n 2119 dma-names = "rx", "tx";
2120 }; 2120 };
2121 ssi6: ssi-6 { 2121 ssi6: ssi-6 {
2122 inter 2122 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
2123 dmas 2123 dmas = <&audma0 0x0d>, <&audma1 0x0e>;
2124 dma-n 2124 dma-names = "rx", "tx";
2125 }; 2125 };
2126 ssi7: ssi-7 { 2126 ssi7: ssi-7 {
2127 inter 2127 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
2128 dmas 2128 dmas = <&audma0 0x0f>, <&audma1 0x10>;
2129 dma-n 2129 dma-names = "rx", "tx";
2130 }; 2130 };
2131 ssi8: ssi-8 { 2131 ssi8: ssi-8 {
2132 inter 2132 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
2133 dmas 2133 dmas = <&audma0 0x11>, <&audma1 0x12>;
2134 dma-n 2134 dma-names = "rx", "tx";
2135 }; 2135 };
2136 ssi9: ssi-9 { 2136 ssi9: ssi-9 {
2137 inter 2137 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
2138 dmas 2138 dmas = <&audma0 0x13>, <&audma1 0x14>;
2139 dma-n 2139 dma-names = "rx", "tx";
2140 }; 2140 };
2141 }; 2141 };
2142 }; 2142 };
2143 2143
2144 mlp: mlp@ec520000 { 2144 mlp: mlp@ec520000 {
2145 compatible = "renesas 2145 compatible = "renesas,r8a77965-mlp",
2146 "renesas 2146 "renesas,rcar-gen3-mlp";
2147 reg = <0 0xec520000 0 2147 reg = <0 0xec520000 0 0x800>;
2148 interrupts = <GIC_SPI 2148 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
2149 <GIC_SPI 385 2149 <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>;
2150 clocks = <&cpg CPG_MO 2150 clocks = <&cpg CPG_MOD 802>;
2151 power-domains = <&sys 2151 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
2152 resets = <&cpg 802>; 2152 resets = <&cpg 802>;
2153 status = "disabled"; 2153 status = "disabled";
2154 }; 2154 };
2155 2155
2156 audma0: dma-controller@ec7000 2156 audma0: dma-controller@ec700000 {
2157 compatible = "renesas 2157 compatible = "renesas,dmac-r8a77965",
2158 "renesas 2158 "renesas,rcar-dmac";
2159 reg = <0 0xec700000 0 2159 reg = <0 0xec700000 0 0x10000>;
2160 interrupts = <GIC_SPI 2160 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
2161 <GIC_SPI 2161 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
2162 <GIC_SPI 2162 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
2163 <GIC_SPI 2163 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
2164 <GIC_SPI 2164 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
2165 <GIC_SPI 2165 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
2166 <GIC_SPI 2166 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
2167 <GIC_SPI 2167 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
2168 <GIC_SPI 2168 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
2169 <GIC_SPI 2169 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
2170 <GIC_SPI 2170 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
2171 <GIC_SPI 2171 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
2172 <GIC_SPI 2172 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
2173 <GIC_SPI 2173 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
2174 <GIC_SPI 2174 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
2175 <GIC_SPI 2175 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
2176 <GIC_SPI 2176 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
2177 interrupt-names = "er 2177 interrupt-names = "error",
2178 "ch0" 2178 "ch0", "ch1", "ch2", "ch3",
2179 "ch4" 2179 "ch4", "ch5", "ch6", "ch7",
2180 "ch8" 2180 "ch8", "ch9", "ch10", "ch11",
2181 "ch12 2181 "ch12", "ch13", "ch14", "ch15";
2182 clocks = <&cpg CPG_MO 2182 clocks = <&cpg CPG_MOD 502>;
2183 clock-names = "fck"; 2183 clock-names = "fck";
2184 power-domains = <&sys 2184 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
2185 resets = <&cpg 502>; 2185 resets = <&cpg 502>;
2186 #dma-cells = <1>; 2186 #dma-cells = <1>;
2187 dma-channels = <16>; 2187 dma-channels = <16>;
2188 iommus = <&ipmmu_mp 0 <<
2189 <&ipmmu_mp 2 <<
2190 <&ipmmu_mp 4 <<
2191 <&ipmmu_mp 6 <<
2192 <&ipmmu_mp 8 <<
2193 <&ipmmu_mp 1 <<
2194 <&ipmmu_mp 1 <<
2195 <&ipmmu_mp 1 <<
2196 }; 2188 };
2197 2189
2198 audma1: dma-controller@ec7200 2190 audma1: dma-controller@ec720000 {
2199 compatible = "renesas 2191 compatible = "renesas,dmac-r8a77965",
2200 "renesas 2192 "renesas,rcar-dmac";
2201 reg = <0 0xec720000 0 2193 reg = <0 0xec720000 0 0x10000>;
2202 interrupts = <GIC_SPI 2194 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
2203 <GIC_SPI 2195 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
2204 <GIC_SPI 2196 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
2205 <GIC_SPI 2197 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
2206 <GIC_SPI 2198 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
2207 <GIC_SPI 2199 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
2208 <GIC_SPI 2200 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
2209 <GIC_SPI 2201 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
2210 <GIC_SPI 2202 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
2211 <GIC_SPI 2203 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
2212 <GIC_SPI 2204 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
2213 <GIC_SPI 2205 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
2214 <GIC_SPI 2206 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
2215 <GIC_SPI 2207 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
2216 <GIC_SPI 2208 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
2217 <GIC_SPI 2209 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
2218 <GIC_SPI 2210 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
2219 interrupt-names = "er 2211 interrupt-names = "error",
2220 "ch0" 2212 "ch0", "ch1", "ch2", "ch3",
2221 "ch4" 2213 "ch4", "ch5", "ch6", "ch7",
2222 "ch8" 2214 "ch8", "ch9", "ch10", "ch11",
2223 "ch12 2215 "ch12", "ch13", "ch14", "ch15";
2224 clocks = <&cpg CPG_MO 2216 clocks = <&cpg CPG_MOD 501>;
2225 clock-names = "fck"; 2217 clock-names = "fck";
2226 power-domains = <&sys 2218 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
2227 resets = <&cpg 501>; 2219 resets = <&cpg 501>;
2228 #dma-cells = <1>; 2220 #dma-cells = <1>;
2229 dma-channels = <16>; 2221 dma-channels = <16>;
2230 iommus = <&ipmmu_mp 1 <<
2231 <&ipmmu_mp 1 <<
2232 <&ipmmu_mp 2 <<
2233 <&ipmmu_mp 2 <<
2234 <&ipmmu_mp 2 <<
2235 <&ipmmu_mp 2 <<
2236 <&ipmmu_mp 2 <<
2237 <&ipmmu_mp 3 <<
2238 }; 2222 };
2239 2223
2240 xhci0: usb@ee000000 { 2224 xhci0: usb@ee000000 {
2241 compatible = "renesas 2225 compatible = "renesas,xhci-r8a77965",
2242 "renesas 2226 "renesas,rcar-gen3-xhci";
2243 reg = <0 0xee000000 0 2227 reg = <0 0xee000000 0 0xc00>;
2244 interrupts = <GIC_SPI 2228 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
2245 clocks = <&cpg CPG_MO 2229 clocks = <&cpg CPG_MOD 328>;
2246 power-domains = <&sys 2230 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
2247 resets = <&cpg 328>; 2231 resets = <&cpg 328>;
2248 status = "disabled"; 2232 status = "disabled";
2249 }; 2233 };
2250 2234
2251 usb3_peri0: usb@ee020000 { 2235 usb3_peri0: usb@ee020000 {
2252 compatible = "renesas 2236 compatible = "renesas,r8a77965-usb3-peri",
2253 "renesas 2237 "renesas,rcar-gen3-usb3-peri";
2254 reg = <0 0xee020000 0 2238 reg = <0 0xee020000 0 0x400>;
2255 interrupts = <GIC_SPI 2239 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
2256 clocks = <&cpg CPG_MO 2240 clocks = <&cpg CPG_MOD 328>;
2257 power-domains = <&sys 2241 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
2258 resets = <&cpg 328>; 2242 resets = <&cpg 328>;
2259 status = "disabled"; 2243 status = "disabled";
2260 }; 2244 };
2261 2245
2262 ohci0: usb@ee080000 { 2246 ohci0: usb@ee080000 {
2263 compatible = "generic 2247 compatible = "generic-ohci";
2264 reg = <0 0xee080000 0 2248 reg = <0 0xee080000 0 0x100>;
2265 interrupts = <GIC_SPI 2249 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
2266 clocks = <&cpg CPG_MO 2250 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
2267 phys = <&usb2_phy0 1> 2251 phys = <&usb2_phy0 1>;
2268 phy-names = "usb"; 2252 phy-names = "usb";
2269 power-domains = <&sys 2253 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
2270 resets = <&cpg 703>, 2254 resets = <&cpg 703>, <&cpg 704>;
2271 status = "disabled"; 2255 status = "disabled";
2272 }; 2256 };
2273 2257
2274 ohci1: usb@ee0a0000 { 2258 ohci1: usb@ee0a0000 {
2275 compatible = "generic 2259 compatible = "generic-ohci";
2276 reg = <0 0xee0a0000 0 2260 reg = <0 0xee0a0000 0 0x100>;
2277 interrupts = <GIC_SPI 2261 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
2278 clocks = <&cpg CPG_MO 2262 clocks = <&cpg CPG_MOD 702>;
2279 phys = <&usb2_phy1 1> 2263 phys = <&usb2_phy1 1>;
2280 phy-names = "usb"; 2264 phy-names = "usb";
2281 power-domains = <&sys 2265 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
2282 resets = <&cpg 702>; 2266 resets = <&cpg 702>;
2283 status = "disabled"; 2267 status = "disabled";
2284 }; 2268 };
2285 2269
2286 ehci0: usb@ee080100 { 2270 ehci0: usb@ee080100 {
2287 compatible = "generic 2271 compatible = "generic-ehci";
2288 reg = <0 0xee080100 0 2272 reg = <0 0xee080100 0 0x100>;
2289 interrupts = <GIC_SPI 2273 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
2290 clocks = <&cpg CPG_MO 2274 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
2291 phys = <&usb2_phy0 2> 2275 phys = <&usb2_phy0 2>;
2292 phy-names = "usb"; 2276 phy-names = "usb";
2293 companion = <&ohci0>; 2277 companion = <&ohci0>;
2294 power-domains = <&sys 2278 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
2295 resets = <&cpg 703>, 2279 resets = <&cpg 703>, <&cpg 704>;
2296 status = "disabled"; 2280 status = "disabled";
2297 }; 2281 };
2298 2282
2299 ehci1: usb@ee0a0100 { 2283 ehci1: usb@ee0a0100 {
2300 compatible = "generic 2284 compatible = "generic-ehci";
2301 reg = <0 0xee0a0100 0 2285 reg = <0 0xee0a0100 0 0x100>;
2302 interrupts = <GIC_SPI 2286 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
2303 clocks = <&cpg CPG_MO 2287 clocks = <&cpg CPG_MOD 702>;
2304 phys = <&usb2_phy1 2> 2288 phys = <&usb2_phy1 2>;
2305 phy-names = "usb"; 2289 phy-names = "usb";
2306 companion = <&ohci1>; 2290 companion = <&ohci1>;
2307 power-domains = <&sys 2291 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
2308 resets = <&cpg 702>; 2292 resets = <&cpg 702>;
2309 status = "disabled"; 2293 status = "disabled";
2310 }; 2294 };
2311 2295
2312 usb2_phy0: usb-phy@ee080200 { 2296 usb2_phy0: usb-phy@ee080200 {
2313 compatible = "renesas 2297 compatible = "renesas,usb2-phy-r8a77965",
2314 "renesas 2298 "renesas,rcar-gen3-usb2-phy";
2315 reg = <0 0xee080200 0 2299 reg = <0 0xee080200 0 0x700>;
2316 interrupts = <GIC_SPI 2300 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
2317 clocks = <&cpg CPG_MO 2301 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
2318 power-domains = <&sys 2302 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
2319 resets = <&cpg 703>, 2303 resets = <&cpg 703>, <&cpg 704>;
2320 #phy-cells = <1>; 2304 #phy-cells = <1>;
2321 status = "disabled"; 2305 status = "disabled";
2322 }; 2306 };
2323 2307
2324 usb2_phy1: usb-phy@ee0a0200 { 2308 usb2_phy1: usb-phy@ee0a0200 {
2325 compatible = "renesas 2309 compatible = "renesas,usb2-phy-r8a77965",
2326 "renesas 2310 "renesas,rcar-gen3-usb2-phy";
2327 reg = <0 0xee0a0200 0 2311 reg = <0 0xee0a0200 0 0x700>;
2328 clocks = <&cpg CPG_MO 2312 clocks = <&cpg CPG_MOD 702>;
2329 power-domains = <&sys 2313 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
2330 resets = <&cpg 702>; 2314 resets = <&cpg 702>;
2331 #phy-cells = <1>; 2315 #phy-cells = <1>;
2332 status = "disabled"; 2316 status = "disabled";
2333 }; 2317 };
2334 2318
2335 sdhi0: mmc@ee100000 { 2319 sdhi0: mmc@ee100000 {
2336 compatible = "renesas 2320 compatible = "renesas,sdhi-r8a77965",
2337 "renesas 2321 "renesas,rcar-gen3-sdhi";
2338 reg = <0 0xee100000 0 2322 reg = <0 0xee100000 0 0x2000>;
2339 interrupts = <GIC_SPI 2323 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
2340 clocks = <&cpg CPG_MO 2324 clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A77965_CLK_SD0H>;
2341 clock-names = "core", 2325 clock-names = "core", "clkh";
2342 max-frequency = <2000 2326 max-frequency = <200000000>;
2343 power-domains = <&sys 2327 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
2344 resets = <&cpg 314>; 2328 resets = <&cpg 314>;
2345 iommus = <&ipmmu_ds1 2329 iommus = <&ipmmu_ds1 32>;
2346 status = "disabled"; 2330 status = "disabled";
2347 }; 2331 };
2348 2332
2349 sdhi1: mmc@ee120000 { 2333 sdhi1: mmc@ee120000 {
2350 compatible = "renesas 2334 compatible = "renesas,sdhi-r8a77965",
2351 "renesas 2335 "renesas,rcar-gen3-sdhi";
2352 reg = <0 0xee120000 0 2336 reg = <0 0xee120000 0 0x2000>;
2353 interrupts = <GIC_SPI 2337 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
2354 clocks = <&cpg CPG_MO 2338 clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A77965_CLK_SD1H>;
2355 clock-names = "core", 2339 clock-names = "core", "clkh";
2356 max-frequency = <2000 2340 max-frequency = <200000000>;
2357 power-domains = <&sys 2341 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
2358 resets = <&cpg 313>; 2342 resets = <&cpg 313>;
2359 iommus = <&ipmmu_ds1 2343 iommus = <&ipmmu_ds1 33>;
2360 status = "disabled"; 2344 status = "disabled";
2361 }; 2345 };
2362 2346
2363 sdhi2: mmc@ee140000 { 2347 sdhi2: mmc@ee140000 {
2364 compatible = "renesas 2348 compatible = "renesas,sdhi-r8a77965",
2365 "renesas 2349 "renesas,rcar-gen3-sdhi";
2366 reg = <0 0xee140000 0 2350 reg = <0 0xee140000 0 0x2000>;
2367 interrupts = <GIC_SPI 2351 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
2368 clocks = <&cpg CPG_MO 2352 clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A77965_CLK_SD2H>;
2369 clock-names = "core", 2353 clock-names = "core", "clkh";
2370 max-frequency = <2000 2354 max-frequency = <200000000>;
2371 power-domains = <&sys 2355 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
2372 resets = <&cpg 312>; 2356 resets = <&cpg 312>;
2373 iommus = <&ipmmu_ds1 2357 iommus = <&ipmmu_ds1 34>;
2374 status = "disabled"; 2358 status = "disabled";
2375 }; 2359 };
2376 2360
2377 sdhi3: mmc@ee160000 { 2361 sdhi3: mmc@ee160000 {
2378 compatible = "renesas 2362 compatible = "renesas,sdhi-r8a77965",
2379 "renesas 2363 "renesas,rcar-gen3-sdhi";
2380 reg = <0 0xee160000 0 2364 reg = <0 0xee160000 0 0x2000>;
2381 interrupts = <GIC_SPI 2365 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
2382 clocks = <&cpg CPG_MO 2366 clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A77965_CLK_SD3H>;
2383 clock-names = "core", 2367 clock-names = "core", "clkh";
2384 max-frequency = <2000 2368 max-frequency = <200000000>;
2385 power-domains = <&sys 2369 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
2386 resets = <&cpg 311>; 2370 resets = <&cpg 311>;
2387 iommus = <&ipmmu_ds1 2371 iommus = <&ipmmu_ds1 35>;
2388 status = "disabled"; 2372 status = "disabled";
2389 }; 2373 };
2390 2374
2391 rpc: spi@ee200000 { 2375 rpc: spi@ee200000 {
2392 compatible = "renesas 2376 compatible = "renesas,r8a77965-rpc-if",
2393 "renesas 2377 "renesas,rcar-gen3-rpc-if";
2394 reg = <0 0xee200000 0 2378 reg = <0 0xee200000 0 0x200>,
2395 <0 0x08000000 0 2379 <0 0x08000000 0 0x04000000>,
2396 <0 0xee208000 0 2380 <0 0xee208000 0 0x100>;
2397 reg-names = "regs", " 2381 reg-names = "regs", "dirmap", "wbuf";
2398 interrupts = <GIC_SPI 2382 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
2399 clocks = <&cpg CPG_MO 2383 clocks = <&cpg CPG_MOD 917>;
2400 power-domains = <&sys 2384 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
2401 resets = <&cpg 917>; 2385 resets = <&cpg 917>;
2402 #address-cells = <1>; 2386 #address-cells = <1>;
2403 #size-cells = <0>; 2387 #size-cells = <0>;
2404 status = "disabled"; 2388 status = "disabled";
2405 }; 2389 };
2406 2390
2407 sata: sata@ee300000 { 2391 sata: sata@ee300000 {
2408 compatible = "renesas 2392 compatible = "renesas,sata-r8a77965",
2409 "renesas 2393 "renesas,rcar-gen3-sata";
2410 reg = <0 0xee300000 0 2394 reg = <0 0xee300000 0 0x200000>;
2411 interrupts = <GIC_SPI 2395 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
2412 clocks = <&cpg CPG_MO 2396 clocks = <&cpg CPG_MOD 815>;
2413 power-domains = <&sys 2397 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
2414 resets = <&cpg 815>; 2398 resets = <&cpg 815>;
2415 iommus = <&ipmmu_hc 2 <<
2416 status = "disabled"; 2399 status = "disabled";
2417 }; 2400 };
2418 2401
2419 gic: interrupt-controller@f10 2402 gic: interrupt-controller@f1010000 {
2420 compatible = "arm,gic 2403 compatible = "arm,gic-400";
2421 #interrupt-cells = <3 2404 #interrupt-cells = <3>;
2422 #address-cells = <0>; 2405 #address-cells = <0>;
2423 interrupt-controller; 2406 interrupt-controller;
2424 reg = <0x0 0xf1010000 2407 reg = <0x0 0xf1010000 0 0x1000>,
2425 <0x0 0xf1020000 2408 <0x0 0xf1020000 0 0x20000>,
2426 <0x0 0xf1040000 2409 <0x0 0xf1040000 0 0x20000>,
2427 <0x0 0xf1060000 2410 <0x0 0xf1060000 0 0x20000>;
2428 interrupts = <GIC_PPI 2411 interrupts = <GIC_PPI 9
2429 (GIC_ 2412 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
2430 clocks = <&cpg CPG_MO 2413 clocks = <&cpg CPG_MOD 408>;
2431 clock-names = "clk"; 2414 clock-names = "clk";
2432 power-domains = <&sys 2415 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
2433 resets = <&cpg 408>; 2416 resets = <&cpg 408>;
2434 }; 2417 };
2435 2418
2436 pciec0: pcie@fe000000 { 2419 pciec0: pcie@fe000000 {
2437 compatible = "renesas 2420 compatible = "renesas,pcie-r8a77965",
2438 "renesas 2421 "renesas,pcie-rcar-gen3";
2439 reg = <0 0xfe000000 0 2422 reg = <0 0xfe000000 0 0x80000>;
2440 #address-cells = <3>; 2423 #address-cells = <3>;
2441 #size-cells = <2>; 2424 #size-cells = <2>;
2442 bus-range = <0x00 0xf 2425 bus-range = <0x00 0xff>;
2443 device_type = "pci"; 2426 device_type = "pci";
2444 ranges = <0x01000000 2427 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
2445 <0x02000000 2428 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
2446 <0x02000000 2429 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
2447 <0x42000000 2430 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
2448 /* Map all possible D 2431 /* Map all possible DDR/IOMMU as inbound ranges */
2449 dma-ranges = <0x42000 2432 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
2450 interrupts = <GIC_SPI 2433 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
2451 <GIC_SPI 117 2434 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
2452 <GIC_SPI 118 2435 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
2453 #interrupt-cells = <1 2436 #interrupt-cells = <1>;
2454 interrupt-map-mask = 2437 interrupt-map-mask = <0 0 0 0>;
2455 interrupt-map = <0 0 2438 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
2456 clocks = <&cpg CPG_MO 2439 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
2457 clock-names = "pcie", 2440 clock-names = "pcie", "pcie_bus";
2458 power-domains = <&sys 2441 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
2459 resets = <&cpg 319>; 2442 resets = <&cpg 319>;
2460 iommu-map = <0 &ipmmu 2443 iommu-map = <0 &ipmmu_hc 0 1>;
2461 iommu-map-mask = <0>; 2444 iommu-map-mask = <0>;
2462 status = "disabled"; 2445 status = "disabled";
2463 }; 2446 };
2464 2447
2465 pciec1: pcie@ee800000 { 2448 pciec1: pcie@ee800000 {
2466 compatible = "renesas 2449 compatible = "renesas,pcie-r8a77965",
2467 "renesas 2450 "renesas,pcie-rcar-gen3";
2468 reg = <0 0xee800000 0 2451 reg = <0 0xee800000 0 0x80000>;
2469 #address-cells = <3>; 2452 #address-cells = <3>;
2470 #size-cells = <2>; 2453 #size-cells = <2>;
2471 bus-range = <0x00 0xf 2454 bus-range = <0x00 0xff>;
2472 device_type = "pci"; 2455 device_type = "pci";
2473 ranges = <0x01000000 2456 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
2474 <0x02000000 2457 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
2475 <0x02000000 2458 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
2476 <0x42000000 2459 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
2477 /* Map all possible D 2460 /* Map all possible DDR/IOMMU as inbound ranges */
2478 dma-ranges = <0x42000 2461 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
2479 interrupts = <GIC_SPI 2462 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
2480 <GIC_SPI 149 2463 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
2481 <GIC_SPI 150 2464 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
2482 #interrupt-cells = <1 2465 #interrupt-cells = <1>;
2483 interrupt-map-mask = 2466 interrupt-map-mask = <0 0 0 0>;
2484 interrupt-map = <0 0 2467 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2485 clocks = <&cpg CPG_MO 2468 clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>;
2486 clock-names = "pcie", 2469 clock-names = "pcie", "pcie_bus";
2487 power-domains = <&sys 2470 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
2488 resets = <&cpg 318>; 2471 resets = <&cpg 318>;
2489 iommu-map = <0 &ipmmu 2472 iommu-map = <0 &ipmmu_hc 1 1>;
2490 iommu-map-mask = <0>; 2473 iommu-map-mask = <0>;
2491 status = "disabled"; 2474 status = "disabled";
2492 }; 2475 };
2493 2476
2494 fdp1@fe940000 { 2477 fdp1@fe940000 {
2495 compatible = "renesas 2478 compatible = "renesas,fdp1";
2496 reg = <0 0xfe940000 0 2479 reg = <0 0xfe940000 0 0x2400>;
2497 interrupts = <GIC_SPI 2480 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
2498 clocks = <&cpg CPG_MO 2481 clocks = <&cpg CPG_MOD 119>;
2499 power-domains = <&sys 2482 power-domains = <&sysc R8A77965_PD_A3VP>;
2500 resets = <&cpg 119>; 2483 resets = <&cpg 119>;
2501 renesas,fcp = <&fcpf0 2484 renesas,fcp = <&fcpf0>;
2502 }; 2485 };
2503 2486
2504 fcpf0: fcp@fe950000 { 2487 fcpf0: fcp@fe950000 {
2505 compatible = "renesas 2488 compatible = "renesas,fcpf";
2506 reg = <0 0xfe950000 0 2489 reg = <0 0xfe950000 0 0x200>;
2507 clocks = <&cpg CPG_MO 2490 clocks = <&cpg CPG_MOD 615>;
2508 power-domains = <&sys 2491 power-domains = <&sysc R8A77965_PD_A3VP>;
2509 resets = <&cpg 615>; 2492 resets = <&cpg 615>;
2510 iommus = <&ipmmu_vp0 <<
2511 }; 2493 };
2512 2494
2513 vspb: vsp@fe960000 { 2495 vspb: vsp@fe960000 {
2514 compatible = "renesas 2496 compatible = "renesas,vsp2";
2515 reg = <0 0xfe960000 0 2497 reg = <0 0xfe960000 0 0x8000>;
2516 interrupts = <GIC_SPI 2498 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
2517 clocks = <&cpg CPG_MO 2499 clocks = <&cpg CPG_MOD 626>;
2518 power-domains = <&sys 2500 power-domains = <&sysc R8A77965_PD_A3VP>;
2519 resets = <&cpg 626>; 2501 resets = <&cpg 626>;
2520 2502
2521 renesas,fcp = <&fcpvb 2503 renesas,fcp = <&fcpvb0>;
2522 }; 2504 };
2523 2505
2524 vspi0: vsp@fe9a0000 { 2506 vspi0: vsp@fe9a0000 {
2525 compatible = "renesas 2507 compatible = "renesas,vsp2";
2526 reg = <0 0xfe9a0000 0 2508 reg = <0 0xfe9a0000 0 0x8000>;
2527 interrupts = <GIC_SPI 2509 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
2528 clocks = <&cpg CPG_MO 2510 clocks = <&cpg CPG_MOD 631>;
2529 power-domains = <&sys 2511 power-domains = <&sysc R8A77965_PD_A3VP>;
2530 resets = <&cpg 631>; 2512 resets = <&cpg 631>;
2531 2513
2532 renesas,fcp = <&fcpvi 2514 renesas,fcp = <&fcpvi0>;
2533 }; 2515 };
2534 2516
2535 vspd0: vsp@fea20000 { 2517 vspd0: vsp@fea20000 {
2536 compatible = "renesas 2518 compatible = "renesas,vsp2";
2537 reg = <0 0xfea20000 0 2519 reg = <0 0xfea20000 0 0x5000>;
2538 interrupts = <GIC_SPI 2520 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
2539 clocks = <&cpg CPG_MO 2521 clocks = <&cpg CPG_MOD 623>;
2540 power-domains = <&sys 2522 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
2541 resets = <&cpg 623>; 2523 resets = <&cpg 623>;
2542 2524
2543 renesas,fcp = <&fcpvd 2525 renesas,fcp = <&fcpvd0>;
2544 }; 2526 };
2545 2527
2546 vspd1: vsp@fea28000 { 2528 vspd1: vsp@fea28000 {
2547 compatible = "renesas 2529 compatible = "renesas,vsp2";
2548 reg = <0 0xfea28000 0 2530 reg = <0 0xfea28000 0 0x5000>;
2549 interrupts = <GIC_SPI 2531 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
2550 clocks = <&cpg CPG_MO 2532 clocks = <&cpg CPG_MOD 622>;
2551 power-domains = <&sys 2533 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
2552 resets = <&cpg 622>; 2534 resets = <&cpg 622>;
2553 2535
2554 renesas,fcp = <&fcpvd 2536 renesas,fcp = <&fcpvd1>;
2555 }; 2537 };
2556 2538
2557 fcpvb0: fcp@fe96f000 { 2539 fcpvb0: fcp@fe96f000 {
2558 compatible = "renesas 2540 compatible = "renesas,fcpv";
2559 reg = <0 0xfe96f000 0 2541 reg = <0 0xfe96f000 0 0x200>;
2560 clocks = <&cpg CPG_MO 2542 clocks = <&cpg CPG_MOD 607>;
2561 power-domains = <&sys 2543 power-domains = <&sysc R8A77965_PD_A3VP>;
2562 resets = <&cpg 607>; 2544 resets = <&cpg 607>;
2563 iommus = <&ipmmu_vp0 <<
2564 }; 2545 };
2565 2546
2566 fcpvd0: fcp@fea27000 { 2547 fcpvd0: fcp@fea27000 {
2567 compatible = "renesas 2548 compatible = "renesas,fcpv";
2568 reg = <0 0xfea27000 0 2549 reg = <0 0xfea27000 0 0x200>;
2569 clocks = <&cpg CPG_MO 2550 clocks = <&cpg CPG_MOD 603>;
2570 power-domains = <&sys 2551 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
2571 resets = <&cpg 603>; 2552 resets = <&cpg 603>;
2572 iommus = <&ipmmu_vi0 <<
2573 }; 2553 };
2574 2554
2575 fcpvd1: fcp@fea2f000 { 2555 fcpvd1: fcp@fea2f000 {
2576 compatible = "renesas 2556 compatible = "renesas,fcpv";
2577 reg = <0 0xfea2f000 0 2557 reg = <0 0xfea2f000 0 0x200>;
2578 clocks = <&cpg CPG_MO 2558 clocks = <&cpg CPG_MOD 602>;
2579 power-domains = <&sys 2559 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
2580 resets = <&cpg 602>; 2560 resets = <&cpg 602>;
2581 iommus = <&ipmmu_vi0 <<
2582 }; 2561 };
2583 2562
2584 fcpvi0: fcp@fe9af000 { 2563 fcpvi0: fcp@fe9af000 {
2585 compatible = "renesas 2564 compatible = "renesas,fcpv";
2586 reg = <0 0xfe9af000 0 2565 reg = <0 0xfe9af000 0 0x200>;
2587 clocks = <&cpg CPG_MO 2566 clocks = <&cpg CPG_MOD 611>;
2588 power-domains = <&sys 2567 power-domains = <&sysc R8A77965_PD_A3VP>;
2589 resets = <&cpg 611>; 2568 resets = <&cpg 611>;
2590 iommus = <&ipmmu_vp0 <<
2591 }; 2569 };
2592 2570
2593 cmm0: cmm@fea40000 { 2571 cmm0: cmm@fea40000 {
2594 compatible = "renesas 2572 compatible = "renesas,r8a77965-cmm",
2595 "renesas 2573 "renesas,rcar-gen3-cmm";
2596 reg = <0 0xfea40000 0 2574 reg = <0 0xfea40000 0 0x1000>;
2597 power-domains = <&sys 2575 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
2598 clocks = <&cpg CPG_MO 2576 clocks = <&cpg CPG_MOD 711>;
2599 resets = <&cpg 711>; 2577 resets = <&cpg 711>;
2600 }; 2578 };
2601 2579
2602 cmm1: cmm@fea50000 { 2580 cmm1: cmm@fea50000 {
2603 compatible = "renesas 2581 compatible = "renesas,r8a77965-cmm",
2604 "renesas 2582 "renesas,rcar-gen3-cmm";
2605 reg = <0 0xfea50000 0 2583 reg = <0 0xfea50000 0 0x1000>;
2606 power-domains = <&sys 2584 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
2607 clocks = <&cpg CPG_MO 2585 clocks = <&cpg CPG_MOD 710>;
2608 resets = <&cpg 710>; 2586 resets = <&cpg 710>;
2609 }; 2587 };
2610 2588
2611 cmm3: cmm@fea70000 { 2589 cmm3: cmm@fea70000 {
2612 compatible = "renesas 2590 compatible = "renesas,r8a77965-cmm",
2613 "renesas 2591 "renesas,rcar-gen3-cmm";
2614 reg = <0 0xfea70000 0 2592 reg = <0 0xfea70000 0 0x1000>;
2615 power-domains = <&sys 2593 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
2616 clocks = <&cpg CPG_MO 2594 clocks = <&cpg CPG_MOD 708>;
2617 resets = <&cpg 708>; 2595 resets = <&cpg 708>;
2618 }; 2596 };
2619 2597
2620 csi20: csi2@fea80000 { 2598 csi20: csi2@fea80000 {
2621 compatible = "renesas 2599 compatible = "renesas,r8a77965-csi2";
2622 reg = <0 0xfea80000 0 2600 reg = <0 0xfea80000 0 0x10000>;
2623 interrupts = <GIC_SPI 2601 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
2624 clocks = <&cpg CPG_MO 2602 clocks = <&cpg CPG_MOD 714>;
2625 power-domains = <&sys 2603 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
2626 resets = <&cpg 714>; 2604 resets = <&cpg 714>;
2627 status = "disabled"; 2605 status = "disabled";
2628 2606
2629 ports { 2607 ports {
2630 #address-cell 2608 #address-cells = <1>;
2631 #size-cells = 2609 #size-cells = <0>;
2632 2610
2633 port@0 { 2611 port@0 {
2634 reg = 2612 reg = <0>;
2635 }; 2613 };
2636 2614
2637 port@1 { 2615 port@1 {
2638 #addr 2616 #address-cells = <1>;
2639 #size 2617 #size-cells = <0>;
2640 2618
2641 reg = 2619 reg = <1>;
2642 2620
2643 csi20 2621 csi20vin0: endpoint@0 {
2644 2622 reg = <0>;
2645 2623 remote-endpoint = <&vin0csi20>;
2646 }; 2624 };
2647 csi20 2625 csi20vin1: endpoint@1 {
2648 2626 reg = <1>;
2649 2627 remote-endpoint = <&vin1csi20>;
2650 }; 2628 };
2651 csi20 2629 csi20vin2: endpoint@2 {
2652 2630 reg = <2>;
2653 2631 remote-endpoint = <&vin2csi20>;
2654 }; 2632 };
2655 csi20 2633 csi20vin3: endpoint@3 {
2656 2634 reg = <3>;
2657 2635 remote-endpoint = <&vin3csi20>;
2658 }; 2636 };
2659 csi20 2637 csi20vin4: endpoint@4 {
2660 2638 reg = <4>;
2661 2639 remote-endpoint = <&vin4csi20>;
2662 }; 2640 };
2663 csi20 2641 csi20vin5: endpoint@5 {
2664 2642 reg = <5>;
2665 2643 remote-endpoint = <&vin5csi20>;
2666 }; 2644 };
2667 csi20 2645 csi20vin6: endpoint@6 {
2668 2646 reg = <6>;
2669 2647 remote-endpoint = <&vin6csi20>;
2670 }; 2648 };
2671 csi20 2649 csi20vin7: endpoint@7 {
2672 2650 reg = <7>;
2673 2651 remote-endpoint = <&vin7csi20>;
2674 }; 2652 };
2675 }; 2653 };
2676 }; 2654 };
2677 }; 2655 };
2678 2656
2679 csi40: csi2@feaa0000 { 2657 csi40: csi2@feaa0000 {
2680 compatible = "renesas 2658 compatible = "renesas,r8a77965-csi2";
2681 reg = <0 0xfeaa0000 0 2659 reg = <0 0xfeaa0000 0 0x10000>;
2682 interrupts = <GIC_SPI 2660 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
2683 clocks = <&cpg CPG_MO 2661 clocks = <&cpg CPG_MOD 716>;
2684 power-domains = <&sys 2662 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
2685 resets = <&cpg 716>; 2663 resets = <&cpg 716>;
2686 status = "disabled"; 2664 status = "disabled";
2687 2665
2688 ports { 2666 ports {
2689 #address-cell 2667 #address-cells = <1>;
2690 #size-cells = 2668 #size-cells = <0>;
2691 2669
2692 port@0 { 2670 port@0 {
2693 reg = 2671 reg = <0>;
2694 }; 2672 };
2695 2673
2696 port@1 { 2674 port@1 {
2697 #addr 2675 #address-cells = <1>;
2698 #size 2676 #size-cells = <0>;
2699 2677
2700 reg = 2678 reg = <1>;
2701 2679
2702 csi40 2680 csi40vin0: endpoint@0 {
2703 2681 reg = <0>;
2704 2682 remote-endpoint = <&vin0csi40>;
2705 }; 2683 };
2706 csi40 2684 csi40vin1: endpoint@1 {
2707 2685 reg = <1>;
2708 2686 remote-endpoint = <&vin1csi40>;
2709 }; 2687 };
2710 csi40 2688 csi40vin2: endpoint@2 {
2711 2689 reg = <2>;
2712 2690 remote-endpoint = <&vin2csi40>;
2713 }; 2691 };
2714 csi40 2692 csi40vin3: endpoint@3 {
2715 2693 reg = <3>;
2716 2694 remote-endpoint = <&vin3csi40>;
2717 }; 2695 };
2718 csi40 2696 csi40vin4: endpoint@4 {
2719 2697 reg = <4>;
2720 2698 remote-endpoint = <&vin4csi40>;
2721 }; 2699 };
2722 csi40 2700 csi40vin5: endpoint@5 {
2723 2701 reg = <5>;
2724 2702 remote-endpoint = <&vin5csi40>;
2725 }; 2703 };
2726 csi40 2704 csi40vin6: endpoint@6 {
2727 2705 reg = <6>;
2728 2706 remote-endpoint = <&vin6csi40>;
2729 }; 2707 };
2730 csi40 2708 csi40vin7: endpoint@7 {
2731 2709 reg = <7>;
2732 2710 remote-endpoint = <&vin7csi40>;
2733 }; 2711 };
2734 }; 2712 };
2735 }; 2713 };
2736 }; 2714 };
2737 2715
2738 hdmi0: hdmi@fead0000 { 2716 hdmi0: hdmi@fead0000 {
2739 compatible = "renesas 2717 compatible = "renesas,r8a77965-hdmi",
2740 "renesas 2718 "renesas,rcar-gen3-hdmi";
2741 reg = <0 0xfead0000 0 2719 reg = <0 0xfead0000 0 0x10000>;
2742 interrupts = <GIC_SPI 2720 interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
2743 clocks = <&cpg CPG_MO 2721 clocks = <&cpg CPG_MOD 729>,
2744 <&cpg CPG_CO 2722 <&cpg CPG_CORE R8A77965_CLK_HDMI>;
2745 clock-names = "iahb", 2723 clock-names = "iahb", "isfr";
2746 power-domains = <&sys 2724 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
2747 resets = <&cpg 729>; 2725 resets = <&cpg 729>;
2748 status = "disabled"; 2726 status = "disabled";
2749 2727
2750 ports { 2728 ports {
2751 #address-cell 2729 #address-cells = <1>;
2752 #size-cells = 2730 #size-cells = <0>;
2753 port@0 { 2731 port@0 {
2754 reg = 2732 reg = <0>;
2755 dw_hd 2733 dw_hdmi0_in: endpoint {
2756 2734 remote-endpoint = <&du_out_hdmi0>;
2757 }; 2735 };
2758 }; 2736 };
2759 port@1 { 2737 port@1 {
2760 reg = 2738 reg = <1>;
2761 }; 2739 };
2762 }; 2740 };
2763 }; 2741 };
2764 2742
2765 du: display@feb00000 { 2743 du: display@feb00000 {
2766 compatible = "renesas 2744 compatible = "renesas,du-r8a77965";
2767 reg = <0 0xfeb00000 0 2745 reg = <0 0xfeb00000 0 0x80000>;
2768 interrupts = <GIC_SPI 2746 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
2769 <GIC_SPI 2747 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
2770 <GIC_SPI 2748 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
2771 clocks = <&cpg CPG_MO 2749 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
2772 <&cpg CPG_MO 2750 <&cpg CPG_MOD 721>;
2773 clock-names = "du.0", 2751 clock-names = "du.0", "du.1", "du.3";
2774 resets = <&cpg 724>, 2752 resets = <&cpg 724>, <&cpg 722>;
2775 reset-names = "du.0", 2753 reset-names = "du.0", "du.3";
2776 2754
2777 renesas,cmms = <&cmm0 2755 renesas,cmms = <&cmm0>, <&cmm1>, <&cmm3>;
2778 renesas,vsps = <&vspd 2756 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>;
2779 2757
2780 status = "disabled"; 2758 status = "disabled";
2781 2759
2782 ports { 2760 ports {
2783 #address-cell 2761 #address-cells = <1>;
2784 #size-cells = 2762 #size-cells = <0>;
2785 2763
2786 port@0 { 2764 port@0 {
2787 reg = 2765 reg = <0>;
2788 }; 2766 };
2789 port@1 { 2767 port@1 {
2790 reg = 2768 reg = <1>;
2791 du_ou 2769 du_out_hdmi0: endpoint {
2792 2770 remote-endpoint = <&dw_hdmi0_in>;
2793 }; 2771 };
2794 }; 2772 };
2795 port@2 { 2773 port@2 {
2796 reg = 2774 reg = <2>;
2797 du_ou 2775 du_out_lvds0: endpoint {
2798 2776 remote-endpoint = <&lvds0_in>;
2799 }; 2777 };
2800 }; 2778 };
2801 }; 2779 };
2802 }; 2780 };
2803 2781
2804 lvds0: lvds@feb90000 { 2782 lvds0: lvds@feb90000 {
2805 compatible = "renesas 2783 compatible = "renesas,r8a77965-lvds";
2806 reg = <0 0xfeb90000 0 2784 reg = <0 0xfeb90000 0 0x14>;
2807 clocks = <&cpg CPG_MO 2785 clocks = <&cpg CPG_MOD 727>;
2808 power-domains = <&sys 2786 power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
2809 resets = <&cpg 727>; 2787 resets = <&cpg 727>;
2810 status = "disabled"; 2788 status = "disabled";
2811 2789
2812 ports { 2790 ports {
2813 #address-cell 2791 #address-cells = <1>;
2814 #size-cells = 2792 #size-cells = <0>;
2815 2793
2816 port@0 { 2794 port@0 {
2817 reg = 2795 reg = <0>;
2818 lvds0 2796 lvds0_in: endpoint {
2819 2797 remote-endpoint = <&du_out_lvds0>;
2820 }; 2798 };
2821 }; 2799 };
2822 port@1 { 2800 port@1 {
2823 reg = 2801 reg = <1>;
2824 }; 2802 };
2825 }; 2803 };
2826 }; 2804 };
2827 2805
2828 prr: chipid@fff00044 { 2806 prr: chipid@fff00044 {
2829 compatible = "renesas 2807 compatible = "renesas,prr";
2830 reg = <0 0xfff00044 0 2808 reg = <0 0xfff00044 0 4>;
2831 }; 2809 };
2832 }; 2810 };
2833 2811
2834 thermal-zones { 2812 thermal-zones {
2835 sensor1_thermal: sensor1-ther 2813 sensor1_thermal: sensor1-thermal {
2836 polling-delay-passive 2814 polling-delay-passive = <250>;
2837 polling-delay = <1000 2815 polling-delay = <1000>;
2838 thermal-sensors = <&t 2816 thermal-sensors = <&tsc 0>;
2839 sustainable-power = < 2817 sustainable-power = <2439>;
2840 2818
2841 trips { 2819 trips {
2842 sensor1_crit: 2820 sensor1_crit: sensor1-crit {
2843 tempe 2821 temperature = <120000>;
2844 hyste 2822 hysteresis = <1000>;
2845 type 2823 type = "critical";
2846 }; 2824 };
2847 }; 2825 };
2848 }; 2826 };
2849 2827
2850 sensor2_thermal: sensor2-ther 2828 sensor2_thermal: sensor2-thermal {
2851 polling-delay-passive 2829 polling-delay-passive = <250>;
2852 polling-delay = <1000 2830 polling-delay = <1000>;
2853 thermal-sensors = <&t 2831 thermal-sensors = <&tsc 1>;
2854 sustainable-power = < 2832 sustainable-power = <2439>;
2855 2833
2856 trips { 2834 trips {
2857 sensor2_crit: 2835 sensor2_crit: sensor2-crit {
2858 tempe 2836 temperature = <120000>;
2859 hyste 2837 hysteresis = <1000>;
2860 type 2838 type = "critical";
2861 }; 2839 };
2862 }; 2840 };
2863 }; 2841 };
2864 2842
2865 sensor3_thermal: sensor3-ther 2843 sensor3_thermal: sensor3-thermal {
2866 polling-delay-passive 2844 polling-delay-passive = <250>;
2867 polling-delay = <1000 2845 polling-delay = <1000>;
2868 thermal-sensors = <&t 2846 thermal-sensors = <&tsc 2>;
2869 sustainable-power = < 2847 sustainable-power = <2439>;
2870 2848
2871 trips { 2849 trips {
2872 target: trip- 2850 target: trip-point1 {
2873 /* mi 2851 /* miliCelsius */
2874 tempe 2852 temperature = <100000>;
2875 hyste 2853 hysteresis = <1000>;
2876 type 2854 type = "passive";
2877 }; 2855 };
2878 2856
2879 sensor3_crit: 2857 sensor3_crit: sensor3-crit {
2880 tempe 2858 temperature = <120000>;
2881 hyste 2859 hysteresis = <1000>;
2882 type 2860 type = "critical";
2883 }; 2861 };
2884 }; 2862 };
2885 2863
2886 cooling-maps { 2864 cooling-maps {
2887 map0 { 2865 map0 {
2888 trip 2866 trip = <&target>;
2889 cooli 2867 cooling-device = <&a57_0 2 4>;
2890 contr 2868 contribution = <1024>;
2891 }; 2869 };
2892 }; 2870 };
2893 }; 2871 };
2894 }; 2872 };
2895 2873
2896 timer { 2874 timer {
2897 compatible = "arm,armv8-timer 2875 compatible = "arm,armv8-timer";
2898 interrupts-extended = <&gic G 2876 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
2899 <&gic G 2877 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
2900 <&gic G 2878 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
2901 <&gic G 2879 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
2902 interrupt-names = "sec-phys", 2880 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys";
2903 }; 2881 };
2904 2882
2905 /* External USB clocks - can be overr 2883 /* External USB clocks - can be overridden by the board */
2906 usb3s0_clk: usb3s0 { 2884 usb3s0_clk: usb3s0 {
2907 compatible = "fixed-clock"; 2885 compatible = "fixed-clock";
2908 #clock-cells = <0>; 2886 #clock-cells = <0>;
2909 clock-frequency = <0>; 2887 clock-frequency = <0>;
2910 }; 2888 };
2911 2889
2912 usb_extal_clk: usb_extal { 2890 usb_extal_clk: usb_extal {
2913 compatible = "fixed-clock"; 2891 compatible = "fixed-clock";
2914 #clock-cells = <0>; 2892 #clock-cells = <0>;
2915 clock-frequency = <0>; 2893 clock-frequency = <0>;
2916 }; 2894 };
2917 }; 2895 };
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