1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * Device Tree Source for the V3M Starter Kit 3 * Device Tree Source for the V3M Starter Kit board
4 * 4 *
5 * Copyright (C) 2017 Renesas Electronics Corp 5 * Copyright (C) 2017 Renesas Electronics Corp.
6 * Copyright (C) 2017 Cogent Embedded, Inc. 6 * Copyright (C) 2017 Cogent Embedded, Inc.
7 */ 7 */
8 8
9 /dts-v1/; 9 /dts-v1/;
10 #include "r8a77970.dtsi" 10 #include "r8a77970.dtsi"
11 #include <dt-bindings/gpio/gpio.h> <<
12 11
13 / { 12 / {
14 model = "Renesas V3M Starter Kit board 13 model = "Renesas V3M Starter Kit board";
15 compatible = "renesas,v3msk", "renesas 14 compatible = "renesas,v3msk", "renesas,r8a77970";
16 15
17 aliases { 16 aliases {
18 i2c0 = &i2c0; <<
19 i2c1 = &i2c1; <<
20 i2c2 = &i2c2; <<
21 i2c3 = &i2c3; <<
22 i2c4 = &i2c4; <<
23 serial0 = &scif0; 17 serial0 = &scif0;
24 }; 18 };
25 19
26 chosen { 20 chosen {
27 stdout-path = "serial0:115200n 21 stdout-path = "serial0:115200n8";
28 }; 22 };
29 23
30 hdmi-out { 24 hdmi-out {
31 compatible = "hdmi-connector"; 25 compatible = "hdmi-connector";
32 type = "a"; 26 type = "a";
33 27
34 port { 28 port {
35 hdmi_con: endpoint { 29 hdmi_con: endpoint {
36 remote-endpoin 30 remote-endpoint = <&adv7511_out>;
37 }; 31 };
38 }; 32 };
39 }; 33 };
40 34
41 lvds-decoder { 35 lvds-decoder {
42 compatible = "thine,thc63lvd10 36 compatible = "thine,thc63lvd1024";
43 vcc-supply = <&vcc_d3_3v>; 37 vcc-supply = <&vcc_d3_3v>;
44 38
45 ports { 39 ports {
46 #address-cells = <1>; 40 #address-cells = <1>;
47 #size-cells = <0>; 41 #size-cells = <0>;
48 42
49 port@0 { 43 port@0 {
50 reg = <0>; 44 reg = <0>;
51 thc63lvd1024_i 45 thc63lvd1024_in: endpoint {
52 remote 46 remote-endpoint = <&lvds0_out>;
53 }; 47 };
54 }; 48 };
55 49
56 port@2 { 50 port@2 {
57 reg = <2>; 51 reg = <2>;
58 thc63lvd1024_o 52 thc63lvd1024_out: endpoint {
59 remote 53 remote-endpoint = <&adv7511_in>;
60 }; 54 };
61 }; 55 };
62 }; 56 };
63 }; 57 };
64 58
65 memory@48000000 { 59 memory@48000000 {
66 device_type = "memory"; 60 device_type = "memory";
67 /* first 128MB is reserved for 61 /* first 128MB is reserved for secure area. */
68 reg = <0x0 0x48000000 0x0 0x78 62 reg = <0x0 0x48000000 0x0 0x78000000>;
69 }; 63 };
70 64
71 osc5_clk: osc5-clock { 65 osc5_clk: osc5-clock {
72 compatible = "fixed-clock"; 66 compatible = "fixed-clock";
73 #clock-cells = <0>; 67 #clock-cells = <0>;
74 clock-frequency = <148500000>; 68 clock-frequency = <148500000>;
75 }; 69 };
76 70
77 vcc_d1_8v: regulator-0 { 71 vcc_d1_8v: regulator-0 {
78 compatible = "regulator-fixed" 72 compatible = "regulator-fixed";
79 regulator-name = "VCC_D1.8V"; 73 regulator-name = "VCC_D1.8V";
80 regulator-min-microvolt = <180 74 regulator-min-microvolt = <1800000>;
81 regulator-max-microvolt = <180 75 regulator-max-microvolt = <1800000>;
82 regulator-boot-on; 76 regulator-boot-on;
83 regulator-always-on; 77 regulator-always-on;
84 }; 78 };
85 79
86 vcc_d3_3v: regulator-1 { 80 vcc_d3_3v: regulator-1 {
87 compatible = "regulator-fixed" 81 compatible = "regulator-fixed";
88 regulator-name = "VCC_D3.3V"; 82 regulator-name = "VCC_D3.3V";
89 regulator-min-microvolt = <330 83 regulator-min-microvolt = <3300000>;
90 regulator-max-microvolt = <330 84 regulator-max-microvolt = <3300000>;
91 regulator-boot-on; 85 regulator-boot-on;
92 regulator-always-on; 86 regulator-always-on;
93 }; 87 };
94 88
95 vcc_vddq_vin0: regulator-2 { 89 vcc_vddq_vin0: regulator-2 {
96 compatible = "regulator-fixed" 90 compatible = "regulator-fixed";
97 regulator-name = "VCC_VDDQ_VIN 91 regulator-name = "VCC_VDDQ_VIN0";
98 regulator-min-microvolt = <330 92 regulator-min-microvolt = <3300000>;
99 regulator-max-microvolt = <330 93 regulator-max-microvolt = <3300000>;
100 regulator-boot-on; 94 regulator-boot-on;
101 regulator-always-on; 95 regulator-always-on;
102 }; 96 };
103 }; 97 };
104 98
105 &avb { 99 &avb {
106 pinctrl-0 = <&avb_pins>; 100 pinctrl-0 = <&avb_pins>;
107 pinctrl-names = "default"; 101 pinctrl-names = "default";
108 102
109 renesas,no-ether-link; 103 renesas,no-ether-link;
110 phy-handle = <&phy0>; 104 phy-handle = <&phy0>;
111 rx-internal-delay-ps = <1800>; 105 rx-internal-delay-ps = <1800>;
112 tx-internal-delay-ps = <2000>; 106 tx-internal-delay-ps = <2000>;
113 status = "okay"; 107 status = "okay";
114 108
115 phy0: ethernet-phy@0 { 109 phy0: ethernet-phy@0 {
116 compatible = "ethernet-phy-id0 <<
117 "ethernet-phy-iee <<
118 rxc-skew-ps = <1500>; 110 rxc-skew-ps = <1500>;
119 reg = <0>; 111 reg = <0>;
120 interrupt-parent = <&gpio1>; 112 interrupt-parent = <&gpio1>;
121 interrupts = <17 IRQ_TYPE_LEVE 113 interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
122 reset-gpios = <&gpio1 16 GPIO_ <<
123 }; 114 };
124 }; 115 };
125 116
126 &du { 117 &du {
127 clocks = <&cpg CPG_MOD 724>, 118 clocks = <&cpg CPG_MOD 724>,
128 <&osc5_clk>; 119 <&osc5_clk>;
129 clock-names = "du.0", "dclkin.0"; 120 clock-names = "du.0", "dclkin.0";
130 status = "okay"; 121 status = "okay";
131 }; 122 };
132 123
133 &extal_clk { 124 &extal_clk {
134 clock-frequency = <16666666>; 125 clock-frequency = <16666666>;
135 }; 126 };
136 127
137 &extalr_clk { 128 &extalr_clk {
138 clock-frequency = <32768>; 129 clock-frequency = <32768>;
139 }; 130 };
140 131
141 &i2c0 { 132 &i2c0 {
142 pinctrl-0 = <&i2c0_pins>; 133 pinctrl-0 = <&i2c0_pins>;
143 pinctrl-names = "default"; 134 pinctrl-names = "default";
144 135
145 status = "okay"; 136 status = "okay";
146 clock-frequency = <400000>; 137 clock-frequency = <400000>;
147 138
148 hdmi@39 { !! 139 hdmi@39{
149 compatible = "adi,adv7511w"; 140 compatible = "adi,adv7511w";
150 #sound-dai-cells = <0>; 141 #sound-dai-cells = <0>;
151 reg = <0x39>; 142 reg = <0x39>;
152 interrupt-parent = <&gpio1>; 143 interrupt-parent = <&gpio1>;
153 interrupts = <20 IRQ_TYPE_LEVE 144 interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
154 avdd-supply = <&vcc_d1_8v>; 145 avdd-supply = <&vcc_d1_8v>;
155 dvdd-supply = <&vcc_d1_8v>; 146 dvdd-supply = <&vcc_d1_8v>;
156 pvdd-supply = <&vcc_d1_8v>; 147 pvdd-supply = <&vcc_d1_8v>;
157 bgvdd-supply = <&vcc_d1_8v>; 148 bgvdd-supply = <&vcc_d1_8v>;
158 dvdd-3v-supply = <&vcc_d3_3v>; 149 dvdd-3v-supply = <&vcc_d3_3v>;
159 150
160 adi,input-depth = <8>; 151 adi,input-depth = <8>;
161 adi,input-colorspace = "rgb"; 152 adi,input-colorspace = "rgb";
162 adi,input-clock = "1x"; 153 adi,input-clock = "1x";
163 154
164 ports { 155 ports {
165 #address-cells = <1>; 156 #address-cells = <1>;
166 #size-cells = <0>; 157 #size-cells = <0>;
167 158
168 port@0 { 159 port@0 {
169 reg = <0>; 160 reg = <0>;
170 adv7511_in: en 161 adv7511_in: endpoint {
171 remote 162 remote-endpoint = <&thc63lvd1024_out>;
172 }; 163 };
173 }; 164 };
174 165
175 port@1 { 166 port@1 {
176 reg = <1>; 167 reg = <1>;
177 adv7511_out: e 168 adv7511_out: endpoint {
178 remote 169 remote-endpoint = <&hdmi_con>;
179 }; 170 };
180 }; 171 };
181 }; 172 };
182 }; 173 };
183 }; 174 };
184 175
185 &lvds0 { 176 &lvds0 {
186 status = "okay"; 177 status = "okay";
187 178
188 ports { 179 ports {
189 port@1 { 180 port@1 {
190 lvds0_out: endpoint { 181 lvds0_out: endpoint {
191 remote-endpoin 182 remote-endpoint = <&thc63lvd1024_in>;
192 }; 183 };
193 }; 184 };
194 }; 185 };
195 }; 186 };
196 187
197 &mmc0 { 188 &mmc0 {
198 pinctrl-0 = <&mmc_pins>; 189 pinctrl-0 = <&mmc_pins>;
199 pinctrl-names = "default"; 190 pinctrl-names = "default";
200 191
201 vmmc-supply = <&vcc_d3_3v>; 192 vmmc-supply = <&vcc_d3_3v>;
202 vqmmc-supply = <&vcc_vddq_vin0>; 193 vqmmc-supply = <&vcc_vddq_vin0>;
203 bus-width = <8>; 194 bus-width = <8>;
204 non-removable; 195 non-removable;
205 status = "okay"; 196 status = "okay";
206 }; 197 };
207 198
208 &pfc { 199 &pfc {
209 avb_pins: avb0 { 200 avb_pins: avb0 {
210 groups = "avb0_mdio", "avb0_rg 201 groups = "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk";
211 function = "avb0"; 202 function = "avb0";
212 }; 203 };
213 204
214 i2c0_pins: i2c0 { 205 i2c0_pins: i2c0 {
215 groups = "i2c0"; 206 groups = "i2c0";
216 function = "i2c0"; 207 function = "i2c0";
217 }; 208 };
218 209
219 mmc_pins: mmc_3_3v { 210 mmc_pins: mmc_3_3v {
220 groups = "mmc_data8", "mmc_ctr 211 groups = "mmc_data8", "mmc_ctrl";
221 function = "mmc"; 212 function = "mmc";
222 power-source = <3300>; 213 power-source = <3300>;
223 }; 214 };
224 215
225 qspi0_pins: qspi0 { 216 qspi0_pins: qspi0 {
226 groups = "qspi0_ctrl", "qspi0_ 217 groups = "qspi0_ctrl", "qspi0_data4";
227 function = "qspi0"; 218 function = "qspi0";
228 }; 219 };
229 220
230 scif0_pins: scif0 { 221 scif0_pins: scif0 {
231 groups = "scif0_data"; 222 groups = "scif0_data";
232 function = "scif0"; 223 function = "scif0";
233 }; 224 };
234 }; 225 };
235 226
236 &rpc { 227 &rpc {
237 pinctrl-0 = <&qspi0_pins>; 228 pinctrl-0 = <&qspi0_pins>;
238 pinctrl-names = "default"; 229 pinctrl-names = "default";
239 230
240 status = "okay"; 231 status = "okay";
241 232
242 flash@0 { 233 flash@0 {
243 compatible = "spansion,s25fs51 234 compatible = "spansion,s25fs512s", "jedec,spi-nor";
244 reg = <0>; 235 reg = <0>;
245 spi-max-frequency = <50000000> 236 spi-max-frequency = <50000000>;
246 spi-rx-bus-width = <4>; 237 spi-rx-bus-width = <4>;
247 238
248 partitions { 239 partitions {
249 compatible = "fixed-pa 240 compatible = "fixed-partitions";
250 #address-cells = <1>; 241 #address-cells = <1>;
251 #size-cells = <1>; 242 #size-cells = <1>;
252 243
253 bootparam@0 { 244 bootparam@0 {
254 reg = <0x00000 245 reg = <0x00000000 0x040000>;
255 read-only; 246 read-only;
256 }; 247 };
257 cr7@40000 { 248 cr7@40000 {
258 reg = <0x00040 249 reg = <0x00040000 0x080000>;
259 read-only; 250 read-only;
260 }; 251 };
261 cert_header_sa3@c0000 252 cert_header_sa3@c0000 {
262 reg = <0x000c0 253 reg = <0x000c0000 0x080000>;
263 read-only; 254 read-only;
264 }; 255 };
265 bl2@140000 { 256 bl2@140000 {
266 reg = <0x00140 257 reg = <0x00140000 0x040000>;
267 read-only; 258 read-only;
268 }; 259 };
269 cert_header_sa6@180000 260 cert_header_sa6@180000 {
270 reg = <0x00180 261 reg = <0x00180000 0x040000>;
271 read-only; 262 read-only;
272 }; 263 };
273 bl31@1c0000 { 264 bl31@1c0000 {
274 reg = <0x001c0 265 reg = <0x001c0000 0x460000>;
275 read-only; 266 read-only;
276 }; 267 };
277 uboot@640000 { 268 uboot@640000 {
278 reg = <0x00640 269 reg = <0x00640000 0x0c0000>;
279 read-only; 270 read-only;
280 }; 271 };
281 uboot-env@700000 { 272 uboot-env@700000 {
282 reg = <0x00700 273 reg = <0x00700000 0x040000>;
283 read-only; 274 read-only;
284 }; 275 };
285 dtb@740000 { 276 dtb@740000 {
286 reg = <0x00740 277 reg = <0x00740000 0x080000>;
287 }; 278 };
288 kernel@7c0000 { 279 kernel@7c0000 {
289 reg = <0x007c0 280 reg = <0x007c0000 0x1400000>;
290 }; 281 };
291 user@1bc0000 { 282 user@1bc0000 {
292 reg = <0x01bc0 283 reg = <0x01bc0000 0x2440000>;
293 }; 284 };
294 }; 285 };
295 }; 286 };
296 }; 287 };
297 288
298 &scif0 { 289 &scif0 {
299 pinctrl-0 = <&scif0_pins>; 290 pinctrl-0 = <&scif0_pins>;
300 pinctrl-names = "default"; 291 pinctrl-names = "default";
301 292
302 status = "okay"; 293 status = "okay";
303 }; 294 };
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