1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * Device Tree Source for the V3M Starter Kit 3 * Device Tree Source for the V3M Starter Kit board
4 * 4 *
5 * Copyright (C) 2017 Renesas Electronics Corp 5 * Copyright (C) 2017 Renesas Electronics Corp.
6 * Copyright (C) 2017 Cogent Embedded, Inc. 6 * Copyright (C) 2017 Cogent Embedded, Inc.
7 */ 7 */
8 8
9 /dts-v1/; 9 /dts-v1/;
10 #include "r8a77970.dtsi" 10 #include "r8a77970.dtsi"
11 #include <dt-bindings/gpio/gpio.h> 11 #include <dt-bindings/gpio/gpio.h>
12 12
13 / { 13 / {
14 model = "Renesas V3M Starter Kit board 14 model = "Renesas V3M Starter Kit board";
15 compatible = "renesas,v3msk", "renesas 15 compatible = "renesas,v3msk", "renesas,r8a77970";
16 16
17 aliases { 17 aliases {
18 i2c0 = &i2c0; <<
19 i2c1 = &i2c1; <<
20 i2c2 = &i2c2; <<
21 i2c3 = &i2c3; <<
22 i2c4 = &i2c4; <<
23 serial0 = &scif0; 18 serial0 = &scif0;
24 }; 19 };
25 20
26 chosen { 21 chosen {
27 stdout-path = "serial0:115200n 22 stdout-path = "serial0:115200n8";
28 }; 23 };
29 24
30 hdmi-out { 25 hdmi-out {
31 compatible = "hdmi-connector"; 26 compatible = "hdmi-connector";
32 type = "a"; 27 type = "a";
33 28
34 port { 29 port {
35 hdmi_con: endpoint { 30 hdmi_con: endpoint {
36 remote-endpoin 31 remote-endpoint = <&adv7511_out>;
37 }; 32 };
38 }; 33 };
39 }; 34 };
40 35
41 lvds-decoder { 36 lvds-decoder {
42 compatible = "thine,thc63lvd10 37 compatible = "thine,thc63lvd1024";
43 vcc-supply = <&vcc_d3_3v>; 38 vcc-supply = <&vcc_d3_3v>;
44 39
45 ports { 40 ports {
46 #address-cells = <1>; 41 #address-cells = <1>;
47 #size-cells = <0>; 42 #size-cells = <0>;
48 43
49 port@0 { 44 port@0 {
50 reg = <0>; 45 reg = <0>;
51 thc63lvd1024_i 46 thc63lvd1024_in: endpoint {
52 remote 47 remote-endpoint = <&lvds0_out>;
53 }; 48 };
54 }; 49 };
55 50
56 port@2 { 51 port@2 {
57 reg = <2>; 52 reg = <2>;
58 thc63lvd1024_o 53 thc63lvd1024_out: endpoint {
59 remote 54 remote-endpoint = <&adv7511_in>;
60 }; 55 };
61 }; 56 };
62 }; 57 };
63 }; 58 };
64 59
65 memory@48000000 { 60 memory@48000000 {
66 device_type = "memory"; 61 device_type = "memory";
67 /* first 128MB is reserved for 62 /* first 128MB is reserved for secure area. */
68 reg = <0x0 0x48000000 0x0 0x78 63 reg = <0x0 0x48000000 0x0 0x78000000>;
69 }; 64 };
70 65
71 osc5_clk: osc5-clock { 66 osc5_clk: osc5-clock {
72 compatible = "fixed-clock"; 67 compatible = "fixed-clock";
73 #clock-cells = <0>; 68 #clock-cells = <0>;
74 clock-frequency = <148500000>; 69 clock-frequency = <148500000>;
75 }; 70 };
76 71
77 vcc_d1_8v: regulator-0 { 72 vcc_d1_8v: regulator-0 {
78 compatible = "regulator-fixed" 73 compatible = "regulator-fixed";
79 regulator-name = "VCC_D1.8V"; 74 regulator-name = "VCC_D1.8V";
80 regulator-min-microvolt = <180 75 regulator-min-microvolt = <1800000>;
81 regulator-max-microvolt = <180 76 regulator-max-microvolt = <1800000>;
82 regulator-boot-on; 77 regulator-boot-on;
83 regulator-always-on; 78 regulator-always-on;
84 }; 79 };
85 80
86 vcc_d3_3v: regulator-1 { 81 vcc_d3_3v: regulator-1 {
87 compatible = "regulator-fixed" 82 compatible = "regulator-fixed";
88 regulator-name = "VCC_D3.3V"; 83 regulator-name = "VCC_D3.3V";
89 regulator-min-microvolt = <330 84 regulator-min-microvolt = <3300000>;
90 regulator-max-microvolt = <330 85 regulator-max-microvolt = <3300000>;
91 regulator-boot-on; 86 regulator-boot-on;
92 regulator-always-on; 87 regulator-always-on;
93 }; 88 };
94 89
95 vcc_vddq_vin0: regulator-2 { 90 vcc_vddq_vin0: regulator-2 {
96 compatible = "regulator-fixed" 91 compatible = "regulator-fixed";
97 regulator-name = "VCC_VDDQ_VIN 92 regulator-name = "VCC_VDDQ_VIN0";
98 regulator-min-microvolt = <330 93 regulator-min-microvolt = <3300000>;
99 regulator-max-microvolt = <330 94 regulator-max-microvolt = <3300000>;
100 regulator-boot-on; 95 regulator-boot-on;
101 regulator-always-on; 96 regulator-always-on;
102 }; 97 };
103 }; 98 };
104 99
105 &avb { 100 &avb {
106 pinctrl-0 = <&avb_pins>; 101 pinctrl-0 = <&avb_pins>;
107 pinctrl-names = "default"; 102 pinctrl-names = "default";
108 103
109 renesas,no-ether-link; 104 renesas,no-ether-link;
110 phy-handle = <&phy0>; 105 phy-handle = <&phy0>;
111 rx-internal-delay-ps = <1800>; 106 rx-internal-delay-ps = <1800>;
112 tx-internal-delay-ps = <2000>; 107 tx-internal-delay-ps = <2000>;
113 status = "okay"; 108 status = "okay";
114 109
115 phy0: ethernet-phy@0 { 110 phy0: ethernet-phy@0 {
116 compatible = "ethernet-phy-id0 111 compatible = "ethernet-phy-id0022.1622",
117 "ethernet-phy-iee 112 "ethernet-phy-ieee802.3-c22";
118 rxc-skew-ps = <1500>; 113 rxc-skew-ps = <1500>;
119 reg = <0>; 114 reg = <0>;
120 interrupt-parent = <&gpio1>; 115 interrupt-parent = <&gpio1>;
121 interrupts = <17 IRQ_TYPE_LEVE 116 interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
122 reset-gpios = <&gpio1 16 GPIO_ 117 reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
123 }; 118 };
124 }; 119 };
125 120
126 &du { 121 &du {
127 clocks = <&cpg CPG_MOD 724>, 122 clocks = <&cpg CPG_MOD 724>,
128 <&osc5_clk>; 123 <&osc5_clk>;
129 clock-names = "du.0", "dclkin.0"; 124 clock-names = "du.0", "dclkin.0";
130 status = "okay"; 125 status = "okay";
131 }; 126 };
132 127
133 &extal_clk { 128 &extal_clk {
134 clock-frequency = <16666666>; 129 clock-frequency = <16666666>;
135 }; 130 };
136 131
137 &extalr_clk { 132 &extalr_clk {
138 clock-frequency = <32768>; 133 clock-frequency = <32768>;
139 }; 134 };
140 135
141 &i2c0 { 136 &i2c0 {
142 pinctrl-0 = <&i2c0_pins>; 137 pinctrl-0 = <&i2c0_pins>;
143 pinctrl-names = "default"; 138 pinctrl-names = "default";
144 139
145 status = "okay"; 140 status = "okay";
146 clock-frequency = <400000>; 141 clock-frequency = <400000>;
147 142
148 hdmi@39 { !! 143 hdmi@39{
149 compatible = "adi,adv7511w"; 144 compatible = "adi,adv7511w";
150 #sound-dai-cells = <0>; 145 #sound-dai-cells = <0>;
151 reg = <0x39>; 146 reg = <0x39>;
152 interrupt-parent = <&gpio1>; 147 interrupt-parent = <&gpio1>;
153 interrupts = <20 IRQ_TYPE_LEVE 148 interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
154 avdd-supply = <&vcc_d1_8v>; 149 avdd-supply = <&vcc_d1_8v>;
155 dvdd-supply = <&vcc_d1_8v>; 150 dvdd-supply = <&vcc_d1_8v>;
156 pvdd-supply = <&vcc_d1_8v>; 151 pvdd-supply = <&vcc_d1_8v>;
157 bgvdd-supply = <&vcc_d1_8v>; 152 bgvdd-supply = <&vcc_d1_8v>;
158 dvdd-3v-supply = <&vcc_d3_3v>; 153 dvdd-3v-supply = <&vcc_d3_3v>;
159 154
160 adi,input-depth = <8>; 155 adi,input-depth = <8>;
161 adi,input-colorspace = "rgb"; 156 adi,input-colorspace = "rgb";
162 adi,input-clock = "1x"; 157 adi,input-clock = "1x";
163 158
164 ports { 159 ports {
165 #address-cells = <1>; 160 #address-cells = <1>;
166 #size-cells = <0>; 161 #size-cells = <0>;
167 162
168 port@0 { 163 port@0 {
169 reg = <0>; 164 reg = <0>;
170 adv7511_in: en 165 adv7511_in: endpoint {
171 remote 166 remote-endpoint = <&thc63lvd1024_out>;
172 }; 167 };
173 }; 168 };
174 169
175 port@1 { 170 port@1 {
176 reg = <1>; 171 reg = <1>;
177 adv7511_out: e 172 adv7511_out: endpoint {
178 remote 173 remote-endpoint = <&hdmi_con>;
179 }; 174 };
180 }; 175 };
181 }; 176 };
182 }; 177 };
183 }; 178 };
184 179
185 &lvds0 { 180 &lvds0 {
186 status = "okay"; 181 status = "okay";
187 182
188 ports { 183 ports {
189 port@1 { 184 port@1 {
190 lvds0_out: endpoint { 185 lvds0_out: endpoint {
191 remote-endpoin 186 remote-endpoint = <&thc63lvd1024_in>;
192 }; 187 };
193 }; 188 };
194 }; 189 };
195 }; 190 };
196 191
197 &mmc0 { 192 &mmc0 {
198 pinctrl-0 = <&mmc_pins>; 193 pinctrl-0 = <&mmc_pins>;
199 pinctrl-names = "default"; 194 pinctrl-names = "default";
200 195
201 vmmc-supply = <&vcc_d3_3v>; 196 vmmc-supply = <&vcc_d3_3v>;
202 vqmmc-supply = <&vcc_vddq_vin0>; 197 vqmmc-supply = <&vcc_vddq_vin0>;
203 bus-width = <8>; 198 bus-width = <8>;
204 non-removable; 199 non-removable;
205 status = "okay"; 200 status = "okay";
206 }; 201 };
207 202
208 &pfc { 203 &pfc {
209 avb_pins: avb0 { 204 avb_pins: avb0 {
210 groups = "avb0_mdio", "avb0_rg 205 groups = "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk";
211 function = "avb0"; 206 function = "avb0";
212 }; 207 };
213 208
214 i2c0_pins: i2c0 { 209 i2c0_pins: i2c0 {
215 groups = "i2c0"; 210 groups = "i2c0";
216 function = "i2c0"; 211 function = "i2c0";
217 }; 212 };
218 213
219 mmc_pins: mmc_3_3v { 214 mmc_pins: mmc_3_3v {
220 groups = "mmc_data8", "mmc_ctr 215 groups = "mmc_data8", "mmc_ctrl";
221 function = "mmc"; 216 function = "mmc";
222 power-source = <3300>; 217 power-source = <3300>;
223 }; 218 };
224 219
225 qspi0_pins: qspi0 { 220 qspi0_pins: qspi0 {
226 groups = "qspi0_ctrl", "qspi0_ 221 groups = "qspi0_ctrl", "qspi0_data4";
227 function = "qspi0"; 222 function = "qspi0";
228 }; 223 };
229 224
230 scif0_pins: scif0 { 225 scif0_pins: scif0 {
231 groups = "scif0_data"; 226 groups = "scif0_data";
232 function = "scif0"; 227 function = "scif0";
233 }; 228 };
234 }; 229 };
235 230
236 &rpc { 231 &rpc {
237 pinctrl-0 = <&qspi0_pins>; 232 pinctrl-0 = <&qspi0_pins>;
238 pinctrl-names = "default"; 233 pinctrl-names = "default";
239 234
240 status = "okay"; 235 status = "okay";
241 236
242 flash@0 { 237 flash@0 {
243 compatible = "spansion,s25fs51 238 compatible = "spansion,s25fs512s", "jedec,spi-nor";
244 reg = <0>; 239 reg = <0>;
245 spi-max-frequency = <50000000> 240 spi-max-frequency = <50000000>;
246 spi-rx-bus-width = <4>; 241 spi-rx-bus-width = <4>;
247 242
248 partitions { 243 partitions {
249 compatible = "fixed-pa 244 compatible = "fixed-partitions";
250 #address-cells = <1>; 245 #address-cells = <1>;
251 #size-cells = <1>; 246 #size-cells = <1>;
252 247
253 bootparam@0 { 248 bootparam@0 {
254 reg = <0x00000 249 reg = <0x00000000 0x040000>;
255 read-only; 250 read-only;
256 }; 251 };
257 cr7@40000 { 252 cr7@40000 {
258 reg = <0x00040 253 reg = <0x00040000 0x080000>;
259 read-only; 254 read-only;
260 }; 255 };
261 cert_header_sa3@c0000 256 cert_header_sa3@c0000 {
262 reg = <0x000c0 257 reg = <0x000c0000 0x080000>;
263 read-only; 258 read-only;
264 }; 259 };
265 bl2@140000 { 260 bl2@140000 {
266 reg = <0x00140 261 reg = <0x00140000 0x040000>;
267 read-only; 262 read-only;
268 }; 263 };
269 cert_header_sa6@180000 264 cert_header_sa6@180000 {
270 reg = <0x00180 265 reg = <0x00180000 0x040000>;
271 read-only; 266 read-only;
272 }; 267 };
273 bl31@1c0000 { 268 bl31@1c0000 {
274 reg = <0x001c0 269 reg = <0x001c0000 0x460000>;
275 read-only; 270 read-only;
276 }; 271 };
277 uboot@640000 { 272 uboot@640000 {
278 reg = <0x00640 273 reg = <0x00640000 0x0c0000>;
279 read-only; 274 read-only;
280 }; 275 };
281 uboot-env@700000 { 276 uboot-env@700000 {
282 reg = <0x00700 277 reg = <0x00700000 0x040000>;
283 read-only; 278 read-only;
284 }; 279 };
285 dtb@740000 { 280 dtb@740000 {
286 reg = <0x00740 281 reg = <0x00740000 0x080000>;
287 }; 282 };
288 kernel@7c0000 { 283 kernel@7c0000 {
289 reg = <0x007c0 284 reg = <0x007c0000 0x1400000>;
290 }; 285 };
291 user@1bc0000 { 286 user@1bc0000 {
292 reg = <0x01bc0 287 reg = <0x01bc0000 0x2440000>;
293 }; 288 };
294 }; 289 };
295 }; 290 };
296 }; 291 };
297 292
298 &scif0 { 293 &scif0 {
299 pinctrl-0 = <&scif0_pins>; 294 pinctrl-0 = <&scif0_pins>;
300 pinctrl-names = "default"; 295 pinctrl-names = "default";
301 296
302 status = "okay"; 297 status = "okay";
303 }; 298 };
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