1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * Device Tree Source for the R-Car E3 (R8A779 3 * Device Tree Source for the R-Car E3 (R8A77990) SoC
4 * 4 *
5 * Copyright (C) 2018-2019 Renesas Electronics 5 * Copyright (C) 2018-2019 Renesas Electronics Corp.
6 */ 6 */
7 7
8 #include <dt-bindings/clock/r8a77990-cpg-mssr. 8 #include <dt-bindings/clock/r8a77990-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm 9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a77990-sysc.h> 10 #include <dt-bindings/power/r8a77990-sysc.h>
11 11
12 / { 12 / {
13 compatible = "renesas,r8a77990"; 13 compatible = "renesas,r8a77990";
14 #address-cells = <2>; 14 #address-cells = <2>;
15 #size-cells = <2>; 15 #size-cells = <2>;
16 16
17 /* 17 /*
18 * The external audio clocks are confi 18 * The external audio clocks are configured as 0 Hz fixed frequency
19 * clocks by default. 19 * clocks by default.
20 * Boards that provide audio clocks sh 20 * Boards that provide audio clocks should override them.
21 */ 21 */
22 audio_clk_a: audio_clk_a { 22 audio_clk_a: audio_clk_a {
23 compatible = "fixed-clock"; 23 compatible = "fixed-clock";
24 #clock-cells = <0>; 24 #clock-cells = <0>;
25 clock-frequency = <0>; 25 clock-frequency = <0>;
26 }; 26 };
27 27
28 audio_clk_b: audio_clk_b { 28 audio_clk_b: audio_clk_b {
29 compatible = "fixed-clock"; 29 compatible = "fixed-clock";
30 #clock-cells = <0>; 30 #clock-cells = <0>;
31 clock-frequency = <0>; 31 clock-frequency = <0>;
32 }; 32 };
33 33
34 audio_clk_c: audio_clk_c { 34 audio_clk_c: audio_clk_c {
35 compatible = "fixed-clock"; 35 compatible = "fixed-clock";
36 #clock-cells = <0>; 36 #clock-cells = <0>;
37 clock-frequency = <0>; 37 clock-frequency = <0>;
38 }; 38 };
39 39
40 /* External CAN clock - to be overridd 40 /* External CAN clock - to be overridden by boards that provide it */
41 can_clk: can { 41 can_clk: can {
42 compatible = "fixed-clock"; 42 compatible = "fixed-clock";
43 #clock-cells = <0>; 43 #clock-cells = <0>;
44 clock-frequency = <0>; 44 clock-frequency = <0>;
45 }; 45 };
46 46
47 cluster1_opp: opp-table-1 { 47 cluster1_opp: opp-table-1 {
48 compatible = "operating-points 48 compatible = "operating-points-v2";
49 opp-shared; 49 opp-shared;
50 opp-800000000 { 50 opp-800000000 {
51 opp-hz = /bits/ 64 <80 51 opp-hz = /bits/ 64 <800000000>;
52 clock-latency-ns = <30 52 clock-latency-ns = <300000>;
53 }; 53 };
54 opp-1000000000 { 54 opp-1000000000 {
55 opp-hz = /bits/ 64 <10 55 opp-hz = /bits/ 64 <1000000000>;
56 clock-latency-ns = <30 56 clock-latency-ns = <300000>;
57 }; 57 };
58 opp-1200000000 { 58 opp-1200000000 {
59 opp-hz = /bits/ 64 <12 59 opp-hz = /bits/ 64 <1200000000>;
60 clock-latency-ns = <30 60 clock-latency-ns = <300000>;
61 opp-suspend; 61 opp-suspend;
62 }; 62 };
63 }; 63 };
64 64
65 cpus { 65 cpus {
66 #address-cells = <1>; 66 #address-cells = <1>;
67 #size-cells = <0>; 67 #size-cells = <0>;
68 68
69 a53_0: cpu@0 { 69 a53_0: cpu@0 {
70 compatible = "arm,cort 70 compatible = "arm,cortex-a53";
71 reg = <0>; 71 reg = <0>;
72 device_type = "cpu"; 72 device_type = "cpu";
73 #cooling-cells = <2>; 73 #cooling-cells = <2>;
74 power-domains = <&sysc 74 power-domains = <&sysc R8A77990_PD_CA53_CPU0>;
75 next-level-cache = <&L 75 next-level-cache = <&L2_CA53>;
76 enable-method = "psci" 76 enable-method = "psci";
77 cpu-idle-states = <&CP 77 cpu-idle-states = <&CPU_SLEEP_0>;
78 dynamic-power-coeffici 78 dynamic-power-coefficient = <277>;
79 clocks = <&cpg CPG_COR 79 clocks = <&cpg CPG_CORE R8A77990_CLK_Z2>;
80 operating-points-v2 = 80 operating-points-v2 = <&cluster1_opp>;
81 }; 81 };
82 82
83 a53_1: cpu@1 { 83 a53_1: cpu@1 {
84 compatible = "arm,cort 84 compatible = "arm,cortex-a53";
85 reg = <1>; 85 reg = <1>;
86 device_type = "cpu"; 86 device_type = "cpu";
87 power-domains = <&sysc 87 power-domains = <&sysc R8A77990_PD_CA53_CPU1>;
88 next-level-cache = <&L 88 next-level-cache = <&L2_CA53>;
89 enable-method = "psci" 89 enable-method = "psci";
90 cpu-idle-states = <&CP 90 cpu-idle-states = <&CPU_SLEEP_0>;
91 clocks = <&cpg CPG_COR 91 clocks = <&cpg CPG_CORE R8A77990_CLK_Z2>;
92 operating-points-v2 = 92 operating-points-v2 = <&cluster1_opp>;
93 }; 93 };
94 94
95 L2_CA53: cache-controller-0 { 95 L2_CA53: cache-controller-0 {
96 compatible = "cache"; 96 compatible = "cache";
97 power-domains = <&sysc 97 power-domains = <&sysc R8A77990_PD_CA53_SCU>;
98 cache-unified; 98 cache-unified;
99 cache-level = <2>; 99 cache-level = <2>;
100 }; 100 };
101 101
102 idle-states { 102 idle-states {
103 entry-method = "psci"; 103 entry-method = "psci";
104 104
105 CPU_SLEEP_0: cpu-sleep 105 CPU_SLEEP_0: cpu-sleep-0 {
106 compatible = " 106 compatible = "arm,idle-state";
107 arm,psci-suspe 107 arm,psci-suspend-param = <0x0010000>;
108 local-timer-st 108 local-timer-stop;
109 entry-latency- 109 entry-latency-us = <700>;
110 exit-latency-u 110 exit-latency-us = <700>;
111 min-residency- 111 min-residency-us = <5000>;
112 }; 112 };
113 }; 113 };
114 }; 114 };
115 115
116 extal_clk: extal { 116 extal_clk: extal {
117 compatible = "fixed-clock"; 117 compatible = "fixed-clock";
118 #clock-cells = <0>; 118 #clock-cells = <0>;
119 /* This value must be overridd 119 /* This value must be overridden by the board */
120 clock-frequency = <0>; 120 clock-frequency = <0>;
121 }; 121 };
122 122
123 /* External PCIe clock - can be overri 123 /* External PCIe clock - can be overridden by the board */
124 pcie_bus_clk: pcie_bus { 124 pcie_bus_clk: pcie_bus {
125 compatible = "fixed-clock"; 125 compatible = "fixed-clock";
126 #clock-cells = <0>; 126 #clock-cells = <0>;
127 clock-frequency = <0>; 127 clock-frequency = <0>;
128 }; 128 };
129 129
130 pmu_a53 { 130 pmu_a53 {
131 compatible = "arm,cortex-a53-p 131 compatible = "arm,cortex-a53-pmu";
132 interrupts-extended = <&gic GI 132 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
133 <&gic GI 133 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
134 interrupt-affinity = <&a53_0>, 134 interrupt-affinity = <&a53_0>, <&a53_1>;
135 }; 135 };
136 136
137 psci { 137 psci {
138 compatible = "arm,psci-1.0", " 138 compatible = "arm,psci-1.0", "arm,psci-0.2";
139 method = "smc"; 139 method = "smc";
140 }; 140 };
141 141
142 /* External SCIF clock - to be overrid 142 /* External SCIF clock - to be overridden by boards that provide it */
143 scif_clk: scif { 143 scif_clk: scif {
144 compatible = "fixed-clock"; 144 compatible = "fixed-clock";
145 #clock-cells = <0>; 145 #clock-cells = <0>;
146 clock-frequency = <0>; 146 clock-frequency = <0>;
147 }; 147 };
148 148
149 soc: soc { 149 soc: soc {
150 compatible = "simple-bus"; 150 compatible = "simple-bus";
151 interrupt-parent = <&gic>; 151 interrupt-parent = <&gic>;
152 #address-cells = <2>; 152 #address-cells = <2>;
153 #size-cells = <2>; 153 #size-cells = <2>;
154 ranges; 154 ranges;
155 155
156 rwdt: watchdog@e6020000 { 156 rwdt: watchdog@e6020000 {
157 compatible = "renesas, 157 compatible = "renesas,r8a77990-wdt",
158 "renesas, 158 "renesas,rcar-gen3-wdt";
159 reg = <0 0xe6020000 0 159 reg = <0 0xe6020000 0 0x0c>;
160 interrupts = <GIC_SPI 160 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
161 clocks = <&cpg CPG_MOD 161 clocks = <&cpg CPG_MOD 402>;
162 power-domains = <&sysc 162 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
163 resets = <&cpg 402>; 163 resets = <&cpg 402>;
164 status = "disabled"; 164 status = "disabled";
165 }; 165 };
166 166
167 gpio0: gpio@e6050000 { 167 gpio0: gpio@e6050000 {
168 compatible = "renesas, 168 compatible = "renesas,gpio-r8a77990",
169 "renesas, 169 "renesas,rcar-gen3-gpio";
170 reg = <0 0xe6050000 0 170 reg = <0 0xe6050000 0 0x50>;
171 interrupts = <GIC_SPI 171 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
172 #gpio-cells = <2>; 172 #gpio-cells = <2>;
173 gpio-controller; 173 gpio-controller;
174 gpio-ranges = <&pfc 0 174 gpio-ranges = <&pfc 0 0 18>;
175 #interrupt-cells = <2> 175 #interrupt-cells = <2>;
176 interrupt-controller; 176 interrupt-controller;
177 clocks = <&cpg CPG_MOD 177 clocks = <&cpg CPG_MOD 912>;
178 power-domains = <&sysc 178 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
179 resets = <&cpg 912>; 179 resets = <&cpg 912>;
180 }; 180 };
181 181
182 gpio1: gpio@e6051000 { 182 gpio1: gpio@e6051000 {
183 compatible = "renesas, 183 compatible = "renesas,gpio-r8a77990",
184 "renesas, 184 "renesas,rcar-gen3-gpio";
185 reg = <0 0xe6051000 0 185 reg = <0 0xe6051000 0 0x50>;
186 interrupts = <GIC_SPI 186 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
187 #gpio-cells = <2>; 187 #gpio-cells = <2>;
188 gpio-controller; 188 gpio-controller;
189 gpio-ranges = <&pfc 0 189 gpio-ranges = <&pfc 0 32 23>;
190 #interrupt-cells = <2> 190 #interrupt-cells = <2>;
191 interrupt-controller; 191 interrupt-controller;
192 clocks = <&cpg CPG_MOD 192 clocks = <&cpg CPG_MOD 911>;
193 power-domains = <&sysc 193 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
194 resets = <&cpg 911>; 194 resets = <&cpg 911>;
195 }; 195 };
196 196
197 gpio2: gpio@e6052000 { 197 gpio2: gpio@e6052000 {
198 compatible = "renesas, 198 compatible = "renesas,gpio-r8a77990",
199 "renesas, 199 "renesas,rcar-gen3-gpio";
200 reg = <0 0xe6052000 0 200 reg = <0 0xe6052000 0 0x50>;
201 interrupts = <GIC_SPI 201 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
202 #gpio-cells = <2>; 202 #gpio-cells = <2>;
203 gpio-controller; 203 gpio-controller;
204 gpio-ranges = <&pfc 0 204 gpio-ranges = <&pfc 0 64 26>;
205 #interrupt-cells = <2> 205 #interrupt-cells = <2>;
206 interrupt-controller; 206 interrupt-controller;
207 clocks = <&cpg CPG_MOD 207 clocks = <&cpg CPG_MOD 910>;
208 power-domains = <&sysc 208 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
209 resets = <&cpg 910>; 209 resets = <&cpg 910>;
210 }; 210 };
211 211
212 gpio3: gpio@e6053000 { 212 gpio3: gpio@e6053000 {
213 compatible = "renesas, 213 compatible = "renesas,gpio-r8a77990",
214 "renesas, 214 "renesas,rcar-gen3-gpio";
215 reg = <0 0xe6053000 0 215 reg = <0 0xe6053000 0 0x50>;
216 interrupts = <GIC_SPI 216 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
217 #gpio-cells = <2>; 217 #gpio-cells = <2>;
218 gpio-controller; 218 gpio-controller;
219 gpio-ranges = <&pfc 0 219 gpio-ranges = <&pfc 0 96 16>;
220 #interrupt-cells = <2> 220 #interrupt-cells = <2>;
221 interrupt-controller; 221 interrupt-controller;
222 clocks = <&cpg CPG_MOD 222 clocks = <&cpg CPG_MOD 909>;
223 power-domains = <&sysc 223 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
224 resets = <&cpg 909>; 224 resets = <&cpg 909>;
225 }; 225 };
226 226
227 gpio4: gpio@e6054000 { 227 gpio4: gpio@e6054000 {
228 compatible = "renesas, 228 compatible = "renesas,gpio-r8a77990",
229 "renesas, 229 "renesas,rcar-gen3-gpio";
230 reg = <0 0xe6054000 0 230 reg = <0 0xe6054000 0 0x50>;
231 interrupts = <GIC_SPI 231 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
232 #gpio-cells = <2>; 232 #gpio-cells = <2>;
233 gpio-controller; 233 gpio-controller;
234 gpio-ranges = <&pfc 0 234 gpio-ranges = <&pfc 0 128 11>;
235 #interrupt-cells = <2> 235 #interrupt-cells = <2>;
236 interrupt-controller; 236 interrupt-controller;
237 clocks = <&cpg CPG_MOD 237 clocks = <&cpg CPG_MOD 908>;
238 power-domains = <&sysc 238 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
239 resets = <&cpg 908>; 239 resets = <&cpg 908>;
240 }; 240 };
241 241
242 gpio5: gpio@e6055000 { 242 gpio5: gpio@e6055000 {
243 compatible = "renesas, 243 compatible = "renesas,gpio-r8a77990",
244 "renesas, 244 "renesas,rcar-gen3-gpio";
245 reg = <0 0xe6055000 0 245 reg = <0 0xe6055000 0 0x50>;
246 interrupts = <GIC_SPI 246 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
247 #gpio-cells = <2>; 247 #gpio-cells = <2>;
248 gpio-controller; 248 gpio-controller;
249 gpio-ranges = <&pfc 0 249 gpio-ranges = <&pfc 0 160 20>;
250 #interrupt-cells = <2> 250 #interrupt-cells = <2>;
251 interrupt-controller; 251 interrupt-controller;
252 clocks = <&cpg CPG_MOD 252 clocks = <&cpg CPG_MOD 907>;
253 power-domains = <&sysc 253 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
254 resets = <&cpg 907>; 254 resets = <&cpg 907>;
255 }; 255 };
256 256
257 gpio6: gpio@e6055400 { 257 gpio6: gpio@e6055400 {
258 compatible = "renesas, 258 compatible = "renesas,gpio-r8a77990",
259 "renesas, 259 "renesas,rcar-gen3-gpio";
260 reg = <0 0xe6055400 0 260 reg = <0 0xe6055400 0 0x50>;
261 interrupts = <GIC_SPI 261 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
262 #gpio-cells = <2>; 262 #gpio-cells = <2>;
263 gpio-controller; 263 gpio-controller;
264 gpio-ranges = <&pfc 0 264 gpio-ranges = <&pfc 0 192 18>;
265 #interrupt-cells = <2> 265 #interrupt-cells = <2>;
266 interrupt-controller; 266 interrupt-controller;
267 clocks = <&cpg CPG_MOD 267 clocks = <&cpg CPG_MOD 906>;
268 power-domains = <&sysc 268 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
269 resets = <&cpg 906>; 269 resets = <&cpg 906>;
270 }; 270 };
271 271
272 pfc: pinctrl@e6060000 { 272 pfc: pinctrl@e6060000 {
273 compatible = "renesas, 273 compatible = "renesas,pfc-r8a77990";
274 reg = <0 0xe6060000 0 274 reg = <0 0xe6060000 0 0x508>;
275 }; 275 };
276 276
277 i2c_dvfs: i2c@e60b0000 { 277 i2c_dvfs: i2c@e60b0000 {
278 #address-cells = <1>; 278 #address-cells = <1>;
279 #size-cells = <0>; 279 #size-cells = <0>;
280 compatible = "renesas, 280 compatible = "renesas,iic-r8a77990",
281 "renesas, 281 "renesas,rcar-gen3-iic",
282 "renesas, 282 "renesas,rmobile-iic";
283 reg = <0 0xe60b0000 0 283 reg = <0 0xe60b0000 0 0x425>;
284 interrupts = <GIC_SPI 284 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
285 clocks = <&cpg CPG_MOD 285 clocks = <&cpg CPG_MOD 926>;
286 power-domains = <&sysc 286 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
287 resets = <&cpg 926>; 287 resets = <&cpg 926>;
288 dmas = <&dmac0 0x11>, 288 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
289 dma-names = "tx", "rx" 289 dma-names = "tx", "rx";
290 status = "disabled"; 290 status = "disabled";
291 }; 291 };
292 292
293 cmt0: timer@e60f0000 { 293 cmt0: timer@e60f0000 {
294 compatible = "renesas, 294 compatible = "renesas,r8a77990-cmt0",
295 "renesas, 295 "renesas,rcar-gen3-cmt0";
296 reg = <0 0xe60f0000 0 296 reg = <0 0xe60f0000 0 0x1004>;
297 interrupts = <GIC_SPI 297 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
298 <GIC_SPI 298 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
299 clocks = <&cpg CPG_MOD 299 clocks = <&cpg CPG_MOD 303>;
300 clock-names = "fck"; 300 clock-names = "fck";
301 power-domains = <&sysc 301 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
302 resets = <&cpg 303>; 302 resets = <&cpg 303>;
303 status = "disabled"; 303 status = "disabled";
304 }; 304 };
305 305
306 cmt1: timer@e6130000 { 306 cmt1: timer@e6130000 {
307 compatible = "renesas, 307 compatible = "renesas,r8a77990-cmt1",
308 "renesas, 308 "renesas,rcar-gen3-cmt1";
309 reg = <0 0xe6130000 0 309 reg = <0 0xe6130000 0 0x1004>;
310 interrupts = <GIC_SPI 310 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
311 <GIC_SPI 311 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
312 <GIC_SPI 312 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
313 <GIC_SPI 313 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
314 <GIC_SPI 314 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
315 <GIC_SPI 315 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
316 <GIC_SPI 316 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
317 <GIC_SPI 317 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
318 clocks = <&cpg CPG_MOD 318 clocks = <&cpg CPG_MOD 302>;
319 clock-names = "fck"; 319 clock-names = "fck";
320 power-domains = <&sysc 320 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
321 resets = <&cpg 302>; 321 resets = <&cpg 302>;
322 status = "disabled"; 322 status = "disabled";
323 }; 323 };
324 324
325 cmt2: timer@e6140000 { 325 cmt2: timer@e6140000 {
326 compatible = "renesas, 326 compatible = "renesas,r8a77990-cmt1",
327 "renesas, 327 "renesas,rcar-gen3-cmt1";
328 reg = <0 0xe6140000 0 328 reg = <0 0xe6140000 0 0x1004>;
329 interrupts = <GIC_SPI 329 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
330 <GIC_SPI 330 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
331 <GIC_SPI 331 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
332 <GIC_SPI 332 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
333 <GIC_SPI 333 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
334 <GIC_SPI 334 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
335 <GIC_SPI 335 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
336 <GIC_SPI 336 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
337 clocks = <&cpg CPG_MOD 337 clocks = <&cpg CPG_MOD 301>;
338 clock-names = "fck"; 338 clock-names = "fck";
339 power-domains = <&sysc 339 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
340 resets = <&cpg 301>; 340 resets = <&cpg 301>;
341 status = "disabled"; 341 status = "disabled";
342 }; 342 };
343 343
344 cmt3: timer@e6148000 { 344 cmt3: timer@e6148000 {
345 compatible = "renesas, 345 compatible = "renesas,r8a77990-cmt1",
346 "renesas, 346 "renesas,rcar-gen3-cmt1";
347 reg = <0 0xe6148000 0 347 reg = <0 0xe6148000 0 0x1004>;
348 interrupts = <GIC_SPI 348 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
349 <GIC_SPI 349 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
350 <GIC_SPI 350 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
351 <GIC_SPI 351 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
352 <GIC_SPI 352 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
353 <GIC_SPI 353 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
354 <GIC_SPI 354 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
355 <GIC_SPI 355 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
356 clocks = <&cpg CPG_MOD 356 clocks = <&cpg CPG_MOD 300>;
357 clock-names = "fck"; 357 clock-names = "fck";
358 power-domains = <&sysc 358 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
359 resets = <&cpg 300>; 359 resets = <&cpg 300>;
360 status = "disabled"; 360 status = "disabled";
361 }; 361 };
362 362
363 cpg: clock-controller@e6150000 363 cpg: clock-controller@e6150000 {
364 compatible = "renesas, 364 compatible = "renesas,r8a77990-cpg-mssr";
365 reg = <0 0xe6150000 0 365 reg = <0 0xe6150000 0 0x1000>;
366 clocks = <&extal_clk>; 366 clocks = <&extal_clk>;
367 clock-names = "extal"; 367 clock-names = "extal";
368 #clock-cells = <2>; 368 #clock-cells = <2>;
369 #power-domain-cells = 369 #power-domain-cells = <0>;
370 #reset-cells = <1>; 370 #reset-cells = <1>;
371 }; 371 };
372 372
373 rst: reset-controller@e6160000 373 rst: reset-controller@e6160000 {
374 compatible = "renesas, 374 compatible = "renesas,r8a77990-rst";
375 reg = <0 0xe6160000 0 375 reg = <0 0xe6160000 0 0x0200>;
376 }; 376 };
377 377
378 sysc: system-controller@e61800 378 sysc: system-controller@e6180000 {
379 compatible = "renesas, 379 compatible = "renesas,r8a77990-sysc";
380 reg = <0 0xe6180000 0 380 reg = <0 0xe6180000 0 0x0400>;
381 #power-domain-cells = 381 #power-domain-cells = <1>;
382 }; 382 };
383 383
384 thermal: thermal@e6190000 { 384 thermal: thermal@e6190000 {
385 compatible = "renesas, 385 compatible = "renesas,thermal-r8a77990";
386 reg = <0 0xe6190000 0 386 reg = <0 0xe6190000 0 0x10>, <0 0xe6190100 0 0x38>;
387 interrupts = <GIC_SPI 387 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
388 <GIC_SPI 388 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
389 <GIC_SPI 389 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
390 clocks = <&cpg CPG_MOD 390 clocks = <&cpg CPG_MOD 522>;
391 power-domains = <&sysc 391 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
392 resets = <&cpg 522>; 392 resets = <&cpg 522>;
393 #thermal-sensor-cells 393 #thermal-sensor-cells = <0>;
394 }; 394 };
395 395
396 intc_ex: interrupt-controller@ 396 intc_ex: interrupt-controller@e61c0000 {
397 compatible = "renesas, 397 compatible = "renesas,intc-ex-r8a77990", "renesas,irqc";
398 #interrupt-cells = <2> 398 #interrupt-cells = <2>;
399 interrupt-controller; 399 interrupt-controller;
400 reg = <0 0xe61c0000 0 400 reg = <0 0xe61c0000 0 0x200>;
401 interrupts = <GIC_SPI 401 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
402 <GIC_SPI 402 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
403 <GIC_SPI 403 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
404 <GIC_SPI 404 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
405 <GIC_SPI 405 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
406 <GIC_SPI 406 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
407 clocks = <&cpg CPG_MOD 407 clocks = <&cpg CPG_MOD 407>;
408 power-domains = <&sysc 408 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
409 resets = <&cpg 407>; 409 resets = <&cpg 407>;
410 }; 410 };
411 411
412 tmu0: timer@e61e0000 { 412 tmu0: timer@e61e0000 {
413 compatible = "renesas, 413 compatible = "renesas,tmu-r8a77990", "renesas,tmu";
414 reg = <0 0xe61e0000 0 414 reg = <0 0xe61e0000 0 0x30>;
415 interrupts = <GIC_SPI 415 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
416 <GIC_SPI 416 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
417 <GIC_SPI 417 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
418 interrupt-names = "tun 418 interrupt-names = "tuni0", "tuni1", "tuni2";
419 clocks = <&cpg CPG_MOD 419 clocks = <&cpg CPG_MOD 125>;
420 clock-names = "fck"; 420 clock-names = "fck";
421 power-domains = <&sysc 421 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
422 resets = <&cpg 125>; 422 resets = <&cpg 125>;
423 status = "disabled"; 423 status = "disabled";
424 }; 424 };
425 425
426 tmu1: timer@e6fc0000 { 426 tmu1: timer@e6fc0000 {
427 compatible = "renesas, 427 compatible = "renesas,tmu-r8a77990", "renesas,tmu";
428 reg = <0 0xe6fc0000 0 428 reg = <0 0xe6fc0000 0 0x30>;
429 interrupts = <GIC_SPI 429 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
430 <GIC_SPI 430 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
431 <GIC_SPI 431 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
432 <GIC_SPI 432 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
433 interrupt-names = "tun 433 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
434 clocks = <&cpg CPG_MOD 434 clocks = <&cpg CPG_MOD 124>;
435 clock-names = "fck"; 435 clock-names = "fck";
436 power-domains = <&sysc 436 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
437 resets = <&cpg 124>; 437 resets = <&cpg 124>;
438 status = "disabled"; 438 status = "disabled";
439 }; 439 };
440 440
441 tmu2: timer@e6fd0000 { 441 tmu2: timer@e6fd0000 {
442 compatible = "renesas, 442 compatible = "renesas,tmu-r8a77990", "renesas,tmu";
443 reg = <0 0xe6fd0000 0 443 reg = <0 0xe6fd0000 0 0x30>;
444 interrupts = <GIC_SPI 444 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
445 <GIC_SPI 445 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
446 <GIC_SPI 446 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
447 <GIC_SPI 447 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
448 interrupt-names = "tun 448 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
449 clocks = <&cpg CPG_MOD 449 clocks = <&cpg CPG_MOD 123>;
450 clock-names = "fck"; 450 clock-names = "fck";
451 power-domains = <&sysc 451 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
452 resets = <&cpg 123>; 452 resets = <&cpg 123>;
453 status = "disabled"; 453 status = "disabled";
454 }; 454 };
455 455
456 tmu3: timer@e6fe0000 { 456 tmu3: timer@e6fe0000 {
457 compatible = "renesas, 457 compatible = "renesas,tmu-r8a77990", "renesas,tmu";
458 reg = <0 0xe6fe0000 0 458 reg = <0 0xe6fe0000 0 0x30>;
459 interrupts = <GIC_SPI 459 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
460 <GIC_SPI 460 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
461 <GIC_SPI 461 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
462 interrupt-names = "tun 462 interrupt-names = "tuni0", "tuni1", "tuni2";
463 clocks = <&cpg CPG_MOD 463 clocks = <&cpg CPG_MOD 122>;
464 clock-names = "fck"; 464 clock-names = "fck";
465 power-domains = <&sysc 465 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
466 resets = <&cpg 122>; 466 resets = <&cpg 122>;
467 status = "disabled"; 467 status = "disabled";
468 }; 468 };
469 469
470 tmu4: timer@ffc00000 { 470 tmu4: timer@ffc00000 {
471 compatible = "renesas, 471 compatible = "renesas,tmu-r8a77990", "renesas,tmu";
472 reg = <0 0xffc00000 0 472 reg = <0 0xffc00000 0 0x30>;
473 interrupts = <GIC_SPI 473 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
474 <GIC_SPI 474 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
475 <GIC_SPI 475 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
476 interrupt-names = "tun 476 interrupt-names = "tuni0", "tuni1", "tuni2";
477 clocks = <&cpg CPG_MOD 477 clocks = <&cpg CPG_MOD 121>;
478 clock-names = "fck"; 478 clock-names = "fck";
479 power-domains = <&sysc 479 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
480 resets = <&cpg 121>; 480 resets = <&cpg 121>;
481 status = "disabled"; 481 status = "disabled";
482 }; 482 };
483 483
484 i2c0: i2c@e6500000 { 484 i2c0: i2c@e6500000 {
485 #address-cells = <1>; 485 #address-cells = <1>;
486 #size-cells = <0>; 486 #size-cells = <0>;
487 compatible = "renesas, 487 compatible = "renesas,i2c-r8a77990",
488 "renesas, 488 "renesas,rcar-gen3-i2c";
489 reg = <0 0xe6500000 0 489 reg = <0 0xe6500000 0 0x40>;
490 interrupts = <GIC_SPI 490 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
491 clocks = <&cpg CPG_MOD 491 clocks = <&cpg CPG_MOD 931>;
492 power-domains = <&sysc 492 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
493 resets = <&cpg 931>; 493 resets = <&cpg 931>;
494 dmas = <&dmac1 0x91>, 494 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
495 <&dmac2 0x91>, 495 <&dmac2 0x91>, <&dmac2 0x90>;
496 dma-names = "tx", "rx" 496 dma-names = "tx", "rx", "tx", "rx";
497 i2c-scl-internal-delay 497 i2c-scl-internal-delay-ns = <110>;
498 status = "disabled"; 498 status = "disabled";
499 }; 499 };
500 500
501 i2c1: i2c@e6508000 { 501 i2c1: i2c@e6508000 {
502 #address-cells = <1>; 502 #address-cells = <1>;
503 #size-cells = <0>; 503 #size-cells = <0>;
504 compatible = "renesas, 504 compatible = "renesas,i2c-r8a77990",
505 "renesas, 505 "renesas,rcar-gen3-i2c";
506 reg = <0 0xe6508000 0 506 reg = <0 0xe6508000 0 0x40>;
507 interrupts = <GIC_SPI 507 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
508 clocks = <&cpg CPG_MOD 508 clocks = <&cpg CPG_MOD 930>;
509 power-domains = <&sysc 509 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
510 resets = <&cpg 930>; 510 resets = <&cpg 930>;
511 dmas = <&dmac1 0x93>, 511 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
512 <&dmac2 0x93>, 512 <&dmac2 0x93>, <&dmac2 0x92>;
513 dma-names = "tx", "rx" 513 dma-names = "tx", "rx", "tx", "rx";
514 i2c-scl-internal-delay 514 i2c-scl-internal-delay-ns = <6>;
515 status = "disabled"; 515 status = "disabled";
516 }; 516 };
517 517
518 i2c2: i2c@e6510000 { 518 i2c2: i2c@e6510000 {
519 #address-cells = <1>; 519 #address-cells = <1>;
520 #size-cells = <0>; 520 #size-cells = <0>;
521 compatible = "renesas, 521 compatible = "renesas,i2c-r8a77990",
522 "renesas, 522 "renesas,rcar-gen3-i2c";
523 reg = <0 0xe6510000 0 523 reg = <0 0xe6510000 0 0x40>;
524 interrupts = <GIC_SPI 524 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
525 clocks = <&cpg CPG_MOD 525 clocks = <&cpg CPG_MOD 929>;
526 power-domains = <&sysc 526 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
527 resets = <&cpg 929>; 527 resets = <&cpg 929>;
528 dmas = <&dmac1 0x95>, 528 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
529 <&dmac2 0x95>, 529 <&dmac2 0x95>, <&dmac2 0x94>;
530 dma-names = "tx", "rx" 530 dma-names = "tx", "rx", "tx", "rx";
531 i2c-scl-internal-delay 531 i2c-scl-internal-delay-ns = <6>;
532 status = "disabled"; 532 status = "disabled";
533 }; 533 };
534 534
535 i2c3: i2c@e66d0000 { 535 i2c3: i2c@e66d0000 {
536 #address-cells = <1>; 536 #address-cells = <1>;
537 #size-cells = <0>; 537 #size-cells = <0>;
538 compatible = "renesas, 538 compatible = "renesas,i2c-r8a77990",
539 "renesas, 539 "renesas,rcar-gen3-i2c";
540 reg = <0 0xe66d0000 0 540 reg = <0 0xe66d0000 0 0x40>;
541 interrupts = <GIC_SPI 541 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
542 clocks = <&cpg CPG_MOD 542 clocks = <&cpg CPG_MOD 928>;
543 power-domains = <&sysc 543 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
544 resets = <&cpg 928>; 544 resets = <&cpg 928>;
545 dmas = <&dmac0 0x97>, 545 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
546 dma-names = "tx", "rx" 546 dma-names = "tx", "rx";
547 i2c-scl-internal-delay 547 i2c-scl-internal-delay-ns = <110>;
548 status = "disabled"; 548 status = "disabled";
549 }; 549 };
550 550
551 i2c4: i2c@e66d8000 { 551 i2c4: i2c@e66d8000 {
552 #address-cells = <1>; 552 #address-cells = <1>;
553 #size-cells = <0>; 553 #size-cells = <0>;
554 compatible = "renesas, 554 compatible = "renesas,i2c-r8a77990",
555 "renesas, 555 "renesas,rcar-gen3-i2c";
556 reg = <0 0xe66d8000 0 556 reg = <0 0xe66d8000 0 0x40>;
557 interrupts = <GIC_SPI 557 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
558 clocks = <&cpg CPG_MOD 558 clocks = <&cpg CPG_MOD 927>;
559 power-domains = <&sysc 559 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
560 resets = <&cpg 927>; 560 resets = <&cpg 927>;
561 dmas = <&dmac0 0x99>, 561 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
562 dma-names = "tx", "rx" 562 dma-names = "tx", "rx";
563 i2c-scl-internal-delay 563 i2c-scl-internal-delay-ns = <6>;
564 status = "disabled"; 564 status = "disabled";
565 }; 565 };
566 566
567 i2c5: i2c@e66e0000 { 567 i2c5: i2c@e66e0000 {
568 #address-cells = <1>; 568 #address-cells = <1>;
569 #size-cells = <0>; 569 #size-cells = <0>;
570 compatible = "renesas, 570 compatible = "renesas,i2c-r8a77990",
571 "renesas, 571 "renesas,rcar-gen3-i2c";
572 reg = <0 0xe66e0000 0 572 reg = <0 0xe66e0000 0 0x40>;
573 interrupts = <GIC_SPI 573 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
574 clocks = <&cpg CPG_MOD 574 clocks = <&cpg CPG_MOD 919>;
575 power-domains = <&sysc 575 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
576 resets = <&cpg 919>; 576 resets = <&cpg 919>;
577 dmas = <&dmac0 0x9b>, 577 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
578 dma-names = "tx", "rx" 578 dma-names = "tx", "rx";
579 i2c-scl-internal-delay 579 i2c-scl-internal-delay-ns = <6>;
580 status = "disabled"; 580 status = "disabled";
581 }; 581 };
582 582
583 i2c6: i2c@e66e8000 { 583 i2c6: i2c@e66e8000 {
584 #address-cells = <1>; 584 #address-cells = <1>;
585 #size-cells = <0>; 585 #size-cells = <0>;
586 compatible = "renesas, 586 compatible = "renesas,i2c-r8a77990",
587 "renesas, 587 "renesas,rcar-gen3-i2c";
588 reg = <0 0xe66e8000 0 588 reg = <0 0xe66e8000 0 0x40>;
589 interrupts = <GIC_SPI 589 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
590 clocks = <&cpg CPG_MOD 590 clocks = <&cpg CPG_MOD 918>;
591 power-domains = <&sysc 591 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
592 resets = <&cpg 918>; 592 resets = <&cpg 918>;
593 dmas = <&dmac0 0x9d>, 593 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
594 dma-names = "tx", "rx" 594 dma-names = "tx", "rx";
595 i2c-scl-internal-delay 595 i2c-scl-internal-delay-ns = <6>;
596 status = "disabled"; 596 status = "disabled";
597 }; 597 };
598 598
599 i2c7: i2c@e6690000 { 599 i2c7: i2c@e6690000 {
600 #address-cells = <1>; 600 #address-cells = <1>;
601 #size-cells = <0>; 601 #size-cells = <0>;
602 compatible = "renesas, 602 compatible = "renesas,i2c-r8a77990",
603 "renesas, 603 "renesas,rcar-gen3-i2c";
604 reg = <0 0xe6690000 0 604 reg = <0 0xe6690000 0 0x40>;
605 interrupts = <GIC_SPI 605 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
606 clocks = <&cpg CPG_MOD 606 clocks = <&cpg CPG_MOD 1003>;
607 power-domains = <&sysc 607 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
608 resets = <&cpg 1003>; 608 resets = <&cpg 1003>;
609 i2c-scl-internal-delay 609 i2c-scl-internal-delay-ns = <6>;
610 status = "disabled"; 610 status = "disabled";
611 }; 611 };
612 612
613 hscif0: serial@e6540000 { 613 hscif0: serial@e6540000 {
614 compatible = "renesas, 614 compatible = "renesas,hscif-r8a77990",
615 "renesas, 615 "renesas,rcar-gen3-hscif",
616 "renesas, 616 "renesas,hscif";
617 reg = <0 0xe6540000 0 617 reg = <0 0xe6540000 0 0x60>;
618 interrupts = <GIC_SPI 618 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
619 clocks = <&cpg CPG_MOD 619 clocks = <&cpg CPG_MOD 520>,
620 <&cpg CPG_COR 620 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
621 <&scif_clk>; 621 <&scif_clk>;
622 clock-names = "fck", " 622 clock-names = "fck", "brg_int", "scif_clk";
623 dmas = <&dmac1 0x31>, 623 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
624 <&dmac2 0x31>, 624 <&dmac2 0x31>, <&dmac2 0x30>;
625 dma-names = "tx", "rx" 625 dma-names = "tx", "rx", "tx", "rx";
626 power-domains = <&sysc 626 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
627 resets = <&cpg 520>; 627 resets = <&cpg 520>;
628 status = "disabled"; 628 status = "disabled";
629 }; 629 };
630 630
631 hscif1: serial@e6550000 { 631 hscif1: serial@e6550000 {
632 compatible = "renesas, 632 compatible = "renesas,hscif-r8a77990",
633 "renesas, 633 "renesas,rcar-gen3-hscif",
634 "renesas, 634 "renesas,hscif";
635 reg = <0 0xe6550000 0 635 reg = <0 0xe6550000 0 0x60>;
636 interrupts = <GIC_SPI 636 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
637 clocks = <&cpg CPG_MOD 637 clocks = <&cpg CPG_MOD 519>,
638 <&cpg CPG_COR 638 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
639 <&scif_clk>; 639 <&scif_clk>;
640 clock-names = "fck", " 640 clock-names = "fck", "brg_int", "scif_clk";
641 dmas = <&dmac1 0x33>, 641 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
642 <&dmac2 0x33>, 642 <&dmac2 0x33>, <&dmac2 0x32>;
643 dma-names = "tx", "rx" 643 dma-names = "tx", "rx", "tx", "rx";
644 power-domains = <&sysc 644 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
645 resets = <&cpg 519>; 645 resets = <&cpg 519>;
646 status = "disabled"; 646 status = "disabled";
647 }; 647 };
648 648
649 hscif2: serial@e6560000 { 649 hscif2: serial@e6560000 {
650 compatible = "renesas, 650 compatible = "renesas,hscif-r8a77990",
651 "renesas, 651 "renesas,rcar-gen3-hscif",
652 "renesas, 652 "renesas,hscif";
653 reg = <0 0xe6560000 0 653 reg = <0 0xe6560000 0 0x60>;
654 interrupts = <GIC_SPI 654 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
655 clocks = <&cpg CPG_MOD 655 clocks = <&cpg CPG_MOD 518>,
656 <&cpg CPG_COR 656 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
657 <&scif_clk>; 657 <&scif_clk>;
658 clock-names = "fck", " 658 clock-names = "fck", "brg_int", "scif_clk";
659 dmas = <&dmac1 0x35>, 659 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
660 <&dmac2 0x35>, 660 <&dmac2 0x35>, <&dmac2 0x34>;
661 dma-names = "tx", "rx" 661 dma-names = "tx", "rx", "tx", "rx";
662 power-domains = <&sysc 662 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
663 resets = <&cpg 518>; 663 resets = <&cpg 518>;
664 status = "disabled"; 664 status = "disabled";
665 }; 665 };
666 666
667 hscif3: serial@e66a0000 { 667 hscif3: serial@e66a0000 {
668 compatible = "renesas, 668 compatible = "renesas,hscif-r8a77990",
669 "renesas, 669 "renesas,rcar-gen3-hscif",
670 "renesas, 670 "renesas,hscif";
671 reg = <0 0xe66a0000 0 671 reg = <0 0xe66a0000 0 0x60>;
672 interrupts = <GIC_SPI 672 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
673 clocks = <&cpg CPG_MOD 673 clocks = <&cpg CPG_MOD 517>,
674 <&cpg CPG_COR 674 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
675 <&scif_clk>; 675 <&scif_clk>;
676 clock-names = "fck", " 676 clock-names = "fck", "brg_int", "scif_clk";
677 dmas = <&dmac0 0x37>, 677 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
678 dma-names = "tx", "rx" 678 dma-names = "tx", "rx";
679 power-domains = <&sysc 679 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
680 resets = <&cpg 517>; 680 resets = <&cpg 517>;
681 status = "disabled"; 681 status = "disabled";
682 }; 682 };
683 683
684 hscif4: serial@e66b0000 { 684 hscif4: serial@e66b0000 {
685 compatible = "renesas, 685 compatible = "renesas,hscif-r8a77990",
686 "renesas, 686 "renesas,rcar-gen3-hscif",
687 "renesas, 687 "renesas,hscif";
688 reg = <0 0xe66b0000 0 688 reg = <0 0xe66b0000 0 0x60>;
689 interrupts = <GIC_SPI 689 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
690 clocks = <&cpg CPG_MOD 690 clocks = <&cpg CPG_MOD 516>,
691 <&cpg CPG_COR 691 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
692 <&scif_clk>; 692 <&scif_clk>;
693 clock-names = "fck", " 693 clock-names = "fck", "brg_int", "scif_clk";
694 dmas = <&dmac0 0x39>, 694 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
695 dma-names = "tx", "rx" 695 dma-names = "tx", "rx";
696 power-domains = <&sysc 696 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
697 resets = <&cpg 516>; 697 resets = <&cpg 516>;
698 status = "disabled"; 698 status = "disabled";
699 }; 699 };
700 700
701 hsusb: usb@e6590000 { 701 hsusb: usb@e6590000 {
702 compatible = "renesas, 702 compatible = "renesas,usbhs-r8a77990",
703 "renesas, 703 "renesas,rcar-gen3-usbhs";
704 reg = <0 0xe6590000 0 704 reg = <0 0xe6590000 0 0x200>;
705 interrupts = <GIC_SPI 705 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
706 clocks = <&cpg CPG_MOD 706 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
707 dmas = <&usb_dmac0 0>, 707 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
708 <&usb_dmac1 0>, 708 <&usb_dmac1 0>, <&usb_dmac1 1>;
709 dma-names = "ch0", "ch 709 dma-names = "ch0", "ch1", "ch2", "ch3";
710 renesas,buswait = <11> 710 renesas,buswait = <11>;
711 phys = <&usb2_phy0 3>; 711 phys = <&usb2_phy0 3>;
712 phy-names = "usb"; 712 phy-names = "usb";
713 power-domains = <&sysc 713 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
714 resets = <&cpg 704>, < 714 resets = <&cpg 704>, <&cpg 703>;
715 status = "disabled"; 715 status = "disabled";
716 }; 716 };
717 717
718 usb_dmac0: dma-controller@e65a 718 usb_dmac0: dma-controller@e65a0000 {
719 compatible = "renesas, 719 compatible = "renesas,r8a77990-usb-dmac",
720 "renesas, 720 "renesas,usb-dmac";
721 reg = <0 0xe65a0000 0 721 reg = <0 0xe65a0000 0 0x100>;
722 interrupts = <GIC_SPI 722 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
723 <GIC_SPI 723 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
724 interrupt-names = "ch0 724 interrupt-names = "ch0", "ch1";
725 clocks = <&cpg CPG_MOD 725 clocks = <&cpg CPG_MOD 330>;
726 power-domains = <&sysc 726 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
727 resets = <&cpg 330>; 727 resets = <&cpg 330>;
728 #dma-cells = <1>; 728 #dma-cells = <1>;
729 dma-channels = <2>; 729 dma-channels = <2>;
730 }; 730 };
731 731
732 usb_dmac1: dma-controller@e65b 732 usb_dmac1: dma-controller@e65b0000 {
733 compatible = "renesas, 733 compatible = "renesas,r8a77990-usb-dmac",
734 "renesas, 734 "renesas,usb-dmac";
735 reg = <0 0xe65b0000 0 735 reg = <0 0xe65b0000 0 0x100>;
736 interrupts = <GIC_SPI 736 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
737 <GIC_SPI 737 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
738 interrupt-names = "ch0 738 interrupt-names = "ch0", "ch1";
739 clocks = <&cpg CPG_MOD 739 clocks = <&cpg CPG_MOD 331>;
740 power-domains = <&sysc 740 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
741 resets = <&cpg 331>; 741 resets = <&cpg 331>;
742 #dma-cells = <1>; 742 #dma-cells = <1>;
743 dma-channels = <2>; 743 dma-channels = <2>;
744 }; 744 };
745 745
746 arm_cc630p: crypto@e6601000 { 746 arm_cc630p: crypto@e6601000 {
747 compatible = "arm,cryp 747 compatible = "arm,cryptocell-630p-ree";
748 interrupts = <GIC_SPI 748 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
749 reg = <0x0 0xe6601000 749 reg = <0x0 0xe6601000 0 0x1000>;
750 clocks = <&cpg CPG_MOD 750 clocks = <&cpg CPG_MOD 229>;
751 resets = <&cpg 229>; 751 resets = <&cpg 229>;
752 power-domains = <&sysc 752 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
753 }; 753 };
754 754
755 dmac0: dma-controller@e6700000 755 dmac0: dma-controller@e6700000 {
756 compatible = "renesas, 756 compatible = "renesas,dmac-r8a77990",
757 "renesas, 757 "renesas,rcar-dmac";
758 reg = <0 0xe6700000 0 758 reg = <0 0xe6700000 0 0x10000>;
759 interrupts = <GIC_SPI 759 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
760 <GIC_SPI 760 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
761 <GIC_SPI 761 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
762 <GIC_SPI 762 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
763 <GIC_SPI 763 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
764 <GIC_SPI 764 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
765 <GIC_SPI 765 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
766 <GIC_SPI 766 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
767 <GIC_SPI 767 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
768 <GIC_SPI 768 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
769 <GIC_SPI 769 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
770 <GIC_SPI 770 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
771 <GIC_SPI 771 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
772 <GIC_SPI 772 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
773 <GIC_SPI 773 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
774 <GIC_SPI 774 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
775 <GIC_SPI 775 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
776 interrupt-names = "err 776 interrupt-names = "error",
777 "ch0", 777 "ch0", "ch1", "ch2", "ch3",
778 "ch4", 778 "ch4", "ch5", "ch6", "ch7",
779 "ch8", 779 "ch8", "ch9", "ch10", "ch11",
780 "ch12" 780 "ch12", "ch13", "ch14", "ch15";
781 clocks = <&cpg CPG_MOD 781 clocks = <&cpg CPG_MOD 219>;
782 clock-names = "fck"; 782 clock-names = "fck";
783 power-domains = <&sysc 783 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
784 resets = <&cpg 219>; 784 resets = <&cpg 219>;
785 #dma-cells = <1>; 785 #dma-cells = <1>;
786 dma-channels = <16>; 786 dma-channels = <16>;
787 iommus = <&ipmmu_ds0 0 787 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
788 <&ipmmu_ds0 2>, 788 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
789 <&ipmmu_ds0 4>, 789 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
790 <&ipmmu_ds0 6>, 790 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
791 <&ipmmu_ds0 8>, 791 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
792 <&ipmmu_ds0 10> 792 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
793 <&ipmmu_ds0 12> 793 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
794 <&ipmmu_ds0 14> 794 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
795 }; 795 };
796 796
797 dmac1: dma-controller@e7300000 797 dmac1: dma-controller@e7300000 {
798 compatible = "renesas, 798 compatible = "renesas,dmac-r8a77990",
799 "renesas, 799 "renesas,rcar-dmac";
800 reg = <0 0xe7300000 0 800 reg = <0 0xe7300000 0 0x10000>;
801 interrupts = <GIC_SPI 801 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
802 <GIC_SPI 802 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
803 <GIC_SPI 803 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
804 <GIC_SPI 804 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
805 <GIC_SPI 805 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
806 <GIC_SPI 806 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
807 <GIC_SPI 807 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
808 <GIC_SPI 808 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
809 <GIC_SPI 809 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
810 <GIC_SPI 810 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
811 <GIC_SPI 811 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
812 <GIC_SPI 812 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
813 <GIC_SPI 813 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
814 <GIC_SPI 814 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
815 <GIC_SPI 815 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
816 <GIC_SPI 816 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
817 <GIC_SPI 817 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
818 interrupt-names = "err 818 interrupt-names = "error",
819 "ch0", 819 "ch0", "ch1", "ch2", "ch3",
820 "ch4", 820 "ch4", "ch5", "ch6", "ch7",
821 "ch8", 821 "ch8", "ch9", "ch10", "ch11",
822 "ch12" 822 "ch12", "ch13", "ch14", "ch15";
823 clocks = <&cpg CPG_MOD 823 clocks = <&cpg CPG_MOD 218>;
824 clock-names = "fck"; 824 clock-names = "fck";
825 power-domains = <&sysc 825 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
826 resets = <&cpg 218>; 826 resets = <&cpg 218>;
827 #dma-cells = <1>; 827 #dma-cells = <1>;
828 dma-channels = <16>; 828 dma-channels = <16>;
829 iommus = <&ipmmu_ds1 0 829 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
830 <&ipmmu_ds1 2>, 830 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
831 <&ipmmu_ds1 4>, 831 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
832 <&ipmmu_ds1 6>, 832 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
833 <&ipmmu_ds1 8>, 833 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
834 <&ipmmu_ds1 10> 834 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
835 <&ipmmu_ds1 12> 835 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
836 <&ipmmu_ds1 14> 836 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
837 }; 837 };
838 838
839 dmac2: dma-controller@e7310000 839 dmac2: dma-controller@e7310000 {
840 compatible = "renesas, 840 compatible = "renesas,dmac-r8a77990",
841 "renesas, 841 "renesas,rcar-dmac";
842 reg = <0 0xe7310000 0 842 reg = <0 0xe7310000 0 0x10000>;
843 interrupts = <GIC_SPI 843 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
844 <GIC_SPI 844 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
845 <GIC_SPI 845 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
846 <GIC_SPI 846 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
847 <GIC_SPI 847 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
848 <GIC_SPI 848 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
849 <GIC_SPI 849 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
850 <GIC_SPI 850 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
851 <GIC_SPI 851 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
852 <GIC_SPI 852 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
853 <GIC_SPI 853 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
854 <GIC_SPI 854 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
855 <GIC_SPI 855 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
856 <GIC_SPI 856 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
857 <GIC_SPI 857 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
858 <GIC_SPI 858 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
859 <GIC_SPI 859 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
860 interrupt-names = "err 860 interrupt-names = "error",
861 "ch0", 861 "ch0", "ch1", "ch2", "ch3",
862 "ch4", 862 "ch4", "ch5", "ch6", "ch7",
863 "ch8", 863 "ch8", "ch9", "ch10", "ch11",
864 "ch12" 864 "ch12", "ch13", "ch14", "ch15";
865 clocks = <&cpg CPG_MOD 865 clocks = <&cpg CPG_MOD 217>;
866 clock-names = "fck"; 866 clock-names = "fck";
867 power-domains = <&sysc 867 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
868 resets = <&cpg 217>; 868 resets = <&cpg 217>;
869 #dma-cells = <1>; 869 #dma-cells = <1>;
870 dma-channels = <16>; 870 dma-channels = <16>;
871 iommus = <&ipmmu_ds1 1 871 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
872 <&ipmmu_ds1 18> 872 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
873 <&ipmmu_ds1 20> 873 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
874 <&ipmmu_ds1 22> 874 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
875 <&ipmmu_ds1 24> 875 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
876 <&ipmmu_ds1 26> 876 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
877 <&ipmmu_ds1 28> 877 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
878 <&ipmmu_ds1 30> 878 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
879 }; 879 };
880 880
881 ipmmu_ds0: iommu@e6740000 { 881 ipmmu_ds0: iommu@e6740000 {
882 compatible = "renesas, 882 compatible = "renesas,ipmmu-r8a77990";
883 reg = <0 0xe6740000 0 883 reg = <0 0xe6740000 0 0x1000>;
884 renesas,ipmmu-main = < 884 renesas,ipmmu-main = <&ipmmu_mm 0>;
885 power-domains = <&sysc 885 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
886 #iommu-cells = <1>; 886 #iommu-cells = <1>;
887 }; 887 };
888 888
889 ipmmu_ds1: iommu@e7740000 { 889 ipmmu_ds1: iommu@e7740000 {
890 compatible = "renesas, 890 compatible = "renesas,ipmmu-r8a77990";
891 reg = <0 0xe7740000 0 891 reg = <0 0xe7740000 0 0x1000>;
892 renesas,ipmmu-main = < 892 renesas,ipmmu-main = <&ipmmu_mm 1>;
893 power-domains = <&sysc 893 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
894 #iommu-cells = <1>; 894 #iommu-cells = <1>;
895 }; 895 };
896 896
897 ipmmu_hc: iommu@e6570000 { 897 ipmmu_hc: iommu@e6570000 {
898 compatible = "renesas, 898 compatible = "renesas,ipmmu-r8a77990";
899 reg = <0 0xe6570000 0 899 reg = <0 0xe6570000 0 0x1000>;
900 renesas,ipmmu-main = < 900 renesas,ipmmu-main = <&ipmmu_mm 2>;
901 power-domains = <&sysc 901 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
902 #iommu-cells = <1>; 902 #iommu-cells = <1>;
903 }; 903 };
904 904
905 ipmmu_mm: iommu@e67b0000 { 905 ipmmu_mm: iommu@e67b0000 {
906 compatible = "renesas, 906 compatible = "renesas,ipmmu-r8a77990";
907 reg = <0 0xe67b0000 0 907 reg = <0 0xe67b0000 0 0x1000>;
908 interrupts = <GIC_SPI 908 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
909 <GIC_SPI 909 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
910 power-domains = <&sysc 910 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
911 #iommu-cells = <1>; 911 #iommu-cells = <1>;
912 }; 912 };
913 913
914 ipmmu_mp: iommu@ec670000 { 914 ipmmu_mp: iommu@ec670000 {
915 compatible = "renesas, 915 compatible = "renesas,ipmmu-r8a77990";
916 reg = <0 0xec670000 0 916 reg = <0 0xec670000 0 0x1000>;
917 renesas,ipmmu-main = < 917 renesas,ipmmu-main = <&ipmmu_mm 4>;
918 power-domains = <&sysc 918 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
919 #iommu-cells = <1>; 919 #iommu-cells = <1>;
920 }; 920 };
921 921
922 ipmmu_pv0: iommu@fd800000 { 922 ipmmu_pv0: iommu@fd800000 {
923 compatible = "renesas, 923 compatible = "renesas,ipmmu-r8a77990";
924 reg = <0 0xfd800000 0 924 reg = <0 0xfd800000 0 0x1000>;
925 renesas,ipmmu-main = < 925 renesas,ipmmu-main = <&ipmmu_mm 6>;
926 power-domains = <&sysc 926 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
927 #iommu-cells = <1>; 927 #iommu-cells = <1>;
928 }; 928 };
929 929
930 ipmmu_rt: iommu@ffc80000 { 930 ipmmu_rt: iommu@ffc80000 {
931 compatible = "renesas, 931 compatible = "renesas,ipmmu-r8a77990";
932 reg = <0 0xffc80000 0 932 reg = <0 0xffc80000 0 0x1000>;
933 renesas,ipmmu-main = < 933 renesas,ipmmu-main = <&ipmmu_mm 10>;
934 power-domains = <&sysc 934 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
935 #iommu-cells = <1>; 935 #iommu-cells = <1>;
936 }; 936 };
937 937
938 ipmmu_vc0: iommu@fe6b0000 { 938 ipmmu_vc0: iommu@fe6b0000 {
939 compatible = "renesas, 939 compatible = "renesas,ipmmu-r8a77990";
940 reg = <0 0xfe6b0000 0 940 reg = <0 0xfe6b0000 0 0x1000>;
941 renesas,ipmmu-main = < 941 renesas,ipmmu-main = <&ipmmu_mm 12>;
942 power-domains = <&sysc 942 power-domains = <&sysc R8A77990_PD_A3VC>;
943 #iommu-cells = <1>; 943 #iommu-cells = <1>;
944 }; 944 };
945 945
946 ipmmu_vi0: iommu@febd0000 { 946 ipmmu_vi0: iommu@febd0000 {
947 compatible = "renesas, 947 compatible = "renesas,ipmmu-r8a77990";
948 reg = <0 0xfebd0000 0 948 reg = <0 0xfebd0000 0 0x1000>;
949 renesas,ipmmu-main = < 949 renesas,ipmmu-main = <&ipmmu_mm 14>;
950 power-domains = <&sysc 950 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
951 #iommu-cells = <1>; 951 #iommu-cells = <1>;
952 }; 952 };
953 953
954 ipmmu_vp0: iommu@fe990000 { 954 ipmmu_vp0: iommu@fe990000 {
955 compatible = "renesas, 955 compatible = "renesas,ipmmu-r8a77990";
956 reg = <0 0xfe990000 0 956 reg = <0 0xfe990000 0 0x1000>;
957 renesas,ipmmu-main = < 957 renesas,ipmmu-main = <&ipmmu_mm 16>;
958 power-domains = <&sysc 958 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
959 #iommu-cells = <1>; 959 #iommu-cells = <1>;
960 }; 960 };
961 961
962 avb: ethernet@e6800000 { 962 avb: ethernet@e6800000 {
963 compatible = "renesas, 963 compatible = "renesas,etheravb-r8a77990",
964 "renesas, 964 "renesas,etheravb-rcar-gen3";
965 reg = <0 0xe6800000 0 965 reg = <0 0xe6800000 0 0x800>;
966 interrupts = <GIC_SPI 966 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
967 <GIC_SPI 967 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
968 <GIC_SPI 968 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
969 <GIC_SPI 969 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
970 <GIC_SPI 970 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
971 <GIC_SPI 971 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
972 <GIC_SPI 972 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
973 <GIC_SPI 973 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
974 <GIC_SPI 974 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
975 <GIC_SPI 975 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
976 <GIC_SPI 976 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
977 <GIC_SPI 977 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
978 <GIC_SPI 978 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
979 <GIC_SPI 979 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
980 <GIC_SPI 980 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
981 <GIC_SPI 981 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
982 <GIC_SPI 982 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
983 <GIC_SPI 983 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
984 <GIC_SPI 984 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
985 <GIC_SPI 985 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
986 <GIC_SPI 986 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
987 <GIC_SPI 987 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
988 <GIC_SPI 988 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
989 <GIC_SPI 989 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
990 <GIC_SPI 990 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
991 interrupt-names = "ch0 991 interrupt-names = "ch0", "ch1", "ch2", "ch3",
992 "ch4 992 "ch4", "ch5", "ch6", "ch7",
993 "ch8 993 "ch8", "ch9", "ch10", "ch11",
994 "ch1 994 "ch12", "ch13", "ch14", "ch15",
995 "ch1 995 "ch16", "ch17", "ch18", "ch19",
996 "ch2 996 "ch20", "ch21", "ch22", "ch23",
997 "ch2 997 "ch24";
998 clocks = <&cpg CPG_MOD 998 clocks = <&cpg CPG_MOD 812>;
999 clock-names = "fck"; 999 clock-names = "fck";
1000 power-domains = <&sys 1000 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1001 resets = <&cpg 812>; 1001 resets = <&cpg 812>;
1002 phy-mode = "rgmii"; 1002 phy-mode = "rgmii";
1003 rx-internal-delay-ps 1003 rx-internal-delay-ps = <0>;
1004 iommus = <&ipmmu_ds0 1004 iommus = <&ipmmu_ds0 16>;
1005 #address-cells = <1>; 1005 #address-cells = <1>;
1006 #size-cells = <0>; 1006 #size-cells = <0>;
1007 status = "disabled"; 1007 status = "disabled";
1008 }; 1008 };
1009 1009
1010 can0: can@e6c30000 { 1010 can0: can@e6c30000 {
1011 compatible = "renesas 1011 compatible = "renesas,can-r8a77990",
1012 "renesas 1012 "renesas,rcar-gen3-can";
1013 reg = <0 0xe6c30000 0 1013 reg = <0 0xe6c30000 0 0x1000>;
1014 interrupts = <GIC_SPI 1014 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
1015 clocks = <&cpg CPG_MO 1015 clocks = <&cpg CPG_MOD 916>,
1016 <&cpg CPG_CORE 1016 <&cpg CPG_CORE R8A77990_CLK_CANFD>,
1017 <&can_clk>; 1017 <&can_clk>;
1018 clock-names = "clkp1" 1018 clock-names = "clkp1", "clkp2", "can_clk";
1019 assigned-clocks = <&c 1019 assigned-clocks = <&cpg CPG_CORE R8A77990_CLK_CANFD>;
1020 assigned-clock-rates 1020 assigned-clock-rates = <40000000>;
1021 power-domains = <&sys 1021 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1022 resets = <&cpg 916>; 1022 resets = <&cpg 916>;
1023 status = "disabled"; 1023 status = "disabled";
1024 }; 1024 };
1025 1025
1026 can1: can@e6c38000 { 1026 can1: can@e6c38000 {
1027 compatible = "renesas 1027 compatible = "renesas,can-r8a77990",
1028 "renesas 1028 "renesas,rcar-gen3-can";
1029 reg = <0 0xe6c38000 0 1029 reg = <0 0xe6c38000 0 0x1000>;
1030 interrupts = <GIC_SPI 1030 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
1031 clocks = <&cpg CPG_MO 1031 clocks = <&cpg CPG_MOD 915>,
1032 <&cpg CPG_CORE 1032 <&cpg CPG_CORE R8A77990_CLK_CANFD>,
1033 <&can_clk>; 1033 <&can_clk>;
1034 clock-names = "clkp1" 1034 clock-names = "clkp1", "clkp2", "can_clk";
1035 assigned-clocks = <&c 1035 assigned-clocks = <&cpg CPG_CORE R8A77990_CLK_CANFD>;
1036 assigned-clock-rates 1036 assigned-clock-rates = <40000000>;
1037 power-domains = <&sys 1037 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1038 resets = <&cpg 915>; 1038 resets = <&cpg 915>;
1039 status = "disabled"; 1039 status = "disabled";
1040 }; 1040 };
1041 1041
1042 canfd: can@e66c0000 { 1042 canfd: can@e66c0000 {
1043 compatible = "renesas 1043 compatible = "renesas,r8a77990-canfd",
1044 "renesas 1044 "renesas,rcar-gen3-canfd";
1045 reg = <0 0xe66c0000 0 1045 reg = <0 0xe66c0000 0 0x8000>;
1046 interrupts = <GIC_SPI 1046 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
1047 <GIC_SPI 3 1047 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1048 interrupt-names = "ch 1048 interrupt-names = "ch_int", "g_int";
1049 clocks = <&cpg CPG_MO 1049 clocks = <&cpg CPG_MOD 914>,
1050 <&cpg CPG_CORE 1050 <&cpg CPG_CORE R8A77990_CLK_CANFD>,
1051 <&can_clk>; 1051 <&can_clk>;
1052 clock-names = "fck", 1052 clock-names = "fck", "canfd", "can_clk";
1053 assigned-clocks = <&c 1053 assigned-clocks = <&cpg CPG_CORE R8A77990_CLK_CANFD>;
1054 assigned-clock-rates 1054 assigned-clock-rates = <40000000>;
1055 power-domains = <&sys 1055 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1056 resets = <&cpg 914>; 1056 resets = <&cpg 914>;
1057 status = "disabled"; 1057 status = "disabled";
1058 1058
1059 channel0 { 1059 channel0 {
1060 status = "dis 1060 status = "disabled";
1061 }; 1061 };
1062 1062
1063 channel1 { 1063 channel1 {
1064 status = "dis 1064 status = "disabled";
1065 }; 1065 };
1066 }; 1066 };
1067 1067
1068 pwm0: pwm@e6e30000 { 1068 pwm0: pwm@e6e30000 {
1069 compatible = "renesas 1069 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
1070 reg = <0 0xe6e30000 0 1070 reg = <0 0xe6e30000 0 0x8>;
1071 clocks = <&cpg CPG_MO 1071 clocks = <&cpg CPG_MOD 523>;
1072 power-domains = <&sys 1072 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1073 resets = <&cpg 523>; 1073 resets = <&cpg 523>;
1074 #pwm-cells = <2>; 1074 #pwm-cells = <2>;
1075 status = "disabled"; 1075 status = "disabled";
1076 }; 1076 };
1077 1077
1078 pwm1: pwm@e6e31000 { 1078 pwm1: pwm@e6e31000 {
1079 compatible = "renesas 1079 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
1080 reg = <0 0xe6e31000 0 1080 reg = <0 0xe6e31000 0 0x8>;
1081 clocks = <&cpg CPG_MO 1081 clocks = <&cpg CPG_MOD 523>;
1082 power-domains = <&sys 1082 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1083 resets = <&cpg 523>; 1083 resets = <&cpg 523>;
1084 #pwm-cells = <2>; 1084 #pwm-cells = <2>;
1085 status = "disabled"; 1085 status = "disabled";
1086 }; 1086 };
1087 1087
1088 pwm2: pwm@e6e32000 { 1088 pwm2: pwm@e6e32000 {
1089 compatible = "renesas 1089 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
1090 reg = <0 0xe6e32000 0 1090 reg = <0 0xe6e32000 0 0x8>;
1091 clocks = <&cpg CPG_MO 1091 clocks = <&cpg CPG_MOD 523>;
1092 power-domains = <&sys 1092 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1093 resets = <&cpg 523>; 1093 resets = <&cpg 523>;
1094 #pwm-cells = <2>; 1094 #pwm-cells = <2>;
1095 status = "disabled"; 1095 status = "disabled";
1096 }; 1096 };
1097 1097
1098 pwm3: pwm@e6e33000 { 1098 pwm3: pwm@e6e33000 {
1099 compatible = "renesas 1099 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
1100 reg = <0 0xe6e33000 0 1100 reg = <0 0xe6e33000 0 0x8>;
1101 clocks = <&cpg CPG_MO 1101 clocks = <&cpg CPG_MOD 523>;
1102 power-domains = <&sys 1102 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1103 resets = <&cpg 523>; 1103 resets = <&cpg 523>;
1104 #pwm-cells = <2>; 1104 #pwm-cells = <2>;
1105 status = "disabled"; 1105 status = "disabled";
1106 }; 1106 };
1107 1107
1108 pwm4: pwm@e6e34000 { 1108 pwm4: pwm@e6e34000 {
1109 compatible = "renesas 1109 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
1110 reg = <0 0xe6e34000 0 1110 reg = <0 0xe6e34000 0 0x8>;
1111 clocks = <&cpg CPG_MO 1111 clocks = <&cpg CPG_MOD 523>;
1112 power-domains = <&sys 1112 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1113 resets = <&cpg 523>; 1113 resets = <&cpg 523>;
1114 #pwm-cells = <2>; 1114 #pwm-cells = <2>;
1115 status = "disabled"; 1115 status = "disabled";
1116 }; 1116 };
1117 1117
1118 pwm5: pwm@e6e35000 { 1118 pwm5: pwm@e6e35000 {
1119 compatible = "renesas 1119 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
1120 reg = <0 0xe6e35000 0 1120 reg = <0 0xe6e35000 0 0x8>;
1121 clocks = <&cpg CPG_MO 1121 clocks = <&cpg CPG_MOD 523>;
1122 power-domains = <&sys 1122 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1123 resets = <&cpg 523>; 1123 resets = <&cpg 523>;
1124 #pwm-cells = <2>; 1124 #pwm-cells = <2>;
1125 status = "disabled"; 1125 status = "disabled";
1126 }; 1126 };
1127 1127
1128 pwm6: pwm@e6e36000 { 1128 pwm6: pwm@e6e36000 {
1129 compatible = "renesas 1129 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
1130 reg = <0 0xe6e36000 0 1130 reg = <0 0xe6e36000 0 0x8>;
1131 clocks = <&cpg CPG_MO 1131 clocks = <&cpg CPG_MOD 523>;
1132 power-domains = <&sys 1132 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1133 resets = <&cpg 523>; 1133 resets = <&cpg 523>;
1134 #pwm-cells = <2>; 1134 #pwm-cells = <2>;
1135 status = "disabled"; 1135 status = "disabled";
1136 }; 1136 };
1137 1137
1138 scif0: serial@e6e60000 { 1138 scif0: serial@e6e60000 {
1139 compatible = "renesas 1139 compatible = "renesas,scif-r8a77990",
1140 "renesas 1140 "renesas,rcar-gen3-scif", "renesas,scif";
1141 reg = <0 0xe6e60000 0 1141 reg = <0 0xe6e60000 0 64>;
1142 interrupts = <GIC_SPI 1142 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
1143 clocks = <&cpg CPG_MO 1143 clocks = <&cpg CPG_MOD 207>,
1144 <&cpg CPG_CO 1144 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
1145 <&scif_clk>; 1145 <&scif_clk>;
1146 clock-names = "fck", 1146 clock-names = "fck", "brg_int", "scif_clk";
1147 dmas = <&dmac1 0x51>, 1147 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1148 <&dmac2 0x51>, 1148 <&dmac2 0x51>, <&dmac2 0x50>;
1149 dma-names = "tx", "rx 1149 dma-names = "tx", "rx", "tx", "rx";
1150 power-domains = <&sys 1150 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1151 resets = <&cpg 207>; 1151 resets = <&cpg 207>;
1152 status = "disabled"; 1152 status = "disabled";
1153 }; 1153 };
1154 1154
1155 scif1: serial@e6e68000 { 1155 scif1: serial@e6e68000 {
1156 compatible = "renesas 1156 compatible = "renesas,scif-r8a77990",
1157 "renesas 1157 "renesas,rcar-gen3-scif", "renesas,scif";
1158 reg = <0 0xe6e68000 0 1158 reg = <0 0xe6e68000 0 64>;
1159 interrupts = <GIC_SPI 1159 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
1160 clocks = <&cpg CPG_MO 1160 clocks = <&cpg CPG_MOD 206>,
1161 <&cpg CPG_CO 1161 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
1162 <&scif_clk>; 1162 <&scif_clk>;
1163 clock-names = "fck", 1163 clock-names = "fck", "brg_int", "scif_clk";
1164 dmas = <&dmac1 0x53>, 1164 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1165 <&dmac2 0x53>, 1165 <&dmac2 0x53>, <&dmac2 0x52>;
1166 dma-names = "tx", "rx 1166 dma-names = "tx", "rx", "tx", "rx";
1167 power-domains = <&sys 1167 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1168 resets = <&cpg 206>; 1168 resets = <&cpg 206>;
1169 status = "disabled"; 1169 status = "disabled";
1170 }; 1170 };
1171 1171
1172 scif2: serial@e6e88000 { 1172 scif2: serial@e6e88000 {
1173 compatible = "renesas 1173 compatible = "renesas,scif-r8a77990",
1174 "renesas 1174 "renesas,rcar-gen3-scif", "renesas,scif";
1175 reg = <0 0xe6e88000 0 1175 reg = <0 0xe6e88000 0 64>;
1176 interrupts = <GIC_SPI 1176 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
1177 clocks = <&cpg CPG_MO 1177 clocks = <&cpg CPG_MOD 310>,
1178 <&cpg CPG_CO 1178 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
1179 <&scif_clk>; 1179 <&scif_clk>;
1180 clock-names = "fck", 1180 clock-names = "fck", "brg_int", "scif_clk";
1181 dmas = <&dmac1 0x13>, 1181 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1182 <&dmac2 0x13>, 1182 <&dmac2 0x13>, <&dmac2 0x12>;
1183 dma-names = "tx", "rx 1183 dma-names = "tx", "rx", "tx", "rx";
1184 power-domains = <&sys 1184 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1185 resets = <&cpg 310>; 1185 resets = <&cpg 310>;
1186 status = "disabled"; 1186 status = "disabled";
1187 }; 1187 };
1188 1188
1189 scif3: serial@e6c50000 { 1189 scif3: serial@e6c50000 {
1190 compatible = "renesas 1190 compatible = "renesas,scif-r8a77990",
1191 "renesas 1191 "renesas,rcar-gen3-scif", "renesas,scif";
1192 reg = <0 0xe6c50000 0 1192 reg = <0 0xe6c50000 0 64>;
1193 interrupts = <GIC_SPI 1193 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1194 clocks = <&cpg CPG_MO 1194 clocks = <&cpg CPG_MOD 204>,
1195 <&cpg CPG_CO 1195 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
1196 <&scif_clk>; 1196 <&scif_clk>;
1197 clock-names = "fck", 1197 clock-names = "fck", "brg_int", "scif_clk";
1198 dmas = <&dmac0 0x57>, 1198 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1199 dma-names = "tx", "rx 1199 dma-names = "tx", "rx";
1200 power-domains = <&sys 1200 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1201 resets = <&cpg 204>; 1201 resets = <&cpg 204>;
1202 status = "disabled"; 1202 status = "disabled";
1203 }; 1203 };
1204 1204
1205 scif4: serial@e6c40000 { 1205 scif4: serial@e6c40000 {
1206 compatible = "renesas 1206 compatible = "renesas,scif-r8a77990",
1207 "renesas 1207 "renesas,rcar-gen3-scif", "renesas,scif";
1208 reg = <0 0xe6c40000 0 1208 reg = <0 0xe6c40000 0 64>;
1209 interrupts = <GIC_SPI 1209 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1210 clocks = <&cpg CPG_MO 1210 clocks = <&cpg CPG_MOD 203>,
1211 <&cpg CPG_CO 1211 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
1212 <&scif_clk>; 1212 <&scif_clk>;
1213 clock-names = "fck", 1213 clock-names = "fck", "brg_int", "scif_clk";
1214 dmas = <&dmac0 0x59>, 1214 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1215 dma-names = "tx", "rx 1215 dma-names = "tx", "rx";
1216 power-domains = <&sys 1216 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1217 resets = <&cpg 203>; 1217 resets = <&cpg 203>;
1218 status = "disabled"; 1218 status = "disabled";
1219 }; 1219 };
1220 1220
1221 scif5: serial@e6f30000 { 1221 scif5: serial@e6f30000 {
1222 compatible = "renesas 1222 compatible = "renesas,scif-r8a77990",
1223 "renesas 1223 "renesas,rcar-gen3-scif", "renesas,scif";
1224 reg = <0 0xe6f30000 0 1224 reg = <0 0xe6f30000 0 64>;
1225 interrupts = <GIC_SPI 1225 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1226 clocks = <&cpg CPG_MO 1226 clocks = <&cpg CPG_MOD 202>,
1227 <&cpg CPG_CO 1227 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
1228 <&scif_clk>; 1228 <&scif_clk>;
1229 clock-names = "fck", 1229 clock-names = "fck", "brg_int", "scif_clk";
1230 dmas = <&dmac0 0x5b>, 1230 dmas = <&dmac0 0x5b>, <&dmac0 0x5a>;
1231 dma-names = "tx", "rx 1231 dma-names = "tx", "rx";
1232 power-domains = <&sys 1232 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1233 resets = <&cpg 202>; 1233 resets = <&cpg 202>;
1234 status = "disabled"; 1234 status = "disabled";
1235 }; 1235 };
1236 1236
1237 msiof0: spi@e6e90000 { 1237 msiof0: spi@e6e90000 {
1238 compatible = "renesas 1238 compatible = "renesas,msiof-r8a77990",
1239 "renesas 1239 "renesas,rcar-gen3-msiof";
1240 reg = <0 0xe6e90000 0 1240 reg = <0 0xe6e90000 0 0x0064>;
1241 interrupts = <GIC_SPI 1241 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1242 clocks = <&cpg CPG_MO 1242 clocks = <&cpg CPG_MOD 211>;
1243 dmas = <&dmac1 0x41>, 1243 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1244 <&dmac2 0x41>, 1244 <&dmac2 0x41>, <&dmac2 0x40>;
1245 dma-names = "tx", "rx 1245 dma-names = "tx", "rx", "tx", "rx";
1246 power-domains = <&sys 1246 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1247 resets = <&cpg 211>; 1247 resets = <&cpg 211>;
1248 #address-cells = <1>; 1248 #address-cells = <1>;
1249 #size-cells = <0>; 1249 #size-cells = <0>;
1250 status = "disabled"; 1250 status = "disabled";
1251 }; 1251 };
1252 1252
1253 msiof1: spi@e6ea0000 { 1253 msiof1: spi@e6ea0000 {
1254 compatible = "renesas 1254 compatible = "renesas,msiof-r8a77990",
1255 "renesas 1255 "renesas,rcar-gen3-msiof";
1256 reg = <0 0xe6ea0000 0 1256 reg = <0 0xe6ea0000 0 0x0064>;
1257 interrupts = <GIC_SPI 1257 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1258 clocks = <&cpg CPG_MO 1258 clocks = <&cpg CPG_MOD 210>;
1259 dmas = <&dmac0 0x43>, 1259 dmas = <&dmac0 0x43>, <&dmac0 0x42>;
1260 dma-names = "tx", "rx 1260 dma-names = "tx", "rx";
1261 power-domains = <&sys 1261 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1262 resets = <&cpg 210>; 1262 resets = <&cpg 210>;
1263 #address-cells = <1>; 1263 #address-cells = <1>;
1264 #size-cells = <0>; 1264 #size-cells = <0>;
1265 status = "disabled"; 1265 status = "disabled";
1266 }; 1266 };
1267 1267
1268 msiof2: spi@e6c00000 { 1268 msiof2: spi@e6c00000 {
1269 compatible = "renesas 1269 compatible = "renesas,msiof-r8a77990",
1270 "renesas 1270 "renesas,rcar-gen3-msiof";
1271 reg = <0 0xe6c00000 0 1271 reg = <0 0xe6c00000 0 0x0064>;
1272 interrupts = <GIC_SPI 1272 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1273 clocks = <&cpg CPG_MO 1273 clocks = <&cpg CPG_MOD 209>;
1274 dmas = <&dmac0 0x45>, 1274 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1275 dma-names = "tx", "rx 1275 dma-names = "tx", "rx";
1276 power-domains = <&sys 1276 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1277 resets = <&cpg 209>; 1277 resets = <&cpg 209>;
1278 #address-cells = <1>; 1278 #address-cells = <1>;
1279 #size-cells = <0>; 1279 #size-cells = <0>;
1280 status = "disabled"; 1280 status = "disabled";
1281 }; 1281 };
1282 1282
1283 msiof3: spi@e6c10000 { 1283 msiof3: spi@e6c10000 {
1284 compatible = "renesas 1284 compatible = "renesas,msiof-r8a77990",
1285 "renesas 1285 "renesas,rcar-gen3-msiof";
1286 reg = <0 0xe6c10000 0 1286 reg = <0 0xe6c10000 0 0x0064>;
1287 interrupts = <GIC_SPI 1287 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1288 clocks = <&cpg CPG_MO 1288 clocks = <&cpg CPG_MOD 208>;
1289 dmas = <&dmac0 0x47>, 1289 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1290 dma-names = "tx", "rx 1290 dma-names = "tx", "rx";
1291 power-domains = <&sys 1291 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1292 resets = <&cpg 208>; 1292 resets = <&cpg 208>;
1293 #address-cells = <1>; 1293 #address-cells = <1>;
1294 #size-cells = <0>; 1294 #size-cells = <0>;
1295 status = "disabled"; 1295 status = "disabled";
1296 }; 1296 };
1297 1297
1298 vin4: video@e6ef4000 { 1298 vin4: video@e6ef4000 {
1299 compatible = "renesas 1299 compatible = "renesas,vin-r8a77990";
1300 reg = <0 0xe6ef4000 0 1300 reg = <0 0xe6ef4000 0 0x1000>;
1301 interrupts = <GIC_SPI 1301 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
1302 clocks = <&cpg CPG_MO 1302 clocks = <&cpg CPG_MOD 807>;
1303 power-domains = <&sys 1303 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1304 resets = <&cpg 807>; 1304 resets = <&cpg 807>;
1305 renesas,id = <4>; 1305 renesas,id = <4>;
1306 status = "disabled"; 1306 status = "disabled";
1307 1307
1308 ports { 1308 ports {
1309 #address-cell 1309 #address-cells = <1>;
1310 #size-cells = 1310 #size-cells = <0>;
1311 1311
1312 port@1 { 1312 port@1 {
1313 #addr 1313 #address-cells = <1>;
1314 #size 1314 #size-cells = <0>;
1315 1315
1316 reg = 1316 reg = <1>;
1317 1317
1318 vin4c 1318 vin4csi40: endpoint@2 {
1319 1319 reg = <2>;
1320 1320 remote-endpoint = <&csi40vin4>;
1321 }; 1321 };
1322 }; 1322 };
1323 }; 1323 };
1324 }; 1324 };
1325 1325
1326 vin5: video@e6ef5000 { 1326 vin5: video@e6ef5000 {
1327 compatible = "renesas 1327 compatible = "renesas,vin-r8a77990";
1328 reg = <0 0xe6ef5000 0 1328 reg = <0 0xe6ef5000 0 0x1000>;
1329 interrupts = <GIC_SPI 1329 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
1330 clocks = <&cpg CPG_MO 1330 clocks = <&cpg CPG_MOD 806>;
1331 power-domains = <&sys 1331 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1332 resets = <&cpg 806>; 1332 resets = <&cpg 806>;
1333 renesas,id = <5>; 1333 renesas,id = <5>;
1334 status = "disabled"; 1334 status = "disabled";
1335 1335
1336 ports { 1336 ports {
1337 #address-cell 1337 #address-cells = <1>;
1338 #size-cells = 1338 #size-cells = <0>;
1339 1339
1340 port@1 { 1340 port@1 {
1341 #addr 1341 #address-cells = <1>;
1342 #size 1342 #size-cells = <0>;
1343 1343
1344 reg = 1344 reg = <1>;
1345 1345
1346 vin5c 1346 vin5csi40: endpoint@2 {
1347 1347 reg = <2>;
1348 1348 remote-endpoint = <&csi40vin5>;
1349 }; 1349 };
1350 }; 1350 };
1351 }; 1351 };
1352 }; 1352 };
1353 1353
1354 drif00: rif@e6f40000 { 1354 drif00: rif@e6f40000 {
1355 compatible = "renesas 1355 compatible = "renesas,r8a77990-drif",
1356 "renesas 1356 "renesas,rcar-gen3-drif";
1357 reg = <0 0xe6f40000 0 1357 reg = <0 0xe6f40000 0 0x84>;
1358 interrupts = <GIC_SPI 1358 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1359 clocks = <&cpg CPG_MO 1359 clocks = <&cpg CPG_MOD 515>;
1360 clock-names = "fck"; 1360 clock-names = "fck";
1361 dmas = <&dmac1 0x20>, 1361 dmas = <&dmac1 0x20>, <&dmac2 0x20>;
1362 dma-names = "rx", "rx 1362 dma-names = "rx", "rx";
1363 power-domains = <&sys 1363 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1364 resets = <&cpg 515>; 1364 resets = <&cpg 515>;
1365 renesas,bonding = <&d 1365 renesas,bonding = <&drif01>;
1366 status = "disabled"; 1366 status = "disabled";
1367 }; 1367 };
1368 1368
1369 drif01: rif@e6f50000 { 1369 drif01: rif@e6f50000 {
1370 compatible = "renesas 1370 compatible = "renesas,r8a77990-drif",
1371 "renesas 1371 "renesas,rcar-gen3-drif";
1372 reg = <0 0xe6f50000 0 1372 reg = <0 0xe6f50000 0 0x84>;
1373 interrupts = <GIC_SPI 1373 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1374 clocks = <&cpg CPG_MO 1374 clocks = <&cpg CPG_MOD 514>;
1375 clock-names = "fck"; 1375 clock-names = "fck";
1376 dmas = <&dmac1 0x22>, 1376 dmas = <&dmac1 0x22>, <&dmac2 0x22>;
1377 dma-names = "rx", "rx 1377 dma-names = "rx", "rx";
1378 power-domains = <&sys 1378 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1379 resets = <&cpg 514>; 1379 resets = <&cpg 514>;
1380 renesas,bonding = <&d 1380 renesas,bonding = <&drif00>;
1381 status = "disabled"; 1381 status = "disabled";
1382 }; 1382 };
1383 1383
1384 drif10: rif@e6f60000 { 1384 drif10: rif@e6f60000 {
1385 compatible = "renesas 1385 compatible = "renesas,r8a77990-drif",
1386 "renesas 1386 "renesas,rcar-gen3-drif";
1387 reg = <0 0xe6f60000 0 1387 reg = <0 0xe6f60000 0 0x84>;
1388 interrupts = <GIC_SPI 1388 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1389 clocks = <&cpg CPG_MO 1389 clocks = <&cpg CPG_MOD 513>;
1390 clock-names = "fck"; 1390 clock-names = "fck";
1391 dmas = <&dmac1 0x24>, 1391 dmas = <&dmac1 0x24>, <&dmac2 0x24>;
1392 dma-names = "rx", "rx 1392 dma-names = "rx", "rx";
1393 power-domains = <&sys 1393 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1394 resets = <&cpg 513>; 1394 resets = <&cpg 513>;
1395 renesas,bonding = <&d 1395 renesas,bonding = <&drif11>;
1396 status = "disabled"; 1396 status = "disabled";
1397 }; 1397 };
1398 1398
1399 drif11: rif@e6f70000 { 1399 drif11: rif@e6f70000 {
1400 compatible = "renesas 1400 compatible = "renesas,r8a77990-drif",
1401 "renesas 1401 "renesas,rcar-gen3-drif";
1402 reg = <0 0xe6f70000 0 1402 reg = <0 0xe6f70000 0 0x84>;
1403 interrupts = <GIC_SPI 1403 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1404 clocks = <&cpg CPG_MO 1404 clocks = <&cpg CPG_MOD 512>;
1405 clock-names = "fck"; 1405 clock-names = "fck";
1406 dmas = <&dmac1 0x26>, 1406 dmas = <&dmac1 0x26>, <&dmac2 0x26>;
1407 dma-names = "rx", "rx 1407 dma-names = "rx", "rx";
1408 power-domains = <&sys 1408 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1409 resets = <&cpg 512>; 1409 resets = <&cpg 512>;
1410 renesas,bonding = <&d 1410 renesas,bonding = <&drif10>;
1411 status = "disabled"; 1411 status = "disabled";
1412 }; 1412 };
1413 1413
1414 drif20: rif@e6f80000 { 1414 drif20: rif@e6f80000 {
1415 compatible = "renesas 1415 compatible = "renesas,r8a77990-drif",
1416 "renesas 1416 "renesas,rcar-gen3-drif";
1417 reg = <0 0xe6f80000 0 1417 reg = <0 0xe6f80000 0 0x84>;
1418 interrupts = <GIC_SPI 1418 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1419 clocks = <&cpg CPG_MO 1419 clocks = <&cpg CPG_MOD 511>;
1420 clock-names = "fck"; 1420 clock-names = "fck";
1421 dmas = <&dmac0 0x28>; 1421 dmas = <&dmac0 0x28>;
1422 dma-names = "rx"; 1422 dma-names = "rx";
1423 power-domains = <&sys 1423 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1424 resets = <&cpg 511>; 1424 resets = <&cpg 511>;
1425 renesas,bonding = <&d 1425 renesas,bonding = <&drif21>;
1426 status = "disabled"; 1426 status = "disabled";
1427 }; 1427 };
1428 1428
1429 drif21: rif@e6f90000 { 1429 drif21: rif@e6f90000 {
1430 compatible = "renesas 1430 compatible = "renesas,r8a77990-drif",
1431 "renesas 1431 "renesas,rcar-gen3-drif";
1432 reg = <0 0xe6f90000 0 1432 reg = <0 0xe6f90000 0 0x84>;
1433 interrupts = <GIC_SPI 1433 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1434 clocks = <&cpg CPG_MO 1434 clocks = <&cpg CPG_MOD 510>;
1435 clock-names = "fck"; 1435 clock-names = "fck";
1436 dmas = <&dmac0 0x2a>; 1436 dmas = <&dmac0 0x2a>;
1437 dma-names = "rx"; 1437 dma-names = "rx";
1438 power-domains = <&sys 1438 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1439 resets = <&cpg 510>; 1439 resets = <&cpg 510>;
1440 renesas,bonding = <&d 1440 renesas,bonding = <&drif20>;
1441 status = "disabled"; 1441 status = "disabled";
1442 }; 1442 };
1443 1443
1444 drif30: rif@e6fa0000 { 1444 drif30: rif@e6fa0000 {
1445 compatible = "renesas 1445 compatible = "renesas,r8a77990-drif",
1446 "renesas 1446 "renesas,rcar-gen3-drif";
1447 reg = <0 0xe6fa0000 0 1447 reg = <0 0xe6fa0000 0 0x84>;
1448 interrupts = <GIC_SPI 1448 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1449 clocks = <&cpg CPG_MO 1449 clocks = <&cpg CPG_MOD 509>;
1450 clock-names = "fck"; 1450 clock-names = "fck";
1451 dmas = <&dmac0 0x2c>; 1451 dmas = <&dmac0 0x2c>;
1452 dma-names = "rx"; 1452 dma-names = "rx";
1453 power-domains = <&sys 1453 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1454 resets = <&cpg 509>; 1454 resets = <&cpg 509>;
1455 renesas,bonding = <&d 1455 renesas,bonding = <&drif31>;
1456 status = "disabled"; 1456 status = "disabled";
1457 }; 1457 };
1458 1458
1459 drif31: rif@e6fb0000 { 1459 drif31: rif@e6fb0000 {
1460 compatible = "renesas 1460 compatible = "renesas,r8a77990-drif",
1461 "renesas 1461 "renesas,rcar-gen3-drif";
1462 reg = <0 0xe6fb0000 0 1462 reg = <0 0xe6fb0000 0 0x84>;
1463 interrupts = <GIC_SPI 1463 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1464 clocks = <&cpg CPG_MO 1464 clocks = <&cpg CPG_MOD 508>;
1465 clock-names = "fck"; 1465 clock-names = "fck";
1466 dmas = <&dmac0 0x2e>; 1466 dmas = <&dmac0 0x2e>;
1467 dma-names = "rx"; 1467 dma-names = "rx";
1468 power-domains = <&sys 1468 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1469 resets = <&cpg 508>; 1469 resets = <&cpg 508>;
1470 renesas,bonding = <&d 1470 renesas,bonding = <&drif30>;
1471 status = "disabled"; 1471 status = "disabled";
1472 }; 1472 };
1473 1473
1474 rcar_sound: sound@ec500000 { 1474 rcar_sound: sound@ec500000 {
1475 /* 1475 /*
1476 * #sound-dai-cells i 1476 * #sound-dai-cells is required if simple-card
1477 * 1477 *
1478 * Single DAI : #soun 1478 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1479 * Multi DAI : #soun 1479 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1480 */ 1480 */
1481 /* 1481 /*
1482 * #clock-cells is re 1482 * #clock-cells is required for audio_clkout0/1/2/3
1483 * 1483 *
1484 * clkout : #cl 1484 * clkout : #clock-cells = <0>; <&rcar_sound>;
1485 * clkout0/1/2/3: #cl 1485 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
1486 */ 1486 */
1487 compatible = "renesas 1487 compatible = "renesas,rcar_sound-r8a77990", "renesas,rcar_sound-gen3";
1488 reg = <0 0xec500000 0 1488 reg = <0 0xec500000 0 0x1000>, /* SCU */
1489 <0 0xec5a0000 0 1489 <0 0xec5a0000 0 0x100>, /* ADG */
1490 <0 0xec540000 0 1490 <0 0xec540000 0 0x1000>, /* SSIU */
1491 <0 0xec541000 0 1491 <0 0xec541000 0 0x280>, /* SSI */
1492 <0 0xec760000 0 1492 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
1493 reg-names = "scu", "a 1493 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1494 1494
1495 clocks = <&cpg CPG_MO 1495 clocks = <&cpg CPG_MOD 1005>,
1496 <&cpg CPG_MO 1496 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
1497 <&cpg CPG_MO 1497 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
1498 <&cpg CPG_MO 1498 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
1499 <&cpg CPG_MO 1499 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
1500 <&cpg CPG_MO 1500 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
1501 <&cpg CPG_MO 1501 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
1502 <&cpg CPG_MO 1502 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
1503 <&cpg CPG_MO 1503 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
1504 <&cpg CPG_MO 1504 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
1505 <&cpg CPG_MO 1505 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
1506 <&cpg CPG_MO 1506 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1507 <&cpg CPG_MO 1507 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1508 <&cpg CPG_MO 1508 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
1509 <&audio_clk_ 1509 <&audio_clk_a>, <&audio_clk_b>,
1510 <&audio_clk_ 1510 <&audio_clk_c>,
1511 <&cpg CPG_MO 1511 <&cpg CPG_MOD 922>;
1512 clock-names = "ssi-al 1512 clock-names = "ssi-all",
1513 "ssi.9" 1513 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1514 "ssi.5" 1514 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1515 "ssi.1" 1515 "ssi.1", "ssi.0",
1516 "src.9" 1516 "src.9", "src.8", "src.7", "src.6",
1517 "src.5" 1517 "src.5", "src.4", "src.3", "src.2",
1518 "src.1" 1518 "src.1", "src.0",
1519 "mix.1" 1519 "mix.1", "mix.0",
1520 "ctu.1" 1520 "ctu.1", "ctu.0",
1521 "dvc.0" 1521 "dvc.0", "dvc.1",
1522 "clk_a" 1522 "clk_a", "clk_b", "clk_c", "clk_i";
1523 power-domains = <&sys 1523 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1524 resets = <&cpg 1005>, 1524 resets = <&cpg 1005>,
1525 <&cpg 1006>, 1525 <&cpg 1006>, <&cpg 1007>,
1526 <&cpg 1008>, 1526 <&cpg 1008>, <&cpg 1009>,
1527 <&cpg 1010>, 1527 <&cpg 1010>, <&cpg 1011>,
1528 <&cpg 1012>, 1528 <&cpg 1012>, <&cpg 1013>,
1529 <&cpg 1014>, 1529 <&cpg 1014>, <&cpg 1015>;
1530 reset-names = "ssi-al 1530 reset-names = "ssi-all",
1531 "ssi.9" 1531 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1532 "ssi.5" 1532 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1533 "ssi.1" 1533 "ssi.1", "ssi.0";
1534 status = "disabled"; 1534 status = "disabled";
1535 1535
1536 rcar_sound,ctu { 1536 rcar_sound,ctu {
1537 ctu00: ctu-0 1537 ctu00: ctu-0 { };
1538 ctu01: ctu-1 1538 ctu01: ctu-1 { };
1539 ctu02: ctu-2 1539 ctu02: ctu-2 { };
1540 ctu03: ctu-3 1540 ctu03: ctu-3 { };
1541 ctu10: ctu-4 1541 ctu10: ctu-4 { };
1542 ctu11: ctu-5 1542 ctu11: ctu-5 { };
1543 ctu12: ctu-6 1543 ctu12: ctu-6 { };
1544 ctu13: ctu-7 1544 ctu13: ctu-7 { };
1545 }; 1545 };
1546 1546
1547 rcar_sound,dvc { 1547 rcar_sound,dvc {
1548 dvc0: dvc-0 { 1548 dvc0: dvc-0 {
1549 dmas 1549 dmas = <&audma0 0xbc>;
1550 dma-n 1550 dma-names = "tx";
1551 }; 1551 };
1552 dvc1: dvc-1 { 1552 dvc1: dvc-1 {
1553 dmas 1553 dmas = <&audma0 0xbe>;
1554 dma-n 1554 dma-names = "tx";
1555 }; 1555 };
1556 }; 1556 };
1557 1557
1558 rcar_sound,mix { 1558 rcar_sound,mix {
1559 mix0: mix-0 { 1559 mix0: mix-0 { };
1560 mix1: mix-1 { 1560 mix1: mix-1 { };
1561 }; 1561 };
1562 1562
1563 rcar_sound,src { 1563 rcar_sound,src {
1564 src0: src-0 { 1564 src0: src-0 {
1565 inter 1565 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1566 dmas 1566 dmas = <&audma0 0x85>, <&audma0 0x9a>;
1567 dma-n 1567 dma-names = "rx", "tx";
1568 }; 1568 };
1569 src1: src-1 { 1569 src1: src-1 {
1570 inter 1570 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1571 dmas 1571 dmas = <&audma0 0x87>, <&audma0 0x9c>;
1572 dma-n 1572 dma-names = "rx", "tx";
1573 }; 1573 };
1574 src2: src-2 { 1574 src2: src-2 {
1575 inter 1575 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1576 dmas 1576 dmas = <&audma0 0x89>, <&audma0 0x9e>;
1577 dma-n 1577 dma-names = "rx", "tx";
1578 }; 1578 };
1579 src3: src-3 { 1579 src3: src-3 {
1580 inter 1580 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1581 dmas 1581 dmas = <&audma0 0x8b>, <&audma0 0xa0>;
1582 dma-n 1582 dma-names = "rx", "tx";
1583 }; 1583 };
1584 src4: src-4 { 1584 src4: src-4 {
1585 inter 1585 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1586 dmas 1586 dmas = <&audma0 0x8d>, <&audma0 0xb0>;
1587 dma-n 1587 dma-names = "rx", "tx";
1588 }; 1588 };
1589 src5: src-5 { 1589 src5: src-5 {
1590 inter 1590 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1591 dmas 1591 dmas = <&audma0 0x8f>, <&audma0 0xb2>;
1592 dma-n 1592 dma-names = "rx", "tx";
1593 }; 1593 };
1594 src6: src-6 { 1594 src6: src-6 {
1595 inter 1595 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1596 dmas 1596 dmas = <&audma0 0x91>, <&audma0 0xb4>;
1597 dma-n 1597 dma-names = "rx", "tx";
1598 }; 1598 };
1599 src7: src-7 { 1599 src7: src-7 {
1600 inter 1600 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1601 dmas 1601 dmas = <&audma0 0x93>, <&audma0 0xb6>;
1602 dma-n 1602 dma-names = "rx", "tx";
1603 }; 1603 };
1604 src8: src-8 { 1604 src8: src-8 {
1605 inter 1605 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1606 dmas 1606 dmas = <&audma0 0x95>, <&audma0 0xb8>;
1607 dma-n 1607 dma-names = "rx", "tx";
1608 }; 1608 };
1609 src9: src-9 { 1609 src9: src-9 {
1610 inter 1610 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
1611 dmas 1611 dmas = <&audma0 0x97>, <&audma0 0xba>;
1612 dma-n 1612 dma-names = "rx", "tx";
1613 }; 1613 };
1614 }; 1614 };
1615 1615
1616 rcar_sound,ssi { 1616 rcar_sound,ssi {
1617 ssi0: ssi-0 { 1617 ssi0: ssi-0 {
1618 inter 1618 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
1619 dmas 1619 dmas = <&audma0 0x01>, <&audma0 0x02>,
1620 1620 <&audma0 0x15>, <&audma0 0x16>;
1621 dma-n 1621 dma-names = "rx", "tx", "rxu", "txu";
1622 }; 1622 };
1623 ssi1: ssi-1 { 1623 ssi1: ssi-1 {
1624 inter 1624 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
1625 dmas 1625 dmas = <&audma0 0x03>, <&audma0 0x04>,
1626 1626 <&audma0 0x49>, <&audma0 0x4a>;
1627 dma-n 1627 dma-names = "rx", "tx", "rxu", "txu";
1628 }; 1628 };
1629 ssi2: ssi-2 { 1629 ssi2: ssi-2 {
1630 inter 1630 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
1631 dmas 1631 dmas = <&audma0 0x05>, <&audma0 0x06>,
1632 1632 <&audma0 0x63>, <&audma0 0x64>;
1633 dma-n 1633 dma-names = "rx", "tx", "rxu", "txu";
1634 }; 1634 };
1635 ssi3: ssi-3 { 1635 ssi3: ssi-3 {
1636 inter 1636 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1637 dmas 1637 dmas = <&audma0 0x07>, <&audma0 0x08>,
1638 1638 <&audma0 0x6f>, <&audma0 0x70>;
1639 dma-n 1639 dma-names = "rx", "tx", "rxu", "txu";
1640 }; 1640 };
1641 ssi4: ssi-4 { 1641 ssi4: ssi-4 {
1642 inter 1642 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1643 dmas 1643 dmas = <&audma0 0x09>, <&audma0 0x0a>,
1644 1644 <&audma0 0x71>, <&audma0 0x72>;
1645 dma-n 1645 dma-names = "rx", "tx", "rxu", "txu";
1646 }; 1646 };
1647 ssi5: ssi-5 { 1647 ssi5: ssi-5 {
1648 inter 1648 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1649 dmas 1649 dmas = <&audma0 0x0b>, <&audma0 0x0c>,
1650 1650 <&audma0 0x73>, <&audma0 0x74>;
1651 dma-n 1651 dma-names = "rx", "tx", "rxu", "txu";
1652 }; 1652 };
1653 ssi6: ssi-6 { 1653 ssi6: ssi-6 {
1654 inter 1654 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
1655 dmas 1655 dmas = <&audma0 0x0d>, <&audma0 0x0e>,
1656 1656 <&audma0 0x75>, <&audma0 0x76>;
1657 dma-n 1657 dma-names = "rx", "tx", "rxu", "txu";
1658 }; 1658 };
1659 ssi7: ssi-7 { 1659 ssi7: ssi-7 {
1660 inter 1660 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
1661 dmas 1661 dmas = <&audma0 0x0f>, <&audma0 0x10>,
1662 1662 <&audma0 0x79>, <&audma0 0x7a>;
1663 dma-n 1663 dma-names = "rx", "tx", "rxu", "txu";
1664 }; 1664 };
1665 ssi8: ssi-8 { 1665 ssi8: ssi-8 {
1666 inter 1666 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
1667 dmas 1667 dmas = <&audma0 0x11>, <&audma0 0x12>,
1668 1668 <&audma0 0x7b>, <&audma0 0x7c>;
1669 dma-n 1669 dma-names = "rx", "tx", "rxu", "txu";
1670 }; 1670 };
1671 ssi9: ssi-9 { 1671 ssi9: ssi-9 {
1672 inter 1672 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
1673 dmas 1673 dmas = <&audma0 0x13>, <&audma0 0x14>,
1674 1674 <&audma0 0x7d>, <&audma0 0x7e>;
1675 dma-n 1675 dma-names = "rx", "tx", "rxu", "txu";
1676 }; 1676 };
1677 }; 1677 };
1678 }; 1678 };
1679 1679
1680 mlp: mlp@ec520000 { 1680 mlp: mlp@ec520000 {
1681 compatible = "renesas 1681 compatible = "renesas,r8a77990-mlp",
1682 "renesas 1682 "renesas,rcar-gen3-mlp";
1683 reg = <0 0xec520000 0 1683 reg = <0 0xec520000 0 0x800>;
1684 interrupts = <GIC_SPI 1684 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
1685 <GIC_SPI 385 1685 <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>;
1686 clocks = <&cpg CPG_MO 1686 clocks = <&cpg CPG_MOD 802>;
1687 power-domains = <&sys 1687 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1688 resets = <&cpg 802>; 1688 resets = <&cpg 802>;
1689 status = "disabled"; 1689 status = "disabled";
1690 }; 1690 };
1691 1691
1692 audma0: dma-controller@ec7000 1692 audma0: dma-controller@ec700000 {
1693 compatible = "renesas 1693 compatible = "renesas,dmac-r8a77990",
1694 "renesas 1694 "renesas,rcar-dmac";
1695 reg = <0 0xec700000 0 1695 reg = <0 0xec700000 0 0x10000>;
1696 interrupts = <GIC_SPI 1696 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
1697 <GIC_SPI 1697 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
1698 <GIC_SPI 1698 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
1699 <GIC_SPI 1699 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
1700 <GIC_SPI 1700 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
1701 <GIC_SPI 1701 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
1702 <GIC_SPI 1702 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
1703 <GIC_SPI 1703 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
1704 <GIC_SPI 1704 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
1705 <GIC_SPI 1705 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
1706 <GIC_SPI 1706 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1707 <GIC_SPI 1707 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
1708 <GIC_SPI 1708 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
1709 <GIC_SPI 1709 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
1710 <GIC_SPI 1710 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
1711 <GIC_SPI 1711 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1712 <GIC_SPI 1712 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
1713 interrupt-names = "er 1713 interrupt-names = "error",
1714 "ch0" 1714 "ch0", "ch1", "ch2", "ch3",
1715 "ch4" 1715 "ch4", "ch5", "ch6", "ch7",
1716 "ch8" 1716 "ch8", "ch9", "ch10", "ch11",
1717 "ch12 1717 "ch12", "ch13", "ch14", "ch15";
1718 clocks = <&cpg CPG_MO 1718 clocks = <&cpg CPG_MOD 502>;
1719 clock-names = "fck"; 1719 clock-names = "fck";
1720 power-domains = <&sys 1720 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1721 resets = <&cpg 502>; 1721 resets = <&cpg 502>;
1722 #dma-cells = <1>; 1722 #dma-cells = <1>;
1723 dma-channels = <16>; 1723 dma-channels = <16>;
1724 iommus = <&ipmmu_mp 0 1724 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
1725 <&ipmmu_mp 2 1725 <&ipmmu_mp 2>, <&ipmmu_mp 3>,
1726 <&ipmmu_mp 4 1726 <&ipmmu_mp 4>, <&ipmmu_mp 5>,
1727 <&ipmmu_mp 6 1727 <&ipmmu_mp 6>, <&ipmmu_mp 7>,
1728 <&ipmmu_mp 8 1728 <&ipmmu_mp 8>, <&ipmmu_mp 9>,
1729 <&ipmmu_mp 1 1729 <&ipmmu_mp 10>, <&ipmmu_mp 11>,
1730 <&ipmmu_mp 1 1730 <&ipmmu_mp 12>, <&ipmmu_mp 13>,
1731 <&ipmmu_mp 1 1731 <&ipmmu_mp 14>, <&ipmmu_mp 15>;
1732 }; 1732 };
1733 1733
1734 xhci0: usb@ee000000 { 1734 xhci0: usb@ee000000 {
1735 compatible = "renesas 1735 compatible = "renesas,xhci-r8a77990",
1736 "renesas 1736 "renesas,rcar-gen3-xhci";
1737 reg = <0 0xee000000 0 1737 reg = <0 0xee000000 0 0xc00>;
1738 interrupts = <GIC_SPI 1738 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1739 clocks = <&cpg CPG_MO 1739 clocks = <&cpg CPG_MOD 328>;
1740 power-domains = <&sys 1740 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1741 resets = <&cpg 328>; 1741 resets = <&cpg 328>;
1742 status = "disabled"; 1742 status = "disabled";
1743 }; 1743 };
1744 1744
1745 usb3_peri0: usb@ee020000 { 1745 usb3_peri0: usb@ee020000 {
1746 compatible = "renesas 1746 compatible = "renesas,r8a77990-usb3-peri",
1747 "renesas 1747 "renesas,rcar-gen3-usb3-peri";
1748 reg = <0 0xee020000 0 1748 reg = <0 0xee020000 0 0x400>;
1749 interrupts = <GIC_SPI 1749 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1750 clocks = <&cpg CPG_MO 1750 clocks = <&cpg CPG_MOD 328>;
1751 power-domains = <&sys 1751 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1752 resets = <&cpg 328>; 1752 resets = <&cpg 328>;
1753 status = "disabled"; 1753 status = "disabled";
1754 }; 1754 };
1755 1755
1756 ohci0: usb@ee080000 { 1756 ohci0: usb@ee080000 {
1757 compatible = "generic 1757 compatible = "generic-ohci";
1758 reg = <0 0xee080000 0 1758 reg = <0 0xee080000 0 0x100>;
1759 interrupts = <GIC_SPI 1759 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1760 clocks = <&cpg CPG_MO 1760 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
1761 phys = <&usb2_phy0 1> 1761 phys = <&usb2_phy0 1>;
1762 phy-names = "usb"; 1762 phy-names = "usb";
1763 power-domains = <&sys 1763 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1764 resets = <&cpg 703>, 1764 resets = <&cpg 703>, <&cpg 704>;
1765 status = "disabled"; 1765 status = "disabled";
1766 }; 1766 };
1767 1767
1768 ehci0: usb@ee080100 { 1768 ehci0: usb@ee080100 {
1769 compatible = "generic 1769 compatible = "generic-ehci";
1770 reg = <0 0xee080100 0 1770 reg = <0 0xee080100 0 0x100>;
1771 interrupts = <GIC_SPI 1771 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1772 clocks = <&cpg CPG_MO 1772 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
1773 phys = <&usb2_phy0 2> 1773 phys = <&usb2_phy0 2>;
1774 phy-names = "usb"; 1774 phy-names = "usb";
1775 companion = <&ohci0>; 1775 companion = <&ohci0>;
1776 power-domains = <&sys 1776 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1777 resets = <&cpg 703>, 1777 resets = <&cpg 703>, <&cpg 704>;
1778 status = "disabled"; 1778 status = "disabled";
1779 }; 1779 };
1780 1780
1781 usb2_phy0: usb-phy@ee080200 { 1781 usb2_phy0: usb-phy@ee080200 {
1782 compatible = "renesas 1782 compatible = "renesas,usb2-phy-r8a77990",
1783 "renesas 1783 "renesas,rcar-gen3-usb2-phy";
1784 reg = <0 0xee080200 0 1784 reg = <0 0xee080200 0 0x700>;
1785 interrupts = <GIC_SPI 1785 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1786 clocks = <&cpg CPG_MO 1786 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
1787 power-domains = <&sys 1787 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1788 resets = <&cpg 703>, 1788 resets = <&cpg 703>, <&cpg 704>;
1789 #phy-cells = <1>; 1789 #phy-cells = <1>;
1790 status = "disabled"; 1790 status = "disabled";
1791 }; 1791 };
1792 1792
1793 sdhi0: mmc@ee100000 { 1793 sdhi0: mmc@ee100000 {
1794 compatible = "renesas 1794 compatible = "renesas,sdhi-r8a77990",
1795 "renesas 1795 "renesas,rcar-gen3-sdhi";
1796 reg = <0 0xee100000 0 1796 reg = <0 0xee100000 0 0x2000>;
1797 interrupts = <GIC_SPI 1797 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
1798 clocks = <&cpg CPG_MO 1798 clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A77990_CLK_SD0H>;
1799 clock-names = "core", 1799 clock-names = "core", "clkh";
1800 max-frequency = <2000 1800 max-frequency = <200000000>;
1801 power-domains = <&sys 1801 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1802 resets = <&cpg 314>; 1802 resets = <&cpg 314>;
1803 iommus = <&ipmmu_ds1 1803 iommus = <&ipmmu_ds1 32>;
1804 status = "disabled"; 1804 status = "disabled";
1805 }; 1805 };
1806 1806
1807 sdhi1: mmc@ee120000 { 1807 sdhi1: mmc@ee120000 {
1808 compatible = "renesas 1808 compatible = "renesas,sdhi-r8a77990",
1809 "renesas 1809 "renesas,rcar-gen3-sdhi";
1810 reg = <0 0xee120000 0 1810 reg = <0 0xee120000 0 0x2000>;
1811 interrupts = <GIC_SPI 1811 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
1812 clocks = <&cpg CPG_MO 1812 clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A77990_CLK_SD1H>;
1813 clock-names = "core", 1813 clock-names = "core", "clkh";
1814 max-frequency = <2000 1814 max-frequency = <200000000>;
1815 power-domains = <&sys 1815 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1816 resets = <&cpg 313>; 1816 resets = <&cpg 313>;
1817 iommus = <&ipmmu_ds1 1817 iommus = <&ipmmu_ds1 33>;
1818 status = "disabled"; 1818 status = "disabled";
1819 }; 1819 };
1820 1820
1821 sdhi3: mmc@ee160000 { 1821 sdhi3: mmc@ee160000 {
1822 compatible = "renesas 1822 compatible = "renesas,sdhi-r8a77990",
1823 "renesas 1823 "renesas,rcar-gen3-sdhi";
1824 reg = <0 0xee160000 0 1824 reg = <0 0xee160000 0 0x2000>;
1825 interrupts = <GIC_SPI 1825 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
1826 clocks = <&cpg CPG_MO 1826 clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A77990_CLK_SD3H>;
1827 clock-names = "core", 1827 clock-names = "core", "clkh";
1828 max-frequency = <2000 1828 max-frequency = <200000000>;
1829 power-domains = <&sys 1829 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1830 resets = <&cpg 311>; 1830 resets = <&cpg 311>;
1831 iommus = <&ipmmu_ds1 1831 iommus = <&ipmmu_ds1 35>;
1832 status = "disabled"; 1832 status = "disabled";
1833 }; 1833 };
1834 1834
1835 rpc: spi@ee200000 { 1835 rpc: spi@ee200000 {
1836 compatible = "renesas 1836 compatible = "renesas,r8a77990-rpc-if",
1837 "renesas 1837 "renesas,rcar-gen3-rpc-if";
1838 reg = <0 0xee200000 0 1838 reg = <0 0xee200000 0 0x200>,
1839 <0 0x08000000 0 1839 <0 0x08000000 0 0x04000000>,
1840 <0 0xee208000 0 1840 <0 0xee208000 0 0x100>;
1841 reg-names = "regs", " 1841 reg-names = "regs", "dirmap", "wbuf";
1842 interrupts = <GIC_SPI 1842 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
1843 clocks = <&cpg CPG_MO 1843 clocks = <&cpg CPG_MOD 917>;
1844 power-domains = <&sys 1844 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1845 resets = <&cpg 917>; 1845 resets = <&cpg 917>;
1846 #address-cells = <1>; 1846 #address-cells = <1>;
1847 #size-cells = <0>; 1847 #size-cells = <0>;
1848 status = "disabled"; 1848 status = "disabled";
1849 }; 1849 };
1850 1850
1851 gic: interrupt-controller@f10 1851 gic: interrupt-controller@f1010000 {
1852 compatible = "arm,gic 1852 compatible = "arm,gic-400";
1853 #interrupt-cells = <3 1853 #interrupt-cells = <3>;
1854 #address-cells = <0>; 1854 #address-cells = <0>;
1855 interrupt-controller; 1855 interrupt-controller;
1856 reg = <0x0 0xf1010000 1856 reg = <0x0 0xf1010000 0 0x1000>,
1857 <0x0 0xf1020000 1857 <0x0 0xf1020000 0 0x20000>,
1858 <0x0 0xf1040000 1858 <0x0 0xf1040000 0 0x20000>,
1859 <0x0 0xf1060000 1859 <0x0 0xf1060000 0 0x20000>;
1860 interrupts = <GIC_PPI 1860 interrupts = <GIC_PPI 9
1861 (GIC_ 1861 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
1862 clocks = <&cpg CPG_MO 1862 clocks = <&cpg CPG_MOD 408>;
1863 clock-names = "clk"; 1863 clock-names = "clk";
1864 power-domains = <&sys 1864 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1865 resets = <&cpg 408>; 1865 resets = <&cpg 408>;
1866 }; 1866 };
1867 1867
1868 pciec0: pcie@fe000000 { 1868 pciec0: pcie@fe000000 {
1869 compatible = "renesas 1869 compatible = "renesas,pcie-r8a77990",
1870 "renesas 1870 "renesas,pcie-rcar-gen3";
1871 reg = <0 0xfe000000 0 1871 reg = <0 0xfe000000 0 0x80000>;
1872 #address-cells = <3>; 1872 #address-cells = <3>;
1873 #size-cells = <2>; 1873 #size-cells = <2>;
1874 bus-range = <0x00 0xf 1874 bus-range = <0x00 0xff>;
1875 device_type = "pci"; 1875 device_type = "pci";
1876 ranges = <0x01000000 1876 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
1877 <0x02000000 1877 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
1878 <0x02000000 1878 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
1879 <0x42000000 1879 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1880 /* Map all possible D 1880 /* Map all possible DDR/IOMMU as inbound ranges */
1881 dma-ranges = <0x42000 1881 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
1882 interrupts = <GIC_SPI 1882 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1883 <GIC_SPI 1883 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1884 <GIC_SPI 1884 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1885 #interrupt-cells = <1 1885 #interrupt-cells = <1>;
1886 interrupt-map-mask = 1886 interrupt-map-mask = <0 0 0 0>;
1887 interrupt-map = <0 0 1887 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1888 clocks = <&cpg CPG_MO 1888 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
1889 clock-names = "pcie", 1889 clock-names = "pcie", "pcie_bus";
1890 power-domains = <&sys 1890 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1891 resets = <&cpg 319>; 1891 resets = <&cpg 319>;
1892 iommu-map = <0 &ipmmu 1892 iommu-map = <0 &ipmmu_hc 0 1>;
1893 iommu-map-mask = <0>; 1893 iommu-map-mask = <0>;
1894 status = "disabled"; 1894 status = "disabled";
1895 }; 1895 };
1896 1896
1897 vspb0: vsp@fe960000 { 1897 vspb0: vsp@fe960000 {
1898 compatible = "renesas 1898 compatible = "renesas,vsp2";
1899 reg = <0 0xfe960000 0 1899 reg = <0 0xfe960000 0 0x8000>;
1900 interrupts = <GIC_SPI 1900 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
1901 clocks = <&cpg CPG_MO 1901 clocks = <&cpg CPG_MOD 626>;
1902 power-domains = <&sys 1902 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1903 resets = <&cpg 626>; 1903 resets = <&cpg 626>;
1904 renesas,fcp = <&fcpvb 1904 renesas,fcp = <&fcpvb0>;
1905 }; 1905 };
1906 1906
1907 fcpvb0: fcp@fe96f000 { 1907 fcpvb0: fcp@fe96f000 {
1908 compatible = "renesas 1908 compatible = "renesas,fcpv";
1909 reg = <0 0xfe96f000 0 1909 reg = <0 0xfe96f000 0 0x200>;
1910 clocks = <&cpg CPG_MO 1910 clocks = <&cpg CPG_MOD 607>;
1911 power-domains = <&sys 1911 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1912 resets = <&cpg 607>; 1912 resets = <&cpg 607>;
1913 iommus = <&ipmmu_vp0 1913 iommus = <&ipmmu_vp0 5>;
1914 }; 1914 };
1915 1915
1916 vspi0: vsp@fe9a0000 { 1916 vspi0: vsp@fe9a0000 {
1917 compatible = "renesas 1917 compatible = "renesas,vsp2";
1918 reg = <0 0xfe9a0000 0 1918 reg = <0 0xfe9a0000 0 0x8000>;
1919 interrupts = <GIC_SPI 1919 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
1920 clocks = <&cpg CPG_MO 1920 clocks = <&cpg CPG_MOD 631>;
1921 power-domains = <&sys 1921 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1922 resets = <&cpg 631>; 1922 resets = <&cpg 631>;
1923 renesas,fcp = <&fcpvi 1923 renesas,fcp = <&fcpvi0>;
1924 }; 1924 };
1925 1925
1926 fcpvi0: fcp@fe9af000 { 1926 fcpvi0: fcp@fe9af000 {
1927 compatible = "renesas 1927 compatible = "renesas,fcpv";
1928 reg = <0 0xfe9af000 0 1928 reg = <0 0xfe9af000 0 0x200>;
1929 clocks = <&cpg CPG_MO 1929 clocks = <&cpg CPG_MOD 611>;
1930 power-domains = <&sys 1930 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1931 resets = <&cpg 611>; 1931 resets = <&cpg 611>;
1932 iommus = <&ipmmu_vp0 1932 iommus = <&ipmmu_vp0 8>;
1933 }; 1933 };
1934 1934
1935 vspd0: vsp@fea20000 { 1935 vspd0: vsp@fea20000 {
1936 compatible = "renesas 1936 compatible = "renesas,vsp2";
1937 reg = <0 0xfea20000 0 1937 reg = <0 0xfea20000 0 0x7000>;
1938 interrupts = <GIC_SPI 1938 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
1939 clocks = <&cpg CPG_MO 1939 clocks = <&cpg CPG_MOD 623>;
1940 power-domains = <&sys 1940 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1941 resets = <&cpg 623>; 1941 resets = <&cpg 623>;
1942 renesas,fcp = <&fcpvd 1942 renesas,fcp = <&fcpvd0>;
1943 }; 1943 };
1944 1944
1945 fcpvd0: fcp@fea27000 { 1945 fcpvd0: fcp@fea27000 {
1946 compatible = "renesas 1946 compatible = "renesas,fcpv";
1947 reg = <0 0xfea27000 0 1947 reg = <0 0xfea27000 0 0x200>;
1948 clocks = <&cpg CPG_MO 1948 clocks = <&cpg CPG_MOD 603>;
1949 power-domains = <&sys 1949 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1950 resets = <&cpg 603>; 1950 resets = <&cpg 603>;
1951 iommus = <&ipmmu_vi0 1951 iommus = <&ipmmu_vi0 8>;
1952 }; 1952 };
1953 1953
1954 vspd1: vsp@fea28000 { 1954 vspd1: vsp@fea28000 {
1955 compatible = "renesas 1955 compatible = "renesas,vsp2";
1956 reg = <0 0xfea28000 0 1956 reg = <0 0xfea28000 0 0x7000>;
1957 interrupts = <GIC_SPI 1957 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
1958 clocks = <&cpg CPG_MO 1958 clocks = <&cpg CPG_MOD 622>;
1959 power-domains = <&sys 1959 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1960 resets = <&cpg 622>; 1960 resets = <&cpg 622>;
1961 renesas,fcp = <&fcpvd 1961 renesas,fcp = <&fcpvd1>;
1962 }; 1962 };
1963 1963
1964 fcpvd1: fcp@fea2f000 { 1964 fcpvd1: fcp@fea2f000 {
1965 compatible = "renesas 1965 compatible = "renesas,fcpv";
1966 reg = <0 0xfea2f000 0 1966 reg = <0 0xfea2f000 0 0x200>;
1967 clocks = <&cpg CPG_MO 1967 clocks = <&cpg CPG_MOD 602>;
1968 power-domains = <&sys 1968 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1969 resets = <&cpg 602>; 1969 resets = <&cpg 602>;
1970 iommus = <&ipmmu_vi0 1970 iommus = <&ipmmu_vi0 9>;
1971 }; 1971 };
1972 1972
1973 cmm0: cmm@fea40000 { 1973 cmm0: cmm@fea40000 {
1974 compatible = "renesas 1974 compatible = "renesas,r8a77990-cmm",
1975 "renesas 1975 "renesas,rcar-gen3-cmm";
1976 reg = <0 0xfea40000 0 1976 reg = <0 0xfea40000 0 0x1000>;
1977 power-domains = <&sys 1977 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1978 clocks = <&cpg CPG_MO 1978 clocks = <&cpg CPG_MOD 711>;
1979 resets = <&cpg 711>; 1979 resets = <&cpg 711>;
1980 }; 1980 };
1981 1981
1982 cmm1: cmm@fea50000 { 1982 cmm1: cmm@fea50000 {
1983 compatible = "renesas 1983 compatible = "renesas,r8a77990-cmm",
1984 "renesas 1984 "renesas,rcar-gen3-cmm";
1985 reg = <0 0xfea50000 0 1985 reg = <0 0xfea50000 0 0x1000>;
1986 power-domains = <&sys 1986 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1987 clocks = <&cpg CPG_MO 1987 clocks = <&cpg CPG_MOD 710>;
1988 resets = <&cpg 710>; 1988 resets = <&cpg 710>;
1989 }; 1989 };
1990 1990
1991 csi40: csi2@feaa0000 { 1991 csi40: csi2@feaa0000 {
1992 compatible = "renesas 1992 compatible = "renesas,r8a77990-csi2";
1993 reg = <0 0xfeaa0000 0 1993 reg = <0 0xfeaa0000 0 0x10000>;
1994 interrupts = <GIC_SPI 1994 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
1995 clocks = <&cpg CPG_MO 1995 clocks = <&cpg CPG_MOD 716>;
1996 power-domains = <&sys 1996 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1997 resets = <&cpg 716>; 1997 resets = <&cpg 716>;
1998 status = "disabled"; 1998 status = "disabled";
1999 1999
2000 ports { 2000 ports {
2001 #address-cell 2001 #address-cells = <1>;
2002 #size-cells = 2002 #size-cells = <0>;
2003 2003
2004 port@0 { 2004 port@0 {
2005 reg = 2005 reg = <0>;
2006 }; 2006 };
2007 2007
2008 port@1 { 2008 port@1 {
2009 #addr 2009 #address-cells = <1>;
2010 #size 2010 #size-cells = <0>;
2011 2011
2012 reg = 2012 reg = <1>;
2013 2013
2014 csi40 2014 csi40vin4: endpoint@0 {
2015 2015 reg = <0>;
2016 2016 remote-endpoint = <&vin4csi40>;
2017 }; 2017 };
2018 csi40 2018 csi40vin5: endpoint@1 {
2019 2019 reg = <1>;
2020 2020 remote-endpoint = <&vin5csi40>;
2021 }; 2021 };
2022 }; 2022 };
2023 }; 2023 };
2024 }; 2024 };
2025 2025
2026 du: display@feb00000 { 2026 du: display@feb00000 {
2027 compatible = "renesas 2027 compatible = "renesas,du-r8a77990";
2028 reg = <0 0xfeb00000 0 2028 reg = <0 0xfeb00000 0 0x40000>;
2029 interrupts = <GIC_SPI 2029 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
2030 <GIC_SPI 2030 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
2031 clocks = <&cpg CPG_MO 2031 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
2032 clock-names = "du.0", 2032 clock-names = "du.0", "du.1";
2033 resets = <&cpg 724>; 2033 resets = <&cpg 724>;
2034 reset-names = "du.0"; 2034 reset-names = "du.0";
2035 2035
2036 renesas,cmms = <&cmm0 2036 renesas,cmms = <&cmm0>, <&cmm1>;
2037 renesas,vsps = <&vspd 2037 renesas,vsps = <&vspd0 0>, <&vspd1 0>;
2038 2038
2039 status = "disabled"; 2039 status = "disabled";
2040 2040
2041 ports { 2041 ports {
2042 #address-cell 2042 #address-cells = <1>;
2043 #size-cells = 2043 #size-cells = <0>;
2044 2044
2045 port@0 { 2045 port@0 {
2046 reg = 2046 reg = <0>;
2047 }; 2047 };
2048 2048
2049 port@1 { 2049 port@1 {
2050 reg = 2050 reg = <1>;
2051 du_ou 2051 du_out_lvds0: endpoint {
2052 2052 remote-endpoint = <&lvds0_in>;
2053 }; 2053 };
2054 }; 2054 };
2055 2055
2056 port@2 { 2056 port@2 {
2057 reg = 2057 reg = <2>;
2058 du_ou 2058 du_out_lvds1: endpoint {
2059 2059 remote-endpoint = <&lvds1_in>;
2060 }; 2060 };
2061 }; 2061 };
2062 }; 2062 };
2063 }; 2063 };
2064 2064
2065 lvds0: lvds-encoder@feb90000 2065 lvds0: lvds-encoder@feb90000 {
2066 compatible = "renesas 2066 compatible = "renesas,r8a77990-lvds";
2067 reg = <0 0xfeb90000 0 2067 reg = <0 0xfeb90000 0 0x20>;
2068 clocks = <&cpg CPG_MO 2068 clocks = <&cpg CPG_MOD 727>;
2069 power-domains = <&sys 2069 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
2070 resets = <&cpg 727>; 2070 resets = <&cpg 727>;
2071 status = "disabled"; 2071 status = "disabled";
2072 2072
2073 renesas,companion = < 2073 renesas,companion = <&lvds1>;
2074 2074
2075 ports { 2075 ports {
2076 #address-cell 2076 #address-cells = <1>;
2077 #size-cells = 2077 #size-cells = <0>;
2078 2078
2079 port@0 { 2079 port@0 {
2080 reg = 2080 reg = <0>;
2081 lvds0 2081 lvds0_in: endpoint {
2082 2082 remote-endpoint = <&du_out_lvds0>;
2083 }; 2083 };
2084 }; 2084 };
2085 2085
2086 port@1 { 2086 port@1 {
2087 reg = 2087 reg = <1>;
2088 }; 2088 };
2089 }; 2089 };
2090 }; 2090 };
2091 2091
2092 lvds1: lvds-encoder@feb90100 2092 lvds1: lvds-encoder@feb90100 {
2093 compatible = "renesas 2093 compatible = "renesas,r8a77990-lvds";
2094 reg = <0 0xfeb90100 0 2094 reg = <0 0xfeb90100 0 0x20>;
2095 clocks = <&cpg CPG_MO 2095 clocks = <&cpg CPG_MOD 727>;
2096 power-domains = <&sys 2096 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
2097 resets = <&cpg 726>; 2097 resets = <&cpg 726>;
2098 status = "disabled"; 2098 status = "disabled";
2099 2099
2100 ports { 2100 ports {
2101 #address-cell 2101 #address-cells = <1>;
2102 #size-cells = 2102 #size-cells = <0>;
2103 2103
2104 port@0 { 2104 port@0 {
2105 reg = 2105 reg = <0>;
2106 lvds1 2106 lvds1_in: endpoint {
2107 2107 remote-endpoint = <&du_out_lvds1>;
2108 }; 2108 };
2109 }; 2109 };
2110 2110
2111 port@1 { 2111 port@1 {
2112 reg = 2112 reg = <1>;
2113 }; 2113 };
2114 }; 2114 };
2115 }; 2115 };
2116 2116
2117 prr: chipid@fff00044 { 2117 prr: chipid@fff00044 {
2118 compatible = "renesas 2118 compatible = "renesas,prr";
2119 reg = <0 0xfff00044 0 2119 reg = <0 0xfff00044 0 4>;
2120 }; 2120 };
2121 }; 2121 };
2122 2122
2123 thermal-zones { 2123 thermal-zones {
2124 cpu-thermal { 2124 cpu-thermal {
2125 polling-delay-passive 2125 polling-delay-passive = <250>;
2126 polling-delay = <0>; 2126 polling-delay = <0>;
2127 thermal-sensors = <&t 2127 thermal-sensors = <&thermal>;
2128 sustainable-power = < 2128 sustainable-power = <717>;
2129 2129
2130 cooling-maps { 2130 cooling-maps {
2131 map0 { 2131 map0 {
2132 trip 2132 trip = <&target>;
2133 cooli 2133 cooling-device = <&a53_0 0 2>;
2134 contr 2134 contribution = <1024>;
2135 }; 2135 };
2136 }; 2136 };
2137 2137
2138 trips { 2138 trips {
2139 sensor1_crit: 2139 sensor1_crit: sensor1-crit {
2140 tempe 2140 temperature = <120000>;
2141 hyste 2141 hysteresis = <2000>;
2142 type 2142 type = "critical";
2143 }; 2143 };
2144 2144
2145 target: trip- 2145 target: trip-point1 {
2146 tempe 2146 temperature = <100000>;
2147 hyste 2147 hysteresis = <2000>;
2148 type 2148 type = "passive";
2149 }; 2149 };
2150 }; 2150 };
2151 }; 2151 };
2152 }; 2152 };
2153 2153
2154 timer { 2154 timer {
2155 compatible = "arm,armv8-timer 2155 compatible = "arm,armv8-timer";
2156 interrupts-extended = <&gic G 2156 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
2157 <&gic G 2157 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
2158 <&gic G 2158 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
2159 <&gic G 2159 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
2160 interrupt-names = "sec-phys", 2160 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys";
2161 }; 2161 };
2162 }; 2162 };
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