1 // SPDX-License-Identifier: GPL-2.0 !! 1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* 2 /*
3 * Device Tree Source for the R-Car E3 (R8A779 !! 3 * Device Tree Source for the r8a77990 SoC
4 * 4 *
5 * Copyright (C) 2018-2019 Renesas Electronics !! 5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */ 6 */
7 7
8 #include <dt-bindings/clock/r8a77990-cpg-mssr. !! 8 #include <dt-bindings/clock/renesas-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm 9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a77990-sysc.h> 10 #include <dt-bindings/power/r8a77990-sysc.h>
11 11
12 / { 12 / {
13 compatible = "renesas,r8a77990"; 13 compatible = "renesas,r8a77990";
14 #address-cells = <2>; 14 #address-cells = <2>;
15 #size-cells = <2>; 15 #size-cells = <2>;
16 16
17 /* <<
18 * The external audio clocks are confi <<
19 * clocks by default. <<
20 * Boards that provide audio clocks sh <<
21 */ <<
22 audio_clk_a: audio_clk_a { <<
23 compatible = "fixed-clock"; <<
24 #clock-cells = <0>; <<
25 clock-frequency = <0>; <<
26 }; <<
27 <<
28 audio_clk_b: audio_clk_b { <<
29 compatible = "fixed-clock"; <<
30 #clock-cells = <0>; <<
31 clock-frequency = <0>; <<
32 }; <<
33 <<
34 audio_clk_c: audio_clk_c { <<
35 compatible = "fixed-clock"; <<
36 #clock-cells = <0>; <<
37 clock-frequency = <0>; <<
38 }; <<
39 <<
40 /* External CAN clock - to be overridd <<
41 can_clk: can { <<
42 compatible = "fixed-clock"; <<
43 #clock-cells = <0>; <<
44 clock-frequency = <0>; <<
45 }; <<
46 <<
47 cluster1_opp: opp-table-1 { <<
48 compatible = "operating-points <<
49 opp-shared; <<
50 opp-800000000 { <<
51 opp-hz = /bits/ 64 <80 <<
52 clock-latency-ns = <30 <<
53 }; <<
54 opp-1000000000 { <<
55 opp-hz = /bits/ 64 <10 <<
56 clock-latency-ns = <30 <<
57 }; <<
58 opp-1200000000 { <<
59 opp-hz = /bits/ 64 <12 <<
60 clock-latency-ns = <30 <<
61 opp-suspend; <<
62 }; <<
63 }; <<
64 <<
65 cpus { 17 cpus {
66 #address-cells = <1>; 18 #address-cells = <1>;
67 #size-cells = <0>; 19 #size-cells = <0>;
68 20
69 a53_0: cpu@0 { 21 a53_0: cpu@0 {
70 compatible = "arm,cort !! 22 compatible = "arm,cortex-a53", "arm,armv8";
71 reg = <0>; 23 reg = <0>;
72 device_type = "cpu"; 24 device_type = "cpu";
73 #cooling-cells = <2>; !! 25 power-domains = <&sysc 5>;
74 power-domains = <&sysc <<
75 next-level-cache = <&L 26 next-level-cache = <&L2_CA53>;
76 enable-method = "psci" 27 enable-method = "psci";
77 cpu-idle-states = <&CP <<
78 dynamic-power-coeffici <<
79 clocks = <&cpg CPG_COR <<
80 operating-points-v2 = <<
81 }; 28 };
82 29
83 a53_1: cpu@1 { 30 a53_1: cpu@1 {
84 compatible = "arm,cort !! 31 compatible = "arm,cortex-a53", "arm,armv8";
85 reg = <1>; 32 reg = <1>;
86 device_type = "cpu"; 33 device_type = "cpu";
87 power-domains = <&sysc !! 34 power-domains = <&sysc 6>;
88 next-level-cache = <&L 35 next-level-cache = <&L2_CA53>;
89 enable-method = "psci" 36 enable-method = "psci";
90 cpu-idle-states = <&CP <<
91 clocks = <&cpg CPG_COR <<
92 operating-points-v2 = <<
93 }; 37 };
94 38
95 L2_CA53: cache-controller-0 { 39 L2_CA53: cache-controller-0 {
96 compatible = "cache"; 40 compatible = "cache";
97 power-domains = <&sysc !! 41 power-domains = <&sysc 21>;
98 cache-unified; 42 cache-unified;
99 cache-level = <2>; 43 cache-level = <2>;
100 }; 44 };
101 <<
102 idle-states { <<
103 entry-method = "psci"; <<
104 <<
105 CPU_SLEEP_0: cpu-sleep <<
106 compatible = " <<
107 arm,psci-suspe <<
108 local-timer-st <<
109 entry-latency- <<
110 exit-latency-u <<
111 min-residency- <<
112 }; <<
113 }; <<
114 }; 45 };
115 46
116 extal_clk: extal { 47 extal_clk: extal {
117 compatible = "fixed-clock"; 48 compatible = "fixed-clock";
118 #clock-cells = <0>; 49 #clock-cells = <0>;
119 /* This value must be overridd 50 /* This value must be overridden by the board */
120 clock-frequency = <0>; 51 clock-frequency = <0>;
121 }; 52 };
122 53
123 /* External PCIe clock - can be overri <<
124 pcie_bus_clk: pcie_bus { <<
125 compatible = "fixed-clock"; <<
126 #clock-cells = <0>; <<
127 clock-frequency = <0>; <<
128 }; <<
129 <<
130 pmu_a53 { 54 pmu_a53 {
131 compatible = "arm,cortex-a53-p 55 compatible = "arm,cortex-a53-pmu";
132 interrupts-extended = <&gic GI 56 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
133 <&gic GI 57 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
134 interrupt-affinity = <&a53_0>, 58 interrupt-affinity = <&a53_0>, <&a53_1>;
135 }; 59 };
136 60
137 psci { 61 psci {
138 compatible = "arm,psci-1.0", " 62 compatible = "arm,psci-1.0", "arm,psci-0.2";
139 method = "smc"; 63 method = "smc";
140 }; 64 };
141 65
142 /* External SCIF clock - to be overrid <<
143 scif_clk: scif { <<
144 compatible = "fixed-clock"; <<
145 #clock-cells = <0>; <<
146 clock-frequency = <0>; <<
147 }; <<
148 <<
149 soc: soc { 66 soc: soc {
150 compatible = "simple-bus"; 67 compatible = "simple-bus";
151 interrupt-parent = <&gic>; 68 interrupt-parent = <&gic>;
152 #address-cells = <2>; 69 #address-cells = <2>;
153 #size-cells = <2>; 70 #size-cells = <2>;
154 ranges; 71 ranges;
155 72
156 rwdt: watchdog@e6020000 { 73 rwdt: watchdog@e6020000 {
157 compatible = "renesas, 74 compatible = "renesas,r8a77990-wdt",
158 "renesas, 75 "renesas,rcar-gen3-wdt";
159 reg = <0 0xe6020000 0 76 reg = <0 0xe6020000 0 0x0c>;
160 interrupts = <GIC_SPI <<
161 clocks = <&cpg CPG_MOD 77 clocks = <&cpg CPG_MOD 402>;
162 power-domains = <&sysc !! 78 power-domains = <&sysc 32>;
163 resets = <&cpg 402>; 79 resets = <&cpg 402>;
164 status = "disabled"; 80 status = "disabled";
165 }; 81 };
166 82
167 gpio0: gpio@e6050000 { 83 gpio0: gpio@e6050000 {
168 compatible = "renesas, 84 compatible = "renesas,gpio-r8a77990",
169 "renesas, 85 "renesas,rcar-gen3-gpio";
170 reg = <0 0xe6050000 0 86 reg = <0 0xe6050000 0 0x50>;
171 interrupts = <GIC_SPI 87 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
172 #gpio-cells = <2>; 88 #gpio-cells = <2>;
173 gpio-controller; 89 gpio-controller;
174 gpio-ranges = <&pfc 0 90 gpio-ranges = <&pfc 0 0 18>;
175 #interrupt-cells = <2> 91 #interrupt-cells = <2>;
176 interrupt-controller; 92 interrupt-controller;
177 clocks = <&cpg CPG_MOD 93 clocks = <&cpg CPG_MOD 912>;
178 power-domains = <&sysc !! 94 power-domains = <&sysc 32>;
179 resets = <&cpg 912>; 95 resets = <&cpg 912>;
180 }; 96 };
181 97
182 gpio1: gpio@e6051000 { 98 gpio1: gpio@e6051000 {
183 compatible = "renesas, 99 compatible = "renesas,gpio-r8a77990",
184 "renesas, 100 "renesas,rcar-gen3-gpio";
185 reg = <0 0xe6051000 0 101 reg = <0 0xe6051000 0 0x50>;
186 interrupts = <GIC_SPI 102 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
187 #gpio-cells = <2>; 103 #gpio-cells = <2>;
188 gpio-controller; 104 gpio-controller;
189 gpio-ranges = <&pfc 0 105 gpio-ranges = <&pfc 0 32 23>;
190 #interrupt-cells = <2> 106 #interrupt-cells = <2>;
191 interrupt-controller; 107 interrupt-controller;
192 clocks = <&cpg CPG_MOD 108 clocks = <&cpg CPG_MOD 911>;
193 power-domains = <&sysc !! 109 power-domains = <&sysc 32>;
194 resets = <&cpg 911>; 110 resets = <&cpg 911>;
195 }; 111 };
196 112
197 gpio2: gpio@e6052000 { 113 gpio2: gpio@e6052000 {
198 compatible = "renesas, 114 compatible = "renesas,gpio-r8a77990",
199 "renesas, 115 "renesas,rcar-gen3-gpio";
200 reg = <0 0xe6052000 0 116 reg = <0 0xe6052000 0 0x50>;
201 interrupts = <GIC_SPI 117 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
202 #gpio-cells = <2>; 118 #gpio-cells = <2>;
203 gpio-controller; 119 gpio-controller;
204 gpio-ranges = <&pfc 0 120 gpio-ranges = <&pfc 0 64 26>;
205 #interrupt-cells = <2> 121 #interrupt-cells = <2>;
206 interrupt-controller; 122 interrupt-controller;
207 clocks = <&cpg CPG_MOD 123 clocks = <&cpg CPG_MOD 910>;
208 power-domains = <&sysc !! 124 power-domains = <&sysc 32>;
209 resets = <&cpg 910>; 125 resets = <&cpg 910>;
210 }; 126 };
211 127
212 gpio3: gpio@e6053000 { 128 gpio3: gpio@e6053000 {
213 compatible = "renesas, 129 compatible = "renesas,gpio-r8a77990",
214 "renesas, 130 "renesas,rcar-gen3-gpio";
215 reg = <0 0xe6053000 0 131 reg = <0 0xe6053000 0 0x50>;
216 interrupts = <GIC_SPI 132 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
217 #gpio-cells = <2>; 133 #gpio-cells = <2>;
218 gpio-controller; 134 gpio-controller;
219 gpio-ranges = <&pfc 0 135 gpio-ranges = <&pfc 0 96 16>;
220 #interrupt-cells = <2> 136 #interrupt-cells = <2>;
221 interrupt-controller; 137 interrupt-controller;
222 clocks = <&cpg CPG_MOD 138 clocks = <&cpg CPG_MOD 909>;
223 power-domains = <&sysc !! 139 power-domains = <&sysc 32>;
224 resets = <&cpg 909>; 140 resets = <&cpg 909>;
225 }; 141 };
226 142
227 gpio4: gpio@e6054000 { 143 gpio4: gpio@e6054000 {
228 compatible = "renesas, 144 compatible = "renesas,gpio-r8a77990",
229 "renesas, 145 "renesas,rcar-gen3-gpio";
230 reg = <0 0xe6054000 0 146 reg = <0 0xe6054000 0 0x50>;
231 interrupts = <GIC_SPI 147 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
232 #gpio-cells = <2>; 148 #gpio-cells = <2>;
233 gpio-controller; 149 gpio-controller;
234 gpio-ranges = <&pfc 0 150 gpio-ranges = <&pfc 0 128 11>;
235 #interrupt-cells = <2> 151 #interrupt-cells = <2>;
236 interrupt-controller; 152 interrupt-controller;
237 clocks = <&cpg CPG_MOD 153 clocks = <&cpg CPG_MOD 908>;
238 power-domains = <&sysc !! 154 power-domains = <&sysc 32>;
239 resets = <&cpg 908>; 155 resets = <&cpg 908>;
240 }; 156 };
241 157
242 gpio5: gpio@e6055000 { 158 gpio5: gpio@e6055000 {
243 compatible = "renesas, 159 compatible = "renesas,gpio-r8a77990",
244 "renesas, 160 "renesas,rcar-gen3-gpio";
245 reg = <0 0xe6055000 0 161 reg = <0 0xe6055000 0 0x50>;
246 interrupts = <GIC_SPI 162 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
247 #gpio-cells = <2>; 163 #gpio-cells = <2>;
248 gpio-controller; 164 gpio-controller;
249 gpio-ranges = <&pfc 0 165 gpio-ranges = <&pfc 0 160 20>;
250 #interrupt-cells = <2> 166 #interrupt-cells = <2>;
251 interrupt-controller; 167 interrupt-controller;
252 clocks = <&cpg CPG_MOD 168 clocks = <&cpg CPG_MOD 907>;
253 power-domains = <&sysc !! 169 power-domains = <&sysc 32>;
254 resets = <&cpg 907>; 170 resets = <&cpg 907>;
255 }; 171 };
256 172
257 gpio6: gpio@e6055400 { 173 gpio6: gpio@e6055400 {
258 compatible = "renesas, 174 compatible = "renesas,gpio-r8a77990",
259 "renesas, 175 "renesas,rcar-gen3-gpio";
260 reg = <0 0xe6055400 0 176 reg = <0 0xe6055400 0 0x50>;
261 interrupts = <GIC_SPI 177 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
262 #gpio-cells = <2>; 178 #gpio-cells = <2>;
263 gpio-controller; 179 gpio-controller;
264 gpio-ranges = <&pfc 0 180 gpio-ranges = <&pfc 0 192 18>;
265 #interrupt-cells = <2> 181 #interrupt-cells = <2>;
266 interrupt-controller; 182 interrupt-controller;
267 clocks = <&cpg CPG_MOD 183 clocks = <&cpg CPG_MOD 906>;
268 power-domains = <&sysc !! 184 power-domains = <&sysc 32>;
269 resets = <&cpg 906>; 185 resets = <&cpg 906>;
270 }; 186 };
271 187
272 pfc: pinctrl@e6060000 { !! 188 pfc: pin-controller@e6060000 {
273 compatible = "renesas, 189 compatible = "renesas,pfc-r8a77990";
274 reg = <0 0xe6060000 0 190 reg = <0 0xe6060000 0 0x508>;
275 }; 191 };
276 192
277 i2c_dvfs: i2c@e60b0000 { <<
278 #address-cells = <1>; <<
279 #size-cells = <0>; <<
280 compatible = "renesas, <<
281 "renesas, <<
282 "renesas, <<
283 reg = <0 0xe60b0000 0 <<
284 interrupts = <GIC_SPI <<
285 clocks = <&cpg CPG_MOD <<
286 power-domains = <&sysc <<
287 resets = <&cpg 926>; <<
288 dmas = <&dmac0 0x11>, <<
289 dma-names = "tx", "rx" <<
290 status = "disabled"; <<
291 }; <<
292 <<
293 cmt0: timer@e60f0000 { <<
294 compatible = "renesas, <<
295 "renesas, <<
296 reg = <0 0xe60f0000 0 <<
297 interrupts = <GIC_SPI <<
298 <GIC_SPI <<
299 clocks = <&cpg CPG_MOD <<
300 clock-names = "fck"; <<
301 power-domains = <&sysc <<
302 resets = <&cpg 303>; <<
303 status = "disabled"; <<
304 }; <<
305 <<
306 cmt1: timer@e6130000 { <<
307 compatible = "renesas, <<
308 "renesas, <<
309 reg = <0 0xe6130000 0 <<
310 interrupts = <GIC_SPI <<
311 <GIC_SPI <<
312 <GIC_SPI <<
313 <GIC_SPI <<
314 <GIC_SPI <<
315 <GIC_SPI <<
316 <GIC_SPI <<
317 <GIC_SPI <<
318 clocks = <&cpg CPG_MOD <<
319 clock-names = "fck"; <<
320 power-domains = <&sysc <<
321 resets = <&cpg 302>; <<
322 status = "disabled"; <<
323 }; <<
324 <<
325 cmt2: timer@e6140000 { <<
326 compatible = "renesas, <<
327 "renesas, <<
328 reg = <0 0xe6140000 0 <<
329 interrupts = <GIC_SPI <<
330 <GIC_SPI <<
331 <GIC_SPI <<
332 <GIC_SPI <<
333 <GIC_SPI <<
334 <GIC_SPI <<
335 <GIC_SPI <<
336 <GIC_SPI <<
337 clocks = <&cpg CPG_MOD <<
338 clock-names = "fck"; <<
339 power-domains = <&sysc <<
340 resets = <&cpg 301>; <<
341 status = "disabled"; <<
342 }; <<
343 <<
344 cmt3: timer@e6148000 { <<
345 compatible = "renesas, <<
346 "renesas, <<
347 reg = <0 0xe6148000 0 <<
348 interrupts = <GIC_SPI <<
349 <GIC_SPI <<
350 <GIC_SPI <<
351 <GIC_SPI <<
352 <GIC_SPI <<
353 <GIC_SPI <<
354 <GIC_SPI <<
355 <GIC_SPI <<
356 clocks = <&cpg CPG_MOD <<
357 clock-names = "fck"; <<
358 power-domains = <&sysc <<
359 resets = <&cpg 300>; <<
360 status = "disabled"; <<
361 }; <<
362 <<
363 cpg: clock-controller@e6150000 193 cpg: clock-controller@e6150000 {
364 compatible = "renesas, 194 compatible = "renesas,r8a77990-cpg-mssr";
365 reg = <0 0xe6150000 0 195 reg = <0 0xe6150000 0 0x1000>;
366 clocks = <&extal_clk>; 196 clocks = <&extal_clk>;
367 clock-names = "extal"; 197 clock-names = "extal";
368 #clock-cells = <2>; 198 #clock-cells = <2>;
369 #power-domain-cells = 199 #power-domain-cells = <0>;
370 #reset-cells = <1>; 200 #reset-cells = <1>;
371 }; 201 };
372 202
373 rst: reset-controller@e6160000 203 rst: reset-controller@e6160000 {
374 compatible = "renesas, 204 compatible = "renesas,r8a77990-rst";
375 reg = <0 0xe6160000 0 205 reg = <0 0xe6160000 0 0x0200>;
376 }; 206 };
377 207
378 sysc: system-controller@e61800 208 sysc: system-controller@e6180000 {
379 compatible = "renesas, 209 compatible = "renesas,r8a77990-sysc";
380 reg = <0 0xe6180000 0 210 reg = <0 0xe6180000 0 0x0400>;
381 #power-domain-cells = 211 #power-domain-cells = <1>;
382 }; 212 };
383 213
384 thermal: thermal@e6190000 { !! 214 ipmmu_ds0: mmu@e6740000 {
385 compatible = "renesas, <<
386 reg = <0 0xe6190000 0 <<
387 interrupts = <GIC_SPI <<
388 <GIC_SPI <<
389 <GIC_SPI <<
390 clocks = <&cpg CPG_MOD <<
391 power-domains = <&sysc <<
392 resets = <&cpg 522>; <<
393 #thermal-sensor-cells <<
394 }; <<
395 <<
396 intc_ex: interrupt-controller@ <<
397 compatible = "renesas, <<
398 #interrupt-cells = <2> <<
399 interrupt-controller; <<
400 reg = <0 0xe61c0000 0 <<
401 interrupts = <GIC_SPI <<
402 <GIC_SPI <<
403 <GIC_SPI <<
404 <GIC_SPI <<
405 <GIC_SPI <<
406 <GIC_SPI <<
407 clocks = <&cpg CPG_MOD <<
408 power-domains = <&sysc <<
409 resets = <&cpg 407>; <<
410 }; <<
411 <<
412 tmu0: timer@e61e0000 { <<
413 compatible = "renesas, <<
414 reg = <0 0xe61e0000 0 <<
415 interrupts = <GIC_SPI <<
416 <GIC_SPI <<
417 <GIC_SPI <<
418 interrupt-names = "tun <<
419 clocks = <&cpg CPG_MOD <<
420 clock-names = "fck"; <<
421 power-domains = <&sysc <<
422 resets = <&cpg 125>; <<
423 status = "disabled"; <<
424 }; <<
425 <<
426 tmu1: timer@e6fc0000 { <<
427 compatible = "renesas, <<
428 reg = <0 0xe6fc0000 0 <<
429 interrupts = <GIC_SPI <<
430 <GIC_SPI <<
431 <GIC_SPI <<
432 <GIC_SPI <<
433 interrupt-names = "tun <<
434 clocks = <&cpg CPG_MOD <<
435 clock-names = "fck"; <<
436 power-domains = <&sysc <<
437 resets = <&cpg 124>; <<
438 status = "disabled"; <<
439 }; <<
440 <<
441 tmu2: timer@e6fd0000 { <<
442 compatible = "renesas, <<
443 reg = <0 0xe6fd0000 0 <<
444 interrupts = <GIC_SPI <<
445 <GIC_SPI <<
446 <GIC_SPI <<
447 <GIC_SPI <<
448 interrupt-names = "tun <<
449 clocks = <&cpg CPG_MOD <<
450 clock-names = "fck"; <<
451 power-domains = <&sysc <<
452 resets = <&cpg 123>; <<
453 status = "disabled"; <<
454 }; <<
455 <<
456 tmu3: timer@e6fe0000 { <<
457 compatible = "renesas, <<
458 reg = <0 0xe6fe0000 0 <<
459 interrupts = <GIC_SPI <<
460 <GIC_SPI <<
461 <GIC_SPI <<
462 interrupt-names = "tun <<
463 clocks = <&cpg CPG_MOD <<
464 clock-names = "fck"; <<
465 power-domains = <&sysc <<
466 resets = <&cpg 122>; <<
467 status = "disabled"; <<
468 }; <<
469 <<
470 tmu4: timer@ffc00000 { <<
471 compatible = "renesas, <<
472 reg = <0 0xffc00000 0 <<
473 interrupts = <GIC_SPI <<
474 <GIC_SPI <<
475 <GIC_SPI <<
476 interrupt-names = "tun <<
477 clocks = <&cpg CPG_MOD <<
478 clock-names = "fck"; <<
479 power-domains = <&sysc <<
480 resets = <&cpg 121>; <<
481 status = "disabled"; <<
482 }; <<
483 <<
484 i2c0: i2c@e6500000 { <<
485 #address-cells = <1>; <<
486 #size-cells = <0>; <<
487 compatible = "renesas, <<
488 "renesas, <<
489 reg = <0 0xe6500000 0 <<
490 interrupts = <GIC_SPI <<
491 clocks = <&cpg CPG_MOD <<
492 power-domains = <&sysc <<
493 resets = <&cpg 931>; <<
494 dmas = <&dmac1 0x91>, <<
495 <&dmac2 0x91>, <<
496 dma-names = "tx", "rx" <<
497 i2c-scl-internal-delay <<
498 status = "disabled"; <<
499 }; <<
500 <<
501 i2c1: i2c@e6508000 { <<
502 #address-cells = <1>; <<
503 #size-cells = <0>; <<
504 compatible = "renesas, <<
505 "renesas, <<
506 reg = <0 0xe6508000 0 <<
507 interrupts = <GIC_SPI <<
508 clocks = <&cpg CPG_MOD <<
509 power-domains = <&sysc <<
510 resets = <&cpg 930>; <<
511 dmas = <&dmac1 0x93>, <<
512 <&dmac2 0x93>, <<
513 dma-names = "tx", "rx" <<
514 i2c-scl-internal-delay <<
515 status = "disabled"; <<
516 }; <<
517 <<
518 i2c2: i2c@e6510000 { <<
519 #address-cells = <1>; <<
520 #size-cells = <0>; <<
521 compatible = "renesas, <<
522 "renesas, <<
523 reg = <0 0xe6510000 0 <<
524 interrupts = <GIC_SPI <<
525 clocks = <&cpg CPG_MOD <<
526 power-domains = <&sysc <<
527 resets = <&cpg 929>; <<
528 dmas = <&dmac1 0x95>, <<
529 <&dmac2 0x95>, <<
530 dma-names = "tx", "rx" <<
531 i2c-scl-internal-delay <<
532 status = "disabled"; <<
533 }; <<
534 <<
535 i2c3: i2c@e66d0000 { <<
536 #address-cells = <1>; <<
537 #size-cells = <0>; <<
538 compatible = "renesas, <<
539 "renesas, <<
540 reg = <0 0xe66d0000 0 <<
541 interrupts = <GIC_SPI <<
542 clocks = <&cpg CPG_MOD <<
543 power-domains = <&sysc <<
544 resets = <&cpg 928>; <<
545 dmas = <&dmac0 0x97>, <<
546 dma-names = "tx", "rx" <<
547 i2c-scl-internal-delay <<
548 status = "disabled"; <<
549 }; <<
550 <<
551 i2c4: i2c@e66d8000 { <<
552 #address-cells = <1>; <<
553 #size-cells = <0>; <<
554 compatible = "renesas, <<
555 "renesas, <<
556 reg = <0 0xe66d8000 0 <<
557 interrupts = <GIC_SPI <<
558 clocks = <&cpg CPG_MOD <<
559 power-domains = <&sysc <<
560 resets = <&cpg 927>; <<
561 dmas = <&dmac0 0x99>, <<
562 dma-names = "tx", "rx" <<
563 i2c-scl-internal-delay <<
564 status = "disabled"; <<
565 }; <<
566 <<
567 i2c5: i2c@e66e0000 { <<
568 #address-cells = <1>; <<
569 #size-cells = <0>; <<
570 compatible = "renesas, <<
571 "renesas, <<
572 reg = <0 0xe66e0000 0 <<
573 interrupts = <GIC_SPI <<
574 clocks = <&cpg CPG_MOD <<
575 power-domains = <&sysc <<
576 resets = <&cpg 919>; <<
577 dmas = <&dmac0 0x9b>, <<
578 dma-names = "tx", "rx" <<
579 i2c-scl-internal-delay <<
580 status = "disabled"; <<
581 }; <<
582 <<
583 i2c6: i2c@e66e8000 { <<
584 #address-cells = <1>; <<
585 #size-cells = <0>; <<
586 compatible = "renesas, <<
587 "renesas, <<
588 reg = <0 0xe66e8000 0 <<
589 interrupts = <GIC_SPI <<
590 clocks = <&cpg CPG_MOD <<
591 power-domains = <&sysc <<
592 resets = <&cpg 918>; <<
593 dmas = <&dmac0 0x9d>, <<
594 dma-names = "tx", "rx" <<
595 i2c-scl-internal-delay <<
596 status = "disabled"; <<
597 }; <<
598 <<
599 i2c7: i2c@e6690000 { <<
600 #address-cells = <1>; <<
601 #size-cells = <0>; <<
602 compatible = "renesas, <<
603 "renesas, <<
604 reg = <0 0xe6690000 0 <<
605 interrupts = <GIC_SPI <<
606 clocks = <&cpg CPG_MOD <<
607 power-domains = <&sysc <<
608 resets = <&cpg 1003>; <<
609 i2c-scl-internal-delay <<
610 status = "disabled"; <<
611 }; <<
612 <<
613 hscif0: serial@e6540000 { <<
614 compatible = "renesas, <<
615 "renesas, <<
616 "renesas, <<
617 reg = <0 0xe6540000 0 <<
618 interrupts = <GIC_SPI <<
619 clocks = <&cpg CPG_MOD <<
620 <&cpg CPG_COR <<
621 <&scif_clk>; <<
622 clock-names = "fck", " <<
623 dmas = <&dmac1 0x31>, <<
624 <&dmac2 0x31>, <<
625 dma-names = "tx", "rx" <<
626 power-domains = <&sysc <<
627 resets = <&cpg 520>; <<
628 status = "disabled"; <<
629 }; <<
630 <<
631 hscif1: serial@e6550000 { <<
632 compatible = "renesas, <<
633 "renesas, <<
634 "renesas, <<
635 reg = <0 0xe6550000 0 <<
636 interrupts = <GIC_SPI <<
637 clocks = <&cpg CPG_MOD <<
638 <&cpg CPG_COR <<
639 <&scif_clk>; <<
640 clock-names = "fck", " <<
641 dmas = <&dmac1 0x33>, <<
642 <&dmac2 0x33>, <<
643 dma-names = "tx", "rx" <<
644 power-domains = <&sysc <<
645 resets = <&cpg 519>; <<
646 status = "disabled"; <<
647 }; <<
648 <<
649 hscif2: serial@e6560000 { <<
650 compatible = "renesas, <<
651 "renesas, <<
652 "renesas, <<
653 reg = <0 0xe6560000 0 <<
654 interrupts = <GIC_SPI <<
655 clocks = <&cpg CPG_MOD <<
656 <&cpg CPG_COR <<
657 <&scif_clk>; <<
658 clock-names = "fck", " <<
659 dmas = <&dmac1 0x35>, <<
660 <&dmac2 0x35>, <<
661 dma-names = "tx", "rx" <<
662 power-domains = <&sysc <<
663 resets = <&cpg 518>; <<
664 status = "disabled"; <<
665 }; <<
666 <<
667 hscif3: serial@e66a0000 { <<
668 compatible = "renesas, <<
669 "renesas, <<
670 "renesas, <<
671 reg = <0 0xe66a0000 0 <<
672 interrupts = <GIC_SPI <<
673 clocks = <&cpg CPG_MOD <<
674 <&cpg CPG_COR <<
675 <&scif_clk>; <<
676 clock-names = "fck", " <<
677 dmas = <&dmac0 0x37>, <<
678 dma-names = "tx", "rx" <<
679 power-domains = <&sysc <<
680 resets = <&cpg 517>; <<
681 status = "disabled"; <<
682 }; <<
683 <<
684 hscif4: serial@e66b0000 { <<
685 compatible = "renesas, <<
686 "renesas, <<
687 "renesas, <<
688 reg = <0 0xe66b0000 0 <<
689 interrupts = <GIC_SPI <<
690 clocks = <&cpg CPG_MOD <<
691 <&cpg CPG_COR <<
692 <&scif_clk>; <<
693 clock-names = "fck", " <<
694 dmas = <&dmac0 0x39>, <<
695 dma-names = "tx", "rx" <<
696 power-domains = <&sysc <<
697 resets = <&cpg 516>; <<
698 status = "disabled"; <<
699 }; <<
700 <<
701 hsusb: usb@e6590000 { <<
702 compatible = "renesas, <<
703 "renesas, <<
704 reg = <0 0xe6590000 0 <<
705 interrupts = <GIC_SPI <<
706 clocks = <&cpg CPG_MOD <<
707 dmas = <&usb_dmac0 0>, <<
708 <&usb_dmac1 0>, <<
709 dma-names = "ch0", "ch <<
710 renesas,buswait = <11> <<
711 phys = <&usb2_phy0 3>; <<
712 phy-names = "usb"; <<
713 power-domains = <&sysc <<
714 resets = <&cpg 704>, < <<
715 status = "disabled"; <<
716 }; <<
717 <<
718 usb_dmac0: dma-controller@e65a <<
719 compatible = "renesas, <<
720 "renesas, <<
721 reg = <0 0xe65a0000 0 <<
722 interrupts = <GIC_SPI <<
723 <GIC_SPI <<
724 interrupt-names = "ch0 <<
725 clocks = <&cpg CPG_MOD <<
726 power-domains = <&sysc <<
727 resets = <&cpg 330>; <<
728 #dma-cells = <1>; <<
729 dma-channels = <2>; <<
730 }; <<
731 <<
732 usb_dmac1: dma-controller@e65b <<
733 compatible = "renesas, <<
734 "renesas, <<
735 reg = <0 0xe65b0000 0 <<
736 interrupts = <GIC_SPI <<
737 <GIC_SPI <<
738 interrupt-names = "ch0 <<
739 clocks = <&cpg CPG_MOD <<
740 power-domains = <&sysc <<
741 resets = <&cpg 331>; <<
742 #dma-cells = <1>; <<
743 dma-channels = <2>; <<
744 }; <<
745 <<
746 arm_cc630p: crypto@e6601000 { <<
747 compatible = "arm,cryp <<
748 interrupts = <GIC_SPI <<
749 reg = <0x0 0xe6601000 <<
750 clocks = <&cpg CPG_MOD <<
751 resets = <&cpg 229>; <<
752 power-domains = <&sysc <<
753 }; <<
754 <<
755 dmac0: dma-controller@e6700000 <<
756 compatible = "renesas, <<
757 "renesas, <<
758 reg = <0 0xe6700000 0 <<
759 interrupts = <GIC_SPI <<
760 <GIC_SPI <<
761 <GIC_SPI <<
762 <GIC_SPI <<
763 <GIC_SPI <<
764 <GIC_SPI <<
765 <GIC_SPI <<
766 <GIC_SPI <<
767 <GIC_SPI <<
768 <GIC_SPI <<
769 <GIC_SPI <<
770 <GIC_SPI <<
771 <GIC_SPI <<
772 <GIC_SPI <<
773 <GIC_SPI <<
774 <GIC_SPI <<
775 <GIC_SPI <<
776 interrupt-names = "err <<
777 "ch0", <<
778 "ch4", <<
779 "ch8", <<
780 "ch12" <<
781 clocks = <&cpg CPG_MOD <<
782 clock-names = "fck"; <<
783 power-domains = <&sysc <<
784 resets = <&cpg 219>; <<
785 #dma-cells = <1>; <<
786 dma-channels = <16>; <<
787 iommus = <&ipmmu_ds0 0 <<
788 <&ipmmu_ds0 2>, <<
789 <&ipmmu_ds0 4>, <<
790 <&ipmmu_ds0 6>, <<
791 <&ipmmu_ds0 8>, <<
792 <&ipmmu_ds0 10> <<
793 <&ipmmu_ds0 12> <<
794 <&ipmmu_ds0 14> <<
795 }; <<
796 <<
797 dmac1: dma-controller@e7300000 <<
798 compatible = "renesas, <<
799 "renesas, <<
800 reg = <0 0xe7300000 0 <<
801 interrupts = <GIC_SPI <<
802 <GIC_SPI <<
803 <GIC_SPI <<
804 <GIC_SPI <<
805 <GIC_SPI <<
806 <GIC_SPI <<
807 <GIC_SPI <<
808 <GIC_SPI <<
809 <GIC_SPI <<
810 <GIC_SPI <<
811 <GIC_SPI <<
812 <GIC_SPI <<
813 <GIC_SPI <<
814 <GIC_SPI <<
815 <GIC_SPI <<
816 <GIC_SPI <<
817 <GIC_SPI <<
818 interrupt-names = "err <<
819 "ch0", <<
820 "ch4", <<
821 "ch8", <<
822 "ch12" <<
823 clocks = <&cpg CPG_MOD <<
824 clock-names = "fck"; <<
825 power-domains = <&sysc <<
826 resets = <&cpg 218>; <<
827 #dma-cells = <1>; <<
828 dma-channels = <16>; <<
829 iommus = <&ipmmu_ds1 0 <<
830 <&ipmmu_ds1 2>, <<
831 <&ipmmu_ds1 4>, <<
832 <&ipmmu_ds1 6>, <<
833 <&ipmmu_ds1 8>, <<
834 <&ipmmu_ds1 10> <<
835 <&ipmmu_ds1 12> <<
836 <&ipmmu_ds1 14> <<
837 }; <<
838 <<
839 dmac2: dma-controller@e7310000 <<
840 compatible = "renesas, <<
841 "renesas, <<
842 reg = <0 0xe7310000 0 <<
843 interrupts = <GIC_SPI <<
844 <GIC_SPI <<
845 <GIC_SPI <<
846 <GIC_SPI <<
847 <GIC_SPI <<
848 <GIC_SPI <<
849 <GIC_SPI <<
850 <GIC_SPI <<
851 <GIC_SPI <<
852 <GIC_SPI <<
853 <GIC_SPI <<
854 <GIC_SPI <<
855 <GIC_SPI <<
856 <GIC_SPI <<
857 <GIC_SPI <<
858 <GIC_SPI <<
859 <GIC_SPI <<
860 interrupt-names = "err <<
861 "ch0", <<
862 "ch4", <<
863 "ch8", <<
864 "ch12" <<
865 clocks = <&cpg CPG_MOD <<
866 clock-names = "fck"; <<
867 power-domains = <&sysc <<
868 resets = <&cpg 217>; <<
869 #dma-cells = <1>; <<
870 dma-channels = <16>; <<
871 iommus = <&ipmmu_ds1 1 <<
872 <&ipmmu_ds1 18> <<
873 <&ipmmu_ds1 20> <<
874 <&ipmmu_ds1 22> <<
875 <&ipmmu_ds1 24> <<
876 <&ipmmu_ds1 26> <<
877 <&ipmmu_ds1 28> <<
878 <&ipmmu_ds1 30> <<
879 }; <<
880 <<
881 ipmmu_ds0: iommu@e6740000 { <<
882 compatible = "renesas, 215 compatible = "renesas,ipmmu-r8a77990";
883 reg = <0 0xe6740000 0 216 reg = <0 0xe6740000 0 0x1000>;
884 renesas,ipmmu-main = < 217 renesas,ipmmu-main = <&ipmmu_mm 0>;
885 power-domains = <&sysc 218 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
886 #iommu-cells = <1>; 219 #iommu-cells = <1>;
887 }; 220 };
888 221
889 ipmmu_ds1: iommu@e7740000 { !! 222 ipmmu_ds1: mmu@e7740000 {
890 compatible = "renesas, 223 compatible = "renesas,ipmmu-r8a77990";
891 reg = <0 0xe7740000 0 224 reg = <0 0xe7740000 0 0x1000>;
892 renesas,ipmmu-main = < 225 renesas,ipmmu-main = <&ipmmu_mm 1>;
893 power-domains = <&sysc 226 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
894 #iommu-cells = <1>; 227 #iommu-cells = <1>;
895 }; 228 };
896 229
897 ipmmu_hc: iommu@e6570000 { !! 230 ipmmu_hc: mmu@e6570000 {
898 compatible = "renesas, 231 compatible = "renesas,ipmmu-r8a77990";
899 reg = <0 0xe6570000 0 232 reg = <0 0xe6570000 0 0x1000>;
900 renesas,ipmmu-main = < 233 renesas,ipmmu-main = <&ipmmu_mm 2>;
901 power-domains = <&sysc 234 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
902 #iommu-cells = <1>; 235 #iommu-cells = <1>;
903 }; 236 };
904 237
905 ipmmu_mm: iommu@e67b0000 { !! 238 ipmmu_mm: mmu@e67b0000 {
906 compatible = "renesas, 239 compatible = "renesas,ipmmu-r8a77990";
907 reg = <0 0xe67b0000 0 240 reg = <0 0xe67b0000 0 0x1000>;
908 interrupts = <GIC_SPI 241 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
909 <GIC_SPI 242 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
910 power-domains = <&sysc 243 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
911 #iommu-cells = <1>; 244 #iommu-cells = <1>;
912 }; 245 };
913 246
914 ipmmu_mp: iommu@ec670000 { !! 247 ipmmu_mp: mmu@ec670000 {
915 compatible = "renesas, 248 compatible = "renesas,ipmmu-r8a77990";
916 reg = <0 0xec670000 0 249 reg = <0 0xec670000 0 0x1000>;
917 renesas,ipmmu-main = < 250 renesas,ipmmu-main = <&ipmmu_mm 4>;
918 power-domains = <&sysc 251 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
919 #iommu-cells = <1>; 252 #iommu-cells = <1>;
920 }; 253 };
921 254
922 ipmmu_pv0: iommu@fd800000 { !! 255 ipmmu_pv0: mmu@fd800000 {
923 compatible = "renesas, 256 compatible = "renesas,ipmmu-r8a77990";
924 reg = <0 0xfd800000 0 257 reg = <0 0xfd800000 0 0x1000>;
925 renesas,ipmmu-main = < 258 renesas,ipmmu-main = <&ipmmu_mm 6>;
926 power-domains = <&sysc 259 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
927 #iommu-cells = <1>; 260 #iommu-cells = <1>;
928 }; 261 };
929 262
930 ipmmu_rt: iommu@ffc80000 { !! 263 ipmmu_rt: mmu@ffc80000 {
931 compatible = "renesas, 264 compatible = "renesas,ipmmu-r8a77990";
932 reg = <0 0xffc80000 0 265 reg = <0 0xffc80000 0 0x1000>;
933 renesas,ipmmu-main = < 266 renesas,ipmmu-main = <&ipmmu_mm 10>;
934 power-domains = <&sysc 267 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
935 #iommu-cells = <1>; 268 #iommu-cells = <1>;
936 }; 269 };
937 270
938 ipmmu_vc0: iommu@fe6b0000 { !! 271 ipmmu_vc0: mmu@fe6b0000 {
939 compatible = "renesas, 272 compatible = "renesas,ipmmu-r8a77990";
940 reg = <0 0xfe6b0000 0 273 reg = <0 0xfe6b0000 0 0x1000>;
941 renesas,ipmmu-main = < 274 renesas,ipmmu-main = <&ipmmu_mm 12>;
942 power-domains = <&sysc 275 power-domains = <&sysc R8A77990_PD_A3VC>;
943 #iommu-cells = <1>; 276 #iommu-cells = <1>;
944 }; 277 };
945 278
946 ipmmu_vi0: iommu@febd0000 { !! 279 ipmmu_vi0: mmu@febd0000 {
947 compatible = "renesas, 280 compatible = "renesas,ipmmu-r8a77990";
948 reg = <0 0xfebd0000 0 281 reg = <0 0xfebd0000 0 0x1000>;
949 renesas,ipmmu-main = < 282 renesas,ipmmu-main = <&ipmmu_mm 14>;
950 power-domains = <&sysc 283 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
951 #iommu-cells = <1>; 284 #iommu-cells = <1>;
952 }; 285 };
953 286
954 ipmmu_vp0: iommu@fe990000 { !! 287 ipmmu_vp0: mmu@fe990000 {
955 compatible = "renesas, 288 compatible = "renesas,ipmmu-r8a77990";
956 reg = <0 0xfe990000 0 289 reg = <0 0xfe990000 0 0x1000>;
957 renesas,ipmmu-main = < 290 renesas,ipmmu-main = <&ipmmu_mm 16>;
958 power-domains = <&sysc 291 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
959 #iommu-cells = <1>; 292 #iommu-cells = <1>;
960 }; 293 };
961 294
962 avb: ethernet@e6800000 { 295 avb: ethernet@e6800000 {
963 compatible = "renesas, 296 compatible = "renesas,etheravb-r8a77990",
964 "renesas, 297 "renesas,etheravb-rcar-gen3";
965 reg = <0 0xe6800000 0 298 reg = <0 0xe6800000 0 0x800>;
966 interrupts = <GIC_SPI 299 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
967 <GIC_SPI 300 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
968 <GIC_SPI 301 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
969 <GIC_SPI 302 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
970 <GIC_SPI 303 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
971 <GIC_SPI 304 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
972 <GIC_SPI 305 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
973 <GIC_SPI 306 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
974 <GIC_SPI 307 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
975 <GIC_SPI 308 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
976 <GIC_SPI 309 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
977 <GIC_SPI 310 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
978 <GIC_SPI 311 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
979 <GIC_SPI 312 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
980 <GIC_SPI 313 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
981 <GIC_SPI 314 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
982 <GIC_SPI 315 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
983 <GIC_SPI 316 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
984 <GIC_SPI 317 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
985 <GIC_SPI 318 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
986 <GIC_SPI 319 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
987 <GIC_SPI 320 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
988 <GIC_SPI 321 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
989 <GIC_SPI 322 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
990 <GIC_SPI 323 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
991 interrupt-names = "ch0 324 interrupt-names = "ch0", "ch1", "ch2", "ch3",
992 "ch4 325 "ch4", "ch5", "ch6", "ch7",
993 "ch8 326 "ch8", "ch9", "ch10", "ch11",
994 "ch1 327 "ch12", "ch13", "ch14", "ch15",
995 "ch1 328 "ch16", "ch17", "ch18", "ch19",
996 "ch2 329 "ch20", "ch21", "ch22", "ch23",
997 "ch2 330 "ch24";
998 clocks = <&cpg CPG_MOD 331 clocks = <&cpg CPG_MOD 812>;
999 clock-names = "fck"; !! 332 power-domains = <&sysc 32>;
1000 power-domains = <&sys <<
1001 resets = <&cpg 812>; 333 resets = <&cpg 812>;
1002 phy-mode = "rgmii"; 334 phy-mode = "rgmii";
1003 rx-internal-delay-ps <<
1004 iommus = <&ipmmu_ds0 <<
1005 #address-cells = <1>; 335 #address-cells = <1>;
1006 #size-cells = <0>; 336 #size-cells = <0>;
1007 status = "disabled"; 337 status = "disabled";
1008 }; 338 };
1009 339
1010 can0: can@e6c30000 { <<
1011 compatible = "renesas <<
1012 "renesas <<
1013 reg = <0 0xe6c30000 0 <<
1014 interrupts = <GIC_SPI <<
1015 clocks = <&cpg CPG_MO <<
1016 <&cpg CPG_CORE <<
1017 <&can_clk>; <<
1018 clock-names = "clkp1" <<
1019 assigned-clocks = <&c <<
1020 assigned-clock-rates <<
1021 power-domains = <&sys <<
1022 resets = <&cpg 916>; <<
1023 status = "disabled"; <<
1024 }; <<
1025 <<
1026 can1: can@e6c38000 { <<
1027 compatible = "renesas <<
1028 "renesas <<
1029 reg = <0 0xe6c38000 0 <<
1030 interrupts = <GIC_SPI <<
1031 clocks = <&cpg CPG_MO <<
1032 <&cpg CPG_CORE <<
1033 <&can_clk>; <<
1034 clock-names = "clkp1" <<
1035 assigned-clocks = <&c <<
1036 assigned-clock-rates <<
1037 power-domains = <&sys <<
1038 resets = <&cpg 915>; <<
1039 status = "disabled"; <<
1040 }; <<
1041 <<
1042 canfd: can@e66c0000 { <<
1043 compatible = "renesas <<
1044 "renesas <<
1045 reg = <0 0xe66c0000 0 <<
1046 interrupts = <GIC_SPI <<
1047 <GIC_SPI 3 <<
1048 interrupt-names = "ch <<
1049 clocks = <&cpg CPG_MO <<
1050 <&cpg CPG_CORE <<
1051 <&can_clk>; <<
1052 clock-names = "fck", <<
1053 assigned-clocks = <&c <<
1054 assigned-clock-rates <<
1055 power-domains = <&sys <<
1056 resets = <&cpg 914>; <<
1057 status = "disabled"; <<
1058 <<
1059 channel0 { <<
1060 status = "dis <<
1061 }; <<
1062 <<
1063 channel1 { <<
1064 status = "dis <<
1065 }; <<
1066 }; <<
1067 <<
1068 pwm0: pwm@e6e30000 { <<
1069 compatible = "renesas <<
1070 reg = <0 0xe6e30000 0 <<
1071 clocks = <&cpg CPG_MO <<
1072 power-domains = <&sys <<
1073 resets = <&cpg 523>; <<
1074 #pwm-cells = <2>; <<
1075 status = "disabled"; <<
1076 }; <<
1077 <<
1078 pwm1: pwm@e6e31000 { <<
1079 compatible = "renesas <<
1080 reg = <0 0xe6e31000 0 <<
1081 clocks = <&cpg CPG_MO <<
1082 power-domains = <&sys <<
1083 resets = <&cpg 523>; <<
1084 #pwm-cells = <2>; <<
1085 status = "disabled"; <<
1086 }; <<
1087 <<
1088 pwm2: pwm@e6e32000 { <<
1089 compatible = "renesas <<
1090 reg = <0 0xe6e32000 0 <<
1091 clocks = <&cpg CPG_MO <<
1092 power-domains = <&sys <<
1093 resets = <&cpg 523>; <<
1094 #pwm-cells = <2>; <<
1095 status = "disabled"; <<
1096 }; <<
1097 <<
1098 pwm3: pwm@e6e33000 { <<
1099 compatible = "renesas <<
1100 reg = <0 0xe6e33000 0 <<
1101 clocks = <&cpg CPG_MO <<
1102 power-domains = <&sys <<
1103 resets = <&cpg 523>; <<
1104 #pwm-cells = <2>; <<
1105 status = "disabled"; <<
1106 }; <<
1107 <<
1108 pwm4: pwm@e6e34000 { <<
1109 compatible = "renesas <<
1110 reg = <0 0xe6e34000 0 <<
1111 clocks = <&cpg CPG_MO <<
1112 power-domains = <&sys <<
1113 resets = <&cpg 523>; <<
1114 #pwm-cells = <2>; <<
1115 status = "disabled"; <<
1116 }; <<
1117 <<
1118 pwm5: pwm@e6e35000 { <<
1119 compatible = "renesas <<
1120 reg = <0 0xe6e35000 0 <<
1121 clocks = <&cpg CPG_MO <<
1122 power-domains = <&sys <<
1123 resets = <&cpg 523>; <<
1124 #pwm-cells = <2>; <<
1125 status = "disabled"; <<
1126 }; <<
1127 <<
1128 pwm6: pwm@e6e36000 { <<
1129 compatible = "renesas <<
1130 reg = <0 0xe6e36000 0 <<
1131 clocks = <&cpg CPG_MO <<
1132 power-domains = <&sys <<
1133 resets = <&cpg 523>; <<
1134 #pwm-cells = <2>; <<
1135 status = "disabled"; <<
1136 }; <<
1137 <<
1138 scif0: serial@e6e60000 { <<
1139 compatible = "renesas <<
1140 "renesas <<
1141 reg = <0 0xe6e60000 0 <<
1142 interrupts = <GIC_SPI <<
1143 clocks = <&cpg CPG_MO <<
1144 <&cpg CPG_CO <<
1145 <&scif_clk>; <<
1146 clock-names = "fck", <<
1147 dmas = <&dmac1 0x51>, <<
1148 <&dmac2 0x51>, <<
1149 dma-names = "tx", "rx <<
1150 power-domains = <&sys <<
1151 resets = <&cpg 207>; <<
1152 status = "disabled"; <<
1153 }; <<
1154 <<
1155 scif1: serial@e6e68000 { <<
1156 compatible = "renesas <<
1157 "renesas <<
1158 reg = <0 0xe6e68000 0 <<
1159 interrupts = <GIC_SPI <<
1160 clocks = <&cpg CPG_MO <<
1161 <&cpg CPG_CO <<
1162 <&scif_clk>; <<
1163 clock-names = "fck", <<
1164 dmas = <&dmac1 0x53>, <<
1165 <&dmac2 0x53>, <<
1166 dma-names = "tx", "rx <<
1167 power-domains = <&sys <<
1168 resets = <&cpg 206>; <<
1169 status = "disabled"; <<
1170 }; <<
1171 <<
1172 scif2: serial@e6e88000 { 340 scif2: serial@e6e88000 {
1173 compatible = "renesas 341 compatible = "renesas,scif-r8a77990",
1174 "renesas 342 "renesas,rcar-gen3-scif", "renesas,scif";
1175 reg = <0 0xe6e88000 0 343 reg = <0 0xe6e88000 0 64>;
1176 interrupts = <GIC_SPI 344 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
1177 clocks = <&cpg CPG_MO !! 345 clocks = <&cpg CPG_MOD 310>;
1178 <&cpg CPG_CO <<
1179 <&scif_clk>; <<
1180 clock-names = "fck", <<
1181 dmas = <&dmac1 0x13>, <<
1182 <&dmac2 0x13>, <<
1183 dma-names = "tx", "rx <<
1184 power-domains = <&sys <<
1185 resets = <&cpg 310>; <<
1186 status = "disabled"; <<
1187 }; <<
1188 <<
1189 scif3: serial@e6c50000 { <<
1190 compatible = "renesas <<
1191 "renesas <<
1192 reg = <0 0xe6c50000 0 <<
1193 interrupts = <GIC_SPI <<
1194 clocks = <&cpg CPG_MO <<
1195 <&cpg CPG_CO <<
1196 <&scif_clk>; <<
1197 clock-names = "fck", <<
1198 dmas = <&dmac0 0x57>, <<
1199 dma-names = "tx", "rx <<
1200 power-domains = <&sys <<
1201 resets = <&cpg 204>; <<
1202 status = "disabled"; <<
1203 }; <<
1204 <<
1205 scif4: serial@e6c40000 { <<
1206 compatible = "renesas <<
1207 "renesas <<
1208 reg = <0 0xe6c40000 0 <<
1209 interrupts = <GIC_SPI <<
1210 clocks = <&cpg CPG_MO <<
1211 <&cpg CPG_CO <<
1212 <&scif_clk>; <<
1213 clock-names = "fck", <<
1214 dmas = <&dmac0 0x59>, <<
1215 dma-names = "tx", "rx <<
1216 power-domains = <&sys <<
1217 resets = <&cpg 203>; <<
1218 status = "disabled"; <<
1219 }; <<
1220 <<
1221 scif5: serial@e6f30000 { <<
1222 compatible = "renesas <<
1223 "renesas <<
1224 reg = <0 0xe6f30000 0 <<
1225 interrupts = <GIC_SPI <<
1226 clocks = <&cpg CPG_MO <<
1227 <&cpg CPG_CO <<
1228 <&scif_clk>; <<
1229 clock-names = "fck", <<
1230 dmas = <&dmac0 0x5b>, <<
1231 dma-names = "tx", "rx <<
1232 power-domains = <&sys <<
1233 resets = <&cpg 202>; <<
1234 status = "disabled"; <<
1235 }; <<
1236 <<
1237 msiof0: spi@e6e90000 { <<
1238 compatible = "renesas <<
1239 "renesas <<
1240 reg = <0 0xe6e90000 0 <<
1241 interrupts = <GIC_SPI <<
1242 clocks = <&cpg CPG_MO <<
1243 dmas = <&dmac1 0x41>, <<
1244 <&dmac2 0x41>, <<
1245 dma-names = "tx", "rx <<
1246 power-domains = <&sys <<
1247 resets = <&cpg 211>; <<
1248 #address-cells = <1>; <<
1249 #size-cells = <0>; <<
1250 status = "disabled"; <<
1251 }; <<
1252 <<
1253 msiof1: spi@e6ea0000 { <<
1254 compatible = "renesas <<
1255 "renesas <<
1256 reg = <0 0xe6ea0000 0 <<
1257 interrupts = <GIC_SPI <<
1258 clocks = <&cpg CPG_MO <<
1259 dmas = <&dmac0 0x43>, <<
1260 dma-names = "tx", "rx <<
1261 power-domains = <&sys <<
1262 resets = <&cpg 210>; <<
1263 #address-cells = <1>; <<
1264 #size-cells = <0>; <<
1265 status = "disabled"; <<
1266 }; <<
1267 <<
1268 msiof2: spi@e6c00000 { <<
1269 compatible = "renesas <<
1270 "renesas <<
1271 reg = <0 0xe6c00000 0 <<
1272 interrupts = <GIC_SPI <<
1273 clocks = <&cpg CPG_MO <<
1274 dmas = <&dmac0 0x45>, <<
1275 dma-names = "tx", "rx <<
1276 power-domains = <&sys <<
1277 resets = <&cpg 209>; <<
1278 #address-cells = <1>; <<
1279 #size-cells = <0>; <<
1280 status = "disabled"; <<
1281 }; <<
1282 <<
1283 msiof3: spi@e6c10000 { <<
1284 compatible = "renesas <<
1285 "renesas <<
1286 reg = <0 0xe6c10000 0 <<
1287 interrupts = <GIC_SPI <<
1288 clocks = <&cpg CPG_MO <<
1289 dmas = <&dmac0 0x47>, <<
1290 dma-names = "tx", "rx <<
1291 power-domains = <&sys <<
1292 resets = <&cpg 208>; <<
1293 #address-cells = <1>; <<
1294 #size-cells = <0>; <<
1295 status = "disabled"; <<
1296 }; <<
1297 <<
1298 vin4: video@e6ef4000 { <<
1299 compatible = "renesas <<
1300 reg = <0 0xe6ef4000 0 <<
1301 interrupts = <GIC_SPI <<
1302 clocks = <&cpg CPG_MO <<
1303 power-domains = <&sys <<
1304 resets = <&cpg 807>; <<
1305 renesas,id = <4>; <<
1306 status = "disabled"; <<
1307 <<
1308 ports { <<
1309 #address-cell <<
1310 #size-cells = <<
1311 <<
1312 port@1 { <<
1313 #addr <<
1314 #size <<
1315 <<
1316 reg = <<
1317 <<
1318 vin4c <<
1319 <<
1320 <<
1321 }; <<
1322 }; <<
1323 }; <<
1324 }; <<
1325 <<
1326 vin5: video@e6ef5000 { <<
1327 compatible = "renesas <<
1328 reg = <0 0xe6ef5000 0 <<
1329 interrupts = <GIC_SPI <<
1330 clocks = <&cpg CPG_MO <<
1331 power-domains = <&sys <<
1332 resets = <&cpg 806>; <<
1333 renesas,id = <5>; <<
1334 status = "disabled"; <<
1335 <<
1336 ports { <<
1337 #address-cell <<
1338 #size-cells = <<
1339 <<
1340 port@1 { <<
1341 #addr <<
1342 #size <<
1343 <<
1344 reg = <<
1345 <<
1346 vin5c <<
1347 <<
1348 <<
1349 }; <<
1350 }; <<
1351 }; <<
1352 }; <<
1353 <<
1354 drif00: rif@e6f40000 { <<
1355 compatible = "renesas <<
1356 "renesas <<
1357 reg = <0 0xe6f40000 0 <<
1358 interrupts = <GIC_SPI <<
1359 clocks = <&cpg CPG_MO <<
1360 clock-names = "fck"; <<
1361 dmas = <&dmac1 0x20>, <<
1362 dma-names = "rx", "rx <<
1363 power-domains = <&sys <<
1364 resets = <&cpg 515>; <<
1365 renesas,bonding = <&d <<
1366 status = "disabled"; <<
1367 }; <<
1368 <<
1369 drif01: rif@e6f50000 { <<
1370 compatible = "renesas <<
1371 "renesas <<
1372 reg = <0 0xe6f50000 0 <<
1373 interrupts = <GIC_SPI <<
1374 clocks = <&cpg CPG_MO <<
1375 clock-names = "fck"; 346 clock-names = "fck";
1376 dmas = <&dmac1 0x22>, !! 347 power-domains = <&sysc 32>;
1377 dma-names = "rx", "rx !! 348 resets = <&cpg 310>;
1378 power-domains = <&sys <<
1379 resets = <&cpg 514>; <<
1380 renesas,bonding = <&d <<
1381 status = "disabled"; <<
1382 }; <<
1383 <<
1384 drif10: rif@e6f60000 { <<
1385 compatible = "renesas <<
1386 "renesas <<
1387 reg = <0 0xe6f60000 0 <<
1388 interrupts = <GIC_SPI <<
1389 clocks = <&cpg CPG_MO <<
1390 clock-names = "fck"; <<
1391 dmas = <&dmac1 0x24>, <<
1392 dma-names = "rx", "rx <<
1393 power-domains = <&sys <<
1394 resets = <&cpg 513>; <<
1395 renesas,bonding = <&d <<
1396 status = "disabled"; <<
1397 }; <<
1398 <<
1399 drif11: rif@e6f70000 { <<
1400 compatible = "renesas <<
1401 "renesas <<
1402 reg = <0 0xe6f70000 0 <<
1403 interrupts = <GIC_SPI <<
1404 clocks = <&cpg CPG_MO <<
1405 clock-names = "fck"; <<
1406 dmas = <&dmac1 0x26>, <<
1407 dma-names = "rx", "rx <<
1408 power-domains = <&sys <<
1409 resets = <&cpg 512>; <<
1410 renesas,bonding = <&d <<
1411 status = "disabled"; <<
1412 }; <<
1413 <<
1414 drif20: rif@e6f80000 { <<
1415 compatible = "renesas <<
1416 "renesas <<
1417 reg = <0 0xe6f80000 0 <<
1418 interrupts = <GIC_SPI <<
1419 clocks = <&cpg CPG_MO <<
1420 clock-names = "fck"; <<
1421 dmas = <&dmac0 0x28>; <<
1422 dma-names = "rx"; <<
1423 power-domains = <&sys <<
1424 resets = <&cpg 511>; <<
1425 renesas,bonding = <&d <<
1426 status = "disabled"; <<
1427 }; <<
1428 <<
1429 drif21: rif@e6f90000 { <<
1430 compatible = "renesas <<
1431 "renesas <<
1432 reg = <0 0xe6f90000 0 <<
1433 interrupts = <GIC_SPI <<
1434 clocks = <&cpg CPG_MO <<
1435 clock-names = "fck"; <<
1436 dmas = <&dmac0 0x2a>; <<
1437 dma-names = "rx"; <<
1438 power-domains = <&sys <<
1439 resets = <&cpg 510>; <<
1440 renesas,bonding = <&d <<
1441 status = "disabled"; <<
1442 }; <<
1443 <<
1444 drif30: rif@e6fa0000 { <<
1445 compatible = "renesas <<
1446 "renesas <<
1447 reg = <0 0xe6fa0000 0 <<
1448 interrupts = <GIC_SPI <<
1449 clocks = <&cpg CPG_MO <<
1450 clock-names = "fck"; <<
1451 dmas = <&dmac0 0x2c>; <<
1452 dma-names = "rx"; <<
1453 power-domains = <&sys <<
1454 resets = <&cpg 509>; <<
1455 renesas,bonding = <&d <<
1456 status = "disabled"; <<
1457 }; <<
1458 <<
1459 drif31: rif@e6fb0000 { <<
1460 compatible = "renesas <<
1461 "renesas <<
1462 reg = <0 0xe6fb0000 0 <<
1463 interrupts = <GIC_SPI <<
1464 clocks = <&cpg CPG_MO <<
1465 clock-names = "fck"; <<
1466 dmas = <&dmac0 0x2e>; <<
1467 dma-names = "rx"; <<
1468 power-domains = <&sys <<
1469 resets = <&cpg 508>; <<
1470 renesas,bonding = <&d <<
1471 status = "disabled"; <<
1472 }; <<
1473 <<
1474 rcar_sound: sound@ec500000 { <<
1475 /* <<
1476 * #sound-dai-cells i <<
1477 * <<
1478 * Single DAI : #soun <<
1479 * Multi DAI : #soun <<
1480 */ <<
1481 /* <<
1482 * #clock-cells is re <<
1483 * <<
1484 * clkout : #cl <<
1485 * clkout0/1/2/3: #cl <<
1486 */ <<
1487 compatible = "renesas <<
1488 reg = <0 0xec500000 0 <<
1489 <0 0xec5a0000 0 <<
1490 <0 0xec540000 0 <<
1491 <0 0xec541000 0 <<
1492 <0 0xec760000 0 <<
1493 reg-names = "scu", "a <<
1494 <<
1495 clocks = <&cpg CPG_MO <<
1496 <&cpg CPG_MO <<
1497 <&cpg CPG_MO <<
1498 <&cpg CPG_MO <<
1499 <&cpg CPG_MO <<
1500 <&cpg CPG_MO <<
1501 <&cpg CPG_MO <<
1502 <&cpg CPG_MO <<
1503 <&cpg CPG_MO <<
1504 <&cpg CPG_MO <<
1505 <&cpg CPG_MO <<
1506 <&cpg CPG_MO <<
1507 <&cpg CPG_MO <<
1508 <&cpg CPG_MO <<
1509 <&audio_clk_ <<
1510 <&audio_clk_ <<
1511 <&cpg CPG_MO <<
1512 clock-names = "ssi-al <<
1513 "ssi.9" <<
1514 "ssi.5" <<
1515 "ssi.1" <<
1516 "src.9" <<
1517 "src.5" <<
1518 "src.1" <<
1519 "mix.1" <<
1520 "ctu.1" <<
1521 "dvc.0" <<
1522 "clk_a" <<
1523 power-domains = <&sys <<
1524 resets = <&cpg 1005>, <<
1525 <&cpg 1006>, <<
1526 <&cpg 1008>, <<
1527 <&cpg 1010>, <<
1528 <&cpg 1012>, <<
1529 <&cpg 1014>, <<
1530 reset-names = "ssi-al <<
1531 "ssi.9" <<
1532 "ssi.5" <<
1533 "ssi.1" <<
1534 status = "disabled"; <<
1535 <<
1536 rcar_sound,ctu { <<
1537 ctu00: ctu-0 <<
1538 ctu01: ctu-1 <<
1539 ctu02: ctu-2 <<
1540 ctu03: ctu-3 <<
1541 ctu10: ctu-4 <<
1542 ctu11: ctu-5 <<
1543 ctu12: ctu-6 <<
1544 ctu13: ctu-7 <<
1545 }; <<
1546 <<
1547 rcar_sound,dvc { <<
1548 dvc0: dvc-0 { <<
1549 dmas <<
1550 dma-n <<
1551 }; <<
1552 dvc1: dvc-1 { <<
1553 dmas <<
1554 dma-n <<
1555 }; <<
1556 }; <<
1557 <<
1558 rcar_sound,mix { <<
1559 mix0: mix-0 { <<
1560 mix1: mix-1 { <<
1561 }; <<
1562 <<
1563 rcar_sound,src { <<
1564 src0: src-0 { <<
1565 inter <<
1566 dmas <<
1567 dma-n <<
1568 }; <<
1569 src1: src-1 { <<
1570 inter <<
1571 dmas <<
1572 dma-n <<
1573 }; <<
1574 src2: src-2 { <<
1575 inter <<
1576 dmas <<
1577 dma-n <<
1578 }; <<
1579 src3: src-3 { <<
1580 inter <<
1581 dmas <<
1582 dma-n <<
1583 }; <<
1584 src4: src-4 { <<
1585 inter <<
1586 dmas <<
1587 dma-n <<
1588 }; <<
1589 src5: src-5 { <<
1590 inter <<
1591 dmas <<
1592 dma-n <<
1593 }; <<
1594 src6: src-6 { <<
1595 inter <<
1596 dmas <<
1597 dma-n <<
1598 }; <<
1599 src7: src-7 { <<
1600 inter <<
1601 dmas <<
1602 dma-n <<
1603 }; <<
1604 src8: src-8 { <<
1605 inter <<
1606 dmas <<
1607 dma-n <<
1608 }; <<
1609 src9: src-9 { <<
1610 inter <<
1611 dmas <<
1612 dma-n <<
1613 }; <<
1614 }; <<
1615 <<
1616 rcar_sound,ssi { <<
1617 ssi0: ssi-0 { <<
1618 inter <<
1619 dmas <<
1620 <<
1621 dma-n <<
1622 }; <<
1623 ssi1: ssi-1 { <<
1624 inter <<
1625 dmas <<
1626 <<
1627 dma-n <<
1628 }; <<
1629 ssi2: ssi-2 { <<
1630 inter <<
1631 dmas <<
1632 <<
1633 dma-n <<
1634 }; <<
1635 ssi3: ssi-3 { <<
1636 inter <<
1637 dmas <<
1638 <<
1639 dma-n <<
1640 }; <<
1641 ssi4: ssi-4 { <<
1642 inter <<
1643 dmas <<
1644 <<
1645 dma-n <<
1646 }; <<
1647 ssi5: ssi-5 { <<
1648 inter <<
1649 dmas <<
1650 <<
1651 dma-n <<
1652 }; <<
1653 ssi6: ssi-6 { <<
1654 inter <<
1655 dmas <<
1656 <<
1657 dma-n <<
1658 }; <<
1659 ssi7: ssi-7 { <<
1660 inter <<
1661 dmas <<
1662 <<
1663 dma-n <<
1664 }; <<
1665 ssi8: ssi-8 { <<
1666 inter <<
1667 dmas <<
1668 <<
1669 dma-n <<
1670 }; <<
1671 ssi9: ssi-9 { <<
1672 inter <<
1673 dmas <<
1674 <<
1675 dma-n <<
1676 }; <<
1677 }; <<
1678 }; <<
1679 <<
1680 mlp: mlp@ec520000 { <<
1681 compatible = "renesas <<
1682 "renesas <<
1683 reg = <0 0xec520000 0 <<
1684 interrupts = <GIC_SPI <<
1685 <GIC_SPI 385 <<
1686 clocks = <&cpg CPG_MO <<
1687 power-domains = <&sys <<
1688 resets = <&cpg 802>; <<
1689 status = "disabled"; 349 status = "disabled";
1690 }; 350 };
1691 351
1692 audma0: dma-controller@ec7000 <<
1693 compatible = "renesas <<
1694 "renesas <<
1695 reg = <0 0xec700000 0 <<
1696 interrupts = <GIC_SPI <<
1697 <GIC_SPI <<
1698 <GIC_SPI <<
1699 <GIC_SPI <<
1700 <GIC_SPI <<
1701 <GIC_SPI <<
1702 <GIC_SPI <<
1703 <GIC_SPI <<
1704 <GIC_SPI <<
1705 <GIC_SPI <<
1706 <GIC_SPI <<
1707 <GIC_SPI <<
1708 <GIC_SPI <<
1709 <GIC_SPI <<
1710 <GIC_SPI <<
1711 <GIC_SPI <<
1712 <GIC_SPI <<
1713 interrupt-names = "er <<
1714 "ch0" <<
1715 "ch4" <<
1716 "ch8" <<
1717 "ch12 <<
1718 clocks = <&cpg CPG_MO <<
1719 clock-names = "fck"; <<
1720 power-domains = <&sys <<
1721 resets = <&cpg 502>; <<
1722 #dma-cells = <1>; <<
1723 dma-channels = <16>; <<
1724 iommus = <&ipmmu_mp 0 <<
1725 <&ipmmu_mp 2 <<
1726 <&ipmmu_mp 4 <<
1727 <&ipmmu_mp 6 <<
1728 <&ipmmu_mp 8 <<
1729 <&ipmmu_mp 1 <<
1730 <&ipmmu_mp 1 <<
1731 <&ipmmu_mp 1 <<
1732 }; <<
1733 <<
1734 xhci0: usb@ee000000 { 352 xhci0: usb@ee000000 {
1735 compatible = "renesas 353 compatible = "renesas,xhci-r8a77990",
1736 "renesas 354 "renesas,rcar-gen3-xhci";
1737 reg = <0 0xee000000 0 355 reg = <0 0xee000000 0 0xc00>;
1738 interrupts = <GIC_SPI 356 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1739 clocks = <&cpg CPG_MO 357 clocks = <&cpg CPG_MOD 328>;
1740 power-domains = <&sys 358 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1741 resets = <&cpg 328>; 359 resets = <&cpg 328>;
1742 status = "disabled"; 360 status = "disabled";
1743 }; 361 };
1744 362
1745 usb3_peri0: usb@ee020000 { <<
1746 compatible = "renesas <<
1747 "renesas <<
1748 reg = <0 0xee020000 0 <<
1749 interrupts = <GIC_SPI <<
1750 clocks = <&cpg CPG_MO <<
1751 power-domains = <&sys <<
1752 resets = <&cpg 328>; <<
1753 status = "disabled"; <<
1754 }; <<
1755 <<
1756 ohci0: usb@ee080000 { 363 ohci0: usb@ee080000 {
1757 compatible = "generic 364 compatible = "generic-ohci";
1758 reg = <0 0xee080000 0 365 reg = <0 0xee080000 0 0x100>;
1759 interrupts = <GIC_SPI 366 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1760 clocks = <&cpg CPG_MO !! 367 clocks = <&cpg CPG_MOD 703>;
1761 phys = <&usb2_phy0 1> !! 368 phys = <&usb2_phy0>;
1762 phy-names = "usb"; 369 phy-names = "usb";
1763 power-domains = <&sys !! 370 power-domains = <&sysc 32>;
1764 resets = <&cpg 703>, !! 371 resets = <&cpg 703>;
1765 status = "disabled"; 372 status = "disabled";
1766 }; 373 };
1767 374
1768 ehci0: usb@ee080100 { 375 ehci0: usb@ee080100 {
1769 compatible = "generic 376 compatible = "generic-ehci";
1770 reg = <0 0xee080100 0 377 reg = <0 0xee080100 0 0x100>;
1771 interrupts = <GIC_SPI 378 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1772 clocks = <&cpg CPG_MO !! 379 clocks = <&cpg CPG_MOD 703>;
1773 phys = <&usb2_phy0 2> !! 380 phys = <&usb2_phy0>;
1774 phy-names = "usb"; 381 phy-names = "usb";
1775 companion = <&ohci0>; 382 companion = <&ohci0>;
1776 power-domains = <&sys !! 383 power-domains = <&sysc 32>;
1777 resets = <&cpg 703>, !! 384 resets = <&cpg 703>;
1778 status = "disabled"; 385 status = "disabled";
1779 }; 386 };
1780 387
1781 usb2_phy0: usb-phy@ee080200 { 388 usb2_phy0: usb-phy@ee080200 {
1782 compatible = "renesas 389 compatible = "renesas,usb2-phy-r8a77990",
1783 "renesas 390 "renesas,rcar-gen3-usb2-phy";
1784 reg = <0 0xee080200 0 391 reg = <0 0xee080200 0 0x700>;
1785 interrupts = <GIC_SPI 392 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1786 clocks = <&cpg CPG_MO !! 393 clocks = <&cpg CPG_MOD 703>;
1787 power-domains = <&sys !! 394 power-domains = <&sysc 32>;
1788 resets = <&cpg 703>, !! 395 resets = <&cpg 703>;
1789 #phy-cells = <1>; !! 396 #phy-cells = <0>;
1790 status = "disabled"; <<
1791 }; <<
1792 <<
1793 sdhi0: mmc@ee100000 { <<
1794 compatible = "renesas <<
1795 "renesas <<
1796 reg = <0 0xee100000 0 <<
1797 interrupts = <GIC_SPI <<
1798 clocks = <&cpg CPG_MO <<
1799 clock-names = "core", <<
1800 max-frequency = <2000 <<
1801 power-domains = <&sys <<
1802 resets = <&cpg 314>; <<
1803 iommus = <&ipmmu_ds1 <<
1804 status = "disabled"; <<
1805 }; <<
1806 <<
1807 sdhi1: mmc@ee120000 { <<
1808 compatible = "renesas <<
1809 "renesas <<
1810 reg = <0 0xee120000 0 <<
1811 interrupts = <GIC_SPI <<
1812 clocks = <&cpg CPG_MO <<
1813 clock-names = "core", <<
1814 max-frequency = <2000 <<
1815 power-domains = <&sys <<
1816 resets = <&cpg 313>; <<
1817 iommus = <&ipmmu_ds1 <<
1818 status = "disabled"; <<
1819 }; <<
1820 <<
1821 sdhi3: mmc@ee160000 { <<
1822 compatible = "renesas <<
1823 "renesas <<
1824 reg = <0 0xee160000 0 <<
1825 interrupts = <GIC_SPI <<
1826 clocks = <&cpg CPG_MO <<
1827 clock-names = "core", <<
1828 max-frequency = <2000 <<
1829 power-domains = <&sys <<
1830 resets = <&cpg 311>; <<
1831 iommus = <&ipmmu_ds1 <<
1832 status = "disabled"; <<
1833 }; <<
1834 <<
1835 rpc: spi@ee200000 { <<
1836 compatible = "renesas <<
1837 "renesas <<
1838 reg = <0 0xee200000 0 <<
1839 <0 0x08000000 0 <<
1840 <0 0xee208000 0 <<
1841 reg-names = "regs", " <<
1842 interrupts = <GIC_SPI <<
1843 clocks = <&cpg CPG_MO <<
1844 power-domains = <&sys <<
1845 resets = <&cpg 917>; <<
1846 #address-cells = <1>; <<
1847 #size-cells = <0>; <<
1848 status = "disabled"; 397 status = "disabled";
1849 }; 398 };
1850 399
1851 gic: interrupt-controller@f10 400 gic: interrupt-controller@f1010000 {
1852 compatible = "arm,gic 401 compatible = "arm,gic-400";
1853 #interrupt-cells = <3 402 #interrupt-cells = <3>;
1854 #address-cells = <0>; 403 #address-cells = <0>;
1855 interrupt-controller; 404 interrupt-controller;
1856 reg = <0x0 0xf1010000 405 reg = <0x0 0xf1010000 0 0x1000>,
1857 <0x0 0xf1020000 406 <0x0 0xf1020000 0 0x20000>,
1858 <0x0 0xf1040000 407 <0x0 0xf1040000 0 0x20000>,
1859 <0x0 0xf1060000 408 <0x0 0xf1060000 0 0x20000>;
1860 interrupts = <GIC_PPI 409 interrupts = <GIC_PPI 9
1861 (GIC_ 410 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
1862 clocks = <&cpg CPG_MO 411 clocks = <&cpg CPG_MOD 408>;
1863 clock-names = "clk"; 412 clock-names = "clk";
1864 power-domains = <&sys !! 413 power-domains = <&sysc 32>;
1865 resets = <&cpg 408>; 414 resets = <&cpg 408>;
1866 }; 415 };
1867 416
1868 pciec0: pcie@fe000000 { <<
1869 compatible = "renesas <<
1870 "renesas <<
1871 reg = <0 0xfe000000 0 <<
1872 #address-cells = <3>; <<
1873 #size-cells = <2>; <<
1874 bus-range = <0x00 0xf <<
1875 device_type = "pci"; <<
1876 ranges = <0x01000000 <<
1877 <0x02000000 <<
1878 <0x02000000 <<
1879 <0x42000000 <<
1880 /* Map all possible D <<
1881 dma-ranges = <0x42000 <<
1882 interrupts = <GIC_SPI <<
1883 <GIC_SPI <<
1884 <GIC_SPI <<
1885 #interrupt-cells = <1 <<
1886 interrupt-map-mask = <<
1887 interrupt-map = <0 0 <<
1888 clocks = <&cpg CPG_MO <<
1889 clock-names = "pcie", <<
1890 power-domains = <&sys <<
1891 resets = <&cpg 319>; <<
1892 iommu-map = <0 &ipmmu <<
1893 iommu-map-mask = <0>; <<
1894 status = "disabled"; <<
1895 }; <<
1896 <<
1897 vspb0: vsp@fe960000 { <<
1898 compatible = "renesas <<
1899 reg = <0 0xfe960000 0 <<
1900 interrupts = <GIC_SPI <<
1901 clocks = <&cpg CPG_MO <<
1902 power-domains = <&sys <<
1903 resets = <&cpg 626>; <<
1904 renesas,fcp = <&fcpvb <<
1905 }; <<
1906 <<
1907 fcpvb0: fcp@fe96f000 { <<
1908 compatible = "renesas <<
1909 reg = <0 0xfe96f000 0 <<
1910 clocks = <&cpg CPG_MO <<
1911 power-domains = <&sys <<
1912 resets = <&cpg 607>; <<
1913 iommus = <&ipmmu_vp0 <<
1914 }; <<
1915 <<
1916 vspi0: vsp@fe9a0000 { <<
1917 compatible = "renesas <<
1918 reg = <0 0xfe9a0000 0 <<
1919 interrupts = <GIC_SPI <<
1920 clocks = <&cpg CPG_MO <<
1921 power-domains = <&sys <<
1922 resets = <&cpg 631>; <<
1923 renesas,fcp = <&fcpvi <<
1924 }; <<
1925 <<
1926 fcpvi0: fcp@fe9af000 { <<
1927 compatible = "renesas <<
1928 reg = <0 0xfe9af000 0 <<
1929 clocks = <&cpg CPG_MO <<
1930 power-domains = <&sys <<
1931 resets = <&cpg 611>; <<
1932 iommus = <&ipmmu_vp0 <<
1933 }; <<
1934 <<
1935 vspd0: vsp@fea20000 { <<
1936 compatible = "renesas <<
1937 reg = <0 0xfea20000 0 <<
1938 interrupts = <GIC_SPI <<
1939 clocks = <&cpg CPG_MO <<
1940 power-domains = <&sys <<
1941 resets = <&cpg 623>; <<
1942 renesas,fcp = <&fcpvd <<
1943 }; <<
1944 <<
1945 fcpvd0: fcp@fea27000 { <<
1946 compatible = "renesas <<
1947 reg = <0 0xfea27000 0 <<
1948 clocks = <&cpg CPG_MO <<
1949 power-domains = <&sys <<
1950 resets = <&cpg 603>; <<
1951 iommus = <&ipmmu_vi0 <<
1952 }; <<
1953 <<
1954 vspd1: vsp@fea28000 { <<
1955 compatible = "renesas <<
1956 reg = <0 0xfea28000 0 <<
1957 interrupts = <GIC_SPI <<
1958 clocks = <&cpg CPG_MO <<
1959 power-domains = <&sys <<
1960 resets = <&cpg 622>; <<
1961 renesas,fcp = <&fcpvd <<
1962 }; <<
1963 <<
1964 fcpvd1: fcp@fea2f000 { <<
1965 compatible = "renesas <<
1966 reg = <0 0xfea2f000 0 <<
1967 clocks = <&cpg CPG_MO <<
1968 power-domains = <&sys <<
1969 resets = <&cpg 602>; <<
1970 iommus = <&ipmmu_vi0 <<
1971 }; <<
1972 <<
1973 cmm0: cmm@fea40000 { <<
1974 compatible = "renesas <<
1975 "renesas <<
1976 reg = <0 0xfea40000 0 <<
1977 power-domains = <&sys <<
1978 clocks = <&cpg CPG_MO <<
1979 resets = <&cpg 711>; <<
1980 }; <<
1981 <<
1982 cmm1: cmm@fea50000 { <<
1983 compatible = "renesas <<
1984 "renesas <<
1985 reg = <0 0xfea50000 0 <<
1986 power-domains = <&sys <<
1987 clocks = <&cpg CPG_MO <<
1988 resets = <&cpg 710>; <<
1989 }; <<
1990 <<
1991 csi40: csi2@feaa0000 { <<
1992 compatible = "renesas <<
1993 reg = <0 0xfeaa0000 0 <<
1994 interrupts = <GIC_SPI <<
1995 clocks = <&cpg CPG_MO <<
1996 power-domains = <&sys <<
1997 resets = <&cpg 716>; <<
1998 status = "disabled"; <<
1999 <<
2000 ports { <<
2001 #address-cell <<
2002 #size-cells = <<
2003 <<
2004 port@0 { <<
2005 reg = <<
2006 }; <<
2007 <<
2008 port@1 { <<
2009 #addr <<
2010 #size <<
2011 <<
2012 reg = <<
2013 <<
2014 csi40 <<
2015 <<
2016 <<
2017 }; <<
2018 csi40 <<
2019 <<
2020 <<
2021 }; <<
2022 }; <<
2023 }; <<
2024 }; <<
2025 <<
2026 du: display@feb00000 { <<
2027 compatible = "renesas <<
2028 reg = <0 0xfeb00000 0 <<
2029 interrupts = <GIC_SPI <<
2030 <GIC_SPI <<
2031 clocks = <&cpg CPG_MO <<
2032 clock-names = "du.0", <<
2033 resets = <&cpg 724>; <<
2034 reset-names = "du.0"; <<
2035 <<
2036 renesas,cmms = <&cmm0 <<
2037 renesas,vsps = <&vspd <<
2038 <<
2039 status = "disabled"; <<
2040 <<
2041 ports { <<
2042 #address-cell <<
2043 #size-cells = <<
2044 <<
2045 port@0 { <<
2046 reg = <<
2047 }; <<
2048 <<
2049 port@1 { <<
2050 reg = <<
2051 du_ou <<
2052 <<
2053 }; <<
2054 }; <<
2055 <<
2056 port@2 { <<
2057 reg = <<
2058 du_ou <<
2059 <<
2060 }; <<
2061 }; <<
2062 }; <<
2063 }; <<
2064 <<
2065 lvds0: lvds-encoder@feb90000 <<
2066 compatible = "renesas <<
2067 reg = <0 0xfeb90000 0 <<
2068 clocks = <&cpg CPG_MO <<
2069 power-domains = <&sys <<
2070 resets = <&cpg 727>; <<
2071 status = "disabled"; <<
2072 <<
2073 renesas,companion = < <<
2074 <<
2075 ports { <<
2076 #address-cell <<
2077 #size-cells = <<
2078 <<
2079 port@0 { <<
2080 reg = <<
2081 lvds0 <<
2082 <<
2083 }; <<
2084 }; <<
2085 <<
2086 port@1 { <<
2087 reg = <<
2088 }; <<
2089 }; <<
2090 }; <<
2091 <<
2092 lvds1: lvds-encoder@feb90100 <<
2093 compatible = "renesas <<
2094 reg = <0 0xfeb90100 0 <<
2095 clocks = <&cpg CPG_MO <<
2096 power-domains = <&sys <<
2097 resets = <&cpg 726>; <<
2098 status = "disabled"; <<
2099 <<
2100 ports { <<
2101 #address-cell <<
2102 #size-cells = <<
2103 <<
2104 port@0 { <<
2105 reg = <<
2106 lvds1 <<
2107 <<
2108 }; <<
2109 }; <<
2110 <<
2111 port@1 { <<
2112 reg = <<
2113 }; <<
2114 }; <<
2115 }; <<
2116 <<
2117 prr: chipid@fff00044 { 417 prr: chipid@fff00044 {
2118 compatible = "renesas 418 compatible = "renesas,prr";
2119 reg = <0 0xfff00044 0 419 reg = <0 0xfff00044 0 4>;
2120 }; 420 };
2121 }; 421 };
2122 422
2123 thermal-zones { <<
2124 cpu-thermal { <<
2125 polling-delay-passive <<
2126 polling-delay = <0>; <<
2127 thermal-sensors = <&t <<
2128 sustainable-power = < <<
2129 <<
2130 cooling-maps { <<
2131 map0 { <<
2132 trip <<
2133 cooli <<
2134 contr <<
2135 }; <<
2136 }; <<
2137 <<
2138 trips { <<
2139 sensor1_crit: <<
2140 tempe <<
2141 hyste <<
2142 type <<
2143 }; <<
2144 <<
2145 target: trip- <<
2146 tempe <<
2147 hyste <<
2148 type <<
2149 }; <<
2150 }; <<
2151 }; <<
2152 }; <<
2153 <<
2154 timer { 423 timer {
2155 compatible = "arm,armv8-timer 424 compatible = "arm,armv8-timer";
2156 interrupts-extended = <&gic G 425 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
2157 <&gic G 426 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
2158 <&gic G 427 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
2159 <&gic G 428 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
2160 interrupt-names = "sec-phys", <<
2161 }; 429 };
2162 }; 430 };
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