1 // SPDX-License-Identifier: GPL-2.0 !! 1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* 2 /*
3 * Device Tree Source for the R-Car E3 (R8A779 3 * Device Tree Source for the R-Car E3 (R8A77990) SoC
4 * 4 *
5 * Copyright (C) 2018-2019 Renesas Electronics 5 * Copyright (C) 2018-2019 Renesas Electronics Corp.
6 */ 6 */
7 7
8 #include <dt-bindings/clock/r8a77990-cpg-mssr. 8 #include <dt-bindings/clock/r8a77990-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm 9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a77990-sysc.h> 10 #include <dt-bindings/power/r8a77990-sysc.h>
11 11
12 / { 12 / {
13 compatible = "renesas,r8a77990"; 13 compatible = "renesas,r8a77990";
14 #address-cells = <2>; 14 #address-cells = <2>;
15 #size-cells = <2>; 15 #size-cells = <2>;
16 16
>> 17 aliases {
>> 18 i2c0 = &i2c0;
>> 19 i2c1 = &i2c1;
>> 20 i2c2 = &i2c2;
>> 21 i2c3 = &i2c3;
>> 22 i2c4 = &i2c4;
>> 23 i2c5 = &i2c5;
>> 24 i2c6 = &i2c6;
>> 25 i2c7 = &i2c7;
>> 26 };
>> 27
17 /* 28 /*
18 * The external audio clocks are confi 29 * The external audio clocks are configured as 0 Hz fixed frequency
19 * clocks by default. 30 * clocks by default.
20 * Boards that provide audio clocks sh 31 * Boards that provide audio clocks should override them.
21 */ 32 */
22 audio_clk_a: audio_clk_a { 33 audio_clk_a: audio_clk_a {
23 compatible = "fixed-clock"; 34 compatible = "fixed-clock";
24 #clock-cells = <0>; 35 #clock-cells = <0>;
25 clock-frequency = <0>; 36 clock-frequency = <0>;
26 }; 37 };
27 38
28 audio_clk_b: audio_clk_b { 39 audio_clk_b: audio_clk_b {
29 compatible = "fixed-clock"; 40 compatible = "fixed-clock";
30 #clock-cells = <0>; 41 #clock-cells = <0>;
31 clock-frequency = <0>; 42 clock-frequency = <0>;
32 }; 43 };
33 44
34 audio_clk_c: audio_clk_c { 45 audio_clk_c: audio_clk_c {
35 compatible = "fixed-clock"; 46 compatible = "fixed-clock";
36 #clock-cells = <0>; 47 #clock-cells = <0>;
37 clock-frequency = <0>; 48 clock-frequency = <0>;
38 }; 49 };
39 50
40 /* External CAN clock - to be overridd 51 /* External CAN clock - to be overridden by boards that provide it */
41 can_clk: can { 52 can_clk: can {
42 compatible = "fixed-clock"; 53 compatible = "fixed-clock";
43 #clock-cells = <0>; 54 #clock-cells = <0>;
44 clock-frequency = <0>; 55 clock-frequency = <0>;
45 }; 56 };
46 57
47 cluster1_opp: opp-table-1 { <<
48 compatible = "operating-points <<
49 opp-shared; <<
50 opp-800000000 { <<
51 opp-hz = /bits/ 64 <80 <<
52 clock-latency-ns = <30 <<
53 }; <<
54 opp-1000000000 { <<
55 opp-hz = /bits/ 64 <10 <<
56 clock-latency-ns = <30 <<
57 }; <<
58 opp-1200000000 { <<
59 opp-hz = /bits/ 64 <12 <<
60 clock-latency-ns = <30 <<
61 opp-suspend; <<
62 }; <<
63 }; <<
64 <<
65 cpus { 58 cpus {
66 #address-cells = <1>; 59 #address-cells = <1>;
67 #size-cells = <0>; 60 #size-cells = <0>;
68 61
69 a53_0: cpu@0 { 62 a53_0: cpu@0 {
70 compatible = "arm,cort !! 63 compatible = "arm,cortex-a53", "arm,armv8";
71 reg = <0>; 64 reg = <0>;
72 device_type = "cpu"; 65 device_type = "cpu";
73 #cooling-cells = <2>; <<
74 power-domains = <&sysc 66 power-domains = <&sysc R8A77990_PD_CA53_CPU0>;
75 next-level-cache = <&L 67 next-level-cache = <&L2_CA53>;
76 enable-method = "psci" 68 enable-method = "psci";
77 cpu-idle-states = <&CP <<
78 dynamic-power-coeffici <<
79 clocks = <&cpg CPG_COR <<
80 operating-points-v2 = <<
81 }; 69 };
82 70
83 a53_1: cpu@1 { 71 a53_1: cpu@1 {
84 compatible = "arm,cort !! 72 compatible = "arm,cortex-a53", "arm,armv8";
85 reg = <1>; 73 reg = <1>;
86 device_type = "cpu"; 74 device_type = "cpu";
87 power-domains = <&sysc 75 power-domains = <&sysc R8A77990_PD_CA53_CPU1>;
88 next-level-cache = <&L 76 next-level-cache = <&L2_CA53>;
89 enable-method = "psci" 77 enable-method = "psci";
90 cpu-idle-states = <&CP <<
91 clocks = <&cpg CPG_COR <<
92 operating-points-v2 = <<
93 }; 78 };
94 79
95 L2_CA53: cache-controller-0 { 80 L2_CA53: cache-controller-0 {
96 compatible = "cache"; 81 compatible = "cache";
97 power-domains = <&sysc 82 power-domains = <&sysc R8A77990_PD_CA53_SCU>;
98 cache-unified; 83 cache-unified;
99 cache-level = <2>; 84 cache-level = <2>;
100 }; 85 };
101 <<
102 idle-states { <<
103 entry-method = "psci"; <<
104 <<
105 CPU_SLEEP_0: cpu-sleep <<
106 compatible = " <<
107 arm,psci-suspe <<
108 local-timer-st <<
109 entry-latency- <<
110 exit-latency-u <<
111 min-residency- <<
112 }; <<
113 }; <<
114 }; 86 };
115 87
116 extal_clk: extal { 88 extal_clk: extal {
117 compatible = "fixed-clock"; 89 compatible = "fixed-clock";
118 #clock-cells = <0>; 90 #clock-cells = <0>;
119 /* This value must be overridd 91 /* This value must be overridden by the board */
120 clock-frequency = <0>; 92 clock-frequency = <0>;
121 }; 93 };
122 94
123 /* External PCIe clock - can be overri 95 /* External PCIe clock - can be overridden by the board */
124 pcie_bus_clk: pcie_bus { 96 pcie_bus_clk: pcie_bus {
125 compatible = "fixed-clock"; 97 compatible = "fixed-clock";
126 #clock-cells = <0>; 98 #clock-cells = <0>;
127 clock-frequency = <0>; 99 clock-frequency = <0>;
128 }; 100 };
129 101
130 pmu_a53 { 102 pmu_a53 {
131 compatible = "arm,cortex-a53-p 103 compatible = "arm,cortex-a53-pmu";
132 interrupts-extended = <&gic GI 104 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
133 <&gic GI 105 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
134 interrupt-affinity = <&a53_0>, 106 interrupt-affinity = <&a53_0>, <&a53_1>;
135 }; 107 };
136 108
137 psci { 109 psci {
138 compatible = "arm,psci-1.0", " 110 compatible = "arm,psci-1.0", "arm,psci-0.2";
139 method = "smc"; 111 method = "smc";
140 }; 112 };
141 113
142 /* External SCIF clock - to be overrid 114 /* External SCIF clock - to be overridden by boards that provide it */
143 scif_clk: scif { 115 scif_clk: scif {
144 compatible = "fixed-clock"; 116 compatible = "fixed-clock";
145 #clock-cells = <0>; 117 #clock-cells = <0>;
146 clock-frequency = <0>; 118 clock-frequency = <0>;
147 }; 119 };
148 120
149 soc: soc { 121 soc: soc {
150 compatible = "simple-bus"; 122 compatible = "simple-bus";
151 interrupt-parent = <&gic>; 123 interrupt-parent = <&gic>;
152 #address-cells = <2>; 124 #address-cells = <2>;
153 #size-cells = <2>; 125 #size-cells = <2>;
154 ranges; 126 ranges;
155 127
156 rwdt: watchdog@e6020000 { 128 rwdt: watchdog@e6020000 {
157 compatible = "renesas, 129 compatible = "renesas,r8a77990-wdt",
158 "renesas, 130 "renesas,rcar-gen3-wdt";
159 reg = <0 0xe6020000 0 131 reg = <0 0xe6020000 0 0x0c>;
160 interrupts = <GIC_SPI <<
161 clocks = <&cpg CPG_MOD 132 clocks = <&cpg CPG_MOD 402>;
162 power-domains = <&sysc 133 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
163 resets = <&cpg 402>; 134 resets = <&cpg 402>;
164 status = "disabled"; 135 status = "disabled";
165 }; 136 };
166 137
167 gpio0: gpio@e6050000 { 138 gpio0: gpio@e6050000 {
168 compatible = "renesas, 139 compatible = "renesas,gpio-r8a77990",
169 "renesas, 140 "renesas,rcar-gen3-gpio";
170 reg = <0 0xe6050000 0 141 reg = <0 0xe6050000 0 0x50>;
171 interrupts = <GIC_SPI 142 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
172 #gpio-cells = <2>; 143 #gpio-cells = <2>;
173 gpio-controller; 144 gpio-controller;
174 gpio-ranges = <&pfc 0 145 gpio-ranges = <&pfc 0 0 18>;
175 #interrupt-cells = <2> 146 #interrupt-cells = <2>;
176 interrupt-controller; 147 interrupt-controller;
177 clocks = <&cpg CPG_MOD 148 clocks = <&cpg CPG_MOD 912>;
178 power-domains = <&sysc 149 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
179 resets = <&cpg 912>; 150 resets = <&cpg 912>;
180 }; 151 };
181 152
182 gpio1: gpio@e6051000 { 153 gpio1: gpio@e6051000 {
183 compatible = "renesas, 154 compatible = "renesas,gpio-r8a77990",
184 "renesas, 155 "renesas,rcar-gen3-gpio";
185 reg = <0 0xe6051000 0 156 reg = <0 0xe6051000 0 0x50>;
186 interrupts = <GIC_SPI 157 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
187 #gpio-cells = <2>; 158 #gpio-cells = <2>;
188 gpio-controller; 159 gpio-controller;
189 gpio-ranges = <&pfc 0 160 gpio-ranges = <&pfc 0 32 23>;
190 #interrupt-cells = <2> 161 #interrupt-cells = <2>;
191 interrupt-controller; 162 interrupt-controller;
192 clocks = <&cpg CPG_MOD 163 clocks = <&cpg CPG_MOD 911>;
193 power-domains = <&sysc 164 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
194 resets = <&cpg 911>; 165 resets = <&cpg 911>;
195 }; 166 };
196 167
197 gpio2: gpio@e6052000 { 168 gpio2: gpio@e6052000 {
198 compatible = "renesas, 169 compatible = "renesas,gpio-r8a77990",
199 "renesas, 170 "renesas,rcar-gen3-gpio";
200 reg = <0 0xe6052000 0 171 reg = <0 0xe6052000 0 0x50>;
201 interrupts = <GIC_SPI 172 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
202 #gpio-cells = <2>; 173 #gpio-cells = <2>;
203 gpio-controller; 174 gpio-controller;
204 gpio-ranges = <&pfc 0 175 gpio-ranges = <&pfc 0 64 26>;
205 #interrupt-cells = <2> 176 #interrupt-cells = <2>;
206 interrupt-controller; 177 interrupt-controller;
207 clocks = <&cpg CPG_MOD 178 clocks = <&cpg CPG_MOD 910>;
208 power-domains = <&sysc 179 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
209 resets = <&cpg 910>; 180 resets = <&cpg 910>;
210 }; 181 };
211 182
212 gpio3: gpio@e6053000 { 183 gpio3: gpio@e6053000 {
213 compatible = "renesas, 184 compatible = "renesas,gpio-r8a77990",
214 "renesas, 185 "renesas,rcar-gen3-gpio";
215 reg = <0 0xe6053000 0 186 reg = <0 0xe6053000 0 0x50>;
216 interrupts = <GIC_SPI 187 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
217 #gpio-cells = <2>; 188 #gpio-cells = <2>;
218 gpio-controller; 189 gpio-controller;
219 gpio-ranges = <&pfc 0 190 gpio-ranges = <&pfc 0 96 16>;
220 #interrupt-cells = <2> 191 #interrupt-cells = <2>;
221 interrupt-controller; 192 interrupt-controller;
222 clocks = <&cpg CPG_MOD 193 clocks = <&cpg CPG_MOD 909>;
223 power-domains = <&sysc 194 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
224 resets = <&cpg 909>; 195 resets = <&cpg 909>;
225 }; 196 };
226 197
227 gpio4: gpio@e6054000 { 198 gpio4: gpio@e6054000 {
228 compatible = "renesas, 199 compatible = "renesas,gpio-r8a77990",
229 "renesas, 200 "renesas,rcar-gen3-gpio";
230 reg = <0 0xe6054000 0 201 reg = <0 0xe6054000 0 0x50>;
231 interrupts = <GIC_SPI 202 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
232 #gpio-cells = <2>; 203 #gpio-cells = <2>;
233 gpio-controller; 204 gpio-controller;
234 gpio-ranges = <&pfc 0 205 gpio-ranges = <&pfc 0 128 11>;
235 #interrupt-cells = <2> 206 #interrupt-cells = <2>;
236 interrupt-controller; 207 interrupt-controller;
237 clocks = <&cpg CPG_MOD 208 clocks = <&cpg CPG_MOD 908>;
238 power-domains = <&sysc 209 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
239 resets = <&cpg 908>; 210 resets = <&cpg 908>;
240 }; 211 };
241 212
242 gpio5: gpio@e6055000 { 213 gpio5: gpio@e6055000 {
243 compatible = "renesas, 214 compatible = "renesas,gpio-r8a77990",
244 "renesas, 215 "renesas,rcar-gen3-gpio";
245 reg = <0 0xe6055000 0 216 reg = <0 0xe6055000 0 0x50>;
246 interrupts = <GIC_SPI 217 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
247 #gpio-cells = <2>; 218 #gpio-cells = <2>;
248 gpio-controller; 219 gpio-controller;
249 gpio-ranges = <&pfc 0 220 gpio-ranges = <&pfc 0 160 20>;
250 #interrupt-cells = <2> 221 #interrupt-cells = <2>;
251 interrupt-controller; 222 interrupt-controller;
252 clocks = <&cpg CPG_MOD 223 clocks = <&cpg CPG_MOD 907>;
253 power-domains = <&sysc 224 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
254 resets = <&cpg 907>; 225 resets = <&cpg 907>;
255 }; 226 };
256 227
257 gpio6: gpio@e6055400 { 228 gpio6: gpio@e6055400 {
258 compatible = "renesas, 229 compatible = "renesas,gpio-r8a77990",
259 "renesas, 230 "renesas,rcar-gen3-gpio";
260 reg = <0 0xe6055400 0 231 reg = <0 0xe6055400 0 0x50>;
261 interrupts = <GIC_SPI 232 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
262 #gpio-cells = <2>; 233 #gpio-cells = <2>;
263 gpio-controller; 234 gpio-controller;
264 gpio-ranges = <&pfc 0 235 gpio-ranges = <&pfc 0 192 18>;
265 #interrupt-cells = <2> 236 #interrupt-cells = <2>;
266 interrupt-controller; 237 interrupt-controller;
267 clocks = <&cpg CPG_MOD 238 clocks = <&cpg CPG_MOD 906>;
268 power-domains = <&sysc 239 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
269 resets = <&cpg 906>; 240 resets = <&cpg 906>;
270 }; 241 };
271 242
272 pfc: pinctrl@e6060000 { <<
273 compatible = "renesas, <<
274 reg = <0 0xe6060000 0 <<
275 }; <<
276 <<
277 i2c_dvfs: i2c@e60b0000 { <<
278 #address-cells = <1>; <<
279 #size-cells = <0>; <<
280 compatible = "renesas, <<
281 "renesas, <<
282 "renesas, <<
283 reg = <0 0xe60b0000 0 <<
284 interrupts = <GIC_SPI <<
285 clocks = <&cpg CPG_MOD <<
286 power-domains = <&sysc <<
287 resets = <&cpg 926>; <<
288 dmas = <&dmac0 0x11>, <<
289 dma-names = "tx", "rx" <<
290 status = "disabled"; <<
291 }; <<
292 <<
293 cmt0: timer@e60f0000 { <<
294 compatible = "renesas, <<
295 "renesas, <<
296 reg = <0 0xe60f0000 0 <<
297 interrupts = <GIC_SPI <<
298 <GIC_SPI <<
299 clocks = <&cpg CPG_MOD <<
300 clock-names = "fck"; <<
301 power-domains = <&sysc <<
302 resets = <&cpg 303>; <<
303 status = "disabled"; <<
304 }; <<
305 <<
306 cmt1: timer@e6130000 { <<
307 compatible = "renesas, <<
308 "renesas, <<
309 reg = <0 0xe6130000 0 <<
310 interrupts = <GIC_SPI <<
311 <GIC_SPI <<
312 <GIC_SPI <<
313 <GIC_SPI <<
314 <GIC_SPI <<
315 <GIC_SPI <<
316 <GIC_SPI <<
317 <GIC_SPI <<
318 clocks = <&cpg CPG_MOD <<
319 clock-names = "fck"; <<
320 power-domains = <&sysc <<
321 resets = <&cpg 302>; <<
322 status = "disabled"; <<
323 }; <<
324 <<
325 cmt2: timer@e6140000 { <<
326 compatible = "renesas, <<
327 "renesas, <<
328 reg = <0 0xe6140000 0 <<
329 interrupts = <GIC_SPI <<
330 <GIC_SPI <<
331 <GIC_SPI <<
332 <GIC_SPI <<
333 <GIC_SPI <<
334 <GIC_SPI <<
335 <GIC_SPI <<
336 <GIC_SPI <<
337 clocks = <&cpg CPG_MOD <<
338 clock-names = "fck"; <<
339 power-domains = <&sysc <<
340 resets = <&cpg 301>; <<
341 status = "disabled"; <<
342 }; <<
343 <<
344 cmt3: timer@e6148000 { <<
345 compatible = "renesas, <<
346 "renesas, <<
347 reg = <0 0xe6148000 0 <<
348 interrupts = <GIC_SPI <<
349 <GIC_SPI <<
350 <GIC_SPI <<
351 <GIC_SPI <<
352 <GIC_SPI <<
353 <GIC_SPI <<
354 <GIC_SPI <<
355 <GIC_SPI <<
356 clocks = <&cpg CPG_MOD <<
357 clock-names = "fck"; <<
358 power-domains = <&sysc <<
359 resets = <&cpg 300>; <<
360 status = "disabled"; <<
361 }; <<
362 <<
363 cpg: clock-controller@e6150000 <<
364 compatible = "renesas, <<
365 reg = <0 0xe6150000 0 <<
366 clocks = <&extal_clk>; <<
367 clock-names = "extal"; <<
368 #clock-cells = <2>; <<
369 #power-domain-cells = <<
370 #reset-cells = <1>; <<
371 }; <<
372 <<
373 rst: reset-controller@e6160000 <<
374 compatible = "renesas, <<
375 reg = <0 0xe6160000 0 <<
376 }; <<
377 <<
378 sysc: system-controller@e61800 <<
379 compatible = "renesas, <<
380 reg = <0 0xe6180000 0 <<
381 #power-domain-cells = <<
382 }; <<
383 <<
384 thermal: thermal@e6190000 { <<
385 compatible = "renesas, <<
386 reg = <0 0xe6190000 0 <<
387 interrupts = <GIC_SPI <<
388 <GIC_SPI <<
389 <GIC_SPI <<
390 clocks = <&cpg CPG_MOD <<
391 power-domains = <&sysc <<
392 resets = <&cpg 522>; <<
393 #thermal-sensor-cells <<
394 }; <<
395 <<
396 intc_ex: interrupt-controller@ <<
397 compatible = "renesas, <<
398 #interrupt-cells = <2> <<
399 interrupt-controller; <<
400 reg = <0 0xe61c0000 0 <<
401 interrupts = <GIC_SPI <<
402 <GIC_SPI <<
403 <GIC_SPI <<
404 <GIC_SPI <<
405 <GIC_SPI <<
406 <GIC_SPI <<
407 clocks = <&cpg CPG_MOD <<
408 power-domains = <&sysc <<
409 resets = <&cpg 407>; <<
410 }; <<
411 <<
412 tmu0: timer@e61e0000 { <<
413 compatible = "renesas, <<
414 reg = <0 0xe61e0000 0 <<
415 interrupts = <GIC_SPI <<
416 <GIC_SPI <<
417 <GIC_SPI <<
418 interrupt-names = "tun <<
419 clocks = <&cpg CPG_MOD <<
420 clock-names = "fck"; <<
421 power-domains = <&sysc <<
422 resets = <&cpg 125>; <<
423 status = "disabled"; <<
424 }; <<
425 <<
426 tmu1: timer@e6fc0000 { <<
427 compatible = "renesas, <<
428 reg = <0 0xe6fc0000 0 <<
429 interrupts = <GIC_SPI <<
430 <GIC_SPI <<
431 <GIC_SPI <<
432 <GIC_SPI <<
433 interrupt-names = "tun <<
434 clocks = <&cpg CPG_MOD <<
435 clock-names = "fck"; <<
436 power-domains = <&sysc <<
437 resets = <&cpg 124>; <<
438 status = "disabled"; <<
439 }; <<
440 <<
441 tmu2: timer@e6fd0000 { <<
442 compatible = "renesas, <<
443 reg = <0 0xe6fd0000 0 <<
444 interrupts = <GIC_SPI <<
445 <GIC_SPI <<
446 <GIC_SPI <<
447 <GIC_SPI <<
448 interrupt-names = "tun <<
449 clocks = <&cpg CPG_MOD <<
450 clock-names = "fck"; <<
451 power-domains = <&sysc <<
452 resets = <&cpg 123>; <<
453 status = "disabled"; <<
454 }; <<
455 <<
456 tmu3: timer@e6fe0000 { <<
457 compatible = "renesas, <<
458 reg = <0 0xe6fe0000 0 <<
459 interrupts = <GIC_SPI <<
460 <GIC_SPI <<
461 <GIC_SPI <<
462 interrupt-names = "tun <<
463 clocks = <&cpg CPG_MOD <<
464 clock-names = "fck"; <<
465 power-domains = <&sysc <<
466 resets = <&cpg 122>; <<
467 status = "disabled"; <<
468 }; <<
469 <<
470 tmu4: timer@ffc00000 { <<
471 compatible = "renesas, <<
472 reg = <0 0xffc00000 0 <<
473 interrupts = <GIC_SPI <<
474 <GIC_SPI <<
475 <GIC_SPI <<
476 interrupt-names = "tun <<
477 clocks = <&cpg CPG_MOD <<
478 clock-names = "fck"; <<
479 power-domains = <&sysc <<
480 resets = <&cpg 121>; <<
481 status = "disabled"; <<
482 }; <<
483 <<
484 i2c0: i2c@e6500000 { 243 i2c0: i2c@e6500000 {
485 #address-cells = <1>; 244 #address-cells = <1>;
486 #size-cells = <0>; 245 #size-cells = <0>;
487 compatible = "renesas, 246 compatible = "renesas,i2c-r8a77990",
488 "renesas, 247 "renesas,rcar-gen3-i2c";
489 reg = <0 0xe6500000 0 248 reg = <0 0xe6500000 0 0x40>;
490 interrupts = <GIC_SPI 249 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
491 clocks = <&cpg CPG_MOD 250 clocks = <&cpg CPG_MOD 931>;
492 power-domains = <&sysc 251 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
493 resets = <&cpg 931>; 252 resets = <&cpg 931>;
494 dmas = <&dmac1 0x91>, 253 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
495 <&dmac2 0x91>, 254 <&dmac2 0x91>, <&dmac2 0x90>;
496 dma-names = "tx", "rx" 255 dma-names = "tx", "rx", "tx", "rx";
497 i2c-scl-internal-delay 256 i2c-scl-internal-delay-ns = <110>;
498 status = "disabled"; 257 status = "disabled";
499 }; 258 };
500 259
501 i2c1: i2c@e6508000 { 260 i2c1: i2c@e6508000 {
502 #address-cells = <1>; 261 #address-cells = <1>;
503 #size-cells = <0>; 262 #size-cells = <0>;
504 compatible = "renesas, 263 compatible = "renesas,i2c-r8a77990",
505 "renesas, 264 "renesas,rcar-gen3-i2c";
506 reg = <0 0xe6508000 0 265 reg = <0 0xe6508000 0 0x40>;
507 interrupts = <GIC_SPI 266 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
508 clocks = <&cpg CPG_MOD 267 clocks = <&cpg CPG_MOD 930>;
509 power-domains = <&sysc 268 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
510 resets = <&cpg 930>; 269 resets = <&cpg 930>;
511 dmas = <&dmac1 0x93>, 270 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
512 <&dmac2 0x93>, 271 <&dmac2 0x93>, <&dmac2 0x92>;
513 dma-names = "tx", "rx" 272 dma-names = "tx", "rx", "tx", "rx";
514 i2c-scl-internal-delay 273 i2c-scl-internal-delay-ns = <6>;
515 status = "disabled"; 274 status = "disabled";
516 }; 275 };
517 276
518 i2c2: i2c@e6510000 { 277 i2c2: i2c@e6510000 {
519 #address-cells = <1>; 278 #address-cells = <1>;
520 #size-cells = <0>; 279 #size-cells = <0>;
521 compatible = "renesas, 280 compatible = "renesas,i2c-r8a77990",
522 "renesas, 281 "renesas,rcar-gen3-i2c";
523 reg = <0 0xe6510000 0 282 reg = <0 0xe6510000 0 0x40>;
524 interrupts = <GIC_SPI 283 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
525 clocks = <&cpg CPG_MOD 284 clocks = <&cpg CPG_MOD 929>;
526 power-domains = <&sysc 285 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
527 resets = <&cpg 929>; 286 resets = <&cpg 929>;
528 dmas = <&dmac1 0x95>, 287 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
529 <&dmac2 0x95>, 288 <&dmac2 0x95>, <&dmac2 0x94>;
530 dma-names = "tx", "rx" 289 dma-names = "tx", "rx", "tx", "rx";
531 i2c-scl-internal-delay 290 i2c-scl-internal-delay-ns = <6>;
532 status = "disabled"; 291 status = "disabled";
533 }; 292 };
534 293
535 i2c3: i2c@e66d0000 { 294 i2c3: i2c@e66d0000 {
536 #address-cells = <1>; 295 #address-cells = <1>;
537 #size-cells = <0>; 296 #size-cells = <0>;
538 compatible = "renesas, 297 compatible = "renesas,i2c-r8a77990",
539 "renesas, 298 "renesas,rcar-gen3-i2c";
540 reg = <0 0xe66d0000 0 299 reg = <0 0xe66d0000 0 0x40>;
541 interrupts = <GIC_SPI 300 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
542 clocks = <&cpg CPG_MOD 301 clocks = <&cpg CPG_MOD 928>;
543 power-domains = <&sysc 302 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
544 resets = <&cpg 928>; 303 resets = <&cpg 928>;
545 dmas = <&dmac0 0x97>, 304 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
546 dma-names = "tx", "rx" 305 dma-names = "tx", "rx";
547 i2c-scl-internal-delay 306 i2c-scl-internal-delay-ns = <110>;
548 status = "disabled"; 307 status = "disabled";
549 }; 308 };
550 309
551 i2c4: i2c@e66d8000 { 310 i2c4: i2c@e66d8000 {
552 #address-cells = <1>; 311 #address-cells = <1>;
553 #size-cells = <0>; 312 #size-cells = <0>;
554 compatible = "renesas, 313 compatible = "renesas,i2c-r8a77990",
555 "renesas, 314 "renesas,rcar-gen3-i2c";
556 reg = <0 0xe66d8000 0 315 reg = <0 0xe66d8000 0 0x40>;
557 interrupts = <GIC_SPI 316 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
558 clocks = <&cpg CPG_MOD 317 clocks = <&cpg CPG_MOD 927>;
559 power-domains = <&sysc 318 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
560 resets = <&cpg 927>; 319 resets = <&cpg 927>;
561 dmas = <&dmac0 0x99>, 320 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
562 dma-names = "tx", "rx" 321 dma-names = "tx", "rx";
563 i2c-scl-internal-delay 322 i2c-scl-internal-delay-ns = <6>;
564 status = "disabled"; 323 status = "disabled";
565 }; 324 };
566 325
567 i2c5: i2c@e66e0000 { 326 i2c5: i2c@e66e0000 {
568 #address-cells = <1>; 327 #address-cells = <1>;
569 #size-cells = <0>; 328 #size-cells = <0>;
570 compatible = "renesas, 329 compatible = "renesas,i2c-r8a77990",
571 "renesas, 330 "renesas,rcar-gen3-i2c";
572 reg = <0 0xe66e0000 0 331 reg = <0 0xe66e0000 0 0x40>;
573 interrupts = <GIC_SPI 332 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
574 clocks = <&cpg CPG_MOD 333 clocks = <&cpg CPG_MOD 919>;
575 power-domains = <&sysc 334 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
576 resets = <&cpg 919>; 335 resets = <&cpg 919>;
577 dmas = <&dmac0 0x9b>, 336 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
578 dma-names = "tx", "rx" 337 dma-names = "tx", "rx";
579 i2c-scl-internal-delay 338 i2c-scl-internal-delay-ns = <6>;
580 status = "disabled"; 339 status = "disabled";
581 }; 340 };
582 341
583 i2c6: i2c@e66e8000 { 342 i2c6: i2c@e66e8000 {
584 #address-cells = <1>; 343 #address-cells = <1>;
585 #size-cells = <0>; 344 #size-cells = <0>;
586 compatible = "renesas, 345 compatible = "renesas,i2c-r8a77990",
587 "renesas, 346 "renesas,rcar-gen3-i2c";
588 reg = <0 0xe66e8000 0 347 reg = <0 0xe66e8000 0 0x40>;
589 interrupts = <GIC_SPI 348 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
590 clocks = <&cpg CPG_MOD 349 clocks = <&cpg CPG_MOD 918>;
591 power-domains = <&sysc 350 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
592 resets = <&cpg 918>; 351 resets = <&cpg 918>;
593 dmas = <&dmac0 0x9d>, 352 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
594 dma-names = "tx", "rx" 353 dma-names = "tx", "rx";
595 i2c-scl-internal-delay 354 i2c-scl-internal-delay-ns = <6>;
596 status = "disabled"; 355 status = "disabled";
597 }; 356 };
598 357
599 i2c7: i2c@e6690000 { 358 i2c7: i2c@e6690000 {
600 #address-cells = <1>; 359 #address-cells = <1>;
601 #size-cells = <0>; 360 #size-cells = <0>;
602 compatible = "renesas, 361 compatible = "renesas,i2c-r8a77990",
603 "renesas, 362 "renesas,rcar-gen3-i2c";
604 reg = <0 0xe6690000 0 363 reg = <0 0xe6690000 0 0x40>;
605 interrupts = <GIC_SPI 364 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
606 clocks = <&cpg CPG_MOD 365 clocks = <&cpg CPG_MOD 1003>;
607 power-domains = <&sysc 366 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
608 resets = <&cpg 1003>; 367 resets = <&cpg 1003>;
609 i2c-scl-internal-delay 368 i2c-scl-internal-delay-ns = <6>;
610 status = "disabled"; 369 status = "disabled";
611 }; 370 };
612 371
>> 372 pfc: pin-controller@e6060000 {
>> 373 compatible = "renesas,pfc-r8a77990";
>> 374 reg = <0 0xe6060000 0 0x508>;
>> 375 };
>> 376
>> 377 i2c_dvfs: i2c@e60b0000 {
>> 378 #address-cells = <1>;
>> 379 #size-cells = <0>;
>> 380 compatible = "renesas,iic-r8a77990";
>> 381 reg = <0 0xe60b0000 0 0x15>;
>> 382 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
>> 383 clocks = <&cpg CPG_MOD 926>;
>> 384 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
>> 385 resets = <&cpg 926>;
>> 386 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
>> 387 dma-names = "tx", "rx";
>> 388 status = "disabled";
>> 389 };
>> 390
>> 391 cpg: clock-controller@e6150000 {
>> 392 compatible = "renesas,r8a77990-cpg-mssr";
>> 393 reg = <0 0xe6150000 0 0x1000>;
>> 394 clocks = <&extal_clk>;
>> 395 clock-names = "extal";
>> 396 #clock-cells = <2>;
>> 397 #power-domain-cells = <0>;
>> 398 #reset-cells = <1>;
>> 399 };
>> 400
>> 401 rst: reset-controller@e6160000 {
>> 402 compatible = "renesas,r8a77990-rst";
>> 403 reg = <0 0xe6160000 0 0x0200>;
>> 404 };
>> 405
>> 406 sysc: system-controller@e6180000 {
>> 407 compatible = "renesas,r8a77990-sysc";
>> 408 reg = <0 0xe6180000 0 0x0400>;
>> 409 #power-domain-cells = <1>;
>> 410 };
>> 411
>> 412 thermal: thermal@e6190000 {
>> 413 compatible = "renesas,thermal-r8a77990";
>> 414 reg = <0 0xe6190000 0 0x10>, <0 0xe6190100 0 0x38>;
>> 415 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
>> 416 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
>> 417 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
>> 418 clocks = <&cpg CPG_MOD 522>;
>> 419 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
>> 420 resets = <&cpg 522>;
>> 421 #thermal-sensor-cells = <0>;
>> 422 };
>> 423
>> 424 intc_ex: interrupt-controller@e61c0000 {
>> 425 compatible = "renesas,intc-ex-r8a77990", "renesas,irqc";
>> 426 #interrupt-cells = <2>;
>> 427 interrupt-controller;
>> 428 reg = <0 0xe61c0000 0 0x200>;
>> 429 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
>> 430 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
>> 431 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
>> 432 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
>> 433 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
>> 434 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
>> 435 clocks = <&cpg CPG_MOD 407>;
>> 436 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
>> 437 resets = <&cpg 407>;
>> 438 };
>> 439
613 hscif0: serial@e6540000 { 440 hscif0: serial@e6540000 {
614 compatible = "renesas, 441 compatible = "renesas,hscif-r8a77990",
615 "renesas, 442 "renesas,rcar-gen3-hscif",
616 "renesas, 443 "renesas,hscif";
617 reg = <0 0xe6540000 0 444 reg = <0 0xe6540000 0 0x60>;
618 interrupts = <GIC_SPI 445 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
619 clocks = <&cpg CPG_MOD 446 clocks = <&cpg CPG_MOD 520>,
620 <&cpg CPG_COR 447 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
621 <&scif_clk>; 448 <&scif_clk>;
622 clock-names = "fck", " 449 clock-names = "fck", "brg_int", "scif_clk";
623 dmas = <&dmac1 0x31>, 450 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
624 <&dmac2 0x31>, 451 <&dmac2 0x31>, <&dmac2 0x30>;
625 dma-names = "tx", "rx" 452 dma-names = "tx", "rx", "tx", "rx";
626 power-domains = <&sysc 453 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
627 resets = <&cpg 520>; 454 resets = <&cpg 520>;
628 status = "disabled"; 455 status = "disabled";
629 }; 456 };
630 457
631 hscif1: serial@e6550000 { 458 hscif1: serial@e6550000 {
632 compatible = "renesas, 459 compatible = "renesas,hscif-r8a77990",
633 "renesas, 460 "renesas,rcar-gen3-hscif",
634 "renesas, 461 "renesas,hscif";
635 reg = <0 0xe6550000 0 462 reg = <0 0xe6550000 0 0x60>;
636 interrupts = <GIC_SPI 463 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
637 clocks = <&cpg CPG_MOD 464 clocks = <&cpg CPG_MOD 519>,
638 <&cpg CPG_COR 465 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
639 <&scif_clk>; 466 <&scif_clk>;
640 clock-names = "fck", " 467 clock-names = "fck", "brg_int", "scif_clk";
641 dmas = <&dmac1 0x33>, 468 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
642 <&dmac2 0x33>, 469 <&dmac2 0x33>, <&dmac2 0x32>;
643 dma-names = "tx", "rx" 470 dma-names = "tx", "rx", "tx", "rx";
644 power-domains = <&sysc 471 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
645 resets = <&cpg 519>; 472 resets = <&cpg 519>;
646 status = "disabled"; 473 status = "disabled";
647 }; 474 };
648 475
649 hscif2: serial@e6560000 { 476 hscif2: serial@e6560000 {
650 compatible = "renesas, 477 compatible = "renesas,hscif-r8a77990",
651 "renesas, 478 "renesas,rcar-gen3-hscif",
652 "renesas, 479 "renesas,hscif";
653 reg = <0 0xe6560000 0 480 reg = <0 0xe6560000 0 0x60>;
654 interrupts = <GIC_SPI 481 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
655 clocks = <&cpg CPG_MOD 482 clocks = <&cpg CPG_MOD 518>,
656 <&cpg CPG_COR 483 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
657 <&scif_clk>; 484 <&scif_clk>;
658 clock-names = "fck", " 485 clock-names = "fck", "brg_int", "scif_clk";
659 dmas = <&dmac1 0x35>, 486 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
660 <&dmac2 0x35>, 487 <&dmac2 0x35>, <&dmac2 0x34>;
661 dma-names = "tx", "rx" 488 dma-names = "tx", "rx", "tx", "rx";
662 power-domains = <&sysc 489 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
663 resets = <&cpg 518>; 490 resets = <&cpg 518>;
664 status = "disabled"; 491 status = "disabled";
665 }; 492 };
666 493
667 hscif3: serial@e66a0000 { 494 hscif3: serial@e66a0000 {
668 compatible = "renesas, 495 compatible = "renesas,hscif-r8a77990",
669 "renesas, 496 "renesas,rcar-gen3-hscif",
670 "renesas, 497 "renesas,hscif";
671 reg = <0 0xe66a0000 0 498 reg = <0 0xe66a0000 0 0x60>;
672 interrupts = <GIC_SPI 499 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
673 clocks = <&cpg CPG_MOD 500 clocks = <&cpg CPG_MOD 517>,
674 <&cpg CPG_COR 501 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
675 <&scif_clk>; 502 <&scif_clk>;
676 clock-names = "fck", " 503 clock-names = "fck", "brg_int", "scif_clk";
677 dmas = <&dmac0 0x37>, 504 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
678 dma-names = "tx", "rx" 505 dma-names = "tx", "rx";
679 power-domains = <&sysc 506 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
680 resets = <&cpg 517>; 507 resets = <&cpg 517>;
681 status = "disabled"; 508 status = "disabled";
682 }; 509 };
683 510
684 hscif4: serial@e66b0000 { 511 hscif4: serial@e66b0000 {
685 compatible = "renesas, 512 compatible = "renesas,hscif-r8a77990",
686 "renesas, 513 "renesas,rcar-gen3-hscif",
687 "renesas, 514 "renesas,hscif";
688 reg = <0 0xe66b0000 0 515 reg = <0 0xe66b0000 0 0x60>;
689 interrupts = <GIC_SPI 516 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
690 clocks = <&cpg CPG_MOD 517 clocks = <&cpg CPG_MOD 516>,
691 <&cpg CPG_COR 518 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
692 <&scif_clk>; 519 <&scif_clk>;
693 clock-names = "fck", " 520 clock-names = "fck", "brg_int", "scif_clk";
694 dmas = <&dmac0 0x39>, 521 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
695 dma-names = "tx", "rx" 522 dma-names = "tx", "rx";
696 power-domains = <&sysc 523 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
697 resets = <&cpg 516>; 524 resets = <&cpg 516>;
698 status = "disabled"; 525 status = "disabled";
699 }; 526 };
700 527
701 hsusb: usb@e6590000 { 528 hsusb: usb@e6590000 {
702 compatible = "renesas, 529 compatible = "renesas,usbhs-r8a77990",
703 "renesas, 530 "renesas,rcar-gen3-usbhs";
704 reg = <0 0xe6590000 0 531 reg = <0 0xe6590000 0 0x200>;
705 interrupts = <GIC_SPI 532 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
706 clocks = <&cpg CPG_MOD 533 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
707 dmas = <&usb_dmac0 0>, 534 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
708 <&usb_dmac1 0>, 535 <&usb_dmac1 0>, <&usb_dmac1 1>;
709 dma-names = "ch0", "ch 536 dma-names = "ch0", "ch1", "ch2", "ch3";
710 renesas,buswait = <11> 537 renesas,buswait = <11>;
711 phys = <&usb2_phy0 3>; !! 538 phys = <&usb2_phy0>;
712 phy-names = "usb"; 539 phy-names = "usb";
713 power-domains = <&sysc 540 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
714 resets = <&cpg 704>, < 541 resets = <&cpg 704>, <&cpg 703>;
715 status = "disabled"; 542 status = "disabled";
716 }; 543 };
717 544
718 usb_dmac0: dma-controller@e65a 545 usb_dmac0: dma-controller@e65a0000 {
719 compatible = "renesas, 546 compatible = "renesas,r8a77990-usb-dmac",
720 "renesas, 547 "renesas,usb-dmac";
721 reg = <0 0xe65a0000 0 548 reg = <0 0xe65a0000 0 0x100>;
722 interrupts = <GIC_SPI !! 549 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
723 <GIC_SPI !! 550 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
724 interrupt-names = "ch0 551 interrupt-names = "ch0", "ch1";
725 clocks = <&cpg CPG_MOD 552 clocks = <&cpg CPG_MOD 330>;
726 power-domains = <&sysc 553 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
727 resets = <&cpg 330>; 554 resets = <&cpg 330>;
728 #dma-cells = <1>; 555 #dma-cells = <1>;
729 dma-channels = <2>; 556 dma-channels = <2>;
730 }; 557 };
731 558
732 usb_dmac1: dma-controller@e65b 559 usb_dmac1: dma-controller@e65b0000 {
733 compatible = "renesas, 560 compatible = "renesas,r8a77990-usb-dmac",
734 "renesas, 561 "renesas,usb-dmac";
735 reg = <0 0xe65b0000 0 562 reg = <0 0xe65b0000 0 0x100>;
736 interrupts = <GIC_SPI !! 563 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
737 <GIC_SPI !! 564 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
738 interrupt-names = "ch0 565 interrupt-names = "ch0", "ch1";
739 clocks = <&cpg CPG_MOD 566 clocks = <&cpg CPG_MOD 331>;
740 power-domains = <&sysc 567 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
741 resets = <&cpg 331>; 568 resets = <&cpg 331>;
742 #dma-cells = <1>; 569 #dma-cells = <1>;
743 dma-channels = <2>; 570 dma-channels = <2>;
744 }; 571 };
745 572
746 arm_cc630p: crypto@e6601000 { <<
747 compatible = "arm,cryp <<
748 interrupts = <GIC_SPI <<
749 reg = <0x0 0xe6601000 <<
750 clocks = <&cpg CPG_MOD <<
751 resets = <&cpg 229>; <<
752 power-domains = <&sysc <<
753 }; <<
754 <<
755 dmac0: dma-controller@e6700000 573 dmac0: dma-controller@e6700000 {
756 compatible = "renesas, 574 compatible = "renesas,dmac-r8a77990",
757 "renesas, 575 "renesas,rcar-dmac";
758 reg = <0 0xe6700000 0 576 reg = <0 0xe6700000 0 0x10000>;
759 interrupts = <GIC_SPI !! 577 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH
760 <GIC_SPI !! 578 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
761 <GIC_SPI !! 579 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
762 <GIC_SPI !! 580 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
763 <GIC_SPI !! 581 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
764 <GIC_SPI !! 582 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
765 <GIC_SPI !! 583 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
766 <GIC_SPI !! 584 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
767 <GIC_SPI !! 585 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
768 <GIC_SPI !! 586 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
769 <GIC_SPI !! 587 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
770 <GIC_SPI !! 588 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
771 <GIC_SPI !! 589 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
772 <GIC_SPI !! 590 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
773 <GIC_SPI !! 591 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
774 <GIC_SPI !! 592 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH
775 <GIC_SPI !! 593 GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
776 interrupt-names = "err 594 interrupt-names = "error",
777 "ch0", 595 "ch0", "ch1", "ch2", "ch3",
778 "ch4", 596 "ch4", "ch5", "ch6", "ch7",
779 "ch8", 597 "ch8", "ch9", "ch10", "ch11",
780 "ch12" 598 "ch12", "ch13", "ch14", "ch15";
781 clocks = <&cpg CPG_MOD 599 clocks = <&cpg CPG_MOD 219>;
782 clock-names = "fck"; 600 clock-names = "fck";
783 power-domains = <&sysc 601 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
784 resets = <&cpg 219>; 602 resets = <&cpg 219>;
785 #dma-cells = <1>; 603 #dma-cells = <1>;
786 dma-channels = <16>; 604 dma-channels = <16>;
787 iommus = <&ipmmu_ds0 0 605 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
788 <&ipmmu_ds0 2>, 606 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
789 <&ipmmu_ds0 4>, 607 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
790 <&ipmmu_ds0 6>, 608 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
791 <&ipmmu_ds0 8>, 609 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
792 <&ipmmu_ds0 10> 610 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
793 <&ipmmu_ds0 12> 611 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
794 <&ipmmu_ds0 14> 612 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
795 }; 613 };
796 614
797 dmac1: dma-controller@e7300000 615 dmac1: dma-controller@e7300000 {
798 compatible = "renesas, 616 compatible = "renesas,dmac-r8a77990",
799 "renesas, 617 "renesas,rcar-dmac";
800 reg = <0 0xe7300000 0 618 reg = <0 0xe7300000 0 0x10000>;
801 interrupts = <GIC_SPI !! 619 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
802 <GIC_SPI !! 620 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
803 <GIC_SPI !! 621 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
804 <GIC_SPI !! 622 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
805 <GIC_SPI !! 623 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
806 <GIC_SPI !! 624 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
807 <GIC_SPI !! 625 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
808 <GIC_SPI !! 626 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
809 <GIC_SPI !! 627 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
810 <GIC_SPI !! 628 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
811 <GIC_SPI !! 629 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
812 <GIC_SPI !! 630 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
813 <GIC_SPI !! 631 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
814 <GIC_SPI !! 632 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
815 <GIC_SPI !! 633 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
816 <GIC_SPI !! 634 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
817 <GIC_SPI !! 635 GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
818 interrupt-names = "err 636 interrupt-names = "error",
819 "ch0", 637 "ch0", "ch1", "ch2", "ch3",
820 "ch4", 638 "ch4", "ch5", "ch6", "ch7",
821 "ch8", 639 "ch8", "ch9", "ch10", "ch11",
822 "ch12" 640 "ch12", "ch13", "ch14", "ch15";
823 clocks = <&cpg CPG_MOD 641 clocks = <&cpg CPG_MOD 218>;
824 clock-names = "fck"; 642 clock-names = "fck";
825 power-domains = <&sysc 643 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
826 resets = <&cpg 218>; 644 resets = <&cpg 218>;
827 #dma-cells = <1>; 645 #dma-cells = <1>;
828 dma-channels = <16>; 646 dma-channels = <16>;
829 iommus = <&ipmmu_ds1 0 647 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
830 <&ipmmu_ds1 2>, 648 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
831 <&ipmmu_ds1 4>, 649 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
832 <&ipmmu_ds1 6>, 650 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
833 <&ipmmu_ds1 8>, 651 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
834 <&ipmmu_ds1 10> 652 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
835 <&ipmmu_ds1 12> 653 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
836 <&ipmmu_ds1 14> 654 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
837 }; 655 };
838 656
839 dmac2: dma-controller@e7310000 657 dmac2: dma-controller@e7310000 {
840 compatible = "renesas, 658 compatible = "renesas,dmac-r8a77990",
841 "renesas, 659 "renesas,rcar-dmac";
842 reg = <0 0xe7310000 0 660 reg = <0 0xe7310000 0 0x10000>;
843 interrupts = <GIC_SPI !! 661 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH
844 <GIC_SPI !! 662 GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH
845 <GIC_SPI !! 663 GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH
846 <GIC_SPI !! 664 GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH
847 <GIC_SPI !! 665 GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH
848 <GIC_SPI !! 666 GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH
849 <GIC_SPI !! 667 GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH
850 <GIC_SPI !! 668 GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH
851 <GIC_SPI !! 669 GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH
852 <GIC_SPI !! 670 GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH
853 <GIC_SPI !! 671 GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH
854 <GIC_SPI !! 672 GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH
855 <GIC_SPI !! 673 GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH
856 <GIC_SPI !! 674 GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH
857 <GIC_SPI !! 675 GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH
858 <GIC_SPI !! 676 GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH
859 <GIC_SPI !! 677 GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
860 interrupt-names = "err 678 interrupt-names = "error",
861 "ch0", 679 "ch0", "ch1", "ch2", "ch3",
862 "ch4", 680 "ch4", "ch5", "ch6", "ch7",
863 "ch8", 681 "ch8", "ch9", "ch10", "ch11",
864 "ch12" 682 "ch12", "ch13", "ch14", "ch15";
865 clocks = <&cpg CPG_MOD 683 clocks = <&cpg CPG_MOD 217>;
866 clock-names = "fck"; 684 clock-names = "fck";
867 power-domains = <&sysc 685 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
868 resets = <&cpg 217>; 686 resets = <&cpg 217>;
869 #dma-cells = <1>; 687 #dma-cells = <1>;
870 dma-channels = <16>; 688 dma-channels = <16>;
871 iommus = <&ipmmu_ds1 1 689 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
872 <&ipmmu_ds1 18> 690 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
873 <&ipmmu_ds1 20> 691 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
874 <&ipmmu_ds1 22> 692 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
875 <&ipmmu_ds1 24> 693 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
876 <&ipmmu_ds1 26> 694 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
877 <&ipmmu_ds1 28> 695 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
878 <&ipmmu_ds1 30> 696 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
879 }; 697 };
880 698
881 ipmmu_ds0: iommu@e6740000 { !! 699 ipmmu_ds0: mmu@e6740000 {
882 compatible = "renesas, 700 compatible = "renesas,ipmmu-r8a77990";
883 reg = <0 0xe6740000 0 701 reg = <0 0xe6740000 0 0x1000>;
884 renesas,ipmmu-main = < 702 renesas,ipmmu-main = <&ipmmu_mm 0>;
885 power-domains = <&sysc 703 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
886 #iommu-cells = <1>; 704 #iommu-cells = <1>;
887 }; 705 };
888 706
889 ipmmu_ds1: iommu@e7740000 { !! 707 ipmmu_ds1: mmu@e7740000 {
890 compatible = "renesas, 708 compatible = "renesas,ipmmu-r8a77990";
891 reg = <0 0xe7740000 0 709 reg = <0 0xe7740000 0 0x1000>;
892 renesas,ipmmu-main = < 710 renesas,ipmmu-main = <&ipmmu_mm 1>;
893 power-domains = <&sysc 711 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
894 #iommu-cells = <1>; 712 #iommu-cells = <1>;
895 }; 713 };
896 714
897 ipmmu_hc: iommu@e6570000 { !! 715 ipmmu_hc: mmu@e6570000 {
898 compatible = "renesas, 716 compatible = "renesas,ipmmu-r8a77990";
899 reg = <0 0xe6570000 0 717 reg = <0 0xe6570000 0 0x1000>;
900 renesas,ipmmu-main = < 718 renesas,ipmmu-main = <&ipmmu_mm 2>;
901 power-domains = <&sysc 719 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
902 #iommu-cells = <1>; 720 #iommu-cells = <1>;
903 }; 721 };
904 722
905 ipmmu_mm: iommu@e67b0000 { !! 723 ipmmu_mm: mmu@e67b0000 {
906 compatible = "renesas, 724 compatible = "renesas,ipmmu-r8a77990";
907 reg = <0 0xe67b0000 0 725 reg = <0 0xe67b0000 0 0x1000>;
908 interrupts = <GIC_SPI 726 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
909 <GIC_SPI 727 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
910 power-domains = <&sysc 728 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
911 #iommu-cells = <1>; 729 #iommu-cells = <1>;
912 }; 730 };
913 731
914 ipmmu_mp: iommu@ec670000 { !! 732 ipmmu_mp: mmu@ec670000 {
915 compatible = "renesas, 733 compatible = "renesas,ipmmu-r8a77990";
916 reg = <0 0xec670000 0 734 reg = <0 0xec670000 0 0x1000>;
917 renesas,ipmmu-main = < 735 renesas,ipmmu-main = <&ipmmu_mm 4>;
918 power-domains = <&sysc 736 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
919 #iommu-cells = <1>; 737 #iommu-cells = <1>;
920 }; 738 };
921 739
922 ipmmu_pv0: iommu@fd800000 { !! 740 ipmmu_pv0: mmu@fd800000 {
923 compatible = "renesas, 741 compatible = "renesas,ipmmu-r8a77990";
924 reg = <0 0xfd800000 0 742 reg = <0 0xfd800000 0 0x1000>;
925 renesas,ipmmu-main = < 743 renesas,ipmmu-main = <&ipmmu_mm 6>;
926 power-domains = <&sysc 744 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
927 #iommu-cells = <1>; 745 #iommu-cells = <1>;
928 }; 746 };
929 747
930 ipmmu_rt: iommu@ffc80000 { !! 748 ipmmu_rt: mmu@ffc80000 {
931 compatible = "renesas, 749 compatible = "renesas,ipmmu-r8a77990";
932 reg = <0 0xffc80000 0 750 reg = <0 0xffc80000 0 0x1000>;
933 renesas,ipmmu-main = < 751 renesas,ipmmu-main = <&ipmmu_mm 10>;
934 power-domains = <&sysc 752 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
935 #iommu-cells = <1>; 753 #iommu-cells = <1>;
936 }; 754 };
937 755
938 ipmmu_vc0: iommu@fe6b0000 { !! 756 ipmmu_vc0: mmu@fe6b0000 {
939 compatible = "renesas, 757 compatible = "renesas,ipmmu-r8a77990";
940 reg = <0 0xfe6b0000 0 758 reg = <0 0xfe6b0000 0 0x1000>;
941 renesas,ipmmu-main = < 759 renesas,ipmmu-main = <&ipmmu_mm 12>;
942 power-domains = <&sysc 760 power-domains = <&sysc R8A77990_PD_A3VC>;
943 #iommu-cells = <1>; 761 #iommu-cells = <1>;
944 }; 762 };
945 763
946 ipmmu_vi0: iommu@febd0000 { !! 764 ipmmu_vi0: mmu@febd0000 {
947 compatible = "renesas, 765 compatible = "renesas,ipmmu-r8a77990";
948 reg = <0 0xfebd0000 0 766 reg = <0 0xfebd0000 0 0x1000>;
949 renesas,ipmmu-main = < 767 renesas,ipmmu-main = <&ipmmu_mm 14>;
950 power-domains = <&sysc 768 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
951 #iommu-cells = <1>; 769 #iommu-cells = <1>;
952 }; 770 };
953 771
954 ipmmu_vp0: iommu@fe990000 { !! 772 ipmmu_vp0: mmu@fe990000 {
955 compatible = "renesas, 773 compatible = "renesas,ipmmu-r8a77990";
956 reg = <0 0xfe990000 0 774 reg = <0 0xfe990000 0 0x1000>;
957 renesas,ipmmu-main = < 775 renesas,ipmmu-main = <&ipmmu_mm 16>;
958 power-domains = <&sysc 776 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
959 #iommu-cells = <1>; 777 #iommu-cells = <1>;
960 }; 778 };
961 779
962 avb: ethernet@e6800000 { 780 avb: ethernet@e6800000 {
963 compatible = "renesas, 781 compatible = "renesas,etheravb-r8a77990",
964 "renesas, 782 "renesas,etheravb-rcar-gen3";
965 reg = <0 0xe6800000 0 783 reg = <0 0xe6800000 0 0x800>;
966 interrupts = <GIC_SPI 784 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
967 <GIC_SPI 785 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
968 <GIC_SPI 786 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
969 <GIC_SPI 787 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
970 <GIC_SPI 788 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
971 <GIC_SPI 789 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
972 <GIC_SPI 790 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
973 <GIC_SPI 791 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
974 <GIC_SPI 792 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
975 <GIC_SPI 793 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
976 <GIC_SPI 794 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
977 <GIC_SPI 795 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
978 <GIC_SPI 796 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
979 <GIC_SPI 797 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
980 <GIC_SPI 798 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
981 <GIC_SPI 799 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
982 <GIC_SPI 800 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
983 <GIC_SPI 801 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
984 <GIC_SPI 802 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
985 <GIC_SPI 803 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
986 <GIC_SPI 804 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
987 <GIC_SPI 805 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
988 <GIC_SPI 806 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
989 <GIC_SPI 807 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
990 <GIC_SPI 808 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
991 interrupt-names = "ch0 809 interrupt-names = "ch0", "ch1", "ch2", "ch3",
992 "ch4 810 "ch4", "ch5", "ch6", "ch7",
993 "ch8 811 "ch8", "ch9", "ch10", "ch11",
994 "ch1 812 "ch12", "ch13", "ch14", "ch15",
995 "ch1 813 "ch16", "ch17", "ch18", "ch19",
996 "ch2 814 "ch20", "ch21", "ch22", "ch23",
997 "ch2 815 "ch24";
998 clocks = <&cpg CPG_MOD 816 clocks = <&cpg CPG_MOD 812>;
999 clock-names = "fck"; <<
1000 power-domains = <&sys 817 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1001 resets = <&cpg 812>; 818 resets = <&cpg 812>;
1002 phy-mode = "rgmii"; 819 phy-mode = "rgmii";
1003 rx-internal-delay-ps <<
1004 iommus = <&ipmmu_ds0 820 iommus = <&ipmmu_ds0 16>;
1005 #address-cells = <1>; 821 #address-cells = <1>;
1006 #size-cells = <0>; 822 #size-cells = <0>;
1007 status = "disabled"; 823 status = "disabled";
1008 }; 824 };
1009 825
1010 can0: can@e6c30000 { 826 can0: can@e6c30000 {
1011 compatible = "renesas 827 compatible = "renesas,can-r8a77990",
1012 "renesas 828 "renesas,rcar-gen3-can";
1013 reg = <0 0xe6c30000 0 829 reg = <0 0xe6c30000 0 0x1000>;
1014 interrupts = <GIC_SPI 830 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
1015 clocks = <&cpg CPG_MO 831 clocks = <&cpg CPG_MOD 916>,
1016 <&cpg CPG_CORE 832 <&cpg CPG_CORE R8A77990_CLK_CANFD>,
1017 <&can_clk>; 833 <&can_clk>;
1018 clock-names = "clkp1" 834 clock-names = "clkp1", "clkp2", "can_clk";
1019 assigned-clocks = <&c 835 assigned-clocks = <&cpg CPG_CORE R8A77990_CLK_CANFD>;
1020 assigned-clock-rates 836 assigned-clock-rates = <40000000>;
1021 power-domains = <&sys 837 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1022 resets = <&cpg 916>; 838 resets = <&cpg 916>;
1023 status = "disabled"; 839 status = "disabled";
1024 }; 840 };
1025 841
1026 can1: can@e6c38000 { 842 can1: can@e6c38000 {
1027 compatible = "renesas 843 compatible = "renesas,can-r8a77990",
1028 "renesas 844 "renesas,rcar-gen3-can";
1029 reg = <0 0xe6c38000 0 845 reg = <0 0xe6c38000 0 0x1000>;
1030 interrupts = <GIC_SPI 846 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
1031 clocks = <&cpg CPG_MO 847 clocks = <&cpg CPG_MOD 915>,
1032 <&cpg CPG_CORE 848 <&cpg CPG_CORE R8A77990_CLK_CANFD>,
1033 <&can_clk>; 849 <&can_clk>;
1034 clock-names = "clkp1" 850 clock-names = "clkp1", "clkp2", "can_clk";
1035 assigned-clocks = <&c 851 assigned-clocks = <&cpg CPG_CORE R8A77990_CLK_CANFD>;
1036 assigned-clock-rates 852 assigned-clock-rates = <40000000>;
1037 power-domains = <&sys 853 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1038 resets = <&cpg 915>; 854 resets = <&cpg 915>;
1039 status = "disabled"; 855 status = "disabled";
1040 }; 856 };
1041 857
1042 canfd: can@e66c0000 { 858 canfd: can@e66c0000 {
1043 compatible = "renesas 859 compatible = "renesas,r8a77990-canfd",
1044 "renesas 860 "renesas,rcar-gen3-canfd";
1045 reg = <0 0xe66c0000 0 861 reg = <0 0xe66c0000 0 0x8000>;
1046 interrupts = <GIC_SPI 862 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
1047 <GIC_SPI 3 863 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1048 interrupt-names = "ch <<
1049 clocks = <&cpg CPG_MO 864 clocks = <&cpg CPG_MOD 914>,
1050 <&cpg CPG_CORE 865 <&cpg CPG_CORE R8A77990_CLK_CANFD>,
1051 <&can_clk>; 866 <&can_clk>;
1052 clock-names = "fck", 867 clock-names = "fck", "canfd", "can_clk";
1053 assigned-clocks = <&c 868 assigned-clocks = <&cpg CPG_CORE R8A77990_CLK_CANFD>;
1054 assigned-clock-rates 869 assigned-clock-rates = <40000000>;
1055 power-domains = <&sys 870 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1056 resets = <&cpg 914>; 871 resets = <&cpg 914>;
1057 status = "disabled"; 872 status = "disabled";
1058 873
1059 channel0 { 874 channel0 {
1060 status = "dis 875 status = "disabled";
1061 }; 876 };
1062 877
1063 channel1 { 878 channel1 {
1064 status = "dis 879 status = "disabled";
1065 }; 880 };
1066 }; 881 };
1067 882
1068 pwm0: pwm@e6e30000 { 883 pwm0: pwm@e6e30000 {
1069 compatible = "renesas 884 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
1070 reg = <0 0xe6e30000 0 885 reg = <0 0xe6e30000 0 0x8>;
1071 clocks = <&cpg CPG_MO 886 clocks = <&cpg CPG_MOD 523>;
1072 power-domains = <&sys 887 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1073 resets = <&cpg 523>; 888 resets = <&cpg 523>;
1074 #pwm-cells = <2>; 889 #pwm-cells = <2>;
1075 status = "disabled"; 890 status = "disabled";
1076 }; 891 };
1077 892
1078 pwm1: pwm@e6e31000 { 893 pwm1: pwm@e6e31000 {
1079 compatible = "renesas 894 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
1080 reg = <0 0xe6e31000 0 895 reg = <0 0xe6e31000 0 0x8>;
1081 clocks = <&cpg CPG_MO 896 clocks = <&cpg CPG_MOD 523>;
1082 power-domains = <&sys 897 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1083 resets = <&cpg 523>; 898 resets = <&cpg 523>;
1084 #pwm-cells = <2>; 899 #pwm-cells = <2>;
1085 status = "disabled"; 900 status = "disabled";
1086 }; 901 };
1087 902
1088 pwm2: pwm@e6e32000 { 903 pwm2: pwm@e6e32000 {
1089 compatible = "renesas 904 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
1090 reg = <0 0xe6e32000 0 905 reg = <0 0xe6e32000 0 0x8>;
1091 clocks = <&cpg CPG_MO 906 clocks = <&cpg CPG_MOD 523>;
1092 power-domains = <&sys 907 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1093 resets = <&cpg 523>; 908 resets = <&cpg 523>;
1094 #pwm-cells = <2>; 909 #pwm-cells = <2>;
1095 status = "disabled"; 910 status = "disabled";
1096 }; 911 };
1097 912
1098 pwm3: pwm@e6e33000 { 913 pwm3: pwm@e6e33000 {
1099 compatible = "renesas 914 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
1100 reg = <0 0xe6e33000 0 915 reg = <0 0xe6e33000 0 0x8>;
1101 clocks = <&cpg CPG_MO 916 clocks = <&cpg CPG_MOD 523>;
1102 power-domains = <&sys 917 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1103 resets = <&cpg 523>; 918 resets = <&cpg 523>;
1104 #pwm-cells = <2>; 919 #pwm-cells = <2>;
1105 status = "disabled"; 920 status = "disabled";
1106 }; 921 };
1107 922
1108 pwm4: pwm@e6e34000 { 923 pwm4: pwm@e6e34000 {
1109 compatible = "renesas 924 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
1110 reg = <0 0xe6e34000 0 925 reg = <0 0xe6e34000 0 0x8>;
1111 clocks = <&cpg CPG_MO 926 clocks = <&cpg CPG_MOD 523>;
1112 power-domains = <&sys 927 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1113 resets = <&cpg 523>; 928 resets = <&cpg 523>;
1114 #pwm-cells = <2>; 929 #pwm-cells = <2>;
1115 status = "disabled"; 930 status = "disabled";
1116 }; 931 };
1117 932
1118 pwm5: pwm@e6e35000 { 933 pwm5: pwm@e6e35000 {
1119 compatible = "renesas 934 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
1120 reg = <0 0xe6e35000 0 935 reg = <0 0xe6e35000 0 0x8>;
1121 clocks = <&cpg CPG_MO 936 clocks = <&cpg CPG_MOD 523>;
1122 power-domains = <&sys 937 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1123 resets = <&cpg 523>; 938 resets = <&cpg 523>;
1124 #pwm-cells = <2>; 939 #pwm-cells = <2>;
1125 status = "disabled"; 940 status = "disabled";
1126 }; 941 };
1127 942
1128 pwm6: pwm@e6e36000 { 943 pwm6: pwm@e6e36000 {
1129 compatible = "renesas 944 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
1130 reg = <0 0xe6e36000 0 945 reg = <0 0xe6e36000 0 0x8>;
1131 clocks = <&cpg CPG_MO 946 clocks = <&cpg CPG_MOD 523>;
1132 power-domains = <&sys 947 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1133 resets = <&cpg 523>; 948 resets = <&cpg 523>;
1134 #pwm-cells = <2>; 949 #pwm-cells = <2>;
1135 status = "disabled"; 950 status = "disabled";
1136 }; 951 };
1137 952
1138 scif0: serial@e6e60000 { 953 scif0: serial@e6e60000 {
1139 compatible = "renesas 954 compatible = "renesas,scif-r8a77990",
1140 "renesas 955 "renesas,rcar-gen3-scif", "renesas,scif";
1141 reg = <0 0xe6e60000 0 956 reg = <0 0xe6e60000 0 64>;
1142 interrupts = <GIC_SPI 957 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
1143 clocks = <&cpg CPG_MO 958 clocks = <&cpg CPG_MOD 207>,
1144 <&cpg CPG_CO 959 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
1145 <&scif_clk>; 960 <&scif_clk>;
1146 clock-names = "fck", 961 clock-names = "fck", "brg_int", "scif_clk";
1147 dmas = <&dmac1 0x51>, 962 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1148 <&dmac2 0x51>, 963 <&dmac2 0x51>, <&dmac2 0x50>;
1149 dma-names = "tx", "rx 964 dma-names = "tx", "rx", "tx", "rx";
1150 power-domains = <&sys 965 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1151 resets = <&cpg 207>; 966 resets = <&cpg 207>;
1152 status = "disabled"; 967 status = "disabled";
1153 }; 968 };
1154 969
1155 scif1: serial@e6e68000 { 970 scif1: serial@e6e68000 {
1156 compatible = "renesas 971 compatible = "renesas,scif-r8a77990",
1157 "renesas 972 "renesas,rcar-gen3-scif", "renesas,scif";
1158 reg = <0 0xe6e68000 0 973 reg = <0 0xe6e68000 0 64>;
1159 interrupts = <GIC_SPI 974 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
1160 clocks = <&cpg CPG_MO 975 clocks = <&cpg CPG_MOD 206>,
1161 <&cpg CPG_CO 976 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
1162 <&scif_clk>; 977 <&scif_clk>;
1163 clock-names = "fck", 978 clock-names = "fck", "brg_int", "scif_clk";
1164 dmas = <&dmac1 0x53>, 979 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1165 <&dmac2 0x53>, 980 <&dmac2 0x53>, <&dmac2 0x52>;
1166 dma-names = "tx", "rx 981 dma-names = "tx", "rx", "tx", "rx";
1167 power-domains = <&sys 982 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1168 resets = <&cpg 206>; 983 resets = <&cpg 206>;
1169 status = "disabled"; 984 status = "disabled";
1170 }; 985 };
1171 986
1172 scif2: serial@e6e88000 { 987 scif2: serial@e6e88000 {
1173 compatible = "renesas 988 compatible = "renesas,scif-r8a77990",
1174 "renesas 989 "renesas,rcar-gen3-scif", "renesas,scif";
1175 reg = <0 0xe6e88000 0 990 reg = <0 0xe6e88000 0 64>;
1176 interrupts = <GIC_SPI 991 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
1177 clocks = <&cpg CPG_MO 992 clocks = <&cpg CPG_MOD 310>,
1178 <&cpg CPG_CO 993 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
1179 <&scif_clk>; 994 <&scif_clk>;
1180 clock-names = "fck", 995 clock-names = "fck", "brg_int", "scif_clk";
1181 dmas = <&dmac1 0x13>, !! 996
1182 <&dmac2 0x13>, <<
1183 dma-names = "tx", "rx <<
1184 power-domains = <&sys 997 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1185 resets = <&cpg 310>; 998 resets = <&cpg 310>;
1186 status = "disabled"; 999 status = "disabled";
1187 }; 1000 };
1188 1001
1189 scif3: serial@e6c50000 { 1002 scif3: serial@e6c50000 {
1190 compatible = "renesas 1003 compatible = "renesas,scif-r8a77990",
1191 "renesas 1004 "renesas,rcar-gen3-scif", "renesas,scif";
1192 reg = <0 0xe6c50000 0 1005 reg = <0 0xe6c50000 0 64>;
1193 interrupts = <GIC_SPI 1006 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1194 clocks = <&cpg CPG_MO 1007 clocks = <&cpg CPG_MOD 204>,
1195 <&cpg CPG_CO 1008 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
1196 <&scif_clk>; 1009 <&scif_clk>;
1197 clock-names = "fck", 1010 clock-names = "fck", "brg_int", "scif_clk";
1198 dmas = <&dmac0 0x57>, 1011 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1199 dma-names = "tx", "rx 1012 dma-names = "tx", "rx";
1200 power-domains = <&sys 1013 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1201 resets = <&cpg 204>; 1014 resets = <&cpg 204>;
1202 status = "disabled"; 1015 status = "disabled";
1203 }; 1016 };
1204 1017
1205 scif4: serial@e6c40000 { 1018 scif4: serial@e6c40000 {
1206 compatible = "renesas 1019 compatible = "renesas,scif-r8a77990",
1207 "renesas 1020 "renesas,rcar-gen3-scif", "renesas,scif";
1208 reg = <0 0xe6c40000 0 1021 reg = <0 0xe6c40000 0 64>;
1209 interrupts = <GIC_SPI 1022 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1210 clocks = <&cpg CPG_MO 1023 clocks = <&cpg CPG_MOD 203>,
1211 <&cpg CPG_CO 1024 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
1212 <&scif_clk>; 1025 <&scif_clk>;
1213 clock-names = "fck", 1026 clock-names = "fck", "brg_int", "scif_clk";
1214 dmas = <&dmac0 0x59>, 1027 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1215 dma-names = "tx", "rx 1028 dma-names = "tx", "rx";
1216 power-domains = <&sys 1029 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1217 resets = <&cpg 203>; 1030 resets = <&cpg 203>;
1218 status = "disabled"; 1031 status = "disabled";
1219 }; 1032 };
1220 1033
1221 scif5: serial@e6f30000 { 1034 scif5: serial@e6f30000 {
1222 compatible = "renesas 1035 compatible = "renesas,scif-r8a77990",
1223 "renesas 1036 "renesas,rcar-gen3-scif", "renesas,scif";
1224 reg = <0 0xe6f30000 0 1037 reg = <0 0xe6f30000 0 64>;
1225 interrupts = <GIC_SPI 1038 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1226 clocks = <&cpg CPG_MO 1039 clocks = <&cpg CPG_MOD 202>,
1227 <&cpg CPG_CO 1040 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
1228 <&scif_clk>; 1041 <&scif_clk>;
1229 clock-names = "fck", 1042 clock-names = "fck", "brg_int", "scif_clk";
1230 dmas = <&dmac0 0x5b>, 1043 dmas = <&dmac0 0x5b>, <&dmac0 0x5a>;
1231 dma-names = "tx", "rx 1044 dma-names = "tx", "rx";
1232 power-domains = <&sys 1045 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1233 resets = <&cpg 202>; 1046 resets = <&cpg 202>;
1234 status = "disabled"; 1047 status = "disabled";
1235 }; 1048 };
1236 1049
1237 msiof0: spi@e6e90000 { 1050 msiof0: spi@e6e90000 {
1238 compatible = "renesas 1051 compatible = "renesas,msiof-r8a77990",
1239 "renesas 1052 "renesas,rcar-gen3-msiof";
1240 reg = <0 0xe6e90000 0 1053 reg = <0 0xe6e90000 0 0x0064>;
1241 interrupts = <GIC_SPI 1054 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1242 clocks = <&cpg CPG_MO 1055 clocks = <&cpg CPG_MOD 211>;
1243 dmas = <&dmac1 0x41>, 1056 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1244 <&dmac2 0x41>, 1057 <&dmac2 0x41>, <&dmac2 0x40>;
1245 dma-names = "tx", "rx 1058 dma-names = "tx", "rx", "tx", "rx";
1246 power-domains = <&sys 1059 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1247 resets = <&cpg 211>; 1060 resets = <&cpg 211>;
1248 #address-cells = <1>; 1061 #address-cells = <1>;
1249 #size-cells = <0>; 1062 #size-cells = <0>;
1250 status = "disabled"; 1063 status = "disabled";
1251 }; 1064 };
1252 1065
1253 msiof1: spi@e6ea0000 { 1066 msiof1: spi@e6ea0000 {
1254 compatible = "renesas 1067 compatible = "renesas,msiof-r8a77990",
1255 "renesas 1068 "renesas,rcar-gen3-msiof";
1256 reg = <0 0xe6ea0000 0 1069 reg = <0 0xe6ea0000 0 0x0064>;
1257 interrupts = <GIC_SPI 1070 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1258 clocks = <&cpg CPG_MO 1071 clocks = <&cpg CPG_MOD 210>;
1259 dmas = <&dmac0 0x43>, !! 1072 dmas = <&dmac1 0x43>, <&dmac1 0x42>,
1260 dma-names = "tx", "rx !! 1073 <&dmac2 0x43>, <&dmac2 0x42>;
>> 1074 dma-names = "tx", "rx", "tx", "rx";
1261 power-domains = <&sys 1075 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1262 resets = <&cpg 210>; 1076 resets = <&cpg 210>;
1263 #address-cells = <1>; 1077 #address-cells = <1>;
1264 #size-cells = <0>; 1078 #size-cells = <0>;
1265 status = "disabled"; 1079 status = "disabled";
1266 }; 1080 };
1267 1081
1268 msiof2: spi@e6c00000 { 1082 msiof2: spi@e6c00000 {
1269 compatible = "renesas 1083 compatible = "renesas,msiof-r8a77990",
1270 "renesas 1084 "renesas,rcar-gen3-msiof";
1271 reg = <0 0xe6c00000 0 1085 reg = <0 0xe6c00000 0 0x0064>;
1272 interrupts = <GIC_SPI 1086 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1273 clocks = <&cpg CPG_MO 1087 clocks = <&cpg CPG_MOD 209>;
1274 dmas = <&dmac0 0x45>, 1088 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1275 dma-names = "tx", "rx 1089 dma-names = "tx", "rx";
1276 power-domains = <&sys 1090 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1277 resets = <&cpg 209>; 1091 resets = <&cpg 209>;
1278 #address-cells = <1>; 1092 #address-cells = <1>;
1279 #size-cells = <0>; 1093 #size-cells = <0>;
1280 status = "disabled"; 1094 status = "disabled";
1281 }; 1095 };
1282 1096
1283 msiof3: spi@e6c10000 { 1097 msiof3: spi@e6c10000 {
1284 compatible = "renesas 1098 compatible = "renesas,msiof-r8a77990",
1285 "renesas 1099 "renesas,rcar-gen3-msiof";
1286 reg = <0 0xe6c10000 0 1100 reg = <0 0xe6c10000 0 0x0064>;
1287 interrupts = <GIC_SPI 1101 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1288 clocks = <&cpg CPG_MO 1102 clocks = <&cpg CPG_MOD 208>;
1289 dmas = <&dmac0 0x47>, 1103 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1290 dma-names = "tx", "rx 1104 dma-names = "tx", "rx";
1291 power-domains = <&sys 1105 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1292 resets = <&cpg 208>; 1106 resets = <&cpg 208>;
1293 #address-cells = <1>; 1107 #address-cells = <1>;
1294 #size-cells = <0>; 1108 #size-cells = <0>;
1295 status = "disabled"; 1109 status = "disabled";
1296 }; 1110 };
1297 1111
1298 vin4: video@e6ef4000 { 1112 vin4: video@e6ef4000 {
1299 compatible = "renesas 1113 compatible = "renesas,vin-r8a77990";
1300 reg = <0 0xe6ef4000 0 1114 reg = <0 0xe6ef4000 0 0x1000>;
1301 interrupts = <GIC_SPI 1115 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
1302 clocks = <&cpg CPG_MO 1116 clocks = <&cpg CPG_MOD 807>;
1303 power-domains = <&sys 1117 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1304 resets = <&cpg 807>; 1118 resets = <&cpg 807>;
1305 renesas,id = <4>; 1119 renesas,id = <4>;
1306 status = "disabled"; 1120 status = "disabled";
1307 1121
1308 ports { 1122 ports {
1309 #address-cell 1123 #address-cells = <1>;
1310 #size-cells = 1124 #size-cells = <0>;
1311 1125
1312 port@1 { 1126 port@1 {
1313 #addr 1127 #address-cells = <1>;
1314 #size 1128 #size-cells = <0>;
1315 1129
1316 reg = 1130 reg = <1>;
1317 1131
1318 vin4c 1132 vin4csi40: endpoint@2 {
1319 1133 reg = <2>;
1320 !! 1134 remote-endpoint= <&csi40vin4>;
1321 }; 1135 };
1322 }; 1136 };
1323 }; 1137 };
1324 }; 1138 };
1325 1139
1326 vin5: video@e6ef5000 { 1140 vin5: video@e6ef5000 {
1327 compatible = "renesas 1141 compatible = "renesas,vin-r8a77990";
1328 reg = <0 0xe6ef5000 0 1142 reg = <0 0xe6ef5000 0 0x1000>;
1329 interrupts = <GIC_SPI 1143 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
1330 clocks = <&cpg CPG_MO 1144 clocks = <&cpg CPG_MOD 806>;
1331 power-domains = <&sys 1145 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1332 resets = <&cpg 806>; 1146 resets = <&cpg 806>;
1333 renesas,id = <5>; 1147 renesas,id = <5>;
1334 status = "disabled"; 1148 status = "disabled";
1335 1149
1336 ports { 1150 ports {
1337 #address-cell 1151 #address-cells = <1>;
1338 #size-cells = 1152 #size-cells = <0>;
1339 1153
1340 port@1 { 1154 port@1 {
1341 #addr 1155 #address-cells = <1>;
1342 #size 1156 #size-cells = <0>;
1343 1157
1344 reg = 1158 reg = <1>;
1345 1159
1346 vin5c 1160 vin5csi40: endpoint@2 {
1347 1161 reg = <2>;
1348 !! 1162 remote-endpoint= <&csi40vin5>;
1349 }; 1163 };
1350 }; 1164 };
1351 }; 1165 };
1352 }; 1166 };
1353 1167
1354 drif00: rif@e6f40000 { <<
1355 compatible = "renesas <<
1356 "renesas <<
1357 reg = <0 0xe6f40000 0 <<
1358 interrupts = <GIC_SPI <<
1359 clocks = <&cpg CPG_MO <<
1360 clock-names = "fck"; <<
1361 dmas = <&dmac1 0x20>, <<
1362 dma-names = "rx", "rx <<
1363 power-domains = <&sys <<
1364 resets = <&cpg 515>; <<
1365 renesas,bonding = <&d <<
1366 status = "disabled"; <<
1367 }; <<
1368 <<
1369 drif01: rif@e6f50000 { <<
1370 compatible = "renesas <<
1371 "renesas <<
1372 reg = <0 0xe6f50000 0 <<
1373 interrupts = <GIC_SPI <<
1374 clocks = <&cpg CPG_MO <<
1375 clock-names = "fck"; <<
1376 dmas = <&dmac1 0x22>, <<
1377 dma-names = "rx", "rx <<
1378 power-domains = <&sys <<
1379 resets = <&cpg 514>; <<
1380 renesas,bonding = <&d <<
1381 status = "disabled"; <<
1382 }; <<
1383 <<
1384 drif10: rif@e6f60000 { <<
1385 compatible = "renesas <<
1386 "renesas <<
1387 reg = <0 0xe6f60000 0 <<
1388 interrupts = <GIC_SPI <<
1389 clocks = <&cpg CPG_MO <<
1390 clock-names = "fck"; <<
1391 dmas = <&dmac1 0x24>, <<
1392 dma-names = "rx", "rx <<
1393 power-domains = <&sys <<
1394 resets = <&cpg 513>; <<
1395 renesas,bonding = <&d <<
1396 status = "disabled"; <<
1397 }; <<
1398 <<
1399 drif11: rif@e6f70000 { <<
1400 compatible = "renesas <<
1401 "renesas <<
1402 reg = <0 0xe6f70000 0 <<
1403 interrupts = <GIC_SPI <<
1404 clocks = <&cpg CPG_MO <<
1405 clock-names = "fck"; <<
1406 dmas = <&dmac1 0x26>, <<
1407 dma-names = "rx", "rx <<
1408 power-domains = <&sys <<
1409 resets = <&cpg 512>; <<
1410 renesas,bonding = <&d <<
1411 status = "disabled"; <<
1412 }; <<
1413 <<
1414 drif20: rif@e6f80000 { <<
1415 compatible = "renesas <<
1416 "renesas <<
1417 reg = <0 0xe6f80000 0 <<
1418 interrupts = <GIC_SPI <<
1419 clocks = <&cpg CPG_MO <<
1420 clock-names = "fck"; <<
1421 dmas = <&dmac0 0x28>; <<
1422 dma-names = "rx"; <<
1423 power-domains = <&sys <<
1424 resets = <&cpg 511>; <<
1425 renesas,bonding = <&d <<
1426 status = "disabled"; <<
1427 }; <<
1428 <<
1429 drif21: rif@e6f90000 { <<
1430 compatible = "renesas <<
1431 "renesas <<
1432 reg = <0 0xe6f90000 0 <<
1433 interrupts = <GIC_SPI <<
1434 clocks = <&cpg CPG_MO <<
1435 clock-names = "fck"; <<
1436 dmas = <&dmac0 0x2a>; <<
1437 dma-names = "rx"; <<
1438 power-domains = <&sys <<
1439 resets = <&cpg 510>; <<
1440 renesas,bonding = <&d <<
1441 status = "disabled"; <<
1442 }; <<
1443 <<
1444 drif30: rif@e6fa0000 { <<
1445 compatible = "renesas <<
1446 "renesas <<
1447 reg = <0 0xe6fa0000 0 <<
1448 interrupts = <GIC_SPI <<
1449 clocks = <&cpg CPG_MO <<
1450 clock-names = "fck"; <<
1451 dmas = <&dmac0 0x2c>; <<
1452 dma-names = "rx"; <<
1453 power-domains = <&sys <<
1454 resets = <&cpg 509>; <<
1455 renesas,bonding = <&d <<
1456 status = "disabled"; <<
1457 }; <<
1458 <<
1459 drif31: rif@e6fb0000 { <<
1460 compatible = "renesas <<
1461 "renesas <<
1462 reg = <0 0xe6fb0000 0 <<
1463 interrupts = <GIC_SPI <<
1464 clocks = <&cpg CPG_MO <<
1465 clock-names = "fck"; <<
1466 dmas = <&dmac0 0x2e>; <<
1467 dma-names = "rx"; <<
1468 power-domains = <&sys <<
1469 resets = <&cpg 508>; <<
1470 renesas,bonding = <&d <<
1471 status = "disabled"; <<
1472 }; <<
1473 <<
1474 rcar_sound: sound@ec500000 { 1168 rcar_sound: sound@ec500000 {
1475 /* 1169 /*
1476 * #sound-dai-cells i !! 1170 * #sound-dai-cells is required
1477 * 1171 *
1478 * Single DAI : #soun 1172 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1479 * Multi DAI : #soun 1173 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1480 */ 1174 */
1481 /* 1175 /*
1482 * #clock-cells is re 1176 * #clock-cells is required for audio_clkout0/1/2/3
1483 * 1177 *
1484 * clkout : #cl 1178 * clkout : #clock-cells = <0>; <&rcar_sound>;
1485 * clkout0/1/2/3: #cl 1179 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
1486 */ 1180 */
1487 compatible = "renesas !! 1181 compatible = "renesas,rcar_sound-r8a77990", "renesas,rcar_sound-gen3";
1488 reg = <0 0xec500000 0 !! 1182 reg = <0 0xec500000 0 0x1000>, /* SCU */
1489 <0 0xec5a0000 0 !! 1183 <0 0xec5a0000 0 0x100>, /* ADG */
1490 <0 0xec540000 0 !! 1184 <0 0xec540000 0 0x1000>, /* SSIU */
1491 <0 0xec541000 0 !! 1185 <0 0xec541000 0 0x280>, /* SSI */
1492 <0 0xec760000 0 !! 1186 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
1493 reg-names = "scu", "a 1187 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1494 1188
1495 clocks = <&cpg CPG_MO 1189 clocks = <&cpg CPG_MOD 1005>,
1496 <&cpg CPG_MO 1190 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
1497 <&cpg CPG_MO 1191 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
1498 <&cpg CPG_MO 1192 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
1499 <&cpg CPG_MO 1193 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
1500 <&cpg CPG_MO 1194 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
1501 <&cpg CPG_MO 1195 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
1502 <&cpg CPG_MO 1196 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
1503 <&cpg CPG_MO 1197 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
1504 <&cpg CPG_MO 1198 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
1505 <&cpg CPG_MO 1199 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
1506 <&cpg CPG_MO 1200 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1507 <&cpg CPG_MO 1201 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1508 <&cpg CPG_MO 1202 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
1509 <&audio_clk_ 1203 <&audio_clk_a>, <&audio_clk_b>,
1510 <&audio_clk_ 1204 <&audio_clk_c>,
1511 <&cpg CPG_MO !! 1205 <&cpg CPG_CORE R8A77990_CLK_ZA2>;
1512 clock-names = "ssi-al 1206 clock-names = "ssi-all",
1513 "ssi.9" 1207 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1514 "ssi.5" 1208 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1515 "ssi.1" 1209 "ssi.1", "ssi.0",
1516 "src.9" 1210 "src.9", "src.8", "src.7", "src.6",
1517 "src.5" 1211 "src.5", "src.4", "src.3", "src.2",
1518 "src.1" 1212 "src.1", "src.0",
1519 "mix.1" 1213 "mix.1", "mix.0",
1520 "ctu.1" 1214 "ctu.1", "ctu.0",
1521 "dvc.0" 1215 "dvc.0", "dvc.1",
1522 "clk_a" 1216 "clk_a", "clk_b", "clk_c", "clk_i";
1523 power-domains = <&sys 1217 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1524 resets = <&cpg 1005>, 1218 resets = <&cpg 1005>,
1525 <&cpg 1006>, 1219 <&cpg 1006>, <&cpg 1007>,
1526 <&cpg 1008>, 1220 <&cpg 1008>, <&cpg 1009>,
1527 <&cpg 1010>, 1221 <&cpg 1010>, <&cpg 1011>,
1528 <&cpg 1012>, 1222 <&cpg 1012>, <&cpg 1013>,
1529 <&cpg 1014>, 1223 <&cpg 1014>, <&cpg 1015>;
1530 reset-names = "ssi-al 1224 reset-names = "ssi-all",
1531 "ssi.9" 1225 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1532 "ssi.5" 1226 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1533 "ssi.1" 1227 "ssi.1", "ssi.0";
1534 status = "disabled"; 1228 status = "disabled";
1535 1229
1536 rcar_sound,ctu { <<
1537 ctu00: ctu-0 <<
1538 ctu01: ctu-1 <<
1539 ctu02: ctu-2 <<
1540 ctu03: ctu-3 <<
1541 ctu10: ctu-4 <<
1542 ctu11: ctu-5 <<
1543 ctu12: ctu-6 <<
1544 ctu13: ctu-7 <<
1545 }; <<
1546 <<
1547 rcar_sound,dvc { 1230 rcar_sound,dvc {
1548 dvc0: dvc-0 { 1231 dvc0: dvc-0 {
1549 dmas 1232 dmas = <&audma0 0xbc>;
1550 dma-n 1233 dma-names = "tx";
1551 }; 1234 };
1552 dvc1: dvc-1 { 1235 dvc1: dvc-1 {
1553 dmas 1236 dmas = <&audma0 0xbe>;
1554 dma-n 1237 dma-names = "tx";
1555 }; 1238 };
1556 }; 1239 };
1557 1240
1558 rcar_sound,mix { 1241 rcar_sound,mix {
1559 mix0: mix-0 { 1242 mix0: mix-0 { };
1560 mix1: mix-1 { 1243 mix1: mix-1 { };
1561 }; 1244 };
1562 1245
>> 1246 rcar_sound,ctu {
>> 1247 ctu00: ctu-0 { };
>> 1248 ctu01: ctu-1 { };
>> 1249 ctu02: ctu-2 { };
>> 1250 ctu03: ctu-3 { };
>> 1251 ctu10: ctu-4 { };
>> 1252 ctu11: ctu-5 { };
>> 1253 ctu12: ctu-6 { };
>> 1254 ctu13: ctu-7 { };
>> 1255 };
>> 1256
1563 rcar_sound,src { 1257 rcar_sound,src {
1564 src0: src-0 { 1258 src0: src-0 {
1565 inter 1259 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1566 dmas 1260 dmas = <&audma0 0x85>, <&audma0 0x9a>;
1567 dma-n 1261 dma-names = "rx", "tx";
1568 }; 1262 };
1569 src1: src-1 { 1263 src1: src-1 {
1570 inter 1264 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1571 dmas 1265 dmas = <&audma0 0x87>, <&audma0 0x9c>;
1572 dma-n 1266 dma-names = "rx", "tx";
1573 }; 1267 };
1574 src2: src-2 { 1268 src2: src-2 {
1575 inter 1269 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1576 dmas 1270 dmas = <&audma0 0x89>, <&audma0 0x9e>;
1577 dma-n 1271 dma-names = "rx", "tx";
1578 }; 1272 };
1579 src3: src-3 { 1273 src3: src-3 {
1580 inter 1274 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1581 dmas 1275 dmas = <&audma0 0x8b>, <&audma0 0xa0>;
1582 dma-n 1276 dma-names = "rx", "tx";
1583 }; 1277 };
1584 src4: src-4 { 1278 src4: src-4 {
1585 inter 1279 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1586 dmas 1280 dmas = <&audma0 0x8d>, <&audma0 0xb0>;
1587 dma-n 1281 dma-names = "rx", "tx";
1588 }; 1282 };
1589 src5: src-5 { 1283 src5: src-5 {
1590 inter 1284 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1591 dmas 1285 dmas = <&audma0 0x8f>, <&audma0 0xb2>;
1592 dma-n 1286 dma-names = "rx", "tx";
1593 }; 1287 };
1594 src6: src-6 { 1288 src6: src-6 {
1595 inter 1289 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1596 dmas 1290 dmas = <&audma0 0x91>, <&audma0 0xb4>;
1597 dma-n 1291 dma-names = "rx", "tx";
1598 }; 1292 };
1599 src7: src-7 { 1293 src7: src-7 {
1600 inter 1294 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1601 dmas 1295 dmas = <&audma0 0x93>, <&audma0 0xb6>;
1602 dma-n 1296 dma-names = "rx", "tx";
1603 }; 1297 };
1604 src8: src-8 { 1298 src8: src-8 {
1605 inter 1299 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1606 dmas 1300 dmas = <&audma0 0x95>, <&audma0 0xb8>;
1607 dma-n 1301 dma-names = "rx", "tx";
1608 }; 1302 };
1609 src9: src-9 { 1303 src9: src-9 {
1610 inter 1304 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
1611 dmas 1305 dmas = <&audma0 0x97>, <&audma0 0xba>;
1612 dma-n 1306 dma-names = "rx", "tx";
1613 }; 1307 };
1614 }; 1308 };
1615 1309
1616 rcar_sound,ssi { 1310 rcar_sound,ssi {
1617 ssi0: ssi-0 { 1311 ssi0: ssi-0 {
1618 inter 1312 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
1619 dmas 1313 dmas = <&audma0 0x01>, <&audma0 0x02>,
1620 1314 <&audma0 0x15>, <&audma0 0x16>;
1621 dma-n 1315 dma-names = "rx", "tx", "rxu", "txu";
1622 }; 1316 };
1623 ssi1: ssi-1 { 1317 ssi1: ssi-1 {
1624 inter 1318 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
1625 dmas 1319 dmas = <&audma0 0x03>, <&audma0 0x04>,
1626 1320 <&audma0 0x49>, <&audma0 0x4a>;
1627 dma-n 1321 dma-names = "rx", "tx", "rxu", "txu";
1628 }; 1322 };
1629 ssi2: ssi-2 { 1323 ssi2: ssi-2 {
1630 inter 1324 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
1631 dmas 1325 dmas = <&audma0 0x05>, <&audma0 0x06>,
1632 1326 <&audma0 0x63>, <&audma0 0x64>;
1633 dma-n 1327 dma-names = "rx", "tx", "rxu", "txu";
1634 }; 1328 };
1635 ssi3: ssi-3 { 1329 ssi3: ssi-3 {
1636 inter 1330 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1637 dmas 1331 dmas = <&audma0 0x07>, <&audma0 0x08>,
1638 1332 <&audma0 0x6f>, <&audma0 0x70>;
1639 dma-n 1333 dma-names = "rx", "tx", "rxu", "txu";
1640 }; 1334 };
1641 ssi4: ssi-4 { 1335 ssi4: ssi-4 {
1642 inter 1336 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1643 dmas 1337 dmas = <&audma0 0x09>, <&audma0 0x0a>,
1644 1338 <&audma0 0x71>, <&audma0 0x72>;
1645 dma-n 1339 dma-names = "rx", "tx", "rxu", "txu";
1646 }; 1340 };
1647 ssi5: ssi-5 { 1341 ssi5: ssi-5 {
1648 inter 1342 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1649 dmas 1343 dmas = <&audma0 0x0b>, <&audma0 0x0c>,
1650 1344 <&audma0 0x73>, <&audma0 0x74>;
1651 dma-n 1345 dma-names = "rx", "tx", "rxu", "txu";
1652 }; 1346 };
1653 ssi6: ssi-6 { 1347 ssi6: ssi-6 {
1654 inter 1348 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
1655 dmas 1349 dmas = <&audma0 0x0d>, <&audma0 0x0e>,
1656 1350 <&audma0 0x75>, <&audma0 0x76>;
1657 dma-n 1351 dma-names = "rx", "tx", "rxu", "txu";
1658 }; 1352 };
1659 ssi7: ssi-7 { 1353 ssi7: ssi-7 {
1660 inter 1354 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
1661 dmas 1355 dmas = <&audma0 0x0f>, <&audma0 0x10>,
1662 1356 <&audma0 0x79>, <&audma0 0x7a>;
1663 dma-n 1357 dma-names = "rx", "tx", "rxu", "txu";
1664 }; 1358 };
1665 ssi8: ssi-8 { 1359 ssi8: ssi-8 {
1666 inter 1360 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
1667 dmas 1361 dmas = <&audma0 0x11>, <&audma0 0x12>,
1668 1362 <&audma0 0x7b>, <&audma0 0x7c>;
1669 dma-n 1363 dma-names = "rx", "tx", "rxu", "txu";
1670 }; 1364 };
1671 ssi9: ssi-9 { 1365 ssi9: ssi-9 {
1672 inter 1366 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
1673 dmas 1367 dmas = <&audma0 0x13>, <&audma0 0x14>,
1674 1368 <&audma0 0x7d>, <&audma0 0x7e>;
1675 dma-n 1369 dma-names = "rx", "tx", "rxu", "txu";
1676 }; 1370 };
1677 }; 1371 };
1678 }; 1372 };
1679 1373
1680 mlp: mlp@ec520000 { <<
1681 compatible = "renesas <<
1682 "renesas <<
1683 reg = <0 0xec520000 0 <<
1684 interrupts = <GIC_SPI <<
1685 <GIC_SPI 385 <<
1686 clocks = <&cpg CPG_MO <<
1687 power-domains = <&sys <<
1688 resets = <&cpg 802>; <<
1689 status = "disabled"; <<
1690 }; <<
1691 <<
1692 audma0: dma-controller@ec7000 1374 audma0: dma-controller@ec700000 {
1693 compatible = "renesas 1375 compatible = "renesas,dmac-r8a77990",
1694 "renesas 1376 "renesas,rcar-dmac";
1695 reg = <0 0xec700000 0 1377 reg = <0 0xec700000 0 0x10000>;
1696 interrupts = <GIC_SPI !! 1378 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH
1697 <GIC_SPI !! 1379 GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
1698 <GIC_SPI !! 1380 GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
1699 <GIC_SPI !! 1381 GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
1700 <GIC_SPI !! 1382 GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
1701 <GIC_SPI !! 1383 GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
1702 <GIC_SPI !! 1384 GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
1703 <GIC_SPI !! 1385 GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
1704 <GIC_SPI !! 1386 GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
1705 <GIC_SPI !! 1387 GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
1706 <GIC_SPI !! 1388 GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
1707 <GIC_SPI !! 1389 GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
1708 <GIC_SPI !! 1390 GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
1709 <GIC_SPI !! 1391 GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH
1710 <GIC_SPI !! 1392 GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
1711 <GIC_SPI !! 1393 GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
1712 <GIC_SPI !! 1394 GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
1713 interrupt-names = "er 1395 interrupt-names = "error",
1714 "ch0" 1396 "ch0", "ch1", "ch2", "ch3",
1715 "ch4" 1397 "ch4", "ch5", "ch6", "ch7",
1716 "ch8" 1398 "ch8", "ch9", "ch10", "ch11",
1717 "ch12 1399 "ch12", "ch13", "ch14", "ch15";
1718 clocks = <&cpg CPG_MO 1400 clocks = <&cpg CPG_MOD 502>;
1719 clock-names = "fck"; 1401 clock-names = "fck";
1720 power-domains = <&sys 1402 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1721 resets = <&cpg 502>; 1403 resets = <&cpg 502>;
1722 #dma-cells = <1>; 1404 #dma-cells = <1>;
1723 dma-channels = <16>; 1405 dma-channels = <16>;
1724 iommus = <&ipmmu_mp 0 1406 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
1725 <&ipmmu_mp 2 1407 <&ipmmu_mp 2>, <&ipmmu_mp 3>,
1726 <&ipmmu_mp 4 1408 <&ipmmu_mp 4>, <&ipmmu_mp 5>,
1727 <&ipmmu_mp 6 1409 <&ipmmu_mp 6>, <&ipmmu_mp 7>,
1728 <&ipmmu_mp 8 1410 <&ipmmu_mp 8>, <&ipmmu_mp 9>,
1729 <&ipmmu_mp 1 1411 <&ipmmu_mp 10>, <&ipmmu_mp 11>,
1730 <&ipmmu_mp 1 1412 <&ipmmu_mp 12>, <&ipmmu_mp 13>,
1731 <&ipmmu_mp 1 1413 <&ipmmu_mp 14>, <&ipmmu_mp 15>;
1732 }; 1414 };
1733 1415
1734 xhci0: usb@ee000000 { 1416 xhci0: usb@ee000000 {
1735 compatible = "renesas 1417 compatible = "renesas,xhci-r8a77990",
1736 "renesas 1418 "renesas,rcar-gen3-xhci";
1737 reg = <0 0xee000000 0 1419 reg = <0 0xee000000 0 0xc00>;
1738 interrupts = <GIC_SPI 1420 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1739 clocks = <&cpg CPG_MO 1421 clocks = <&cpg CPG_MOD 328>;
1740 power-domains = <&sys 1422 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1741 resets = <&cpg 328>; 1423 resets = <&cpg 328>;
1742 status = "disabled"; 1424 status = "disabled";
1743 }; 1425 };
1744 1426
1745 usb3_peri0: usb@ee020000 { 1427 usb3_peri0: usb@ee020000 {
1746 compatible = "renesas 1428 compatible = "renesas,r8a77990-usb3-peri",
1747 "renesas 1429 "renesas,rcar-gen3-usb3-peri";
1748 reg = <0 0xee020000 0 1430 reg = <0 0xee020000 0 0x400>;
1749 interrupts = <GIC_SPI 1431 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1750 clocks = <&cpg CPG_MO 1432 clocks = <&cpg CPG_MOD 328>;
1751 power-domains = <&sys 1433 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1752 resets = <&cpg 328>; 1434 resets = <&cpg 328>;
1753 status = "disabled"; 1435 status = "disabled";
1754 }; 1436 };
1755 1437
1756 ohci0: usb@ee080000 { 1438 ohci0: usb@ee080000 {
1757 compatible = "generic 1439 compatible = "generic-ohci";
1758 reg = <0 0xee080000 0 1440 reg = <0 0xee080000 0 0x100>;
1759 interrupts = <GIC_SPI 1441 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1760 clocks = <&cpg CPG_MO 1442 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
1761 phys = <&usb2_phy0 1> !! 1443 phys = <&usb2_phy0>;
1762 phy-names = "usb"; 1444 phy-names = "usb";
1763 power-domains = <&sys 1445 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1764 resets = <&cpg 703>, 1446 resets = <&cpg 703>, <&cpg 704>;
1765 status = "disabled"; 1447 status = "disabled";
1766 }; 1448 };
1767 1449
1768 ehci0: usb@ee080100 { 1450 ehci0: usb@ee080100 {
1769 compatible = "generic 1451 compatible = "generic-ehci";
1770 reg = <0 0xee080100 0 1452 reg = <0 0xee080100 0 0x100>;
1771 interrupts = <GIC_SPI 1453 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1772 clocks = <&cpg CPG_MO 1454 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
1773 phys = <&usb2_phy0 2> !! 1455 phys = <&usb2_phy0>;
1774 phy-names = "usb"; 1456 phy-names = "usb";
1775 companion = <&ohci0>; 1457 companion = <&ohci0>;
1776 power-domains = <&sys 1458 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1777 resets = <&cpg 703>, 1459 resets = <&cpg 703>, <&cpg 704>;
1778 status = "disabled"; 1460 status = "disabled";
1779 }; 1461 };
1780 1462
1781 usb2_phy0: usb-phy@ee080200 { 1463 usb2_phy0: usb-phy@ee080200 {
1782 compatible = "renesas 1464 compatible = "renesas,usb2-phy-r8a77990",
1783 "renesas 1465 "renesas,rcar-gen3-usb2-phy";
1784 reg = <0 0xee080200 0 1466 reg = <0 0xee080200 0 0x700>;
1785 interrupts = <GIC_SPI 1467 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1786 clocks = <&cpg CPG_MO 1468 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
1787 power-domains = <&sys 1469 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1788 resets = <&cpg 703>, 1470 resets = <&cpg 703>, <&cpg 704>;
1789 #phy-cells = <1>; !! 1471 #phy-cells = <0>;
1790 status = "disabled"; 1472 status = "disabled";
1791 }; 1473 };
1792 1474
1793 sdhi0: mmc@ee100000 { !! 1475 sdhi0: sd@ee100000 {
1794 compatible = "renesas 1476 compatible = "renesas,sdhi-r8a77990",
1795 "renesas 1477 "renesas,rcar-gen3-sdhi";
1796 reg = <0 0xee100000 0 1478 reg = <0 0xee100000 0 0x2000>;
1797 interrupts = <GIC_SPI 1479 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
1798 clocks = <&cpg CPG_MO !! 1480 clocks = <&cpg CPG_MOD 314>;
1799 clock-names = "core", <<
1800 max-frequency = <2000 1481 max-frequency = <200000000>;
1801 power-domains = <&sys 1482 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1802 resets = <&cpg 314>; 1483 resets = <&cpg 314>;
1803 iommus = <&ipmmu_ds1 <<
1804 status = "disabled"; 1484 status = "disabled";
1805 }; 1485 };
1806 1486
1807 sdhi1: mmc@ee120000 { !! 1487 sdhi1: sd@ee120000 {
1808 compatible = "renesas 1488 compatible = "renesas,sdhi-r8a77990",
1809 "renesas 1489 "renesas,rcar-gen3-sdhi";
1810 reg = <0 0xee120000 0 1490 reg = <0 0xee120000 0 0x2000>;
1811 interrupts = <GIC_SPI 1491 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
1812 clocks = <&cpg CPG_MO !! 1492 clocks = <&cpg CPG_MOD 313>;
1813 clock-names = "core", <<
1814 max-frequency = <2000 1493 max-frequency = <200000000>;
1815 power-domains = <&sys 1494 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1816 resets = <&cpg 313>; 1495 resets = <&cpg 313>;
1817 iommus = <&ipmmu_ds1 <<
1818 status = "disabled"; 1496 status = "disabled";
1819 }; 1497 };
1820 1498
1821 sdhi3: mmc@ee160000 { !! 1499 sdhi3: sd@ee160000 {
1822 compatible = "renesas 1500 compatible = "renesas,sdhi-r8a77990",
1823 "renesas 1501 "renesas,rcar-gen3-sdhi";
1824 reg = <0 0xee160000 0 1502 reg = <0 0xee160000 0 0x2000>;
1825 interrupts = <GIC_SPI 1503 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
1826 clocks = <&cpg CPG_MO !! 1504 clocks = <&cpg CPG_MOD 311>;
1827 clock-names = "core", <<
1828 max-frequency = <2000 1505 max-frequency = <200000000>;
1829 power-domains = <&sys 1506 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1830 resets = <&cpg 311>; 1507 resets = <&cpg 311>;
1831 iommus = <&ipmmu_ds1 <<
1832 status = "disabled"; <<
1833 }; <<
1834 <<
1835 rpc: spi@ee200000 { <<
1836 compatible = "renesas <<
1837 "renesas <<
1838 reg = <0 0xee200000 0 <<
1839 <0 0x08000000 0 <<
1840 <0 0xee208000 0 <<
1841 reg-names = "regs", " <<
1842 interrupts = <GIC_SPI <<
1843 clocks = <&cpg CPG_MO <<
1844 power-domains = <&sys <<
1845 resets = <&cpg 917>; <<
1846 #address-cells = <1>; <<
1847 #size-cells = <0>; <<
1848 status = "disabled"; 1508 status = "disabled";
1849 }; 1509 };
1850 1510
1851 gic: interrupt-controller@f10 1511 gic: interrupt-controller@f1010000 {
1852 compatible = "arm,gic 1512 compatible = "arm,gic-400";
1853 #interrupt-cells = <3 1513 #interrupt-cells = <3>;
1854 #address-cells = <0>; 1514 #address-cells = <0>;
1855 interrupt-controller; 1515 interrupt-controller;
1856 reg = <0x0 0xf1010000 1516 reg = <0x0 0xf1010000 0 0x1000>,
1857 <0x0 0xf1020000 1517 <0x0 0xf1020000 0 0x20000>,
1858 <0x0 0xf1040000 1518 <0x0 0xf1040000 0 0x20000>,
1859 <0x0 0xf1060000 1519 <0x0 0xf1060000 0 0x20000>;
1860 interrupts = <GIC_PPI 1520 interrupts = <GIC_PPI 9
1861 (GIC_ 1521 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
1862 clocks = <&cpg CPG_MO 1522 clocks = <&cpg CPG_MOD 408>;
1863 clock-names = "clk"; 1523 clock-names = "clk";
1864 power-domains = <&sys 1524 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1865 resets = <&cpg 408>; 1525 resets = <&cpg 408>;
1866 }; 1526 };
1867 1527
1868 pciec0: pcie@fe000000 { <<
1869 compatible = "renesas <<
1870 "renesas <<
1871 reg = <0 0xfe000000 0 <<
1872 #address-cells = <3>; <<
1873 #size-cells = <2>; <<
1874 bus-range = <0x00 0xf <<
1875 device_type = "pci"; <<
1876 ranges = <0x01000000 <<
1877 <0x02000000 <<
1878 <0x02000000 <<
1879 <0x42000000 <<
1880 /* Map all possible D <<
1881 dma-ranges = <0x42000 <<
1882 interrupts = <GIC_SPI <<
1883 <GIC_SPI <<
1884 <GIC_SPI <<
1885 #interrupt-cells = <1 <<
1886 interrupt-map-mask = <<
1887 interrupt-map = <0 0 <<
1888 clocks = <&cpg CPG_MO <<
1889 clock-names = "pcie", <<
1890 power-domains = <&sys <<
1891 resets = <&cpg 319>; <<
1892 iommu-map = <0 &ipmmu <<
1893 iommu-map-mask = <0>; <<
1894 status = "disabled"; <<
1895 }; <<
1896 <<
1897 vspb0: vsp@fe960000 { 1528 vspb0: vsp@fe960000 {
1898 compatible = "renesas 1529 compatible = "renesas,vsp2";
1899 reg = <0 0xfe960000 0 1530 reg = <0 0xfe960000 0 0x8000>;
1900 interrupts = <GIC_SPI 1531 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
1901 clocks = <&cpg CPG_MO 1532 clocks = <&cpg CPG_MOD 626>;
1902 power-domains = <&sys 1533 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1903 resets = <&cpg 626>; 1534 resets = <&cpg 626>;
1904 renesas,fcp = <&fcpvb 1535 renesas,fcp = <&fcpvb0>;
1905 }; 1536 };
1906 1537
1907 fcpvb0: fcp@fe96f000 { 1538 fcpvb0: fcp@fe96f000 {
1908 compatible = "renesas 1539 compatible = "renesas,fcpv";
1909 reg = <0 0xfe96f000 0 1540 reg = <0 0xfe96f000 0 0x200>;
1910 clocks = <&cpg CPG_MO 1541 clocks = <&cpg CPG_MOD 607>;
1911 power-domains = <&sys 1542 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1912 resets = <&cpg 607>; 1543 resets = <&cpg 607>;
1913 iommus = <&ipmmu_vp0 1544 iommus = <&ipmmu_vp0 5>;
1914 }; 1545 };
1915 1546
1916 vspi0: vsp@fe9a0000 { 1547 vspi0: vsp@fe9a0000 {
1917 compatible = "renesas 1548 compatible = "renesas,vsp2";
1918 reg = <0 0xfe9a0000 0 1549 reg = <0 0xfe9a0000 0 0x8000>;
1919 interrupts = <GIC_SPI 1550 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
1920 clocks = <&cpg CPG_MO 1551 clocks = <&cpg CPG_MOD 631>;
1921 power-domains = <&sys 1552 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1922 resets = <&cpg 631>; 1553 resets = <&cpg 631>;
1923 renesas,fcp = <&fcpvi 1554 renesas,fcp = <&fcpvi0>;
1924 }; 1555 };
1925 1556
1926 fcpvi0: fcp@fe9af000 { 1557 fcpvi0: fcp@fe9af000 {
1927 compatible = "renesas 1558 compatible = "renesas,fcpv";
1928 reg = <0 0xfe9af000 0 1559 reg = <0 0xfe9af000 0 0x200>;
1929 clocks = <&cpg CPG_MO 1560 clocks = <&cpg CPG_MOD 611>;
1930 power-domains = <&sys 1561 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1931 resets = <&cpg 611>; 1562 resets = <&cpg 611>;
1932 iommus = <&ipmmu_vp0 1563 iommus = <&ipmmu_vp0 8>;
1933 }; 1564 };
1934 1565
1935 vspd0: vsp@fea20000 { 1566 vspd0: vsp@fea20000 {
1936 compatible = "renesas 1567 compatible = "renesas,vsp2";
1937 reg = <0 0xfea20000 0 1568 reg = <0 0xfea20000 0 0x7000>;
1938 interrupts = <GIC_SPI 1569 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
1939 clocks = <&cpg CPG_MO 1570 clocks = <&cpg CPG_MOD 623>;
1940 power-domains = <&sys 1571 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1941 resets = <&cpg 623>; 1572 resets = <&cpg 623>;
1942 renesas,fcp = <&fcpvd 1573 renesas,fcp = <&fcpvd0>;
1943 }; 1574 };
1944 1575
1945 fcpvd0: fcp@fea27000 { 1576 fcpvd0: fcp@fea27000 {
1946 compatible = "renesas 1577 compatible = "renesas,fcpv";
1947 reg = <0 0xfea27000 0 1578 reg = <0 0xfea27000 0 0x200>;
1948 clocks = <&cpg CPG_MO 1579 clocks = <&cpg CPG_MOD 603>;
1949 power-domains = <&sys 1580 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1950 resets = <&cpg 603>; 1581 resets = <&cpg 603>;
1951 iommus = <&ipmmu_vi0 1582 iommus = <&ipmmu_vi0 8>;
1952 }; 1583 };
1953 1584
1954 vspd1: vsp@fea28000 { 1585 vspd1: vsp@fea28000 {
1955 compatible = "renesas 1586 compatible = "renesas,vsp2";
1956 reg = <0 0xfea28000 0 1587 reg = <0 0xfea28000 0 0x7000>;
1957 interrupts = <GIC_SPI 1588 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
1958 clocks = <&cpg CPG_MO 1589 clocks = <&cpg CPG_MOD 622>;
1959 power-domains = <&sys 1590 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1960 resets = <&cpg 622>; 1591 resets = <&cpg 622>;
1961 renesas,fcp = <&fcpvd 1592 renesas,fcp = <&fcpvd1>;
1962 }; 1593 };
1963 1594
1964 fcpvd1: fcp@fea2f000 { 1595 fcpvd1: fcp@fea2f000 {
1965 compatible = "renesas 1596 compatible = "renesas,fcpv";
1966 reg = <0 0xfea2f000 0 1597 reg = <0 0xfea2f000 0 0x200>;
1967 clocks = <&cpg CPG_MO 1598 clocks = <&cpg CPG_MOD 602>;
1968 power-domains = <&sys 1599 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1969 resets = <&cpg 602>; 1600 resets = <&cpg 602>;
1970 iommus = <&ipmmu_vi0 1601 iommus = <&ipmmu_vi0 9>;
1971 }; 1602 };
1972 1603
1973 cmm0: cmm@fea40000 { <<
1974 compatible = "renesas <<
1975 "renesas <<
1976 reg = <0 0xfea40000 0 <<
1977 power-domains = <&sys <<
1978 clocks = <&cpg CPG_MO <<
1979 resets = <&cpg 711>; <<
1980 }; <<
1981 <<
1982 cmm1: cmm@fea50000 { <<
1983 compatible = "renesas <<
1984 "renesas <<
1985 reg = <0 0xfea50000 0 <<
1986 power-domains = <&sys <<
1987 clocks = <&cpg CPG_MO <<
1988 resets = <&cpg 710>; <<
1989 }; <<
1990 <<
1991 csi40: csi2@feaa0000 { 1604 csi40: csi2@feaa0000 {
1992 compatible = "renesas !! 1605 compatible = "renesas,r8a77990-csi2", "renesas,rcar-gen3-csi2";
1993 reg = <0 0xfeaa0000 0 1606 reg = <0 0xfeaa0000 0 0x10000>;
1994 interrupts = <GIC_SPI 1607 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
1995 clocks = <&cpg CPG_MO 1608 clocks = <&cpg CPG_MOD 716>;
1996 power-domains = <&sys 1609 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1997 resets = <&cpg 716>; 1610 resets = <&cpg 716>;
1998 status = "disabled"; 1611 status = "disabled";
1999 1612
2000 ports { 1613 ports {
2001 #address-cell 1614 #address-cells = <1>;
2002 #size-cells = 1615 #size-cells = <0>;
2003 1616
2004 port@0 { <<
2005 reg = <<
2006 }; <<
2007 <<
2008 port@1 { 1617 port@1 {
2009 #addr 1618 #address-cells = <1>;
2010 #size 1619 #size-cells = <0>;
2011 1620
2012 reg = 1621 reg = <1>;
2013 1622
2014 csi40 1623 csi40vin4: endpoint@0 {
2015 1624 reg = <0>;
2016 1625 remote-endpoint = <&vin4csi40>;
2017 }; 1626 };
2018 csi40 1627 csi40vin5: endpoint@1 {
2019 1628 reg = <1>;
2020 1629 remote-endpoint = <&vin5csi40>;
2021 }; 1630 };
2022 }; 1631 };
2023 }; 1632 };
2024 }; 1633 };
2025 1634
2026 du: display@feb00000 { 1635 du: display@feb00000 {
2027 compatible = "renesas 1636 compatible = "renesas,du-r8a77990";
2028 reg = <0 0xfeb00000 0 !! 1637 reg = <0 0xfeb00000 0 0x80000>;
2029 interrupts = <GIC_SPI 1638 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
2030 <GIC_SPI 1639 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
2031 clocks = <&cpg CPG_MO !! 1640 clocks = <&cpg CPG_MOD 724>,
>> 1641 <&cpg CPG_MOD 723>;
2032 clock-names = "du.0", 1642 clock-names = "du.0", "du.1";
2033 resets = <&cpg 724>; !! 1643 vsps = <&vspd0 0 &vspd1 0>;
2034 reset-names = "du.0"; <<
2035 <<
2036 renesas,cmms = <&cmm0 <<
2037 renesas,vsps = <&vspd <<
2038 <<
2039 status = "disabled"; 1644 status = "disabled";
2040 1645
2041 ports { 1646 ports {
2042 #address-cell 1647 #address-cells = <1>;
2043 #size-cells = 1648 #size-cells = <0>;
2044 1649
2045 port@0 { 1650 port@0 {
2046 reg = 1651 reg = <0>;
>> 1652 du_out_rgb: endpoint {
>> 1653 };
2047 }; 1654 };
2048 1655
2049 port@1 { 1656 port@1 {
2050 reg = 1657 reg = <1>;
2051 du_ou 1658 du_out_lvds0: endpoint {
2052 1659 remote-endpoint = <&lvds0_in>;
2053 }; 1660 };
2054 }; 1661 };
2055 1662
2056 port@2 { 1663 port@2 {
2057 reg = 1664 reg = <2>;
2058 du_ou 1665 du_out_lvds1: endpoint {
2059 1666 remote-endpoint = <&lvds1_in>;
2060 }; 1667 };
2061 }; 1668 };
2062 }; 1669 };
2063 }; 1670 };
2064 1671
2065 lvds0: lvds-encoder@feb90000 1672 lvds0: lvds-encoder@feb90000 {
2066 compatible = "renesas 1673 compatible = "renesas,r8a77990-lvds";
2067 reg = <0 0xfeb90000 0 1674 reg = <0 0xfeb90000 0 0x20>;
2068 clocks = <&cpg CPG_MO 1675 clocks = <&cpg CPG_MOD 727>;
2069 power-domains = <&sys 1676 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
2070 resets = <&cpg 727>; 1677 resets = <&cpg 727>;
2071 status = "disabled"; 1678 status = "disabled";
2072 1679
2073 renesas,companion = < <<
2074 <<
2075 ports { 1680 ports {
2076 #address-cell 1681 #address-cells = <1>;
2077 #size-cells = 1682 #size-cells = <0>;
2078 1683
2079 port@0 { 1684 port@0 {
2080 reg = 1685 reg = <0>;
2081 lvds0 1686 lvds0_in: endpoint {
2082 1687 remote-endpoint = <&du_out_lvds0>;
2083 }; 1688 };
2084 }; 1689 };
2085 1690
2086 port@1 { 1691 port@1 {
2087 reg = 1692 reg = <1>;
>> 1693 lvds0_out: endpoint {
>> 1694 };
2088 }; 1695 };
2089 }; 1696 };
2090 }; 1697 };
2091 1698
2092 lvds1: lvds-encoder@feb90100 1699 lvds1: lvds-encoder@feb90100 {
2093 compatible = "renesas 1700 compatible = "renesas,r8a77990-lvds";
2094 reg = <0 0xfeb90100 0 1701 reg = <0 0xfeb90100 0 0x20>;
2095 clocks = <&cpg CPG_MO 1702 clocks = <&cpg CPG_MOD 727>;
2096 power-domains = <&sys 1703 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
2097 resets = <&cpg 726>; 1704 resets = <&cpg 726>;
2098 status = "disabled"; 1705 status = "disabled";
2099 1706
2100 ports { 1707 ports {
2101 #address-cell 1708 #address-cells = <1>;
2102 #size-cells = 1709 #size-cells = <0>;
2103 1710
2104 port@0 { 1711 port@0 {
2105 reg = 1712 reg = <0>;
2106 lvds1 1713 lvds1_in: endpoint {
2107 1714 remote-endpoint = <&du_out_lvds1>;
2108 }; 1715 };
2109 }; 1716 };
2110 1717
2111 port@1 { 1718 port@1 {
2112 reg = 1719 reg = <1>;
>> 1720 lvds1_out: endpoint {
>> 1721 };
2113 }; 1722 };
2114 }; 1723 };
2115 }; 1724 };
2116 1725
>> 1726 pciec0: pcie@fe000000 {
>> 1727 compatible = "renesas,pcie-r8a77990",
>> 1728 "renesas,pcie-rcar-gen3";
>> 1729 reg = <0 0xfe000000 0 0x80000>;
>> 1730 #address-cells = <3>;
>> 1731 #size-cells = <2>;
>> 1732 bus-range = <0x00 0xff>;
>> 1733 device_type = "pci";
>> 1734 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
>> 1735 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
>> 1736 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
>> 1737 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
>> 1738 /* Map all possible DDR as inbound ranges */
>> 1739 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;
>> 1740 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
>> 1741 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
>> 1742 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
>> 1743 #interrupt-cells = <1>;
>> 1744 interrupt-map-mask = <0 0 0 0>;
>> 1745 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
>> 1746 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
>> 1747 clock-names = "pcie", "pcie_bus";
>> 1748 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
>> 1749 resets = <&cpg 319>;
>> 1750 status = "disabled";
>> 1751 };
>> 1752
2117 prr: chipid@fff00044 { 1753 prr: chipid@fff00044 {
2118 compatible = "renesas 1754 compatible = "renesas,prr";
2119 reg = <0 0xfff00044 0 1755 reg = <0 0xfff00044 0 4>;
2120 }; 1756 };
2121 }; 1757 };
2122 1758
2123 thermal-zones { 1759 thermal-zones {
2124 cpu-thermal { 1760 cpu-thermal {
2125 polling-delay-passive 1761 polling-delay-passive = <250>;
2126 polling-delay = <0>; !! 1762 polling-delay = <1000>;
2127 thermal-sensors = <&t 1763 thermal-sensors = <&thermal>;
2128 sustainable-power = < <<
2129 <<
2130 cooling-maps { <<
2131 map0 { <<
2132 trip <<
2133 cooli <<
2134 contr <<
2135 }; <<
2136 }; <<
2137 1764
2138 trips { 1765 trips {
2139 sensor1_crit: !! 1766 cpu-crit {
2140 tempe 1767 temperature = <120000>;
2141 hyste 1768 hysteresis = <2000>;
2142 type 1769 type = "critical";
2143 }; 1770 };
>> 1771 };
2144 1772
2145 target: trip- !! 1773 cooling-maps {
2146 tempe <<
2147 hyste <<
2148 type <<
2149 }; <<
2150 }; 1774 };
2151 }; 1775 };
2152 }; 1776 };
2153 1777
2154 timer { 1778 timer {
2155 compatible = "arm,armv8-timer 1779 compatible = "arm,armv8-timer";
2156 interrupts-extended = <&gic G 1780 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
2157 <&gic G 1781 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
2158 <&gic G 1782 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
2159 <&gic G 1783 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
2160 interrupt-names = "sec-phys", <<
2161 }; 1784 };
2162 }; 1785 };
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