1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * Device Tree Source for the R-Car E3 (R8A779 3 * Device Tree Source for the R-Car E3 (R8A77990) SoC
4 * 4 *
5 * Copyright (C) 2018-2019 Renesas Electronics 5 * Copyright (C) 2018-2019 Renesas Electronics Corp.
6 */ 6 */
7 7
8 #include <dt-bindings/clock/r8a77990-cpg-mssr. 8 #include <dt-bindings/clock/r8a77990-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm 9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a77990-sysc.h> 10 #include <dt-bindings/power/r8a77990-sysc.h>
11 11
12 / { 12 / {
13 compatible = "renesas,r8a77990"; 13 compatible = "renesas,r8a77990";
14 #address-cells = <2>; 14 #address-cells = <2>;
15 #size-cells = <2>; 15 #size-cells = <2>;
16 16
>> 17 aliases {
>> 18 i2c0 = &i2c0;
>> 19 i2c1 = &i2c1;
>> 20 i2c2 = &i2c2;
>> 21 i2c3 = &i2c3;
>> 22 i2c4 = &i2c4;
>> 23 i2c5 = &i2c5;
>> 24 i2c6 = &i2c6;
>> 25 i2c7 = &i2c7;
>> 26 };
>> 27
17 /* 28 /*
18 * The external audio clocks are confi 29 * The external audio clocks are configured as 0 Hz fixed frequency
19 * clocks by default. 30 * clocks by default.
20 * Boards that provide audio clocks sh 31 * Boards that provide audio clocks should override them.
21 */ 32 */
22 audio_clk_a: audio_clk_a { 33 audio_clk_a: audio_clk_a {
23 compatible = "fixed-clock"; 34 compatible = "fixed-clock";
24 #clock-cells = <0>; 35 #clock-cells = <0>;
25 clock-frequency = <0>; 36 clock-frequency = <0>;
26 }; 37 };
27 38
28 audio_clk_b: audio_clk_b { 39 audio_clk_b: audio_clk_b {
29 compatible = "fixed-clock"; 40 compatible = "fixed-clock";
30 #clock-cells = <0>; 41 #clock-cells = <0>;
31 clock-frequency = <0>; 42 clock-frequency = <0>;
32 }; 43 };
33 44
34 audio_clk_c: audio_clk_c { 45 audio_clk_c: audio_clk_c {
35 compatible = "fixed-clock"; 46 compatible = "fixed-clock";
36 #clock-cells = <0>; 47 #clock-cells = <0>;
37 clock-frequency = <0>; 48 clock-frequency = <0>;
38 }; 49 };
39 50
40 /* External CAN clock - to be overridd 51 /* External CAN clock - to be overridden by boards that provide it */
41 can_clk: can { 52 can_clk: can {
42 compatible = "fixed-clock"; 53 compatible = "fixed-clock";
43 #clock-cells = <0>; 54 #clock-cells = <0>;
44 clock-frequency = <0>; 55 clock-frequency = <0>;
45 }; 56 };
46 57
47 cluster1_opp: opp-table-1 { !! 58 cluster1_opp: opp_table10 {
48 compatible = "operating-points 59 compatible = "operating-points-v2";
49 opp-shared; 60 opp-shared;
50 opp-800000000 { 61 opp-800000000 {
51 opp-hz = /bits/ 64 <80 62 opp-hz = /bits/ 64 <800000000>;
52 clock-latency-ns = <30 63 clock-latency-ns = <300000>;
53 }; 64 };
54 opp-1000000000 { 65 opp-1000000000 {
55 opp-hz = /bits/ 64 <10 66 opp-hz = /bits/ 64 <1000000000>;
56 clock-latency-ns = <30 67 clock-latency-ns = <300000>;
57 }; 68 };
58 opp-1200000000 { 69 opp-1200000000 {
59 opp-hz = /bits/ 64 <12 70 opp-hz = /bits/ 64 <1200000000>;
60 clock-latency-ns = <30 71 clock-latency-ns = <300000>;
61 opp-suspend; 72 opp-suspend;
62 }; 73 };
63 }; 74 };
64 75
65 cpus { 76 cpus {
66 #address-cells = <1>; 77 #address-cells = <1>;
67 #size-cells = <0>; 78 #size-cells = <0>;
68 79
69 a53_0: cpu@0 { 80 a53_0: cpu@0 {
70 compatible = "arm,cort 81 compatible = "arm,cortex-a53";
71 reg = <0>; 82 reg = <0>;
72 device_type = "cpu"; 83 device_type = "cpu";
73 #cooling-cells = <2>; 84 #cooling-cells = <2>;
74 power-domains = <&sysc 85 power-domains = <&sysc R8A77990_PD_CA53_CPU0>;
75 next-level-cache = <&L 86 next-level-cache = <&L2_CA53>;
76 enable-method = "psci" 87 enable-method = "psci";
77 cpu-idle-states = <&CP 88 cpu-idle-states = <&CPU_SLEEP_0>;
78 dynamic-power-coeffici 89 dynamic-power-coefficient = <277>;
79 clocks = <&cpg CPG_COR !! 90 clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>;
80 operating-points-v2 = 91 operating-points-v2 = <&cluster1_opp>;
81 }; 92 };
82 93
83 a53_1: cpu@1 { 94 a53_1: cpu@1 {
84 compatible = "arm,cort 95 compatible = "arm,cortex-a53";
85 reg = <1>; 96 reg = <1>;
86 device_type = "cpu"; 97 device_type = "cpu";
87 power-domains = <&sysc 98 power-domains = <&sysc R8A77990_PD_CA53_CPU1>;
88 next-level-cache = <&L 99 next-level-cache = <&L2_CA53>;
89 enable-method = "psci" 100 enable-method = "psci";
90 cpu-idle-states = <&CP 101 cpu-idle-states = <&CPU_SLEEP_0>;
91 clocks = <&cpg CPG_COR !! 102 clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>;
92 operating-points-v2 = 103 operating-points-v2 = <&cluster1_opp>;
93 }; 104 };
94 105
95 L2_CA53: cache-controller-0 { 106 L2_CA53: cache-controller-0 {
96 compatible = "cache"; 107 compatible = "cache";
97 power-domains = <&sysc 108 power-domains = <&sysc R8A77990_PD_CA53_SCU>;
98 cache-unified; 109 cache-unified;
99 cache-level = <2>; 110 cache-level = <2>;
100 }; 111 };
101 112
102 idle-states { 113 idle-states {
103 entry-method = "psci"; 114 entry-method = "psci";
104 115
105 CPU_SLEEP_0: cpu-sleep 116 CPU_SLEEP_0: cpu-sleep-0 {
106 compatible = " 117 compatible = "arm,idle-state";
107 arm,psci-suspe 118 arm,psci-suspend-param = <0x0010000>;
108 local-timer-st 119 local-timer-stop;
109 entry-latency- 120 entry-latency-us = <700>;
110 exit-latency-u 121 exit-latency-us = <700>;
111 min-residency- 122 min-residency-us = <5000>;
112 }; 123 };
113 }; 124 };
114 }; 125 };
115 126
116 extal_clk: extal { 127 extal_clk: extal {
117 compatible = "fixed-clock"; 128 compatible = "fixed-clock";
118 #clock-cells = <0>; 129 #clock-cells = <0>;
119 /* This value must be overridd 130 /* This value must be overridden by the board */
120 clock-frequency = <0>; 131 clock-frequency = <0>;
121 }; 132 };
122 133
123 /* External PCIe clock - can be overri 134 /* External PCIe clock - can be overridden by the board */
124 pcie_bus_clk: pcie_bus { 135 pcie_bus_clk: pcie_bus {
125 compatible = "fixed-clock"; 136 compatible = "fixed-clock";
126 #clock-cells = <0>; 137 #clock-cells = <0>;
127 clock-frequency = <0>; 138 clock-frequency = <0>;
128 }; 139 };
129 140
130 pmu_a53 { 141 pmu_a53 {
131 compatible = "arm,cortex-a53-p 142 compatible = "arm,cortex-a53-pmu";
132 interrupts-extended = <&gic GI 143 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
133 <&gic GI 144 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
134 interrupt-affinity = <&a53_0>, 145 interrupt-affinity = <&a53_0>, <&a53_1>;
135 }; 146 };
136 147
137 psci { 148 psci {
138 compatible = "arm,psci-1.0", " 149 compatible = "arm,psci-1.0", "arm,psci-0.2";
139 method = "smc"; 150 method = "smc";
140 }; 151 };
141 152
142 /* External SCIF clock - to be overrid 153 /* External SCIF clock - to be overridden by boards that provide it */
143 scif_clk: scif { 154 scif_clk: scif {
144 compatible = "fixed-clock"; 155 compatible = "fixed-clock";
145 #clock-cells = <0>; 156 #clock-cells = <0>;
146 clock-frequency = <0>; 157 clock-frequency = <0>;
147 }; 158 };
148 159
149 soc: soc { 160 soc: soc {
150 compatible = "simple-bus"; 161 compatible = "simple-bus";
151 interrupt-parent = <&gic>; 162 interrupt-parent = <&gic>;
152 #address-cells = <2>; 163 #address-cells = <2>;
153 #size-cells = <2>; 164 #size-cells = <2>;
154 ranges; 165 ranges;
155 166
156 rwdt: watchdog@e6020000 { 167 rwdt: watchdog@e6020000 {
157 compatible = "renesas, 168 compatible = "renesas,r8a77990-wdt",
158 "renesas, 169 "renesas,rcar-gen3-wdt";
159 reg = <0 0xe6020000 0 170 reg = <0 0xe6020000 0 0x0c>;
160 interrupts = <GIC_SPI <<
161 clocks = <&cpg CPG_MOD 171 clocks = <&cpg CPG_MOD 402>;
162 power-domains = <&sysc 172 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
163 resets = <&cpg 402>; 173 resets = <&cpg 402>;
164 status = "disabled"; 174 status = "disabled";
165 }; 175 };
166 176
167 gpio0: gpio@e6050000 { 177 gpio0: gpio@e6050000 {
168 compatible = "renesas, 178 compatible = "renesas,gpio-r8a77990",
169 "renesas, 179 "renesas,rcar-gen3-gpio";
170 reg = <0 0xe6050000 0 180 reg = <0 0xe6050000 0 0x50>;
171 interrupts = <GIC_SPI 181 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
172 #gpio-cells = <2>; 182 #gpio-cells = <2>;
173 gpio-controller; 183 gpio-controller;
174 gpio-ranges = <&pfc 0 184 gpio-ranges = <&pfc 0 0 18>;
175 #interrupt-cells = <2> 185 #interrupt-cells = <2>;
176 interrupt-controller; 186 interrupt-controller;
177 clocks = <&cpg CPG_MOD 187 clocks = <&cpg CPG_MOD 912>;
178 power-domains = <&sysc 188 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
179 resets = <&cpg 912>; 189 resets = <&cpg 912>;
180 }; 190 };
181 191
182 gpio1: gpio@e6051000 { 192 gpio1: gpio@e6051000 {
183 compatible = "renesas, 193 compatible = "renesas,gpio-r8a77990",
184 "renesas, 194 "renesas,rcar-gen3-gpio";
185 reg = <0 0xe6051000 0 195 reg = <0 0xe6051000 0 0x50>;
186 interrupts = <GIC_SPI 196 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
187 #gpio-cells = <2>; 197 #gpio-cells = <2>;
188 gpio-controller; 198 gpio-controller;
189 gpio-ranges = <&pfc 0 199 gpio-ranges = <&pfc 0 32 23>;
190 #interrupt-cells = <2> 200 #interrupt-cells = <2>;
191 interrupt-controller; 201 interrupt-controller;
192 clocks = <&cpg CPG_MOD 202 clocks = <&cpg CPG_MOD 911>;
193 power-domains = <&sysc 203 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
194 resets = <&cpg 911>; 204 resets = <&cpg 911>;
195 }; 205 };
196 206
197 gpio2: gpio@e6052000 { 207 gpio2: gpio@e6052000 {
198 compatible = "renesas, 208 compatible = "renesas,gpio-r8a77990",
199 "renesas, 209 "renesas,rcar-gen3-gpio";
200 reg = <0 0xe6052000 0 210 reg = <0 0xe6052000 0 0x50>;
201 interrupts = <GIC_SPI 211 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
202 #gpio-cells = <2>; 212 #gpio-cells = <2>;
203 gpio-controller; 213 gpio-controller;
204 gpio-ranges = <&pfc 0 214 gpio-ranges = <&pfc 0 64 26>;
205 #interrupt-cells = <2> 215 #interrupt-cells = <2>;
206 interrupt-controller; 216 interrupt-controller;
207 clocks = <&cpg CPG_MOD 217 clocks = <&cpg CPG_MOD 910>;
208 power-domains = <&sysc 218 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
209 resets = <&cpg 910>; 219 resets = <&cpg 910>;
210 }; 220 };
211 221
212 gpio3: gpio@e6053000 { 222 gpio3: gpio@e6053000 {
213 compatible = "renesas, 223 compatible = "renesas,gpio-r8a77990",
214 "renesas, 224 "renesas,rcar-gen3-gpio";
215 reg = <0 0xe6053000 0 225 reg = <0 0xe6053000 0 0x50>;
216 interrupts = <GIC_SPI 226 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
217 #gpio-cells = <2>; 227 #gpio-cells = <2>;
218 gpio-controller; 228 gpio-controller;
219 gpio-ranges = <&pfc 0 229 gpio-ranges = <&pfc 0 96 16>;
220 #interrupt-cells = <2> 230 #interrupt-cells = <2>;
221 interrupt-controller; 231 interrupt-controller;
222 clocks = <&cpg CPG_MOD 232 clocks = <&cpg CPG_MOD 909>;
223 power-domains = <&sysc 233 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
224 resets = <&cpg 909>; 234 resets = <&cpg 909>;
225 }; 235 };
226 236
227 gpio4: gpio@e6054000 { 237 gpio4: gpio@e6054000 {
228 compatible = "renesas, 238 compatible = "renesas,gpio-r8a77990",
229 "renesas, 239 "renesas,rcar-gen3-gpio";
230 reg = <0 0xe6054000 0 240 reg = <0 0xe6054000 0 0x50>;
231 interrupts = <GIC_SPI 241 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
232 #gpio-cells = <2>; 242 #gpio-cells = <2>;
233 gpio-controller; 243 gpio-controller;
234 gpio-ranges = <&pfc 0 244 gpio-ranges = <&pfc 0 128 11>;
235 #interrupt-cells = <2> 245 #interrupt-cells = <2>;
236 interrupt-controller; 246 interrupt-controller;
237 clocks = <&cpg CPG_MOD 247 clocks = <&cpg CPG_MOD 908>;
238 power-domains = <&sysc 248 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
239 resets = <&cpg 908>; 249 resets = <&cpg 908>;
240 }; 250 };
241 251
242 gpio5: gpio@e6055000 { 252 gpio5: gpio@e6055000 {
243 compatible = "renesas, 253 compatible = "renesas,gpio-r8a77990",
244 "renesas, 254 "renesas,rcar-gen3-gpio";
245 reg = <0 0xe6055000 0 255 reg = <0 0xe6055000 0 0x50>;
246 interrupts = <GIC_SPI 256 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
247 #gpio-cells = <2>; 257 #gpio-cells = <2>;
248 gpio-controller; 258 gpio-controller;
249 gpio-ranges = <&pfc 0 259 gpio-ranges = <&pfc 0 160 20>;
250 #interrupt-cells = <2> 260 #interrupt-cells = <2>;
251 interrupt-controller; 261 interrupt-controller;
252 clocks = <&cpg CPG_MOD 262 clocks = <&cpg CPG_MOD 907>;
253 power-domains = <&sysc 263 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
254 resets = <&cpg 907>; 264 resets = <&cpg 907>;
255 }; 265 };
256 266
257 gpio6: gpio@e6055400 { 267 gpio6: gpio@e6055400 {
258 compatible = "renesas, 268 compatible = "renesas,gpio-r8a77990",
259 "renesas, 269 "renesas,rcar-gen3-gpio";
260 reg = <0 0xe6055400 0 270 reg = <0 0xe6055400 0 0x50>;
261 interrupts = <GIC_SPI 271 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
262 #gpio-cells = <2>; 272 #gpio-cells = <2>;
263 gpio-controller; 273 gpio-controller;
264 gpio-ranges = <&pfc 0 274 gpio-ranges = <&pfc 0 192 18>;
265 #interrupt-cells = <2> 275 #interrupt-cells = <2>;
266 interrupt-controller; 276 interrupt-controller;
267 clocks = <&cpg CPG_MOD 277 clocks = <&cpg CPG_MOD 906>;
268 power-domains = <&sysc 278 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
269 resets = <&cpg 906>; 279 resets = <&cpg 906>;
270 }; 280 };
271 281
272 pfc: pinctrl@e6060000 { 282 pfc: pinctrl@e6060000 {
273 compatible = "renesas, 283 compatible = "renesas,pfc-r8a77990";
274 reg = <0 0xe6060000 0 284 reg = <0 0xe6060000 0 0x508>;
275 }; 285 };
276 286
277 i2c_dvfs: i2c@e60b0000 { 287 i2c_dvfs: i2c@e60b0000 {
278 #address-cells = <1>; 288 #address-cells = <1>;
279 #size-cells = <0>; 289 #size-cells = <0>;
280 compatible = "renesas, !! 290 compatible = "renesas,iic-r8a77990";
281 "renesas, !! 291 reg = <0 0xe60b0000 0 0x15>;
282 "renesas, <<
283 reg = <0 0xe60b0000 0 <<
284 interrupts = <GIC_SPI 292 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
285 clocks = <&cpg CPG_MOD 293 clocks = <&cpg CPG_MOD 926>;
286 power-domains = <&sysc 294 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
287 resets = <&cpg 926>; 295 resets = <&cpg 926>;
288 dmas = <&dmac0 0x11>, 296 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
289 dma-names = "tx", "rx" 297 dma-names = "tx", "rx";
290 status = "disabled"; 298 status = "disabled";
291 }; 299 };
292 300
293 cmt0: timer@e60f0000 { 301 cmt0: timer@e60f0000 {
294 compatible = "renesas, 302 compatible = "renesas,r8a77990-cmt0",
295 "renesas, 303 "renesas,rcar-gen3-cmt0";
296 reg = <0 0xe60f0000 0 304 reg = <0 0xe60f0000 0 0x1004>;
297 interrupts = <GIC_SPI 305 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
298 <GIC_SPI 306 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
299 clocks = <&cpg CPG_MOD 307 clocks = <&cpg CPG_MOD 303>;
300 clock-names = "fck"; 308 clock-names = "fck";
301 power-domains = <&sysc 309 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
302 resets = <&cpg 303>; 310 resets = <&cpg 303>;
303 status = "disabled"; 311 status = "disabled";
304 }; 312 };
305 313
306 cmt1: timer@e6130000 { 314 cmt1: timer@e6130000 {
307 compatible = "renesas, 315 compatible = "renesas,r8a77990-cmt1",
308 "renesas, 316 "renesas,rcar-gen3-cmt1";
309 reg = <0 0xe6130000 0 317 reg = <0 0xe6130000 0 0x1004>;
310 interrupts = <GIC_SPI 318 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
311 <GIC_SPI 319 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
312 <GIC_SPI 320 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
313 <GIC_SPI 321 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
314 <GIC_SPI 322 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
315 <GIC_SPI 323 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
316 <GIC_SPI 324 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
317 <GIC_SPI 325 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
318 clocks = <&cpg CPG_MOD 326 clocks = <&cpg CPG_MOD 302>;
319 clock-names = "fck"; 327 clock-names = "fck";
320 power-domains = <&sysc 328 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
321 resets = <&cpg 302>; 329 resets = <&cpg 302>;
322 status = "disabled"; 330 status = "disabled";
323 }; 331 };
324 332
325 cmt2: timer@e6140000 { 333 cmt2: timer@e6140000 {
326 compatible = "renesas, 334 compatible = "renesas,r8a77990-cmt1",
327 "renesas, 335 "renesas,rcar-gen3-cmt1";
328 reg = <0 0xe6140000 0 336 reg = <0 0xe6140000 0 0x1004>;
329 interrupts = <GIC_SPI 337 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
330 <GIC_SPI 338 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
331 <GIC_SPI 339 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
332 <GIC_SPI 340 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
333 <GIC_SPI 341 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
334 <GIC_SPI 342 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
335 <GIC_SPI 343 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
336 <GIC_SPI 344 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
337 clocks = <&cpg CPG_MOD 345 clocks = <&cpg CPG_MOD 301>;
338 clock-names = "fck"; 346 clock-names = "fck";
339 power-domains = <&sysc 347 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
340 resets = <&cpg 301>; 348 resets = <&cpg 301>;
341 status = "disabled"; 349 status = "disabled";
342 }; 350 };
343 351
344 cmt3: timer@e6148000 { 352 cmt3: timer@e6148000 {
345 compatible = "renesas, 353 compatible = "renesas,r8a77990-cmt1",
346 "renesas, 354 "renesas,rcar-gen3-cmt1";
347 reg = <0 0xe6148000 0 355 reg = <0 0xe6148000 0 0x1004>;
348 interrupts = <GIC_SPI 356 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
349 <GIC_SPI 357 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
350 <GIC_SPI 358 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
351 <GIC_SPI 359 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
352 <GIC_SPI 360 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
353 <GIC_SPI 361 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
354 <GIC_SPI 362 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
355 <GIC_SPI 363 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
356 clocks = <&cpg CPG_MOD 364 clocks = <&cpg CPG_MOD 300>;
357 clock-names = "fck"; 365 clock-names = "fck";
358 power-domains = <&sysc 366 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
359 resets = <&cpg 300>; 367 resets = <&cpg 300>;
360 status = "disabled"; 368 status = "disabled";
361 }; 369 };
362 370
363 cpg: clock-controller@e6150000 371 cpg: clock-controller@e6150000 {
364 compatible = "renesas, 372 compatible = "renesas,r8a77990-cpg-mssr";
365 reg = <0 0xe6150000 0 373 reg = <0 0xe6150000 0 0x1000>;
366 clocks = <&extal_clk>; 374 clocks = <&extal_clk>;
367 clock-names = "extal"; 375 clock-names = "extal";
368 #clock-cells = <2>; 376 #clock-cells = <2>;
369 #power-domain-cells = 377 #power-domain-cells = <0>;
370 #reset-cells = <1>; 378 #reset-cells = <1>;
371 }; 379 };
372 380
373 rst: reset-controller@e6160000 381 rst: reset-controller@e6160000 {
374 compatible = "renesas, 382 compatible = "renesas,r8a77990-rst";
375 reg = <0 0xe6160000 0 383 reg = <0 0xe6160000 0 0x0200>;
376 }; 384 };
377 385
378 sysc: system-controller@e61800 386 sysc: system-controller@e6180000 {
379 compatible = "renesas, 387 compatible = "renesas,r8a77990-sysc";
380 reg = <0 0xe6180000 0 388 reg = <0 0xe6180000 0 0x0400>;
381 #power-domain-cells = 389 #power-domain-cells = <1>;
382 }; 390 };
383 391
384 thermal: thermal@e6190000 { 392 thermal: thermal@e6190000 {
385 compatible = "renesas, 393 compatible = "renesas,thermal-r8a77990";
386 reg = <0 0xe6190000 0 394 reg = <0 0xe6190000 0 0x10>, <0 0xe6190100 0 0x38>;
387 interrupts = <GIC_SPI 395 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
388 <GIC_SPI 396 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
389 <GIC_SPI 397 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
390 clocks = <&cpg CPG_MOD 398 clocks = <&cpg CPG_MOD 522>;
391 power-domains = <&sysc 399 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
392 resets = <&cpg 522>; 400 resets = <&cpg 522>;
393 #thermal-sensor-cells 401 #thermal-sensor-cells = <0>;
394 }; 402 };
395 403
396 intc_ex: interrupt-controller@ 404 intc_ex: interrupt-controller@e61c0000 {
397 compatible = "renesas, 405 compatible = "renesas,intc-ex-r8a77990", "renesas,irqc";
398 #interrupt-cells = <2> 406 #interrupt-cells = <2>;
399 interrupt-controller; 407 interrupt-controller;
400 reg = <0 0xe61c0000 0 408 reg = <0 0xe61c0000 0 0x200>;
401 interrupts = <GIC_SPI 409 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
402 <GIC_SPI 410 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
403 <GIC_SPI 411 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
404 <GIC_SPI 412 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
405 <GIC_SPI 413 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
406 <GIC_SPI 414 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
407 clocks = <&cpg CPG_MOD 415 clocks = <&cpg CPG_MOD 407>;
408 power-domains = <&sysc 416 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
409 resets = <&cpg 407>; 417 resets = <&cpg 407>;
410 }; 418 };
411 419
412 tmu0: timer@e61e0000 { <<
413 compatible = "renesas, <<
414 reg = <0 0xe61e0000 0 <<
415 interrupts = <GIC_SPI <<
416 <GIC_SPI <<
417 <GIC_SPI <<
418 interrupt-names = "tun <<
419 clocks = <&cpg CPG_MOD <<
420 clock-names = "fck"; <<
421 power-domains = <&sysc <<
422 resets = <&cpg 125>; <<
423 status = "disabled"; <<
424 }; <<
425 <<
426 tmu1: timer@e6fc0000 { <<
427 compatible = "renesas, <<
428 reg = <0 0xe6fc0000 0 <<
429 interrupts = <GIC_SPI <<
430 <GIC_SPI <<
431 <GIC_SPI <<
432 <GIC_SPI <<
433 interrupt-names = "tun <<
434 clocks = <&cpg CPG_MOD <<
435 clock-names = "fck"; <<
436 power-domains = <&sysc <<
437 resets = <&cpg 124>; <<
438 status = "disabled"; <<
439 }; <<
440 <<
441 tmu2: timer@e6fd0000 { <<
442 compatible = "renesas, <<
443 reg = <0 0xe6fd0000 0 <<
444 interrupts = <GIC_SPI <<
445 <GIC_SPI <<
446 <GIC_SPI <<
447 <GIC_SPI <<
448 interrupt-names = "tun <<
449 clocks = <&cpg CPG_MOD <<
450 clock-names = "fck"; <<
451 power-domains = <&sysc <<
452 resets = <&cpg 123>; <<
453 status = "disabled"; <<
454 }; <<
455 <<
456 tmu3: timer@e6fe0000 { <<
457 compatible = "renesas, <<
458 reg = <0 0xe6fe0000 0 <<
459 interrupts = <GIC_SPI <<
460 <GIC_SPI <<
461 <GIC_SPI <<
462 interrupt-names = "tun <<
463 clocks = <&cpg CPG_MOD <<
464 clock-names = "fck"; <<
465 power-domains = <&sysc <<
466 resets = <&cpg 122>; <<
467 status = "disabled"; <<
468 }; <<
469 <<
470 tmu4: timer@ffc00000 { <<
471 compatible = "renesas, <<
472 reg = <0 0xffc00000 0 <<
473 interrupts = <GIC_SPI <<
474 <GIC_SPI <<
475 <GIC_SPI <<
476 interrupt-names = "tun <<
477 clocks = <&cpg CPG_MOD <<
478 clock-names = "fck"; <<
479 power-domains = <&sysc <<
480 resets = <&cpg 121>; <<
481 status = "disabled"; <<
482 }; <<
483 <<
484 i2c0: i2c@e6500000 { 420 i2c0: i2c@e6500000 {
485 #address-cells = <1>; 421 #address-cells = <1>;
486 #size-cells = <0>; 422 #size-cells = <0>;
487 compatible = "renesas, 423 compatible = "renesas,i2c-r8a77990",
488 "renesas, 424 "renesas,rcar-gen3-i2c";
489 reg = <0 0xe6500000 0 425 reg = <0 0xe6500000 0 0x40>;
490 interrupts = <GIC_SPI 426 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
491 clocks = <&cpg CPG_MOD 427 clocks = <&cpg CPG_MOD 931>;
492 power-domains = <&sysc 428 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
493 resets = <&cpg 931>; 429 resets = <&cpg 931>;
494 dmas = <&dmac1 0x91>, 430 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
495 <&dmac2 0x91>, 431 <&dmac2 0x91>, <&dmac2 0x90>;
496 dma-names = "tx", "rx" 432 dma-names = "tx", "rx", "tx", "rx";
497 i2c-scl-internal-delay 433 i2c-scl-internal-delay-ns = <110>;
498 status = "disabled"; 434 status = "disabled";
499 }; 435 };
500 436
501 i2c1: i2c@e6508000 { 437 i2c1: i2c@e6508000 {
502 #address-cells = <1>; 438 #address-cells = <1>;
503 #size-cells = <0>; 439 #size-cells = <0>;
504 compatible = "renesas, 440 compatible = "renesas,i2c-r8a77990",
505 "renesas, 441 "renesas,rcar-gen3-i2c";
506 reg = <0 0xe6508000 0 442 reg = <0 0xe6508000 0 0x40>;
507 interrupts = <GIC_SPI 443 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
508 clocks = <&cpg CPG_MOD 444 clocks = <&cpg CPG_MOD 930>;
509 power-domains = <&sysc 445 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
510 resets = <&cpg 930>; 446 resets = <&cpg 930>;
511 dmas = <&dmac1 0x93>, 447 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
512 <&dmac2 0x93>, 448 <&dmac2 0x93>, <&dmac2 0x92>;
513 dma-names = "tx", "rx" 449 dma-names = "tx", "rx", "tx", "rx";
514 i2c-scl-internal-delay 450 i2c-scl-internal-delay-ns = <6>;
515 status = "disabled"; 451 status = "disabled";
516 }; 452 };
517 453
518 i2c2: i2c@e6510000 { 454 i2c2: i2c@e6510000 {
519 #address-cells = <1>; 455 #address-cells = <1>;
520 #size-cells = <0>; 456 #size-cells = <0>;
521 compatible = "renesas, 457 compatible = "renesas,i2c-r8a77990",
522 "renesas, 458 "renesas,rcar-gen3-i2c";
523 reg = <0 0xe6510000 0 459 reg = <0 0xe6510000 0 0x40>;
524 interrupts = <GIC_SPI 460 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
525 clocks = <&cpg CPG_MOD 461 clocks = <&cpg CPG_MOD 929>;
526 power-domains = <&sysc 462 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
527 resets = <&cpg 929>; 463 resets = <&cpg 929>;
528 dmas = <&dmac1 0x95>, 464 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
529 <&dmac2 0x95>, 465 <&dmac2 0x95>, <&dmac2 0x94>;
530 dma-names = "tx", "rx" 466 dma-names = "tx", "rx", "tx", "rx";
531 i2c-scl-internal-delay 467 i2c-scl-internal-delay-ns = <6>;
532 status = "disabled"; 468 status = "disabled";
533 }; 469 };
534 470
535 i2c3: i2c@e66d0000 { 471 i2c3: i2c@e66d0000 {
536 #address-cells = <1>; 472 #address-cells = <1>;
537 #size-cells = <0>; 473 #size-cells = <0>;
538 compatible = "renesas, 474 compatible = "renesas,i2c-r8a77990",
539 "renesas, 475 "renesas,rcar-gen3-i2c";
540 reg = <0 0xe66d0000 0 476 reg = <0 0xe66d0000 0 0x40>;
541 interrupts = <GIC_SPI 477 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
542 clocks = <&cpg CPG_MOD 478 clocks = <&cpg CPG_MOD 928>;
543 power-domains = <&sysc 479 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
544 resets = <&cpg 928>; 480 resets = <&cpg 928>;
545 dmas = <&dmac0 0x97>, 481 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
546 dma-names = "tx", "rx" 482 dma-names = "tx", "rx";
547 i2c-scl-internal-delay 483 i2c-scl-internal-delay-ns = <110>;
548 status = "disabled"; 484 status = "disabled";
549 }; 485 };
550 486
551 i2c4: i2c@e66d8000 { 487 i2c4: i2c@e66d8000 {
552 #address-cells = <1>; 488 #address-cells = <1>;
553 #size-cells = <0>; 489 #size-cells = <0>;
554 compatible = "renesas, 490 compatible = "renesas,i2c-r8a77990",
555 "renesas, 491 "renesas,rcar-gen3-i2c";
556 reg = <0 0xe66d8000 0 492 reg = <0 0xe66d8000 0 0x40>;
557 interrupts = <GIC_SPI 493 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
558 clocks = <&cpg CPG_MOD 494 clocks = <&cpg CPG_MOD 927>;
559 power-domains = <&sysc 495 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
560 resets = <&cpg 927>; 496 resets = <&cpg 927>;
561 dmas = <&dmac0 0x99>, 497 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
562 dma-names = "tx", "rx" 498 dma-names = "tx", "rx";
563 i2c-scl-internal-delay 499 i2c-scl-internal-delay-ns = <6>;
564 status = "disabled"; 500 status = "disabled";
565 }; 501 };
566 502
567 i2c5: i2c@e66e0000 { 503 i2c5: i2c@e66e0000 {
568 #address-cells = <1>; 504 #address-cells = <1>;
569 #size-cells = <0>; 505 #size-cells = <0>;
570 compatible = "renesas, 506 compatible = "renesas,i2c-r8a77990",
571 "renesas, 507 "renesas,rcar-gen3-i2c";
572 reg = <0 0xe66e0000 0 508 reg = <0 0xe66e0000 0 0x40>;
573 interrupts = <GIC_SPI 509 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
574 clocks = <&cpg CPG_MOD 510 clocks = <&cpg CPG_MOD 919>;
575 power-domains = <&sysc 511 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
576 resets = <&cpg 919>; 512 resets = <&cpg 919>;
577 dmas = <&dmac0 0x9b>, 513 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
578 dma-names = "tx", "rx" 514 dma-names = "tx", "rx";
579 i2c-scl-internal-delay 515 i2c-scl-internal-delay-ns = <6>;
580 status = "disabled"; 516 status = "disabled";
581 }; 517 };
582 518
583 i2c6: i2c@e66e8000 { 519 i2c6: i2c@e66e8000 {
584 #address-cells = <1>; 520 #address-cells = <1>;
585 #size-cells = <0>; 521 #size-cells = <0>;
586 compatible = "renesas, 522 compatible = "renesas,i2c-r8a77990",
587 "renesas, 523 "renesas,rcar-gen3-i2c";
588 reg = <0 0xe66e8000 0 524 reg = <0 0xe66e8000 0 0x40>;
589 interrupts = <GIC_SPI 525 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
590 clocks = <&cpg CPG_MOD 526 clocks = <&cpg CPG_MOD 918>;
591 power-domains = <&sysc 527 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
592 resets = <&cpg 918>; 528 resets = <&cpg 918>;
593 dmas = <&dmac0 0x9d>, 529 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
594 dma-names = "tx", "rx" 530 dma-names = "tx", "rx";
595 i2c-scl-internal-delay 531 i2c-scl-internal-delay-ns = <6>;
596 status = "disabled"; 532 status = "disabled";
597 }; 533 };
598 534
599 i2c7: i2c@e6690000 { 535 i2c7: i2c@e6690000 {
600 #address-cells = <1>; 536 #address-cells = <1>;
601 #size-cells = <0>; 537 #size-cells = <0>;
602 compatible = "renesas, 538 compatible = "renesas,i2c-r8a77990",
603 "renesas, 539 "renesas,rcar-gen3-i2c";
604 reg = <0 0xe6690000 0 540 reg = <0 0xe6690000 0 0x40>;
605 interrupts = <GIC_SPI 541 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
606 clocks = <&cpg CPG_MOD 542 clocks = <&cpg CPG_MOD 1003>;
607 power-domains = <&sysc 543 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
608 resets = <&cpg 1003>; 544 resets = <&cpg 1003>;
609 i2c-scl-internal-delay 545 i2c-scl-internal-delay-ns = <6>;
610 status = "disabled"; 546 status = "disabled";
611 }; 547 };
612 548
613 hscif0: serial@e6540000 { 549 hscif0: serial@e6540000 {
614 compatible = "renesas, 550 compatible = "renesas,hscif-r8a77990",
615 "renesas, 551 "renesas,rcar-gen3-hscif",
616 "renesas, 552 "renesas,hscif";
617 reg = <0 0xe6540000 0 553 reg = <0 0xe6540000 0 0x60>;
618 interrupts = <GIC_SPI 554 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
619 clocks = <&cpg CPG_MOD 555 clocks = <&cpg CPG_MOD 520>,
620 <&cpg CPG_COR 556 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
621 <&scif_clk>; 557 <&scif_clk>;
622 clock-names = "fck", " 558 clock-names = "fck", "brg_int", "scif_clk";
623 dmas = <&dmac1 0x31>, 559 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
624 <&dmac2 0x31>, 560 <&dmac2 0x31>, <&dmac2 0x30>;
625 dma-names = "tx", "rx" 561 dma-names = "tx", "rx", "tx", "rx";
626 power-domains = <&sysc 562 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
627 resets = <&cpg 520>; 563 resets = <&cpg 520>;
628 status = "disabled"; 564 status = "disabled";
629 }; 565 };
630 566
631 hscif1: serial@e6550000 { 567 hscif1: serial@e6550000 {
632 compatible = "renesas, 568 compatible = "renesas,hscif-r8a77990",
633 "renesas, 569 "renesas,rcar-gen3-hscif",
634 "renesas, 570 "renesas,hscif";
635 reg = <0 0xe6550000 0 571 reg = <0 0xe6550000 0 0x60>;
636 interrupts = <GIC_SPI 572 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
637 clocks = <&cpg CPG_MOD 573 clocks = <&cpg CPG_MOD 519>,
638 <&cpg CPG_COR 574 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
639 <&scif_clk>; 575 <&scif_clk>;
640 clock-names = "fck", " 576 clock-names = "fck", "brg_int", "scif_clk";
641 dmas = <&dmac1 0x33>, 577 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
642 <&dmac2 0x33>, 578 <&dmac2 0x33>, <&dmac2 0x32>;
643 dma-names = "tx", "rx" 579 dma-names = "tx", "rx", "tx", "rx";
644 power-domains = <&sysc 580 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
645 resets = <&cpg 519>; 581 resets = <&cpg 519>;
646 status = "disabled"; 582 status = "disabled";
647 }; 583 };
648 584
649 hscif2: serial@e6560000 { 585 hscif2: serial@e6560000 {
650 compatible = "renesas, 586 compatible = "renesas,hscif-r8a77990",
651 "renesas, 587 "renesas,rcar-gen3-hscif",
652 "renesas, 588 "renesas,hscif";
653 reg = <0 0xe6560000 0 589 reg = <0 0xe6560000 0 0x60>;
654 interrupts = <GIC_SPI 590 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
655 clocks = <&cpg CPG_MOD 591 clocks = <&cpg CPG_MOD 518>,
656 <&cpg CPG_COR 592 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
657 <&scif_clk>; 593 <&scif_clk>;
658 clock-names = "fck", " 594 clock-names = "fck", "brg_int", "scif_clk";
659 dmas = <&dmac1 0x35>, 595 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
660 <&dmac2 0x35>, 596 <&dmac2 0x35>, <&dmac2 0x34>;
661 dma-names = "tx", "rx" 597 dma-names = "tx", "rx", "tx", "rx";
662 power-domains = <&sysc 598 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
663 resets = <&cpg 518>; 599 resets = <&cpg 518>;
664 status = "disabled"; 600 status = "disabled";
665 }; 601 };
666 602
667 hscif3: serial@e66a0000 { 603 hscif3: serial@e66a0000 {
668 compatible = "renesas, 604 compatible = "renesas,hscif-r8a77990",
669 "renesas, 605 "renesas,rcar-gen3-hscif",
670 "renesas, 606 "renesas,hscif";
671 reg = <0 0xe66a0000 0 607 reg = <0 0xe66a0000 0 0x60>;
672 interrupts = <GIC_SPI 608 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
673 clocks = <&cpg CPG_MOD 609 clocks = <&cpg CPG_MOD 517>,
674 <&cpg CPG_COR 610 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
675 <&scif_clk>; 611 <&scif_clk>;
676 clock-names = "fck", " 612 clock-names = "fck", "brg_int", "scif_clk";
677 dmas = <&dmac0 0x37>, 613 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
678 dma-names = "tx", "rx" 614 dma-names = "tx", "rx";
679 power-domains = <&sysc 615 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
680 resets = <&cpg 517>; 616 resets = <&cpg 517>;
681 status = "disabled"; 617 status = "disabled";
682 }; 618 };
683 619
684 hscif4: serial@e66b0000 { 620 hscif4: serial@e66b0000 {
685 compatible = "renesas, 621 compatible = "renesas,hscif-r8a77990",
686 "renesas, 622 "renesas,rcar-gen3-hscif",
687 "renesas, 623 "renesas,hscif";
688 reg = <0 0xe66b0000 0 624 reg = <0 0xe66b0000 0 0x60>;
689 interrupts = <GIC_SPI 625 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
690 clocks = <&cpg CPG_MOD 626 clocks = <&cpg CPG_MOD 516>,
691 <&cpg CPG_COR 627 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
692 <&scif_clk>; 628 <&scif_clk>;
693 clock-names = "fck", " 629 clock-names = "fck", "brg_int", "scif_clk";
694 dmas = <&dmac0 0x39>, 630 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
695 dma-names = "tx", "rx" 631 dma-names = "tx", "rx";
696 power-domains = <&sysc 632 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
697 resets = <&cpg 516>; 633 resets = <&cpg 516>;
698 status = "disabled"; 634 status = "disabled";
699 }; 635 };
700 636
701 hsusb: usb@e6590000 { 637 hsusb: usb@e6590000 {
702 compatible = "renesas, 638 compatible = "renesas,usbhs-r8a77990",
703 "renesas, 639 "renesas,rcar-gen3-usbhs";
704 reg = <0 0xe6590000 0 640 reg = <0 0xe6590000 0 0x200>;
705 interrupts = <GIC_SPI 641 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
706 clocks = <&cpg CPG_MOD 642 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
707 dmas = <&usb_dmac0 0>, 643 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
708 <&usb_dmac1 0>, 644 <&usb_dmac1 0>, <&usb_dmac1 1>;
709 dma-names = "ch0", "ch 645 dma-names = "ch0", "ch1", "ch2", "ch3";
710 renesas,buswait = <11> 646 renesas,buswait = <11>;
711 phys = <&usb2_phy0 3>; 647 phys = <&usb2_phy0 3>;
712 phy-names = "usb"; 648 phy-names = "usb";
713 power-domains = <&sysc 649 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
714 resets = <&cpg 704>, < 650 resets = <&cpg 704>, <&cpg 703>;
715 status = "disabled"; 651 status = "disabled";
716 }; 652 };
717 653
718 usb_dmac0: dma-controller@e65a 654 usb_dmac0: dma-controller@e65a0000 {
719 compatible = "renesas, 655 compatible = "renesas,r8a77990-usb-dmac",
720 "renesas, 656 "renesas,usb-dmac";
721 reg = <0 0xe65a0000 0 657 reg = <0 0xe65a0000 0 0x100>;
722 interrupts = <GIC_SPI 658 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
723 <GIC_SPI 659 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
724 interrupt-names = "ch0 660 interrupt-names = "ch0", "ch1";
725 clocks = <&cpg CPG_MOD 661 clocks = <&cpg CPG_MOD 330>;
726 power-domains = <&sysc 662 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
727 resets = <&cpg 330>; 663 resets = <&cpg 330>;
728 #dma-cells = <1>; 664 #dma-cells = <1>;
729 dma-channels = <2>; 665 dma-channels = <2>;
730 }; 666 };
731 667
732 usb_dmac1: dma-controller@e65b 668 usb_dmac1: dma-controller@e65b0000 {
733 compatible = "renesas, 669 compatible = "renesas,r8a77990-usb-dmac",
734 "renesas, 670 "renesas,usb-dmac";
735 reg = <0 0xe65b0000 0 671 reg = <0 0xe65b0000 0 0x100>;
736 interrupts = <GIC_SPI 672 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
737 <GIC_SPI 673 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
738 interrupt-names = "ch0 674 interrupt-names = "ch0", "ch1";
739 clocks = <&cpg CPG_MOD 675 clocks = <&cpg CPG_MOD 331>;
740 power-domains = <&sysc 676 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
741 resets = <&cpg 331>; 677 resets = <&cpg 331>;
742 #dma-cells = <1>; 678 #dma-cells = <1>;
743 dma-channels = <2>; 679 dma-channels = <2>;
744 }; 680 };
745 681
746 arm_cc630p: crypto@e6601000 { 682 arm_cc630p: crypto@e6601000 {
747 compatible = "arm,cryp 683 compatible = "arm,cryptocell-630p-ree";
748 interrupts = <GIC_SPI 684 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
749 reg = <0x0 0xe6601000 685 reg = <0x0 0xe6601000 0 0x1000>;
750 clocks = <&cpg CPG_MOD 686 clocks = <&cpg CPG_MOD 229>;
751 resets = <&cpg 229>; 687 resets = <&cpg 229>;
752 power-domains = <&sysc 688 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
753 }; 689 };
754 690
755 dmac0: dma-controller@e6700000 691 dmac0: dma-controller@e6700000 {
756 compatible = "renesas, 692 compatible = "renesas,dmac-r8a77990",
757 "renesas, 693 "renesas,rcar-dmac";
758 reg = <0 0xe6700000 0 694 reg = <0 0xe6700000 0 0x10000>;
759 interrupts = <GIC_SPI 695 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
760 <GIC_SPI 696 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
761 <GIC_SPI 697 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
762 <GIC_SPI 698 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
763 <GIC_SPI 699 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
764 <GIC_SPI 700 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
765 <GIC_SPI 701 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
766 <GIC_SPI 702 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
767 <GIC_SPI 703 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
768 <GIC_SPI 704 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
769 <GIC_SPI 705 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
770 <GIC_SPI 706 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
771 <GIC_SPI 707 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
772 <GIC_SPI 708 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
773 <GIC_SPI 709 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
774 <GIC_SPI 710 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
775 <GIC_SPI 711 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
776 interrupt-names = "err 712 interrupt-names = "error",
777 "ch0", 713 "ch0", "ch1", "ch2", "ch3",
778 "ch4", 714 "ch4", "ch5", "ch6", "ch7",
779 "ch8", 715 "ch8", "ch9", "ch10", "ch11",
780 "ch12" 716 "ch12", "ch13", "ch14", "ch15";
781 clocks = <&cpg CPG_MOD 717 clocks = <&cpg CPG_MOD 219>;
782 clock-names = "fck"; 718 clock-names = "fck";
783 power-domains = <&sysc 719 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
784 resets = <&cpg 219>; 720 resets = <&cpg 219>;
785 #dma-cells = <1>; 721 #dma-cells = <1>;
786 dma-channels = <16>; 722 dma-channels = <16>;
787 iommus = <&ipmmu_ds0 0 723 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
788 <&ipmmu_ds0 2>, 724 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
789 <&ipmmu_ds0 4>, 725 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
790 <&ipmmu_ds0 6>, 726 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
791 <&ipmmu_ds0 8>, 727 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
792 <&ipmmu_ds0 10> 728 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
793 <&ipmmu_ds0 12> 729 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
794 <&ipmmu_ds0 14> 730 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
795 }; 731 };
796 732
797 dmac1: dma-controller@e7300000 733 dmac1: dma-controller@e7300000 {
798 compatible = "renesas, 734 compatible = "renesas,dmac-r8a77990",
799 "renesas, 735 "renesas,rcar-dmac";
800 reg = <0 0xe7300000 0 736 reg = <0 0xe7300000 0 0x10000>;
801 interrupts = <GIC_SPI 737 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
802 <GIC_SPI 738 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
803 <GIC_SPI 739 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
804 <GIC_SPI 740 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
805 <GIC_SPI 741 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
806 <GIC_SPI 742 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
807 <GIC_SPI 743 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
808 <GIC_SPI 744 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
809 <GIC_SPI 745 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
810 <GIC_SPI 746 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
811 <GIC_SPI 747 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
812 <GIC_SPI 748 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
813 <GIC_SPI 749 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
814 <GIC_SPI 750 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
815 <GIC_SPI 751 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
816 <GIC_SPI 752 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
817 <GIC_SPI 753 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
818 interrupt-names = "err 754 interrupt-names = "error",
819 "ch0", 755 "ch0", "ch1", "ch2", "ch3",
820 "ch4", 756 "ch4", "ch5", "ch6", "ch7",
821 "ch8", 757 "ch8", "ch9", "ch10", "ch11",
822 "ch12" 758 "ch12", "ch13", "ch14", "ch15";
823 clocks = <&cpg CPG_MOD 759 clocks = <&cpg CPG_MOD 218>;
824 clock-names = "fck"; 760 clock-names = "fck";
825 power-domains = <&sysc 761 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
826 resets = <&cpg 218>; 762 resets = <&cpg 218>;
827 #dma-cells = <1>; 763 #dma-cells = <1>;
828 dma-channels = <16>; 764 dma-channels = <16>;
829 iommus = <&ipmmu_ds1 0 765 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
830 <&ipmmu_ds1 2>, 766 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
831 <&ipmmu_ds1 4>, 767 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
832 <&ipmmu_ds1 6>, 768 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
833 <&ipmmu_ds1 8>, 769 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
834 <&ipmmu_ds1 10> 770 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
835 <&ipmmu_ds1 12> 771 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
836 <&ipmmu_ds1 14> 772 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
837 }; 773 };
838 774
839 dmac2: dma-controller@e7310000 775 dmac2: dma-controller@e7310000 {
840 compatible = "renesas, 776 compatible = "renesas,dmac-r8a77990",
841 "renesas, 777 "renesas,rcar-dmac";
842 reg = <0 0xe7310000 0 778 reg = <0 0xe7310000 0 0x10000>;
843 interrupts = <GIC_SPI 779 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
844 <GIC_SPI 780 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
845 <GIC_SPI 781 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
846 <GIC_SPI 782 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
847 <GIC_SPI 783 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
848 <GIC_SPI 784 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
849 <GIC_SPI 785 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
850 <GIC_SPI 786 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
851 <GIC_SPI 787 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
852 <GIC_SPI 788 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
853 <GIC_SPI 789 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
854 <GIC_SPI 790 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
855 <GIC_SPI 791 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
856 <GIC_SPI 792 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
857 <GIC_SPI 793 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
858 <GIC_SPI 794 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
859 <GIC_SPI 795 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
860 interrupt-names = "err 796 interrupt-names = "error",
861 "ch0", 797 "ch0", "ch1", "ch2", "ch3",
862 "ch4", 798 "ch4", "ch5", "ch6", "ch7",
863 "ch8", 799 "ch8", "ch9", "ch10", "ch11",
864 "ch12" 800 "ch12", "ch13", "ch14", "ch15";
865 clocks = <&cpg CPG_MOD 801 clocks = <&cpg CPG_MOD 217>;
866 clock-names = "fck"; 802 clock-names = "fck";
867 power-domains = <&sysc 803 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
868 resets = <&cpg 217>; 804 resets = <&cpg 217>;
869 #dma-cells = <1>; 805 #dma-cells = <1>;
870 dma-channels = <16>; 806 dma-channels = <16>;
871 iommus = <&ipmmu_ds1 1 807 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
872 <&ipmmu_ds1 18> 808 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
873 <&ipmmu_ds1 20> 809 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
874 <&ipmmu_ds1 22> 810 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
875 <&ipmmu_ds1 24> 811 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
876 <&ipmmu_ds1 26> 812 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
877 <&ipmmu_ds1 28> 813 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
878 <&ipmmu_ds1 30> 814 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
879 }; 815 };
880 816
881 ipmmu_ds0: iommu@e6740000 { 817 ipmmu_ds0: iommu@e6740000 {
882 compatible = "renesas, 818 compatible = "renesas,ipmmu-r8a77990";
883 reg = <0 0xe6740000 0 819 reg = <0 0xe6740000 0 0x1000>;
884 renesas,ipmmu-main = < 820 renesas,ipmmu-main = <&ipmmu_mm 0>;
885 power-domains = <&sysc 821 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
886 #iommu-cells = <1>; 822 #iommu-cells = <1>;
887 }; 823 };
888 824
889 ipmmu_ds1: iommu@e7740000 { 825 ipmmu_ds1: iommu@e7740000 {
890 compatible = "renesas, 826 compatible = "renesas,ipmmu-r8a77990";
891 reg = <0 0xe7740000 0 827 reg = <0 0xe7740000 0 0x1000>;
892 renesas,ipmmu-main = < 828 renesas,ipmmu-main = <&ipmmu_mm 1>;
893 power-domains = <&sysc 829 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
894 #iommu-cells = <1>; 830 #iommu-cells = <1>;
895 }; 831 };
896 832
897 ipmmu_hc: iommu@e6570000 { 833 ipmmu_hc: iommu@e6570000 {
898 compatible = "renesas, 834 compatible = "renesas,ipmmu-r8a77990";
899 reg = <0 0xe6570000 0 835 reg = <0 0xe6570000 0 0x1000>;
900 renesas,ipmmu-main = < 836 renesas,ipmmu-main = <&ipmmu_mm 2>;
901 power-domains = <&sysc 837 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
902 #iommu-cells = <1>; 838 #iommu-cells = <1>;
903 }; 839 };
904 840
905 ipmmu_mm: iommu@e67b0000 { 841 ipmmu_mm: iommu@e67b0000 {
906 compatible = "renesas, 842 compatible = "renesas,ipmmu-r8a77990";
907 reg = <0 0xe67b0000 0 843 reg = <0 0xe67b0000 0 0x1000>;
908 interrupts = <GIC_SPI 844 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
909 <GIC_SPI 845 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
910 power-domains = <&sysc 846 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
911 #iommu-cells = <1>; 847 #iommu-cells = <1>;
912 }; 848 };
913 849
914 ipmmu_mp: iommu@ec670000 { 850 ipmmu_mp: iommu@ec670000 {
915 compatible = "renesas, 851 compatible = "renesas,ipmmu-r8a77990";
916 reg = <0 0xec670000 0 852 reg = <0 0xec670000 0 0x1000>;
917 renesas,ipmmu-main = < 853 renesas,ipmmu-main = <&ipmmu_mm 4>;
918 power-domains = <&sysc 854 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
919 #iommu-cells = <1>; 855 #iommu-cells = <1>;
920 }; 856 };
921 857
922 ipmmu_pv0: iommu@fd800000 { 858 ipmmu_pv0: iommu@fd800000 {
923 compatible = "renesas, 859 compatible = "renesas,ipmmu-r8a77990";
924 reg = <0 0xfd800000 0 860 reg = <0 0xfd800000 0 0x1000>;
925 renesas,ipmmu-main = < 861 renesas,ipmmu-main = <&ipmmu_mm 6>;
926 power-domains = <&sysc 862 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
927 #iommu-cells = <1>; 863 #iommu-cells = <1>;
928 }; 864 };
929 865
930 ipmmu_rt: iommu@ffc80000 { 866 ipmmu_rt: iommu@ffc80000 {
931 compatible = "renesas, 867 compatible = "renesas,ipmmu-r8a77990";
932 reg = <0 0xffc80000 0 868 reg = <0 0xffc80000 0 0x1000>;
933 renesas,ipmmu-main = < 869 renesas,ipmmu-main = <&ipmmu_mm 10>;
934 power-domains = <&sysc 870 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
935 #iommu-cells = <1>; 871 #iommu-cells = <1>;
936 }; 872 };
937 873
938 ipmmu_vc0: iommu@fe6b0000 { 874 ipmmu_vc0: iommu@fe6b0000 {
939 compatible = "renesas, 875 compatible = "renesas,ipmmu-r8a77990";
940 reg = <0 0xfe6b0000 0 876 reg = <0 0xfe6b0000 0 0x1000>;
941 renesas,ipmmu-main = < 877 renesas,ipmmu-main = <&ipmmu_mm 12>;
942 power-domains = <&sysc 878 power-domains = <&sysc R8A77990_PD_A3VC>;
943 #iommu-cells = <1>; 879 #iommu-cells = <1>;
944 }; 880 };
945 881
946 ipmmu_vi0: iommu@febd0000 { 882 ipmmu_vi0: iommu@febd0000 {
947 compatible = "renesas, 883 compatible = "renesas,ipmmu-r8a77990";
948 reg = <0 0xfebd0000 0 884 reg = <0 0xfebd0000 0 0x1000>;
949 renesas,ipmmu-main = < 885 renesas,ipmmu-main = <&ipmmu_mm 14>;
950 power-domains = <&sysc 886 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
951 #iommu-cells = <1>; 887 #iommu-cells = <1>;
952 }; 888 };
953 889
954 ipmmu_vp0: iommu@fe990000 { 890 ipmmu_vp0: iommu@fe990000 {
955 compatible = "renesas, 891 compatible = "renesas,ipmmu-r8a77990";
956 reg = <0 0xfe990000 0 892 reg = <0 0xfe990000 0 0x1000>;
957 renesas,ipmmu-main = < 893 renesas,ipmmu-main = <&ipmmu_mm 16>;
958 power-domains = <&sysc 894 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
959 #iommu-cells = <1>; 895 #iommu-cells = <1>;
960 }; 896 };
961 897
962 avb: ethernet@e6800000 { 898 avb: ethernet@e6800000 {
963 compatible = "renesas, 899 compatible = "renesas,etheravb-r8a77990",
964 "renesas, 900 "renesas,etheravb-rcar-gen3";
965 reg = <0 0xe6800000 0 901 reg = <0 0xe6800000 0 0x800>;
966 interrupts = <GIC_SPI 902 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
967 <GIC_SPI 903 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
968 <GIC_SPI 904 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
969 <GIC_SPI 905 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
970 <GIC_SPI 906 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
971 <GIC_SPI 907 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
972 <GIC_SPI 908 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
973 <GIC_SPI 909 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
974 <GIC_SPI 910 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
975 <GIC_SPI 911 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
976 <GIC_SPI 912 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
977 <GIC_SPI 913 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
978 <GIC_SPI 914 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
979 <GIC_SPI 915 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
980 <GIC_SPI 916 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
981 <GIC_SPI 917 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
982 <GIC_SPI 918 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
983 <GIC_SPI 919 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
984 <GIC_SPI 920 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
985 <GIC_SPI 921 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
986 <GIC_SPI 922 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
987 <GIC_SPI 923 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
988 <GIC_SPI 924 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
989 <GIC_SPI 925 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
990 <GIC_SPI 926 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
991 interrupt-names = "ch0 927 interrupt-names = "ch0", "ch1", "ch2", "ch3",
992 "ch4 928 "ch4", "ch5", "ch6", "ch7",
993 "ch8 929 "ch8", "ch9", "ch10", "ch11",
994 "ch1 930 "ch12", "ch13", "ch14", "ch15",
995 "ch1 931 "ch16", "ch17", "ch18", "ch19",
996 "ch2 932 "ch20", "ch21", "ch22", "ch23",
997 "ch2 933 "ch24";
998 clocks = <&cpg CPG_MOD 934 clocks = <&cpg CPG_MOD 812>;
999 clock-names = "fck"; <<
1000 power-domains = <&sys 935 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1001 resets = <&cpg 812>; 936 resets = <&cpg 812>;
1002 phy-mode = "rgmii"; 937 phy-mode = "rgmii";
1003 rx-internal-delay-ps <<
1004 iommus = <&ipmmu_ds0 938 iommus = <&ipmmu_ds0 16>;
1005 #address-cells = <1>; 939 #address-cells = <1>;
1006 #size-cells = <0>; 940 #size-cells = <0>;
1007 status = "disabled"; 941 status = "disabled";
1008 }; 942 };
1009 943
1010 can0: can@e6c30000 { 944 can0: can@e6c30000 {
1011 compatible = "renesas 945 compatible = "renesas,can-r8a77990",
1012 "renesas 946 "renesas,rcar-gen3-can";
1013 reg = <0 0xe6c30000 0 947 reg = <0 0xe6c30000 0 0x1000>;
1014 interrupts = <GIC_SPI 948 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
1015 clocks = <&cpg CPG_MO 949 clocks = <&cpg CPG_MOD 916>,
1016 <&cpg CPG_CORE 950 <&cpg CPG_CORE R8A77990_CLK_CANFD>,
1017 <&can_clk>; 951 <&can_clk>;
1018 clock-names = "clkp1" 952 clock-names = "clkp1", "clkp2", "can_clk";
1019 assigned-clocks = <&c 953 assigned-clocks = <&cpg CPG_CORE R8A77990_CLK_CANFD>;
1020 assigned-clock-rates 954 assigned-clock-rates = <40000000>;
1021 power-domains = <&sys 955 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1022 resets = <&cpg 916>; 956 resets = <&cpg 916>;
1023 status = "disabled"; 957 status = "disabled";
1024 }; 958 };
1025 959
1026 can1: can@e6c38000 { 960 can1: can@e6c38000 {
1027 compatible = "renesas 961 compatible = "renesas,can-r8a77990",
1028 "renesas 962 "renesas,rcar-gen3-can";
1029 reg = <0 0xe6c38000 0 963 reg = <0 0xe6c38000 0 0x1000>;
1030 interrupts = <GIC_SPI 964 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
1031 clocks = <&cpg CPG_MO 965 clocks = <&cpg CPG_MOD 915>,
1032 <&cpg CPG_CORE 966 <&cpg CPG_CORE R8A77990_CLK_CANFD>,
1033 <&can_clk>; 967 <&can_clk>;
1034 clock-names = "clkp1" 968 clock-names = "clkp1", "clkp2", "can_clk";
1035 assigned-clocks = <&c 969 assigned-clocks = <&cpg CPG_CORE R8A77990_CLK_CANFD>;
1036 assigned-clock-rates 970 assigned-clock-rates = <40000000>;
1037 power-domains = <&sys 971 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1038 resets = <&cpg 915>; 972 resets = <&cpg 915>;
1039 status = "disabled"; 973 status = "disabled";
1040 }; 974 };
1041 975
1042 canfd: can@e66c0000 { 976 canfd: can@e66c0000 {
1043 compatible = "renesas 977 compatible = "renesas,r8a77990-canfd",
1044 "renesas 978 "renesas,rcar-gen3-canfd";
1045 reg = <0 0xe66c0000 0 979 reg = <0 0xe66c0000 0 0x8000>;
1046 interrupts = <GIC_SPI 980 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
1047 <GIC_SPI 3 981 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1048 interrupt-names = "ch <<
1049 clocks = <&cpg CPG_MO 982 clocks = <&cpg CPG_MOD 914>,
1050 <&cpg CPG_CORE 983 <&cpg CPG_CORE R8A77990_CLK_CANFD>,
1051 <&can_clk>; 984 <&can_clk>;
1052 clock-names = "fck", 985 clock-names = "fck", "canfd", "can_clk";
1053 assigned-clocks = <&c 986 assigned-clocks = <&cpg CPG_CORE R8A77990_CLK_CANFD>;
1054 assigned-clock-rates 987 assigned-clock-rates = <40000000>;
1055 power-domains = <&sys 988 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1056 resets = <&cpg 914>; 989 resets = <&cpg 914>;
1057 status = "disabled"; 990 status = "disabled";
1058 991
1059 channel0 { 992 channel0 {
1060 status = "dis 993 status = "disabled";
1061 }; 994 };
1062 995
1063 channel1 { 996 channel1 {
1064 status = "dis 997 status = "disabled";
1065 }; 998 };
1066 }; 999 };
1067 1000
1068 pwm0: pwm@e6e30000 { 1001 pwm0: pwm@e6e30000 {
1069 compatible = "renesas 1002 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
1070 reg = <0 0xe6e30000 0 1003 reg = <0 0xe6e30000 0 0x8>;
1071 clocks = <&cpg CPG_MO 1004 clocks = <&cpg CPG_MOD 523>;
1072 power-domains = <&sys 1005 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1073 resets = <&cpg 523>; 1006 resets = <&cpg 523>;
1074 #pwm-cells = <2>; 1007 #pwm-cells = <2>;
1075 status = "disabled"; 1008 status = "disabled";
1076 }; 1009 };
1077 1010
1078 pwm1: pwm@e6e31000 { 1011 pwm1: pwm@e6e31000 {
1079 compatible = "renesas 1012 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
1080 reg = <0 0xe6e31000 0 1013 reg = <0 0xe6e31000 0 0x8>;
1081 clocks = <&cpg CPG_MO 1014 clocks = <&cpg CPG_MOD 523>;
1082 power-domains = <&sys 1015 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1083 resets = <&cpg 523>; 1016 resets = <&cpg 523>;
1084 #pwm-cells = <2>; 1017 #pwm-cells = <2>;
1085 status = "disabled"; 1018 status = "disabled";
1086 }; 1019 };
1087 1020
1088 pwm2: pwm@e6e32000 { 1021 pwm2: pwm@e6e32000 {
1089 compatible = "renesas 1022 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
1090 reg = <0 0xe6e32000 0 1023 reg = <0 0xe6e32000 0 0x8>;
1091 clocks = <&cpg CPG_MO 1024 clocks = <&cpg CPG_MOD 523>;
1092 power-domains = <&sys 1025 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1093 resets = <&cpg 523>; 1026 resets = <&cpg 523>;
1094 #pwm-cells = <2>; 1027 #pwm-cells = <2>;
1095 status = "disabled"; 1028 status = "disabled";
1096 }; 1029 };
1097 1030
1098 pwm3: pwm@e6e33000 { 1031 pwm3: pwm@e6e33000 {
1099 compatible = "renesas 1032 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
1100 reg = <0 0xe6e33000 0 1033 reg = <0 0xe6e33000 0 0x8>;
1101 clocks = <&cpg CPG_MO 1034 clocks = <&cpg CPG_MOD 523>;
1102 power-domains = <&sys 1035 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1103 resets = <&cpg 523>; 1036 resets = <&cpg 523>;
1104 #pwm-cells = <2>; 1037 #pwm-cells = <2>;
1105 status = "disabled"; 1038 status = "disabled";
1106 }; 1039 };
1107 1040
1108 pwm4: pwm@e6e34000 { 1041 pwm4: pwm@e6e34000 {
1109 compatible = "renesas 1042 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
1110 reg = <0 0xe6e34000 0 1043 reg = <0 0xe6e34000 0 0x8>;
1111 clocks = <&cpg CPG_MO 1044 clocks = <&cpg CPG_MOD 523>;
1112 power-domains = <&sys 1045 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1113 resets = <&cpg 523>; 1046 resets = <&cpg 523>;
1114 #pwm-cells = <2>; 1047 #pwm-cells = <2>;
1115 status = "disabled"; 1048 status = "disabled";
1116 }; 1049 };
1117 1050
1118 pwm5: pwm@e6e35000 { 1051 pwm5: pwm@e6e35000 {
1119 compatible = "renesas 1052 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
1120 reg = <0 0xe6e35000 0 1053 reg = <0 0xe6e35000 0 0x8>;
1121 clocks = <&cpg CPG_MO 1054 clocks = <&cpg CPG_MOD 523>;
1122 power-domains = <&sys 1055 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1123 resets = <&cpg 523>; 1056 resets = <&cpg 523>;
1124 #pwm-cells = <2>; 1057 #pwm-cells = <2>;
1125 status = "disabled"; 1058 status = "disabled";
1126 }; 1059 };
1127 1060
1128 pwm6: pwm@e6e36000 { 1061 pwm6: pwm@e6e36000 {
1129 compatible = "renesas 1062 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
1130 reg = <0 0xe6e36000 0 1063 reg = <0 0xe6e36000 0 0x8>;
1131 clocks = <&cpg CPG_MO 1064 clocks = <&cpg CPG_MOD 523>;
1132 power-domains = <&sys 1065 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1133 resets = <&cpg 523>; 1066 resets = <&cpg 523>;
1134 #pwm-cells = <2>; 1067 #pwm-cells = <2>;
1135 status = "disabled"; 1068 status = "disabled";
1136 }; 1069 };
1137 1070
1138 scif0: serial@e6e60000 { 1071 scif0: serial@e6e60000 {
1139 compatible = "renesas 1072 compatible = "renesas,scif-r8a77990",
1140 "renesas 1073 "renesas,rcar-gen3-scif", "renesas,scif";
1141 reg = <0 0xe6e60000 0 1074 reg = <0 0xe6e60000 0 64>;
1142 interrupts = <GIC_SPI 1075 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
1143 clocks = <&cpg CPG_MO 1076 clocks = <&cpg CPG_MOD 207>,
1144 <&cpg CPG_CO 1077 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
1145 <&scif_clk>; 1078 <&scif_clk>;
1146 clock-names = "fck", 1079 clock-names = "fck", "brg_int", "scif_clk";
1147 dmas = <&dmac1 0x51>, 1080 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1148 <&dmac2 0x51>, 1081 <&dmac2 0x51>, <&dmac2 0x50>;
1149 dma-names = "tx", "rx 1082 dma-names = "tx", "rx", "tx", "rx";
1150 power-domains = <&sys 1083 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1151 resets = <&cpg 207>; 1084 resets = <&cpg 207>;
1152 status = "disabled"; 1085 status = "disabled";
1153 }; 1086 };
1154 1087
1155 scif1: serial@e6e68000 { 1088 scif1: serial@e6e68000 {
1156 compatible = "renesas 1089 compatible = "renesas,scif-r8a77990",
1157 "renesas 1090 "renesas,rcar-gen3-scif", "renesas,scif";
1158 reg = <0 0xe6e68000 0 1091 reg = <0 0xe6e68000 0 64>;
1159 interrupts = <GIC_SPI 1092 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
1160 clocks = <&cpg CPG_MO 1093 clocks = <&cpg CPG_MOD 206>,
1161 <&cpg CPG_CO 1094 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
1162 <&scif_clk>; 1095 <&scif_clk>;
1163 clock-names = "fck", 1096 clock-names = "fck", "brg_int", "scif_clk";
1164 dmas = <&dmac1 0x53>, 1097 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1165 <&dmac2 0x53>, 1098 <&dmac2 0x53>, <&dmac2 0x52>;
1166 dma-names = "tx", "rx 1099 dma-names = "tx", "rx", "tx", "rx";
1167 power-domains = <&sys 1100 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1168 resets = <&cpg 206>; 1101 resets = <&cpg 206>;
1169 status = "disabled"; 1102 status = "disabled";
1170 }; 1103 };
1171 1104
1172 scif2: serial@e6e88000 { 1105 scif2: serial@e6e88000 {
1173 compatible = "renesas 1106 compatible = "renesas,scif-r8a77990",
1174 "renesas 1107 "renesas,rcar-gen3-scif", "renesas,scif";
1175 reg = <0 0xe6e88000 0 1108 reg = <0 0xe6e88000 0 64>;
1176 interrupts = <GIC_SPI 1109 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
1177 clocks = <&cpg CPG_MO 1110 clocks = <&cpg CPG_MOD 310>,
1178 <&cpg CPG_CO 1111 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
1179 <&scif_clk>; 1112 <&scif_clk>;
1180 clock-names = "fck", 1113 clock-names = "fck", "brg_int", "scif_clk";
1181 dmas = <&dmac1 0x13>, 1114 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1182 <&dmac2 0x13>, 1115 <&dmac2 0x13>, <&dmac2 0x12>;
1183 dma-names = "tx", "rx 1116 dma-names = "tx", "rx", "tx", "rx";
1184 power-domains = <&sys 1117 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1185 resets = <&cpg 310>; 1118 resets = <&cpg 310>;
1186 status = "disabled"; 1119 status = "disabled";
1187 }; 1120 };
1188 1121
1189 scif3: serial@e6c50000 { 1122 scif3: serial@e6c50000 {
1190 compatible = "renesas 1123 compatible = "renesas,scif-r8a77990",
1191 "renesas 1124 "renesas,rcar-gen3-scif", "renesas,scif";
1192 reg = <0 0xe6c50000 0 1125 reg = <0 0xe6c50000 0 64>;
1193 interrupts = <GIC_SPI 1126 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1194 clocks = <&cpg CPG_MO 1127 clocks = <&cpg CPG_MOD 204>,
1195 <&cpg CPG_CO 1128 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
1196 <&scif_clk>; 1129 <&scif_clk>;
1197 clock-names = "fck", 1130 clock-names = "fck", "brg_int", "scif_clk";
1198 dmas = <&dmac0 0x57>, 1131 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1199 dma-names = "tx", "rx 1132 dma-names = "tx", "rx";
1200 power-domains = <&sys 1133 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1201 resets = <&cpg 204>; 1134 resets = <&cpg 204>;
1202 status = "disabled"; 1135 status = "disabled";
1203 }; 1136 };
1204 1137
1205 scif4: serial@e6c40000 { 1138 scif4: serial@e6c40000 {
1206 compatible = "renesas 1139 compatible = "renesas,scif-r8a77990",
1207 "renesas 1140 "renesas,rcar-gen3-scif", "renesas,scif";
1208 reg = <0 0xe6c40000 0 1141 reg = <0 0xe6c40000 0 64>;
1209 interrupts = <GIC_SPI 1142 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1210 clocks = <&cpg CPG_MO 1143 clocks = <&cpg CPG_MOD 203>,
1211 <&cpg CPG_CO 1144 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
1212 <&scif_clk>; 1145 <&scif_clk>;
1213 clock-names = "fck", 1146 clock-names = "fck", "brg_int", "scif_clk";
1214 dmas = <&dmac0 0x59>, 1147 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1215 dma-names = "tx", "rx 1148 dma-names = "tx", "rx";
1216 power-domains = <&sys 1149 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1217 resets = <&cpg 203>; 1150 resets = <&cpg 203>;
1218 status = "disabled"; 1151 status = "disabled";
1219 }; 1152 };
1220 1153
1221 scif5: serial@e6f30000 { 1154 scif5: serial@e6f30000 {
1222 compatible = "renesas 1155 compatible = "renesas,scif-r8a77990",
1223 "renesas 1156 "renesas,rcar-gen3-scif", "renesas,scif";
1224 reg = <0 0xe6f30000 0 1157 reg = <0 0xe6f30000 0 64>;
1225 interrupts = <GIC_SPI 1158 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1226 clocks = <&cpg CPG_MO 1159 clocks = <&cpg CPG_MOD 202>,
1227 <&cpg CPG_CO 1160 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
1228 <&scif_clk>; 1161 <&scif_clk>;
1229 clock-names = "fck", 1162 clock-names = "fck", "brg_int", "scif_clk";
1230 dmas = <&dmac0 0x5b>, 1163 dmas = <&dmac0 0x5b>, <&dmac0 0x5a>;
1231 dma-names = "tx", "rx 1164 dma-names = "tx", "rx";
1232 power-domains = <&sys 1165 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1233 resets = <&cpg 202>; 1166 resets = <&cpg 202>;
1234 status = "disabled"; 1167 status = "disabled";
1235 }; 1168 };
1236 1169
1237 msiof0: spi@e6e90000 { 1170 msiof0: spi@e6e90000 {
1238 compatible = "renesas 1171 compatible = "renesas,msiof-r8a77990",
1239 "renesas 1172 "renesas,rcar-gen3-msiof";
1240 reg = <0 0xe6e90000 0 1173 reg = <0 0xe6e90000 0 0x0064>;
1241 interrupts = <GIC_SPI 1174 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1242 clocks = <&cpg CPG_MO 1175 clocks = <&cpg CPG_MOD 211>;
1243 dmas = <&dmac1 0x41>, 1176 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1244 <&dmac2 0x41>, 1177 <&dmac2 0x41>, <&dmac2 0x40>;
1245 dma-names = "tx", "rx 1178 dma-names = "tx", "rx", "tx", "rx";
1246 power-domains = <&sys 1179 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1247 resets = <&cpg 211>; 1180 resets = <&cpg 211>;
1248 #address-cells = <1>; 1181 #address-cells = <1>;
1249 #size-cells = <0>; 1182 #size-cells = <0>;
1250 status = "disabled"; 1183 status = "disabled";
1251 }; 1184 };
1252 1185
1253 msiof1: spi@e6ea0000 { 1186 msiof1: spi@e6ea0000 {
1254 compatible = "renesas 1187 compatible = "renesas,msiof-r8a77990",
1255 "renesas 1188 "renesas,rcar-gen3-msiof";
1256 reg = <0 0xe6ea0000 0 1189 reg = <0 0xe6ea0000 0 0x0064>;
1257 interrupts = <GIC_SPI 1190 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1258 clocks = <&cpg CPG_MO 1191 clocks = <&cpg CPG_MOD 210>;
1259 dmas = <&dmac0 0x43>, 1192 dmas = <&dmac0 0x43>, <&dmac0 0x42>;
1260 dma-names = "tx", "rx 1193 dma-names = "tx", "rx";
1261 power-domains = <&sys 1194 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1262 resets = <&cpg 210>; 1195 resets = <&cpg 210>;
1263 #address-cells = <1>; 1196 #address-cells = <1>;
1264 #size-cells = <0>; 1197 #size-cells = <0>;
1265 status = "disabled"; 1198 status = "disabled";
1266 }; 1199 };
1267 1200
1268 msiof2: spi@e6c00000 { 1201 msiof2: spi@e6c00000 {
1269 compatible = "renesas 1202 compatible = "renesas,msiof-r8a77990",
1270 "renesas 1203 "renesas,rcar-gen3-msiof";
1271 reg = <0 0xe6c00000 0 1204 reg = <0 0xe6c00000 0 0x0064>;
1272 interrupts = <GIC_SPI 1205 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1273 clocks = <&cpg CPG_MO 1206 clocks = <&cpg CPG_MOD 209>;
1274 dmas = <&dmac0 0x45>, 1207 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1275 dma-names = "tx", "rx 1208 dma-names = "tx", "rx";
1276 power-domains = <&sys 1209 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1277 resets = <&cpg 209>; 1210 resets = <&cpg 209>;
1278 #address-cells = <1>; 1211 #address-cells = <1>;
1279 #size-cells = <0>; 1212 #size-cells = <0>;
1280 status = "disabled"; 1213 status = "disabled";
1281 }; 1214 };
1282 1215
1283 msiof3: spi@e6c10000 { 1216 msiof3: spi@e6c10000 {
1284 compatible = "renesas 1217 compatible = "renesas,msiof-r8a77990",
1285 "renesas 1218 "renesas,rcar-gen3-msiof";
1286 reg = <0 0xe6c10000 0 1219 reg = <0 0xe6c10000 0 0x0064>;
1287 interrupts = <GIC_SPI 1220 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1288 clocks = <&cpg CPG_MO 1221 clocks = <&cpg CPG_MOD 208>;
1289 dmas = <&dmac0 0x47>, 1222 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1290 dma-names = "tx", "rx 1223 dma-names = "tx", "rx";
1291 power-domains = <&sys 1224 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1292 resets = <&cpg 208>; 1225 resets = <&cpg 208>;
1293 #address-cells = <1>; 1226 #address-cells = <1>;
1294 #size-cells = <0>; 1227 #size-cells = <0>;
1295 status = "disabled"; 1228 status = "disabled";
1296 }; 1229 };
1297 1230
1298 vin4: video@e6ef4000 { 1231 vin4: video@e6ef4000 {
1299 compatible = "renesas 1232 compatible = "renesas,vin-r8a77990";
1300 reg = <0 0xe6ef4000 0 1233 reg = <0 0xe6ef4000 0 0x1000>;
1301 interrupts = <GIC_SPI 1234 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
1302 clocks = <&cpg CPG_MO 1235 clocks = <&cpg CPG_MOD 807>;
1303 power-domains = <&sys 1236 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1304 resets = <&cpg 807>; 1237 resets = <&cpg 807>;
1305 renesas,id = <4>; 1238 renesas,id = <4>;
1306 status = "disabled"; 1239 status = "disabled";
1307 1240
1308 ports { 1241 ports {
1309 #address-cell 1242 #address-cells = <1>;
1310 #size-cells = 1243 #size-cells = <0>;
1311 1244
1312 port@1 { 1245 port@1 {
1313 #addr 1246 #address-cells = <1>;
1314 #size 1247 #size-cells = <0>;
1315 1248
1316 reg = 1249 reg = <1>;
1317 1250
1318 vin4c 1251 vin4csi40: endpoint@2 {
1319 1252 reg = <2>;
1320 !! 1253 remote-endpoint= <&csi40vin4>;
1321 }; 1254 };
1322 }; 1255 };
1323 }; 1256 };
1324 }; 1257 };
1325 1258
1326 vin5: video@e6ef5000 { 1259 vin5: video@e6ef5000 {
1327 compatible = "renesas 1260 compatible = "renesas,vin-r8a77990";
1328 reg = <0 0xe6ef5000 0 1261 reg = <0 0xe6ef5000 0 0x1000>;
1329 interrupts = <GIC_SPI 1262 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
1330 clocks = <&cpg CPG_MO 1263 clocks = <&cpg CPG_MOD 806>;
1331 power-domains = <&sys 1264 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1332 resets = <&cpg 806>; 1265 resets = <&cpg 806>;
1333 renesas,id = <5>; 1266 renesas,id = <5>;
1334 status = "disabled"; 1267 status = "disabled";
1335 1268
1336 ports { 1269 ports {
1337 #address-cell 1270 #address-cells = <1>;
1338 #size-cells = 1271 #size-cells = <0>;
1339 1272
1340 port@1 { 1273 port@1 {
1341 #addr 1274 #address-cells = <1>;
1342 #size 1275 #size-cells = <0>;
1343 1276
1344 reg = 1277 reg = <1>;
1345 1278
1346 vin5c 1279 vin5csi40: endpoint@2 {
1347 1280 reg = <2>;
1348 !! 1281 remote-endpoint= <&csi40vin5>;
1349 }; 1282 };
1350 }; 1283 };
1351 }; 1284 };
1352 }; 1285 };
1353 1286
1354 drif00: rif@e6f40000 { 1287 drif00: rif@e6f40000 {
1355 compatible = "renesas 1288 compatible = "renesas,r8a77990-drif",
1356 "renesas 1289 "renesas,rcar-gen3-drif";
1357 reg = <0 0xe6f40000 0 1290 reg = <0 0xe6f40000 0 0x84>;
1358 interrupts = <GIC_SPI 1291 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1359 clocks = <&cpg CPG_MO 1292 clocks = <&cpg CPG_MOD 515>;
1360 clock-names = "fck"; 1293 clock-names = "fck";
1361 dmas = <&dmac1 0x20>, 1294 dmas = <&dmac1 0x20>, <&dmac2 0x20>;
1362 dma-names = "rx", "rx 1295 dma-names = "rx", "rx";
1363 power-domains = <&sys 1296 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1364 resets = <&cpg 515>; 1297 resets = <&cpg 515>;
1365 renesas,bonding = <&d 1298 renesas,bonding = <&drif01>;
1366 status = "disabled"; 1299 status = "disabled";
1367 }; 1300 };
1368 1301
1369 drif01: rif@e6f50000 { 1302 drif01: rif@e6f50000 {
1370 compatible = "renesas 1303 compatible = "renesas,r8a77990-drif",
1371 "renesas 1304 "renesas,rcar-gen3-drif";
1372 reg = <0 0xe6f50000 0 1305 reg = <0 0xe6f50000 0 0x84>;
1373 interrupts = <GIC_SPI 1306 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1374 clocks = <&cpg CPG_MO 1307 clocks = <&cpg CPG_MOD 514>;
1375 clock-names = "fck"; 1308 clock-names = "fck";
1376 dmas = <&dmac1 0x22>, 1309 dmas = <&dmac1 0x22>, <&dmac2 0x22>;
1377 dma-names = "rx", "rx 1310 dma-names = "rx", "rx";
1378 power-domains = <&sys 1311 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1379 resets = <&cpg 514>; 1312 resets = <&cpg 514>;
1380 renesas,bonding = <&d 1313 renesas,bonding = <&drif00>;
1381 status = "disabled"; 1314 status = "disabled";
1382 }; 1315 };
1383 1316
1384 drif10: rif@e6f60000 { 1317 drif10: rif@e6f60000 {
1385 compatible = "renesas 1318 compatible = "renesas,r8a77990-drif",
1386 "renesas 1319 "renesas,rcar-gen3-drif";
1387 reg = <0 0xe6f60000 0 1320 reg = <0 0xe6f60000 0 0x84>;
1388 interrupts = <GIC_SPI 1321 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1389 clocks = <&cpg CPG_MO 1322 clocks = <&cpg CPG_MOD 513>;
1390 clock-names = "fck"; 1323 clock-names = "fck";
1391 dmas = <&dmac1 0x24>, 1324 dmas = <&dmac1 0x24>, <&dmac2 0x24>;
1392 dma-names = "rx", "rx 1325 dma-names = "rx", "rx";
1393 power-domains = <&sys 1326 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1394 resets = <&cpg 513>; 1327 resets = <&cpg 513>;
1395 renesas,bonding = <&d 1328 renesas,bonding = <&drif11>;
1396 status = "disabled"; 1329 status = "disabled";
1397 }; 1330 };
1398 1331
1399 drif11: rif@e6f70000 { 1332 drif11: rif@e6f70000 {
1400 compatible = "renesas 1333 compatible = "renesas,r8a77990-drif",
1401 "renesas 1334 "renesas,rcar-gen3-drif";
1402 reg = <0 0xe6f70000 0 1335 reg = <0 0xe6f70000 0 0x84>;
1403 interrupts = <GIC_SPI 1336 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1404 clocks = <&cpg CPG_MO 1337 clocks = <&cpg CPG_MOD 512>;
1405 clock-names = "fck"; 1338 clock-names = "fck";
1406 dmas = <&dmac1 0x26>, 1339 dmas = <&dmac1 0x26>, <&dmac2 0x26>;
1407 dma-names = "rx", "rx 1340 dma-names = "rx", "rx";
1408 power-domains = <&sys 1341 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1409 resets = <&cpg 512>; 1342 resets = <&cpg 512>;
1410 renesas,bonding = <&d 1343 renesas,bonding = <&drif10>;
1411 status = "disabled"; 1344 status = "disabled";
1412 }; 1345 };
1413 1346
1414 drif20: rif@e6f80000 { 1347 drif20: rif@e6f80000 {
1415 compatible = "renesas 1348 compatible = "renesas,r8a77990-drif",
1416 "renesas 1349 "renesas,rcar-gen3-drif";
1417 reg = <0 0xe6f80000 0 1350 reg = <0 0xe6f80000 0 0x84>;
1418 interrupts = <GIC_SPI 1351 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1419 clocks = <&cpg CPG_MO 1352 clocks = <&cpg CPG_MOD 511>;
1420 clock-names = "fck"; 1353 clock-names = "fck";
1421 dmas = <&dmac0 0x28>; 1354 dmas = <&dmac0 0x28>;
1422 dma-names = "rx"; 1355 dma-names = "rx";
1423 power-domains = <&sys 1356 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1424 resets = <&cpg 511>; 1357 resets = <&cpg 511>;
1425 renesas,bonding = <&d 1358 renesas,bonding = <&drif21>;
1426 status = "disabled"; 1359 status = "disabled";
1427 }; 1360 };
1428 1361
1429 drif21: rif@e6f90000 { 1362 drif21: rif@e6f90000 {
1430 compatible = "renesas 1363 compatible = "renesas,r8a77990-drif",
1431 "renesas 1364 "renesas,rcar-gen3-drif";
1432 reg = <0 0xe6f90000 0 1365 reg = <0 0xe6f90000 0 0x84>;
1433 interrupts = <GIC_SPI 1366 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1434 clocks = <&cpg CPG_MO 1367 clocks = <&cpg CPG_MOD 510>;
1435 clock-names = "fck"; 1368 clock-names = "fck";
1436 dmas = <&dmac0 0x2a>; 1369 dmas = <&dmac0 0x2a>;
1437 dma-names = "rx"; 1370 dma-names = "rx";
1438 power-domains = <&sys 1371 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1439 resets = <&cpg 510>; 1372 resets = <&cpg 510>;
1440 renesas,bonding = <&d 1373 renesas,bonding = <&drif20>;
1441 status = "disabled"; 1374 status = "disabled";
1442 }; 1375 };
1443 1376
1444 drif30: rif@e6fa0000 { 1377 drif30: rif@e6fa0000 {
1445 compatible = "renesas 1378 compatible = "renesas,r8a77990-drif",
1446 "renesas 1379 "renesas,rcar-gen3-drif";
1447 reg = <0 0xe6fa0000 0 1380 reg = <0 0xe6fa0000 0 0x84>;
1448 interrupts = <GIC_SPI 1381 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1449 clocks = <&cpg CPG_MO 1382 clocks = <&cpg CPG_MOD 509>;
1450 clock-names = "fck"; 1383 clock-names = "fck";
1451 dmas = <&dmac0 0x2c>; 1384 dmas = <&dmac0 0x2c>;
1452 dma-names = "rx"; 1385 dma-names = "rx";
1453 power-domains = <&sys 1386 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1454 resets = <&cpg 509>; 1387 resets = <&cpg 509>;
1455 renesas,bonding = <&d 1388 renesas,bonding = <&drif31>;
1456 status = "disabled"; 1389 status = "disabled";
1457 }; 1390 };
1458 1391
1459 drif31: rif@e6fb0000 { 1392 drif31: rif@e6fb0000 {
1460 compatible = "renesas 1393 compatible = "renesas,r8a77990-drif",
1461 "renesas 1394 "renesas,rcar-gen3-drif";
1462 reg = <0 0xe6fb0000 0 1395 reg = <0 0xe6fb0000 0 0x84>;
1463 interrupts = <GIC_SPI 1396 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1464 clocks = <&cpg CPG_MO 1397 clocks = <&cpg CPG_MOD 508>;
1465 clock-names = "fck"; 1398 clock-names = "fck";
1466 dmas = <&dmac0 0x2e>; 1399 dmas = <&dmac0 0x2e>;
1467 dma-names = "rx"; 1400 dma-names = "rx";
1468 power-domains = <&sys 1401 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1469 resets = <&cpg 508>; 1402 resets = <&cpg 508>;
1470 renesas,bonding = <&d 1403 renesas,bonding = <&drif30>;
1471 status = "disabled"; 1404 status = "disabled";
1472 }; 1405 };
1473 1406
1474 rcar_sound: sound@ec500000 { 1407 rcar_sound: sound@ec500000 {
1475 /* 1408 /*
1476 * #sound-dai-cells i !! 1409 * #sound-dai-cells is required
1477 * 1410 *
1478 * Single DAI : #soun 1411 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1479 * Multi DAI : #soun 1412 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1480 */ 1413 */
1481 /* 1414 /*
1482 * #clock-cells is re 1415 * #clock-cells is required for audio_clkout0/1/2/3
1483 * 1416 *
1484 * clkout : #cl 1417 * clkout : #clock-cells = <0>; <&rcar_sound>;
1485 * clkout0/1/2/3: #cl 1418 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
1486 */ 1419 */
1487 compatible = "renesas !! 1420 compatible = "renesas,rcar_sound-r8a77990", "renesas,rcar_sound-gen3";
1488 reg = <0 0xec500000 0 !! 1421 reg = <0 0xec500000 0 0x1000>, /* SCU */
1489 <0 0xec5a0000 0 !! 1422 <0 0xec5a0000 0 0x100>, /* ADG */
1490 <0 0xec540000 0 !! 1423 <0 0xec540000 0 0x1000>, /* SSIU */
1491 <0 0xec541000 0 !! 1424 <0 0xec541000 0 0x280>, /* SSI */
1492 <0 0xec760000 0 !! 1425 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
1493 reg-names = "scu", "a 1426 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1494 1427
1495 clocks = <&cpg CPG_MO 1428 clocks = <&cpg CPG_MOD 1005>,
1496 <&cpg CPG_MO 1429 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
1497 <&cpg CPG_MO 1430 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
1498 <&cpg CPG_MO 1431 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
1499 <&cpg CPG_MO 1432 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
1500 <&cpg CPG_MO 1433 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
1501 <&cpg CPG_MO 1434 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
1502 <&cpg CPG_MO 1435 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
1503 <&cpg CPG_MO 1436 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
1504 <&cpg CPG_MO 1437 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
1505 <&cpg CPG_MO 1438 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
1506 <&cpg CPG_MO 1439 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1507 <&cpg CPG_MO 1440 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1508 <&cpg CPG_MO 1441 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
1509 <&audio_clk_ 1442 <&audio_clk_a>, <&audio_clk_b>,
1510 <&audio_clk_ 1443 <&audio_clk_c>,
1511 <&cpg CPG_MO !! 1444 <&cpg CPG_CORE R8A77990_CLK_ZA2>;
1512 clock-names = "ssi-al 1445 clock-names = "ssi-all",
1513 "ssi.9" 1446 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1514 "ssi.5" 1447 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1515 "ssi.1" 1448 "ssi.1", "ssi.0",
1516 "src.9" 1449 "src.9", "src.8", "src.7", "src.6",
1517 "src.5" 1450 "src.5", "src.4", "src.3", "src.2",
1518 "src.1" 1451 "src.1", "src.0",
1519 "mix.1" 1452 "mix.1", "mix.0",
1520 "ctu.1" 1453 "ctu.1", "ctu.0",
1521 "dvc.0" 1454 "dvc.0", "dvc.1",
1522 "clk_a" 1455 "clk_a", "clk_b", "clk_c", "clk_i";
1523 power-domains = <&sys 1456 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1524 resets = <&cpg 1005>, 1457 resets = <&cpg 1005>,
1525 <&cpg 1006>, 1458 <&cpg 1006>, <&cpg 1007>,
1526 <&cpg 1008>, 1459 <&cpg 1008>, <&cpg 1009>,
1527 <&cpg 1010>, 1460 <&cpg 1010>, <&cpg 1011>,
1528 <&cpg 1012>, 1461 <&cpg 1012>, <&cpg 1013>,
1529 <&cpg 1014>, 1462 <&cpg 1014>, <&cpg 1015>;
1530 reset-names = "ssi-al 1463 reset-names = "ssi-all",
1531 "ssi.9" 1464 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1532 "ssi.5" 1465 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1533 "ssi.1" 1466 "ssi.1", "ssi.0";
1534 status = "disabled"; 1467 status = "disabled";
1535 1468
1536 rcar_sound,ctu { 1469 rcar_sound,ctu {
1537 ctu00: ctu-0 1470 ctu00: ctu-0 { };
1538 ctu01: ctu-1 1471 ctu01: ctu-1 { };
1539 ctu02: ctu-2 1472 ctu02: ctu-2 { };
1540 ctu03: ctu-3 1473 ctu03: ctu-3 { };
1541 ctu10: ctu-4 1474 ctu10: ctu-4 { };
1542 ctu11: ctu-5 1475 ctu11: ctu-5 { };
1543 ctu12: ctu-6 1476 ctu12: ctu-6 { };
1544 ctu13: ctu-7 1477 ctu13: ctu-7 { };
1545 }; 1478 };
1546 1479
1547 rcar_sound,dvc { 1480 rcar_sound,dvc {
1548 dvc0: dvc-0 { 1481 dvc0: dvc-0 {
1549 dmas 1482 dmas = <&audma0 0xbc>;
1550 dma-n 1483 dma-names = "tx";
1551 }; 1484 };
1552 dvc1: dvc-1 { 1485 dvc1: dvc-1 {
1553 dmas 1486 dmas = <&audma0 0xbe>;
1554 dma-n 1487 dma-names = "tx";
1555 }; 1488 };
1556 }; 1489 };
1557 1490
1558 rcar_sound,mix { 1491 rcar_sound,mix {
1559 mix0: mix-0 { 1492 mix0: mix-0 { };
1560 mix1: mix-1 { 1493 mix1: mix-1 { };
1561 }; 1494 };
1562 1495
1563 rcar_sound,src { 1496 rcar_sound,src {
1564 src0: src-0 { 1497 src0: src-0 {
1565 inter 1498 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1566 dmas 1499 dmas = <&audma0 0x85>, <&audma0 0x9a>;
1567 dma-n 1500 dma-names = "rx", "tx";
1568 }; 1501 };
1569 src1: src-1 { 1502 src1: src-1 {
1570 inter 1503 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1571 dmas 1504 dmas = <&audma0 0x87>, <&audma0 0x9c>;
1572 dma-n 1505 dma-names = "rx", "tx";
1573 }; 1506 };
1574 src2: src-2 { 1507 src2: src-2 {
1575 inter 1508 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1576 dmas 1509 dmas = <&audma0 0x89>, <&audma0 0x9e>;
1577 dma-n 1510 dma-names = "rx", "tx";
1578 }; 1511 };
1579 src3: src-3 { 1512 src3: src-3 {
1580 inter 1513 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1581 dmas 1514 dmas = <&audma0 0x8b>, <&audma0 0xa0>;
1582 dma-n 1515 dma-names = "rx", "tx";
1583 }; 1516 };
1584 src4: src-4 { 1517 src4: src-4 {
1585 inter 1518 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1586 dmas 1519 dmas = <&audma0 0x8d>, <&audma0 0xb0>;
1587 dma-n 1520 dma-names = "rx", "tx";
1588 }; 1521 };
1589 src5: src-5 { 1522 src5: src-5 {
1590 inter 1523 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1591 dmas 1524 dmas = <&audma0 0x8f>, <&audma0 0xb2>;
1592 dma-n 1525 dma-names = "rx", "tx";
1593 }; 1526 };
1594 src6: src-6 { 1527 src6: src-6 {
1595 inter 1528 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1596 dmas 1529 dmas = <&audma0 0x91>, <&audma0 0xb4>;
1597 dma-n 1530 dma-names = "rx", "tx";
1598 }; 1531 };
1599 src7: src-7 { 1532 src7: src-7 {
1600 inter 1533 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1601 dmas 1534 dmas = <&audma0 0x93>, <&audma0 0xb6>;
1602 dma-n 1535 dma-names = "rx", "tx";
1603 }; 1536 };
1604 src8: src-8 { 1537 src8: src-8 {
1605 inter 1538 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1606 dmas 1539 dmas = <&audma0 0x95>, <&audma0 0xb8>;
1607 dma-n 1540 dma-names = "rx", "tx";
1608 }; 1541 };
1609 src9: src-9 { 1542 src9: src-9 {
1610 inter 1543 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
1611 dmas 1544 dmas = <&audma0 0x97>, <&audma0 0xba>;
1612 dma-n 1545 dma-names = "rx", "tx";
1613 }; 1546 };
1614 }; 1547 };
1615 1548
1616 rcar_sound,ssi { 1549 rcar_sound,ssi {
1617 ssi0: ssi-0 { 1550 ssi0: ssi-0 {
1618 inter 1551 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
1619 dmas 1552 dmas = <&audma0 0x01>, <&audma0 0x02>,
1620 1553 <&audma0 0x15>, <&audma0 0x16>;
1621 dma-n 1554 dma-names = "rx", "tx", "rxu", "txu";
1622 }; 1555 };
1623 ssi1: ssi-1 { 1556 ssi1: ssi-1 {
1624 inter 1557 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
1625 dmas 1558 dmas = <&audma0 0x03>, <&audma0 0x04>,
1626 1559 <&audma0 0x49>, <&audma0 0x4a>;
1627 dma-n 1560 dma-names = "rx", "tx", "rxu", "txu";
1628 }; 1561 };
1629 ssi2: ssi-2 { 1562 ssi2: ssi-2 {
1630 inter 1563 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
1631 dmas 1564 dmas = <&audma0 0x05>, <&audma0 0x06>,
1632 1565 <&audma0 0x63>, <&audma0 0x64>;
1633 dma-n 1566 dma-names = "rx", "tx", "rxu", "txu";
1634 }; 1567 };
1635 ssi3: ssi-3 { 1568 ssi3: ssi-3 {
1636 inter 1569 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1637 dmas 1570 dmas = <&audma0 0x07>, <&audma0 0x08>,
1638 1571 <&audma0 0x6f>, <&audma0 0x70>;
1639 dma-n 1572 dma-names = "rx", "tx", "rxu", "txu";
1640 }; 1573 };
1641 ssi4: ssi-4 { 1574 ssi4: ssi-4 {
1642 inter 1575 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1643 dmas 1576 dmas = <&audma0 0x09>, <&audma0 0x0a>,
1644 1577 <&audma0 0x71>, <&audma0 0x72>;
1645 dma-n 1578 dma-names = "rx", "tx", "rxu", "txu";
1646 }; 1579 };
1647 ssi5: ssi-5 { 1580 ssi5: ssi-5 {
1648 inter 1581 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1649 dmas 1582 dmas = <&audma0 0x0b>, <&audma0 0x0c>,
1650 1583 <&audma0 0x73>, <&audma0 0x74>;
1651 dma-n 1584 dma-names = "rx", "tx", "rxu", "txu";
1652 }; 1585 };
1653 ssi6: ssi-6 { 1586 ssi6: ssi-6 {
1654 inter 1587 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
1655 dmas 1588 dmas = <&audma0 0x0d>, <&audma0 0x0e>,
1656 1589 <&audma0 0x75>, <&audma0 0x76>;
1657 dma-n 1590 dma-names = "rx", "tx", "rxu", "txu";
1658 }; 1591 };
1659 ssi7: ssi-7 { 1592 ssi7: ssi-7 {
1660 inter 1593 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
1661 dmas 1594 dmas = <&audma0 0x0f>, <&audma0 0x10>,
1662 1595 <&audma0 0x79>, <&audma0 0x7a>;
1663 dma-n 1596 dma-names = "rx", "tx", "rxu", "txu";
1664 }; 1597 };
1665 ssi8: ssi-8 { 1598 ssi8: ssi-8 {
1666 inter 1599 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
1667 dmas 1600 dmas = <&audma0 0x11>, <&audma0 0x12>,
1668 1601 <&audma0 0x7b>, <&audma0 0x7c>;
1669 dma-n 1602 dma-names = "rx", "tx", "rxu", "txu";
1670 }; 1603 };
1671 ssi9: ssi-9 { 1604 ssi9: ssi-9 {
1672 inter 1605 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
1673 dmas 1606 dmas = <&audma0 0x13>, <&audma0 0x14>,
1674 1607 <&audma0 0x7d>, <&audma0 0x7e>;
1675 dma-n 1608 dma-names = "rx", "tx", "rxu", "txu";
1676 }; 1609 };
1677 }; 1610 };
1678 }; 1611 };
1679 1612
1680 mlp: mlp@ec520000 { <<
1681 compatible = "renesas <<
1682 "renesas <<
1683 reg = <0 0xec520000 0 <<
1684 interrupts = <GIC_SPI <<
1685 <GIC_SPI 385 <<
1686 clocks = <&cpg CPG_MO <<
1687 power-domains = <&sys <<
1688 resets = <&cpg 802>; <<
1689 status = "disabled"; <<
1690 }; <<
1691 <<
1692 audma0: dma-controller@ec7000 1613 audma0: dma-controller@ec700000 {
1693 compatible = "renesas 1614 compatible = "renesas,dmac-r8a77990",
1694 "renesas 1615 "renesas,rcar-dmac";
1695 reg = <0 0xec700000 0 1616 reg = <0 0xec700000 0 0x10000>;
1696 interrupts = <GIC_SPI 1617 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
1697 <GIC_SPI 1618 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
1698 <GIC_SPI 1619 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
1699 <GIC_SPI 1620 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
1700 <GIC_SPI 1621 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
1701 <GIC_SPI 1622 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
1702 <GIC_SPI 1623 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
1703 <GIC_SPI 1624 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
1704 <GIC_SPI 1625 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
1705 <GIC_SPI 1626 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
1706 <GIC_SPI 1627 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1707 <GIC_SPI 1628 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
1708 <GIC_SPI 1629 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
1709 <GIC_SPI 1630 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
1710 <GIC_SPI 1631 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
1711 <GIC_SPI 1632 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1712 <GIC_SPI 1633 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
1713 interrupt-names = "er 1634 interrupt-names = "error",
1714 "ch0" 1635 "ch0", "ch1", "ch2", "ch3",
1715 "ch4" 1636 "ch4", "ch5", "ch6", "ch7",
1716 "ch8" 1637 "ch8", "ch9", "ch10", "ch11",
1717 "ch12 1638 "ch12", "ch13", "ch14", "ch15";
1718 clocks = <&cpg CPG_MO 1639 clocks = <&cpg CPG_MOD 502>;
1719 clock-names = "fck"; 1640 clock-names = "fck";
1720 power-domains = <&sys 1641 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1721 resets = <&cpg 502>; 1642 resets = <&cpg 502>;
1722 #dma-cells = <1>; 1643 #dma-cells = <1>;
1723 dma-channels = <16>; 1644 dma-channels = <16>;
1724 iommus = <&ipmmu_mp 0 1645 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
1725 <&ipmmu_mp 2 1646 <&ipmmu_mp 2>, <&ipmmu_mp 3>,
1726 <&ipmmu_mp 4 1647 <&ipmmu_mp 4>, <&ipmmu_mp 5>,
1727 <&ipmmu_mp 6 1648 <&ipmmu_mp 6>, <&ipmmu_mp 7>,
1728 <&ipmmu_mp 8 1649 <&ipmmu_mp 8>, <&ipmmu_mp 9>,
1729 <&ipmmu_mp 1 1650 <&ipmmu_mp 10>, <&ipmmu_mp 11>,
1730 <&ipmmu_mp 1 1651 <&ipmmu_mp 12>, <&ipmmu_mp 13>,
1731 <&ipmmu_mp 1 1652 <&ipmmu_mp 14>, <&ipmmu_mp 15>;
1732 }; 1653 };
1733 1654
1734 xhci0: usb@ee000000 { 1655 xhci0: usb@ee000000 {
1735 compatible = "renesas 1656 compatible = "renesas,xhci-r8a77990",
1736 "renesas 1657 "renesas,rcar-gen3-xhci";
1737 reg = <0 0xee000000 0 1658 reg = <0 0xee000000 0 0xc00>;
1738 interrupts = <GIC_SPI 1659 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1739 clocks = <&cpg CPG_MO 1660 clocks = <&cpg CPG_MOD 328>;
1740 power-domains = <&sys 1661 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1741 resets = <&cpg 328>; 1662 resets = <&cpg 328>;
1742 status = "disabled"; 1663 status = "disabled";
1743 }; 1664 };
1744 1665
1745 usb3_peri0: usb@ee020000 { 1666 usb3_peri0: usb@ee020000 {
1746 compatible = "renesas 1667 compatible = "renesas,r8a77990-usb3-peri",
1747 "renesas 1668 "renesas,rcar-gen3-usb3-peri";
1748 reg = <0 0xee020000 0 1669 reg = <0 0xee020000 0 0x400>;
1749 interrupts = <GIC_SPI 1670 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1750 clocks = <&cpg CPG_MO 1671 clocks = <&cpg CPG_MOD 328>;
1751 power-domains = <&sys 1672 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1752 resets = <&cpg 328>; 1673 resets = <&cpg 328>;
1753 status = "disabled"; 1674 status = "disabled";
1754 }; 1675 };
1755 1676
1756 ohci0: usb@ee080000 { 1677 ohci0: usb@ee080000 {
1757 compatible = "generic 1678 compatible = "generic-ohci";
1758 reg = <0 0xee080000 0 1679 reg = <0 0xee080000 0 0x100>;
1759 interrupts = <GIC_SPI 1680 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1760 clocks = <&cpg CPG_MO 1681 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
1761 phys = <&usb2_phy0 1> 1682 phys = <&usb2_phy0 1>;
1762 phy-names = "usb"; 1683 phy-names = "usb";
1763 power-domains = <&sys 1684 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1764 resets = <&cpg 703>, 1685 resets = <&cpg 703>, <&cpg 704>;
1765 status = "disabled"; 1686 status = "disabled";
1766 }; 1687 };
1767 1688
1768 ehci0: usb@ee080100 { 1689 ehci0: usb@ee080100 {
1769 compatible = "generic 1690 compatible = "generic-ehci";
1770 reg = <0 0xee080100 0 1691 reg = <0 0xee080100 0 0x100>;
1771 interrupts = <GIC_SPI 1692 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1772 clocks = <&cpg CPG_MO 1693 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
1773 phys = <&usb2_phy0 2> 1694 phys = <&usb2_phy0 2>;
1774 phy-names = "usb"; 1695 phy-names = "usb";
1775 companion = <&ohci0>; 1696 companion = <&ohci0>;
1776 power-domains = <&sys 1697 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1777 resets = <&cpg 703>, 1698 resets = <&cpg 703>, <&cpg 704>;
1778 status = "disabled"; 1699 status = "disabled";
1779 }; 1700 };
1780 1701
1781 usb2_phy0: usb-phy@ee080200 { 1702 usb2_phy0: usb-phy@ee080200 {
1782 compatible = "renesas 1703 compatible = "renesas,usb2-phy-r8a77990",
1783 "renesas 1704 "renesas,rcar-gen3-usb2-phy";
1784 reg = <0 0xee080200 0 1705 reg = <0 0xee080200 0 0x700>;
1785 interrupts = <GIC_SPI 1706 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1786 clocks = <&cpg CPG_MO 1707 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
1787 power-domains = <&sys 1708 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1788 resets = <&cpg 703>, 1709 resets = <&cpg 703>, <&cpg 704>;
1789 #phy-cells = <1>; 1710 #phy-cells = <1>;
1790 status = "disabled"; 1711 status = "disabled";
1791 }; 1712 };
1792 1713
1793 sdhi0: mmc@ee100000 { 1714 sdhi0: mmc@ee100000 {
1794 compatible = "renesas 1715 compatible = "renesas,sdhi-r8a77990",
1795 "renesas 1716 "renesas,rcar-gen3-sdhi";
1796 reg = <0 0xee100000 0 1717 reg = <0 0xee100000 0 0x2000>;
1797 interrupts = <GIC_SPI 1718 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
1798 clocks = <&cpg CPG_MO !! 1719 clocks = <&cpg CPG_MOD 314>;
1799 clock-names = "core", <<
1800 max-frequency = <2000 1720 max-frequency = <200000000>;
1801 power-domains = <&sys 1721 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1802 resets = <&cpg 314>; 1722 resets = <&cpg 314>;
1803 iommus = <&ipmmu_ds1 1723 iommus = <&ipmmu_ds1 32>;
1804 status = "disabled"; 1724 status = "disabled";
1805 }; 1725 };
1806 1726
1807 sdhi1: mmc@ee120000 { 1727 sdhi1: mmc@ee120000 {
1808 compatible = "renesas 1728 compatible = "renesas,sdhi-r8a77990",
1809 "renesas 1729 "renesas,rcar-gen3-sdhi";
1810 reg = <0 0xee120000 0 1730 reg = <0 0xee120000 0 0x2000>;
1811 interrupts = <GIC_SPI 1731 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
1812 clocks = <&cpg CPG_MO !! 1732 clocks = <&cpg CPG_MOD 313>;
1813 clock-names = "core", <<
1814 max-frequency = <2000 1733 max-frequency = <200000000>;
1815 power-domains = <&sys 1734 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1816 resets = <&cpg 313>; 1735 resets = <&cpg 313>;
1817 iommus = <&ipmmu_ds1 1736 iommus = <&ipmmu_ds1 33>;
1818 status = "disabled"; 1737 status = "disabled";
1819 }; 1738 };
1820 1739
1821 sdhi3: mmc@ee160000 { 1740 sdhi3: mmc@ee160000 {
1822 compatible = "renesas 1741 compatible = "renesas,sdhi-r8a77990",
1823 "renesas 1742 "renesas,rcar-gen3-sdhi";
1824 reg = <0 0xee160000 0 1743 reg = <0 0xee160000 0 0x2000>;
1825 interrupts = <GIC_SPI 1744 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
1826 clocks = <&cpg CPG_MO !! 1745 clocks = <&cpg CPG_MOD 311>;
1827 clock-names = "core", <<
1828 max-frequency = <2000 1746 max-frequency = <200000000>;
1829 power-domains = <&sys 1747 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1830 resets = <&cpg 311>; 1748 resets = <&cpg 311>;
1831 iommus = <&ipmmu_ds1 1749 iommus = <&ipmmu_ds1 35>;
1832 status = "disabled"; 1750 status = "disabled";
1833 }; 1751 };
1834 1752
1835 rpc: spi@ee200000 { <<
1836 compatible = "renesas <<
1837 "renesas <<
1838 reg = <0 0xee200000 0 <<
1839 <0 0x08000000 0 <<
1840 <0 0xee208000 0 <<
1841 reg-names = "regs", " <<
1842 interrupts = <GIC_SPI <<
1843 clocks = <&cpg CPG_MO <<
1844 power-domains = <&sys <<
1845 resets = <&cpg 917>; <<
1846 #address-cells = <1>; <<
1847 #size-cells = <0>; <<
1848 status = "disabled"; <<
1849 }; <<
1850 <<
1851 gic: interrupt-controller@f10 1753 gic: interrupt-controller@f1010000 {
1852 compatible = "arm,gic 1754 compatible = "arm,gic-400";
1853 #interrupt-cells = <3 1755 #interrupt-cells = <3>;
1854 #address-cells = <0>; 1756 #address-cells = <0>;
1855 interrupt-controller; 1757 interrupt-controller;
1856 reg = <0x0 0xf1010000 1758 reg = <0x0 0xf1010000 0 0x1000>,
1857 <0x0 0xf1020000 1759 <0x0 0xf1020000 0 0x20000>,
1858 <0x0 0xf1040000 1760 <0x0 0xf1040000 0 0x20000>,
1859 <0x0 0xf1060000 1761 <0x0 0xf1060000 0 0x20000>;
1860 interrupts = <GIC_PPI 1762 interrupts = <GIC_PPI 9
1861 (GIC_ 1763 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
1862 clocks = <&cpg CPG_MO 1764 clocks = <&cpg CPG_MOD 408>;
1863 clock-names = "clk"; 1765 clock-names = "clk";
1864 power-domains = <&sys 1766 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1865 resets = <&cpg 408>; 1767 resets = <&cpg 408>;
1866 }; 1768 };
1867 1769
1868 pciec0: pcie@fe000000 { 1770 pciec0: pcie@fe000000 {
1869 compatible = "renesas 1771 compatible = "renesas,pcie-r8a77990",
1870 "renesas 1772 "renesas,pcie-rcar-gen3";
1871 reg = <0 0xfe000000 0 1773 reg = <0 0xfe000000 0 0x80000>;
1872 #address-cells = <3>; 1774 #address-cells = <3>;
1873 #size-cells = <2>; 1775 #size-cells = <2>;
1874 bus-range = <0x00 0xf 1776 bus-range = <0x00 0xff>;
1875 device_type = "pci"; 1777 device_type = "pci";
1876 ranges = <0x01000000 1778 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
1877 <0x02000000 1779 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
1878 <0x02000000 1780 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
1879 <0x42000000 1781 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1880 /* Map all possible D !! 1782 /* Map all possible DDR as inbound ranges */
1881 dma-ranges = <0x42000 !! 1783 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;
1882 interrupts = <GIC_SPI 1784 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1883 <GIC_SPI 1785 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1884 <GIC_SPI 1786 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1885 #interrupt-cells = <1 1787 #interrupt-cells = <1>;
1886 interrupt-map-mask = 1788 interrupt-map-mask = <0 0 0 0>;
1887 interrupt-map = <0 0 1789 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1888 clocks = <&cpg CPG_MO 1790 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
1889 clock-names = "pcie", 1791 clock-names = "pcie", "pcie_bus";
1890 power-domains = <&sys 1792 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1891 resets = <&cpg 319>; 1793 resets = <&cpg 319>;
1892 iommu-map = <0 &ipmmu <<
1893 iommu-map-mask = <0>; <<
1894 status = "disabled"; 1794 status = "disabled";
1895 }; 1795 };
1896 1796
1897 vspb0: vsp@fe960000 { 1797 vspb0: vsp@fe960000 {
1898 compatible = "renesas 1798 compatible = "renesas,vsp2";
1899 reg = <0 0xfe960000 0 1799 reg = <0 0xfe960000 0 0x8000>;
1900 interrupts = <GIC_SPI 1800 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
1901 clocks = <&cpg CPG_MO 1801 clocks = <&cpg CPG_MOD 626>;
1902 power-domains = <&sys 1802 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1903 resets = <&cpg 626>; 1803 resets = <&cpg 626>;
1904 renesas,fcp = <&fcpvb 1804 renesas,fcp = <&fcpvb0>;
1905 }; 1805 };
1906 1806
1907 fcpvb0: fcp@fe96f000 { 1807 fcpvb0: fcp@fe96f000 {
1908 compatible = "renesas 1808 compatible = "renesas,fcpv";
1909 reg = <0 0xfe96f000 0 1809 reg = <0 0xfe96f000 0 0x200>;
1910 clocks = <&cpg CPG_MO 1810 clocks = <&cpg CPG_MOD 607>;
1911 power-domains = <&sys 1811 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1912 resets = <&cpg 607>; 1812 resets = <&cpg 607>;
1913 iommus = <&ipmmu_vp0 1813 iommus = <&ipmmu_vp0 5>;
1914 }; 1814 };
1915 1815
1916 vspi0: vsp@fe9a0000 { 1816 vspi0: vsp@fe9a0000 {
1917 compatible = "renesas 1817 compatible = "renesas,vsp2";
1918 reg = <0 0xfe9a0000 0 1818 reg = <0 0xfe9a0000 0 0x8000>;
1919 interrupts = <GIC_SPI 1819 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
1920 clocks = <&cpg CPG_MO 1820 clocks = <&cpg CPG_MOD 631>;
1921 power-domains = <&sys 1821 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1922 resets = <&cpg 631>; 1822 resets = <&cpg 631>;
1923 renesas,fcp = <&fcpvi 1823 renesas,fcp = <&fcpvi0>;
1924 }; 1824 };
1925 1825
1926 fcpvi0: fcp@fe9af000 { 1826 fcpvi0: fcp@fe9af000 {
1927 compatible = "renesas 1827 compatible = "renesas,fcpv";
1928 reg = <0 0xfe9af000 0 1828 reg = <0 0xfe9af000 0 0x200>;
1929 clocks = <&cpg CPG_MO 1829 clocks = <&cpg CPG_MOD 611>;
1930 power-domains = <&sys 1830 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1931 resets = <&cpg 611>; 1831 resets = <&cpg 611>;
1932 iommus = <&ipmmu_vp0 1832 iommus = <&ipmmu_vp0 8>;
1933 }; 1833 };
1934 1834
1935 vspd0: vsp@fea20000 { 1835 vspd0: vsp@fea20000 {
1936 compatible = "renesas 1836 compatible = "renesas,vsp2";
1937 reg = <0 0xfea20000 0 1837 reg = <0 0xfea20000 0 0x7000>;
1938 interrupts = <GIC_SPI 1838 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
1939 clocks = <&cpg CPG_MO 1839 clocks = <&cpg CPG_MOD 623>;
1940 power-domains = <&sys 1840 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1941 resets = <&cpg 623>; 1841 resets = <&cpg 623>;
1942 renesas,fcp = <&fcpvd 1842 renesas,fcp = <&fcpvd0>;
1943 }; 1843 };
1944 1844
1945 fcpvd0: fcp@fea27000 { 1845 fcpvd0: fcp@fea27000 {
1946 compatible = "renesas 1846 compatible = "renesas,fcpv";
1947 reg = <0 0xfea27000 0 1847 reg = <0 0xfea27000 0 0x200>;
1948 clocks = <&cpg CPG_MO 1848 clocks = <&cpg CPG_MOD 603>;
1949 power-domains = <&sys 1849 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1950 resets = <&cpg 603>; 1850 resets = <&cpg 603>;
1951 iommus = <&ipmmu_vi0 1851 iommus = <&ipmmu_vi0 8>;
1952 }; 1852 };
1953 1853
1954 vspd1: vsp@fea28000 { 1854 vspd1: vsp@fea28000 {
1955 compatible = "renesas 1855 compatible = "renesas,vsp2";
1956 reg = <0 0xfea28000 0 1856 reg = <0 0xfea28000 0 0x7000>;
1957 interrupts = <GIC_SPI 1857 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
1958 clocks = <&cpg CPG_MO 1858 clocks = <&cpg CPG_MOD 622>;
1959 power-domains = <&sys 1859 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1960 resets = <&cpg 622>; 1860 resets = <&cpg 622>;
1961 renesas,fcp = <&fcpvd 1861 renesas,fcp = <&fcpvd1>;
1962 }; 1862 };
1963 1863
1964 fcpvd1: fcp@fea2f000 { 1864 fcpvd1: fcp@fea2f000 {
1965 compatible = "renesas 1865 compatible = "renesas,fcpv";
1966 reg = <0 0xfea2f000 0 1866 reg = <0 0xfea2f000 0 0x200>;
1967 clocks = <&cpg CPG_MO 1867 clocks = <&cpg CPG_MOD 602>;
1968 power-domains = <&sys 1868 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1969 resets = <&cpg 602>; 1869 resets = <&cpg 602>;
1970 iommus = <&ipmmu_vi0 1870 iommus = <&ipmmu_vi0 9>;
1971 }; 1871 };
1972 1872
1973 cmm0: cmm@fea40000 { 1873 cmm0: cmm@fea40000 {
1974 compatible = "renesas 1874 compatible = "renesas,r8a77990-cmm",
1975 "renesas 1875 "renesas,rcar-gen3-cmm";
1976 reg = <0 0xfea40000 0 1876 reg = <0 0xfea40000 0 0x1000>;
1977 power-domains = <&sys 1877 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1978 clocks = <&cpg CPG_MO 1878 clocks = <&cpg CPG_MOD 711>;
1979 resets = <&cpg 711>; 1879 resets = <&cpg 711>;
1980 }; 1880 };
1981 1881
1982 cmm1: cmm@fea50000 { 1882 cmm1: cmm@fea50000 {
1983 compatible = "renesas 1883 compatible = "renesas,r8a77990-cmm",
1984 "renesas 1884 "renesas,rcar-gen3-cmm";
1985 reg = <0 0xfea50000 0 1885 reg = <0 0xfea50000 0 0x1000>;
1986 power-domains = <&sys 1886 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1987 clocks = <&cpg CPG_MO 1887 clocks = <&cpg CPG_MOD 710>;
1988 resets = <&cpg 710>; 1888 resets = <&cpg 710>;
1989 }; 1889 };
1990 1890
1991 csi40: csi2@feaa0000 { 1891 csi40: csi2@feaa0000 {
1992 compatible = "renesas 1892 compatible = "renesas,r8a77990-csi2";
1993 reg = <0 0xfeaa0000 0 1893 reg = <0 0xfeaa0000 0 0x10000>;
1994 interrupts = <GIC_SPI 1894 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
1995 clocks = <&cpg CPG_MO 1895 clocks = <&cpg CPG_MOD 716>;
1996 power-domains = <&sys 1896 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1997 resets = <&cpg 716>; 1897 resets = <&cpg 716>;
1998 status = "disabled"; 1898 status = "disabled";
1999 1899
2000 ports { 1900 ports {
2001 #address-cell 1901 #address-cells = <1>;
2002 #size-cells = 1902 #size-cells = <0>;
2003 1903
2004 port@0 { <<
2005 reg = <<
2006 }; <<
2007 <<
2008 port@1 { 1904 port@1 {
2009 #addr 1905 #address-cells = <1>;
2010 #size 1906 #size-cells = <0>;
2011 1907
2012 reg = 1908 reg = <1>;
2013 1909
2014 csi40 1910 csi40vin4: endpoint@0 {
2015 1911 reg = <0>;
2016 1912 remote-endpoint = <&vin4csi40>;
2017 }; 1913 };
2018 csi40 1914 csi40vin5: endpoint@1 {
2019 1915 reg = <1>;
2020 1916 remote-endpoint = <&vin5csi40>;
2021 }; 1917 };
2022 }; 1918 };
2023 }; 1919 };
2024 }; 1920 };
2025 1921
2026 du: display@feb00000 { 1922 du: display@feb00000 {
2027 compatible = "renesas 1923 compatible = "renesas,du-r8a77990";
2028 reg = <0 0xfeb00000 0 1924 reg = <0 0xfeb00000 0 0x40000>;
2029 interrupts = <GIC_SPI 1925 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
2030 <GIC_SPI 1926 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
2031 clocks = <&cpg CPG_MO 1927 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
2032 clock-names = "du.0", 1928 clock-names = "du.0", "du.1";
2033 resets = <&cpg 724>; 1929 resets = <&cpg 724>;
2034 reset-names = "du.0"; 1930 reset-names = "du.0";
2035 1931
2036 renesas,cmms = <&cmm0 1932 renesas,cmms = <&cmm0>, <&cmm1>;
2037 renesas,vsps = <&vspd 1933 renesas,vsps = <&vspd0 0>, <&vspd1 0>;
2038 1934
2039 status = "disabled"; 1935 status = "disabled";
2040 1936
2041 ports { 1937 ports {
2042 #address-cell 1938 #address-cells = <1>;
2043 #size-cells = 1939 #size-cells = <0>;
2044 1940
2045 port@0 { 1941 port@0 {
2046 reg = 1942 reg = <0>;
>> 1943 du_out_rgb: endpoint {
>> 1944 };
2047 }; 1945 };
2048 1946
2049 port@1 { 1947 port@1 {
2050 reg = 1948 reg = <1>;
2051 du_ou 1949 du_out_lvds0: endpoint {
2052 1950 remote-endpoint = <&lvds0_in>;
2053 }; 1951 };
2054 }; 1952 };
2055 1953
2056 port@2 { 1954 port@2 {
2057 reg = 1955 reg = <2>;
2058 du_ou 1956 du_out_lvds1: endpoint {
2059 1957 remote-endpoint = <&lvds1_in>;
2060 }; 1958 };
2061 }; 1959 };
2062 }; 1960 };
2063 }; 1961 };
2064 1962
2065 lvds0: lvds-encoder@feb90000 1963 lvds0: lvds-encoder@feb90000 {
2066 compatible = "renesas 1964 compatible = "renesas,r8a77990-lvds";
2067 reg = <0 0xfeb90000 0 1965 reg = <0 0xfeb90000 0 0x20>;
2068 clocks = <&cpg CPG_MO 1966 clocks = <&cpg CPG_MOD 727>;
2069 power-domains = <&sys 1967 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
2070 resets = <&cpg 727>; 1968 resets = <&cpg 727>;
2071 status = "disabled"; 1969 status = "disabled";
2072 1970
2073 renesas,companion = < 1971 renesas,companion = <&lvds1>;
2074 1972
2075 ports { 1973 ports {
2076 #address-cell 1974 #address-cells = <1>;
2077 #size-cells = 1975 #size-cells = <0>;
2078 1976
2079 port@0 { 1977 port@0 {
2080 reg = 1978 reg = <0>;
2081 lvds0 1979 lvds0_in: endpoint {
2082 1980 remote-endpoint = <&du_out_lvds0>;
2083 }; 1981 };
2084 }; 1982 };
2085 1983
2086 port@1 { 1984 port@1 {
2087 reg = 1985 reg = <1>;
>> 1986 lvds0_out: endpoint {
>> 1987 };
2088 }; 1988 };
2089 }; 1989 };
2090 }; 1990 };
2091 1991
2092 lvds1: lvds-encoder@feb90100 1992 lvds1: lvds-encoder@feb90100 {
2093 compatible = "renesas 1993 compatible = "renesas,r8a77990-lvds";
2094 reg = <0 0xfeb90100 0 1994 reg = <0 0xfeb90100 0 0x20>;
2095 clocks = <&cpg CPG_MO 1995 clocks = <&cpg CPG_MOD 727>;
2096 power-domains = <&sys 1996 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
2097 resets = <&cpg 726>; 1997 resets = <&cpg 726>;
2098 status = "disabled"; 1998 status = "disabled";
2099 1999
2100 ports { 2000 ports {
2101 #address-cell 2001 #address-cells = <1>;
2102 #size-cells = 2002 #size-cells = <0>;
2103 2003
2104 port@0 { 2004 port@0 {
2105 reg = 2005 reg = <0>;
2106 lvds1 2006 lvds1_in: endpoint {
2107 2007 remote-endpoint = <&du_out_lvds1>;
2108 }; 2008 };
2109 }; 2009 };
2110 2010
2111 port@1 { 2011 port@1 {
2112 reg = 2012 reg = <1>;
>> 2013 lvds1_out: endpoint {
>> 2014 };
2113 }; 2015 };
2114 }; 2016 };
2115 }; 2017 };
2116 2018
2117 prr: chipid@fff00044 { 2019 prr: chipid@fff00044 {
2118 compatible = "renesas 2020 compatible = "renesas,prr";
2119 reg = <0 0xfff00044 0 2021 reg = <0 0xfff00044 0 4>;
2120 }; 2022 };
2121 }; 2023 };
2122 2024
2123 thermal-zones { 2025 thermal-zones {
2124 cpu-thermal { 2026 cpu-thermal {
2125 polling-delay-passive 2027 polling-delay-passive = <250>;
2126 polling-delay = <0>; 2028 polling-delay = <0>;
2127 thermal-sensors = <&t 2029 thermal-sensors = <&thermal>;
2128 sustainable-power = < 2030 sustainable-power = <717>;
2129 2031
2130 cooling-maps { 2032 cooling-maps {
2131 map0 { 2033 map0 {
2132 trip 2034 trip = <&target>;
2133 cooli 2035 cooling-device = <&a53_0 0 2>;
2134 contr 2036 contribution = <1024>;
2135 }; 2037 };
2136 }; 2038 };
2137 2039
2138 trips { 2040 trips {
2139 sensor1_crit: 2041 sensor1_crit: sensor1-crit {
2140 tempe 2042 temperature = <120000>;
2141 hyste 2043 hysteresis = <2000>;
2142 type 2044 type = "critical";
2143 }; 2045 };
2144 2046
2145 target: trip- 2047 target: trip-point1 {
2146 tempe 2048 temperature = <100000>;
2147 hyste 2049 hysteresis = <2000>;
2148 type 2050 type = "passive";
2149 }; 2051 };
2150 }; 2052 };
2151 }; 2053 };
2152 }; 2054 };
2153 2055
2154 timer { 2056 timer {
2155 compatible = "arm,armv8-timer 2057 compatible = "arm,armv8-timer";
2156 interrupts-extended = <&gic G 2058 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
2157 <&gic G 2059 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
2158 <&gic G 2060 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
2159 <&gic G 2061 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
2160 interrupt-names = "sec-phys", <<
2161 }; 2062 };
2162 }; 2063 };
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